1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
54 #include "langhooks.h"
58 #include "dwarf2out.h"
63 struct processor_costs cypress_costs
= {
64 COSTS_N_INSNS (2), /* int load */
65 COSTS_N_INSNS (2), /* int signed load */
66 COSTS_N_INSNS (2), /* int zeroed load */
67 COSTS_N_INSNS (2), /* float load */
68 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
69 COSTS_N_INSNS (5), /* fadd, fsub */
70 COSTS_N_INSNS (1), /* fcmp */
71 COSTS_N_INSNS (1), /* fmov, fmovr */
72 COSTS_N_INSNS (7), /* fmul */
73 COSTS_N_INSNS (37), /* fdivs */
74 COSTS_N_INSNS (37), /* fdivd */
75 COSTS_N_INSNS (63), /* fsqrts */
76 COSTS_N_INSNS (63), /* fsqrtd */
77 COSTS_N_INSNS (1), /* imul */
78 COSTS_N_INSNS (1), /* imulX */
79 0, /* imul bit factor */
80 COSTS_N_INSNS (1), /* idiv */
81 COSTS_N_INSNS (1), /* idivX */
82 COSTS_N_INSNS (1), /* movcc/movr */
83 0, /* shift penalty */
87 struct processor_costs supersparc_costs
= {
88 COSTS_N_INSNS (1), /* int load */
89 COSTS_N_INSNS (1), /* int signed load */
90 COSTS_N_INSNS (1), /* int zeroed load */
91 COSTS_N_INSNS (0), /* float load */
92 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
93 COSTS_N_INSNS (3), /* fadd, fsub */
94 COSTS_N_INSNS (3), /* fcmp */
95 COSTS_N_INSNS (1), /* fmov, fmovr */
96 COSTS_N_INSNS (3), /* fmul */
97 COSTS_N_INSNS (6), /* fdivs */
98 COSTS_N_INSNS (9), /* fdivd */
99 COSTS_N_INSNS (12), /* fsqrts */
100 COSTS_N_INSNS (12), /* fsqrtd */
101 COSTS_N_INSNS (4), /* imul */
102 COSTS_N_INSNS (4), /* imulX */
103 0, /* imul bit factor */
104 COSTS_N_INSNS (4), /* idiv */
105 COSTS_N_INSNS (4), /* idivX */
106 COSTS_N_INSNS (1), /* movcc/movr */
107 1, /* shift penalty */
111 struct processor_costs hypersparc_costs
= {
112 COSTS_N_INSNS (1), /* int load */
113 COSTS_N_INSNS (1), /* int signed load */
114 COSTS_N_INSNS (1), /* int zeroed load */
115 COSTS_N_INSNS (1), /* float load */
116 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
117 COSTS_N_INSNS (1), /* fadd, fsub */
118 COSTS_N_INSNS (1), /* fcmp */
119 COSTS_N_INSNS (1), /* fmov, fmovr */
120 COSTS_N_INSNS (1), /* fmul */
121 COSTS_N_INSNS (8), /* fdivs */
122 COSTS_N_INSNS (12), /* fdivd */
123 COSTS_N_INSNS (17), /* fsqrts */
124 COSTS_N_INSNS (17), /* fsqrtd */
125 COSTS_N_INSNS (17), /* imul */
126 COSTS_N_INSNS (17), /* imulX */
127 0, /* imul bit factor */
128 COSTS_N_INSNS (17), /* idiv */
129 COSTS_N_INSNS (17), /* idivX */
130 COSTS_N_INSNS (1), /* movcc/movr */
131 0, /* shift penalty */
135 struct processor_costs leon_costs
= {
136 COSTS_N_INSNS (1), /* int load */
137 COSTS_N_INSNS (1), /* int signed load */
138 COSTS_N_INSNS (1), /* int zeroed load */
139 COSTS_N_INSNS (1), /* float load */
140 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
141 COSTS_N_INSNS (1), /* fadd, fsub */
142 COSTS_N_INSNS (1), /* fcmp */
143 COSTS_N_INSNS (1), /* fmov, fmovr */
144 COSTS_N_INSNS (1), /* fmul */
145 COSTS_N_INSNS (15), /* fdivs */
146 COSTS_N_INSNS (15), /* fdivd */
147 COSTS_N_INSNS (23), /* fsqrts */
148 COSTS_N_INSNS (23), /* fsqrtd */
149 COSTS_N_INSNS (5), /* imul */
150 COSTS_N_INSNS (5), /* imulX */
151 0, /* imul bit factor */
152 COSTS_N_INSNS (5), /* idiv */
153 COSTS_N_INSNS (5), /* idivX */
154 COSTS_N_INSNS (1), /* movcc/movr */
155 0, /* shift penalty */
159 struct processor_costs sparclet_costs
= {
160 COSTS_N_INSNS (3), /* int load */
161 COSTS_N_INSNS (3), /* int signed load */
162 COSTS_N_INSNS (1), /* int zeroed load */
163 COSTS_N_INSNS (1), /* float load */
164 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
165 COSTS_N_INSNS (1), /* fadd, fsub */
166 COSTS_N_INSNS (1), /* fcmp */
167 COSTS_N_INSNS (1), /* fmov, fmovr */
168 COSTS_N_INSNS (1), /* fmul */
169 COSTS_N_INSNS (1), /* fdivs */
170 COSTS_N_INSNS (1), /* fdivd */
171 COSTS_N_INSNS (1), /* fsqrts */
172 COSTS_N_INSNS (1), /* fsqrtd */
173 COSTS_N_INSNS (5), /* imul */
174 COSTS_N_INSNS (5), /* imulX */
175 0, /* imul bit factor */
176 COSTS_N_INSNS (5), /* idiv */
177 COSTS_N_INSNS (5), /* idivX */
178 COSTS_N_INSNS (1), /* movcc/movr */
179 0, /* shift penalty */
183 struct processor_costs ultrasparc_costs
= {
184 COSTS_N_INSNS (2), /* int load */
185 COSTS_N_INSNS (3), /* int signed load */
186 COSTS_N_INSNS (2), /* int zeroed load */
187 COSTS_N_INSNS (2), /* float load */
188 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
189 COSTS_N_INSNS (4), /* fadd, fsub */
190 COSTS_N_INSNS (1), /* fcmp */
191 COSTS_N_INSNS (2), /* fmov, fmovr */
192 COSTS_N_INSNS (4), /* fmul */
193 COSTS_N_INSNS (13), /* fdivs */
194 COSTS_N_INSNS (23), /* fdivd */
195 COSTS_N_INSNS (13), /* fsqrts */
196 COSTS_N_INSNS (23), /* fsqrtd */
197 COSTS_N_INSNS (4), /* imul */
198 COSTS_N_INSNS (4), /* imulX */
199 2, /* imul bit factor */
200 COSTS_N_INSNS (37), /* idiv */
201 COSTS_N_INSNS (68), /* idivX */
202 COSTS_N_INSNS (2), /* movcc/movr */
203 2, /* shift penalty */
207 struct processor_costs ultrasparc3_costs
= {
208 COSTS_N_INSNS (2), /* int load */
209 COSTS_N_INSNS (3), /* int signed load */
210 COSTS_N_INSNS (3), /* int zeroed load */
211 COSTS_N_INSNS (2), /* float load */
212 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
213 COSTS_N_INSNS (4), /* fadd, fsub */
214 COSTS_N_INSNS (5), /* fcmp */
215 COSTS_N_INSNS (3), /* fmov, fmovr */
216 COSTS_N_INSNS (4), /* fmul */
217 COSTS_N_INSNS (17), /* fdivs */
218 COSTS_N_INSNS (20), /* fdivd */
219 COSTS_N_INSNS (20), /* fsqrts */
220 COSTS_N_INSNS (29), /* fsqrtd */
221 COSTS_N_INSNS (6), /* imul */
222 COSTS_N_INSNS (6), /* imulX */
223 0, /* imul bit factor */
224 COSTS_N_INSNS (40), /* idiv */
225 COSTS_N_INSNS (71), /* idivX */
226 COSTS_N_INSNS (2), /* movcc/movr */
227 0, /* shift penalty */
231 struct processor_costs niagara_costs
= {
232 COSTS_N_INSNS (3), /* int load */
233 COSTS_N_INSNS (3), /* int signed load */
234 COSTS_N_INSNS (3), /* int zeroed load */
235 COSTS_N_INSNS (9), /* float load */
236 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
237 COSTS_N_INSNS (8), /* fadd, fsub */
238 COSTS_N_INSNS (26), /* fcmp */
239 COSTS_N_INSNS (8), /* fmov, fmovr */
240 COSTS_N_INSNS (29), /* fmul */
241 COSTS_N_INSNS (54), /* fdivs */
242 COSTS_N_INSNS (83), /* fdivd */
243 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
244 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
245 COSTS_N_INSNS (11), /* imul */
246 COSTS_N_INSNS (11), /* imulX */
247 0, /* imul bit factor */
248 COSTS_N_INSNS (72), /* idiv */
249 COSTS_N_INSNS (72), /* idivX */
250 COSTS_N_INSNS (1), /* movcc/movr */
251 0, /* shift penalty */
255 struct processor_costs niagara2_costs
= {
256 COSTS_N_INSNS (3), /* int load */
257 COSTS_N_INSNS (3), /* int signed load */
258 COSTS_N_INSNS (3), /* int zeroed load */
259 COSTS_N_INSNS (3), /* float load */
260 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
261 COSTS_N_INSNS (6), /* fadd, fsub */
262 COSTS_N_INSNS (6), /* fcmp */
263 COSTS_N_INSNS (6), /* fmov, fmovr */
264 COSTS_N_INSNS (6), /* fmul */
265 COSTS_N_INSNS (19), /* fdivs */
266 COSTS_N_INSNS (33), /* fdivd */
267 COSTS_N_INSNS (19), /* fsqrts */
268 COSTS_N_INSNS (33), /* fsqrtd */
269 COSTS_N_INSNS (5), /* imul */
270 COSTS_N_INSNS (5), /* imulX */
271 0, /* imul bit factor */
272 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
274 COSTS_N_INSNS (1), /* movcc/movr */
275 0, /* shift penalty */
279 struct processor_costs niagara3_costs
= {
280 COSTS_N_INSNS (3), /* int load */
281 COSTS_N_INSNS (3), /* int signed load */
282 COSTS_N_INSNS (3), /* int zeroed load */
283 COSTS_N_INSNS (3), /* float load */
284 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
285 COSTS_N_INSNS (9), /* fadd, fsub */
286 COSTS_N_INSNS (9), /* fcmp */
287 COSTS_N_INSNS (9), /* fmov, fmovr */
288 COSTS_N_INSNS (9), /* fmul */
289 COSTS_N_INSNS (23), /* fdivs */
290 COSTS_N_INSNS (37), /* fdivd */
291 COSTS_N_INSNS (23), /* fsqrts */
292 COSTS_N_INSNS (37), /* fsqrtd */
293 COSTS_N_INSNS (9), /* imul */
294 COSTS_N_INSNS (9), /* imulX */
295 0, /* imul bit factor */
296 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
297 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
298 COSTS_N_INSNS (1), /* movcc/movr */
299 0, /* shift penalty */
302 const struct processor_costs
*sparc_costs
= &cypress_costs
;
304 #ifdef HAVE_AS_RELAX_OPTION
305 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
306 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
307 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
308 somebody does not branch between the sethi and jmp. */
309 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
311 #define LEAF_SIBCALL_SLOT_RESERVED_P \
312 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
315 /* Vector to say how input registers are mapped to output registers.
316 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
317 eliminate it. You must use -fomit-frame-pointer to get that. */
318 char leaf_reg_remap
[] =
319 { 0, 1, 2, 3, 4, 5, 6, 7,
320 -1, -1, -1, -1, -1, -1, 14, -1,
321 -1, -1, -1, -1, -1, -1, -1, -1,
322 8, 9, 10, 11, 12, 13, -1, 15,
324 32, 33, 34, 35, 36, 37, 38, 39,
325 40, 41, 42, 43, 44, 45, 46, 47,
326 48, 49, 50, 51, 52, 53, 54, 55,
327 56, 57, 58, 59, 60, 61, 62, 63,
328 64, 65, 66, 67, 68, 69, 70, 71,
329 72, 73, 74, 75, 76, 77, 78, 79,
330 80, 81, 82, 83, 84, 85, 86, 87,
331 88, 89, 90, 91, 92, 93, 94, 95,
332 96, 97, 98, 99, 100, 101, 102};
334 /* Vector, indexed by hard register number, which contains 1
335 for a register that is allowable in a candidate for leaf
336 function treatment. */
337 char sparc_leaf_regs
[] =
338 { 1, 1, 1, 1, 1, 1, 1, 1,
339 0, 0, 0, 0, 0, 0, 1, 0,
340 0, 0, 0, 0, 0, 0, 0, 0,
341 1, 1, 1, 1, 1, 1, 0, 1,
342 1, 1, 1, 1, 1, 1, 1, 1,
343 1, 1, 1, 1, 1, 1, 1, 1,
344 1, 1, 1, 1, 1, 1, 1, 1,
345 1, 1, 1, 1, 1, 1, 1, 1,
346 1, 1, 1, 1, 1, 1, 1, 1,
347 1, 1, 1, 1, 1, 1, 1, 1,
348 1, 1, 1, 1, 1, 1, 1, 1,
349 1, 1, 1, 1, 1, 1, 1, 1,
350 1, 1, 1, 1, 1, 1, 1};
352 struct GTY(()) machine_function
354 /* Size of the frame of the function. */
355 HOST_WIDE_INT frame_size
;
357 /* Size of the frame of the function minus the register window save area
358 and the outgoing argument area. */
359 HOST_WIDE_INT apparent_frame_size
;
361 /* Register we pretend the frame pointer is allocated to. Normally, this
362 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
363 record "offset" separately as it may be too big for (reg + disp). */
365 HOST_WIDE_INT frame_base_offset
;
367 /* Some local-dynamic TLS symbol name. */
368 const char *some_ld_name
;
370 /* Number of global or FP registers to be saved (as 4-byte quantities). */
371 int n_global_fp_regs
;
373 /* True if the current function is leaf and uses only leaf regs,
374 so that the SPARC leaf function optimization can be applied.
375 Private version of current_function_uses_only_leaf_regs, see
376 sparc_expand_prologue for the rationale. */
379 /* True if the prologue saves local or in registers. */
380 bool save_local_in_regs_p
;
382 /* True if the data calculated by sparc_expand_prologue are valid. */
383 bool prologue_data_valid_p
;
386 #define sparc_frame_size cfun->machine->frame_size
387 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
388 #define sparc_frame_base_reg cfun->machine->frame_base_reg
389 #define sparc_frame_base_offset cfun->machine->frame_base_offset
390 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
391 #define sparc_leaf_function_p cfun->machine->leaf_function_p
392 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
393 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
395 /* 1 if the next opcode is to be specially indented. */
396 int sparc_indent_opcode
= 0;
398 static void sparc_option_override (void);
399 static void sparc_init_modes (void);
400 static void scan_record_type (const_tree
, int *, int *, int *);
401 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
402 const_tree
, bool, bool, int *, int *);
404 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
405 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
407 static void sparc_emit_set_const32 (rtx
, rtx
);
408 static void sparc_emit_set_const64 (rtx
, rtx
);
409 static void sparc_output_addr_vec (rtx
);
410 static void sparc_output_addr_diff_vec (rtx
);
411 static void sparc_output_deferred_case_vectors (void);
412 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
413 static bool sparc_legitimate_constant_p (enum machine_mode
, rtx
);
414 static rtx
sparc_builtin_saveregs (void);
415 static int epilogue_renumber (rtx
*, int);
416 static bool sparc_assemble_integer (rtx
, unsigned int, int);
417 static int set_extends (rtx
);
418 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
419 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
420 #ifdef TARGET_SOLARIS
421 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
422 tree
) ATTRIBUTE_UNUSED
;
424 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
425 static int sparc_issue_rate (void);
426 static void sparc_sched_init (FILE *, int, int);
427 static int sparc_use_sched_lookahead (void);
429 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
430 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
431 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
432 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
433 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
435 static bool sparc_function_ok_for_sibcall (tree
, tree
);
436 static void sparc_init_libfuncs (void);
437 static void sparc_init_builtins (void);
438 static void sparc_vis_init_builtins (void);
439 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
440 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
441 static int sparc_vis_mul8x16 (int, int);
442 static tree
sparc_handle_vis_mul8x16 (int, tree
, tree
, tree
);
443 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
444 HOST_WIDE_INT
, tree
);
445 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
446 HOST_WIDE_INT
, const_tree
);
447 static struct machine_function
* sparc_init_machine_status (void);
448 static bool sparc_cannot_force_const_mem (enum machine_mode
, rtx
);
449 static rtx
sparc_tls_get_addr (void);
450 static rtx
sparc_tls_got (void);
451 static const char *get_some_local_dynamic_name (void);
452 static int get_some_local_dynamic_name_1 (rtx
*, void *);
453 static int sparc_register_move_cost (enum machine_mode
,
454 reg_class_t
, reg_class_t
);
455 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
456 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
457 static rtx
sparc_libcall_value (enum machine_mode
, const_rtx
);
458 static bool sparc_function_value_regno_p (const unsigned int);
459 static rtx
sparc_struct_value_rtx (tree
, int);
460 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
461 int *, const_tree
, int);
462 static bool sparc_return_in_memory (const_tree
, const_tree
);
463 static bool sparc_strict_argument_naming (cumulative_args_t
);
464 static void sparc_va_start (tree
, rtx
);
465 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
466 static bool sparc_vector_mode_supported_p (enum machine_mode
);
467 static bool sparc_tls_referenced_p (rtx
);
468 static rtx
sparc_legitimize_tls_address (rtx
);
469 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
470 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
471 static rtx
sparc_delegitimize_address (rtx
);
472 static bool sparc_mode_dependent_address_p (const_rtx
);
473 static bool sparc_pass_by_reference (cumulative_args_t
,
474 enum machine_mode
, const_tree
, bool);
475 static void sparc_function_arg_advance (cumulative_args_t
,
476 enum machine_mode
, const_tree
, bool);
477 static rtx
sparc_function_arg_1 (cumulative_args_t
,
478 enum machine_mode
, const_tree
, bool, bool);
479 static rtx
sparc_function_arg (cumulative_args_t
,
480 enum machine_mode
, const_tree
, bool);
481 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
482 enum machine_mode
, const_tree
, bool);
483 static unsigned int sparc_function_arg_boundary (enum machine_mode
,
485 static int sparc_arg_partial_bytes (cumulative_args_t
,
486 enum machine_mode
, tree
, bool);
487 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
488 static void sparc_file_end (void);
489 static bool sparc_frame_pointer_required (void);
490 static bool sparc_can_eliminate (const int, const int);
491 static rtx
sparc_builtin_setjmp_frame_value (void);
492 static void sparc_conditional_register_usage (void);
493 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
494 static const char *sparc_mangle_type (const_tree
);
496 static void sparc_trampoline_init (rtx
, tree
, rtx
);
497 static enum machine_mode
sparc_preferred_simd_mode (enum machine_mode
);
498 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
499 static bool sparc_print_operand_punct_valid_p (unsigned char);
500 static void sparc_print_operand (FILE *, rtx
, int);
501 static void sparc_print_operand_address (FILE *, rtx
);
503 #ifdef SUBTARGET_ATTRIBUTE_TABLE
504 /* Table of valid machine attributes. */
505 static const struct attribute_spec sparc_attribute_table
[] =
507 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
509 SUBTARGET_ATTRIBUTE_TABLE
,
510 { NULL
, 0, 0, false, false, false, NULL
, false }
514 /* Option handling. */
517 enum cmodel sparc_cmodel
;
519 char sparc_hard_reg_printed
[8];
521 /* Initialize the GCC target structure. */
523 /* The default is to use .half rather than .short for aligned HI objects. */
524 #undef TARGET_ASM_ALIGNED_HI_OP
525 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
527 #undef TARGET_ASM_UNALIGNED_HI_OP
528 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
529 #undef TARGET_ASM_UNALIGNED_SI_OP
530 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
531 #undef TARGET_ASM_UNALIGNED_DI_OP
532 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
534 /* The target hook has to handle DI-mode values. */
535 #undef TARGET_ASM_INTEGER
536 #define TARGET_ASM_INTEGER sparc_assemble_integer
538 #undef TARGET_ASM_FUNCTION_PROLOGUE
539 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
540 #undef TARGET_ASM_FUNCTION_EPILOGUE
541 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
543 #undef TARGET_SCHED_ADJUST_COST
544 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
545 #undef TARGET_SCHED_ISSUE_RATE
546 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
547 #undef TARGET_SCHED_INIT
548 #define TARGET_SCHED_INIT sparc_sched_init
549 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
550 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
552 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
553 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
555 #undef TARGET_INIT_LIBFUNCS
556 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
557 #undef TARGET_INIT_BUILTINS
558 #define TARGET_INIT_BUILTINS sparc_init_builtins
560 #undef TARGET_LEGITIMIZE_ADDRESS
561 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
562 #undef TARGET_DELEGITIMIZE_ADDRESS
563 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
564 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
565 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
567 #undef TARGET_EXPAND_BUILTIN
568 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
569 #undef TARGET_FOLD_BUILTIN
570 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
573 #undef TARGET_HAVE_TLS
574 #define TARGET_HAVE_TLS true
577 #undef TARGET_CANNOT_FORCE_CONST_MEM
578 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
580 #undef TARGET_ASM_OUTPUT_MI_THUNK
581 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
582 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
583 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
585 #undef TARGET_RTX_COSTS
586 #define TARGET_RTX_COSTS sparc_rtx_costs
587 #undef TARGET_ADDRESS_COST
588 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
589 #undef TARGET_REGISTER_MOVE_COST
590 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
592 #undef TARGET_PROMOTE_FUNCTION_MODE
593 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
595 #undef TARGET_FUNCTION_VALUE
596 #define TARGET_FUNCTION_VALUE sparc_function_value
597 #undef TARGET_LIBCALL_VALUE
598 #define TARGET_LIBCALL_VALUE sparc_libcall_value
599 #undef TARGET_FUNCTION_VALUE_REGNO_P
600 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
602 #undef TARGET_STRUCT_VALUE_RTX
603 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
604 #undef TARGET_RETURN_IN_MEMORY
605 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
606 #undef TARGET_MUST_PASS_IN_STACK
607 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
608 #undef TARGET_PASS_BY_REFERENCE
609 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
610 #undef TARGET_ARG_PARTIAL_BYTES
611 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
612 #undef TARGET_FUNCTION_ARG_ADVANCE
613 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
614 #undef TARGET_FUNCTION_ARG
615 #define TARGET_FUNCTION_ARG sparc_function_arg
616 #undef TARGET_FUNCTION_INCOMING_ARG
617 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
618 #undef TARGET_FUNCTION_ARG_BOUNDARY
619 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
621 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
622 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
623 #undef TARGET_STRICT_ARGUMENT_NAMING
624 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
626 #undef TARGET_EXPAND_BUILTIN_VA_START
627 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
628 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
629 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
631 #undef TARGET_VECTOR_MODE_SUPPORTED_P
632 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
634 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
635 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
637 #ifdef SUBTARGET_INSERT_ATTRIBUTES
638 #undef TARGET_INSERT_ATTRIBUTES
639 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
642 #ifdef SUBTARGET_ATTRIBUTE_TABLE
643 #undef TARGET_ATTRIBUTE_TABLE
644 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
647 #undef TARGET_RELAXED_ORDERING
648 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
650 #undef TARGET_OPTION_OVERRIDE
651 #define TARGET_OPTION_OVERRIDE sparc_option_override
653 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
654 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
655 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
658 #undef TARGET_ASM_FILE_END
659 #define TARGET_ASM_FILE_END sparc_file_end
661 #undef TARGET_FRAME_POINTER_REQUIRED
662 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
664 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
665 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
667 #undef TARGET_CAN_ELIMINATE
668 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
670 #undef TARGET_PREFERRED_RELOAD_CLASS
671 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
673 #undef TARGET_CONDITIONAL_REGISTER_USAGE
674 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
676 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
677 #undef TARGET_MANGLE_TYPE
678 #define TARGET_MANGLE_TYPE sparc_mangle_type
681 #undef TARGET_LEGITIMATE_ADDRESS_P
682 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
684 #undef TARGET_LEGITIMATE_CONSTANT_P
685 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
687 #undef TARGET_TRAMPOLINE_INIT
688 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
690 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
691 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
692 #undef TARGET_PRINT_OPERAND
693 #define TARGET_PRINT_OPERAND sparc_print_operand
694 #undef TARGET_PRINT_OPERAND_ADDRESS
695 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
697 struct gcc_target targetm
= TARGET_INITIALIZER
;
699 /* Validate and override various options, and do some machine dependent
703 sparc_option_override (void)
705 static struct code_model
{
706 const char *const name
;
707 const enum cmodel value
;
708 } const cmodels
[] = {
710 { "medlow", CM_MEDLOW
},
711 { "medmid", CM_MEDMID
},
712 { "medany", CM_MEDANY
},
713 { "embmedany", CM_EMBMEDANY
},
714 { NULL
, (enum cmodel
) 0 }
716 const struct code_model
*cmodel
;
717 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
718 static struct cpu_default
{
720 const enum processor_type processor
;
721 } const cpu_default
[] = {
722 /* There must be one entry here for each TARGET_CPU value. */
723 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
724 { TARGET_CPU_v8
, PROCESSOR_V8
},
725 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
726 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
727 { TARGET_CPU_leon
, PROCESSOR_LEON
},
728 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
729 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
730 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
731 { TARGET_CPU_v9
, PROCESSOR_V9
},
732 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
733 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
734 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
735 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
736 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
737 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
740 const struct cpu_default
*def
;
741 /* Table of values for -m{cpu,tune}=. This must match the order of
742 the PROCESSOR_* enumeration. */
743 static struct cpu_table
{
746 } const cpu_table
[] = {
749 { MASK_ISA
, MASK_V8
},
750 /* TI TMS390Z55 supersparc */
751 { MASK_ISA
, MASK_V8
},
752 { MASK_ISA
, MASK_V8
|MASK_FPU
},
754 { MASK_ISA
, MASK_V8
|MASK_FPU
},
755 { MASK_ISA
, MASK_SPARCLITE
},
756 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
757 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
758 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
759 { MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
760 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
761 { MASK_ISA
, MASK_SPARCLET
},
763 { MASK_ISA
, MASK_SPARCLET
},
764 { MASK_ISA
, MASK_V9
},
765 /* UltraSPARC I, II, IIi */
767 /* Although insns using %y are deprecated, it is a clear win. */
768 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
770 /* ??? Check if %y issue still holds true. */
772 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
775 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
777 { MASK_ISA
, MASK_V9
},
779 { MASK_ISA
, MASK_V9
| MASK_FMAF
},
781 { MASK_ISA
, MASK_V9
| MASK_FMAF
},
783 const struct cpu_table
*cpu
;
787 #ifdef SUBTARGET_OVERRIDE_OPTIONS
788 SUBTARGET_OVERRIDE_OPTIONS
;
791 #ifndef SPARC_BI_ARCH
792 /* Check for unsupported architecture size. */
793 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
794 error ("%s is not supported by this configuration",
795 DEFAULT_ARCH32_P
? "-m64" : "-m32");
798 /* We force all 64bit archs to use 128 bit long double */
799 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
801 error ("-mlong-double-64 not allowed with -m64");
802 target_flags
|= MASK_LONG_DOUBLE_128
;
805 /* Code model selection. */
806 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
810 sparc_cmodel
= CM_32
;
813 if (sparc_cmodel_string
!= NULL
)
817 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
818 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
820 if (cmodel
->name
== NULL
)
821 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
823 sparc_cmodel
= cmodel
->value
;
826 error ("-mcmodel= is not supported on 32 bit systems");
829 /* Check that -fcall-saved-REG wasn't specified for out registers. */
830 for (i
= 8; i
< 16; i
++)
831 if (!call_used_regs
[i
])
833 error ("-fcall-saved-REG is not supported for out registers");
834 call_used_regs
[i
] = 1;
837 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
839 /* Set the default CPU. */
840 if (!global_options_set
.x_sparc_cpu_and_features
)
842 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
843 if (def
->cpu
== TARGET_CPU_DEFAULT
)
845 gcc_assert (def
->cpu
!= -1);
846 sparc_cpu_and_features
= def
->processor
;
848 if (!global_options_set
.x_sparc_cpu
)
849 sparc_cpu
= sparc_cpu_and_features
;
851 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
852 target_flags
&= ~cpu
->disable
;
853 target_flags
|= cpu
->enable
;
855 /* If -mfpu or -mno-fpu was explicitly used, don't override with
856 the processor default. */
857 if (target_flags_explicit
& MASK_FPU
)
858 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
860 /* Don't allow -mvis or -mfmaf if FPU is disabled. */
862 target_flags
&= ~(MASK_VIS
| MASK_FMAF
);
864 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
866 -m64 also implies v9. */
867 if (TARGET_VIS
|| TARGET_ARCH64
)
869 target_flags
|= MASK_V9
;
870 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
873 /* -mvis also implies -mv8plus on 32-bit */
874 if (TARGET_VIS
&& ! TARGET_ARCH64
)
875 target_flags
|= MASK_V8PLUS
;
877 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
878 if (TARGET_V9
&& TARGET_ARCH32
)
879 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
881 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
882 if (! TARGET_V9
|| TARGET_ARCH64
)
883 target_flags
&= ~MASK_V8PLUS
;
885 /* Don't use stack biasing in 32 bit mode. */
887 target_flags
&= ~MASK_STACK_BIAS
;
889 /* Supply a default value for align_functions. */
890 if (align_functions
== 0
891 && (sparc_cpu
== PROCESSOR_ULTRASPARC
892 || sparc_cpu
== PROCESSOR_ULTRASPARC3
893 || sparc_cpu
== PROCESSOR_NIAGARA
894 || sparc_cpu
== PROCESSOR_NIAGARA2
895 || sparc_cpu
== PROCESSOR_NIAGARA3
896 || sparc_cpu
== PROCESSOR_NIAGARA4
))
897 align_functions
= 32;
899 /* Validate PCC_STRUCT_RETURN. */
900 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
901 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
903 /* Only use .uaxword when compiling for a 64-bit target. */
905 targetm
.asm_out
.unaligned_op
.di
= NULL
;
907 /* Do various machine dependent initializations. */
910 /* Set up function hooks. */
911 init_machine_status
= sparc_init_machine_status
;
916 case PROCESSOR_CYPRESS
:
917 sparc_costs
= &cypress_costs
;
920 case PROCESSOR_SPARCLITE
:
921 case PROCESSOR_SUPERSPARC
:
922 sparc_costs
= &supersparc_costs
;
926 case PROCESSOR_HYPERSPARC
:
927 case PROCESSOR_SPARCLITE86X
:
928 sparc_costs
= &hypersparc_costs
;
931 sparc_costs
= &leon_costs
;
933 case PROCESSOR_SPARCLET
:
934 case PROCESSOR_TSC701
:
935 sparc_costs
= &sparclet_costs
;
938 case PROCESSOR_ULTRASPARC
:
939 sparc_costs
= &ultrasparc_costs
;
941 case PROCESSOR_ULTRASPARC3
:
942 sparc_costs
= &ultrasparc3_costs
;
944 case PROCESSOR_NIAGARA
:
945 sparc_costs
= &niagara_costs
;
947 case PROCESSOR_NIAGARA2
:
948 sparc_costs
= &niagara2_costs
;
950 case PROCESSOR_NIAGARA3
:
951 case PROCESSOR_NIAGARA4
:
952 sparc_costs
= &niagara3_costs
;
954 case PROCESSOR_NATIVE
:
958 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
959 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
960 target_flags
|= MASK_LONG_DOUBLE_128
;
963 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
964 ((sparc_cpu
== PROCESSOR_ULTRASPARC
965 || sparc_cpu
== PROCESSOR_NIAGARA
966 || sparc_cpu
== PROCESSOR_NIAGARA2
967 || sparc_cpu
== PROCESSOR_NIAGARA3
968 || sparc_cpu
== PROCESSOR_NIAGARA4
)
970 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
972 global_options
.x_param_values
,
973 global_options_set
.x_param_values
);
974 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
975 ((sparc_cpu
== PROCESSOR_ULTRASPARC
976 || sparc_cpu
== PROCESSOR_ULTRASPARC3
977 || sparc_cpu
== PROCESSOR_NIAGARA
978 || sparc_cpu
== PROCESSOR_NIAGARA2
979 || sparc_cpu
== PROCESSOR_NIAGARA3
980 || sparc_cpu
== PROCESSOR_NIAGARA4
)
982 global_options
.x_param_values
,
983 global_options_set
.x_param_values
);
985 /* Disable save slot sharing for call-clobbered registers by default.
986 The IRA sharing algorithm works on single registers only and this
987 pessimizes for double floating-point registers. */
988 if (!global_options_set
.x_flag_ira_share_save_slots
)
989 flag_ira_share_save_slots
= 0;
992 /* Miscellaneous utilities. */
994 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
995 or branch on register contents instructions. */
998 v9_regcmp_p (enum rtx_code code
)
1000 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1001 || code
== LE
|| code
== GT
);
1004 /* Nonzero if OP is a floating point constant which can
1005 be loaded into an integer register using a single
1006 sethi instruction. */
1011 if (GET_CODE (op
) == CONST_DOUBLE
)
1016 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1017 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1018 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1024 /* Nonzero if OP is a floating point constant which can
1025 be loaded into an integer register using a single
1031 if (GET_CODE (op
) == CONST_DOUBLE
)
1036 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1037 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1038 return SPARC_SIMM13_P (i
);
1044 /* Nonzero if OP is a floating point constant which can
1045 be loaded into an integer register using a high/losum
1046 instruction sequence. */
1049 fp_high_losum_p (rtx op
)
1051 /* The constraints calling this should only be in
1052 SFmode move insns, so any constant which cannot
1053 be moved using a single insn will do. */
1054 if (GET_CODE (op
) == CONST_DOUBLE
)
1059 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1060 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1061 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1067 /* Return true if the address of LABEL can be loaded by means of the
1068 mov{si,di}_pic_label_ref patterns in PIC mode. */
1071 can_use_mov_pic_label_ref (rtx label
)
1073 /* VxWorks does not impose a fixed gap between segments; the run-time
1074 gap can be different from the object-file gap. We therefore can't
1075 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1076 are absolutely sure that X is in the same segment as the GOT.
1077 Unfortunately, the flexibility of linker scripts means that we
1078 can't be sure of that in general, so assume that GOT-relative
1079 accesses are never valid on VxWorks. */
1080 if (TARGET_VXWORKS_RTP
)
1083 /* Similarly, if the label is non-local, it might end up being placed
1084 in a different section than the current one; now mov_pic_label_ref
1085 requires the label and the code to be in the same section. */
1086 if (LABEL_REF_NONLOCAL_P (label
))
1089 /* Finally, if we are reordering basic blocks and partition into hot
1090 and cold sections, this might happen for any label. */
1091 if (flag_reorder_blocks_and_partition
)
1097 /* Expand a move instruction. Return true if all work is done. */
1100 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
1102 /* Handle sets of MEM first. */
1103 if (GET_CODE (operands
[0]) == MEM
)
1105 /* 0 is a register (or a pair of registers) on SPARC. */
1106 if (register_or_zero_operand (operands
[1], mode
))
1109 if (!reload_in_progress
)
1111 operands
[0] = validize_mem (operands
[0]);
1112 operands
[1] = force_reg (mode
, operands
[1]);
1116 /* Fixup TLS cases. */
1118 && CONSTANT_P (operands
[1])
1119 && sparc_tls_referenced_p (operands
[1]))
1121 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1125 /* Fixup PIC cases. */
1126 if (flag_pic
&& CONSTANT_P (operands
[1]))
1128 if (pic_address_needs_scratch (operands
[1]))
1129 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1131 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1132 if (GET_CODE (operands
[1]) == LABEL_REF
1133 && can_use_mov_pic_label_ref (operands
[1]))
1137 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1143 gcc_assert (TARGET_ARCH64
);
1144 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1149 if (symbolic_operand (operands
[1], mode
))
1152 = sparc_legitimize_pic_address (operands
[1],
1154 ? operands
[0] : NULL_RTX
);
1159 /* If we are trying to toss an integer constant into FP registers,
1160 or loading a FP or vector constant, force it into memory. */
1161 if (CONSTANT_P (operands
[1])
1162 && REG_P (operands
[0])
1163 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1164 || SCALAR_FLOAT_MODE_P (mode
)
1165 || VECTOR_MODE_P (mode
)))
1167 /* emit_group_store will send such bogosity to us when it is
1168 not storing directly into memory. So fix this up to avoid
1169 crashes in output_constant_pool. */
1170 if (operands
[1] == const0_rtx
)
1171 operands
[1] = CONST0_RTX (mode
);
1173 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1174 always other regs. */
1175 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1176 && (const_zero_operand (operands
[1], mode
)
1177 || const_all_ones_operand (operands
[1], mode
)))
1180 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1181 /* We are able to build any SF constant in integer registers
1182 with at most 2 instructions. */
1184 /* And any DF constant in integer registers. */
1186 && (reload_completed
|| reload_in_progress
))))
1189 operands
[1] = force_const_mem (mode
, operands
[1]);
1190 if (!reload_in_progress
)
1191 operands
[1] = validize_mem (operands
[1]);
1195 /* Accept non-constants and valid constants unmodified. */
1196 if (!CONSTANT_P (operands
[1])
1197 || GET_CODE (operands
[1]) == HIGH
1198 || input_operand (operands
[1], mode
))
1204 /* All QImode constants require only one insn, so proceed. */
1209 sparc_emit_set_const32 (operands
[0], operands
[1]);
1213 /* input_operand should have filtered out 32-bit mode. */
1214 sparc_emit_set_const64 (operands
[0], operands
[1]);
1224 /* Load OP1, a 32-bit constant, into OP0, a register.
1225 We know it can't be done in one insn when we get
1226 here, the move expander guarantees this. */
1229 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1231 enum machine_mode mode
= GET_MODE (op0
);
1234 if (reload_in_progress
|| reload_completed
)
1237 temp
= gen_reg_rtx (mode
);
1239 if (GET_CODE (op1
) == CONST_INT
)
1241 gcc_assert (!small_int_operand (op1
, mode
)
1242 && !const_high_operand (op1
, mode
));
1244 /* Emit them as real moves instead of a HIGH/LO_SUM,
1245 this way CSE can see everything and reuse intermediate
1246 values if it wants. */
1247 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1248 GEN_INT (INTVAL (op1
)
1249 & ~(HOST_WIDE_INT
)0x3ff)));
1251 emit_insn (gen_rtx_SET (VOIDmode
,
1253 gen_rtx_IOR (mode
, temp
,
1254 GEN_INT (INTVAL (op1
) & 0x3ff))));
1258 /* A symbol, emit in the traditional way. */
1259 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1260 gen_rtx_HIGH (mode
, op1
)));
1261 emit_insn (gen_rtx_SET (VOIDmode
,
1262 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1266 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1267 If TEMP is nonzero, we are forbidden to use any other scratch
1268 registers. Otherwise, we are allowed to generate them as needed.
1270 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1271 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1274 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1276 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1279 if (temp
&& GET_MODE (temp
) == TImode
)
1282 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1285 /* SPARC-V9 code-model support. */
1286 switch (sparc_cmodel
)
1289 /* The range spanned by all instructions in the object is less
1290 than 2^31 bytes (2GB) and the distance from any instruction
1291 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1292 than 2^31 bytes (2GB).
1294 The executable must be in the low 4TB of the virtual address
1297 sethi %hi(symbol), %temp1
1298 or %temp1, %lo(symbol), %reg */
1300 temp1
= temp
; /* op0 is allowed. */
1302 temp1
= gen_reg_rtx (DImode
);
1304 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1305 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1309 /* The range spanned by all instructions in the object is less
1310 than 2^31 bytes (2GB) and the distance from any instruction
1311 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1312 than 2^31 bytes (2GB).
1314 The executable must be in the low 16TB of the virtual address
1317 sethi %h44(symbol), %temp1
1318 or %temp1, %m44(symbol), %temp2
1319 sllx %temp2, 12, %temp3
1320 or %temp3, %l44(symbol), %reg */
1325 temp3
= temp
; /* op0 is allowed. */
1329 temp1
= gen_reg_rtx (DImode
);
1330 temp2
= gen_reg_rtx (DImode
);
1331 temp3
= gen_reg_rtx (DImode
);
1334 emit_insn (gen_seth44 (temp1
, op1
));
1335 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1336 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1337 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1338 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1342 /* The range spanned by all instructions in the object is less
1343 than 2^31 bytes (2GB) and the distance from any instruction
1344 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1345 than 2^31 bytes (2GB).
1347 The executable can be placed anywhere in the virtual address
1350 sethi %hh(symbol), %temp1
1351 sethi %lm(symbol), %temp2
1352 or %temp1, %hm(symbol), %temp3
1353 sllx %temp3, 32, %temp4
1354 or %temp4, %temp2, %temp5
1355 or %temp5, %lo(symbol), %reg */
1358 /* It is possible that one of the registers we got for operands[2]
1359 might coincide with that of operands[0] (which is why we made
1360 it TImode). Pick the other one to use as our scratch. */
1361 if (rtx_equal_p (temp
, op0
))
1363 gcc_assert (ti_temp
);
1364 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1367 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1374 temp1
= gen_reg_rtx (DImode
);
1375 temp2
= gen_reg_rtx (DImode
);
1376 temp3
= gen_reg_rtx (DImode
);
1377 temp4
= gen_reg_rtx (DImode
);
1378 temp5
= gen_reg_rtx (DImode
);
1381 emit_insn (gen_sethh (temp1
, op1
));
1382 emit_insn (gen_setlm (temp2
, op1
));
1383 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1384 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1385 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1386 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1387 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1388 emit_insn (gen_setlo (op0
, temp5
, op1
));
1392 /* Old old old backwards compatibility kruft here.
1393 Essentially it is MEDLOW with a fixed 64-bit
1394 virtual base added to all data segment addresses.
1395 Text-segment stuff is computed like MEDANY, we can't
1396 reuse the code above because the relocation knobs
1399 Data segment: sethi %hi(symbol), %temp1
1400 add %temp1, EMBMEDANY_BASE_REG, %temp2
1401 or %temp2, %lo(symbol), %reg */
1402 if (data_segment_operand (op1
, GET_MODE (op1
)))
1406 temp1
= temp
; /* op0 is allowed. */
1411 temp1
= gen_reg_rtx (DImode
);
1412 temp2
= gen_reg_rtx (DImode
);
1415 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1416 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1417 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1420 /* Text segment: sethi %uhi(symbol), %temp1
1421 sethi %hi(symbol), %temp2
1422 or %temp1, %ulo(symbol), %temp3
1423 sllx %temp3, 32, %temp4
1424 or %temp4, %temp2, %temp5
1425 or %temp5, %lo(symbol), %reg */
1430 /* It is possible that one of the registers we got for operands[2]
1431 might coincide with that of operands[0] (which is why we made
1432 it TImode). Pick the other one to use as our scratch. */
1433 if (rtx_equal_p (temp
, op0
))
1435 gcc_assert (ti_temp
);
1436 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1439 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1446 temp1
= gen_reg_rtx (DImode
);
1447 temp2
= gen_reg_rtx (DImode
);
1448 temp3
= gen_reg_rtx (DImode
);
1449 temp4
= gen_reg_rtx (DImode
);
1450 temp5
= gen_reg_rtx (DImode
);
1453 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1454 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1455 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1456 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1457 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1458 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1459 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1460 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1469 #if HOST_BITS_PER_WIDE_INT == 32
1471 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1476 /* These avoid problems when cross compiling. If we do not
1477 go through all this hair then the optimizer will see
1478 invalid REG_EQUAL notes or in some cases none at all. */
1479 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1480 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1481 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1482 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1484 /* The optimizer is not to assume anything about exactly
1485 which bits are set for a HIGH, they are unspecified.
1486 Unfortunately this leads to many missed optimizations
1487 during CSE. We mask out the non-HIGH bits, and matches
1488 a plain movdi, to alleviate this problem. */
1490 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1492 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1496 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1498 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1502 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1504 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1508 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1510 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1513 /* Worker routines for 64-bit constant formation on arch64.
1514 One of the key things to be doing in these emissions is
1515 to create as many temp REGs as possible. This makes it
1516 possible for half-built constants to be used later when
1517 such values are similar to something required later on.
1518 Without doing this, the optimizer cannot see such
1521 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1522 unsigned HOST_WIDE_INT
, int);
1525 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1526 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1528 unsigned HOST_WIDE_INT high_bits
;
1531 high_bits
= (~low_bits
) & 0xffffffff;
1533 high_bits
= low_bits
;
1535 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1538 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1539 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1543 /* If we are XOR'ing with -1, then we should emit a one's complement
1544 instead. This way the combiner will notice logical operations
1545 such as ANDN later on and substitute. */
1546 if ((low_bits
& 0x3ff) == 0x3ff)
1548 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1549 gen_rtx_NOT (DImode
, temp
)));
1553 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1554 gen_safe_XOR64 (temp
,
1555 (-(HOST_WIDE_INT
)0x400
1556 | (low_bits
& 0x3ff)))));
1561 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1562 unsigned HOST_WIDE_INT
, int);
1565 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1566 unsigned HOST_WIDE_INT high_bits
,
1567 unsigned HOST_WIDE_INT low_immediate
,
1572 if ((high_bits
& 0xfffffc00) != 0)
1574 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1575 if ((high_bits
& ~0xfffffc00) != 0)
1576 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1577 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1583 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1587 /* Now shift it up into place. */
1588 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1589 gen_rtx_ASHIFT (DImode
, temp2
,
1590 GEN_INT (shift_count
))));
1592 /* If there is a low immediate part piece, finish up by
1593 putting that in as well. */
1594 if (low_immediate
!= 0)
1595 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1596 gen_safe_OR64 (op0
, low_immediate
)));
1599 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1600 unsigned HOST_WIDE_INT
);
1602 /* Full 64-bit constant decomposition. Even though this is the
1603 'worst' case, we still optimize a few things away. */
1605 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1606 unsigned HOST_WIDE_INT high_bits
,
1607 unsigned HOST_WIDE_INT low_bits
)
1611 if (reload_in_progress
|| reload_completed
)
1614 sub_temp
= gen_reg_rtx (DImode
);
1616 if ((high_bits
& 0xfffffc00) != 0)
1618 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1619 if ((high_bits
& ~0xfffffc00) != 0)
1620 emit_insn (gen_rtx_SET (VOIDmode
,
1622 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1628 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1632 if (!reload_in_progress
&& !reload_completed
)
1634 rtx temp2
= gen_reg_rtx (DImode
);
1635 rtx temp3
= gen_reg_rtx (DImode
);
1636 rtx temp4
= gen_reg_rtx (DImode
);
1638 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1639 gen_rtx_ASHIFT (DImode
, sub_temp
,
1642 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1643 if ((low_bits
& ~0xfffffc00) != 0)
1645 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1646 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1647 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1648 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1652 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1653 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1658 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1659 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1660 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1663 /* We are in the middle of reload, so this is really
1664 painful. However we do still make an attempt to
1665 avoid emitting truly stupid code. */
1666 if (low1
!= const0_rtx
)
1668 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1669 gen_rtx_ASHIFT (DImode
, sub_temp
,
1670 GEN_INT (to_shift
))));
1671 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1672 gen_rtx_IOR (DImode
, op0
, low1
)));
1680 if (low2
!= const0_rtx
)
1682 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1683 gen_rtx_ASHIFT (DImode
, sub_temp
,
1684 GEN_INT (to_shift
))));
1685 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1686 gen_rtx_IOR (DImode
, op0
, low2
)));
1694 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1695 gen_rtx_ASHIFT (DImode
, sub_temp
,
1696 GEN_INT (to_shift
))));
1697 if (low3
!= const0_rtx
)
1698 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1699 gen_rtx_IOR (DImode
, op0
, low3
)));
1704 /* Analyze a 64-bit constant for certain properties. */
1705 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1706 unsigned HOST_WIDE_INT
,
1707 int *, int *, int *);
1710 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1711 unsigned HOST_WIDE_INT low_bits
,
1712 int *hbsp
, int *lbsp
, int *abbasp
)
1714 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1717 lowest_bit_set
= highest_bit_set
= -1;
1721 if ((lowest_bit_set
== -1)
1722 && ((low_bits
>> i
) & 1))
1724 if ((highest_bit_set
== -1)
1725 && ((high_bits
>> (32 - i
- 1)) & 1))
1726 highest_bit_set
= (64 - i
- 1);
1729 && ((highest_bit_set
== -1)
1730 || (lowest_bit_set
== -1)));
1736 if ((lowest_bit_set
== -1)
1737 && ((high_bits
>> i
) & 1))
1738 lowest_bit_set
= i
+ 32;
1739 if ((highest_bit_set
== -1)
1740 && ((low_bits
>> (32 - i
- 1)) & 1))
1741 highest_bit_set
= 32 - i
- 1;
1744 && ((highest_bit_set
== -1)
1745 || (lowest_bit_set
== -1)));
1747 /* If there are no bits set this should have gone out
1748 as one instruction! */
1749 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
1750 all_bits_between_are_set
= 1;
1751 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1755 if ((low_bits
& (1 << i
)) != 0)
1760 if ((high_bits
& (1 << (i
- 32))) != 0)
1763 all_bits_between_are_set
= 0;
1766 *hbsp
= highest_bit_set
;
1767 *lbsp
= lowest_bit_set
;
1768 *abbasp
= all_bits_between_are_set
;
1771 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1774 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1775 unsigned HOST_WIDE_INT low_bits
)
1777 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1780 || high_bits
== 0xffffffff)
1783 analyze_64bit_constant (high_bits
, low_bits
,
1784 &highest_bit_set
, &lowest_bit_set
,
1785 &all_bits_between_are_set
);
1787 if ((highest_bit_set
== 63
1788 || lowest_bit_set
== 0)
1789 && all_bits_between_are_set
!= 0)
1792 if ((highest_bit_set
- lowest_bit_set
) < 21)
1798 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1799 unsigned HOST_WIDE_INT
,
1802 static unsigned HOST_WIDE_INT
1803 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1804 unsigned HOST_WIDE_INT low_bits
,
1805 int lowest_bit_set
, int shift
)
1807 HOST_WIDE_INT hi
, lo
;
1809 if (lowest_bit_set
< 32)
1811 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1812 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1817 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1819 gcc_assert (! (hi
& lo
));
1823 /* Here we are sure to be arch64 and this is an integer constant
1824 being loaded into a register. Emit the most efficient
1825 insn sequence possible. Detection of all the 1-insn cases
1826 has been done already. */
1828 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1830 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1831 int lowest_bit_set
, highest_bit_set
;
1832 int all_bits_between_are_set
;
1835 /* Sanity check that we know what we are working with. */
1836 gcc_assert (TARGET_ARCH64
1837 && (GET_CODE (op0
) == SUBREG
1838 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
1840 if (reload_in_progress
|| reload_completed
)
1843 if (GET_CODE (op1
) != CONST_INT
)
1845 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1850 temp
= gen_reg_rtx (DImode
);
1852 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1853 low_bits
= (INTVAL (op1
) & 0xffffffff);
1855 /* low_bits bits 0 --> 31
1856 high_bits bits 32 --> 63 */
1858 analyze_64bit_constant (high_bits
, low_bits
,
1859 &highest_bit_set
, &lowest_bit_set
,
1860 &all_bits_between_are_set
);
1862 /* First try for a 2-insn sequence. */
1864 /* These situations are preferred because the optimizer can
1865 * do more things with them:
1867 * sllx %reg, shift, %reg
1869 * srlx %reg, shift, %reg
1870 * 3) mov some_small_const, %reg
1871 * sllx %reg, shift, %reg
1873 if (((highest_bit_set
== 63
1874 || lowest_bit_set
== 0)
1875 && all_bits_between_are_set
!= 0)
1876 || ((highest_bit_set
- lowest_bit_set
) < 12))
1878 HOST_WIDE_INT the_const
= -1;
1879 int shift
= lowest_bit_set
;
1881 if ((highest_bit_set
!= 63
1882 && lowest_bit_set
!= 0)
1883 || all_bits_between_are_set
== 0)
1886 create_simple_focus_bits (high_bits
, low_bits
,
1889 else if (lowest_bit_set
== 0)
1890 shift
= -(63 - highest_bit_set
);
1892 gcc_assert (SPARC_SIMM13_P (the_const
));
1893 gcc_assert (shift
!= 0);
1895 emit_insn (gen_safe_SET64 (temp
, the_const
));
1897 emit_insn (gen_rtx_SET (VOIDmode
,
1899 gen_rtx_ASHIFT (DImode
,
1903 emit_insn (gen_rtx_SET (VOIDmode
,
1905 gen_rtx_LSHIFTRT (DImode
,
1907 GEN_INT (-shift
))));
1911 /* Now a range of 22 or less bits set somewhere.
1912 * 1) sethi %hi(focus_bits), %reg
1913 * sllx %reg, shift, %reg
1914 * 2) sethi %hi(focus_bits), %reg
1915 * srlx %reg, shift, %reg
1917 if ((highest_bit_set
- lowest_bit_set
) < 21)
1919 unsigned HOST_WIDE_INT focus_bits
=
1920 create_simple_focus_bits (high_bits
, low_bits
,
1921 lowest_bit_set
, 10);
1923 gcc_assert (SPARC_SETHI_P (focus_bits
));
1924 gcc_assert (lowest_bit_set
!= 10);
1926 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
1928 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1929 if (lowest_bit_set
< 10)
1930 emit_insn (gen_rtx_SET (VOIDmode
,
1932 gen_rtx_LSHIFTRT (DImode
, temp
,
1933 GEN_INT (10 - lowest_bit_set
))));
1934 else if (lowest_bit_set
> 10)
1935 emit_insn (gen_rtx_SET (VOIDmode
,
1937 gen_rtx_ASHIFT (DImode
, temp
,
1938 GEN_INT (lowest_bit_set
- 10))));
1942 /* 1) sethi %hi(low_bits), %reg
1943 * or %reg, %lo(low_bits), %reg
1944 * 2) sethi %hi(~low_bits), %reg
1945 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1948 || high_bits
== 0xffffffff)
1950 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1951 (high_bits
== 0xffffffff));
1955 /* Now, try 3-insn sequences. */
1957 /* 1) sethi %hi(high_bits), %reg
1958 * or %reg, %lo(high_bits), %reg
1959 * sllx %reg, 32, %reg
1963 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1967 /* We may be able to do something quick
1968 when the constant is negated, so try that. */
1969 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1970 (~low_bits
) & 0xfffffc00))
1972 /* NOTE: The trailing bits get XOR'd so we need the
1973 non-negated bits, not the negated ones. */
1974 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
1976 if ((((~high_bits
) & 0xffffffff) == 0
1977 && ((~low_bits
) & 0x80000000) == 0)
1978 || (((~high_bits
) & 0xffffffff) == 0xffffffff
1979 && ((~low_bits
) & 0x80000000) != 0))
1981 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
1983 if ((SPARC_SETHI_P (fast_int
)
1984 && (~high_bits
& 0xffffffff) == 0)
1985 || SPARC_SIMM13_P (fast_int
))
1986 emit_insn (gen_safe_SET64 (temp
, fast_int
));
1988 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
1993 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
1994 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
1995 sparc_emit_set_const64 (temp
, negated_const
);
1998 /* If we are XOR'ing with -1, then we should emit a one's complement
1999 instead. This way the combiner will notice logical operations
2000 such as ANDN later on and substitute. */
2001 if (trailing_bits
== 0x3ff)
2003 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2004 gen_rtx_NOT (DImode
, temp
)));
2008 emit_insn (gen_rtx_SET (VOIDmode
,
2010 gen_safe_XOR64 (temp
,
2011 (-0x400 | trailing_bits
))));
2016 /* 1) sethi %hi(xxx), %reg
2017 * or %reg, %lo(xxx), %reg
2018 * sllx %reg, yyy, %reg
2020 * ??? This is just a generalized version of the low_bits==0
2021 * thing above, FIXME...
2023 if ((highest_bit_set
- lowest_bit_set
) < 32)
2025 unsigned HOST_WIDE_INT focus_bits
=
2026 create_simple_focus_bits (high_bits
, low_bits
,
2029 /* We can't get here in this state. */
2030 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2032 /* So what we know is that the set bits straddle the
2033 middle of the 64-bit word. */
2034 sparc_emit_set_const64_quick2 (op0
, temp
,
2040 /* 1) sethi %hi(high_bits), %reg
2041 * or %reg, %lo(high_bits), %reg
2042 * sllx %reg, 32, %reg
2043 * or %reg, low_bits, %reg
2045 if (SPARC_SIMM13_P(low_bits
)
2046 && ((int)low_bits
> 0))
2048 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2052 /* The easiest way when all else fails, is full decomposition. */
2053 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2055 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2057 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2058 return the mode to be used for the comparison. For floating-point,
2059 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2060 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2061 processing is needed. */
2064 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2066 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2092 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2093 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2095 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2096 return CCX_NOOVmode
;
2102 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2109 /* Emit the compare insn and return the CC reg for a CODE comparison
2110 with operands X and Y. */
2113 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2115 enum machine_mode mode
;
2118 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2121 mode
= SELECT_CC_MODE (code
, x
, y
);
2123 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2124 fcc regs (cse can't tell they're really call clobbered regs and will
2125 remove a duplicate comparison even if there is an intervening function
2126 call - it will then try to reload the cc reg via an int reg which is why
2127 we need the movcc patterns). It is possible to provide the movcc
2128 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2129 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2130 to tell cse that CCFPE mode registers (even pseudos) are call
2133 /* ??? This is an experiment. Rather than making changes to cse which may
2134 or may not be easy/clean, we do our own cse. This is possible because
2135 we will generate hard registers. Cse knows they're call clobbered (it
2136 doesn't know the same thing about pseudos). If we guess wrong, no big
2137 deal, but if we win, great! */
2139 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2140 #if 1 /* experiment */
2143 /* We cycle through the registers to ensure they're all exercised. */
2144 static int next_fcc_reg
= 0;
2145 /* Previous x,y for each fcc reg. */
2146 static rtx prev_args
[4][2];
2148 /* Scan prev_args for x,y. */
2149 for (reg
= 0; reg
< 4; reg
++)
2150 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2155 prev_args
[reg
][0] = x
;
2156 prev_args
[reg
][1] = y
;
2157 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2159 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2162 cc_reg
= gen_reg_rtx (mode
);
2163 #endif /* ! experiment */
2164 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2165 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2167 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2169 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2170 will only result in an unrecognizable insn so no point in asserting. */
2171 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2177 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2180 gen_compare_reg (rtx cmp
)
2182 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2185 /* This function is used for v9 only.
2186 DEST is the target of the Scc insn.
2187 CODE is the code for an Scc's comparison.
2188 X and Y are the values we compare.
2190 This function is needed to turn
2193 (gt (reg:CCX 100 %icc)
2197 (gt:DI (reg:CCX 100 %icc)
2200 IE: The instruction recognizer needs to see the mode of the comparison to
2201 find the right instruction. We could use "gt:DI" right in the
2202 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2205 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2208 && (GET_MODE (x
) == DImode
2209 || GET_MODE (dest
) == DImode
))
2212 /* Try to use the movrCC insns. */
2214 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2216 && v9_regcmp_p (compare_code
))
2221 /* Special case for op0 != 0. This can be done with one instruction if
2224 if (compare_code
== NE
2225 && GET_MODE (dest
) == DImode
2226 && rtx_equal_p (op0
, dest
))
2228 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2229 gen_rtx_IF_THEN_ELSE (DImode
,
2230 gen_rtx_fmt_ee (compare_code
, DImode
,
2237 if (reg_overlap_mentioned_p (dest
, op0
))
2239 /* Handle the case where dest == x.
2240 We "early clobber" the result. */
2241 op0
= gen_reg_rtx (GET_MODE (x
));
2242 emit_move_insn (op0
, x
);
2245 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2246 if (GET_MODE (op0
) != DImode
)
2248 temp
= gen_reg_rtx (DImode
);
2249 convert_move (temp
, op0
, 0);
2253 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2254 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2255 gen_rtx_fmt_ee (compare_code
, DImode
,
2263 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2266 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2267 && GET_MODE (x
) != CCX_NOOVmode
);
2269 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2270 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2271 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2272 gen_rtx_fmt_ee (compare_code
,
2273 GET_MODE (x
), x
, y
),
2274 const1_rtx
, dest
)));
2280 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2281 without jumps using the addx/subx instructions. */
2284 emit_scc_insn (rtx operands
[])
2291 /* The quad-word fp compare library routines all return nonzero to indicate
2292 true, which is different from the equivalent libgcc routines, so we must
2293 handle them specially here. */
2294 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2296 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2297 GET_CODE (operands
[1]));
2298 operands
[2] = XEXP (operands
[1], 0);
2299 operands
[3] = XEXP (operands
[1], 1);
2302 code
= GET_CODE (operands
[1]);
2306 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2307 more applications). The exception to this is "reg != 0" which can
2308 be done in one instruction on v9 (so we do it). */
2311 if (GET_MODE (x
) == SImode
)
2313 rtx pat
= gen_seqsi_special (operands
[0], x
, y
);
2317 else if (GET_MODE (x
) == DImode
)
2319 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2327 if (GET_MODE (x
) == SImode
)
2329 rtx pat
= gen_snesi_special (operands
[0], x
, y
);
2333 else if (GET_MODE (x
) == DImode
)
2335 rtx pat
= gen_snedi_special (operands
[0], x
, y
);
2341 /* For the rest, on v9 we can use conditional moves. */
2345 if (gen_v9_scc (operands
[0], code
, x
, y
))
2349 /* We can do LTU and GEU using the addx/subx instructions too. And
2350 for GTU/LEU, if both operands are registers swap them and fall
2351 back to the easy case. */
2352 if (code
== GTU
|| code
== LEU
)
2354 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2355 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
2360 code
= swap_condition (code
);
2364 if (code
== LTU
|| code
== GEU
)
2366 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2367 gen_rtx_fmt_ee (code
, SImode
,
2368 gen_compare_reg_1 (code
, x
, y
),
2373 /* Nope, do branches. */
2377 /* Emit a conditional jump insn for the v9 architecture using comparison code
2378 CODE and jump target LABEL.
2379 This function exists to take advantage of the v9 brxx insns. */
2382 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2384 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2386 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2387 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2389 gen_rtx_LABEL_REF (VOIDmode
, label
),
2394 emit_conditional_branch_insn (rtx operands
[])
2396 /* The quad-word fp compare library routines all return nonzero to indicate
2397 true, which is different from the equivalent libgcc routines, so we must
2398 handle them specially here. */
2399 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
2401 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
2402 GET_CODE (operands
[0]));
2403 operands
[1] = XEXP (operands
[0], 0);
2404 operands
[2] = XEXP (operands
[0], 1);
2407 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
2408 && GET_CODE (operands
[1]) == REG
2409 && GET_MODE (operands
[1]) == DImode
)
2411 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
2415 operands
[1] = gen_compare_reg (operands
[0]);
2416 operands
[2] = const0_rtx
;
2417 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
2418 operands
[1], operands
[2]);
2419 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
2424 /* Generate a DFmode part of a hard TFmode register.
2425 REG is the TFmode hard register, LOW is 1 for the
2426 low 64bit of the register and 0 otherwise.
2429 gen_df_reg (rtx reg
, int low
)
2431 int regno
= REGNO (reg
);
2433 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2434 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2435 return gen_rtx_REG (DFmode
, regno
);
2438 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2439 Unlike normal calls, TFmode operands are passed by reference. It is
2440 assumed that no more than 3 operands are required. */
2443 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2445 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2448 /* We only expect to be called for conversions, unary, and binary ops. */
2449 gcc_assert (nargs
== 2 || nargs
== 3);
2451 for (i
= 0; i
< nargs
; ++i
)
2453 rtx this_arg
= operands
[i
];
2456 /* TFmode arguments and return values are passed by reference. */
2457 if (GET_MODE (this_arg
) == TFmode
)
2459 int force_stack_temp
;
2461 force_stack_temp
= 0;
2462 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2463 force_stack_temp
= 1;
2465 if (GET_CODE (this_arg
) == MEM
2466 && ! force_stack_temp
)
2467 this_arg
= XEXP (this_arg
, 0);
2468 else if (CONSTANT_P (this_arg
)
2469 && ! force_stack_temp
)
2471 this_slot
= force_const_mem (TFmode
, this_arg
);
2472 this_arg
= XEXP (this_slot
, 0);
2476 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2478 /* Operand 0 is the return value. We'll copy it out later. */
2480 emit_move_insn (this_slot
, this_arg
);
2482 ret_slot
= this_slot
;
2484 this_arg
= XEXP (this_slot
, 0);
2491 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2493 if (GET_MODE (operands
[0]) == TFmode
)
2496 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2497 arg
[0], GET_MODE (arg
[0]),
2498 arg
[1], GET_MODE (arg
[1]));
2500 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2501 arg
[0], GET_MODE (arg
[0]),
2502 arg
[1], GET_MODE (arg
[1]),
2503 arg
[2], GET_MODE (arg
[2]));
2506 emit_move_insn (operands
[0], ret_slot
);
2512 gcc_assert (nargs
== 2);
2514 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2515 GET_MODE (operands
[0]), 1,
2516 arg
[1], GET_MODE (arg
[1]));
2518 if (ret
!= operands
[0])
2519 emit_move_insn (operands
[0], ret
);
2523 /* Expand soft-float TFmode calls to sparc abi routines. */
2526 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2548 emit_soft_tfmode_libcall (func
, 3, operands
);
2552 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2556 gcc_assert (code
== SQRT
);
2559 emit_soft_tfmode_libcall (func
, 2, operands
);
2563 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2570 switch (GET_MODE (operands
[1]))
2583 case FLOAT_TRUNCATE
:
2584 switch (GET_MODE (operands
[0]))
2598 switch (GET_MODE (operands
[1]))
2603 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
2613 case UNSIGNED_FLOAT
:
2614 switch (GET_MODE (operands
[1]))
2619 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
2630 switch (GET_MODE (operands
[0]))
2644 switch (GET_MODE (operands
[0]))
2661 emit_soft_tfmode_libcall (func
, 2, operands
);
2664 /* Expand a hard-float tfmode operation. All arguments must be in
2668 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2672 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2674 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2675 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2679 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2680 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2681 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2682 operands
[1], operands
[2]);
2685 if (register_operand (operands
[0], VOIDmode
))
2688 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2690 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2692 if (dest
!= operands
[0])
2693 emit_move_insn (operands
[0], dest
);
2697 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2699 if (TARGET_HARD_QUAD
)
2700 emit_hard_tfmode_operation (code
, operands
);
2702 emit_soft_tfmode_binop (code
, operands
);
2706 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2708 if (TARGET_HARD_QUAD
)
2709 emit_hard_tfmode_operation (code
, operands
);
2711 emit_soft_tfmode_unop (code
, operands
);
2715 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2717 if (TARGET_HARD_QUAD
)
2718 emit_hard_tfmode_operation (code
, operands
);
2720 emit_soft_tfmode_cvt (code
, operands
);
2723 /* Return nonzero if a branch/jump/call instruction will be emitting
2724 nop into its delay slot. */
2727 empty_delay_slot (rtx insn
)
2731 /* If no previous instruction (should not happen), return true. */
2732 if (PREV_INSN (insn
) == NULL
)
2735 seq
= NEXT_INSN (PREV_INSN (insn
));
2736 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2742 /* Return nonzero if TRIAL can go into the call delay slot. */
2745 tls_call_delay (rtx trial
)
2750 call __tls_get_addr, %tgd_call (foo)
2751 add %l7, %o0, %o0, %tgd_add (foo)
2752 while Sun as/ld does not. */
2753 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2756 pat
= PATTERN (trial
);
2758 /* We must reject tgd_add{32|64}, i.e.
2759 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2760 and tldm_add{32|64}, i.e.
2761 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2763 if (GET_CODE (pat
) == SET
2764 && GET_CODE (SET_SRC (pat
)) == PLUS
)
2766 rtx unspec
= XEXP (SET_SRC (pat
), 1);
2768 if (GET_CODE (unspec
) == UNSPEC
2769 && (XINT (unspec
, 1) == UNSPEC_TLSGD
2770 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
2777 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2778 instruction. RETURN_P is true if the v9 variant 'return' is to be
2779 considered in the test too.
2781 TRIAL must be a SET whose destination is a REG appropriate for the
2782 'restore' instruction or, if RETURN_P is true, for the 'return'
2786 eligible_for_restore_insn (rtx trial
, bool return_p
)
2788 rtx pat
= PATTERN (trial
);
2789 rtx src
= SET_SRC (pat
);
2791 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2792 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2793 && arith_operand (src
, GET_MODE (src
)))
2796 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2798 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2801 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2802 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2803 && arith_double_operand (src
, GET_MODE (src
)))
2804 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2806 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2807 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
2810 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2811 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
2814 /* If we have the 'return' instruction, anything that does not use
2815 local or output registers and can go into a delay slot wins. */
2818 && !epilogue_renumber (&pat
, 1)
2819 && get_attr_in_uncond_branch_delay (trial
)
2820 == IN_UNCOND_BRANCH_DELAY_TRUE
)
2823 /* The 'restore src1,src2,dest' pattern for SImode. */
2824 else if (GET_CODE (src
) == PLUS
2825 && register_operand (XEXP (src
, 0), SImode
)
2826 && arith_operand (XEXP (src
, 1), SImode
))
2829 /* The 'restore src1,src2,dest' pattern for DImode. */
2830 else if (GET_CODE (src
) == PLUS
2831 && register_operand (XEXP (src
, 0), DImode
)
2832 && arith_double_operand (XEXP (src
, 1), DImode
))
2835 /* The 'restore src1,%lo(src2),dest' pattern. */
2836 else if (GET_CODE (src
) == LO_SUM
2837 && ! TARGET_CM_MEDMID
2838 && ((register_operand (XEXP (src
, 0), SImode
)
2839 && immediate_operand (XEXP (src
, 1), SImode
))
2841 && register_operand (XEXP (src
, 0), DImode
)
2842 && immediate_operand (XEXP (src
, 1), DImode
))))
2845 /* The 'restore src,src,dest' pattern. */
2846 else if (GET_CODE (src
) == ASHIFT
2847 && (register_operand (XEXP (src
, 0), SImode
)
2848 || register_operand (XEXP (src
, 0), DImode
))
2849 && XEXP (src
, 1) == const1_rtx
)
2855 /* Return nonzero if TRIAL can go into the function return's delay slot. */
2858 eligible_for_return_delay (rtx trial
)
2863 if (GET_CODE (trial
) != INSN
)
2866 if (get_attr_length (trial
) != 1)
2869 /* If the function uses __builtin_eh_return, the eh_return machinery
2870 occupies the delay slot. */
2871 if (crtl
->calls_eh_return
)
2874 /* In the case of a leaf or flat function, anything can go into the slot. */
2875 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2877 get_attr_in_uncond_branch_delay (trial
) == IN_UNCOND_BRANCH_DELAY_TRUE
;
2879 pat
= PATTERN (trial
);
2880 if (GET_CODE (pat
) == PARALLEL
)
2886 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
2888 rtx expr
= XVECEXP (pat
, 0, i
);
2889 if (GET_CODE (expr
) != SET
)
2891 if (GET_CODE (SET_DEST (expr
)) != REG
)
2893 regno
= REGNO (SET_DEST (expr
));
2894 if (regno
>= 8 && regno
< 24)
2897 return !epilogue_renumber (&pat
, 1)
2898 && (get_attr_in_uncond_branch_delay (trial
)
2899 == IN_UNCOND_BRANCH_DELAY_TRUE
);
2902 if (GET_CODE (pat
) != SET
)
2905 if (GET_CODE (SET_DEST (pat
)) != REG
)
2908 regno
= REGNO (SET_DEST (pat
));
2910 /* Otherwise, only operations which can be done in tandem with
2911 a `restore' or `return' insn can go into the delay slot. */
2912 if (regno
>= 8 && regno
< 24)
2915 /* If this instruction sets up floating point register and we have a return
2916 instruction, it can probably go in. But restore will not work
2920 && !epilogue_renumber (&pat
, 1)
2921 && get_attr_in_uncond_branch_delay (trial
)
2922 == IN_UNCOND_BRANCH_DELAY_TRUE
);
2924 return eligible_for_restore_insn (trial
, true);
2927 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
2930 eligible_for_sibcall_delay (rtx trial
)
2934 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2937 if (get_attr_length (trial
) != 1)
2940 pat
= PATTERN (trial
);
2942 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2944 /* If the tail call is done using the call instruction,
2945 we have to restore %o7 in the delay slot. */
2946 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
2949 /* %g1 is used to build the function address */
2950 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2956 /* Otherwise, only operations which can be done in tandem with
2957 a `restore' insn can go into the delay slot. */
2958 if (GET_CODE (SET_DEST (pat
)) != REG
2959 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
2960 || REGNO (SET_DEST (pat
)) >= 32)
2963 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2965 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2968 return eligible_for_restore_insn (trial
, false);
2972 short_branch (int uid1
, int uid2
)
2974 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
2976 /* Leave a few words of "slop". */
2977 if (delta
>= -1023 && delta
<= 1022)
2983 /* Return nonzero if REG is not used after INSN.
2984 We assume REG is a reload reg, and therefore does
2985 not live past labels or calls or jumps. */
2987 reg_unused_after (rtx reg
, rtx insn
)
2989 enum rtx_code code
, prev_code
= UNKNOWN
;
2991 while ((insn
= NEXT_INSN (insn
)))
2993 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
2996 code
= GET_CODE (insn
);
2997 if (GET_CODE (insn
) == CODE_LABEL
)
3002 rtx set
= single_set (insn
);
3003 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
3006 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
3008 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
3016 /* Determine if it's legal to put X into the constant pool. This
3017 is not possible if X contains the address of a symbol that is
3018 not constant (TLS) or not known at final link time (PIC). */
3021 sparc_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
3023 switch (GET_CODE (x
))
3028 /* Accept all non-symbolic constants. */
3032 /* Labels are OK iff we are non-PIC. */
3033 return flag_pic
!= 0;
3036 /* 'Naked' TLS symbol references are never OK,
3037 non-TLS symbols are OK iff we are non-PIC. */
3038 if (SYMBOL_REF_TLS_MODEL (x
))
3041 return flag_pic
!= 0;
3044 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3047 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3048 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3056 /* Global Offset Table support. */
3057 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3058 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3060 /* Return the SYMBOL_REF for the Global Offset Table. */
3062 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3067 if (!sparc_got_symbol
)
3068 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3070 return sparc_got_symbol
;
3073 /* Ensure that we are not using patterns that are not OK with PIC. */
3083 op
= recog_data
.operand
[i
];
3084 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3085 && (GET_CODE (op
) != CONST
3086 || (GET_CODE (XEXP (op
, 0)) == MINUS
3087 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3088 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3095 /* Return true if X is an address which needs a temporary register when
3096 reloaded while generating PIC code. */
3099 pic_address_needs_scratch (rtx x
)
3101 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3102 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3103 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3104 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3105 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3111 /* Determine if a given RTX is a valid constant. We already know this
3112 satisfies CONSTANT_P. */
3115 sparc_legitimate_constant_p (enum machine_mode mode
, rtx x
)
3117 switch (GET_CODE (x
))
3121 if (sparc_tls_referenced_p (x
))
3126 if (GET_MODE (x
) == VOIDmode
)
3129 /* Floating point constants are generally not ok.
3130 The only exception is 0.0 and all-ones in VIS. */
3132 && SCALAR_FLOAT_MODE_P (mode
)
3133 && (const_zero_operand (x
, mode
)
3134 || const_all_ones_operand (x
, mode
)))
3140 /* Vector constants are generally not ok.
3141 The only exception is 0 or -1 in VIS. */
3143 && (const_zero_operand (x
, mode
)
3144 || const_all_ones_operand (x
, mode
)))
3156 /* Determine if a given RTX is a valid constant address. */
3159 constant_address_p (rtx x
)
3161 switch (GET_CODE (x
))
3169 if (flag_pic
&& pic_address_needs_scratch (x
))
3171 return sparc_legitimate_constant_p (Pmode
, x
);
3174 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3181 /* Nonzero if the constant value X is a legitimate general operand
3182 when generating PIC code. It is given that flag_pic is on and
3183 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3186 legitimate_pic_operand_p (rtx x
)
3188 if (pic_address_needs_scratch (x
))
3190 if (sparc_tls_referenced_p (x
))
3195 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3197 && INTVAL (X) >= -0x1000 \
3198 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3200 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3202 && INTVAL (X) >= -0x1000 \
3203 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3205 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3207 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3208 ordinarily. This changes a bit when generating PIC. */
3211 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3213 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3215 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3217 else if (GET_CODE (addr
) == PLUS
)
3219 rs1
= XEXP (addr
, 0);
3220 rs2
= XEXP (addr
, 1);
3222 /* Canonicalize. REG comes first, if there are no regs,
3223 LO_SUM comes first. */
3225 && GET_CODE (rs1
) != SUBREG
3227 || GET_CODE (rs2
) == SUBREG
3228 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3230 rs1
= XEXP (addr
, 1);
3231 rs2
= XEXP (addr
, 0);
3235 && rs1
== pic_offset_table_rtx
3237 && GET_CODE (rs2
) != SUBREG
3238 && GET_CODE (rs2
) != LO_SUM
3239 && GET_CODE (rs2
) != MEM
3240 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3241 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3242 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3244 || GET_CODE (rs1
) == SUBREG
)
3245 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3250 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3251 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3253 /* We prohibit REG + REG for TFmode when there are no quad move insns
3254 and we consequently need to split. We do this because REG+REG
3255 is not an offsettable address. If we get the situation in reload
3256 where source and destination of a movtf pattern are both MEMs with
3257 REG+REG address, then only one of them gets converted to an
3258 offsettable address. */
3260 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3263 /* We prohibit REG + REG on ARCH32 if not optimizing for
3264 DFmode/DImode because then mem_min_alignment is likely to be zero
3265 after reload and the forced split would lack a matching splitter
3267 if (TARGET_ARCH32
&& !optimize
3268 && (mode
== DFmode
|| mode
== DImode
))
3271 else if (USE_AS_OFFSETABLE_LO10
3272 && GET_CODE (rs1
) == LO_SUM
3274 && ! TARGET_CM_MEDMID
3275 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
3278 imm1
= XEXP (rs1
, 1);
3279 rs1
= XEXP (rs1
, 0);
3280 if (!CONSTANT_P (imm1
)
3281 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3285 else if (GET_CODE (addr
) == LO_SUM
)
3287 rs1
= XEXP (addr
, 0);
3288 imm1
= XEXP (addr
, 1);
3290 if (!CONSTANT_P (imm1
)
3291 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3294 /* We can't allow TFmode in 32-bit mode, because an offset greater
3295 than the alignment (8) may cause the LO_SUM to overflow. */
3296 if (mode
== TFmode
&& TARGET_ARCH32
)
3299 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3304 if (GET_CODE (rs1
) == SUBREG
)
3305 rs1
= SUBREG_REG (rs1
);
3311 if (GET_CODE (rs2
) == SUBREG
)
3312 rs2
= SUBREG_REG (rs2
);
3319 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3320 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3325 if ((REGNO (rs1
) >= 32
3326 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3327 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3329 && (REGNO (rs2
) >= 32
3330 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3331 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3337 /* Return the SYMBOL_REF for the tls_get_addr function. */
3339 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
3342 sparc_tls_get_addr (void)
3344 if (!sparc_tls_symbol
)
3345 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3347 return sparc_tls_symbol
;
3350 /* Return the Global Offset Table to be used in TLS mode. */
3353 sparc_tls_got (void)
3355 /* In PIC mode, this is just the PIC offset table. */
3358 crtl
->uses_pic_offset_table
= 1;
3359 return pic_offset_table_rtx
;
3362 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3363 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3364 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
3366 load_got_register ();
3367 return global_offset_table_rtx
;
3370 /* In all other cases, we load a new pseudo with the GOT symbol. */
3371 return copy_to_reg (sparc_got ());
3374 /* Return true if X contains a thread-local symbol. */
3377 sparc_tls_referenced_p (rtx x
)
3379 if (!TARGET_HAVE_TLS
)
3382 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3383 x
= XEXP (XEXP (x
, 0), 0);
3385 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
3388 /* That's all we handle in sparc_legitimize_tls_address for now. */
3392 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3393 this (thread-local) address. */
3396 sparc_legitimize_tls_address (rtx addr
)
3398 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3400 gcc_assert (can_create_pseudo_p ());
3402 if (GET_CODE (addr
) == SYMBOL_REF
)
3403 switch (SYMBOL_REF_TLS_MODEL (addr
))
3405 case TLS_MODEL_GLOBAL_DYNAMIC
:
3407 temp1
= gen_reg_rtx (SImode
);
3408 temp2
= gen_reg_rtx (SImode
);
3409 ret
= gen_reg_rtx (Pmode
);
3410 o0
= gen_rtx_REG (Pmode
, 8);
3411 got
= sparc_tls_got ();
3412 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3413 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3416 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3417 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3422 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3423 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3426 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3427 insn
= get_insns ();
3429 emit_libcall_block (insn
, ret
, o0
, addr
);
3432 case TLS_MODEL_LOCAL_DYNAMIC
:
3434 temp1
= gen_reg_rtx (SImode
);
3435 temp2
= gen_reg_rtx (SImode
);
3436 temp3
= gen_reg_rtx (Pmode
);
3437 ret
= gen_reg_rtx (Pmode
);
3438 o0
= gen_rtx_REG (Pmode
, 8);
3439 got
= sparc_tls_got ();
3440 emit_insn (gen_tldm_hi22 (temp1
));
3441 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3444 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3445 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3450 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3451 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3454 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3455 insn
= get_insns ();
3457 emit_libcall_block (insn
, temp3
, o0
,
3458 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3459 UNSPEC_TLSLD_BASE
));
3460 temp1
= gen_reg_rtx (SImode
);
3461 temp2
= gen_reg_rtx (SImode
);
3462 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3463 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3465 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3467 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3470 case TLS_MODEL_INITIAL_EXEC
:
3471 temp1
= gen_reg_rtx (SImode
);
3472 temp2
= gen_reg_rtx (SImode
);
3473 temp3
= gen_reg_rtx (Pmode
);
3474 got
= sparc_tls_got ();
3475 emit_insn (gen_tie_hi22 (temp1
, addr
));
3476 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3478 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3480 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3483 ret
= gen_reg_rtx (Pmode
);
3485 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3488 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3492 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3495 case TLS_MODEL_LOCAL_EXEC
:
3496 temp1
= gen_reg_rtx (Pmode
);
3497 temp2
= gen_reg_rtx (Pmode
);
3500 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3501 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3505 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3506 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3508 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3515 else if (GET_CODE (addr
) == CONST
)
3519 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
3521 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
3522 offset
= XEXP (XEXP (addr
, 0), 1);
3524 base
= force_operand (base
, NULL_RTX
);
3525 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
3526 offset
= force_reg (Pmode
, offset
);
3527 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
3531 gcc_unreachable (); /* for now ... */
3536 /* Legitimize PIC addresses. If the address is already position-independent,
3537 we return ORIG. Newly generated position-independent addresses go into a
3538 reg. This is REG if nonzero, otherwise we allocate register(s) as
3542 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
3544 bool gotdata_op
= false;
3546 if (GET_CODE (orig
) == SYMBOL_REF
3547 /* See the comment in sparc_expand_move. */
3548 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
3550 rtx pic_ref
, address
;
3555 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3556 reg
= gen_reg_rtx (Pmode
);
3561 /* If not during reload, allocate another temp reg here for loading
3562 in the address, so that these instructions can be optimized
3564 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3565 ? reg
: gen_reg_rtx (Pmode
));
3567 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3568 won't get confused into thinking that these two instructions
3569 are loading in the true address of the symbol. If in the
3570 future a PIC rtx exists, that should be used instead. */
3573 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3574 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3578 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3579 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3587 crtl
->uses_pic_offset_table
= 1;
3591 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
3592 pic_offset_table_rtx
,
3595 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
3596 pic_offset_table_rtx
,
3602 = gen_const_mem (Pmode
,
3603 gen_rtx_PLUS (Pmode
,
3604 pic_offset_table_rtx
, address
));
3605 insn
= emit_move_insn (reg
, pic_ref
);
3608 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3610 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3613 else if (GET_CODE (orig
) == CONST
)
3617 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3618 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3623 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3624 reg
= gen_reg_rtx (Pmode
);
3627 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3628 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
3629 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
3630 base
== reg
? NULL_RTX
: reg
);
3632 if (GET_CODE (offset
) == CONST_INT
)
3634 if (SMALL_INT (offset
))
3635 return plus_constant (base
, INTVAL (offset
));
3636 else if (! reload_in_progress
&& ! reload_completed
)
3637 offset
= force_reg (Pmode
, offset
);
3639 /* If we reach here, then something is seriously wrong. */
3642 return gen_rtx_PLUS (Pmode
, base
, offset
);
3644 else if (GET_CODE (orig
) == LABEL_REF
)
3645 /* ??? We ought to be checking that the register is live instead, in case
3646 it is eliminated. */
3647 crtl
->uses_pic_offset_table
= 1;
3652 /* Try machine-dependent ways of modifying an illegitimate address X
3653 to be legitimate. If we find one, return the new, valid address.
3655 OLDX is the address as it was before break_out_memory_refs was called.
3656 In some cases it is useful to look at this to decide what needs to be done.
3658 MODE is the mode of the operand pointed to by X.
3660 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3663 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3664 enum machine_mode mode
)
3668 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3669 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3670 force_operand (XEXP (x
, 0), NULL_RTX
));
3671 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3672 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3673 force_operand (XEXP (x
, 1), NULL_RTX
));
3674 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3675 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3677 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3678 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3679 force_operand (XEXP (x
, 1), NULL_RTX
));
3681 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
3684 if (sparc_tls_referenced_p (x
))
3685 x
= sparc_legitimize_tls_address (x
);
3687 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
3688 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3689 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3690 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3691 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3692 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3693 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3694 else if (GET_CODE (x
) == SYMBOL_REF
3695 || GET_CODE (x
) == CONST
3696 || GET_CODE (x
) == LABEL_REF
)
3697 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3702 /* Delegitimize an address that was legitimized by the above function. */
3705 sparc_delegitimize_address (rtx x
)
3707 x
= delegitimize_mem_from_attrs (x
);
3709 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
3710 switch (XINT (XEXP (x
, 1), 1))
3712 case UNSPEC_MOVE_PIC
:
3714 x
= XVECEXP (XEXP (x
, 1), 0, 0);
3715 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3721 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3722 if (GET_CODE (x
) == MINUS
3723 && REG_P (XEXP (x
, 0))
3724 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
3725 && GET_CODE (XEXP (x
, 1)) == LO_SUM
3726 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
3727 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
3729 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
3730 gcc_assert (GET_CODE (x
) == LABEL_REF
);
3736 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3737 replace the input X, or the original X if no replacement is called for.
3738 The output parameter *WIN is 1 if the calling macro should goto WIN,
3741 For SPARC, we wish to handle addresses by splitting them into
3742 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3743 This cuts the number of extra insns by one.
3745 Do nothing when generating PIC code and the address is a symbolic
3746 operand or requires a scratch register. */
3749 sparc_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3750 int opnum
, int type
,
3751 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3753 /* Decompose SImode constants into HIGH+LO_SUM. */
3755 && (mode
!= TFmode
|| TARGET_ARCH64
)
3756 && GET_MODE (x
) == SImode
3757 && GET_CODE (x
) != LO_SUM
3758 && GET_CODE (x
) != HIGH
3759 && sparc_cmodel
<= CM_MEDLOW
3761 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
3763 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
3764 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3765 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3766 opnum
, (enum reload_type
)type
);
3771 /* We have to recognize what we have already generated above. */
3772 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
3774 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3775 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3776 opnum
, (enum reload_type
)type
);
3785 /* Return true if ADDR (a legitimate address expression)
3786 has an effect that depends on the machine mode it is used for.
3792 is not equivalent to
3794 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3796 because [%l7+a+1] is interpreted as the address of (a+1). */
3800 sparc_mode_dependent_address_p (const_rtx addr
)
3802 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
3804 rtx op0
= XEXP (addr
, 0);
3805 rtx op1
= XEXP (addr
, 1);
3806 if (op0
== pic_offset_table_rtx
3807 && symbolic_operand (op1
, VOIDmode
))
3814 #ifdef HAVE_GAS_HIDDEN
3815 # define USE_HIDDEN_LINKONCE 1
3817 # define USE_HIDDEN_LINKONCE 0
3821 get_pc_thunk_name (char name
[32], unsigned int regno
)
3823 const char *reg_name
= reg_names
[regno
];
3825 /* Skip the leading '%' as that cannot be used in a
3829 if (USE_HIDDEN_LINKONCE
)
3830 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
3832 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
3835 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
3838 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
3840 int orig_flag_pic
= flag_pic
;
3843 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3846 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
3848 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
3849 flag_pic
= orig_flag_pic
;
3854 /* Emit code to load the GOT register. */
3857 load_got_register (void)
3859 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3860 if (!global_offset_table_rtx
)
3861 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
3863 if (TARGET_VXWORKS_RTP
)
3864 emit_insn (gen_vxworks_load_got ());
3867 /* The GOT symbol is subject to a PC-relative relocation so we need a
3868 helper function to add the PC value and thus get the final value. */
3869 if (!got_helper_rtx
)
3872 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
3873 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
3876 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
3878 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
3881 /* Need to emit this whether or not we obey regdecls,
3882 since setjmp/longjmp can cause life info to screw up.
3883 ??? In the case where we don't obey regdecls, this is not sufficient
3884 since we may not fall out the bottom. */
3885 emit_use (global_offset_table_rtx
);
3888 /* Emit a call instruction with the pattern given by PAT. ADDR is the
3889 address of the call target. */
3892 sparc_emit_call_insn (rtx pat
, rtx addr
)
3896 insn
= emit_call_insn (pat
);
3898 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3899 if (TARGET_VXWORKS_RTP
3901 && GET_CODE (addr
) == SYMBOL_REF
3902 && (SYMBOL_REF_DECL (addr
)
3903 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
3904 : !SYMBOL_REF_LOCAL_P (addr
)))
3906 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3907 crtl
->uses_pic_offset_table
= 1;
3911 /* Return 1 if RTX is a MEM which is known to be aligned to at
3912 least a DESIRED byte boundary. */
3915 mem_min_alignment (rtx mem
, int desired
)
3917 rtx addr
, base
, offset
;
3919 /* If it's not a MEM we can't accept it. */
3920 if (GET_CODE (mem
) != MEM
)
3924 if (!TARGET_UNALIGNED_DOUBLES
3925 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
3928 /* ??? The rest of the function predates MEM_ALIGN so
3929 there is probably a bit of redundancy. */
3930 addr
= XEXP (mem
, 0);
3931 base
= offset
= NULL_RTX
;
3932 if (GET_CODE (addr
) == PLUS
)
3934 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3936 base
= XEXP (addr
, 0);
3938 /* What we are saying here is that if the base
3939 REG is aligned properly, the compiler will make
3940 sure any REG based index upon it will be so
3942 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3943 offset
= XEXP (addr
, 1);
3945 offset
= const0_rtx
;
3948 else if (GET_CODE (addr
) == REG
)
3951 offset
= const0_rtx
;
3954 if (base
!= NULL_RTX
)
3956 int regno
= REGNO (base
);
3958 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3960 /* Check if the compiler has recorded some information
3961 about the alignment of the base REG. If reload has
3962 completed, we already matched with proper alignments.
3963 If not running global_alloc, reload might give us
3964 unaligned pointer to local stack though. */
3966 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3967 || (optimize
&& reload_completed
))
3968 && (INTVAL (offset
) & (desired
- 1)) == 0)
3973 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3977 else if (! TARGET_UNALIGNED_DOUBLES
3978 || CONSTANT_P (addr
)
3979 || GET_CODE (addr
) == LO_SUM
)
3981 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3982 is true, in which case we can only assume that an access is aligned if
3983 it is to a constant address, or the address involves a LO_SUM. */
3987 /* An obviously unaligned address. */
3992 /* Vectors to keep interesting information about registers where it can easily
3993 be got. We used to use the actual mode value as the bit number, but there
3994 are more than 32 modes now. Instead we use two tables: one indexed by
3995 hard register number, and one indexed by mode. */
3997 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3998 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
3999 mapped into one sparc_mode_class mode. */
4001 enum sparc_mode_class
{
4002 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4003 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4007 /* Modes for single-word and smaller quantities. */
4008 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4010 /* Modes for double-word and smaller quantities. */
4011 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4013 /* Modes for quad-word and smaller quantities. */
4014 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4016 /* Modes for 8-word and smaller quantities. */
4017 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4019 /* Modes for single-float quantities. We must allow any single word or
4020 smaller quantity. This is because the fix/float conversion instructions
4021 take integer inputs/outputs from the float registers. */
4022 #define SF_MODES (S_MODES)
4024 /* Modes for double-float and smaller quantities. */
4025 #define DF_MODES (D_MODES)
4027 /* Modes for quad-float and smaller quantities. */
4028 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4030 /* Modes for quad-float pairs and smaller quantities. */
4031 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4033 /* Modes for double-float only quantities. */
4034 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4036 /* Modes for quad-float and double-float only quantities. */
4037 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4039 /* Modes for quad-float pairs and double-float only quantities. */
4040 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4042 /* Modes for condition codes. */
4043 #define CC_MODES (1 << (int) CC_MODE)
4044 #define CCFP_MODES (1 << (int) CCFP_MODE)
4046 /* Value is 1 if register/mode pair is acceptable on sparc.
4047 The funny mixture of D and T modes is because integer operations
4048 do not specially operate on tetra quantities, so non-quad-aligned
4049 registers can hold quadword quantities (except %o4 and %i4 because
4050 they cross fixed registers). */
4052 /* This points to either the 32 bit or the 64 bit version. */
4053 const int *hard_regno_mode_classes
;
4055 static const int hard_32bit_mode_classes
[] = {
4056 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4057 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4058 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4059 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4061 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4062 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4063 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4064 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4066 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4067 and none can hold SFmode/SImode values. */
4068 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4069 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4070 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4071 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4074 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4076 /* %icc, %sfp, %gsr */
4077 CC_MODES
, 0, D_MODES
4080 static const int hard_64bit_mode_classes
[] = {
4081 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4082 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4083 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4084 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4086 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4087 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4088 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4089 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4091 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4092 and none can hold SFmode/SImode values. */
4093 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4094 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4095 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4096 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4099 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4101 /* %icc, %sfp, %gsr */
4102 CC_MODES
, 0, D_MODES
4105 int sparc_mode_class
[NUM_MACHINE_MODES
];
4107 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4110 sparc_init_modes (void)
4114 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4116 switch (GET_MODE_CLASS (i
))
4119 case MODE_PARTIAL_INT
:
4120 case MODE_COMPLEX_INT
:
4121 if (GET_MODE_SIZE (i
) <= 4)
4122 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4123 else if (GET_MODE_SIZE (i
) == 8)
4124 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4125 else if (GET_MODE_SIZE (i
) == 16)
4126 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4127 else if (GET_MODE_SIZE (i
) == 32)
4128 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4130 sparc_mode_class
[i
] = 0;
4132 case MODE_VECTOR_INT
:
4133 if (GET_MODE_SIZE (i
) <= 4)
4134 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
4135 else if (GET_MODE_SIZE (i
) == 8)
4136 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
4139 case MODE_COMPLEX_FLOAT
:
4140 if (GET_MODE_SIZE (i
) <= 4)
4141 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4142 else if (GET_MODE_SIZE (i
) == 8)
4143 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4144 else if (GET_MODE_SIZE (i
) == 16)
4145 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4146 else if (GET_MODE_SIZE (i
) == 32)
4147 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4149 sparc_mode_class
[i
] = 0;
4152 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
4153 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4155 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4158 sparc_mode_class
[i
] = 0;
4164 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4166 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4168 /* Initialize the array used by REGNO_REG_CLASS. */
4169 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4171 if (i
< 16 && TARGET_V8PLUS
)
4172 sparc_regno_reg_class
[i
] = I64_REGS
;
4173 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4174 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4176 sparc_regno_reg_class
[i
] = FP_REGS
;
4178 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4180 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4182 sparc_regno_reg_class
[i
] = NO_REGS
;
4186 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4189 save_global_or_fp_reg_p (unsigned int regno
,
4190 int leaf_function ATTRIBUTE_UNUSED
)
4192 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4195 /* Return whether the return address register (%i7) is needed. */
4198 return_addr_reg_needed_p (int leaf_function
)
4200 /* If it is live, for example because of __builtin_return_address (0). */
4201 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4204 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4206 /* Loading the GOT register clobbers %o7. */
4207 || crtl
->uses_pic_offset_table
4208 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4214 /* Return whether REGNO, a local or in register, must be saved/restored. */
4217 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4219 /* General case: call-saved registers live at some point. */
4220 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4223 /* Frame pointer register (%fp) if needed. */
4224 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4227 /* Return address register (%i7) if needed. */
4228 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4231 /* GOT register (%l7) if needed. */
4232 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4235 /* If the function accesses prior frames, the frame pointer and the return
4236 address of the previous frame must be saved on the stack. */
4237 if (crtl
->accesses_prior_frames
4238 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4244 /* Compute the frame size required by the function. This function is called
4245 during the reload pass and also by sparc_expand_prologue. */
4248 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4250 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4251 int args_size
, n_global_fp_regs
= 0;
4252 bool save_local_in_regs_p
= false;
4255 /* If the function allocates dynamic stack space, the dynamic offset is
4256 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4257 if (leaf_function
&& !cfun
->calls_alloca
)
4260 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
4262 /* Calculate space needed for global registers. */
4264 for (i
= 0; i
< 8; i
++)
4265 if (save_global_or_fp_reg_p (i
, 0))
4266 n_global_fp_regs
+= 2;
4268 for (i
= 0; i
< 8; i
+= 2)
4269 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4270 n_global_fp_regs
+= 2;
4272 /* In the flat window model, find out which local and in registers need to
4273 be saved. We don't reserve space in the current frame for them as they
4274 will be spilled into the register window save area of the caller's frame.
4275 However, as soon as we use this register window save area, we must create
4276 that of the current frame to make it the live one. */
4278 for (i
= 16; i
< 32; i
++)
4279 if (save_local_or_in_reg_p (i
, leaf_function
))
4281 save_local_in_regs_p
= true;
4285 /* Calculate space needed for FP registers. */
4286 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
4287 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4288 n_global_fp_regs
+= 2;
4291 && n_global_fp_regs
== 0
4293 && !save_local_in_regs_p
)
4294 frame_size
= apparent_frame_size
= 0;
4297 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4298 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
4299 apparent_frame_size
+= n_global_fp_regs
* 4;
4301 /* We need to add the size of the outgoing argument area. */
4302 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
4304 /* And that of the register window save area. */
4305 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
4307 /* Finally, bump to the appropriate alignment. */
4308 frame_size
= SPARC_STACK_ALIGN (frame_size
);
4311 /* Set up values for use in prologue and epilogue. */
4312 sparc_frame_size
= frame_size
;
4313 sparc_apparent_frame_size
= apparent_frame_size
;
4314 sparc_n_global_fp_regs
= n_global_fp_regs
;
4315 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
4320 /* Output any necessary .register pseudo-ops. */
4323 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
4325 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4331 /* Check if %g[2367] were used without
4332 .register being printed for them already. */
4333 for (i
= 2; i
< 8; i
++)
4335 if (df_regs_ever_live_p (i
)
4336 && ! sparc_hard_reg_printed
[i
])
4338 sparc_hard_reg_printed
[i
] = 1;
4339 /* %g7 is used as TLS base register, use #ignore
4340 for it instead of #scratch. */
4341 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
4342 i
== 7 ? "ignore" : "scratch");
4349 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4351 #if PROBE_INTERVAL > 4096
4352 #error Cannot use indexed addressing mode for stack probing
4355 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4356 inclusive. These are offsets from the current stack pointer.
4358 Note that we don't use the REG+REG addressing mode for the probes because
4359 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4360 so the advantages of having a single code win here. */
4363 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
4365 rtx g1
= gen_rtx_REG (Pmode
, 1);
4367 /* See if we have a constant small number of probes to generate. If so,
4368 that's the easy case. */
4369 if (size
<= PROBE_INTERVAL
)
4371 emit_move_insn (g1
, GEN_INT (first
));
4372 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4373 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4374 emit_stack_probe (plus_constant (g1
, -size
));
4377 /* The run-time loop is made up of 10 insns in the generic case while the
4378 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4379 else if (size
<= 5 * PROBE_INTERVAL
)
4383 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
4384 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4385 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4386 emit_stack_probe (g1
);
4388 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4389 it exceeds SIZE. If only two probes are needed, this will not
4390 generate any code. Then probe at FIRST + SIZE. */
4391 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
4393 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4394 plus_constant (g1
, -PROBE_INTERVAL
)));
4395 emit_stack_probe (g1
);
4398 emit_stack_probe (plus_constant (g1
, (i
- PROBE_INTERVAL
) - size
));
4401 /* Otherwise, do the same as above, but in a loop. Note that we must be
4402 extra careful with variables wrapping around because we might be at
4403 the very top (or the very bottom) of the address space and we have
4404 to be able to handle this case properly; in particular, we use an
4405 equality test for the loop condition. */
4408 HOST_WIDE_INT rounded_size
;
4409 rtx g4
= gen_rtx_REG (Pmode
, 4);
4411 emit_move_insn (g1
, GEN_INT (first
));
4414 /* Step 1: round SIZE to the previous multiple of the interval. */
4416 rounded_size
= size
& -PROBE_INTERVAL
;
4417 emit_move_insn (g4
, GEN_INT (rounded_size
));
4420 /* Step 2: compute initial and final value of the loop counter. */
4422 /* TEST_ADDR = SP + FIRST. */
4423 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4424 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4426 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4427 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
4432 while (TEST_ADDR != LAST_ADDR)
4434 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4438 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4439 until it is equal to ROUNDED_SIZE. */
4442 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
4444 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
4447 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4448 that SIZE is equal to ROUNDED_SIZE. */
4450 if (size
!= rounded_size
)
4451 emit_stack_probe (plus_constant (g4
, rounded_size
- size
));
4454 /* Make sure nothing is scheduled before we are done. */
4455 emit_insn (gen_blockage ());
4458 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4459 absolute addresses. */
4462 output_probe_stack_range (rtx reg1
, rtx reg2
)
4464 static int labelno
= 0;
4465 char loop_lab
[32], end_lab
[32];
4468 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
4469 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
4471 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
4473 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4476 output_asm_insn ("cmp\t%0, %1", xops
);
4478 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
4480 fputs ("\tbe\t", asm_out_file
);
4481 assemble_name_raw (asm_out_file
, end_lab
);
4482 fputc ('\n', asm_out_file
);
4484 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4485 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
4486 output_asm_insn (" add\t%0, %1, %0", xops
);
4488 /* Probe at TEST_ADDR and branch. */
4490 fputs ("\tba,pt\t%xcc,", asm_out_file
);
4492 fputs ("\tba\t", asm_out_file
);
4493 assemble_name_raw (asm_out_file
, loop_lab
);
4494 fputc ('\n', asm_out_file
);
4495 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
4496 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
4498 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
4503 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4504 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4505 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4506 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4507 the action to be performed if it returns false. Return the new offset. */
4509 typedef bool (*sorr_pred_t
) (unsigned int, int);
4510 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
4513 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
4514 int offset
, int leaf_function
, sorr_pred_t save_p
,
4515 sorr_act_t action_true
, sorr_act_t action_false
)
4520 if (TARGET_ARCH64
&& high
<= 32)
4524 for (i
= low
; i
< high
; i
++)
4526 if (save_p (i
, leaf_function
))
4528 mem
= gen_frame_mem (DImode
, plus_constant (base
, offset
));
4529 if (action_true
== SORR_SAVE
)
4531 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
4532 RTX_FRAME_RELATED_P (insn
) = 1;
4534 else /* action_true == SORR_RESTORE */
4536 /* The frame pointer must be restored last since its old
4537 value may be used as base address for the frame. This
4538 is problematic in 64-bit mode only because of the lack
4539 of double-word load instruction. */
4540 if (i
== HARD_FRAME_POINTER_REGNUM
)
4543 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
4547 else if (action_false
== SORR_ADVANCE
)
4553 mem
= gen_frame_mem (DImode
, plus_constant (base
, fp_offset
));
4554 emit_move_insn (hard_frame_pointer_rtx
, mem
);
4559 for (i
= low
; i
< high
; i
+= 2)
4561 bool reg0
= save_p (i
, leaf_function
);
4562 bool reg1
= save_p (i
+ 1, leaf_function
);
4563 enum machine_mode mode
;
4568 mode
= i
< 32 ? DImode
: DFmode
;
4573 mode
= i
< 32 ? SImode
: SFmode
;
4578 mode
= i
< 32 ? SImode
: SFmode
;
4584 if (action_false
== SORR_ADVANCE
)
4589 mem
= gen_frame_mem (mode
, plus_constant (base
, offset
));
4590 if (action_true
== SORR_SAVE
)
4592 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
4593 RTX_FRAME_RELATED_P (insn
) = 1;
4597 mem
= gen_frame_mem (SImode
, plus_constant (base
, offset
));
4598 set1
= gen_rtx_SET (VOIDmode
, mem
,
4599 gen_rtx_REG (SImode
, regno
));
4600 RTX_FRAME_RELATED_P (set1
) = 1;
4602 = gen_frame_mem (SImode
, plus_constant (base
, offset
+ 4));
4603 set2
= gen_rtx_SET (VOIDmode
, mem
,
4604 gen_rtx_REG (SImode
, regno
+ 1));
4605 RTX_FRAME_RELATED_P (set2
) = 1;
4606 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4607 gen_rtx_PARALLEL (VOIDmode
,
4608 gen_rtvec (2, set1
, set2
)));
4611 else /* action_true == SORR_RESTORE */
4612 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
4614 /* Always preserve double-word alignment. */
4615 offset
= (offset
+ 8) & -8;
4622 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4625 emit_adjust_base_to_offset (rtx base
, int offset
)
4627 /* ??? This might be optimized a little as %g1 might already have a
4628 value close enough that a single add insn will do. */
4629 /* ??? Although, all of this is probably only a temporary fix because
4630 if %g1 can hold a function result, then sparc_expand_epilogue will
4631 lose (the result will be clobbered). */
4632 rtx new_base
= gen_rtx_REG (Pmode
, 1);
4633 emit_move_insn (new_base
, GEN_INT (offset
));
4634 emit_insn (gen_rtx_SET (VOIDmode
,
4635 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
4639 /* Emit code to save/restore call-saved global and FP registers. */
4642 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
4644 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
4646 base
= emit_adjust_base_to_offset (base
, offset
);
4651 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
4652 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4653 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
4654 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4657 /* Emit code to save/restore call-saved local and in registers. */
4660 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
4662 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
4664 base
= emit_adjust_base_to_offset (base
, offset
);
4668 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
4669 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
4672 /* Emit a window_save insn. */
4675 emit_window_save (rtx increment
)
4677 rtx insn
= emit_insn (gen_window_save (increment
));
4678 RTX_FRAME_RELATED_P (insn
) = 1;
4680 /* The incoming return address (%o7) is saved in %i7. */
4681 add_reg_note (insn
, REG_CFA_REGISTER
,
4682 gen_rtx_SET (VOIDmode
,
4683 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
4685 INCOMING_RETURN_ADDR_REGNUM
)));
4687 /* The window save event. */
4688 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
4690 /* The CFA is %fp, the hard frame pointer. */
4691 add_reg_note (insn
, REG_CFA_DEF_CFA
,
4692 plus_constant (hard_frame_pointer_rtx
,
4693 INCOMING_FRAME_SP_OFFSET
));
4698 /* Generate an increment for the stack pointer. */
4701 gen_stack_pointer_inc (rtx increment
)
4703 return gen_rtx_SET (VOIDmode
,
4705 gen_rtx_PLUS (Pmode
,
4710 /* Generate a decrement for the stack pointer. */
4713 gen_stack_pointer_dec (rtx decrement
)
4715 return gen_rtx_SET (VOIDmode
,
4717 gen_rtx_MINUS (Pmode
,
4722 /* Expand the function prologue. The prologue is responsible for reserving
4723 storage for the frame, saving the call-saved registers and loading the
4724 GOT register if needed. */
4727 sparc_expand_prologue (void)
4732 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4733 on the final value of the flag means deferring the prologue/epilogue
4734 expansion until just before the second scheduling pass, which is too
4735 late to emit multiple epilogues or return insns.
4737 Of course we are making the assumption that the value of the flag
4738 will not change between now and its final value. Of the three parts
4739 of the formula, only the last one can reasonably vary. Let's take a
4740 closer look, after assuming that the first two ones are set to true
4741 (otherwise the last value is effectively silenced).
4743 If only_leaf_regs_used returns false, the global predicate will also
4744 be false so the actual frame size calculated below will be positive.
4745 As a consequence, the save_register_window insn will be emitted in
4746 the instruction stream; now this insn explicitly references %fp
4747 which is not a leaf register so only_leaf_regs_used will always
4748 return false subsequently.
4750 If only_leaf_regs_used returns true, we hope that the subsequent
4751 optimization passes won't cause non-leaf registers to pop up. For
4752 example, the regrename pass has special provisions to not rename to
4753 non-leaf registers in a leaf function. */
4754 sparc_leaf_function_p
4755 = optimize
> 0 && current_function_is_leaf
&& only_leaf_regs_used ();
4757 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4759 if (flag_stack_usage_info
)
4760 current_function_static_stack_size
= size
;
4762 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4763 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4767 else if (sparc_leaf_function_p
)
4769 rtx size_int_rtx
= GEN_INT (-size
);
4772 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4773 else if (size
<= 8192)
4775 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4776 /* %sp is still the CFA register. */
4777 RTX_FRAME_RELATED_P (insn
) = 1;
4778 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4782 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4783 emit_move_insn (size_rtx
, size_int_rtx
);
4784 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4785 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4786 gen_stack_pointer_inc (size_int_rtx
));
4789 RTX_FRAME_RELATED_P (insn
) = 1;
4793 rtx size_int_rtx
= GEN_INT (-size
);
4796 emit_window_save (size_int_rtx
);
4797 else if (size
<= 8192)
4799 emit_window_save (GEN_INT (-4096));
4800 /* %sp is not the CFA register anymore. */
4801 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4805 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4806 emit_move_insn (size_rtx
, size_int_rtx
);
4807 emit_window_save (size_rtx
);
4811 if (sparc_leaf_function_p
)
4813 sparc_frame_base_reg
= stack_pointer_rtx
;
4814 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4818 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4819 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4822 if (sparc_n_global_fp_regs
> 0)
4823 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4824 sparc_frame_base_offset
4825 - sparc_apparent_frame_size
,
4828 /* Load the GOT register if needed. */
4829 if (crtl
->uses_pic_offset_table
)
4830 load_got_register ();
4832 /* Advertise that the data calculated just above are now valid. */
4833 sparc_prologue_data_valid_p
= true;
4836 /* Expand the function prologue. The prologue is responsible for reserving
4837 storage for the frame, saving the call-saved registers and loading the
4838 GOT register if needed. */
4841 sparc_flat_expand_prologue (void)
4846 sparc_leaf_function_p
= optimize
> 0 && current_function_is_leaf
;
4848 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4850 if (flag_stack_usage_info
)
4851 current_function_static_stack_size
= size
;
4853 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4854 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4856 if (sparc_save_local_in_regs_p
)
4857 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
4864 rtx size_int_rtx
, size_rtx
;
4866 size_rtx
= size_int_rtx
= GEN_INT (-size
);
4868 /* We establish the frame (i.e. decrement the stack pointer) first, even
4869 if we use a frame pointer, because we cannot clobber any call-saved
4870 registers, including the frame pointer, if we haven't created a new
4871 register save area, for the sake of compatibility with the ABI. */
4873 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4874 else if (size
<= 8192 && !frame_pointer_needed
)
4876 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4877 RTX_FRAME_RELATED_P (insn
) = 1;
4878 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4882 size_rtx
= gen_rtx_REG (Pmode
, 1);
4883 emit_move_insn (size_rtx
, size_int_rtx
);
4884 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4885 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4886 gen_stack_pointer_inc (size_int_rtx
));
4888 RTX_FRAME_RELATED_P (insn
) = 1;
4890 /* Ensure nothing is scheduled until after the frame is established. */
4891 emit_insn (gen_blockage ());
4893 if (frame_pointer_needed
)
4895 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4896 gen_rtx_MINUS (Pmode
,
4899 RTX_FRAME_RELATED_P (insn
) = 1;
4901 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4902 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4903 plus_constant (stack_pointer_rtx
,
4907 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
4909 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
4910 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
4912 insn
= emit_move_insn (i7
, o7
);
4913 RTX_FRAME_RELATED_P (insn
) = 1;
4915 add_reg_note (insn
, REG_CFA_REGISTER
,
4916 gen_rtx_SET (VOIDmode
, i7
, o7
));
4918 /* Prevent this instruction from ever being considered dead,
4919 even if this function has no epilogue. */
4920 emit_insn (gen_rtx_USE (VOIDmode
, i7
));
4924 if (frame_pointer_needed
)
4926 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4927 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4931 sparc_frame_base_reg
= stack_pointer_rtx
;
4932 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4935 if (sparc_n_global_fp_regs
> 0)
4936 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4937 sparc_frame_base_offset
4938 - sparc_apparent_frame_size
,
4941 /* Load the GOT register if needed. */
4942 if (crtl
->uses_pic_offset_table
)
4943 load_got_register ();
4945 /* Advertise that the data calculated just above are now valid. */
4946 sparc_prologue_data_valid_p
= true;
4949 /* This function generates the assembly code for function entry, which boils
4950 down to emitting the necessary .register directives. */
4953 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4955 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4957 gcc_assert (sparc_leaf_function_p
== current_function_uses_only_leaf_regs
);
4959 sparc_output_scratch_registers (file
);
4962 /* Expand the function epilogue, either normal or part of a sibcall.
4963 We emit all the instructions except the return or the call. */
4966 sparc_expand_epilogue (bool for_eh
)
4968 HOST_WIDE_INT size
= sparc_frame_size
;
4970 if (sparc_n_global_fp_regs
> 0)
4971 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4972 sparc_frame_base_offset
4973 - sparc_apparent_frame_size
,
4976 if (size
== 0 || for_eh
)
4978 else if (sparc_leaf_function_p
)
4981 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
4982 else if (size
<= 8192)
4984 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4985 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
4989 rtx reg
= gen_rtx_REG (Pmode
, 1);
4990 emit_move_insn (reg
, GEN_INT (-size
));
4991 emit_insn (gen_stack_pointer_dec (reg
));
4996 /* Expand the function epilogue, either normal or part of a sibcall.
4997 We emit all the instructions except the return or the call. */
5000 sparc_flat_expand_epilogue (bool for_eh
)
5002 HOST_WIDE_INT size
= sparc_frame_size
;
5004 if (sparc_n_global_fp_regs
> 0)
5005 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5006 sparc_frame_base_offset
5007 - sparc_apparent_frame_size
,
5010 /* If we have a frame pointer, we'll need both to restore it before the
5011 frame is destroyed and use its current value in destroying the frame.
5012 Since we don't have an atomic way to do that in the flat window model,
5013 we save the current value into a temporary register (%g1). */
5014 if (frame_pointer_needed
&& !for_eh
)
5015 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5017 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5018 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5019 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5021 if (sparc_save_local_in_regs_p
)
5022 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5023 sparc_frame_base_offset
,
5026 if (size
== 0 || for_eh
)
5028 else if (frame_pointer_needed
)
5030 /* Make sure the frame is destroyed after everything else is done. */
5031 emit_insn (gen_blockage ());
5033 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5038 emit_insn (gen_blockage ());
5041 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
5042 else if (size
<= 8192)
5044 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5045 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
5049 rtx reg
= gen_rtx_REG (Pmode
, 1);
5050 emit_move_insn (reg
, GEN_INT (-size
));
5051 emit_insn (gen_stack_pointer_dec (reg
));
5056 /* Return true if it is appropriate to emit `return' instructions in the
5057 body of a function. */
5060 sparc_can_use_return_insn_p (void)
5062 return sparc_prologue_data_valid_p
5063 && sparc_n_global_fp_regs
== 0
5065 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5066 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5069 /* This function generates the assembly code for function exit. */
5072 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5074 /* If the last two instructions of a function are "call foo; dslot;"
5075 the return address might point to the first instruction in the next
5076 function and we have to output a dummy nop for the sake of sane
5077 backtraces in such cases. This is pointless for sibling calls since
5078 the return address is explicitly adjusted. */
5080 rtx insn
, last_real_insn
;
5082 insn
= get_last_insn ();
5084 last_real_insn
= prev_real_insn (insn
);
5086 && GET_CODE (last_real_insn
) == INSN
5087 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5088 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5091 && CALL_P (last_real_insn
)
5092 && !SIBLING_CALL_P (last_real_insn
))
5093 fputs("\tnop\n", file
);
5095 sparc_output_deferred_case_vectors ();
5098 /* Output a 'restore' instruction. */
5101 output_restore (rtx pat
)
5107 fputs ("\t restore\n", asm_out_file
);
5111 gcc_assert (GET_CODE (pat
) == SET
);
5113 operands
[0] = SET_DEST (pat
);
5114 pat
= SET_SRC (pat
);
5116 switch (GET_CODE (pat
))
5119 operands
[1] = XEXP (pat
, 0);
5120 operands
[2] = XEXP (pat
, 1);
5121 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5124 operands
[1] = XEXP (pat
, 0);
5125 operands
[2] = XEXP (pat
, 1);
5126 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5129 operands
[1] = XEXP (pat
, 0);
5130 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5131 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5135 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5140 /* Output a return. */
5143 output_return (rtx insn
)
5145 if (crtl
->calls_eh_return
)
5147 /* If the function uses __builtin_eh_return, the eh_return
5148 machinery occupies the delay slot. */
5149 gcc_assert (!final_sequence
);
5151 if (flag_delayed_branch
)
5153 if (!TARGET_FLAT
&& TARGET_V9
)
5154 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5158 fputs ("\trestore\n", asm_out_file
);
5160 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5163 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5168 fputs ("\trestore\n", asm_out_file
);
5170 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5171 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5174 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5176 /* This is a leaf or flat function so we don't have to bother restoring
5177 the register window, which frees us from dealing with the convoluted
5178 semantics of restore/return. We simply output the jump to the
5179 return address and the insn in the delay slot (if any). */
5181 return "jmp\t%%o7+%)%#";
5185 /* This is a regular function so we have to restore the register window.
5186 We may have a pending insn for the delay slot, which will be either
5187 combined with the 'restore' instruction or put in the delay slot of
5188 the 'return' instruction. */
5194 delay
= NEXT_INSN (insn
);
5197 pat
= PATTERN (delay
);
5199 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5201 epilogue_renumber (&pat
, 0);
5202 return "return\t%%i7+%)%#";
5206 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5207 output_restore (pat
);
5208 PATTERN (delay
) = gen_blockage ();
5209 INSN_CODE (delay
) = -1;
5214 /* The delay slot is empty. */
5216 return "return\t%%i7+%)\n\t nop";
5217 else if (flag_delayed_branch
)
5218 return "jmp\t%%i7+%)\n\t restore";
5220 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5227 /* Output a sibling call. */
5230 output_sibcall (rtx insn
, rtx call_operand
)
5234 gcc_assert (flag_delayed_branch
);
5236 operands
[0] = call_operand
;
5238 if (sparc_leaf_function_p
|| TARGET_FLAT
)
5240 /* This is a leaf or flat function so we don't have to bother restoring
5241 the register window. We simply output the jump to the function and
5242 the insn in the delay slot (if any). */
5244 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
5247 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5250 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5251 it into branch if possible. */
5252 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5257 /* This is a regular function so we have to restore the register window.
5258 We may have a pending insn for the delay slot, which will be combined
5259 with the 'restore' instruction. */
5261 output_asm_insn ("call\t%a0, 0", operands
);
5265 rtx delay
= NEXT_INSN (insn
);
5268 output_restore (PATTERN (delay
));
5270 PATTERN (delay
) = gen_blockage ();
5271 INSN_CODE (delay
) = -1;
5274 output_restore (NULL_RTX
);
5280 /* Functions for handling argument passing.
5282 For 32-bit, the first 6 args are normally in registers and the rest are
5283 pushed. Any arg that starts within the first 6 words is at least
5284 partially passed in a register unless its data type forbids.
5286 For 64-bit, the argument registers are laid out as an array of 16 elements
5287 and arguments are added sequentially. The first 6 int args and up to the
5288 first 16 fp args (depending on size) are passed in regs.
5290 Slot Stack Integral Float Float in structure Double Long Double
5291 ---- ----- -------- ----- ------------------ ------ -----------
5292 15 [SP+248] %f31 %f30,%f31 %d30
5293 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5294 13 [SP+232] %f27 %f26,%f27 %d26
5295 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5296 11 [SP+216] %f23 %f22,%f23 %d22
5297 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5298 9 [SP+200] %f19 %f18,%f19 %d18
5299 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5300 7 [SP+184] %f15 %f14,%f15 %d14
5301 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5302 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5303 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5304 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5305 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5306 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5307 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5309 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5311 Integral arguments are always passed as 64-bit quantities appropriately
5314 Passing of floating point values is handled as follows.
5315 If a prototype is in scope:
5316 If the value is in a named argument (i.e. not a stdarg function or a
5317 value not part of the `...') then the value is passed in the appropriate
5319 If the value is part of the `...' and is passed in one of the first 6
5320 slots then the value is passed in the appropriate int reg.
5321 If the value is part of the `...' and is not passed in one of the first 6
5322 slots then the value is passed in memory.
5323 If a prototype is not in scope:
5324 If the value is one of the first 6 arguments the value is passed in the
5325 appropriate integer reg and the appropriate fp reg.
5326 If the value is not one of the first 6 arguments the value is passed in
5327 the appropriate fp reg and in memory.
5330 Summary of the calling conventions implemented by GCC on the SPARC:
5333 size argument return value
5335 small integer <4 int. reg. int. reg.
5336 word 4 int. reg. int. reg.
5337 double word 8 int. reg. int. reg.
5339 _Complex small integer <8 int. reg. int. reg.
5340 _Complex word 8 int. reg. int. reg.
5341 _Complex double word 16 memory int. reg.
5343 vector integer <=8 int. reg. FP reg.
5344 vector integer >8 memory memory
5346 float 4 int. reg. FP reg.
5347 double 8 int. reg. FP reg.
5348 long double 16 memory memory
5350 _Complex float 8 memory FP reg.
5351 _Complex double 16 memory FP reg.
5352 _Complex long double 32 memory FP reg.
5354 vector float any memory memory
5356 aggregate any memory memory
5361 size argument return value
5363 small integer <8 int. reg. int. reg.
5364 word 8 int. reg. int. reg.
5365 double word 16 int. reg. int. reg.
5367 _Complex small integer <16 int. reg. int. reg.
5368 _Complex word 16 int. reg. int. reg.
5369 _Complex double word 32 memory int. reg.
5371 vector integer <=16 FP reg. FP reg.
5372 vector integer 16<s<=32 memory FP reg.
5373 vector integer >32 memory memory
5375 float 4 FP reg. FP reg.
5376 double 8 FP reg. FP reg.
5377 long double 16 FP reg. FP reg.
5379 _Complex float 8 FP reg. FP reg.
5380 _Complex double 16 FP reg. FP reg.
5381 _Complex long double 32 memory FP reg.
5383 vector float <=16 FP reg. FP reg.
5384 vector float 16<s<=32 memory FP reg.
5385 vector float >32 memory memory
5387 aggregate <=16 reg. reg.
5388 aggregate 16<s<=32 memory reg.
5389 aggregate >32 memory memory
5393 Note #1: complex floating-point types follow the extended SPARC ABIs as
5394 implemented by the Sun compiler.
5396 Note #2: integral vector types follow the scalar floating-point types
5397 conventions to match what is implemented by the Sun VIS SDK.
5399 Note #3: floating-point vector types follow the aggregate types
5403 /* Maximum number of int regs for args. */
5404 #define SPARC_INT_ARG_MAX 6
5405 /* Maximum number of fp regs for args. */
5406 #define SPARC_FP_ARG_MAX 16
5408 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5410 /* Handle the INIT_CUMULATIVE_ARGS macro.
5411 Initialize a variable CUM of type CUMULATIVE_ARGS
5412 for a call to a function whose data type is FNTYPE.
5413 For a library call, FNTYPE is 0. */
5416 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
5417 rtx libname ATTRIBUTE_UNUSED
,
5418 tree fndecl ATTRIBUTE_UNUSED
)
5421 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
5422 cum
->libcall_p
= fntype
== 0;
5425 /* Handle promotion of pointer and integer arguments. */
5427 static enum machine_mode
5428 sparc_promote_function_mode (const_tree type
,
5429 enum machine_mode mode
,
5431 const_tree fntype ATTRIBUTE_UNUSED
,
5432 int for_return ATTRIBUTE_UNUSED
)
5434 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
5436 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
5440 /* Integral arguments are passed as full words, as per the ABI. */
5441 if (GET_MODE_CLASS (mode
) == MODE_INT
5442 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5448 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5451 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5453 return TARGET_ARCH64
? true : false;
5456 /* Scan the record type TYPE and return the following predicates:
5457 - INTREGS_P: the record contains at least one field or sub-field
5458 that is eligible for promotion in integer registers.
5459 - FP_REGS_P: the record contains at least one field or sub-field
5460 that is eligible for promotion in floating-point registers.
5461 - PACKED_P: the record contains at least one field that is packed.
5463 Sub-fields are not taken into account for the PACKED_P predicate. */
5466 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
5471 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5473 if (TREE_CODE (field
) == FIELD_DECL
)
5475 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5476 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
5477 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5478 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5484 if (packed_p
&& DECL_PACKED (field
))
5490 /* Compute the slot number to pass an argument in.
5491 Return the slot number or -1 if passing on the stack.
5493 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5494 the preceding args and about the function being called.
5495 MODE is the argument's machine mode.
5496 TYPE is the data type of the argument (as a tree).
5497 This is null for libcalls where that information may
5499 NAMED is nonzero if this argument is a named parameter
5500 (otherwise it is an extra parameter matching an ellipsis).
5501 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5502 *PREGNO records the register number to use if scalar type.
5503 *PPADDING records the amount of padding needed in words. */
5506 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
5507 const_tree type
, bool named
, bool incoming_p
,
5508 int *pregno
, int *ppadding
)
5510 int regbase
= (incoming_p
5511 ? SPARC_INCOMING_INT_ARG_FIRST
5512 : SPARC_OUTGOING_INT_ARG_FIRST
);
5513 int slotno
= cum
->words
;
5514 enum mode_class mclass
;
5519 if (type
&& TREE_ADDRESSABLE (type
))
5525 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
5528 /* For SPARC64, objects requiring 16-byte alignment get it. */
5530 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
5531 && (slotno
& 1) != 0)
5532 slotno
++, *ppadding
= 1;
5534 mclass
= GET_MODE_CLASS (mode
);
5535 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5537 /* Vector types deserve special treatment because they are
5538 polymorphic wrt their mode, depending upon whether VIS
5539 instructions are enabled. */
5540 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
5542 /* The SPARC port defines no floating-point vector modes. */
5543 gcc_assert (mode
== BLKmode
);
5547 /* Integral vector types should either have a vector
5548 mode or an integral mode, because we are guaranteed
5549 by pass_by_reference that their size is not greater
5550 than 16 bytes and TImode is 16-byte wide. */
5551 gcc_assert (mode
!= BLKmode
);
5553 /* Vector integers are handled like floats according to
5555 mclass
= MODE_FLOAT
;
5562 case MODE_COMPLEX_FLOAT
:
5563 case MODE_VECTOR_INT
:
5564 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
5566 if (slotno
>= SPARC_FP_ARG_MAX
)
5568 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
5569 /* Arguments filling only one single FP register are
5570 right-justified in the outer double FP register. */
5571 if (GET_MODE_SIZE (mode
) <= 4)
5578 case MODE_COMPLEX_INT
:
5579 if (slotno
>= SPARC_INT_ARG_MAX
)
5581 regno
= regbase
+ slotno
;
5585 if (mode
== VOIDmode
)
5586 /* MODE is VOIDmode when generating the actual call. */
5589 gcc_assert (mode
== BLKmode
);
5593 || (TREE_CODE (type
) != VECTOR_TYPE
5594 && TREE_CODE (type
) != RECORD_TYPE
))
5596 if (slotno
>= SPARC_INT_ARG_MAX
)
5598 regno
= regbase
+ slotno
;
5600 else /* TARGET_ARCH64 && type */
5602 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
5604 /* First see what kinds of registers we would need. */
5605 if (TREE_CODE (type
) == VECTOR_TYPE
)
5608 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
5610 /* The ABI obviously doesn't specify how packed structures
5611 are passed. These are defined to be passed in int regs
5612 if possible, otherwise memory. */
5613 if (packed_p
|| !named
)
5614 fpregs_p
= 0, intregs_p
= 1;
5616 /* If all arg slots are filled, then must pass on stack. */
5617 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
5620 /* If there are only int args and all int arg slots are filled,
5621 then must pass on stack. */
5622 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
5625 /* Note that even if all int arg slots are filled, fp members may
5626 still be passed in regs if such regs are available.
5627 *PREGNO isn't set because there may be more than one, it's up
5628 to the caller to compute them. */
5641 /* Handle recursive register counting for structure field layout. */
5643 struct function_arg_record_value_parms
5645 rtx ret
; /* return expression being built. */
5646 int slotno
; /* slot number of the argument. */
5647 int named
; /* whether the argument is named. */
5648 int regbase
; /* regno of the base register. */
5649 int stack
; /* 1 if part of the argument is on the stack. */
5650 int intoffset
; /* offset of the first pending integer field. */
5651 unsigned int nregs
; /* number of words passed in registers. */
5654 static void function_arg_record_value_3
5655 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
5656 static void function_arg_record_value_2
5657 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5658 static void function_arg_record_value_1
5659 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5660 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
5661 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
5663 /* A subroutine of function_arg_record_value. Traverse the structure
5664 recursively and determine how many registers will be required. */
5667 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
5668 struct function_arg_record_value_parms
*parms
,
5673 /* We need to compute how many registers are needed so we can
5674 allocate the PARALLEL but before we can do that we need to know
5675 whether there are any packed fields. The ABI obviously doesn't
5676 specify how structures are passed in this case, so they are
5677 defined to be passed in int regs if possible, otherwise memory,
5678 regardless of whether there are fp values present. */
5681 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5683 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5690 /* Compute how many registers we need. */
5691 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5693 if (TREE_CODE (field
) == FIELD_DECL
)
5695 HOST_WIDE_INT bitpos
= startbitpos
;
5697 if (DECL_SIZE (field
) != 0)
5699 if (integer_zerop (DECL_SIZE (field
)))
5702 if (host_integerp (bit_position (field
), 1))
5703 bitpos
+= int_bit_position (field
);
5706 /* ??? FIXME: else assume zero offset. */
5708 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5709 function_arg_record_value_1 (TREE_TYPE (field
),
5713 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5714 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5719 if (parms
->intoffset
!= -1)
5721 unsigned int startbit
, endbit
;
5722 int intslots
, this_slotno
;
5724 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
5725 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5727 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5728 this_slotno
= parms
->slotno
+ parms
->intoffset
5731 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5733 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5734 /* We need to pass this field on the stack. */
5738 parms
->nregs
+= intslots
;
5739 parms
->intoffset
= -1;
5742 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5743 If it wasn't true we wouldn't be here. */
5744 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5745 && DECL_MODE (field
) == BLKmode
)
5746 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5747 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5754 if (parms
->intoffset
== -1)
5755 parms
->intoffset
= bitpos
;
5761 /* A subroutine of function_arg_record_value. Assign the bits of the
5762 structure between parms->intoffset and bitpos to integer registers. */
5765 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
5766 struct function_arg_record_value_parms
*parms
)
5768 enum machine_mode mode
;
5770 unsigned int startbit
, endbit
;
5771 int this_slotno
, intslots
, intoffset
;
5774 if (parms
->intoffset
== -1)
5777 intoffset
= parms
->intoffset
;
5778 parms
->intoffset
= -1;
5780 startbit
= intoffset
& -BITS_PER_WORD
;
5781 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5782 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5783 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
5785 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
5789 /* If this is the trailing part of a word, only load that much into
5790 the register. Otherwise load the whole register. Note that in
5791 the latter case we may pick up unwanted bits. It's not a problem
5792 at the moment but may wish to revisit. */
5794 if (intoffset
% BITS_PER_WORD
!= 0)
5795 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5800 intoffset
/= BITS_PER_UNIT
;
5803 regno
= parms
->regbase
+ this_slotno
;
5804 reg
= gen_rtx_REG (mode
, regno
);
5805 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5806 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5809 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5814 while (intslots
> 0);
5817 /* A subroutine of function_arg_record_value. Traverse the structure
5818 recursively and assign bits to floating point registers. Track which
5819 bits in between need integer registers; invoke function_arg_record_value_3
5820 to make that happen. */
5823 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
5824 struct function_arg_record_value_parms
*parms
,
5830 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5832 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5839 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5841 if (TREE_CODE (field
) == FIELD_DECL
)
5843 HOST_WIDE_INT bitpos
= startbitpos
;
5845 if (DECL_SIZE (field
) != 0)
5847 if (integer_zerop (DECL_SIZE (field
)))
5850 if (host_integerp (bit_position (field
), 1))
5851 bitpos
+= int_bit_position (field
);
5854 /* ??? FIXME: else assume zero offset. */
5856 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5857 function_arg_record_value_2 (TREE_TYPE (field
),
5861 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5862 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5867 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
5868 int regno
, nregs
, pos
;
5869 enum machine_mode mode
= DECL_MODE (field
);
5872 function_arg_record_value_3 (bitpos
, parms
);
5874 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5877 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5878 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5880 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5882 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5888 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
5889 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
5891 reg
= gen_rtx_REG (mode
, regno
);
5892 pos
= bitpos
/ BITS_PER_UNIT
;
5893 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5894 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5898 regno
+= GET_MODE_SIZE (mode
) / 4;
5899 reg
= gen_rtx_REG (mode
, regno
);
5900 pos
+= GET_MODE_SIZE (mode
);
5901 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5902 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5908 if (parms
->intoffset
== -1)
5909 parms
->intoffset
= bitpos
;
5915 /* Used by function_arg and sparc_function_value_1 to implement the complex
5916 conventions of the 64-bit ABI for passing and returning structures.
5917 Return an expression valid as a return value for the FUNCTION_ARG
5918 and TARGET_FUNCTION_VALUE.
5920 TYPE is the data type of the argument (as a tree).
5921 This is null for libcalls where that information may
5923 MODE is the argument's machine mode.
5924 SLOTNO is the index number of the argument's slot in the parameter array.
5925 NAMED is nonzero if this argument is a named parameter
5926 (otherwise it is an extra parameter matching an ellipsis).
5927 REGBASE is the regno of the base register for the parameter array. */
5930 function_arg_record_value (const_tree type
, enum machine_mode mode
,
5931 int slotno
, int named
, int regbase
)
5933 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5934 struct function_arg_record_value_parms parms
;
5937 parms
.ret
= NULL_RTX
;
5938 parms
.slotno
= slotno
;
5939 parms
.named
= named
;
5940 parms
.regbase
= regbase
;
5943 /* Compute how many registers we need. */
5945 parms
.intoffset
= 0;
5946 function_arg_record_value_1 (type
, 0, &parms
, false);
5948 /* Take into account pending integer fields. */
5949 if (parms
.intoffset
!= -1)
5951 unsigned int startbit
, endbit
;
5952 int intslots
, this_slotno
;
5954 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
5955 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5956 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5957 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
5959 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5961 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5962 /* We need to pass this field on the stack. */
5966 parms
.nregs
+= intslots
;
5968 nregs
= parms
.nregs
;
5970 /* Allocate the vector and handle some annoying special cases. */
5973 /* ??? Empty structure has no value? Duh? */
5976 /* Though there's nothing really to store, return a word register
5977 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5978 leads to breakage due to the fact that there are zero bytes to
5980 return gen_rtx_REG (mode
, regbase
);
5984 /* ??? C++ has structures with no fields, and yet a size. Give up
5985 for now and pass everything back in integer registers. */
5986 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5988 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
5989 nregs
= SPARC_INT_ARG_MAX
- slotno
;
5991 gcc_assert (nregs
!= 0);
5993 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
5995 /* If at least one field must be passed on the stack, generate
5996 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5997 also be passed on the stack. We can't do much better because the
5998 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
5999 of structures for which the fields passed exclusively in registers
6000 are not at the beginning of the structure. */
6002 XVECEXP (parms
.ret
, 0, 0)
6003 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6005 /* Fill in the entries. */
6007 parms
.intoffset
= 0;
6008 function_arg_record_value_2 (type
, 0, &parms
, false);
6009 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
6011 gcc_assert (parms
.nregs
== nregs
);
6016 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6017 of the 64-bit ABI for passing and returning unions.
6018 Return an expression valid as a return value for the FUNCTION_ARG
6019 and TARGET_FUNCTION_VALUE.
6021 SIZE is the size in bytes of the union.
6022 MODE is the argument's machine mode.
6023 REGNO is the hard register the union will be passed in. */
6026 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
6029 int nwords
= ROUND_ADVANCE (size
), i
;
6032 /* See comment in previous function for empty structures. */
6034 return gen_rtx_REG (mode
, regno
);
6036 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6039 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6041 for (i
= 0; i
< nwords
; i
++)
6043 /* Unions are passed left-justified. */
6044 XVECEXP (regs
, 0, i
)
6045 = gen_rtx_EXPR_LIST (VOIDmode
,
6046 gen_rtx_REG (word_mode
, regno
),
6047 GEN_INT (UNITS_PER_WORD
* i
));
6054 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6055 for passing and returning large (BLKmode) vectors.
6056 Return an expression valid as a return value for the FUNCTION_ARG
6057 and TARGET_FUNCTION_VALUE.
6059 SIZE is the size in bytes of the vector (at least 8 bytes).
6060 REGNO is the FP hard register the vector will be passed in. */
6063 function_arg_vector_value (int size
, int regno
)
6065 int i
, nregs
= size
/ 8;
6068 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6070 for (i
= 0; i
< nregs
; i
++)
6072 XVECEXP (regs
, 0, i
)
6073 = gen_rtx_EXPR_LIST (VOIDmode
,
6074 gen_rtx_REG (DImode
, regno
+ 2*i
),
6081 /* Determine where to put an argument to a function.
6082 Value is zero to push the argument on the stack,
6083 or a hard register in which to store the argument.
6085 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6086 the preceding args and about the function being called.
6087 MODE is the argument's machine mode.
6088 TYPE is the data type of the argument (as a tree).
6089 This is null for libcalls where that information may
6091 NAMED is true if this argument is a named parameter
6092 (otherwise it is an extra parameter matching an ellipsis).
6093 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6094 TARGET_FUNCTION_INCOMING_ARG. */
6097 sparc_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
6098 const_tree type
, bool named
, bool incoming_p
)
6100 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6102 int regbase
= (incoming_p
6103 ? SPARC_INCOMING_INT_ARG_FIRST
6104 : SPARC_OUTGOING_INT_ARG_FIRST
);
6105 int slotno
, regno
, padding
;
6106 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6108 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6113 /* Vector types deserve special treatment because they are polymorphic wrt
6114 their mode, depending upon whether VIS instructions are enabled. */
6115 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6117 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6118 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6119 || (TARGET_ARCH64
&& size
<= 16));
6121 if (mode
== BLKmode
)
6122 return function_arg_vector_value (size
,
6123 SPARC_FP_ARG_FIRST
+ 2*slotno
);
6125 mclass
= MODE_FLOAT
;
6129 return gen_rtx_REG (mode
, regno
);
6131 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6132 and are promoted to registers if possible. */
6133 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6135 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6136 gcc_assert (size
<= 16);
6138 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6141 /* Unions up to 16 bytes in size are passed in integer registers. */
6142 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6144 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6145 gcc_assert (size
<= 16);
6147 return function_arg_union_value (size
, mode
, slotno
, regno
);
6150 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6151 but also have the slot allocated for them.
6152 If no prototype is in scope fp values in register slots get passed
6153 in two places, either fp regs and int regs or fp regs and memory. */
6154 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6155 && SPARC_FP_REG_P (regno
))
6157 rtx reg
= gen_rtx_REG (mode
, regno
);
6158 if (cum
->prototype_p
|| cum
->libcall_p
)
6160 /* "* 2" because fp reg numbers are recorded in 4 byte
6163 /* ??? This will cause the value to be passed in the fp reg and
6164 in the stack. When a prototype exists we want to pass the
6165 value in the reg but reserve space on the stack. That's an
6166 optimization, and is deferred [for a bit]. */
6167 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6168 return gen_rtx_PARALLEL (mode
,
6170 gen_rtx_EXPR_LIST (VOIDmode
,
6171 NULL_RTX
, const0_rtx
),
6172 gen_rtx_EXPR_LIST (VOIDmode
,
6176 /* ??? It seems that passing back a register even when past
6177 the area declared by REG_PARM_STACK_SPACE will allocate
6178 space appropriately, and will not copy the data onto the
6179 stack, exactly as we desire.
6181 This is due to locate_and_pad_parm being called in
6182 expand_call whenever reg_parm_stack_space > 0, which
6183 while beneficial to our example here, would seem to be
6184 in error from what had been intended. Ho hum... -- r~ */
6192 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6196 /* On incoming, we don't need to know that the value
6197 is passed in %f0 and %i0, and it confuses other parts
6198 causing needless spillage even on the simplest cases. */
6202 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6203 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6205 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6206 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6208 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6212 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6213 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6214 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6219 /* All other aggregate types are passed in an integer register in a mode
6220 corresponding to the size of the type. */
6221 else if (type
&& AGGREGATE_TYPE_P (type
))
6223 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6224 gcc_assert (size
<= 16);
6226 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6229 return gen_rtx_REG (mode
, regno
);
6232 /* Handle the TARGET_FUNCTION_ARG target hook. */
6235 sparc_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
6236 const_tree type
, bool named
)
6238 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6241 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6244 sparc_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
6245 const_tree type
, bool named
)
6247 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
6250 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6253 sparc_function_arg_boundary (enum machine_mode mode
, const_tree type
)
6255 return ((TARGET_ARCH64
6256 && (GET_MODE_ALIGNMENT (mode
) == 128
6257 || (type
&& TYPE_ALIGN (type
) == 128)))
6262 /* For an arg passed partly in registers and partly in memory,
6263 this is the number of bytes of registers used.
6264 For args passed entirely in registers or entirely in memory, zero.
6266 Any arg that starts in the first 6 regs but won't entirely fit in them
6267 needs partial registers on v8. On v9, structures with integer
6268 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6269 values that begin in the last fp reg [where "last fp reg" varies with the
6270 mode] will be split between that reg and memory. */
6273 sparc_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
6274 tree type
, bool named
)
6276 int slotno
, regno
, padding
;
6278 /* We pass false for incoming_p here, it doesn't matter. */
6279 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
6280 false, ®no
, &padding
);
6287 if ((slotno
+ (mode
== BLKmode
6288 ? ROUND_ADVANCE (int_size_in_bytes (type
))
6289 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
6290 > SPARC_INT_ARG_MAX
)
6291 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
6295 /* We are guaranteed by pass_by_reference that the size of the
6296 argument is not greater than 16 bytes, so we only need to return
6297 one word if the argument is partially passed in registers. */
6299 if (type
&& AGGREGATE_TYPE_P (type
))
6301 int size
= int_size_in_bytes (type
);
6303 if (size
> UNITS_PER_WORD
6304 && slotno
== SPARC_INT_ARG_MAX
- 1)
6305 return UNITS_PER_WORD
;
6307 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
6308 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6309 && ! (TARGET_FPU
&& named
)))
6311 /* The complex types are passed as packed types. */
6312 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6313 && slotno
== SPARC_INT_ARG_MAX
- 1)
6314 return UNITS_PER_WORD
;
6316 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6318 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
6320 return UNITS_PER_WORD
;
6327 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6328 Specify whether to pass the argument by reference. */
6331 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6332 enum machine_mode mode
, const_tree type
,
6333 bool named ATTRIBUTE_UNUSED
)
6336 /* Original SPARC 32-bit ABI says that structures and unions,
6337 and quad-precision floats are passed by reference. For Pascal,
6338 also pass arrays by reference. All other base types are passed
6341 Extended ABI (as implemented by the Sun compiler) says that all
6342 complex floats are passed by reference. Pass complex integers
6343 in registers up to 8 bytes. More generally, enforce the 2-word
6344 cap for passing arguments in registers.
6346 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6347 integers are passed like floats of the same size, that is in
6348 registers up to 8 bytes. Pass all vector floats by reference
6349 like structure and unions. */
6350 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6352 /* Catch CDImode, TFmode, DCmode and TCmode. */
6353 || GET_MODE_SIZE (mode
) > 8
6355 && TREE_CODE (type
) == VECTOR_TYPE
6356 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6358 /* Original SPARC 64-bit ABI says that structures and unions
6359 smaller than 16 bytes are passed in registers, as well as
6360 all other base types.
6362 Extended ABI (as implemented by the Sun compiler) says that
6363 complex floats are passed in registers up to 16 bytes. Pass
6364 all complex integers in registers up to 16 bytes. More generally,
6365 enforce the 2-word cap for passing arguments in registers.
6367 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6368 integers are passed like floats of the same size, that is in
6369 registers (up to 16 bytes). Pass all vector floats like structure
6372 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
6373 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6374 /* Catch CTImode and TCmode. */
6375 || GET_MODE_SIZE (mode
) > 16);
6378 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6379 Update the data in CUM to advance over an argument
6380 of mode MODE and data type TYPE.
6381 TYPE is null for libcalls where that information may not be available. */
6384 sparc_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
6385 const_tree type
, bool named
)
6387 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6390 /* We pass false for incoming_p here, it doesn't matter. */
6391 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
6393 /* If argument requires leading padding, add it. */
6394 cum
->words
+= padding
;
6398 cum
->words
+= (mode
!= BLKmode
6399 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6400 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6404 if (type
&& AGGREGATE_TYPE_P (type
))
6406 int size
= int_size_in_bytes (type
);
6410 else if (size
<= 16)
6412 else /* passed by reference */
6417 cum
->words
+= (mode
!= BLKmode
6418 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6419 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6424 /* Handle the FUNCTION_ARG_PADDING macro.
6425 For the 64 bit ABI structs are always stored left shifted in their
6429 function_arg_padding (enum machine_mode mode
, const_tree type
)
6431 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
6434 /* Fall back to the default. */
6435 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
6438 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6439 Specify whether to return the return value in memory. */
6442 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
6445 /* Original SPARC 32-bit ABI says that structures and unions,
6446 and quad-precision floats are returned in memory. All other
6447 base types are returned in registers.
6449 Extended ABI (as implemented by the Sun compiler) says that
6450 all complex floats are returned in registers (8 FP registers
6451 at most for '_Complex long double'). Return all complex integers
6452 in registers (4 at most for '_Complex long long').
6454 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6455 integers are returned like floats of the same size, that is in
6456 registers up to 8 bytes and in memory otherwise. Return all
6457 vector floats in memory like structure and unions; note that
6458 they always have BLKmode like the latter. */
6459 return (TYPE_MODE (type
) == BLKmode
6460 || TYPE_MODE (type
) == TFmode
6461 || (TREE_CODE (type
) == VECTOR_TYPE
6462 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6464 /* Original SPARC 64-bit ABI says that structures and unions
6465 smaller than 32 bytes are returned in registers, as well as
6466 all other base types.
6468 Extended ABI (as implemented by the Sun compiler) says that all
6469 complex floats are returned in registers (8 FP registers at most
6470 for '_Complex long double'). Return all complex integers in
6471 registers (4 at most for '_Complex TItype').
6473 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6474 integers are returned like floats of the same size, that is in
6475 registers. Return all vector floats like structure and unions;
6476 note that they always have BLKmode like the latter. */
6477 return (TYPE_MODE (type
) == BLKmode
6478 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
6481 /* Handle the TARGET_STRUCT_VALUE target hook.
6482 Return where to find the structure return value address. */
6485 sparc_struct_value_rtx (tree fndecl
, int incoming
)
6494 mem
= gen_frame_mem (Pmode
, plus_constant (frame_pointer_rtx
,
6495 STRUCT_VALUE_OFFSET
));
6497 mem
= gen_frame_mem (Pmode
, plus_constant (stack_pointer_rtx
,
6498 STRUCT_VALUE_OFFSET
));
6500 /* Only follow the SPARC ABI for fixed-size structure returns.
6501 Variable size structure returns are handled per the normal
6502 procedures in GCC. This is enabled by -mstd-struct-return */
6504 && sparc_std_struct_return
6505 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
6506 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
6508 /* We must check and adjust the return address, as it is
6509 optional as to whether the return object is really
6511 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
6512 rtx scratch
= gen_reg_rtx (SImode
);
6513 rtx endlab
= gen_label_rtx ();
6515 /* Calculate the return object size */
6516 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
6517 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
6518 /* Construct a temporary return value */
6520 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
6522 /* Implement SPARC 32-bit psABI callee return struct checking:
6524 Fetch the instruction where we will return to and see if
6525 it's an unimp instruction (the most significant 10 bits
6527 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
6528 plus_constant (ret_reg
, 8)));
6529 /* Assume the size is valid and pre-adjust */
6530 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6531 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
6533 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6534 /* Write the address of the memory pointed to by temp_val into
6535 the memory pointed to by mem */
6536 emit_move_insn (mem
, XEXP (temp_val
, 0));
6537 emit_label (endlab
);
6544 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6545 For v9, function return values are subject to the same rules as arguments,
6546 except that up to 32 bytes may be returned in registers. */
6549 sparc_function_value_1 (const_tree type
, enum machine_mode mode
,
6552 /* Beware that the two values are swapped here wrt function_arg. */
6553 int regbase
= (outgoing
6554 ? SPARC_INCOMING_INT_ARG_FIRST
6555 : SPARC_OUTGOING_INT_ARG_FIRST
);
6556 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6559 /* Vector types deserve special treatment because they are polymorphic wrt
6560 their mode, depending upon whether VIS instructions are enabled. */
6561 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6563 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6564 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6565 || (TARGET_ARCH64
&& size
<= 32));
6567 if (mode
== BLKmode
)
6568 return function_arg_vector_value (size
,
6569 SPARC_FP_ARG_FIRST
);
6571 mclass
= MODE_FLOAT
;
6574 if (TARGET_ARCH64
&& type
)
6576 /* Structures up to 32 bytes in size are returned in registers. */
6577 if (TREE_CODE (type
) == RECORD_TYPE
)
6579 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6580 gcc_assert (size
<= 32);
6582 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
6585 /* Unions up to 32 bytes in size are returned in integer registers. */
6586 else if (TREE_CODE (type
) == UNION_TYPE
)
6588 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6589 gcc_assert (size
<= 32);
6591 return function_arg_union_value (size
, mode
, 0, regbase
);
6594 /* Objects that require it are returned in FP registers. */
6595 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6598 /* All other aggregate types are returned in an integer register in a
6599 mode corresponding to the size of the type. */
6600 else if (AGGREGATE_TYPE_P (type
))
6602 /* All other aggregate types are passed in an integer register
6603 in a mode corresponding to the size of the type. */
6604 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6605 gcc_assert (size
<= 32);
6607 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6609 /* ??? We probably should have made the same ABI change in
6610 3.4.0 as the one we made for unions. The latter was
6611 required by the SCD though, while the former is not
6612 specified, so we favored compatibility and efficiency.
6614 Now we're stuck for aggregates larger than 16 bytes,
6615 because OImode vanished in the meantime. Let's not
6616 try to be unduly clever, and simply follow the ABI
6617 for unions in that case. */
6618 if (mode
== BLKmode
)
6619 return function_arg_union_value (size
, mode
, 0, regbase
);
6624 /* We should only have pointer and integer types at this point. This
6625 must match sparc_promote_function_mode. */
6626 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6630 /* We should only have pointer and integer types at this point. This must
6631 match sparc_promote_function_mode. */
6632 else if (TARGET_ARCH32
6633 && mclass
== MODE_INT
6634 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6637 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
6638 regno
= SPARC_FP_ARG_FIRST
;
6642 return gen_rtx_REG (mode
, regno
);
6645 /* Handle TARGET_FUNCTION_VALUE.
6646 On the SPARC, the value is found in the first "output" register, but the
6647 called function leaves it in the first "input" register. */
6650 sparc_function_value (const_tree valtype
,
6651 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
6654 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
6657 /* Handle TARGET_LIBCALL_VALUE. */
6660 sparc_libcall_value (enum machine_mode mode
,
6661 const_rtx fun ATTRIBUTE_UNUSED
)
6663 return sparc_function_value_1 (NULL_TREE
, mode
, false);
6666 /* Handle FUNCTION_VALUE_REGNO_P.
6667 On the SPARC, the first "output" reg is used for integer values, and the
6668 first floating point register is used for floating point values. */
6671 sparc_function_value_regno_p (const unsigned int regno
)
6673 return (regno
== 8 || regno
== 32);
6676 /* Do what is necessary for `va_start'. We look at the current function
6677 to determine if stdarg or varargs is used and return the address of
6678 the first unnamed parameter. */
6681 sparc_builtin_saveregs (void)
6683 int first_reg
= crtl
->args
.info
.words
;
6687 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
6688 emit_move_insn (gen_rtx_MEM (word_mode
,
6689 gen_rtx_PLUS (Pmode
,
6691 GEN_INT (FIRST_PARM_OFFSET (0)
6694 gen_rtx_REG (word_mode
,
6695 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
6697 address
= gen_rtx_PLUS (Pmode
,
6699 GEN_INT (FIRST_PARM_OFFSET (0)
6700 + UNITS_PER_WORD
* first_reg
));
6705 /* Implement `va_start' for stdarg. */
6708 sparc_va_start (tree valist
, rtx nextarg
)
6710 nextarg
= expand_builtin_saveregs ();
6711 std_expand_builtin_va_start (valist
, nextarg
);
6714 /* Implement `va_arg' for stdarg. */
6717 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6720 HOST_WIDE_INT size
, rsize
, align
;
6723 tree ptrtype
= build_pointer_type (type
);
6725 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6728 size
= rsize
= UNITS_PER_WORD
;
6734 size
= int_size_in_bytes (type
);
6735 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6740 /* For SPARC64, objects requiring 16-byte alignment get it. */
6741 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
6742 align
= 2 * UNITS_PER_WORD
;
6744 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6745 are left-justified in their slots. */
6746 if (AGGREGATE_TYPE_P (type
))
6749 size
= rsize
= UNITS_PER_WORD
;
6759 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
6760 incr
= fold_convert (sizetype
, incr
);
6761 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
6763 incr
= fold_convert (ptr_type_node
, incr
);
6766 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6769 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
6770 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
6774 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
6775 addr
= build_va_arg_indirect_ref (addr
);
6778 /* If the address isn't aligned properly for the type, we need a temporary.
6779 FIXME: This is inefficient, usually we can do this in registers. */
6780 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
6782 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6783 tree dest_addr
= build_fold_addr_expr (tmp
);
6784 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
6785 3, dest_addr
, addr
, size_int (rsize
));
6786 TREE_ADDRESSABLE (tmp
) = 1;
6787 gimplify_and_add (copy
, pre_p
);
6792 addr
= fold_convert (ptrtype
, addr
);
6794 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
6795 gimplify_assign (valist
, incr
, post_p
);
6797 return build_va_arg_indirect_ref (addr
);
6800 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6801 Specify whether the vector mode is supported by the hardware. */
6804 sparc_vector_mode_supported_p (enum machine_mode mode
)
6806 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
6809 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6811 static enum machine_mode
6812 sparc_preferred_simd_mode (enum machine_mode mode
)
6830 /* Return the string to output an unconditional branch to LABEL, which is
6831 the operand number of the label.
6833 DEST is the destination insn (i.e. the label), INSN is the source. */
6836 output_ubranch (rtx dest
, int label
, rtx insn
)
6838 static char string
[64];
6839 bool v9_form
= false;
6842 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
6844 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6845 - INSN_ADDRESSES (INSN_UID (insn
)));
6846 /* Leave some instructions for "slop". */
6847 if (delta
>= -260000 && delta
< 260000)
6852 strcpy (string
, "ba%*,pt\t%%xcc, ");
6854 strcpy (string
, "b%*\t");
6856 p
= strchr (string
, '\0');
6867 /* Return the string to output a conditional branch to LABEL, which is
6868 the operand number of the label. OP is the conditional expression.
6869 XEXP (OP, 0) is assumed to be a condition code register (integer or
6870 floating point) and its mode specifies what kind of comparison we made.
6872 DEST is the destination insn (i.e. the label), INSN is the source.
6874 REVERSED is nonzero if we should reverse the sense of the comparison.
6876 ANNUL is nonzero if we should generate an annulling branch. */
6879 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
6882 static char string
[64];
6883 enum rtx_code code
= GET_CODE (op
);
6884 rtx cc_reg
= XEXP (op
, 0);
6885 enum machine_mode mode
= GET_MODE (cc_reg
);
6886 const char *labelno
, *branch
;
6887 int spaces
= 8, far
;
6890 /* v9 branches are limited to +-1MB. If it is too far away,
6903 fbne,a,pn %fcc2, .LC29
6911 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
6914 /* Reversal of FP compares takes care -- an ordered compare
6915 becomes an unordered compare and vice versa. */
6916 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6917 code
= reverse_condition_maybe_unordered (code
);
6919 code
= reverse_condition (code
);
6922 /* Start by writing the branch condition. */
6923 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6974 /* ??? !v9: FP branches cannot be preceded by another floating point
6975 insn. Because there is currently no concept of pre-delay slots,
6976 we can fix this only by always emitting a nop before a floating
6981 strcpy (string
, "nop\n\t");
6982 strcat (string
, branch
);
6995 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7007 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7028 strcpy (string
, branch
);
7030 spaces
-= strlen (branch
);
7031 p
= strchr (string
, '\0');
7033 /* Now add the annulling, the label, and a possible noop. */
7046 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7048 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7049 - INSN_ADDRESSES (INSN_UID (insn
)));
7050 /* Leave some instructions for "slop". */
7051 if (delta
< -260000 || delta
>= 260000)
7055 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7057 static char v9_fcc_labelno
[] = "%%fccX, ";
7058 /* Set the char indicating the number of the fcc reg to use. */
7059 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7060 labelno
= v9_fcc_labelno
;
7063 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7067 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7069 labelno
= "%%xcc, ";
7074 labelno
= "%%icc, ";
7079 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7082 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7095 strcpy (p
, labelno
);
7096 p
= strchr (p
, '\0');
7099 strcpy (p
, ".+12\n\t nop\n\tb\t");
7100 /* Skip the next insn if requested or
7101 if we know that it will be a nop. */
7102 if (annul
|| ! final_sequence
)
7116 /* Emit a library call comparison between floating point X and Y.
7117 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7118 Return the new operator to be used in the comparison sequence.
7120 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7121 values as arguments instead of the TFmode registers themselves,
7122 that's why we cannot call emit_float_lib_cmp. */
7125 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7128 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7129 enum machine_mode mode
;
7130 enum rtx_code new_comparison
;
7135 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7139 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7143 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7147 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7151 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7155 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7166 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7179 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7180 emit_move_insn (slot0
, x
);
7187 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7188 emit_move_insn (slot1
, y
);
7191 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7192 emit_library_call (libfunc
, LCT_NORMAL
,
7194 XEXP (slot0
, 0), Pmode
,
7195 XEXP (slot1
, 0), Pmode
);
7200 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7201 emit_library_call (libfunc
, LCT_NORMAL
,
7203 x
, TFmode
, y
, TFmode
);
7208 /* Immediately move the result of the libcall into a pseudo
7209 register so reload doesn't clobber the value if it needs
7210 the return register for a spill reg. */
7211 result
= gen_reg_rtx (mode
);
7212 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
7217 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
7220 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
7221 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
7224 new_comparison
= (comparison
== UNGT
? GT
: NE
);
7225 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
7227 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
7229 tem
= gen_reg_rtx (mode
);
7231 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
7233 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
7234 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
7237 tem
= gen_reg_rtx (mode
);
7239 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
7241 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
7242 tem2
= gen_reg_rtx (mode
);
7244 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
7246 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
7247 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
7248 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
7254 /* Generate an unsigned DImode to FP conversion. This is the same code
7255 optabs would emit if we didn't have TFmode patterns. */
7258 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
7260 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
7263 in
= force_reg (DImode
, operands
[1]);
7264 neglab
= gen_label_rtx ();
7265 donelab
= gen_label_rtx ();
7266 i0
= gen_reg_rtx (DImode
);
7267 i1
= gen_reg_rtx (DImode
);
7268 f0
= gen_reg_rtx (mode
);
7270 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
7272 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
7273 emit_jump_insn (gen_jump (donelab
));
7276 emit_label (neglab
);
7278 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
7279 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
7280 emit_insn (gen_iordi3 (i0
, i0
, i1
));
7281 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
7282 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
7284 emit_label (donelab
);
7287 /* Generate an FP to unsigned DImode conversion. This is the same code
7288 optabs would emit if we didn't have TFmode patterns. */
7291 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
7293 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
7296 in
= force_reg (mode
, operands
[1]);
7297 neglab
= gen_label_rtx ();
7298 donelab
= gen_label_rtx ();
7299 i0
= gen_reg_rtx (DImode
);
7300 i1
= gen_reg_rtx (DImode
);
7301 limit
= gen_reg_rtx (mode
);
7302 f0
= gen_reg_rtx (mode
);
7304 emit_move_insn (limit
,
7305 CONST_DOUBLE_FROM_REAL_VALUE (
7306 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
7307 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
7309 emit_insn (gen_rtx_SET (VOIDmode
,
7311 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
7312 emit_jump_insn (gen_jump (donelab
));
7315 emit_label (neglab
);
7317 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
7318 emit_insn (gen_rtx_SET (VOIDmode
,
7320 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
7321 emit_insn (gen_movdi (i1
, const1_rtx
));
7322 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
7323 emit_insn (gen_xordi3 (out
, i0
, i1
));
7325 emit_label (donelab
);
7328 /* Return the string to output a conditional branch to LABEL, testing
7329 register REG. LABEL is the operand number of the label; REG is the
7330 operand number of the reg. OP is the conditional expression. The mode
7331 of REG says what kind of comparison we made.
7333 DEST is the destination insn (i.e. the label), INSN is the source.
7335 REVERSED is nonzero if we should reverse the sense of the comparison.
7337 ANNUL is nonzero if we should generate an annulling branch. */
7340 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
7341 int annul
, rtx insn
)
7343 static char string
[64];
7344 enum rtx_code code
= GET_CODE (op
);
7345 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
7350 /* branch on register are limited to +-128KB. If it is too far away,
7363 brgez,a,pn %o1, .LC29
7369 ba,pt %xcc, .LC29 */
7371 far
= get_attr_length (insn
) >= 3;
7373 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7375 code
= reverse_condition (code
);
7377 /* Only 64 bit versions of these instructions exist. */
7378 gcc_assert (mode
== DImode
);
7380 /* Start by writing the branch condition. */
7385 strcpy (string
, "brnz");
7389 strcpy (string
, "brz");
7393 strcpy (string
, "brgez");
7397 strcpy (string
, "brlz");
7401 strcpy (string
, "brlez");
7405 strcpy (string
, "brgz");
7412 p
= strchr (string
, '\0');
7414 /* Now add the annulling, reg, label, and nop. */
7421 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7424 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7429 *p
= p
< string
+ 8 ? '\t' : ' ';
7437 int veryfar
= 1, delta
;
7439 if (INSN_ADDRESSES_SET_P ())
7441 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7442 - INSN_ADDRESSES (INSN_UID (insn
)));
7443 /* Leave some instructions for "slop". */
7444 if (delta
>= -260000 && delta
< 260000)
7448 strcpy (p
, ".+12\n\t nop\n\t");
7449 /* Skip the next insn if requested or
7450 if we know that it will be a nop. */
7451 if (annul
|| ! final_sequence
)
7461 strcpy (p
, "ba,pt\t%%xcc, ");
7475 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7476 Such instructions cannot be used in the delay slot of return insn on v9.
7477 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7481 epilogue_renumber (register rtx
*where
, int test
)
7483 register const char *fmt
;
7485 register enum rtx_code code
;
7490 code
= GET_CODE (*where
);
7495 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
7497 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
7498 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
7506 /* Do not replace the frame pointer with the stack pointer because
7507 it can cause the delayed instruction to load below the stack.
7508 This occurs when instructions like:
7510 (set (reg/i:SI 24 %i0)
7511 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7512 (const_int -20 [0xffffffec])) 0))
7514 are in the return delayed slot. */
7516 if (GET_CODE (XEXP (*where
, 0)) == REG
7517 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
7518 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
7519 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
7524 if (SPARC_STACK_BIAS
7525 && GET_CODE (XEXP (*where
, 0)) == REG
7526 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
7534 fmt
= GET_RTX_FORMAT (code
);
7536 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7541 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
7542 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
7545 else if (fmt
[i
] == 'e'
7546 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
7552 /* Leaf functions and non-leaf functions have different needs. */
7555 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
7558 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
7560 static const int *const reg_alloc_orders
[] = {
7561 reg_leaf_alloc_order
,
7562 reg_nonleaf_alloc_order
};
7565 order_regs_for_local_alloc (void)
7567 static int last_order_nonleaf
= 1;
7569 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
7571 last_order_nonleaf
= !last_order_nonleaf
;
7572 memcpy ((char *) reg_alloc_order
,
7573 (const char *) reg_alloc_orders
[last_order_nonleaf
],
7574 FIRST_PSEUDO_REGISTER
* sizeof (int));
7578 /* Return 1 if REG and MEM are legitimate enough to allow the various
7579 mem<-->reg splits to be run. */
7582 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
7584 /* Punt if we are here by mistake. */
7585 gcc_assert (reload_completed
);
7587 /* We must have an offsettable memory reference. */
7588 if (! offsettable_memref_p (mem
))
7591 /* If we have legitimate args for ldd/std, we do not want
7592 the split to happen. */
7593 if ((REGNO (reg
) % 2) == 0
7594 && mem_min_alignment (mem
, 8))
7601 /* Return 1 if x and y are some kind of REG and they refer to
7602 different hard registers. This test is guaranteed to be
7603 run after reload. */
7606 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
7608 if (GET_CODE (x
) != REG
)
7610 if (GET_CODE (y
) != REG
)
7612 if (REGNO (x
) == REGNO (y
))
7617 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7618 This makes them candidates for using ldd and std insns.
7620 Note reg1 and reg2 *must* be hard registers. */
7623 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
7625 /* We might have been passed a SUBREG. */
7626 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
7629 if (REGNO (reg1
) % 2 != 0)
7632 /* Integer ldd is deprecated in SPARC V9 */
7633 if (TARGET_V9
&& REGNO (reg1
) < 32)
7636 return (REGNO (reg1
) == REGNO (reg2
) - 1);
7639 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7642 This can only happen when addr1 and addr2, the addresses in mem1
7643 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7644 addr1 must also be aligned on a 64-bit boundary.
7646 Also iff dependent_reg_rtx is not null it should not be used to
7647 compute the address for mem1, i.e. we cannot optimize a sequence
7659 But, note that the transformation from:
7664 is perfectly fine. Thus, the peephole2 patterns always pass us
7665 the destination register of the first load, never the second one.
7667 For stores we don't have a similar problem, so dependent_reg_rtx is
7671 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
7675 HOST_WIDE_INT offset1
;
7677 /* The mems cannot be volatile. */
7678 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
7681 /* MEM1 should be aligned on a 64-bit boundary. */
7682 if (MEM_ALIGN (mem1
) < 64)
7685 addr1
= XEXP (mem1
, 0);
7686 addr2
= XEXP (mem2
, 0);
7688 /* Extract a register number and offset (if used) from the first addr. */
7689 if (GET_CODE (addr1
) == PLUS
)
7691 /* If not a REG, return zero. */
7692 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
7696 reg1
= REGNO (XEXP (addr1
, 0));
7697 /* The offset must be constant! */
7698 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
7700 offset1
= INTVAL (XEXP (addr1
, 1));
7703 else if (GET_CODE (addr1
) != REG
)
7707 reg1
= REGNO (addr1
);
7708 /* This was a simple (mem (reg)) expression. Offset is 0. */
7712 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7713 if (GET_CODE (addr2
) != PLUS
)
7716 if (GET_CODE (XEXP (addr2
, 0)) != REG
7717 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
7720 if (reg1
!= REGNO (XEXP (addr2
, 0)))
7723 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
7726 /* The first offset must be evenly divisible by 8 to ensure the
7727 address is 64 bit aligned. */
7728 if (offset1
% 8 != 0)
7731 /* The offset for the second addr must be 4 more than the first addr. */
7732 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
7735 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7740 /* Return 1 if reg is a pseudo, or is the first register in
7741 a hard register pair. This makes it suitable for use in
7742 ldd and std insns. */
7745 register_ok_for_ldd (rtx reg
)
7747 /* We might have been passed a SUBREG. */
7751 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
7752 return (REGNO (reg
) % 2 == 0);
7757 /* Return 1 if OP is a memory whose address is known to be
7758 aligned to 8-byte boundary, or a pseudo during reload.
7759 This makes it suitable for use in ldd and std insns. */
7762 memory_ok_for_ldd (rtx op
)
7766 /* In 64-bit mode, we assume that the address is word-aligned. */
7767 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
7770 if ((reload_in_progress
|| reload_completed
)
7771 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
7774 else if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
7776 if (!(reload_in_progress
&& reg_renumber
[REGNO (op
)] < 0))
7785 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7788 sparc_print_operand_punct_valid_p (unsigned char code
)
7801 /* Implement TARGET_PRINT_OPERAND.
7802 Print operand X (an rtx) in assembler syntax to file FILE.
7803 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7804 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7807 sparc_print_operand (FILE *file
, rtx x
, int code
)
7812 /* Output an insn in a delay slot. */
7814 sparc_indent_opcode
= 1;
7816 fputs ("\n\t nop", file
);
7819 /* Output an annul flag if there's nothing for the delay slot and we
7820 are optimizing. This is always used with '(' below.
7821 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7822 this is a dbx bug. So, we only do this when optimizing.
7823 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7824 Always emit a nop in case the next instruction is a branch. */
7825 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7829 /* Output a 'nop' if there's nothing for the delay slot and we are
7830 not optimizing. This is always used with '*' above. */
7831 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7832 fputs ("\n\t nop", file
);
7833 else if (final_sequence
)
7834 sparc_indent_opcode
= 1;
7837 /* Output the right displacement from the saved PC on function return.
7838 The caller may have placed an "unimp" insn immediately after the call
7839 so we have to account for it. This insn is used in the 32-bit ABI
7840 when calling a function that returns a non zero-sized structure. The
7841 64-bit ABI doesn't have it. Be careful to have this test be the same
7842 as that for the call. The exception is when sparc_std_struct_return
7843 is enabled, the psABI is followed exactly and the adjustment is made
7844 by the code in sparc_struct_value_rtx. The call emitted is the same
7845 when sparc_std_struct_return is enabled. */
7847 && cfun
->returns_struct
7848 && !sparc_std_struct_return
7849 && DECL_SIZE (DECL_RESULT (current_function_decl
))
7850 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
7852 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
7858 /* Output the Embedded Medium/Anywhere code model base register. */
7859 fputs (EMBMEDANY_BASE_REG
, file
);
7862 /* Print some local dynamic TLS name. */
7863 assemble_name (file
, get_some_local_dynamic_name ());
7867 /* Adjust the operand to take into account a RESTORE operation. */
7868 if (GET_CODE (x
) == CONST_INT
)
7870 else if (GET_CODE (x
) != REG
)
7871 output_operand_lossage ("invalid %%Y operand");
7872 else if (REGNO (x
) < 8)
7873 fputs (reg_names
[REGNO (x
)], file
);
7874 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
7875 fputs (reg_names
[REGNO (x
)-16], file
);
7877 output_operand_lossage ("invalid %%Y operand");
7880 /* Print out the low order register name of a register pair. */
7881 if (WORDS_BIG_ENDIAN
)
7882 fputs (reg_names
[REGNO (x
)+1], file
);
7884 fputs (reg_names
[REGNO (x
)], file
);
7887 /* Print out the high order register name of a register pair. */
7888 if (WORDS_BIG_ENDIAN
)
7889 fputs (reg_names
[REGNO (x
)], file
);
7891 fputs (reg_names
[REGNO (x
)+1], file
);
7894 /* Print out the second register name of a register pair or quad.
7895 I.e., R (%o0) => %o1. */
7896 fputs (reg_names
[REGNO (x
)+1], file
);
7899 /* Print out the third register name of a register quad.
7900 I.e., S (%o0) => %o2. */
7901 fputs (reg_names
[REGNO (x
)+2], file
);
7904 /* Print out the fourth register name of a register quad.
7905 I.e., T (%o0) => %o3. */
7906 fputs (reg_names
[REGNO (x
)+3], file
);
7909 /* Print a condition code register. */
7910 if (REGNO (x
) == SPARC_ICC_REG
)
7912 /* We don't handle CC[X]_NOOVmode because they're not supposed
7914 if (GET_MODE (x
) == CCmode
)
7915 fputs ("%icc", file
);
7916 else if (GET_MODE (x
) == CCXmode
)
7917 fputs ("%xcc", file
);
7922 /* %fccN register */
7923 fputs (reg_names
[REGNO (x
)], file
);
7926 /* Print the operand's address only. */
7927 output_address (XEXP (x
, 0));
7930 /* In this case we need a register. Use %g0 if the
7931 operand is const0_rtx. */
7933 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
7935 fputs ("%g0", file
);
7942 switch (GET_CODE (x
))
7944 case IOR
: fputs ("or", file
); break;
7945 case AND
: fputs ("and", file
); break;
7946 case XOR
: fputs ("xor", file
); break;
7947 default: output_operand_lossage ("invalid %%A operand");
7952 switch (GET_CODE (x
))
7954 case IOR
: fputs ("orn", file
); break;
7955 case AND
: fputs ("andn", file
); break;
7956 case XOR
: fputs ("xnor", file
); break;
7957 default: output_operand_lossage ("invalid %%B operand");
7961 /* These are used by the conditional move instructions. */
7965 enum rtx_code rc
= GET_CODE (x
);
7969 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
7970 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7971 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
7973 rc
= reverse_condition (GET_CODE (x
));
7977 case NE
: fputs ("ne", file
); break;
7978 case EQ
: fputs ("e", file
); break;
7979 case GE
: fputs ("ge", file
); break;
7980 case GT
: fputs ("g", file
); break;
7981 case LE
: fputs ("le", file
); break;
7982 case LT
: fputs ("l", file
); break;
7983 case GEU
: fputs ("geu", file
); break;
7984 case GTU
: fputs ("gu", file
); break;
7985 case LEU
: fputs ("leu", file
); break;
7986 case LTU
: fputs ("lu", file
); break;
7987 case LTGT
: fputs ("lg", file
); break;
7988 case UNORDERED
: fputs ("u", file
); break;
7989 case ORDERED
: fputs ("o", file
); break;
7990 case UNLT
: fputs ("ul", file
); break;
7991 case UNLE
: fputs ("ule", file
); break;
7992 case UNGT
: fputs ("ug", file
); break;
7993 case UNGE
: fputs ("uge", file
); break;
7994 case UNEQ
: fputs ("ue", file
); break;
7995 default: output_operand_lossage (code
== 'c'
7996 ? "invalid %%c operand"
7997 : "invalid %%C operand");
8002 /* These are used by the movr instruction pattern. */
8006 enum rtx_code rc
= (code
== 'd'
8007 ? reverse_condition (GET_CODE (x
))
8011 case NE
: fputs ("ne", file
); break;
8012 case EQ
: fputs ("e", file
); break;
8013 case GE
: fputs ("gez", file
); break;
8014 case LT
: fputs ("lz", file
); break;
8015 case LE
: fputs ("lez", file
); break;
8016 case GT
: fputs ("gz", file
); break;
8017 default: output_operand_lossage (code
== 'd'
8018 ? "invalid %%d operand"
8019 : "invalid %%D operand");
8026 /* Print a sign-extended character. */
8027 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
8028 fprintf (file
, "%d", i
);
8033 /* Operand must be a MEM; write its address. */
8034 if (GET_CODE (x
) != MEM
)
8035 output_operand_lossage ("invalid %%f operand");
8036 output_address (XEXP (x
, 0));
8041 /* Print a sign-extended 32-bit value. */
8043 if (GET_CODE(x
) == CONST_INT
)
8045 else if (GET_CODE(x
) == CONST_DOUBLE
)
8046 i
= CONST_DOUBLE_LOW (x
);
8049 output_operand_lossage ("invalid %%s operand");
8052 i
= trunc_int_for_mode (i
, SImode
);
8053 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8058 /* Do nothing special. */
8062 /* Undocumented flag. */
8063 output_operand_lossage ("invalid operand output code");
8066 if (GET_CODE (x
) == REG
)
8067 fputs (reg_names
[REGNO (x
)], file
);
8068 else if (GET_CODE (x
) == MEM
)
8071 /* Poor Sun assembler doesn't understand absolute addressing. */
8072 if (CONSTANT_P (XEXP (x
, 0)))
8073 fputs ("%g0+", file
);
8074 output_address (XEXP (x
, 0));
8077 else if (GET_CODE (x
) == HIGH
)
8079 fputs ("%hi(", file
);
8080 output_addr_const (file
, XEXP (x
, 0));
8083 else if (GET_CODE (x
) == LO_SUM
)
8085 sparc_print_operand (file
, XEXP (x
, 0), 0);
8086 if (TARGET_CM_MEDMID
)
8087 fputs ("+%l44(", file
);
8089 fputs ("+%lo(", file
);
8090 output_addr_const (file
, XEXP (x
, 1));
8093 else if (GET_CODE (x
) == CONST_DOUBLE
8094 && (GET_MODE (x
) == VOIDmode
8095 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
8097 if (CONST_DOUBLE_HIGH (x
) == 0)
8098 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
8099 else if (CONST_DOUBLE_HIGH (x
) == -1
8100 && CONST_DOUBLE_LOW (x
) < 0)
8101 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
8103 output_operand_lossage ("long long constant not a valid immediate operand");
8105 else if (GET_CODE (x
) == CONST_DOUBLE
)
8106 output_operand_lossage ("floating point constant not a valid immediate operand");
8107 else { output_addr_const (file
, x
); }
8110 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8113 sparc_print_operand_address (FILE *file
, rtx x
)
8115 register rtx base
, index
= 0;
8117 register rtx addr
= x
;
8120 fputs (reg_names
[REGNO (addr
)], file
);
8121 else if (GET_CODE (addr
) == PLUS
)
8123 if (CONST_INT_P (XEXP (addr
, 0)))
8124 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
8125 else if (CONST_INT_P (XEXP (addr
, 1)))
8126 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
8128 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
8129 if (GET_CODE (base
) == LO_SUM
)
8131 gcc_assert (USE_AS_OFFSETABLE_LO10
8133 && ! TARGET_CM_MEDMID
);
8134 output_operand (XEXP (base
, 0), 0);
8135 fputs ("+%lo(", file
);
8136 output_address (XEXP (base
, 1));
8137 fprintf (file
, ")+%d", offset
);
8141 fputs (reg_names
[REGNO (base
)], file
);
8143 fprintf (file
, "%+d", offset
);
8144 else if (REG_P (index
))
8145 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
8146 else if (GET_CODE (index
) == SYMBOL_REF
8147 || GET_CODE (index
) == LABEL_REF
8148 || GET_CODE (index
) == CONST
)
8149 fputc ('+', file
), output_addr_const (file
, index
);
8150 else gcc_unreachable ();
8153 else if (GET_CODE (addr
) == MINUS
8154 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
8156 output_addr_const (file
, XEXP (addr
, 0));
8158 output_addr_const (file
, XEXP (addr
, 1));
8159 fputs ("-.)", file
);
8161 else if (GET_CODE (addr
) == LO_SUM
)
8163 output_operand (XEXP (addr
, 0), 0);
8164 if (TARGET_CM_MEDMID
)
8165 fputs ("+%l44(", file
);
8167 fputs ("+%lo(", file
);
8168 output_address (XEXP (addr
, 1));
8172 && GET_CODE (addr
) == CONST
8173 && GET_CODE (XEXP (addr
, 0)) == MINUS
8174 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
8175 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
8176 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
8178 addr
= XEXP (addr
, 0);
8179 output_addr_const (file
, XEXP (addr
, 0));
8180 /* Group the args of the second CONST in parenthesis. */
8182 /* Skip past the second CONST--it does nothing for us. */
8183 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
8184 /* Close the parenthesis. */
8189 output_addr_const (file
, addr
);
8193 /* Target hook for assembling integer objects. The sparc version has
8194 special handling for aligned DI-mode objects. */
8197 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
8199 /* ??? We only output .xword's for symbols and only then in environments
8200 where the assembler can handle them. */
8201 if (aligned_p
&& size
== 8
8202 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
8206 assemble_integer_with_op ("\t.xword\t", x
);
8211 assemble_aligned_integer (4, const0_rtx
);
8212 assemble_aligned_integer (4, x
);
8216 return default_assemble_integer (x
, size
, aligned_p
);
8219 /* Return the value of a code used in the .proc pseudo-op that says
8220 what kind of result this function returns. For non-C types, we pick
8221 the closest C type. */
8223 #ifndef SHORT_TYPE_SIZE
8224 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8227 #ifndef INT_TYPE_SIZE
8228 #define INT_TYPE_SIZE BITS_PER_WORD
8231 #ifndef LONG_TYPE_SIZE
8232 #define LONG_TYPE_SIZE BITS_PER_WORD
8235 #ifndef LONG_LONG_TYPE_SIZE
8236 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8239 #ifndef FLOAT_TYPE_SIZE
8240 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8243 #ifndef DOUBLE_TYPE_SIZE
8244 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8247 #ifndef LONG_DOUBLE_TYPE_SIZE
8248 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8252 sparc_type_code (register tree type
)
8254 register unsigned long qualifiers
= 0;
8255 register unsigned shift
;
8257 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8258 setting more, since some assemblers will give an error for this. Also,
8259 we must be careful to avoid shifts of 32 bits or more to avoid getting
8260 unpredictable results. */
8262 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
8264 switch (TREE_CODE (type
))
8270 qualifiers
|= (3 << shift
);
8275 qualifiers
|= (2 << shift
);
8279 case REFERENCE_TYPE
:
8281 qualifiers
|= (1 << shift
);
8285 return (qualifiers
| 8);
8288 case QUAL_UNION_TYPE
:
8289 return (qualifiers
| 9);
8292 return (qualifiers
| 10);
8295 return (qualifiers
| 16);
8298 /* If this is a range type, consider it to be the underlying
8300 if (TREE_TYPE (type
) != 0)
8303 /* Carefully distinguish all the standard types of C,
8304 without messing up if the language is not C. We do this by
8305 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8306 look at both the names and the above fields, but that's redundant.
8307 Any type whose size is between two C types will be considered
8308 to be the wider of the two types. Also, we do not have a
8309 special code to use for "long long", so anything wider than
8310 long is treated the same. Note that we can't distinguish
8311 between "int" and "long" in this code if they are the same
8312 size, but that's fine, since neither can the assembler. */
8314 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
8315 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
8317 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
8318 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
8320 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
8321 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
8324 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
8327 /* If this is a range type, consider it to be the underlying
8329 if (TREE_TYPE (type
) != 0)
8332 /* Carefully distinguish all the standard types of C,
8333 without messing up if the language is not C. */
8335 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
8336 return (qualifiers
| 6);
8339 return (qualifiers
| 7);
8341 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
8342 /* ??? We need to distinguish between double and float complex types,
8343 but I don't know how yet because I can't reach this code from
8344 existing front-ends. */
8345 return (qualifiers
| 7); /* Who knows? */
8348 case BOOLEAN_TYPE
: /* Boolean truth value type. */
8354 gcc_unreachable (); /* Not a type! */
8361 /* Nested function support. */
8363 /* Emit RTL insns to initialize the variable parts of a trampoline.
8364 FNADDR is an RTX for the address of the function's pure code.
8365 CXT is an RTX for the static chain value for the function.
8367 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8368 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8369 (to store insns). This is a bit excessive. Perhaps a different
8370 mechanism would be better here.
8372 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8375 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8377 /* SPARC 32-bit trampoline:
8380 sethi %hi(static), %g2
8382 or %g2, %lo(static), %g2
8384 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8385 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8389 (adjust_address (m_tramp
, SImode
, 0),
8390 expand_binop (SImode
, ior_optab
,
8391 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
8392 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
8393 NULL_RTX
, 1, OPTAB_DIRECT
));
8396 (adjust_address (m_tramp
, SImode
, 4),
8397 expand_binop (SImode
, ior_optab
,
8398 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
8399 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
8400 NULL_RTX
, 1, OPTAB_DIRECT
));
8403 (adjust_address (m_tramp
, SImode
, 8),
8404 expand_binop (SImode
, ior_optab
,
8405 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
8406 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
8407 NULL_RTX
, 1, OPTAB_DIRECT
));
8410 (adjust_address (m_tramp
, SImode
, 12),
8411 expand_binop (SImode
, ior_optab
,
8412 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
8413 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
8414 NULL_RTX
, 1, OPTAB_DIRECT
));
8416 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8417 aligned on a 16 byte boundary so one flush clears it all. */
8418 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
8419 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8420 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8421 && sparc_cpu
!= PROCESSOR_NIAGARA
8422 && sparc_cpu
!= PROCESSOR_NIAGARA2
8423 && sparc_cpu
!= PROCESSOR_NIAGARA3
8424 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8425 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
8427 /* Call __enable_execute_stack after writing onto the stack to make sure
8428 the stack address is accessible. */
8429 #ifdef HAVE_ENABLE_EXECUTE_STACK
8430 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8431 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8436 /* The 64-bit version is simpler because it makes more sense to load the
8437 values as "immediate" data out of the trampoline. It's also easier since
8438 we can read the PC without clobbering a register. */
8441 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8443 /* SPARC 64-bit trampoline:
8452 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
8453 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
8454 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
8455 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
8456 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
8457 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
8458 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
8459 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
8460 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
8461 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
8462 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
8464 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8465 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8466 && sparc_cpu
!= PROCESSOR_NIAGARA
8467 && sparc_cpu
!= PROCESSOR_NIAGARA2
8468 && sparc_cpu
!= PROCESSOR_NIAGARA3
8469 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8470 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
8472 /* Call __enable_execute_stack after writing onto the stack to make sure
8473 the stack address is accessible. */
8474 #ifdef HAVE_ENABLE_EXECUTE_STACK
8475 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8476 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8480 /* Worker for TARGET_TRAMPOLINE_INIT. */
8483 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
8485 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
8486 cxt
= force_reg (Pmode
, cxt
);
8488 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8490 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8493 /* Adjust the cost of a scheduling dependency. Return the new cost of
8494 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8497 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8499 enum attr_type insn_type
;
8501 if (! recog_memoized (insn
))
8504 insn_type
= get_attr_type (insn
);
8506 if (REG_NOTE_KIND (link
) == 0)
8508 /* Data dependency; DEP_INSN writes a register that INSN reads some
8511 /* if a load, then the dependence must be on the memory address;
8512 add an extra "cycle". Note that the cost could be two cycles
8513 if the reg was written late in an instruction group; we ca not tell
8515 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
8518 /* Get the delay only if the address of the store is the dependence. */
8519 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
8521 rtx pat
= PATTERN(insn
);
8522 rtx dep_pat
= PATTERN (dep_insn
);
8524 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8525 return cost
; /* This should not happen! */
8527 /* The dependency between the two instructions was on the data that
8528 is being stored. Assume that this implies that the address of the
8529 store is not dependent. */
8530 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8533 return cost
+ 3; /* An approximation. */
8536 /* A shift instruction cannot receive its data from an instruction
8537 in the same cycle; add a one cycle penalty. */
8538 if (insn_type
== TYPE_SHIFT
)
8539 return cost
+ 3; /* Split before cascade into shift. */
8543 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8544 INSN writes some cycles later. */
8546 /* These are only significant for the fpu unit; writing a fp reg before
8547 the fpu has finished with it stalls the processor. */
8549 /* Reusing an integer register causes no problems. */
8550 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8558 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8560 enum attr_type insn_type
, dep_type
;
8561 rtx pat
= PATTERN(insn
);
8562 rtx dep_pat
= PATTERN (dep_insn
);
8564 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
8567 insn_type
= get_attr_type (insn
);
8568 dep_type
= get_attr_type (dep_insn
);
8570 switch (REG_NOTE_KIND (link
))
8573 /* Data dependency; DEP_INSN writes a register that INSN reads some
8580 /* Get the delay iff the address of the store is the dependence. */
8581 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8584 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8591 /* If a load, then the dependence must be on the memory address. If
8592 the addresses aren't equal, then it might be a false dependency */
8593 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
8595 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
8596 || GET_CODE (SET_DEST (dep_pat
)) != MEM
8597 || GET_CODE (SET_SRC (pat
)) != MEM
8598 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
8599 XEXP (SET_SRC (pat
), 0)))
8607 /* Compare to branch latency is 0. There is no benefit from
8608 separating compare and branch. */
8609 if (dep_type
== TYPE_COMPARE
)
8611 /* Floating point compare to branch latency is less than
8612 compare to conditional move. */
8613 if (dep_type
== TYPE_FPCMP
)
8622 /* Anti-dependencies only penalize the fpu unit. */
8623 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8635 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
8639 case PROCESSOR_SUPERSPARC
:
8640 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
8642 case PROCESSOR_HYPERSPARC
:
8643 case PROCESSOR_SPARCLITE86X
:
8644 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
8653 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
8654 int sched_verbose ATTRIBUTE_UNUSED
,
8655 int max_ready ATTRIBUTE_UNUSED
)
8659 sparc_use_sched_lookahead (void)
8661 if (sparc_cpu
== PROCESSOR_NIAGARA
8662 || sparc_cpu
== PROCESSOR_NIAGARA2
8663 || sparc_cpu
== PROCESSOR_NIAGARA3
8664 || sparc_cpu
== PROCESSOR_NIAGARA4
)
8666 if (sparc_cpu
== PROCESSOR_ULTRASPARC
8667 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8669 if ((1 << sparc_cpu
) &
8670 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
8671 (1 << PROCESSOR_SPARCLITE86X
)))
8677 sparc_issue_rate (void)
8681 case PROCESSOR_NIAGARA
:
8682 case PROCESSOR_NIAGARA2
:
8683 case PROCESSOR_NIAGARA3
:
8684 case PROCESSOR_NIAGARA4
:
8688 /* Assume V9 processors are capable of at least dual-issue. */
8690 case PROCESSOR_SUPERSPARC
:
8692 case PROCESSOR_HYPERSPARC
:
8693 case PROCESSOR_SPARCLITE86X
:
8695 case PROCESSOR_ULTRASPARC
:
8696 case PROCESSOR_ULTRASPARC3
:
8702 set_extends (rtx insn
)
8704 register rtx pat
= PATTERN (insn
);
8706 switch (GET_CODE (SET_SRC (pat
)))
8708 /* Load and some shift instructions zero extend. */
8711 /* sethi clears the high bits */
8713 /* LO_SUM is used with sethi. sethi cleared the high
8714 bits and the values used with lo_sum are positive */
8716 /* Store flag stores 0 or 1 */
8726 rtx op0
= XEXP (SET_SRC (pat
), 0);
8727 rtx op1
= XEXP (SET_SRC (pat
), 1);
8728 if (GET_CODE (op1
) == CONST_INT
)
8729 return INTVAL (op1
) >= 0;
8730 if (GET_CODE (op0
) != REG
)
8732 if (sparc_check_64 (op0
, insn
) == 1)
8734 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8739 rtx op0
= XEXP (SET_SRC (pat
), 0);
8740 rtx op1
= XEXP (SET_SRC (pat
), 1);
8741 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
8743 if (GET_CODE (op1
) == CONST_INT
)
8744 return INTVAL (op1
) >= 0;
8745 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8748 return GET_MODE (SET_SRC (pat
)) == SImode
;
8749 /* Positive integers leave the high bits zero. */
8751 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
8753 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
8756 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
8758 return sparc_check_64 (SET_SRC (pat
), insn
);
8764 /* We _ought_ to have only one kind per function, but... */
8765 static GTY(()) rtx sparc_addr_diff_list
;
8766 static GTY(()) rtx sparc_addr_list
;
8769 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
8771 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8773 sparc_addr_diff_list
8774 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
8776 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
8780 sparc_output_addr_vec (rtx vec
)
8782 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8783 int idx
, vlen
= XVECLEN (body
, 0);
8785 #ifdef ASM_OUTPUT_ADDR_VEC_START
8786 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8789 #ifdef ASM_OUTPUT_CASE_LABEL
8790 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8793 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8796 for (idx
= 0; idx
< vlen
; idx
++)
8798 ASM_OUTPUT_ADDR_VEC_ELT
8799 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8802 #ifdef ASM_OUTPUT_ADDR_VEC_END
8803 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8808 sparc_output_addr_diff_vec (rtx vec
)
8810 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8811 rtx base
= XEXP (XEXP (body
, 0), 0);
8812 int idx
, vlen
= XVECLEN (body
, 1);
8814 #ifdef ASM_OUTPUT_ADDR_VEC_START
8815 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8818 #ifdef ASM_OUTPUT_CASE_LABEL
8819 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8822 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8825 for (idx
= 0; idx
< vlen
; idx
++)
8827 ASM_OUTPUT_ADDR_DIFF_ELT
8830 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
8831 CODE_LABEL_NUMBER (base
));
8834 #ifdef ASM_OUTPUT_ADDR_VEC_END
8835 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8840 sparc_output_deferred_case_vectors (void)
8845 if (sparc_addr_list
== NULL_RTX
8846 && sparc_addr_diff_list
== NULL_RTX
)
8849 /* Align to cache line in the function's code section. */
8850 switch_to_section (current_function_section ());
8852 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8854 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
8856 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
8857 sparc_output_addr_vec (XEXP (t
, 0));
8858 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
8859 sparc_output_addr_diff_vec (XEXP (t
, 0));
8861 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
8864 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8865 unknown. Return 1 if the high bits are zero, -1 if the register is
8868 sparc_check_64 (rtx x
, rtx insn
)
8870 /* If a register is set only once it is safe to ignore insns this
8871 code does not know how to handle. The loop will either recognize
8872 the single set and return the correct value or fail to recognize
8877 gcc_assert (GET_CODE (x
) == REG
);
8879 if (GET_MODE (x
) == DImode
)
8880 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
8882 if (flag_expensive_optimizations
8883 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
8889 insn
= get_last_insn_anywhere ();
8894 while ((insn
= PREV_INSN (insn
)))
8896 switch (GET_CODE (insn
))
8909 rtx pat
= PATTERN (insn
);
8910 if (GET_CODE (pat
) != SET
)
8912 if (rtx_equal_p (x
, SET_DEST (pat
)))
8913 return set_extends (insn
);
8914 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
8915 return set_extends (insn
);
8916 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
8924 /* Returns assembly code to perform a DImode shift using
8925 a 64-bit global or out register on SPARC-V8+. */
8927 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
8929 static char asm_code
[60];
8931 /* The scratch register is only required when the destination
8932 register is not a 64-bit global or out register. */
8933 if (which_alternative
!= 2)
8934 operands
[3] = operands
[0];
8936 /* We can only shift by constants <= 63. */
8937 if (GET_CODE (operands
[2]) == CONST_INT
)
8938 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
8940 if (GET_CODE (operands
[1]) == CONST_INT
)
8942 output_asm_insn ("mov\t%1, %3", operands
);
8946 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
8947 if (sparc_check_64 (operands
[1], insn
) <= 0)
8948 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
8949 output_asm_insn ("or\t%L1, %3, %3", operands
);
8952 strcpy(asm_code
, opcode
);
8954 if (which_alternative
!= 2)
8955 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8957 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8960 /* Output rtl to increment the profiler label LABELNO
8961 for profiling a function entry. */
8964 sparc_profile_hook (int labelno
)
8969 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
8970 if (NO_PROFILE_COUNTERS
)
8972 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
8976 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8977 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
8978 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
8982 #ifdef TARGET_SOLARIS
8983 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
8986 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
8987 tree decl ATTRIBUTE_UNUSED
)
8989 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
8991 solaris_elf_asm_comdat_section (name
, flags
, decl
);
8995 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
8997 if (!(flags
& SECTION_DEBUG
))
8998 fputs (",#alloc", asm_out_file
);
8999 if (flags
& SECTION_WRITE
)
9000 fputs (",#write", asm_out_file
);
9001 if (flags
& SECTION_TLS
)
9002 fputs (",#tls", asm_out_file
);
9003 if (flags
& SECTION_CODE
)
9004 fputs (",#execinstr", asm_out_file
);
9006 /* ??? Handle SECTION_BSS. */
9008 fputc ('\n', asm_out_file
);
9010 #endif /* TARGET_SOLARIS */
9012 /* We do not allow indirect calls to be optimized into sibling calls.
9014 We cannot use sibling calls when delayed branches are disabled
9015 because they will likely require the call delay slot to be filled.
9017 Also, on SPARC 32-bit we cannot emit a sibling call when the
9018 current function returns a structure. This is because the "unimp
9019 after call" convention would cause the callee to return to the
9020 wrong place. The generic code already disallows cases where the
9021 function being called returns a structure.
9023 It may seem strange how this last case could occur. Usually there
9024 is code after the call which jumps to epilogue code which dumps the
9025 return value into the struct return area. That ought to invalidate
9026 the sibling call right? Well, in the C++ case we can end up passing
9027 the pointer to the struct return area to a constructor (which returns
9028 void) and then nothing else happens. Such a sibling call would look
9029 valid without the added check here.
9031 VxWorks PIC PLT entries require the global pointer to be initialized
9032 on entry. We therefore can't emit sibling calls to them. */
9034 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9037 && flag_delayed_branch
9038 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9039 && !(TARGET_VXWORKS_RTP
9041 && !targetm
.binds_local_p (decl
)));
9044 /* libfunc renaming. */
9047 sparc_init_libfuncs (void)
9051 /* Use the subroutines that Sun's library provides for integer
9052 multiply and divide. The `*' prevents an underscore from
9053 being prepended by the compiler. .umul is a little faster
9055 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9056 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9057 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9058 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9059 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9061 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9062 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9063 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9064 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9065 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9066 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9068 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9069 is because with soft-float, the SFmode and DFmode sqrt
9070 instructions will be absent, and the compiler will notice and
9071 try to use the TFmode sqrt instruction for calls to the
9072 builtin function sqrt, but this fails. */
9074 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9076 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
9077 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
9078 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
9079 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
9080 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
9081 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
9083 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
9084 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
9085 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
9086 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
9088 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
9089 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
9090 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
9091 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
9093 if (DITF_CONVERSION_LIBFUNCS
)
9095 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
9096 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
9097 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
9098 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
9101 if (SUN_CONVERSION_LIBFUNCS
)
9103 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9104 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9105 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9106 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9111 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9112 do not exist in the library. Make sure the compiler does not
9113 emit calls to them by accident. (It should always use the
9114 hardware instructions.) */
9115 set_optab_libfunc (smul_optab
, SImode
, 0);
9116 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9117 set_optab_libfunc (udiv_optab
, SImode
, 0);
9118 set_optab_libfunc (smod_optab
, SImode
, 0);
9119 set_optab_libfunc (umod_optab
, SImode
, 0);
9121 if (SUN_INTEGER_MULTIPLY_64
)
9123 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
9124 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
9125 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
9126 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
9127 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
9130 if (SUN_CONVERSION_LIBFUNCS
)
9132 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
9133 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
9134 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
9135 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
9140 static tree
def_builtin(const char *name
, int code
, tree type
)
9142 return add_builtin_function(name
, type
, code
, BUILT_IN_MD
, NULL
,
9146 static tree
def_builtin_const(const char *name
, int code
, tree type
)
9148 tree t
= def_builtin(name
, code
, type
);
9151 TREE_READONLY (t
) = 1;
9156 /* Implement the TARGET_INIT_BUILTINS target hook.
9157 Create builtin functions for special SPARC instructions. */
9160 sparc_init_builtins (void)
9163 sparc_vis_init_builtins ();
9166 /* Create builtin functions for VIS 1.0 instructions. */
9169 sparc_vis_init_builtins (void)
9171 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
9172 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
9173 tree v4hi
= build_vector_type (intHI_type_node
, 4);
9174 tree v2hi
= build_vector_type (intHI_type_node
, 2);
9175 tree v2si
= build_vector_type (intSI_type_node
, 2);
9177 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
9178 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
9179 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
9180 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
9181 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
9182 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
9183 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
9184 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
9185 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
9186 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
9187 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
9188 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
9189 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
9191 intDI_type_node
, 0);
9192 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
9194 intDI_type_node
, 0);
9195 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
9197 intSI_type_node
, 0);
9198 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
9200 intDI_type_node
, 0);
9201 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
9204 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
9207 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
9209 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
9211 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
9213 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
9215 tree void_ftype_di
= build_function_type_list (void_type_node
,
9216 intDI_type_node
, 0);
9217 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
9220 /* Packing and expanding vectors. */
9221 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
9223 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
9224 v8qi_ftype_v2si_v8qi
);
9225 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
9227 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
9229 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
9230 v8qi_ftype_v4qi_v4qi
);
9232 /* Multiplications. */
9233 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
9234 v4hi_ftype_v4qi_v4hi
);
9235 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
9236 v4hi_ftype_v4qi_v2hi
);
9237 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
9238 v4hi_ftype_v4qi_v2hi
);
9239 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
9240 v4hi_ftype_v8qi_v4hi
);
9241 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
9242 v4hi_ftype_v8qi_v4hi
);
9243 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
9244 v2si_ftype_v4qi_v2hi
);
9245 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
9246 v2si_ftype_v4qi_v2hi
);
9248 /* Data aligning. */
9249 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
9250 v4hi_ftype_v4hi_v4hi
);
9251 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
9252 v8qi_ftype_v8qi_v8qi
);
9253 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
9254 v2si_ftype_v2si_v2si
);
9255 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis
,
9258 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
9260 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
9265 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
9267 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
9272 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
9274 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
9278 /* Pixel distance. */
9279 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
9280 di_ftype_v8qi_v8qi_di
);
9282 /* Edge handling. */
9285 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
9287 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
9289 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
9291 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
9293 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
9295 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
9300 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
9302 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
9304 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
9306 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
9308 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
9310 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
9314 /* Pixel compare. */
9317 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
9318 di_ftype_v4hi_v4hi
);
9319 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
9320 di_ftype_v2si_v2si
);
9321 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
9322 di_ftype_v4hi_v4hi
);
9323 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
9324 di_ftype_v2si_v2si
);
9325 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
9326 di_ftype_v4hi_v4hi
);
9327 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
9328 di_ftype_v2si_v2si
);
9329 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
9330 di_ftype_v4hi_v4hi
);
9331 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
9332 di_ftype_v2si_v2si
);
9336 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
9337 si_ftype_v4hi_v4hi
);
9338 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
9339 si_ftype_v2si_v2si
);
9340 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
9341 si_ftype_v4hi_v4hi
);
9342 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
9343 si_ftype_v2si_v2si
);
9344 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
9345 si_ftype_v4hi_v4hi
);
9346 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
9347 si_ftype_v2si_v2si
);
9348 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
9349 si_ftype_v4hi_v4hi
);
9350 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
9351 si_ftype_v2si_v2si
);
9355 /* Handle TARGET_EXPAND_BUILTIN target hook.
9356 Expand builtin functions for sparc intrinsics. */
9359 sparc_expand_builtin (tree exp
, rtx target
,
9360 rtx subtarget ATTRIBUTE_UNUSED
,
9361 enum machine_mode tmode ATTRIBUTE_UNUSED
,
9362 int ignore ATTRIBUTE_UNUSED
)
9365 call_expr_arg_iterator iter
;
9366 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9367 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
9372 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9376 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9378 || GET_MODE (target
) != tmode
9379 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9380 op
[0] = gen_reg_rtx (tmode
);
9384 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9386 const struct insn_operand_data
*insn_op
;
9388 if (arg
== error_mark_node
)
9392 insn_op
= &insn_data
[icode
].operand
[arg_count
- !nonvoid
];
9393 op
[arg_count
] = expand_normal (arg
);
9395 if (! (*insn_data
[icode
].operand
[arg_count
].predicate
) (op
[arg_count
],
9397 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
9403 pat
= GEN_FCN (icode
) (op
[0]);
9407 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
9409 pat
= GEN_FCN (icode
) (op
[1]);
9412 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
9415 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
9433 sparc_vis_mul8x16 (int e8
, int e16
)
9435 return (e8
* e16
+ 128) / 256;
9438 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9439 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9440 constants. A tree list with the results of the multiplications is returned,
9441 and each element in the list is of INNER_TYPE. */
9444 sparc_handle_vis_mul8x16 (int fncode
, tree inner_type
, tree elts0
, tree elts1
)
9446 tree n_elts
= NULL_TREE
;
9451 case CODE_FOR_fmul8x16_vis
:
9452 for (; elts0
&& elts1
;
9453 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9456 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9457 TREE_INT_CST_LOW (TREE_VALUE (elts1
)));
9458 n_elts
= tree_cons (NULL_TREE
,
9459 build_int_cst (inner_type
, val
),
9464 case CODE_FOR_fmul8x16au_vis
:
9465 scale
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9467 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9470 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9472 n_elts
= tree_cons (NULL_TREE
,
9473 build_int_cst (inner_type
, val
),
9478 case CODE_FOR_fmul8x16al_vis
:
9479 scale
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1
)));
9481 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9484 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9486 n_elts
= tree_cons (NULL_TREE
,
9487 build_int_cst (inner_type
, val
),
9496 return nreverse (n_elts
);
9499 /* Handle TARGET_FOLD_BUILTIN target hook.
9500 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9501 result of the function call is ignored. NULL_TREE is returned if the
9502 function could not be folded. */
9505 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
9506 tree
*args
, bool ignore
)
9508 tree arg0
, arg1
, arg2
;
9509 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
9510 enum insn_code icode
= (enum insn_code
) DECL_FUNCTION_CODE (fndecl
);
9513 && icode
!= CODE_FOR_alignaddrsi_vis
9514 && icode
!= CODE_FOR_alignaddrdi_vis
9515 && icode
!= CODE_FOR_wrgsr_vis
)
9516 return build_zero_cst (rtype
);
9520 case CODE_FOR_fexpand_vis
:
9524 if (TREE_CODE (arg0
) == VECTOR_CST
)
9526 tree inner_type
= TREE_TYPE (rtype
);
9527 tree elts
= TREE_VECTOR_CST_ELTS (arg0
);
9528 tree n_elts
= NULL_TREE
;
9530 for (; elts
; elts
= TREE_CHAIN (elts
))
9532 unsigned int val
= TREE_INT_CST_LOW (TREE_VALUE (elts
)) << 4;
9533 n_elts
= tree_cons (NULL_TREE
,
9534 build_int_cst (inner_type
, val
),
9537 return build_vector (rtype
, nreverse (n_elts
));
9541 case CODE_FOR_fmul8x16_vis
:
9542 case CODE_FOR_fmul8x16au_vis
:
9543 case CODE_FOR_fmul8x16al_vis
:
9549 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9551 tree inner_type
= TREE_TYPE (rtype
);
9552 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9553 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9554 tree n_elts
= sparc_handle_vis_mul8x16 (icode
, inner_type
, elts0
,
9557 return build_vector (rtype
, n_elts
);
9561 case CODE_FOR_fpmerge_vis
:
9567 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9569 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9570 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9571 tree n_elts
= NULL_TREE
;
9573 for (; elts0
&& elts1
;
9574 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9576 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts0
), n_elts
);
9577 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts1
), n_elts
);
9580 return build_vector (rtype
, nreverse (n_elts
));
9584 case CODE_FOR_pdist_vis
:
9592 if (TREE_CODE (arg0
) == VECTOR_CST
9593 && TREE_CODE (arg1
) == VECTOR_CST
9594 && TREE_CODE (arg2
) == INTEGER_CST
)
9597 unsigned HOST_WIDE_INT low
= TREE_INT_CST_LOW (arg2
);
9598 HOST_WIDE_INT high
= TREE_INT_CST_HIGH (arg2
);
9599 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9600 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9602 for (; elts0
&& elts1
;
9603 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9605 unsigned HOST_WIDE_INT
9606 low0
= TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9607 low1
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9608 HOST_WIDE_INT high0
= TREE_INT_CST_HIGH (TREE_VALUE (elts0
));
9609 HOST_WIDE_INT high1
= TREE_INT_CST_HIGH (TREE_VALUE (elts1
));
9611 unsigned HOST_WIDE_INT l
;
9614 overflow
|= neg_double (low1
, high1
, &l
, &h
);
9615 overflow
|= add_double (low0
, high0
, l
, h
, &l
, &h
);
9617 overflow
|= neg_double (l
, h
, &l
, &h
);
9619 overflow
|= add_double (low
, high
, l
, h
, &low
, &high
);
9622 gcc_assert (overflow
== 0);
9624 return build_int_cst_wide (rtype
, low
, high
);
9634 /* ??? This duplicates information provided to the compiler by the
9635 ??? scheduler description. Some day, teach genautomata to output
9636 ??? the latencies and then CSE will just use that. */
9639 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
9640 int *total
, bool speed ATTRIBUTE_UNUSED
)
9642 enum machine_mode mode
= GET_MODE (x
);
9643 bool float_mode_p
= FLOAT_MODE_P (mode
);
9648 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
9666 if (GET_MODE (x
) == VOIDmode
9667 && ((CONST_DOUBLE_HIGH (x
) == 0
9668 && CONST_DOUBLE_LOW (x
) < 0x1000)
9669 || (CONST_DOUBLE_HIGH (x
) == -1
9670 && CONST_DOUBLE_LOW (x
) < 0
9671 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
9678 /* If outer-code was a sign or zero extension, a cost
9679 of COSTS_N_INSNS (1) was already added in. This is
9680 why we are subtracting it back out. */
9681 if (outer_code
== ZERO_EXTEND
)
9683 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
9685 else if (outer_code
== SIGN_EXTEND
)
9687 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
9689 else if (float_mode_p
)
9691 *total
= sparc_costs
->float_load
;
9695 *total
= sparc_costs
->int_load
;
9703 *total
= sparc_costs
->float_plusminus
;
9705 *total
= COSTS_N_INSNS (1);
9712 gcc_assert (float_mode_p
);
9713 *total
= sparc_costs
->float_mul
;
9716 if (GET_CODE (sub
) == NEG
)
9717 sub
= XEXP (sub
, 0);
9718 *total
+= rtx_cost (sub
, FMA
, 0, speed
);
9721 if (GET_CODE (sub
) == NEG
)
9722 sub
= XEXP (sub
, 0);
9723 *total
+= rtx_cost (sub
, FMA
, 2, speed
);
9729 *total
= sparc_costs
->float_mul
;
9730 else if (! TARGET_HARD_MUL
)
9731 *total
= COSTS_N_INSNS (25);
9737 if (sparc_costs
->int_mul_bit_factor
)
9741 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9743 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
9744 for (nbits
= 0; value
!= 0; value
&= value
- 1)
9747 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
9748 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
9750 rtx x1
= XEXP (x
, 1);
9751 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
9752 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
9754 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
9756 for (; value2
!= 0; value2
&= value2
- 1)
9764 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
9765 bit_cost
= COSTS_N_INSNS (bit_cost
);
9769 *total
= sparc_costs
->int_mulX
+ bit_cost
;
9771 *total
= sparc_costs
->int_mul
+ bit_cost
;
9778 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
9788 *total
= sparc_costs
->float_div_df
;
9790 *total
= sparc_costs
->float_div_sf
;
9795 *total
= sparc_costs
->int_divX
;
9797 *total
= sparc_costs
->int_div
;
9804 *total
= COSTS_N_INSNS (1);
9811 case UNSIGNED_FLOAT
:
9815 case FLOAT_TRUNCATE
:
9816 *total
= sparc_costs
->float_move
;
9821 *total
= sparc_costs
->float_sqrt_df
;
9823 *total
= sparc_costs
->float_sqrt_sf
;
9828 *total
= sparc_costs
->float_cmp
;
9830 *total
= COSTS_N_INSNS (1);
9835 *total
= sparc_costs
->float_cmove
;
9837 *total
= sparc_costs
->int_cmove
;
9841 /* Handle the NAND vector patterns. */
9842 if (sparc_vector_mode_supported_p (GET_MODE (x
))
9843 && GET_CODE (XEXP (x
, 0)) == NOT
9844 && GET_CODE (XEXP (x
, 1)) == NOT
)
9846 *total
= COSTS_N_INSNS (1);
9857 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
9860 general_or_i64_p (reg_class_t rclass
)
9862 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
9865 /* Implement TARGET_REGISTER_MOVE_COST. */
9868 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
9869 reg_class_t from
, reg_class_t to
)
9871 if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
9872 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
))
9873 || from
== FPCC_REGS
9876 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9877 || sparc_cpu
== PROCESSOR_ULTRASPARC3
9878 || sparc_cpu
== PROCESSOR_NIAGARA
9879 || sparc_cpu
== PROCESSOR_NIAGARA2
9880 || sparc_cpu
== PROCESSOR_NIAGARA3
9881 || sparc_cpu
== PROCESSOR_NIAGARA4
)
9890 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
9891 This is achieved by means of a manual dynamic stack space allocation in
9892 the current frame. We make the assumption that SEQ doesn't contain any
9893 function calls, with the possible exception of calls to the GOT helper. */
9896 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
9898 /* We must preserve the lowest 16 words for the register save area. */
9899 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
9900 /* We really need only 2 words of fresh stack space. */
9901 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
9904 = gen_rtx_MEM (word_mode
, plus_constant (stack_pointer_rtx
,
9905 SPARC_STACK_BIAS
+ offset
));
9907 emit_insn (gen_stack_pointer_dec (GEN_INT (size
)));
9908 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
9910 emit_insn (gen_rtx_SET (VOIDmode
,
9911 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
9915 emit_insn (gen_rtx_SET (VOIDmode
,
9917 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
9918 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
9919 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
9922 /* Output the assembler code for a thunk function. THUNK_DECL is the
9923 declaration for the thunk function itself, FUNCTION is the decl for
9924 the target function. DELTA is an immediate constant offset to be
9925 added to THIS. If VCALL_OFFSET is nonzero, the word at address
9926 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
9929 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
9930 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9933 rtx this_rtx
, insn
, funexp
;
9934 unsigned int int_arg_first
;
9936 reload_completed
= 1;
9937 epilogue_completed
= 1;
9939 emit_note (NOTE_INSN_PROLOGUE_END
);
9943 sparc_leaf_function_p
= 1;
9945 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
9947 else if (flag_delayed_branch
)
9949 /* We will emit a regular sibcall below, so we need to instruct
9950 output_sibcall that we are in a leaf function. */
9951 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
9953 /* This will cause final.c to invoke leaf_renumber_regs so we
9954 must behave as if we were in a not-yet-leafified function. */
9955 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
9959 /* We will emit the sibcall manually below, so we will need to
9960 manually spill non-leaf registers. */
9961 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
9963 /* We really are in a leaf function. */
9964 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
9967 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9968 returns a structure, the structure return pointer is there instead. */
9970 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9971 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
9973 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
9975 /* Add DELTA. When possible use a plain add, otherwise load it into
9976 a register first. */
9979 rtx delta_rtx
= GEN_INT (delta
);
9981 if (! SPARC_SIMM13_P (delta
))
9983 rtx scratch
= gen_rtx_REG (Pmode
, 1);
9984 emit_move_insn (scratch
, delta_rtx
);
9985 delta_rtx
= scratch
;
9988 /* THIS_RTX += DELTA. */
9989 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
9992 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
9995 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
9996 rtx scratch
= gen_rtx_REG (Pmode
, 1);
9998 gcc_assert (vcall_offset
< 0);
10000 /* SCRATCH = *THIS_RTX. */
10001 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
10003 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
10004 may not have any available scratch register at this point. */
10005 if (SPARC_SIMM13_P (vcall_offset
))
10007 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
10008 else if (! fixed_regs
[5]
10009 /* The below sequence is made up of at least 2 insns,
10010 while the default method may need only one. */
10011 && vcall_offset
< -8192)
10013 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
10014 emit_move_insn (scratch2
, vcall_offset_rtx
);
10015 vcall_offset_rtx
= scratch2
;
10019 rtx increment
= GEN_INT (-4096);
10021 /* VCALL_OFFSET is a negative number whose typical range can be
10022 estimated as -32768..0 in 32-bit mode. In almost all cases
10023 it is therefore cheaper to emit multiple add insns than
10024 spilling and loading the constant into a register (at least
10026 while (! SPARC_SIMM13_P (vcall_offset
))
10028 emit_insn (gen_add2_insn (scratch
, increment
));
10029 vcall_offset
+= 4096;
10031 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
10034 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
10035 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
10036 gen_rtx_PLUS (Pmode
,
10038 vcall_offset_rtx
)));
10040 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
10041 emit_insn (gen_add2_insn (this_rtx
, scratch
));
10044 /* Generate a tail call to the target function. */
10045 if (! TREE_USED (function
))
10047 assemble_external (function
);
10048 TREE_USED (function
) = 1;
10050 funexp
= XEXP (DECL_RTL (function
), 0);
10052 if (flag_delayed_branch
)
10054 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
10055 insn
= emit_call_insn (gen_sibcall (funexp
));
10056 SIBLING_CALL_P (insn
) = 1;
10060 /* The hoops we have to jump through in order to generate a sibcall
10061 without using delay slots... */
10062 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
10066 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
10068 load_got_register (); /* clobbers %o7 */
10069 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
10070 seq
= get_insns ();
10072 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
10074 else if (TARGET_ARCH32
)
10076 emit_insn (gen_rtx_SET (VOIDmode
,
10078 gen_rtx_HIGH (SImode
, funexp
)));
10079 emit_insn (gen_rtx_SET (VOIDmode
,
10081 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
10083 else /* TARGET_ARCH64 */
10085 switch (sparc_cmodel
)
10089 /* The destination can serve as a temporary. */
10090 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
10095 /* The destination cannot serve as a temporary. */
10096 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
10098 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
10099 seq
= get_insns ();
10101 emit_and_preserve (seq
, spill_reg
, 0);
10105 gcc_unreachable ();
10109 emit_jump_insn (gen_indirect_jump (scratch
));
10114 /* Run just enough of rest_of_compilation to get the insns emitted.
10115 There's not really enough bulk here to make other passes such as
10116 instruction scheduling worth while. Note that use_thunk calls
10117 assemble_start_function and assemble_end_function. */
10118 insn
= get_insns ();
10119 insn_locators_alloc ();
10120 shorten_branches (insn
);
10121 final_start_function (insn
, file
, 1);
10122 final (insn
, file
, 1);
10123 final_end_function ();
10125 reload_completed
= 0;
10126 epilogue_completed
= 0;
10129 /* Return true if sparc_output_mi_thunk would be able to output the
10130 assembler code for the thunk function specified by the arguments
10131 it is passed, and false otherwise. */
10133 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
10134 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
10135 HOST_WIDE_INT vcall_offset
,
10136 const_tree function ATTRIBUTE_UNUSED
)
10138 /* Bound the loop used in the default method above. */
10139 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
10142 /* How to allocate a 'struct machine_function'. */
10144 static struct machine_function
*
10145 sparc_init_machine_status (void)
10147 return ggc_alloc_cleared_machine_function ();
10150 /* Locate some local-dynamic symbol still in use by this function
10151 so that we can print its name in local-dynamic base patterns. */
10153 static const char *
10154 get_some_local_dynamic_name (void)
10158 if (cfun
->machine
->some_ld_name
)
10159 return cfun
->machine
->some_ld_name
;
10161 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10163 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
10164 return cfun
->machine
->some_ld_name
;
10166 gcc_unreachable ();
10170 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
10175 && GET_CODE (x
) == SYMBOL_REF
10176 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
10178 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
10185 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10186 We need to emit DTP-relative relocations. */
10189 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
10194 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
10197 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
10200 gcc_unreachable ();
10202 output_addr_const (file
, x
);
10206 /* Do whatever processing is required at the end of a file. */
10209 sparc_file_end (void)
10211 /* If we need to emit the special GOT helper function, do so now. */
10212 if (got_helper_rtx
)
10214 const char *name
= XSTR (got_helper_rtx
, 0);
10215 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
10216 #ifdef DWARF2_UNWIND_INFO
10220 if (USE_HIDDEN_LINKONCE
)
10222 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
10223 get_identifier (name
),
10224 build_function_type_list (void_type_node
,
10226 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
10227 NULL_TREE
, void_type_node
);
10228 TREE_STATIC (decl
) = 1;
10229 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
10230 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
10231 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
10232 resolve_unique_section (decl
, 0, flag_function_sections
);
10233 allocate_struct_function (decl
, true);
10234 cfun
->is_thunk
= 1;
10235 current_function_decl
= decl
;
10236 init_varasm_status ();
10237 assemble_start_function (decl
, name
);
10241 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10242 switch_to_section (text_section
);
10244 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10245 ASM_OUTPUT_LABEL (asm_out_file
, name
);
10248 #ifdef DWARF2_UNWIND_INFO
10249 do_cfi
= dwarf2out_do_cfi_asm ();
10251 fprintf (asm_out_file
, "\t.cfi_startproc\n");
10253 if (flag_delayed_branch
)
10254 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10255 reg_name
, reg_name
);
10257 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10258 reg_name
, reg_name
);
10259 #ifdef DWARF2_UNWIND_INFO
10261 fprintf (asm_out_file
, "\t.cfi_endproc\n");
10265 if (NEED_INDICATE_EXEC_STACK
)
10266 file_end_indicate_exec_stack ();
10268 #ifdef TARGET_SOLARIS
10269 solaris_file_end ();
10273 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10274 /* Implement TARGET_MANGLE_TYPE. */
10276 static const char *
10277 sparc_mangle_type (const_tree type
)
10280 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
10281 && TARGET_LONG_DOUBLE_128
)
10284 /* For all other types, use normal C++ mangling. */
10289 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10290 compare and swap on the word containing the byte or half-word. */
10293 sparc_expand_compare_and_swap_12 (rtx result
, rtx mem
, rtx oldval
, rtx newval
)
10295 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
10296 rtx addr
= gen_reg_rtx (Pmode
);
10297 rtx off
= gen_reg_rtx (SImode
);
10298 rtx oldv
= gen_reg_rtx (SImode
);
10299 rtx newv
= gen_reg_rtx (SImode
);
10300 rtx oldvalue
= gen_reg_rtx (SImode
);
10301 rtx newvalue
= gen_reg_rtx (SImode
);
10302 rtx res
= gen_reg_rtx (SImode
);
10303 rtx resv
= gen_reg_rtx (SImode
);
10304 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
10306 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
10307 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
10309 if (Pmode
!= SImode
)
10310 addr1
= gen_lowpart (SImode
, addr1
);
10311 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10312 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
10314 memsi
= gen_rtx_MEM (SImode
, addr
);
10315 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
10316 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
10318 val
= force_reg (SImode
, memsi
);
10320 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10321 gen_rtx_XOR (SImode
, off
,
10322 GEN_INT (GET_MODE (mem
) == QImode
10325 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10326 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
10328 if (GET_MODE (mem
) == QImode
)
10329 mask
= force_reg (SImode
, GEN_INT (0xff));
10331 mask
= force_reg (SImode
, GEN_INT (0xffff));
10333 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
10334 gen_rtx_ASHIFT (SImode
, mask
, off
)));
10336 emit_insn (gen_rtx_SET (VOIDmode
, val
,
10337 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10340 oldval
= gen_lowpart (SImode
, oldval
);
10341 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10342 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
10344 newval
= gen_lowpart_common (SImode
, newval
);
10345 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10346 gen_rtx_ASHIFT (SImode
, newval
, off
)));
10348 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10349 gen_rtx_AND (SImode
, oldv
, mask
)));
10351 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10352 gen_rtx_AND (SImode
, newv
, mask
)));
10354 end_label
= gen_label_rtx ();
10355 loop_label
= gen_label_rtx ();
10356 emit_label (loop_label
);
10358 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
10359 gen_rtx_IOR (SImode
, oldv
, val
)));
10361 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
10362 gen_rtx_IOR (SImode
, newv
, val
)));
10364 emit_insn (gen_sync_compare_and_swapsi (res
, memsi
, oldvalue
, newvalue
));
10366 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
10368 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
10369 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10372 cc
= gen_compare_reg_1 (NE
, resv
, val
);
10373 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
10375 /* Use cbranchcc4 to separate the compare and branch! */
10376 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
10377 cc
, const0_rtx
, loop_label
));
10379 emit_label (end_label
);
10381 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10382 gen_rtx_AND (SImode
, res
, mask
)));
10384 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10385 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
10387 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
10390 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10393 sparc_frame_pointer_required (void)
10395 /* If the stack pointer is dynamically modified in the function, it cannot
10396 serve as the frame pointer. */
10397 if (cfun
->calls_alloca
)
10400 /* If the function receives nonlocal gotos, it needs to save the frame
10401 pointer in the nonlocal_goto_save_area object. */
10402 if (cfun
->has_nonlocal_label
)
10405 /* In flat mode, that's it. */
10409 /* Otherwise, the frame pointer is required if the function isn't leaf. */
10410 return !(current_function_is_leaf
&& only_leaf_regs_used ());
10413 /* The way this is structured, we can't eliminate SFP in favor of SP
10414 if the frame pointer is required: we want to use the SFP->HFP elimination
10415 in that case. But the test in update_eliminables doesn't know we are
10416 assuming below that we only do the former elimination. */
10419 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10421 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
10424 /* Return the hard frame pointer directly to bypass the stack bias. */
10427 sparc_builtin_setjmp_frame_value (void)
10429 return hard_frame_pointer_rtx
;
10432 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
10433 they won't be allocated. */
10436 sparc_conditional_register_usage (void)
10438 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
10440 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10441 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10443 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
10444 /* then honor it. */
10445 if (TARGET_ARCH32
&& fixed_regs
[5])
10447 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
10452 for (regno
= SPARC_FIRST_V9_FP_REG
;
10453 regno
<= SPARC_LAST_V9_FP_REG
;
10455 fixed_regs
[regno
] = 1;
10456 /* %fcc0 is used by v8 and v9. */
10457 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
10458 regno
<= SPARC_LAST_V9_FCC_REG
;
10460 fixed_regs
[regno
] = 1;
10465 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
10466 fixed_regs
[regno
] = 1;
10468 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
10469 /* then honor it. Likewise with g3 and g4. */
10470 if (fixed_regs
[2] == 2)
10471 fixed_regs
[2] = ! TARGET_APP_REGS
;
10472 if (fixed_regs
[3] == 2)
10473 fixed_regs
[3] = ! TARGET_APP_REGS
;
10474 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
10475 fixed_regs
[4] = ! TARGET_APP_REGS
;
10476 else if (TARGET_CM_EMBMEDANY
)
10478 else if (fixed_regs
[4] == 2)
10483 /* Disable leaf functions. */
10484 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
10485 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
10486 leaf_reg_remap
[regno
] = regno
;
10489 global_regs
[SPARC_GSR_REG
] = 1;
10492 /* Implement TARGET_PREFERRED_RELOAD_CLASS
10494 - We can't load constants into FP registers.
10495 - We can't load FP constants into integer registers when soft-float,
10496 because there is no soft-float pattern with a r/F constraint.
10497 - We can't load FP constants into integer registers for TFmode unless
10498 it is 0.0L, because there is no movtf pattern with a r/F constraint.
10499 - Try and reload integer constants (symbolic or otherwise) back into
10500 registers directly, rather than having them dumped to memory. */
10503 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
10505 if (CONSTANT_P (x
))
10507 if (FP_REG_CLASS_P (rclass
)
10508 || rclass
== GENERAL_OR_FP_REGS
10509 || rclass
== GENERAL_OR_EXTRA_FP_REGS
10510 || (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
&& ! TARGET_FPU
)
10511 || (GET_MODE (x
) == TFmode
&& ! const_zero_operand (x
, TFmode
)))
10514 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
10515 return GENERAL_REGS
;
10521 #include "gt-sparc.h"