1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
54 #include "langhooks.h"
58 #include "dwarf2out.h"
63 struct processor_costs cypress_costs
= {
64 COSTS_N_INSNS (2), /* int load */
65 COSTS_N_INSNS (2), /* int signed load */
66 COSTS_N_INSNS (2), /* int zeroed load */
67 COSTS_N_INSNS (2), /* float load */
68 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
69 COSTS_N_INSNS (5), /* fadd, fsub */
70 COSTS_N_INSNS (1), /* fcmp */
71 COSTS_N_INSNS (1), /* fmov, fmovr */
72 COSTS_N_INSNS (7), /* fmul */
73 COSTS_N_INSNS (37), /* fdivs */
74 COSTS_N_INSNS (37), /* fdivd */
75 COSTS_N_INSNS (63), /* fsqrts */
76 COSTS_N_INSNS (63), /* fsqrtd */
77 COSTS_N_INSNS (1), /* imul */
78 COSTS_N_INSNS (1), /* imulX */
79 0, /* imul bit factor */
80 COSTS_N_INSNS (1), /* idiv */
81 COSTS_N_INSNS (1), /* idivX */
82 COSTS_N_INSNS (1), /* movcc/movr */
83 0, /* shift penalty */
87 struct processor_costs supersparc_costs
= {
88 COSTS_N_INSNS (1), /* int load */
89 COSTS_N_INSNS (1), /* int signed load */
90 COSTS_N_INSNS (1), /* int zeroed load */
91 COSTS_N_INSNS (0), /* float load */
92 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
93 COSTS_N_INSNS (3), /* fadd, fsub */
94 COSTS_N_INSNS (3), /* fcmp */
95 COSTS_N_INSNS (1), /* fmov, fmovr */
96 COSTS_N_INSNS (3), /* fmul */
97 COSTS_N_INSNS (6), /* fdivs */
98 COSTS_N_INSNS (9), /* fdivd */
99 COSTS_N_INSNS (12), /* fsqrts */
100 COSTS_N_INSNS (12), /* fsqrtd */
101 COSTS_N_INSNS (4), /* imul */
102 COSTS_N_INSNS (4), /* imulX */
103 0, /* imul bit factor */
104 COSTS_N_INSNS (4), /* idiv */
105 COSTS_N_INSNS (4), /* idivX */
106 COSTS_N_INSNS (1), /* movcc/movr */
107 1, /* shift penalty */
111 struct processor_costs hypersparc_costs
= {
112 COSTS_N_INSNS (1), /* int load */
113 COSTS_N_INSNS (1), /* int signed load */
114 COSTS_N_INSNS (1), /* int zeroed load */
115 COSTS_N_INSNS (1), /* float load */
116 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
117 COSTS_N_INSNS (1), /* fadd, fsub */
118 COSTS_N_INSNS (1), /* fcmp */
119 COSTS_N_INSNS (1), /* fmov, fmovr */
120 COSTS_N_INSNS (1), /* fmul */
121 COSTS_N_INSNS (8), /* fdivs */
122 COSTS_N_INSNS (12), /* fdivd */
123 COSTS_N_INSNS (17), /* fsqrts */
124 COSTS_N_INSNS (17), /* fsqrtd */
125 COSTS_N_INSNS (17), /* imul */
126 COSTS_N_INSNS (17), /* imulX */
127 0, /* imul bit factor */
128 COSTS_N_INSNS (17), /* idiv */
129 COSTS_N_INSNS (17), /* idivX */
130 COSTS_N_INSNS (1), /* movcc/movr */
131 0, /* shift penalty */
135 struct processor_costs leon_costs
= {
136 COSTS_N_INSNS (1), /* int load */
137 COSTS_N_INSNS (1), /* int signed load */
138 COSTS_N_INSNS (1), /* int zeroed load */
139 COSTS_N_INSNS (1), /* float load */
140 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
141 COSTS_N_INSNS (1), /* fadd, fsub */
142 COSTS_N_INSNS (1), /* fcmp */
143 COSTS_N_INSNS (1), /* fmov, fmovr */
144 COSTS_N_INSNS (1), /* fmul */
145 COSTS_N_INSNS (15), /* fdivs */
146 COSTS_N_INSNS (15), /* fdivd */
147 COSTS_N_INSNS (23), /* fsqrts */
148 COSTS_N_INSNS (23), /* fsqrtd */
149 COSTS_N_INSNS (5), /* imul */
150 COSTS_N_INSNS (5), /* imulX */
151 0, /* imul bit factor */
152 COSTS_N_INSNS (5), /* idiv */
153 COSTS_N_INSNS (5), /* idivX */
154 COSTS_N_INSNS (1), /* movcc/movr */
155 0, /* shift penalty */
159 struct processor_costs sparclet_costs
= {
160 COSTS_N_INSNS (3), /* int load */
161 COSTS_N_INSNS (3), /* int signed load */
162 COSTS_N_INSNS (1), /* int zeroed load */
163 COSTS_N_INSNS (1), /* float load */
164 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
165 COSTS_N_INSNS (1), /* fadd, fsub */
166 COSTS_N_INSNS (1), /* fcmp */
167 COSTS_N_INSNS (1), /* fmov, fmovr */
168 COSTS_N_INSNS (1), /* fmul */
169 COSTS_N_INSNS (1), /* fdivs */
170 COSTS_N_INSNS (1), /* fdivd */
171 COSTS_N_INSNS (1), /* fsqrts */
172 COSTS_N_INSNS (1), /* fsqrtd */
173 COSTS_N_INSNS (5), /* imul */
174 COSTS_N_INSNS (5), /* imulX */
175 0, /* imul bit factor */
176 COSTS_N_INSNS (5), /* idiv */
177 COSTS_N_INSNS (5), /* idivX */
178 COSTS_N_INSNS (1), /* movcc/movr */
179 0, /* shift penalty */
183 struct processor_costs ultrasparc_costs
= {
184 COSTS_N_INSNS (2), /* int load */
185 COSTS_N_INSNS (3), /* int signed load */
186 COSTS_N_INSNS (2), /* int zeroed load */
187 COSTS_N_INSNS (2), /* float load */
188 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
189 COSTS_N_INSNS (4), /* fadd, fsub */
190 COSTS_N_INSNS (1), /* fcmp */
191 COSTS_N_INSNS (2), /* fmov, fmovr */
192 COSTS_N_INSNS (4), /* fmul */
193 COSTS_N_INSNS (13), /* fdivs */
194 COSTS_N_INSNS (23), /* fdivd */
195 COSTS_N_INSNS (13), /* fsqrts */
196 COSTS_N_INSNS (23), /* fsqrtd */
197 COSTS_N_INSNS (4), /* imul */
198 COSTS_N_INSNS (4), /* imulX */
199 2, /* imul bit factor */
200 COSTS_N_INSNS (37), /* idiv */
201 COSTS_N_INSNS (68), /* idivX */
202 COSTS_N_INSNS (2), /* movcc/movr */
203 2, /* shift penalty */
207 struct processor_costs ultrasparc3_costs
= {
208 COSTS_N_INSNS (2), /* int load */
209 COSTS_N_INSNS (3), /* int signed load */
210 COSTS_N_INSNS (3), /* int zeroed load */
211 COSTS_N_INSNS (2), /* float load */
212 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
213 COSTS_N_INSNS (4), /* fadd, fsub */
214 COSTS_N_INSNS (5), /* fcmp */
215 COSTS_N_INSNS (3), /* fmov, fmovr */
216 COSTS_N_INSNS (4), /* fmul */
217 COSTS_N_INSNS (17), /* fdivs */
218 COSTS_N_INSNS (20), /* fdivd */
219 COSTS_N_INSNS (20), /* fsqrts */
220 COSTS_N_INSNS (29), /* fsqrtd */
221 COSTS_N_INSNS (6), /* imul */
222 COSTS_N_INSNS (6), /* imulX */
223 0, /* imul bit factor */
224 COSTS_N_INSNS (40), /* idiv */
225 COSTS_N_INSNS (71), /* idivX */
226 COSTS_N_INSNS (2), /* movcc/movr */
227 0, /* shift penalty */
231 struct processor_costs niagara_costs
= {
232 COSTS_N_INSNS (3), /* int load */
233 COSTS_N_INSNS (3), /* int signed load */
234 COSTS_N_INSNS (3), /* int zeroed load */
235 COSTS_N_INSNS (9), /* float load */
236 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
237 COSTS_N_INSNS (8), /* fadd, fsub */
238 COSTS_N_INSNS (26), /* fcmp */
239 COSTS_N_INSNS (8), /* fmov, fmovr */
240 COSTS_N_INSNS (29), /* fmul */
241 COSTS_N_INSNS (54), /* fdivs */
242 COSTS_N_INSNS (83), /* fdivd */
243 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
244 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
245 COSTS_N_INSNS (11), /* imul */
246 COSTS_N_INSNS (11), /* imulX */
247 0, /* imul bit factor */
248 COSTS_N_INSNS (72), /* idiv */
249 COSTS_N_INSNS (72), /* idivX */
250 COSTS_N_INSNS (1), /* movcc/movr */
251 0, /* shift penalty */
255 struct processor_costs niagara2_costs
= {
256 COSTS_N_INSNS (3), /* int load */
257 COSTS_N_INSNS (3), /* int signed load */
258 COSTS_N_INSNS (3), /* int zeroed load */
259 COSTS_N_INSNS (3), /* float load */
260 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
261 COSTS_N_INSNS (6), /* fadd, fsub */
262 COSTS_N_INSNS (6), /* fcmp */
263 COSTS_N_INSNS (6), /* fmov, fmovr */
264 COSTS_N_INSNS (6), /* fmul */
265 COSTS_N_INSNS (19), /* fdivs */
266 COSTS_N_INSNS (33), /* fdivd */
267 COSTS_N_INSNS (19), /* fsqrts */
268 COSTS_N_INSNS (33), /* fsqrtd */
269 COSTS_N_INSNS (5), /* imul */
270 COSTS_N_INSNS (5), /* imulX */
271 0, /* imul bit factor */
272 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
274 COSTS_N_INSNS (1), /* movcc/movr */
275 0, /* shift penalty */
279 struct processor_costs niagara3_costs
= {
280 COSTS_N_INSNS (3), /* int load */
281 COSTS_N_INSNS (3), /* int signed load */
282 COSTS_N_INSNS (3), /* int zeroed load */
283 COSTS_N_INSNS (3), /* float load */
284 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
285 COSTS_N_INSNS (9), /* fadd, fsub */
286 COSTS_N_INSNS (9), /* fcmp */
287 COSTS_N_INSNS (9), /* fmov, fmovr */
288 COSTS_N_INSNS (9), /* fmul */
289 COSTS_N_INSNS (23), /* fdivs */
290 COSTS_N_INSNS (37), /* fdivd */
291 COSTS_N_INSNS (23), /* fsqrts */
292 COSTS_N_INSNS (37), /* fsqrtd */
293 COSTS_N_INSNS (9), /* imul */
294 COSTS_N_INSNS (9), /* imulX */
295 0, /* imul bit factor */
296 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
297 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
298 COSTS_N_INSNS (1), /* movcc/movr */
299 0, /* shift penalty */
302 const struct processor_costs
*sparc_costs
= &cypress_costs
;
304 #ifdef HAVE_AS_RELAX_OPTION
305 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
306 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
307 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
308 somebody does not branch between the sethi and jmp. */
309 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
311 #define LEAF_SIBCALL_SLOT_RESERVED_P \
312 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
315 /* Vector to say how input registers are mapped to output registers.
316 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
317 eliminate it. You must use -fomit-frame-pointer to get that. */
318 char leaf_reg_remap
[] =
319 { 0, 1, 2, 3, 4, 5, 6, 7,
320 -1, -1, -1, -1, -1, -1, 14, -1,
321 -1, -1, -1, -1, -1, -1, -1, -1,
322 8, 9, 10, 11, 12, 13, -1, 15,
324 32, 33, 34, 35, 36, 37, 38, 39,
325 40, 41, 42, 43, 44, 45, 46, 47,
326 48, 49, 50, 51, 52, 53, 54, 55,
327 56, 57, 58, 59, 60, 61, 62, 63,
328 64, 65, 66, 67, 68, 69, 70, 71,
329 72, 73, 74, 75, 76, 77, 78, 79,
330 80, 81, 82, 83, 84, 85, 86, 87,
331 88, 89, 90, 91, 92, 93, 94, 95,
332 96, 97, 98, 99, 100, 101, 102};
334 /* Vector, indexed by hard register number, which contains 1
335 for a register that is allowable in a candidate for leaf
336 function treatment. */
337 char sparc_leaf_regs
[] =
338 { 1, 1, 1, 1, 1, 1, 1, 1,
339 0, 0, 0, 0, 0, 0, 1, 0,
340 0, 0, 0, 0, 0, 0, 0, 0,
341 1, 1, 1, 1, 1, 1, 0, 1,
342 1, 1, 1, 1, 1, 1, 1, 1,
343 1, 1, 1, 1, 1, 1, 1, 1,
344 1, 1, 1, 1, 1, 1, 1, 1,
345 1, 1, 1, 1, 1, 1, 1, 1,
346 1, 1, 1, 1, 1, 1, 1, 1,
347 1, 1, 1, 1, 1, 1, 1, 1,
348 1, 1, 1, 1, 1, 1, 1, 1,
349 1, 1, 1, 1, 1, 1, 1, 1,
350 1, 1, 1, 1, 1, 1, 1};
352 struct GTY(()) machine_function
354 /* Size of the frame of the function. */
355 HOST_WIDE_INT frame_size
;
357 /* Size of the frame of the function minus the register window save area
358 and the outgoing argument area. */
359 HOST_WIDE_INT apparent_frame_size
;
361 /* Register we pretend the frame pointer is allocated to. Normally, this
362 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
363 record "offset" separately as it may be too big for (reg + disp). */
365 HOST_WIDE_INT frame_base_offset
;
367 /* Some local-dynamic TLS symbol name. */
368 const char *some_ld_name
;
370 /* Number of global or FP registers to be saved (as 4-byte quantities). */
371 int n_global_fp_regs
;
373 /* True if the current function is leaf and uses only leaf regs,
374 so that the SPARC leaf function optimization can be applied.
375 Private version of current_function_uses_only_leaf_regs, see
376 sparc_expand_prologue for the rationale. */
379 /* True if the prologue saves local or in registers. */
380 bool save_local_in_regs_p
;
382 /* True if the data calculated by sparc_expand_prologue are valid. */
383 bool prologue_data_valid_p
;
386 #define sparc_frame_size cfun->machine->frame_size
387 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
388 #define sparc_frame_base_reg cfun->machine->frame_base_reg
389 #define sparc_frame_base_offset cfun->machine->frame_base_offset
390 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
391 #define sparc_leaf_function_p cfun->machine->leaf_function_p
392 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
393 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
395 /* 1 if the next opcode is to be specially indented. */
396 int sparc_indent_opcode
= 0;
398 static void sparc_option_override (void);
399 static void sparc_init_modes (void);
400 static void scan_record_type (const_tree
, int *, int *, int *);
401 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
402 const_tree
, bool, bool, int *, int *);
404 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
405 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
407 static void sparc_emit_set_const32 (rtx
, rtx
);
408 static void sparc_emit_set_const64 (rtx
, rtx
);
409 static void sparc_output_addr_vec (rtx
);
410 static void sparc_output_addr_diff_vec (rtx
);
411 static void sparc_output_deferred_case_vectors (void);
412 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
413 static bool sparc_legitimate_constant_p (enum machine_mode
, rtx
);
414 static rtx
sparc_builtin_saveregs (void);
415 static int epilogue_renumber (rtx
*, int);
416 static bool sparc_assemble_integer (rtx
, unsigned int, int);
417 static int set_extends (rtx
);
418 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
419 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
420 #ifdef TARGET_SOLARIS
421 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
422 tree
) ATTRIBUTE_UNUSED
;
424 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
425 static int sparc_issue_rate (void);
426 static void sparc_sched_init (FILE *, int, int);
427 static int sparc_use_sched_lookahead (void);
429 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
430 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
431 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
432 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
433 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
435 static bool sparc_function_ok_for_sibcall (tree
, tree
);
436 static void sparc_init_libfuncs (void);
437 static void sparc_init_builtins (void);
438 static void sparc_vis_init_builtins (void);
439 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
440 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
441 static int sparc_vis_mul8x16 (int, int);
442 static tree
sparc_handle_vis_mul8x16 (int, tree
, tree
, tree
);
443 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
444 HOST_WIDE_INT
, tree
);
445 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
446 HOST_WIDE_INT
, const_tree
);
447 static void sparc_reorg (void);
448 static struct machine_function
* sparc_init_machine_status (void);
449 static bool sparc_cannot_force_const_mem (enum machine_mode
, rtx
);
450 static rtx
sparc_tls_get_addr (void);
451 static rtx
sparc_tls_got (void);
452 static const char *get_some_local_dynamic_name (void);
453 static int get_some_local_dynamic_name_1 (rtx
*, void *);
454 static int sparc_register_move_cost (enum machine_mode
,
455 reg_class_t
, reg_class_t
);
456 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
457 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
458 static rtx
sparc_libcall_value (enum machine_mode
, const_rtx
);
459 static bool sparc_function_value_regno_p (const unsigned int);
460 static rtx
sparc_struct_value_rtx (tree
, int);
461 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
462 int *, const_tree
, int);
463 static bool sparc_return_in_memory (const_tree
, const_tree
);
464 static bool sparc_strict_argument_naming (cumulative_args_t
);
465 static void sparc_va_start (tree
, rtx
);
466 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
467 static bool sparc_vector_mode_supported_p (enum machine_mode
);
468 static bool sparc_tls_referenced_p (rtx
);
469 static rtx
sparc_legitimize_tls_address (rtx
);
470 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
471 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
472 static rtx
sparc_delegitimize_address (rtx
);
473 static bool sparc_mode_dependent_address_p (const_rtx
);
474 static bool sparc_pass_by_reference (cumulative_args_t
,
475 enum machine_mode
, const_tree
, bool);
476 static void sparc_function_arg_advance (cumulative_args_t
,
477 enum machine_mode
, const_tree
, bool);
478 static rtx
sparc_function_arg_1 (cumulative_args_t
,
479 enum machine_mode
, const_tree
, bool, bool);
480 static rtx
sparc_function_arg (cumulative_args_t
,
481 enum machine_mode
, const_tree
, bool);
482 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
483 enum machine_mode
, const_tree
, bool);
484 static unsigned int sparc_function_arg_boundary (enum machine_mode
,
486 static int sparc_arg_partial_bytes (cumulative_args_t
,
487 enum machine_mode
, tree
, bool);
488 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
489 static void sparc_file_end (void);
490 static bool sparc_frame_pointer_required (void);
491 static bool sparc_can_eliminate (const int, const int);
492 static rtx
sparc_builtin_setjmp_frame_value (void);
493 static void sparc_conditional_register_usage (void);
494 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
495 static const char *sparc_mangle_type (const_tree
);
497 static void sparc_trampoline_init (rtx
, tree
, rtx
);
498 static enum machine_mode
sparc_preferred_simd_mode (enum machine_mode
);
499 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
500 static bool sparc_print_operand_punct_valid_p (unsigned char);
501 static void sparc_print_operand (FILE *, rtx
, int);
502 static void sparc_print_operand_address (FILE *, rtx
);
504 #ifdef SUBTARGET_ATTRIBUTE_TABLE
505 /* Table of valid machine attributes. */
506 static const struct attribute_spec sparc_attribute_table
[] =
508 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
510 SUBTARGET_ATTRIBUTE_TABLE
,
511 { NULL
, 0, 0, false, false, false, NULL
, false }
515 /* Option handling. */
518 enum cmodel sparc_cmodel
;
520 char sparc_hard_reg_printed
[8];
522 /* Initialize the GCC target structure. */
524 /* The default is to use .half rather than .short for aligned HI objects. */
525 #undef TARGET_ASM_ALIGNED_HI_OP
526 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
528 #undef TARGET_ASM_UNALIGNED_HI_OP
529 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
530 #undef TARGET_ASM_UNALIGNED_SI_OP
531 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
532 #undef TARGET_ASM_UNALIGNED_DI_OP
533 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
535 /* The target hook has to handle DI-mode values. */
536 #undef TARGET_ASM_INTEGER
537 #define TARGET_ASM_INTEGER sparc_assemble_integer
539 #undef TARGET_ASM_FUNCTION_PROLOGUE
540 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
541 #undef TARGET_ASM_FUNCTION_EPILOGUE
542 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
544 #undef TARGET_SCHED_ADJUST_COST
545 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
546 #undef TARGET_SCHED_ISSUE_RATE
547 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
548 #undef TARGET_SCHED_INIT
549 #define TARGET_SCHED_INIT sparc_sched_init
550 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
551 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
553 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
554 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
556 #undef TARGET_INIT_LIBFUNCS
557 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
558 #undef TARGET_INIT_BUILTINS
559 #define TARGET_INIT_BUILTINS sparc_init_builtins
561 #undef TARGET_LEGITIMIZE_ADDRESS
562 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
563 #undef TARGET_DELEGITIMIZE_ADDRESS
564 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
565 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
566 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
568 #undef TARGET_EXPAND_BUILTIN
569 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
570 #undef TARGET_FOLD_BUILTIN
571 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
574 #undef TARGET_HAVE_TLS
575 #define TARGET_HAVE_TLS true
578 #undef TARGET_CANNOT_FORCE_CONST_MEM
579 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
581 #undef TARGET_ASM_OUTPUT_MI_THUNK
582 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
583 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
584 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
586 #undef TARGET_MACHINE_DEPENDENT_REORG
587 #define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg
589 #undef TARGET_RTX_COSTS
590 #define TARGET_RTX_COSTS sparc_rtx_costs
591 #undef TARGET_ADDRESS_COST
592 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
593 #undef TARGET_REGISTER_MOVE_COST
594 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
596 #undef TARGET_PROMOTE_FUNCTION_MODE
597 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
599 #undef TARGET_FUNCTION_VALUE
600 #define TARGET_FUNCTION_VALUE sparc_function_value
601 #undef TARGET_LIBCALL_VALUE
602 #define TARGET_LIBCALL_VALUE sparc_libcall_value
603 #undef TARGET_FUNCTION_VALUE_REGNO_P
604 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
606 #undef TARGET_STRUCT_VALUE_RTX
607 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
608 #undef TARGET_RETURN_IN_MEMORY
609 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
610 #undef TARGET_MUST_PASS_IN_STACK
611 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
612 #undef TARGET_PASS_BY_REFERENCE
613 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
614 #undef TARGET_ARG_PARTIAL_BYTES
615 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
616 #undef TARGET_FUNCTION_ARG_ADVANCE
617 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
618 #undef TARGET_FUNCTION_ARG
619 #define TARGET_FUNCTION_ARG sparc_function_arg
620 #undef TARGET_FUNCTION_INCOMING_ARG
621 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
622 #undef TARGET_FUNCTION_ARG_BOUNDARY
623 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
625 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
626 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
627 #undef TARGET_STRICT_ARGUMENT_NAMING
628 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
630 #undef TARGET_EXPAND_BUILTIN_VA_START
631 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
632 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
633 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
635 #undef TARGET_VECTOR_MODE_SUPPORTED_P
636 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
638 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
639 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
641 #ifdef SUBTARGET_INSERT_ATTRIBUTES
642 #undef TARGET_INSERT_ATTRIBUTES
643 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
646 #ifdef SUBTARGET_ATTRIBUTE_TABLE
647 #undef TARGET_ATTRIBUTE_TABLE
648 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
651 #undef TARGET_RELAXED_ORDERING
652 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
654 #undef TARGET_OPTION_OVERRIDE
655 #define TARGET_OPTION_OVERRIDE sparc_option_override
657 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
658 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
659 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
662 #undef TARGET_ASM_FILE_END
663 #define TARGET_ASM_FILE_END sparc_file_end
665 #undef TARGET_FRAME_POINTER_REQUIRED
666 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
668 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
669 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
671 #undef TARGET_CAN_ELIMINATE
672 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
674 #undef TARGET_PREFERRED_RELOAD_CLASS
675 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
677 #undef TARGET_CONDITIONAL_REGISTER_USAGE
678 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
680 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
681 #undef TARGET_MANGLE_TYPE
682 #define TARGET_MANGLE_TYPE sparc_mangle_type
685 #undef TARGET_LEGITIMATE_ADDRESS_P
686 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
688 #undef TARGET_LEGITIMATE_CONSTANT_P
689 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
691 #undef TARGET_TRAMPOLINE_INIT
692 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
694 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
695 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
696 #undef TARGET_PRINT_OPERAND
697 #define TARGET_PRINT_OPERAND sparc_print_operand
698 #undef TARGET_PRINT_OPERAND_ADDRESS
699 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
701 struct gcc_target targetm
= TARGET_INITIALIZER
;
703 /* Validate and override various options, and do some machine dependent
707 sparc_option_override (void)
709 static struct code_model
{
710 const char *const name
;
711 const enum cmodel value
;
712 } const cmodels
[] = {
714 { "medlow", CM_MEDLOW
},
715 { "medmid", CM_MEDMID
},
716 { "medany", CM_MEDANY
},
717 { "embmedany", CM_EMBMEDANY
},
718 { NULL
, (enum cmodel
) 0 }
720 const struct code_model
*cmodel
;
721 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
722 static struct cpu_default
{
724 const enum processor_type processor
;
725 } const cpu_default
[] = {
726 /* There must be one entry here for each TARGET_CPU value. */
727 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
728 { TARGET_CPU_v8
, PROCESSOR_V8
},
729 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
730 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
731 { TARGET_CPU_leon
, PROCESSOR_LEON
},
732 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
733 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
734 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
735 { TARGET_CPU_v9
, PROCESSOR_V9
},
736 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
737 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
738 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
739 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
740 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
741 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
744 const struct cpu_default
*def
;
745 /* Table of values for -m{cpu,tune}=. This must match the order of
746 the PROCESSOR_* enumeration. */
747 static struct cpu_table
{
750 } const cpu_table
[] = {
753 { MASK_ISA
, MASK_V8
},
754 /* TI TMS390Z55 supersparc */
755 { MASK_ISA
, MASK_V8
},
756 { MASK_ISA
, MASK_V8
|MASK_FPU
},
758 { MASK_ISA
, MASK_V8
|MASK_FPU
},
759 { MASK_ISA
, MASK_SPARCLITE
},
760 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
761 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
762 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
763 { MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
764 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
765 { MASK_ISA
, MASK_SPARCLET
},
767 { MASK_ISA
, MASK_SPARCLET
},
768 { MASK_ISA
, MASK_V9
},
769 /* UltraSPARC I, II, IIi */
771 /* Although insns using %y are deprecated, it is a clear win. */
772 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
774 /* ??? Check if %y issue still holds true. */
776 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
779 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
781 { MASK_ISA
, MASK_V9
|MASK_POPC
|MASK_VIS2
},
783 { MASK_ISA
, MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
785 { MASK_ISA
, MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
787 const struct cpu_table
*cpu
;
791 #ifdef SUBTARGET_OVERRIDE_OPTIONS
792 SUBTARGET_OVERRIDE_OPTIONS
;
795 #ifndef SPARC_BI_ARCH
796 /* Check for unsupported architecture size. */
797 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
798 error ("%s is not supported by this configuration",
799 DEFAULT_ARCH32_P
? "-m64" : "-m32");
802 /* We force all 64bit archs to use 128 bit long double */
803 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
805 error ("-mlong-double-64 not allowed with -m64");
806 target_flags
|= MASK_LONG_DOUBLE_128
;
809 /* Code model selection. */
810 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
814 sparc_cmodel
= CM_32
;
817 if (sparc_cmodel_string
!= NULL
)
821 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
822 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
824 if (cmodel
->name
== NULL
)
825 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
827 sparc_cmodel
= cmodel
->value
;
830 error ("-mcmodel= is not supported on 32 bit systems");
833 /* Check that -fcall-saved-REG wasn't specified for out registers. */
834 for (i
= 8; i
< 16; i
++)
835 if (!call_used_regs
[i
])
837 error ("-fcall-saved-REG is not supported for out registers");
838 call_used_regs
[i
] = 1;
841 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
843 /* Set the default CPU. */
844 if (!global_options_set
.x_sparc_cpu_and_features
)
846 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
847 if (def
->cpu
== TARGET_CPU_DEFAULT
)
849 gcc_assert (def
->cpu
!= -1);
850 sparc_cpu_and_features
= def
->processor
;
852 if (!global_options_set
.x_sparc_cpu
)
853 sparc_cpu
= sparc_cpu_and_features
;
855 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
856 target_flags
&= ~cpu
->disable
;
857 target_flags
|= (cpu
->enable
858 #ifndef HAVE_AS_FMAF_HPC_VIS3
859 & ~(MASK_FMAF
| MASK_VIS3
)
863 /* If -mfpu or -mno-fpu was explicitly used, don't override with
864 the processor default. */
865 if (target_flags_explicit
& MASK_FPU
)
866 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
868 /* -mvis2 implies -mvis */
870 target_flags
|= MASK_VIS
;
872 /* -mvis3 implies -mvis2 and -mvis */
874 target_flags
|= MASK_VIS2
| MASK_VIS
;
876 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is disabled. */
878 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_FMAF
);
880 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
882 -m64 also implies v9. */
883 if (TARGET_VIS
|| TARGET_ARCH64
)
885 target_flags
|= MASK_V9
;
886 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
889 /* -mvis also implies -mv8plus on 32-bit */
890 if (TARGET_VIS
&& ! TARGET_ARCH64
)
891 target_flags
|= MASK_V8PLUS
;
893 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
894 if (TARGET_V9
&& TARGET_ARCH32
)
895 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
897 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
898 if (! TARGET_V9
|| TARGET_ARCH64
)
899 target_flags
&= ~MASK_V8PLUS
;
901 /* Don't use stack biasing in 32 bit mode. */
903 target_flags
&= ~MASK_STACK_BIAS
;
905 /* Supply a default value for align_functions. */
906 if (align_functions
== 0
907 && (sparc_cpu
== PROCESSOR_ULTRASPARC
908 || sparc_cpu
== PROCESSOR_ULTRASPARC3
909 || sparc_cpu
== PROCESSOR_NIAGARA
910 || sparc_cpu
== PROCESSOR_NIAGARA2
911 || sparc_cpu
== PROCESSOR_NIAGARA3
912 || sparc_cpu
== PROCESSOR_NIAGARA4
))
913 align_functions
= 32;
915 /* Validate PCC_STRUCT_RETURN. */
916 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
917 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
919 /* Only use .uaxword when compiling for a 64-bit target. */
921 targetm
.asm_out
.unaligned_op
.di
= NULL
;
923 /* Do various machine dependent initializations. */
926 /* Set up function hooks. */
927 init_machine_status
= sparc_init_machine_status
;
932 case PROCESSOR_CYPRESS
:
933 sparc_costs
= &cypress_costs
;
936 case PROCESSOR_SPARCLITE
:
937 case PROCESSOR_SUPERSPARC
:
938 sparc_costs
= &supersparc_costs
;
942 case PROCESSOR_HYPERSPARC
:
943 case PROCESSOR_SPARCLITE86X
:
944 sparc_costs
= &hypersparc_costs
;
947 sparc_costs
= &leon_costs
;
949 case PROCESSOR_SPARCLET
:
950 case PROCESSOR_TSC701
:
951 sparc_costs
= &sparclet_costs
;
954 case PROCESSOR_ULTRASPARC
:
955 sparc_costs
= &ultrasparc_costs
;
957 case PROCESSOR_ULTRASPARC3
:
958 sparc_costs
= &ultrasparc3_costs
;
960 case PROCESSOR_NIAGARA
:
961 sparc_costs
= &niagara_costs
;
963 case PROCESSOR_NIAGARA2
:
964 sparc_costs
= &niagara2_costs
;
966 case PROCESSOR_NIAGARA3
:
967 case PROCESSOR_NIAGARA4
:
968 sparc_costs
= &niagara3_costs
;
970 case PROCESSOR_NATIVE
:
974 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
975 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
976 target_flags
|= MASK_LONG_DOUBLE_128
;
979 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
980 ((sparc_cpu
== PROCESSOR_ULTRASPARC
981 || sparc_cpu
== PROCESSOR_NIAGARA
982 || sparc_cpu
== PROCESSOR_NIAGARA2
983 || sparc_cpu
== PROCESSOR_NIAGARA3
984 || sparc_cpu
== PROCESSOR_NIAGARA4
)
986 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
988 global_options
.x_param_values
,
989 global_options_set
.x_param_values
);
990 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
991 ((sparc_cpu
== PROCESSOR_ULTRASPARC
992 || sparc_cpu
== PROCESSOR_ULTRASPARC3
993 || sparc_cpu
== PROCESSOR_NIAGARA
994 || sparc_cpu
== PROCESSOR_NIAGARA2
995 || sparc_cpu
== PROCESSOR_NIAGARA3
996 || sparc_cpu
== PROCESSOR_NIAGARA4
)
998 global_options
.x_param_values
,
999 global_options_set
.x_param_values
);
1001 /* Disable save slot sharing for call-clobbered registers by default.
1002 The IRA sharing algorithm works on single registers only and this
1003 pessimizes for double floating-point registers. */
1004 if (!global_options_set
.x_flag_ira_share_save_slots
)
1005 flag_ira_share_save_slots
= 0;
1008 /* Miscellaneous utilities. */
1010 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1011 or branch on register contents instructions. */
1014 v9_regcmp_p (enum rtx_code code
)
1016 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1017 || code
== LE
|| code
== GT
);
1020 /* Nonzero if OP is a floating point constant which can
1021 be loaded into an integer register using a single
1022 sethi instruction. */
1027 if (GET_CODE (op
) == CONST_DOUBLE
)
1032 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1033 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1034 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1040 /* Nonzero if OP is a floating point constant which can
1041 be loaded into an integer register using a single
1047 if (GET_CODE (op
) == CONST_DOUBLE
)
1052 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1053 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1054 return SPARC_SIMM13_P (i
);
1060 /* Nonzero if OP is a floating point constant which can
1061 be loaded into an integer register using a high/losum
1062 instruction sequence. */
1065 fp_high_losum_p (rtx op
)
1067 /* The constraints calling this should only be in
1068 SFmode move insns, so any constant which cannot
1069 be moved using a single insn will do. */
1070 if (GET_CODE (op
) == CONST_DOUBLE
)
1075 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1076 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1077 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1083 /* Return true if the address of LABEL can be loaded by means of the
1084 mov{si,di}_pic_label_ref patterns in PIC mode. */
1087 can_use_mov_pic_label_ref (rtx label
)
1089 /* VxWorks does not impose a fixed gap between segments; the run-time
1090 gap can be different from the object-file gap. We therefore can't
1091 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1092 are absolutely sure that X is in the same segment as the GOT.
1093 Unfortunately, the flexibility of linker scripts means that we
1094 can't be sure of that in general, so assume that GOT-relative
1095 accesses are never valid on VxWorks. */
1096 if (TARGET_VXWORKS_RTP
)
1099 /* Similarly, if the label is non-local, it might end up being placed
1100 in a different section than the current one; now mov_pic_label_ref
1101 requires the label and the code to be in the same section. */
1102 if (LABEL_REF_NONLOCAL_P (label
))
1105 /* Finally, if we are reordering basic blocks and partition into hot
1106 and cold sections, this might happen for any label. */
1107 if (flag_reorder_blocks_and_partition
)
1113 /* Expand a move instruction. Return true if all work is done. */
1116 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
1118 /* Handle sets of MEM first. */
1119 if (GET_CODE (operands
[0]) == MEM
)
1121 /* 0 is a register (or a pair of registers) on SPARC. */
1122 if (register_or_zero_operand (operands
[1], mode
))
1125 if (!reload_in_progress
)
1127 operands
[0] = validize_mem (operands
[0]);
1128 operands
[1] = force_reg (mode
, operands
[1]);
1132 /* Fixup TLS cases. */
1134 && CONSTANT_P (operands
[1])
1135 && sparc_tls_referenced_p (operands
[1]))
1137 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1141 /* Fixup PIC cases. */
1142 if (flag_pic
&& CONSTANT_P (operands
[1]))
1144 if (pic_address_needs_scratch (operands
[1]))
1145 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1147 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1148 if (GET_CODE (operands
[1]) == LABEL_REF
1149 && can_use_mov_pic_label_ref (operands
[1]))
1153 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1159 gcc_assert (TARGET_ARCH64
);
1160 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1165 if (symbolic_operand (operands
[1], mode
))
1168 = sparc_legitimize_pic_address (operands
[1],
1170 ? operands
[0] : NULL_RTX
);
1175 /* If we are trying to toss an integer constant into FP registers,
1176 or loading a FP or vector constant, force it into memory. */
1177 if (CONSTANT_P (operands
[1])
1178 && REG_P (operands
[0])
1179 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1180 || SCALAR_FLOAT_MODE_P (mode
)
1181 || VECTOR_MODE_P (mode
)))
1183 /* emit_group_store will send such bogosity to us when it is
1184 not storing directly into memory. So fix this up to avoid
1185 crashes in output_constant_pool. */
1186 if (operands
[1] == const0_rtx
)
1187 operands
[1] = CONST0_RTX (mode
);
1189 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1190 always other regs. */
1191 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1192 && (const_zero_operand (operands
[1], mode
)
1193 || const_all_ones_operand (operands
[1], mode
)))
1196 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1197 /* We are able to build any SF constant in integer registers
1198 with at most 2 instructions. */
1200 /* And any DF constant in integer registers. */
1202 && (reload_completed
|| reload_in_progress
))))
1205 operands
[1] = force_const_mem (mode
, operands
[1]);
1206 if (!reload_in_progress
)
1207 operands
[1] = validize_mem (operands
[1]);
1211 /* Accept non-constants and valid constants unmodified. */
1212 if (!CONSTANT_P (operands
[1])
1213 || GET_CODE (operands
[1]) == HIGH
1214 || input_operand (operands
[1], mode
))
1220 /* All QImode constants require only one insn, so proceed. */
1225 sparc_emit_set_const32 (operands
[0], operands
[1]);
1229 /* input_operand should have filtered out 32-bit mode. */
1230 sparc_emit_set_const64 (operands
[0], operands
[1]);
1240 /* Load OP1, a 32-bit constant, into OP0, a register.
1241 We know it can't be done in one insn when we get
1242 here, the move expander guarantees this. */
1245 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1247 enum machine_mode mode
= GET_MODE (op0
);
1250 if (reload_in_progress
|| reload_completed
)
1253 temp
= gen_reg_rtx (mode
);
1255 if (GET_CODE (op1
) == CONST_INT
)
1257 gcc_assert (!small_int_operand (op1
, mode
)
1258 && !const_high_operand (op1
, mode
));
1260 /* Emit them as real moves instead of a HIGH/LO_SUM,
1261 this way CSE can see everything and reuse intermediate
1262 values if it wants. */
1263 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1264 GEN_INT (INTVAL (op1
)
1265 & ~(HOST_WIDE_INT
)0x3ff)));
1267 emit_insn (gen_rtx_SET (VOIDmode
,
1269 gen_rtx_IOR (mode
, temp
,
1270 GEN_INT (INTVAL (op1
) & 0x3ff))));
1274 /* A symbol, emit in the traditional way. */
1275 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1276 gen_rtx_HIGH (mode
, op1
)));
1277 emit_insn (gen_rtx_SET (VOIDmode
,
1278 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1282 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1283 If TEMP is nonzero, we are forbidden to use any other scratch
1284 registers. Otherwise, we are allowed to generate them as needed.
1286 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1287 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1290 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1292 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1295 if (temp
&& GET_MODE (temp
) == TImode
)
1298 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1301 /* SPARC-V9 code-model support. */
1302 switch (sparc_cmodel
)
1305 /* The range spanned by all instructions in the object is less
1306 than 2^31 bytes (2GB) and the distance from any instruction
1307 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1308 than 2^31 bytes (2GB).
1310 The executable must be in the low 4TB of the virtual address
1313 sethi %hi(symbol), %temp1
1314 or %temp1, %lo(symbol), %reg */
1316 temp1
= temp
; /* op0 is allowed. */
1318 temp1
= gen_reg_rtx (DImode
);
1320 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1321 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1325 /* The range spanned by all instructions in the object is less
1326 than 2^31 bytes (2GB) and the distance from any instruction
1327 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1328 than 2^31 bytes (2GB).
1330 The executable must be in the low 16TB of the virtual address
1333 sethi %h44(symbol), %temp1
1334 or %temp1, %m44(symbol), %temp2
1335 sllx %temp2, 12, %temp3
1336 or %temp3, %l44(symbol), %reg */
1341 temp3
= temp
; /* op0 is allowed. */
1345 temp1
= gen_reg_rtx (DImode
);
1346 temp2
= gen_reg_rtx (DImode
);
1347 temp3
= gen_reg_rtx (DImode
);
1350 emit_insn (gen_seth44 (temp1
, op1
));
1351 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1352 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1353 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1354 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1358 /* The range spanned by all instructions in the object is less
1359 than 2^31 bytes (2GB) and the distance from any instruction
1360 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1361 than 2^31 bytes (2GB).
1363 The executable can be placed anywhere in the virtual address
1366 sethi %hh(symbol), %temp1
1367 sethi %lm(symbol), %temp2
1368 or %temp1, %hm(symbol), %temp3
1369 sllx %temp3, 32, %temp4
1370 or %temp4, %temp2, %temp5
1371 or %temp5, %lo(symbol), %reg */
1374 /* It is possible that one of the registers we got for operands[2]
1375 might coincide with that of operands[0] (which is why we made
1376 it TImode). Pick the other one to use as our scratch. */
1377 if (rtx_equal_p (temp
, op0
))
1379 gcc_assert (ti_temp
);
1380 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1383 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1390 temp1
= gen_reg_rtx (DImode
);
1391 temp2
= gen_reg_rtx (DImode
);
1392 temp3
= gen_reg_rtx (DImode
);
1393 temp4
= gen_reg_rtx (DImode
);
1394 temp5
= gen_reg_rtx (DImode
);
1397 emit_insn (gen_sethh (temp1
, op1
));
1398 emit_insn (gen_setlm (temp2
, op1
));
1399 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1400 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1401 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1402 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1403 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1404 emit_insn (gen_setlo (op0
, temp5
, op1
));
1408 /* Old old old backwards compatibility kruft here.
1409 Essentially it is MEDLOW with a fixed 64-bit
1410 virtual base added to all data segment addresses.
1411 Text-segment stuff is computed like MEDANY, we can't
1412 reuse the code above because the relocation knobs
1415 Data segment: sethi %hi(symbol), %temp1
1416 add %temp1, EMBMEDANY_BASE_REG, %temp2
1417 or %temp2, %lo(symbol), %reg */
1418 if (data_segment_operand (op1
, GET_MODE (op1
)))
1422 temp1
= temp
; /* op0 is allowed. */
1427 temp1
= gen_reg_rtx (DImode
);
1428 temp2
= gen_reg_rtx (DImode
);
1431 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1432 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1433 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1436 /* Text segment: sethi %uhi(symbol), %temp1
1437 sethi %hi(symbol), %temp2
1438 or %temp1, %ulo(symbol), %temp3
1439 sllx %temp3, 32, %temp4
1440 or %temp4, %temp2, %temp5
1441 or %temp5, %lo(symbol), %reg */
1446 /* It is possible that one of the registers we got for operands[2]
1447 might coincide with that of operands[0] (which is why we made
1448 it TImode). Pick the other one to use as our scratch. */
1449 if (rtx_equal_p (temp
, op0
))
1451 gcc_assert (ti_temp
);
1452 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1455 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1462 temp1
= gen_reg_rtx (DImode
);
1463 temp2
= gen_reg_rtx (DImode
);
1464 temp3
= gen_reg_rtx (DImode
);
1465 temp4
= gen_reg_rtx (DImode
);
1466 temp5
= gen_reg_rtx (DImode
);
1469 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1470 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1471 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1472 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1473 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1474 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1475 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1476 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1485 #if HOST_BITS_PER_WIDE_INT == 32
1487 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1492 /* These avoid problems when cross compiling. If we do not
1493 go through all this hair then the optimizer will see
1494 invalid REG_EQUAL notes or in some cases none at all. */
1495 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1496 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1497 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1498 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1500 /* The optimizer is not to assume anything about exactly
1501 which bits are set for a HIGH, they are unspecified.
1502 Unfortunately this leads to many missed optimizations
1503 during CSE. We mask out the non-HIGH bits, and matches
1504 a plain movdi, to alleviate this problem. */
1506 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1508 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1512 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1514 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1518 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1520 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1524 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1526 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1529 /* Worker routines for 64-bit constant formation on arch64.
1530 One of the key things to be doing in these emissions is
1531 to create as many temp REGs as possible. This makes it
1532 possible for half-built constants to be used later when
1533 such values are similar to something required later on.
1534 Without doing this, the optimizer cannot see such
1537 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1538 unsigned HOST_WIDE_INT
, int);
1541 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1542 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1544 unsigned HOST_WIDE_INT high_bits
;
1547 high_bits
= (~low_bits
) & 0xffffffff;
1549 high_bits
= low_bits
;
1551 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1554 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1555 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1559 /* If we are XOR'ing with -1, then we should emit a one's complement
1560 instead. This way the combiner will notice logical operations
1561 such as ANDN later on and substitute. */
1562 if ((low_bits
& 0x3ff) == 0x3ff)
1564 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1565 gen_rtx_NOT (DImode
, temp
)));
1569 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1570 gen_safe_XOR64 (temp
,
1571 (-(HOST_WIDE_INT
)0x400
1572 | (low_bits
& 0x3ff)))));
1577 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1578 unsigned HOST_WIDE_INT
, int);
1581 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1582 unsigned HOST_WIDE_INT high_bits
,
1583 unsigned HOST_WIDE_INT low_immediate
,
1588 if ((high_bits
& 0xfffffc00) != 0)
1590 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1591 if ((high_bits
& ~0xfffffc00) != 0)
1592 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1593 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1599 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1603 /* Now shift it up into place. */
1604 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1605 gen_rtx_ASHIFT (DImode
, temp2
,
1606 GEN_INT (shift_count
))));
1608 /* If there is a low immediate part piece, finish up by
1609 putting that in as well. */
1610 if (low_immediate
!= 0)
1611 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1612 gen_safe_OR64 (op0
, low_immediate
)));
1615 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1616 unsigned HOST_WIDE_INT
);
1618 /* Full 64-bit constant decomposition. Even though this is the
1619 'worst' case, we still optimize a few things away. */
1621 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1622 unsigned HOST_WIDE_INT high_bits
,
1623 unsigned HOST_WIDE_INT low_bits
)
1627 if (reload_in_progress
|| reload_completed
)
1630 sub_temp
= gen_reg_rtx (DImode
);
1632 if ((high_bits
& 0xfffffc00) != 0)
1634 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1635 if ((high_bits
& ~0xfffffc00) != 0)
1636 emit_insn (gen_rtx_SET (VOIDmode
,
1638 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1644 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1648 if (!reload_in_progress
&& !reload_completed
)
1650 rtx temp2
= gen_reg_rtx (DImode
);
1651 rtx temp3
= gen_reg_rtx (DImode
);
1652 rtx temp4
= gen_reg_rtx (DImode
);
1654 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1655 gen_rtx_ASHIFT (DImode
, sub_temp
,
1658 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1659 if ((low_bits
& ~0xfffffc00) != 0)
1661 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1662 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1663 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1664 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1668 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1669 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1674 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1675 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1676 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1679 /* We are in the middle of reload, so this is really
1680 painful. However we do still make an attempt to
1681 avoid emitting truly stupid code. */
1682 if (low1
!= const0_rtx
)
1684 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1685 gen_rtx_ASHIFT (DImode
, sub_temp
,
1686 GEN_INT (to_shift
))));
1687 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1688 gen_rtx_IOR (DImode
, op0
, low1
)));
1696 if (low2
!= const0_rtx
)
1698 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1699 gen_rtx_ASHIFT (DImode
, sub_temp
,
1700 GEN_INT (to_shift
))));
1701 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1702 gen_rtx_IOR (DImode
, op0
, low2
)));
1710 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1711 gen_rtx_ASHIFT (DImode
, sub_temp
,
1712 GEN_INT (to_shift
))));
1713 if (low3
!= const0_rtx
)
1714 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1715 gen_rtx_IOR (DImode
, op0
, low3
)));
1720 /* Analyze a 64-bit constant for certain properties. */
1721 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1722 unsigned HOST_WIDE_INT
,
1723 int *, int *, int *);
1726 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1727 unsigned HOST_WIDE_INT low_bits
,
1728 int *hbsp
, int *lbsp
, int *abbasp
)
1730 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1733 lowest_bit_set
= highest_bit_set
= -1;
1737 if ((lowest_bit_set
== -1)
1738 && ((low_bits
>> i
) & 1))
1740 if ((highest_bit_set
== -1)
1741 && ((high_bits
>> (32 - i
- 1)) & 1))
1742 highest_bit_set
= (64 - i
- 1);
1745 && ((highest_bit_set
== -1)
1746 || (lowest_bit_set
== -1)));
1752 if ((lowest_bit_set
== -1)
1753 && ((high_bits
>> i
) & 1))
1754 lowest_bit_set
= i
+ 32;
1755 if ((highest_bit_set
== -1)
1756 && ((low_bits
>> (32 - i
- 1)) & 1))
1757 highest_bit_set
= 32 - i
- 1;
1760 && ((highest_bit_set
== -1)
1761 || (lowest_bit_set
== -1)));
1763 /* If there are no bits set this should have gone out
1764 as one instruction! */
1765 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
1766 all_bits_between_are_set
= 1;
1767 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1771 if ((low_bits
& (1 << i
)) != 0)
1776 if ((high_bits
& (1 << (i
- 32))) != 0)
1779 all_bits_between_are_set
= 0;
1782 *hbsp
= highest_bit_set
;
1783 *lbsp
= lowest_bit_set
;
1784 *abbasp
= all_bits_between_are_set
;
1787 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1790 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1791 unsigned HOST_WIDE_INT low_bits
)
1793 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1796 || high_bits
== 0xffffffff)
1799 analyze_64bit_constant (high_bits
, low_bits
,
1800 &highest_bit_set
, &lowest_bit_set
,
1801 &all_bits_between_are_set
);
1803 if ((highest_bit_set
== 63
1804 || lowest_bit_set
== 0)
1805 && all_bits_between_are_set
!= 0)
1808 if ((highest_bit_set
- lowest_bit_set
) < 21)
1814 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1815 unsigned HOST_WIDE_INT
,
1818 static unsigned HOST_WIDE_INT
1819 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1820 unsigned HOST_WIDE_INT low_bits
,
1821 int lowest_bit_set
, int shift
)
1823 HOST_WIDE_INT hi
, lo
;
1825 if (lowest_bit_set
< 32)
1827 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1828 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1833 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1835 gcc_assert (! (hi
& lo
));
1839 /* Here we are sure to be arch64 and this is an integer constant
1840 being loaded into a register. Emit the most efficient
1841 insn sequence possible. Detection of all the 1-insn cases
1842 has been done already. */
1844 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1846 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1847 int lowest_bit_set
, highest_bit_set
;
1848 int all_bits_between_are_set
;
1851 /* Sanity check that we know what we are working with. */
1852 gcc_assert (TARGET_ARCH64
1853 && (GET_CODE (op0
) == SUBREG
1854 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
1856 if (reload_in_progress
|| reload_completed
)
1859 if (GET_CODE (op1
) != CONST_INT
)
1861 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1866 temp
= gen_reg_rtx (DImode
);
1868 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1869 low_bits
= (INTVAL (op1
) & 0xffffffff);
1871 /* low_bits bits 0 --> 31
1872 high_bits bits 32 --> 63 */
1874 analyze_64bit_constant (high_bits
, low_bits
,
1875 &highest_bit_set
, &lowest_bit_set
,
1876 &all_bits_between_are_set
);
1878 /* First try for a 2-insn sequence. */
1880 /* These situations are preferred because the optimizer can
1881 * do more things with them:
1883 * sllx %reg, shift, %reg
1885 * srlx %reg, shift, %reg
1886 * 3) mov some_small_const, %reg
1887 * sllx %reg, shift, %reg
1889 if (((highest_bit_set
== 63
1890 || lowest_bit_set
== 0)
1891 && all_bits_between_are_set
!= 0)
1892 || ((highest_bit_set
- lowest_bit_set
) < 12))
1894 HOST_WIDE_INT the_const
= -1;
1895 int shift
= lowest_bit_set
;
1897 if ((highest_bit_set
!= 63
1898 && lowest_bit_set
!= 0)
1899 || all_bits_between_are_set
== 0)
1902 create_simple_focus_bits (high_bits
, low_bits
,
1905 else if (lowest_bit_set
== 0)
1906 shift
= -(63 - highest_bit_set
);
1908 gcc_assert (SPARC_SIMM13_P (the_const
));
1909 gcc_assert (shift
!= 0);
1911 emit_insn (gen_safe_SET64 (temp
, the_const
));
1913 emit_insn (gen_rtx_SET (VOIDmode
,
1915 gen_rtx_ASHIFT (DImode
,
1919 emit_insn (gen_rtx_SET (VOIDmode
,
1921 gen_rtx_LSHIFTRT (DImode
,
1923 GEN_INT (-shift
))));
1927 /* Now a range of 22 or less bits set somewhere.
1928 * 1) sethi %hi(focus_bits), %reg
1929 * sllx %reg, shift, %reg
1930 * 2) sethi %hi(focus_bits), %reg
1931 * srlx %reg, shift, %reg
1933 if ((highest_bit_set
- lowest_bit_set
) < 21)
1935 unsigned HOST_WIDE_INT focus_bits
=
1936 create_simple_focus_bits (high_bits
, low_bits
,
1937 lowest_bit_set
, 10);
1939 gcc_assert (SPARC_SETHI_P (focus_bits
));
1940 gcc_assert (lowest_bit_set
!= 10);
1942 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
1944 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1945 if (lowest_bit_set
< 10)
1946 emit_insn (gen_rtx_SET (VOIDmode
,
1948 gen_rtx_LSHIFTRT (DImode
, temp
,
1949 GEN_INT (10 - lowest_bit_set
))));
1950 else if (lowest_bit_set
> 10)
1951 emit_insn (gen_rtx_SET (VOIDmode
,
1953 gen_rtx_ASHIFT (DImode
, temp
,
1954 GEN_INT (lowest_bit_set
- 10))));
1958 /* 1) sethi %hi(low_bits), %reg
1959 * or %reg, %lo(low_bits), %reg
1960 * 2) sethi %hi(~low_bits), %reg
1961 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1964 || high_bits
== 0xffffffff)
1966 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1967 (high_bits
== 0xffffffff));
1971 /* Now, try 3-insn sequences. */
1973 /* 1) sethi %hi(high_bits), %reg
1974 * or %reg, %lo(high_bits), %reg
1975 * sllx %reg, 32, %reg
1979 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1983 /* We may be able to do something quick
1984 when the constant is negated, so try that. */
1985 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1986 (~low_bits
) & 0xfffffc00))
1988 /* NOTE: The trailing bits get XOR'd so we need the
1989 non-negated bits, not the negated ones. */
1990 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
1992 if ((((~high_bits
) & 0xffffffff) == 0
1993 && ((~low_bits
) & 0x80000000) == 0)
1994 || (((~high_bits
) & 0xffffffff) == 0xffffffff
1995 && ((~low_bits
) & 0x80000000) != 0))
1997 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
1999 if ((SPARC_SETHI_P (fast_int
)
2000 && (~high_bits
& 0xffffffff) == 0)
2001 || SPARC_SIMM13_P (fast_int
))
2002 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2004 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2009 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2010 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2011 sparc_emit_set_const64 (temp
, negated_const
);
2014 /* If we are XOR'ing with -1, then we should emit a one's complement
2015 instead. This way the combiner will notice logical operations
2016 such as ANDN later on and substitute. */
2017 if (trailing_bits
== 0x3ff)
2019 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2020 gen_rtx_NOT (DImode
, temp
)));
2024 emit_insn (gen_rtx_SET (VOIDmode
,
2026 gen_safe_XOR64 (temp
,
2027 (-0x400 | trailing_bits
))));
2032 /* 1) sethi %hi(xxx), %reg
2033 * or %reg, %lo(xxx), %reg
2034 * sllx %reg, yyy, %reg
2036 * ??? This is just a generalized version of the low_bits==0
2037 * thing above, FIXME...
2039 if ((highest_bit_set
- lowest_bit_set
) < 32)
2041 unsigned HOST_WIDE_INT focus_bits
=
2042 create_simple_focus_bits (high_bits
, low_bits
,
2045 /* We can't get here in this state. */
2046 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2048 /* So what we know is that the set bits straddle the
2049 middle of the 64-bit word. */
2050 sparc_emit_set_const64_quick2 (op0
, temp
,
2056 /* 1) sethi %hi(high_bits), %reg
2057 * or %reg, %lo(high_bits), %reg
2058 * sllx %reg, 32, %reg
2059 * or %reg, low_bits, %reg
2061 if (SPARC_SIMM13_P(low_bits
)
2062 && ((int)low_bits
> 0))
2064 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2068 /* The easiest way when all else fails, is full decomposition. */
2069 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2071 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2073 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2074 return the mode to be used for the comparison. For floating-point,
2075 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2076 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2077 processing is needed. */
2080 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2082 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2108 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2109 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2111 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2112 return CCX_NOOVmode
;
2118 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2125 /* Emit the compare insn and return the CC reg for a CODE comparison
2126 with operands X and Y. */
2129 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2131 enum machine_mode mode
;
2134 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2137 mode
= SELECT_CC_MODE (code
, x
, y
);
2139 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2140 fcc regs (cse can't tell they're really call clobbered regs and will
2141 remove a duplicate comparison even if there is an intervening function
2142 call - it will then try to reload the cc reg via an int reg which is why
2143 we need the movcc patterns). It is possible to provide the movcc
2144 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2145 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2146 to tell cse that CCFPE mode registers (even pseudos) are call
2149 /* ??? This is an experiment. Rather than making changes to cse which may
2150 or may not be easy/clean, we do our own cse. This is possible because
2151 we will generate hard registers. Cse knows they're call clobbered (it
2152 doesn't know the same thing about pseudos). If we guess wrong, no big
2153 deal, but if we win, great! */
2155 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2156 #if 1 /* experiment */
2159 /* We cycle through the registers to ensure they're all exercised. */
2160 static int next_fcc_reg
= 0;
2161 /* Previous x,y for each fcc reg. */
2162 static rtx prev_args
[4][2];
2164 /* Scan prev_args for x,y. */
2165 for (reg
= 0; reg
< 4; reg
++)
2166 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2171 prev_args
[reg
][0] = x
;
2172 prev_args
[reg
][1] = y
;
2173 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2175 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2178 cc_reg
= gen_reg_rtx (mode
);
2179 #endif /* ! experiment */
2180 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2181 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2183 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2185 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2186 will only result in an unrecognizable insn so no point in asserting. */
2187 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2193 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2196 gen_compare_reg (rtx cmp
)
2198 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2201 /* This function is used for v9 only.
2202 DEST is the target of the Scc insn.
2203 CODE is the code for an Scc's comparison.
2204 X and Y are the values we compare.
2206 This function is needed to turn
2209 (gt (reg:CCX 100 %icc)
2213 (gt:DI (reg:CCX 100 %icc)
2216 IE: The instruction recognizer needs to see the mode of the comparison to
2217 find the right instruction. We could use "gt:DI" right in the
2218 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2221 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2224 && (GET_MODE (x
) == DImode
2225 || GET_MODE (dest
) == DImode
))
2228 /* Try to use the movrCC insns. */
2230 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2232 && v9_regcmp_p (compare_code
))
2237 /* Special case for op0 != 0. This can be done with one instruction if
2240 if (compare_code
== NE
2241 && GET_MODE (dest
) == DImode
2242 && rtx_equal_p (op0
, dest
))
2244 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2245 gen_rtx_IF_THEN_ELSE (DImode
,
2246 gen_rtx_fmt_ee (compare_code
, DImode
,
2253 if (reg_overlap_mentioned_p (dest
, op0
))
2255 /* Handle the case where dest == x.
2256 We "early clobber" the result. */
2257 op0
= gen_reg_rtx (GET_MODE (x
));
2258 emit_move_insn (op0
, x
);
2261 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2262 if (GET_MODE (op0
) != DImode
)
2264 temp
= gen_reg_rtx (DImode
);
2265 convert_move (temp
, op0
, 0);
2269 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2270 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2271 gen_rtx_fmt_ee (compare_code
, DImode
,
2279 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2282 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2283 && GET_MODE (x
) != CCX_NOOVmode
);
2285 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2286 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2287 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2288 gen_rtx_fmt_ee (compare_code
,
2289 GET_MODE (x
), x
, y
),
2290 const1_rtx
, dest
)));
2296 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2297 without jumps using the addx/subx instructions. */
2300 emit_scc_insn (rtx operands
[])
2307 /* The quad-word fp compare library routines all return nonzero to indicate
2308 true, which is different from the equivalent libgcc routines, so we must
2309 handle them specially here. */
2310 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2312 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2313 GET_CODE (operands
[1]));
2314 operands
[2] = XEXP (operands
[1], 0);
2315 operands
[3] = XEXP (operands
[1], 1);
2318 code
= GET_CODE (operands
[1]);
2322 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2323 more applications). The exception to this is "reg != 0" which can
2324 be done in one instruction on v9 (so we do it). */
2327 if (GET_MODE (x
) == SImode
)
2329 rtx pat
= gen_seqsi_special (operands
[0], x
, y
);
2333 else if (GET_MODE (x
) == DImode
)
2335 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2343 if (GET_MODE (x
) == SImode
)
2345 rtx pat
= gen_snesi_special (operands
[0], x
, y
);
2349 else if (GET_MODE (x
) == DImode
)
2351 rtx pat
= gen_snedi_special (operands
[0], x
, y
);
2357 /* For the rest, on v9 we can use conditional moves. */
2361 if (gen_v9_scc (operands
[0], code
, x
, y
))
2365 /* We can do LTU and GEU using the addx/subx instructions too. And
2366 for GTU/LEU, if both operands are registers swap them and fall
2367 back to the easy case. */
2368 if (code
== GTU
|| code
== LEU
)
2370 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2371 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
2376 code
= swap_condition (code
);
2380 if (code
== LTU
|| code
== GEU
)
2382 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2383 gen_rtx_fmt_ee (code
, SImode
,
2384 gen_compare_reg_1 (code
, x
, y
),
2389 /* Nope, do branches. */
2393 /* Emit a conditional jump insn for the v9 architecture using comparison code
2394 CODE and jump target LABEL.
2395 This function exists to take advantage of the v9 brxx insns. */
2398 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2400 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2402 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2403 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2405 gen_rtx_LABEL_REF (VOIDmode
, label
),
2410 emit_conditional_branch_insn (rtx operands
[])
2412 /* The quad-word fp compare library routines all return nonzero to indicate
2413 true, which is different from the equivalent libgcc routines, so we must
2414 handle them specially here. */
2415 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
2417 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
2418 GET_CODE (operands
[0]));
2419 operands
[1] = XEXP (operands
[0], 0);
2420 operands
[2] = XEXP (operands
[0], 1);
2423 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
2424 && GET_CODE (operands
[1]) == REG
2425 && GET_MODE (operands
[1]) == DImode
)
2427 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
2431 operands
[1] = gen_compare_reg (operands
[0]);
2432 operands
[2] = const0_rtx
;
2433 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
2434 operands
[1], operands
[2]);
2435 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
2440 /* Generate a DFmode part of a hard TFmode register.
2441 REG is the TFmode hard register, LOW is 1 for the
2442 low 64bit of the register and 0 otherwise.
2445 gen_df_reg (rtx reg
, int low
)
2447 int regno
= REGNO (reg
);
2449 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2450 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2451 return gen_rtx_REG (DFmode
, regno
);
2454 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2455 Unlike normal calls, TFmode operands are passed by reference. It is
2456 assumed that no more than 3 operands are required. */
2459 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2461 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2464 /* We only expect to be called for conversions, unary, and binary ops. */
2465 gcc_assert (nargs
== 2 || nargs
== 3);
2467 for (i
= 0; i
< nargs
; ++i
)
2469 rtx this_arg
= operands
[i
];
2472 /* TFmode arguments and return values are passed by reference. */
2473 if (GET_MODE (this_arg
) == TFmode
)
2475 int force_stack_temp
;
2477 force_stack_temp
= 0;
2478 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2479 force_stack_temp
= 1;
2481 if (GET_CODE (this_arg
) == MEM
2482 && ! force_stack_temp
)
2483 this_arg
= XEXP (this_arg
, 0);
2484 else if (CONSTANT_P (this_arg
)
2485 && ! force_stack_temp
)
2487 this_slot
= force_const_mem (TFmode
, this_arg
);
2488 this_arg
= XEXP (this_slot
, 0);
2492 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2494 /* Operand 0 is the return value. We'll copy it out later. */
2496 emit_move_insn (this_slot
, this_arg
);
2498 ret_slot
= this_slot
;
2500 this_arg
= XEXP (this_slot
, 0);
2507 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2509 if (GET_MODE (operands
[0]) == TFmode
)
2512 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2513 arg
[0], GET_MODE (arg
[0]),
2514 arg
[1], GET_MODE (arg
[1]));
2516 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2517 arg
[0], GET_MODE (arg
[0]),
2518 arg
[1], GET_MODE (arg
[1]),
2519 arg
[2], GET_MODE (arg
[2]));
2522 emit_move_insn (operands
[0], ret_slot
);
2528 gcc_assert (nargs
== 2);
2530 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2531 GET_MODE (operands
[0]), 1,
2532 arg
[1], GET_MODE (arg
[1]));
2534 if (ret
!= operands
[0])
2535 emit_move_insn (operands
[0], ret
);
2539 /* Expand soft-float TFmode calls to sparc abi routines. */
2542 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2564 emit_soft_tfmode_libcall (func
, 3, operands
);
2568 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2572 gcc_assert (code
== SQRT
);
2575 emit_soft_tfmode_libcall (func
, 2, operands
);
2579 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2586 switch (GET_MODE (operands
[1]))
2599 case FLOAT_TRUNCATE
:
2600 switch (GET_MODE (operands
[0]))
2614 switch (GET_MODE (operands
[1]))
2619 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
2629 case UNSIGNED_FLOAT
:
2630 switch (GET_MODE (operands
[1]))
2635 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
2646 switch (GET_MODE (operands
[0]))
2660 switch (GET_MODE (operands
[0]))
2677 emit_soft_tfmode_libcall (func
, 2, operands
);
2680 /* Expand a hard-float tfmode operation. All arguments must be in
2684 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2688 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2690 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2691 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2695 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2696 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2697 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2698 operands
[1], operands
[2]);
2701 if (register_operand (operands
[0], VOIDmode
))
2704 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2706 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2708 if (dest
!= operands
[0])
2709 emit_move_insn (operands
[0], dest
);
2713 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2715 if (TARGET_HARD_QUAD
)
2716 emit_hard_tfmode_operation (code
, operands
);
2718 emit_soft_tfmode_binop (code
, operands
);
2722 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2724 if (TARGET_HARD_QUAD
)
2725 emit_hard_tfmode_operation (code
, operands
);
2727 emit_soft_tfmode_unop (code
, operands
);
2731 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2733 if (TARGET_HARD_QUAD
)
2734 emit_hard_tfmode_operation (code
, operands
);
2736 emit_soft_tfmode_cvt (code
, operands
);
2739 /* Return nonzero if a branch/jump/call instruction will be emitting
2740 nop into its delay slot. */
2743 empty_delay_slot (rtx insn
)
2747 /* If no previous instruction (should not happen), return true. */
2748 if (PREV_INSN (insn
) == NULL
)
2751 seq
= NEXT_INSN (PREV_INSN (insn
));
2752 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2758 /* Return nonzero if TRIAL can go into the call delay slot. */
2761 tls_call_delay (rtx trial
)
2766 call __tls_get_addr, %tgd_call (foo)
2767 add %l7, %o0, %o0, %tgd_add (foo)
2768 while Sun as/ld does not. */
2769 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2772 pat
= PATTERN (trial
);
2774 /* We must reject tgd_add{32|64}, i.e.
2775 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2776 and tldm_add{32|64}, i.e.
2777 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2779 if (GET_CODE (pat
) == SET
2780 && GET_CODE (SET_SRC (pat
)) == PLUS
)
2782 rtx unspec
= XEXP (SET_SRC (pat
), 1);
2784 if (GET_CODE (unspec
) == UNSPEC
2785 && (XINT (unspec
, 1) == UNSPEC_TLSGD
2786 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
2793 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2794 instruction. RETURN_P is true if the v9 variant 'return' is to be
2795 considered in the test too.
2797 TRIAL must be a SET whose destination is a REG appropriate for the
2798 'restore' instruction or, if RETURN_P is true, for the 'return'
2802 eligible_for_restore_insn (rtx trial
, bool return_p
)
2804 rtx pat
= PATTERN (trial
);
2805 rtx src
= SET_SRC (pat
);
2807 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2808 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2809 && arith_operand (src
, GET_MODE (src
)))
2812 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2814 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2817 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2818 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2819 && arith_double_operand (src
, GET_MODE (src
)))
2820 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2822 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2823 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
2826 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2827 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
2830 /* If we have the 'return' instruction, anything that does not use
2831 local or output registers and can go into a delay slot wins. */
2834 && !epilogue_renumber (&pat
, 1)
2835 && get_attr_in_uncond_branch_delay (trial
)
2836 == IN_UNCOND_BRANCH_DELAY_TRUE
)
2839 /* The 'restore src1,src2,dest' pattern for SImode. */
2840 else if (GET_CODE (src
) == PLUS
2841 && register_operand (XEXP (src
, 0), SImode
)
2842 && arith_operand (XEXP (src
, 1), SImode
))
2845 /* The 'restore src1,src2,dest' pattern for DImode. */
2846 else if (GET_CODE (src
) == PLUS
2847 && register_operand (XEXP (src
, 0), DImode
)
2848 && arith_double_operand (XEXP (src
, 1), DImode
))
2851 /* The 'restore src1,%lo(src2),dest' pattern. */
2852 else if (GET_CODE (src
) == LO_SUM
2853 && ! TARGET_CM_MEDMID
2854 && ((register_operand (XEXP (src
, 0), SImode
)
2855 && immediate_operand (XEXP (src
, 1), SImode
))
2857 && register_operand (XEXP (src
, 0), DImode
)
2858 && immediate_operand (XEXP (src
, 1), DImode
))))
2861 /* The 'restore src,src,dest' pattern. */
2862 else if (GET_CODE (src
) == ASHIFT
2863 && (register_operand (XEXP (src
, 0), SImode
)
2864 || register_operand (XEXP (src
, 0), DImode
))
2865 && XEXP (src
, 1) == const1_rtx
)
2871 /* Return nonzero if TRIAL can go into the function return's delay slot. */
2874 eligible_for_return_delay (rtx trial
)
2879 if (GET_CODE (trial
) != INSN
)
2882 if (get_attr_length (trial
) != 1)
2885 /* If the function uses __builtin_eh_return, the eh_return machinery
2886 occupies the delay slot. */
2887 if (crtl
->calls_eh_return
)
2890 /* In the case of a leaf or flat function, anything can go into the slot. */
2891 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2893 get_attr_in_uncond_branch_delay (trial
) == IN_UNCOND_BRANCH_DELAY_TRUE
;
2895 pat
= PATTERN (trial
);
2896 if (GET_CODE (pat
) == PARALLEL
)
2902 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
2904 rtx expr
= XVECEXP (pat
, 0, i
);
2905 if (GET_CODE (expr
) != SET
)
2907 if (GET_CODE (SET_DEST (expr
)) != REG
)
2909 regno
= REGNO (SET_DEST (expr
));
2910 if (regno
>= 8 && regno
< 24)
2913 return !epilogue_renumber (&pat
, 1)
2914 && (get_attr_in_uncond_branch_delay (trial
)
2915 == IN_UNCOND_BRANCH_DELAY_TRUE
);
2918 if (GET_CODE (pat
) != SET
)
2921 if (GET_CODE (SET_DEST (pat
)) != REG
)
2924 regno
= REGNO (SET_DEST (pat
));
2926 /* Otherwise, only operations which can be done in tandem with
2927 a `restore' or `return' insn can go into the delay slot. */
2928 if (regno
>= 8 && regno
< 24)
2931 /* If this instruction sets up floating point register and we have a return
2932 instruction, it can probably go in. But restore will not work
2936 && !epilogue_renumber (&pat
, 1)
2937 && get_attr_in_uncond_branch_delay (trial
)
2938 == IN_UNCOND_BRANCH_DELAY_TRUE
);
2940 return eligible_for_restore_insn (trial
, true);
2943 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
2946 eligible_for_sibcall_delay (rtx trial
)
2950 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2953 if (get_attr_length (trial
) != 1)
2956 pat
= PATTERN (trial
);
2958 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2960 /* If the tail call is done using the call instruction,
2961 we have to restore %o7 in the delay slot. */
2962 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
2965 /* %g1 is used to build the function address */
2966 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2972 /* Otherwise, only operations which can be done in tandem with
2973 a `restore' insn can go into the delay slot. */
2974 if (GET_CODE (SET_DEST (pat
)) != REG
2975 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
2976 || REGNO (SET_DEST (pat
)) >= 32)
2979 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2981 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2984 return eligible_for_restore_insn (trial
, false);
2988 short_branch (int uid1
, int uid2
)
2990 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
2992 /* Leave a few words of "slop". */
2993 if (delta
>= -1023 && delta
<= 1022)
2999 /* Return nonzero if REG is not used after INSN.
3000 We assume REG is a reload reg, and therefore does
3001 not live past labels or calls or jumps. */
3003 reg_unused_after (rtx reg
, rtx insn
)
3005 enum rtx_code code
, prev_code
= UNKNOWN
;
3007 while ((insn
= NEXT_INSN (insn
)))
3009 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
3012 code
= GET_CODE (insn
);
3013 if (GET_CODE (insn
) == CODE_LABEL
)
3018 rtx set
= single_set (insn
);
3019 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
3022 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
3024 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
3032 /* Determine if it's legal to put X into the constant pool. This
3033 is not possible if X contains the address of a symbol that is
3034 not constant (TLS) or not known at final link time (PIC). */
3037 sparc_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
3039 switch (GET_CODE (x
))
3044 /* Accept all non-symbolic constants. */
3048 /* Labels are OK iff we are non-PIC. */
3049 return flag_pic
!= 0;
3052 /* 'Naked' TLS symbol references are never OK,
3053 non-TLS symbols are OK iff we are non-PIC. */
3054 if (SYMBOL_REF_TLS_MODEL (x
))
3057 return flag_pic
!= 0;
3060 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3063 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3064 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3072 /* Global Offset Table support. */
3073 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3074 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3076 /* Return the SYMBOL_REF for the Global Offset Table. */
3078 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3083 if (!sparc_got_symbol
)
3084 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3086 return sparc_got_symbol
;
3089 /* Ensure that we are not using patterns that are not OK with PIC. */
3099 op
= recog_data
.operand
[i
];
3100 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3101 && (GET_CODE (op
) != CONST
3102 || (GET_CODE (XEXP (op
, 0)) == MINUS
3103 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3104 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3111 /* Return true if X is an address which needs a temporary register when
3112 reloaded while generating PIC code. */
3115 pic_address_needs_scratch (rtx x
)
3117 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3118 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3119 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3120 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3121 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3127 /* Determine if a given RTX is a valid constant. We already know this
3128 satisfies CONSTANT_P. */
3131 sparc_legitimate_constant_p (enum machine_mode mode
, rtx x
)
3133 switch (GET_CODE (x
))
3137 if (sparc_tls_referenced_p (x
))
3142 if (GET_MODE (x
) == VOIDmode
)
3145 /* Floating point constants are generally not ok.
3146 The only exception is 0.0 and all-ones in VIS. */
3148 && SCALAR_FLOAT_MODE_P (mode
)
3149 && (const_zero_operand (x
, mode
)
3150 || const_all_ones_operand (x
, mode
)))
3156 /* Vector constants are generally not ok.
3157 The only exception is 0 or -1 in VIS. */
3159 && (const_zero_operand (x
, mode
)
3160 || const_all_ones_operand (x
, mode
)))
3172 /* Determine if a given RTX is a valid constant address. */
3175 constant_address_p (rtx x
)
3177 switch (GET_CODE (x
))
3185 if (flag_pic
&& pic_address_needs_scratch (x
))
3187 return sparc_legitimate_constant_p (Pmode
, x
);
3190 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3197 /* Nonzero if the constant value X is a legitimate general operand
3198 when generating PIC code. It is given that flag_pic is on and
3199 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3202 legitimate_pic_operand_p (rtx x
)
3204 if (pic_address_needs_scratch (x
))
3206 if (sparc_tls_referenced_p (x
))
3211 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3213 && INTVAL (X) >= -0x1000 \
3214 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3216 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3218 && INTVAL (X) >= -0x1000 \
3219 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3221 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3223 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3224 ordinarily. This changes a bit when generating PIC. */
3227 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3229 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3231 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3233 else if (GET_CODE (addr
) == PLUS
)
3235 rs1
= XEXP (addr
, 0);
3236 rs2
= XEXP (addr
, 1);
3238 /* Canonicalize. REG comes first, if there are no regs,
3239 LO_SUM comes first. */
3241 && GET_CODE (rs1
) != SUBREG
3243 || GET_CODE (rs2
) == SUBREG
3244 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3246 rs1
= XEXP (addr
, 1);
3247 rs2
= XEXP (addr
, 0);
3251 && rs1
== pic_offset_table_rtx
3253 && GET_CODE (rs2
) != SUBREG
3254 && GET_CODE (rs2
) != LO_SUM
3255 && GET_CODE (rs2
) != MEM
3256 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3257 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3258 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3260 || GET_CODE (rs1
) == SUBREG
)
3261 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3266 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3267 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3269 /* We prohibit REG + REG for TFmode when there are no quad move insns
3270 and we consequently need to split. We do this because REG+REG
3271 is not an offsettable address. If we get the situation in reload
3272 where source and destination of a movtf pattern are both MEMs with
3273 REG+REG address, then only one of them gets converted to an
3274 offsettable address. */
3276 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3279 /* We prohibit REG + REG on ARCH32 if not optimizing for
3280 DFmode/DImode because then mem_min_alignment is likely to be zero
3281 after reload and the forced split would lack a matching splitter
3283 if (TARGET_ARCH32
&& !optimize
3284 && (mode
== DFmode
|| mode
== DImode
))
3287 else if (USE_AS_OFFSETABLE_LO10
3288 && GET_CODE (rs1
) == LO_SUM
3290 && ! TARGET_CM_MEDMID
3291 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
3294 imm1
= XEXP (rs1
, 1);
3295 rs1
= XEXP (rs1
, 0);
3296 if (!CONSTANT_P (imm1
)
3297 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3301 else if (GET_CODE (addr
) == LO_SUM
)
3303 rs1
= XEXP (addr
, 0);
3304 imm1
= XEXP (addr
, 1);
3306 if (!CONSTANT_P (imm1
)
3307 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3310 /* We can't allow TFmode in 32-bit mode, because an offset greater
3311 than the alignment (8) may cause the LO_SUM to overflow. */
3312 if (mode
== TFmode
&& TARGET_ARCH32
)
3315 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3320 if (GET_CODE (rs1
) == SUBREG
)
3321 rs1
= SUBREG_REG (rs1
);
3327 if (GET_CODE (rs2
) == SUBREG
)
3328 rs2
= SUBREG_REG (rs2
);
3335 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3336 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3341 if ((REGNO (rs1
) >= 32
3342 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3343 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3345 && (REGNO (rs2
) >= 32
3346 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3347 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3353 /* Return the SYMBOL_REF for the tls_get_addr function. */
3355 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
3358 sparc_tls_get_addr (void)
3360 if (!sparc_tls_symbol
)
3361 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3363 return sparc_tls_symbol
;
3366 /* Return the Global Offset Table to be used in TLS mode. */
3369 sparc_tls_got (void)
3371 /* In PIC mode, this is just the PIC offset table. */
3374 crtl
->uses_pic_offset_table
= 1;
3375 return pic_offset_table_rtx
;
3378 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3379 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3380 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
3382 load_got_register ();
3383 return global_offset_table_rtx
;
3386 /* In all other cases, we load a new pseudo with the GOT symbol. */
3387 return copy_to_reg (sparc_got ());
3390 /* Return true if X contains a thread-local symbol. */
3393 sparc_tls_referenced_p (rtx x
)
3395 if (!TARGET_HAVE_TLS
)
3398 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3399 x
= XEXP (XEXP (x
, 0), 0);
3401 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
3404 /* That's all we handle in sparc_legitimize_tls_address for now. */
3408 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3409 this (thread-local) address. */
3412 sparc_legitimize_tls_address (rtx addr
)
3414 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3416 gcc_assert (can_create_pseudo_p ());
3418 if (GET_CODE (addr
) == SYMBOL_REF
)
3419 switch (SYMBOL_REF_TLS_MODEL (addr
))
3421 case TLS_MODEL_GLOBAL_DYNAMIC
:
3423 temp1
= gen_reg_rtx (SImode
);
3424 temp2
= gen_reg_rtx (SImode
);
3425 ret
= gen_reg_rtx (Pmode
);
3426 o0
= gen_rtx_REG (Pmode
, 8);
3427 got
= sparc_tls_got ();
3428 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3429 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3432 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3433 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3438 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3439 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3442 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3443 insn
= get_insns ();
3445 emit_libcall_block (insn
, ret
, o0
, addr
);
3448 case TLS_MODEL_LOCAL_DYNAMIC
:
3450 temp1
= gen_reg_rtx (SImode
);
3451 temp2
= gen_reg_rtx (SImode
);
3452 temp3
= gen_reg_rtx (Pmode
);
3453 ret
= gen_reg_rtx (Pmode
);
3454 o0
= gen_rtx_REG (Pmode
, 8);
3455 got
= sparc_tls_got ();
3456 emit_insn (gen_tldm_hi22 (temp1
));
3457 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3460 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3461 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3466 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3467 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3470 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3471 insn
= get_insns ();
3473 emit_libcall_block (insn
, temp3
, o0
,
3474 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3475 UNSPEC_TLSLD_BASE
));
3476 temp1
= gen_reg_rtx (SImode
);
3477 temp2
= gen_reg_rtx (SImode
);
3478 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3479 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3481 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3483 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3486 case TLS_MODEL_INITIAL_EXEC
:
3487 temp1
= gen_reg_rtx (SImode
);
3488 temp2
= gen_reg_rtx (SImode
);
3489 temp3
= gen_reg_rtx (Pmode
);
3490 got
= sparc_tls_got ();
3491 emit_insn (gen_tie_hi22 (temp1
, addr
));
3492 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3494 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3496 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3499 ret
= gen_reg_rtx (Pmode
);
3501 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3504 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3508 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3511 case TLS_MODEL_LOCAL_EXEC
:
3512 temp1
= gen_reg_rtx (Pmode
);
3513 temp2
= gen_reg_rtx (Pmode
);
3516 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3517 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3521 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3522 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3524 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3531 else if (GET_CODE (addr
) == CONST
)
3535 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
3537 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
3538 offset
= XEXP (XEXP (addr
, 0), 1);
3540 base
= force_operand (base
, NULL_RTX
);
3541 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
3542 offset
= force_reg (Pmode
, offset
);
3543 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
3547 gcc_unreachable (); /* for now ... */
3552 /* Legitimize PIC addresses. If the address is already position-independent,
3553 we return ORIG. Newly generated position-independent addresses go into a
3554 reg. This is REG if nonzero, otherwise we allocate register(s) as
3558 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
3560 bool gotdata_op
= false;
3562 if (GET_CODE (orig
) == SYMBOL_REF
3563 /* See the comment in sparc_expand_move. */
3564 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
3566 rtx pic_ref
, address
;
3571 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3572 reg
= gen_reg_rtx (Pmode
);
3577 /* If not during reload, allocate another temp reg here for loading
3578 in the address, so that these instructions can be optimized
3580 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3581 ? reg
: gen_reg_rtx (Pmode
));
3583 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3584 won't get confused into thinking that these two instructions
3585 are loading in the true address of the symbol. If in the
3586 future a PIC rtx exists, that should be used instead. */
3589 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3590 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3594 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3595 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3603 crtl
->uses_pic_offset_table
= 1;
3607 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
3608 pic_offset_table_rtx
,
3611 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
3612 pic_offset_table_rtx
,
3618 = gen_const_mem (Pmode
,
3619 gen_rtx_PLUS (Pmode
,
3620 pic_offset_table_rtx
, address
));
3621 insn
= emit_move_insn (reg
, pic_ref
);
3624 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3626 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3629 else if (GET_CODE (orig
) == CONST
)
3633 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3634 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3639 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3640 reg
= gen_reg_rtx (Pmode
);
3643 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3644 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
3645 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
3646 base
== reg
? NULL_RTX
: reg
);
3648 if (GET_CODE (offset
) == CONST_INT
)
3650 if (SMALL_INT (offset
))
3651 return plus_constant (base
, INTVAL (offset
));
3652 else if (! reload_in_progress
&& ! reload_completed
)
3653 offset
= force_reg (Pmode
, offset
);
3655 /* If we reach here, then something is seriously wrong. */
3658 return gen_rtx_PLUS (Pmode
, base
, offset
);
3660 else if (GET_CODE (orig
) == LABEL_REF
)
3661 /* ??? We ought to be checking that the register is live instead, in case
3662 it is eliminated. */
3663 crtl
->uses_pic_offset_table
= 1;
3668 /* Try machine-dependent ways of modifying an illegitimate address X
3669 to be legitimate. If we find one, return the new, valid address.
3671 OLDX is the address as it was before break_out_memory_refs was called.
3672 In some cases it is useful to look at this to decide what needs to be done.
3674 MODE is the mode of the operand pointed to by X.
3676 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3679 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3680 enum machine_mode mode
)
3684 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3685 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3686 force_operand (XEXP (x
, 0), NULL_RTX
));
3687 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3688 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3689 force_operand (XEXP (x
, 1), NULL_RTX
));
3690 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3691 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3693 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3694 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3695 force_operand (XEXP (x
, 1), NULL_RTX
));
3697 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
3700 if (sparc_tls_referenced_p (x
))
3701 x
= sparc_legitimize_tls_address (x
);
3703 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
3704 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3705 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3706 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3707 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3708 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3709 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3710 else if (GET_CODE (x
) == SYMBOL_REF
3711 || GET_CODE (x
) == CONST
3712 || GET_CODE (x
) == LABEL_REF
)
3713 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3718 /* Delegitimize an address that was legitimized by the above function. */
3721 sparc_delegitimize_address (rtx x
)
3723 x
= delegitimize_mem_from_attrs (x
);
3725 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
3726 switch (XINT (XEXP (x
, 1), 1))
3728 case UNSPEC_MOVE_PIC
:
3730 x
= XVECEXP (XEXP (x
, 1), 0, 0);
3731 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3737 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3738 if (GET_CODE (x
) == MINUS
3739 && REG_P (XEXP (x
, 0))
3740 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
3741 && GET_CODE (XEXP (x
, 1)) == LO_SUM
3742 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
3743 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
3745 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
3746 gcc_assert (GET_CODE (x
) == LABEL_REF
);
3752 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3753 replace the input X, or the original X if no replacement is called for.
3754 The output parameter *WIN is 1 if the calling macro should goto WIN,
3757 For SPARC, we wish to handle addresses by splitting them into
3758 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3759 This cuts the number of extra insns by one.
3761 Do nothing when generating PIC code and the address is a symbolic
3762 operand or requires a scratch register. */
3765 sparc_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3766 int opnum
, int type
,
3767 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3769 /* Decompose SImode constants into HIGH+LO_SUM. */
3771 && (mode
!= TFmode
|| TARGET_ARCH64
)
3772 && GET_MODE (x
) == SImode
3773 && GET_CODE (x
) != LO_SUM
3774 && GET_CODE (x
) != HIGH
3775 && sparc_cmodel
<= CM_MEDLOW
3777 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
3779 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
3780 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3781 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3782 opnum
, (enum reload_type
)type
);
3787 /* We have to recognize what we have already generated above. */
3788 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
3790 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3791 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3792 opnum
, (enum reload_type
)type
);
3801 /* Return true if ADDR (a legitimate address expression)
3802 has an effect that depends on the machine mode it is used for.
3808 is not equivalent to
3810 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3812 because [%l7+a+1] is interpreted as the address of (a+1). */
3816 sparc_mode_dependent_address_p (const_rtx addr
)
3818 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
3820 rtx op0
= XEXP (addr
, 0);
3821 rtx op1
= XEXP (addr
, 1);
3822 if (op0
== pic_offset_table_rtx
3823 && symbolic_operand (op1
, VOIDmode
))
3830 #ifdef HAVE_GAS_HIDDEN
3831 # define USE_HIDDEN_LINKONCE 1
3833 # define USE_HIDDEN_LINKONCE 0
3837 get_pc_thunk_name (char name
[32], unsigned int regno
)
3839 const char *reg_name
= reg_names
[regno
];
3841 /* Skip the leading '%' as that cannot be used in a
3845 if (USE_HIDDEN_LINKONCE
)
3846 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
3848 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
3851 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
3854 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
3856 int orig_flag_pic
= flag_pic
;
3859 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3862 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
3864 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
3865 flag_pic
= orig_flag_pic
;
3870 /* Emit code to load the GOT register. */
3873 load_got_register (void)
3875 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3876 if (!global_offset_table_rtx
)
3877 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
3879 if (TARGET_VXWORKS_RTP
)
3880 emit_insn (gen_vxworks_load_got ());
3883 /* The GOT symbol is subject to a PC-relative relocation so we need a
3884 helper function to add the PC value and thus get the final value. */
3885 if (!got_helper_rtx
)
3888 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
3889 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
3892 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
3894 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
3897 /* Need to emit this whether or not we obey regdecls,
3898 since setjmp/longjmp can cause life info to screw up.
3899 ??? In the case where we don't obey regdecls, this is not sufficient
3900 since we may not fall out the bottom. */
3901 emit_use (global_offset_table_rtx
);
3904 /* Emit a call instruction with the pattern given by PAT. ADDR is the
3905 address of the call target. */
3908 sparc_emit_call_insn (rtx pat
, rtx addr
)
3912 insn
= emit_call_insn (pat
);
3914 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3915 if (TARGET_VXWORKS_RTP
3917 && GET_CODE (addr
) == SYMBOL_REF
3918 && (SYMBOL_REF_DECL (addr
)
3919 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
3920 : !SYMBOL_REF_LOCAL_P (addr
)))
3922 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3923 crtl
->uses_pic_offset_table
= 1;
3927 /* Return 1 if RTX is a MEM which is known to be aligned to at
3928 least a DESIRED byte boundary. */
3931 mem_min_alignment (rtx mem
, int desired
)
3933 rtx addr
, base
, offset
;
3935 /* If it's not a MEM we can't accept it. */
3936 if (GET_CODE (mem
) != MEM
)
3940 if (!TARGET_UNALIGNED_DOUBLES
3941 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
3944 /* ??? The rest of the function predates MEM_ALIGN so
3945 there is probably a bit of redundancy. */
3946 addr
= XEXP (mem
, 0);
3947 base
= offset
= NULL_RTX
;
3948 if (GET_CODE (addr
) == PLUS
)
3950 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3952 base
= XEXP (addr
, 0);
3954 /* What we are saying here is that if the base
3955 REG is aligned properly, the compiler will make
3956 sure any REG based index upon it will be so
3958 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3959 offset
= XEXP (addr
, 1);
3961 offset
= const0_rtx
;
3964 else if (GET_CODE (addr
) == REG
)
3967 offset
= const0_rtx
;
3970 if (base
!= NULL_RTX
)
3972 int regno
= REGNO (base
);
3974 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3976 /* Check if the compiler has recorded some information
3977 about the alignment of the base REG. If reload has
3978 completed, we already matched with proper alignments.
3979 If not running global_alloc, reload might give us
3980 unaligned pointer to local stack though. */
3982 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3983 || (optimize
&& reload_completed
))
3984 && (INTVAL (offset
) & (desired
- 1)) == 0)
3989 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3993 else if (! TARGET_UNALIGNED_DOUBLES
3994 || CONSTANT_P (addr
)
3995 || GET_CODE (addr
) == LO_SUM
)
3997 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3998 is true, in which case we can only assume that an access is aligned if
3999 it is to a constant address, or the address involves a LO_SUM. */
4003 /* An obviously unaligned address. */
4008 /* Vectors to keep interesting information about registers where it can easily
4009 be got. We used to use the actual mode value as the bit number, but there
4010 are more than 32 modes now. Instead we use two tables: one indexed by
4011 hard register number, and one indexed by mode. */
4013 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4014 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4015 mapped into one sparc_mode_class mode. */
4017 enum sparc_mode_class
{
4018 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4019 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4023 /* Modes for single-word and smaller quantities. */
4024 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4026 /* Modes for double-word and smaller quantities. */
4027 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4029 /* Modes for quad-word and smaller quantities. */
4030 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4032 /* Modes for 8-word and smaller quantities. */
4033 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4035 /* Modes for single-float quantities. We must allow any single word or
4036 smaller quantity. This is because the fix/float conversion instructions
4037 take integer inputs/outputs from the float registers. */
4038 #define SF_MODES (S_MODES)
4040 /* Modes for double-float and smaller quantities. */
4041 #define DF_MODES (D_MODES)
4043 /* Modes for quad-float and smaller quantities. */
4044 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4046 /* Modes for quad-float pairs and smaller quantities. */
4047 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4049 /* Modes for double-float only quantities. */
4050 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4052 /* Modes for quad-float and double-float only quantities. */
4053 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4055 /* Modes for quad-float pairs and double-float only quantities. */
4056 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4058 /* Modes for condition codes. */
4059 #define CC_MODES (1 << (int) CC_MODE)
4060 #define CCFP_MODES (1 << (int) CCFP_MODE)
4062 /* Value is 1 if register/mode pair is acceptable on sparc.
4063 The funny mixture of D and T modes is because integer operations
4064 do not specially operate on tetra quantities, so non-quad-aligned
4065 registers can hold quadword quantities (except %o4 and %i4 because
4066 they cross fixed registers). */
4068 /* This points to either the 32 bit or the 64 bit version. */
4069 const int *hard_regno_mode_classes
;
4071 static const int hard_32bit_mode_classes
[] = {
4072 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4073 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4074 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4075 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4077 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4078 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4079 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4080 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4082 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4083 and none can hold SFmode/SImode values. */
4084 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4085 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4086 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4087 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4090 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4092 /* %icc, %sfp, %gsr */
4093 CC_MODES
, 0, D_MODES
4096 static const int hard_64bit_mode_classes
[] = {
4097 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4098 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4099 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4100 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4102 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4103 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4104 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4105 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4107 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4108 and none can hold SFmode/SImode values. */
4109 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4110 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4111 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4112 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4115 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4117 /* %icc, %sfp, %gsr */
4118 CC_MODES
, 0, D_MODES
4121 int sparc_mode_class
[NUM_MACHINE_MODES
];
4123 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4126 sparc_init_modes (void)
4130 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4132 switch (GET_MODE_CLASS (i
))
4135 case MODE_PARTIAL_INT
:
4136 case MODE_COMPLEX_INT
:
4137 if (GET_MODE_SIZE (i
) <= 4)
4138 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4139 else if (GET_MODE_SIZE (i
) == 8)
4140 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4141 else if (GET_MODE_SIZE (i
) == 16)
4142 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4143 else if (GET_MODE_SIZE (i
) == 32)
4144 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4146 sparc_mode_class
[i
] = 0;
4148 case MODE_VECTOR_INT
:
4149 if (GET_MODE_SIZE (i
) <= 4)
4150 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
4151 else if (GET_MODE_SIZE (i
) == 8)
4152 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
4155 case MODE_COMPLEX_FLOAT
:
4156 if (GET_MODE_SIZE (i
) <= 4)
4157 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4158 else if (GET_MODE_SIZE (i
) == 8)
4159 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4160 else if (GET_MODE_SIZE (i
) == 16)
4161 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4162 else if (GET_MODE_SIZE (i
) == 32)
4163 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4165 sparc_mode_class
[i
] = 0;
4168 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
4169 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4171 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4174 sparc_mode_class
[i
] = 0;
4180 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4182 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4184 /* Initialize the array used by REGNO_REG_CLASS. */
4185 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4187 if (i
< 16 && TARGET_V8PLUS
)
4188 sparc_regno_reg_class
[i
] = I64_REGS
;
4189 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4190 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4192 sparc_regno_reg_class
[i
] = FP_REGS
;
4194 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4196 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4198 sparc_regno_reg_class
[i
] = NO_REGS
;
4202 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4205 save_global_or_fp_reg_p (unsigned int regno
,
4206 int leaf_function ATTRIBUTE_UNUSED
)
4208 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4211 /* Return whether the return address register (%i7) is needed. */
4214 return_addr_reg_needed_p (int leaf_function
)
4216 /* If it is live, for example because of __builtin_return_address (0). */
4217 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4220 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4222 /* Loading the GOT register clobbers %o7. */
4223 || crtl
->uses_pic_offset_table
4224 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4230 /* Return whether REGNO, a local or in register, must be saved/restored. */
4233 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4235 /* General case: call-saved registers live at some point. */
4236 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4239 /* Frame pointer register (%fp) if needed. */
4240 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4243 /* Return address register (%i7) if needed. */
4244 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4247 /* GOT register (%l7) if needed. */
4248 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4251 /* If the function accesses prior frames, the frame pointer and the return
4252 address of the previous frame must be saved on the stack. */
4253 if (crtl
->accesses_prior_frames
4254 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4260 /* Compute the frame size required by the function. This function is called
4261 during the reload pass and also by sparc_expand_prologue. */
4264 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4266 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4267 int args_size
, n_global_fp_regs
= 0;
4268 bool save_local_in_regs_p
= false;
4271 /* If the function allocates dynamic stack space, the dynamic offset is
4272 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4273 if (leaf_function
&& !cfun
->calls_alloca
)
4276 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
4278 /* Calculate space needed for global registers. */
4280 for (i
= 0; i
< 8; i
++)
4281 if (save_global_or_fp_reg_p (i
, 0))
4282 n_global_fp_regs
+= 2;
4284 for (i
= 0; i
< 8; i
+= 2)
4285 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4286 n_global_fp_regs
+= 2;
4288 /* In the flat window model, find out which local and in registers need to
4289 be saved. We don't reserve space in the current frame for them as they
4290 will be spilled into the register window save area of the caller's frame.
4291 However, as soon as we use this register window save area, we must create
4292 that of the current frame to make it the live one. */
4294 for (i
= 16; i
< 32; i
++)
4295 if (save_local_or_in_reg_p (i
, leaf_function
))
4297 save_local_in_regs_p
= true;
4301 /* Calculate space needed for FP registers. */
4302 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
4303 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4304 n_global_fp_regs
+= 2;
4307 && n_global_fp_regs
== 0
4309 && !save_local_in_regs_p
)
4310 frame_size
= apparent_frame_size
= 0;
4313 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4314 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
4315 apparent_frame_size
+= n_global_fp_regs
* 4;
4317 /* We need to add the size of the outgoing argument area. */
4318 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
4320 /* And that of the register window save area. */
4321 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
4323 /* Finally, bump to the appropriate alignment. */
4324 frame_size
= SPARC_STACK_ALIGN (frame_size
);
4327 /* Set up values for use in prologue and epilogue. */
4328 sparc_frame_size
= frame_size
;
4329 sparc_apparent_frame_size
= apparent_frame_size
;
4330 sparc_n_global_fp_regs
= n_global_fp_regs
;
4331 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
4336 /* Output any necessary .register pseudo-ops. */
4339 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
4341 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4347 /* Check if %g[2367] were used without
4348 .register being printed for them already. */
4349 for (i
= 2; i
< 8; i
++)
4351 if (df_regs_ever_live_p (i
)
4352 && ! sparc_hard_reg_printed
[i
])
4354 sparc_hard_reg_printed
[i
] = 1;
4355 /* %g7 is used as TLS base register, use #ignore
4356 for it instead of #scratch. */
4357 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
4358 i
== 7 ? "ignore" : "scratch");
4365 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4367 #if PROBE_INTERVAL > 4096
4368 #error Cannot use indexed addressing mode for stack probing
4371 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4372 inclusive. These are offsets from the current stack pointer.
4374 Note that we don't use the REG+REG addressing mode for the probes because
4375 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4376 so the advantages of having a single code win here. */
4379 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
4381 rtx g1
= gen_rtx_REG (Pmode
, 1);
4383 /* See if we have a constant small number of probes to generate. If so,
4384 that's the easy case. */
4385 if (size
<= PROBE_INTERVAL
)
4387 emit_move_insn (g1
, GEN_INT (first
));
4388 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4389 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4390 emit_stack_probe (plus_constant (g1
, -size
));
4393 /* The run-time loop is made up of 10 insns in the generic case while the
4394 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4395 else if (size
<= 5 * PROBE_INTERVAL
)
4399 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
4400 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4401 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4402 emit_stack_probe (g1
);
4404 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4405 it exceeds SIZE. If only two probes are needed, this will not
4406 generate any code. Then probe at FIRST + SIZE. */
4407 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
4409 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4410 plus_constant (g1
, -PROBE_INTERVAL
)));
4411 emit_stack_probe (g1
);
4414 emit_stack_probe (plus_constant (g1
, (i
- PROBE_INTERVAL
) - size
));
4417 /* Otherwise, do the same as above, but in a loop. Note that we must be
4418 extra careful with variables wrapping around because we might be at
4419 the very top (or the very bottom) of the address space and we have
4420 to be able to handle this case properly; in particular, we use an
4421 equality test for the loop condition. */
4424 HOST_WIDE_INT rounded_size
;
4425 rtx g4
= gen_rtx_REG (Pmode
, 4);
4427 emit_move_insn (g1
, GEN_INT (first
));
4430 /* Step 1: round SIZE to the previous multiple of the interval. */
4432 rounded_size
= size
& -PROBE_INTERVAL
;
4433 emit_move_insn (g4
, GEN_INT (rounded_size
));
4436 /* Step 2: compute initial and final value of the loop counter. */
4438 /* TEST_ADDR = SP + FIRST. */
4439 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4440 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4442 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4443 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
4448 while (TEST_ADDR != LAST_ADDR)
4450 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4454 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4455 until it is equal to ROUNDED_SIZE. */
4458 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
4460 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
4463 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4464 that SIZE is equal to ROUNDED_SIZE. */
4466 if (size
!= rounded_size
)
4467 emit_stack_probe (plus_constant (g4
, rounded_size
- size
));
4470 /* Make sure nothing is scheduled before we are done. */
4471 emit_insn (gen_blockage ());
4474 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4475 absolute addresses. */
4478 output_probe_stack_range (rtx reg1
, rtx reg2
)
4480 static int labelno
= 0;
4481 char loop_lab
[32], end_lab
[32];
4484 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
4485 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
4487 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
4489 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4492 output_asm_insn ("cmp\t%0, %1", xops
);
4494 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
4496 fputs ("\tbe\t", asm_out_file
);
4497 assemble_name_raw (asm_out_file
, end_lab
);
4498 fputc ('\n', asm_out_file
);
4500 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4501 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
4502 output_asm_insn (" add\t%0, %1, %0", xops
);
4504 /* Probe at TEST_ADDR and branch. */
4506 fputs ("\tba,pt\t%xcc,", asm_out_file
);
4508 fputs ("\tba\t", asm_out_file
);
4509 assemble_name_raw (asm_out_file
, loop_lab
);
4510 fputc ('\n', asm_out_file
);
4511 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
4512 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
4514 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
4519 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4520 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4521 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4522 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4523 the action to be performed if it returns false. Return the new offset. */
4525 typedef bool (*sorr_pred_t
) (unsigned int, int);
4526 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
4529 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
4530 int offset
, int leaf_function
, sorr_pred_t save_p
,
4531 sorr_act_t action_true
, sorr_act_t action_false
)
4536 if (TARGET_ARCH64
&& high
<= 32)
4540 for (i
= low
; i
< high
; i
++)
4542 if (save_p (i
, leaf_function
))
4544 mem
= gen_frame_mem (DImode
, plus_constant (base
, offset
));
4545 if (action_true
== SORR_SAVE
)
4547 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
4548 RTX_FRAME_RELATED_P (insn
) = 1;
4550 else /* action_true == SORR_RESTORE */
4552 /* The frame pointer must be restored last since its old
4553 value may be used as base address for the frame. This
4554 is problematic in 64-bit mode only because of the lack
4555 of double-word load instruction. */
4556 if (i
== HARD_FRAME_POINTER_REGNUM
)
4559 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
4563 else if (action_false
== SORR_ADVANCE
)
4569 mem
= gen_frame_mem (DImode
, plus_constant (base
, fp_offset
));
4570 emit_move_insn (hard_frame_pointer_rtx
, mem
);
4575 for (i
= low
; i
< high
; i
+= 2)
4577 bool reg0
= save_p (i
, leaf_function
);
4578 bool reg1
= save_p (i
+ 1, leaf_function
);
4579 enum machine_mode mode
;
4584 mode
= i
< 32 ? DImode
: DFmode
;
4589 mode
= i
< 32 ? SImode
: SFmode
;
4594 mode
= i
< 32 ? SImode
: SFmode
;
4600 if (action_false
== SORR_ADVANCE
)
4605 mem
= gen_frame_mem (mode
, plus_constant (base
, offset
));
4606 if (action_true
== SORR_SAVE
)
4608 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
4609 RTX_FRAME_RELATED_P (insn
) = 1;
4613 mem
= gen_frame_mem (SImode
, plus_constant (base
, offset
));
4614 set1
= gen_rtx_SET (VOIDmode
, mem
,
4615 gen_rtx_REG (SImode
, regno
));
4616 RTX_FRAME_RELATED_P (set1
) = 1;
4618 = gen_frame_mem (SImode
, plus_constant (base
, offset
+ 4));
4619 set2
= gen_rtx_SET (VOIDmode
, mem
,
4620 gen_rtx_REG (SImode
, regno
+ 1));
4621 RTX_FRAME_RELATED_P (set2
) = 1;
4622 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4623 gen_rtx_PARALLEL (VOIDmode
,
4624 gen_rtvec (2, set1
, set2
)));
4627 else /* action_true == SORR_RESTORE */
4628 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
4630 /* Always preserve double-word alignment. */
4631 offset
= (offset
+ 8) & -8;
4638 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4641 emit_adjust_base_to_offset (rtx base
, int offset
)
4643 /* ??? This might be optimized a little as %g1 might already have a
4644 value close enough that a single add insn will do. */
4645 /* ??? Although, all of this is probably only a temporary fix because
4646 if %g1 can hold a function result, then sparc_expand_epilogue will
4647 lose (the result will be clobbered). */
4648 rtx new_base
= gen_rtx_REG (Pmode
, 1);
4649 emit_move_insn (new_base
, GEN_INT (offset
));
4650 emit_insn (gen_rtx_SET (VOIDmode
,
4651 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
4655 /* Emit code to save/restore call-saved global and FP registers. */
4658 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
4660 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
4662 base
= emit_adjust_base_to_offset (base
, offset
);
4667 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
4668 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4669 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
4670 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4673 /* Emit code to save/restore call-saved local and in registers. */
4676 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
4678 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
4680 base
= emit_adjust_base_to_offset (base
, offset
);
4684 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
4685 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
4688 /* Emit a window_save insn. */
4691 emit_window_save (rtx increment
)
4693 rtx insn
= emit_insn (gen_window_save (increment
));
4694 RTX_FRAME_RELATED_P (insn
) = 1;
4696 /* The incoming return address (%o7) is saved in %i7. */
4697 add_reg_note (insn
, REG_CFA_REGISTER
,
4698 gen_rtx_SET (VOIDmode
,
4699 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
4701 INCOMING_RETURN_ADDR_REGNUM
)));
4703 /* The window save event. */
4704 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
4706 /* The CFA is %fp, the hard frame pointer. */
4707 add_reg_note (insn
, REG_CFA_DEF_CFA
,
4708 plus_constant (hard_frame_pointer_rtx
,
4709 INCOMING_FRAME_SP_OFFSET
));
4714 /* Generate an increment for the stack pointer. */
4717 gen_stack_pointer_inc (rtx increment
)
4719 return gen_rtx_SET (VOIDmode
,
4721 gen_rtx_PLUS (Pmode
,
4726 /* Generate a decrement for the stack pointer. */
4729 gen_stack_pointer_dec (rtx decrement
)
4731 return gen_rtx_SET (VOIDmode
,
4733 gen_rtx_MINUS (Pmode
,
4738 /* Expand the function prologue. The prologue is responsible for reserving
4739 storage for the frame, saving the call-saved registers and loading the
4740 GOT register if needed. */
4743 sparc_expand_prologue (void)
4748 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4749 on the final value of the flag means deferring the prologue/epilogue
4750 expansion until just before the second scheduling pass, which is too
4751 late to emit multiple epilogues or return insns.
4753 Of course we are making the assumption that the value of the flag
4754 will not change between now and its final value. Of the three parts
4755 of the formula, only the last one can reasonably vary. Let's take a
4756 closer look, after assuming that the first two ones are set to true
4757 (otherwise the last value is effectively silenced).
4759 If only_leaf_regs_used returns false, the global predicate will also
4760 be false so the actual frame size calculated below will be positive.
4761 As a consequence, the save_register_window insn will be emitted in
4762 the instruction stream; now this insn explicitly references %fp
4763 which is not a leaf register so only_leaf_regs_used will always
4764 return false subsequently.
4766 If only_leaf_regs_used returns true, we hope that the subsequent
4767 optimization passes won't cause non-leaf registers to pop up. For
4768 example, the regrename pass has special provisions to not rename to
4769 non-leaf registers in a leaf function. */
4770 sparc_leaf_function_p
4771 = optimize
> 0 && current_function_is_leaf
&& only_leaf_regs_used ();
4773 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4775 if (flag_stack_usage_info
)
4776 current_function_static_stack_size
= size
;
4778 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4779 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4783 else if (sparc_leaf_function_p
)
4785 rtx size_int_rtx
= GEN_INT (-size
);
4788 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4789 else if (size
<= 8192)
4791 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4792 /* %sp is still the CFA register. */
4793 RTX_FRAME_RELATED_P (insn
) = 1;
4794 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4798 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4799 emit_move_insn (size_rtx
, size_int_rtx
);
4800 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4801 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4802 gen_stack_pointer_inc (size_int_rtx
));
4805 RTX_FRAME_RELATED_P (insn
) = 1;
4809 rtx size_int_rtx
= GEN_INT (-size
);
4812 emit_window_save (size_int_rtx
);
4813 else if (size
<= 8192)
4815 emit_window_save (GEN_INT (-4096));
4816 /* %sp is not the CFA register anymore. */
4817 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4821 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4822 emit_move_insn (size_rtx
, size_int_rtx
);
4823 emit_window_save (size_rtx
);
4827 if (sparc_leaf_function_p
)
4829 sparc_frame_base_reg
= stack_pointer_rtx
;
4830 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4834 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4835 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4838 if (sparc_n_global_fp_regs
> 0)
4839 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4840 sparc_frame_base_offset
4841 - sparc_apparent_frame_size
,
4844 /* Load the GOT register if needed. */
4845 if (crtl
->uses_pic_offset_table
)
4846 load_got_register ();
4848 /* Advertise that the data calculated just above are now valid. */
4849 sparc_prologue_data_valid_p
= true;
4852 /* Expand the function prologue. The prologue is responsible for reserving
4853 storage for the frame, saving the call-saved registers and loading the
4854 GOT register if needed. */
4857 sparc_flat_expand_prologue (void)
4862 sparc_leaf_function_p
= optimize
> 0 && current_function_is_leaf
;
4864 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4866 if (flag_stack_usage_info
)
4867 current_function_static_stack_size
= size
;
4869 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4870 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4872 if (sparc_save_local_in_regs_p
)
4873 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
4880 rtx size_int_rtx
, size_rtx
;
4882 size_rtx
= size_int_rtx
= GEN_INT (-size
);
4884 /* We establish the frame (i.e. decrement the stack pointer) first, even
4885 if we use a frame pointer, because we cannot clobber any call-saved
4886 registers, including the frame pointer, if we haven't created a new
4887 register save area, for the sake of compatibility with the ABI. */
4889 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4890 else if (size
<= 8192 && !frame_pointer_needed
)
4892 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4893 RTX_FRAME_RELATED_P (insn
) = 1;
4894 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4898 size_rtx
= gen_rtx_REG (Pmode
, 1);
4899 emit_move_insn (size_rtx
, size_int_rtx
);
4900 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4901 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4902 gen_stack_pointer_inc (size_int_rtx
));
4904 RTX_FRAME_RELATED_P (insn
) = 1;
4906 /* Ensure nothing is scheduled until after the frame is established. */
4907 emit_insn (gen_blockage ());
4909 if (frame_pointer_needed
)
4911 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4912 gen_rtx_MINUS (Pmode
,
4915 RTX_FRAME_RELATED_P (insn
) = 1;
4917 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4918 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4919 plus_constant (stack_pointer_rtx
,
4923 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
4925 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
4926 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
4928 insn
= emit_move_insn (i7
, o7
);
4929 RTX_FRAME_RELATED_P (insn
) = 1;
4931 add_reg_note (insn
, REG_CFA_REGISTER
,
4932 gen_rtx_SET (VOIDmode
, i7
, o7
));
4934 /* Prevent this instruction from ever being considered dead,
4935 even if this function has no epilogue. */
4936 emit_insn (gen_rtx_USE (VOIDmode
, i7
));
4940 if (frame_pointer_needed
)
4942 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4943 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4947 sparc_frame_base_reg
= stack_pointer_rtx
;
4948 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4951 if (sparc_n_global_fp_regs
> 0)
4952 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4953 sparc_frame_base_offset
4954 - sparc_apparent_frame_size
,
4957 /* Load the GOT register if needed. */
4958 if (crtl
->uses_pic_offset_table
)
4959 load_got_register ();
4961 /* Advertise that the data calculated just above are now valid. */
4962 sparc_prologue_data_valid_p
= true;
4965 /* This function generates the assembly code for function entry, which boils
4966 down to emitting the necessary .register directives. */
4969 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4971 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4973 gcc_assert (sparc_leaf_function_p
== current_function_uses_only_leaf_regs
);
4975 sparc_output_scratch_registers (file
);
4978 /* Expand the function epilogue, either normal or part of a sibcall.
4979 We emit all the instructions except the return or the call. */
4982 sparc_expand_epilogue (bool for_eh
)
4984 HOST_WIDE_INT size
= sparc_frame_size
;
4986 if (sparc_n_global_fp_regs
> 0)
4987 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4988 sparc_frame_base_offset
4989 - sparc_apparent_frame_size
,
4992 if (size
== 0 || for_eh
)
4994 else if (sparc_leaf_function_p
)
4997 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
4998 else if (size
<= 8192)
5000 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5001 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
5005 rtx reg
= gen_rtx_REG (Pmode
, 1);
5006 emit_move_insn (reg
, GEN_INT (-size
));
5007 emit_insn (gen_stack_pointer_dec (reg
));
5012 /* Expand the function epilogue, either normal or part of a sibcall.
5013 We emit all the instructions except the return or the call. */
5016 sparc_flat_expand_epilogue (bool for_eh
)
5018 HOST_WIDE_INT size
= sparc_frame_size
;
5020 if (sparc_n_global_fp_regs
> 0)
5021 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5022 sparc_frame_base_offset
5023 - sparc_apparent_frame_size
,
5026 /* If we have a frame pointer, we'll need both to restore it before the
5027 frame is destroyed and use its current value in destroying the frame.
5028 Since we don't have an atomic way to do that in the flat window model,
5029 we save the current value into a temporary register (%g1). */
5030 if (frame_pointer_needed
&& !for_eh
)
5031 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5033 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5034 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5035 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5037 if (sparc_save_local_in_regs_p
)
5038 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5039 sparc_frame_base_offset
,
5042 if (size
== 0 || for_eh
)
5044 else if (frame_pointer_needed
)
5046 /* Make sure the frame is destroyed after everything else is done. */
5047 emit_insn (gen_blockage ());
5049 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5054 emit_insn (gen_blockage ());
5057 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
5058 else if (size
<= 8192)
5060 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5061 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
5065 rtx reg
= gen_rtx_REG (Pmode
, 1);
5066 emit_move_insn (reg
, GEN_INT (-size
));
5067 emit_insn (gen_stack_pointer_dec (reg
));
5072 /* Return true if it is appropriate to emit `return' instructions in the
5073 body of a function. */
5076 sparc_can_use_return_insn_p (void)
5078 return sparc_prologue_data_valid_p
5079 && sparc_n_global_fp_regs
== 0
5081 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5082 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5085 /* This function generates the assembly code for function exit. */
5088 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5090 /* If the last two instructions of a function are "call foo; dslot;"
5091 the return address might point to the first instruction in the next
5092 function and we have to output a dummy nop for the sake of sane
5093 backtraces in such cases. This is pointless for sibling calls since
5094 the return address is explicitly adjusted. */
5096 rtx insn
, last_real_insn
;
5098 insn
= get_last_insn ();
5100 last_real_insn
= prev_real_insn (insn
);
5102 && GET_CODE (last_real_insn
) == INSN
5103 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5104 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5107 && CALL_P (last_real_insn
)
5108 && !SIBLING_CALL_P (last_real_insn
))
5109 fputs("\tnop\n", file
);
5111 sparc_output_deferred_case_vectors ();
5114 /* Output a 'restore' instruction. */
5117 output_restore (rtx pat
)
5123 fputs ("\t restore\n", asm_out_file
);
5127 gcc_assert (GET_CODE (pat
) == SET
);
5129 operands
[0] = SET_DEST (pat
);
5130 pat
= SET_SRC (pat
);
5132 switch (GET_CODE (pat
))
5135 operands
[1] = XEXP (pat
, 0);
5136 operands
[2] = XEXP (pat
, 1);
5137 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5140 operands
[1] = XEXP (pat
, 0);
5141 operands
[2] = XEXP (pat
, 1);
5142 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5145 operands
[1] = XEXP (pat
, 0);
5146 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5147 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5151 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5156 /* Output a return. */
5159 output_return (rtx insn
)
5161 if (crtl
->calls_eh_return
)
5163 /* If the function uses __builtin_eh_return, the eh_return
5164 machinery occupies the delay slot. */
5165 gcc_assert (!final_sequence
);
5167 if (flag_delayed_branch
)
5169 if (!TARGET_FLAT
&& TARGET_V9
)
5170 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5174 fputs ("\trestore\n", asm_out_file
);
5176 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5179 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5184 fputs ("\trestore\n", asm_out_file
);
5186 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5187 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5190 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5192 /* This is a leaf or flat function so we don't have to bother restoring
5193 the register window, which frees us from dealing with the convoluted
5194 semantics of restore/return. We simply output the jump to the
5195 return address and the insn in the delay slot (if any). */
5197 return "jmp\t%%o7+%)%#";
5201 /* This is a regular function so we have to restore the register window.
5202 We may have a pending insn for the delay slot, which will be either
5203 combined with the 'restore' instruction or put in the delay slot of
5204 the 'return' instruction. */
5210 delay
= NEXT_INSN (insn
);
5213 pat
= PATTERN (delay
);
5215 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5217 epilogue_renumber (&pat
, 0);
5218 return "return\t%%i7+%)%#";
5222 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5223 output_restore (pat
);
5224 PATTERN (delay
) = gen_blockage ();
5225 INSN_CODE (delay
) = -1;
5230 /* The delay slot is empty. */
5232 return "return\t%%i7+%)\n\t nop";
5233 else if (flag_delayed_branch
)
5234 return "jmp\t%%i7+%)\n\t restore";
5236 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5243 /* Output a sibling call. */
5246 output_sibcall (rtx insn
, rtx call_operand
)
5250 gcc_assert (flag_delayed_branch
);
5252 operands
[0] = call_operand
;
5254 if (sparc_leaf_function_p
|| TARGET_FLAT
)
5256 /* This is a leaf or flat function so we don't have to bother restoring
5257 the register window. We simply output the jump to the function and
5258 the insn in the delay slot (if any). */
5260 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
5263 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5266 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5267 it into branch if possible. */
5268 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5273 /* This is a regular function so we have to restore the register window.
5274 We may have a pending insn for the delay slot, which will be combined
5275 with the 'restore' instruction. */
5277 output_asm_insn ("call\t%a0, 0", operands
);
5281 rtx delay
= NEXT_INSN (insn
);
5284 output_restore (PATTERN (delay
));
5286 PATTERN (delay
) = gen_blockage ();
5287 INSN_CODE (delay
) = -1;
5290 output_restore (NULL_RTX
);
5296 /* Functions for handling argument passing.
5298 For 32-bit, the first 6 args are normally in registers and the rest are
5299 pushed. Any arg that starts within the first 6 words is at least
5300 partially passed in a register unless its data type forbids.
5302 For 64-bit, the argument registers are laid out as an array of 16 elements
5303 and arguments are added sequentially. The first 6 int args and up to the
5304 first 16 fp args (depending on size) are passed in regs.
5306 Slot Stack Integral Float Float in structure Double Long Double
5307 ---- ----- -------- ----- ------------------ ------ -----------
5308 15 [SP+248] %f31 %f30,%f31 %d30
5309 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5310 13 [SP+232] %f27 %f26,%f27 %d26
5311 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5312 11 [SP+216] %f23 %f22,%f23 %d22
5313 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5314 9 [SP+200] %f19 %f18,%f19 %d18
5315 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5316 7 [SP+184] %f15 %f14,%f15 %d14
5317 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5318 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5319 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5320 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5321 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5322 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5323 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5325 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5327 Integral arguments are always passed as 64-bit quantities appropriately
5330 Passing of floating point values is handled as follows.
5331 If a prototype is in scope:
5332 If the value is in a named argument (i.e. not a stdarg function or a
5333 value not part of the `...') then the value is passed in the appropriate
5335 If the value is part of the `...' and is passed in one of the first 6
5336 slots then the value is passed in the appropriate int reg.
5337 If the value is part of the `...' and is not passed in one of the first 6
5338 slots then the value is passed in memory.
5339 If a prototype is not in scope:
5340 If the value is one of the first 6 arguments the value is passed in the
5341 appropriate integer reg and the appropriate fp reg.
5342 If the value is not one of the first 6 arguments the value is passed in
5343 the appropriate fp reg and in memory.
5346 Summary of the calling conventions implemented by GCC on the SPARC:
5349 size argument return value
5351 small integer <4 int. reg. int. reg.
5352 word 4 int. reg. int. reg.
5353 double word 8 int. reg. int. reg.
5355 _Complex small integer <8 int. reg. int. reg.
5356 _Complex word 8 int. reg. int. reg.
5357 _Complex double word 16 memory int. reg.
5359 vector integer <=8 int. reg. FP reg.
5360 vector integer >8 memory memory
5362 float 4 int. reg. FP reg.
5363 double 8 int. reg. FP reg.
5364 long double 16 memory memory
5366 _Complex float 8 memory FP reg.
5367 _Complex double 16 memory FP reg.
5368 _Complex long double 32 memory FP reg.
5370 vector float any memory memory
5372 aggregate any memory memory
5377 size argument return value
5379 small integer <8 int. reg. int. reg.
5380 word 8 int. reg. int. reg.
5381 double word 16 int. reg. int. reg.
5383 _Complex small integer <16 int. reg. int. reg.
5384 _Complex word 16 int. reg. int. reg.
5385 _Complex double word 32 memory int. reg.
5387 vector integer <=16 FP reg. FP reg.
5388 vector integer 16<s<=32 memory FP reg.
5389 vector integer >32 memory memory
5391 float 4 FP reg. FP reg.
5392 double 8 FP reg. FP reg.
5393 long double 16 FP reg. FP reg.
5395 _Complex float 8 FP reg. FP reg.
5396 _Complex double 16 FP reg. FP reg.
5397 _Complex long double 32 memory FP reg.
5399 vector float <=16 FP reg. FP reg.
5400 vector float 16<s<=32 memory FP reg.
5401 vector float >32 memory memory
5403 aggregate <=16 reg. reg.
5404 aggregate 16<s<=32 memory reg.
5405 aggregate >32 memory memory
5409 Note #1: complex floating-point types follow the extended SPARC ABIs as
5410 implemented by the Sun compiler.
5412 Note #2: integral vector types follow the scalar floating-point types
5413 conventions to match what is implemented by the Sun VIS SDK.
5415 Note #3: floating-point vector types follow the aggregate types
5419 /* Maximum number of int regs for args. */
5420 #define SPARC_INT_ARG_MAX 6
5421 /* Maximum number of fp regs for args. */
5422 #define SPARC_FP_ARG_MAX 16
5424 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5426 /* Handle the INIT_CUMULATIVE_ARGS macro.
5427 Initialize a variable CUM of type CUMULATIVE_ARGS
5428 for a call to a function whose data type is FNTYPE.
5429 For a library call, FNTYPE is 0. */
5432 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
5433 rtx libname ATTRIBUTE_UNUSED
,
5434 tree fndecl ATTRIBUTE_UNUSED
)
5437 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
5438 cum
->libcall_p
= fntype
== 0;
5441 /* Handle promotion of pointer and integer arguments. */
5443 static enum machine_mode
5444 sparc_promote_function_mode (const_tree type
,
5445 enum machine_mode mode
,
5447 const_tree fntype ATTRIBUTE_UNUSED
,
5448 int for_return ATTRIBUTE_UNUSED
)
5450 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
5452 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
5456 /* Integral arguments are passed as full words, as per the ABI. */
5457 if (GET_MODE_CLASS (mode
) == MODE_INT
5458 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5464 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5467 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5469 return TARGET_ARCH64
? true : false;
5472 /* Scan the record type TYPE and return the following predicates:
5473 - INTREGS_P: the record contains at least one field or sub-field
5474 that is eligible for promotion in integer registers.
5475 - FP_REGS_P: the record contains at least one field or sub-field
5476 that is eligible for promotion in floating-point registers.
5477 - PACKED_P: the record contains at least one field that is packed.
5479 Sub-fields are not taken into account for the PACKED_P predicate. */
5482 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
5487 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5489 if (TREE_CODE (field
) == FIELD_DECL
)
5491 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5492 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
5493 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5494 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5500 if (packed_p
&& DECL_PACKED (field
))
5506 /* Compute the slot number to pass an argument in.
5507 Return the slot number or -1 if passing on the stack.
5509 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5510 the preceding args and about the function being called.
5511 MODE is the argument's machine mode.
5512 TYPE is the data type of the argument (as a tree).
5513 This is null for libcalls where that information may
5515 NAMED is nonzero if this argument is a named parameter
5516 (otherwise it is an extra parameter matching an ellipsis).
5517 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5518 *PREGNO records the register number to use if scalar type.
5519 *PPADDING records the amount of padding needed in words. */
5522 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
5523 const_tree type
, bool named
, bool incoming_p
,
5524 int *pregno
, int *ppadding
)
5526 int regbase
= (incoming_p
5527 ? SPARC_INCOMING_INT_ARG_FIRST
5528 : SPARC_OUTGOING_INT_ARG_FIRST
);
5529 int slotno
= cum
->words
;
5530 enum mode_class mclass
;
5535 if (type
&& TREE_ADDRESSABLE (type
))
5541 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
5544 /* For SPARC64, objects requiring 16-byte alignment get it. */
5546 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
5547 && (slotno
& 1) != 0)
5548 slotno
++, *ppadding
= 1;
5550 mclass
= GET_MODE_CLASS (mode
);
5551 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5553 /* Vector types deserve special treatment because they are
5554 polymorphic wrt their mode, depending upon whether VIS
5555 instructions are enabled. */
5556 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
5558 /* The SPARC port defines no floating-point vector modes. */
5559 gcc_assert (mode
== BLKmode
);
5563 /* Integral vector types should either have a vector
5564 mode or an integral mode, because we are guaranteed
5565 by pass_by_reference that their size is not greater
5566 than 16 bytes and TImode is 16-byte wide. */
5567 gcc_assert (mode
!= BLKmode
);
5569 /* Vector integers are handled like floats according to
5571 mclass
= MODE_FLOAT
;
5578 case MODE_COMPLEX_FLOAT
:
5579 case MODE_VECTOR_INT
:
5580 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
5582 if (slotno
>= SPARC_FP_ARG_MAX
)
5584 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
5585 /* Arguments filling only one single FP register are
5586 right-justified in the outer double FP register. */
5587 if (GET_MODE_SIZE (mode
) <= 4)
5594 case MODE_COMPLEX_INT
:
5595 if (slotno
>= SPARC_INT_ARG_MAX
)
5597 regno
= regbase
+ slotno
;
5601 if (mode
== VOIDmode
)
5602 /* MODE is VOIDmode when generating the actual call. */
5605 gcc_assert (mode
== BLKmode
);
5609 || (TREE_CODE (type
) != VECTOR_TYPE
5610 && TREE_CODE (type
) != RECORD_TYPE
))
5612 if (slotno
>= SPARC_INT_ARG_MAX
)
5614 regno
= regbase
+ slotno
;
5616 else /* TARGET_ARCH64 && type */
5618 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
5620 /* First see what kinds of registers we would need. */
5621 if (TREE_CODE (type
) == VECTOR_TYPE
)
5624 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
5626 /* The ABI obviously doesn't specify how packed structures
5627 are passed. These are defined to be passed in int regs
5628 if possible, otherwise memory. */
5629 if (packed_p
|| !named
)
5630 fpregs_p
= 0, intregs_p
= 1;
5632 /* If all arg slots are filled, then must pass on stack. */
5633 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
5636 /* If there are only int args and all int arg slots are filled,
5637 then must pass on stack. */
5638 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
5641 /* Note that even if all int arg slots are filled, fp members may
5642 still be passed in regs if such regs are available.
5643 *PREGNO isn't set because there may be more than one, it's up
5644 to the caller to compute them. */
5657 /* Handle recursive register counting for structure field layout. */
5659 struct function_arg_record_value_parms
5661 rtx ret
; /* return expression being built. */
5662 int slotno
; /* slot number of the argument. */
5663 int named
; /* whether the argument is named. */
5664 int regbase
; /* regno of the base register. */
5665 int stack
; /* 1 if part of the argument is on the stack. */
5666 int intoffset
; /* offset of the first pending integer field. */
5667 unsigned int nregs
; /* number of words passed in registers. */
5670 static void function_arg_record_value_3
5671 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
5672 static void function_arg_record_value_2
5673 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5674 static void function_arg_record_value_1
5675 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5676 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
5677 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
5679 /* A subroutine of function_arg_record_value. Traverse the structure
5680 recursively and determine how many registers will be required. */
5683 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
5684 struct function_arg_record_value_parms
*parms
,
5689 /* We need to compute how many registers are needed so we can
5690 allocate the PARALLEL but before we can do that we need to know
5691 whether there are any packed fields. The ABI obviously doesn't
5692 specify how structures are passed in this case, so they are
5693 defined to be passed in int regs if possible, otherwise memory,
5694 regardless of whether there are fp values present. */
5697 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5699 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5706 /* Compute how many registers we need. */
5707 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5709 if (TREE_CODE (field
) == FIELD_DECL
)
5711 HOST_WIDE_INT bitpos
= startbitpos
;
5713 if (DECL_SIZE (field
) != 0)
5715 if (integer_zerop (DECL_SIZE (field
)))
5718 if (host_integerp (bit_position (field
), 1))
5719 bitpos
+= int_bit_position (field
);
5722 /* ??? FIXME: else assume zero offset. */
5724 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5725 function_arg_record_value_1 (TREE_TYPE (field
),
5729 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5730 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5735 if (parms
->intoffset
!= -1)
5737 unsigned int startbit
, endbit
;
5738 int intslots
, this_slotno
;
5740 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
5741 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5743 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5744 this_slotno
= parms
->slotno
+ parms
->intoffset
5747 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5749 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5750 /* We need to pass this field on the stack. */
5754 parms
->nregs
+= intslots
;
5755 parms
->intoffset
= -1;
5758 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5759 If it wasn't true we wouldn't be here. */
5760 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5761 && DECL_MODE (field
) == BLKmode
)
5762 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5763 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5770 if (parms
->intoffset
== -1)
5771 parms
->intoffset
= bitpos
;
5777 /* A subroutine of function_arg_record_value. Assign the bits of the
5778 structure between parms->intoffset and bitpos to integer registers. */
5781 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
5782 struct function_arg_record_value_parms
*parms
)
5784 enum machine_mode mode
;
5786 unsigned int startbit
, endbit
;
5787 int this_slotno
, intslots
, intoffset
;
5790 if (parms
->intoffset
== -1)
5793 intoffset
= parms
->intoffset
;
5794 parms
->intoffset
= -1;
5796 startbit
= intoffset
& -BITS_PER_WORD
;
5797 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5798 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5799 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
5801 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
5805 /* If this is the trailing part of a word, only load that much into
5806 the register. Otherwise load the whole register. Note that in
5807 the latter case we may pick up unwanted bits. It's not a problem
5808 at the moment but may wish to revisit. */
5810 if (intoffset
% BITS_PER_WORD
!= 0)
5811 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5816 intoffset
/= BITS_PER_UNIT
;
5819 regno
= parms
->regbase
+ this_slotno
;
5820 reg
= gen_rtx_REG (mode
, regno
);
5821 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5822 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5825 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5830 while (intslots
> 0);
5833 /* A subroutine of function_arg_record_value. Traverse the structure
5834 recursively and assign bits to floating point registers. Track which
5835 bits in between need integer registers; invoke function_arg_record_value_3
5836 to make that happen. */
5839 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
5840 struct function_arg_record_value_parms
*parms
,
5846 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5848 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5855 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5857 if (TREE_CODE (field
) == FIELD_DECL
)
5859 HOST_WIDE_INT bitpos
= startbitpos
;
5861 if (DECL_SIZE (field
) != 0)
5863 if (integer_zerop (DECL_SIZE (field
)))
5866 if (host_integerp (bit_position (field
), 1))
5867 bitpos
+= int_bit_position (field
);
5870 /* ??? FIXME: else assume zero offset. */
5872 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5873 function_arg_record_value_2 (TREE_TYPE (field
),
5877 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5878 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5883 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
5884 int regno
, nregs
, pos
;
5885 enum machine_mode mode
= DECL_MODE (field
);
5888 function_arg_record_value_3 (bitpos
, parms
);
5890 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5893 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5894 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5896 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5898 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5904 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
5905 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
5907 reg
= gen_rtx_REG (mode
, regno
);
5908 pos
= bitpos
/ BITS_PER_UNIT
;
5909 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5910 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5914 regno
+= GET_MODE_SIZE (mode
) / 4;
5915 reg
= gen_rtx_REG (mode
, regno
);
5916 pos
+= GET_MODE_SIZE (mode
);
5917 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5918 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5924 if (parms
->intoffset
== -1)
5925 parms
->intoffset
= bitpos
;
5931 /* Used by function_arg and sparc_function_value_1 to implement the complex
5932 conventions of the 64-bit ABI for passing and returning structures.
5933 Return an expression valid as a return value for the FUNCTION_ARG
5934 and TARGET_FUNCTION_VALUE.
5936 TYPE is the data type of the argument (as a tree).
5937 This is null for libcalls where that information may
5939 MODE is the argument's machine mode.
5940 SLOTNO is the index number of the argument's slot in the parameter array.
5941 NAMED is nonzero if this argument is a named parameter
5942 (otherwise it is an extra parameter matching an ellipsis).
5943 REGBASE is the regno of the base register for the parameter array. */
5946 function_arg_record_value (const_tree type
, enum machine_mode mode
,
5947 int slotno
, int named
, int regbase
)
5949 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5950 struct function_arg_record_value_parms parms
;
5953 parms
.ret
= NULL_RTX
;
5954 parms
.slotno
= slotno
;
5955 parms
.named
= named
;
5956 parms
.regbase
= regbase
;
5959 /* Compute how many registers we need. */
5961 parms
.intoffset
= 0;
5962 function_arg_record_value_1 (type
, 0, &parms
, false);
5964 /* Take into account pending integer fields. */
5965 if (parms
.intoffset
!= -1)
5967 unsigned int startbit
, endbit
;
5968 int intslots
, this_slotno
;
5970 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
5971 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5972 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5973 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
5975 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5977 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5978 /* We need to pass this field on the stack. */
5982 parms
.nregs
+= intslots
;
5984 nregs
= parms
.nregs
;
5986 /* Allocate the vector and handle some annoying special cases. */
5989 /* ??? Empty structure has no value? Duh? */
5992 /* Though there's nothing really to store, return a word register
5993 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5994 leads to breakage due to the fact that there are zero bytes to
5996 return gen_rtx_REG (mode
, regbase
);
6000 /* ??? C++ has structures with no fields, and yet a size. Give up
6001 for now and pass everything back in integer registers. */
6002 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6004 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
6005 nregs
= SPARC_INT_ARG_MAX
- slotno
;
6007 gcc_assert (nregs
!= 0);
6009 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
6011 /* If at least one field must be passed on the stack, generate
6012 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6013 also be passed on the stack. We can't do much better because the
6014 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6015 of structures for which the fields passed exclusively in registers
6016 are not at the beginning of the structure. */
6018 XVECEXP (parms
.ret
, 0, 0)
6019 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6021 /* Fill in the entries. */
6023 parms
.intoffset
= 0;
6024 function_arg_record_value_2 (type
, 0, &parms
, false);
6025 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
6027 gcc_assert (parms
.nregs
== nregs
);
6032 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6033 of the 64-bit ABI for passing and returning unions.
6034 Return an expression valid as a return value for the FUNCTION_ARG
6035 and TARGET_FUNCTION_VALUE.
6037 SIZE is the size in bytes of the union.
6038 MODE is the argument's machine mode.
6039 REGNO is the hard register the union will be passed in. */
6042 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
6045 int nwords
= ROUND_ADVANCE (size
), i
;
6048 /* See comment in previous function for empty structures. */
6050 return gen_rtx_REG (mode
, regno
);
6052 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6055 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6057 for (i
= 0; i
< nwords
; i
++)
6059 /* Unions are passed left-justified. */
6060 XVECEXP (regs
, 0, i
)
6061 = gen_rtx_EXPR_LIST (VOIDmode
,
6062 gen_rtx_REG (word_mode
, regno
),
6063 GEN_INT (UNITS_PER_WORD
* i
));
6070 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6071 for passing and returning large (BLKmode) vectors.
6072 Return an expression valid as a return value for the FUNCTION_ARG
6073 and TARGET_FUNCTION_VALUE.
6075 SIZE is the size in bytes of the vector (at least 8 bytes).
6076 REGNO is the FP hard register the vector will be passed in. */
6079 function_arg_vector_value (int size
, int regno
)
6081 int i
, nregs
= size
/ 8;
6084 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6086 for (i
= 0; i
< nregs
; i
++)
6088 XVECEXP (regs
, 0, i
)
6089 = gen_rtx_EXPR_LIST (VOIDmode
,
6090 gen_rtx_REG (DImode
, regno
+ 2*i
),
6097 /* Determine where to put an argument to a function.
6098 Value is zero to push the argument on the stack,
6099 or a hard register in which to store the argument.
6101 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6102 the preceding args and about the function being called.
6103 MODE is the argument's machine mode.
6104 TYPE is the data type of the argument (as a tree).
6105 This is null for libcalls where that information may
6107 NAMED is true if this argument is a named parameter
6108 (otherwise it is an extra parameter matching an ellipsis).
6109 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6110 TARGET_FUNCTION_INCOMING_ARG. */
6113 sparc_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
6114 const_tree type
, bool named
, bool incoming_p
)
6116 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6118 int regbase
= (incoming_p
6119 ? SPARC_INCOMING_INT_ARG_FIRST
6120 : SPARC_OUTGOING_INT_ARG_FIRST
);
6121 int slotno
, regno
, padding
;
6122 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6124 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6129 /* Vector types deserve special treatment because they are polymorphic wrt
6130 their mode, depending upon whether VIS instructions are enabled. */
6131 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6133 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6134 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6135 || (TARGET_ARCH64
&& size
<= 16));
6137 if (mode
== BLKmode
)
6138 return function_arg_vector_value (size
,
6139 SPARC_FP_ARG_FIRST
+ 2*slotno
);
6141 mclass
= MODE_FLOAT
;
6145 return gen_rtx_REG (mode
, regno
);
6147 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6148 and are promoted to registers if possible. */
6149 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6151 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6152 gcc_assert (size
<= 16);
6154 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6157 /* Unions up to 16 bytes in size are passed in integer registers. */
6158 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6160 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6161 gcc_assert (size
<= 16);
6163 return function_arg_union_value (size
, mode
, slotno
, regno
);
6166 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6167 but also have the slot allocated for them.
6168 If no prototype is in scope fp values in register slots get passed
6169 in two places, either fp regs and int regs or fp regs and memory. */
6170 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6171 && SPARC_FP_REG_P (regno
))
6173 rtx reg
= gen_rtx_REG (mode
, regno
);
6174 if (cum
->prototype_p
|| cum
->libcall_p
)
6176 /* "* 2" because fp reg numbers are recorded in 4 byte
6179 /* ??? This will cause the value to be passed in the fp reg and
6180 in the stack. When a prototype exists we want to pass the
6181 value in the reg but reserve space on the stack. That's an
6182 optimization, and is deferred [for a bit]. */
6183 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6184 return gen_rtx_PARALLEL (mode
,
6186 gen_rtx_EXPR_LIST (VOIDmode
,
6187 NULL_RTX
, const0_rtx
),
6188 gen_rtx_EXPR_LIST (VOIDmode
,
6192 /* ??? It seems that passing back a register even when past
6193 the area declared by REG_PARM_STACK_SPACE will allocate
6194 space appropriately, and will not copy the data onto the
6195 stack, exactly as we desire.
6197 This is due to locate_and_pad_parm being called in
6198 expand_call whenever reg_parm_stack_space > 0, which
6199 while beneficial to our example here, would seem to be
6200 in error from what had been intended. Ho hum... -- r~ */
6208 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6212 /* On incoming, we don't need to know that the value
6213 is passed in %f0 and %i0, and it confuses other parts
6214 causing needless spillage even on the simplest cases. */
6218 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6219 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6221 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6222 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6224 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6228 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6229 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6230 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6235 /* All other aggregate types are passed in an integer register in a mode
6236 corresponding to the size of the type. */
6237 else if (type
&& AGGREGATE_TYPE_P (type
))
6239 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6240 gcc_assert (size
<= 16);
6242 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6245 return gen_rtx_REG (mode
, regno
);
6248 /* Handle the TARGET_FUNCTION_ARG target hook. */
6251 sparc_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
6252 const_tree type
, bool named
)
6254 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6257 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6260 sparc_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
6261 const_tree type
, bool named
)
6263 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
6266 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6269 sparc_function_arg_boundary (enum machine_mode mode
, const_tree type
)
6271 return ((TARGET_ARCH64
6272 && (GET_MODE_ALIGNMENT (mode
) == 128
6273 || (type
&& TYPE_ALIGN (type
) == 128)))
6278 /* For an arg passed partly in registers and partly in memory,
6279 this is the number of bytes of registers used.
6280 For args passed entirely in registers or entirely in memory, zero.
6282 Any arg that starts in the first 6 regs but won't entirely fit in them
6283 needs partial registers on v8. On v9, structures with integer
6284 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6285 values that begin in the last fp reg [where "last fp reg" varies with the
6286 mode] will be split between that reg and memory. */
6289 sparc_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
6290 tree type
, bool named
)
6292 int slotno
, regno
, padding
;
6294 /* We pass false for incoming_p here, it doesn't matter. */
6295 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
6296 false, ®no
, &padding
);
6303 if ((slotno
+ (mode
== BLKmode
6304 ? ROUND_ADVANCE (int_size_in_bytes (type
))
6305 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
6306 > SPARC_INT_ARG_MAX
)
6307 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
6311 /* We are guaranteed by pass_by_reference that the size of the
6312 argument is not greater than 16 bytes, so we only need to return
6313 one word if the argument is partially passed in registers. */
6315 if (type
&& AGGREGATE_TYPE_P (type
))
6317 int size
= int_size_in_bytes (type
);
6319 if (size
> UNITS_PER_WORD
6320 && slotno
== SPARC_INT_ARG_MAX
- 1)
6321 return UNITS_PER_WORD
;
6323 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
6324 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6325 && ! (TARGET_FPU
&& named
)))
6327 /* The complex types are passed as packed types. */
6328 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6329 && slotno
== SPARC_INT_ARG_MAX
- 1)
6330 return UNITS_PER_WORD
;
6332 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6334 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
6336 return UNITS_PER_WORD
;
6343 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6344 Specify whether to pass the argument by reference. */
6347 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6348 enum machine_mode mode
, const_tree type
,
6349 bool named ATTRIBUTE_UNUSED
)
6352 /* Original SPARC 32-bit ABI says that structures and unions,
6353 and quad-precision floats are passed by reference. For Pascal,
6354 also pass arrays by reference. All other base types are passed
6357 Extended ABI (as implemented by the Sun compiler) says that all
6358 complex floats are passed by reference. Pass complex integers
6359 in registers up to 8 bytes. More generally, enforce the 2-word
6360 cap for passing arguments in registers.
6362 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6363 integers are passed like floats of the same size, that is in
6364 registers up to 8 bytes. Pass all vector floats by reference
6365 like structure and unions. */
6366 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6368 /* Catch CDImode, TFmode, DCmode and TCmode. */
6369 || GET_MODE_SIZE (mode
) > 8
6371 && TREE_CODE (type
) == VECTOR_TYPE
6372 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6374 /* Original SPARC 64-bit ABI says that structures and unions
6375 smaller than 16 bytes are passed in registers, as well as
6376 all other base types.
6378 Extended ABI (as implemented by the Sun compiler) says that
6379 complex floats are passed in registers up to 16 bytes. Pass
6380 all complex integers in registers up to 16 bytes. More generally,
6381 enforce the 2-word cap for passing arguments in registers.
6383 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6384 integers are passed like floats of the same size, that is in
6385 registers (up to 16 bytes). Pass all vector floats like structure
6388 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
6389 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6390 /* Catch CTImode and TCmode. */
6391 || GET_MODE_SIZE (mode
) > 16);
6394 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6395 Update the data in CUM to advance over an argument
6396 of mode MODE and data type TYPE.
6397 TYPE is null for libcalls where that information may not be available. */
6400 sparc_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
6401 const_tree type
, bool named
)
6403 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6406 /* We pass false for incoming_p here, it doesn't matter. */
6407 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
6409 /* If argument requires leading padding, add it. */
6410 cum
->words
+= padding
;
6414 cum
->words
+= (mode
!= BLKmode
6415 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6416 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6420 if (type
&& AGGREGATE_TYPE_P (type
))
6422 int size
= int_size_in_bytes (type
);
6426 else if (size
<= 16)
6428 else /* passed by reference */
6433 cum
->words
+= (mode
!= BLKmode
6434 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6435 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6440 /* Handle the FUNCTION_ARG_PADDING macro.
6441 For the 64 bit ABI structs are always stored left shifted in their
6445 function_arg_padding (enum machine_mode mode
, const_tree type
)
6447 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
6450 /* Fall back to the default. */
6451 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
6454 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6455 Specify whether to return the return value in memory. */
6458 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
6461 /* Original SPARC 32-bit ABI says that structures and unions,
6462 and quad-precision floats are returned in memory. All other
6463 base types are returned in registers.
6465 Extended ABI (as implemented by the Sun compiler) says that
6466 all complex floats are returned in registers (8 FP registers
6467 at most for '_Complex long double'). Return all complex integers
6468 in registers (4 at most for '_Complex long long').
6470 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6471 integers are returned like floats of the same size, that is in
6472 registers up to 8 bytes and in memory otherwise. Return all
6473 vector floats in memory like structure and unions; note that
6474 they always have BLKmode like the latter. */
6475 return (TYPE_MODE (type
) == BLKmode
6476 || TYPE_MODE (type
) == TFmode
6477 || (TREE_CODE (type
) == VECTOR_TYPE
6478 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6480 /* Original SPARC 64-bit ABI says that structures and unions
6481 smaller than 32 bytes are returned in registers, as well as
6482 all other base types.
6484 Extended ABI (as implemented by the Sun compiler) says that all
6485 complex floats are returned in registers (8 FP registers at most
6486 for '_Complex long double'). Return all complex integers in
6487 registers (4 at most for '_Complex TItype').
6489 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6490 integers are returned like floats of the same size, that is in
6491 registers. Return all vector floats like structure and unions;
6492 note that they always have BLKmode like the latter. */
6493 return (TYPE_MODE (type
) == BLKmode
6494 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
6497 /* Handle the TARGET_STRUCT_VALUE target hook.
6498 Return where to find the structure return value address. */
6501 sparc_struct_value_rtx (tree fndecl
, int incoming
)
6510 mem
= gen_frame_mem (Pmode
, plus_constant (frame_pointer_rtx
,
6511 STRUCT_VALUE_OFFSET
));
6513 mem
= gen_frame_mem (Pmode
, plus_constant (stack_pointer_rtx
,
6514 STRUCT_VALUE_OFFSET
));
6516 /* Only follow the SPARC ABI for fixed-size structure returns.
6517 Variable size structure returns are handled per the normal
6518 procedures in GCC. This is enabled by -mstd-struct-return */
6520 && sparc_std_struct_return
6521 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
6522 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
6524 /* We must check and adjust the return address, as it is
6525 optional as to whether the return object is really
6527 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
6528 rtx scratch
= gen_reg_rtx (SImode
);
6529 rtx endlab
= gen_label_rtx ();
6531 /* Calculate the return object size */
6532 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
6533 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
6534 /* Construct a temporary return value */
6536 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
6538 /* Implement SPARC 32-bit psABI callee return struct checking:
6540 Fetch the instruction where we will return to and see if
6541 it's an unimp instruction (the most significant 10 bits
6543 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
6544 plus_constant (ret_reg
, 8)));
6545 /* Assume the size is valid and pre-adjust */
6546 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6547 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
6549 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6550 /* Write the address of the memory pointed to by temp_val into
6551 the memory pointed to by mem */
6552 emit_move_insn (mem
, XEXP (temp_val
, 0));
6553 emit_label (endlab
);
6560 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6561 For v9, function return values are subject to the same rules as arguments,
6562 except that up to 32 bytes may be returned in registers. */
6565 sparc_function_value_1 (const_tree type
, enum machine_mode mode
,
6568 /* Beware that the two values are swapped here wrt function_arg. */
6569 int regbase
= (outgoing
6570 ? SPARC_INCOMING_INT_ARG_FIRST
6571 : SPARC_OUTGOING_INT_ARG_FIRST
);
6572 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6575 /* Vector types deserve special treatment because they are polymorphic wrt
6576 their mode, depending upon whether VIS instructions are enabled. */
6577 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6579 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6580 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6581 || (TARGET_ARCH64
&& size
<= 32));
6583 if (mode
== BLKmode
)
6584 return function_arg_vector_value (size
,
6585 SPARC_FP_ARG_FIRST
);
6587 mclass
= MODE_FLOAT
;
6590 if (TARGET_ARCH64
&& type
)
6592 /* Structures up to 32 bytes in size are returned in registers. */
6593 if (TREE_CODE (type
) == RECORD_TYPE
)
6595 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6596 gcc_assert (size
<= 32);
6598 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
6601 /* Unions up to 32 bytes in size are returned in integer registers. */
6602 else if (TREE_CODE (type
) == UNION_TYPE
)
6604 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6605 gcc_assert (size
<= 32);
6607 return function_arg_union_value (size
, mode
, 0, regbase
);
6610 /* Objects that require it are returned in FP registers. */
6611 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6614 /* All other aggregate types are returned in an integer register in a
6615 mode corresponding to the size of the type. */
6616 else if (AGGREGATE_TYPE_P (type
))
6618 /* All other aggregate types are passed in an integer register
6619 in a mode corresponding to the size of the type. */
6620 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6621 gcc_assert (size
<= 32);
6623 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6625 /* ??? We probably should have made the same ABI change in
6626 3.4.0 as the one we made for unions. The latter was
6627 required by the SCD though, while the former is not
6628 specified, so we favored compatibility and efficiency.
6630 Now we're stuck for aggregates larger than 16 bytes,
6631 because OImode vanished in the meantime. Let's not
6632 try to be unduly clever, and simply follow the ABI
6633 for unions in that case. */
6634 if (mode
== BLKmode
)
6635 return function_arg_union_value (size
, mode
, 0, regbase
);
6640 /* We should only have pointer and integer types at this point. This
6641 must match sparc_promote_function_mode. */
6642 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6646 /* We should only have pointer and integer types at this point. This must
6647 match sparc_promote_function_mode. */
6648 else if (TARGET_ARCH32
6649 && mclass
== MODE_INT
6650 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6653 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
6654 regno
= SPARC_FP_ARG_FIRST
;
6658 return gen_rtx_REG (mode
, regno
);
6661 /* Handle TARGET_FUNCTION_VALUE.
6662 On the SPARC, the value is found in the first "output" register, but the
6663 called function leaves it in the first "input" register. */
6666 sparc_function_value (const_tree valtype
,
6667 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
6670 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
6673 /* Handle TARGET_LIBCALL_VALUE. */
6676 sparc_libcall_value (enum machine_mode mode
,
6677 const_rtx fun ATTRIBUTE_UNUSED
)
6679 return sparc_function_value_1 (NULL_TREE
, mode
, false);
6682 /* Handle FUNCTION_VALUE_REGNO_P.
6683 On the SPARC, the first "output" reg is used for integer values, and the
6684 first floating point register is used for floating point values. */
6687 sparc_function_value_regno_p (const unsigned int regno
)
6689 return (regno
== 8 || regno
== 32);
6692 /* Do what is necessary for `va_start'. We look at the current function
6693 to determine if stdarg or varargs is used and return the address of
6694 the first unnamed parameter. */
6697 sparc_builtin_saveregs (void)
6699 int first_reg
= crtl
->args
.info
.words
;
6703 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
6704 emit_move_insn (gen_rtx_MEM (word_mode
,
6705 gen_rtx_PLUS (Pmode
,
6707 GEN_INT (FIRST_PARM_OFFSET (0)
6710 gen_rtx_REG (word_mode
,
6711 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
6713 address
= gen_rtx_PLUS (Pmode
,
6715 GEN_INT (FIRST_PARM_OFFSET (0)
6716 + UNITS_PER_WORD
* first_reg
));
6721 /* Implement `va_start' for stdarg. */
6724 sparc_va_start (tree valist
, rtx nextarg
)
6726 nextarg
= expand_builtin_saveregs ();
6727 std_expand_builtin_va_start (valist
, nextarg
);
6730 /* Implement `va_arg' for stdarg. */
6733 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6736 HOST_WIDE_INT size
, rsize
, align
;
6739 tree ptrtype
= build_pointer_type (type
);
6741 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6744 size
= rsize
= UNITS_PER_WORD
;
6750 size
= int_size_in_bytes (type
);
6751 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6756 /* For SPARC64, objects requiring 16-byte alignment get it. */
6757 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
6758 align
= 2 * UNITS_PER_WORD
;
6760 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6761 are left-justified in their slots. */
6762 if (AGGREGATE_TYPE_P (type
))
6765 size
= rsize
= UNITS_PER_WORD
;
6775 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
6776 incr
= fold_convert (sizetype
, incr
);
6777 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
6779 incr
= fold_convert (ptr_type_node
, incr
);
6782 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6785 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
6786 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
6790 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
6791 addr
= build_va_arg_indirect_ref (addr
);
6794 /* If the address isn't aligned properly for the type, we need a temporary.
6795 FIXME: This is inefficient, usually we can do this in registers. */
6796 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
6798 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6799 tree dest_addr
= build_fold_addr_expr (tmp
);
6800 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
6801 3, dest_addr
, addr
, size_int (rsize
));
6802 TREE_ADDRESSABLE (tmp
) = 1;
6803 gimplify_and_add (copy
, pre_p
);
6808 addr
= fold_convert (ptrtype
, addr
);
6810 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
6811 gimplify_assign (valist
, incr
, post_p
);
6813 return build_va_arg_indirect_ref (addr
);
6816 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6817 Specify whether the vector mode is supported by the hardware. */
6820 sparc_vector_mode_supported_p (enum machine_mode mode
)
6822 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
6825 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6827 static enum machine_mode
6828 sparc_preferred_simd_mode (enum machine_mode mode
)
6846 /* Return the string to output an unconditional branch to LABEL, which is
6847 the operand number of the label.
6849 DEST is the destination insn (i.e. the label), INSN is the source. */
6852 output_ubranch (rtx dest
, int label
, rtx insn
)
6854 static char string
[64];
6855 bool v9_form
= false;
6858 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
6860 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6861 - INSN_ADDRESSES (INSN_UID (insn
)));
6862 /* Leave some instructions for "slop". */
6863 if (delta
>= -260000 && delta
< 260000)
6868 strcpy (string
, "ba%*,pt\t%%xcc, ");
6870 strcpy (string
, "b%*\t");
6872 p
= strchr (string
, '\0');
6883 /* Return the string to output a conditional branch to LABEL, which is
6884 the operand number of the label. OP is the conditional expression.
6885 XEXP (OP, 0) is assumed to be a condition code register (integer or
6886 floating point) and its mode specifies what kind of comparison we made.
6888 DEST is the destination insn (i.e. the label), INSN is the source.
6890 REVERSED is nonzero if we should reverse the sense of the comparison.
6892 ANNUL is nonzero if we should generate an annulling branch. */
6895 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
6898 static char string
[64];
6899 enum rtx_code code
= GET_CODE (op
);
6900 rtx cc_reg
= XEXP (op
, 0);
6901 enum machine_mode mode
= GET_MODE (cc_reg
);
6902 const char *labelno
, *branch
;
6903 int spaces
= 8, far
;
6906 /* v9 branches are limited to +-1MB. If it is too far away,
6919 fbne,a,pn %fcc2, .LC29
6927 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
6930 /* Reversal of FP compares takes care -- an ordered compare
6931 becomes an unordered compare and vice versa. */
6932 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6933 code
= reverse_condition_maybe_unordered (code
);
6935 code
= reverse_condition (code
);
6938 /* Start by writing the branch condition. */
6939 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6990 /* ??? !v9: FP branches cannot be preceded by another floating point
6991 insn. Because there is currently no concept of pre-delay slots,
6992 we can fix this only by always emitting a nop before a floating
6997 strcpy (string
, "nop\n\t");
6998 strcat (string
, branch
);
7011 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7023 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7044 strcpy (string
, branch
);
7046 spaces
-= strlen (branch
);
7047 p
= strchr (string
, '\0');
7049 /* Now add the annulling, the label, and a possible noop. */
7062 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7064 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7065 - INSN_ADDRESSES (INSN_UID (insn
)));
7066 /* Leave some instructions for "slop". */
7067 if (delta
< -260000 || delta
>= 260000)
7071 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7073 static char v9_fcc_labelno
[] = "%%fccX, ";
7074 /* Set the char indicating the number of the fcc reg to use. */
7075 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7076 labelno
= v9_fcc_labelno
;
7079 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7083 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7085 labelno
= "%%xcc, ";
7090 labelno
= "%%icc, ";
7095 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7098 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7111 strcpy (p
, labelno
);
7112 p
= strchr (p
, '\0');
7115 strcpy (p
, ".+12\n\t nop\n\tb\t");
7116 /* Skip the next insn if requested or
7117 if we know that it will be a nop. */
7118 if (annul
|| ! final_sequence
)
7132 /* Emit a library call comparison between floating point X and Y.
7133 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7134 Return the new operator to be used in the comparison sequence.
7136 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7137 values as arguments instead of the TFmode registers themselves,
7138 that's why we cannot call emit_float_lib_cmp. */
7141 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7144 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7145 enum machine_mode mode
;
7146 enum rtx_code new_comparison
;
7151 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7155 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7159 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7163 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7167 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7171 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7182 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7195 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7196 emit_move_insn (slot0
, x
);
7203 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7204 emit_move_insn (slot1
, y
);
7207 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7208 emit_library_call (libfunc
, LCT_NORMAL
,
7210 XEXP (slot0
, 0), Pmode
,
7211 XEXP (slot1
, 0), Pmode
);
7216 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7217 emit_library_call (libfunc
, LCT_NORMAL
,
7219 x
, TFmode
, y
, TFmode
);
7224 /* Immediately move the result of the libcall into a pseudo
7225 register so reload doesn't clobber the value if it needs
7226 the return register for a spill reg. */
7227 result
= gen_reg_rtx (mode
);
7228 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
7233 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
7236 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
7237 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
7240 new_comparison
= (comparison
== UNGT
? GT
: NE
);
7241 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
7243 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
7245 tem
= gen_reg_rtx (mode
);
7247 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
7249 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
7250 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
7253 tem
= gen_reg_rtx (mode
);
7255 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
7257 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
7258 tem2
= gen_reg_rtx (mode
);
7260 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
7262 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
7263 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
7264 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
7270 /* Generate an unsigned DImode to FP conversion. This is the same code
7271 optabs would emit if we didn't have TFmode patterns. */
7274 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
7276 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
7279 in
= force_reg (DImode
, operands
[1]);
7280 neglab
= gen_label_rtx ();
7281 donelab
= gen_label_rtx ();
7282 i0
= gen_reg_rtx (DImode
);
7283 i1
= gen_reg_rtx (DImode
);
7284 f0
= gen_reg_rtx (mode
);
7286 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
7288 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
7289 emit_jump_insn (gen_jump (donelab
));
7292 emit_label (neglab
);
7294 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
7295 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
7296 emit_insn (gen_iordi3 (i0
, i0
, i1
));
7297 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
7298 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
7300 emit_label (donelab
);
7303 /* Generate an FP to unsigned DImode conversion. This is the same code
7304 optabs would emit if we didn't have TFmode patterns. */
7307 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
7309 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
7312 in
= force_reg (mode
, operands
[1]);
7313 neglab
= gen_label_rtx ();
7314 donelab
= gen_label_rtx ();
7315 i0
= gen_reg_rtx (DImode
);
7316 i1
= gen_reg_rtx (DImode
);
7317 limit
= gen_reg_rtx (mode
);
7318 f0
= gen_reg_rtx (mode
);
7320 emit_move_insn (limit
,
7321 CONST_DOUBLE_FROM_REAL_VALUE (
7322 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
7323 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
7325 emit_insn (gen_rtx_SET (VOIDmode
,
7327 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
7328 emit_jump_insn (gen_jump (donelab
));
7331 emit_label (neglab
);
7333 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
7334 emit_insn (gen_rtx_SET (VOIDmode
,
7336 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
7337 emit_insn (gen_movdi (i1
, const1_rtx
));
7338 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
7339 emit_insn (gen_xordi3 (out
, i0
, i1
));
7341 emit_label (donelab
);
7344 /* Return the string to output a conditional branch to LABEL, testing
7345 register REG. LABEL is the operand number of the label; REG is the
7346 operand number of the reg. OP is the conditional expression. The mode
7347 of REG says what kind of comparison we made.
7349 DEST is the destination insn (i.e. the label), INSN is the source.
7351 REVERSED is nonzero if we should reverse the sense of the comparison.
7353 ANNUL is nonzero if we should generate an annulling branch. */
7356 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
7357 int annul
, rtx insn
)
7359 static char string
[64];
7360 enum rtx_code code
= GET_CODE (op
);
7361 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
7366 /* branch on register are limited to +-128KB. If it is too far away,
7379 brgez,a,pn %o1, .LC29
7385 ba,pt %xcc, .LC29 */
7387 far
= get_attr_length (insn
) >= 3;
7389 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7391 code
= reverse_condition (code
);
7393 /* Only 64 bit versions of these instructions exist. */
7394 gcc_assert (mode
== DImode
);
7396 /* Start by writing the branch condition. */
7401 strcpy (string
, "brnz");
7405 strcpy (string
, "brz");
7409 strcpy (string
, "brgez");
7413 strcpy (string
, "brlz");
7417 strcpy (string
, "brlez");
7421 strcpy (string
, "brgz");
7428 p
= strchr (string
, '\0');
7430 /* Now add the annulling, reg, label, and nop. */
7437 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7440 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7445 *p
= p
< string
+ 8 ? '\t' : ' ';
7453 int veryfar
= 1, delta
;
7455 if (INSN_ADDRESSES_SET_P ())
7457 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7458 - INSN_ADDRESSES (INSN_UID (insn
)));
7459 /* Leave some instructions for "slop". */
7460 if (delta
>= -260000 && delta
< 260000)
7464 strcpy (p
, ".+12\n\t nop\n\t");
7465 /* Skip the next insn if requested or
7466 if we know that it will be a nop. */
7467 if (annul
|| ! final_sequence
)
7477 strcpy (p
, "ba,pt\t%%xcc, ");
7491 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7492 Such instructions cannot be used in the delay slot of return insn on v9.
7493 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7497 epilogue_renumber (register rtx
*where
, int test
)
7499 register const char *fmt
;
7501 register enum rtx_code code
;
7506 code
= GET_CODE (*where
);
7511 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
7513 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
7514 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
7522 /* Do not replace the frame pointer with the stack pointer because
7523 it can cause the delayed instruction to load below the stack.
7524 This occurs when instructions like:
7526 (set (reg/i:SI 24 %i0)
7527 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7528 (const_int -20 [0xffffffec])) 0))
7530 are in the return delayed slot. */
7532 if (GET_CODE (XEXP (*where
, 0)) == REG
7533 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
7534 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
7535 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
7540 if (SPARC_STACK_BIAS
7541 && GET_CODE (XEXP (*where
, 0)) == REG
7542 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
7550 fmt
= GET_RTX_FORMAT (code
);
7552 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7557 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
7558 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
7561 else if (fmt
[i
] == 'e'
7562 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
7568 /* Leaf functions and non-leaf functions have different needs. */
7571 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
7574 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
7576 static const int *const reg_alloc_orders
[] = {
7577 reg_leaf_alloc_order
,
7578 reg_nonleaf_alloc_order
};
7581 order_regs_for_local_alloc (void)
7583 static int last_order_nonleaf
= 1;
7585 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
7587 last_order_nonleaf
= !last_order_nonleaf
;
7588 memcpy ((char *) reg_alloc_order
,
7589 (const char *) reg_alloc_orders
[last_order_nonleaf
],
7590 FIRST_PSEUDO_REGISTER
* sizeof (int));
7594 /* Return 1 if REG and MEM are legitimate enough to allow the various
7595 mem<-->reg splits to be run. */
7598 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
7600 /* Punt if we are here by mistake. */
7601 gcc_assert (reload_completed
);
7603 /* We must have an offsettable memory reference. */
7604 if (! offsettable_memref_p (mem
))
7607 /* If we have legitimate args for ldd/std, we do not want
7608 the split to happen. */
7609 if ((REGNO (reg
) % 2) == 0
7610 && mem_min_alignment (mem
, 8))
7617 /* Return 1 if x and y are some kind of REG and they refer to
7618 different hard registers. This test is guaranteed to be
7619 run after reload. */
7622 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
7624 if (GET_CODE (x
) != REG
)
7626 if (GET_CODE (y
) != REG
)
7628 if (REGNO (x
) == REGNO (y
))
7633 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7634 This makes them candidates for using ldd and std insns.
7636 Note reg1 and reg2 *must* be hard registers. */
7639 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
7641 /* We might have been passed a SUBREG. */
7642 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
7645 if (REGNO (reg1
) % 2 != 0)
7648 /* Integer ldd is deprecated in SPARC V9 */
7649 if (TARGET_V9
&& REGNO (reg1
) < 32)
7652 return (REGNO (reg1
) == REGNO (reg2
) - 1);
7655 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7658 This can only happen when addr1 and addr2, the addresses in mem1
7659 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7660 addr1 must also be aligned on a 64-bit boundary.
7662 Also iff dependent_reg_rtx is not null it should not be used to
7663 compute the address for mem1, i.e. we cannot optimize a sequence
7675 But, note that the transformation from:
7680 is perfectly fine. Thus, the peephole2 patterns always pass us
7681 the destination register of the first load, never the second one.
7683 For stores we don't have a similar problem, so dependent_reg_rtx is
7687 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
7691 HOST_WIDE_INT offset1
;
7693 /* The mems cannot be volatile. */
7694 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
7697 /* MEM1 should be aligned on a 64-bit boundary. */
7698 if (MEM_ALIGN (mem1
) < 64)
7701 addr1
= XEXP (mem1
, 0);
7702 addr2
= XEXP (mem2
, 0);
7704 /* Extract a register number and offset (if used) from the first addr. */
7705 if (GET_CODE (addr1
) == PLUS
)
7707 /* If not a REG, return zero. */
7708 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
7712 reg1
= REGNO (XEXP (addr1
, 0));
7713 /* The offset must be constant! */
7714 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
7716 offset1
= INTVAL (XEXP (addr1
, 1));
7719 else if (GET_CODE (addr1
) != REG
)
7723 reg1
= REGNO (addr1
);
7724 /* This was a simple (mem (reg)) expression. Offset is 0. */
7728 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7729 if (GET_CODE (addr2
) != PLUS
)
7732 if (GET_CODE (XEXP (addr2
, 0)) != REG
7733 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
7736 if (reg1
!= REGNO (XEXP (addr2
, 0)))
7739 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
7742 /* The first offset must be evenly divisible by 8 to ensure the
7743 address is 64 bit aligned. */
7744 if (offset1
% 8 != 0)
7747 /* The offset for the second addr must be 4 more than the first addr. */
7748 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
7751 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7756 /* Return 1 if reg is a pseudo, or is the first register in
7757 a hard register pair. This makes it suitable for use in
7758 ldd and std insns. */
7761 register_ok_for_ldd (rtx reg
)
7763 /* We might have been passed a SUBREG. */
7767 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
7768 return (REGNO (reg
) % 2 == 0);
7773 /* Return 1 if OP is a memory whose address is known to be
7774 aligned to 8-byte boundary, or a pseudo during reload.
7775 This makes it suitable for use in ldd and std insns. */
7778 memory_ok_for_ldd (rtx op
)
7782 /* In 64-bit mode, we assume that the address is word-aligned. */
7783 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
7786 if ((reload_in_progress
|| reload_completed
)
7787 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
7790 else if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
7792 if (!(reload_in_progress
&& reg_renumber
[REGNO (op
)] < 0))
7801 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7804 sparc_print_operand_punct_valid_p (unsigned char code
)
7817 /* Implement TARGET_PRINT_OPERAND.
7818 Print operand X (an rtx) in assembler syntax to file FILE.
7819 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7820 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7823 sparc_print_operand (FILE *file
, rtx x
, int code
)
7828 /* Output an insn in a delay slot. */
7830 sparc_indent_opcode
= 1;
7832 fputs ("\n\t nop", file
);
7835 /* Output an annul flag if there's nothing for the delay slot and we
7836 are optimizing. This is always used with '(' below.
7837 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7838 this is a dbx bug. So, we only do this when optimizing.
7839 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7840 Always emit a nop in case the next instruction is a branch. */
7841 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7845 /* Output a 'nop' if there's nothing for the delay slot and we are
7846 not optimizing. This is always used with '*' above. */
7847 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7848 fputs ("\n\t nop", file
);
7849 else if (final_sequence
)
7850 sparc_indent_opcode
= 1;
7853 /* Output the right displacement from the saved PC on function return.
7854 The caller may have placed an "unimp" insn immediately after the call
7855 so we have to account for it. This insn is used in the 32-bit ABI
7856 when calling a function that returns a non zero-sized structure. The
7857 64-bit ABI doesn't have it. Be careful to have this test be the same
7858 as that for the call. The exception is when sparc_std_struct_return
7859 is enabled, the psABI is followed exactly and the adjustment is made
7860 by the code in sparc_struct_value_rtx. The call emitted is the same
7861 when sparc_std_struct_return is enabled. */
7863 && cfun
->returns_struct
7864 && !sparc_std_struct_return
7865 && DECL_SIZE (DECL_RESULT (current_function_decl
))
7866 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
7868 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
7874 /* Output the Embedded Medium/Anywhere code model base register. */
7875 fputs (EMBMEDANY_BASE_REG
, file
);
7878 /* Print some local dynamic TLS name. */
7879 assemble_name (file
, get_some_local_dynamic_name ());
7883 /* Adjust the operand to take into account a RESTORE operation. */
7884 if (GET_CODE (x
) == CONST_INT
)
7886 else if (GET_CODE (x
) != REG
)
7887 output_operand_lossage ("invalid %%Y operand");
7888 else if (REGNO (x
) < 8)
7889 fputs (reg_names
[REGNO (x
)], file
);
7890 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
7891 fputs (reg_names
[REGNO (x
)-16], file
);
7893 output_operand_lossage ("invalid %%Y operand");
7896 /* Print out the low order register name of a register pair. */
7897 if (WORDS_BIG_ENDIAN
)
7898 fputs (reg_names
[REGNO (x
)+1], file
);
7900 fputs (reg_names
[REGNO (x
)], file
);
7903 /* Print out the high order register name of a register pair. */
7904 if (WORDS_BIG_ENDIAN
)
7905 fputs (reg_names
[REGNO (x
)], file
);
7907 fputs (reg_names
[REGNO (x
)+1], file
);
7910 /* Print out the second register name of a register pair or quad.
7911 I.e., R (%o0) => %o1. */
7912 fputs (reg_names
[REGNO (x
)+1], file
);
7915 /* Print out the third register name of a register quad.
7916 I.e., S (%o0) => %o2. */
7917 fputs (reg_names
[REGNO (x
)+2], file
);
7920 /* Print out the fourth register name of a register quad.
7921 I.e., T (%o0) => %o3. */
7922 fputs (reg_names
[REGNO (x
)+3], file
);
7925 /* Print a condition code register. */
7926 if (REGNO (x
) == SPARC_ICC_REG
)
7928 /* We don't handle CC[X]_NOOVmode because they're not supposed
7930 if (GET_MODE (x
) == CCmode
)
7931 fputs ("%icc", file
);
7932 else if (GET_MODE (x
) == CCXmode
)
7933 fputs ("%xcc", file
);
7938 /* %fccN register */
7939 fputs (reg_names
[REGNO (x
)], file
);
7942 /* Print the operand's address only. */
7943 output_address (XEXP (x
, 0));
7946 /* In this case we need a register. Use %g0 if the
7947 operand is const0_rtx. */
7949 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
7951 fputs ("%g0", file
);
7958 switch (GET_CODE (x
))
7960 case IOR
: fputs ("or", file
); break;
7961 case AND
: fputs ("and", file
); break;
7962 case XOR
: fputs ("xor", file
); break;
7963 default: output_operand_lossage ("invalid %%A operand");
7968 switch (GET_CODE (x
))
7970 case IOR
: fputs ("orn", file
); break;
7971 case AND
: fputs ("andn", file
); break;
7972 case XOR
: fputs ("xnor", file
); break;
7973 default: output_operand_lossage ("invalid %%B operand");
7977 /* These are used by the conditional move instructions. */
7981 enum rtx_code rc
= GET_CODE (x
);
7985 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
7986 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7987 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
7989 rc
= reverse_condition (GET_CODE (x
));
7993 case NE
: fputs ("ne", file
); break;
7994 case EQ
: fputs ("e", file
); break;
7995 case GE
: fputs ("ge", file
); break;
7996 case GT
: fputs ("g", file
); break;
7997 case LE
: fputs ("le", file
); break;
7998 case LT
: fputs ("l", file
); break;
7999 case GEU
: fputs ("geu", file
); break;
8000 case GTU
: fputs ("gu", file
); break;
8001 case LEU
: fputs ("leu", file
); break;
8002 case LTU
: fputs ("lu", file
); break;
8003 case LTGT
: fputs ("lg", file
); break;
8004 case UNORDERED
: fputs ("u", file
); break;
8005 case ORDERED
: fputs ("o", file
); break;
8006 case UNLT
: fputs ("ul", file
); break;
8007 case UNLE
: fputs ("ule", file
); break;
8008 case UNGT
: fputs ("ug", file
); break;
8009 case UNGE
: fputs ("uge", file
); break;
8010 case UNEQ
: fputs ("ue", file
); break;
8011 default: output_operand_lossage (code
== 'c'
8012 ? "invalid %%c operand"
8013 : "invalid %%C operand");
8018 /* These are used by the movr instruction pattern. */
8022 enum rtx_code rc
= (code
== 'd'
8023 ? reverse_condition (GET_CODE (x
))
8027 case NE
: fputs ("ne", file
); break;
8028 case EQ
: fputs ("e", file
); break;
8029 case GE
: fputs ("gez", file
); break;
8030 case LT
: fputs ("lz", file
); break;
8031 case LE
: fputs ("lez", file
); break;
8032 case GT
: fputs ("gz", file
); break;
8033 default: output_operand_lossage (code
== 'd'
8034 ? "invalid %%d operand"
8035 : "invalid %%D operand");
8042 /* Print a sign-extended character. */
8043 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
8044 fprintf (file
, "%d", i
);
8049 /* Operand must be a MEM; write its address. */
8050 if (GET_CODE (x
) != MEM
)
8051 output_operand_lossage ("invalid %%f operand");
8052 output_address (XEXP (x
, 0));
8057 /* Print a sign-extended 32-bit value. */
8059 if (GET_CODE(x
) == CONST_INT
)
8061 else if (GET_CODE(x
) == CONST_DOUBLE
)
8062 i
= CONST_DOUBLE_LOW (x
);
8065 output_operand_lossage ("invalid %%s operand");
8068 i
= trunc_int_for_mode (i
, SImode
);
8069 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8074 /* Do nothing special. */
8078 /* Undocumented flag. */
8079 output_operand_lossage ("invalid operand output code");
8082 if (GET_CODE (x
) == REG
)
8083 fputs (reg_names
[REGNO (x
)], file
);
8084 else if (GET_CODE (x
) == MEM
)
8087 /* Poor Sun assembler doesn't understand absolute addressing. */
8088 if (CONSTANT_P (XEXP (x
, 0)))
8089 fputs ("%g0+", file
);
8090 output_address (XEXP (x
, 0));
8093 else if (GET_CODE (x
) == HIGH
)
8095 fputs ("%hi(", file
);
8096 output_addr_const (file
, XEXP (x
, 0));
8099 else if (GET_CODE (x
) == LO_SUM
)
8101 sparc_print_operand (file
, XEXP (x
, 0), 0);
8102 if (TARGET_CM_MEDMID
)
8103 fputs ("+%l44(", file
);
8105 fputs ("+%lo(", file
);
8106 output_addr_const (file
, XEXP (x
, 1));
8109 else if (GET_CODE (x
) == CONST_DOUBLE
8110 && (GET_MODE (x
) == VOIDmode
8111 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
8113 if (CONST_DOUBLE_HIGH (x
) == 0)
8114 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
8115 else if (CONST_DOUBLE_HIGH (x
) == -1
8116 && CONST_DOUBLE_LOW (x
) < 0)
8117 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
8119 output_operand_lossage ("long long constant not a valid immediate operand");
8121 else if (GET_CODE (x
) == CONST_DOUBLE
)
8122 output_operand_lossage ("floating point constant not a valid immediate operand");
8123 else { output_addr_const (file
, x
); }
8126 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8129 sparc_print_operand_address (FILE *file
, rtx x
)
8131 register rtx base
, index
= 0;
8133 register rtx addr
= x
;
8136 fputs (reg_names
[REGNO (addr
)], file
);
8137 else if (GET_CODE (addr
) == PLUS
)
8139 if (CONST_INT_P (XEXP (addr
, 0)))
8140 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
8141 else if (CONST_INT_P (XEXP (addr
, 1)))
8142 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
8144 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
8145 if (GET_CODE (base
) == LO_SUM
)
8147 gcc_assert (USE_AS_OFFSETABLE_LO10
8149 && ! TARGET_CM_MEDMID
);
8150 output_operand (XEXP (base
, 0), 0);
8151 fputs ("+%lo(", file
);
8152 output_address (XEXP (base
, 1));
8153 fprintf (file
, ")+%d", offset
);
8157 fputs (reg_names
[REGNO (base
)], file
);
8159 fprintf (file
, "%+d", offset
);
8160 else if (REG_P (index
))
8161 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
8162 else if (GET_CODE (index
) == SYMBOL_REF
8163 || GET_CODE (index
) == LABEL_REF
8164 || GET_CODE (index
) == CONST
)
8165 fputc ('+', file
), output_addr_const (file
, index
);
8166 else gcc_unreachable ();
8169 else if (GET_CODE (addr
) == MINUS
8170 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
8172 output_addr_const (file
, XEXP (addr
, 0));
8174 output_addr_const (file
, XEXP (addr
, 1));
8175 fputs ("-.)", file
);
8177 else if (GET_CODE (addr
) == LO_SUM
)
8179 output_operand (XEXP (addr
, 0), 0);
8180 if (TARGET_CM_MEDMID
)
8181 fputs ("+%l44(", file
);
8183 fputs ("+%lo(", file
);
8184 output_address (XEXP (addr
, 1));
8188 && GET_CODE (addr
) == CONST
8189 && GET_CODE (XEXP (addr
, 0)) == MINUS
8190 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
8191 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
8192 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
8194 addr
= XEXP (addr
, 0);
8195 output_addr_const (file
, XEXP (addr
, 0));
8196 /* Group the args of the second CONST in parenthesis. */
8198 /* Skip past the second CONST--it does nothing for us. */
8199 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
8200 /* Close the parenthesis. */
8205 output_addr_const (file
, addr
);
8209 /* Target hook for assembling integer objects. The sparc version has
8210 special handling for aligned DI-mode objects. */
8213 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
8215 /* ??? We only output .xword's for symbols and only then in environments
8216 where the assembler can handle them. */
8217 if (aligned_p
&& size
== 8
8218 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
8222 assemble_integer_with_op ("\t.xword\t", x
);
8227 assemble_aligned_integer (4, const0_rtx
);
8228 assemble_aligned_integer (4, x
);
8232 return default_assemble_integer (x
, size
, aligned_p
);
8235 /* Return the value of a code used in the .proc pseudo-op that says
8236 what kind of result this function returns. For non-C types, we pick
8237 the closest C type. */
8239 #ifndef SHORT_TYPE_SIZE
8240 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8243 #ifndef INT_TYPE_SIZE
8244 #define INT_TYPE_SIZE BITS_PER_WORD
8247 #ifndef LONG_TYPE_SIZE
8248 #define LONG_TYPE_SIZE BITS_PER_WORD
8251 #ifndef LONG_LONG_TYPE_SIZE
8252 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8255 #ifndef FLOAT_TYPE_SIZE
8256 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8259 #ifndef DOUBLE_TYPE_SIZE
8260 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8263 #ifndef LONG_DOUBLE_TYPE_SIZE
8264 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8268 sparc_type_code (register tree type
)
8270 register unsigned long qualifiers
= 0;
8271 register unsigned shift
;
8273 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8274 setting more, since some assemblers will give an error for this. Also,
8275 we must be careful to avoid shifts of 32 bits or more to avoid getting
8276 unpredictable results. */
8278 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
8280 switch (TREE_CODE (type
))
8286 qualifiers
|= (3 << shift
);
8291 qualifiers
|= (2 << shift
);
8295 case REFERENCE_TYPE
:
8297 qualifiers
|= (1 << shift
);
8301 return (qualifiers
| 8);
8304 case QUAL_UNION_TYPE
:
8305 return (qualifiers
| 9);
8308 return (qualifiers
| 10);
8311 return (qualifiers
| 16);
8314 /* If this is a range type, consider it to be the underlying
8316 if (TREE_TYPE (type
) != 0)
8319 /* Carefully distinguish all the standard types of C,
8320 without messing up if the language is not C. We do this by
8321 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8322 look at both the names and the above fields, but that's redundant.
8323 Any type whose size is between two C types will be considered
8324 to be the wider of the two types. Also, we do not have a
8325 special code to use for "long long", so anything wider than
8326 long is treated the same. Note that we can't distinguish
8327 between "int" and "long" in this code if they are the same
8328 size, but that's fine, since neither can the assembler. */
8330 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
8331 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
8333 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
8334 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
8336 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
8337 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
8340 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
8343 /* If this is a range type, consider it to be the underlying
8345 if (TREE_TYPE (type
) != 0)
8348 /* Carefully distinguish all the standard types of C,
8349 without messing up if the language is not C. */
8351 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
8352 return (qualifiers
| 6);
8355 return (qualifiers
| 7);
8357 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
8358 /* ??? We need to distinguish between double and float complex types,
8359 but I don't know how yet because I can't reach this code from
8360 existing front-ends. */
8361 return (qualifiers
| 7); /* Who knows? */
8364 case BOOLEAN_TYPE
: /* Boolean truth value type. */
8370 gcc_unreachable (); /* Not a type! */
8377 /* Nested function support. */
8379 /* Emit RTL insns to initialize the variable parts of a trampoline.
8380 FNADDR is an RTX for the address of the function's pure code.
8381 CXT is an RTX for the static chain value for the function.
8383 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8384 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8385 (to store insns). This is a bit excessive. Perhaps a different
8386 mechanism would be better here.
8388 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8391 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8393 /* SPARC 32-bit trampoline:
8396 sethi %hi(static), %g2
8398 or %g2, %lo(static), %g2
8400 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8401 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8405 (adjust_address (m_tramp
, SImode
, 0),
8406 expand_binop (SImode
, ior_optab
,
8407 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
8408 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
8409 NULL_RTX
, 1, OPTAB_DIRECT
));
8412 (adjust_address (m_tramp
, SImode
, 4),
8413 expand_binop (SImode
, ior_optab
,
8414 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
8415 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
8416 NULL_RTX
, 1, OPTAB_DIRECT
));
8419 (adjust_address (m_tramp
, SImode
, 8),
8420 expand_binop (SImode
, ior_optab
,
8421 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
8422 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
8423 NULL_RTX
, 1, OPTAB_DIRECT
));
8426 (adjust_address (m_tramp
, SImode
, 12),
8427 expand_binop (SImode
, ior_optab
,
8428 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
8429 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
8430 NULL_RTX
, 1, OPTAB_DIRECT
));
8432 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8433 aligned on a 16 byte boundary so one flush clears it all. */
8434 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
8435 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8436 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8437 && sparc_cpu
!= PROCESSOR_NIAGARA
8438 && sparc_cpu
!= PROCESSOR_NIAGARA2
8439 && sparc_cpu
!= PROCESSOR_NIAGARA3
8440 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8441 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
8443 /* Call __enable_execute_stack after writing onto the stack to make sure
8444 the stack address is accessible. */
8445 #ifdef HAVE_ENABLE_EXECUTE_STACK
8446 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8447 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8452 /* The 64-bit version is simpler because it makes more sense to load the
8453 values as "immediate" data out of the trampoline. It's also easier since
8454 we can read the PC without clobbering a register. */
8457 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8459 /* SPARC 64-bit trampoline:
8468 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
8469 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
8470 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
8471 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
8472 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
8473 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
8474 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
8475 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
8476 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
8477 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
8478 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
8480 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8481 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8482 && sparc_cpu
!= PROCESSOR_NIAGARA
8483 && sparc_cpu
!= PROCESSOR_NIAGARA2
8484 && sparc_cpu
!= PROCESSOR_NIAGARA3
8485 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8486 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
8488 /* Call __enable_execute_stack after writing onto the stack to make sure
8489 the stack address is accessible. */
8490 #ifdef HAVE_ENABLE_EXECUTE_STACK
8491 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8492 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8496 /* Worker for TARGET_TRAMPOLINE_INIT. */
8499 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
8501 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
8502 cxt
= force_reg (Pmode
, cxt
);
8504 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8506 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8509 /* Adjust the cost of a scheduling dependency. Return the new cost of
8510 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8513 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8515 enum attr_type insn_type
;
8517 if (! recog_memoized (insn
))
8520 insn_type
= get_attr_type (insn
);
8522 if (REG_NOTE_KIND (link
) == 0)
8524 /* Data dependency; DEP_INSN writes a register that INSN reads some
8527 /* if a load, then the dependence must be on the memory address;
8528 add an extra "cycle". Note that the cost could be two cycles
8529 if the reg was written late in an instruction group; we ca not tell
8531 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
8534 /* Get the delay only if the address of the store is the dependence. */
8535 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
8537 rtx pat
= PATTERN(insn
);
8538 rtx dep_pat
= PATTERN (dep_insn
);
8540 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8541 return cost
; /* This should not happen! */
8543 /* The dependency between the two instructions was on the data that
8544 is being stored. Assume that this implies that the address of the
8545 store is not dependent. */
8546 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8549 return cost
+ 3; /* An approximation. */
8552 /* A shift instruction cannot receive its data from an instruction
8553 in the same cycle; add a one cycle penalty. */
8554 if (insn_type
== TYPE_SHIFT
)
8555 return cost
+ 3; /* Split before cascade into shift. */
8559 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8560 INSN writes some cycles later. */
8562 /* These are only significant for the fpu unit; writing a fp reg before
8563 the fpu has finished with it stalls the processor. */
8565 /* Reusing an integer register causes no problems. */
8566 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8574 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8576 enum attr_type insn_type
, dep_type
;
8577 rtx pat
= PATTERN(insn
);
8578 rtx dep_pat
= PATTERN (dep_insn
);
8580 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
8583 insn_type
= get_attr_type (insn
);
8584 dep_type
= get_attr_type (dep_insn
);
8586 switch (REG_NOTE_KIND (link
))
8589 /* Data dependency; DEP_INSN writes a register that INSN reads some
8596 /* Get the delay iff the address of the store is the dependence. */
8597 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8600 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8607 /* If a load, then the dependence must be on the memory address. If
8608 the addresses aren't equal, then it might be a false dependency */
8609 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
8611 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
8612 || GET_CODE (SET_DEST (dep_pat
)) != MEM
8613 || GET_CODE (SET_SRC (pat
)) != MEM
8614 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
8615 XEXP (SET_SRC (pat
), 0)))
8623 /* Compare to branch latency is 0. There is no benefit from
8624 separating compare and branch. */
8625 if (dep_type
== TYPE_COMPARE
)
8627 /* Floating point compare to branch latency is less than
8628 compare to conditional move. */
8629 if (dep_type
== TYPE_FPCMP
)
8638 /* Anti-dependencies only penalize the fpu unit. */
8639 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8651 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
8655 case PROCESSOR_SUPERSPARC
:
8656 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
8658 case PROCESSOR_HYPERSPARC
:
8659 case PROCESSOR_SPARCLITE86X
:
8660 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
8669 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
8670 int sched_verbose ATTRIBUTE_UNUSED
,
8671 int max_ready ATTRIBUTE_UNUSED
)
8675 sparc_use_sched_lookahead (void)
8677 if (sparc_cpu
== PROCESSOR_NIAGARA
8678 || sparc_cpu
== PROCESSOR_NIAGARA2
8679 || sparc_cpu
== PROCESSOR_NIAGARA3
8680 || sparc_cpu
== PROCESSOR_NIAGARA4
)
8682 if (sparc_cpu
== PROCESSOR_ULTRASPARC
8683 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8685 if ((1 << sparc_cpu
) &
8686 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
8687 (1 << PROCESSOR_SPARCLITE86X
)))
8693 sparc_issue_rate (void)
8697 case PROCESSOR_NIAGARA
:
8698 case PROCESSOR_NIAGARA2
:
8699 case PROCESSOR_NIAGARA3
:
8700 case PROCESSOR_NIAGARA4
:
8704 /* Assume V9 processors are capable of at least dual-issue. */
8706 case PROCESSOR_SUPERSPARC
:
8708 case PROCESSOR_HYPERSPARC
:
8709 case PROCESSOR_SPARCLITE86X
:
8711 case PROCESSOR_ULTRASPARC
:
8712 case PROCESSOR_ULTRASPARC3
:
8718 set_extends (rtx insn
)
8720 register rtx pat
= PATTERN (insn
);
8722 switch (GET_CODE (SET_SRC (pat
)))
8724 /* Load and some shift instructions zero extend. */
8727 /* sethi clears the high bits */
8729 /* LO_SUM is used with sethi. sethi cleared the high
8730 bits and the values used with lo_sum are positive */
8732 /* Store flag stores 0 or 1 */
8742 rtx op0
= XEXP (SET_SRC (pat
), 0);
8743 rtx op1
= XEXP (SET_SRC (pat
), 1);
8744 if (GET_CODE (op1
) == CONST_INT
)
8745 return INTVAL (op1
) >= 0;
8746 if (GET_CODE (op0
) != REG
)
8748 if (sparc_check_64 (op0
, insn
) == 1)
8750 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8755 rtx op0
= XEXP (SET_SRC (pat
), 0);
8756 rtx op1
= XEXP (SET_SRC (pat
), 1);
8757 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
8759 if (GET_CODE (op1
) == CONST_INT
)
8760 return INTVAL (op1
) >= 0;
8761 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8764 return GET_MODE (SET_SRC (pat
)) == SImode
;
8765 /* Positive integers leave the high bits zero. */
8767 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
8769 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
8772 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
8774 return sparc_check_64 (SET_SRC (pat
), insn
);
8780 /* We _ought_ to have only one kind per function, but... */
8781 static GTY(()) rtx sparc_addr_diff_list
;
8782 static GTY(()) rtx sparc_addr_list
;
8785 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
8787 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8789 sparc_addr_diff_list
8790 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
8792 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
8796 sparc_output_addr_vec (rtx vec
)
8798 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8799 int idx
, vlen
= XVECLEN (body
, 0);
8801 #ifdef ASM_OUTPUT_ADDR_VEC_START
8802 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8805 #ifdef ASM_OUTPUT_CASE_LABEL
8806 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8809 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8812 for (idx
= 0; idx
< vlen
; idx
++)
8814 ASM_OUTPUT_ADDR_VEC_ELT
8815 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8818 #ifdef ASM_OUTPUT_ADDR_VEC_END
8819 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8824 sparc_output_addr_diff_vec (rtx vec
)
8826 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8827 rtx base
= XEXP (XEXP (body
, 0), 0);
8828 int idx
, vlen
= XVECLEN (body
, 1);
8830 #ifdef ASM_OUTPUT_ADDR_VEC_START
8831 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8834 #ifdef ASM_OUTPUT_CASE_LABEL
8835 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8838 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8841 for (idx
= 0; idx
< vlen
; idx
++)
8843 ASM_OUTPUT_ADDR_DIFF_ELT
8846 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
8847 CODE_LABEL_NUMBER (base
));
8850 #ifdef ASM_OUTPUT_ADDR_VEC_END
8851 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8856 sparc_output_deferred_case_vectors (void)
8861 if (sparc_addr_list
== NULL_RTX
8862 && sparc_addr_diff_list
== NULL_RTX
)
8865 /* Align to cache line in the function's code section. */
8866 switch_to_section (current_function_section ());
8868 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8870 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
8872 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
8873 sparc_output_addr_vec (XEXP (t
, 0));
8874 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
8875 sparc_output_addr_diff_vec (XEXP (t
, 0));
8877 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
8880 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8881 unknown. Return 1 if the high bits are zero, -1 if the register is
8884 sparc_check_64 (rtx x
, rtx insn
)
8886 /* If a register is set only once it is safe to ignore insns this
8887 code does not know how to handle. The loop will either recognize
8888 the single set and return the correct value or fail to recognize
8893 gcc_assert (GET_CODE (x
) == REG
);
8895 if (GET_MODE (x
) == DImode
)
8896 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
8898 if (flag_expensive_optimizations
8899 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
8905 insn
= get_last_insn_anywhere ();
8910 while ((insn
= PREV_INSN (insn
)))
8912 switch (GET_CODE (insn
))
8925 rtx pat
= PATTERN (insn
);
8926 if (GET_CODE (pat
) != SET
)
8928 if (rtx_equal_p (x
, SET_DEST (pat
)))
8929 return set_extends (insn
);
8930 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
8931 return set_extends (insn
);
8932 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
8940 /* Returns assembly code to perform a DImode shift using
8941 a 64-bit global or out register on SPARC-V8+. */
8943 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
8945 static char asm_code
[60];
8947 /* The scratch register is only required when the destination
8948 register is not a 64-bit global or out register. */
8949 if (which_alternative
!= 2)
8950 operands
[3] = operands
[0];
8952 /* We can only shift by constants <= 63. */
8953 if (GET_CODE (operands
[2]) == CONST_INT
)
8954 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
8956 if (GET_CODE (operands
[1]) == CONST_INT
)
8958 output_asm_insn ("mov\t%1, %3", operands
);
8962 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
8963 if (sparc_check_64 (operands
[1], insn
) <= 0)
8964 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
8965 output_asm_insn ("or\t%L1, %3, %3", operands
);
8968 strcpy(asm_code
, opcode
);
8970 if (which_alternative
!= 2)
8971 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8973 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8976 /* Output rtl to increment the profiler label LABELNO
8977 for profiling a function entry. */
8980 sparc_profile_hook (int labelno
)
8985 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
8986 if (NO_PROFILE_COUNTERS
)
8988 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
8992 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8993 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
8994 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
8998 #ifdef TARGET_SOLARIS
8999 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9002 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
9003 tree decl ATTRIBUTE_UNUSED
)
9005 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
9007 solaris_elf_asm_comdat_section (name
, flags
, decl
);
9011 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
9013 if (!(flags
& SECTION_DEBUG
))
9014 fputs (",#alloc", asm_out_file
);
9015 if (flags
& SECTION_WRITE
)
9016 fputs (",#write", asm_out_file
);
9017 if (flags
& SECTION_TLS
)
9018 fputs (",#tls", asm_out_file
);
9019 if (flags
& SECTION_CODE
)
9020 fputs (",#execinstr", asm_out_file
);
9022 /* ??? Handle SECTION_BSS. */
9024 fputc ('\n', asm_out_file
);
9026 #endif /* TARGET_SOLARIS */
9028 /* We do not allow indirect calls to be optimized into sibling calls.
9030 We cannot use sibling calls when delayed branches are disabled
9031 because they will likely require the call delay slot to be filled.
9033 Also, on SPARC 32-bit we cannot emit a sibling call when the
9034 current function returns a structure. This is because the "unimp
9035 after call" convention would cause the callee to return to the
9036 wrong place. The generic code already disallows cases where the
9037 function being called returns a structure.
9039 It may seem strange how this last case could occur. Usually there
9040 is code after the call which jumps to epilogue code which dumps the
9041 return value into the struct return area. That ought to invalidate
9042 the sibling call right? Well, in the C++ case we can end up passing
9043 the pointer to the struct return area to a constructor (which returns
9044 void) and then nothing else happens. Such a sibling call would look
9045 valid without the added check here.
9047 VxWorks PIC PLT entries require the global pointer to be initialized
9048 on entry. We therefore can't emit sibling calls to them. */
9050 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9053 && flag_delayed_branch
9054 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9055 && !(TARGET_VXWORKS_RTP
9057 && !targetm
.binds_local_p (decl
)));
9060 /* libfunc renaming. */
9063 sparc_init_libfuncs (void)
9067 /* Use the subroutines that Sun's library provides for integer
9068 multiply and divide. The `*' prevents an underscore from
9069 being prepended by the compiler. .umul is a little faster
9071 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9072 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9073 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9074 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9075 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9077 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9078 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9079 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9080 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9081 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9082 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9084 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9085 is because with soft-float, the SFmode and DFmode sqrt
9086 instructions will be absent, and the compiler will notice and
9087 try to use the TFmode sqrt instruction for calls to the
9088 builtin function sqrt, but this fails. */
9090 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9092 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
9093 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
9094 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
9095 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
9096 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
9097 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
9099 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
9100 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
9101 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
9102 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
9104 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
9105 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
9106 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
9107 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
9109 if (DITF_CONVERSION_LIBFUNCS
)
9111 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
9112 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
9113 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
9114 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
9117 if (SUN_CONVERSION_LIBFUNCS
)
9119 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9120 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9121 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9122 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9127 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9128 do not exist in the library. Make sure the compiler does not
9129 emit calls to them by accident. (It should always use the
9130 hardware instructions.) */
9131 set_optab_libfunc (smul_optab
, SImode
, 0);
9132 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9133 set_optab_libfunc (udiv_optab
, SImode
, 0);
9134 set_optab_libfunc (smod_optab
, SImode
, 0);
9135 set_optab_libfunc (umod_optab
, SImode
, 0);
9137 if (SUN_INTEGER_MULTIPLY_64
)
9139 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
9140 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
9141 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
9142 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
9143 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
9146 if (SUN_CONVERSION_LIBFUNCS
)
9148 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
9149 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
9150 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
9151 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
9156 static tree
def_builtin(const char *name
, int code
, tree type
)
9158 return add_builtin_function(name
, type
, code
, BUILT_IN_MD
, NULL
,
9162 static tree
def_builtin_const(const char *name
, int code
, tree type
)
9164 tree t
= def_builtin(name
, code
, type
);
9167 TREE_READONLY (t
) = 1;
9172 /* Implement the TARGET_INIT_BUILTINS target hook.
9173 Create builtin functions for special SPARC instructions. */
9176 sparc_init_builtins (void)
9179 sparc_vis_init_builtins ();
9182 /* Create builtin functions for VIS 1.0 instructions. */
9185 sparc_vis_init_builtins (void)
9187 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
9188 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
9189 tree v4hi
= build_vector_type (intHI_type_node
, 4);
9190 tree v2hi
= build_vector_type (intHI_type_node
, 2);
9191 tree v2si
= build_vector_type (intSI_type_node
, 2);
9192 tree v1si
= build_vector_type (intSI_type_node
, 1);
9194 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
9195 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
9196 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
9197 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
9198 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
9199 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
9200 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
9201 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
9202 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
9203 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
9204 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
9205 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
9206 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
9207 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
9208 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
9210 intDI_type_node
, 0);
9211 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
9213 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
9215 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
9217 intDI_type_node
, 0);
9218 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
9220 intSI_type_node
, 0);
9221 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
9223 intSI_type_node
, 0);
9224 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
9226 intDI_type_node
, 0);
9227 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
9230 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
9233 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
9235 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
9237 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
9239 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
9241 tree void_ftype_di
= build_function_type_list (void_type_node
,
9242 intDI_type_node
, 0);
9243 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
9245 tree void_ftype_si
= build_function_type_list (void_type_node
,
9246 intSI_type_node
, 0);
9247 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
9249 float_type_node
, 0);
9250 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
9252 double_type_node
, 0);
9254 /* Packing and expanding vectors. */
9255 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
9257 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
9258 v8qi_ftype_v2si_v8qi
);
9259 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
9261 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
9263 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
9264 v8qi_ftype_v4qi_v4qi
);
9266 /* Multiplications. */
9267 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
9268 v4hi_ftype_v4qi_v4hi
);
9269 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
9270 v4hi_ftype_v4qi_v2hi
);
9271 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
9272 v4hi_ftype_v4qi_v2hi
);
9273 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
9274 v4hi_ftype_v8qi_v4hi
);
9275 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
9276 v4hi_ftype_v8qi_v4hi
);
9277 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
9278 v2si_ftype_v4qi_v2hi
);
9279 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
9280 v2si_ftype_v4qi_v2hi
);
9282 /* Data aligning. */
9283 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
9284 v4hi_ftype_v4hi_v4hi
);
9285 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
9286 v8qi_ftype_v8qi_v8qi
);
9287 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
9288 v2si_ftype_v2si_v2si
);
9289 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis
,
9292 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
9294 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
9299 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
9301 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
9306 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
9308 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
9312 /* Pixel distance. */
9313 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
9314 di_ftype_v8qi_v8qi_di
);
9316 /* Edge handling. */
9319 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
9321 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
9323 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
9325 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
9327 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
9329 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
9333 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
9335 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
9337 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
9339 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
9341 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
9343 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
9349 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
9351 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
9353 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
9355 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
9357 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
9359 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
9363 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
9365 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
9367 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
9369 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
9371 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
9373 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
9378 /* Pixel compare. */
9381 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
9382 di_ftype_v4hi_v4hi
);
9383 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
9384 di_ftype_v2si_v2si
);
9385 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
9386 di_ftype_v4hi_v4hi
);
9387 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
9388 di_ftype_v2si_v2si
);
9389 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
9390 di_ftype_v4hi_v4hi
);
9391 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
9392 di_ftype_v2si_v2si
);
9393 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
9394 di_ftype_v4hi_v4hi
);
9395 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
9396 di_ftype_v2si_v2si
);
9400 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
9401 si_ftype_v4hi_v4hi
);
9402 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
9403 si_ftype_v2si_v2si
);
9404 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
9405 si_ftype_v4hi_v4hi
);
9406 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
9407 si_ftype_v2si_v2si
);
9408 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
9409 si_ftype_v4hi_v4hi
);
9410 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
9411 si_ftype_v2si_v2si
);
9412 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
9413 si_ftype_v4hi_v4hi
);
9414 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
9415 si_ftype_v2si_v2si
);
9418 /* Addition and subtraction. */
9419 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
9420 v4hi_ftype_v4hi_v4hi
);
9421 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
9422 v2hi_ftype_v2hi_v2hi
);
9423 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
9424 v2si_ftype_v2si_v2si
);
9425 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addsi3
,
9426 v1si_ftype_v1si_v1si
);
9427 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
9428 v4hi_ftype_v4hi_v4hi
);
9429 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
9430 v2hi_ftype_v2hi_v2hi
);
9431 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
9432 v2si_ftype_v2si_v2si
);
9433 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subsi3
,
9434 v1si_ftype_v1si_v1si
);
9436 /* Three-dimensional array addressing. */
9439 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
9441 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
9443 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
9448 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
9450 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
9452 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
9458 /* Byte mask and shuffle */
9460 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
9463 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
9465 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
9466 v4hi_ftype_v4hi_v4hi
);
9467 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
9468 v8qi_ftype_v8qi_v8qi
);
9469 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
9470 v2si_ftype_v2si_v2si
);
9471 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshuffledi_vis
,
9479 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
9481 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
9483 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
9488 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
9490 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
9492 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
9496 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
9497 v4hi_ftype_v4hi_v4hi
);
9499 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
9500 v4hi_ftype_v4hi_v4hi
);
9501 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
9502 v4hi_ftype_v4hi_v4hi
);
9503 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
9504 v4hi_ftype_v4hi_v4hi
);
9505 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
9506 v4hi_ftype_v4hi_v4hi
);
9507 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
9508 v2si_ftype_v2si_v2si
);
9509 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
9510 v2si_ftype_v2si_v2si
);
9511 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
9512 v2si_ftype_v2si_v2si
);
9513 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
9514 v2si_ftype_v2si_v2si
);
9517 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
9518 di_ftype_v8qi_v8qi
);
9520 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
9521 si_ftype_v8qi_v8qi
);
9523 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
9524 v4hi_ftype_v4hi_v4hi
);
9525 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
9527 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
9530 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
9531 v4hi_ftype_v4hi_v4hi
);
9532 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
9533 v2hi_ftype_v2hi_v2hi
);
9534 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
9535 v4hi_ftype_v4hi_v4hi
);
9536 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
9537 v2hi_ftype_v2hi_v2hi
);
9538 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
9539 v2si_ftype_v2si_v2si
);
9540 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddsi3
,
9541 v1si_ftype_v1si_v1si
);
9542 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
9543 v2si_ftype_v2si_v2si
);
9544 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubsi3
,
9545 v1si_ftype_v1si_v1si
);
9549 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
9550 di_ftype_v8qi_v8qi
);
9551 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
9552 di_ftype_v8qi_v8qi
);
9553 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
9554 di_ftype_v8qi_v8qi
);
9555 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
9556 di_ftype_v8qi_v8qi
);
9560 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
9561 si_ftype_v8qi_v8qi
);
9562 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
9563 si_ftype_v8qi_v8qi
);
9564 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
9565 si_ftype_v8qi_v8qi
);
9566 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
9567 si_ftype_v8qi_v8qi
);
9570 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
9572 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
9574 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
9576 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
9578 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
9580 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
9583 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
9585 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
9587 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
9592 /* Handle TARGET_EXPAND_BUILTIN target hook.
9593 Expand builtin functions for sparc intrinsics. */
9596 sparc_expand_builtin (tree exp
, rtx target
,
9597 rtx subtarget ATTRIBUTE_UNUSED
,
9598 enum machine_mode tmode ATTRIBUTE_UNUSED
,
9599 int ignore ATTRIBUTE_UNUSED
)
9602 call_expr_arg_iterator iter
;
9603 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9604 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
9609 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9613 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9615 || GET_MODE (target
) != tmode
9616 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9617 op
[0] = gen_reg_rtx (tmode
);
9621 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9623 const struct insn_operand_data
*insn_op
;
9626 if (arg
== error_mark_node
)
9630 idx
= arg_count
- !nonvoid
;
9631 insn_op
= &insn_data
[icode
].operand
[idx
];
9632 op
[arg_count
] = expand_normal (arg
);
9634 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
9636 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
9642 pat
= GEN_FCN (icode
) (op
[0]);
9646 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
9648 pat
= GEN_FCN (icode
) (op
[1]);
9651 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
9654 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
9672 sparc_vis_mul8x16 (int e8
, int e16
)
9674 return (e8
* e16
+ 128) / 256;
9677 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9678 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9679 constants. A tree list with the results of the multiplications is returned,
9680 and each element in the list is of INNER_TYPE. */
9683 sparc_handle_vis_mul8x16 (int fncode
, tree inner_type
, tree elts0
, tree elts1
)
9685 tree n_elts
= NULL_TREE
;
9690 case CODE_FOR_fmul8x16_vis
:
9691 for (; elts0
&& elts1
;
9692 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9695 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9696 TREE_INT_CST_LOW (TREE_VALUE (elts1
)));
9697 n_elts
= tree_cons (NULL_TREE
,
9698 build_int_cst (inner_type
, val
),
9703 case CODE_FOR_fmul8x16au_vis
:
9704 scale
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9706 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9709 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9711 n_elts
= tree_cons (NULL_TREE
,
9712 build_int_cst (inner_type
, val
),
9717 case CODE_FOR_fmul8x16al_vis
:
9718 scale
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1
)));
9720 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9723 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9725 n_elts
= tree_cons (NULL_TREE
,
9726 build_int_cst (inner_type
, val
),
9735 return nreverse (n_elts
);
9738 /* Handle TARGET_FOLD_BUILTIN target hook.
9739 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9740 result of the function call is ignored. NULL_TREE is returned if the
9741 function could not be folded. */
9744 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
9745 tree
*args
, bool ignore
)
9747 tree arg0
, arg1
, arg2
;
9748 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
9749 enum insn_code icode
= (enum insn_code
) DECL_FUNCTION_CODE (fndecl
);
9753 /* Note that a switch statement instead of the sequence of tests would
9754 be incorrect as many of the CODE_FOR values could be CODE_FOR_nothing
9755 and that would yield multiple alternatives with identical values. */
9756 if (icode
== CODE_FOR_alignaddrsi_vis
9757 || icode
== CODE_FOR_alignaddrdi_vis
9758 || icode
== CODE_FOR_wrgsr_vis
9759 || icode
== CODE_FOR_bmasksi_vis
9760 || icode
== CODE_FOR_bmaskdi_vis
9761 || icode
== CODE_FOR_cmask8si_vis
9762 || icode
== CODE_FOR_cmask8di_vis
9763 || icode
== CODE_FOR_cmask16si_vis
9764 || icode
== CODE_FOR_cmask16di_vis
9765 || icode
== CODE_FOR_cmask32si_vis
9766 || icode
== CODE_FOR_cmask32di_vis
)
9769 return build_zero_cst (rtype
);
9774 case CODE_FOR_fexpand_vis
:
9778 if (TREE_CODE (arg0
) == VECTOR_CST
)
9780 tree inner_type
= TREE_TYPE (rtype
);
9781 tree elts
= TREE_VECTOR_CST_ELTS (arg0
);
9782 tree n_elts
= NULL_TREE
;
9784 for (; elts
; elts
= TREE_CHAIN (elts
))
9786 unsigned int val
= TREE_INT_CST_LOW (TREE_VALUE (elts
)) << 4;
9787 n_elts
= tree_cons (NULL_TREE
,
9788 build_int_cst (inner_type
, val
),
9791 return build_vector (rtype
, nreverse (n_elts
));
9795 case CODE_FOR_fmul8x16_vis
:
9796 case CODE_FOR_fmul8x16au_vis
:
9797 case CODE_FOR_fmul8x16al_vis
:
9803 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9805 tree inner_type
= TREE_TYPE (rtype
);
9806 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9807 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9808 tree n_elts
= sparc_handle_vis_mul8x16 (icode
, inner_type
, elts0
,
9811 return build_vector (rtype
, n_elts
);
9815 case CODE_FOR_fpmerge_vis
:
9821 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9823 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9824 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9825 tree n_elts
= NULL_TREE
;
9827 for (; elts0
&& elts1
;
9828 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9830 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts0
), n_elts
);
9831 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts1
), n_elts
);
9834 return build_vector (rtype
, nreverse (n_elts
));
9838 case CODE_FOR_pdist_vis
:
9846 if (TREE_CODE (arg0
) == VECTOR_CST
9847 && TREE_CODE (arg1
) == VECTOR_CST
9848 && TREE_CODE (arg2
) == INTEGER_CST
)
9851 unsigned HOST_WIDE_INT low
= TREE_INT_CST_LOW (arg2
);
9852 HOST_WIDE_INT high
= TREE_INT_CST_HIGH (arg2
);
9853 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9854 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9856 for (; elts0
&& elts1
;
9857 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9859 unsigned HOST_WIDE_INT
9860 low0
= TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9861 low1
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9862 HOST_WIDE_INT high0
= TREE_INT_CST_HIGH (TREE_VALUE (elts0
));
9863 HOST_WIDE_INT high1
= TREE_INT_CST_HIGH (TREE_VALUE (elts1
));
9865 unsigned HOST_WIDE_INT l
;
9868 overflow
|= neg_double (low1
, high1
, &l
, &h
);
9869 overflow
|= add_double (low0
, high0
, l
, h
, &l
, &h
);
9871 overflow
|= neg_double (l
, h
, &l
, &h
);
9873 overflow
|= add_double (low
, high
, l
, h
, &low
, &high
);
9876 gcc_assert (overflow
== 0);
9878 return build_int_cst_wide (rtype
, low
, high
);
9888 /* ??? This duplicates information provided to the compiler by the
9889 ??? scheduler description. Some day, teach genautomata to output
9890 ??? the latencies and then CSE will just use that. */
9893 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
9894 int *total
, bool speed ATTRIBUTE_UNUSED
)
9896 enum machine_mode mode
= GET_MODE (x
);
9897 bool float_mode_p
= FLOAT_MODE_P (mode
);
9902 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
9920 if (GET_MODE (x
) == VOIDmode
9921 && ((CONST_DOUBLE_HIGH (x
) == 0
9922 && CONST_DOUBLE_LOW (x
) < 0x1000)
9923 || (CONST_DOUBLE_HIGH (x
) == -1
9924 && CONST_DOUBLE_LOW (x
) < 0
9925 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
9932 /* If outer-code was a sign or zero extension, a cost
9933 of COSTS_N_INSNS (1) was already added in. This is
9934 why we are subtracting it back out. */
9935 if (outer_code
== ZERO_EXTEND
)
9937 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
9939 else if (outer_code
== SIGN_EXTEND
)
9941 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
9943 else if (float_mode_p
)
9945 *total
= sparc_costs
->float_load
;
9949 *total
= sparc_costs
->int_load
;
9957 *total
= sparc_costs
->float_plusminus
;
9959 *total
= COSTS_N_INSNS (1);
9966 gcc_assert (float_mode_p
);
9967 *total
= sparc_costs
->float_mul
;
9970 if (GET_CODE (sub
) == NEG
)
9971 sub
= XEXP (sub
, 0);
9972 *total
+= rtx_cost (sub
, FMA
, 0, speed
);
9975 if (GET_CODE (sub
) == NEG
)
9976 sub
= XEXP (sub
, 0);
9977 *total
+= rtx_cost (sub
, FMA
, 2, speed
);
9983 *total
= sparc_costs
->float_mul
;
9984 else if (! TARGET_HARD_MUL
)
9985 *total
= COSTS_N_INSNS (25);
9991 if (sparc_costs
->int_mul_bit_factor
)
9995 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9997 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
9998 for (nbits
= 0; value
!= 0; value
&= value
- 1)
10001 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
10002 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
10004 rtx x1
= XEXP (x
, 1);
10005 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
10006 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
10008 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
10010 for (; value2
!= 0; value2
&= value2
- 1)
10018 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
10019 bit_cost
= COSTS_N_INSNS (bit_cost
);
10022 if (mode
== DImode
)
10023 *total
= sparc_costs
->int_mulX
+ bit_cost
;
10025 *total
= sparc_costs
->int_mul
+ bit_cost
;
10032 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
10041 if (mode
== DFmode
)
10042 *total
= sparc_costs
->float_div_df
;
10044 *total
= sparc_costs
->float_div_sf
;
10048 if (mode
== DImode
)
10049 *total
= sparc_costs
->int_divX
;
10051 *total
= sparc_costs
->int_div
;
10056 if (! float_mode_p
)
10058 *total
= COSTS_N_INSNS (1);
10065 case UNSIGNED_FLOAT
:
10069 case FLOAT_TRUNCATE
:
10070 *total
= sparc_costs
->float_move
;
10074 if (mode
== DFmode
)
10075 *total
= sparc_costs
->float_sqrt_df
;
10077 *total
= sparc_costs
->float_sqrt_sf
;
10082 *total
= sparc_costs
->float_cmp
;
10084 *total
= COSTS_N_INSNS (1);
10089 *total
= sparc_costs
->float_cmove
;
10091 *total
= sparc_costs
->int_cmove
;
10095 /* Handle the NAND vector patterns. */
10096 if (sparc_vector_mode_supported_p (GET_MODE (x
))
10097 && GET_CODE (XEXP (x
, 0)) == NOT
10098 && GET_CODE (XEXP (x
, 1)) == NOT
)
10100 *total
= COSTS_N_INSNS (1);
10111 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
10114 general_or_i64_p (reg_class_t rclass
)
10116 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
10119 /* Implement TARGET_REGISTER_MOVE_COST. */
10122 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
10123 reg_class_t from
, reg_class_t to
)
10125 if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
10126 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
))
10127 || from
== FPCC_REGS
10128 || to
== FPCC_REGS
)
10130 if (sparc_cpu
== PROCESSOR_ULTRASPARC
10131 || sparc_cpu
== PROCESSOR_ULTRASPARC3
10132 || sparc_cpu
== PROCESSOR_NIAGARA
10133 || sparc_cpu
== PROCESSOR_NIAGARA2
10134 || sparc_cpu
== PROCESSOR_NIAGARA3
10135 || sparc_cpu
== PROCESSOR_NIAGARA4
)
10144 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
10145 This is achieved by means of a manual dynamic stack space allocation in
10146 the current frame. We make the assumption that SEQ doesn't contain any
10147 function calls, with the possible exception of calls to the GOT helper. */
10150 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
10152 /* We must preserve the lowest 16 words for the register save area. */
10153 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
10154 /* We really need only 2 words of fresh stack space. */
10155 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
10158 = gen_rtx_MEM (word_mode
, plus_constant (stack_pointer_rtx
,
10159 SPARC_STACK_BIAS
+ offset
));
10161 emit_insn (gen_stack_pointer_dec (GEN_INT (size
)));
10162 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
10164 emit_insn (gen_rtx_SET (VOIDmode
,
10165 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
10169 emit_insn (gen_rtx_SET (VOIDmode
,
10171 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
10172 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
10173 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
10176 /* Output the assembler code for a thunk function. THUNK_DECL is the
10177 declaration for the thunk function itself, FUNCTION is the decl for
10178 the target function. DELTA is an immediate constant offset to be
10179 added to THIS. If VCALL_OFFSET is nonzero, the word at address
10180 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
10183 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
10184 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
10187 rtx this_rtx
, insn
, funexp
;
10188 unsigned int int_arg_first
;
10190 reload_completed
= 1;
10191 epilogue_completed
= 1;
10193 emit_note (NOTE_INSN_PROLOGUE_END
);
10197 sparc_leaf_function_p
= 1;
10199 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
10201 else if (flag_delayed_branch
)
10203 /* We will emit a regular sibcall below, so we need to instruct
10204 output_sibcall that we are in a leaf function. */
10205 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
10207 /* This will cause final.c to invoke leaf_renumber_regs so we
10208 must behave as if we were in a not-yet-leafified function. */
10209 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
10213 /* We will emit the sibcall manually below, so we will need to
10214 manually spill non-leaf registers. */
10215 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
10217 /* We really are in a leaf function. */
10218 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
10221 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
10222 returns a structure, the structure return pointer is there instead. */
10224 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
10225 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
10227 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
10229 /* Add DELTA. When possible use a plain add, otherwise load it into
10230 a register first. */
10233 rtx delta_rtx
= GEN_INT (delta
);
10235 if (! SPARC_SIMM13_P (delta
))
10237 rtx scratch
= gen_rtx_REG (Pmode
, 1);
10238 emit_move_insn (scratch
, delta_rtx
);
10239 delta_rtx
= scratch
;
10242 /* THIS_RTX += DELTA. */
10243 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
10246 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
10249 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
10250 rtx scratch
= gen_rtx_REG (Pmode
, 1);
10252 gcc_assert (vcall_offset
< 0);
10254 /* SCRATCH = *THIS_RTX. */
10255 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
10257 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
10258 may not have any available scratch register at this point. */
10259 if (SPARC_SIMM13_P (vcall_offset
))
10261 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
10262 else if (! fixed_regs
[5]
10263 /* The below sequence is made up of at least 2 insns,
10264 while the default method may need only one. */
10265 && vcall_offset
< -8192)
10267 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
10268 emit_move_insn (scratch2
, vcall_offset_rtx
);
10269 vcall_offset_rtx
= scratch2
;
10273 rtx increment
= GEN_INT (-4096);
10275 /* VCALL_OFFSET is a negative number whose typical range can be
10276 estimated as -32768..0 in 32-bit mode. In almost all cases
10277 it is therefore cheaper to emit multiple add insns than
10278 spilling and loading the constant into a register (at least
10280 while (! SPARC_SIMM13_P (vcall_offset
))
10282 emit_insn (gen_add2_insn (scratch
, increment
));
10283 vcall_offset
+= 4096;
10285 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
10288 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
10289 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
10290 gen_rtx_PLUS (Pmode
,
10292 vcall_offset_rtx
)));
10294 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
10295 emit_insn (gen_add2_insn (this_rtx
, scratch
));
10298 /* Generate a tail call to the target function. */
10299 if (! TREE_USED (function
))
10301 assemble_external (function
);
10302 TREE_USED (function
) = 1;
10304 funexp
= XEXP (DECL_RTL (function
), 0);
10306 if (flag_delayed_branch
)
10308 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
10309 insn
= emit_call_insn (gen_sibcall (funexp
));
10310 SIBLING_CALL_P (insn
) = 1;
10314 /* The hoops we have to jump through in order to generate a sibcall
10315 without using delay slots... */
10316 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
10320 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
10322 load_got_register (); /* clobbers %o7 */
10323 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
10324 seq
= get_insns ();
10326 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
10328 else if (TARGET_ARCH32
)
10330 emit_insn (gen_rtx_SET (VOIDmode
,
10332 gen_rtx_HIGH (SImode
, funexp
)));
10333 emit_insn (gen_rtx_SET (VOIDmode
,
10335 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
10337 else /* TARGET_ARCH64 */
10339 switch (sparc_cmodel
)
10343 /* The destination can serve as a temporary. */
10344 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
10349 /* The destination cannot serve as a temporary. */
10350 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
10352 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
10353 seq
= get_insns ();
10355 emit_and_preserve (seq
, spill_reg
, 0);
10359 gcc_unreachable ();
10363 emit_jump_insn (gen_indirect_jump (scratch
));
10368 /* Run just enough of rest_of_compilation to get the insns emitted.
10369 There's not really enough bulk here to make other passes such as
10370 instruction scheduling worth while. Note that use_thunk calls
10371 assemble_start_function and assemble_end_function. */
10372 insn
= get_insns ();
10373 insn_locators_alloc ();
10374 shorten_branches (insn
);
10375 final_start_function (insn
, file
, 1);
10376 final (insn
, file
, 1);
10377 final_end_function ();
10379 reload_completed
= 0;
10380 epilogue_completed
= 0;
10383 /* Return true if sparc_output_mi_thunk would be able to output the
10384 assembler code for the thunk function specified by the arguments
10385 it is passed, and false otherwise. */
10387 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
10388 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
10389 HOST_WIDE_INT vcall_offset
,
10390 const_tree function ATTRIBUTE_UNUSED
)
10392 /* Bound the loop used in the default method above. */
10393 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
10396 /* We use the machine specific reorg pass to enable workarounds for errata. */
10403 /* The only erratum we handle for now is that of the AT697F processor. */
10404 if (!sparc_fix_at697f
)
10407 /* We need to have the (essentially) final form of the insn stream in order
10408 to properly detect the various hazards. Run delay slot scheduling. */
10409 if (optimize
> 0 && flag_delayed_branch
)
10410 dbr_schedule (get_insns ());
10412 /* Now look for specific patterns in the insn stream. */
10413 for (insn
= get_insns (); insn
; insn
= next
)
10415 bool insert_nop
= false;
10418 /* Look for a single-word load into an odd-numbered FP register. */
10419 if (NONJUMP_INSN_P (insn
)
10420 && (set
= single_set (insn
)) != NULL_RTX
10421 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
10422 && MEM_P (SET_SRC (set
))
10423 && REG_P (SET_DEST (set
))
10424 && REGNO (SET_DEST (set
)) > 31
10425 && REGNO (SET_DEST (set
)) % 2 != 0)
10427 /* The wrong dependency is on the enclosing double register. */
10428 unsigned int x
= REGNO (SET_DEST (set
)) - 1;
10429 unsigned int src1
, src2
, dest
;
10432 /* If the insn has a delay slot, then it cannot be problematic. */
10433 next
= next_active_insn (insn
);
10434 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
10438 extract_insn (next
);
10439 code
= INSN_CODE (next
);
10444 case CODE_FOR_adddf3
:
10445 case CODE_FOR_subdf3
:
10446 case CODE_FOR_muldf3
:
10447 case CODE_FOR_divdf3
:
10448 dest
= REGNO (recog_data
.operand
[0]);
10449 src1
= REGNO (recog_data
.operand
[1]);
10450 src2
= REGNO (recog_data
.operand
[2]);
10454 ld [address], %fx+1
10455 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
10456 if ((src1
== x
|| src2
== x
)
10457 && (dest
== src1
|| dest
== src2
))
10463 ld [address], %fx+1
10464 FPOPd %fx, %fx, %fx */
10467 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
10472 case CODE_FOR_sqrtdf2
:
10473 dest
= REGNO (recog_data
.operand
[0]);
10474 src1
= REGNO (recog_data
.operand
[1]);
10476 ld [address], %fx+1
10478 if (src1
== x
&& dest
== src1
)
10487 next
= NEXT_INSN (insn
);
10490 emit_insn_after (gen_nop (), insn
);
10494 /* How to allocate a 'struct machine_function'. */
10496 static struct machine_function
*
10497 sparc_init_machine_status (void)
10499 return ggc_alloc_cleared_machine_function ();
10502 /* Locate some local-dynamic symbol still in use by this function
10503 so that we can print its name in local-dynamic base patterns. */
10505 static const char *
10506 get_some_local_dynamic_name (void)
10510 if (cfun
->machine
->some_ld_name
)
10511 return cfun
->machine
->some_ld_name
;
10513 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10515 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
10516 return cfun
->machine
->some_ld_name
;
10518 gcc_unreachable ();
10522 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
10527 && GET_CODE (x
) == SYMBOL_REF
10528 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
10530 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
10537 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10538 We need to emit DTP-relative relocations. */
10541 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
10546 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
10549 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
10552 gcc_unreachable ();
10554 output_addr_const (file
, x
);
10558 /* Do whatever processing is required at the end of a file. */
10561 sparc_file_end (void)
10563 /* If we need to emit the special GOT helper function, do so now. */
10564 if (got_helper_rtx
)
10566 const char *name
= XSTR (got_helper_rtx
, 0);
10567 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
10568 #ifdef DWARF2_UNWIND_INFO
10572 if (USE_HIDDEN_LINKONCE
)
10574 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
10575 get_identifier (name
),
10576 build_function_type_list (void_type_node
,
10578 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
10579 NULL_TREE
, void_type_node
);
10580 TREE_STATIC (decl
) = 1;
10581 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
10582 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
10583 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
10584 resolve_unique_section (decl
, 0, flag_function_sections
);
10585 allocate_struct_function (decl
, true);
10586 cfun
->is_thunk
= 1;
10587 current_function_decl
= decl
;
10588 init_varasm_status ();
10589 assemble_start_function (decl
, name
);
10593 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10594 switch_to_section (text_section
);
10596 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10597 ASM_OUTPUT_LABEL (asm_out_file
, name
);
10600 #ifdef DWARF2_UNWIND_INFO
10601 do_cfi
= dwarf2out_do_cfi_asm ();
10603 fprintf (asm_out_file
, "\t.cfi_startproc\n");
10605 if (flag_delayed_branch
)
10606 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10607 reg_name
, reg_name
);
10609 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10610 reg_name
, reg_name
);
10611 #ifdef DWARF2_UNWIND_INFO
10613 fprintf (asm_out_file
, "\t.cfi_endproc\n");
10617 if (NEED_INDICATE_EXEC_STACK
)
10618 file_end_indicate_exec_stack ();
10620 #ifdef TARGET_SOLARIS
10621 solaris_file_end ();
10625 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10626 /* Implement TARGET_MANGLE_TYPE. */
10628 static const char *
10629 sparc_mangle_type (const_tree type
)
10632 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
10633 && TARGET_LONG_DOUBLE_128
)
10636 /* For all other types, use normal C++ mangling. */
10641 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10642 compare and swap on the word containing the byte or half-word. */
10645 sparc_expand_compare_and_swap_12 (rtx result
, rtx mem
, rtx oldval
, rtx newval
)
10647 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
10648 rtx addr
= gen_reg_rtx (Pmode
);
10649 rtx off
= gen_reg_rtx (SImode
);
10650 rtx oldv
= gen_reg_rtx (SImode
);
10651 rtx newv
= gen_reg_rtx (SImode
);
10652 rtx oldvalue
= gen_reg_rtx (SImode
);
10653 rtx newvalue
= gen_reg_rtx (SImode
);
10654 rtx res
= gen_reg_rtx (SImode
);
10655 rtx resv
= gen_reg_rtx (SImode
);
10656 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
10658 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
10659 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
10661 if (Pmode
!= SImode
)
10662 addr1
= gen_lowpart (SImode
, addr1
);
10663 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10664 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
10666 memsi
= gen_rtx_MEM (SImode
, addr
);
10667 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
10668 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
10670 val
= force_reg (SImode
, memsi
);
10672 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10673 gen_rtx_XOR (SImode
, off
,
10674 GEN_INT (GET_MODE (mem
) == QImode
10677 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10678 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
10680 if (GET_MODE (mem
) == QImode
)
10681 mask
= force_reg (SImode
, GEN_INT (0xff));
10683 mask
= force_reg (SImode
, GEN_INT (0xffff));
10685 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
10686 gen_rtx_ASHIFT (SImode
, mask
, off
)));
10688 emit_insn (gen_rtx_SET (VOIDmode
, val
,
10689 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10692 oldval
= gen_lowpart (SImode
, oldval
);
10693 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10694 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
10696 newval
= gen_lowpart_common (SImode
, newval
);
10697 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10698 gen_rtx_ASHIFT (SImode
, newval
, off
)));
10700 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10701 gen_rtx_AND (SImode
, oldv
, mask
)));
10703 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10704 gen_rtx_AND (SImode
, newv
, mask
)));
10706 end_label
= gen_label_rtx ();
10707 loop_label
= gen_label_rtx ();
10708 emit_label (loop_label
);
10710 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
10711 gen_rtx_IOR (SImode
, oldv
, val
)));
10713 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
10714 gen_rtx_IOR (SImode
, newv
, val
)));
10716 emit_insn (gen_sync_compare_and_swapsi (res
, memsi
, oldvalue
, newvalue
));
10718 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
10720 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
10721 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10724 cc
= gen_compare_reg_1 (NE
, resv
, val
);
10725 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
10727 /* Use cbranchcc4 to separate the compare and branch! */
10728 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
10729 cc
, const0_rtx
, loop_label
));
10731 emit_label (end_label
);
10733 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10734 gen_rtx_AND (SImode
, res
, mask
)));
10736 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10737 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
10739 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
10742 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10745 sparc_frame_pointer_required (void)
10747 /* If the stack pointer is dynamically modified in the function, it cannot
10748 serve as the frame pointer. */
10749 if (cfun
->calls_alloca
)
10752 /* If the function receives nonlocal gotos, it needs to save the frame
10753 pointer in the nonlocal_goto_save_area object. */
10754 if (cfun
->has_nonlocal_label
)
10757 /* In flat mode, that's it. */
10761 /* Otherwise, the frame pointer is required if the function isn't leaf. */
10762 return !(current_function_is_leaf
&& only_leaf_regs_used ());
10765 /* The way this is structured, we can't eliminate SFP in favor of SP
10766 if the frame pointer is required: we want to use the SFP->HFP elimination
10767 in that case. But the test in update_eliminables doesn't know we are
10768 assuming below that we only do the former elimination. */
10771 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10773 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
10776 /* Return the hard frame pointer directly to bypass the stack bias. */
10779 sparc_builtin_setjmp_frame_value (void)
10781 return hard_frame_pointer_rtx
;
10784 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
10785 they won't be allocated. */
10788 sparc_conditional_register_usage (void)
10790 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
10792 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10793 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10795 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
10796 /* then honor it. */
10797 if (TARGET_ARCH32
&& fixed_regs
[5])
10799 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
10804 for (regno
= SPARC_FIRST_V9_FP_REG
;
10805 regno
<= SPARC_LAST_V9_FP_REG
;
10807 fixed_regs
[regno
] = 1;
10808 /* %fcc0 is used by v8 and v9. */
10809 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
10810 regno
<= SPARC_LAST_V9_FCC_REG
;
10812 fixed_regs
[regno
] = 1;
10817 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
10818 fixed_regs
[regno
] = 1;
10820 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
10821 /* then honor it. Likewise with g3 and g4. */
10822 if (fixed_regs
[2] == 2)
10823 fixed_regs
[2] = ! TARGET_APP_REGS
;
10824 if (fixed_regs
[3] == 2)
10825 fixed_regs
[3] = ! TARGET_APP_REGS
;
10826 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
10827 fixed_regs
[4] = ! TARGET_APP_REGS
;
10828 else if (TARGET_CM_EMBMEDANY
)
10830 else if (fixed_regs
[4] == 2)
10835 /* Disable leaf functions. */
10836 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
10837 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
10838 leaf_reg_remap
[regno
] = regno
;
10841 global_regs
[SPARC_GSR_REG
] = 1;
10844 /* Implement TARGET_PREFERRED_RELOAD_CLASS
10846 - We can't load constants into FP registers.
10847 - We can't load FP constants into integer registers when soft-float,
10848 because there is no soft-float pattern with a r/F constraint.
10849 - We can't load FP constants into integer registers for TFmode unless
10850 it is 0.0L, because there is no movtf pattern with a r/F constraint.
10851 - Try and reload integer constants (symbolic or otherwise) back into
10852 registers directly, rather than having them dumped to memory. */
10855 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
10857 if (CONSTANT_P (x
))
10859 if (FP_REG_CLASS_P (rclass
)
10860 || rclass
== GENERAL_OR_FP_REGS
10861 || rclass
== GENERAL_OR_EXTRA_FP_REGS
10862 || (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
&& ! TARGET_FPU
)
10863 || (GET_MODE (x
) == TFmode
&& ! const_zero_operand (x
, TFmode
)))
10866 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
10867 return GENERAL_REGS
;
10874 output_v8plus_mult (rtx insn
, rtx
*operands
, const char *name
)
10878 gcc_assert (! TARGET_ARCH64
);
10880 if (sparc_check_64 (operands
[1], insn
) <= 0)
10881 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
10882 if (which_alternative
== 1)
10883 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
10884 if (GET_CODE (operands
[2]) == CONST_INT
)
10886 if (which_alternative
== 1)
10888 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
10889 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", name
);
10890 output_asm_insn (mulstr
, operands
);
10891 return "srlx\t%L0, 32, %H0";
10895 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
10896 output_asm_insn ("or\t%L1, %3, %3", operands
);
10897 sprintf (mulstr
, "%s\t%%3, %%2, %%3", name
);
10898 output_asm_insn (mulstr
, operands
);
10899 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
10900 return "mov\t%3, %L0";
10903 else if (rtx_equal_p (operands
[1], operands
[2]))
10905 if (which_alternative
== 1)
10907 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
10908 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", name
);
10909 output_asm_insn (mulstr
, operands
);
10910 return "srlx\t%L0, 32, %H0";
10914 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
10915 output_asm_insn ("or\t%L1, %3, %3", operands
);
10916 sprintf (mulstr
, "%s\t%%3, %%3, %%3", name
);
10917 output_asm_insn (mulstr
, operands
);
10918 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
10919 return "mov\t%3, %L0";
10922 if (sparc_check_64 (operands
[2], insn
) <= 0)
10923 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
10924 if (which_alternative
== 1)
10926 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
10927 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
10928 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
10929 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", name
);
10930 output_asm_insn (mulstr
, operands
);
10931 return "srlx\t%L0, 32, %H0";
10935 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
10936 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
10937 output_asm_insn ("or\t%L1, %3, %3", operands
);
10938 output_asm_insn ("or\t%L2, %4, %4", operands
);
10939 sprintf (mulstr
, "%s\t%%3, %%4, %%3", name
);
10940 output_asm_insn (mulstr
, operands
);
10941 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
10942 return "mov\t%3, %L0";
10946 #include "gt-sparc.h"