1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Define the specific costs for a given cpu */
30 struct processor_costs
{
34 /* Integer signed load */
37 /* Integer zeroed load */
43 /* fmov, fneg, fabs */
47 const int float_plusminus
;
53 const int float_cmove
;
59 const int float_div_sf
;
62 const int float_div_df
;
65 const int float_sqrt_sf
;
68 const int float_sqrt_df
;
76 /* integer multiply cost for each bit set past the most
77 significant 3, so the formula for multiply cost becomes:
80 highest_bit = highest_clear_bit(rs1);
82 highest_bit = highest_set_bit(rs1);
85 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
87 A value of zero indicates that the multiply costs is fixed,
89 const int int_mul_bit_factor
;
100 /* penalty for shifts, due to scheduling rules etc. */
101 const int shift_penalty
;
104 extern const struct processor_costs
*sparc_costs
;
106 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
107 Solaris only; otherwise just define __sparc__. Sadly the headers
108 are such a mess there is no Solaris-specific header. */
109 #define TARGET_CPU_CPP_BUILTINS() \
112 builtin_define_std ("sparc"); \
115 builtin_assert ("cpu=sparc64"); \
116 builtin_assert ("machine=sparc64"); \
120 builtin_assert ("cpu=sparc"); \
121 builtin_assert ("machine=sparc"); \
126 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
127 /* #define SPARC_BI_ARCH */
129 /* Macro used later in this file to determine default architecture. */
130 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
132 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
133 architectures to compile for. We allow targets to choose compile time or
134 runtime selection. */
136 #if defined(__sparcv9) || defined(__arch64__)
137 #define TARGET_ARCH32 0
139 #define TARGET_ARCH32 1
143 #define TARGET_ARCH32 (! TARGET_64BIT)
145 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
146 #endif /* SPARC_BI_ARCH */
147 #endif /* IN_LIBGCC2 */
148 #define TARGET_ARCH64 (! TARGET_ARCH32)
150 /* Code model selection in 64-bit environment.
152 The machine mode used for addresses is 32-bit wide:
154 TARGET_CM_32: 32-bit address space.
155 It is the code model used when generating 32-bit code.
157 The machine mode used for addresses is 64-bit wide:
159 TARGET_CM_MEDLOW: 32-bit address space.
160 The executable must be in the low 32 bits of memory.
161 This avoids generating %uhi and %ulo terms. Programs
162 can be statically or dynamically linked.
164 TARGET_CM_MEDMID: 44-bit address space.
165 The executable must be in the low 44 bits of memory,
166 and the %[hml]44 terms are used. The text and data
167 segments have a maximum size of 2GB (31-bit span).
168 The maximum offset from any instruction to the label
169 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
171 TARGET_CM_MEDANY: 64-bit address space.
172 The text and data segments have a maximum size of 2GB
173 (31-bit span) and may be located anywhere in memory.
174 The maximum offset from any instruction to the label
175 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
177 TARGET_CM_EMBMEDANY: 64-bit address space.
178 The text and data segments have a maximum size of 2GB
179 (31-bit span) and may be located anywhere in memory.
180 The global register %g4 contains the start address of
181 the data segment. Programs are statically linked and
182 PIC is not supported.
184 Different code models are not supported in 32-bit environment. */
194 /* Value of -mcmodel specified by user. */
195 extern const char *sparc_cmodel_string
;
197 extern enum cmodel sparc_cmodel
;
199 /* V9 code model selection. */
200 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
201 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
202 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
203 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
205 #define SPARC_DEFAULT_CMODEL CM_32
207 /* This is call-clobbered in the normal ABI, but is reserved in the
208 home grown (aka upward compatible) embedded ABI. */
209 #define EMBMEDANY_BASE_REG "%g4"
211 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
212 and specified by the user via --with-cpu=foo.
213 This specifies the cpu implementation, not the architecture size. */
214 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
216 #define TARGET_CPU_sparc 0
217 #define TARGET_CPU_v7 0 /* alias for previous */
218 #define TARGET_CPU_sparclet 1
219 #define TARGET_CPU_sparclite 2
220 #define TARGET_CPU_v8 3 /* generic v8 implementation */
221 #define TARGET_CPU_supersparc 4
222 #define TARGET_CPU_hypersparc 5
223 #define TARGET_CPU_sparc86x 6
224 #define TARGET_CPU_sparclite86x 6
225 #define TARGET_CPU_v9 7 /* generic v9 implementation */
226 #define TARGET_CPU_sparcv9 7 /* alias */
227 #define TARGET_CPU_sparc64 7 /* alias */
228 #define TARGET_CPU_ultrasparc 8
229 #define TARGET_CPU_ultrasparc3 9
231 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
232 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
233 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
235 #define CPP_CPU32_DEFAULT_SPEC ""
236 #define ASM_CPU32_DEFAULT_SPEC ""
238 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
239 /* ??? What does Sun's CC pass? */
240 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
241 /* ??? It's not clear how other assemblers will handle this, so by default
242 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
243 is handled in sol2.h. */
244 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
246 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
247 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
248 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
250 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
251 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
252 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
257 #define CPP_CPU64_DEFAULT_SPEC ""
258 #define ASM_CPU64_DEFAULT_SPEC ""
260 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
261 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
262 #define CPP_CPU32_DEFAULT_SPEC ""
263 #define ASM_CPU32_DEFAULT_SPEC ""
266 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
267 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
268 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
271 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
272 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
273 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
276 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
277 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
278 #define ASM_CPU32_DEFAULT_SPEC ""
281 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
282 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
283 #define ASM_CPU32_DEFAULT_SPEC ""
286 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
287 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
288 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
293 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
294 #error Unrecognized value in TARGET_CPU_DEFAULT.
299 #define CPP_CPU_DEFAULT_SPEC \
300 (DEFAULT_ARCH32_P ? "\
301 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
302 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
304 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
305 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
307 #define ASM_CPU_DEFAULT_SPEC \
308 (DEFAULT_ARCH32_P ? "\
309 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
310 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
312 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
313 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
316 #else /* !SPARC_BI_ARCH */
318 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
319 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
321 #endif /* !SPARC_BI_ARCH */
323 /* Define macros to distinguish architectures. */
325 /* Common CPP definitions used by CPP_SPEC amongst the various targets
326 for handling -mcpu=xxx switches. */
327 #define CPP_CPU_SPEC "\
328 %{msoft-float:-D_SOFT_FLOAT} \
330 %{msparclite:-D__sparclite__} \
331 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
332 %{mv8:-D__sparc_v8__} \
333 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
334 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
335 %{mcpu=sparclite:-D__sparclite__} \
336 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
337 %{mcpu=v8:-D__sparc_v8__} \
338 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
339 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
340 %{mcpu=sparclite86x:-D__sparclite86x__} \
341 %{mcpu=v9:-D__sparc_v9__} \
342 %{mcpu=ultrasparc:-D__sparc_v9__} \
343 %{mcpu=ultrasparc3:-D__sparc_v9__} \
344 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
346 #define CPP_ARCH32_SPEC ""
347 #define CPP_ARCH64_SPEC "-D__arch64__"
349 #define CPP_ARCH_DEFAULT_SPEC \
350 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
352 #define CPP_ARCH_SPEC "\
353 %{m32:%(cpp_arch32)} \
354 %{m64:%(cpp_arch64)} \
355 %{!m32:%{!m64:%(cpp_arch_default)}} \
358 /* Macros to distinguish endianness. */
359 #define CPP_ENDIAN_SPEC "\
360 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
361 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
363 /* Macros to distinguish the particular subtarget. */
364 #define CPP_SUBTARGET_SPEC ""
366 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
368 /* Prevent error on `-sun4' and `-target sun4' options. */
369 /* This used to translate -dalign to -malign, but that is no good
370 because it can't turn off the usual meaning of making debugging dumps. */
371 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
372 ??? Delete support for -m<cpu> for 2.9. */
375 %{sun4:} %{target:} \
376 %{mcypress:-mcpu=cypress} \
377 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
378 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
381 /* Override in target specific files. */
382 #define ASM_CPU_SPEC "\
383 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
384 %{msparclite:-Asparclite} \
385 %{mf930:-Asparclite} %{mf934:-Asparclite} \
386 %{mcpu=sparclite:-Asparclite} \
387 %{mcpu=sparclite86x:-Asparclite} \
388 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
389 %{mv8plus:-Av8plus} \
391 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
392 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
393 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
396 /* Word size selection, among other things.
397 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
399 #define ASM_ARCH32_SPEC "-32"
400 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
401 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
403 #define ASM_ARCH64_SPEC "-64"
405 #define ASM_ARCH_DEFAULT_SPEC \
406 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
408 #define ASM_ARCH_SPEC "\
409 %{m32:%(asm_arch32)} \
410 %{m64:%(asm_arch64)} \
411 %{!m32:%{!m64:%(asm_arch_default)}} \
414 #ifdef HAVE_AS_RELAX_OPTION
415 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
417 #define ASM_RELAX_SPEC ""
420 /* Special flags to the Sun-4 assembler when using pipe for input. */
423 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
424 %(asm_cpu) %(asm_relax)"
426 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
428 /* This macro defines names of additional specifications to put in the specs
429 that can be used in various specifications like CC1_SPEC. Its definition
430 is an initializer with a subgrouping for each command option.
432 Each subgrouping contains a string constant, that defines the
433 specification name, and a string constant that used by the GCC driver
436 Do not define this macro if it does not need to do anything. */
438 #define EXTRA_SPECS \
439 { "cpp_cpu", CPP_CPU_SPEC }, \
440 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
441 { "cpp_arch32", CPP_ARCH32_SPEC }, \
442 { "cpp_arch64", CPP_ARCH64_SPEC }, \
443 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
444 { "cpp_arch", CPP_ARCH_SPEC }, \
445 { "cpp_endian", CPP_ENDIAN_SPEC }, \
446 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
447 { "asm_cpu", ASM_CPU_SPEC }, \
448 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
449 { "asm_arch32", ASM_ARCH32_SPEC }, \
450 { "asm_arch64", ASM_ARCH64_SPEC }, \
451 { "asm_relax", ASM_RELAX_SPEC }, \
452 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
453 { "asm_arch", ASM_ARCH_SPEC }, \
454 SUBTARGET_EXTRA_SPECS
456 #define SUBTARGET_EXTRA_SPECS
458 /* Because libgcc can generate references back to libc (via .umul etc.) we have
459 to list libc again after the second libgcc. */
460 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
463 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
464 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
466 /* ??? This should be 32 bits for v9 but what can we do? */
467 #define WCHAR_TYPE "short unsigned int"
468 #define WCHAR_TYPE_SIZE 16
470 /* Show we can debug even without a frame pointer. */
471 #define CAN_DEBUG_WITHOUT_FP
473 #define OVERRIDE_OPTIONS sparc_override_options ()
475 /* Generate DBX debugging information. */
477 #define DBX_DEBUGGING_INFO 1
479 /* Run-time compilation parameters selecting different hardware subsets. */
481 extern int target_flags
;
483 /* Nonzero if we should generate code to use the fpu. */
485 #define TARGET_FPU (target_flags & MASK_FPU)
487 /* Nonzero if we should assume that double pointers might be unaligned.
488 This can happen when linking gcc compiled code with other compilers,
489 because the ABI only guarantees 4 byte alignment. */
490 #define MASK_UNALIGNED_DOUBLES 4
491 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
493 /* Nonzero means that we should generate code for a v8 sparc. */
495 #define TARGET_V8 (target_flags & MASK_V8)
497 /* Nonzero means that we should generate code for a sparclite.
498 This enables the sparclite specific instructions, but does not affect
499 whether FPU instructions are emitted. */
500 #define MASK_SPARCLITE 0x10
501 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
503 /* Nonzero if we're compiling for the sparclet. */
504 #define MASK_SPARCLET 0x20
505 #define TARGET_SPARCLET (target_flags & MASK_SPARCLET)
507 /* Nonzero if we're compiling for v9 sparc.
508 Note that v9's can run in 32 bit mode so this doesn't necessarily mean
509 the word size is 64. */
511 #define TARGET_V9 (target_flags & MASK_V9)
513 /* Nonzero to generate code that uses the instructions deprecated in
514 the v9 architecture. This option only applies to v9 systems. */
515 /* ??? This isn't user selectable yet. It's used to enable such insns
516 on 32 bit v9 systems and for the moment they're permanently disabled
517 on 64 bit v9 systems. */
518 #define MASK_DEPRECATED_V8_INSNS 0x80
519 #define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)
521 /* Mask of all CPU selection flags. */
523 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
525 /* Nonzero means don't pass `-assert pure-text' to the linker. */
526 #define MASK_IMPURE_TEXT 0x100
527 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)
529 /* 0x200 is unused */
531 /* Nonzero means use the registers that the SPARC ABI reserves for
532 application software. This must be the default to coincide with the
533 setting in FIXED_REGISTERS. */
534 #define MASK_APP_REGS 0x400
535 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
537 /* Option to select how quad word floating point is implemented.
538 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
539 Otherwise, we use the SPARC ABI quad library functions. */
540 #define MASK_HARD_QUAD 0x800
541 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
543 /* Nonzero on little-endian machines. */
544 /* ??? Little endian support currently only exists for sparc86x-elf and
545 sparc64-elf configurations. May eventually want to expand the support
546 to all targets, but for now it's kept local to only those two. */
547 #define MASK_LITTLE_ENDIAN 0x1000
548 #define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)
550 /* 0x2000, 0x4000 are unused */
552 /* Nonzero if pointers are 64 bits. */
553 #define MASK_PTR64 0x8000
554 #define TARGET_PTR64 (target_flags & MASK_PTR64)
556 /* Nonzero if generating code to run in a 64 bit environment.
557 This is intended to only be used by TARGET_ARCH{32,64} as they are the
558 mechanism used to control compile time or run time selection. */
559 #define MASK_64BIT 0x10000
560 #define TARGET_64BIT (target_flags & MASK_64BIT)
562 /* 0x20000,0x40000 unused */
564 /* Nonzero means use a stack bias of 2047. Stack offsets are obtained by
565 adding 2047 to %sp. This option is for v9 only and is the default. */
566 #define MASK_STACK_BIAS 0x80000
567 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
569 /* 0x100000,0x200000 unused */
571 /* Nonzero means -m{,no-}fpu was passed on the command line. */
572 #define MASK_FPU_SET 0x400000
573 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET)
575 /* Use the UltraSPARC Visual Instruction Set extensions. */
576 #define MASK_VIS 0x1000000
577 #define TARGET_VIS (target_flags & MASK_VIS)
579 /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of
580 the current out and global registers and Linux 2.2+ as well. */
581 #define MASK_V8PLUS 0x2000000
582 #define TARGET_V8PLUS (target_flags & MASK_V8PLUS)
584 /* Force a the fastest alignment on structures to take advantage of
586 #define MASK_FASTER_STRUCTS 0x4000000
587 #define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS)
589 /* Use IEEE quad long double. */
590 #define MASK_LONG_DOUBLE_128 0x8000000
591 #define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
593 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
594 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
595 to get high 32 bits. False in V8+ or V9 because multiply stores
596 a 64 bit result in a register. */
598 #define TARGET_HARD_MUL32 \
599 ((TARGET_V8 || TARGET_SPARCLITE \
600 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
601 && ! TARGET_V8PLUS && TARGET_ARCH32)
603 #define TARGET_HARD_MUL \
604 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
605 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
608 /* Macro to define tables used to set the flags.
609 This is a list in braces of pairs in braces,
610 each pair being { "NAME", VALUE }
611 where VALUE is the bits to set or minus the bits to clear.
612 An empty string NAME is used to identify the default VALUE. */
614 #define TARGET_SWITCHES \
615 { {"fpu", MASK_FPU | MASK_FPU_SET, \
616 N_("Use hardware fp") }, \
617 {"no-fpu", -MASK_FPU, \
618 N_("Do not use hardware fp") }, \
619 {"no-fpu", MASK_FPU_SET, NULL, }, \
620 {"hard-float", MASK_FPU | MASK_FPU_SET, \
621 N_("Use hardware fp") }, \
622 {"soft-float", -MASK_FPU, \
623 N_("Do not use hardware fp") }, \
624 {"soft-float", MASK_FPU_SET, NULL }, \
625 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
626 N_("Assume possible double misalignment") }, \
627 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
628 N_("Assume all doubles are aligned") }, \
629 {"impure-text", MASK_IMPURE_TEXT, \
630 N_("Pass -assert pure-text to linker") }, \
631 {"no-impure-text", -MASK_IMPURE_TEXT, \
632 N_("Do not pass -assert pure-text to linker") }, \
633 {"app-regs", MASK_APP_REGS, \
634 N_("Use ABI reserved registers") }, \
635 {"no-app-regs", -MASK_APP_REGS, \
636 N_("Do not use ABI reserved registers") }, \
637 {"hard-quad-float", MASK_HARD_QUAD, \
638 N_("Use hardware quad fp instructions") }, \
639 {"soft-quad-float", -MASK_HARD_QUAD, \
640 N_("Do not use hardware quad fp instructions") }, \
641 {"v8plus", MASK_V8PLUS, \
642 N_("Compile for v8plus ABI") }, \
643 {"no-v8plus", -MASK_V8PLUS, \
644 N_("Do not compile for v8plus ABI") }, \
646 N_("Utilize Visual Instruction Set") }, \
647 {"no-vis", -MASK_VIS, \
648 N_("Do not utilize Visual Instruction Set") }, \
649 {"ptr64", MASK_PTR64, \
650 N_("Pointers are 64-bit") }, \
651 {"ptr32", -MASK_PTR64, \
652 N_("Pointers are 32-bit") }, \
653 {"32", -MASK_64BIT, \
654 N_("Use 32-bit ABI") }, \
656 N_("Use 64-bit ABI") }, \
657 {"stack-bias", MASK_STACK_BIAS, \
658 N_("Use stack bias") }, \
659 {"no-stack-bias", -MASK_STACK_BIAS, \
660 N_("Do not use stack bias") }, \
661 {"faster-structs", MASK_FASTER_STRUCTS, \
662 N_("Use structs on stronger alignment for double-word copies") }, \
663 {"no-faster-structs", -MASK_FASTER_STRUCTS, \
664 N_("Do not use structs on stronger alignment for double-word copies") }, \
666 N_("Optimize tail call instructions in assembler and linker") }, \
668 N_("Do not optimize tail call instructions in assembler or linker") }, \
670 { "", TARGET_DEFAULT, ""}}
672 /* MASK_APP_REGS must always be the default because that's what
673 FIXED_REGISTERS is set to and -ffixed- is processed before
674 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
675 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
677 /* This is meant to be redefined in target specific files. */
678 #define SUBTARGET_SWITCHES
681 These must match the values for the cpu attribute in sparc.md. */
682 enum processor_type
{
686 PROCESSOR_SUPERSPARC
,
690 PROCESSOR_HYPERSPARC
,
691 PROCESSOR_SPARCLITE86X
,
695 PROCESSOR_ULTRASPARC
,
696 PROCESSOR_ULTRASPARC3
699 /* This is set from -m{cpu,tune}=xxx. */
700 extern enum processor_type sparc_cpu
;
702 /* Recast the cpu class to be the cpu attribute.
703 Every file includes us, but not every file includes insn-attr.h. */
704 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
706 #define TARGET_OPTIONS \
708 { "cpu=", &sparc_select[1].string, \
709 N_("Use features of and schedule code for given CPU"), 0}, \
710 { "tune=", &sparc_select[2].string, \
711 N_("Schedule code for given CPU"), 0}, \
712 { "cmodel=", &sparc_cmodel_string, \
713 N_("Use given SPARC code model"), 0}, \
717 /* This is meant to be redefined in target specific files. */
718 #define SUBTARGET_OPTIONS
720 /* Support for a compile-time default CPU, et cetera. The rules are:
721 --with-cpu is ignored if -mcpu is specified.
722 --with-tune is ignored if -mtune is specified.
723 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
725 #define OPTION_DEFAULT_SPECS \
726 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
727 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
728 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
730 /* sparc_select[0] is reserved for the default cpu. */
731 struct sparc_cpu_select
734 const char *const name
;
735 const int set_tune_p
;
736 const int set_arch_p
;
739 extern struct sparc_cpu_select sparc_select
[];
741 /* target machine storage layout */
743 /* Define this if most significant bit is lowest numbered
744 in instructions that operate on numbered bit-fields. */
745 #define BITS_BIG_ENDIAN 1
747 /* Define this if most significant byte of a word is the lowest numbered. */
748 #define BYTES_BIG_ENDIAN 1
750 /* Define this if most significant word of a multiword number is the lowest
752 #define WORDS_BIG_ENDIAN 1
754 /* Define this to set the endianness to use in libgcc2.c, which can
755 not depend on target_flags. */
756 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
757 #define LIBGCC2_WORDS_BIG_ENDIAN 0
759 #define LIBGCC2_WORDS_BIG_ENDIAN 1
762 #define MAX_BITS_PER_WORD 64
764 /* Width of a word, in units (bytes). */
765 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
767 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
769 #define MIN_UNITS_PER_WORD 4
772 #define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : 0)
774 /* Now define the sizes of the C data types. */
776 #define SHORT_TYPE_SIZE 16
777 #define INT_TYPE_SIZE 32
778 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
779 #define LONG_LONG_TYPE_SIZE 64
780 #define FLOAT_TYPE_SIZE 32
781 #define DOUBLE_TYPE_SIZE 64
782 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
783 SPARC ABI says that it is 128-bit wide. */
784 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
786 /* Width in bits of a pointer.
787 See also the macro `Pmode' defined below. */
788 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
790 /* If we have to extend pointers (only when TARGET_ARCH64 and not
791 TARGET_PTR64), we want to do it unsigned. This macro does nothing
792 if ptr_mode and Pmode are the same. */
793 #define POINTERS_EXTEND_UNSIGNED 1
795 /* For TARGET_ARCH64 we need this, as we don't have instructions
796 for arithmetic operations which do zero/sign extension at the same time,
797 so without this we end up with a srl/sra after every assignment to an
798 user variable, which means very very bad code. */
799 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
801 && GET_MODE_CLASS (MODE) == MODE_INT \
802 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
805 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
806 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
808 /* Boundary (in *bits*) on which stack pointer should be aligned. */
809 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
810 then sp+2047 is 128-bit aligned so sp is really only byte-aligned. */
811 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
812 /* Temporary hack until the FIXME above is fixed. This macro is used
813 only in pad_to_arg_alignment in function.c; see the comment there
814 for details about what it does. */
815 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
817 /* ALIGN FRAMES on double word boundaries */
819 #define SPARC_STACK_ALIGN(LOC) \
820 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
822 /* Allocation boundary (in *bits*) for the code of a function. */
823 #define FUNCTION_BOUNDARY 32
825 /* Alignment of field after `int : 0' in a structure. */
826 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
828 /* Every structure's size must be a multiple of this. */
829 #define STRUCTURE_SIZE_BOUNDARY 8
831 /* A bit-field declared as `int' forces `int' alignment for the struct. */
832 #define PCC_BITFIELD_TYPE_MATTERS 1
834 /* No data type wants to be aligned rounder than this. */
835 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
837 /* The best alignment to use in cases where we have a choice. */
838 #define FASTEST_ALIGNMENT 64
840 /* Define this macro as an expression for the alignment of a structure
841 (given by STRUCT as a tree node) if the alignment computed in the
842 usual way is COMPUTED and the alignment explicitly specified was
845 The default is to use SPECIFIED if it is larger; otherwise, use
846 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
847 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
848 (TARGET_FASTER_STRUCTS ? \
849 ((TREE_CODE (STRUCT) == RECORD_TYPE \
850 || TREE_CODE (STRUCT) == UNION_TYPE \
851 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
852 && TYPE_FIELDS (STRUCT) != 0 \
853 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
854 : MAX ((COMPUTED), (SPECIFIED))) \
855 : MAX ((COMPUTED), (SPECIFIED)))
857 /* Make strings word-aligned so strcpy from constants will be faster. */
858 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
859 ((TREE_CODE (EXP) == STRING_CST \
860 && (ALIGN) < FASTEST_ALIGNMENT) \
861 ? FASTEST_ALIGNMENT : (ALIGN))
863 /* Make arrays of chars word-aligned for the same reasons. */
864 #define DATA_ALIGNMENT(TYPE, ALIGN) \
865 (TREE_CODE (TYPE) == ARRAY_TYPE \
866 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
867 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
869 /* Set this nonzero if move instructions will actually fail to work
870 when given unaligned data. */
871 #define STRICT_ALIGNMENT 1
873 /* Things that must be doubleword aligned cannot go in the text section,
874 because the linker fails to align the text section enough!
875 Put them in the data section. This macro is only used in this file. */
876 #define MAX_TEXT_ALIGN 32
878 /* Standard register usage. */
880 /* Number of actual hardware registers.
881 The hardware registers are assigned numbers for the compiler
882 from 0 to just below FIRST_PSEUDO_REGISTER.
883 All registers that the compiler knows about must be given numbers,
884 even those that are not normally considered general registers.
886 SPARC has 32 integer registers and 32 floating point registers.
887 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
888 accessible. We still account for them to simplify register computations
889 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
891 Register 100 is used as the integer condition code register.
892 Register 101 is used as the soft frame pointer register. */
894 #define FIRST_PSEUDO_REGISTER 102
896 #define SPARC_FIRST_FP_REG 32
897 /* Additional V9 fp regs. */
898 #define SPARC_FIRST_V9_FP_REG 64
899 #define SPARC_LAST_V9_FP_REG 95
900 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
901 #define SPARC_FIRST_V9_FCC_REG 96
902 #define SPARC_LAST_V9_FCC_REG 99
904 #define SPARC_FCC_REG 96
905 /* Integer CC reg. We don't distinguish %icc from %xcc. */
906 #define SPARC_ICC_REG 100
908 /* Nonzero if REGNO is an fp reg. */
909 #define SPARC_FP_REG_P(REGNO) \
910 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
912 /* Argument passing regs. */
913 #define SPARC_OUTGOING_INT_ARG_FIRST 8
914 #define SPARC_INCOMING_INT_ARG_FIRST 24
915 #define SPARC_FP_ARG_FIRST 32
917 /* 1 for registers that have pervasive standard uses
918 and are not available for the register allocator.
921 g1 is free to use as temporary.
922 g2-g4 are reserved for applications. Gcc normally uses them as
923 temporaries, but this can be disabled via the -mno-app-regs option.
924 g5 through g7 are reserved for the operating system.
927 g1,g5 are free to use as temporaries, and are free to use between calls
928 if the call is to an external function via the PLT.
929 g4 is free to use as a temporary in the non-embedded case.
930 g4 is reserved in the embedded case.
931 g2-g3 are reserved for applications. Gcc normally uses them as
932 temporaries, but this can be disabled via the -mno-app-regs option.
933 g6-g7 are reserved for the operating system (or application in
935 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
936 currently be a fixed register until this pattern is rewritten.
937 Register 1 is also used when restoring call-preserved registers in large
940 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
941 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
944 #define FIXED_REGISTERS \
945 {1, 0, 2, 2, 2, 2, 1, 1, \
946 0, 0, 0, 0, 0, 0, 1, 0, \
947 0, 0, 0, 0, 0, 0, 0, 0, \
948 0, 0, 0, 0, 0, 0, 1, 1, \
950 0, 0, 0, 0, 0, 0, 0, 0, \
951 0, 0, 0, 0, 0, 0, 0, 0, \
952 0, 0, 0, 0, 0, 0, 0, 0, \
953 0, 0, 0, 0, 0, 0, 0, 0, \
955 0, 0, 0, 0, 0, 0, 0, 0, \
956 0, 0, 0, 0, 0, 0, 0, 0, \
957 0, 0, 0, 0, 0, 0, 0, 0, \
958 0, 0, 0, 0, 0, 0, 0, 0, \
962 /* 1 for registers not available across function calls.
963 These must include the FIXED_REGISTERS and also any
964 registers that can be used without being saved.
965 The latter must include the registers where values are returned
966 and the register where structure-value addresses are passed.
967 Aside from that, you can include as many other registers as you like. */
969 #define CALL_USED_REGISTERS \
970 {1, 1, 1, 1, 1, 1, 1, 1, \
971 1, 1, 1, 1, 1, 1, 1, 1, \
972 0, 0, 0, 0, 0, 0, 0, 0, \
973 0, 0, 0, 0, 0, 0, 1, 1, \
975 1, 1, 1, 1, 1, 1, 1, 1, \
976 1, 1, 1, 1, 1, 1, 1, 1, \
977 1, 1, 1, 1, 1, 1, 1, 1, \
978 1, 1, 1, 1, 1, 1, 1, 1, \
980 1, 1, 1, 1, 1, 1, 1, 1, \
981 1, 1, 1, 1, 1, 1, 1, 1, \
982 1, 1, 1, 1, 1, 1, 1, 1, \
983 1, 1, 1, 1, 1, 1, 1, 1, \
987 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
988 they won't be allocated. */
990 #define CONDITIONAL_REGISTER_USAGE \
993 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
995 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
996 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
998 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
999 /* then honor it. */ \
1000 if (TARGET_ARCH32 && fixed_regs[5]) \
1001 fixed_regs[5] = 1; \
1002 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
1003 fixed_regs[5] = 0; \
1007 for (regno = SPARC_FIRST_V9_FP_REG; \
1008 regno <= SPARC_LAST_V9_FP_REG; \
1010 fixed_regs[regno] = 1; \
1011 /* %fcc0 is used by v8 and v9. */ \
1012 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
1013 regno <= SPARC_LAST_V9_FCC_REG; \
1015 fixed_regs[regno] = 1; \
1020 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
1021 fixed_regs[regno] = 1; \
1023 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
1024 /* then honor it. Likewise with g3 and g4. */ \
1025 if (fixed_regs[2] == 2) \
1026 fixed_regs[2] = ! TARGET_APP_REGS; \
1027 if (fixed_regs[3] == 2) \
1028 fixed_regs[3] = ! TARGET_APP_REGS; \
1029 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
1030 fixed_regs[4] = ! TARGET_APP_REGS; \
1031 else if (TARGET_CM_EMBMEDANY) \
1032 fixed_regs[4] = 1; \
1033 else if (fixed_regs[4] == 2) \
1034 fixed_regs[4] = 0; \
1038 /* Return number of consecutive hard regs needed starting at reg REGNO
1039 to hold something of mode MODE.
1040 This is ordinarily the length in words of a value of mode MODE
1041 but can be less for certain modes in special long registers.
1043 On SPARC, ordinary registers hold 32 bits worth;
1044 this means both integer and floating point registers.
1045 On v9, integer regs hold 64 bits worth; floating point regs hold
1046 32 bits worth (this includes the new fp regs as even the odd ones are
1047 included in the hard register count). */
1049 #define HARD_REGNO_NREGS(REGNO, MODE) \
1051 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
1052 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
1053 : (GET_MODE_SIZE (MODE) + 3) / 4) \
1054 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1056 /* Due to the ARCH64 discrepancy above we must override this next
1058 #define REGMODE_NATURAL_SIZE(MODE) \
1059 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
1061 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1062 See sparc.c for how we initialize this. */
1063 extern const int *hard_regno_mode_classes
;
1064 extern int sparc_mode_class
[];
1066 /* ??? Because of the funny way we pass parameters we should allow certain
1067 ??? types of float/complex values to be in integer registers during
1068 ??? RTL generation. This only matters on arch32. */
1069 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1070 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
1072 /* Value is 1 if it is a good idea to tie two pseudo registers
1073 when one has mode MODE1 and one has mode MODE2.
1074 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1075 for any hard reg, then this must be 0 for correct output.
1077 For V9: SFmode can't be combined with other float modes, because they can't
1078 be allocated to the %d registers. Also, DFmode won't fit in odd %f
1079 registers, but SFmode will. */
1080 #define MODES_TIEABLE_P(MODE1, MODE2) \
1081 ((MODE1) == (MODE2) \
1082 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1084 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
1085 || (MODE1 != SFmode && MODE2 != SFmode)))))
1087 /* Specify the registers used for certain standard purposes.
1088 The values of these macros are register numbers. */
1090 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
1091 /* #define PC_REGNUM */
1093 /* Register to use for pushing function arguments. */
1094 #define STACK_POINTER_REGNUM 14
1096 /* The stack bias (amount by which the hardware register is offset by). */
1097 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
1099 /* Actual top-of-stack address is 92/176 greater than the contents of the
1100 stack pointer register for !v9/v9. That is:
1101 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
1102 address, and 6*4 bytes for the 6 register parameters.
1103 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
1105 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
1107 /* Base register for access to local variables of the function. */
1108 #define HARD_FRAME_POINTER_REGNUM 30
1110 /* The soft frame pointer does not have the stack bias applied. */
1111 #define FRAME_POINTER_REGNUM 101
1113 /* Given the stack bias, the stack pointer isn't actually aligned. */
1114 #define INIT_EXPANDERS \
1116 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
1118 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
1119 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
1123 /* Value should be nonzero if functions must have frame pointers.
1124 Zero means the frame pointer need not be set up (and parms
1125 may be accessed via the stack pointer) in functions that seem suitable.
1126 Used in flow.c, global.c, ra.c and reload1.c. */
1127 #define FRAME_POINTER_REQUIRED \
1128 (! (leaf_function_p () && only_leaf_regs_used ()))
1130 /* Base register for access to arguments of the function. */
1131 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1133 /* Register in which static-chain is passed to a function. This must
1134 not be a register used by the prologue. */
1135 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
1137 /* Register which holds offset table for position-independent
1140 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
1142 /* Pick a default value we can notice from override_options:
1144 v9: Default is off. */
1146 #define DEFAULT_PCC_STRUCT_RETURN -1
1148 /* Functions which return large structures get the address
1149 to place the wanted value at offset 64 from the frame.
1150 Must reserve 64 bytes for the in and local registers.
1151 v9: Functions which return large structures get the address to place the
1152 wanted value from an invisible first argument. */
1153 #define STRUCT_VALUE_OFFSET 64
1155 /* Define the classes of registers for register constraints in the
1156 machine description. Also define ranges of constants.
1158 One of the classes must always be named ALL_REGS and include all hard regs.
1159 If there is more than one class, another class must be named NO_REGS
1160 and contain no registers.
1162 The name GENERAL_REGS must be the name of a class (or an alias for
1163 another name such as ALL_REGS). This is the class of registers
1164 that is allowed by "g" or "r" in a register constraint.
1165 Also, registers outside this class are allocated only when
1166 instructions express preferences for them.
1168 The classes must be numbered in nondecreasing order; that is,
1169 a larger-numbered class must never be contained completely
1170 in a smaller-numbered class.
1172 For any two classes, it is very desirable that there be another
1173 class that represents their union. */
1175 /* The SPARC has various kinds of registers: general, floating point,
1176 and condition codes [well, it has others as well, but none that we
1177 care directly about].
1179 For v9 we must distinguish between the upper and lower floating point
1180 registers because the upper ones can't hold SFmode values.
1181 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1182 satisfying a group need for a class will also satisfy a single need for
1183 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1186 It is important that one class contains all the general and all the standard
1187 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1188 because reg_class_record() will bias the selection in favor of fp regs,
1189 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1190 because FP_REGS > GENERAL_REGS.
1192 It is also important that one class contain all the general and all the
1193 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
1194 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
1195 allocate_reload_reg() to bypass it causing an abort because the compiler
1196 thinks it doesn't have a spill reg when in fact it does.
1198 v9 also has 4 floating point condition code registers. Since we don't
1199 have a class that is the union of FPCC_REGS with either of the others,
1200 it is important that it appear first. Otherwise the compiler will die
1201 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1204 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1205 may try to use it to hold an SImode value. See register_operand.
1206 ??? Should %fcc[0123] be handled similarly?
1209 enum reg_class
{ NO_REGS
, FPCC_REGS
, I64_REGS
, GENERAL_REGS
, FP_REGS
,
1210 EXTRA_FP_REGS
, GENERAL_OR_FP_REGS
, GENERAL_OR_EXTRA_FP_REGS
,
1211 ALL_REGS
, LIM_REG_CLASSES
};
1213 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1215 /* Give names of register classes as strings for dump file. */
1217 #define REG_CLASS_NAMES \
1218 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1219 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1222 /* Define which registers fit in which classes.
1223 This is an initializer for a vector of HARD_REG_SET
1224 of length N_REG_CLASSES. */
1226 #define REG_CLASS_CONTENTS \
1227 {{0, 0, 0, 0}, /* NO_REGS */ \
1228 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1229 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1230 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1231 {0, -1, 0, 0}, /* FP_REGS */ \
1232 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1233 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1234 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1235 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1237 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1239 SImode loads to floating-point registers are not zero-extended.
1240 The definition for LOAD_EXTEND_OP specifies that integer loads
1241 narrower than BITS_PER_WORD will be zero-extended. As a result,
1242 we inhibit changes from SImode unless they are to a mode that is
1243 identical in size. */
1245 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1247 && (FROM) == SImode \
1248 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1249 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1251 /* The same information, inverted:
1252 Return the class number of the smallest class containing
1253 reg number REGNO. This could be a conditional expression
1254 or could index an array. */
1256 extern enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
1258 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1260 /* This is the order in which to allocate registers normally.
1262 We put %f0-%f7 last among the float registers, so as to make it more
1263 likely that a pseudo-register which dies in the float return register
1264 area will get allocated to the float return register, thus saving a move
1265 instruction at the end of the function.
1267 Similarly for integer return value registers.
1269 We know in this case that we will not end up with a leaf function.
1271 The register allocator is given the global and out registers first
1272 because these registers are call clobbered and thus less useful to
1273 global register allocation.
1275 Next we list the local and in registers. They are not call clobbered
1276 and thus very useful for global register allocation. We list the input
1277 registers before the locals so that it is more likely the incoming
1278 arguments received in those registers can just stay there and not be
1281 #define REG_ALLOC_ORDER \
1282 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1283 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1285 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1286 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1287 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1288 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1289 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1290 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1291 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1292 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1293 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1294 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1295 96, 97, 98, 99, /* %fcc0-3 */ \
1296 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1298 /* This is the order in which to allocate registers for
1299 leaf functions. If all registers can fit in the global and
1300 output registers, then we have the possibility of having a leaf
1303 The macro actually mentioned the input registers first,
1304 because they get renumbered into the output registers once
1305 we know really do have a leaf function.
1307 To be more precise, this register allocation order is used
1308 when %o7 is found to not be clobbered right before register
1309 allocation. Normally, the reason %o7 would be clobbered is
1310 due to a call which could not be transformed into a sibling
1313 As a consequence, it is possible to use the leaf register
1314 allocation order and not end up with a leaf function. We will
1315 not get suboptimal register allocation in that case because by
1316 definition of being potentially leaf, there were no function
1317 calls. Therefore, allocation order within the local register
1318 window is not critical like it is when we do have function calls. */
1320 #define REG_LEAF_ALLOC_ORDER \
1321 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1322 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1324 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1325 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1326 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1327 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1328 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1329 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1330 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1331 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1332 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1333 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1334 96, 97, 98, 99, /* %fcc0-3 */ \
1335 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1337 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1339 extern char sparc_leaf_regs
[];
1340 #define LEAF_REGISTERS sparc_leaf_regs
1342 extern char leaf_reg_remap
[];
1343 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1345 /* The class value for index registers, and the one for base regs. */
1346 #define INDEX_REG_CLASS GENERAL_REGS
1347 #define BASE_REG_CLASS GENERAL_REGS
1349 /* Local macro to handle the two v9 classes of FP regs. */
1350 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1352 /* Get reg_class from a letter such as appears in the machine description.
1353 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1354 .md file for v8 and v9.
1355 'd' and 'b' are used for single and double precision VIS operations,
1357 'h' is used for V8+ 64 bit global and out registers. */
1359 #define REG_CLASS_FROM_LETTER(C) \
1361 ? ((C) == 'f' ? FP_REGS \
1362 : (C) == 'e' ? EXTRA_FP_REGS \
1363 : (C) == 'c' ? FPCC_REGS \
1364 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1365 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1366 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1368 : ((C) == 'f' ? FP_REGS \
1369 : (C) == 'e' ? FP_REGS \
1370 : (C) == 'c' ? FPCC_REGS \
1373 /* The letters I, J, K, L and M in a register constraint string
1374 can be used to stand for particular ranges of immediate operands.
1375 This macro defines what the ranges are.
1376 C is the letter, and VALUE is a constant value.
1377 Return 1 if VALUE is in the range specified by C.
1379 `I' is used for the range of constants an insn can actually contain.
1380 `J' is used for the range which is just zero (since that is R0).
1381 `K' is used for constants which can be loaded with a single sethi insn.
1382 `L' is used for the range of constants supported by the movcc insns.
1383 `M' is used for the range of constants supported by the movrcc insns.
1384 `N' is like K, but for constants wider than 32 bits.
1385 `O' is used for the range which is just 4096. */
1387 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1388 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1389 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1390 /* 10 and 11 bit immediates are only used for a few specific insns.
1391 SMALL_INT is used throughout the port so we continue to use it. */
1392 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1393 /* 13 bit immediate, considering only the low 32 bits */
1394 #define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
1395 (INTVAL (X), SImode)))
1396 #define SPARC_SETHI_P(X) \
1397 (((unsigned HOST_WIDE_INT) (X) \
1398 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1399 #define SPARC_SETHI32_P(X) \
1400 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1402 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1403 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1404 : (C) == 'J' ? (VALUE) == 0 \
1405 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1406 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1407 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1408 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1409 : (C) == 'O' ? (VALUE) == 4096 \
1412 /* Similar, but for floating constants, and defining letters G and H.
1413 Here VALUE is the CONST_DOUBLE rtx itself. */
1415 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1416 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
1417 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1418 : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \
1421 /* Given an rtx X being reloaded into a reg required to be
1422 in class CLASS, return the class of reg to actually use.
1423 In general this is just CLASS; but on some machines
1424 in some cases it is preferable to use a more restrictive class. */
1425 /* - We can't load constants into FP registers.
1426 - We can't load FP constants into integer registers when soft-float,
1427 because there is no soft-float pattern with a r/F constraint.
1428 - We can't load FP constants into integer registers for TFmode unless
1429 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1430 - Try and reload integer constants (symbolic or otherwise) back into
1431 registers directly, rather than having them dumped to memory. */
1433 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1435 ? ((FP_REG_CLASS_P (CLASS) \
1436 || (CLASS) == GENERAL_OR_FP_REGS \
1437 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1438 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1440 || (GET_MODE (X) == TFmode \
1441 && ! fp_zero_operand (X, TFmode))) \
1443 : (!FP_REG_CLASS_P (CLASS) \
1444 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1449 /* Return the register class of a scratch register needed to load IN into
1450 a register of class CLASS in MODE.
1452 We need a temporary when loading/storing a HImode/QImode value
1453 between memory and the FPU registers. This can happen when combine puts
1454 a paradoxical subreg in a float/fix conversion insn.
1456 We need a temporary when loading/storing a DFmode value between
1457 unaligned memory and the upper FPU registers. */
1459 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1460 ((FP_REG_CLASS_P (CLASS) \
1461 && ((MODE) == HImode || (MODE) == QImode) \
1462 && (GET_CODE (IN) == MEM \
1463 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1464 && true_regnum (IN) == -1))) \
1466 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1467 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1468 && ! mem_min_alignment ((IN), 8)) \
1470 : (((TARGET_CM_MEDANY \
1471 && symbolic_operand ((IN), (MODE))) \
1472 || (TARGET_CM_EMBMEDANY \
1473 && text_segment_operand ((IN), (MODE)))) \
1478 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1479 ((FP_REG_CLASS_P (CLASS) \
1480 && ((MODE) == HImode || (MODE) == QImode) \
1481 && (GET_CODE (IN) == MEM \
1482 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1483 && true_regnum (IN) == -1))) \
1485 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1486 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1487 && ! mem_min_alignment ((IN), 8)) \
1489 : (((TARGET_CM_MEDANY \
1490 && symbolic_operand ((IN), (MODE))) \
1491 || (TARGET_CM_EMBMEDANY \
1492 && text_segment_operand ((IN), (MODE)))) \
1497 /* On SPARC it is not possible to directly move data between
1498 GENERAL_REGS and FP_REGS. */
1499 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1500 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1502 /* Return the stack location to use for secondary memory needed reloads.
1503 We want to use the reserved location just below the frame pointer.
1504 However, we must ensure that there is a frame, so use assign_stack_local
1505 if the frame size is zero. */
1506 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1507 (get_frame_size () == 0 \
1508 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1509 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1510 STARTING_FRAME_OFFSET)))
1512 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1513 because the movsi and movsf patterns don't handle r/f moves.
1514 For v8 we copy the default definition. */
1515 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1517 ? (GET_MODE_BITSIZE (MODE) < 32 \
1518 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1520 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1521 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1524 /* Return the maximum number of consecutive registers
1525 needed to represent mode MODE in a register of class CLASS. */
1526 /* On SPARC, this is the size of MODE in words. */
1527 #define CLASS_MAX_NREGS(CLASS, MODE) \
1528 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1529 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1531 /* Stack layout; function entry, exit and calling. */
1533 /* Define this if pushing a word on the stack
1534 makes the stack pointer a smaller address. */
1535 #define STACK_GROWS_DOWNWARD
1537 /* Define this if the nominal address of the stack frame
1538 is at the high-address end of the local variables;
1539 that is, each additional local variable allocated
1540 goes at a more negative offset in the frame. */
1541 #define FRAME_GROWS_DOWNWARD
1543 /* Offset within stack frame to start allocating local variables at.
1544 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1545 first local allocated. Otherwise, it is the offset to the BEGINNING
1546 of the first local allocated. */
1547 /* This allows space for one TFmode floating point value. */
1548 #define STARTING_FRAME_OFFSET \
1549 (TARGET_ARCH64 ? -16 \
1550 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1552 /* If we generate an insn to push BYTES bytes,
1553 this says how many the stack pointer really advances by.
1554 On SPARC, don't define this because there are no push insns. */
1555 /* #define PUSH_ROUNDING(BYTES) */
1557 /* Offset of first parameter from the argument pointer register value.
1558 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1559 even if this function isn't going to use it.
1560 v9: This is 128 for the ins and locals. */
1561 #define FIRST_PARM_OFFSET(FNDECL) \
1562 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1564 /* Offset from the argument pointer register value to the CFA.
1565 This is different from FIRST_PARM_OFFSET because the register window
1566 comes between the CFA and the arguments. */
1567 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1569 /* When a parameter is passed in a register, stack space is still
1571 !v9: All 6 possible integer registers have backing store allocated.
1572 v9: Only space for the arguments passed is allocated. */
1573 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1574 meaning to the backend. Further, we need to be able to detect if a
1575 varargs/unprototyped function is called, as they may want to spill more
1576 registers than we've provided space. Ugly, ugly. So for now we retain
1577 all 6 slots even for v9. */
1578 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1580 /* Definitions for register elimination. */
1582 #define ELIMINABLE_REGS \
1583 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1584 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1586 /* The way this is structured, we can't eliminate SFP in favor of SP
1587 if the frame pointer is required: we want to use the SFP->HFP elimination
1588 in that case. But the test in update_eliminables doesn't know we are
1589 assuming below that we only do the former elimination. */
1590 #define CAN_ELIMINATE(FROM, TO) \
1591 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1593 /* We always pretend that this is a leaf function because if it's not,
1594 there's no point in trying to eliminate the frame pointer. If it
1595 is a leaf function, we guessed right! */
1596 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1598 if ((TO) == STACK_POINTER_REGNUM) \
1599 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \
1602 (OFFSET) += SPARC_STACK_BIAS; \
1605 /* Keep the stack pointer constant throughout the function.
1606 This is both an optimization and a necessity: longjmp
1607 doesn't behave itself when the stack pointer moves within
1609 #define ACCUMULATE_OUTGOING_ARGS 1
1611 /* Value is the number of bytes of arguments automatically
1612 popped when returning from a subroutine call.
1613 FUNDECL is the declaration node of the function (as a tree),
1614 FUNTYPE is the data type of the function (as a tree),
1615 or for a library call it is an identifier node for the subroutine name.
1616 SIZE is the number of bytes of arguments passed on the stack. */
1618 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1620 /* Define this macro if the target machine has "register windows". This
1621 C expression returns the register number as seen by the called function
1622 corresponding to register number OUT as seen by the calling function.
1623 Return OUT if register number OUT is not an outbound register. */
1625 #define INCOMING_REGNO(OUT) \
1626 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1628 /* Define this macro if the target machine has "register windows". This
1629 C expression returns the register number as seen by the calling function
1630 corresponding to register number IN as seen by the called function.
1631 Return IN if register number IN is not an inbound register. */
1633 #define OUTGOING_REGNO(IN) \
1634 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1636 /* Define this macro if the target machine has register windows. This
1637 C expression returns true if the register is call-saved but is in the
1640 #define LOCAL_REGNO(REGNO) \
1641 ((REGNO) >= 16 && (REGNO) <= 31)
1643 /* Define how to find the value returned by a function.
1644 VALTYPE is the data type of the value (as a tree).
1645 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1646 otherwise, FUNC is 0. */
1648 /* On SPARC the value is found in the first "output" register. */
1650 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1651 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1653 /* But the called function leaves it in the first "input" register. */
1655 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1656 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1658 /* Define how to find the value returned by a library function
1659 assuming the value has mode MODE. */
1661 #define LIBCALL_VALUE(MODE) \
1662 function_value (NULL_TREE, (MODE), 1)
1664 /* 1 if N is a possible register number for a function value
1665 as seen by the caller.
1666 On SPARC, the first "output" reg is used for integer values,
1667 and the first floating point register is used for floating point values. */
1669 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1671 /* Define the size of space to allocate for the return value of an
1674 #define APPLY_RESULT_SIZE 16
1676 /* 1 if N is a possible register number for function argument passing.
1677 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1679 #define FUNCTION_ARG_REGNO_P(N) \
1681 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1682 : ((N) >= 8 && (N) <= 13))
1684 /* Define a data type for recording info about an argument list
1685 during the scan of that argument list. This data type should
1686 hold all necessary information about the function itself
1687 and about the args processed so far, enough to enable macros
1688 such as FUNCTION_ARG to determine where the next arg should go.
1690 On SPARC (!v9), this is a single integer, which is a number of words
1691 of arguments scanned so far (including the invisible argument,
1692 if any, which holds the structure-value-address).
1693 Thus 7 or more means all following args should go on the stack.
1695 For v9, we also need to know whether a prototype is present. */
1698 int words
; /* number of words passed so far */
1699 int prototype_p
; /* nonzero if a prototype is present */
1700 int libcall_p
; /* nonzero if a library call */
1702 #define CUMULATIVE_ARGS struct sparc_args
1704 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1705 for a call to a function whose data type is FNTYPE.
1706 For a library call, FNTYPE is 0. */
1708 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1709 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1711 /* Update the data in CUM to advance over an argument
1712 of mode MODE and data type TYPE.
1713 TYPE is null for libcalls where that information may not be available. */
1715 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1716 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1718 /* Determine where to put an argument to a function.
1719 Value is zero to push the argument on the stack,
1720 or a hard register in which to store the argument.
1722 MODE is the argument's machine mode.
1723 TYPE is the data type of the argument (as a tree).
1724 This is null for libcalls where that information may
1726 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1727 the preceding args and about the function being called.
1728 NAMED is nonzero if this argument is a named parameter
1729 (otherwise it is an extra parameter matching an ellipsis). */
1731 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1732 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1734 /* Define where a function finds its arguments.
1735 This is different from FUNCTION_ARG because of register windows. */
1737 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1738 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1740 /* For an arg passed partly in registers and partly in memory,
1741 this is the number of registers used.
1742 For args passed entirely in registers or entirely in memory, zero. */
1744 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1745 function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED))
1747 /* If defined, a C expression which determines whether, and in which direction,
1748 to pad out an argument with extra space. The value should be of type
1749 `enum direction': either `upward' to pad above the argument,
1750 `downward' to pad below, or `none' to inhibit padding. */
1752 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1753 function_arg_padding ((MODE), (TYPE))
1755 /* If defined, a C expression that gives the alignment boundary, in bits,
1756 of an argument with the specified mode and type. If it is not defined,
1757 PARM_BOUNDARY is used for all arguments.
1758 For sparc64, objects requiring 16 byte alignment are passed that way. */
1760 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1762 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1763 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1764 ? 128 : PARM_BOUNDARY)
1766 /* Define the information needed to generate branch and scc insns. This is
1767 stored from the compare operation. Note that we can't use "rtx" here
1768 since it hasn't been defined! */
1770 extern GTY(()) rtx sparc_compare_op0
;
1771 extern GTY(()) rtx sparc_compare_op1
;
1774 /* Generate the special assembly code needed to tell the assembler whatever
1775 it might need to know about the return value of a function.
1777 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1778 information to the assembler relating to peephole optimization (done in
1781 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1782 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1784 /* Output the special assembly code needed to tell the assembler some
1785 register is used as global register variable.
1787 SPARC 64bit psABI declares registers %g2 and %g3 as application
1788 registers and %g6 and %g7 as OS registers. Any object using them
1789 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1790 and how they are used (scratch or some global variable).
1791 Linker will then refuse to link together objects which use those
1792 registers incompatibly.
1794 Unless the registers are used for scratch, two different global
1795 registers cannot be declared to the same name, so in the unlikely
1796 case of a global register variable occupying more than one register
1797 we prefix the second and following registers with .gnu.part1. etc. */
1799 extern char sparc_hard_reg_printed
[8];
1801 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1802 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1804 if (TARGET_ARCH64) \
1806 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1808 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1809 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1811 if (reg == (REGNO)) \
1812 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1814 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1815 reg, reg - (REGNO), (NAME)); \
1816 sparc_hard_reg_printed[reg] = 1; \
1823 /* Emit rtl for profiling. */
1824 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1826 /* All the work done in PROFILE_HOOK, but still required. */
1827 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1829 /* Set the name of the mcount function for the system. */
1830 #define MCOUNT_FUNCTION "*mcount"
1832 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1833 the stack pointer does not matter. The value is tested only in
1834 functions that have frame pointers.
1835 No definition is equivalent to always zero. */
1837 #define EXIT_IGNORE_STACK \
1838 (get_frame_size () != 0 \
1839 || current_function_calls_alloca || current_function_outgoing_args_size)
1841 /* Define registers used by the epilogue and return instruction. */
1842 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
1843 || (current_function_calls_eh_return && (REGNO) == 1))
1845 /* Length in units of the trampoline for entering a nested function. */
1847 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1849 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1851 /* Emit RTL insns to initialize the variable parts of a trampoline.
1852 FNADDR is an RTX for the address of the function's pure code.
1853 CXT is an RTX for the static chain value for the function. */
1855 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1856 if (TARGET_ARCH64) \
1857 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1859 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1861 /* Implement `va_start' for varargs and stdarg. */
1862 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1863 sparc_va_start (valist, nextarg)
1865 /* Generate RTL to flush the register windows so as to make arbitrary frames
1867 #define SETUP_FRAME_ADDRESSES() \
1868 emit_insn (gen_flush_register_windows ())
1870 /* Given an rtx for the address of a frame,
1871 return an rtx for the address of the word in the frame
1872 that holds the dynamic chain--the previous frame's address. */
1873 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1874 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1876 /* The return address isn't on the stack, it is in a register, so we can't
1877 access it from the current frame pointer. We can access it from the
1878 previous frame pointer though by reading a value from the register window
1880 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1882 /* This is the offset of the return address to the true next instruction to be
1883 executed for the current function. */
1884 #define RETURN_ADDR_OFFSET \
1885 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1887 /* The current return address is in %i7. The return address of anything
1888 farther back is in the register window save area at [%fp+60]. */
1889 /* ??? This ignores the fact that the actual return address is +8 for normal
1890 returns, and +12 for structure returns. */
1891 #define RETURN_ADDR_RTX(count, frame) \
1893 ? gen_rtx_REG (Pmode, 31) \
1894 : gen_rtx_MEM (Pmode, \
1895 memory_address (Pmode, plus_constant (frame, \
1896 15 * UNITS_PER_WORD \
1897 + SPARC_STACK_BIAS))))
1899 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1900 +12, but always using +8 is close enough for frame unwind purposes.
1901 Actually, just using %o7 is close enough for unwinding, but %o7+8
1902 is something you can return to. */
1903 #define INCOMING_RETURN_ADDR_RTX \
1904 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1905 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1907 /* The offset from the incoming value of %sp to the top of the stack frame
1908 for the current function. On sparc64, we have to account for the stack
1910 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1912 /* Describe how we implement __builtin_eh_return. */
1913 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1914 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1915 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1917 /* Select a format to encode pointers in exception handling data. CODE
1918 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1919 true if the symbol may be affected by dynamic relocations.
1921 If assembler and linker properly support .uaword %r_disp32(foo),
1922 then use PC relative 32-bit relocations instead of absolute relocs
1923 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1924 for binaries, to save memory.
1926 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1927 symbol %r_disp32() is against was not local, but .hidden. In that
1928 case, we have to use DW_EH_PE_absptr for pic personality. */
1929 #ifdef HAVE_AS_SPARC_UA_PCREL
1930 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1931 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1933 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1934 : ((TARGET_ARCH64 && ! GLOBAL) \
1935 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1938 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1940 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1941 : ((TARGET_ARCH64 && ! GLOBAL) \
1942 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1946 /* Emit a PC-relative relocation. */
1947 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1949 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1950 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1951 assemble_name (FILE, LABEL); \
1952 fputc (')', FILE); \
1956 /* Addressing modes, and classification of registers for them. */
1958 /* Macros to check register numbers against specific register classes. */
1960 /* These assume that REGNO is a hard or pseudo reg number.
1961 They give nonzero only if REGNO is a hard reg of the suitable class
1962 or a pseudo reg currently allocated to a suitable hard reg.
1963 Since they use reg_renumber, they are safe only once reg_renumber
1964 has been allocated, which happens in local-alloc.c. */
1966 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1967 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
1968 || (REGNO) == FRAME_POINTER_REGNUM \
1969 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1971 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1973 #define REGNO_OK_FOR_FP_P(REGNO) \
1974 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1975 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1976 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1978 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1979 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1981 /* Now macros that check whether X is a register and also,
1982 strictly, whether it is in a specified class.
1984 These macros are specific to the SPARC, and may be used only
1985 in code for printing assembler insns and in conditions for
1986 define_optimization. */
1988 /* 1 if X is an fp register. */
1990 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1992 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
1993 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
1995 /* Maximum number of registers that can appear in a valid memory address. */
1997 #define MAX_REGS_PER_ADDRESS 2
1999 /* Recognize any constant value that is a valid address.
2000 When PIC, we do not accept an address that would require a scratch reg
2001 to load into a register. */
2003 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
2005 /* Define this, so that when PIC, reload won't try to reload invalid
2006 addresses which require two reload registers. */
2008 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
2010 /* Nonzero if the constant value X is a legitimate general operand.
2011 Anything can be made to work except floating point constants.
2012 If TARGET_VIS, 0.0 can be made to work as well. */
2014 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
2016 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2017 and check its validity for a certain class.
2018 We have two alternate definitions for each of them.
2019 The usual definition accepts all pseudo regs; the other rejects
2020 them unless they have been allocated suitable hard regs.
2021 The symbol REG_OK_STRICT causes the latter definition to be used.
2023 Most source files want to accept pseudo regs in the hope that
2024 they will get allocated to the class that the insn wants them to be in.
2025 Source files for reload pass need to be strict.
2026 After reload, it makes no difference, since pseudo regs have
2027 been eliminated by then. */
2029 /* Optional extra constraints for this machine.
2031 'Q' handles floating point constants which can be moved into
2032 an integer register with a single sethi instruction.
2034 'R' handles floating point constants which can be moved into
2035 an integer register with a single mov instruction.
2037 'S' handles floating point constants which can be moved into
2038 an integer register using a high/lo_sum sequence.
2040 'T' handles memory addresses where the alignment is known to
2041 be at least 8 bytes.
2043 `U' handles all pseudo registers or a hard even numbered
2044 integer register, needed for ldd/std instructions.
2046 'W' handles the memory operand when moving operands in/out
2047 of 'e' constraint floating point registers.
2049 'Y' handles the zero vector constant. */
2051 #ifndef REG_OK_STRICT
2053 /* Nonzero if X is a hard reg that can be used as an index
2054 or if it is a pseudo reg. */
2055 #define REG_OK_FOR_INDEX_P(X) \
2057 || REGNO (X) == FRAME_POINTER_REGNUM \
2058 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2060 /* Nonzero if X is a hard reg that can be used as a base reg
2061 or if it is a pseudo reg. */
2062 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
2064 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
2065 'W' is like 'T' but is assumed true on arch64.
2067 Remember to accept pseudo-registers for memory constraints if reload is
2070 #define EXTRA_CONSTRAINT(OP, C) \
2071 sparc_extra_constraint_check(OP, C, 0)
2075 /* Nonzero if X is a hard reg that can be used as an index. */
2076 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
2077 /* Nonzero if X is a hard reg that can be used as a base reg. */
2078 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2080 #define EXTRA_CONSTRAINT(OP, C) \
2081 sparc_extra_constraint_check(OP, C, 1)
2085 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
2087 #ifdef HAVE_AS_OFFSETABLE_LO10
2088 #define USE_AS_OFFSETABLE_LO10 1
2090 #define USE_AS_OFFSETABLE_LO10 0
2093 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2094 that is a valid memory address for an instruction.
2095 The MODE argument is the machine mode for the MEM expression
2096 that wants to use this address.
2098 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
2099 ordinarily. This changes a bit when generating PIC.
2101 If you change this, execute "rm explow.o recog.o reload.o". */
2103 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
2105 #define RTX_OK_FOR_BASE_P(X) \
2106 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2107 || (GET_CODE (X) == SUBREG \
2108 && GET_CODE (SUBREG_REG (X)) == REG \
2109 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2111 #define RTX_OK_FOR_INDEX_P(X) \
2112 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2113 || (GET_CODE (X) == SUBREG \
2114 && GET_CODE (SUBREG_REG (X)) == REG \
2115 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
2117 #define RTX_OK_FOR_OFFSET_P(X) \
2118 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
2120 #define RTX_OK_FOR_OLO10_P(X) \
2121 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
2123 #ifdef REG_OK_STRICT
2124 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2126 if (legitimate_address_p (MODE, X, 1)) \
2130 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2132 if (legitimate_address_p (MODE, X, 0)) \
2137 /* Go to LABEL if ADDR (a legitimate address expression)
2138 has an effect that depends on the machine mode it is used for.
2144 is not equivalent to
2146 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
2148 because [%l7+a+1] is interpreted as the address of (a+1). */
2150 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2152 if (flag_pic == 1) \
2154 if (GET_CODE (ADDR) == PLUS) \
2156 rtx op0 = XEXP (ADDR, 0); \
2157 rtx op1 = XEXP (ADDR, 1); \
2158 if (op0 == pic_offset_table_rtx \
2159 && SYMBOLIC_CONST (op1)) \
2165 /* Try machine-dependent ways of modifying an illegitimate address
2166 to be legitimate. If we find one, return the new, valid address.
2167 This macro is used in only one place: `memory_address' in explow.c.
2169 OLDX is the address as it was before break_out_memory_refs was called.
2170 In some cases it is useful to look at this to decide what needs to be done.
2172 MODE and WIN are passed so that this macro can use
2173 GO_IF_LEGITIMATE_ADDRESS.
2175 It is always safe for this macro to do nothing. It exists to recognize
2176 opportunities to optimize the output. */
2178 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2179 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2181 (X) = legitimize_address (X, OLDX, MODE); \
2182 if (memory_address_p (MODE, X)) \
2186 /* Try a machine-dependent way of reloading an illegitimate address
2187 operand. If we find one, push the reload and jump to WIN. This
2188 macro is used in only one place: `find_reloads_address' in reload.c.
2190 For SPARC 32, we wish to handle addresses by splitting them into
2191 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2192 This cuts the number of extra insns by one.
2194 Do nothing when generating PIC code and the address is a
2195 symbolic operand or requires a scratch register. */
2197 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2199 /* Decompose SImode constants into hi+lo_sum. We do have to \
2200 rerecognize what we produce, so be careful. */ \
2201 if (CONSTANT_P (X) \
2202 && (MODE != TFmode || TARGET_ARCH64) \
2203 && GET_MODE (X) == SImode \
2204 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2206 && (symbolic_operand (X, Pmode) \
2207 || pic_address_needs_scratch (X))) \
2208 && sparc_cmodel <= CM_MEDLOW) \
2210 X = gen_rtx_LO_SUM (GET_MODE (X), \
2211 gen_rtx_HIGH (GET_MODE (X), X), X); \
2212 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2213 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2217 /* ??? 64-bit reloads. */ \
2220 /* Specify the machine mode that this machine uses
2221 for the index in the tablejump instruction. */
2222 /* If we ever implement any of the full models (such as CM_FULLANY),
2223 this has to be DImode in that case */
2224 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2225 #define CASE_VECTOR_MODE \
2226 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2228 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2229 we have to sign extend which slows things down. */
2230 #define CASE_VECTOR_MODE \
2231 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2234 /* Define this as 1 if `char' should by default be signed; else as 0. */
2235 #define DEFAULT_SIGNED_CHAR 1
2237 /* Max number of bytes we can move from memory to memory
2238 in one reasonably fast instruction. */
2241 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2242 move-instruction pairs, we will do a movmem or libcall instead. */
2244 #define MOVE_RATIO (optimize_size ? 3 : 8)
2246 /* Define if operations between registers always perform the operation
2247 on the full register even if a narrower mode is specified. */
2248 #define WORD_REGISTER_OPERATIONS
2250 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2251 will either zero-extend or sign-extend. The value of this macro should
2252 be the code that says which one of the two operations is implicitly
2253 done, UNKNOWN if none. */
2254 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2256 /* Nonzero if access to memory by bytes is slow and undesirable.
2257 For RISC chips, it means that access to memory by bytes is no
2258 better than access by words when possible, so grab a whole word
2259 and maybe make use of that. */
2260 #define SLOW_BYTE_ACCESS 1
2262 /* Define this to be nonzero if shift instructions ignore all but the low-order
2264 #define SHIFT_COUNT_TRUNCATED 1
2266 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2267 is done just by pretending it is already truncated. */
2268 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2270 /* Specify the machine mode used for addresses. */
2271 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2273 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2274 return the mode to be used for the comparison. For floating-point,
2275 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2276 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2277 processing is needed. */
2278 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2280 /* Return nonzero if MODE implies a floating point inequality can be
2281 reversed. For SPARC this is always true because we have a full
2282 compliment of ordered and unordered comparisons, but until generic
2283 code knows how to reverse it correctly we keep the old definition. */
2284 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2286 /* A function address in a call instruction for indexing purposes. */
2287 #define FUNCTION_MODE Pmode
2289 /* Define this if addresses of constant functions
2290 shouldn't be put through pseudo regs where they can be cse'd.
2291 Desirable on machines where ordinary constants are expensive
2292 but a CALL with constant address is cheap. */
2293 #define NO_FUNCTION_CSE
2295 /* alloca should avoid clobbering the old register save area. */
2296 #define SETJMP_VIA_SAVE_AREA
2298 /* The _Q_* comparison libcalls return booleans. */
2299 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2301 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
2302 that the inputs are fully consumed before the output memory is clobbered. */
2304 #define TARGET_BUGGY_QP_LIB 0
2306 /* Assume by default that we do not have the Solaris-specific conversion
2307 routines nor 64-bit integer multiply and divide routines. */
2309 #define SUN_CONVERSION_LIBFUNCS 0
2310 #define DITF_CONVERSION_LIBFUNCS 0
2311 #define SUN_INTEGER_MULTIPLY_64 0
2313 /* Compute extra cost of moving data between one register class
2315 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2316 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2317 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2318 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2319 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2320 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2321 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
2323 /* Provide the cost of a branch. For pre-v9 processors we use
2324 a value of 3 to take into account the potential annulling of
2325 the delay slot (which ends up being a bubble in the pipeline slot)
2326 plus a cycle to take into consideration the instruction cache
2329 On v9 and later, which have branch prediction facilities, we set
2330 it to the depth of the pipeline as that is the cost of a
2331 mispredicted branch. */
2333 #define BRANCH_COST \
2334 ((sparc_cpu == PROCESSOR_V9 \
2335 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2337 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2340 #define PREFETCH_BLOCK \
2341 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2342 || sparc_cpu == PROCESSOR_ULTRASPARC3) \
2345 #define SIMULTANEOUS_PREFETCHES \
2346 ((sparc_cpu == PROCESSOR_ULTRASPARC) \
2348 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2351 /* Control the assembler format that we output. */
2353 /* A C string constant describing how to begin a comment in the target
2354 assembler language. The compiler assumes that the comment will end at
2355 the end of the line. */
2357 #define ASM_COMMENT_START "!"
2359 /* Output to assembler file text saying following lines
2360 may contain character constants, extra white space, comments, etc. */
2362 #define ASM_APP_ON ""
2364 /* Output to assembler file text saying following lines
2365 no longer contain unusual constructs. */
2367 #define ASM_APP_OFF ""
2369 /* How to refer to registers in assembler output.
2370 This sequence is indexed by compiler's hard-register-number (see above). */
2372 #define REGISTER_NAMES \
2373 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2374 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2375 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2376 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2377 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2378 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2379 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2380 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2381 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2382 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2383 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2384 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2385 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2387 /* Define additional names for use in asm clobbers and asm declarations. */
2389 #define ADDITIONAL_REGISTER_NAMES \
2390 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2392 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2393 can run past this up to a continuation point. Once we used 1500, but
2394 a single entry in C++ can run more than 500 bytes, due to the length of
2395 mangled symbol names. dbxout.c should really be fixed to do
2396 continuations when they are actually needed instead of trying to
2398 #define DBX_CONTIN_LENGTH 1000
2400 /* This is how to output a command to make the user-level label named NAME
2401 defined for reference from other files. */
2403 /* Globalizing directive for a label. */
2404 #define GLOBAL_ASM_OP "\t.global "
2406 /* The prefix to add to user-visible assembler symbols. */
2408 #define USER_LABEL_PREFIX "_"
2410 /* This is how to store into the string LABEL
2411 the symbol_ref name of an internal numbered label where
2412 PREFIX is the class of label and NUM is the number within the class.
2413 This is suitable for output with `assemble_name'. */
2415 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2416 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2418 /* This is how we hook in and defer the case-vector until the end of
2420 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2421 sparc_defer_case_vector ((LAB),(VEC), 0)
2423 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2424 sparc_defer_case_vector ((LAB),(VEC), 1)
2426 /* This is how to output an element of a case-vector that is absolute. */
2428 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2431 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2432 if (CASE_VECTOR_MODE == SImode) \
2433 fprintf (FILE, "\t.word\t"); \
2435 fprintf (FILE, "\t.xword\t"); \
2436 assemble_name (FILE, label); \
2437 fputc ('\n', FILE); \
2440 /* This is how to output an element of a case-vector that is relative.
2441 (SPARC uses such vectors only when generating PIC.) */
2443 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2446 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2447 if (CASE_VECTOR_MODE == SImode) \
2448 fprintf (FILE, "\t.word\t"); \
2450 fprintf (FILE, "\t.xword\t"); \
2451 assemble_name (FILE, label); \
2452 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2453 fputc ('-', FILE); \
2454 assemble_name (FILE, label); \
2455 fputc ('\n', FILE); \
2458 /* This is what to output before and after case-vector (both
2459 relative and absolute). If .subsection -1 works, we put case-vectors
2460 at the beginning of the current section. */
2462 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2464 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2465 fprintf(FILE, "\t.subsection\t-1\n")
2467 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2468 fprintf(FILE, "\t.previous\n")
2472 /* This is how to output an assembler line
2473 that says to advance the location counter
2474 to a multiple of 2**LOG bytes. */
2476 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2478 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2480 /* This is how to output an assembler line that says to advance
2481 the location counter to a multiple of 2**LOG bytes using the
2482 "nop" instruction as padding. */
2483 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2485 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2487 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2488 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2490 /* This says how to output an assembler line
2491 to define a global common symbol. */
2493 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2494 ( fputs ("\t.common ", (FILE)), \
2495 assemble_name ((FILE), (NAME)), \
2496 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
2498 /* This says how to output an assembler line to define a local common
2501 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2502 ( fputs ("\t.reserve ", (FILE)), \
2503 assemble_name ((FILE), (NAME)), \
2504 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
2505 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2507 /* A C statement (sans semicolon) to output to the stdio stream
2508 FILE the assembler definition of uninitialized global DECL named
2509 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2510 Try to use asm_output_aligned_bss to implement this macro. */
2512 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2514 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2517 #define IDENT_ASM_OP "\t.ident\t"
2519 /* Output #ident as a .ident. */
2521 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2522 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2524 /* Prettify the assembly. */
2526 extern int sparc_indent_opcode
;
2528 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
2530 if (sparc_indent_opcode) \
2533 sparc_indent_opcode = 0; \
2537 /* Emit a dtp-relative reference to a TLS variable. */
2540 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2541 sparc_output_dwarf_dtprel (FILE, SIZE, X)
2544 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2545 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
2546 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')
2548 /* Print operand X (an rtx) in assembler syntax to file FILE.
2549 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2550 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2552 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2554 /* Print a memory address as an operand to reference that memory location. */
2556 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2557 { register rtx base, index = 0; \
2559 register rtx addr = ADDR; \
2560 if (GET_CODE (addr) == REG) \
2561 fputs (reg_names[REGNO (addr)], FILE); \
2562 else if (GET_CODE (addr) == PLUS) \
2564 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2565 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2566 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2567 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2569 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2570 if (GET_CODE (base) == LO_SUM) \
2572 if (! USE_AS_OFFSETABLE_LO10 \
2574 || TARGET_CM_MEDMID) \
2576 output_operand (XEXP (base, 0), 0); \
2577 fputs ("+%lo(", FILE); \
2578 output_address (XEXP (base, 1)); \
2579 fprintf (FILE, ")+%d", offset); \
2583 fputs (reg_names[REGNO (base)], FILE); \
2585 fprintf (FILE, "%+d", offset); \
2586 else if (GET_CODE (index) == REG) \
2587 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2588 else if (GET_CODE (index) == SYMBOL_REF \
2589 || GET_CODE (index) == CONST) \
2590 fputc ('+', FILE), output_addr_const (FILE, index); \
2594 else if (GET_CODE (addr) == MINUS \
2595 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2597 output_addr_const (FILE, XEXP (addr, 0)); \
2598 fputs ("-(", FILE); \
2599 output_addr_const (FILE, XEXP (addr, 1)); \
2600 fputs ("-.)", FILE); \
2602 else if (GET_CODE (addr) == LO_SUM) \
2604 output_operand (XEXP (addr, 0), 0); \
2605 if (TARGET_CM_MEDMID) \
2606 fputs ("+%l44(", FILE); \
2608 fputs ("+%lo(", FILE); \
2609 output_address (XEXP (addr, 1)); \
2610 fputc (')', FILE); \
2612 else if (flag_pic && GET_CODE (addr) == CONST \
2613 && GET_CODE (XEXP (addr, 0)) == MINUS \
2614 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2615 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2616 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2618 addr = XEXP (addr, 0); \
2619 output_addr_const (FILE, XEXP (addr, 0)); \
2620 /* Group the args of the second CONST in parenthesis. */ \
2621 fputs ("-(", FILE); \
2622 /* Skip past the second CONST--it does nothing for us. */\
2623 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2624 /* Close the parenthesis. */ \
2625 fputc (')', FILE); \
2629 output_addr_const (FILE, addr); \
2634 #define TARGET_TLS 1
2636 #define TARGET_TLS 0
2638 #define TARGET_SUN_TLS TARGET_TLS
2639 #define TARGET_GNU_TLS 0
2641 /* Define the codes that are matched by predicates in sparc.c. */
2643 #define PREDICATE_CODES \
2644 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2645 {"const1_operand", {CONST_INT}}, \
2646 {"fp_zero_operand", {CONST_DOUBLE}}, \
2647 {"fp_register_operand", {SUBREG, REG}}, \
2648 {"intreg_operand", {SUBREG, REG}}, \
2649 {"fcc_reg_operand", {REG}}, \
2650 {"fcc0_reg_operand", {REG}}, \
2651 {"icc_or_fcc_reg_operand", {REG}}, \
2652 {"call_operand", {MEM}}, \
2653 {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
2654 SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
2655 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2656 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2657 {"label_ref_operand", {LABEL_REF}}, \
2658 {"sp64_medium_pic_operand", {CONST}}, \
2659 {"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
2660 {"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
2661 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
2662 {"splittable_symbolic_memory_operand", {MEM}}, \
2663 {"splittable_immediate_memory_operand", {MEM}}, \
2664 {"eq_or_neq", {EQ, NE}}, \
2665 {"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
2666 {"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2667 {"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
2668 {"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
2669 {"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
2670 {"cc_arithop", {AND, IOR, XOR}}, \
2671 {"cc_arithopn", {AND, IOR}}, \
2672 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2673 {"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
2674 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2675 {"arith10_operand", {SUBREG, REG, CONST_INT}}, \
2676 {"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2677 {"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2678 {"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2679 {"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2680 {"small_int", {CONST_INT}}, \
2681 {"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
2682 {"uns_small_int", {CONST_INT}}, \
2683 {"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
2684 {"clobbered_register", {REG}}, \
2685 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
2686 {"compare_operand", {SUBREG, REG, ZERO_EXTRACT}}, \
2687 {"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
2688 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, \
2689 {"tgd_symbolic_operand", {SYMBOL_REF}}, \
2690 {"tld_symbolic_operand", {SYMBOL_REF}}, \
2691 {"tie_symbolic_operand", {SYMBOL_REF}}, \
2692 {"tle_symbolic_operand", {SYMBOL_REF}},
2694 /* The number of Pmode words for the setjmp buffer. */
2695 #define JMP_BUF_SIZE 12
2697 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic)