1 ;; Machine description for SPARC chip for GCC
2 ;; Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 ;; Contributed by Michael Tiemann (tiemann@cygnus.com)
5 ;; 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (UNSPEC_UPDATE_RETURN 1)
31 (UNSPEC_MOVE_PIC_LABEL 5)
37 (UNSPEC_EMB_TEXTUHI 13)
38 (UNSPEC_EMB_TEXTHI 14)
39 (UNSPEC_EMB_TEXTULO 15)
52 ;; The upper 32 fp regs on the v9 can't hold SFmode values. To deal with this
53 ;; a second register class, EXTRA_FP_REGS, exists for the v9 chip. The name
54 ;; is a bit of a misnomer as it covers all 64 fp regs. The corresponding
55 ;; constraint letter is 'e'. To avoid any confusion, 'e' is used instead of
56 ;; 'f' for all DF/TFmode values, including those that are specific to the v8.
58 ;; Attribute for cpu type.
59 ;; These must match the values for enum processor_type in sparc.h.
66 hypersparc,sparclite86x,
71 (const (symbol_ref "sparc_cpu_attr")))
73 ;; Attribute for the instruction set.
74 ;; At present we only need to distinguish v9/!v9, but for clarity we
75 ;; test TARGET_V8 too.
76 (define_attr "isa" "v6,v8,v9,sparclet"
78 (cond [(symbol_ref "TARGET_V9") (const_string "v9")
79 (symbol_ref "TARGET_V8") (const_string "v8")
80 (symbol_ref "TARGET_SPARCLET") (const_string "sparclet")]
81 (const_string "v6"))))
84 (define_attr "arch" "arch32bit,arch64bit"
86 (cond [(symbol_ref "TARGET_ARCH64") (const_string "arch64bit")]
87 (const_string "arch32bit"))))
94 uncond_branch,branch,call,sibcall,call_no_delay_slot,
104 multi,flushw,iflush,trap"
105 (const_string "ialu"))
107 ;; true if branch/call has empty delay slot and will emit a nop in it
108 (define_attr "empty_delay_slot" "false,true"
109 (symbol_ref "empty_delay_slot (insn)"))
111 (define_attr "branch_type" "none,icc,fcc,reg" (const_string "none"))
113 (define_attr "pic" "false,true"
114 (symbol_ref "flag_pic != 0"))
116 (define_attr "current_function_calls_alloca" "false,true"
117 (symbol_ref "current_function_calls_alloca != 0"))
119 (define_attr "flat" "false,true"
120 (symbol_ref "TARGET_FLAT != 0"))
122 ;; Length (in # of insns).
123 (define_attr "length" ""
124 (cond [(eq_attr "type" "uncond_branch,call,sibcall")
125 (if_then_else (eq_attr "empty_delay_slot" "true")
128 (eq_attr "branch_type" "icc")
129 (if_then_else (match_operand 0 "noov_compare64_op" "")
130 (if_then_else (lt (pc) (match_dup 1))
131 (if_then_else (lt (minus (match_dup 1) (pc)) (const_int 260000))
132 (if_then_else (eq_attr "empty_delay_slot" "true")
135 (if_then_else (eq_attr "empty_delay_slot" "true")
138 (if_then_else (lt (minus (pc) (match_dup 1)) (const_int 260000))
139 (if_then_else (eq_attr "empty_delay_slot" "true")
142 (if_then_else (eq_attr "empty_delay_slot" "true")
145 (if_then_else (eq_attr "empty_delay_slot" "true")
148 (eq_attr "branch_type" "fcc")
149 (if_then_else (match_operand 0 "fcc0_reg_operand" "")
150 (if_then_else (eq_attr "empty_delay_slot" "true")
153 (if_then_else (lt (pc) (match_dup 2))
154 (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 260000))
155 (if_then_else (eq_attr "empty_delay_slot" "true")
158 (if_then_else (eq_attr "empty_delay_slot" "true")
161 (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 260000))
162 (if_then_else (eq_attr "empty_delay_slot" "true")
165 (if_then_else (eq_attr "empty_delay_slot" "true")
168 (eq_attr "branch_type" "reg")
169 (if_then_else (lt (pc) (match_dup 2))
170 (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 32000))
171 (if_then_else (eq_attr "empty_delay_slot" "true")
174 (if_then_else (eq_attr "empty_delay_slot" "true")
177 (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 32000))
178 (if_then_else (eq_attr "empty_delay_slot" "true")
181 (if_then_else (eq_attr "empty_delay_slot" "true")
187 (define_attr "fptype" "single,double" (const_string "single"))
189 ;; UltraSPARC-III integer load type.
190 (define_attr "us3load_type" "2cycle,3cycle" (const_string "2cycle"))
192 (define_asm_attributes
193 [(set_attr "length" "2")
194 (set_attr "type" "multi")])
196 ;; Attributes for instruction and branch scheduling
198 (define_attr "in_call_delay" "false,true"
199 (cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
200 (const_string "false")
201 (eq_attr "type" "load,fpload,store,fpstore")
202 (if_then_else (eq_attr "length" "1")
203 (const_string "true")
204 (const_string "false"))]
205 (if_then_else (eq_attr "length" "1")
206 (const_string "true")
207 (const_string "false"))))
209 (define_delay (eq_attr "type" "call")
210 [(eq_attr "in_call_delay" "true") (nil) (nil)])
212 (define_attr "eligible_for_sibcall_delay" "false,true"
213 (symbol_ref "eligible_for_sibcall_delay (insn)"))
215 (define_delay (eq_attr "type" "sibcall")
216 [(eq_attr "eligible_for_sibcall_delay" "true") (nil) (nil)])
218 (define_attr "leaf_function" "false,true"
219 (const (symbol_ref "current_function_uses_only_leaf_regs")))
221 ;; ??? Should implement the notion of predelay slots for floating point
222 ;; branches. This would allow us to remove the nop always inserted before
223 ;; a floating point branch.
225 ;; ??? It is OK for fill_simple_delay_slots to put load/store instructions
226 ;; in a delay slot, but it is not OK for fill_eager_delay_slots to do so.
227 ;; This is because doing so will add several pipeline stalls to the path
228 ;; that the load/store did not come from. Unfortunately, there is no way
229 ;; to prevent fill_eager_delay_slots from using load/store without completely
230 ;; disabling them. For the SPEC benchmark set, this is a serious lose,
231 ;; because it prevents us from moving back the final store of inner loops.
233 (define_attr "in_branch_delay" "false,true"
234 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
235 (eq_attr "length" "1"))
236 (const_string "true")
237 (const_string "false")))
239 (define_attr "in_uncond_branch_delay" "false,true"
240 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
241 (eq_attr "length" "1"))
242 (const_string "true")
243 (const_string "false")))
245 (define_attr "in_annul_branch_delay" "false,true"
246 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
247 (eq_attr "length" "1"))
248 (const_string "true")
249 (const_string "false")))
251 (define_delay (eq_attr "type" "branch")
252 [(eq_attr "in_branch_delay" "true")
253 (nil) (eq_attr "in_annul_branch_delay" "true")])
255 (define_delay (eq_attr "type" "uncond_branch")
256 [(eq_attr "in_uncond_branch_delay" "true")
259 ;; Include SPARC DFA schedulers
261 (include "cypress.md")
262 (include "supersparc.md")
263 (include "hypersparc.md")
264 (include "sparclet.md")
265 (include "ultra1_2.md")
266 (include "ultra3.md")
269 ;; Compare instructions.
270 ;; This controls RTL generation and register allocation.
272 ;; We generate RTL for comparisons and branches by having the cmpxx
273 ;; patterns store away the operands. Then, the scc and bcc patterns
274 ;; emit RTL for both the compare and the branch.
276 ;; We do this because we want to generate different code for an sne and
277 ;; seq insn. In those cases, if the second operand of the compare is not
278 ;; const0_rtx, we want to compute the xor of the two operands and test
281 ;; We start with the DEFINE_EXPANDs, then the DEFINE_INSNs to match
282 ;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc
283 ;; insns that actually require more than one machine instruction.
285 ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
287 (define_expand "cmpsi"
289 (compare:CC (match_operand:SI 0 "register_operand" "")
290 (match_operand:SI 1 "arith_operand" "")))]
293 sparc_compare_op0 = operands[0];
294 sparc_compare_op1 = operands[1];
298 (define_expand "cmpdi"
300 (compare:CCX (match_operand:DI 0 "register_operand" "")
301 (match_operand:DI 1 "arith_double_operand" "")))]
304 sparc_compare_op0 = operands[0];
305 sparc_compare_op1 = operands[1];
309 (define_expand "cmpsf"
310 ;; The 96 here isn't ever used by anyone.
312 (compare:CCFP (match_operand:SF 0 "register_operand" "")
313 (match_operand:SF 1 "register_operand" "")))]
316 sparc_compare_op0 = operands[0];
317 sparc_compare_op1 = operands[1];
321 (define_expand "cmpdf"
322 ;; The 96 here isn't ever used by anyone.
324 (compare:CCFP (match_operand:DF 0 "register_operand" "")
325 (match_operand:DF 1 "register_operand" "")))]
328 sparc_compare_op0 = operands[0];
329 sparc_compare_op1 = operands[1];
333 (define_expand "cmptf"
334 ;; The 96 here isn't ever used by anyone.
336 (compare:CCFP (match_operand:TF 0 "register_operand" "")
337 (match_operand:TF 1 "register_operand" "")))]
340 sparc_compare_op0 = operands[0];
341 sparc_compare_op1 = operands[1];
345 ;; Now the compare DEFINE_INSNs.
347 (define_insn "*cmpsi_insn"
349 (compare:CC (match_operand:SI 0 "register_operand" "r")
350 (match_operand:SI 1 "arith_operand" "rI")))]
353 [(set_attr "type" "compare")])
355 (define_insn "*cmpdi_sp64"
357 (compare:CCX (match_operand:DI 0 "register_operand" "r")
358 (match_operand:DI 1 "arith_double_operand" "rHI")))]
361 [(set_attr "type" "compare")])
363 (define_insn "*cmpsf_fpe"
364 [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
365 (compare:CCFPE (match_operand:SF 1 "register_operand" "f")
366 (match_operand:SF 2 "register_operand" "f")))]
370 return "fcmpes\t%0, %1, %2";
371 return "fcmpes\t%1, %2";
373 [(set_attr "type" "fpcmp")])
375 (define_insn "*cmpdf_fpe"
376 [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
377 (compare:CCFPE (match_operand:DF 1 "register_operand" "e")
378 (match_operand:DF 2 "register_operand" "e")))]
382 return "fcmped\t%0, %1, %2";
383 return "fcmped\t%1, %2";
385 [(set_attr "type" "fpcmp")
386 (set_attr "fptype" "double")])
388 (define_insn "*cmptf_fpe"
389 [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
390 (compare:CCFPE (match_operand:TF 1 "register_operand" "e")
391 (match_operand:TF 2 "register_operand" "e")))]
392 "TARGET_FPU && TARGET_HARD_QUAD"
395 return "fcmpeq\t%0, %1, %2";
396 return "fcmpeq\t%1, %2";
398 [(set_attr "type" "fpcmp")])
400 (define_insn "*cmpsf_fp"
401 [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
402 (compare:CCFP (match_operand:SF 1 "register_operand" "f")
403 (match_operand:SF 2 "register_operand" "f")))]
407 return "fcmps\t%0, %1, %2";
408 return "fcmps\t%1, %2";
410 [(set_attr "type" "fpcmp")])
412 (define_insn "*cmpdf_fp"
413 [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
414 (compare:CCFP (match_operand:DF 1 "register_operand" "e")
415 (match_operand:DF 2 "register_operand" "e")))]
419 return "fcmpd\t%0, %1, %2";
420 return "fcmpd\t%1, %2";
422 [(set_attr "type" "fpcmp")
423 (set_attr "fptype" "double")])
425 (define_insn "*cmptf_fp"
426 [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
427 (compare:CCFP (match_operand:TF 1 "register_operand" "e")
428 (match_operand:TF 2 "register_operand" "e")))]
429 "TARGET_FPU && TARGET_HARD_QUAD"
432 return "fcmpq\t%0, %1, %2";
433 return "fcmpq\t%1, %2";
435 [(set_attr "type" "fpcmp")])
437 ;; Next come the scc insns. For seq, sne, sgeu, and sltu, we can do this
438 ;; without jumps using the addx/subx instructions. For seq/sne on v9 we use
439 ;; the same code as v8 (the addx/subx method has more applications). The
440 ;; exception to this is "reg != 0" which can be done in one instruction on v9
441 ;; (so we do it). For the rest, on v9 we use conditional moves; on v8, we do
444 ;; Seq_special[_xxx] and sne_special[_xxx] clobber the CC reg, because they
445 ;; generate addcc/subcc instructions.
447 (define_expand "seqsi_special"
449 (xor:SI (match_operand:SI 1 "register_operand" "")
450 (match_operand:SI 2 "register_operand" "")))
451 (parallel [(set (match_operand:SI 0 "register_operand" "")
452 (eq:SI (match_dup 3) (const_int 0)))
453 (clobber (reg:CC 100))])]
455 { operands[3] = gen_reg_rtx (SImode); })
457 (define_expand "seqdi_special"
459 (xor:DI (match_operand:DI 1 "register_operand" "")
460 (match_operand:DI 2 "register_operand" "")))
461 (set (match_operand:DI 0 "register_operand" "")
462 (eq:DI (match_dup 3) (const_int 0)))]
464 { operands[3] = gen_reg_rtx (DImode); })
466 (define_expand "snesi_special"
468 (xor:SI (match_operand:SI 1 "register_operand" "")
469 (match_operand:SI 2 "register_operand" "")))
470 (parallel [(set (match_operand:SI 0 "register_operand" "")
471 (ne:SI (match_dup 3) (const_int 0)))
472 (clobber (reg:CC 100))])]
474 { operands[3] = gen_reg_rtx (SImode); })
476 (define_expand "snedi_special"
478 (xor:DI (match_operand:DI 1 "register_operand" "")
479 (match_operand:DI 2 "register_operand" "")))
480 (set (match_operand:DI 0 "register_operand" "")
481 (ne:DI (match_dup 3) (const_int 0)))]
483 { operands[3] = gen_reg_rtx (DImode); })
485 (define_expand "seqdi_special_trunc"
487 (xor:DI (match_operand:DI 1 "register_operand" "")
488 (match_operand:DI 2 "register_operand" "")))
489 (set (match_operand:SI 0 "register_operand" "")
490 (eq:SI (match_dup 3) (const_int 0)))]
492 { operands[3] = gen_reg_rtx (DImode); })
494 (define_expand "snedi_special_trunc"
496 (xor:DI (match_operand:DI 1 "register_operand" "")
497 (match_operand:DI 2 "register_operand" "")))
498 (set (match_operand:SI 0 "register_operand" "")
499 (ne:SI (match_dup 3) (const_int 0)))]
501 { operands[3] = gen_reg_rtx (DImode); })
503 (define_expand "seqsi_special_extend"
505 (xor:SI (match_operand:SI 1 "register_operand" "")
506 (match_operand:SI 2 "register_operand" "")))
507 (parallel [(set (match_operand:DI 0 "register_operand" "")
508 (eq:DI (match_dup 3) (const_int 0)))
509 (clobber (reg:CC 100))])]
511 { operands[3] = gen_reg_rtx (SImode); })
513 (define_expand "snesi_special_extend"
515 (xor:SI (match_operand:SI 1 "register_operand" "")
516 (match_operand:SI 2 "register_operand" "")))
517 (parallel [(set (match_operand:DI 0 "register_operand" "")
518 (ne:DI (match_dup 3) (const_int 0)))
519 (clobber (reg:CC 100))])]
521 { operands[3] = gen_reg_rtx (SImode); })
523 ;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
524 ;; However, the code handles both SImode and DImode.
526 [(set (match_operand:SI 0 "intreg_operand" "")
527 (eq:SI (match_dup 1) (const_int 0)))]
530 if (GET_MODE (sparc_compare_op0) == SImode)
534 if (GET_MODE (operands[0]) == SImode)
535 pat = gen_seqsi_special (operands[0], sparc_compare_op0,
537 else if (! TARGET_ARCH64)
540 pat = gen_seqsi_special_extend (operands[0], sparc_compare_op0,
545 else if (GET_MODE (sparc_compare_op0) == DImode)
551 else if (GET_MODE (operands[0]) == SImode)
552 pat = gen_seqdi_special_trunc (operands[0], sparc_compare_op0,
555 pat = gen_seqdi_special (operands[0], sparc_compare_op0,
560 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
562 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
563 emit_jump_insn (gen_sne (operands[0]));
568 if (gen_v9_scc (EQ, operands))
575 ;; ??? v9: Operand 0 needs a mode, so SImode was chosen.
576 ;; However, the code handles both SImode and DImode.
578 [(set (match_operand:SI 0 "intreg_operand" "")
579 (ne:SI (match_dup 1) (const_int 0)))]
582 if (GET_MODE (sparc_compare_op0) == SImode)
586 if (GET_MODE (operands[0]) == SImode)
587 pat = gen_snesi_special (operands[0], sparc_compare_op0,
589 else if (! TARGET_ARCH64)
592 pat = gen_snesi_special_extend (operands[0], sparc_compare_op0,
597 else if (GET_MODE (sparc_compare_op0) == DImode)
603 else if (GET_MODE (operands[0]) == SImode)
604 pat = gen_snedi_special_trunc (operands[0], sparc_compare_op0,
607 pat = gen_snedi_special (operands[0], sparc_compare_op0,
612 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
614 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
615 emit_jump_insn (gen_sne (operands[0]));
620 if (gen_v9_scc (NE, operands))
628 [(set (match_operand:SI 0 "intreg_operand" "")
629 (gt:SI (match_dup 1) (const_int 0)))]
632 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
634 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
635 emit_jump_insn (gen_sne (operands[0]));
640 if (gen_v9_scc (GT, operands))
648 [(set (match_operand:SI 0 "intreg_operand" "")
649 (lt:SI (match_dup 1) (const_int 0)))]
652 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
654 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
655 emit_jump_insn (gen_sne (operands[0]));
660 if (gen_v9_scc (LT, operands))
668 [(set (match_operand:SI 0 "intreg_operand" "")
669 (ge:SI (match_dup 1) (const_int 0)))]
672 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
674 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
675 emit_jump_insn (gen_sne (operands[0]));
680 if (gen_v9_scc (GE, operands))
688 [(set (match_operand:SI 0 "intreg_operand" "")
689 (le:SI (match_dup 1) (const_int 0)))]
692 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
694 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
695 emit_jump_insn (gen_sne (operands[0]));
700 if (gen_v9_scc (LE, operands))
707 (define_expand "sgtu"
708 [(set (match_operand:SI 0 "intreg_operand" "")
709 (gtu:SI (match_dup 1) (const_int 0)))]
716 /* We can do ltu easily, so if both operands are registers, swap them and
718 if ((GET_CODE (sparc_compare_op0) == REG
719 || GET_CODE (sparc_compare_op0) == SUBREG)
720 && (GET_CODE (sparc_compare_op1) == REG
721 || GET_CODE (sparc_compare_op1) == SUBREG))
723 tem = sparc_compare_op0;
724 sparc_compare_op0 = sparc_compare_op1;
725 sparc_compare_op1 = tem;
726 pat = gen_sltu (operands[0]);
735 if (gen_v9_scc (GTU, operands))
741 (define_expand "sltu"
742 [(set (match_operand:SI 0 "intreg_operand" "")
743 (ltu:SI (match_dup 1) (const_int 0)))]
748 if (gen_v9_scc (LTU, operands))
751 operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
754 (define_expand "sgeu"
755 [(set (match_operand:SI 0 "intreg_operand" "")
756 (geu:SI (match_dup 1) (const_int 0)))]
761 if (gen_v9_scc (GEU, operands))
764 operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
767 (define_expand "sleu"
768 [(set (match_operand:SI 0 "intreg_operand" "")
769 (leu:SI (match_dup 1) (const_int 0)))]
776 /* We can do geu easily, so if both operands are registers, swap them and
778 if ((GET_CODE (sparc_compare_op0) == REG
779 || GET_CODE (sparc_compare_op0) == SUBREG)
780 && (GET_CODE (sparc_compare_op1) == REG
781 || GET_CODE (sparc_compare_op1) == SUBREG))
783 tem = sparc_compare_op0;
784 sparc_compare_op0 = sparc_compare_op1;
785 sparc_compare_op1 = tem;
786 pat = gen_sgeu (operands[0]);
795 if (gen_v9_scc (LEU, operands))
801 ;; Now the DEFINE_INSNs for the scc cases.
803 ;; The SEQ and SNE patterns are special because they can be done
804 ;; without any branching and do not involve a COMPARE. We want
805 ;; them to always use the splitz below so the results can be
808 (define_insn_and_split "*snesi_zero"
809 [(set (match_operand:SI 0 "register_operand" "=r")
810 (ne:SI (match_operand:SI 1 "register_operand" "r")
812 (clobber (reg:CC 100))]
816 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
818 (set (match_dup 0) (ltu:SI (reg:CC 100) (const_int 0)))]
820 [(set_attr "length" "2")])
822 (define_insn_and_split "*neg_snesi_zero"
823 [(set (match_operand:SI 0 "register_operand" "=r")
824 (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
826 (clobber (reg:CC 100))]
830 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
832 (set (match_dup 0) (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
834 [(set_attr "length" "2")])
836 (define_insn_and_split "*snesi_zero_extend"
837 [(set (match_operand:DI 0 "register_operand" "=r")
838 (ne:DI (match_operand:SI 1 "register_operand" "r")
840 (clobber (reg:CC 100))]
844 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0)
847 (set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0)
849 (ltu:SI (reg:CC_NOOV 100)
852 [(set_attr "length" "2")])
854 (define_insn_and_split "*snedi_zero"
855 [(set (match_operand:DI 0 "register_operand" "=&r")
856 (ne:DI (match_operand:DI 1 "register_operand" "r")
860 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
861 [(set (match_dup 0) (const_int 0))
862 (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
867 [(set_attr "length" "2")])
869 (define_insn_and_split "*neg_snedi_zero"
870 [(set (match_operand:DI 0 "register_operand" "=&r")
871 (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r")
875 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
876 [(set (match_dup 0) (const_int 0))
877 (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1)
882 [(set_attr "length" "2")])
884 (define_insn_and_split "*snedi_zero_trunc"
885 [(set (match_operand:SI 0 "register_operand" "=&r")
886 (ne:SI (match_operand:DI 1 "register_operand" "r")
890 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
891 [(set (match_dup 0) (const_int 0))
892 (set (match_dup 0) (if_then_else:SI (ne:DI (match_dup 1)
897 [(set_attr "length" "2")])
899 (define_insn_and_split "*seqsi_zero"
900 [(set (match_operand:SI 0 "register_operand" "=r")
901 (eq:SI (match_operand:SI 1 "register_operand" "r")
903 (clobber (reg:CC 100))]
907 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
909 (set (match_dup 0) (geu:SI (reg:CC 100) (const_int 0)))]
911 [(set_attr "length" "2")])
913 (define_insn_and_split "*neg_seqsi_zero"
914 [(set (match_operand:SI 0 "register_operand" "=r")
915 (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
917 (clobber (reg:CC 100))]
921 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
923 (set (match_dup 0) (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
925 [(set_attr "length" "2")])
927 (define_insn_and_split "*seqsi_zero_extend"
928 [(set (match_operand:DI 0 "register_operand" "=r")
929 (eq:DI (match_operand:SI 1 "register_operand" "r")
931 (clobber (reg:CC 100))]
935 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0)
938 (set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0)
940 (ltu:SI (reg:CC_NOOV 100)
943 [(set_attr "length" "2")])
945 (define_insn_and_split "*seqdi_zero"
946 [(set (match_operand:DI 0 "register_operand" "=&r")
947 (eq:DI (match_operand:DI 1 "register_operand" "r")
951 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
952 [(set (match_dup 0) (const_int 0))
953 (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
958 [(set_attr "length" "2")])
960 (define_insn_and_split "*neg_seqdi_zero"
961 [(set (match_operand:DI 0 "register_operand" "=&r")
962 (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r")
966 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
967 [(set (match_dup 0) (const_int 0))
968 (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1)
973 [(set_attr "length" "2")])
975 (define_insn_and_split "*seqdi_zero_trunc"
976 [(set (match_operand:SI 0 "register_operand" "=&r")
977 (eq:SI (match_operand:DI 1 "register_operand" "r")
981 "&& ! reg_overlap_mentioned_p (operands[1], operands[0])"
982 [(set (match_dup 0) (const_int 0))
983 (set (match_dup 0) (if_then_else:SI (eq:DI (match_dup 1)
988 [(set_attr "length" "2")])
990 ;; We can also do (x + (i == 0)) and related, so put them in.
991 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
994 (define_insn_and_split "*x_plus_i_ne_0"
995 [(set (match_operand:SI 0 "register_operand" "=r")
996 (plus:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
998 (match_operand:SI 2 "register_operand" "r")))
999 (clobber (reg:CC 100))]
1003 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1005 (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1008 [(set_attr "length" "2")])
1010 (define_insn_and_split "*x_minus_i_ne_0"
1011 [(set (match_operand:SI 0 "register_operand" "=r")
1012 (minus:SI (match_operand:SI 2 "register_operand" "r")
1013 (ne:SI (match_operand:SI 1 "register_operand" "r")
1015 (clobber (reg:CC 100))]
1019 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1021 (set (match_dup 0) (minus:SI (match_dup 2)
1022 (ltu:SI (reg:CC 100) (const_int 0))))]
1024 [(set_attr "length" "2")])
1026 (define_insn_and_split "*x_plus_i_eq_0"
1027 [(set (match_operand:SI 0 "register_operand" "=r")
1028 (plus:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
1030 (match_operand:SI 2 "register_operand" "r")))
1031 (clobber (reg:CC 100))]
1035 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1037 (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0))
1040 [(set_attr "length" "2")])
1042 (define_insn_and_split "*x_minus_i_eq_0"
1043 [(set (match_operand:SI 0 "register_operand" "=r")
1044 (minus:SI (match_operand:SI 2 "register_operand" "r")
1045 (eq:SI (match_operand:SI 1 "register_operand" "r")
1047 (clobber (reg:CC 100))]
1051 [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
1053 (set (match_dup 0) (minus:SI (match_dup 2)
1054 (geu:SI (reg:CC 100) (const_int 0))))]
1056 [(set_attr "length" "2")])
1058 ;; We can also do GEU and LTU directly, but these operate after a compare.
1059 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
1062 (define_insn "*sltu_insn"
1063 [(set (match_operand:SI 0 "register_operand" "=r")
1064 (ltu:SI (reg:CC 100) (const_int 0)))]
1067 [(set_attr "type" "ialuX")])
1069 (define_insn "*neg_sltu_insn"
1070 [(set (match_operand:SI 0 "register_operand" "=r")
1071 (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
1074 [(set_attr "type" "ialuX")])
1076 ;; ??? Combine should canonicalize these next two to the same pattern.
1077 (define_insn "*neg_sltu_minus_x"
1078 [(set (match_operand:SI 0 "register_operand" "=r")
1079 (minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0)))
1080 (match_operand:SI 1 "arith_operand" "rI")))]
1082 "subx\t%%g0, %1, %0"
1083 [(set_attr "type" "ialuX")])
1085 (define_insn "*neg_sltu_plus_x"
1086 [(set (match_operand:SI 0 "register_operand" "=r")
1087 (neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1088 (match_operand:SI 1 "arith_operand" "rI"))))]
1090 "subx\t%%g0, %1, %0"
1091 [(set_attr "type" "ialuX")])
1093 (define_insn "*sgeu_insn"
1094 [(set (match_operand:SI 0 "register_operand" "=r")
1095 (geu:SI (reg:CC 100) (const_int 0)))]
1097 "subx\t%%g0, -1, %0"
1098 [(set_attr "type" "ialuX")])
1100 (define_insn "*neg_sgeu_insn"
1101 [(set (match_operand:SI 0 "register_operand" "=r")
1102 (neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
1104 "addx\t%%g0, -1, %0"
1105 [(set_attr "type" "ialuX")])
1107 ;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in.
1108 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
1111 (define_insn "*sltu_plus_x"
1112 [(set (match_operand:SI 0 "register_operand" "=r")
1113 (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1114 (match_operand:SI 1 "arith_operand" "rI")))]
1116 "addx\t%%g0, %1, %0"
1117 [(set_attr "type" "ialuX")])
1119 (define_insn "*sltu_plus_x_plus_y"
1120 [(set (match_operand:SI 0 "register_operand" "=r")
1121 (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1122 (plus:SI (match_operand:SI 1 "arith_operand" "%r")
1123 (match_operand:SI 2 "arith_operand" "rI"))))]
1126 [(set_attr "type" "ialuX")])
1128 (define_insn "*x_minus_sltu"
1129 [(set (match_operand:SI 0 "register_operand" "=r")
1130 (minus:SI (match_operand:SI 1 "register_operand" "r")
1131 (ltu:SI (reg:CC 100) (const_int 0))))]
1134 [(set_attr "type" "ialuX")])
1136 ;; ??? Combine should canonicalize these next two to the same pattern.
1137 (define_insn "*x_minus_y_minus_sltu"
1138 [(set (match_operand:SI 0 "register_operand" "=r")
1139 (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
1140 (match_operand:SI 2 "arith_operand" "rI"))
1141 (ltu:SI (reg:CC 100) (const_int 0))))]
1144 [(set_attr "type" "ialuX")])
1146 (define_insn "*x_minus_sltu_plus_y"
1147 [(set (match_operand:SI 0 "register_operand" "=r")
1148 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
1149 (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
1150 (match_operand:SI 2 "arith_operand" "rI"))))]
1153 [(set_attr "type" "ialuX")])
1155 (define_insn "*sgeu_plus_x"
1156 [(set (match_operand:SI 0 "register_operand" "=r")
1157 (plus:SI (geu:SI (reg:CC 100) (const_int 0))
1158 (match_operand:SI 1 "register_operand" "r")))]
1161 [(set_attr "type" "ialuX")])
1163 (define_insn "*x_minus_sgeu"
1164 [(set (match_operand:SI 0 "register_operand" "=r")
1165 (minus:SI (match_operand:SI 1 "register_operand" "r")
1166 (geu:SI (reg:CC 100) (const_int 0))))]
1169 [(set_attr "type" "ialuX")])
1172 [(set (match_operand:SI 0 "register_operand" "")
1173 (match_operator:SI 2 "noov_compare_op"
1174 [(match_operand 1 "icc_or_fcc_reg_operand" "")
1176 ;; 32 bit LTU/GEU are better implemented using addx/subx
1177 "TARGET_V9 && REGNO (operands[1]) == SPARC_ICC_REG
1178 && (GET_MODE (operands[1]) == CCXmode
1179 || (GET_CODE (operands[2]) != LTU && GET_CODE (operands[2]) != GEU))"
1180 [(set (match_dup 0) (const_int 0))
1182 (if_then_else:SI (match_op_dup:SI 2 [(match_dup 1) (const_int 0)])
1188 ;; These control RTL generation for conditional jump insns
1190 ;; The quad-word fp compare library routines all return nonzero to indicate
1191 ;; true, which is different from the equivalent libgcc routines, so we must
1192 ;; handle them specially here.
1194 (define_expand "beq"
1196 (if_then_else (eq (match_dup 1) (const_int 0))
1197 (label_ref (match_operand 0 "" ""))
1201 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1202 && GET_CODE (sparc_compare_op0) == REG
1203 && GET_MODE (sparc_compare_op0) == DImode)
1205 emit_v9_brxx_insn (EQ, sparc_compare_op0, operands[0]);
1208 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1210 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, EQ);
1211 emit_jump_insn (gen_bne (operands[0]));
1214 operands[1] = gen_compare_reg (EQ, sparc_compare_op0, sparc_compare_op1);
1217 (define_expand "bne"
1219 (if_then_else (ne (match_dup 1) (const_int 0))
1220 (label_ref (match_operand 0 "" ""))
1224 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1225 && GET_CODE (sparc_compare_op0) == REG
1226 && GET_MODE (sparc_compare_op0) == DImode)
1228 emit_v9_brxx_insn (NE, sparc_compare_op0, operands[0]);
1231 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1233 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, NE);
1234 emit_jump_insn (gen_bne (operands[0]));
1237 operands[1] = gen_compare_reg (NE, sparc_compare_op0, sparc_compare_op1);
1240 (define_expand "bgt"
1242 (if_then_else (gt (match_dup 1) (const_int 0))
1243 (label_ref (match_operand 0 "" ""))
1247 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1248 && GET_CODE (sparc_compare_op0) == REG
1249 && GET_MODE (sparc_compare_op0) == DImode)
1251 emit_v9_brxx_insn (GT, sparc_compare_op0, operands[0]);
1254 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1256 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GT);
1257 emit_jump_insn (gen_bne (operands[0]));
1260 operands[1] = gen_compare_reg (GT, sparc_compare_op0, sparc_compare_op1);
1263 (define_expand "bgtu"
1265 (if_then_else (gtu (match_dup 1) (const_int 0))
1266 (label_ref (match_operand 0 "" ""))
1270 operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1);
1273 (define_expand "blt"
1275 (if_then_else (lt (match_dup 1) (const_int 0))
1276 (label_ref (match_operand 0 "" ""))
1280 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1281 && GET_CODE (sparc_compare_op0) == REG
1282 && GET_MODE (sparc_compare_op0) == DImode)
1284 emit_v9_brxx_insn (LT, sparc_compare_op0, operands[0]);
1287 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1289 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LT);
1290 emit_jump_insn (gen_bne (operands[0]));
1293 operands[1] = gen_compare_reg (LT, sparc_compare_op0, sparc_compare_op1);
1296 (define_expand "bltu"
1298 (if_then_else (ltu (match_dup 1) (const_int 0))
1299 (label_ref (match_operand 0 "" ""))
1303 operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1);
1306 (define_expand "bge"
1308 (if_then_else (ge (match_dup 1) (const_int 0))
1309 (label_ref (match_operand 0 "" ""))
1313 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1314 && GET_CODE (sparc_compare_op0) == REG
1315 && GET_MODE (sparc_compare_op0) == DImode)
1317 emit_v9_brxx_insn (GE, sparc_compare_op0, operands[0]);
1320 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1322 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, GE);
1323 emit_jump_insn (gen_bne (operands[0]));
1326 operands[1] = gen_compare_reg (GE, sparc_compare_op0, sparc_compare_op1);
1329 (define_expand "bgeu"
1331 (if_then_else (geu (match_dup 1) (const_int 0))
1332 (label_ref (match_operand 0 "" ""))
1336 operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1);
1339 (define_expand "ble"
1341 (if_then_else (le (match_dup 1) (const_int 0))
1342 (label_ref (match_operand 0 "" ""))
1346 if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx
1347 && GET_CODE (sparc_compare_op0) == REG
1348 && GET_MODE (sparc_compare_op0) == DImode)
1350 emit_v9_brxx_insn (LE, sparc_compare_op0, operands[0]);
1353 else if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1355 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LE);
1356 emit_jump_insn (gen_bne (operands[0]));
1359 operands[1] = gen_compare_reg (LE, sparc_compare_op0, sparc_compare_op1);
1362 (define_expand "bleu"
1364 (if_then_else (leu (match_dup 1) (const_int 0))
1365 (label_ref (match_operand 0 "" ""))
1369 operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1);
1372 (define_expand "bunordered"
1374 (if_then_else (unordered (match_dup 1) (const_int 0))
1375 (label_ref (match_operand 0 "" ""))
1379 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1381 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1,
1383 emit_jump_insn (gen_beq (operands[0]));
1386 operands[1] = gen_compare_reg (UNORDERED, sparc_compare_op0,
1390 (define_expand "bordered"
1392 (if_then_else (ordered (match_dup 1) (const_int 0))
1393 (label_ref (match_operand 0 "" ""))
1397 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1399 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, ORDERED);
1400 emit_jump_insn (gen_bne (operands[0]));
1403 operands[1] = gen_compare_reg (ORDERED, sparc_compare_op0,
1407 (define_expand "bungt"
1409 (if_then_else (ungt (match_dup 1) (const_int 0))
1410 (label_ref (match_operand 0 "" ""))
1414 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1416 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNGT);
1417 emit_jump_insn (gen_bgt (operands[0]));
1420 operands[1] = gen_compare_reg (UNGT, sparc_compare_op0, sparc_compare_op1);
1423 (define_expand "bunlt"
1425 (if_then_else (unlt (match_dup 1) (const_int 0))
1426 (label_ref (match_operand 0 "" ""))
1430 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1432 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNLT);
1433 emit_jump_insn (gen_bne (operands[0]));
1436 operands[1] = gen_compare_reg (UNLT, sparc_compare_op0, sparc_compare_op1);
1439 (define_expand "buneq"
1441 (if_then_else (uneq (match_dup 1) (const_int 0))
1442 (label_ref (match_operand 0 "" ""))
1446 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1448 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNEQ);
1449 emit_jump_insn (gen_beq (operands[0]));
1452 operands[1] = gen_compare_reg (UNEQ, sparc_compare_op0, sparc_compare_op1);
1455 (define_expand "bunge"
1457 (if_then_else (unge (match_dup 1) (const_int 0))
1458 (label_ref (match_operand 0 "" ""))
1462 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1464 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNGE);
1465 emit_jump_insn (gen_bne (operands[0]));
1468 operands[1] = gen_compare_reg (UNGE, sparc_compare_op0, sparc_compare_op1);
1471 (define_expand "bunle"
1473 (if_then_else (unle (match_dup 1) (const_int 0))
1474 (label_ref (match_operand 0 "" ""))
1478 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1480 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, UNLE);
1481 emit_jump_insn (gen_bne (operands[0]));
1484 operands[1] = gen_compare_reg (UNLE, sparc_compare_op0, sparc_compare_op1);
1487 (define_expand "bltgt"
1489 (if_then_else (ltgt (match_dup 1) (const_int 0))
1490 (label_ref (match_operand 0 "" ""))
1494 if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
1496 sparc_emit_float_lib_cmp (sparc_compare_op0, sparc_compare_op1, LTGT);
1497 emit_jump_insn (gen_bne (operands[0]));
1500 operands[1] = gen_compare_reg (LTGT, sparc_compare_op0, sparc_compare_op1);
1503 ;; Now match both normal and inverted jump.
1505 ;; XXX fpcmp nop braindamage
1506 (define_insn "*normal_branch"
1508 (if_then_else (match_operator 0 "noov_compare_op"
1509 [(reg 100) (const_int 0)])
1510 (label_ref (match_operand 1 "" ""))
1514 return output_cbranch (operands[0], operands[1], 1, 0,
1515 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1516 ! final_sequence, insn);
1518 [(set_attr "type" "branch")
1519 (set_attr "branch_type" "icc")])
1521 ;; XXX fpcmp nop braindamage
1522 (define_insn "*inverted_branch"
1524 (if_then_else (match_operator 0 "noov_compare_op"
1525 [(reg 100) (const_int 0)])
1527 (label_ref (match_operand 1 "" ""))))]
1530 return output_cbranch (operands[0], operands[1], 1, 1,
1531 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1532 ! final_sequence, insn);
1534 [(set_attr "type" "branch")
1535 (set_attr "branch_type" "icc")])
1537 ;; XXX fpcmp nop braindamage
1538 (define_insn "*normal_fp_branch"
1540 (if_then_else (match_operator 1 "comparison_operator"
1541 [(match_operand:CCFP 0 "fcc_reg_operand" "c")
1543 (label_ref (match_operand 2 "" ""))
1547 return output_cbranch (operands[1], operands[2], 2, 0,
1548 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1549 ! final_sequence, insn);
1551 [(set_attr "type" "branch")
1552 (set_attr "branch_type" "fcc")])
1554 ;; XXX fpcmp nop braindamage
1555 (define_insn "*inverted_fp_branch"
1557 (if_then_else (match_operator 1 "comparison_operator"
1558 [(match_operand:CCFP 0 "fcc_reg_operand" "c")
1561 (label_ref (match_operand 2 "" ""))))]
1564 return output_cbranch (operands[1], operands[2], 2, 1,
1565 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1566 ! final_sequence, insn);
1568 [(set_attr "type" "branch")
1569 (set_attr "branch_type" "fcc")])
1571 ;; XXX fpcmp nop braindamage
1572 (define_insn "*normal_fpe_branch"
1574 (if_then_else (match_operator 1 "comparison_operator"
1575 [(match_operand:CCFPE 0 "fcc_reg_operand" "c")
1577 (label_ref (match_operand 2 "" ""))
1581 return output_cbranch (operands[1], operands[2], 2, 0,
1582 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1583 ! final_sequence, insn);
1585 [(set_attr "type" "branch")
1586 (set_attr "branch_type" "fcc")])
1588 ;; XXX fpcmp nop braindamage
1589 (define_insn "*inverted_fpe_branch"
1591 (if_then_else (match_operator 1 "comparison_operator"
1592 [(match_operand:CCFPE 0 "fcc_reg_operand" "c")
1595 (label_ref (match_operand 2 "" ""))))]
1598 return output_cbranch (operands[1], operands[2], 2, 1,
1599 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1600 ! final_sequence, insn);
1602 [(set_attr "type" "branch")
1603 (set_attr "branch_type" "fcc")])
1605 ;; SPARC V9-specific jump insns. None of these are guaranteed to be
1606 ;; in the architecture.
1608 ;; There are no 32 bit brreg insns.
1611 (define_insn "*normal_int_branch_sp64"
1613 (if_then_else (match_operator 0 "v9_regcmp_op"
1614 [(match_operand:DI 1 "register_operand" "r")
1616 (label_ref (match_operand 2 "" ""))
1620 return output_v9branch (operands[0], operands[2], 1, 2, 0,
1621 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1622 ! final_sequence, insn);
1624 [(set_attr "type" "branch")
1625 (set_attr "branch_type" "reg")])
1628 (define_insn "*inverted_int_branch_sp64"
1630 (if_then_else (match_operator 0 "v9_regcmp_op"
1631 [(match_operand:DI 1 "register_operand" "r")
1634 (label_ref (match_operand 2 "" ""))))]
1637 return output_v9branch (operands[0], operands[2], 1, 2, 1,
1638 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1639 ! final_sequence, insn);
1641 [(set_attr "type" "branch")
1642 (set_attr "branch_type" "reg")])
1644 ;; Load program counter insns.
1646 (define_insn "get_pc"
1647 [(clobber (reg:SI 15))
1648 (set (match_operand 0 "register_operand" "=r")
1649 (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] UNSPEC_GET_PC))]
1650 "flag_pic && REGNO (operands[0]) == 23"
1651 "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\tadd\t%0, %%lo(%a1+4), %0"
1652 [(set_attr "type" "multi")
1653 (set_attr "length" "3")])
1656 ;; Move instructions
1658 (define_expand "movqi"
1659 [(set (match_operand:QI 0 "general_operand" "")
1660 (match_operand:QI 1 "general_operand" ""))]
1663 /* Working with CONST_INTs is easier, so convert
1664 a double if needed. */
1665 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1667 operands[1] = GEN_INT (trunc_int_for_mode
1668 (CONST_DOUBLE_LOW (operands[1]), QImode));
1671 /* Handle sets of MEM first. */
1672 if (GET_CODE (operands[0]) == MEM)
1674 if (reg_or_0_operand (operands[1], QImode))
1677 if (! reload_in_progress)
1679 operands[0] = validize_mem (operands[0]);
1680 operands[1] = force_reg (QImode, operands[1]);
1684 /* Fixup PIC cases. */
1687 if (CONSTANT_P (operands[1])
1688 && pic_address_needs_scratch (operands[1]))
1689 operands[1] = legitimize_pic_address (operands[1], QImode, 0);
1691 if (symbolic_operand (operands[1], QImode))
1693 operands[1] = legitimize_pic_address (operands[1],
1695 (reload_in_progress ?
1702 /* All QI constants require only one insn, so proceed. */
1708 (define_insn "*movqi_insn"
1709 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m")
1710 (match_operand:QI 1 "input_operand" "rI,m,rJ"))]
1711 "(register_operand (operands[0], QImode)
1712 || reg_or_0_operand (operands[1], QImode))"
1717 [(set_attr "type" "*,load,store")
1718 (set_attr "us3load_type" "*,3cycle,*")])
1720 (define_expand "movhi"
1721 [(set (match_operand:HI 0 "general_operand" "")
1722 (match_operand:HI 1 "general_operand" ""))]
1725 /* Working with CONST_INTs is easier, so convert
1726 a double if needed. */
1727 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1728 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
1730 /* Handle sets of MEM first. */
1731 if (GET_CODE (operands[0]) == MEM)
1733 if (reg_or_0_operand (operands[1], HImode))
1736 if (! reload_in_progress)
1738 operands[0] = validize_mem (operands[0]);
1739 operands[1] = force_reg (HImode, operands[1]);
1743 /* Fixup PIC cases. */
1746 if (CONSTANT_P (operands[1])
1747 && pic_address_needs_scratch (operands[1]))
1748 operands[1] = legitimize_pic_address (operands[1], HImode, 0);
1750 if (symbolic_operand (operands[1], HImode))
1752 operands[1] = legitimize_pic_address (operands[1],
1754 (reload_in_progress ?
1761 /* This makes sure we will not get rematched due to splittage. */
1762 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], HImode))
1764 else if (CONSTANT_P (operands[1])
1765 && GET_CODE (operands[1]) != HIGH
1766 && GET_CODE (operands[1]) != LO_SUM)
1768 sparc_emit_set_const32 (operands[0], operands[1]);
1775 (define_insn "*movhi_const64_special"
1776 [(set (match_operand:HI 0 "register_operand" "=r")
1777 (match_operand:HI 1 "const64_high_operand" ""))]
1779 "sethi\t%%hi(%a1), %0")
1781 (define_insn "*movhi_insn"
1782 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1783 (match_operand:HI 1 "input_operand" "rI,K,m,rJ"))]
1784 "(register_operand (operands[0], HImode)
1785 || reg_or_0_operand (operands[1], HImode))"
1788 sethi\t%%hi(%a1), %0
1791 [(set_attr "type" "*,*,load,store")
1792 (set_attr "us3load_type" "*,*,3cycle,*")])
1794 ;; We always work with constants here.
1795 (define_insn "*movhi_lo_sum"
1796 [(set (match_operand:HI 0 "register_operand" "=r")
1797 (ior:HI (match_operand:HI 1 "arith_operand" "%r")
1798 (match_operand:HI 2 "arith_operand" "I")))]
1802 (define_expand "movsi"
1803 [(set (match_operand:SI 0 "general_operand" "")
1804 (match_operand:SI 1 "general_operand" ""))]
1807 /* Working with CONST_INTs is easier, so convert
1808 a double if needed. */
1809 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1810 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
1812 /* Handle sets of MEM first. */
1813 if (GET_CODE (operands[0]) == MEM)
1815 if (reg_or_0_operand (operands[1], SImode))
1818 if (! reload_in_progress)
1820 operands[0] = validize_mem (operands[0]);
1821 operands[1] = force_reg (SImode, operands[1]);
1825 /* Fixup PIC cases. */
1828 if (CONSTANT_P (operands[1])
1829 && pic_address_needs_scratch (operands[1]))
1830 operands[1] = legitimize_pic_address (operands[1], SImode, 0);
1832 if (GET_CODE (operands[1]) == LABEL_REF)
1835 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1]));
1839 if (symbolic_operand (operands[1], SImode))
1841 operands[1] = legitimize_pic_address (operands[1],
1843 (reload_in_progress ?
1850 /* If we are trying to toss an integer constant into the
1851 FPU registers, force it into memory. */
1852 if (GET_CODE (operands[0]) == REG
1853 && REGNO (operands[0]) >= SPARC_FIRST_FP_REG
1854 && REGNO (operands[0]) <= SPARC_LAST_V9_FP_REG
1855 && CONSTANT_P (operands[1]))
1856 operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
1859 /* This makes sure we will not get rematched due to splittage. */
1860 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
1862 else if (CONSTANT_P (operands[1])
1863 && GET_CODE (operands[1]) != HIGH
1864 && GET_CODE (operands[1]) != LO_SUM)
1866 sparc_emit_set_const32 (operands[0], operands[1]);
1873 ;; This is needed to show CSE exactly which bits are set
1874 ;; in a 64-bit register by sethi instructions.
1875 (define_insn "*movsi_const64_special"
1876 [(set (match_operand:SI 0 "register_operand" "=r")
1877 (match_operand:SI 1 "const64_high_operand" ""))]
1879 "sethi\t%%hi(%a1), %0")
1881 (define_insn "*movsi_insn"
1882 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d")
1883 (match_operand:SI 1 "input_operand" "rI,!f,K,J,m,!m,rJ,!f,J"))]
1884 "(register_operand (operands[0], SImode)
1885 || reg_or_0_operand (operands[1], SImode))"
1889 sethi\t%%hi(%a1), %0
1896 [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fpmove")])
1898 (define_insn "*movsi_lo_sum"
1899 [(set (match_operand:SI 0 "register_operand" "=r")
1900 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1901 (match_operand:SI 2 "immediate_operand" "in")))]
1903 "or\t%1, %%lo(%a2), %0")
1905 (define_insn "*movsi_high"
1906 [(set (match_operand:SI 0 "register_operand" "=r")
1907 (high:SI (match_operand:SI 1 "immediate_operand" "in")))]
1909 "sethi\t%%hi(%a1), %0")
1911 ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
1912 ;; so that CSE won't optimize the address computation away.
1913 (define_insn "movsi_lo_sum_pic"
1914 [(set (match_operand:SI 0 "register_operand" "=r")
1915 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1916 (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))]
1918 "or\t%1, %%lo(%a2), %0")
1920 (define_insn "movsi_high_pic"
1921 [(set (match_operand:SI 0 "register_operand" "=r")
1922 (high:SI (unspec:SI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))]
1923 "flag_pic && check_pic (1)"
1924 "sethi\t%%hi(%a1), %0")
1926 (define_expand "movsi_pic_label_ref"
1927 [(set (match_dup 3) (high:SI
1928 (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
1929 (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
1930 (set (match_dup 4) (lo_sum:SI (match_dup 3)
1931 (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
1932 (set (match_operand:SI 0 "register_operand" "=r")
1933 (minus:SI (match_dup 5) (match_dup 4)))]
1936 current_function_uses_pic_offset_table = 1;
1937 operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1940 operands[3] = operands[0];
1941 operands[4] = operands[0];
1945 operands[3] = gen_reg_rtx (SImode);
1946 operands[4] = gen_reg_rtx (SImode);
1948 operands[5] = pic_offset_table_rtx;
1951 (define_insn "*movsi_high_pic_label_ref"
1952 [(set (match_operand:SI 0 "register_operand" "=r")
1954 (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
1955 (match_operand:SI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
1957 "sethi\t%%hi(%a2-(%a1-.)), %0")
1959 (define_insn "*movsi_lo_sum_pic_label_ref"
1960 [(set (match_operand:SI 0 "register_operand" "=r")
1961 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1962 (unspec:SI [(match_operand:SI 2 "label_ref_operand" "")
1963 (match_operand:SI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
1965 "or\t%1, %%lo(%a3-(%a2-.)), %0")
1967 (define_expand "movdi"
1968 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
1969 (match_operand:DI 1 "general_operand" ""))]
1972 /* Where possible, convert CONST_DOUBLE into a CONST_INT. */
1973 if (GET_CODE (operands[1]) == CONST_DOUBLE
1974 #if HOST_BITS_PER_WIDE_INT == 32
1975 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
1976 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
1977 || (CONST_DOUBLE_HIGH (operands[1]) == (HOST_WIDE_INT) 0xffffffff
1978 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))
1981 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
1983 /* Handle MEM cases first. */
1984 if (GET_CODE (operands[0]) == MEM)
1986 /* If it's a REG, we can always do it.
1987 The const zero case is more complex, on v9
1988 we can always perform it. */
1989 if (register_operand (operands[1], DImode)
1991 && (operands[1] == const0_rtx)))
1994 if (! reload_in_progress)
1996 operands[0] = validize_mem (operands[0]);
1997 operands[1] = force_reg (DImode, operands[1]);
2003 if (CONSTANT_P (operands[1])
2004 && pic_address_needs_scratch (operands[1]))
2005 operands[1] = legitimize_pic_address (operands[1], DImode, 0);
2007 if (GET_CODE (operands[1]) == LABEL_REF)
2009 if (! TARGET_ARCH64)
2011 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1]));
2015 if (symbolic_operand (operands[1], DImode))
2017 operands[1] = legitimize_pic_address (operands[1],
2019 (reload_in_progress ?
2026 /* If we are trying to toss an integer constant into the
2027 FPU registers, force it into memory. */
2028 if (GET_CODE (operands[0]) == REG
2029 && REGNO (operands[0]) >= SPARC_FIRST_FP_REG
2030 && REGNO (operands[0]) <= SPARC_LAST_V9_FP_REG
2031 && CONSTANT_P (operands[1]))
2032 operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
2035 /* This makes sure we will not get rematched due to splittage. */
2036 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
2038 else if (TARGET_ARCH64
2039 && CONSTANT_P (operands[1])
2040 && GET_CODE (operands[1]) != HIGH
2041 && GET_CODE (operands[1]) != LO_SUM)
2043 sparc_emit_set_const64 (operands[0], operands[1]);
2051 ;; Be careful, fmovd does not exist when !v9.
2052 ;; We match MEM moves directly when we have correct even
2053 ;; numbered registers, but fall into splits otherwise.
2054 ;; The constraint ordering here is really important to
2055 ;; avoid insane problems in reload, especially for patterns
2058 ;; (set (mem:DI (plus:SI (reg:SI 30 %fp)
2059 ;; (const_int -5016)))
2063 (define_insn "*movdi_insn_sp32_v9"
2064 [(set (match_operand:DI 0 "nonimmediate_operand"
2065 "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W")
2066 (match_operand:DI 1 "input_operand"
2067 " J,J,U,T,r,o,i,r, f, T, o, f, e, W, e"))]
2068 "! TARGET_ARCH64 && TARGET_V9
2069 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2086 [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore")
2087 (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*")
2088 (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
2090 (define_insn "*movdi_insn_sp32"
2091 [(set (match_operand:DI 0 "nonimmediate_operand"
2092 "=o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
2093 (match_operand:DI 1 "input_operand"
2094 " J,U,T,r,o,i,r, f, T, o, f, f"))]
2096 && (register_operand (operands[0], DImode)
2097 || register_operand (operands[1], DImode))"
2111 [(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
2112 (set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
2114 ;; The following are generated by sparc_emit_set_const64
2115 (define_insn "*movdi_sp64_dbl"
2116 [(set (match_operand:DI 0 "register_operand" "=r")
2117 (match_operand:DI 1 "const64_operand" ""))]
2119 && HOST_BITS_PER_WIDE_INT != 64)"
2122 ;; This is needed to show CSE exactly which bits are set
2123 ;; in a 64-bit register by sethi instructions.
2124 (define_insn "*movdi_const64_special"
2125 [(set (match_operand:DI 0 "register_operand" "=r")
2126 (match_operand:DI 1 "const64_high_operand" ""))]
2128 "sethi\t%%hi(%a1), %0")
2130 (define_insn "*movdi_insn_sp64_novis"
2131 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W")
2132 (match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,W,e"))]
2133 "TARGET_ARCH64 && ! TARGET_VIS
2134 && (register_operand (operands[0], DImode)
2135 || reg_or_0_operand (operands[1], DImode))"
2138 sethi\t%%hi(%a1), %0
2145 [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore")
2146 (set_attr "fptype" "*,*,*,*,*,double,*,*")])
2148 (define_insn "*movdi_insn_sp64_vis"
2149 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W,b")
2150 (match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,W,e,J"))]
2151 "TARGET_ARCH64 && TARGET_VIS &&
2152 (register_operand (operands[0], DImode)
2153 || reg_or_0_operand (operands[1], DImode))"
2156 sethi\t%%hi(%a1), %0
2164 [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fpmove")
2165 (set_attr "fptype" "*,*,*,*,*,double,*,*,double")])
2167 (define_expand "movdi_pic_label_ref"
2168 [(set (match_dup 3) (high:DI
2169 (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
2170 (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
2171 (set (match_dup 4) (lo_sum:DI (match_dup 3)
2172 (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
2173 (set (match_operand:DI 0 "register_operand" "=r")
2174 (minus:DI (match_dup 5) (match_dup 4)))]
2175 "TARGET_ARCH64 && flag_pic"
2177 current_function_uses_pic_offset_table = 1;
2178 operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2181 operands[3] = operands[0];
2182 operands[4] = operands[0];
2186 operands[3] = gen_reg_rtx (DImode);
2187 operands[4] = gen_reg_rtx (DImode);
2189 operands[5] = pic_offset_table_rtx;
2192 (define_insn "*movdi_high_pic_label_ref"
2193 [(set (match_operand:DI 0 "register_operand" "=r")
2195 (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
2196 (match_operand:DI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
2197 "TARGET_ARCH64 && flag_pic"
2198 "sethi\t%%hi(%a2-(%a1-.)), %0")
2200 (define_insn "*movdi_lo_sum_pic_label_ref"
2201 [(set (match_operand:DI 0 "register_operand" "=r")
2202 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2203 (unspec:DI [(match_operand:DI 2 "label_ref_operand" "")
2204 (match_operand:DI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
2205 "TARGET_ARCH64 && flag_pic"
2206 "or\t%1, %%lo(%a3-(%a2-.)), %0")
2208 ;; SPARC-v9 code model support insns. See sparc_emit_set_symbolic_const64
2209 ;; in sparc.c to see what is going on here... PIC stuff comes first.
2211 (define_insn "movdi_lo_sum_pic"
2212 [(set (match_operand:DI 0 "register_operand" "=r")
2213 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2214 (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))]
2215 "TARGET_ARCH64 && flag_pic"
2216 "or\t%1, %%lo(%a2), %0")
2218 (define_insn "movdi_high_pic"
2219 [(set (match_operand:DI 0 "register_operand" "=r")
2220 (high:DI (unspec:DI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))]
2221 "TARGET_ARCH64 && flag_pic && check_pic (1)"
2222 "sethi\t%%hi(%a1), %0")
2224 (define_insn "*sethi_di_medlow_embmedany_pic"
2225 [(set (match_operand:DI 0 "register_operand" "=r")
2226 (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))]
2227 "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
2228 "sethi\t%%hi(%a1), %0")
2230 (define_insn "*sethi_di_medlow"
2231 [(set (match_operand:DI 0 "register_operand" "=r")
2232 (high:DI (match_operand:DI 1 "symbolic_operand" "")))]
2233 "TARGET_CM_MEDLOW && check_pic (1)"
2234 "sethi\t%%hi(%a1), %0")
2236 (define_insn "*losum_di_medlow"
2237 [(set (match_operand:DI 0 "register_operand" "=r")
2238 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2239 (match_operand:DI 2 "symbolic_operand" "")))]
2241 "or\t%1, %%lo(%a2), %0")
2243 (define_insn "seth44"
2244 [(set (match_operand:DI 0 "register_operand" "=r")
2245 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))]
2247 "sethi\t%%h44(%a1), %0")
2249 (define_insn "setm44"
2250 [(set (match_operand:DI 0 "register_operand" "=r")
2251 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2252 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))]
2254 "or\t%1, %%m44(%a2), %0")
2256 (define_insn "setl44"
2257 [(set (match_operand:DI 0 "register_operand" "=r")
2258 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2259 (match_operand:DI 2 "symbolic_operand" "")))]
2261 "or\t%1, %%l44(%a2), %0")
2263 (define_insn "sethh"
2264 [(set (match_operand:DI 0 "register_operand" "=r")
2265 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))]
2267 "sethi\t%%hh(%a1), %0")
2269 (define_insn "setlm"
2270 [(set (match_operand:DI 0 "register_operand" "=r")
2271 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))]
2273 "sethi\t%%lm(%a1), %0")
2275 (define_insn "sethm"
2276 [(set (match_operand:DI 0 "register_operand" "=r")
2277 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2278 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))]
2280 "or\t%1, %%hm(%a2), %0")
2282 (define_insn "setlo"
2283 [(set (match_operand:DI 0 "register_operand" "=r")
2284 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2285 (match_operand:DI 2 "symbolic_operand" "")))]
2287 "or\t%1, %%lo(%a2), %0")
2289 (define_insn "embmedany_sethi"
2290 [(set (match_operand:DI 0 "register_operand" "=r")
2291 (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))]
2292 "TARGET_CM_EMBMEDANY && check_pic (1)"
2293 "sethi\t%%hi(%a1), %0")
2295 (define_insn "embmedany_losum"
2296 [(set (match_operand:DI 0 "register_operand" "=r")
2297 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2298 (match_operand:DI 2 "data_segment_operand" "")))]
2299 "TARGET_CM_EMBMEDANY"
2300 "add\t%1, %%lo(%a2), %0")
2302 (define_insn "embmedany_brsum"
2303 [(set (match_operand:DI 0 "register_operand" "=r")
2304 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))]
2305 "TARGET_CM_EMBMEDANY"
2308 (define_insn "embmedany_textuhi"
2309 [(set (match_operand:DI 0 "register_operand" "=r")
2310 (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))]
2311 "TARGET_CM_EMBMEDANY && check_pic (1)"
2312 "sethi\t%%uhi(%a1), %0")
2314 (define_insn "embmedany_texthi"
2315 [(set (match_operand:DI 0 "register_operand" "=r")
2316 (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))]
2317 "TARGET_CM_EMBMEDANY && check_pic (1)"
2318 "sethi\t%%hi(%a1), %0")
2320 (define_insn "embmedany_textulo"
2321 [(set (match_operand:DI 0 "register_operand" "=r")
2322 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2323 (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))]
2324 "TARGET_CM_EMBMEDANY"
2325 "or\t%1, %%ulo(%a2), %0")
2327 (define_insn "embmedany_textlo"
2328 [(set (match_operand:DI 0 "register_operand" "=r")
2329 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2330 (match_operand:DI 2 "text_segment_operand" "")))]
2331 "TARGET_CM_EMBMEDANY"
2332 "or\t%1, %%lo(%a2), %0")
2334 ;; Now some patterns to help reload out a bit.
2335 (define_expand "reload_indi"
2336 [(parallel [(match_operand:DI 0 "register_operand" "=r")
2337 (match_operand:DI 1 "immediate_operand" "")
2338 (match_operand:TI 2 "register_operand" "=&r")])]
2340 || TARGET_CM_EMBMEDANY)
2343 sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
2347 (define_expand "reload_outdi"
2348 [(parallel [(match_operand:DI 0 "register_operand" "=r")
2349 (match_operand:DI 1 "immediate_operand" "")
2350 (match_operand:TI 2 "register_operand" "=&r")])]
2352 || TARGET_CM_EMBMEDANY)
2355 sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
2359 ;; Split up putting CONSTs and REGs into DI regs when !arch64
2361 [(set (match_operand:DI 0 "register_operand" "")
2362 (match_operand:DI 1 "const_int_operand" ""))]
2363 "! TARGET_ARCH64 && reload_completed"
2364 [(clobber (const_int 0))]
2366 #if HOST_BITS_PER_WIDE_INT == 32
2367 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
2368 (INTVAL (operands[1]) < 0) ?
2371 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2374 unsigned int low, high;
2376 low = trunc_int_for_mode (INTVAL (operands[1]), SImode);
2377 high = trunc_int_for_mode (INTVAL (operands[1]) >> 32, SImode);
2378 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), GEN_INT (high)));
2380 /* Slick... but this trick loses if this subreg constant part
2381 can be done in one insn. */
2382 if (low == high && (low & 0x3ff) != 0 && low + 0x1000 >= 0x2000)
2383 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2384 gen_highpart (SImode, operands[0])));
2386 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), GEN_INT (low)));
2392 [(set (match_operand:DI 0 "register_operand" "")
2393 (match_operand:DI 1 "const_double_operand" ""))]
2397 && ((GET_CODE (operands[0]) == REG
2398 && REGNO (operands[0]) < 32)
2399 || (GET_CODE (operands[0]) == SUBREG
2400 && GET_CODE (SUBREG_REG (operands[0])) == REG
2401 && REGNO (SUBREG_REG (operands[0])) < 32))))"
2402 [(clobber (const_int 0))]
2404 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
2405 GEN_INT (CONST_DOUBLE_HIGH (operands[1]))));
2407 /* Slick... but this trick loses if this subreg constant part
2408 can be done in one insn. */
2409 if (CONST_DOUBLE_LOW (operands[1]) == CONST_DOUBLE_HIGH (operands[1])
2410 && !(SPARC_SETHI32_P (CONST_DOUBLE_HIGH (operands[1]))
2411 || SPARC_SIMM13_P (CONST_DOUBLE_HIGH (operands[1]))))
2413 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2414 gen_highpart (SImode, operands[0])));
2418 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
2419 GEN_INT (CONST_DOUBLE_LOW (operands[1]))));
2425 [(set (match_operand:DI 0 "register_operand" "")
2426 (match_operand:DI 1 "register_operand" ""))]
2430 && ((GET_CODE (operands[0]) == REG
2431 && REGNO (operands[0]) < 32)
2432 || (GET_CODE (operands[0]) == SUBREG
2433 && GET_CODE (SUBREG_REG (operands[0])) == REG
2434 && REGNO (SUBREG_REG (operands[0])) < 32))))"
2435 [(clobber (const_int 0))]
2437 rtx set_dest = operands[0];
2438 rtx set_src = operands[1];
2442 dest1 = gen_highpart (SImode, set_dest);
2443 dest2 = gen_lowpart (SImode, set_dest);
2444 src1 = gen_highpart (SImode, set_src);
2445 src2 = gen_lowpart (SImode, set_src);
2447 /* Now emit using the real source and destination we found, swapping
2448 the order if we detect overlap. */
2449 if (reg_overlap_mentioned_p (dest1, src2))
2451 emit_insn (gen_movsi (dest2, src2));
2452 emit_insn (gen_movsi (dest1, src1));
2456 emit_insn (gen_movsi (dest1, src1));
2457 emit_insn (gen_movsi (dest2, src2));
2462 ;; Now handle the cases of memory moves from/to non-even
2463 ;; DI mode register pairs.
2465 [(set (match_operand:DI 0 "register_operand" "")
2466 (match_operand:DI 1 "memory_operand" ""))]
2469 && sparc_splitdi_legitimate (operands[0], operands[1]))"
2470 [(clobber (const_int 0))]
2472 rtx word0 = adjust_address (operands[1], SImode, 0);
2473 rtx word1 = adjust_address (operands[1], SImode, 4);
2474 rtx high_part = gen_highpart (SImode, operands[0]);
2475 rtx low_part = gen_lowpart (SImode, operands[0]);
2477 if (reg_overlap_mentioned_p (high_part, word1))
2479 emit_insn (gen_movsi (low_part, word1));
2480 emit_insn (gen_movsi (high_part, word0));
2484 emit_insn (gen_movsi (high_part, word0));
2485 emit_insn (gen_movsi (low_part, word1));
2491 [(set (match_operand:DI 0 "memory_operand" "")
2492 (match_operand:DI 1 "register_operand" ""))]
2495 && sparc_splitdi_legitimate (operands[1], operands[0]))"
2496 [(clobber (const_int 0))]
2498 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0),
2499 gen_highpart (SImode, operands[1])));
2500 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4),
2501 gen_lowpart (SImode, operands[1])));
2506 [(set (match_operand:DI 0 "memory_operand" "")
2511 && ! mem_min_alignment (operands[0], 8)))
2512 && offsettable_memref_p (operands[0])"
2513 [(clobber (const_int 0))]
2515 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), const0_rtx));
2516 emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx));
2520 ;; Floating point move insns
2522 (define_insn "*movsf_insn_novis"
2523 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,*r,*r,*r,*r,*r,f,m,m")
2524 (match_operand:SF 1 "input_operand" "f,G,Q,*rR,S,m,m,f,*rG"))]
2525 "(TARGET_FPU && ! TARGET_VIS)
2526 && (register_operand (operands[0], SFmode)
2527 || register_operand (operands[1], SFmode)
2528 || fp_zero_operand (operands[1], SFmode))"
2530 if (GET_CODE (operands[1]) == CONST_DOUBLE
2531 && (which_alternative == 2
2532 || which_alternative == 3
2533 || which_alternative == 4))
2538 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2539 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2540 operands[1] = GEN_INT (i);
2543 switch (which_alternative)
2546 return "fmovs\t%1, %0";
2550 return "sethi\t%%hi(%a1), %0";
2552 return "mov\t%1, %0";
2557 return "ld\t%1, %0";
2560 return "st\t%r1, %0";
2565 [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")])
2567 (define_insn "*movsf_insn_vis"
2568 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m")
2569 (match_operand:SF 1 "input_operand" "f,G,G,Q,*rR,S,m,m,f,*rG"))]
2570 "(TARGET_FPU && TARGET_VIS)
2571 && (register_operand (operands[0], SFmode)
2572 || register_operand (operands[1], SFmode)
2573 || fp_zero_operand (operands[1], SFmode))"
2575 if (GET_CODE (operands[1]) == CONST_DOUBLE
2576 && (which_alternative == 3
2577 || which_alternative == 4
2578 || which_alternative == 5))
2583 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2584 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2585 operands[1] = GEN_INT (i);
2588 switch (which_alternative)
2591 return "fmovs\t%1, %0";
2593 return "fzeros\t%0";
2597 return "sethi\t%%hi(%a1), %0";
2599 return "mov\t%1, %0";
2604 return "ld\t%1, %0";
2607 return "st\t%r1, %0";
2612 [(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store")])
2614 ;; Exactly the same as above, except that all `f' cases are deleted.
2615 ;; This is necessary to prevent reload from ever trying to use a `f' reg
2618 (define_insn "*movsf_no_f_insn"
2619 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,r,m")
2620 (match_operand:SF 1 "input_operand" "G,Q,rR,S,m,rG"))]
2622 && (register_operand (operands[0], SFmode)
2623 || register_operand (operands[1], SFmode)
2624 || fp_zero_operand (operands[1], SFmode))"
2626 if (GET_CODE (operands[1]) == CONST_DOUBLE
2627 && (which_alternative == 1
2628 || which_alternative == 2
2629 || which_alternative == 3))
2634 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2635 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2636 operands[1] = GEN_INT (i);
2639 switch (which_alternative)
2644 return "sethi\t%%hi(%a1), %0";
2646 return "mov\t%1, %0";
2650 return "ld\t%1, %0";
2652 return "st\t%r1, %0";
2657 [(set_attr "type" "*,*,*,*,load,store")])
2659 (define_insn "*movsf_lo_sum"
2660 [(set (match_operand:SF 0 "register_operand" "=r")
2661 (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
2662 (match_operand:SF 2 "const_double_operand" "S")))]
2663 "fp_high_losum_p (operands[2])"
2668 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
2669 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2670 operands[2] = GEN_INT (i);
2671 return "or\t%1, %%lo(%a2), %0";
2674 (define_insn "*movsf_high"
2675 [(set (match_operand:SF 0 "register_operand" "=r")
2676 (high:SF (match_operand:SF 1 "const_double_operand" "S")))]
2677 "fp_high_losum_p (operands[1])"
2682 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2683 REAL_VALUE_TO_TARGET_SINGLE (r, i);
2684 operands[1] = GEN_INT (i);
2685 return "sethi\t%%hi(%1), %0";
2689 [(set (match_operand:SF 0 "register_operand" "")
2690 (match_operand:SF 1 "const_double_operand" ""))]
2691 "fp_high_losum_p (operands[1])
2692 && (GET_CODE (operands[0]) == REG
2693 && REGNO (operands[0]) < 32)"
2694 [(set (match_dup 0) (high:SF (match_dup 1)))
2695 (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
2697 (define_expand "movsf"
2698 [(set (match_operand:SF 0 "general_operand" "")
2699 (match_operand:SF 1 "general_operand" ""))]
2702 /* Force SFmode constants into memory. */
2703 if (GET_CODE (operands[0]) == REG
2704 && CONSTANT_P (operands[1]))
2706 /* emit_group_store will send such bogosity to us when it is
2707 not storing directly into memory. So fix this up to avoid
2708 crashes in output_constant_pool. */
2709 if (operands [1] == const0_rtx)
2710 operands[1] = CONST0_RTX (SFmode);
2712 if (TARGET_VIS && fp_zero_operand (operands[1], SFmode))
2715 /* We are able to build any SF constant in integer registers
2716 with at most 2 instructions. */
2717 if (REGNO (operands[0]) < 32)
2720 operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
2724 /* Handle sets of MEM first. */
2725 if (GET_CODE (operands[0]) == MEM)
2727 if (register_operand (operands[1], SFmode)
2728 || fp_zero_operand (operands[1], SFmode))
2731 if (! reload_in_progress)
2733 operands[0] = validize_mem (operands[0]);
2734 operands[1] = force_reg (SFmode, operands[1]);
2738 /* Fixup PIC cases. */
2741 if (CONSTANT_P (operands[1])
2742 && pic_address_needs_scratch (operands[1]))
2743 operands[1] = legitimize_pic_address (operands[1], SFmode, 0);
2745 if (symbolic_operand (operands[1], SFmode))
2747 operands[1] = legitimize_pic_address (operands[1],
2749 (reload_in_progress ?
2759 (define_expand "movdf"
2760 [(set (match_operand:DF 0 "general_operand" "")
2761 (match_operand:DF 1 "general_operand" ""))]
2764 /* Force DFmode constants into memory. */
2765 if (GET_CODE (operands[0]) == REG
2766 && CONSTANT_P (operands[1]))
2768 /* emit_group_store will send such bogosity to us when it is
2769 not storing directly into memory. So fix this up to avoid
2770 crashes in output_constant_pool. */
2771 if (operands [1] == const0_rtx)
2772 operands[1] = CONST0_RTX (DFmode);
2774 if ((TARGET_VIS || REGNO (operands[0]) < 32)
2775 && fp_zero_operand (operands[1], DFmode))
2778 /* We are able to build any DF constant in integer registers. */
2779 if (REGNO (operands[0]) < 32
2780 && (reload_completed || reload_in_progress))
2783 operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
2787 /* Handle MEM cases first. */
2788 if (GET_CODE (operands[0]) == MEM)
2790 if (register_operand (operands[1], DFmode)
2791 || fp_zero_operand (operands[1], DFmode))
2794 if (! reload_in_progress)
2796 operands[0] = validize_mem (operands[0]);
2797 operands[1] = force_reg (DFmode, operands[1]);
2801 /* Fixup PIC cases. */
2804 if (CONSTANT_P (operands[1])
2805 && pic_address_needs_scratch (operands[1]))
2806 operands[1] = legitimize_pic_address (operands[1], DFmode, 0);
2808 if (symbolic_operand (operands[1], DFmode))
2810 operands[1] = legitimize_pic_address (operands[1],
2812 (reload_in_progress ?
2822 ;; Be careful, fmovd does not exist when !v9.
2823 (define_insn "*movdf_insn_sp32"
2824 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,W,U,T,o,e,*r,o,e,o")
2825 (match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
2828 && (register_operand (operands[0], DFmode)
2829 || register_operand (operands[1], DFmode)
2830 || fp_zero_operand (operands[1], DFmode))"
2842 [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*")
2843 (set_attr "length" "*,*,*,*,2,2,2,2,2,2")])
2845 (define_insn "*movdf_no_e_insn_sp32"
2846 [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
2847 (match_operand:DF 1 "input_operand" "T,U,G,ro,r"))]
2851 && (register_operand (operands[0], DFmode)
2852 || register_operand (operands[1], DFmode)
2853 || fp_zero_operand (operands[1], DFmode))"
2860 [(set_attr "type" "load,store,*,*,*")
2861 (set_attr "length" "*,*,2,2,2")])
2863 (define_insn "*movdf_no_e_insn_v9_sp32"
2864 [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
2865 (match_operand:DF 1 "input_operand" "T,U,G,ro,rG"))]
2869 && (register_operand (operands[0], DFmode)
2870 || register_operand (operands[1], DFmode)
2871 || fp_zero_operand (operands[1], DFmode))"
2878 [(set_attr "type" "load,store,store,*,*")
2879 (set_attr "length" "*,*,*,2,2")])
2881 ;; We have available v9 double floats but not 64-bit
2882 ;; integer registers and no VIS.
2883 (define_insn "*movdf_insn_v9only_novis"
2884 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,T,W,U,T,f,*r,o")
2885 (match_operand:DF 1 "input_operand" "e,W#F,G,e,T,U,o#F,*roF,*rGf"))]
2890 && (register_operand (operands[0], DFmode)
2891 || register_operand (operands[1], DFmode)
2892 || fp_zero_operand (operands[1], DFmode))"
2903 [(set_attr "type" "fpmove,load,store,store,load,store,*,*,*")
2904 (set_attr "length" "*,*,*,*,*,*,2,2,2")
2905 (set_attr "fptype" "double,*,*,*,*,*,*,*,*")])
2907 ;; We have available v9 double floats but not 64-bit
2908 ;; integer registers but we have VIS.
2909 (define_insn "*movdf_insn_v9only_vis"
2910 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,f,*r,o")
2911 (match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGf"))]
2915 && (register_operand (operands[0], DFmode)
2916 || register_operand (operands[1], DFmode)
2917 || fp_zero_operand (operands[1], DFmode))"
2929 [(set_attr "type" "fpmove,fpmove,load,store,store,load,store,*,*,*")
2930 (set_attr "length" "*,*,*,*,*,*,*,2,2,2")
2931 (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
2933 ;; We have available both v9 double floats and 64-bit
2934 ;; integer registers. No VIS though.
2935 (define_insn "*movdf_insn_sp64_novis"
2936 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,W,*r,*r,m,*r")
2937 (match_operand:DF 1 "input_operand" "e,W#F,e,*rG,m,*rG,F"))]
2941 && (register_operand (operands[0], DFmode)
2942 || register_operand (operands[1], DFmode)
2943 || fp_zero_operand (operands[1], DFmode))"
2952 [(set_attr "type" "fpmove,load,store,*,load,store,*")
2953 (set_attr "length" "*,*,*,*,*,*,2")
2954 (set_attr "fptype" "double,*,*,*,*,*,*")])
2956 ;; We have available both v9 double floats and 64-bit
2957 ;; integer registers. And we have VIS.
2958 (define_insn "*movdf_insn_sp64_vis"
2959 [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,W,*r,*r,m,*r")
2960 (match_operand:DF 1 "input_operand" "G,e,W#F,e,*rG,m,*rG,F"))]
2964 && (register_operand (operands[0], DFmode)
2965 || register_operand (operands[1], DFmode)
2966 || fp_zero_operand (operands[1], DFmode))"
2976 [(set_attr "type" "fpmove,fpmove,load,store,*,load,store,*")
2977 (set_attr "length" "*,*,*,*,*,*,*,2")
2978 (set_attr "fptype" "double,double,*,*,*,*,*,*")])
2980 (define_insn "*movdf_no_e_insn_sp64"
2981 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
2982 (match_operand:DF 1 "input_operand" "r,m,rG"))]
2985 && (register_operand (operands[0], DFmode)
2986 || register_operand (operands[1], DFmode)
2987 || fp_zero_operand (operands[1], DFmode))"
2992 [(set_attr "type" "*,load,store")])
2995 [(set (match_operand:DF 0 "register_operand" "")
2996 (match_operand:DF 1 "const_double_operand" ""))]
2998 && (GET_CODE (operands[0]) == REG
2999 && REGNO (operands[0]) < 32)
3000 && ! fp_zero_operand(operands[1], DFmode)
3001 && reload_completed"
3002 [(clobber (const_int 0))]
3007 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
3008 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
3009 operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));
3013 #if HOST_BITS_PER_WIDE_INT == 64
3016 val = ((HOST_WIDE_INT)(unsigned long)l[1] |
3017 ((HOST_WIDE_INT)(unsigned long)l[0] << 32));
3018 emit_insn (gen_movdi (operands[0], GEN_INT (val)));
3020 emit_insn (gen_movdi (operands[0],
3021 immed_double_const (l[1], l[0], DImode)));
3026 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]),
3029 /* Slick... but this trick loses if this subreg constant part
3030 can be done in one insn. */
3032 && !(SPARC_SETHI32_P (l[0])
3033 || SPARC_SIMM13_P (l[0])))
3035 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
3036 gen_highpart (SImode, operands[0])));
3040 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
3047 ;; Ok, now the splits to handle all the multi insn and
3048 ;; mis-aligned memory address cases.
3049 ;; In these splits please take note that we must be
3050 ;; careful when V9 but not ARCH64 because the integer
3051 ;; register DFmode cases must be handled.
3053 [(set (match_operand:DF 0 "register_operand" "")
3054 (match_operand:DF 1 "register_operand" ""))]
3057 && ((GET_CODE (operands[0]) == REG
3058 && REGNO (operands[0]) < 32)
3059 || (GET_CODE (operands[0]) == SUBREG
3060 && GET_CODE (SUBREG_REG (operands[0])) == REG
3061 && REGNO (SUBREG_REG (operands[0])) < 32))))
3062 && reload_completed"
3063 [(clobber (const_int 0))]
3065 rtx set_dest = operands[0];
3066 rtx set_src = operands[1];
3070 dest1 = gen_highpart (SFmode, set_dest);
3071 dest2 = gen_lowpart (SFmode, set_dest);
3072 src1 = gen_highpart (SFmode, set_src);
3073 src2 = gen_lowpart (SFmode, set_src);
3075 /* Now emit using the real source and destination we found, swapping
3076 the order if we detect overlap. */
3077 if (reg_overlap_mentioned_p (dest1, src2))
3079 emit_insn (gen_movsf (dest2, src2));
3080 emit_insn (gen_movsf (dest1, src1));
3084 emit_insn (gen_movsf (dest1, src1));
3085 emit_insn (gen_movsf (dest2, src2));
3091 [(set (match_operand:DF 0 "register_operand" "")
3092 (match_operand:DF 1 "memory_operand" ""))]
3095 && (((REGNO (operands[0]) % 2) != 0)
3096 || ! mem_min_alignment (operands[1], 8))
3097 && offsettable_memref_p (operands[1])"
3098 [(clobber (const_int 0))]
3100 rtx word0 = adjust_address (operands[1], SFmode, 0);
3101 rtx word1 = adjust_address (operands[1], SFmode, 4);
3103 if (reg_overlap_mentioned_p (gen_highpart (SFmode, operands[0]), word1))
3105 emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]),
3107 emit_insn (gen_movsf (gen_highpart (SFmode, operands[0]),
3112 emit_insn (gen_movsf (gen_highpart (SFmode, operands[0]),
3114 emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]),
3121 [(set (match_operand:DF 0 "memory_operand" "")
3122 (match_operand:DF 1 "register_operand" ""))]
3125 && (((REGNO (operands[1]) % 2) != 0)
3126 || ! mem_min_alignment (operands[0], 8))
3127 && offsettable_memref_p (operands[0])"
3128 [(clobber (const_int 0))]
3130 rtx word0 = adjust_address (operands[0], SFmode, 0);
3131 rtx word1 = adjust_address (operands[0], SFmode, 4);
3133 emit_insn (gen_movsf (word0,
3134 gen_highpart (SFmode, operands[1])));
3135 emit_insn (gen_movsf (word1,
3136 gen_lowpart (SFmode, operands[1])));
3141 [(set (match_operand:DF 0 "memory_operand" "")
3142 (match_operand:DF 1 "fp_zero_operand" ""))]
3146 && ! mem_min_alignment (operands[0], 8)))
3147 && offsettable_memref_p (operands[0])"
3148 [(clobber (const_int 0))]
3152 dest1 = adjust_address (operands[0], SFmode, 0);
3153 dest2 = adjust_address (operands[0], SFmode, 4);
3155 emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
3156 emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode)));
3161 [(set (match_operand:DF 0 "register_operand" "")
3162 (match_operand:DF 1 "fp_zero_operand" ""))]
3165 && ((GET_CODE (operands[0]) == REG
3166 && REGNO (operands[0]) < 32)
3167 || (GET_CODE (operands[0]) == SUBREG
3168 && GET_CODE (SUBREG_REG (operands[0])) == REG
3169 && REGNO (SUBREG_REG (operands[0])) < 32))"
3170 [(clobber (const_int 0))]
3172 rtx set_dest = operands[0];
3175 dest1 = gen_highpart (SFmode, set_dest);
3176 dest2 = gen_lowpart (SFmode, set_dest);
3177 emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
3178 emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode)));
3182 (define_expand "movtf"
3183 [(set (match_operand:TF 0 "general_operand" "")
3184 (match_operand:TF 1 "general_operand" ""))]
3187 /* Force TFmode constants into memory. */
3188 if (GET_CODE (operands[0]) == REG
3189 && CONSTANT_P (operands[1]))
3191 /* emit_group_store will send such bogosity to us when it is
3192 not storing directly into memory. So fix this up to avoid
3193 crashes in output_constant_pool. */
3194 if (operands [1] == const0_rtx)
3195 operands[1] = CONST0_RTX (TFmode);
3197 if (TARGET_VIS && fp_zero_operand (operands[1], TFmode))
3200 operands[1] = validize_mem (force_const_mem (GET_MODE (operands[0]),
3204 /* Handle MEM cases first, note that only v9 guarantees
3205 full 16-byte alignment for quads. */
3206 if (GET_CODE (operands[0]) == MEM)
3208 if (register_operand (operands[1], TFmode)
3209 || fp_zero_operand (operands[1], TFmode))
3212 if (! reload_in_progress)
3214 operands[0] = validize_mem (operands[0]);
3215 operands[1] = force_reg (TFmode, operands[1]);
3219 /* Fixup PIC cases. */
3222 if (CONSTANT_P (operands[1])
3223 && pic_address_needs_scratch (operands[1]))
3224 operands[1] = legitimize_pic_address (operands[1], TFmode, 0);
3226 if (symbolic_operand (operands[1], TFmode))
3228 operands[1] = legitimize_pic_address (operands[1],
3230 (reload_in_progress ?
3240 ;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so
3241 ;; we must split them all. :-(
3242 (define_insn "*movtf_insn_sp32"
3243 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
3244 (match_operand:TF 1 "input_operand" "oe,GeUr,o,roG"))]
3248 && (register_operand (operands[0], TFmode)
3249 || register_operand (operands[1], TFmode)
3250 || fp_zero_operand (operands[1], TFmode))"
3252 [(set_attr "length" "4")])
3254 (define_insn "*movtf_insn_vis_sp32"
3255 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,U,r")
3256 (match_operand:TF 1 "input_operand" "Goe,GeUr,o,roG"))]
3260 && (register_operand (operands[0], TFmode)
3261 || register_operand (operands[1], TFmode)
3262 || fp_zero_operand (operands[1], TFmode))"
3264 [(set_attr "length" "4")])
3266 ;; Exactly the same as above, except that all `e' cases are deleted.
3267 ;; This is necessary to prevent reload from ever trying to use a `e' reg
3270 (define_insn "*movtf_no_e_insn_sp32"
3271 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
3272 (match_operand:TF 1 "input_operand" "G,o,U,roG,r"))]
3275 && (register_operand (operands[0], TFmode)
3276 || register_operand (operands[1], TFmode)
3277 || fp_zero_operand (operands[1], TFmode))"
3279 [(set_attr "length" "4")])
3281 ;; Now handle the float reg cases directly when arch64,
3282 ;; hard_quad, and proper reg number alignment are all true.
3283 (define_insn "*movtf_insn_hq_sp64"
3284 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,o,r")
3285 (match_operand:TF 1 "input_operand" "e,m,e,Gr,roG"))]
3290 && (register_operand (operands[0], TFmode)
3291 || register_operand (operands[1], TFmode)
3292 || fp_zero_operand (operands[1], TFmode))"
3299 [(set_attr "type" "fpmove,fpload,fpstore,*,*")
3300 (set_attr "length" "*,*,*,2,2")])
3302 (define_insn "*movtf_insn_hq_vis_sp64"
3303 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o")
3304 (match_operand:TF 1 "input_operand" "e,m,e,G,roG,r"))]
3309 && (register_operand (operands[0], TFmode)
3310 || register_operand (operands[1], TFmode)
3311 || fp_zero_operand (operands[1], TFmode))"
3319 [(set_attr "type" "fpmove,fpload,fpstore,*,*,*")
3320 (set_attr "length" "*,*,*,2,2,2")])
3322 ;; Now we allow the integer register cases even when
3323 ;; only arch64 is true.
3324 (define_insn "*movtf_insn_sp64"
3325 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
3326 (match_operand:TF 1 "input_operand" "oe,Ger,orG"))]
3330 && ! TARGET_HARD_QUAD
3331 && (register_operand (operands[0], TFmode)
3332 || register_operand (operands[1], TFmode)
3333 || fp_zero_operand (operands[1], TFmode))"
3335 [(set_attr "length" "2")])
3337 (define_insn "*movtf_insn_vis_sp64"
3338 [(set (match_operand:TF 0 "nonimmediate_operand" "=e,o,r")
3339 (match_operand:TF 1 "input_operand" "Goe,Ger,orG"))]
3343 && ! TARGET_HARD_QUAD
3344 && (register_operand (operands[0], TFmode)
3345 || register_operand (operands[1], TFmode)
3346 || fp_zero_operand (operands[1], TFmode))"
3348 [(set_attr "length" "2")])
3350 (define_insn "*movtf_no_e_insn_sp64"
3351 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
3352 (match_operand:TF 1 "input_operand" "orG,rG"))]
3355 && (register_operand (operands[0], TFmode)
3356 || register_operand (operands[1], TFmode)
3357 || fp_zero_operand (operands[1], TFmode))"
3359 [(set_attr "length" "2")])
3361 ;; Now all the splits to handle multi-insn TF mode moves.
3363 [(set (match_operand:TF 0 "register_operand" "")
3364 (match_operand:TF 1 "register_operand" ""))]
3368 && ! TARGET_HARD_QUAD)
3369 || ! fp_register_operand (operands[0], TFmode))"
3370 [(clobber (const_int 0))]
3372 rtx set_dest = operands[0];
3373 rtx set_src = operands[1];
3377 dest1 = gen_df_reg (set_dest, 0);
3378 dest2 = gen_df_reg (set_dest, 1);
3379 src1 = gen_df_reg (set_src, 0);
3380 src2 = gen_df_reg (set_src, 1);
3382 /* Now emit using the real source and destination we found, swapping
3383 the order if we detect overlap. */
3384 if (reg_overlap_mentioned_p (dest1, src2))
3386 emit_insn (gen_movdf (dest2, src2));
3387 emit_insn (gen_movdf (dest1, src1));
3391 emit_insn (gen_movdf (dest1, src1));
3392 emit_insn (gen_movdf (dest2, src2));
3398 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3399 (match_operand:TF 1 "fp_zero_operand" ""))]
3401 [(clobber (const_int 0))]
3403 rtx set_dest = operands[0];
3406 switch (GET_CODE (set_dest))
3409 dest1 = gen_df_reg (set_dest, 0);
3410 dest2 = gen_df_reg (set_dest, 1);
3413 dest1 = adjust_address (set_dest, DFmode, 0);
3414 dest2 = adjust_address (set_dest, DFmode, 8);
3420 emit_insn (gen_movdf (dest1, CONST0_RTX (DFmode)));
3421 emit_insn (gen_movdf (dest2, CONST0_RTX (DFmode)));
3426 [(set (match_operand:TF 0 "register_operand" "")
3427 (match_operand:TF 1 "memory_operand" ""))]
3429 && offsettable_memref_p (operands[1])
3431 || ! TARGET_HARD_QUAD
3432 || ! fp_register_operand (operands[0], TFmode)))"
3433 [(clobber (const_int 0))]
3435 rtx word0 = adjust_address (operands[1], DFmode, 0);
3436 rtx word1 = adjust_address (operands[1], DFmode, 8);
3437 rtx set_dest, dest1, dest2;
3439 set_dest = operands[0];
3441 dest1 = gen_df_reg (set_dest, 0);
3442 dest2 = gen_df_reg (set_dest, 1);
3444 /* Now output, ordering such that we don't clobber any registers
3445 mentioned in the address. */
3446 if (reg_overlap_mentioned_p (dest1, word1))
3449 emit_insn (gen_movdf (dest2, word1));
3450 emit_insn (gen_movdf (dest1, word0));
3454 emit_insn (gen_movdf (dest1, word0));
3455 emit_insn (gen_movdf (dest2, word1));
3461 [(set (match_operand:TF 0 "memory_operand" "")
3462 (match_operand:TF 1 "register_operand" ""))]
3464 && offsettable_memref_p (operands[0])
3466 || ! TARGET_HARD_QUAD
3467 || ! fp_register_operand (operands[1], TFmode)))"
3468 [(clobber (const_int 0))]
3470 rtx set_src = operands[1];
3472 emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 0),
3473 gen_df_reg (set_src, 0)));
3474 emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 8),
3475 gen_df_reg (set_src, 1)));
3479 ;; SPARC V9 conditional move instructions.
3481 ;; We can handle larger constants here for some flavors, but for now we keep
3482 ;; it simple and only allow those constants supported by all flavors.
3483 ;; Note that emit_conditional_move canonicalizes operands 2,3 so that operand
3484 ;; 3 contains the constant if one is present, but we handle either for
3485 ;; generality (sparc.c puts a constant in operand 2).
3487 (define_expand "movqicc"
3488 [(set (match_operand:QI 0 "register_operand" "")
3489 (if_then_else:QI (match_operand 1 "comparison_operator" "")
3490 (match_operand:QI 2 "arith10_operand" "")
3491 (match_operand:QI 3 "arith10_operand" "")))]
3494 enum rtx_code code = GET_CODE (operands[1]);
3496 if (GET_MODE (sparc_compare_op0) == DImode
3500 if (sparc_compare_op1 == const0_rtx
3501 && GET_CODE (sparc_compare_op0) == REG
3502 && GET_MODE (sparc_compare_op0) == DImode
3503 && v9_regcmp_p (code))
3505 operands[1] = gen_rtx_fmt_ee (code, DImode,
3506 sparc_compare_op0, sparc_compare_op1);
3510 rtx cc_reg = gen_compare_reg (code,
3511 sparc_compare_op0, sparc_compare_op1);
3512 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
3516 (define_expand "movhicc"
3517 [(set (match_operand:HI 0 "register_operand" "")
3518 (if_then_else:HI (match_operand 1 "comparison_operator" "")
3519 (match_operand:HI 2 "arith10_operand" "")
3520 (match_operand:HI 3 "arith10_operand" "")))]
3523 enum rtx_code code = GET_CODE (operands[1]);
3525 if (GET_MODE (sparc_compare_op0) == DImode
3529 if (sparc_compare_op1 == const0_rtx
3530 && GET_CODE (sparc_compare_op0) == REG
3531 && GET_MODE (sparc_compare_op0) == DImode
3532 && v9_regcmp_p (code))
3534 operands[1] = gen_rtx_fmt_ee (code, DImode,
3535 sparc_compare_op0, sparc_compare_op1);
3539 rtx cc_reg = gen_compare_reg (code,
3540 sparc_compare_op0, sparc_compare_op1);
3541 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
3545 (define_expand "movsicc"
3546 [(set (match_operand:SI 0 "register_operand" "")
3547 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3548 (match_operand:SI 2 "arith10_operand" "")
3549 (match_operand:SI 3 "arith10_operand" "")))]
3552 enum rtx_code code = GET_CODE (operands[1]);
3553 enum machine_mode op0_mode = GET_MODE (sparc_compare_op0);
3555 if (sparc_compare_op1 == const0_rtx
3556 && GET_CODE (sparc_compare_op0) == REG
3557 && (TARGET_ARCH64 && op0_mode == DImode && v9_regcmp_p (code)))
3559 operands[1] = gen_rtx_fmt_ee (code, op0_mode,
3560 sparc_compare_op0, sparc_compare_op1);
3564 rtx cc_reg = gen_compare_reg (code,
3565 sparc_compare_op0, sparc_compare_op1);
3566 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg),
3567 cc_reg, const0_rtx);
3571 (define_expand "movdicc"
3572 [(set (match_operand:DI 0 "register_operand" "")
3573 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3574 (match_operand:DI 2 "arith10_double_operand" "")
3575 (match_operand:DI 3 "arith10_double_operand" "")))]
3578 enum rtx_code code = GET_CODE (operands[1]);
3580 if (sparc_compare_op1 == const0_rtx
3581 && GET_CODE (sparc_compare_op0) == REG
3582 && GET_MODE (sparc_compare_op0) == DImode
3583 && v9_regcmp_p (code))
3585 operands[1] = gen_rtx_fmt_ee (code, DImode,
3586 sparc_compare_op0, sparc_compare_op1);
3590 rtx cc_reg = gen_compare_reg (code,
3591 sparc_compare_op0, sparc_compare_op1);
3592 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg),
3593 cc_reg, const0_rtx);
3597 (define_expand "movsfcc"
3598 [(set (match_operand:SF 0 "register_operand" "")
3599 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3600 (match_operand:SF 2 "register_operand" "")
3601 (match_operand:SF 3 "register_operand" "")))]
3602 "TARGET_V9 && TARGET_FPU"
3604 enum rtx_code code = GET_CODE (operands[1]);
3606 if (GET_MODE (sparc_compare_op0) == DImode
3610 if (sparc_compare_op1 == const0_rtx
3611 && GET_CODE (sparc_compare_op0) == REG
3612 && GET_MODE (sparc_compare_op0) == DImode
3613 && v9_regcmp_p (code))
3615 operands[1] = gen_rtx_fmt_ee (code, DImode,
3616 sparc_compare_op0, sparc_compare_op1);
3620 rtx cc_reg = gen_compare_reg (code,
3621 sparc_compare_op0, sparc_compare_op1);
3622 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
3626 (define_expand "movdfcc"
3627 [(set (match_operand:DF 0 "register_operand" "")
3628 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3629 (match_operand:DF 2 "register_operand" "")
3630 (match_operand:DF 3 "register_operand" "")))]
3631 "TARGET_V9 && TARGET_FPU"
3633 enum rtx_code code = GET_CODE (operands[1]);
3635 if (GET_MODE (sparc_compare_op0) == DImode
3639 if (sparc_compare_op1 == const0_rtx
3640 && GET_CODE (sparc_compare_op0) == REG
3641 && GET_MODE (sparc_compare_op0) == DImode
3642 && v9_regcmp_p (code))
3644 operands[1] = gen_rtx_fmt_ee (code, DImode,
3645 sparc_compare_op0, sparc_compare_op1);
3649 rtx cc_reg = gen_compare_reg (code,
3650 sparc_compare_op0, sparc_compare_op1);
3651 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
3655 (define_expand "movtfcc"
3656 [(set (match_operand:TF 0 "register_operand" "")
3657 (if_then_else:TF (match_operand 1 "comparison_operator" "")
3658 (match_operand:TF 2 "register_operand" "")
3659 (match_operand:TF 3 "register_operand" "")))]
3660 "TARGET_V9 && TARGET_FPU"
3662 enum rtx_code code = GET_CODE (operands[1]);
3664 if (GET_MODE (sparc_compare_op0) == DImode
3668 if (sparc_compare_op1 == const0_rtx
3669 && GET_CODE (sparc_compare_op0) == REG
3670 && GET_MODE (sparc_compare_op0) == DImode
3671 && v9_regcmp_p (code))
3673 operands[1] = gen_rtx_fmt_ee (code, DImode,
3674 sparc_compare_op0, sparc_compare_op1);
3678 rtx cc_reg = gen_compare_reg (code,
3679 sparc_compare_op0, sparc_compare_op1);
3680 operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
3684 ;; Conditional move define_insns.
3686 (define_insn "*movqi_cc_sp64"
3687 [(set (match_operand:QI 0 "register_operand" "=r,r")
3688 (if_then_else:QI (match_operator 1 "comparison_operator"
3689 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3691 (match_operand:QI 3 "arith11_operand" "rL,0")
3692 (match_operand:QI 4 "arith11_operand" "0,rL")))]
3696 mov%c1\t%x2, %4, %0"
3697 [(set_attr "type" "cmove")])
3699 (define_insn "*movhi_cc_sp64"
3700 [(set (match_operand:HI 0 "register_operand" "=r,r")
3701 (if_then_else:HI (match_operator 1 "comparison_operator"
3702 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3704 (match_operand:HI 3 "arith11_operand" "rL,0")
3705 (match_operand:HI 4 "arith11_operand" "0,rL")))]
3709 mov%c1\t%x2, %4, %0"
3710 [(set_attr "type" "cmove")])
3712 (define_insn "*movsi_cc_sp64"
3713 [(set (match_operand:SI 0 "register_operand" "=r,r")
3714 (if_then_else:SI (match_operator 1 "comparison_operator"
3715 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3717 (match_operand:SI 3 "arith11_operand" "rL,0")
3718 (match_operand:SI 4 "arith11_operand" "0,rL")))]
3722 mov%c1\t%x2, %4, %0"
3723 [(set_attr "type" "cmove")])
3725 ;; ??? The constraints of operands 3,4 need work.
3726 (define_insn "*movdi_cc_sp64"
3727 [(set (match_operand:DI 0 "register_operand" "=r,r")
3728 (if_then_else:DI (match_operator 1 "comparison_operator"
3729 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3731 (match_operand:DI 3 "arith11_double_operand" "rLH,0")
3732 (match_operand:DI 4 "arith11_double_operand" "0,rLH")))]
3736 mov%c1\t%x2, %4, %0"
3737 [(set_attr "type" "cmove")])
3739 (define_insn "*movdi_cc_sp64_trunc"
3740 [(set (match_operand:SI 0 "register_operand" "=r,r")
3741 (if_then_else:SI (match_operator 1 "comparison_operator"
3742 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3744 (match_operand:SI 3 "arith11_double_operand" "rLH,0")
3745 (match_operand:SI 4 "arith11_double_operand" "0,rLH")))]
3749 mov%c1\t%x2, %4, %0"
3750 [(set_attr "type" "cmove")])
3752 (define_insn "*movsf_cc_sp64"
3753 [(set (match_operand:SF 0 "register_operand" "=f,f")
3754 (if_then_else:SF (match_operator 1 "comparison_operator"
3755 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3757 (match_operand:SF 3 "register_operand" "f,0")
3758 (match_operand:SF 4 "register_operand" "0,f")))]
3759 "TARGET_V9 && TARGET_FPU"
3761 fmovs%C1\t%x2, %3, %0
3762 fmovs%c1\t%x2, %4, %0"
3763 [(set_attr "type" "fpcmove")])
3765 (define_insn "movdf_cc_sp64"
3766 [(set (match_operand:DF 0 "register_operand" "=e,e")
3767 (if_then_else:DF (match_operator 1 "comparison_operator"
3768 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3770 (match_operand:DF 3 "register_operand" "e,0")
3771 (match_operand:DF 4 "register_operand" "0,e")))]
3772 "TARGET_V9 && TARGET_FPU"
3774 fmovd%C1\t%x2, %3, %0
3775 fmovd%c1\t%x2, %4, %0"
3776 [(set_attr "type" "fpcmove")
3777 (set_attr "fptype" "double")])
3779 (define_insn "*movtf_cc_hq_sp64"
3780 [(set (match_operand:TF 0 "register_operand" "=e,e")
3781 (if_then_else:TF (match_operator 1 "comparison_operator"
3782 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3784 (match_operand:TF 3 "register_operand" "e,0")
3785 (match_operand:TF 4 "register_operand" "0,e")))]
3786 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
3788 fmovq%C1\t%x2, %3, %0
3789 fmovq%c1\t%x2, %4, %0"
3790 [(set_attr "type" "fpcmove")])
3792 (define_insn_and_split "*movtf_cc_sp64"
3793 [(set (match_operand:TF 0 "register_operand" "=e,e")
3794 (if_then_else:TF (match_operator 1 "comparison_operator"
3795 [(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
3797 (match_operand:TF 3 "register_operand" "e,0")
3798 (match_operand:TF 4 "register_operand" "0,e")))]
3799 "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
3801 "&& reload_completed"
3802 [(clobber (const_int 0))]
3804 rtx set_dest = operands[0];
3805 rtx set_srca = operands[3];
3806 rtx set_srcb = operands[4];
3807 int third = rtx_equal_p (set_dest, set_srca);
3809 rtx srca1, srca2, srcb1, srcb2;
3811 dest1 = gen_df_reg (set_dest, 0);
3812 dest2 = gen_df_reg (set_dest, 1);
3813 srca1 = gen_df_reg (set_srca, 0);
3814 srca2 = gen_df_reg (set_srca, 1);
3815 srcb1 = gen_df_reg (set_srcb, 0);
3816 srcb2 = gen_df_reg (set_srcb, 1);
3818 /* Now emit using the real source and destination we found, swapping
3819 the order if we detect overlap. */
3820 if ((third && reg_overlap_mentioned_p (dest1, srcb2))
3821 || (!third && reg_overlap_mentioned_p (dest1, srca2)))
3823 emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
3824 emit_insn (gen_movdf_cc_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
3828 emit_insn (gen_movdf_cc_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
3829 emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
3833 [(set_attr "length" "2")])
3835 (define_insn "*movqi_cc_reg_sp64"
3836 [(set (match_operand:QI 0 "register_operand" "=r,r")
3837 (if_then_else:QI (match_operator 1 "v9_regcmp_op"
3838 [(match_operand:DI 2 "register_operand" "r,r")
3840 (match_operand:QI 3 "arith10_operand" "rM,0")
3841 (match_operand:QI 4 "arith10_operand" "0,rM")))]
3844 movr%D1\t%2, %r3, %0
3845 movr%d1\t%2, %r4, %0"
3846 [(set_attr "type" "cmove")])
3848 (define_insn "*movhi_cc_reg_sp64"
3849 [(set (match_operand:HI 0 "register_operand" "=r,r")
3850 (if_then_else:HI (match_operator 1 "v9_regcmp_op"
3851 [(match_operand:DI 2 "register_operand" "r,r")
3853 (match_operand:HI 3 "arith10_operand" "rM,0")
3854 (match_operand:HI 4 "arith10_operand" "0,rM")))]
3857 movr%D1\t%2, %r3, %0
3858 movr%d1\t%2, %r4, %0"
3859 [(set_attr "type" "cmove")])
3861 (define_insn "*movsi_cc_reg_sp64"
3862 [(set (match_operand:SI 0 "register_operand" "=r,r")
3863 (if_then_else:SI (match_operator 1 "v9_regcmp_op"
3864 [(match_operand:DI 2 "register_operand" "r,r")
3866 (match_operand:SI 3 "arith10_operand" "rM,0")
3867 (match_operand:SI 4 "arith10_operand" "0,rM")))]
3870 movr%D1\t%2, %r3, %0
3871 movr%d1\t%2, %r4, %0"
3872 [(set_attr "type" "cmove")])
3874 ;; ??? The constraints of operands 3,4 need work.
3875 (define_insn "*movdi_cc_reg_sp64"
3876 [(set (match_operand:DI 0 "register_operand" "=r,r")
3877 (if_then_else:DI (match_operator 1 "v9_regcmp_op"
3878 [(match_operand:DI 2 "register_operand" "r,r")
3880 (match_operand:DI 3 "arith10_double_operand" "rMH,0")
3881 (match_operand:DI 4 "arith10_double_operand" "0,rMH")))]
3884 movr%D1\t%2, %r3, %0
3885 movr%d1\t%2, %r4, %0"
3886 [(set_attr "type" "cmove")])
3888 (define_insn "*movdi_cc_reg_sp64_trunc"
3889 [(set (match_operand:SI 0 "register_operand" "=r,r")
3890 (if_then_else:SI (match_operator 1 "v9_regcmp_op"
3891 [(match_operand:DI 2 "register_operand" "r,r")
3893 (match_operand:SI 3 "arith10_double_operand" "rMH,0")
3894 (match_operand:SI 4 "arith10_double_operand" "0,rMH")))]
3897 movr%D1\t%2, %r3, %0
3898 movr%d1\t%2, %r4, %0"
3899 [(set_attr "type" "cmove")])
3901 (define_insn "*movsf_cc_reg_sp64"
3902 [(set (match_operand:SF 0 "register_operand" "=f,f")
3903 (if_then_else:SF (match_operator 1 "v9_regcmp_op"
3904 [(match_operand:DI 2 "register_operand" "r,r")
3906 (match_operand:SF 3 "register_operand" "f,0")
3907 (match_operand:SF 4 "register_operand" "0,f")))]
3908 "TARGET_ARCH64 && TARGET_FPU"
3910 fmovrs%D1\t%2, %3, %0
3911 fmovrs%d1\t%2, %4, %0"
3912 [(set_attr "type" "fpcrmove")])
3914 (define_insn "movdf_cc_reg_sp64"
3915 [(set (match_operand:DF 0 "register_operand" "=e,e")
3916 (if_then_else:DF (match_operator 1 "v9_regcmp_op"
3917 [(match_operand:DI 2 "register_operand" "r,r")
3919 (match_operand:DF 3 "register_operand" "e,0")
3920 (match_operand:DF 4 "register_operand" "0,e")))]
3921 "TARGET_ARCH64 && TARGET_FPU"
3923 fmovrd%D1\t%2, %3, %0
3924 fmovrd%d1\t%2, %4, %0"
3925 [(set_attr "type" "fpcrmove")
3926 (set_attr "fptype" "double")])
3928 (define_insn "*movtf_cc_reg_hq_sp64"
3929 [(set (match_operand:TF 0 "register_operand" "=e,e")
3930 (if_then_else:TF (match_operator 1 "v9_regcmp_op"
3931 [(match_operand:DI 2 "register_operand" "r,r")
3933 (match_operand:TF 3 "register_operand" "e,0")
3934 (match_operand:TF 4 "register_operand" "0,e")))]
3935 "TARGET_ARCH64 && TARGET_FPU && TARGET_HARD_QUAD"
3937 fmovrq%D1\t%2, %3, %0
3938 fmovrq%d1\t%2, %4, %0"
3939 [(set_attr "type" "fpcrmove")])
3941 (define_insn_and_split "*movtf_cc_reg_sp64"
3942 [(set (match_operand:TF 0 "register_operand" "=e,e")
3943 (if_then_else:TF (match_operator 1 "v9_regcmp_op"
3944 [(match_operand:DI 2 "register_operand" "r,r")
3946 (match_operand:TF 3 "register_operand" "e,0")
3947 (match_operand:TF 4 "register_operand" "0,e")))]
3948 "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD"
3950 "&& reload_completed"
3951 [(clobber (const_int 0))]
3953 rtx set_dest = operands[0];
3954 rtx set_srca = operands[3];
3955 rtx set_srcb = operands[4];
3956 int third = rtx_equal_p (set_dest, set_srca);
3958 rtx srca1, srca2, srcb1, srcb2;
3960 dest1 = gen_df_reg (set_dest, 0);
3961 dest2 = gen_df_reg (set_dest, 1);
3962 srca1 = gen_df_reg (set_srca, 0);
3963 srca2 = gen_df_reg (set_srca, 1);
3964 srcb1 = gen_df_reg (set_srcb, 0);
3965 srcb2 = gen_df_reg (set_srcb, 1);
3967 /* Now emit using the real source and destination we found, swapping
3968 the order if we detect overlap. */
3969 if ((third && reg_overlap_mentioned_p (dest1, srcb2))
3970 || (!third && reg_overlap_mentioned_p (dest1, srca2)))
3972 emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
3973 emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
3977 emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, srcb1));
3978 emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2));
3982 [(set_attr "length" "2")])
3985 ;;- zero extension instructions
3987 ;; These patterns originally accepted general_operands, however, slightly
3988 ;; better code is generated by only accepting register_operands, and then
3989 ;; letting combine generate the ldu[hb] insns.
3991 (define_expand "zero_extendhisi2"
3992 [(set (match_operand:SI 0 "register_operand" "")
3993 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
3996 rtx temp = gen_reg_rtx (SImode);
3997 rtx shift_16 = GEN_INT (16);
3998 int op1_subbyte = 0;
4000 if (GET_CODE (operand1) == SUBREG)
4002 op1_subbyte = SUBREG_BYTE (operand1);
4003 op1_subbyte /= GET_MODE_SIZE (SImode);
4004 op1_subbyte *= GET_MODE_SIZE (SImode);
4005 operand1 = XEXP (operand1, 0);
4008 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
4010 emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
4014 (define_insn "*zero_extendhisi2_insn"
4015 [(set (match_operand:SI 0 "register_operand" "=r")
4016 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
4019 [(set_attr "type" "load")
4020 (set_attr "us3load_type" "3cycle")])
4022 (define_expand "zero_extendqihi2"
4023 [(set (match_operand:HI 0 "register_operand" "")
4024 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4028 (define_insn "*zero_extendqihi2_insn"
4029 [(set (match_operand:HI 0 "register_operand" "=r,r")
4030 (zero_extend:HI (match_operand:QI 1 "input_operand" "r,m")))]
4031 "GET_CODE (operands[1]) != CONST_INT"
4035 [(set_attr "type" "*,load")
4036 (set_attr "us3load_type" "*,3cycle")])
4038 (define_expand "zero_extendqisi2"
4039 [(set (match_operand:SI 0 "register_operand" "")
4040 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
4044 (define_insn "*zero_extendqisi2_insn"
4045 [(set (match_operand:SI 0 "register_operand" "=r,r")
4046 (zero_extend:SI (match_operand:QI 1 "input_operand" "r,m")))]
4047 "GET_CODE (operands[1]) != CONST_INT"
4051 [(set_attr "type" "*,load")
4052 (set_attr "us3load_type" "*,3cycle")])
4054 (define_expand "zero_extendqidi2"
4055 [(set (match_operand:DI 0 "register_operand" "")
4056 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
4060 (define_insn "*zero_extendqidi2_insn"
4061 [(set (match_operand:DI 0 "register_operand" "=r,r")
4062 (zero_extend:DI (match_operand:QI 1 "input_operand" "r,m")))]
4063 "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
4067 [(set_attr "type" "*,load")
4068 (set_attr "us3load_type" "*,3cycle")])
4070 (define_expand "zero_extendhidi2"
4071 [(set (match_operand:DI 0 "register_operand" "")
4072 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
4075 rtx temp = gen_reg_rtx (DImode);
4076 rtx shift_48 = GEN_INT (48);
4077 int op1_subbyte = 0;
4079 if (GET_CODE (operand1) == SUBREG)
4081 op1_subbyte = SUBREG_BYTE (operand1);
4082 op1_subbyte /= GET_MODE_SIZE (DImode);
4083 op1_subbyte *= GET_MODE_SIZE (DImode);
4084 operand1 = XEXP (operand1, 0);
4087 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
4089 emit_insn (gen_lshrdi3 (operand0, temp, shift_48));
4093 (define_insn "*zero_extendhidi2_insn"
4094 [(set (match_operand:DI 0 "register_operand" "=r")
4095 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
4098 [(set_attr "type" "load")
4099 (set_attr "us3load_type" "3cycle")])
4102 ;; ??? Write truncdisi pattern using sra?
4104 (define_expand "zero_extendsidi2"
4105 [(set (match_operand:DI 0 "register_operand" "")
4106 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
4110 (define_insn "*zero_extendsidi2_insn_sp64"
4111 [(set (match_operand:DI 0 "register_operand" "=r,r")
4112 (zero_extend:DI (match_operand:SI 1 "input_operand" "r,m")))]
4113 "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
4117 [(set_attr "type" "shift,load")])
4119 (define_insn_and_split "*zero_extendsidi2_insn_sp32"
4120 [(set (match_operand:DI 0 "register_operand" "=r")
4121 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4124 "&& reload_completed"
4125 [(set (match_dup 2) (match_dup 3))
4126 (set (match_dup 4) (match_dup 5))]
4130 dest1 = gen_highpart (SImode, operands[0]);
4131 dest2 = gen_lowpart (SImode, operands[0]);
4133 /* Swap the order in case of overlap. */
4134 if (REGNO (dest1) == REGNO (operands[1]))
4136 operands[2] = dest2;
4137 operands[3] = operands[1];
4138 operands[4] = dest1;
4139 operands[5] = const0_rtx;
4143 operands[2] = dest1;
4144 operands[3] = const0_rtx;
4145 operands[4] = dest2;
4146 operands[5] = operands[1];
4149 [(set_attr "length" "2")])
4151 ;; Simplify comparisons of extended values.
4153 (define_insn "*cmp_zero_extendqisi2"
4155 (compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r"))
4158 "andcc\t%0, 0xff, %%g0"
4159 [(set_attr "type" "compare")])
4161 (define_insn "*cmp_zero_qi"
4163 (compare:CC (match_operand:QI 0 "register_operand" "r")
4166 "andcc\t%0, 0xff, %%g0"
4167 [(set_attr "type" "compare")])
4169 (define_insn "*cmp_zero_extendqisi2_set"
4171 (compare:CC (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
4173 (set (match_operand:SI 0 "register_operand" "=r")
4174 (zero_extend:SI (match_dup 1)))]
4176 "andcc\t%1, 0xff, %0"
4177 [(set_attr "type" "compare")])
4179 (define_insn "*cmp_zero_extendqisi2_andcc_set"
4181 (compare:CC (and:SI (match_operand:SI 1 "register_operand" "r")
4184 (set (match_operand:SI 0 "register_operand" "=r")
4185 (zero_extend:SI (subreg:QI (match_dup 1) 0)))]
4187 "andcc\t%1, 0xff, %0"
4188 [(set_attr "type" "compare")])
4190 (define_insn "*cmp_zero_extendqidi2"
4192 (compare:CCX (zero_extend:DI (match_operand:QI 0 "register_operand" "r"))
4195 "andcc\t%0, 0xff, %%g0"
4196 [(set_attr "type" "compare")])
4198 (define_insn "*cmp_zero_qi_sp64"
4200 (compare:CCX (match_operand:QI 0 "register_operand" "r")
4203 "andcc\t%0, 0xff, %%g0"
4204 [(set_attr "type" "compare")])
4206 (define_insn "*cmp_zero_extendqidi2_set"
4208 (compare:CCX (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
4210 (set (match_operand:DI 0 "register_operand" "=r")
4211 (zero_extend:DI (match_dup 1)))]
4213 "andcc\t%1, 0xff, %0"
4214 [(set_attr "type" "compare")])
4216 (define_insn "*cmp_zero_extendqidi2_andcc_set"
4218 (compare:CCX (and:DI (match_operand:DI 1 "register_operand" "r")
4221 (set (match_operand:DI 0 "register_operand" "=r")
4222 (zero_extend:DI (subreg:QI (match_dup 1) 0)))]
4224 "andcc\t%1, 0xff, %0"
4225 [(set_attr "type" "compare")])
4227 ;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare.
4229 (define_insn "*cmp_siqi_trunc"
4231 (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 3)
4234 "andcc\t%0, 0xff, %%g0"
4235 [(set_attr "type" "compare")])
4237 (define_insn "*cmp_siqi_trunc_set"
4239 (compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 3)
4241 (set (match_operand:QI 0 "register_operand" "=r")
4242 (subreg:QI (match_dup 1) 3))]
4244 "andcc\t%1, 0xff, %0"
4245 [(set_attr "type" "compare")])
4247 (define_insn "*cmp_diqi_trunc"
4249 (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 7)
4252 "andcc\t%0, 0xff, %%g0"
4253 [(set_attr "type" "compare")])
4255 (define_insn "*cmp_diqi_trunc_set"
4257 (compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 7)
4259 (set (match_operand:QI 0 "register_operand" "=r")
4260 (subreg:QI (match_dup 1) 7))]
4262 "andcc\t%1, 0xff, %0"
4263 [(set_attr "type" "compare")])
4265 ;;- sign extension instructions
4267 ;; These patterns originally accepted general_operands, however, slightly
4268 ;; better code is generated by only accepting register_operands, and then
4269 ;; letting combine generate the lds[hb] insns.
4271 (define_expand "extendhisi2"
4272 [(set (match_operand:SI 0 "register_operand" "")
4273 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
4276 rtx temp = gen_reg_rtx (SImode);
4277 rtx shift_16 = GEN_INT (16);
4278 int op1_subbyte = 0;
4280 if (GET_CODE (operand1) == SUBREG)
4282 op1_subbyte = SUBREG_BYTE (operand1);
4283 op1_subbyte /= GET_MODE_SIZE (SImode);
4284 op1_subbyte *= GET_MODE_SIZE (SImode);
4285 operand1 = XEXP (operand1, 0);
4288 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
4290 emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
4294 (define_insn "*sign_extendhisi2_insn"
4295 [(set (match_operand:SI 0 "register_operand" "=r")
4296 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
4299 [(set_attr "type" "sload")
4300 (set_attr "us3load_type" "3cycle")])
4302 (define_expand "extendqihi2"
4303 [(set (match_operand:HI 0 "register_operand" "")
4304 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
4307 rtx temp = gen_reg_rtx (SImode);
4308 rtx shift_24 = GEN_INT (24);
4309 int op1_subbyte = 0;
4310 int op0_subbyte = 0;
4312 if (GET_CODE (operand1) == SUBREG)
4314 op1_subbyte = SUBREG_BYTE (operand1);
4315 op1_subbyte /= GET_MODE_SIZE (SImode);
4316 op1_subbyte *= GET_MODE_SIZE (SImode);
4317 operand1 = XEXP (operand1, 0);
4319 if (GET_CODE (operand0) == SUBREG)
4321 op0_subbyte = SUBREG_BYTE (operand0);
4322 op0_subbyte /= GET_MODE_SIZE (SImode);
4323 op0_subbyte *= GET_MODE_SIZE (SImode);
4324 operand0 = XEXP (operand0, 0);
4326 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
4328 if (GET_MODE (operand0) != SImode)
4329 operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subbyte);
4330 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
4334 (define_insn "*sign_extendqihi2_insn"
4335 [(set (match_operand:HI 0 "register_operand" "=r")
4336 (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
4339 [(set_attr "type" "sload")
4340 (set_attr "us3load_type" "3cycle")])
4342 (define_expand "extendqisi2"
4343 [(set (match_operand:SI 0 "register_operand" "")
4344 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
4347 rtx temp = gen_reg_rtx (SImode);
4348 rtx shift_24 = GEN_INT (24);
4349 int op1_subbyte = 0;
4351 if (GET_CODE (operand1) == SUBREG)
4353 op1_subbyte = SUBREG_BYTE (operand1);
4354 op1_subbyte /= GET_MODE_SIZE (SImode);
4355 op1_subbyte *= GET_MODE_SIZE (SImode);
4356 operand1 = XEXP (operand1, 0);
4359 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
4361 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
4365 (define_insn "*sign_extendqisi2_insn"
4366 [(set (match_operand:SI 0 "register_operand" "=r")
4367 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
4370 [(set_attr "type" "sload")
4371 (set_attr "us3load_type" "3cycle")])
4373 (define_expand "extendqidi2"
4374 [(set (match_operand:DI 0 "register_operand" "")
4375 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
4378 rtx temp = gen_reg_rtx (DImode);
4379 rtx shift_56 = GEN_INT (56);
4380 int op1_subbyte = 0;
4382 if (GET_CODE (operand1) == SUBREG)
4384 op1_subbyte = SUBREG_BYTE (operand1);
4385 op1_subbyte /= GET_MODE_SIZE (DImode);
4386 op1_subbyte *= GET_MODE_SIZE (DImode);
4387 operand1 = XEXP (operand1, 0);
4390 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
4392 emit_insn (gen_ashrdi3 (operand0, temp, shift_56));
4396 (define_insn "*sign_extendqidi2_insn"
4397 [(set (match_operand:DI 0 "register_operand" "=r")
4398 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
4401 [(set_attr "type" "sload")
4402 (set_attr "us3load_type" "3cycle")])
4404 (define_expand "extendhidi2"
4405 [(set (match_operand:DI 0 "register_operand" "")
4406 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
4409 rtx temp = gen_reg_rtx (DImode);
4410 rtx shift_48 = GEN_INT (48);
4411 int op1_subbyte = 0;
4413 if (GET_CODE (operand1) == SUBREG)
4415 op1_subbyte = SUBREG_BYTE (operand1);
4416 op1_subbyte /= GET_MODE_SIZE (DImode);
4417 op1_subbyte *= GET_MODE_SIZE (DImode);
4418 operand1 = XEXP (operand1, 0);
4421 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
4423 emit_insn (gen_ashrdi3 (operand0, temp, shift_48));
4427 (define_insn "*sign_extendhidi2_insn"
4428 [(set (match_operand:DI 0 "register_operand" "=r")
4429 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
4432 [(set_attr "type" "sload")
4433 (set_attr "us3load_type" "3cycle")])
4435 (define_expand "extendsidi2"
4436 [(set (match_operand:DI 0 "register_operand" "")
4437 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))]
4441 (define_insn "*sign_extendsidi2_insn"
4442 [(set (match_operand:DI 0 "register_operand" "=r,r")
4443 (sign_extend:DI (match_operand:SI 1 "input_operand" "r,m")))]
4448 [(set_attr "type" "shift,sload")
4449 (set_attr "us3load_type" "*,3cycle")])
4451 ;; Special pattern for optimizing bit-field compares. This is needed
4452 ;; because combine uses this as a canonical form.
4454 (define_insn "*cmp_zero_extract"
4457 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
4458 (match_operand:SI 1 "small_int_or_double" "n")
4459 (match_operand:SI 2 "small_int_or_double" "n"))
4461 "(GET_CODE (operands[2]) == CONST_INT
4462 && INTVAL (operands[2]) > 19)
4463 || (GET_CODE (operands[2]) == CONST_DOUBLE
4464 && CONST_DOUBLE_LOW (operands[2]) > 19)"
4466 int len = (GET_CODE (operands[1]) == CONST_INT
4467 ? INTVAL (operands[1])
4468 : CONST_DOUBLE_LOW (operands[1]));
4470 (GET_CODE (operands[2]) == CONST_INT
4471 ? INTVAL (operands[2])
4472 : CONST_DOUBLE_LOW (operands[2])) - len;
4473 HOST_WIDE_INT mask = ((1 << len) - 1) << pos;
4475 operands[1] = GEN_INT (mask);
4476 return "andcc\t%0, %1, %%g0";
4478 [(set_attr "type" "compare")])
4480 (define_insn "*cmp_zero_extract_sp64"
4483 (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
4484 (match_operand:SI 1 "small_int_or_double" "n")
4485 (match_operand:SI 2 "small_int_or_double" "n"))
4488 && ((GET_CODE (operands[2]) == CONST_INT
4489 && INTVAL (operands[2]) > 51)
4490 || (GET_CODE (operands[2]) == CONST_DOUBLE
4491 && CONST_DOUBLE_LOW (operands[2]) > 51))"
4493 int len = (GET_CODE (operands[1]) == CONST_INT
4494 ? INTVAL (operands[1])
4495 : CONST_DOUBLE_LOW (operands[1]));
4497 (GET_CODE (operands[2]) == CONST_INT
4498 ? INTVAL (operands[2])
4499 : CONST_DOUBLE_LOW (operands[2])) - len;
4500 HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
4502 operands[1] = GEN_INT (mask);
4503 return "andcc\t%0, %1, %%g0";
4505 [(set_attr "type" "compare")])
4507 ;; Conversions between float, double and long double.
4509 (define_insn "extendsfdf2"
4510 [(set (match_operand:DF 0 "register_operand" "=e")
4512 (match_operand:SF 1 "register_operand" "f")))]
4515 [(set_attr "type" "fp")
4516 (set_attr "fptype" "double")])
4518 (define_expand "extendsftf2"
4519 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4521 (match_operand:SF 1 "register_operand" "")))]
4522 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4523 "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;")
4525 (define_insn "*extendsftf2_hq"
4526 [(set (match_operand:TF 0 "register_operand" "=e")
4528 (match_operand:SF 1 "register_operand" "f")))]
4529 "TARGET_FPU && TARGET_HARD_QUAD"
4531 [(set_attr "type" "fp")])
4533 (define_expand "extenddftf2"
4534 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4536 (match_operand:DF 1 "register_operand" "")))]
4537 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4538 "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;")
4540 (define_insn "*extenddftf2_hq"
4541 [(set (match_operand:TF 0 "register_operand" "=e")
4543 (match_operand:DF 1 "register_operand" "e")))]
4544 "TARGET_FPU && TARGET_HARD_QUAD"
4546 [(set_attr "type" "fp")])
4548 (define_insn "truncdfsf2"
4549 [(set (match_operand:SF 0 "register_operand" "=f")
4551 (match_operand:DF 1 "register_operand" "e")))]
4554 [(set_attr "type" "fp")
4555 (set_attr "fptype" "double")])
4557 (define_expand "trunctfsf2"
4558 [(set (match_operand:SF 0 "register_operand" "")
4560 (match_operand:TF 1 "general_operand" "")))]
4561 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4562 "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;")
4564 (define_insn "*trunctfsf2_hq"
4565 [(set (match_operand:SF 0 "register_operand" "=f")
4567 (match_operand:TF 1 "register_operand" "e")))]
4568 "TARGET_FPU && TARGET_HARD_QUAD"
4570 [(set_attr "type" "fp")])
4572 (define_expand "trunctfdf2"
4573 [(set (match_operand:DF 0 "register_operand" "")
4575 (match_operand:TF 1 "general_operand" "")))]
4576 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4577 "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;")
4579 (define_insn "*trunctfdf2_hq"
4580 [(set (match_operand:DF 0 "register_operand" "=e")
4582 (match_operand:TF 1 "register_operand" "e")))]
4583 "TARGET_FPU && TARGET_HARD_QUAD"
4585 [(set_attr "type" "fp")])
4587 ;; Conversion between fixed point and floating point.
4589 (define_insn "floatsisf2"
4590 [(set (match_operand:SF 0 "register_operand" "=f")
4591 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4594 [(set_attr "type" "fp")
4595 (set_attr "fptype" "double")])
4597 (define_insn "floatsidf2"
4598 [(set (match_operand:DF 0 "register_operand" "=e")
4599 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4602 [(set_attr "type" "fp")
4603 (set_attr "fptype" "double")])
4605 (define_expand "floatsitf2"
4606 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4607 (float:TF (match_operand:SI 1 "register_operand" "")))]
4608 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4609 "emit_tfmode_cvt (FLOAT, operands); DONE;")
4611 (define_insn "*floatsitf2_hq"
4612 [(set (match_operand:TF 0 "register_operand" "=e")
4613 (float:TF (match_operand:SI 1 "register_operand" "f")))]
4614 "TARGET_FPU && TARGET_HARD_QUAD"
4616 [(set_attr "type" "fp")])
4618 (define_expand "floatunssitf2"
4619 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4620 (unsigned_float:TF (match_operand:SI 1 "register_operand" "")))]
4621 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
4622 "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;")
4624 ;; Now the same for 64 bit sources.
4626 (define_insn "floatdisf2"
4627 [(set (match_operand:SF 0 "register_operand" "=f")
4628 (float:SF (match_operand:DI 1 "register_operand" "e")))]
4629 "TARGET_V9 && TARGET_FPU"
4631 [(set_attr "type" "fp")
4632 (set_attr "fptype" "double")])
4634 (define_expand "floatunsdisf2"
4635 [(use (match_operand:SF 0 "register_operand" ""))
4636 (use (match_operand:DI 1 "register_operand" ""))]
4637 "TARGET_ARCH64 && TARGET_FPU"
4638 "sparc_emit_floatunsdi (operands); DONE;")
4640 (define_insn "floatdidf2"
4641 [(set (match_operand:DF 0 "register_operand" "=e")
4642 (float:DF (match_operand:DI 1 "register_operand" "e")))]
4643 "TARGET_V9 && TARGET_FPU"
4645 [(set_attr "type" "fp")
4646 (set_attr "fptype" "double")])
4648 (define_expand "floatunsdidf2"
4649 [(use (match_operand:DF 0 "register_operand" ""))
4650 (use (match_operand:DI 1 "register_operand" ""))]
4651 "TARGET_ARCH64 && TARGET_FPU"
4652 "sparc_emit_floatunsdi (operands); DONE;")
4654 (define_expand "floatditf2"
4655 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4656 (float:TF (match_operand:DI 1 "register_operand" "")))]
4657 "TARGET_FPU && TARGET_V9 && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4658 "emit_tfmode_cvt (FLOAT, operands); DONE;")
4660 (define_insn "*floatditf2_hq"
4661 [(set (match_operand:TF 0 "register_operand" "=e")
4662 (float:TF (match_operand:DI 1 "register_operand" "e")))]
4663 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
4665 [(set_attr "type" "fp")])
4667 (define_expand "floatunsditf2"
4668 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4669 (unsigned_float:TF (match_operand:DI 1 "register_operand" "")))]
4670 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
4671 "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;")
4673 ;; Convert a float to an actual integer.
4674 ;; Truncation is performed as part of the conversion.
4676 (define_insn "fix_truncsfsi2"
4677 [(set (match_operand:SI 0 "register_operand" "=f")
4678 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4681 [(set_attr "type" "fp")
4682 (set_attr "fptype" "double")])
4684 (define_insn "fix_truncdfsi2"
4685 [(set (match_operand:SI 0 "register_operand" "=f")
4686 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
4689 [(set_attr "type" "fp")
4690 (set_attr "fptype" "double")])
4692 (define_expand "fix_trunctfsi2"
4693 [(set (match_operand:SI 0 "register_operand" "")
4694 (fix:SI (match_operand:TF 1 "general_operand" "")))]
4695 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4696 "emit_tfmode_cvt (FIX, operands); DONE;")
4698 (define_insn "*fix_trunctfsi2_hq"
4699 [(set (match_operand:SI 0 "register_operand" "=f")
4700 (fix:SI (match_operand:TF 1 "register_operand" "e")))]
4701 "TARGET_FPU && TARGET_HARD_QUAD"
4703 [(set_attr "type" "fp")])
4705 (define_expand "fixuns_trunctfsi2"
4706 [(set (match_operand:SI 0 "register_operand" "")
4707 (unsigned_fix:SI (match_operand:TF 1 "general_operand" "")))]
4708 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
4709 "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
4711 ;; Now the same, for V9 targets
4713 (define_insn "fix_truncsfdi2"
4714 [(set (match_operand:DI 0 "register_operand" "=e")
4715 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4716 "TARGET_V9 && TARGET_FPU"
4718 [(set_attr "type" "fp")
4719 (set_attr "fptype" "double")])
4721 (define_insn "fix_truncdfdi2"
4722 [(set (match_operand:DI 0 "register_operand" "=e")
4723 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
4724 "TARGET_V9 && TARGET_FPU"
4726 [(set_attr "type" "fp")
4727 (set_attr "fptype" "double")])
4729 (define_expand "fix_trunctfdi2"
4730 [(set (match_operand:DI 0 "register_operand" "")
4731 (fix:DI (match_operand:TF 1 "general_operand" "")))]
4732 "TARGET_V9 && TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
4733 "emit_tfmode_cvt (FIX, operands); DONE;")
4735 (define_insn "*fix_trunctfdi2_hq"
4736 [(set (match_operand:DI 0 "register_operand" "=e")
4737 (fix:DI (match_operand:TF 1 "register_operand" "e")))]
4738 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
4740 [(set_attr "type" "fp")])
4742 (define_expand "fixuns_trunctfdi2"
4743 [(set (match_operand:DI 0 "register_operand" "")
4744 (unsigned_fix:DI (match_operand:TF 1 "general_operand" "")))]
4745 "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD"
4746 "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
4748 ;;- arithmetic instructions
4750 (define_expand "adddi3"
4751 [(set (match_operand:DI 0 "register_operand" "")
4752 (plus:DI (match_operand:DI 1 "register_operand" "")
4753 (match_operand:DI 2 "arith_double_add_operand" "")))]
4756 if (! TARGET_ARCH64)
4758 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
4759 gen_rtx_SET (VOIDmode, operands[0],
4760 gen_rtx_PLUS (DImode, operands[1],
4762 gen_rtx_CLOBBER (VOIDmode,
4763 gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
4768 (define_insn_and_split "adddi3_insn_sp32"
4769 [(set (match_operand:DI 0 "register_operand" "=r")
4770 (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
4771 (match_operand:DI 2 "arith_double_operand" "rHI")))
4772 (clobber (reg:CC 100))]
4775 "&& reload_completed"
4776 [(parallel [(set (reg:CC_NOOV 100)
4777 (compare:CC_NOOV (plus:SI (match_dup 4)
4781 (plus:SI (match_dup 4) (match_dup 5)))])
4783 (plus:SI (plus:SI (match_dup 7)
4785 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4787 operands[3] = gen_lowpart (SImode, operands[0]);
4788 operands[4] = gen_lowpart (SImode, operands[1]);
4789 operands[5] = gen_lowpart (SImode, operands[2]);
4790 operands[6] = gen_highpart (SImode, operands[0]);
4791 operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
4792 #if HOST_BITS_PER_WIDE_INT == 32
4793 if (GET_CODE (operands[2]) == CONST_INT)
4795 if (INTVAL (operands[2]) < 0)
4796 operands[8] = constm1_rtx;
4798 operands[8] = const0_rtx;
4802 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
4804 [(set_attr "length" "2")])
4807 [(set (match_operand:DI 0 "register_operand" "")
4808 (minus:DI (match_operand:DI 1 "arith_double_operand" "")
4809 (match_operand:DI 2 "arith_double_operand" "")))
4810 (clobber (reg:CC 100))]
4811 "! TARGET_ARCH64 && reload_completed"
4812 [(parallel [(set (reg:CC_NOOV 100)
4813 (compare:CC_NOOV (minus:SI (match_dup 4)
4817 (minus:SI (match_dup 4) (match_dup 5)))])
4819 (minus:SI (minus:SI (match_dup 7)
4821 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4823 operands[3] = gen_lowpart (SImode, operands[0]);
4824 operands[4] = gen_lowpart (SImode, operands[1]);
4825 operands[5] = gen_lowpart (SImode, operands[2]);
4826 operands[6] = gen_highpart (SImode, operands[0]);
4827 operands[7] = gen_highpart (SImode, operands[1]);
4828 #if HOST_BITS_PER_WIDE_INT == 32
4829 if (GET_CODE (operands[2]) == CONST_INT)
4831 if (INTVAL (operands[2]) < 0)
4832 operands[8] = constm1_rtx;
4834 operands[8] = const0_rtx;
4838 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
4841 ;; LTU here means "carry set"
4843 [(set (match_operand:SI 0 "register_operand" "=r")
4844 (plus:SI (plus:SI (match_operand:SI 1 "arith_operand" "%r")
4845 (match_operand:SI 2 "arith_operand" "rI"))
4846 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4849 [(set_attr "type" "ialuX")])
4851 (define_insn_and_split "*addx_extend_sp32"
4852 [(set (match_operand:DI 0 "register_operand" "=r")
4853 (zero_extend:DI (plus:SI (plus:SI
4854 (match_operand:SI 1 "reg_or_0_operand" "%rJ")
4855 (match_operand:SI 2 "arith_operand" "rI"))
4856 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4859 "&& reload_completed"
4860 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
4861 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
4862 (set (match_dup 4) (const_int 0))]
4863 "operands[3] = gen_lowpart (SImode, operands[0]);
4864 operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);"
4865 [(set_attr "length" "2")])
4867 (define_insn "*addx_extend_sp64"
4868 [(set (match_operand:DI 0 "register_operand" "=r")
4869 (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
4870 (match_operand:SI 2 "arith_operand" "rI"))
4871 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4874 [(set_attr "type" "ialuX")])
4877 [(set (match_operand:SI 0 "register_operand" "=r")
4878 (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
4879 (match_operand:SI 2 "arith_operand" "rI"))
4880 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4883 [(set_attr "type" "ialuX")])
4885 (define_insn "*subx_extend_sp64"
4886 [(set (match_operand:DI 0 "register_operand" "=r")
4887 (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
4888 (match_operand:SI 2 "arith_operand" "rI"))
4889 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4892 [(set_attr "type" "ialuX")])
4894 (define_insn_and_split "*subx_extend"
4895 [(set (match_operand:DI 0 "register_operand" "=r")
4896 (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
4897 (match_operand:SI 2 "arith_operand" "rI"))
4898 (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
4901 "&& reload_completed"
4902 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
4903 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))
4904 (set (match_dup 4) (const_int 0))]
4905 "operands[3] = gen_lowpart (SImode, operands[0]);
4906 operands[4] = gen_highpart (SImode, operands[0]);"
4907 [(set_attr "length" "2")])
4909 (define_insn_and_split ""
4910 [(set (match_operand:DI 0 "register_operand" "=r")
4911 (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4912 (match_operand:DI 2 "register_operand" "r")))
4913 (clobber (reg:CC 100))]
4916 "&& reload_completed"
4917 [(parallel [(set (reg:CC_NOOV 100)
4918 (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1))
4920 (set (match_dup 5) (plus:SI (match_dup 3) (match_dup 1)))])
4922 (plus:SI (plus:SI (match_dup 4) (const_int 0))
4923 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
4924 "operands[3] = gen_lowpart (SImode, operands[2]);
4925 operands[4] = gen_highpart (SImode, operands[2]);
4926 operands[5] = gen_lowpart (SImode, operands[0]);
4927 operands[6] = gen_highpart (SImode, operands[0]);"
4928 [(set_attr "length" "2")])
4930 (define_insn "*adddi3_sp64"
4931 [(set (match_operand:DI 0 "register_operand" "=r,r")
4932 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4933 (match_operand:DI 2 "arith_double_add_operand" "rHI,O")))]
4939 (define_insn "addsi3"
4940 [(set (match_operand:SI 0 "register_operand" "=r,r,d")
4941 (plus:SI (match_operand:SI 1 "register_operand" "%r,r,d")
4942 (match_operand:SI 2 "arith_add_operand" "rI,O,d")))]
4947 fpadd32s\t%1, %2, %0"
4948 [(set_attr "type" "*,*,fp")])
4950 (define_insn "*cmp_cc_plus"
4951 [(set (reg:CC_NOOV 100)
4952 (compare:CC_NOOV (plus:SI (match_operand:SI 0 "arith_operand" "%r")
4953 (match_operand:SI 1 "arith_operand" "rI"))
4956 "addcc\t%0, %1, %%g0"
4957 [(set_attr "type" "compare")])
4959 (define_insn "*cmp_ccx_plus"
4960 [(set (reg:CCX_NOOV 100)
4961 (compare:CCX_NOOV (plus:DI (match_operand:DI 0 "arith_double_operand" "%r")
4962 (match_operand:DI 1 "arith_double_operand" "rHI"))
4965 "addcc\t%0, %1, %%g0"
4966 [(set_attr "type" "compare")])
4968 (define_insn "*cmp_cc_plus_set"
4969 [(set (reg:CC_NOOV 100)
4970 (compare:CC_NOOV (plus:SI (match_operand:SI 1 "arith_operand" "%r")
4971 (match_operand:SI 2 "arith_operand" "rI"))
4973 (set (match_operand:SI 0 "register_operand" "=r")
4974 (plus:SI (match_dup 1) (match_dup 2)))]
4977 [(set_attr "type" "compare")])
4979 (define_insn "*cmp_ccx_plus_set"
4980 [(set (reg:CCX_NOOV 100)
4981 (compare:CCX_NOOV (plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
4982 (match_operand:DI 2 "arith_double_operand" "rHI"))
4984 (set (match_operand:DI 0 "register_operand" "=r")
4985 (plus:DI (match_dup 1) (match_dup 2)))]
4988 [(set_attr "type" "compare")])
4990 (define_expand "subdi3"
4991 [(set (match_operand:DI 0 "register_operand" "")
4992 (minus:DI (match_operand:DI 1 "register_operand" "")
4993 (match_operand:DI 2 "arith_double_add_operand" "")))]
4996 if (! TARGET_ARCH64)
4998 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
4999 gen_rtx_SET (VOIDmode, operands[0],
5000 gen_rtx_MINUS (DImode, operands[1],
5002 gen_rtx_CLOBBER (VOIDmode,
5003 gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
5008 (define_insn_and_split "*subdi3_sp32"
5009 [(set (match_operand:DI 0 "register_operand" "=r")
5010 (minus:DI (match_operand:DI 1 "register_operand" "r")
5011 (match_operand:DI 2 "arith_double_operand" "rHI")))
5012 (clobber (reg:CC 100))]
5015 "&& reload_completed
5016 && (GET_CODE (operands[2]) == CONST_INT
5017 || GET_CODE (operands[2]) == CONST_DOUBLE)"
5018 [(clobber (const_int 0))]
5022 highp = gen_highpart_mode (SImode, DImode, operands[2]);
5023 lowp = gen_lowpart (SImode, operands[2]);
5024 if ((lowp == const0_rtx)
5025 && (operands[0] == operands[1]))
5027 emit_insn (gen_rtx_SET (VOIDmode,
5028 gen_highpart (SImode, operands[0]),
5029 gen_rtx_MINUS (SImode,
5030 gen_highpart_mode (SImode, DImode,
5036 emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]),
5037 gen_lowpart (SImode, operands[1]),
5039 emit_insn (gen_subx (gen_highpart (SImode, operands[0]),
5040 gen_highpart_mode (SImode, DImode, operands[1]),
5045 [(set_attr "length" "2")])
5048 [(set (match_operand:DI 0 "register_operand" "")
5049 (minus:DI (match_operand:DI 1 "register_operand" "")
5050 (match_operand:DI 2 "register_operand" "")))
5051 (clobber (reg:CC 100))]
5053 && reload_completed"
5054 [(clobber (const_int 0))]
5056 emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]),
5057 gen_lowpart (SImode, operands[1]),
5058 gen_lowpart (SImode, operands[2])));
5059 emit_insn (gen_subx (gen_highpart (SImode, operands[0]),
5060 gen_highpart (SImode, operands[1]),
5061 gen_highpart (SImode, operands[2])));
5065 (define_insn_and_split ""
5066 [(set (match_operand:DI 0 "register_operand" "=r")
5067 (minus:DI (match_operand:DI 1 "register_operand" "r")
5068 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))
5069 (clobber (reg:CC 100))]
5072 "&& reload_completed"
5073 [(parallel [(set (reg:CC_NOOV 100)
5074 (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2))
5076 (set (match_dup 5) (minus:SI (match_dup 3) (match_dup 2)))])
5078 (minus:SI (minus:SI (match_dup 4) (const_int 0))
5079 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
5080 "operands[3] = gen_lowpart (SImode, operands[1]);
5081 operands[4] = gen_highpart (SImode, operands[1]);
5082 operands[5] = gen_lowpart (SImode, operands[0]);
5083 operands[6] = gen_highpart (SImode, operands[0]);"
5084 [(set_attr "length" "2")])
5086 (define_insn "*subdi3_sp64"
5087 [(set (match_operand:DI 0 "register_operand" "=r,r")
5088 (minus:DI (match_operand:DI 1 "register_operand" "r,r")
5089 (match_operand:DI 2 "arith_double_add_operand" "rHI,O")))]
5095 (define_insn "subsi3"
5096 [(set (match_operand:SI 0 "register_operand" "=r,r,d")
5097 (minus:SI (match_operand:SI 1 "register_operand" "r,r,d")
5098 (match_operand:SI 2 "arith_add_operand" "rI,O,d")))]
5103 fpsub32s\t%1, %2, %0"
5104 [(set_attr "type" "*,*,fp")])
5106 (define_insn "*cmp_minus_cc"
5107 [(set (reg:CC_NOOV 100)
5108 (compare:CC_NOOV (minus:SI (match_operand:SI 0 "reg_or_0_operand" "rJ")
5109 (match_operand:SI 1 "arith_operand" "rI"))
5112 "subcc\t%r0, %1, %%g0"
5113 [(set_attr "type" "compare")])
5115 (define_insn "*cmp_minus_ccx"
5116 [(set (reg:CCX_NOOV 100)
5117 (compare:CCX_NOOV (minus:DI (match_operand:DI 0 "register_operand" "r")
5118 (match_operand:DI 1 "arith_double_operand" "rHI"))
5121 "subcc\t%0, %1, %%g0"
5122 [(set_attr "type" "compare")])
5124 (define_insn "cmp_minus_cc_set"
5125 [(set (reg:CC_NOOV 100)
5126 (compare:CC_NOOV (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
5127 (match_operand:SI 2 "arith_operand" "rI"))
5129 (set (match_operand:SI 0 "register_operand" "=r")
5130 (minus:SI (match_dup 1) (match_dup 2)))]
5132 "subcc\t%r1, %2, %0"
5133 [(set_attr "type" "compare")])
5135 (define_insn "*cmp_minus_ccx_set"
5136 [(set (reg:CCX_NOOV 100)
5137 (compare:CCX_NOOV (minus:DI (match_operand:DI 1 "register_operand" "r")
5138 (match_operand:DI 2 "arith_double_operand" "rHI"))
5140 (set (match_operand:DI 0 "register_operand" "=r")
5141 (minus:DI (match_dup 1) (match_dup 2)))]
5144 [(set_attr "type" "compare")])
5146 ;; Integer Multiply/Divide.
5148 ;; The 32 bit multiply/divide instructions are deprecated on v9, but at
5149 ;; least in UltraSPARC I, II and IIi it is a win tick-wise.
5151 (define_insn "mulsi3"
5152 [(set (match_operand:SI 0 "register_operand" "=r")
5153 (mult:SI (match_operand:SI 1 "arith_operand" "%r")
5154 (match_operand:SI 2 "arith_operand" "rI")))]
5157 [(set_attr "type" "imul")])
5159 (define_expand "muldi3"
5160 [(set (match_operand:DI 0 "register_operand" "=r")
5161 (mult:DI (match_operand:DI 1 "arith_double_operand" "%r")
5162 (match_operand:DI 2 "arith_double_operand" "rHI")))]
5163 "TARGET_ARCH64 || TARGET_V8PLUS"
5167 emit_insn (gen_muldi3_v8plus (operands[0], operands[1], operands[2]));
5172 (define_insn "*muldi3_sp64"
5173 [(set (match_operand:DI 0 "register_operand" "=r")
5174 (mult:DI (match_operand:DI 1 "arith_double_operand" "%r")
5175 (match_operand:DI 2 "arith_double_operand" "rHI")))]
5178 [(set_attr "type" "imul")])
5180 ;; V8plus wide multiply.
5182 (define_insn "muldi3_v8plus"
5183 [(set (match_operand:DI 0 "register_operand" "=r,h")
5184 (mult:DI (match_operand:DI 1 "arith_double_operand" "%r,0")
5185 (match_operand:DI 2 "arith_double_operand" "rI,rI")))
5186 (clobber (match_scratch:SI 3 "=&h,X"))
5187 (clobber (match_scratch:SI 4 "=&h,X"))]
5190 if (sparc_check_64 (operands[1], insn) <= 0)
5191 output_asm_insn ("srl\t%L1, 0, %L1", operands);
5192 if (which_alternative == 1)
5193 output_asm_insn ("sllx\t%H1, 32, %H1", operands);
5194 if (GET_CODE (operands[2]) == CONST_INT)
5196 if (which_alternative == 1)
5197 return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %2, %L0\;srlx\t%L0, 32, %H0";
5199 return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
5201 else if (rtx_equal_p (operands[1], operands[2]))
5203 if (which_alternative == 1)
5204 return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %H1, %L0\;srlx\t%L0, 32, %H0";
5206 return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %3, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
5208 if (sparc_check_64 (operands[2], insn) <= 0)
5209 output_asm_insn ("srl\t%L2, 0, %L2", operands);
5210 if (which_alternative == 1)
5211 return "or\t%L1, %H1, %H1\n\tsllx\t%H2, 32, %L1\n\tor\t%L2, %L1, %L1\n\tmulx\t%H1, %L1, %L0\;srlx\t%L0, 32, %H0";
5213 return "sllx\t%H1, 32, %3\n\tsllx\t%H2, 32, %4\n\tor\t%L1, %3, %3\n\tor\t%L2, %4, %4\n\tmulx\t%3, %4, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0";
5215 [(set_attr "type" "multi")
5216 (set_attr "length" "9,8")])
5218 (define_insn "*cmp_mul_set"
5220 (compare:CC (mult:SI (match_operand:SI 1 "arith_operand" "%r")
5221 (match_operand:SI 2 "arith_operand" "rI"))
5223 (set (match_operand:SI 0 "register_operand" "=r")
5224 (mult:SI (match_dup 1) (match_dup 2)))]
5225 "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS"
5226 "smulcc\t%1, %2, %0"
5227 [(set_attr "type" "imul")])
5229 (define_expand "mulsidi3"
5230 [(set (match_operand:DI 0 "register_operand" "")
5231 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
5232 (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))))]
5235 if (CONSTANT_P (operands[2]))
5238 emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1],
5240 else if (TARGET_ARCH32)
5241 emit_insn (gen_const_mulsidi3_sp32 (operands[0], operands[1],
5244 emit_insn (gen_const_mulsidi3_sp64 (operands[0], operands[1],
5250 emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2]));
5255 ;; V9 puts the 64 bit product in a 64 bit register. Only out or global
5256 ;; registers can hold 64 bit values in the V8plus environment.
5258 (define_insn "mulsidi3_v8plus"
5259 [(set (match_operand:DI 0 "register_operand" "=h,r")
5260 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5261 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
5262 (clobber (match_scratch:SI 3 "=X,&h"))]
5265 smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
5266 smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
5267 [(set_attr "type" "multi")
5268 (set_attr "length" "2,3")])
5271 (define_insn "const_mulsidi3_v8plus"
5272 [(set (match_operand:DI 0 "register_operand" "=h,r")
5273 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5274 (match_operand:DI 2 "small_int" "I,I")))
5275 (clobber (match_scratch:SI 3 "=X,&h"))]
5278 smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
5279 smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
5280 [(set_attr "type" "multi")
5281 (set_attr "length" "2,3")])
5284 (define_insn "*mulsidi3_sp32"
5285 [(set (match_operand:DI 0 "register_operand" "=r")
5286 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5287 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
5290 return TARGET_SPARCLET
5291 ? "smuld\t%1, %2, %L0"
5292 : "smul\t%1, %2, %L0\n\trd\t%%y, %H0";
5295 (if_then_else (eq_attr "isa" "sparclet")
5296 (const_string "imul") (const_string "multi")))
5297 (set (attr "length")
5298 (if_then_else (eq_attr "isa" "sparclet")
5299 (const_int 1) (const_int 2)))])
5301 (define_insn "*mulsidi3_sp64"
5302 [(set (match_operand:DI 0 "register_operand" "=r")
5303 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5304 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
5305 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5307 [(set_attr "type" "imul")])
5309 ;; Extra pattern, because sign_extend of a constant isn't valid.
5312 (define_insn "const_mulsidi3_sp32"
5313 [(set (match_operand:DI 0 "register_operand" "=r")
5314 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5315 (match_operand:DI 2 "small_int" "I")))]
5318 return TARGET_SPARCLET
5319 ? "smuld\t%1, %2, %L0"
5320 : "smul\t%1, %2, %L0\n\trd\t%%y, %H0";
5323 (if_then_else (eq_attr "isa" "sparclet")
5324 (const_string "imul") (const_string "multi")))
5325 (set (attr "length")
5326 (if_then_else (eq_attr "isa" "sparclet")
5327 (const_int 1) (const_int 2)))])
5329 (define_insn "const_mulsidi3_sp64"
5330 [(set (match_operand:DI 0 "register_operand" "=r")
5331 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5332 (match_operand:DI 2 "small_int" "I")))]
5333 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5335 [(set_attr "type" "imul")])
5337 (define_expand "smulsi3_highpart"
5338 [(set (match_operand:SI 0 "register_operand" "")
5340 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
5341 (sign_extend:DI (match_operand:SI 2 "arith_operand" "")))
5343 "TARGET_HARD_MUL && TARGET_ARCH32"
5345 if (CONSTANT_P (operands[2]))
5349 emit_insn (gen_const_smulsi3_highpart_v8plus (operands[0],
5355 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[1], operands[2]));
5360 emit_insn (gen_smulsi3_highpart_v8plus (operands[0], operands[1],
5361 operands[2], GEN_INT (32)));
5367 (define_insn "smulsi3_highpart_v8plus"
5368 [(set (match_operand:SI 0 "register_operand" "=h,r")
5370 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5371 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
5372 (match_operand:SI 3 "const_int_operand" "i,i"))))
5373 (clobber (match_scratch:SI 4 "=X,&h"))]
5376 smul\t%1, %2, %0\;srlx\t%0, %3, %0
5377 smul\t%1, %2, %4\;srlx\t%4, %3, %0"
5378 [(set_attr "type" "multi")
5379 (set_attr "length" "2")])
5381 ;; The combiner changes TRUNCATE in the previous pattern to SUBREG.
5384 [(set (match_operand:SI 0 "register_operand" "=h,r")
5387 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5388 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
5389 (match_operand:SI 3 "const_int_operand" "i,i"))
5391 (clobber (match_scratch:SI 4 "=X,&h"))]
5394 smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
5395 smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
5396 [(set_attr "type" "multi")
5397 (set_attr "length" "2")])
5400 (define_insn "const_smulsi3_highpart_v8plus"
5401 [(set (match_operand:SI 0 "register_operand" "=h,r")
5403 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5404 (match_operand:DI 2 "small_int" "i,i"))
5405 (match_operand:SI 3 "const_int_operand" "i,i"))))
5406 (clobber (match_scratch:SI 4 "=X,&h"))]
5409 smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
5410 smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
5411 [(set_attr "type" "multi")
5412 (set_attr "length" "2")])
5415 (define_insn "*smulsi3_highpart_sp32"
5416 [(set (match_operand:SI 0 "register_operand" "=r")
5418 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5419 (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
5422 "smul\t%1, %2, %%g0\n\trd\t%%y, %0"
5423 [(set_attr "type" "multi")
5424 (set_attr "length" "2")])
5427 (define_insn "const_smulsi3_highpart"
5428 [(set (match_operand:SI 0 "register_operand" "=r")
5430 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
5431 (match_operand:DI 2 "small_int" "i"))
5434 "smul\t%1, %2, %%g0\n\trd\t%%y, %0"
5435 [(set_attr "type" "multi")
5436 (set_attr "length" "2")])
5438 (define_expand "umulsidi3"
5439 [(set (match_operand:DI 0 "register_operand" "")
5440 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
5441 (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))]
5444 if (CONSTANT_P (operands[2]))
5447 emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1],
5449 else if (TARGET_ARCH32)
5450 emit_insn (gen_const_umulsidi3_sp32 (operands[0], operands[1],
5453 emit_insn (gen_const_umulsidi3_sp64 (operands[0], operands[1],
5459 emit_insn (gen_umulsidi3_v8plus (operands[0], operands[1], operands[2]));
5465 (define_insn "umulsidi3_v8plus"
5466 [(set (match_operand:DI 0 "register_operand" "=h,r")
5467 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5468 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
5469 (clobber (match_scratch:SI 3 "=X,&h"))]
5472 umul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
5473 umul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
5474 [(set_attr "type" "multi")
5475 (set_attr "length" "2,3")])
5478 (define_insn "*umulsidi3_sp32"
5479 [(set (match_operand:DI 0 "register_operand" "=r")
5480 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5481 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
5484 return TARGET_SPARCLET
5485 ? "umuld\t%1, %2, %L0"
5486 : "umul\t%1, %2, %L0\n\trd\t%%y, %H0";
5489 (if_then_else (eq_attr "isa" "sparclet")
5490 (const_string "imul") (const_string "multi")))
5491 (set (attr "length")
5492 (if_then_else (eq_attr "isa" "sparclet")
5493 (const_int 1) (const_int 2)))])
5495 (define_insn "*umulsidi3_sp64"
5496 [(set (match_operand:DI 0 "register_operand" "=r")
5497 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5498 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
5499 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5501 [(set_attr "type" "imul")])
5503 ;; Extra pattern, because sign_extend of a constant isn't valid.
5506 (define_insn "const_umulsidi3_sp32"
5507 [(set (match_operand:DI 0 "register_operand" "=r")
5508 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5509 (match_operand:DI 2 "uns_small_int" "")))]
5512 return TARGET_SPARCLET
5513 ? "umuld\t%1, %s2, %L0"
5514 : "umul\t%1, %s2, %L0\n\trd\t%%y, %H0";
5517 (if_then_else (eq_attr "isa" "sparclet")
5518 (const_string "imul") (const_string "multi")))
5519 (set (attr "length")
5520 (if_then_else (eq_attr "isa" "sparclet")
5521 (const_int 1) (const_int 2)))])
5523 (define_insn "const_umulsidi3_sp64"
5524 [(set (match_operand:DI 0 "register_operand" "=r")
5525 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5526 (match_operand:DI 2 "uns_small_int" "")))]
5527 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5529 [(set_attr "type" "imul")])
5532 (define_insn "const_umulsidi3_v8plus"
5533 [(set (match_operand:DI 0 "register_operand" "=h,r")
5534 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5535 (match_operand:DI 2 "uns_small_int" "")))
5536 (clobber (match_scratch:SI 3 "=X,h"))]
5539 umul\t%1, %s2, %L0\n\tsrlx\t%L0, 32, %H0
5540 umul\t%1, %s2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
5541 [(set_attr "type" "multi")
5542 (set_attr "length" "2,3")])
5544 (define_expand "umulsi3_highpart"
5545 [(set (match_operand:SI 0 "register_operand" "")
5547 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
5548 (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" "")))
5550 "TARGET_HARD_MUL && TARGET_ARCH32"
5552 if (CONSTANT_P (operands[2]))
5556 emit_insn (gen_const_umulsi3_highpart_v8plus (operands[0],
5562 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[1], operands[2]));
5567 emit_insn (gen_umulsi3_highpart_v8plus (operands[0], operands[1],
5568 operands[2], GEN_INT (32)));
5574 (define_insn "umulsi3_highpart_v8plus"
5575 [(set (match_operand:SI 0 "register_operand" "=h,r")
5577 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5578 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
5579 (match_operand:SI 3 "const_int_operand" "i,i"))))
5580 (clobber (match_scratch:SI 4 "=X,h"))]
5583 umul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
5584 umul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
5585 [(set_attr "type" "multi")
5586 (set_attr "length" "2")])
5589 (define_insn "const_umulsi3_highpart_v8plus"
5590 [(set (match_operand:SI 0 "register_operand" "=h,r")
5592 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
5593 (match_operand:DI 2 "uns_small_int" ""))
5594 (match_operand:SI 3 "const_int_operand" "i,i"))))
5595 (clobber (match_scratch:SI 4 "=X,h"))]
5598 umul\t%1, %s2, %0\n\tsrlx\t%0, %3, %0
5599 umul\t%1, %s2, %4\n\tsrlx\t%4, %3, %0"
5600 [(set_attr "type" "multi")
5601 (set_attr "length" "2")])
5604 (define_insn "*umulsi3_highpart_sp32"
5605 [(set (match_operand:SI 0 "register_operand" "=r")
5607 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5608 (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
5611 "umul\t%1, %2, %%g0\n\trd\t%%y, %0"
5612 [(set_attr "type" "multi")
5613 (set_attr "length" "2")])
5616 (define_insn "const_umulsi3_highpart"
5617 [(set (match_operand:SI 0 "register_operand" "=r")
5619 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5620 (match_operand:DI 2 "uns_small_int" ""))
5623 "umul\t%1, %s2, %%g0\n\trd\t%%y, %0"
5624 [(set_attr "type" "multi")
5625 (set_attr "length" "2")])
5627 ;; The v8 architecture specifies that there must be 3 instructions between
5628 ;; a y register write and a use of it for correct results.
5630 (define_expand "divsi3"
5631 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
5632 (div:SI (match_operand:SI 1 "register_operand" "r,r")
5633 (match_operand:SI 2 "input_operand" "rI,m")))
5634 (clobber (match_scratch:SI 3 "=&r,&r"))])]
5635 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5639 operands[3] = gen_reg_rtx(SImode);
5640 emit_insn (gen_ashrsi3 (operands[3], operands[1], GEN_INT (31)));
5641 emit_insn (gen_divsi3_sp64 (operands[0], operands[1], operands[2],
5647 (define_insn "divsi3_sp32"
5648 [(set (match_operand:SI 0 "register_operand" "=r,r")
5649 (div:SI (match_operand:SI 1 "register_operand" "r,r")
5650 (match_operand:SI 2 "input_operand" "rI,m")))
5651 (clobber (match_scratch:SI 3 "=&r,&r"))]
5652 "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS)
5655 if (which_alternative == 0)
5657 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdiv\t%1, %2, %0";
5659 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdiv\t%1, %2, %0";
5662 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tsdiv\t%1, %3, %0";
5664 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0";
5666 [(set_attr "type" "multi")
5667 (set (attr "length")
5668 (if_then_else (eq_attr "isa" "v9")
5669 (const_int 4) (const_int 6)))])
5671 (define_insn "divsi3_sp64"
5672 [(set (match_operand:SI 0 "register_operand" "=r")
5673 (div:SI (match_operand:SI 1 "register_operand" "r")
5674 (match_operand:SI 2 "input_operand" "rI")))
5675 (use (match_operand:SI 3 "register_operand" "r"))]
5676 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5677 "wr\t%%g0, %3, %%y\n\tsdiv\t%1, %2, %0"
5678 [(set_attr "type" "multi")
5679 (set_attr "length" "2")])
5681 (define_insn "divdi3"
5682 [(set (match_operand:DI 0 "register_operand" "=r")
5683 (div:DI (match_operand:DI 1 "register_operand" "r")
5684 (match_operand:DI 2 "arith_double_operand" "rHI")))]
5687 [(set_attr "type" "idiv")])
5689 (define_insn "*cmp_sdiv_cc_set"
5691 (compare:CC (div:SI (match_operand:SI 1 "register_operand" "r")
5692 (match_operand:SI 2 "arith_operand" "rI"))
5694 (set (match_operand:SI 0 "register_operand" "=r")
5695 (div:SI (match_dup 1) (match_dup 2)))
5696 (clobber (match_scratch:SI 3 "=&r"))]
5697 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5700 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdivcc\t%1, %2, %0";
5702 return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdivcc\t%1, %2, %0";
5704 [(set_attr "type" "multi")
5705 (set (attr "length")
5706 (if_then_else (eq_attr "isa" "v9")
5707 (const_int 3) (const_int 6)))])
5710 (define_expand "udivsi3"
5711 [(set (match_operand:SI 0 "register_operand" "")
5712 (udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "")
5713 (match_operand:SI 2 "input_operand" "")))]
5714 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5717 (define_insn "udivsi3_sp32"
5718 [(set (match_operand:SI 0 "register_operand" "=r,&r,&r")
5719 (udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "r,r,m")
5720 (match_operand:SI 2 "input_operand" "rI,m,r")))]
5722 || TARGET_DEPRECATED_V8_INSNS)
5725 output_asm_insn ("wr\t%%g0, %%g0, %%y", operands);
5726 switch (which_alternative)
5729 return "nop\n\tnop\n\tnop\n\tudiv\t%1, %2, %0";
5731 return "ld\t%2, %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0";
5733 return "ld\t%1, %0\n\tnop\n\tnop\n\tudiv\t%0, %2, %0";
5736 [(set_attr "type" "multi")
5737 (set_attr "length" "5")])
5739 (define_insn "udivsi3_sp64"
5740 [(set (match_operand:SI 0 "register_operand" "=r")
5741 (udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "r")
5742 (match_operand:SI 2 "input_operand" "rI")))]
5743 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5744 "wr\t%%g0, 0, %%y\n\tudiv\t%1, %2, %0"
5745 [(set_attr "type" "multi")
5746 (set_attr "length" "2")])
5748 (define_insn "udivdi3"
5749 [(set (match_operand:DI 0 "register_operand" "=r")
5750 (udiv:DI (match_operand:DI 1 "register_operand" "r")
5751 (match_operand:DI 2 "arith_double_operand" "rHI")))]
5754 [(set_attr "type" "idiv")])
5756 (define_insn "*cmp_udiv_cc_set"
5758 (compare:CC (udiv:SI (match_operand:SI 1 "register_operand" "r")
5759 (match_operand:SI 2 "arith_operand" "rI"))
5761 (set (match_operand:SI 0 "register_operand" "=r")
5762 (udiv:SI (match_dup 1) (match_dup 2)))]
5764 || TARGET_DEPRECATED_V8_INSNS"
5767 return "wr\t%%g0, %%g0, %%y\n\tudivcc\t%1, %2, %0";
5769 return "wr\t%%g0, %%g0, %%y\n\tnop\n\tnop\n\tnop\n\tudivcc\t%1, %2, %0";
5771 [(set_attr "type" "multi")
5772 (set (attr "length")
5773 (if_then_else (eq_attr "isa" "v9")
5774 (const_int 2) (const_int 5)))])
5776 ; sparclet multiply/accumulate insns
5778 (define_insn "*smacsi"
5779 [(set (match_operand:SI 0 "register_operand" "=r")
5780 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%r")
5781 (match_operand:SI 2 "arith_operand" "rI"))
5782 (match_operand:SI 3 "register_operand" "0")))]
5785 [(set_attr "type" "imul")])
5787 (define_insn "*smacdi"
5788 [(set (match_operand:DI 0 "register_operand" "=r")
5789 (plus:DI (mult:DI (sign_extend:DI
5790 (match_operand:SI 1 "register_operand" "%r"))
5792 (match_operand:SI 2 "register_operand" "r")))
5793 (match_operand:DI 3 "register_operand" "0")))]
5795 "smacd\t%1, %2, %L0"
5796 [(set_attr "type" "imul")])
5798 (define_insn "*umacdi"
5799 [(set (match_operand:DI 0 "register_operand" "=r")
5800 (plus:DI (mult:DI (zero_extend:DI
5801 (match_operand:SI 1 "register_operand" "%r"))
5803 (match_operand:SI 2 "register_operand" "r")))
5804 (match_operand:DI 3 "register_operand" "0")))]
5806 "umacd\t%1, %2, %L0"
5807 [(set_attr "type" "imul")])
5809 ;;- Boolean instructions
5810 ;; We define DImode `and' so with DImode `not' we can get
5811 ;; DImode `andn'. Other combinations are possible.
5813 (define_expand "anddi3"
5814 [(set (match_operand:DI 0 "register_operand" "")
5815 (and:DI (match_operand:DI 1 "arith_double_operand" "")
5816 (match_operand:DI 2 "arith_double_operand" "")))]
5820 (define_insn "*anddi3_sp32"
5821 [(set (match_operand:DI 0 "register_operand" "=r,b")
5822 (and:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
5823 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
5828 [(set_attr "type" "*,fp")
5829 (set_attr "length" "2,*")
5830 (set_attr "fptype" "double")])
5832 (define_insn "*anddi3_sp64"
5833 [(set (match_operand:DI 0 "register_operand" "=r,b")
5834 (and:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
5835 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
5840 [(set_attr "type" "*,fp")
5841 (set_attr "fptype" "double")])
5843 (define_insn "andsi3"
5844 [(set (match_operand:SI 0 "register_operand" "=r,d")
5845 (and:SI (match_operand:SI 1 "arith_operand" "%r,d")
5846 (match_operand:SI 2 "arith_operand" "rI,d")))]
5851 [(set_attr "type" "*,fp")])
5854 [(set (match_operand:SI 0 "register_operand" "")
5855 (and:SI (match_operand:SI 1 "register_operand" "")
5856 (match_operand:SI 2 "" "")))
5857 (clobber (match_operand:SI 3 "register_operand" ""))]
5858 "GET_CODE (operands[2]) == CONST_INT
5859 && !SMALL_INT32 (operands[2])
5860 && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
5861 [(set (match_dup 3) (match_dup 4))
5862 (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
5864 operands[4] = GEN_INT (~INTVAL (operands[2]));
5867 ;; Split DImode logical operations requiring two instructions.
5869 [(set (match_operand:DI 0 "register_operand" "")
5870 (match_operator:DI 1 "cc_arithop" ; AND, IOR, XOR
5871 [(match_operand:DI 2 "register_operand" "")
5872 (match_operand:DI 3 "arith_double_operand" "")]))]
5875 && ((GET_CODE (operands[0]) == REG
5876 && REGNO (operands[0]) < 32)
5877 || (GET_CODE (operands[0]) == SUBREG
5878 && GET_CODE (SUBREG_REG (operands[0])) == REG
5879 && REGNO (SUBREG_REG (operands[0])) < 32))"
5880 [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)]))
5881 (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
5883 operands[4] = gen_highpart (SImode, operands[0]);
5884 operands[5] = gen_lowpart (SImode, operands[0]);
5885 operands[6] = gen_highpart (SImode, operands[2]);
5886 operands[7] = gen_lowpart (SImode, operands[2]);
5887 #if HOST_BITS_PER_WIDE_INT == 32
5888 if (GET_CODE (operands[3]) == CONST_INT)
5890 if (INTVAL (operands[3]) < 0)
5891 operands[8] = constm1_rtx;
5893 operands[8] = const0_rtx;
5897 operands[8] = gen_highpart_mode (SImode, DImode, operands[3]);
5898 operands[9] = gen_lowpart (SImode, operands[3]);
5901 (define_insn_and_split "*and_not_di_sp32"
5902 [(set (match_operand:DI 0 "register_operand" "=r,b")
5903 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
5904 (match_operand:DI 2 "register_operand" "r,b")))]
5908 fandnot1\t%1, %2, %0"
5909 "&& reload_completed
5910 && ((GET_CODE (operands[0]) == REG
5911 && REGNO (operands[0]) < 32)
5912 || (GET_CODE (operands[0]) == SUBREG
5913 && GET_CODE (SUBREG_REG (operands[0])) == REG
5914 && REGNO (SUBREG_REG (operands[0])) < 32))"
5915 [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))
5916 (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))]
5917 "operands[3] = gen_highpart (SImode, operands[0]);
5918 operands[4] = gen_highpart (SImode, operands[1]);
5919 operands[5] = gen_highpart (SImode, operands[2]);
5920 operands[6] = gen_lowpart (SImode, operands[0]);
5921 operands[7] = gen_lowpart (SImode, operands[1]);
5922 operands[8] = gen_lowpart (SImode, operands[2]);"
5923 [(set_attr "type" "*,fp")
5924 (set_attr "length" "2,*")
5925 (set_attr "fptype" "double")])
5927 (define_insn "*and_not_di_sp64"
5928 [(set (match_operand:DI 0 "register_operand" "=r,b")
5929 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
5930 (match_operand:DI 2 "register_operand" "r,b")))]
5934 fandnot1\t%1, %2, %0"
5935 [(set_attr "type" "*,fp")
5936 (set_attr "fptype" "double")])
5938 (define_insn "*and_not_si"
5939 [(set (match_operand:SI 0 "register_operand" "=r,d")
5940 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r,d"))
5941 (match_operand:SI 2 "register_operand" "r,d")))]
5945 fandnot1s\t%1, %2, %0"
5946 [(set_attr "type" "*,fp")])
5948 (define_expand "iordi3"
5949 [(set (match_operand:DI 0 "register_operand" "")
5950 (ior:DI (match_operand:DI 1 "arith_double_operand" "")
5951 (match_operand:DI 2 "arith_double_operand" "")))]
5955 (define_insn "*iordi3_sp32"
5956 [(set (match_operand:DI 0 "register_operand" "=r,b")
5957 (ior:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
5958 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
5963 [(set_attr "type" "*,fp")
5964 (set_attr "length" "2,*")
5965 (set_attr "fptype" "double")])
5967 (define_insn "*iordi3_sp64"
5968 [(set (match_operand:DI 0 "register_operand" "=r,b")
5969 (ior:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
5970 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
5975 [(set_attr "type" "*,fp")
5976 (set_attr "fptype" "double")])
5978 (define_insn "iorsi3"
5979 [(set (match_operand:SI 0 "register_operand" "=r,d")
5980 (ior:SI (match_operand:SI 1 "arith_operand" "%r,d")
5981 (match_operand:SI 2 "arith_operand" "rI,d")))]
5986 [(set_attr "type" "*,fp")])
5989 [(set (match_operand:SI 0 "register_operand" "")
5990 (ior:SI (match_operand:SI 1 "register_operand" "")
5991 (match_operand:SI 2 "" "")))
5992 (clobber (match_operand:SI 3 "register_operand" ""))]
5993 "GET_CODE (operands[2]) == CONST_INT
5994 && !SMALL_INT32 (operands[2])
5995 && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
5996 [(set (match_dup 3) (match_dup 4))
5997 (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
5999 operands[4] = GEN_INT (~INTVAL (operands[2]));
6002 (define_insn_and_split "*or_not_di_sp32"
6003 [(set (match_operand:DI 0 "register_operand" "=r,b")
6004 (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
6005 (match_operand:DI 2 "register_operand" "r,b")))]
6009 fornot1\t%1, %2, %0"
6010 "&& reload_completed
6011 && ((GET_CODE (operands[0]) == REG
6012 && REGNO (operands[0]) < 32)
6013 || (GET_CODE (operands[0]) == SUBREG
6014 && GET_CODE (SUBREG_REG (operands[0])) == REG
6015 && REGNO (SUBREG_REG (operands[0])) < 32))"
6016 [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))
6017 (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))]
6018 "operands[3] = gen_highpart (SImode, operands[0]);
6019 operands[4] = gen_highpart (SImode, operands[1]);
6020 operands[5] = gen_highpart (SImode, operands[2]);
6021 operands[6] = gen_lowpart (SImode, operands[0]);
6022 operands[7] = gen_lowpart (SImode, operands[1]);
6023 operands[8] = gen_lowpart (SImode, operands[2]);"
6024 [(set_attr "type" "*,fp")
6025 (set_attr "length" "2,*")
6026 (set_attr "fptype" "double")])
6028 (define_insn "*or_not_di_sp64"
6029 [(set (match_operand:DI 0 "register_operand" "=r,b")
6030 (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b"))
6031 (match_operand:DI 2 "register_operand" "r,b")))]
6035 fornot1\t%1, %2, %0"
6036 [(set_attr "type" "*,fp")
6037 (set_attr "fptype" "double")])
6039 (define_insn "*or_not_si"
6040 [(set (match_operand:SI 0 "register_operand" "=r,d")
6041 (ior:SI (not:SI (match_operand:SI 1 "register_operand" "r,d"))
6042 (match_operand:SI 2 "register_operand" "r,d")))]
6046 fornot1s\t%1, %2, %0"
6047 [(set_attr "type" "*,fp")])
6049 (define_expand "xordi3"
6050 [(set (match_operand:DI 0 "register_operand" "")
6051 (xor:DI (match_operand:DI 1 "arith_double_operand" "")
6052 (match_operand:DI 2 "arith_double_operand" "")))]
6056 (define_insn "*xordi3_sp32"
6057 [(set (match_operand:DI 0 "register_operand" "=r,b")
6058 (xor:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
6059 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
6064 [(set_attr "type" "*,fp")
6065 (set_attr "length" "2,*")
6066 (set_attr "fptype" "double")])
6068 (define_insn "*xordi3_sp64"
6069 [(set (match_operand:DI 0 "register_operand" "=r,b")
6070 (xor:DI (match_operand:DI 1 "arith_double_operand" "%rJ,b")
6071 (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
6076 [(set_attr "type" "*,fp")
6077 (set_attr "fptype" "double")])
6079 (define_insn "*xordi3_sp64_dbl"
6080 [(set (match_operand:DI 0 "register_operand" "=r")
6081 (xor:DI (match_operand:DI 1 "register_operand" "r")
6082 (match_operand:DI 2 "const64_operand" "")))]
6084 && HOST_BITS_PER_WIDE_INT != 64)"
6087 (define_insn "xorsi3"
6088 [(set (match_operand:SI 0 "register_operand" "=r,d")
6089 (xor:SI (match_operand:SI 1 "arith_operand" "%rJ,d")
6090 (match_operand:SI 2 "arith_operand" "rI,d")))]
6095 [(set_attr "type" "*,fp")])
6098 [(set (match_operand:SI 0 "register_operand" "")
6099 (xor:SI (match_operand:SI 1 "register_operand" "")
6100 (match_operand:SI 2 "" "")))
6101 (clobber (match_operand:SI 3 "register_operand" ""))]
6102 "GET_CODE (operands[2]) == CONST_INT
6103 && !SMALL_INT32 (operands[2])
6104 && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
6105 [(set (match_dup 3) (match_dup 4))
6106 (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
6108 operands[4] = GEN_INT (~INTVAL (operands[2]));
6112 [(set (match_operand:SI 0 "register_operand" "")
6113 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "")
6114 (match_operand:SI 2 "" ""))))
6115 (clobber (match_operand:SI 3 "register_operand" ""))]
6116 "GET_CODE (operands[2]) == CONST_INT
6117 && !SMALL_INT32 (operands[2])
6118 && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
6119 [(set (match_dup 3) (match_dup 4))
6120 (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
6122 operands[4] = GEN_INT (~INTVAL (operands[2]));
6125 ;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b).
6126 ;; Combine now canonicalizes to the rightmost expression.
6127 (define_insn_and_split "*xor_not_di_sp32"
6128 [(set (match_operand:DI 0 "register_operand" "=r,b")
6129 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "r,b")
6130 (match_operand:DI 2 "register_operand" "r,b"))))]
6135 "&& reload_completed
6136 && ((GET_CODE (operands[0]) == REG
6137 && REGNO (operands[0]) < 32)
6138 || (GET_CODE (operands[0]) == SUBREG
6139 && GET_CODE (SUBREG_REG (operands[0])) == REG
6140 && REGNO (SUBREG_REG (operands[0])) < 32))"
6141 [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5))))
6142 (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))]
6143 "operands[3] = gen_highpart (SImode, operands[0]);
6144 operands[4] = gen_highpart (SImode, operands[1]);
6145 operands[5] = gen_highpart (SImode, operands[2]);
6146 operands[6] = gen_lowpart (SImode, operands[0]);
6147 operands[7] = gen_lowpart (SImode, operands[1]);
6148 operands[8] = gen_lowpart (SImode, operands[2]);"
6149 [(set_attr "type" "*,fp")
6150 (set_attr "length" "2,*")
6151 (set_attr "fptype" "double")])
6153 (define_insn "*xor_not_di_sp64"
6154 [(set (match_operand:DI 0 "register_operand" "=r,b")
6155 (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,b")
6156 (match_operand:DI 2 "arith_double_operand" "rHI,b"))))]
6161 [(set_attr "type" "*,fp")
6162 (set_attr "fptype" "double")])
6164 (define_insn "*xor_not_si"
6165 [(set (match_operand:SI 0 "register_operand" "=r,d")
6166 (not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,d")
6167 (match_operand:SI 2 "arith_operand" "rI,d"))))]
6172 [(set_attr "type" "*,fp")])
6174 ;; These correspond to the above in the case where we also (or only)
6175 ;; want to set the condition code.
6177 (define_insn "*cmp_cc_arith_op"
6180 (match_operator:SI 2 "cc_arithop"
6181 [(match_operand:SI 0 "arith_operand" "%r")
6182 (match_operand:SI 1 "arith_operand" "rI")])
6185 "%A2cc\t%0, %1, %%g0"
6186 [(set_attr "type" "compare")])
6188 (define_insn "*cmp_ccx_arith_op"
6191 (match_operator:DI 2 "cc_arithop"
6192 [(match_operand:DI 0 "arith_double_operand" "%r")
6193 (match_operand:DI 1 "arith_double_operand" "rHI")])
6196 "%A2cc\t%0, %1, %%g0"
6197 [(set_attr "type" "compare")])
6199 (define_insn "*cmp_cc_arith_op_set"
6202 (match_operator:SI 3 "cc_arithop"
6203 [(match_operand:SI 1 "arith_operand" "%r")
6204 (match_operand:SI 2 "arith_operand" "rI")])
6206 (set (match_operand:SI 0 "register_operand" "=r")
6207 (match_operator:SI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))]
6208 "GET_CODE (operands[3]) == GET_CODE (operands[4])"
6210 [(set_attr "type" "compare")])
6212 (define_insn "*cmp_ccx_arith_op_set"
6215 (match_operator:DI 3 "cc_arithop"
6216 [(match_operand:DI 1 "arith_double_operand" "%r")
6217 (match_operand:DI 2 "arith_double_operand" "rHI")])
6219 (set (match_operand:DI 0 "register_operand" "=r")
6220 (match_operator:DI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))]
6221 "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
6223 [(set_attr "type" "compare")])
6225 (define_insn "*cmp_cc_xor_not"
6228 (not:SI (xor:SI (match_operand:SI 0 "reg_or_0_operand" "%rJ")
6229 (match_operand:SI 1 "arith_operand" "rI")))
6232 "xnorcc\t%r0, %1, %%g0"
6233 [(set_attr "type" "compare")])
6235 (define_insn "*cmp_ccx_xor_not"
6238 (not:DI (xor:DI (match_operand:DI 0 "reg_or_0_operand" "%rJ")
6239 (match_operand:DI 1 "arith_double_operand" "rHI")))
6242 "xnorcc\t%r0, %1, %%g0"
6243 [(set_attr "type" "compare")])
6245 (define_insn "*cmp_cc_xor_not_set"
6248 (not:SI (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
6249 (match_operand:SI 2 "arith_operand" "rI")))
6251 (set (match_operand:SI 0 "register_operand" "=r")
6252 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
6254 "xnorcc\t%r1, %2, %0"
6255 [(set_attr "type" "compare")])
6257 (define_insn "*cmp_ccx_xor_not_set"
6260 (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
6261 (match_operand:DI 2 "arith_double_operand" "rHI")))
6263 (set (match_operand:DI 0 "register_operand" "=r")
6264 (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
6266 "xnorcc\t%r1, %2, %0"
6267 [(set_attr "type" "compare")])
6269 (define_insn "*cmp_cc_arith_op_not"
6272 (match_operator:SI 2 "cc_arithopn"
6273 [(not:SI (match_operand:SI 0 "arith_operand" "rI"))
6274 (match_operand:SI 1 "reg_or_0_operand" "rJ")])
6277 "%B2cc\t%r1, %0, %%g0"
6278 [(set_attr "type" "compare")])
6280 (define_insn "*cmp_ccx_arith_op_not"
6283 (match_operator:DI 2 "cc_arithopn"
6284 [(not:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
6285 (match_operand:DI 1 "reg_or_0_operand" "rJ")])
6288 "%B2cc\t%r1, %0, %%g0"
6289 [(set_attr "type" "compare")])
6291 (define_insn "*cmp_cc_arith_op_not_set"
6294 (match_operator:SI 3 "cc_arithopn"
6295 [(not:SI (match_operand:SI 1 "arith_operand" "rI"))
6296 (match_operand:SI 2 "reg_or_0_operand" "rJ")])
6298 (set (match_operand:SI 0 "register_operand" "=r")
6299 (match_operator:SI 4 "cc_arithopn"
6300 [(not:SI (match_dup 1)) (match_dup 2)]))]
6301 "GET_CODE (operands[3]) == GET_CODE (operands[4])"
6302 "%B3cc\t%r2, %1, %0"
6303 [(set_attr "type" "compare")])
6305 (define_insn "*cmp_ccx_arith_op_not_set"
6308 (match_operator:DI 3 "cc_arithopn"
6309 [(not:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
6310 (match_operand:DI 2 "reg_or_0_operand" "rJ")])
6312 (set (match_operand:DI 0 "register_operand" "=r")
6313 (match_operator:DI 4 "cc_arithopn"
6314 [(not:DI (match_dup 1)) (match_dup 2)]))]
6315 "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
6316 "%B3cc\t%r2, %1, %0"
6317 [(set_attr "type" "compare")])
6319 ;; We cannot use the "neg" pseudo insn because the Sun assembler
6320 ;; does not know how to make it work for constants.
6322 (define_expand "negdi2"
6323 [(set (match_operand:DI 0 "register_operand" "=r")
6324 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6327 if (! TARGET_ARCH64)
6329 emit_insn (gen_rtx_PARALLEL
6332 gen_rtx_SET (VOIDmode, operand0,
6333 gen_rtx_NEG (DImode, operand1)),
6334 gen_rtx_CLOBBER (VOIDmode,
6335 gen_rtx_REG (CCmode,
6341 (define_insn_and_split "*negdi2_sp32"
6342 [(set (match_operand:DI 0 "register_operand" "=r")
6343 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6344 (clobber (reg:CC 100))]
6347 "&& reload_completed"
6348 [(parallel [(set (reg:CC_NOOV 100)
6349 (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5))
6351 (set (match_dup 4) (minus:SI (const_int 0) (match_dup 5)))])
6352 (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3))
6353 (ltu:SI (reg:CC 100) (const_int 0))))]
6354 "operands[2] = gen_highpart (SImode, operands[0]);
6355 operands[3] = gen_highpart (SImode, operands[1]);
6356 operands[4] = gen_lowpart (SImode, operands[0]);
6357 operands[5] = gen_lowpart (SImode, operands[1]);"
6358 [(set_attr "length" "2")])
6360 (define_insn "*negdi2_sp64"
6361 [(set (match_operand:DI 0 "register_operand" "=r")
6362 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6364 "sub\t%%g0, %1, %0")
6366 (define_insn "negsi2"
6367 [(set (match_operand:SI 0 "register_operand" "=r")
6368 (neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
6370 "sub\t%%g0, %1, %0")
6372 (define_insn "*cmp_cc_neg"
6373 [(set (reg:CC_NOOV 100)
6374 (compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
6377 "subcc\t%%g0, %0, %%g0"
6378 [(set_attr "type" "compare")])
6380 (define_insn "*cmp_ccx_neg"
6381 [(set (reg:CCX_NOOV 100)
6382 (compare:CCX_NOOV (neg:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
6385 "subcc\t%%g0, %0, %%g0"
6386 [(set_attr "type" "compare")])
6388 (define_insn "*cmp_cc_set_neg"
6389 [(set (reg:CC_NOOV 100)
6390 (compare:CC_NOOV (neg:SI (match_operand:SI 1 "arith_operand" "rI"))
6392 (set (match_operand:SI 0 "register_operand" "=r")
6393 (neg:SI (match_dup 1)))]
6395 "subcc\t%%g0, %1, %0"
6396 [(set_attr "type" "compare")])
6398 (define_insn "*cmp_ccx_set_neg"
6399 [(set (reg:CCX_NOOV 100)
6400 (compare:CCX_NOOV (neg:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
6402 (set (match_operand:DI 0 "register_operand" "=r")
6403 (neg:DI (match_dup 1)))]
6405 "subcc\t%%g0, %1, %0"
6406 [(set_attr "type" "compare")])
6408 ;; We cannot use the "not" pseudo insn because the Sun assembler
6409 ;; does not know how to make it work for constants.
6410 (define_expand "one_cmpldi2"
6411 [(set (match_operand:DI 0 "register_operand" "")
6412 (not:DI (match_operand:DI 1 "register_operand" "")))]
6416 (define_insn_and_split "*one_cmpldi2_sp32"
6417 [(set (match_operand:DI 0 "register_operand" "=r,b")
6418 (not:DI (match_operand:DI 1 "register_operand" "r,b")))]
6423 "&& reload_completed
6424 && ((GET_CODE (operands[0]) == REG
6425 && REGNO (operands[0]) < 32)
6426 || (GET_CODE (operands[0]) == SUBREG
6427 && GET_CODE (SUBREG_REG (operands[0])) == REG
6428 && REGNO (SUBREG_REG (operands[0])) < 32))"
6429 [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0))))
6430 (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))]
6431 "operands[2] = gen_highpart (SImode, operands[0]);
6432 operands[3] = gen_highpart (SImode, operands[1]);
6433 operands[4] = gen_lowpart (SImode, operands[0]);
6434 operands[5] = gen_lowpart (SImode, operands[1]);"
6435 [(set_attr "type" "*,fp")
6436 (set_attr "length" "2,*")
6437 (set_attr "fptype" "double")])
6439 (define_insn "*one_cmpldi2_sp64"
6440 [(set (match_operand:DI 0 "register_operand" "=r,b")
6441 (not:DI (match_operand:DI 1 "arith_double_operand" "rHI,b")))]
6446 [(set_attr "type" "*,fp")
6447 (set_attr "fptype" "double")])
6449 (define_insn "one_cmplsi2"
6450 [(set (match_operand:SI 0 "register_operand" "=r,d")
6451 (not:SI (match_operand:SI 1 "arith_operand" "rI,d")))]
6456 [(set_attr "type" "*,fp")])
6458 (define_insn "*cmp_cc_not"
6460 (compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI"))
6463 "xnorcc\t%%g0, %0, %%g0"
6464 [(set_attr "type" "compare")])
6466 (define_insn "*cmp_ccx_not"
6468 (compare:CCX (not:DI (match_operand:DI 0 "arith_double_operand" "rHI"))
6471 "xnorcc\t%%g0, %0, %%g0"
6472 [(set_attr "type" "compare")])
6474 (define_insn "*cmp_cc_set_not"
6476 (compare:CC (not:SI (match_operand:SI 1 "arith_operand" "rI"))
6478 (set (match_operand:SI 0 "register_operand" "=r")
6479 (not:SI (match_dup 1)))]
6481 "xnorcc\t%%g0, %1, %0"
6482 [(set_attr "type" "compare")])
6484 (define_insn "*cmp_ccx_set_not"
6486 (compare:CCX (not:DI (match_operand:DI 1 "arith_double_operand" "rHI"))
6488 (set (match_operand:DI 0 "register_operand" "=r")
6489 (not:DI (match_dup 1)))]
6491 "xnorcc\t%%g0, %1, %0"
6492 [(set_attr "type" "compare")])
6494 (define_insn "*cmp_cc_set"
6495 [(set (match_operand:SI 0 "register_operand" "=r")
6496 (match_operand:SI 1 "register_operand" "r"))
6498 (compare:CC (match_dup 1)
6502 [(set_attr "type" "compare")])
6504 (define_insn "*cmp_ccx_set64"
6505 [(set (match_operand:DI 0 "register_operand" "=r")
6506 (match_operand:DI 1 "register_operand" "r"))
6508 (compare:CCX (match_dup 1)
6512 [(set_attr "type" "compare")])
6514 ;; Floating point arithmetic instructions.
6516 (define_expand "addtf3"
6517 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6518 (plus:TF (match_operand:TF 1 "general_operand" "")
6519 (match_operand:TF 2 "general_operand" "")))]
6520 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6521 "emit_tfmode_binop (PLUS, operands); DONE;")
6523 (define_insn "*addtf3_hq"
6524 [(set (match_operand:TF 0 "register_operand" "=e")
6525 (plus:TF (match_operand:TF 1 "register_operand" "e")
6526 (match_operand:TF 2 "register_operand" "e")))]
6527 "TARGET_FPU && TARGET_HARD_QUAD"
6529 [(set_attr "type" "fp")])
6531 (define_insn "adddf3"
6532 [(set (match_operand:DF 0 "register_operand" "=e")
6533 (plus:DF (match_operand:DF 1 "register_operand" "e")
6534 (match_operand:DF 2 "register_operand" "e")))]
6537 [(set_attr "type" "fp")
6538 (set_attr "fptype" "double")])
6540 (define_insn "addsf3"
6541 [(set (match_operand:SF 0 "register_operand" "=f")
6542 (plus:SF (match_operand:SF 1 "register_operand" "f")
6543 (match_operand:SF 2 "register_operand" "f")))]
6546 [(set_attr "type" "fp")])
6548 (define_expand "subtf3"
6549 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6550 (minus:TF (match_operand:TF 1 "general_operand" "")
6551 (match_operand:TF 2 "general_operand" "")))]
6552 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6553 "emit_tfmode_binop (MINUS, operands); DONE;")
6555 (define_insn "*subtf3_hq"
6556 [(set (match_operand:TF 0 "register_operand" "=e")
6557 (minus:TF (match_operand:TF 1 "register_operand" "e")
6558 (match_operand:TF 2 "register_operand" "e")))]
6559 "TARGET_FPU && TARGET_HARD_QUAD"
6561 [(set_attr "type" "fp")])
6563 (define_insn "subdf3"
6564 [(set (match_operand:DF 0 "register_operand" "=e")
6565 (minus:DF (match_operand:DF 1 "register_operand" "e")
6566 (match_operand:DF 2 "register_operand" "e")))]
6569 [(set_attr "type" "fp")
6570 (set_attr "fptype" "double")])
6572 (define_insn "subsf3"
6573 [(set (match_operand:SF 0 "register_operand" "=f")
6574 (minus:SF (match_operand:SF 1 "register_operand" "f")
6575 (match_operand:SF 2 "register_operand" "f")))]
6578 [(set_attr "type" "fp")])
6580 (define_expand "multf3"
6581 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6582 (mult:TF (match_operand:TF 1 "general_operand" "")
6583 (match_operand:TF 2 "general_operand" "")))]
6584 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6585 "emit_tfmode_binop (MULT, operands); DONE;")
6587 (define_insn "*multf3_hq"
6588 [(set (match_operand:TF 0 "register_operand" "=e")
6589 (mult:TF (match_operand:TF 1 "register_operand" "e")
6590 (match_operand:TF 2 "register_operand" "e")))]
6591 "TARGET_FPU && TARGET_HARD_QUAD"
6593 [(set_attr "type" "fpmul")])
6595 (define_insn "muldf3"
6596 [(set (match_operand:DF 0 "register_operand" "=e")
6597 (mult:DF (match_operand:DF 1 "register_operand" "e")
6598 (match_operand:DF 2 "register_operand" "e")))]
6601 [(set_attr "type" "fpmul")
6602 (set_attr "fptype" "double")])
6604 (define_insn "mulsf3"
6605 [(set (match_operand:SF 0 "register_operand" "=f")
6606 (mult:SF (match_operand:SF 1 "register_operand" "f")
6607 (match_operand:SF 2 "register_operand" "f")))]
6610 [(set_attr "type" "fpmul")])
6612 (define_insn "*muldf3_extend"
6613 [(set (match_operand:DF 0 "register_operand" "=e")
6614 (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
6615 (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
6616 "(TARGET_V8 || TARGET_V9) && TARGET_FPU"
6617 "fsmuld\t%1, %2, %0"
6618 [(set_attr "type" "fpmul")
6619 (set_attr "fptype" "double")])
6621 (define_insn "*multf3_extend"
6622 [(set (match_operand:TF 0 "register_operand" "=e")
6623 (mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e"))
6624 (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
6625 "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD"
6626 "fdmulq\t%1, %2, %0"
6627 [(set_attr "type" "fpmul")])
6629 (define_expand "divtf3"
6630 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6631 (div:TF (match_operand:TF 1 "general_operand" "")
6632 (match_operand:TF 2 "general_operand" "")))]
6633 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6634 "emit_tfmode_binop (DIV, operands); DONE;")
6636 ;; don't have timing for quad-prec. divide.
6637 (define_insn "*divtf3_hq"
6638 [(set (match_operand:TF 0 "register_operand" "=e")
6639 (div:TF (match_operand:TF 1 "register_operand" "e")
6640 (match_operand:TF 2 "register_operand" "e")))]
6641 "TARGET_FPU && TARGET_HARD_QUAD"
6643 [(set_attr "type" "fpdivd")])
6645 (define_insn "divdf3"
6646 [(set (match_operand:DF 0 "register_operand" "=e")
6647 (div:DF (match_operand:DF 1 "register_operand" "e")
6648 (match_operand:DF 2 "register_operand" "e")))]
6651 [(set_attr "type" "fpdivd")
6652 (set_attr "fptype" "double")])
6654 (define_insn "divsf3"
6655 [(set (match_operand:SF 0 "register_operand" "=f")
6656 (div:SF (match_operand:SF 1 "register_operand" "f")
6657 (match_operand:SF 2 "register_operand" "f")))]
6660 [(set_attr "type" "fpdivs")])
6662 (define_expand "negtf2"
6663 [(set (match_operand:TF 0 "register_operand" "=e,e")
6664 (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
6668 (define_insn_and_split "*negtf2_notv9"
6669 [(set (match_operand:TF 0 "register_operand" "=e,e")
6670 (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
6671 ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
6677 "&& reload_completed
6678 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6679 [(set (match_dup 2) (neg:SF (match_dup 3)))
6680 (set (match_dup 4) (match_dup 5))
6681 (set (match_dup 6) (match_dup 7))]
6682 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6683 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6684 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6685 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
6686 operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6687 operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6688 [(set_attr "type" "fpmove,*")
6689 (set_attr "length" "*,2")])
6691 (define_insn_and_split "*negtf2_v9"
6692 [(set (match_operand:TF 0 "register_operand" "=e,e")
6693 (neg:TF (match_operand:TF 1 "register_operand" "0,e")))]
6694 ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
6695 "TARGET_FPU && TARGET_V9"
6699 "&& reload_completed
6700 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6701 [(set (match_dup 2) (neg:DF (match_dup 3)))
6702 (set (match_dup 4) (match_dup 5))]
6703 "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
6704 operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
6705 operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6706 operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6707 [(set_attr "type" "fpmove,*")
6708 (set_attr "length" "*,2")
6709 (set_attr "fptype" "double")])
6711 (define_expand "negdf2"
6712 [(set (match_operand:DF 0 "register_operand" "")
6713 (neg:DF (match_operand:DF 1 "register_operand" "")))]
6717 (define_insn_and_split "*negdf2_notv9"
6718 [(set (match_operand:DF 0 "register_operand" "=e,e")
6719 (neg:DF (match_operand:DF 1 "register_operand" "0,e")))]
6720 "TARGET_FPU && ! TARGET_V9"
6724 "&& reload_completed
6725 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6726 [(set (match_dup 2) (neg:SF (match_dup 3)))
6727 (set (match_dup 4) (match_dup 5))]
6728 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6729 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6730 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6731 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);"
6732 [(set_attr "type" "fpmove,*")
6733 (set_attr "length" "*,2")])
6735 (define_insn "*negdf2_v9"
6736 [(set (match_operand:DF 0 "register_operand" "=e")
6737 (neg:DF (match_operand:DF 1 "register_operand" "e")))]
6738 "TARGET_FPU && TARGET_V9"
6740 [(set_attr "type" "fpmove")
6741 (set_attr "fptype" "double")])
6743 (define_insn "negsf2"
6744 [(set (match_operand:SF 0 "register_operand" "=f")
6745 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6748 [(set_attr "type" "fpmove")])
6750 (define_expand "abstf2"
6751 [(set (match_operand:TF 0 "register_operand" "")
6752 (abs:TF (match_operand:TF 1 "register_operand" "")))]
6756 (define_insn_and_split "*abstf2_notv9"
6757 [(set (match_operand:TF 0 "register_operand" "=e,e")
6758 (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
6759 ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD.
6760 "TARGET_FPU && ! TARGET_V9"
6764 "&& reload_completed
6765 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6766 [(set (match_dup 2) (abs:SF (match_dup 3)))
6767 (set (match_dup 4) (match_dup 5))
6768 (set (match_dup 6) (match_dup 7))]
6769 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6770 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6771 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6772 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
6773 operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6774 operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6775 [(set_attr "type" "fpmove,*")
6776 (set_attr "length" "*,2")])
6778 (define_insn "*abstf2_hq_v9"
6779 [(set (match_operand:TF 0 "register_operand" "=e,e")
6780 (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
6781 "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD"
6785 [(set_attr "type" "fpmove")
6786 (set_attr "fptype" "double,*")])
6788 (define_insn_and_split "*abstf2_v9"
6789 [(set (match_operand:TF 0 "register_operand" "=e,e")
6790 (abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
6791 "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD"
6795 "&& reload_completed
6796 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6797 [(set (match_dup 2) (abs:DF (match_dup 3)))
6798 (set (match_dup 4) (match_dup 5))]
6799 "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
6800 operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
6801 operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
6802 operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);"
6803 [(set_attr "type" "fpmove,*")
6804 (set_attr "length" "*,2")
6805 (set_attr "fptype" "double,*")])
6807 (define_expand "absdf2"
6808 [(set (match_operand:DF 0 "register_operand" "")
6809 (abs:DF (match_operand:DF 1 "register_operand" "")))]
6813 (define_insn_and_split "*absdf2_notv9"
6814 [(set (match_operand:DF 0 "register_operand" "=e,e")
6815 (abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
6816 "TARGET_FPU && ! TARGET_V9"
6820 "&& reload_completed
6821 && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
6822 [(set (match_dup 2) (abs:SF (match_dup 3)))
6823 (set (match_dup 4) (match_dup 5))]
6824 "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
6825 operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
6826 operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
6827 operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);"
6828 [(set_attr "type" "fpmove,*")
6829 (set_attr "length" "*,2")])
6831 (define_insn "*absdf2_v9"
6832 [(set (match_operand:DF 0 "register_operand" "=e")
6833 (abs:DF (match_operand:DF 1 "register_operand" "e")))]
6834 "TARGET_FPU && TARGET_V9"
6836 [(set_attr "type" "fpmove")
6837 (set_attr "fptype" "double")])
6839 (define_insn "abssf2"
6840 [(set (match_operand:SF 0 "register_operand" "=f")
6841 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6844 [(set_attr "type" "fpmove")])
6846 (define_expand "sqrttf2"
6847 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6848 (sqrt:TF (match_operand:TF 1 "general_operand" "")))]
6849 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6850 "emit_tfmode_unop (SQRT, operands); DONE;")
6852 (define_insn "*sqrttf2_hq"
6853 [(set (match_operand:TF 0 "register_operand" "=e")
6854 (sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
6855 "TARGET_FPU && TARGET_HARD_QUAD"
6857 [(set_attr "type" "fpsqrtd")])
6859 (define_insn "sqrtdf2"
6860 [(set (match_operand:DF 0 "register_operand" "=e")
6861 (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
6864 [(set_attr "type" "fpsqrtd")
6865 (set_attr "fptype" "double")])
6867 (define_insn "sqrtsf2"
6868 [(set (match_operand:SF 0 "register_operand" "=f")
6869 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6872 [(set_attr "type" "fpsqrts")])
6874 ;;- arithmetic shift instructions
6876 (define_insn "ashlsi3"
6877 [(set (match_operand:SI 0 "register_operand" "=r")
6878 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6879 (match_operand:SI 2 "arith_operand" "rI")))]
6882 if (operands[2] == const1_rtx)
6883 return "add\t%1, %1, %0";
6884 return "sll\t%1, %2, %0";
6887 (if_then_else (match_operand 2 "const1_operand" "")
6888 (const_string "ialu") (const_string "shift")))])
6890 (define_expand "ashldi3"
6891 [(set (match_operand:DI 0 "register_operand" "=r")
6892 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6893 (match_operand:SI 2 "arith_operand" "rI")))]
6894 "TARGET_ARCH64 || TARGET_V8PLUS"
6896 if (! TARGET_ARCH64)
6898 if (GET_CODE (operands[2]) == CONST_INT)
6900 emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2]));
6905 (define_insn "*ashldi3_sp64"
6906 [(set (match_operand:DI 0 "register_operand" "=r")
6907 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6908 (match_operand:SI 2 "arith_operand" "rI")))]
6911 if (operands[2] == const1_rtx)
6912 return "add\t%1, %1, %0";
6913 return "sllx\t%1, %2, %0";
6916 (if_then_else (match_operand 2 "const1_operand" "")
6917 (const_string "ialu") (const_string "shift")))])
6920 (define_insn "ashldi3_v8plus"
6921 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
6922 (ashift:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
6923 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
6924 (clobber (match_scratch:SI 3 "=X,X,&h"))]
6926 { return sparc_v8plus_shift (operands, insn, "sllx"); }
6927 [(set_attr "type" "multi")
6928 (set_attr "length" "5,5,6")])
6930 ;; Optimize (1LL<<x)-1
6931 ;; XXX this also needs to be fixed to handle equal subregs
6932 ;; XXX first before we could re-enable it.
6934 ; [(set (match_operand:DI 0 "register_operand" "=h")
6935 ; (plus:DI (ashift:DI (const_int 1)
6936 ; (match_operand:SI 1 "arith_operand" "rI"))
6938 ; "0 && TARGET_V8PLUS"
6940 ; if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[0]))
6941 ; return "mov\t1, %L0\;sllx\t%L0, %1, %L0\;sub\t%L0, 1, %L0\;srlx\t%L0, 32, %H0";
6942 ; return "mov\t1, %H0\;sllx\t%H0, %1, %L0\;sub\t%L0, 1, %L0\;srlx\t%L0, 32, %H0";
6944 ; [(set_attr "type" "multi")
6945 ; (set_attr "length" "4")])
6947 (define_insn "*cmp_cc_ashift_1"
6948 [(set (reg:CC_NOOV 100)
6949 (compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r")
6953 "addcc\t%0, %0, %%g0"
6954 [(set_attr "type" "compare")])
6956 (define_insn "*cmp_cc_set_ashift_1"
6957 [(set (reg:CC_NOOV 100)
6958 (compare:CC_NOOV (ashift:SI (match_operand:SI 1 "register_operand" "r")
6961 (set (match_operand:SI 0 "register_operand" "=r")
6962 (ashift:SI (match_dup 1) (const_int 1)))]
6965 [(set_attr "type" "compare")])
6967 (define_insn "ashrsi3"
6968 [(set (match_operand:SI 0 "register_operand" "=r")
6969 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6970 (match_operand:SI 2 "arith_operand" "rI")))]
6973 [(set_attr "type" "shift")])
6975 (define_insn "*ashrsi3_extend"
6976 [(set (match_operand:DI 0 "register_operand" "=r")
6977 (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6978 (match_operand:SI 2 "arith_operand" "r"))))]
6981 [(set_attr "type" "shift")])
6983 ;; This handles the case as above, but with constant shift instead of
6984 ;; register. Combiner "simplifies" it for us a little bit though.
6985 (define_insn "*ashrsi3_extend2"
6986 [(set (match_operand:DI 0 "register_operand" "=r")
6987 (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
6989 (match_operand:SI 2 "small_int_or_double" "n")))]
6991 && ((GET_CODE (operands[2]) == CONST_INT
6992 && INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) < 64)
6993 || (GET_CODE (operands[2]) == CONST_DOUBLE
6994 && !CONST_DOUBLE_HIGH (operands[2])
6995 && CONST_DOUBLE_LOW (operands[2]) >= 32
6996 && CONST_DOUBLE_LOW (operands[2]) < 64))"
6998 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
7000 return "sra\t%1, %2, %0";
7002 [(set_attr "type" "shift")])
7004 (define_expand "ashrdi3"
7005 [(set (match_operand:DI 0 "register_operand" "=r")
7006 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7007 (match_operand:SI 2 "arith_operand" "rI")))]
7008 "TARGET_ARCH64 || TARGET_V8PLUS"
7010 if (! TARGET_ARCH64)
7012 if (GET_CODE (operands[2]) == CONST_INT)
7013 FAIL; /* prefer generic code in this case */
7014 emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2]));
7020 [(set (match_operand:DI 0 "register_operand" "=r")
7021 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7022 (match_operand:SI 2 "arith_operand" "rI")))]
7025 [(set_attr "type" "shift")])
7028 (define_insn "ashrdi3_v8plus"
7029 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
7030 (ashiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
7031 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
7032 (clobber (match_scratch:SI 3 "=X,X,&h"))]
7034 { return sparc_v8plus_shift (operands, insn, "srax"); }
7035 [(set_attr "type" "multi")
7036 (set_attr "length" "5,5,6")])
7038 (define_insn "lshrsi3"
7039 [(set (match_operand:SI 0 "register_operand" "=r")
7040 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
7041 (match_operand:SI 2 "arith_operand" "rI")))]
7044 [(set_attr "type" "shift")])
7046 ;; This handles the case where
7047 ;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
7048 ;; but combiner "simplifies" it for us.
7049 (define_insn "*lshrsi3_extend"
7050 [(set (match_operand:DI 0 "register_operand" "=r")
7051 (and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
7052 (match_operand:SI 2 "arith_operand" "r")) 0)
7053 (match_operand 3 "" "")))]
7055 && ((GET_CODE (operands[3]) == CONST_DOUBLE
7056 && CONST_DOUBLE_HIGH (operands[3]) == 0
7057 && CONST_DOUBLE_LOW (operands[3]) == 0xffffffff)
7058 || (HOST_BITS_PER_WIDE_INT >= 64
7059 && GET_CODE (operands[3]) == CONST_INT
7060 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff))"
7062 [(set_attr "type" "shift")])
7064 ;; This handles the case where
7065 ;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32))
7066 ;; but combiner "simplifies" it for us.
7067 (define_insn "*lshrsi3_extend2"
7068 [(set (match_operand:DI 0 "register_operand" "=r")
7069 (zero_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
7070 (match_operand 2 "small_int_or_double" "n")
7073 && ((GET_CODE (operands[2]) == CONST_INT
7074 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32)
7075 || (GET_CODE (operands[2]) == CONST_DOUBLE
7076 && CONST_DOUBLE_HIGH (operands[2]) == 0
7077 && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
7079 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
7081 return "srl\t%1, %2, %0";
7083 [(set_attr "type" "shift")])
7085 (define_expand "lshrdi3"
7086 [(set (match_operand:DI 0 "register_operand" "=r")
7087 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
7088 (match_operand:SI 2 "arith_operand" "rI")))]
7089 "TARGET_ARCH64 || TARGET_V8PLUS"
7091 if (! TARGET_ARCH64)
7093 if (GET_CODE (operands[2]) == CONST_INT)
7095 emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2]));
7101 [(set (match_operand:DI 0 "register_operand" "=r")
7102 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
7103 (match_operand:SI 2 "arith_operand" "rI")))]
7106 [(set_attr "type" "shift")])
7109 (define_insn "lshrdi3_v8plus"
7110 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
7111 (lshiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
7112 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
7113 (clobber (match_scratch:SI 3 "=X,X,&h"))]
7115 { return sparc_v8plus_shift (operands, insn, "srlx"); }
7116 [(set_attr "type" "multi")
7117 (set_attr "length" "5,5,6")])
7120 [(set (match_operand:SI 0 "register_operand" "=r")
7121 (ashiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
7123 (match_operand:SI 2 "small_int_or_double" "n")))]
7125 && ((GET_CODE (operands[2]) == CONST_INT
7126 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32)
7127 || (GET_CODE (operands[2]) == CONST_DOUBLE
7128 && !CONST_DOUBLE_HIGH (operands[2])
7129 && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
7131 operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
7133 return "srax\t%1, %2, %0";
7135 [(set_attr "type" "shift")])
7138 [(set (match_operand:SI 0 "register_operand" "=r")
7139 (lshiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7141 (match_operand:SI 2 "small_int_or_double" "n")))]
7143 && ((GET_CODE (operands[2]) == CONST_INT
7144 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32)
7145 || (GET_CODE (operands[2]) == CONST_DOUBLE
7146 && !CONST_DOUBLE_HIGH (operands[2])
7147 && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))"
7149 operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
7151 return "srlx\t%1, %2, %0";
7153 [(set_attr "type" "shift")])
7156 [(set (match_operand:SI 0 "register_operand" "=r")
7157 (ashiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7158 (match_operand:SI 2 "small_int_or_double" "n")) 4)
7159 (match_operand:SI 3 "small_int_or_double" "n")))]
7161 && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT
7162 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
7163 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
7164 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
7166 operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
7168 return "srax\t%1, %2, %0";
7170 [(set_attr "type" "shift")])
7173 [(set (match_operand:SI 0 "register_operand" "=r")
7174 (lshiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
7175 (match_operand:SI 2 "small_int_or_double" "n")) 4)
7176 (match_operand:SI 3 "small_int_or_double" "n")))]
7178 && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT
7179 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
7180 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
7181 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
7183 operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
7185 return "srlx\t%1, %2, %0";
7187 [(set_attr "type" "shift")])
7189 ;; Unconditional and other jump instructions
7190 ;; On the SPARC, by setting the annul bit on an unconditional branch, the
7191 ;; following insn is never executed. This saves us a nop. Dbx does not
7192 ;; handle such branches though, so we only use them when optimizing.
7194 [(set (pc) (label_ref (match_operand 0 "" "")))]
7197 /* TurboSPARC is reported to have problems with
7200 i.e. an empty loop with the annul bit set. The workaround is to use
7204 if (! TARGET_V9 && flag_delayed_branch
7205 && (INSN_ADDRESSES (INSN_UID (operands[0]))
7206 == INSN_ADDRESSES (INSN_UID (insn))))
7209 return TARGET_V9 ? "ba%*,pt\t%%xcc, %l0%(" : "b%*\t%l0%(";
7211 [(set_attr "type" "uncond_branch")])
7213 (define_expand "tablejump"
7214 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
7215 (use (label_ref (match_operand 1 "" "")))])]
7218 if (GET_MODE (operands[0]) != CASE_VECTOR_MODE)
7221 /* In pic mode, our address differences are against the base of the
7222 table. Add that base value back in; CSE ought to be able to combine
7223 the two address loads. */
7227 tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
7229 if (CASE_VECTOR_MODE != Pmode)
7230 tmp2 = gen_rtx_SIGN_EXTEND (Pmode, tmp2);
7231 tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
7232 operands[0] = memory_address (Pmode, tmp);
7236 (define_insn "*tablejump_sp32"
7237 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
7238 (use (label_ref (match_operand 1 "" "")))]
7241 [(set_attr "type" "uncond_branch")])
7243 (define_insn "*tablejump_sp64"
7244 [(set (pc) (match_operand:DI 0 "address_operand" "p"))
7245 (use (label_ref (match_operand 1 "" "")))]
7248 [(set_attr "type" "uncond_branch")])
7250 ;; This pattern recognizes the "instruction" that appears in
7251 ;; a function call that wants a structure value,
7252 ;; to inform the called function if compiled with Sun CC.
7253 ;(define_insn "*unimp_insn"
7254 ; [(match_operand:SI 0 "immediate_operand" "")]
7255 ; "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) > 0"
7257 ; [(set_attr "type" "marker")])
7259 ;;- jump to subroutine
7260 (define_expand "call"
7261 ;; Note that this expression is not used for generating RTL.
7262 ;; All the RTL is generated explicitly below.
7263 [(call (match_operand 0 "call_operand" "")
7264 (match_operand 3 "" "i"))]
7265 ;; operands[2] is next_arg_register
7266 ;; operands[3] is struct_value_size_rtx.
7269 rtx fn_rtx, nregs_rtx;
7271 if (GET_MODE (operands[0]) != FUNCTION_MODE)
7274 if (GET_CODE (XEXP (operands[0], 0)) == LABEL_REF)
7276 /* This is really a PIC sequence. We want to represent
7277 it as a funny jump so its delay slots can be filled.
7279 ??? But if this really *is* a CALL, will not it clobber the
7280 call-clobbered registers? We lose this if it is a JUMP_INSN.
7281 Why cannot we have delay slots filled if it were a CALL? */
7283 if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
7288 gen_rtx_SET (VOIDmode, pc_rtx, XEXP (operands[0], 0)),
7290 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
7296 gen_rtx_SET (VOIDmode, pc_rtx, XEXP (operands[0], 0)),
7297 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
7301 fn_rtx = operands[0];
7303 /* Count the number of parameter registers being used by this call.
7304 if that argument is NULL, it means we are using them all, which
7305 means 6 on the sparc. */
7308 nregs_rtx = GEN_INT (REGNO (operands[2]) - 8);
7310 nregs_rtx = GEN_INT (6);
7312 nregs_rtx = const0_rtx;
7315 if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0)
7319 gen_rtvec (3, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx),
7321 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
7326 gen_rtvec (2, gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx),
7327 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
7331 /* If this call wants a structure value,
7332 emit an unimp insn to let the called function know about this. */
7333 if (! TARGET_ARCH64 && INTVAL (operands[3]) > 0)
7335 rtx insn = emit_insn (operands[3]);
7336 SCHED_GROUP_P (insn) = 1;
7343 ;; We can't use the same pattern for these two insns, because then registers
7344 ;; in the address may not be properly reloaded.
7346 (define_insn "*call_address_sp32"
7347 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
7348 (match_operand 1 "" ""))
7349 (clobber (reg:SI 15))]
7350 ;;- Do not use operand 1 for most machines.
7353 [(set_attr "type" "call")])
7355 (define_insn "*call_symbolic_sp32"
7356 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
7357 (match_operand 1 "" ""))
7358 (clobber (reg:SI 15))]
7359 ;;- Do not use operand 1 for most machines.
7362 [(set_attr "type" "call")])
7364 (define_insn "*call_address_sp64"
7365 [(call (mem:DI (match_operand:DI 0 "address_operand" "p"))
7366 (match_operand 1 "" ""))
7367 (clobber (reg:DI 15))]
7368 ;;- Do not use operand 1 for most machines.
7371 [(set_attr "type" "call")])
7373 (define_insn "*call_symbolic_sp64"
7374 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "s"))
7375 (match_operand 1 "" ""))
7376 (clobber (reg:DI 15))]
7377 ;;- Do not use operand 1 for most machines.
7380 [(set_attr "type" "call")])
7382 ;; This is a call that wants a structure value.
7383 ;; There is no such critter for v9 (??? we may need one anyway).
7384 (define_insn "*call_address_struct_value_sp32"
7385 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
7386 (match_operand 1 "" ""))
7387 (match_operand 2 "immediate_operand" "")
7388 (clobber (reg:SI 15))]
7389 ;;- Do not use operand 1 for most machines.
7390 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0"
7391 "call\t%a0, %1\n\tnop\n\tunimp\t%2"
7392 [(set_attr "type" "call_no_delay_slot")
7393 (set_attr "length" "3")])
7395 ;; This is a call that wants a structure value.
7396 ;; There is no such critter for v9 (??? we may need one anyway).
7397 (define_insn "*call_symbolic_struct_value_sp32"
7398 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
7399 (match_operand 1 "" ""))
7400 (match_operand 2 "immediate_operand" "")
7401 (clobber (reg:SI 15))]
7402 ;;- Do not use operand 1 for most machines.
7403 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0"
7404 "call\t%a0, %1\n\tnop\n\tunimp\t%2"
7405 [(set_attr "type" "call_no_delay_slot")
7406 (set_attr "length" "3")])
7408 ;; This is a call that may want a structure value. This is used for
7410 (define_insn "*call_address_untyped_struct_value_sp32"
7411 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
7412 (match_operand 1 "" ""))
7413 (match_operand 2 "immediate_operand" "")
7414 (clobber (reg:SI 15))]
7415 ;;- Do not use operand 1 for most machines.
7416 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
7417 "call\t%a0, %1\n\tnop\n\tnop"
7418 [(set_attr "type" "call_no_delay_slot")
7419 (set_attr "length" "3")])
7421 ;; This is a call that wants a structure value.
7422 (define_insn "*call_symbolic_untyped_struct_value_sp32"
7423 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
7424 (match_operand 1 "" ""))
7425 (match_operand 2 "immediate_operand" "")
7426 (clobber (reg:SI 15))]
7427 ;;- Do not use operand 1 for most machines.
7428 "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
7429 "call\t%a0, %1\n\tnop\n\tnop"
7430 [(set_attr "type" "call_no_delay_slot")
7431 (set_attr "length" "3")])
7433 (define_expand "call_value"
7434 ;; Note that this expression is not used for generating RTL.
7435 ;; All the RTL is generated explicitly below.
7436 [(set (match_operand 0 "register_operand" "=rf")
7437 (call (match_operand 1 "" "")
7438 (match_operand 4 "" "")))]
7439 ;; operand 2 is stack_size_rtx
7440 ;; operand 3 is next_arg_register
7443 rtx fn_rtx, nregs_rtx;
7446 if (GET_MODE (operands[1]) != FUNCTION_MODE)
7449 fn_rtx = operands[1];
7453 nregs_rtx = GEN_INT (REGNO (operands[3]) - 8);
7455 nregs_rtx = GEN_INT (6);
7457 nregs_rtx = const0_rtx;
7461 gen_rtx_SET (VOIDmode, operands[0],
7462 gen_rtx_CALL (VOIDmode, fn_rtx, nregs_rtx)),
7463 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)));
7465 emit_call_insn (gen_rtx_PARALLEL (VOIDmode, vec));
7470 (define_insn "*call_value_address_sp32"
7471 [(set (match_operand 0 "" "=rf")
7472 (call (mem:SI (match_operand:SI 1 "address_operand" "p"))
7473 (match_operand 2 "" "")))
7474 (clobber (reg:SI 15))]
7475 ;;- Do not use operand 2 for most machines.
7478 [(set_attr "type" "call")])
7480 (define_insn "*call_value_symbolic_sp32"
7481 [(set (match_operand 0 "" "=rf")
7482 (call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
7483 (match_operand 2 "" "")))
7484 (clobber (reg:SI 15))]
7485 ;;- Do not use operand 2 for most machines.
7488 [(set_attr "type" "call")])
7490 (define_insn "*call_value_address_sp64"
7491 [(set (match_operand 0 "" "")
7492 (call (mem:DI (match_operand:DI 1 "address_operand" "p"))
7493 (match_operand 2 "" "")))
7494 (clobber (reg:DI 15))]
7495 ;;- Do not use operand 2 for most machines.
7498 [(set_attr "type" "call")])
7500 (define_insn "*call_value_symbolic_sp64"
7501 [(set (match_operand 0 "" "")
7502 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "s"))
7503 (match_operand 2 "" "")))
7504 (clobber (reg:DI 15))]
7505 ;;- Do not use operand 2 for most machines.
7508 [(set_attr "type" "call")])
7510 (define_expand "untyped_call"
7511 [(parallel [(call (match_operand 0 "" "")
7513 (match_operand 1 "" "")
7514 (match_operand 2 "" "")])]
7519 /* Pass constm1 to indicate that it may expect a structure value, but
7520 we don't know what size it is. */
7521 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, constm1_rtx));
7523 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7525 rtx set = XVECEXP (operands[2], 0, i);
7526 emit_move_insn (SET_DEST (set), SET_SRC (set));
7529 /* The optimizer does not know that the call sets the function value
7530 registers we stored in the result block. We avoid problems by
7531 claiming that all hard registers are used and clobbered at this
7533 emit_insn (gen_blockage ());
7539 (define_expand "sibcall"
7540 [(parallel [(call (match_operand 0 "call_operand" "") (const_int 0))
7545 (define_insn "*sibcall_symbolic_sp32"
7546 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
7547 (match_operand 1 "" ""))
7550 "* return output_sibcall(insn, operands[0]);"
7551 [(set_attr "type" "sibcall")])
7553 (define_insn "*sibcall_symbolic_sp64"
7554 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "s"))
7555 (match_operand 1 "" ""))
7558 "* return output_sibcall(insn, operands[0]);"
7559 [(set_attr "type" "sibcall")])
7561 (define_expand "sibcall_value"
7562 [(parallel [(set (match_operand 0 "register_operand" "=rf")
7563 (call (match_operand 1 "" "") (const_int 0)))
7568 (define_insn "*sibcall_value_symbolic_sp32"
7569 [(set (match_operand 0 "" "=rf")
7570 (call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
7571 (match_operand 2 "" "")))
7574 "* return output_sibcall(insn, operands[1]);"
7575 [(set_attr "type" "sibcall")])
7577 (define_insn "*sibcall_value_symbolic_sp64"
7578 [(set (match_operand 0 "" "")
7579 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "s"))
7580 (match_operand 2 "" "")))
7583 "* return output_sibcall(insn, operands[1]);"
7584 [(set_attr "type" "sibcall")])
7586 (define_expand "sibcall_epilogue"
7591 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7592 ;; all of memory. This blocks insns from being moved across this point.
7594 (define_insn "blockage"
7595 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7598 [(set_attr "length" "0")])
7600 ;; Prepare to return any type including a structure value.
7602 (define_expand "untyped_return"
7603 [(match_operand:BLK 0 "memory_operand" "")
7604 (match_operand 1 "" "")]
7607 rtx valreg1 = gen_rtx_REG (DImode, 24);
7608 rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
7609 rtx result = operands[0];
7611 if (! TARGET_ARCH64)
7613 rtx rtnreg = gen_rtx_REG (SImode, (current_function_uses_only_leaf_regs
7615 rtx value = gen_reg_rtx (SImode);
7617 /* Fetch the instruction where we will return to and see if it's an unimp
7618 instruction (the most significant 10 bits will be zero). If so,
7619 update the return address to skip the unimp instruction. */
7620 emit_move_insn (value,
7621 gen_rtx_MEM (SImode, plus_constant (rtnreg, 8)));
7622 emit_insn (gen_lshrsi3 (value, value, GEN_INT (22)));
7623 emit_insn (gen_update_return (rtnreg, value));
7626 /* Reload the function value registers. */
7627 emit_move_insn (valreg1, adjust_address (result, DImode, 0));
7628 emit_move_insn (valreg2,
7629 adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8));
7631 /* Put USE insns before the return. */
7632 emit_insn (gen_rtx_USE (VOIDmode, valreg1));
7633 emit_insn (gen_rtx_USE (VOIDmode, valreg2));
7635 /* Construct the return. */
7636 expand_null_return ();
7641 ;; This is a bit of a hack. We're incrementing a fixed register (%i7),
7642 ;; and parts of the compiler don't want to believe that the add is needed.
7644 (define_insn "update_return"
7645 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
7646 (match_operand:SI 1 "register_operand" "r")] UNSPEC_UPDATE_RETURN)]
7648 "cmp\t%1, 0\;be,a\t.+8\;add\t%0, 4, %0"
7649 [(set_attr "type" "multi")
7650 (set_attr "length" "3")])
7657 (define_expand "indirect_jump"
7658 [(set (pc) (match_operand 0 "address_operand" "p"))]
7662 (define_insn "*branch_sp32"
7663 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
7666 [(set_attr "type" "uncond_branch")])
7668 (define_insn "*branch_sp64"
7669 [(set (pc) (match_operand:DI 0 "address_operand" "p"))]
7672 [(set_attr "type" "uncond_branch")])
7674 ;; ??? Doesn't work with -mflat.
7675 (define_expand "nonlocal_goto"
7676 [(match_operand:SI 0 "general_operand" "")
7677 (match_operand:SI 1 "general_operand" "")
7678 (match_operand:SI 2 "general_operand" "")
7679 (match_operand:SI 3 "" "")]
7683 rtx chain = operands[0];
7685 rtx lab = operands[1];
7686 rtx stack = operands[2];
7687 rtx fp = operands[3];
7690 /* Trap instruction to flush all the register windows. */
7691 emit_insn (gen_flush_register_windows ());
7693 /* Load the fp value for the containing fn into %fp. This is needed
7694 because STACK refers to %fp. Note that virtual register instantiation
7695 fails if the virtual %fp isn't set from a register. */
7696 if (GET_CODE (fp) != REG)
7697 fp = force_reg (Pmode, fp);
7698 emit_move_insn (virtual_stack_vars_rtx, fp);
7700 /* Find the containing function's current nonlocal goto handler,
7701 which will do any cleanups and then jump to the label. */
7702 labreg = gen_rtx_REG (Pmode, 8);
7703 emit_move_insn (labreg, lab);
7705 /* Restore %fp from stack pointer value for containing function.
7706 The restore insn that follows will move this to %sp,
7707 and reload the appropriate value into %fp. */
7708 emit_move_insn (hard_frame_pointer_rtx, stack);
7710 /* USE of frame_pointer_rtx added for consistency; not clear if
7712 /*emit_insn (gen_rtx_USE (VOIDmode, frame_pointer_rtx));*/
7713 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7716 /* Return, restoring reg window and jumping to goto handler. */
7717 if (TARGET_V9 && GET_CODE (chain) == CONST_INT
7718 && ! (INTVAL (chain) & ~(HOST_WIDE_INT)0xffffffff))
7720 emit_jump_insn (gen_goto_handler_and_restore_v9 (labreg,
7726 /* Put in the static chain register the nonlocal label address. */
7727 emit_move_insn (static_chain_rtx, chain);
7730 emit_insn (gen_rtx_USE (VOIDmode, static_chain_rtx));
7731 emit_jump_insn (gen_goto_handler_and_restore (labreg));
7736 ;; Special trap insn to flush register windows.
7737 (define_insn "flush_register_windows"
7738 [(unspec_volatile [(const_int 0)] UNSPECV_FLUSHW)]
7740 { return TARGET_V9 ? "flushw" : "ta\t3"; }
7741 [(set_attr "type" "flushw")])
7743 (define_insn "goto_handler_and_restore"
7744 [(unspec_volatile [(match_operand 0 "register_operand" "=r")] UNSPECV_GOTO)]
7745 "GET_MODE (operands[0]) == Pmode"
7746 "jmp\t%0+0\n\trestore"
7747 [(set_attr "type" "multi")
7748 (set_attr "length" "2")])
7750 ;;(define_insn "goto_handler_and_restore_v9"
7751 ;; [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r,r")
7752 ;; (match_operand:SI 1 "register_operand" "=r,r")
7753 ;; (match_operand:SI 2 "const_int_operand" "I,n")] UNSPECV_GOTO_V9)]
7754 ;; "TARGET_V9 && ! TARGET_ARCH64"
7756 ;; return\t%0+0\n\tmov\t%2, %Y1
7757 ;; sethi\t%%hi(%2), %1\n\treturn\t%0+0\n\tor\t%Y1, %%lo(%2), %Y1"
7758 ;; [(set_attr "type" "multi")
7759 ;; (set_attr "length" "2,3")])
7761 ;;(define_insn "*goto_handler_and_restore_v9_sp64"
7762 ;; [(unspec_volatile [(match_operand:DI 0 "register_operand" "=r,r")
7763 ;; (match_operand:DI 1 "register_operand" "=r,r")
7764 ;; (match_operand:SI 2 "const_int_operand" "I,n")] UNSPECV_GOTO_V9)]
7765 ;; "TARGET_V9 && TARGET_ARCH64"
7767 ;; return\t%0+0\n\tmov\t%2, %Y1
7768 ;; sethi\t%%hi(%2), %1\n\treturn\t%0+0\n\tor\t%Y1, %%lo(%2), %Y1"
7769 ;; [(set_attr "type" "multi")
7770 ;; (set_attr "length" "2,3")])
7772 ;; For __builtin_setjmp we need to flush register windows iff the function
7773 ;; calls alloca as well, because otherwise the register window might be
7774 ;; saved after %sp adjustment and thus setjmp would crash
7775 (define_expand "builtin_setjmp_setup"
7776 [(match_operand 0 "register_operand" "r")]
7779 emit_insn (gen_do_builtin_setjmp_setup ());
7783 (define_insn "do_builtin_setjmp_setup"
7784 [(unspec_volatile [(const_int 0)] UNSPECV_SETJMP)]
7787 if (! current_function_calls_alloca)
7789 if (! TARGET_V9 || TARGET_FLAT)
7791 fputs ("\tflushw\n", asm_out_file);
7793 fprintf (asm_out_file, "\tst%c\t%%l7, [%%sp+%d]\n",
7794 TARGET_ARCH64 ? 'x' : 'w',
7795 SPARC_STACK_BIAS + 7 * UNITS_PER_WORD);
7796 fprintf (asm_out_file, "\tst%c\t%%fp, [%%sp+%d]\n",
7797 TARGET_ARCH64 ? 'x' : 'w',
7798 SPARC_STACK_BIAS + 14 * UNITS_PER_WORD);
7799 fprintf (asm_out_file, "\tst%c\t%%i7, [%%sp+%d]\n",
7800 TARGET_ARCH64 ? 'x' : 'w',
7801 SPARC_STACK_BIAS + 15 * UNITS_PER_WORD);
7804 [(set_attr "type" "multi")
7805 (set (attr "length")
7806 (cond [(eq_attr "current_function_calls_alloca" "false")
7808 (eq_attr "flat" "true")
7810 (eq_attr "isa" "!v9")
7812 (eq_attr "pic" "true")
7813 (const_int 4)] (const_int 3)))])
7815 ;; Pattern for use after a setjmp to store FP and the return register
7816 ;; into the stack area.
7818 (define_expand "setjmp"
7823 emit_insn (gen_setjmp_64 ());
7825 emit_insn (gen_setjmp_32 ());
7829 (define_expand "setjmp_32"
7830 [(set (mem:SI (plus:SI (reg:SI 14) (const_int 56))) (match_dup 0))
7831 (set (mem:SI (plus:SI (reg:SI 14) (const_int 60))) (reg:SI 31))]
7833 { operands[0] = frame_pointer_rtx; })
7835 (define_expand "setjmp_64"
7836 [(set (mem:DI (plus:DI (reg:DI 14) (const_int 112))) (match_dup 0))
7837 (set (mem:DI (plus:DI (reg:DI 14) (const_int 120))) (reg:DI 31))]
7839 { operands[0] = frame_pointer_rtx; })
7841 ;; Special pattern for the FLUSH instruction.
7843 ; We do SImode and DImode versions of this to quiet down genrecog's complaints
7844 ; of the define_insn otherwise missing a mode. We make "flush", aka
7845 ; gen_flush, the default one since sparc_initialize_trampoline uses
7846 ; it on SImode mem values.
7848 (define_insn "flush"
7849 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
7851 { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
7852 [(set_attr "type" "iflush")])
7854 (define_insn "flushdi"
7855 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_FLUSH)]
7857 { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; }
7858 [(set_attr "type" "iflush")])
7863 ;; The scan instruction searches from the most significant bit while ffs
7864 ;; searches from the least significant bit. The bit index and treatment of
7865 ;; zero also differ. It takes at least 7 instructions to get the proper
7866 ;; result. Here is an obvious 8 instruction sequence.
7869 (define_insn "ffssi2"
7870 [(set (match_operand:SI 0 "register_operand" "=&r")
7871 (ffs:SI (match_operand:SI 1 "register_operand" "r")))
7872 (clobber (match_scratch:SI 2 "=&r"))]
7873 "TARGET_SPARCLITE || TARGET_SPARCLET"
7875 return "sub\t%%g0, %1, %0\;and\t%0, %1, %0\;scan\t%0, 0, %0\;mov\t32, %2\;sub\t%2, %0, %0\;sra\t%0, 31, %2\;and\t%2, 31, %2\;add\t%2, %0, %0";
7877 [(set_attr "type" "multi")
7878 (set_attr "length" "8")])
7880 ;; ??? This should be a define expand, so that the extra instruction have
7881 ;; a chance of being optimized away.
7883 ;; Disabled because none of the UltraSPARCs implement popc. The HAL R1
7884 ;; does, but no one uses that and we don't have a switch for it.
7886 ;(define_insn "ffsdi2"
7887 ; [(set (match_operand:DI 0 "register_operand" "=&r")
7888 ; (ffs:DI (match_operand:DI 1 "register_operand" "r")))
7889 ; (clobber (match_scratch:DI 2 "=&r"))]
7891 ; "neg\t%1, %2\;xnor\t%1, %2, %2\;popc\t%2, %0\;movzr\t%1, 0, %0"
7892 ; [(set_attr "type" "multi")
7893 ; (set_attr "length" "4")])
7897 ;; Peepholes go at the end.
7899 ;; Optimize consecutive loads or stores into ldd and std when possible.
7900 ;; The conditions in which we do this are very restricted and are
7901 ;; explained in the code for {registers,memory}_ok_for_ldd functions.
7904 [(set (match_operand:SI 0 "memory_operand" "")
7906 (set (match_operand:SI 1 "memory_operand" "")
7909 && mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)"
7912 "operands[0] = widen_memory_access (operands[0], DImode, 0);")
7915 [(set (match_operand:SI 0 "memory_operand" "")
7917 (set (match_operand:SI 1 "memory_operand" "")
7920 && mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)"
7923 "operands[1] = widen_memory_access (operands[1], DImode, 0);")
7926 [(set (match_operand:SI 0 "register_operand" "")
7927 (match_operand:SI 1 "memory_operand" ""))
7928 (set (match_operand:SI 2 "register_operand" "")
7929 (match_operand:SI 3 "memory_operand" ""))]
7930 "registers_ok_for_ldd_peep (operands[0], operands[2])
7931 && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
7934 "operands[1] = widen_memory_access (operands[1], DImode, 0);
7935 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));")
7938 [(set (match_operand:SI 0 "memory_operand" "")
7939 (match_operand:SI 1 "register_operand" ""))
7940 (set (match_operand:SI 2 "memory_operand" "")
7941 (match_operand:SI 3 "register_operand" ""))]
7942 "registers_ok_for_ldd_peep (operands[1], operands[3])
7943 && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
7946 "operands[0] = widen_memory_access (operands[0], DImode, 0);
7947 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
7950 [(set (match_operand:SF 0 "register_operand" "")
7951 (match_operand:SF 1 "memory_operand" ""))
7952 (set (match_operand:SF 2 "register_operand" "")
7953 (match_operand:SF 3 "memory_operand" ""))]
7954 "registers_ok_for_ldd_peep (operands[0], operands[2])
7955 && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
7958 "operands[1] = widen_memory_access (operands[1], DFmode, 0);
7959 operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));")
7962 [(set (match_operand:SF 0 "memory_operand" "")
7963 (match_operand:SF 1 "register_operand" ""))
7964 (set (match_operand:SF 2 "memory_operand" "")
7965 (match_operand:SF 3 "register_operand" ""))]
7966 "registers_ok_for_ldd_peep (operands[1], operands[3])
7967 && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
7970 "operands[0] = widen_memory_access (operands[0], DFmode, 0);
7971 operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));")
7974 [(set (match_operand:SI 0 "register_operand" "")
7975 (match_operand:SI 1 "memory_operand" ""))
7976 (set (match_operand:SI 2 "register_operand" "")
7977 (match_operand:SI 3 "memory_operand" ""))]
7978 "registers_ok_for_ldd_peep (operands[2], operands[0])
7979 && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
7982 "operands[3] = widen_memory_access (operands[3], DImode, 0);
7983 operands[2] = gen_rtx_REG (DImode, REGNO (operands[2]));")
7986 [(set (match_operand:SI 0 "memory_operand" "")
7987 (match_operand:SI 1 "register_operand" ""))
7988 (set (match_operand:SI 2 "memory_operand" "")
7989 (match_operand:SI 3 "register_operand" ""))]
7990 "registers_ok_for_ldd_peep (operands[3], operands[1])
7991 && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
7994 "operands[2] = widen_memory_access (operands[2], DImode, 0);
7995 operands[3] = gen_rtx_REG (DImode, REGNO (operands[3]));
7999 [(set (match_operand:SF 0 "register_operand" "")
8000 (match_operand:SF 1 "memory_operand" ""))
8001 (set (match_operand:SF 2 "register_operand" "")
8002 (match_operand:SF 3 "memory_operand" ""))]
8003 "registers_ok_for_ldd_peep (operands[2], operands[0])
8004 && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
8007 "operands[3] = widen_memory_access (operands[3], DFmode, 0);
8008 operands[2] = gen_rtx_REG (DFmode, REGNO (operands[2]));")
8011 [(set (match_operand:SF 0 "memory_operand" "")
8012 (match_operand:SF 1 "register_operand" ""))
8013 (set (match_operand:SF 2 "memory_operand" "")
8014 (match_operand:SF 3 "register_operand" ""))]
8015 "registers_ok_for_ldd_peep (operands[3], operands[1])
8016 && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
8019 "operands[2] = widen_memory_access (operands[2], DFmode, 0);
8020 operands[3] = gen_rtx_REG (DFmode, REGNO (operands[3]));")
8022 ;; Optimize the case of following a reg-reg move with a test
8023 ;; of reg just moved. Don't allow floating point regs for operand 0 or 1.
8024 ;; This can result from a float to fix conversion.
8027 [(set (match_operand:SI 0 "register_operand" "")
8028 (match_operand:SI 1 "register_operand" ""))
8030 (compare:CC (match_operand:SI 2 "register_operand" "")
8032 "(rtx_equal_p (operands[2], operands[0])
8033 || rtx_equal_p (operands[2], operands[1]))
8034 && ! SPARC_FP_REG_P (REGNO (operands[0]))
8035 && ! SPARC_FP_REG_P (REGNO (operands[1]))"
8036 [(parallel [(set (match_dup 0) (match_dup 1))
8038 (compare:CC (match_dup 1) (const_int 0)))])]
8042 [(set (match_operand:DI 0 "register_operand" "")
8043 (match_operand:DI 1 "register_operand" ""))
8045 (compare:CCX (match_operand:DI 2 "register_operand" "")
8048 && (rtx_equal_p (operands[2], operands[0])
8049 || rtx_equal_p (operands[2], operands[1]))
8050 && ! SPARC_FP_REG_P (REGNO (operands[0]))
8051 && ! SPARC_FP_REG_P (REGNO (operands[1]))"
8052 [(parallel [(set (match_dup 0) (match_dup 1))
8054 (compare:CCX (match_dup 1) (const_int 0)))])]
8057 ;; Return peepholes. These are generated by sparc_nonflat_function_epilogue
8058 ;; who then immediately calls final_scan_insn.
8060 (define_insn "*return_qi"
8061 [(set (match_operand:QI 0 "restore_operand" "")
8062 (match_operand:QI 1 "arith_operand" "rI"))
8064 "sparc_emitting_epilogue"
8066 if (! TARGET_ARCH64 && current_function_returns_struct)
8067 return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0";
8068 else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
8069 || IN_OR_GLOBAL_P (operands[1])))
8070 return "return\t%%i7+8\n\tmov\t%Y1, %Y0";
8072 return "ret\n\trestore %%g0, %1, %Y0";
8074 [(set_attr "type" "multi")
8075 (set_attr "length" "2")])
8077 (define_insn "*return_hi"
8078 [(set (match_operand:HI 0 "restore_operand" "")
8079 (match_operand:HI 1 "arith_operand" "rI"))
8081 "sparc_emitting_epilogue"
8083 if (! TARGET_ARCH64 && current_function_returns_struct)
8084 return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0";
8085 else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
8086 || IN_OR_GLOBAL_P (operands[1])))
8087 return "return\t%%i7+8\n\tmov\t%Y1, %Y0";
8089 return "ret\;restore %%g0, %1, %Y0";
8091 [(set_attr "type" "multi")
8092 (set_attr "length" "2")])
8094 (define_insn "*return_si"
8095 [(set (match_operand:SI 0 "restore_operand" "")
8096 (match_operand:SI 1 "arith_operand" "rI"))
8098 "sparc_emitting_epilogue"
8100 if (! TARGET_ARCH64 && current_function_returns_struct)
8101 return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0";
8102 else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT
8103 || IN_OR_GLOBAL_P (operands[1])))
8104 return "return\t%%i7+8\n\tmov\t%Y1, %Y0";
8106 return "ret\;restore %%g0, %1, %Y0";
8108 [(set_attr "type" "multi")
8109 (set_attr "length" "2")])
8111 (define_insn "*return_sf_no_fpu"
8112 [(set (match_operand:SF 0 "restore_operand" "=r")
8113 (match_operand:SF 1 "register_operand" "r"))
8115 "sparc_emitting_epilogue"
8117 if (! TARGET_ARCH64 && current_function_returns_struct)
8118 return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0";
8119 else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]))
8120 return "return\t%%i7+8\n\tmov\t%Y1, %Y0";
8122 return "ret\;restore %%g0, %1, %Y0";
8124 [(set_attr "type" "multi")
8125 (set_attr "length" "2")])
8127 (define_insn "*return_df_no_fpu"
8128 [(set (match_operand:DF 0 "restore_operand" "=r")
8129 (match_operand:DF 1 "register_operand" "r"))
8131 "sparc_emitting_epilogue && TARGET_ARCH64"
8133 if (IN_OR_GLOBAL_P (operands[1]))
8134 return "return\t%%i7+8\n\tmov\t%Y1, %Y0";
8136 return "ret\;restore %%g0, %1, %Y0";
8138 [(set_attr "type" "multi")
8139 (set_attr "length" "2")])
8141 (define_insn "*return_addsi"
8142 [(set (match_operand:SI 0 "restore_operand" "")
8143 (plus:SI (match_operand:SI 1 "register_operand" "r")
8144 (match_operand:SI 2 "arith_operand" "rI")))
8146 "sparc_emitting_epilogue"
8148 if (! TARGET_ARCH64 && current_function_returns_struct)
8149 return "jmp\t%%i7+12\n\trestore %r1, %2, %Y0";
8150 /* If operands are global or in registers, can use return */
8151 else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1])
8152 && (GET_CODE (operands[2]) == CONST_INT
8153 || IN_OR_GLOBAL_P (operands[2])))
8154 return "return\t%%i7+8\n\tadd\t%Y1, %Y2, %Y0";
8156 return "ret\;restore %r1, %2, %Y0";
8158 [(set_attr "type" "multi")
8159 (set_attr "length" "2")])
8161 (define_insn "*return_losum_si"
8162 [(set (match_operand:SI 0 "restore_operand" "")
8163 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8164 (match_operand:SI 2 "immediate_operand" "in")))
8166 "sparc_emitting_epilogue && ! TARGET_CM_MEDMID"
8168 if (! TARGET_ARCH64 && current_function_returns_struct)
8169 return "jmp\t%%i7+12\n\trestore %r1, %%lo(%a2), %Y0";
8170 /* If operands are global or in registers, can use return */
8171 else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]))
8172 return "return\t%%i7+8\n\tor\t%Y1, %%lo(%a2), %Y0";
8174 return "ret\;restore %r1, %%lo(%a2), %Y0";
8176 [(set_attr "type" "multi")
8177 (set_attr "length" "2")])
8179 (define_insn "*return_di"
8180 [(set (match_operand:DI 0 "restore_operand" "")
8181 (match_operand:DI 1 "arith_double_operand" "rHI"))
8183 "sparc_emitting_epilogue && TARGET_ARCH64"
8184 "ret\;restore %%g0, %1, %Y0"
8185 [(set_attr "type" "multi")
8186 (set_attr "length" "2")])
8188 (define_insn "*return_adddi"
8189 [(set (match_operand:DI 0 "restore_operand" "")
8190 (plus:DI (match_operand:DI 1 "arith_operand" "%r")
8191 (match_operand:DI 2 "arith_double_operand" "rHI")))
8193 "sparc_emitting_epilogue && TARGET_ARCH64"
8194 "ret\;restore %r1, %2, %Y0"
8195 [(set_attr "type" "multi")
8196 (set_attr "length" "2")])
8198 (define_insn "*return_losum_di"
8199 [(set (match_operand:DI 0 "restore_operand" "")
8200 (lo_sum:DI (match_operand:DI 1 "arith_operand" "%r")
8201 (match_operand:DI 2 "immediate_operand" "in")))
8203 "sparc_emitting_epilogue && TARGET_ARCH64 && ! TARGET_CM_MEDMID"
8204 "ret\;restore %r1, %%lo(%a2), %Y0"
8205 [(set_attr "type" "multi")
8206 (set_attr "length" "2")])
8208 (define_insn "*return_sf"
8210 (match_operand:SF 0 "register_operand" "f"))
8212 "sparc_emitting_epilogue"
8213 "ret\;fmovs\t%0, %%f0"
8214 [(set_attr "type" "multi")
8215 (set_attr "length" "2")])
8217 ;; Now peepholes to do a call followed by a jump.
8220 [(parallel [(set (match_operand 0 "" "")
8221 (call (mem:SI (match_operand:SI 1 "call_operand_address" "ps"))
8222 (match_operand 2 "" "")))
8223 (clobber (reg:SI 15))])
8224 (set (pc) (label_ref (match_operand 3 "" "")))]
8225 "short_branch (INSN_UID (insn), INSN_UID (operands[3]))
8226 && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1))
8227 && sparc_cpu != PROCESSOR_ULTRASPARC
8228 && sparc_cpu != PROCESSOR_ULTRASPARC3"
8229 "call\t%a1, %2\n\tadd\t%%o7, (%l3-.-4), %%o7")
8232 [(parallel [(call (mem:SI (match_operand:SI 0 "call_operand_address" "ps"))
8233 (match_operand 1 "" ""))
8234 (clobber (reg:SI 15))])
8235 (set (pc) (label_ref (match_operand 2 "" "")))]
8236 "short_branch (INSN_UID (insn), INSN_UID (operands[2]))
8237 && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1))
8238 && sparc_cpu != PROCESSOR_ULTRASPARC
8239 && sparc_cpu != PROCESSOR_ULTRASPARC3"
8240 "call\t%a0, %1\n\tadd\t%%o7, (%l2-.-4), %%o7")
8242 ;; ??? UltraSPARC-III note: A memory operation loading into the floating point register
8243 ;; ??? file, if it hits the prefetch cache, has a chance to dual-issue with other memory
8244 ;; ??? operations. With DFA we might be able to model this, but it requires a lot of
8246 (define_expand "prefetch"
8247 [(match_operand 0 "address_operand" "")
8248 (match_operand 1 "const_int_operand" "")
8249 (match_operand 2 "const_int_operand" "")]
8253 emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2]));
8255 emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2]));
8259 (define_insn "prefetch_64"
8260 [(prefetch (match_operand:DI 0 "address_operand" "p")
8261 (match_operand:DI 1 "const_int_operand" "n")
8262 (match_operand:DI 2 "const_int_operand" "n"))]
8265 static const char * const prefetch_instr[2][2] = {
8267 "prefetch\t[%a0], 1", /* no locality: prefetch for one read */
8268 "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */
8271 "prefetch\t[%a0], 3", /* no locality: prefetch for one write */
8272 "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */
8275 int read_or_write = INTVAL (operands[1]);
8276 int locality = INTVAL (operands[2]);
8278 if (read_or_write != 0 && read_or_write != 1)
8280 if (locality < 0 || locality > 3)
8282 return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
8284 [(set_attr "type" "load")])
8286 (define_insn "prefetch_32"
8287 [(prefetch (match_operand:SI 0 "address_operand" "p")
8288 (match_operand:SI 1 "const_int_operand" "n")
8289 (match_operand:SI 2 "const_int_operand" "n"))]
8292 static const char * const prefetch_instr[2][2] = {
8294 "prefetch\t[%a0], 1", /* no locality: prefetch for one read */
8295 "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */
8298 "prefetch\t[%a0], 3", /* no locality: prefetch for one write */
8299 "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */
8302 int read_or_write = INTVAL (operands[1]);
8303 int locality = INTVAL (operands[2]);
8305 if (read_or_write != 0 && read_or_write != 1)
8307 if (locality < 0 || locality > 3)
8309 return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
8311 [(set_attr "type" "load")])
8313 (define_expand "prologue"
8315 "flag_pic && current_function_uses_pic_offset_table"
8317 load_pic_register ();
8321 ;; We need to reload %l7 for -mflat -fpic,
8322 ;; otherwise %l7 should be preserved simply
8323 ;; by loading the function's register window
8324 (define_expand "exception_receiver"
8326 "TARGET_FLAT && flag_pic"
8328 load_pic_register ();
8333 (define_expand "builtin_setjmp_receiver"
8334 [(label_ref (match_operand 0 "" ""))]
8335 "TARGET_FLAT && flag_pic"
8337 load_pic_register ();
8342 [(trap_if (const_int 1) (const_int 5))]
8345 [(set_attr "type" "trap")])
8347 (define_expand "conditional_trap"
8348 [(trap_if (match_operator 0 "noov_compare_op"
8349 [(match_dup 2) (match_dup 3)])
8350 (match_operand:SI 1 "arith_operand" ""))]
8352 "operands[2] = gen_compare_reg (GET_CODE (operands[0]),
8353 sparc_compare_op0, sparc_compare_op1);
8354 operands[3] = const0_rtx;")
8357 [(trap_if (match_operator 0 "noov_compare_op" [(reg:CC 100) (const_int 0)])
8358 (match_operand:SI 1 "arith_operand" "rM"))]
8361 [(set_attr "type" "trap")])
8364 [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)])
8365 (match_operand:SI 1 "arith_operand" "rM"))]
8368 [(set_attr "type" "trap")])