gcc/config/sparc/supersparc.md

   1 ;; Scheduling description for SuperSPARC.
   2 ;;   Copyright (C) 2002 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 2, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING.  If not, write to
  18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  19 ;; Boston, MA 02110-1301, USA.
  20
  21 ;; The SuperSPARC is a tri-issue, which was considered quite parallel
  22 ;; at the time it was released.  Much like UltraSPARC-I and UltraSPARC-II
  23 ;; there are two integer units but only one of them may take shifts.
  24 ;;
  25 ;; ??? If SuperSPARC has the same slotting rules as ultrasparc for these
  26 ;; ??? shifts, we should model that.
  27
  28 (define_automaton "supersparc_0,supersparc_1")
  29
  30 (define_cpu_unit "ss_memory, ss_shift, ss_iwport0, ss_iwport1" "supersparc_0")
  31 (define_cpu_unit "ss_fpalu" "supersparc_0")
  32 (define_cpu_unit "ss_fpmds" "supersparc_1")
  33
  34 (define_reservation "ss_iwport" "(ss_iwport0 | ss_iwport1)")
  35
  36 (define_insn_reservation "ss_iuload" 1
  37   (and (eq_attr "cpu" "supersparc")
  38     (eq_attr "type" "load,sload"))
  39   "ss_memory")
  40
  41 ;; Ok, fpu loads deliver the result in zero cycles.  But we
  42 ;; have to show the ss_memory reservation somehow, thus...
  43 (define_insn_reservation "ss_fpload" 0
  44   (and (eq_attr "cpu" "supersparc")
  45     (eq_attr "type" "fpload"))
  46   "ss_memory")
  47
  48 (define_bypass 0 "ss_fpload" "ss_fp_alu,ss_fp_mult,ss_fp_divs,ss_fp_divd,ss_fp_sqrt")
  49
  50 (define_insn_reservation "ss_store" 1
  51   (and (eq_attr "cpu" "supersparc")
  52     (eq_attr "type" "store,fpstore"))
  53   "ss_memory")
  54
  55 (define_insn_reservation "ss_ialu_shift" 1
  56   (and (eq_attr "cpu" "supersparc")
  57     (eq_attr "type" "shift"))
  58   "ss_shift + ss_iwport")
  59
  60 (define_insn_reservation "ss_ialu_any" 1
  61   (and (eq_attr "cpu" "supersparc")
  62     (eq_attr "type" "load,sload,store,shift,ialu"))
  63   "ss_iwport")
  64
  65 (define_insn_reservation "ss_fp_alu" 3
  66   (and (eq_attr "cpu" "supersparc")
  67     (eq_attr "type" "fp,fpmove,fpcmp"))
  68   "ss_fpalu, nothing*2")
  69
  70 (define_insn_reservation "ss_fp_mult" 3
  71   (and (eq_attr "cpu" "supersparc")
  72     (eq_attr "type" "fpmul"))
  73   "ss_fpmds, nothing*2")
  74
  75 (define_insn_reservation "ss_fp_divs" 6
  76   (and (eq_attr "cpu" "supersparc")
  77     (eq_attr "type" "fpdivs"))
  78   "ss_fpmds*4, nothing*2")
  79
  80 (define_insn_reservation "ss_fp_divd" 9
  81   (and (eq_attr "cpu" "supersparc")
  82     (eq_attr "type" "fpdivd"))
  83   "ss_fpmds*7, nothing*2")
  84
  85 (define_insn_reservation "ss_fp_sqrt" 12
  86   (and (eq_attr "cpu" "supersparc")
  87     (eq_attr "type" "fpsqrts,fpsqrtd"))
  88   "ss_fpmds*10, nothing*2")
  89
  90 (define_insn_reservation "ss_imul" 4
  91   (and (eq_attr "cpu" "supersparc")
  92     (eq_attr "type" "imul"))
  93   "ss_fpmds*4")