gcc/config/stormy16/stormy16.h

   1 /* Xstormy16 cpu description.
   2    Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007,
   3    2008, 2009, 2010  Free Software Foundation, Inc.
   4    Contributed by Red Hat, Inc.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    GCC is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 \f
  23 /* Driver configuration.  */
  24
  25 #undef  ASM_SPEC
  26 #define ASM_SPEC ""
  27
  28 #undef  LINK_SPEC
  29 #define LINK_SPEC "%{h*} %{v:-V} \
  30                    %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
  31
  32 /* For xstormy16:
  33    - If -msim is specified, everything is built and linked as for the sim.
  34    - If -T is specified, that linker script is used, and it should provide
  35      appropriate libraries.
  36    - If neither is specified, everything is built as for the sim, but no
  37      I/O support is assumed.  */
  38 #undef  LIB_SPEC
  39 #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:%{!T*:-lnosys}} -)"
  40
  41 #undef  STARTFILE_SPEC
  42 #define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
  43
  44 #undef  ENDFILE_SPEC
  45 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
  46
  47 \f
  48 /* Run-time target specifications.  */
  49
  50 #define TARGET_CPU_CPP_BUILTINS()               \
  51   do                                            \
  52     {                                           \
  53       builtin_define_std ("xstormy16");         \
  54       builtin_assert ("machine=xstormy16");     \
  55       builtin_assert ("cpu=xstormy16");         \
  56     }                                           \
  57   while (0)
  58
  59 #define TARGET_VERSION fprintf (stderr, " (xstormy16 cpu core)");
  60 \f
  61 /* Storage Layout.  */
  62
  63 #define BITS_BIG_ENDIAN 1
  64
  65 #define BYTES_BIG_ENDIAN 0
  66
  67 #define WORDS_BIG_ENDIAN 0
  68
  69 #define UNITS_PER_WORD 2
  70
  71 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)       \
  72   do                                            \
  73     {                                           \
  74       if (GET_MODE_CLASS (MODE) == MODE_INT     \
  75           && GET_MODE_SIZE (MODE) < 2)          \
  76         (MODE) = HImode;                        \
  77     }                                           \
  78   while (0)
  79
  80 #define PARM_BOUNDARY 16
  81
  82 #define STACK_BOUNDARY 16
  83
  84 #define FUNCTION_BOUNDARY 16
  85
  86 #define BIGGEST_ALIGNMENT 16
  87
  88 #define DATA_ALIGNMENT(TYPE, ALIGN)             \
  89   (TREE_CODE (TYPE) == ARRAY_TYPE               \
  90    && TYPE_MODE (TREE_TYPE (TYPE)) == QImode    \
  91    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
  92
  93 #define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
  94   (TREE_CODE (EXP) == STRING_CST        \
  95    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
  96
  97 #define STRICT_ALIGNMENT 1
  98
  99 #define PCC_BITFIELD_TYPE_MATTERS 1
 100 \f
 101 /* Layout of Source Language Data Types.  */
 102
 103 #define INT_TYPE_SIZE 16
 104
 105 #define SHORT_TYPE_SIZE 16
 106
 107 #define LONG_TYPE_SIZE 32
 108
 109 #define LONG_LONG_TYPE_SIZE 64
 110
 111 #define FLOAT_TYPE_SIZE 32
 112
 113 #define DOUBLE_TYPE_SIZE 64
 114
 115 #define LONG_DOUBLE_TYPE_SIZE 64
 116
 117 #define DEFAULT_SIGNED_CHAR 0
 118
 119 #define SIZE_TYPE "unsigned int"
 120
 121 #define PTRDIFF_TYPE "int"
 122
 123 #undef  WCHAR_TYPE
 124 #define WCHAR_TYPE "long int"
 125
 126 #undef  WCHAR_TYPE_SIZE
 127 #define WCHAR_TYPE_SIZE 32
 128
 129 \f
 130 /* Register Basics.  */
 131
 132 #define FIRST_PSEUDO_REGISTER 19
 133
 134 #define FIXED_REGISTERS \
 135   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 }
 136
 137 #define CALL_USED_REGISTERS \
 138   { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 }
 139
 140 \f
 141 /* Order of allocation of registers.  */
 142
 143 #define REG_ALLOC_ORDER { 7, 6, 5, 4, 3, 2, 1, 0, 9, 8, 10, 11, 12, 13, 14, 15, 16 }
 144
 145 \f
 146 /* How Values Fit in Registers.  */
 147
 148 #define HARD_REGNO_NREGS(REGNO, MODE)                           \
 149   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 150
 151 #define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO) != 16 || (MODE) == BImode)
 152
 153 /* A C expression that is nonzero if it is desirable to choose register
 154    allocation so as to avoid move instructions between a value of mode MODE1
 155    and a value of mode MODE2.
 156
 157    If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
 158    ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
 159    zero.  */
 160 #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) != BImode && (MODE2) != BImode)
 161
 162 \f
 163 /* Register Classes.  */
 164
 165 enum reg_class
 166 {
 167   NO_REGS,
 168   R0_REGS,
 169   R1_REGS,
 170   TWO_REGS,
 171   R2_REGS,
 172   EIGHT_REGS,
 173   R8_REGS,
 174   ICALL_REGS,
 175   GENERAL_REGS,
 176   ALL_REGS,
 177   LIM_REG_CLASSES
 178 };
 179
 180 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
 181
 182 #define IRA_COVER_CLASSES                       \
 183 {                                               \
 184   GENERAL_REGS, LIM_REG_CLASSES                 \
 185 }
 186
 187 #define REG_CLASS_NAMES                         \
 188 {                                               \
 189   "NO_REGS",                                    \
 190   "R0_REGS",                                    \
 191   "R1_REGS",                                    \
 192   "TWO_REGS",                                   \
 193   "R2_REGS",                                    \
 194   "EIGHT_REGS",                                 \
 195   "R8_REGS",                                    \
 196   "ICALL_REGS",                                 \
 197   "GENERAL_REGS",                               \
 198   "ALL_REGS"                                    \
 199 }
 200
 201 #define REG_CLASS_CONTENTS                      \
 202 {                                               \
 203   { 0x00000 },                                  \
 204   { 0x00001 },                                  \
 205   { 0x00002 },                                  \
 206   { 0x00003 },                                  \
 207   { 0x00004 },                                  \
 208   { 0x000FF },                                  \
 209   { 0x00100 },                                  \
 210   { 0x00300 },                                  \
 211   { 0x6FFFF },                                  \
 212   { (1 << FIRST_PSEUDO_REGISTER) - 1 }          \
 213 }
 214
 215 #define REGNO_REG_CLASS(REGNO)                  \
 216   (  (REGNO) ==  0 ? R0_REGS                    \
 217    : (REGNO) ==  1 ? R1_REGS                    \
 218    : (REGNO) ==  2 ? R2_REGS                    \
 219    : (REGNO) <   8 ? EIGHT_REGS                 \
 220    : (REGNO) ==  8 ? R8_REGS                    \
 221    : (REGNO) <= 18 ? GENERAL_REGS               \
 222    : ALL_REGS)
 223
 224 #define BASE_REG_CLASS GENERAL_REGS
 225
 226 #define INDEX_REG_CLASS GENERAL_REGS
 227
 228 #define REGNO_OK_FOR_BASE_P(NUM) 1
 229
 230 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
 231
 232 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
 233   xstormy16_preferred_reload_class (X, CLASS)
 234
 235 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
 236   xstormy16_preferred_reload_class (X, CLASS)
 237
 238 /* This chip has the interesting property that only the first eight
 239    registers can be moved to/from memory.  */
 240 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X)                  \
 241   xstormy16_secondary_reload_class (CLASS, MODE, X)
 242
 243 #define CLASS_MAX_NREGS(CLASS, MODE) \
 244   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 245
 246 \f
 247 /* Basic Stack Layout.  */
 248
 249 /* We want to use post-increment instructions to push things on the stack,
 250    because we don't have any pre-increment ones.  */
 251 #define STACK_PUSH_CODE POST_INC
 252
 253 #define FRAME_GROWS_DOWNWARD 0
 254
 255 #define ARGS_GROW_DOWNWARD 1
 256
 257 #define STARTING_FRAME_OFFSET 0
 258
 259 #define FIRST_PARM_OFFSET(FUNDECL) 0
 260
 261 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR)       \
 262   ((COUNT) == 0                                 \
 263    ? gen_rtx_MEM (Pmode, arg_pointer_rtx)       \
 264    : NULL_RTX)
 265
 266 #define INCOMING_RETURN_ADDR_RTX  \
 267    gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-4)))
 268
 269 #define INCOMING_FRAME_SP_OFFSET (xstormy16_interrupt_function_p () ? -6 : -4)
 270
 271 \f
 272 /* Register That Address the Stack Frame.  */
 273
 274 #define STATIC_CHAIN_REGNUM      1
 275 #define HARD_FRAME_POINTER_REGNUM 13
 276 #define STACK_POINTER_REGNUM    15
 277 #define CARRY_REGNUM            16
 278 #define FRAME_POINTER_REGNUM    17
 279 #define ARG_POINTER_REGNUM      18
 280
 281 \f
 282 /* Eliminating the Frame Pointer and the Arg Pointer.  */
 283
 284 #define ELIMINABLE_REGS                                 \
 285 {                                                       \
 286   {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},         \
 287   {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},    \
 288   {ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},         \
 289   {ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},    \
 290 }
 291
 292 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 293   (OFFSET) = xstormy16_initial_elimination_offset (FROM, TO)
 294
 295 \f
 296 /* Passing Function Arguments on the Stack.  */
 297
 298 #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
 299
 300 \f
 301 /* Function Arguments in Registers.  */
 302
 303 #define NUM_ARGUMENT_REGISTERS  6
 304 #define FIRST_ARGUMENT_REGISTER 2
 305
 306 #define XSTORMY16_WORD_SIZE(TYPE, MODE)                         \
 307   ((((TYPE) ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))  \
 308     + 1)                                                        \
 309    / 2)
 310
 311 /* For this platform, the value of CUMULATIVE_ARGS is the number of words
 312    of arguments that have been passed in registers so far.  */
 313 #define CUMULATIVE_ARGS int
 314
 315 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 316   (CUM) = 0
 317
 318 #define FUNCTION_ARG_REGNO_P(REGNO)                                     \
 319   ((REGNO) >= FIRST_ARGUMENT_REGISTER                                   \
 320    && (REGNO) < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS)
 321
 322 \f
 323 /* How Scalar Function Values are Returned.  */
 324
 325 /* The number of the hard register that is used to return a scalar value from a
 326    function call.  */
 327 #define RETURN_VALUE_REGNUM     FIRST_ARGUMENT_REGISTER
 328
 329 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 330   xstormy16_function_value (VALTYPE, FUNC)
 331
 332 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, RETURN_VALUE_REGNUM)
 333
 334 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == RETURN_VALUE_REGNUM)
 335
 336 \f
 337 /* Function Entry and Exit.  */
 338
 339 #define EPILOGUE_USES(REGNO) \
 340   xstormy16_epilogue_uses (REGNO)
 341
 342 \f
 343 /* Generating Code for Profiling.  */
 344
 345 /* This declaration must be present, but it can be an abort if profiling is
 346    not implemented.  */
 347
 348 #define FUNCTION_PROFILER(FILE, LABELNO) xstormy16_function_profiler ()
 349
 350 \f
 351 /* Trampolines for Nested Functions.  */
 352
 353 #define TRAMPOLINE_SIZE 8
 354 #define TRAMPOLINE_ALIGNMENT 16
 355 \f
 356
 357 /* Addressing Modes.  */
 358
 359 #define HAVE_POST_INCREMENT 1
 360
 361 #define HAVE_PRE_DECREMENT 1
 362
 363 #define MAX_REGS_PER_ADDRESS 1
 364
 365 #ifdef REG_OK_STRICT
 366 #define REG_OK_FOR_BASE_P(X)                                               \
 367   (REGNO_OK_FOR_BASE_P (REGNO (X)) && (REGNO (X) < FIRST_PSEUDO_REGISTER))
 368 #else
 369 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
 370 #endif
 371
 372 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
 373
 374 /* On this chip, this is true if the address is valid with an offset
 375    of 0 but not of 6, because in that case it cannot be used as an
 376    address for DImode or DFmode, or if the address is a post-increment
 377    or pre-decrement address.  */
 378 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)                        \
 379   if (xstormy16_mode_dependent_address_p (ADDR))                        \
 380     goto LABEL
 381
 382 #define LEGITIMATE_CONSTANT_P(X) 1
 383
 384 \f
 385 /* Describing Relative Costs of Operations.  */
 386
 387 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
 388
 389 #define MEMORY_MOVE_COST(M,C,I) (5 + memory_move_secondary_cost (M, C, I))
 390
 391 #define BRANCH_COST(speed_p, predictable_p) 5
 392
 393 #define SLOW_BYTE_ACCESS 0
 394
 395 #define NO_FUNCTION_CSE
 396
 397 \f
 398 /* Dividing the output into sections.  */
 399
 400 #define TEXT_SECTION_ASM_OP ".text"
 401
 402 #define DATA_SECTION_ASM_OP ".data"
 403
 404 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
 405
 406 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
 407    There are no shared libraries on this target so these sections need
 408    not be writable.
 409
 410    Defined in elfos.h.  */
 411
 412 #undef CTORS_SECTION_ASM_OP
 413 #undef DTORS_SECTION_ASM_OP
 414 #define CTORS_SECTION_ASM_OP    "\t.section\t.ctors,\"a\""
 415 #define DTORS_SECTION_ASM_OP    "\t.section\t.dtors,\"a\""
 416
 417 #define TARGET_ASM_INIT_SECTIONS xstormy16_asm_init_sections
 418
 419 #define JUMP_TABLES_IN_TEXT_SECTION 1
 420 \f
 421 /* The Overall Framework of an Assembler File.  */
 422
 423 #define ASM_COMMENT_START ";"
 424
 425 #define ASM_APP_ON "#APP\n"
 426
 427 #define ASM_APP_OFF "#NO_APP\n"
 428 \f
 429 /* Output of Data.  */
 430
 431 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '|')
 432
 433 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 434   xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
 435 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 436   xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
 437
 438 \f
 439 /* Output and Generation of Labels.  */
 440 #define SYMBOL_FLAG_XSTORMY16_BELOW100  (SYMBOL_FLAG_MACH_DEP << 0)
 441
 442 #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL)   \
 443   do                                            \
 444     {                                           \
 445       const char *rn = XSTR (SYMBOL, 0);        \
 446                                                 \
 447       if (SYMBOL_REF_FUNCTION_P (SYMBOL))       \
 448         ASM_OUTPUT_LABEL_REF ((STREAM), rn);    \
 449       else                                      \
 450         assemble_name (STREAM, rn);             \
 451     }                                           \
 452   while (0)
 453
 454 #define ASM_OUTPUT_LABEL_REF(STREAM, NAME)      \
 455   do                                            \
 456     {                                           \
 457       fputs ("@fptr(", STREAM);                 \
 458       assemble_name (STREAM, NAME);             \
 459       fputc (')', STREAM);                      \
 460     }                                           \
 461   while (0)
 462
 463 /* Globalizing directive for a label.  */
 464 #define GLOBAL_ASM_OP "\t.globl "
 465
 466 \f
 467 /* Output of Assembler Instructions.  */
 468
 469 #define REGISTER_NAMES                                                  \
 470 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",    \
 471   "r11", "r12", "r13", "psw", "sp", "carry", "fp", "ap" }
 472
 473 #define ADDITIONAL_REGISTER_NAMES               \
 474   { { "r14", 14 },                              \
 475     { "r15", 15 } }
 476
 477 #define PRINT_OPERAND(STREAM, X, CODE) xstormy16_print_operand (STREAM, X, CODE)
 478
 479 #define PRINT_OPERAND_ADDRESS(STREAM, X) xstormy16_print_operand_address (STREAM, X)
 480
 481 #define REGISTER_PREFIX ""
 482 #define LOCAL_LABEL_PREFIX "."
 483 #define USER_LABEL_PREFIX ""
 484 #define IMMEDIATE_PREFIX "#"
 485
 486 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
 487   fprintf (STREAM, "\tpush %d\n", REGNO)
 488
 489 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
 490   fprintf (STREAM, "\tpop %d\n", REGNO)
 491
 492 \f
 493 /* Output of dispatch tables.  */
 494
 495 /* This port does not use the ASM_OUTPUT_ADDR_VEC_ELT macro, because
 496    this could cause label alignment to appear between the 'br' and the table,
 497    which would be bad.  Instead, it controls the output of the table
 498    itself.  */
 499 #define ASM_OUTPUT_ADDR_VEC(LABEL, BODY) \
 500   xstormy16_output_addr_vec (file, LABEL, BODY)
 501
 502 /* Alignment for ADDR_VECs is the same as for code.  */
 503 #define ADDR_VEC_ALIGN(ADDR_VEC) 1
 504
 505 \f
 506 /* Assembler Commands for Exception Regions.  */
 507
 508 #define DWARF2_UNWIND_INFO              0
 509 #define DWARF_CIE_DATA_ALIGNMENT        1
 510
 511 #undef  DONT_USE_BUILTIN_SETJMP
 512 #define JMP_BUF_SIZE  8
 513 \f
 514 /* Assembler Commands for Alignment.  */
 515
 516 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
 517   fprintf ((STREAM), "\t.p2align %d\n", (POWER))
 518
 519 \f
 520 /* Macros Affecting all Debug Formats.  */
 521
 522 #undef  PREFERRED_DEBUGGING_TYPE
 523 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 524
 525 \f
 526 /* Macros for SDB and Dwarf Output.  */
 527
 528 /* Define this macro if addresses in Dwarf 2 debugging info should not
 529    be the same size as pointers on the target architecture.  The
 530    macro's value should be the size, in bytes, to use for addresses in
 531    the debugging info.
 532
 533    Some architectures use word addresses to refer to code locations,
 534    but Dwarf 2 info always uses byte addresses.  On such machines,
 535    Dwarf 2 addresses need to be larger than the architecture's
 536    pointers.  */
 537 #define DWARF2_ADDR_SIZE 4
 538
 539 \f
 540 /* Miscellaneous Parameters.  */
 541
 542 #define CASE_VECTOR_MODE SImode
 543
 544 #define WORD_REGISTER_OPERATIONS
 545
 546 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 547
 548 #define MOVE_MAX 2
 549
 550 #define SHIFT_COUNT_TRUNCATED 1
 551
 552 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 553
 554 #define Pmode HImode
 555
 556 #define FUNCTION_MODE HImode
 557
 558 #define NO_IMPLICIT_EXTERN_C