gcc/config/tahoe/tahoe.md

   1 ;; Machine description for GNU compiler, Tahoe version
   2 ;; Copyright (C) 1989, 1994, 1996, 1997 Free Software Foundation, Inc.
   3
   4 ;; This file is part of GNU CC.
   5
   6 ;; GNU CC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 2, or (at your option)
   9 ;; any later version.
  10
  11 ;; GNU CC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GNU CC; see the file COPYING.  If not, write to
  18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  19 ;; Boston, MA 02111-1307, USA.
  20
  21
  22 ; File: tahoe.md
  23 ;
  24 ; Original port made at the University of Buffalo by Devon Bowen,
  25 ; Dale Wiles and Kevin Zachmann.
  26 ;
  27 ; Piet van Oostrum (piet@cs.ruu.nl) made changes for HCX/UX, fixed
  28 ; some bugs and made some improvements (hopefully).
  29 ;
  30 ; Mail bugs reports or fixes to:        gcc@cs.buffalo.edu
  31
  32
  33 ; movdi must call the output_move_double routine to move it around since
  34 ; the tahoe doesn't efficiently support 8 bit moves.
  35
  36 (define_insn "movdi"
  37   [(set (match_operand:DI 0 "general_operand" "=g")
  38         (match_operand:DI 1 "general_operand" "g"))]
  39   ""
  40   "*
  41 {
  42   CC_STATUS_INIT;
  43   return output_move_double (operands);
  44 }")
  45
  46
  47 ; the trick in the movsi is accessing the contents of the sp register.  The
  48 ; tahoe doesn't allow you to access it directly so you have to access the
  49 ; address of the top of the stack instead.
  50
  51 (define_insn "movsi"
  52   [(set (match_operand:SI 0 "general_operand" "=g")
  53         (match_operand:SI 1 "general_operand" "g"))]
  54   ""
  55   "*
  56 {
  57    rtx link;
  58    if (operands[1] == const1_rtx
  59       && (link = find_reg_note (insn, REG_WAS_0, 0))
  60       && ! INSN_DELETED_P (XEXP (link, 0))
  61       && GET_CODE (XEXP (link, 0)) != NOTE
  62       && no_labels_between_p (XEXP (link, 0), insn)
  63       /* Make sure the reg hasn't been clobbered.  */
  64       && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
  65     return \"incl %0\";
  66    if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
  67     {
  68       if (push_operand (operands[0], SImode))
  69         return \"pushab %a1\";
  70       return \"movab %a1,%0\";
  71     }
  72   if (operands[1] == const0_rtx)
  73     return \"clrl %0\";
  74   if (push_operand (operands[0], SImode))
  75     return \"pushl %1\";
  76   if (GET_CODE(operands[1]) == REG && REGNO(operands[1]) == 14)
  77     return \"moval (sp),%0\";
  78   return \"movl %1,%0\";
  79 }")
  80
  81
  82 (define_insn "movhi"
  83   [(set (match_operand:HI 0 "general_operand" "=g")
  84         (match_operand:HI 1 "general_operand" "g"))]
  85   ""
  86   "*
  87 {
  88  rtx link;
  89  if (operands[1] == const1_rtx
  90      && (link = find_reg_note (insn, REG_WAS_0, 0))
  91      && ! INSN_DELETED_P (XEXP (link, 0))
  92      && GET_CODE (XEXP (link, 0)) != NOTE
  93      && no_labels_between_p (XEXP (link, 0), insn)
  94      /* Make sure the reg hasn't been clobbered.  */
  95      && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
  96     return \"incw %0\";
  97   if (operands[1] == const0_rtx)
  98     return \"clrw %0\";
  99   return \"movw %1,%0\";
 100 }")
 101
 102
 103 (define_insn "movqi"
 104   [(set (match_operand:QI 0 "general_operand" "=g")
 105         (match_operand:QI 1 "general_operand" "g"))]
 106   ""
 107   "*
 108 {
 109   if (operands[1] == const0_rtx)
 110     return \"clrb %0\";
 111   return \"movb %1,%0\";
 112 }")
 113
 114
 115 ; movsf has three cases since they can move from one place to another
 116 ; or to/from the fpp and since different instructions are needed for
 117 ; each case.  The fpp related instructions don't set the flags properly.
 118
 119 (define_insn "movsf"
 120   [(set (match_operand:SF 0 "general_operand" "=g,=a,=g")
 121         (match_operand:SF 1 "general_operand" "g,g,a"))]
 122   ""
 123   "*
 124 {
 125   CC_STATUS_INIT;
 126   switch (which_alternative)
 127     {
 128     case 0: return \"movl %1,%0\";
 129     case 1: return \"ldf %1\";
 130     case 2: return \"stf %0\";
 131    }
 132 }")
 133
 134
 135 ; movdf has a number of different cases.  If it's going to or from
 136 ; the fpp, use the special instructions to do it.  If not, use the
 137 ; output_move_double function.
 138
 139 (define_insn "movdf"
 140   [(set (match_operand:DF 0 "general_operand" "=a,=g,?=g")
 141         (match_operand:DF 1 "general_operand" "g,a,g"))]
 142   ""
 143   "*
 144 {
 145   CC_STATUS_INIT;
 146   switch (which_alternative)
 147     {
 148     case 0:
 149       return \"ldd %1\";
 150     case 1:
 151       if (push_operand (operands[0], DFmode))
 152         return \"pushd\";
 153       else
 154         return \"std %0\";
 155     case 2:
 156       return output_move_double (operands);
 157    }
 158 }")
 159
 160
 161 ;========================================================================
 162 ; The tahoe has the following semantics for byte (and similar for word)
 163 ; operands: if the operand is a register or immediate, it takes the full 32
 164 ; bit operand, if the operand is memory, it sign-extends the byte.  The
 165 ; operation is performed on the 32 bit values.  If the destination is a
 166 ; register, the full 32 bit result is stored, if the destination is memory,
 167 ; of course only the low part is stored.  The condition code is based on the
 168 ; 32 bit operation.  Only on the movz instructions the byte from memory is
 169 ; zero-extended rather than sign-extended.
 170
 171 ; This means that for arithmetic instructions we can use addb etc.  to
 172 ; perform a long add from a signed byte from memory to a register.  Of
 173 ; course this would also work for logical operations, but that doesn't seem
 174 ; very useful.
 175
 176 (define_insn ""
 177   [(set (match_operand:SI 0 "register_operand" "=r")
 178         (plus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))
 179                  (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
 180   ""
 181   "addb3 %1,%2,%0")
 182
 183 (define_insn ""
 184   [(set (match_operand:SI 0 "register_operand" "=r")
 185         (plus:SI (match_operand:SI 1 "nonmemory_operand" "%ri")
 186                  (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
 187   ""
 188   "*
 189 {
 190   if (rtx_equal_p (operands[0], operands[1]))
 191     return \"addb2 %2,%0\";
 192   return \"addb3 %1,%2,%0\";
 193 }")
 194
 195 ; We can also consider the result to be a half integer
 196
 197 (define_insn ""
 198   [(set (match_operand:HI 0 "register_operand" "=r")
 199         (plus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))
 200                  (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
 201   ""
 202   "addb3 %1,%2,%0")
 203
 204 (define_insn ""
 205   [(set (match_operand:HI 0 "register_operand" "=r")
 206         (plus:HI (match_operand:HI 1 "nonmemory_operand" "%ri")
 207                  (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
 208   ""
 209   "*
 210 {
 211   if (rtx_equal_p (operands[0], operands[1]))
 212     return \"addb2 %2,%0\";
 213   return \"addb3 %1,%2,%0\";
 214 }")
 215
 216 ; The same applies to words (HI)
 217
 218 (define_insn ""
 219   [(set (match_operand:SI 0 "register_operand" "=r")
 220         (plus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
 221                  (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
 222   ""
 223   "addw3 %1,%2,%0")
 224
 225 (define_insn ""
 226   [(set (match_operand:SI 0 "register_operand" "=r")
 227         (plus:SI (match_operand:SI 1 "nonmemory_operand" "%ri")
 228                  (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
 229   ""
 230   "*
 231 {
 232   if (rtx_equal_p (operands[0], operands[1]))
 233     return \"addw2 %2,%0\";
 234   return \"addw3 %1,%2,%0\";
 235 }")
 236
 237 ; ======================= Now for subtract ==============================
 238
 239 (define_insn ""
 240   [(set (match_operand:SI 0 "register_operand" "=r")
 241         (minus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))
 242                   (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
 243   ""
 244   "subb3 %2,%1,%0")
 245
 246 (define_insn ""
 247   [(set (match_operand:SI 0 "register_operand" "=r")
 248         (minus:SI (match_operand:SI 1 "nonmemory_operand" "ri")
 249                   (sign_extend:SI (match_operand:QI 2 "memory_operand" "m"))))]
 250   ""
 251   "*
 252 {
 253   if (rtx_equal_p (operands[0], operands[1]))
 254     return \"subb2 %2,%0\";
 255   return \"subb3 %2,%1,%0\";
 256 }")
 257
 258 (define_insn ""
 259   [(set (match_operand:SI 0 "register_operand" "=r")
 260         (minus:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))
 261                   (match_operand:SI 2 "nonmemory_operand" "ri")))]
 262   ""
 263   "subb3 %2,%1,%0")
 264
 265 ; We can also consider the result to be a half integer
 266
 267 (define_insn ""
 268   [(set (match_operand:HI 0 "register_operand" "=r")
 269         (minus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))
 270                  (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
 271   ""
 272   "subb3 %2,%1,%0")
 273
 274 (define_insn ""
 275   [(set (match_operand:HI 0 "register_operand" "=r")
 276         (minus:HI (match_operand:HI 1 "nonmemory_operand" "%ri")
 277                  (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"))))]
 278   ""
 279   "*
 280 {
 281   if (rtx_equal_p (operands[0], operands[1]))
 282     return \"subb2 %2,%0\";
 283   return \"subb3 %2,%1,%0\";
 284 }")
 285
 286 (define_insn ""
 287   [(set (match_operand:HI 0 "register_operand" "=r")
 288         (minus:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))
 289                  (match_operand:HI 2 "nonmemory_operand" "ri")))]
 290   ""
 291   "subb3 %2,%1,%0")
 292
 293 ; The same applies to words (HI)
 294
 295 (define_insn ""
 296   [(set (match_operand:SI 0 "register_operand" "=r")
 297         (minus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
 298                   (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
 299   ""
 300   "subw3 %2,%1,%0")
 301
 302 (define_insn ""
 303   [(set (match_operand:SI 0 "register_operand" "=r")
 304         (minus:SI (match_operand:SI 1 "nonmemory_operand" "ri")
 305                  (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))]
 306   ""
 307   "*
 308 {
 309   if (rtx_equal_p (operands[0], operands[1]))
 310     return \"subw2 %2,%0\";
 311   return \"subw3 %2,%1,%0\";
 312 }")
 313
 314 (define_insn ""
 315   [(set (match_operand:SI 0 "register_operand" "=r")
 316         (minus:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
 317                   (match_operand:SI 2 "nonmemory_operand" "ri")))]
 318   ""
 319   "subw3 %2,%1,%0")
 320
 321 ; ======================= Now for neg ==============================
 322
 323 (define_insn ""
 324   [(set (match_operand:SI 0 "register_operand" "=r")
 325         (neg:SI (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
 326   ""
 327   "mnegb %1,%0")
 328
 329 (define_insn ""
 330   [(set (match_operand:HI 0 "register_operand" "=r")
 331         (neg:HI (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))))]
 332   ""
 333   "mnegb %1,%0")
 334
 335 (define_insn ""
 336   [(set (match_operand:SI 0 "register_operand" "=r")
 337         (neg:SI (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
 338   ""
 339   "mnegw %1,%0")
 340
 341 ;========================================================================
 342
 343
 344 (define_insn "addsi3"
 345   [(set (match_operand:SI 0 "general_operand" "=g")
 346         (plus:SI (match_operand:SI 1 "general_operand" "g")
 347                  (match_operand:SI 2 "general_operand" "g")))]
 348   ""
 349   "*
 350 {
 351   if (rtx_equal_p (operands[0], operands[1]))
 352     {
 353       if (operands[2] == const1_rtx)
 354         return \"incl %0\";
 355       if (GET_CODE (operands[2]) == CONST_INT
 356           && INTVAL (operands[2]) == -1)
 357         return \"decl %0\";
 358       if (GET_CODE (operands[2]) == CONST_INT
 359           && (unsigned) (- INTVAL (operands[2])) < 64)
 360         return \"subl2 $%n2,%0\";
 361       return \"addl2 %2,%0\";
 362     }
 363   if (rtx_equal_p (operands[0], operands[2]))
 364     return \"addl2 %1,%0\";
 365   if (GET_CODE (operands[2]) == CONST_INT
 366       && GET_CODE (operands[1]) == REG)
 367     {
 368       if (push_operand (operands[0], SImode))
 369         return \"pushab %c2(%1)\";
 370       return \"movab %c2(%1),%0\";
 371     }
 372   if (GET_CODE (operands[2]) == CONST_INT
 373       && (unsigned) (- INTVAL (operands[2])) < 64)
 374     return \"subl3 $%n2,%1,%0\";
 375   return \"addl3 %1,%2,%0\";
 376 }")
 377
 378
 379 (define_insn "addhi3"
 380   [(set (match_operand:HI 0 "general_operand" "=g")
 381         (plus:HI (match_operand:HI 1 "general_operand" "g")
 382                  (match_operand:HI 2 "general_operand" "g")))]
 383   ""
 384   "*
 385 {
 386   if (rtx_equal_p (operands[0], operands[1]))
 387     {
 388       if (operands[2] == const1_rtx)
 389         return \"incw %0\";
 390       if (GET_CODE (operands[2]) == CONST_INT
 391           && INTVAL (operands[2]) == -1)
 392         return \"decw %0\";
 393       if (GET_CODE (operands[2]) == CONST_INT
 394           && (unsigned) (- INTVAL (operands[2])) < 64)
 395         return \"subw2 $%n2,%0\";
 396       return \"addw2 %2,%0\";
 397     }
 398   if (rtx_equal_p (operands[0], operands[2]))
 399     return \"addw2 %1,%0\";
 400   if (GET_CODE (operands[2]) == CONST_INT
 401       && (unsigned) (- INTVAL (operands[2])) < 64)
 402     return \"subw3 $%n2,%1,%0\";
 403   return \"addw3 %1,%2,%0\";
 404 }")
 405
 406
 407 (define_insn "addqi3"
 408   [(set (match_operand:QI 0 "general_operand" "=g")
 409         (plus:QI (match_operand:QI 1 "general_operand" "g")
 410                  (match_operand:QI 2 "general_operand" "g")))]
 411   ""
 412   "*
 413 {
 414   if (rtx_equal_p (operands[0], operands[1]))
 415     {
 416       if (operands[2] == const1_rtx)
 417         return \"incb %0\";
 418       if (GET_CODE (operands[2]) == CONST_INT
 419           && INTVAL (operands[2]) == -1)
 420         return \"decb %0\";
 421       if (GET_CODE (operands[2]) == CONST_INT
 422           && (unsigned) (- INTVAL (operands[2])) < 64)
 423         return \"subb2 $%n2,%0\";
 424       return \"addb2 %2,%0\";
 425     }
 426   if (rtx_equal_p (operands[0], operands[2]))
 427     return \"addb2 %1,%0\";
 428   if (GET_CODE (operands[2]) == CONST_INT
 429       && (unsigned) (- INTVAL (operands[2])) < 64)
 430     return \"subb3 $%n2,%1,%0\";
 431   return \"addb3 %1,%2,%0\";
 432 }")
 433
 434 ; addsf3 can only add into the fpp register since the fpp is treated
 435 ; as a separate unit in the machine.  It also doesn't set the flags at
 436 ; all.
 437
 438 (define_insn "addsf3"
 439   [(set (match_operand:SF 0 "register_operand" "=a")
 440         (plus:SF (match_operand:SF 1 "register_operand" "%0")
 441                  (match_operand:SF 2 "general_operand" "g")))]
 442   ""
 443   "*
 444 {
 445   CC_STATUS_INIT;
 446   return \"addf %2\";
 447 }")
 448
 449
 450 ; adddf3 can only add into the fpp reg since the fpp is treated as a
 451 ; separate entity.  Doubles can only be read from a register or memory
 452 ; since a double is not an immediate mode.  Flags are not set by this
 453 ; instruction.
 454
 455 (define_insn "adddf3"
 456   [(set (match_operand:DF 0 "register_operand" "=a")
 457         (plus:DF (match_operand:DF 1 "register_operand" "%0")
 458                  (match_operand:DF 2 "general_operand" "rm")))]
 459   ""
 460   "*
 461 {
 462   CC_STATUS_INIT;
 463   return \"addd %2\";
 464 }")
 465
 466
 467 ; Subtraction from the sp (needed by the built in alloc function) needs
 468 ; to be different since the sp cannot be directly read on the tahoe.
 469 ; If it's a simple constant, you just use displacement.  Otherwise, you
 470 ; push the sp, and then do the subtraction off the stack.
 471
 472 (define_insn "subsi3"
 473   [(set (match_operand:SI 0 "general_operand" "=g")
 474         (minus:SI (match_operand:SI 1 "general_operand" "g")
 475                   (match_operand:SI 2 "general_operand" "g")))]
 476   ""
 477   "*
 478 {
 479   if (rtx_equal_p (operands[0], operands[1]))
 480     {
 481       if (operands[2] == const1_rtx)
 482         return \"decl %0\";
 483       if (GET_CODE(operands[0]) == REG && REGNO(operands[0]) == 14)
 484         {
 485           if (GET_CODE(operands[2]) == CONST_INT)
 486             return \"movab %n2(sp),sp\";
 487           else
 488             return \"pushab (sp)\;subl3 %2,(sp),sp\";
 489         }
 490       return \"subl2 %2,%0\";
 491     }
 492   if (rtx_equal_p (operands[1], operands[2]))
 493     return \"clrl %0\";
 494   return \"subl3 %2,%1,%0\";
 495 }")
 496
 497
 498 (define_insn "subhi3"
 499   [(set (match_operand:HI 0 "general_operand" "=g")
 500         (minus:HI (match_operand:HI 1 "general_operand" "g")
 501                   (match_operand:HI 2 "general_operand" "g")))]
 502   ""
 503   "*
 504 {
 505   if (rtx_equal_p (operands[0], operands[1]))
 506     {
 507       if (operands[2] == const1_rtx)
 508         return \"decw %0\";
 509       return \"subw2 %2,%0\";
 510     }
 511   if (rtx_equal_p (operands[1], operands[2]))
 512     return \"clrw %0\";
 513   return \"subw3 %2,%1,%0\";
 514 }")
 515
 516
 517 (define_insn "subqi3"
 518   [(set (match_operand:QI 0 "general_operand" "=g")
 519         (minus:QI (match_operand:QI 1 "general_operand" "g")
 520                   (match_operand:QI 2 "general_operand" "g")))]
 521   ""
 522   "*
 523 {
 524   if (rtx_equal_p (operands[0], operands[1]))
 525     {
 526       if (operands[2] == const1_rtx)
 527         return \"decb %0\";
 528       return \"subb2 %2,%0\";
 529     }
 530   if (rtx_equal_p (operands[1], operands[2]))
 531     return \"clrb %0\";
 532   return \"subb3 %2,%1,%0\";
 533 }")
 534
 535
 536 ; subsf3 can only subtract into the fpp accumulator due to the way
 537 ; the fpp reg is limited by the instruction set.  This also doesn't
 538 ; bother setting up flags.
 539
 540 (define_insn "subsf3"
 541   [(set (match_operand:SF 0 "register_operand" "=a")
 542         (minus:SF (match_operand:SF 1 "register_operand" "0")
 543                   (match_operand:SF 2 "general_operand" "g")))]
 544   ""
 545   "*
 546 {
 547   CC_STATUS_INIT;
 548   return \"subf %2\";
 549 }")
 550
 551
 552 ; subdf3 is set up to subtract into the fpp reg due to limitations
 553 ; of the fpp instruction set.  Doubles can not be immediate.  This
 554 ; instruction does not set the flags.
 555
 556 (define_insn "subdf3"
 557   [(set (match_operand:DF 0 "register_operand" "=a")
 558         (minus:DF (match_operand:DF 1 "register_operand" "0")
 559                   (match_operand:DF 2 "general_operand" "rm")))]
 560   ""
 561   "*
 562 {
 563   CC_STATUS_INIT;
 564   return \"subd %2\";
 565 }")
 566
 567
 568 (define_insn "mulsi3"
 569   [(set (match_operand:SI 0 "general_operand" "=g")
 570         (mult:SI (match_operand:SI 1 "general_operand" "g")
 571                  (match_operand:SI 2 "general_operand" "g")))]
 572   ""
 573   "*
 574 {
 575   if (rtx_equal_p (operands[0], operands[1]))
 576     return \"mull2 %2,%0\";
 577   if (rtx_equal_p (operands[0], operands[2]))
 578     return \"mull2 %1,%0\";
 579   return \"mull3 %1,%2,%0\";
 580 }")
 581
 582
 583 ; mulsf3 can only multiply into the fpp accumulator due to limitations
 584 ; of the fpp.  It also does not set the condition codes properly.
 585
 586 (define_insn "mulsf3"
 587   [(set (match_operand:SF 0 "register_operand" "=a")
 588         (mult:SF (match_operand:SF 1 "register_operand" "%0")
 589                  (match_operand:SF 2 "general_operand" "g")))]
 590   ""
 591   "*
 592 {
 593   CC_STATUS_INIT;
 594   return \"mulf %2\";
 595 }")
 596
 597
 598 ; muldf3 can only multiply into the fpp reg since the fpp is limited
 599 ; from the rest.  Doubles may not be immediate mode.  This does not set
 600 ; the flags like gcc would expect.
 601
 602 (define_insn "muldf3"
 603   [(set (match_operand:DF 0 "register_operand" "=a")
 604         (mult:DF (match_operand:DF 1 "register_operand" "%0")
 605                  (match_operand:DF 2 "general_operand" "rm")))]
 606   ""
 607   "*
 608 {
 609   CC_STATUS_INIT;
 610   return \"muld %2\";
 611 }")
 612
 613
 614
 615 (define_insn "divsi3"
 616   [(set (match_operand:SI 0 "general_operand" "=g")
 617         (div:SI (match_operand:SI 1 "general_operand" "g")
 618                 (match_operand:SI 2 "general_operand" "g")))]
 619   ""
 620   "*
 621 {
 622   if (rtx_equal_p (operands[1], operands[2]))
 623     return \"movl $1,%0\";
 624   if (operands[1] == const0_rtx)
 625     return \"clrl %0\";
 626   if (GET_CODE (operands[2]) == CONST_INT
 627       && INTVAL (operands[2]) == -1)
 628     return \"mnegl %1,%0\";
 629   if (rtx_equal_p (operands[0], operands[1]))
 630     return \"divl2 %2,%0\";
 631   return \"divl3 %2,%1,%0\";
 632 }")
 633
 634
 635 ; divsf3 must divide into the fpp accumulator.  Flags are not set by
 636 ; this instruction, so they are cleared.
 637
 638 (define_insn "divsf3"
 639   [(set (match_operand:SF 0 "register_operand" "=a")
 640         (div:SF (match_operand:SF 1 "register_operand" "0")
 641                 (match_operand:SF 2 "general_operand" "g")))]
 642   ""
 643   "*
 644 {
 645   CC_STATUS_INIT;
 646   return \"divf %2\";
 647 }")
 648
 649
 650 ; divdf3 also must divide into the fpp reg so optimization isn't
 651 ; possible.  Note that doubles cannot be immediate.  The flags here
 652 ; are not set correctly so they must be ignored.
 653
 654 (define_insn "divdf3"
 655   [(set (match_operand:DF 0 "register_operand" "=a")
 656         (div:DF (match_operand:DF 1 "register_operand" "0")
 657                 (match_operand:DF 2 "general_operand" "rm")))]
 658   ""
 659   "*
 660 {
 661   CC_STATUS_INIT;
 662   return \"divd %2\";
 663 }")
 664
 665
 666
 667 (define_insn "andsi3"
 668   [(set (match_operand:SI 0 "general_operand" "=g")
 669         (and:SI (match_operand:SI 1 "general_operand" "g")
 670                 (match_operand:SI 2 "general_operand" "g")))]
 671   ""
 672   "*
 673 {
 674   if (rtx_equal_p (operands[0], operands[1]))
 675     return \"andl2 %2,%0\";
 676   if (rtx_equal_p (operands[0], operands[2]))
 677     return \"andl2 %1,%0\";
 678   return \"andl3 %2,%1,%0\";
 679 }")
 680
 681
 682
 683 (define_insn "andhi3"
 684   [(set (match_operand:HI 0 "general_operand" "=g")
 685         (and:HI (match_operand:HI 1 "general_operand" "g")
 686                 (match_operand:HI 2 "general_operand" "g")))]
 687   ""
 688   "*
 689 {
 690   if (rtx_equal_p (operands[0], operands[1]))
 691     return \"andw2 %2,%0\";
 692   if (rtx_equal_p (operands[0], operands[2]))
 693     return \"andw2 %1,%0\";
 694   return \"andw3 %2,%1,%0\";
 695 }")
 696
 697
 698 (define_insn "andqi3"
 699   [(set (match_operand:QI 0 "general_operand" "=g")
 700         (and:QI (match_operand:QI 1 "general_operand" "g")
 701                 (match_operand:QI 2 "general_operand" "g")))]
 702   ""
 703   "*
 704 {
 705   if (rtx_equal_p (operands[0], operands[1]))
 706     return \"andb2 %2,%0\";
 707   if (rtx_equal_p (operands[0], operands[2]))
 708     return \"andb2 %1,%0\";
 709   return \"andb3 %2,%1,%0\";
 710 }")
 711
 712
 713 (define_insn "iorsi3"
 714   [(set (match_operand:SI 0 "general_operand" "=g")
 715         (ior:SI (match_operand:SI 1 "general_operand" "g")
 716                 (match_operand:SI 2 "general_operand" "g")))]
 717   ""
 718   "*
 719 {
 720   if (rtx_equal_p (operands[0], operands[1]))
 721     return \"orl2 %2,%0\";
 722   if (rtx_equal_p (operands[0], operands[2]))
 723     return \"orl2 %1,%0\";
 724   return \"orl3 %2,%1,%0\";
 725 }")
 726
 727
 728
 729 (define_insn "iorhi3"
 730   [(set (match_operand:HI 0 "general_operand" "=g")
 731         (ior:HI (match_operand:HI 1 "general_operand" "g")
 732                 (match_operand:HI 2 "general_operand" "g")))]
 733   ""
 734   "*
 735 {
 736   if (rtx_equal_p (operands[0], operands[1]))
 737     return \"orw2 %2,%0\";
 738   if (rtx_equal_p (operands[0], operands[2]))
 739     return \"orw2 %1,%0\";
 740   return \"orw3 %2,%1,%0\";
 741 }")
 742
 743
 744
 745 (define_insn "iorqi3"
 746   [(set (match_operand:QI 0 "general_operand" "=g")
 747         (ior:QI (match_operand:QI 1 "general_operand" "g")
 748                 (match_operand:QI 2 "general_operand" "g")))]
 749   ""
 750   "*
 751 {
 752   if (rtx_equal_p (operands[0], operands[1]))
 753     return \"orb2 %2,%0\";
 754   if (rtx_equal_p (operands[0], operands[2]))
 755     return \"orb2 %1,%0\";
 756   return \"orb3 %2,%1,%0\";
 757 }")
 758
 759
 760 (define_insn "xorsi3"
 761   [(set (match_operand:SI 0 "general_operand" "=g")
 762         (xor:SI (match_operand:SI 1 "general_operand" "g")
 763                 (match_operand:SI 2 "general_operand" "g")))]
 764   ""
 765   "*
 766 {
 767   if (rtx_equal_p (operands[0], operands[1]))
 768     return \"xorl2 %2,%0\";
 769   if (rtx_equal_p (operands[0], operands[2]))
 770     return \"xorl2 %1,%0\";
 771   return \"xorl3 %2,%1,%0\";
 772 }")
 773
 774
 775 (define_insn "xorhi3"
 776   [(set (match_operand:HI 0 "general_operand" "=g")
 777         (xor:HI (match_operand:HI 1 "general_operand" "g")
 778                 (match_operand:HI 2 "general_operand" "g")))]
 779   ""
 780   "*
 781 {
 782   if (rtx_equal_p (operands[0], operands[1]))
 783     return \"xorw2 %2,%0\";
 784   if (rtx_equal_p (operands[0], operands[2]))
 785     return \"xorw2 %1,%0\";
 786   return \"xorw3 %2,%1,%0\";
 787 }")
 788
 789
 790 (define_insn "xorqi3"
 791   [(set (match_operand:QI 0 "general_operand" "=g")
 792         (xor:QI (match_operand:QI 1 "general_operand" "g")
 793                 (match_operand:QI 2 "general_operand" "g")))]
 794   ""
 795   "*
 796 {
 797   if (rtx_equal_p (operands[0], operands[1]))
 798     return \"xorb2 %2,%0\";
 799   if (rtx_equal_p (operands[0], operands[2]))
 800     return \"xorb2 %1,%0\";
 801   return \"xorb3 %2,%1,%0\";
 802 }")
 803
 804
 805 ; shifts on the tahoe are expensive, try some magic first...
 806
 807 (define_insn "ashlsi3"
 808   [(set (match_operand:SI 0 "general_operand" "=g")
 809         (ashift:SI (match_operand:SI 1 "general_operand" "g")
 810                    (match_operand:QI 2 "general_operand" "g")))]
 811   ""
 812   "*
 813 {
 814   if (GET_CODE(operands[2]) == REG)
 815       return \"mull3 ___shtab[%2],%1,%0\";
 816   /* if (GET_CODE(operands[2]) == REG)
 817     if (rtx_equal_p (operands[0], operands[1]))
 818       return \"mull2 ___shtab[%2],%1\";
 819     else
 820       return \"mull3 ___shtab[%2],%1,%0\"; */
 821   if (GET_CODE(operands[1]) == REG)
 822     {
 823       if (operands[2] == const1_rtx)
 824         {
 825           CC_STATUS_INIT;
 826           return \"movaw 0[%1],%0\";
 827         }
 828       if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2]) == 2)
 829         {
 830           CC_STATUS_INIT;
 831           return \"moval 0[%1],%0\";
 832         }
 833     }
 834   if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) == 1)
 835     return \"shal %2,%1,%0\";
 836   if (rtx_equal_p (operands[0], operands[1]))
 837     return \"mull2 %s2,%1\";
 838   else
 839     return \"mull3 %s2,%1,%0\";
 840 }")
 841
 842
 843 (define_insn "ashrsi3"
 844   [(set (match_operand:SI 0 "general_operand" "=g")
 845         (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
 846                    (match_operand:QI 2 "general_operand" "g")))]
 847   ""
 848   "shar %2,%1,%0")
 849
 850
 851 ; shifts are very expensive, try some magic first...
 852
 853 (define_insn "lshrsi3"
 854   [(set (match_operand:SI 0 "general_operand" "=g")
 855         (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
 856                    (match_operand:QI 2 "general_operand" "g")))]
 857   ""
 858   "shrl %2,%1,%0")
 859
 860
 861 (define_insn "negsi2"
 862   [(set (match_operand:SI 0 "general_operand" "=g")
 863         (neg:SI (match_operand:SI 1 "general_operand" "g")))]
 864   ""
 865   "mnegl %1,%0")
 866
 867
 868 (define_insn "neghi2"
 869   [(set (match_operand:HI 0 "general_operand" "=g")
 870         (neg:HI (match_operand:HI 1 "general_operand" "g")))]
 871   ""
 872   "mnegw %1,%0")
 873
 874
 875 (define_insn "negqi2"
 876   [(set (match_operand:QI 0 "general_operand" "=g")
 877         (neg:QI (match_operand:QI 1 "general_operand" "g")))]
 878   ""
 879   "mnegb %1,%0")
 880
 881
 882 ; negsf2 can only negate the value already in the fpp accumulator.
 883 ; The value remains in the fpp accumulator.  No flags are set.
 884
 885 (define_insn "negsf2"
 886   [(set (match_operand:SF 0 "register_operand" "=a,=a")
 887         (neg:SF (match_operand:SF 1 "register_operand" "a,g")))]
 888   ""
 889   "*
 890 {
 891   CC_STATUS_INIT;
 892   switch (which_alternative)
 893     {
 894     case 0: return \"negf\";
 895     case 1: return \"lnf %1\";
 896     }
 897 }")
 898
 899
 900 ; negdf2 can only negate the value already in the fpp accumulator.
 901 ; The value remains in the fpp accumulator.  No flags are set.
 902
 903 (define_insn "negdf2"
 904   [(set (match_operand:DF 0 "register_operand" "=a,=a")
 905         (neg:DF (match_operand:DF 1 "register_operand" "a,g")))]
 906   ""
 907   "*
 908 {
 909   CC_STATUS_INIT;
 910   switch (which_alternative)
 911     {
 912     case 0: return \"negd\";
 913     case 1: return \"lnd %1\";
 914     }
 915 }")
 916
 917
 918 ; sqrtsf2 tahoe can calculate the square root of a float in the
 919 ; fpp accumulator.  The answer remains in the fpp accumulator.  No
 920 ; flags are set by this function.
 921
 922 (define_insn "sqrtsf2"
 923   [(set (match_operand:SF 0 "register_operand" "=a")
 924         (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
 925   ""
 926   "*
 927 {
 928   CC_STATUS_INIT;
 929   return \"sqrtf\";
 930 }")
 931
 932
 933 ; ffssi2 tahoe instruction gives one less than gcc desired result for
 934 ; any given input.  So the increment is necessary here.
 935
 936 (define_insn "ffssi2"
 937   [(set (match_operand:SI 0 "general_operand" "=g")
 938         (ffs:SI (match_operand:SI 1 "general_operand" "g")))]
 939   ""
 940   "*
 941 {
 942   if (push_operand(operands[0], SImode))
 943     return \"ffs %1,%0\;incl (sp)\";
 944   return \"ffs %1,%0\;incl %0\";
 945 }")
 946
 947
 948 (define_insn "one_cmplsi2"
 949   [(set (match_operand:SI 0 "general_operand" "=g")
 950         (not:SI (match_operand:SI 1 "general_operand" "g")))]
 951   ""
 952   "mcoml %1,%0")
 953
 954
 955 (define_insn "one_cmplhi2"
 956   [(set (match_operand:HI 0 "general_operand" "=g")
 957         (not:HI (match_operand:HI 1 "general_operand" "g")))]
 958   ""
 959   "mcomw %1,%0")
 960
 961
 962 (define_insn "one_cmplqi2"
 963   [(set (match_operand:QI 0 "general_operand" "=g")
 964         (not:QI (match_operand:QI 1 "general_operand" "g")))]
 965   ""
 966   "mcomb %1,%0")
 967
 968
 969 ; cmpsi works fine, but due to microcode problems, the tahoe doesn't
 970 ; properly compare hi's and qi's.  Leaving them out seems to be acceptable
 971 ; to the compiler, so they were left out.  Compares of the stack are
 972 ; possible, though.
 973
 974 ; There are optimized cases possible, however.  These follow first.
 975
 976 (define_insn ""
 977   [(set (cc0)
 978         (compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m"))
 979                  (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
 980   ""
 981   "cmpw %0,%1")
 982
 983 (define_insn ""
 984   [(set (cc0)
 985         (compare (match_operand:SI 0 "nonmemory_operand" "ri")
 986                  (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
 987   ""
 988   "cmpw %0,%1")
 989
 990 (define_insn ""
 991   [(set (cc0)
 992         (compare (sign_extend:SI (match_operand:HI 0 "memory_operand" "m"))
 993                  (match_operand:SI 1 "nonmemory_operand" "ri")))]
 994   ""
 995   "cmpw %0,%1")
 996
 997 ; zero-extended compares give the same result as sign-extended compares, if
 998 ; the compare is unsigned.  Just see: if both operands are <65536 they are the
 999 ; same in both cases.  If both are >=65536 the you effectively compare x+D
1000 ; with y+D, where D=2**32-2**16, so the result is the same.  if x<65536 and
1001 ; y>=65536 then you compare x with y+D, and in both cases the result is x<y.
1002
1003 (define_insn ""
1004   [(set (cc0)
1005         (compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
1006                  (zero_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
1007   "tahoe_cmp_check (insn, operands[0], 0)"
1008   "cmpw %0,%1")
1009
1010 (define_insn ""
1011   [(set (cc0)
1012         (compare (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
1013                  (match_operand:SI 1 "immediate_operand" "i")))]
1014   "tahoe_cmp_check(insn, operands[1], 65535)"
1015   "*
1016 {
1017   if (INTVAL (operands[1]) > 32767)
1018     operands[1] = GEN_INT (INTVAL (operands[1]) + 0xffff0000);
1019   return \"cmpw %0,%1\";
1020 }")
1021
1022
1023 (define_insn ""
1024   [(set (cc0)
1025         (compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m"))
1026                  (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
1027   ""
1028   "cmpb %0,%1")
1029
1030 (define_insn ""
1031   [(set (cc0)
1032         (compare (match_operand:SI 0 "nonmemory_operand" "ri")
1033                  (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
1034   ""
1035   "cmpb %0,%1")
1036
1037 (define_insn ""
1038   [(set (cc0)
1039         (compare (sign_extend:SI (match_operand:QI 0 "memory_operand" "m"))
1040                  (match_operand:SI 1 "nonmemory_operand" "ri")))]
1041   ""
1042   "cmpb %0,%1")
1043
1044 ; zero-extended compares give the same result as sign-extended compares, if
1045 ; the compare is unsigned.  Just see: if both operands are <128 they are the
1046 ; same in both cases.  If both are >=128 the you effectively compare x+D
1047 ; with y+D, where D=2**32-2**8, so the result is the same.  if x<128 and
1048 ; y>=128 then you compare x with y+D, and in both cases the result is x<y.
1049
1050 (define_insn ""
1051   [(set (cc0)
1052         (compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
1053                  (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))))]
1054   "tahoe_cmp_check (insn, operands[0], 0)"
1055   "cmpb %0,%1")
1056
1057 (define_insn ""
1058   [(set (cc0)
1059         (compare (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
1060                  (match_operand:SI 1 "immediate_operand" "i")))]
1061   "tahoe_cmp_check(insn, operands[1], 255)"
1062   "*
1063 {
1064   if (INTVAL (operands[1]) > 127)
1065     operands[1] = GEN_INT (INTVAL (operands[1]) + 0xffffff00);
1066   return \"cmpb %0,%1\";
1067 }")
1068
1069
1070 (define_insn "cmpsi"
1071   [(set (cc0)
1072         (compare (match_operand:SI 0 "nonimmediate_operand" "g")
1073                  (match_operand:SI 1 "general_operand" "g")))]
1074   ""
1075   "cmpl %0,%1")
1076
1077
1078 ; cmpsf similar to vax, but first operand is expected to be in the
1079 ; fpp accumulator.
1080
1081 (define_insn "cmpsf"
1082   [(set (cc0)
1083         (compare (match_operand:SF 0 "general_operand" "a,g")
1084                (match_operand:SF 1 "general_operand" "g,g")))]
1085   ""
1086   "*
1087 {
1088   switch (which_alternative)
1089     {
1090     case 0: return \"cmpf %1\";
1091     case 1: return \"cmpf2 %0,%1\";
1092     }
1093 }")
1094
1095
1096 ; cmpdf similar to vax, but first operand is expected to be in the
1097 ; fpp accumulator.  Immediate doubles not allowed.
1098
1099 (define_insn "cmpdf"
1100   [(set (cc0)
1101         (compare (match_operand:DF 0 "general_operand" "a,rm")
1102                  (match_operand:DF 1 "general_operand" "rm,rm")))]
1103   ""
1104   "*
1105 {
1106   switch (which_alternative)
1107     {
1108     case 0: return \"cmpd %1\";
1109     case 1: return \"cmpd2 %0,%1\";
1110     }
1111 }")
1112
1113 ;; We don't want to allow a constant operand for test insns because
1114 ;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
1115 ;; be folded while optimizing anyway.
1116
1117 (define_insn "tstsi"
1118   [(set (cc0)
1119         (match_operand:SI 0 "nonimmediate_operand" "g"))]
1120   ""
1121   "tstl %0")
1122
1123
1124 ; small tests from memory are normal, but testing from registers doesn't
1125 ; expand the data properly.  So test in this case does a convert and tests
1126 ; the new register data from the stack.
1127
1128 ; First some special cases that do work
1129
1130
1131 (define_insn ""
1132   [(set (cc0)
1133         (sign_extend:SI (match_operand:HI 0 "memory_operand" "m")))]
1134   ""
1135   "tstw %0")
1136
1137 (define_insn ""
1138   [(set (cc0)
1139         (zero_extend:SI (match_operand:HI 0 "memory_operand" "m")))]
1140   "tahoe_cmp_check (insn, operands[0], 0)"
1141   "tstw %0")
1142
1143
1144 (define_insn "tsthi"
1145   [(set (cc0)
1146         (match_operand:HI 0 "extensible_operand" "m,!r"))]
1147   "GET_MODE (operands[0]) != VOIDmode"
1148   "*
1149 {
1150   rtx xoperands[2];
1151   extern rtx tahoe_reg_conversion_loc;
1152   switch (which_alternative)
1153     {
1154     case 0:
1155       return \"tstw %0\";
1156     case 1:
1157       xoperands[0] = operands[0];
1158       xoperands[1] = tahoe_reg_conversion_loc;
1159       output_asm_insn (\"movl %0,%1\", xoperands);
1160       xoperands[1] = plus_constant (XEXP (tahoe_reg_conversion_loc, 0), 2);
1161       output_asm_insn (\"tstw %a1\", xoperands);
1162       return \"\";
1163     }
1164 }")
1165
1166
1167 (define_insn ""
1168   [(set (cc0)
1169         (sign_extend:SI (match_operand:QI 0 "memory_operand" "m")))]
1170   ""
1171   "tstb %0")
1172
1173 (define_insn ""
1174   [(set (cc0)
1175         (zero_extend:SI (match_operand:QI 0 "memory_operand" "m")))]
1176   "tahoe_cmp_check (insn, operands[0], 0)"
1177   "tstb %0")
1178
1179
1180 (define_insn "tstqi"
1181   [(set (cc0)
1182         (match_operand:QI 0 "extensible_operand" "m,!r"))]
1183   "GET_MODE (operands[0]) != VOIDmode"
1184   "*
1185 {
1186   rtx xoperands[2];
1187   extern rtx tahoe_reg_conversion_loc;
1188   switch (which_alternative)
1189     {
1190     case 0:
1191       return \"tstb %0\";
1192     case 1:
1193       xoperands[0] = operands[0];
1194       xoperands[1] = tahoe_reg_conversion_loc;
1195       output_asm_insn (\"movl %0,%1\", xoperands);
1196       xoperands[1] = plus_constant (XEXP (tahoe_reg_conversion_loc, 0), 3);
1197       output_asm_insn (\"tstb %a1\", xoperands);
1198       return \"\";
1199     }
1200 }")
1201
1202 ; tstsf compares a given value to a value already in the fpp accumulator.
1203 ; No flags are set by this so ignore them.
1204
1205 (define_insn "tstsf"
1206   [(set (cc0)
1207         (match_operand:SF 0 "register_operand" "a"))]
1208   ""
1209   "tstf")
1210
1211
1212 ; tstdf compares a given value to a value already in the fpp accumulator.
1213 ; immediate doubles not allowed.  Flags are ignored after this.
1214
1215 (define_insn "tstdf"
1216   [(set (cc0)
1217         (match_operand:DF 0 "register_operand" "a"))]
1218   ""
1219   "tstd")
1220
1221
1222
1223 ; movstrhi tahoe instruction does not load registers by itself like
1224 ; the vax counterpart does.  registers 0-2 must be primed by hand.
1225 ; we have loaded the registers in the order: dst, src, count.
1226
1227 (define_insn "movstrhi"
1228   [(set (match_operand:BLK 0 "general_operand" "p")
1229          (match_operand:BLK 1 "general_operand" "p"))
1230    (use (match_operand:HI 2 "general_operand" "g"))
1231    (clobber (reg:SI 0))
1232    (clobber (reg:SI 1))
1233    (clobber (reg:SI 2))]
1234   ""
1235   "movab %0,r1\;movab %1,r0\;movl %2,r2\;movblk")
1236
1237
1238 ; floatsisf2 on tahoe converts the long from reg/mem into the fpp
1239 ; accumulator.  There are no hi and qi counterparts.  Flags are not
1240 ; set correctly here.
1241
1242 (define_insn "floatsisf2"
1243   [(set (match_operand:SF 0 "register_operand" "=a")
1244         (float:SF (match_operand:SI 1 "general_operand" "g")))]
1245   ""
1246   "*
1247 {
1248   CC_STATUS_INIT;
1249   return \"cvlf %1\";
1250 }")
1251
1252
1253 ; floatsidf2 on tahoe converts the long from reg/mem into the fpp
1254 ; accumulator.  There are no hi and qi counterparts.  Flags are not
1255 ; set correctly here.
1256
1257 (define_insn "floatsidf2"
1258   [(set (match_operand:DF 0 "register_operand" "=a")
1259         (float:DF (match_operand:SI 1 "general_operand" "g")))]
1260   ""
1261   "*
1262 {
1263   CC_STATUS_INIT;
1264   return \"cvld %1\";
1265 }")
1266
1267
1268 ; fix_truncsfsi2 to convert a float to long, tahoe must have the float
1269 ; in the fpp accumulator.  Flags are not set here.
1270
1271 (define_insn "fix_truncsfsi2"
1272   [(set (match_operand:SI 0 "general_operand" "=g")
1273         (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "a"))))]
1274   ""
1275   "*
1276 {
1277   CC_STATUS_INIT;
1278   return \"cvfl %0\";
1279 }")
1280
1281
1282 ; fix_truncsfsi2 to convert a double to long, tahoe must have the double
1283 ; in the fpp accumulator.  Flags are not set here.
1284
1285 (define_insn "fix_truncdfsi2"
1286   [(set (match_operand:SI 0 "general_operand" "=g")
1287         (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a"))))]
1288   ""
1289   "*
1290 {
1291   CC_STATUS_INIT;
1292   return \"cvdl %0\";
1293 }")
1294
1295
1296 (define_insn "truncsihi2"
1297   [(set (match_operand:HI 0 "general_operand" "=g")
1298         (truncate:HI (match_operand:SI 1 "general_operand" "g")))]
1299   ""
1300   "cvtlw %1,%0")
1301
1302
1303 (define_insn "truncsiqi2"
1304   [(set (match_operand:QI 0 "general_operand" "=g")
1305         (truncate:QI (match_operand:SI 1 "general_operand" "g")))]
1306   ""
1307   "cvtlb %1,%0")
1308
1309
1310 (define_insn "trunchiqi2"
1311   [(set (match_operand:QI 0 "general_operand" "=g")
1312         (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
1313   ""
1314   "cvtwb %1,%0")
1315
1316
1317 ; The fpp related instructions don't set flags, so ignore them
1318 ; after this instruction.
1319
1320 (define_insn "truncdfsf2"
1321   [(set (match_operand:SF 0 "register_operand" "=a")
1322         (float_truncate:SF (match_operand:DF 1 "register_operand" "0")))]
1323   ""
1324   "*
1325 {
1326   CC_STATUS_INIT;
1327   return \"cvdf\";
1328 }")
1329
1330
1331 ; This monster is to cover for the Tahoe's nasty habit of not extending
1332 ; a number if the source is in a register.  (It just moves it!) Case 0 is
1333 ; a normal extend from memory.  Case 1 does the extension from the top of
1334 ; the stack.  Extension from the stack doesn't set the flags right since
1335 ; the moval changes them.
1336
1337 (define_insn "extendhisi2"
1338   [(set (match_operand:SI 0 "general_operand" "=g,?=g")
1339         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
1340   ""
1341   "*
1342 {
1343   switch (which_alternative)
1344     {
1345     case 0:
1346       return \"cvtwl %1,%0\";
1347     case 1:
1348       if (push_operand (operands[0], SImode))
1349         return \"pushl %1\;cvtwl 2(sp),(sp)\";
1350       else
1351         {
1352           CC_STATUS_INIT;
1353           return \"pushl %1\;cvtwl 2(sp),%0\;moval 4(sp),sp\";
1354         }
1355     }
1356 }")
1357
1358 ; This monster is to cover for the Tahoe's nasty habit of not extending
1359 ; a number if the source is in a register.  (It just moves it!) Case 0 is
1360 ; a normal extend from memory.  Case 1 does the extension from the top of
1361 ; the stack.  Extension from the stack doesn't set the flags right since
1362 ; the moval changes them.
1363
1364 (define_insn "extendqisi2"
1365   [(set (match_operand:SI 0 "general_operand" "=g,?=g")
1366         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
1367   ""
1368   "*
1369 {
1370   switch (which_alternative)
1371     {
1372     case 0:
1373       return \"cvtbl %1,%0\";
1374     case 1:
1375       if (push_operand (operands[0], SImode))
1376         return \"pushl %1\;cvtbl 3(sp),(sp)\";
1377       else
1378         {
1379           CC_STATUS_INIT;
1380           return \"pushl %1\;cvtbl 3(sp),%0\;moval 4(sp),sp\";
1381         }
1382     }
1383 }")
1384
1385
1386 ; This monster is to cover for the Tahoe's nasty habit of not extending
1387 ; a number if the source is in a register.  (It just moves it!) Case 0 is
1388 ; a normal extend from memory.  Case 1 does the extension from the top of
1389 ; the stack.  Extension from the stack doesn't set the flags right since
1390 ; the moval changes them.
1391
1392 (define_insn "extendqihi2"
1393   [(set (match_operand:HI 0 "general_operand" "=g,?=g")
1394         (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
1395   ""
1396   "*
1397 {
1398   switch (which_alternative)
1399     {
1400     case 0:
1401       return \"cvtbw %1,%0\";
1402     case 1:
1403       if (push_operand (operands[0], SImode))
1404         return \"pushl %1\;cvtbw 3(sp),(sp)\";
1405       else
1406         {
1407           CC_STATUS_INIT;
1408           return \"pushl %1\;cvtbw 3(sp),%0\;moval 4(sp),sp\";
1409         }
1410      }
1411 }")
1412
1413
1414 ; extendsfdf2 tahoe uses the fpp accumulator to do the extension.
1415 ; It takes a float and loads it up directly as a double.
1416
1417 (define_insn "extendsfdf2"
1418   [(set (match_operand:DF 0 "register_operand" "=a")
1419         (float_extend:DF (match_operand:SF 1 "general_operand" "g")))]
1420   ""
1421   "*
1422 {
1423   CC_STATUS_INIT;
1424   return \"ldfd %1\";
1425 }")
1426
1427
1428 ; movz works fine from memory but not from register for the same reasons
1429 ; the cvt instructions don't work right.  So we use the normal instruction
1430 ; from memory and we use an and to simulate it from register.  This is faster
1431 ; than pulling it off the stack.
1432
1433
1434 (define_insn "zero_extendhisi2"
1435   [(set (match_operand:SI 0 "general_operand" "=g,?=g")
1436         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
1437   ""
1438   "*
1439 {
1440   switch (which_alternative)
1441     {
1442     case 0: return \"movzwl %1,%0\";
1443     case 1: return \"andl3 $0xffff,%1,%0\";
1444     }
1445 }")
1446
1447 ; movz works fine from memory but not from register for the same reasons
1448 ; the cvt instructions don't work right.  So we use the normal instruction
1449 ; from memory and we use an and to simulate it from register.  This is faster
1450 ; than pulling it off the stack.
1451
1452 (define_insn "zero_extendqihi2"
1453   [(set (match_operand:HI 0 "general_operand" "=g,?=g")
1454         (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
1455   ""
1456   "*
1457 {
1458   switch (which_alternative)
1459     {
1460     case 0: return \"movzbw %1,%0\";
1461     case 1: return \"andw3 $0xff,%1,%0\";
1462     }
1463 }")
1464
1465
1466 ; movz works fine from memory but not from register for the same reasons
1467 ; the cvt instructions don't work right.  So we use the normal instruction
1468 ; from memory and we use an and to simulate it from register.  This is faster
1469 ; than pulling it off the stack.
1470
1471 (define_insn "zero_extendqisi2"
1472   [(set (match_operand:SI 0 "general_operand" "=g,?=g")
1473         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
1474   ""
1475   "*
1476 {
1477   switch (which_alternative)
1478     {
1479     case 0: return \"movzbl %1,%0\";
1480     case 1: return \"andl3 $0xff,%1,%0\";
1481     }
1482 }")
1483
1484
1485 (define_insn "beq"
1486   [(set (pc)
1487         (if_then_else (eq (cc0)
1488                           (const_int 0))
1489                       (label_ref (match_operand 0 "" ""))
1490                       (pc)))]
1491   ""
1492   "jeql %l0")
1493
1494
1495 (define_insn "bne"
1496   [(set (pc)
1497         (if_then_else (ne (cc0)
1498                           (const_int 0))
1499                       (label_ref (match_operand 0 "" ""))
1500                       (pc)))]
1501   ""
1502   "jneq %l0")
1503
1504
1505 (define_insn "bgt"
1506   [(set (pc)
1507         (if_then_else (gt (cc0)
1508                           (const_int 0))
1509                       (label_ref (match_operand 0 "" ""))
1510                       (pc)))]
1511   ""
1512   "jgtr %l0")
1513
1514
1515 (define_insn "bgtu"
1516   [(set (pc)
1517         (if_then_else (gtu (cc0)
1518                            (const_int 0))
1519                       (label_ref (match_operand 0 "" ""))
1520                       (pc)))]
1521   ""
1522   "jgtru %l0")
1523
1524
1525 (define_insn "blt"
1526   [(set (pc)
1527         (if_then_else (lt (cc0)
1528                           (const_int 0))
1529                       (label_ref (match_operand 0 "" ""))
1530                       (pc)))]
1531   ""
1532   "jlss %l0")
1533
1534
1535 (define_insn "bltu"
1536   [(set (pc)
1537         (if_then_else (ltu (cc0)
1538                            (const_int 0))
1539                       (label_ref (match_operand 0 "" ""))
1540                       (pc)))]
1541   ""
1542   "jlssu %l0")
1543
1544
1545 (define_insn "bge"
1546   [(set (pc)
1547         (if_then_else (ge (cc0)
1548                           (const_int 0))
1549                       (label_ref (match_operand 0 "" ""))
1550                       (pc)))]
1551   ""
1552   "jgeq %l0")
1553
1554
1555 (define_insn "bgeu"
1556   [(set (pc)
1557         (if_then_else (geu (cc0)
1558                            (const_int 0))
1559                       (label_ref (match_operand 0 "" ""))
1560                       (pc)))]
1561   ""
1562   "jgequ %l0")
1563
1564
1565 (define_insn "ble"
1566   [(set (pc)
1567         (if_then_else (le (cc0)
1568                           (const_int 0))
1569                       (label_ref (match_operand 0 "" ""))
1570                       (pc)))]
1571   ""
1572   "jleq %l0")
1573
1574
1575 (define_insn "bleu"
1576   [(set (pc)
1577         (if_then_else (leu (cc0)
1578                            (const_int 0))
1579                       (label_ref (match_operand 0 "" ""))
1580                       (pc)))]
1581   ""
1582   "jlequ %l0")
1583
1584
1585 ; gcc does not account for register mask/argc longword.  Thus the number
1586 ; for the call = number bytes for args + 4
1587
1588 (define_insn "call"
1589   [(call (match_operand:QI 0 "memory_operand" "m")
1590          (match_operand:QI 1 "general_operand" "g"))]
1591   ""
1592   "*
1593 {
1594   operands[1] = GEN_INT ((INTVAL (operands[1]) + 4));
1595   if (GET_CODE(operands[0]) == MEM
1596       && CONSTANT_ADDRESS_P (XEXP(operands[0], 0))
1597       && INTVAL (operands[1]) < 64)
1598     return \"callf %1,%0\"; /* this is much faster */
1599   return \"calls %1,%0\";
1600 }")
1601
1602 ; gcc does not account for register mask/argc longword.  Thus the number
1603 ; for the call = number bytes for args + 4
1604
1605 (define_insn "call_value"
1606   [(set (match_operand 0 "" "=g")
1607         (call (match_operand:QI 1 "memory_operand" "m")
1608               (match_operand:QI 2 "general_operand" "g")))]
1609   ""
1610   "*
1611 {
1612   operands[2] = GEN_INT ((INTVAL (operands[2]) + 4));
1613   if (GET_CODE(operands[1]) == MEM
1614       && CONSTANT_ADDRESS_P (XEXP(operands[1], 0))
1615       && INTVAL (operands[2]) < 64)
1616     return \"callf %2,%1\"; /* this is much faster */
1617   return \"calls %2,%1\";
1618 }")
1619
1620
1621 (define_insn "return"
1622   [(return)]
1623   ""
1624   "ret")
1625
1626 (define_insn "nop"
1627   [(const_int 0)]
1628   ""
1629   "nop")
1630
1631 ; casesi this code extracted from the vax code.  The instructions are
1632 ; very similar.  Tahoe requires that the table be word aligned.  GCC
1633 ; places the table immediately after, thus the alignment directive.
1634
1635 (define_insn "casesi"
1636   [(set (pc)
1637         (if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
1638                                     (match_operand:SI 1 "general_operand" "g"))
1639                           (match_operand:SI 2 "general_operand" "g"))
1640                       (plus:SI (sign_extend:SI
1641                                 (mem:HI (plus:SI (pc)
1642                                                  (minus:SI (match_dup 0)
1643                                                            (match_dup 1)))))
1644                                (label_ref:SI (match_operand 3 "" "")))
1645                       (pc)))]
1646   ""
1647   "casel %0,%1,%2\;.align %@")
1648
1649
1650 (define_insn "jump"
1651   [(set (pc)
1652         (label_ref (match_operand 0 "" "")))]
1653   ""
1654   "jbr %l0")
1655
1656
1657 ;; This is the list of all the non-standard insn patterns
1658
1659
1660 ; This is used to access the address of a byte.  This is similar to
1661 ; movqi, but the second operand had to be "address_operand" type, so
1662 ; it had to be an unnamed one.
1663
1664 (define_insn ""
1665   [(set (match_operand:SI 0 "general_operand" "=g")
1666         (match_operand:QI 1 "address_operand" "p"))]
1667   ""
1668   "*
1669 {
1670   if (push_operand (operands[0], SImode))
1671     return \"pushab %a1\";
1672   return \"movab %a1,%0\";
1673 }")
1674
1675 ; This is used to access the address of a word.  This is similar to
1676 ; movhi, but the second operand had to be "address_operand" type, so
1677 ; it had to be an unnamed one.
1678
1679 (define_insn ""
1680   [(set (match_operand:SI 0 "general_operand" "=g")
1681         (match_operand:HI 1 "address_operand" "p"))]
1682   ""
1683   "*
1684 {
1685   if (push_operand (operands[0], SImode))
1686     return \"pushaw %a1\";
1687   return \"movaw %a1,%0\";
1688 }")
1689
1690 ; This is used to access the address of a long.  This is similar to
1691 ; movsi, but the second operand had to be "address_operand" type, so
1692 ; it had to be an unnamed one.
1693
1694 (define_insn ""
1695   [(set (match_operand:SI 0 "general_operand" "=g")
1696         (match_operand:SI 1 "address_operand" "p"))]
1697   ""
1698   "*
1699 {
1700   if (push_operand (operands[0], SImode))
1701     return \"pushal %a1\";
1702   return \"moval %a1,%0\";
1703 }")
1704
1705
1706 ; bit test longword instruction, same as vax
1707
1708 (define_insn ""
1709   [(set (cc0)
1710         (and:SI (match_operand:SI 0 "general_operand" "g")
1711                 (match_operand:SI 1 "general_operand" "g")))]
1712   ""
1713   "bitl %0,%1")
1714
1715
1716 ; bit test word instructions, same as vax
1717
1718 (define_insn ""
1719   [(set (cc0)
1720         (and:HI (match_operand:HI 0 "general_operand" "g")
1721                 (match_operand:HI 1 "general_operand" "g")))]
1722   ""
1723   "bitw %0,%1")
1724
1725
1726 ; bit test instructions, same as vax
1727
1728 (define_insn ""
1729   [(set (cc0)
1730         (and:QI (match_operand:QI 0 "general_operand" "g")
1731                 (match_operand:QI 1 "general_operand" "g")))]
1732   ""
1733   "bitb %0,%1")
1734
1735
1736 ; bne counterpart.  in case gcc reverses the conditional.
1737
1738 (define_insn ""
1739   [(set (pc)
1740         (if_then_else (eq (cc0)
1741                           (const_int 0))
1742                       (pc)
1743                       (label_ref (match_operand 0 "" ""))))]
1744   ""
1745   "jneq %l0")
1746
1747
1748 ; beq counterpart.  in case gcc reverses the conditional.
1749
1750 (define_insn ""
1751   [(set (pc)
1752         (if_then_else (ne (cc0)
1753                           (const_int 0))
1754                       (pc)
1755                       (label_ref (match_operand 0 "" ""))))]
1756   ""
1757   "jeql %l0")
1758
1759
1760 ; ble counterpart.  in case gcc reverses the conditional.
1761
1762 (define_insn ""
1763   [(set (pc)
1764         (if_then_else (gt (cc0)
1765                           (const_int 0))
1766                       (pc)
1767                       (label_ref (match_operand 0 "" ""))))]
1768   ""
1769   "jleq %l0")
1770
1771
1772 ; bleu counterpart.  in case gcc reverses the conditional.
1773
1774 (define_insn ""
1775   [(set (pc)
1776         (if_then_else (gtu (cc0)
1777                            (const_int 0))
1778                       (pc)
1779                       (label_ref (match_operand 0 "" ""))))]
1780   ""
1781   "jlequ %l0")
1782
1783
1784 ; bge counterpart.  in case gcc reverses the conditional.
1785
1786 (define_insn ""
1787   [(set (pc)
1788         (if_then_else (lt (cc0)
1789                           (const_int 0))
1790                       (pc)
1791                       (label_ref (match_operand 0 "" ""))))]
1792   ""
1793   "jgeq %l0")
1794
1795
1796 ; bgeu counterpart.  in case gcc reverses the conditional.
1797
1798 (define_insn ""
1799   [(set (pc)
1800         (if_then_else (ltu (cc0)
1801                            (const_int 0))
1802                       (pc)
1803                       (label_ref (match_operand 0 "" ""))))]
1804   ""
1805   "jgequ %l0")
1806
1807
1808 ; blt counterpart.  in case gcc reverses the conditional.
1809
1810 (define_insn ""
1811   [(set (pc)
1812         (if_then_else (ge (cc0)
1813                           (const_int 0))
1814                       (pc)
1815                       (label_ref (match_operand 0 "" ""))))]
1816   ""
1817   "jlss %l0")
1818
1819
1820 ; bltu counterpart.  in case gcc reverses the conditional.
1821
1822 (define_insn ""
1823   [(set (pc)
1824         (if_then_else (geu (cc0)
1825                            (const_int 0))
1826                       (pc)
1827                       (label_ref (match_operand 0 "" ""))))]
1828   ""
1829   "jlssu %l0")
1830
1831
1832 ; bgt counterpart.  in case gcc reverses the conditional.
1833
1834 (define_insn ""
1835   [(set (pc)
1836         (if_then_else (le (cc0)
1837                           (const_int 0))
1838                       (pc)
1839                       (label_ref (match_operand 0 "" ""))))]
1840   ""
1841   "jgtr %l0")
1842
1843
1844 ; bgtu counterpart.  in case gcc reverses the conditional.
1845
1846 (define_insn ""
1847   [(set (pc)
1848         (if_then_else (leu (cc0)
1849                            (const_int 0))
1850                       (pc)
1851                       (label_ref (match_operand 0 "" ""))))]
1852   ""
1853   "jgtru %l0")
1854
1855
1856 ; casesi alternate form as found in vax code.  this form is to
1857 ; compensate for the table's offset being no distance (0 displacement)
1858
1859 (define_insn ""
1860   [(set (pc)
1861         (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1862                           (match_operand:SI 1 "general_operand" "g"))
1863                       (plus:SI (sign_extend:SI
1864                                 (mem:HI (plus:SI (pc)
1865                                                  (minus:SI (match_dup 0)
1866                                                            (const_int 0)))))
1867                                (label_ref:SI (match_operand 3 "" "")))
1868                       (pc)))]
1869   ""
1870   "casel %0,$0,%1\;.align %@")
1871
1872
1873 ; casesi alternate form as found in vax code.  another form to
1874 ; compensate for the table's offset being no distance (0 displacement)
1875
1876 (define_insn ""
1877   [(set (pc)
1878         (if_then_else (le (match_operand:SI 0 "general_operand" "g")
1879                           (match_operand:SI 1 "general_operand" "g"))
1880                       (plus:SI (sign_extend:SI
1881                                 (mem:HI (plus:SI (pc)
1882                                                  (match_dup 0))))
1883                                (label_ref:SI (match_operand 3 "" "")))
1884                       (pc)))]
1885   ""
1886   "casel %0,$0,%1 \;.align %@")
1887
1888 (define_insn ""
1889   [(set (pc)
1890         (if_then_else
1891          (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1892                       (const_int 1))
1893              (match_operand:SI 1 "general_operand" "g"))
1894          (label_ref (match_operand 2 "" ""))
1895          (pc)))
1896    (set (match_dup 0)
1897         (plus:SI (match_dup 0)
1898                  (const_int 1)))]
1899   ""
1900   "aoblss %1,%0,%l2")
1901
1902 (define_insn ""
1903   [(set (pc)
1904         (if_then_else
1905          (le (plus:SI (match_operand:SI 0 "general_operand" "+g")
1906                       (const_int 1))
1907              (match_operand:SI 1 "general_operand" "g"))
1908          (label_ref (match_operand 2 "" ""))
1909          (pc)))
1910    (set (match_dup 0)
1911         (plus:SI (match_dup 0)
1912                  (const_int 1)))]
1913   ""
1914   "aobleq %1,%0,%l2")
1915
1916 (define_insn ""
1917   [(set (pc)
1918         (if_then_else
1919          (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")
1920                       (const_int 1))
1921              (match_operand:SI 1 "general_operand" "g"))
1922          (pc)
1923          (label_ref (match_operand 2 "" ""))))
1924    (set (match_dup 0)
1925         (plus:SI (match_dup 0)
1926                  (const_int 1)))]
1927   ""
1928   "aoblss %1,%0,%l2")
1929
1930 (define_insn ""
1931   [(set (pc)
1932         (if_then_else
1933          (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")
1934                       (const_int 1))
1935              (match_operand:SI 1 "general_operand" "g"))
1936          (pc)
1937          (label_ref (match_operand 2 "" ""))))
1938    (set (match_dup 0)
1939         (plus:SI (match_dup 0)
1940                  (const_int 1)))]
1941   ""
1942   "aobleq %1,%0,%l2")
1943
1944 ; bbs/bbc
1945
1946 (define_insn ""
1947   [(set (pc)
1948         (if_then_else
1949          (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
1950                               (const_int 1)
1951                       (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
1952              (const_int 0))
1953          (label_ref (match_operand 2 "" ""))
1954          (pc)))]
1955   ""
1956   "bbs %1,%0,%l2")
1957
1958 (define_insn ""
1959   [(set (pc)
1960         (if_then_else
1961          (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
1962                               (const_int 1)
1963                       (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
1964              (const_int 0))
1965          (label_ref (match_operand 2 "" ""))
1966          (pc)))]
1967   ""
1968   "bbc %1,%0,%l2")
1969
1970 (define_insn ""
1971   [(set (pc)
1972         (if_then_else
1973          (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
1974                               (const_int 1)
1975                       (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
1976              (const_int 0))
1977          (pc)
1978          (label_ref (match_operand 2 "" ""))))]
1979   ""
1980   "bbc %1,%0,%l2")
1981
1982 (define_insn ""
1983   [(set (pc)
1984         (if_then_else
1985          (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
1986                               (const_int 1)
1987                       (subreg:QI (match_operand:SI 1 "general_operand" "g") 0))
1988              (const_int 0))
1989          (pc)
1990          (label_ref (match_operand 2 "" ""))))]
1991   ""
1992   "bbs %1,%0,%l2")
1993
1994 ; if the shift count is a byte in a register we can use it as a long
1995
1996 (define_insn ""
1997   [(set (pc)
1998         (if_then_else
1999          (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
2000                               (const_int 1)
2001                               (match_operand:QI 1 "register_operand" "r"))
2002              (const_int 0))
2003          (label_ref (match_operand 2 "" ""))
2004          (pc)))]
2005   ""
2006   "bbs %1,%0,%l2")
2007
2008 (define_insn ""
2009   [(set (pc)
2010         (if_then_else
2011          (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
2012                               (const_int 1)
2013                               (match_operand:QI 1 "register_operand" "r"))
2014              (const_int 0))
2015          (label_ref (match_operand 2 "" ""))
2016          (pc)))]
2017   ""
2018   "bbc %1,%0,%l2")
2019
2020 (define_insn ""
2021   [(set (pc)
2022         (if_then_else
2023          (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
2024                               (const_int 1)
2025                               (match_operand:QI 1 "register_operand" "r"))
2026              (const_int 0))
2027          (pc)
2028          (label_ref (match_operand 2 "" ""))))]
2029   ""
2030   "bbc %1,%0,%l2")
2031
2032 (define_insn ""
2033   [(set (pc)
2034         (if_then_else
2035          (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "rm")
2036                               (const_int 1)
2037                               (match_operand:QI 1 "register_operand" "r"))
2038              (const_int 0))
2039          (pc)
2040          (label_ref (match_operand 2 "" ""))))]
2041   ""
2042   "bbs %1,%0,%l2")
2043
2044 ; special case for 1 << constant.  We don't do these because they are slower
2045 ; than the bitl instruction
2046
2047 ;(define_insn ""
2048 ;  [(set (pc)
2049 ;       (if_then_else
2050 ;        (ne (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
2051 ;                    (match_operand:SI 1 "immediate_operand" "i"))
2052 ;            (const_int 0))
2053 ;        (label_ref (match_operand 2 "" ""))
2054 ;        (pc)))]
2055 ;  "GET_CODE (operands[1]) == CONST_INT
2056 ;   && exact_log2 (INTVAL (operands[1])) >= 0"
2057 ;  "*
2058 ;{
2059 ;  operands[1]
2060 ;    = GEN_INT (exact_log2 (INTVAL (operands[1])));
2061 ;  return \"bbs %1,%0,%l2\";
2062 ;}")
2063 ;
2064 ;(define_insn ""
2065 ;  [(set (pc)
2066 ;       (if_then_else
2067 ;        (eq (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
2068 ;                    (match_operand:SI 1 "immediate_operand" "i"))
2069 ;            (const_int 0))
2070 ;        (label_ref (match_operand 2 "" ""))
2071 ;        (pc)))]
2072 ;  "GET_CODE (operands[1]) == CONST_INT
2073 ;   && exact_log2 (INTVAL (operands[1])) >= 0"
2074 ;  "*
2075 ;{
2076 ;  operands[1]
2077 ;    = GEN_INT (exact_log2 (INTVAL (operands[1])));
2078 ;  return \"bbc %1,%0,%l2\";
2079 ;}")
2080 ;
2081 ;(define_insn ""
2082 ;  [(set (pc)
2083 ;       (if_then_else
2084 ;        (ne (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
2085 ;                    (match_operand:SI 1 "immediate_operand" "i"))
2086 ;            (const_int 0))
2087 ;        (pc)
2088 ;        (label_ref (match_operand 2 "" ""))))]
2089 ;  "GET_CODE (operands[1]) == CONST_INT
2090 ;   && exact_log2 (INTVAL (operands[1])) >= 0"
2091 ;  "*
2092 ;{
2093 ;  operands[1]
2094 ;    = GEN_INT (exact_log2 (INTVAL (operands[1])));
2095 ;  return \"bbc %1,%0,%l2\";
2096 ;}")
2097 ;
2098 ;(define_insn ""
2099 ;  [(set (pc)
2100 ;       (if_then_else
2101 ;        (eq (and:SI (match_operand:SI 0 "nonimmediate_operand" "%rm")
2102 ;                    (match_operand:SI 1 "immediate_operand" "i"))
2103 ;            (const_int 0))
2104 ;        (pc)
2105 ;        (label_ref (match_operand 2 "" ""))))]
2106 ;  "GET_CODE (operands[1]) == CONST_INT
2107 ;   && exact_log2 (INTVAL (operands[1])) >= 0"
2108 ;  "*
2109 ;{
2110 ;  operands[1]
2111 ;    = GEN_INT (exact_log2 (INTVAL (operands[1])));
2112 ;  return \"bbs %1,%0,%l2\";
2113 ;}")