gcc/config/we32k/we32k.c

   1 /* Subroutines for insn-output.c for AT&T we32000 Family.
   2    Copyright (C) 1991, 92, 1997, 1998, 1999, 2000
   3    Free Software Foundation, Inc.
   4    Contributed by John Wehle (john@feith1.uucp)
   5
   6 This file is part of GNU CC.
   7
   8 GNU CC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 1, or (at your option)
  11 any later version.
  12
  13 GNU CC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GNU CC; see the file COPYING.  If not, write to
  20 the Free Software Foundation, 59 Temple Place - Suite 330,
  21 Boston, MA 02111-1307, USA.  */
  22
  23
  24 #include "config.h"
  25 #include "system.h"
  26 #include "insn-config.h"
  27 #include "rtl.h"
  28 #include "function.h"
  29 #include "real.h"
  30 #include "recog.h"
  31 #include "output.h"
  32 #include "tm_p.h"
  33
  34 void
  35 output_move_double (operands)
  36      rtx *operands;
  37 {
  38   rtx lsw_operands[2];
  39   rtx lsw_sreg = NULL;
  40   rtx msw_dreg = NULL;
  41
  42   if (GET_CODE (operands[0]) == REG)
  43     {
  44       lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
  45       msw_dreg = operands[0];
  46     }
  47   else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
  48     lsw_operands[0] = adj_offsettable_operand (operands[0], 4);
  49   else
  50     abort ();
  51
  52   if (GET_CODE (operands[1]) == REG)
  53     {
  54       lsw_operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
  55       lsw_sreg = lsw_operands[1];
  56     }
  57   else if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
  58     {
  59       lsw_operands[1] = adj_offsettable_operand (operands[1], 4);
  60       lsw_sreg = operands[1];
  61       for ( ; ; )
  62         {
  63           if (REG_P (lsw_sreg))
  64             break;
  65           if (CONSTANT_ADDRESS_P (lsw_sreg))
  66             {
  67               lsw_sreg = NULL;
  68               break;
  69             }
  70           if (GET_CODE (lsw_sreg) == MEM)
  71             {
  72               lsw_sreg = XEXP (lsw_sreg, 0);
  73               continue;
  74             }
  75           if (GET_CODE (lsw_sreg) == PLUS)
  76             {
  77               if (CONSTANT_ADDRESS_P (XEXP (lsw_sreg, 1)))
  78                 {
  79                   lsw_sreg = XEXP (lsw_sreg, 0);
  80                   continue;
  81                 }
  82               else if (CONSTANT_ADDRESS_P (XEXP (lsw_sreg, 0)))
  83                 {
  84                   lsw_sreg = XEXP (lsw_sreg, 1);
  85                   continue;
  86                 }
  87             }
  88           abort ();
  89         }
  90     }
  91   else if (GET_CODE (operands[1]) == CONST_DOUBLE)
  92     {
  93       lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
  94       operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
  95     }
  96   else if (GET_CODE (operands[1]) == CONST_INT)
  97     {
  98       lsw_operands[1] = operands[1];
  99       operands[1] = const0_rtx;
 100     }
 101   else
 102     abort ();
 103
 104   if (!msw_dreg || !lsw_sreg || REGNO (msw_dreg) != REGNO (lsw_sreg))
 105     {
 106       output_asm_insn ("movw %1, %0", operands);
 107       output_asm_insn ("movw %1, %0", lsw_operands);
 108     }
 109   else
 110     {
 111       output_asm_insn ("movw %1, %0", lsw_operands);
 112       output_asm_insn ("movw %1, %0", operands);
 113     }
 114 }
 115
 116 void
 117 output_push_double (operands)
 118      rtx *operands;
 119 {
 120   rtx lsw_operands[1];
 121
 122   if (GET_CODE (operands[0]) == REG)
 123     lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
 124   else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
 125     lsw_operands[0] = adj_offsettable_operand (operands[0], 4);
 126   else if (GET_CODE (operands[0]) == CONST_DOUBLE)
 127     {
 128       lsw_operands[0] = GEN_INT (CONST_DOUBLE_HIGH (operands[0]));
 129       operands[0] = GEN_INT (CONST_DOUBLE_LOW (operands[0]));
 130     }
 131   else if (GET_CODE (operands[0]) == CONST_INT)
 132     {
 133       lsw_operands[0] = operands[0];
 134       operands[0] = const0_rtx;
 135     }
 136   else
 137     abort ();
 138
 139   output_asm_insn ("pushw %0", operands);
 140   output_asm_insn ("pushw %0", lsw_operands);
 141 }