gcc/config/we32k/we32k.md

   1 ;; Machine description for GNU compiler, AT&T we32000 Version
   2 ;; Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc.
   3 ;; Contributed by John Wehle (john@feith1.uucp)
   4
   5 ;; This file is part of GNU CC.
   6
   7 ;; GNU CC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 1, or (at your option)
  10 ;; any later version.
  11
  12 ;; GNU CC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GNU CC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  20 ;; Boston, MA 02111-1307, USA.
  21
  22
  23 ;;- instruction definitions
  24
  25 ;;- @@The original PO technology requires these to be ordered by speed,
  26 ;;- @@    so that assigner will pick the fastest.
  27
  28 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
  29
  30 ;;- When naming insn's (operand 0 of define_insn) be careful about using
  31 ;;- names from other targets machine descriptions.
  32 \f
  33 ;; move instructions
  34
  35 (define_insn ""
  36   [(set (match_operand:DF 0 "push_operand" "=m")
  37         (match_operand:DF 1 "general_operand" "mrF"))]
  38   ""
  39   "*
  40   {
  41   output_push_double(&operands[1]);
  42
  43   return \"\";
  44   }")
  45
  46 (define_insn "movdf"
  47   [(set (match_operand:DF 0 "nonimmediate_operand" "=mr")
  48         (match_operand:DF 1 "general_operand" "mrF"))]
  49   ""
  50   "*
  51   {
  52   output_move_double(operands);
  53
  54   return \"\";
  55   }")
  56
  57 (define_insn ""
  58   [(set (match_operand:SF 0 "push_operand" "=m")
  59         (match_operand:SF 1 "general_operand" "mrF"))]
  60   ""
  61   "pushw %1")
  62
  63 (define_insn "movsf"
  64   [(set (match_operand:SF 0 "nonimmediate_operand" "=mr")
  65         (match_operand:SF 1 "general_operand" "mrF"))]
  66   ""
  67   "movw %1, %0")
  68
  69 (define_insn ""
  70   [(set (match_operand:DI 0 "push_operand" "=m")
  71         (match_operand:DI 1 "general_operand" "mriF"))]
  72   ""
  73   "*
  74   {
  75   output_push_double(&operands[1]);
  76
  77   return \"\";
  78   }")
  79
  80 (define_insn "movdi"
  81   [(set (match_operand:DI 0 "nonimmediate_operand" "=mr")
  82         (match_operand:DI 1 "general_operand" "mriF"))]
  83   ""
  84   "*
  85   {
  86   output_move_double(operands);
  87
  88   return \"\";
  89   }")
  90
  91 (define_insn ""
  92   [(set (match_operand:SI 0 "push_operand" "=m")
  93         (match_operand:SI 1 "general_operand" "mri"))]
  94   ""
  95   "pushw %1")
  96
  97 (define_insn "movsi"
  98   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
  99         (match_operand:SI 1 "general_operand" "mri"))]
 100   ""
 101   "movw %1, %0")
 102
 103 (define_insn "movhi"
 104   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 105         (match_operand:HI 1 "general_operand" "mri"))]
 106   ""
 107   "movh %1, %0")
 108
 109 (define_insn "movqi"
 110   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 111         (match_operand:QI 1 "general_operand" "mri"))]
 112   ""
 113   "movb %1, %0")
 114 \f
 115 ;; add instructions
 116
 117 (define_insn ""
 118   [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
 119         (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
 120                  (match_operand:DI 2 "general_operand" "oriF")))]
 121   ""
 122   "*
 123   {
 124   rtx label[1];
 125   rtx lsw_operands[3];
 126
 127   if (GET_CODE (operands[0]) == REG)
 128     lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
 129   else
 130     if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
 131       lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
 132     else
 133       abort();
 134
 135   if (GET_CODE (operands[2]) == REG)
 136     lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
 137   else
 138     if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
 139       lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
 140     else
 141       if (GET_CODE (operands[2]) == CONST_DOUBLE)
 142         {
 143         lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
 144         operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
 145         }
 146       else
 147         if (GET_CODE (operands[2]) == CONST_INT)
 148           {
 149           lsw_operands[2] = operands[2];
 150           operands[2] = const0_rtx;
 151           }
 152         else
 153           abort();
 154
 155   label[0] = gen_label_rtx();
 156   LABEL_NUSES(label[0]) = 1;
 157
 158   output_asm_insn(\"addw2 %2, %0\", operands);
 159   output_asm_insn(\"addw2 %2, %0\", lsw_operands);
 160   output_asm_insn(\"BCCB %l0\", label);
 161   output_asm_insn(\"INCW %0\", operands);
 162   output_asm_insn(\"%l0:\", label);
 163
 164   return \"\";
 165   }")
 166
 167 (define_insn "adddi3"
 168   [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
 169         (plus:DI (match_operand:DI 1 "general_operand" "oriF")
 170                  (match_operand:DI 2 "general_operand" "oriF")))]
 171   ""
 172   "*
 173   {
 174   rtx label[1];
 175   rtx lsw_operands[3];
 176
 177   if (GET_CODE (operands[0]) == REG)
 178     lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
 179   else
 180     if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
 181       lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
 182     else
 183       abort();
 184
 185   if (GET_CODE (operands[1]) == REG)
 186     lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
 187   else
 188     if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
 189       lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
 190     else
 191       if (GET_CODE (operands[1]) == CONST_DOUBLE)
 192         {
 193         lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH(operands[1]));
 194         operands[1] = GEN_INT (CONST_DOUBLE_LOW(operands[1]));
 195         }
 196       else
 197         if (GET_CODE (operands[1]) == CONST_INT)
 198           {
 199           lsw_operands[1] = operands[1];
 200           operands[1] = const0_rtx;
 201           }
 202         else
 203           abort();
 204
 205   if (GET_CODE (operands[2]) == REG)
 206     lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
 207   else
 208     if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
 209       lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
 210     else
 211       if (GET_CODE (operands[2]) == CONST_DOUBLE)
 212         {
 213         lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
 214         operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
 215         }
 216       else
 217         if (GET_CODE (operands[2]) == CONST_INT)
 218           {
 219           lsw_operands[2] = operands[2];
 220           operands[2] = const0_rtx;
 221           }
 222         else
 223           abort();
 224
 225   label[0] = gen_label_rtx();
 226   LABEL_NUSES(label[0]) = 1;
 227
 228   output_asm_insn(\"addw3 %2, %1, %0\", operands);
 229   output_asm_insn(\"addw3 %2, %1, %0\", lsw_operands);
 230   output_asm_insn(\"BCCB %l0\", label);
 231   output_asm_insn(\"INCW %0\", operands);
 232   output_asm_insn(\"%l0:\", label);
 233
 234   return \"\";
 235   }")
 236
 237 (define_insn ""
 238   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 239         (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 240                  (match_operand:SI 2 "general_operand" "mri")))]
 241   ""
 242   "addw2 %2, %0")
 243
 244 (define_insn "addsi3"
 245   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 246         (plus:SI (match_operand:SI 1 "general_operand" "mri")
 247                  (match_operand:SI 2 "general_operand" "mri")))]
 248   ""
 249   "addw3 %2, %1, %0")
 250
 251 (define_insn ""
 252   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 253         (plus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
 254                  (match_operand:HI 2 "general_operand" "mri")))]
 255   ""
 256   "addh2 %2, %0")
 257
 258 (define_insn "addhi3"
 259   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 260         (plus:HI (match_operand:HI 1 "general_operand" "mri")
 261                  (match_operand:HI 2 "general_operand" "mri")))]
 262   ""
 263   "addh3 %2, %1, %0")
 264
 265 (define_insn ""
 266   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 267         (plus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
 268                  (match_operand:QI 2 "general_operand" "mri")))]
 269   ""
 270   "addb2 %2, %0")
 271
 272 (define_insn "addqi3"
 273   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 274         (plus:QI (match_operand:QI 1 "general_operand" "mri")
 275                  (match_operand:QI 2 "general_operand" "mri")))]
 276   ""
 277   "addb3 %2, %1, %0")
 278 \f
 279 ;; subtract instructions
 280
 281 (define_insn ""
 282   [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
 283         (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
 284                  (match_operand:DI 2 "general_operand" "oriF")))]
 285   ""
 286   "*
 287   {
 288   rtx label[1];
 289   rtx lsw_operands[3];
 290
 291   if (GET_CODE (operands[0]) == REG)
 292     lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
 293   else
 294     if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
 295       lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
 296     else
 297       abort();
 298
 299   if (GET_CODE (operands[2]) == REG)
 300     lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
 301   else
 302     if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
 303       lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
 304     else
 305       if (GET_CODE (operands[2]) == CONST_DOUBLE)
 306         {
 307         lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
 308         operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
 309         }
 310       else
 311         if (GET_CODE (operands[2]) == CONST_INT)
 312           {
 313           lsw_operands[2] = operands[2];
 314           operands[2] = const0_rtx;
 315           }
 316         else
 317           abort();
 318
 319   label[0] = gen_label_rtx();
 320   LABEL_NUSES(label[0]) = 1;
 321
 322   output_asm_insn(\"subw2 %2, %0\", operands);
 323   output_asm_insn(\"subw2 %2, %0\", lsw_operands);
 324   output_asm_insn(\"BCCB %l0\", label);
 325   output_asm_insn(\"DECW %0\", operands);
 326   output_asm_insn(\"%l0:\", label);
 327
 328   return \"\";
 329   }")
 330
 331 (define_insn "subdi3"
 332   [(set (match_operand:DI 0 "nonimmediate_operand" "=&or")
 333         (minus:DI (match_operand:DI 1 "general_operand" "oriF")
 334                  (match_operand:DI 2 "general_operand" "oriF")))]
 335   ""
 336   "*
 337   {
 338   rtx label[1];
 339   rtx lsw_operands[3];
 340
 341   if (GET_CODE (operands[0]) == REG)
 342     lsw_operands[0] = gen_rtx(REG, SImode, REGNO (operands[0]) + 1);
 343   else
 344     if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
 345       lsw_operands[0] = adj_offsettable_operand(operands[0], 4);
 346     else
 347       abort();
 348
 349   if (GET_CODE (operands[1]) == REG)
 350     lsw_operands[1] = gen_rtx(REG, SImode, REGNO (operands[1]) + 1);
 351   else
 352     if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
 353       lsw_operands[1] = adj_offsettable_operand(operands[1], 4);
 354     else
 355       if (GET_CODE (operands[1]) == CONST_DOUBLE)
 356         {
 357         lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH(operands[1]));
 358         operands[1] = GEN_INT (CONST_DOUBLE_LOW(operands[1]));
 359         }
 360       else
 361         if (GET_CODE (operands[1]) == CONST_INT)
 362           {
 363           lsw_operands[1] = operands[1];
 364           operands[1] = const0_rtx;
 365           }
 366         else
 367           abort();
 368
 369   if (GET_CODE (operands[2]) == REG)
 370     lsw_operands[2] = gen_rtx(REG, SImode, REGNO (operands[2]) + 1);
 371   else
 372     if (GET_CODE (operands[2]) == MEM && offsettable_memref_p (operands[2]))
 373       lsw_operands[2] = adj_offsettable_operand(operands[2], 4);
 374     else
 375       if (GET_CODE (operands[2]) == CONST_DOUBLE)
 376         {
 377         lsw_operands[2] = GEN_INT (CONST_DOUBLE_HIGH(operands[2]));
 378         operands[2] = GEN_INT (CONST_DOUBLE_LOW(operands[2]));
 379         }
 380       else
 381         if (GET_CODE (operands[2]) == CONST_INT)
 382           {
 383           lsw_operands[2] = operands[2];
 384           operands[2] = const0_rtx;
 385           }
 386         else
 387           abort();
 388
 389   label[0] = gen_label_rtx();
 390   LABEL_NUSES(label[0]) = 1;
 391
 392   output_asm_insn(\"subw3 %2, %1, %0\", operands);
 393   output_asm_insn(\"subw3 %2, %1, %0\", lsw_operands);
 394   output_asm_insn(\"BCCB %l0\", label);
 395   output_asm_insn(\"DECW %0\", operands);
 396   output_asm_insn(\"%l0:\", label);
 397
 398   return \"\";
 399   }")
 400
 401 (define_insn ""
 402   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 403         (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 404                   (match_operand:SI 2 "general_operand" "mri")))]
 405   ""
 406   "subw2 %2, %0")
 407
 408 (define_insn "subsi3"
 409   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 410         (minus:SI (match_operand:SI 1 "general_operand" "mri")
 411                   (match_operand:SI 2 "general_operand" "mri")))]
 412   ""
 413   "subw3 %2, %1, %0")
 414
 415 (define_insn ""
 416   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 417         (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0")
 418                   (match_operand:HI 2 "general_operand" "mri")))]
 419   ""
 420   "subh2 %2, %0")
 421
 422 (define_insn "subhi3"
 423   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 424         (minus:HI (match_operand:HI 1 "general_operand" "mri")
 425                   (match_operand:HI 2 "general_operand" "mri")))]
 426   ""
 427   "subh3 %2, %1, %0")
 428
 429 (define_insn ""
 430   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 431         (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0")
 432                   (match_operand:QI 2 "general_operand" "mri")))]
 433   ""
 434   "subb2 %2, %0")
 435
 436 (define_insn "subqi3"
 437   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 438         (minus:QI (match_operand:QI 1 "general_operand" "mri")
 439                   (match_operand:QI 2 "general_operand" "mri")))]
 440   ""
 441   "subb3 %2, %1, %0")
 442 \f
 443 ;; signed multiply instructions
 444
 445 (define_insn ""
 446   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 447         (mult:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 448                  (match_operand:SI 2 "general_operand" "mri")))]
 449   ""
 450   "mulw2 %2, %0")
 451
 452 (define_insn "mulsi3"
 453   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 454         (mult:SI (match_operand:SI 1 "general_operand" "mri")
 455                  (match_operand:SI 2 "general_operand" "mri")))]
 456   ""
 457   "mulw3 %2, %1, %0")
 458
 459 ;; signed divide instructions
 460
 461 (define_insn ""
 462   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 463         (div:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 464                 (match_operand:SI 2 "general_operand" "mri")))]
 465   ""
 466   "divw2 %2, %0")
 467
 468 (define_insn "divsi3"
 469   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 470         (div:SI (match_operand:SI 1 "general_operand" "mri")
 471                 (match_operand:SI 2 "general_operand" "mri")))]
 472   ""
 473   "divw3 %2, %1, %0")
 474
 475 ;; signed modulus instruction
 476
 477 (define_insn ""
 478   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 479         (mod:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 480                 (match_operand:SI 2 "general_operand" "mri")))]
 481   ""
 482   "modw2 %2, %0")
 483
 484 (define_insn "modsi3"
 485   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 486         (mod:SI (match_operand:SI 1 "general_operand" "mri")
 487                 (match_operand:SI 2 "general_operand" "mri")))]
 488   ""
 489   "modw3 %2, %1, %0")
 490 \f
 491 ;; unsigned divide instruction
 492
 493 (define_insn ""
 494   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 495         (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 496                  (match_operand:SI 2 "general_operand" "mri")))]
 497   ""
 498   "udivw2 %2, %0")
 499
 500 (define_insn "udivsi3"
 501   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 502         (udiv:SI (match_operand:SI 1 "general_operand" "mri")
 503                  (match_operand:SI 2 "general_operand" "mri")))]
 504   ""
 505   "udivw3 %2, %1, %0")
 506
 507 ;; unsigned modulus instruction
 508
 509 (define_insn ""
 510   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 511         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 512                  (match_operand:SI 2 "general_operand" "mri")))]
 513   ""
 514   "umodw2 %2, %0")
 515
 516 (define_insn "umodsi3"
 517   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 518         (umod:SI (match_operand:SI 1 "general_operand" "mri")
 519                  (match_operand:SI 2 "general_operand" "mri")))]
 520   ""
 521   "umodw3 %2, %1, %0")
 522 \f
 523 ;; logical-and instructions
 524
 525 (define_insn ""
 526   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 527         (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 528                 (match_operand:SI 2 "general_operand" "mri")))]
 529   ""
 530   "andw2 %2, %0")
 531
 532 (define_insn "andsi3"
 533   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 534         (and:SI (match_operand:SI 1 "general_operand" "mri")
 535                 (match_operand:SI 2 "general_operand" "mri")))]
 536   ""
 537   "andw3 %2, %1, %0")
 538
 539 (define_insn ""
 540   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 541         (and:HI (match_operand:HI 1 "nonimmediate_operand" "0")
 542                 (match_operand:HI 2 "general_operand" "mri")))]
 543   ""
 544   "andh2 %2, %0")
 545
 546 (define_insn "andhi3"
 547   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 548         (and:HI (match_operand:HI 1 "general_operand" "mri")
 549                 (match_operand:HI 2 "general_operand" "mri")))]
 550   ""
 551   "andh3 %2, %1, %0")
 552
 553 (define_insn ""
 554   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 555         (and:QI (match_operand:QI 1 "nonimmediate_operand" "0")
 556                 (match_operand:QI 2 "general_operand" "mri")))]
 557   ""
 558   "andb2 %2, %0")
 559
 560 (define_insn "andqi3"
 561   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 562         (and:QI (match_operand:QI 1 "general_operand" "mri")
 563                 (match_operand:QI 2 "general_operand" "mri")))]
 564   ""
 565   "andb3 %2, %1, %0")
 566 \f
 567 ;; inclusive-or instructions
 568
 569 (define_insn ""
 570   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 571         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 572                 (match_operand:SI 2 "general_operand" "mri")))]
 573   ""
 574   "orw2 %2, %0")
 575
 576 (define_insn "iorsi3"
 577   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 578         (ior:SI (match_operand:SI 1 "general_operand" "mri")
 579                 (match_operand:SI 2 "general_operand" "mri")))]
 580   ""
 581   "orw3 %2, %1, %0")
 582
 583 (define_insn ""
 584   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 585         (ior:HI (match_operand:HI 1 "nonimmediate_operand" "0")
 586                 (match_operand:HI 2 "general_operand" "mri")))]
 587   ""
 588   "orh2 %2, %0")
 589
 590 (define_insn "iorhi3"
 591   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 592         (ior:HI (match_operand:HI 1 "general_operand" "mri")
 593                 (match_operand:HI 2 "general_operand" "mri")))]
 594   ""
 595   "orh3 %2, %1, %0")
 596
 597 (define_insn ""
 598   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 599         (ior:QI (match_operand:QI 1 "nonimmediate_operand" "0")
 600                 (match_operand:QI 2 "general_operand" "mri")))]
 601   ""
 602   "orb2 %2, %0")
 603
 604 (define_insn "iorqi3"
 605   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 606         (ior:QI (match_operand:QI 1 "general_operand" "mri")
 607                 (match_operand:QI 2 "general_operand" "mri")))]
 608   ""
 609   "orb3 %2, %1, %0")
 610 \f
 611 ;; exclusive-or instructions
 612
 613 (define_insn ""
 614   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 615         (xor:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 616                 (match_operand:SI 2 "general_operand" "mri")))]
 617   ""
 618   "xorw2 %2, %0")
 619
 620 (define_insn "xorsi3"
 621   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 622         (xor:SI (match_operand:SI 1 "general_operand" "mri")
 623                 (match_operand:SI 2 "general_operand" "mri")))]
 624   ""
 625   "xorw3 %2, %1, %0")
 626
 627 (define_insn ""
 628   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 629         (xor:HI (match_operand:HI 1 "nonimmediate_operand" "0")
 630                 (match_operand:HI 2 "general_operand" "mri")))]
 631   ""
 632   "xorh2 %2, %0")
 633
 634 (define_insn "xorhi3"
 635   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 636         (xor:HI (match_operand:HI 1 "general_operand" "mri")
 637                 (match_operand:HI 2 "general_operand" "mri")))]
 638   ""
 639   "xorh3 %2, %1, %0")
 640
 641 (define_insn ""
 642   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 643         (xor:QI (match_operand:QI 1 "nonimmediate_operand" "0")
 644                 (match_operand:QI 2 "general_operand" "mri")))]
 645   ""
 646   "xorb2 %2, %0")
 647
 648 (define_insn "xorqi3"
 649   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 650         (xor:QI (match_operand:QI 1 "general_operand" "mri")
 651                 (match_operand:QI 2 "general_operand" "mri")))]
 652   ""
 653   "xorb3 %2, %1, %0")
 654 \f
 655 ;; arithmetic shift instructions
 656
 657 (define_insn "ashlsi3"
 658   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 659         (ashift:SI (match_operand:SI 1 "general_operand" "mri")
 660                    (match_operand:SI 2 "general_operand" "mri")))]
 661   ""
 662   "LLSW3 %2, %1, %0")
 663
 664 (define_insn "ashrsi3"
 665   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 666         (ashiftrt:SI (match_operand:SI 1 "general_operand" "mri")
 667                      (match_operand:SI 2 "general_operand" "mri")))]
 668   ""
 669   "ARSW3 %2, %1, %0")
 670
 671 ;; logical shift instructions
 672
 673 (define_insn "lshrsi3"
 674   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 675         (lshiftrt:SI (match_operand:SI 1 "general_operand" "mri")
 676                      (match_operand:SI 2 "general_operand" "mri")))]
 677   ""
 678   "LRSW3 %2, %1, %0")
 679
 680 ;; rotate instruction
 681
 682 (define_insn "rotrsi3"
 683   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 684         (rotatert: SI (match_operand:SI 1 "general_operand" "mri")
 685                       (match_operand:SI 2 "general_operand" "mri")))]
 686   ""
 687   "ROTW %2, %1, %0")
 688 \f
 689 ;; negate instructions
 690
 691 (define_insn "negsi2"
 692   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 693         (neg:SI (match_operand:SI 1 "general_operand" "mri")))]
 694   ""
 695   "mnegw %1, %0")
 696
 697 (define_insn "neghi2"
 698   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 699         (neg:HI (match_operand:HI 1 "general_operand" "mri")))]
 700   ""
 701   "mnegh %1, %0")
 702
 703 ;; complement instructions
 704
 705 (define_insn "one_cmplsi2"
 706   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 707         (not:SI (match_operand:SI 1 "general_operand" "mri")))]
 708   ""
 709   "mcomw %1, %0")
 710
 711 (define_insn "one_cmplhi2"
 712   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 713         (not:HI (match_operand:HI 1 "general_operand" "mri")))]
 714   ""
 715   "mcomh %1, %0")
 716
 717 (define_insn "one_cmplqi2"
 718   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 719         (not:QI (match_operand:QI 1 "general_operand" "mri")))]
 720   ""
 721   "mcomb %1, %0")
 722 \f
 723 ;; test instruction
 724
 725 ;; We don't want to allow a constant operand for test insns because
 726 ;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
 727 ;; be folded while optimizing anyway.
 728
 729 (define_insn "tstsi"
 730   [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "mr"))]
 731   ""
 732   "TSTW %0")
 733
 734 (define_insn "tsthi"
 735   [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "mr"))]
 736   ""
 737   "TSTH %0")
 738
 739 (define_insn "tstqi"
 740   [(set (cc0) (match_operand:QI 0 "nonimmediate_operand" "mr"))]
 741   ""
 742   "TSTB {sbyte}%0")
 743
 744 ;; compare instruction
 745
 746 (define_insn "cmpsi"
 747   [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "mr")
 748                        (match_operand:SI 1 "general_operand" "mri")))]
 749   ""
 750   "CMPW %1, %0")
 751
 752 (define_insn "cmphi"
 753   [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_operand" "mr")
 754                        (match_operand:HI 1 "general_operand" "mri")))]
 755   ""
 756   "*
 757   {
 758
 759   if (GET_CODE (operands[1]) == CONST_INT &&
 760     ((unsigned long)INTVAL (operands[1]) & 0x8000L))
 761     operands[1] = GEN_INT (INTVAL(operands[1]) | 0xffff0000L);
 762
 763   output_asm_insn(\"CMPH %1, %0\",operands);
 764
 765   return \"\";
 766   }")
 767
 768 (define_insn "cmpqi"
 769   [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_operand" "mr")
 770                        (match_operand:QI 1 "general_operand" "mri")))]
 771   ""
 772   "*
 773   {
 774
 775   if (GET_CODE (operands[1]) == CONST_INT &&
 776     ((unsigned long)INTVAL (operands[1]) & 0x80L))
 777     operands[1] = GEN_INT (INTVAL(operands[1]) | 0xffffff00L);
 778
 779   output_asm_insn(\"CMPB {sbyte}%1, {sbyte}%0\",operands);
 780
 781   return \"\";
 782   }")
 783 \f
 784 ;; truncate instructions
 785
 786 (define_insn ""
 787   [(set (match_operand:SF 0 "register_operand" "=r")
 788         (float_truncate:SF (match_operand:DF 1 "general_operand" "orF")))
 789    (clobber (reg:SI 1))
 790    (clobber (reg:SI 2))]
 791   "REGNO (operands[0]) == 0"
 792   "*
 793   {
 794   output_push_double(&operands[1]);
 795   output_asm_insn(\"call &2, _fdtos\", operands);
 796
 797   return \"\";
 798   }")
 799
 800 (define_expand "truncdfsf2"
 801   [(parallel [(set (reg:SF 0)
 802                (float_truncate:SF (match_operand:DF 1 "general_operand" "orF")))
 803               (clobber (reg:SI 1))
 804               (clobber (reg:SI 2))])
 805    (set (match_operand:SF 0 "nonimmediate_operand" "=mr")
 806         (reg:SF 0))]
 807   ""
 808   "")
 809
 810 (define_insn "truncsihi2"
 811   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 812         (truncate:HI (match_operand:SI 1 "general_operand" "mri")))]
 813   ""
 814   "movtwh %1, %0")
 815
 816 (define_insn "truncsiqi2"
 817   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 818         (truncate:QI (match_operand:SI 1 "general_operand" "mri")))]
 819   ""
 820   "movtwb %1, %0")
 821
 822 (define_insn "trunchiqi2"
 823   [(set (match_operand:QI 0 "nonimmediate_operand" "=mr")
 824         (truncate:QI (match_operand:HI 1 "general_operand" "mri")))]
 825   ""
 826   "movthb %1, %0")
 827 \f
 828 ;; sign-extend move instructions
 829
 830 (define_insn ""
 831   [(set (match_operand:DF 0 "register_operand" "=r")
 832         (float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))
 833    (clobber (reg:SI 2))]
 834   "REGNO (operands[0]) == 0"
 835   "*
 836   {
 837   output_asm_insn(\"pushw %1\", operands);
 838   output_asm_insn(\"call &1, _fstod\", operands);
 839
 840   return \"\";
 841   }")
 842
 843 (define_expand "extendsfdf2"
 844   [(parallel [(set (reg:DF 0)
 845                (float_extend:DF (match_operand:SF 1 "general_operand" "mrF")))
 846               (clobber (reg:SI 2))])
 847    (set (match_operand:DF 0 "nonimmediate_operand" "=or")
 848         (reg:DF 0))]
 849   ""
 850   "")
 851
 852 (define_insn "extendhisi2"
 853   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 854         (sign_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
 855   ""
 856   "movbhw %1, %0")
 857
 858 (define_insn "extendqisi2"
 859   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 860         (sign_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
 861   ""
 862   "movbbw %1, %0")
 863
 864 (define_insn "extendqihi2"
 865   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 866         (sign_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
 867   ""
 868   "movbbh %1, %0")
 869
 870 ;; zero-extend move instructions
 871
 872 (define_insn "zero_extendhisi2"
 873   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 874         (zero_extend:SI (match_operand:HI 1 "general_operand" "mri")))]
 875   ""
 876   "movzhw %1, %0")
 877
 878 (define_insn "zero_extendqisi2"
 879   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 880         (zero_extend:SI (match_operand:QI 1 "general_operand" "mri")))]
 881   ""
 882   "movzbw %1, %0")
 883
 884 (define_insn "zero_extendqihi2"
 885   [(set (match_operand:HI 0 "nonimmediate_operand" "=mr")
 886         (zero_extend:HI (match_operand:QI 1 "general_operand" "mri")))]
 887   ""
 888   "movzbh %1, %0")
 889 \f
 890 ;; bit field instructions
 891
 892 (define_insn "extzv"
 893   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 894         (zero_extract:SI (match_operand:SI 1 "general_operand" "mri")
 895                          (match_operand:SI 2 "immediate_operand" "i")
 896                          (match_operand:SI 3 "general_operand" "mri")))]
 897   ""
 898   "*
 899   {
 900
 901   operands[2] = GEN_INT (INTVAL(operands[2]) - 1);
 902   output_asm_insn(\"EXTFW %2, %3, %1, %0\",operands);
 903
 904   return \"\";
 905   }")
 906
 907 (define_insn ""
 908   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 909         (zero_extract:SI (match_operand:HI 1 "general_operand" "mri")
 910                          (match_operand:SI 2 "immediate_operand" "i")
 911                          (match_operand:SI 3 "general_operand" "mri")))]
 912   ""
 913   "*
 914   {
 915
 916   operands[2] = GEN_INT (INTVAL(operands[2]) - 1);
 917   output_asm_insn(\"EXTFH %2, %3, {uhalf}%1, {uword}%0\",operands);
 918
 919   return \"\";
 920   }")
 921
 922 (define_insn ""
 923   [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
 924         (zero_extract:SI (match_operand:QI 1 "general_operand" "mri")
 925                          (match_operand:SI 2 "immediate_operand" "i")
 926                          (match_operand:SI 3 "general_operand" "mri")))]
 927   ""
 928   "*
 929   {
 930
 931   operands[2] = GEN_INT (INTVAL(operands[2]) - 1);
 932   output_asm_insn(\"EXTFB %2, %3, {ubyte}%1, {uword}%0\",operands);
 933
 934   return \"\";
 935   }")
 936
 937 (define_insn "insv"
 938   [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+mr")
 939                          (match_operand:SI 1 "immediate_operand" "i")
 940                          (match_operand:SI 2 "general_operand" "mri"))
 941         (match_operand:SI 3 "general_operand" "mri"))]
 942   ""
 943   "*
 944   {
 945
 946   operands[1] = GEN_INT (INTVAL(operands[1]) - 1);
 947   output_asm_insn(\"INSFW %1, %2, %3, %0\",operands);
 948
 949   return \"\";
 950   }")
 951
 952 (define_insn ""
 953   [(set (zero_extract:SI (match_operand:HI 0 "nonimmediate_operand" "+mr")
 954                          (match_operand:SI 1 "immediate_operand" "i")
 955                          (match_operand:SI 2 "general_operand" "mri"))
 956         (match_operand:SI 3 "general_operand" "mri"))]
 957   ""
 958   "*
 959   {
 960
 961   operands[1] = GEN_INT (INTVAL(operands[1]) - 1);
 962   output_asm_insn(\"INSFH %1, %2, {uword}%3, {uhalf}%0\",operands);
 963
 964   return \"\";
 965   }")
 966
 967 (define_insn ""
 968   [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+mr")
 969                          (match_operand:SI 1 "immediate_operand" "i")
 970                          (match_operand:SI 2 "general_operand" "mri"))
 971         (match_operand:SI 3 "general_operand" "mri"))]
 972   ""
 973   "*
 974   {
 975
 976   operands[1] = GEN_INT (INTVAL(operands[1]) - 1);
 977   output_asm_insn(\"INSFB %1, %2, {uword}%3, {ubyte}%0\",operands);
 978
 979   return \"\";
 980   }")
 981 \f
 982 ;; conditional branch instructions
 983
 984 (define_insn "beq"
 985   [(set (pc) (if_then_else (eq (cc0) (const_int 0))
 986                            (label_ref (match_operand 0 "" ""))
 987                            (pc)))]
 988   ""
 989   "je %l0")
 990
 991 (define_insn "bne"
 992   [(set (pc) (if_then_else (ne (cc0) (const_int 0))
 993                            (label_ref (match_operand 0 "" ""))
 994                            (pc)))]
 995   ""
 996   "jne %l0")
 997
 998 (define_insn "bgt"
 999   [(set (pc) (if_then_else (gt (cc0) (const_int 0))
1000                            (label_ref (match_operand 0 "" ""))
1001                            (pc)))]
1002   ""
1003   "jg %l0")
1004
1005 (define_insn "bgtu"
1006   [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
1007                            (label_ref (match_operand 0 "" ""))
1008                            (pc)))]
1009   ""
1010   "jgu %l0")
1011
1012 (define_insn "blt"
1013   [(set (pc) (if_then_else (lt (cc0) (const_int 0))
1014                            (label_ref (match_operand 0 "" ""))
1015                            (pc)))]
1016   ""
1017   "jl %l0")
1018
1019 (define_insn "bltu"
1020   [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
1021                            (label_ref (match_operand 0 "" ""))
1022                            (pc)))]
1023   ""
1024   "jlu %l0")
1025
1026 (define_insn "bge"
1027   [(set (pc) (if_then_else (ge (cc0) (const_int 0))
1028                            (label_ref (match_operand 0 "" ""))
1029                            (pc)))]
1030   ""
1031   "jge %l0")
1032
1033 (define_insn "bgeu"
1034   [(set (pc) (if_then_else (geu (cc0) (const_int 0))
1035                            (label_ref (match_operand 0 "" ""))
1036                            (pc)))]
1037   ""
1038   "jgeu %l0")
1039
1040 (define_insn "ble"
1041   [(set (pc) (if_then_else (le (cc0) (const_int 0))
1042                            (label_ref (match_operand 0 "" ""))
1043                            (pc)))]
1044   ""
1045   "jle %l0")
1046
1047 (define_insn "bleu"
1048   [(set (pc) (if_then_else (leu (cc0) (const_int 0))
1049                            (label_ref (match_operand 0 "" ""))
1050                            (pc)))]
1051   ""
1052   "jleu %l0")
1053 \f
1054 ;; reverse-conditional branch instructions
1055
1056 (define_insn ""
1057   [(set (pc) (if_then_else (eq (cc0) (const_int 0))
1058                            (pc)
1059                            (label_ref (match_operand 0 "" ""))))]
1060   ""
1061   "jne %l0")
1062
1063 (define_insn ""
1064   [(set (pc) (if_then_else (ne (cc0) (const_int 0))
1065                            (pc)
1066                            (label_ref (match_operand 0 "" ""))))]
1067   ""
1068   "je %l0")
1069
1070 (define_insn ""
1071   [(set (pc) (if_then_else (gt (cc0) (const_int 0))
1072                            (pc)
1073                            (label_ref (match_operand 0 "" ""))))]
1074   ""
1075   "jle %l0")
1076
1077 (define_insn ""
1078   [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
1079                            (pc)
1080                            (label_ref (match_operand 0 "" ""))))]
1081   ""
1082   "jleu %l0")
1083
1084 (define_insn ""
1085   [(set (pc) (if_then_else (lt (cc0) (const_int 0))
1086                            (pc)
1087                            (label_ref (match_operand 0 "" ""))))]
1088   ""
1089   "jge %l0")
1090
1091 (define_insn ""
1092   [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
1093                            (pc)
1094                            (label_ref (match_operand 0 "" ""))))]
1095   ""
1096   "jgeu %l0")
1097
1098 (define_insn ""
1099   [(set (pc) (if_then_else (ge (cc0) (const_int 0))
1100                            (pc)
1101                            (label_ref (match_operand 0 "" ""))))]
1102   ""
1103   "jl %l0")
1104
1105 (define_insn ""
1106   [(set (pc) (if_then_else (geu (cc0) (const_int 0))
1107                            (pc)
1108                            (label_ref (match_operand 0 "" ""))))]
1109   ""
1110   "jlu %l0")
1111
1112 (define_insn ""
1113   [(set (pc) (if_then_else (le (cc0) (const_int 0))
1114                            (pc)
1115                            (label_ref (match_operand 0 "" ""))))]
1116   ""
1117   "jg %l0")
1118
1119 (define_insn ""
1120   [(set (pc) (if_then_else (leu (cc0) (const_int 0))
1121                            (pc)
1122                            (label_ref (match_operand 0 "" ""))))]
1123   ""
1124   "jgu %l0")
1125 \f
1126 ;; call instructions
1127
1128 (define_insn "call"
1129   [(call (match_operand:QI 0 "memory_operand" "m")
1130          (match_operand:SI 1 "immediate_operand" "i"))]
1131   ""
1132   "call %1/4, %0")
1133
1134 (define_insn "call_value"
1135   [(set (match_operand 0 "register_operand" "=r")
1136         (call (match_operand:QI 1 "memory_operand" "m")
1137               (match_operand:SI 2 "immediate_operand" "i")))]
1138   ""
1139   "call %2/4, %1")
1140
1141 ;; No-op instruction
1142
1143 (define_insn "nop"
1144   [(const_int 0)]
1145   ""
1146   "NOP")
1147
1148 ;; jump through a dispatch table instruction
1149
1150 (define_expand "casesi"
1151   [(use (match_operand:SI 0 "general_operand" "mri"))
1152    (set (cc0) (compare (match_dup 5)
1153                        (match_operand:SI 1 "general_operand" "mri")))
1154    (set (pc) (if_then_else (lt (cc0) (const_int 0))
1155                            (label_ref (match_operand 4 "" ""))
1156                            (pc)))
1157    (set (match_dup 5) (minus:SI (match_dup 5)
1158                                 (match_dup 1)))
1159    (set (cc0) (compare (match_dup 5)
1160                        (match_operand:SI 2 "general_operand" "mri")))
1161    (set (pc) (if_then_else (gtu (cc0) (const_int 0))
1162                            (label_ref (match_dup 4))
1163                            (pc)))
1164    (set (match_dup 5) (ashift:SI (match_dup 5)
1165                                  (const_int 2)))
1166    (set (pc) (mem:SI (plus:SI (label_ref (match_operand 3 "" ""))
1167                               (match_dup 5))))]
1168   ""
1169   "
1170   {
1171   operands[5] = gen_reg_rtx(GET_MODE (operands[0]));
1172   emit_move_insn(operands[5], operands[0]);
1173   }")
1174
1175 ;; jump instructions
1176
1177 (define_insn "indirect_jump"
1178   [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
1179   ""
1180   "jmp %a0")
1181
1182 (define_insn "jump"
1183   [(set (pc) (label_ref (match_operand 0 "" "")))]
1184   ""
1185   "jmp %l0")