1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
33 #include "insn-attr.h"
34 #include "insn-codes.h"
43 #include "diagnostic-core.h"
49 #include "target-def.h"
50 #include "langhooks.h"
55 /* Enumeration for all of the relational tests, so that we can build
56 arrays indexed by the test type, and not worry about the order
74 /* Array giving truth value on whether or not a given hard register
75 can support a given mode. */
76 char xtensa_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
78 /* Current frame size calculated by compute_frame_size. */
79 unsigned xtensa_current_frame_size
;
81 /* Largest block move to handle in-line. */
82 #define LARGEST_MOVE_RATIO 15
84 /* Define the structure for the machine field in struct function. */
85 struct GTY(()) machine_function
87 int accesses_prev_frame
;
91 rtx set_frame_ptr_insn
;
94 /* Vector, indexed by hard register number, which contains 1 for a
95 register that is allowable in a candidate for leaf function
98 const char xtensa_leaf_regs
[FIRST_PSEUDO_REGISTER
] =
100 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
102 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
106 /* Map hard register number to register class */
107 const enum reg_class xtensa_regno_to_class
[FIRST_PSEUDO_REGISTER
] =
109 RL_REGS
, SP_REG
, RL_REGS
, RL_REGS
,
110 RL_REGS
, RL_REGS
, RL_REGS
, GR_REGS
,
111 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
112 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
113 AR_REGS
, AR_REGS
, BR_REGS
,
114 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
115 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
116 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
117 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
121 static void xtensa_option_override (void);
122 static void xtensa_option_optimization (int, int);
123 static enum internal_test
map_test_to_internal_test (enum rtx_code
);
124 static rtx
gen_int_relational (enum rtx_code
, rtx
, rtx
, int *);
125 static rtx
gen_float_relational (enum rtx_code
, rtx
, rtx
);
126 static rtx
gen_conditional_move (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
127 static rtx
fixup_subreg_mem (rtx
);
128 static struct machine_function
* xtensa_init_machine_status (void);
129 static rtx
xtensa_legitimize_tls_address (rtx
);
130 static rtx
xtensa_legitimize_address (rtx
, rtx
, enum machine_mode
);
131 static bool xtensa_return_in_msb (const_tree
);
132 static void printx (FILE *, signed int);
133 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT
);
134 static rtx
xtensa_builtin_saveregs (void);
135 static bool xtensa_legitimate_address_p (enum machine_mode
, rtx
, bool);
136 static unsigned int xtensa_multibss_section_type_flags (tree
, const char *,
137 int) ATTRIBUTE_UNUSED
;
138 static section
*xtensa_select_rtx_section (enum machine_mode
, rtx
,
139 unsigned HOST_WIDE_INT
);
140 static bool xtensa_rtx_costs (rtx
, int, int, int *, bool);
141 static tree
xtensa_build_builtin_va_list (void);
142 static bool xtensa_return_in_memory (const_tree
, const_tree
);
143 static tree
xtensa_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*,
145 static void xtensa_function_arg_advance (CUMULATIVE_ARGS
*, enum machine_mode
,
147 static rtx
xtensa_function_arg (CUMULATIVE_ARGS
*, enum machine_mode
,
149 static rtx
xtensa_function_incoming_arg (CUMULATIVE_ARGS
*,
150 enum machine_mode
, const_tree
, bool);
151 static rtx
xtensa_function_value (const_tree
, const_tree
, bool);
152 static void xtensa_init_builtins (void);
153 static tree
xtensa_fold_builtin (tree
, int, tree
*, bool);
154 static rtx
xtensa_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
155 static void xtensa_va_start (tree
, rtx
);
156 static bool xtensa_frame_pointer_required (void);
157 static rtx
xtensa_static_chain (const_tree
, bool);
158 static void xtensa_asm_trampoline_template (FILE *);
159 static void xtensa_trampoline_init (rtx
, tree
, rtx
);
161 static const int reg_nonleaf_alloc_order
[FIRST_PSEUDO_REGISTER
] =
165 /* This macro generates the assembly code for function exit,
166 on machines that need it. If FUNCTION_EPILOGUE is not defined
167 then individual return instructions are generated for each
168 return statement. Args are same as for FUNCTION_PROLOGUE. */
170 #undef TARGET_ASM_FUNCTION_EPILOGUE
171 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
173 /* These hooks specify assembly directives for creating certain kinds
174 of integer object. */
176 #undef TARGET_ASM_ALIGNED_SI_OP
177 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
179 #undef TARGET_ASM_SELECT_RTX_SECTION
180 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
182 #undef TARGET_DEFAULT_TARGET_FLAGS
183 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
185 #undef TARGET_LEGITIMIZE_ADDRESS
186 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
188 #undef TARGET_RTX_COSTS
189 #define TARGET_RTX_COSTS xtensa_rtx_costs
190 #undef TARGET_ADDRESS_COST
191 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
193 #undef TARGET_BUILD_BUILTIN_VA_LIST
194 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
196 #undef TARGET_EXPAND_BUILTIN_VA_START
197 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
199 #undef TARGET_PROMOTE_FUNCTION_MODE
200 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
201 #undef TARGET_PROMOTE_PROTOTYPES
202 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
204 #undef TARGET_RETURN_IN_MEMORY
205 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
206 #undef TARGET_FUNCTION_VALUE
207 #define TARGET_FUNCTION_VALUE xtensa_function_value
208 #undef TARGET_SPLIT_COMPLEX_ARG
209 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
210 #undef TARGET_MUST_PASS_IN_STACK
211 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
212 #undef TARGET_FUNCTION_ARG_ADVANCE
213 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance
214 #undef TARGET_FUNCTION_ARG
215 #define TARGET_FUNCTION_ARG xtensa_function_arg
216 #undef TARGET_FUNCTION_INCOMING_ARG
217 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg
219 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
220 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
221 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
222 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
224 #undef TARGET_RETURN_IN_MSB
225 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
227 #undef TARGET_INIT_BUILTINS
228 #define TARGET_INIT_BUILTINS xtensa_init_builtins
229 #undef TARGET_FOLD_BUILTIN
230 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
231 #undef TARGET_EXPAND_BUILTIN
232 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
234 #undef TARGET_SECONDARY_RELOAD
235 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
237 #undef TARGET_HAVE_TLS
238 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
240 #undef TARGET_CANNOT_FORCE_CONST_MEM
241 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_tls_referenced_p
243 #undef TARGET_LEGITIMATE_ADDRESS_P
244 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
246 #undef TARGET_FRAME_POINTER_REQUIRED
247 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
249 #undef TARGET_STATIC_CHAIN
250 #define TARGET_STATIC_CHAIN xtensa_static_chain
251 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
252 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template
253 #undef TARGET_TRAMPOLINE_INIT
254 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init
256 #undef TARGET_OPTION_OVERRIDE
257 #define TARGET_OPTION_OVERRIDE xtensa_option_override
258 #undef TARGET_OPTION_OPTIMIZATION
259 #define TARGET_OPTION_OPTIMIZATION xtensa_option_optimization
261 struct gcc_target targetm
= TARGET_INITIALIZER
;
264 /* Functions to test Xtensa immediate operand validity. */
267 xtensa_simm8 (HOST_WIDE_INT v
)
269 return v
>= -128 && v
<= 127;
274 xtensa_simm8x256 (HOST_WIDE_INT v
)
276 return (v
& 255) == 0 && (v
>= -32768 && v
<= 32512);
281 xtensa_simm12b (HOST_WIDE_INT v
)
283 return v
>= -2048 && v
<= 2047;
288 xtensa_uimm8 (HOST_WIDE_INT v
)
290 return v
>= 0 && v
<= 255;
295 xtensa_uimm8x2 (HOST_WIDE_INT v
)
297 return (v
& 1) == 0 && (v
>= 0 && v
<= 510);
302 xtensa_uimm8x4 (HOST_WIDE_INT v
)
304 return (v
& 3) == 0 && (v
>= 0 && v
<= 1020);
309 xtensa_b4const (HOST_WIDE_INT v
)
336 xtensa_b4const_or_zero (HOST_WIDE_INT v
)
340 return xtensa_b4const (v
);
345 xtensa_b4constu (HOST_WIDE_INT v
)
372 xtensa_mask_immediate (HOST_WIDE_INT v
)
374 #define MAX_MASK_SIZE 16
377 for (mask_size
= 1; mask_size
<= MAX_MASK_SIZE
; mask_size
++)
390 /* This is just like the standard true_regnum() function except that it
391 works even when reg_renumber is not initialized. */
394 xt_true_regnum (rtx x
)
396 if (GET_CODE (x
) == REG
)
399 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
400 && reg_renumber
[REGNO (x
)] >= 0)
401 return reg_renumber
[REGNO (x
)];
404 if (GET_CODE (x
) == SUBREG
)
406 int base
= xt_true_regnum (SUBREG_REG (x
));
407 if (base
>= 0 && base
< FIRST_PSEUDO_REGISTER
)
408 return base
+ subreg_regno_offset (REGNO (SUBREG_REG (x
)),
409 GET_MODE (SUBREG_REG (x
)),
410 SUBREG_BYTE (x
), GET_MODE (x
));
417 xtensa_valid_move (enum machine_mode mode
, rtx
*operands
)
419 /* Either the destination or source must be a register, and the
420 MAC16 accumulator doesn't count. */
422 if (register_operand (operands
[0], mode
))
424 int dst_regnum
= xt_true_regnum (operands
[0]);
426 /* The stack pointer can only be assigned with a MOVSP opcode. */
427 if (dst_regnum
== STACK_POINTER_REGNUM
)
428 return (mode
== SImode
429 && register_operand (operands
[1], mode
)
430 && !ACC_REG_P (xt_true_regnum (operands
[1])));
432 if (!ACC_REG_P (dst_regnum
))
435 if (register_operand (operands
[1], mode
))
437 int src_regnum
= xt_true_regnum (operands
[1]);
438 if (!ACC_REG_P (src_regnum
))
446 smalloffset_mem_p (rtx op
)
448 if (GET_CODE (op
) == MEM
)
450 rtx addr
= XEXP (op
, 0);
451 if (GET_CODE (addr
) == REG
)
452 return BASE_REG_P (addr
, 0);
453 if (GET_CODE (addr
) == PLUS
)
455 rtx offset
= XEXP (addr
, 0);
457 if (GET_CODE (offset
) != CONST_INT
)
458 offset
= XEXP (addr
, 1);
459 if (GET_CODE (offset
) != CONST_INT
)
462 val
= INTVAL (offset
);
463 return (val
& 3) == 0 && (val
>= 0 && val
<= 60);
471 constantpool_address_p (rtx addr
)
475 if (GET_CODE (addr
) == CONST
)
479 /* Only handle (PLUS (SYM, OFFSET)) form. */
480 addr
= XEXP (addr
, 0);
481 if (GET_CODE (addr
) != PLUS
)
484 /* Make sure the address is word aligned. */
485 offset
= XEXP (addr
, 1);
486 if ((GET_CODE (offset
) != CONST_INT
)
487 || ((INTVAL (offset
) & 3) != 0))
490 sym
= XEXP (addr
, 0);
493 if ((GET_CODE (sym
) == SYMBOL_REF
)
494 && CONSTANT_POOL_ADDRESS_P (sym
))
501 constantpool_mem_p (rtx op
)
503 if (GET_CODE (op
) == SUBREG
)
504 op
= SUBREG_REG (op
);
505 if (GET_CODE (op
) == MEM
)
506 return constantpool_address_p (XEXP (op
, 0));
511 /* Return TRUE if X is a thread-local symbol. */
514 xtensa_tls_symbol_p (rtx x
)
516 if (! TARGET_HAVE_TLS
)
519 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
524 xtensa_extend_reg (rtx dst
, rtx src
)
526 rtx temp
= gen_reg_rtx (SImode
);
527 rtx shift
= GEN_INT (BITS_PER_WORD
- GET_MODE_BITSIZE (GET_MODE (src
)));
529 /* Generate paradoxical subregs as needed so that the modes match. */
530 src
= simplify_gen_subreg (SImode
, src
, GET_MODE (src
), 0);
531 dst
= simplify_gen_subreg (SImode
, dst
, GET_MODE (dst
), 0);
533 emit_insn (gen_ashlsi3 (temp
, src
, shift
));
534 emit_insn (gen_ashrsi3 (dst
, temp
, shift
));
539 xtensa_mem_offset (unsigned v
, enum machine_mode mode
)
544 /* Handle the worst case for block moves. See xtensa_expand_block_move
545 where we emit an optimized block move operation if the block can be
546 moved in < "move_ratio" pieces. The worst case is when the block is
547 aligned but has a size of (3 mod 4) (does this happen?) so that the
548 last piece requires a byte load/store. */
549 return (xtensa_uimm8 (v
)
550 && xtensa_uimm8 (v
+ MOVE_MAX
* LARGEST_MOVE_RATIO
));
553 return xtensa_uimm8 (v
);
556 return xtensa_uimm8x2 (v
);
559 return (xtensa_uimm8x4 (v
) && xtensa_uimm8x4 (v
+ 4));
565 return xtensa_uimm8x4 (v
);
569 /* Make normal rtx_code into something we can index from an array. */
571 static enum internal_test
572 map_test_to_internal_test (enum rtx_code test_code
)
574 enum internal_test test
= ITEST_MAX
;
579 case EQ
: test
= ITEST_EQ
; break;
580 case NE
: test
= ITEST_NE
; break;
581 case GT
: test
= ITEST_GT
; break;
582 case GE
: test
= ITEST_GE
; break;
583 case LT
: test
= ITEST_LT
; break;
584 case LE
: test
= ITEST_LE
; break;
585 case GTU
: test
= ITEST_GTU
; break;
586 case GEU
: test
= ITEST_GEU
; break;
587 case LTU
: test
= ITEST_LTU
; break;
588 case LEU
: test
= ITEST_LEU
; break;
595 /* Generate the code to compare two integer values. The return value is
596 the comparison expression. */
599 gen_int_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
600 rtx cmp0
, /* first operand to compare */
601 rtx cmp1
, /* second operand to compare */
602 int *p_invert
/* whether branch needs to reverse test */)
606 enum rtx_code test_code
; /* test code to use in insn */
607 bool (*const_range_p
) (HOST_WIDE_INT
); /* range check function */
608 int const_add
; /* constant to add (convert LE -> LT) */
609 int reverse_regs
; /* reverse registers in test */
610 int invert_const
; /* != 0 if invert value if cmp1 is constant */
611 int invert_reg
; /* != 0 if invert value if cmp1 is register */
612 int unsignedp
; /* != 0 for unsigned comparisons. */
615 static struct cmp_info info
[ (int)ITEST_MAX
] = {
617 { EQ
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* EQ */
618 { NE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* NE */
620 { LT
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* GT */
621 { GE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* GE */
622 { LT
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* LT */
623 { GE
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* LE */
625 { LTU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* GTU */
626 { GEU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* GEU */
627 { LTU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* LTU */
628 { GEU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* LEU */
631 enum internal_test test
;
632 enum machine_mode mode
;
633 struct cmp_info
*p_info
;
635 test
= map_test_to_internal_test (test_code
);
636 gcc_assert (test
!= ITEST_MAX
);
638 p_info
= &info
[ (int)test
];
640 mode
= GET_MODE (cmp0
);
641 if (mode
== VOIDmode
)
642 mode
= GET_MODE (cmp1
);
644 /* Make sure we can handle any constants given to us. */
645 if (GET_CODE (cmp1
) == CONST_INT
)
647 HOST_WIDE_INT value
= INTVAL (cmp1
);
648 unsigned HOST_WIDE_INT uvalue
= (unsigned HOST_WIDE_INT
)value
;
650 /* if the immediate overflows or does not fit in the immediate field,
651 spill it to a register */
653 if ((p_info
->unsignedp
?
654 (uvalue
+ p_info
->const_add
> uvalue
) :
655 (value
+ p_info
->const_add
> value
)) != (p_info
->const_add
> 0))
657 cmp1
= force_reg (mode
, cmp1
);
659 else if (!(p_info
->const_range_p
) (value
+ p_info
->const_add
))
661 cmp1
= force_reg (mode
, cmp1
);
664 else if ((GET_CODE (cmp1
) != REG
) && (GET_CODE (cmp1
) != SUBREG
))
666 cmp1
= force_reg (mode
, cmp1
);
669 /* See if we need to invert the result. */
670 *p_invert
= ((GET_CODE (cmp1
) == CONST_INT
)
671 ? p_info
->invert_const
672 : p_info
->invert_reg
);
674 /* Comparison to constants, may involve adding 1 to change a LT into LE.
675 Comparison between two registers, may involve switching operands. */
676 if (GET_CODE (cmp1
) == CONST_INT
)
678 if (p_info
->const_add
!= 0)
679 cmp1
= GEN_INT (INTVAL (cmp1
) + p_info
->const_add
);
682 else if (p_info
->reverse_regs
)
689 return gen_rtx_fmt_ee (p_info
->test_code
, VOIDmode
, cmp0
, cmp1
);
693 /* Generate the code to compare two float values. The return value is
694 the comparison expression. */
697 gen_float_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
698 rtx cmp0
, /* first operand to compare */
699 rtx cmp1
/* second operand to compare */)
701 rtx (*gen_fn
) (rtx
, rtx
, rtx
);
703 int reverse_regs
, invert
;
707 case EQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_seq_sf
; break;
708 case NE
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_seq_sf
; break;
709 case LE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sle_sf
; break;
710 case GT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_slt_sf
; break;
711 case LT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_slt_sf
; break;
712 case GE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sle_sf
; break;
713 case UNEQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_suneq_sf
; break;
714 case LTGT
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_suneq_sf
; break;
715 case UNLE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunle_sf
; break;
716 case UNGT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
717 case UNLT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
718 case UNGE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunle_sf
; break;
720 reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunordered_sf
; break;
722 reverse_regs
= 0; invert
= 1; gen_fn
= gen_sunordered_sf
; break;
724 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
725 reverse_regs
= 0; invert
= 0; gen_fn
= 0; /* avoid compiler warnings */
735 brtmp
= gen_rtx_REG (CCmode
, FPCC_REGNUM
);
736 emit_insn (gen_fn (brtmp
, cmp0
, cmp1
));
738 return gen_rtx_fmt_ee (invert
? EQ
: NE
, VOIDmode
, brtmp
, const0_rtx
);
743 xtensa_expand_conditional_branch (rtx
*operands
, enum machine_mode mode
)
745 enum rtx_code test_code
= GET_CODE (operands
[0]);
746 rtx cmp0
= operands
[1];
747 rtx cmp1
= operands
[2];
756 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
760 cmp
= gen_int_relational (test_code
, cmp0
, cmp1
, &invert
);
764 if (!TARGET_HARD_FLOAT
)
765 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
,
768 cmp
= gen_float_relational (test_code
, cmp0
, cmp1
);
772 /* Generate the branch. */
774 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
783 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
784 gen_rtx_IF_THEN_ELSE (VOIDmode
, cmp
,
791 gen_conditional_move (enum rtx_code code
, enum machine_mode mode
,
798 /* Jump optimization calls get_condition() which canonicalizes
799 comparisons like (GE x <const>) to (GT x <const-1>).
800 Transform those comparisons back to GE, since that is the
801 comparison supported in Xtensa. We shouldn't have to
802 transform <LE x const> comparisons, because neither
803 xtensa_expand_conditional_branch() nor get_condition() will
806 if ((code
== GT
) && (op1
== constm1_rtx
))
811 cmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
813 if (boolean_operator (cmp
, VOIDmode
))
815 /* Swap the operands to make const0 second. */
816 if (op0
== const0_rtx
)
822 /* If not comparing against zero, emit a comparison (subtract). */
823 if (op1
!= const0_rtx
)
825 op0
= expand_binop (SImode
, sub_optab
, op0
, op1
,
826 0, 0, OPTAB_LIB_WIDEN
);
830 else if (branch_operator (cmp
, VOIDmode
))
832 /* Swap the operands to make const0 second. */
833 if (op0
== const0_rtx
)
840 case LT
: code
= GE
; break;
841 case GE
: code
= LT
; break;
842 default: gcc_unreachable ();
846 if (op1
!= const0_rtx
)
852 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
855 if (TARGET_HARD_FLOAT
&& mode
== SFmode
)
856 return gen_float_relational (code
, op0
, op1
);
863 xtensa_expand_conditional_move (rtx
*operands
, int isflt
)
865 rtx dest
= operands
[0];
866 rtx cmp
= operands
[1];
867 enum machine_mode cmp_mode
= GET_MODE (XEXP (cmp
, 0));
868 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
870 if (!(cmp
= gen_conditional_move (GET_CODE (cmp
), cmp_mode
,
871 XEXP (cmp
, 0), XEXP (cmp
, 1))))
875 gen_fn
= (cmp_mode
== SImode
876 ? gen_movsfcc_internal0
877 : gen_movsfcc_internal1
);
879 gen_fn
= (cmp_mode
== SImode
880 ? gen_movsicc_internal0
881 : gen_movsicc_internal1
);
883 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), operands
[2], operands
[3], cmp
));
889 xtensa_expand_scc (rtx operands
[4], enum machine_mode cmp_mode
)
891 rtx dest
= operands
[0];
893 rtx one_tmp
, zero_tmp
;
894 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
896 if (!(cmp
= gen_conditional_move (GET_CODE (operands
[1]), cmp_mode
,
897 operands
[2], operands
[3])))
900 one_tmp
= gen_reg_rtx (SImode
);
901 zero_tmp
= gen_reg_rtx (SImode
);
902 emit_insn (gen_movsi (one_tmp
, const_true_rtx
));
903 emit_insn (gen_movsi (zero_tmp
, const0_rtx
));
905 gen_fn
= (cmp_mode
== SImode
906 ? gen_movsicc_internal0
907 : gen_movsicc_internal1
);
908 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), one_tmp
, zero_tmp
, cmp
));
913 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
914 for the output, i.e., the input operands are twice as big as MODE. */
917 xtensa_split_operand_pair (rtx operands
[4], enum machine_mode mode
)
919 switch (GET_CODE (operands
[1]))
922 operands
[3] = gen_rtx_REG (mode
, REGNO (operands
[1]) + 1);
923 operands
[2] = gen_rtx_REG (mode
, REGNO (operands
[1]));
927 operands
[3] = adjust_address (operands
[1], mode
, GET_MODE_SIZE (mode
));
928 operands
[2] = adjust_address (operands
[1], mode
, 0);
933 split_double (operands
[1], &operands
[2], &operands
[3]);
940 switch (GET_CODE (operands
[0]))
943 operands
[1] = gen_rtx_REG (mode
, REGNO (operands
[0]) + 1);
944 operands
[0] = gen_rtx_REG (mode
, REGNO (operands
[0]));
948 operands
[1] = adjust_address (operands
[0], mode
, GET_MODE_SIZE (mode
));
949 operands
[0] = adjust_address (operands
[0], mode
, 0);
958 /* Emit insns to move operands[1] into operands[0].
959 Return 1 if we have written out everything that needs to be done to
960 do the move. Otherwise, return 0 and the caller will emit the move
964 xtensa_emit_move_sequence (rtx
*operands
, enum machine_mode mode
)
966 rtx src
= operands
[1];
969 && (GET_CODE (src
) != CONST_INT
|| ! xtensa_simm12b (INTVAL (src
))))
971 rtx dst
= operands
[0];
973 if (xtensa_tls_referenced_p (src
))
977 if (GET_CODE (src
) == CONST
&& GET_CODE (XEXP (src
, 0)) == PLUS
)
979 addend
= XEXP (XEXP (src
, 0), 1);
980 src
= XEXP (XEXP (src
, 0), 0);
983 src
= xtensa_legitimize_tls_address (src
);
986 src
= gen_rtx_PLUS (mode
, src
, addend
);
987 src
= force_operand (src
, dst
);
989 emit_move_insn (dst
, src
);
993 if (! TARGET_CONST16
)
995 src
= force_const_mem (SImode
, src
);
999 /* PC-relative loads are always SImode, and CONST16 is only
1000 supported in the movsi pattern, so add a SUBREG for any other
1005 if (register_operand (dst
, mode
))
1007 emit_move_insn (simplify_gen_subreg (SImode
, dst
, mode
, 0), src
);
1012 src
= force_reg (SImode
, src
);
1013 src
= gen_lowpart_SUBREG (mode
, src
);
1019 if (!(reload_in_progress
| reload_completed
)
1020 && !xtensa_valid_move (mode
, operands
))
1021 operands
[1] = force_reg (mode
, operands
[1]);
1023 operands
[1] = xtensa_copy_incoming_a7 (operands
[1]);
1025 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
1026 instruction won't be recognized after reload, so we remove the
1027 subreg and adjust mem accordingly. */
1028 if (reload_in_progress
)
1030 operands
[0] = fixup_subreg_mem (operands
[0]);
1031 operands
[1] = fixup_subreg_mem (operands
[1]);
1038 fixup_subreg_mem (rtx x
)
1040 if (GET_CODE (x
) == SUBREG
1041 && GET_CODE (SUBREG_REG (x
)) == REG
1042 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
)
1045 gen_rtx_SUBREG (GET_MODE (x
),
1046 reg_equiv_mem
[REGNO (SUBREG_REG (x
))],
1048 x
= alter_subreg (&temp
);
1054 /* Check if an incoming argument in a7 is expected to be used soon and
1055 if OPND is a register or register pair that includes a7. If so,
1056 create a new pseudo and copy a7 into that pseudo at the very
1057 beginning of the function, followed by the special "set_frame_ptr"
1058 unspec_volatile insn. The return value is either the original
1059 operand, if it is not a7, or the new pseudo containing a copy of
1060 the incoming argument. This is necessary because the register
1061 allocator will ignore conflicts with a7 and may either assign some
1062 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1063 the incoming argument in a7. By copying the argument out of a7 as
1064 the very first thing, and then immediately following that with an
1065 unspec_volatile to keep the scheduler away, we should avoid any
1066 problems. Putting the set_frame_ptr insn at the beginning, with
1067 only the a7 copy before it, also makes it easier for the prologue
1068 expander to initialize the frame pointer after the a7 copy and to
1069 fix up the a7 copy to use the stack pointer instead of the frame
1073 xtensa_copy_incoming_a7 (rtx opnd
)
1075 rtx entry_insns
= 0;
1077 enum machine_mode mode
;
1079 if (!cfun
->machine
->need_a7_copy
)
1082 /* This function should never be called again once a7 has been copied. */
1083 gcc_assert (!cfun
->machine
->set_frame_ptr_insn
);
1085 mode
= GET_MODE (opnd
);
1087 /* The operand using a7 may come in a later instruction, so just return
1088 the original operand if it doesn't use a7. */
1090 if (GET_CODE (reg
) == SUBREG
)
1092 gcc_assert (SUBREG_BYTE (reg
) == 0);
1093 reg
= SUBREG_REG (reg
);
1095 if (GET_CODE (reg
) != REG
1096 || REGNO (reg
) > A7_REG
1097 || REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) <= A7_REG
)
1100 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1101 gcc_assert (REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) - 1 == A7_REG
);
1103 cfun
->machine
->need_a7_copy
= false;
1105 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1106 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1109 tmp
= gen_reg_rtx (mode
);
1115 /* Copy the value out of A7 here but keep the first word in A6 until
1116 after the set_frame_ptr insn. Otherwise, the register allocator
1117 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1119 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 4),
1120 gen_raw_REG (SImode
, A7_REG
)));
1123 emit_insn (gen_movsf_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1126 emit_insn (gen_movsi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1129 emit_insn (gen_movhi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1132 emit_insn (gen_movqi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1138 cfun
->machine
->set_frame_ptr_insn
= emit_insn (gen_set_frame_ptr ());
1140 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1141 if (mode
== DFmode
|| mode
== DImode
)
1142 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 0),
1143 gen_rtx_REG (SImode
, A7_REG
- 1)));
1144 entry_insns
= get_insns ();
1147 if (cfun
->machine
->vararg_a7
)
1149 /* This is called from within builtin_saveregs, which will insert the
1150 saveregs code at the function entry, ahead of anything placed at
1151 the function entry now. Instead, save the sequence to be inserted
1152 at the beginning of the saveregs code. */
1153 cfun
->machine
->vararg_a7_copy
= entry_insns
;
1157 /* Put entry_insns after the NOTE that starts the function. If
1158 this is inside a start_sequence, make the outer-level insn
1159 chain current, so the code is placed at the start of the
1161 push_topmost_sequence ();
1162 /* Do not use entry_of_function() here. This is called from within
1163 expand_function_start, when the CFG still holds GIMPLE. */
1164 emit_insn_after (entry_insns
, get_insns ());
1165 pop_topmost_sequence ();
1172 /* Try to expand a block move operation to a sequence of RTL move
1173 instructions. If not optimizing, or if the block size is not a
1174 constant, or if the block is too large, the expansion fails and GCC
1175 falls back to calling memcpy().
1177 operands[0] is the destination
1178 operands[1] is the source
1179 operands[2] is the length
1180 operands[3] is the alignment */
1183 xtensa_expand_block_move (rtx
*operands
)
1185 static const enum machine_mode mode_from_align
[] =
1187 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1190 rtx dst_mem
= operands
[0];
1191 rtx src_mem
= operands
[1];
1192 HOST_WIDE_INT bytes
, align
;
1193 int num_pieces
, move_ratio
;
1195 enum machine_mode mode
[2];
1204 /* If this is not a fixed size move, just call memcpy. */
1205 if (!optimize
|| (GET_CODE (operands
[2]) != CONST_INT
))
1208 bytes
= INTVAL (operands
[2]);
1209 align
= INTVAL (operands
[3]);
1211 /* Anything to move? */
1215 if (align
> MOVE_MAX
)
1218 /* Decide whether to expand inline based on the optimization level. */
1221 move_ratio
= LARGEST_MOVE_RATIO
;
1222 num_pieces
= (bytes
/ align
) + (bytes
% align
); /* Close enough anyway. */
1223 if (num_pieces
> move_ratio
)
1226 x
= XEXP (dst_mem
, 0);
1229 x
= force_reg (Pmode
, x
);
1230 dst_mem
= replace_equiv_address (dst_mem
, x
);
1233 x
= XEXP (src_mem
, 0);
1236 x
= force_reg (Pmode
, x
);
1237 src_mem
= replace_equiv_address (src_mem
, x
);
1240 active
[0] = active
[1] = false;
1251 next_amount
= (bytes
>= 4 ? 4 : (bytes
>= 2 ? 2 : 1));
1252 next_amount
= MIN (next_amount
, align
);
1254 amount
[next
] = next_amount
;
1255 mode
[next
] = mode_from_align
[next_amount
];
1256 temp
[next
] = gen_reg_rtx (mode
[next
]);
1258 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1259 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1261 offset_ld
+= next_amount
;
1262 bytes
-= next_amount
;
1263 active
[next
] = true;
1268 active
[phase
] = false;
1270 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1271 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1273 offset_st
+= amount
[phase
];
1276 while (active
[next
]);
1283 xtensa_expand_nonlocal_goto (rtx
*operands
)
1285 rtx goto_handler
= operands
[1];
1286 rtx containing_fp
= operands
[3];
1288 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1289 is too big to generate in-line. */
1291 if (GET_CODE (containing_fp
) != REG
)
1292 containing_fp
= force_reg (Pmode
, containing_fp
);
1294 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_nonlocal_goto"),
1296 containing_fp
, Pmode
,
1297 goto_handler
, Pmode
);
1301 static struct machine_function
*
1302 xtensa_init_machine_status (void)
1304 return ggc_alloc_cleared_machine_function ();
1308 /* Shift VAL of mode MODE left by COUNT bits. */
1311 xtensa_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
1313 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
1314 NULL_RTX
, 1, OPTAB_DIRECT
);
1315 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
1316 NULL_RTX
, 1, OPTAB_DIRECT
);
1320 /* Structure to hold the initial parameters for a compare_and_swap operation
1321 in HImode and QImode. */
1323 struct alignment_context
1325 rtx memsi
; /* SI aligned memory location. */
1326 rtx shift
; /* Bit offset with regard to lsb. */
1327 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
1328 rtx modemaski
; /* ~modemask */
1332 /* Initialize structure AC for word access to HI and QI mode memory. */
1335 init_alignment_context (struct alignment_context
*ac
, rtx mem
)
1337 enum machine_mode mode
= GET_MODE (mem
);
1338 rtx byteoffset
= NULL_RTX
;
1339 bool aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
1342 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
1345 /* Alignment is unknown. */
1348 /* Force the address into a register. */
1349 addr
= force_reg (Pmode
, XEXP (mem
, 0));
1351 /* Align it to SImode. */
1352 align
= expand_simple_binop (Pmode
, AND
, addr
,
1353 GEN_INT (-GET_MODE_SIZE (SImode
)),
1354 NULL_RTX
, 1, OPTAB_DIRECT
);
1356 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
1357 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
1358 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
1359 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
1361 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
1362 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
1363 NULL_RTX
, 1, OPTAB_DIRECT
);
1366 /* Calculate shiftcount. */
1367 if (TARGET_BIG_ENDIAN
)
1369 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
1371 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
1372 NULL_RTX
, 1, OPTAB_DIRECT
);
1377 ac
->shift
= NULL_RTX
;
1379 ac
->shift
= byteoffset
;
1382 if (ac
->shift
!= NULL_RTX
)
1384 /* Shift is the byte count, but we need the bitcount. */
1385 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
,
1386 GEN_INT (BITS_PER_UNIT
),
1387 NULL_RTX
, 1, OPTAB_DIRECT
);
1388 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
1389 GEN_INT (GET_MODE_MASK (mode
)),
1391 NULL_RTX
, 1, OPTAB_DIRECT
);
1394 ac
->modemask
= GEN_INT (GET_MODE_MASK (mode
));
1396 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
1400 /* Expand an atomic compare and swap operation for HImode and QImode.
1401 MEM is the memory location, CMP the old value to compare MEM with
1402 and NEW_RTX the value to set if CMP == MEM. */
1405 xtensa_expand_compare_and_swap (rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
1407 enum machine_mode mode
= GET_MODE (mem
);
1408 struct alignment_context ac
;
1409 rtx tmp
, cmpv
, newv
, val
;
1410 rtx oldval
= gen_reg_rtx (SImode
);
1411 rtx res
= gen_reg_rtx (SImode
);
1412 rtx csloop
= gen_label_rtx ();
1413 rtx csend
= gen_label_rtx ();
1415 init_alignment_context (&ac
, mem
);
1417 if (ac
.shift
!= NULL_RTX
)
1419 cmp
= xtensa_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
1420 new_rtx
= xtensa_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
1423 /* Load the surrounding word into VAL with the MEM value masked out. */
1424 val
= force_reg (SImode
, expand_simple_binop (SImode
, AND
, ac
.memsi
,
1425 ac
.modemaski
, NULL_RTX
, 1,
1427 emit_label (csloop
);
1429 /* Patch CMP and NEW_RTX into VAL at correct position. */
1430 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
1431 NULL_RTX
, 1, OPTAB_DIRECT
));
1432 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
1433 NULL_RTX
, 1, OPTAB_DIRECT
));
1435 /* Jump to end if we're done. */
1436 emit_insn (gen_sync_compare_and_swapsi (res
, ac
.memsi
, cmpv
, newv
));
1437 emit_cmp_and_jump_insns (res
, cmpv
, EQ
, const0_rtx
, SImode
, true, csend
);
1439 /* Check for changes outside mode. */
1440 emit_move_insn (oldval
, val
);
1441 tmp
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
1442 val
, 1, OPTAB_DIRECT
);
1444 emit_move_insn (val
, tmp
);
1446 /* Loop internal if so. */
1447 emit_cmp_and_jump_insns (oldval
, val
, NE
, const0_rtx
, SImode
, true, csloop
);
1451 /* Return the correct part of the bitfield. */
1452 convert_move (target
,
1453 (ac
.shift
== NULL_RTX
? res
1454 : expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
1455 NULL_RTX
, 1, OPTAB_DIRECT
)),
1460 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1461 the default expansion works fine for SImode). MEM is the memory location
1462 and VAL the value to play with. If AFTER is true then store the value
1463 MEM holds after the operation, if AFTER is false then store the value MEM
1464 holds before the operation. If TARGET is zero then discard that value, else
1465 store it to TARGET. */
1468 xtensa_expand_atomic (enum rtx_code code
, rtx target
, rtx mem
, rtx val
,
1471 enum machine_mode mode
= GET_MODE (mem
);
1472 struct alignment_context ac
;
1473 rtx csloop
= gen_label_rtx ();
1475 rtx old
= gen_reg_rtx (SImode
);
1476 rtx new_rtx
= gen_reg_rtx (SImode
);
1477 rtx orig
= NULL_RTX
;
1479 init_alignment_context (&ac
, mem
);
1481 /* Prepare values before the compare-and-swap loop. */
1482 if (ac
.shift
!= NULL_RTX
)
1483 val
= xtensa_expand_mask_and_shift (val
, mode
, ac
.shift
);
1488 orig
= gen_reg_rtx (SImode
);
1489 convert_move (orig
, val
, 1);
1497 case MULT
: /* NAND */
1499 /* val = "11..1<val>11..1" */
1500 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
1501 NULL_RTX
, 1, OPTAB_DIRECT
);
1508 /* Load full word. Subsequent loads are performed by S32C1I. */
1509 cmp
= force_reg (SImode
, ac
.memsi
);
1511 emit_label (csloop
);
1512 emit_move_insn (old
, cmp
);
1518 val
= expand_simple_binop (SImode
, code
, old
, orig
,
1519 NULL_RTX
, 1, OPTAB_DIRECT
);
1520 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
1521 NULL_RTX
, 1, OPTAB_DIRECT
);
1524 tmp
= expand_simple_binop (SImode
, AND
, old
, ac
.modemaski
,
1525 NULL_RTX
, 1, OPTAB_DIRECT
);
1526 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
,
1527 new_rtx
, 1, OPTAB_DIRECT
);
1533 tmp
= expand_simple_binop (SImode
, code
, old
, val
,
1534 new_rtx
, 1, OPTAB_DIRECT
);
1537 case MULT
: /* NAND */
1538 tmp
= expand_simple_binop (SImode
, XOR
, old
, ac
.modemask
,
1539 NULL_RTX
, 1, OPTAB_DIRECT
);
1540 tmp
= expand_simple_binop (SImode
, AND
, tmp
, val
,
1541 new_rtx
, 1, OPTAB_DIRECT
);
1549 emit_move_insn (new_rtx
, tmp
);
1550 emit_insn (gen_sync_compare_and_swapsi (cmp
, ac
.memsi
, old
, new_rtx
));
1551 emit_cmp_and_jump_insns (cmp
, old
, NE
, const0_rtx
, SImode
, true, csloop
);
1555 tmp
= (after
? new_rtx
: cmp
);
1556 convert_move (target
,
1557 (ac
.shift
== NULL_RTX
? tmp
1558 : expand_simple_binop (SImode
, LSHIFTRT
, tmp
, ac
.shift
,
1559 NULL_RTX
, 1, OPTAB_DIRECT
)),
1566 xtensa_setup_frame_addresses (void)
1568 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1569 cfun
->machine
->accesses_prev_frame
= 1;
1572 (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_libgcc_window_spill"),
1577 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1578 a comment showing where the end of the loop is. However, if there is a
1579 label or a branch at the end of the loop then we need to place a nop
1580 there. If the loop ends with a label we need the nop so that branches
1581 targeting that label will target the nop (and thus remain in the loop),
1582 instead of targeting the instruction after the loop (and thus exiting
1583 the loop). If the loop ends with a branch, we need the nop in case the
1584 branch is targeting a location inside the loop. When the branch
1585 executes it will cause the loop count to be decremented even if it is
1586 taken (because it is the last instruction in the loop), so we need to
1587 nop after the branch to prevent the loop count from being decremented
1588 when the branch is taken. */
1591 xtensa_emit_loop_end (rtx insn
, rtx
*operands
)
1595 for (insn
= PREV_INSN (insn
); insn
&& !done
; insn
= PREV_INSN (insn
))
1597 switch (GET_CODE (insn
))
1604 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1610 rtx body
= PATTERN (insn
);
1612 if (GET_CODE (body
) == JUMP_INSN
)
1614 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1617 else if ((GET_CODE (body
) != USE
)
1618 && (GET_CODE (body
) != CLOBBER
))
1625 output_asm_insn ("# loop end for %0", operands
);
1630 xtensa_emit_branch (bool inverted
, bool immed
, rtx
*operands
)
1632 static char result
[64];
1636 code
= GET_CODE (operands
[3]);
1639 case EQ
: op
= inverted
? "ne" : "eq"; break;
1640 case NE
: op
= inverted
? "eq" : "ne"; break;
1641 case LT
: op
= inverted
? "ge" : "lt"; break;
1642 case GE
: op
= inverted
? "lt" : "ge"; break;
1643 case LTU
: op
= inverted
? "geu" : "ltu"; break;
1644 case GEU
: op
= inverted
? "ltu" : "geu"; break;
1645 default: gcc_unreachable ();
1650 if (INTVAL (operands
[1]) == 0)
1651 sprintf (result
, "b%sz%s\t%%0, %%2", op
,
1652 (TARGET_DENSITY
&& (code
== EQ
|| code
== NE
)) ? ".n" : "");
1654 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1657 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1664 xtensa_emit_bit_branch (bool inverted
, bool immed
, rtx
*operands
)
1666 static char result
[64];
1669 switch (GET_CODE (operands
[3]))
1671 case EQ
: op
= inverted
? "bs" : "bc"; break;
1672 case NE
: op
= inverted
? "bc" : "bs"; break;
1673 default: gcc_unreachable ();
1678 unsigned bitnum
= INTVAL (operands
[1]) & 0x1f;
1679 operands
[1] = GEN_INT (bitnum
);
1680 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1683 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1690 xtensa_emit_movcc (bool inverted
, bool isfp
, bool isbool
, rtx
*operands
)
1692 static char result
[64];
1696 code
= GET_CODE (operands
[4]);
1701 case EQ
: op
= inverted
? "t" : "f"; break;
1702 case NE
: op
= inverted
? "f" : "t"; break;
1703 default: gcc_unreachable ();
1710 case EQ
: op
= inverted
? "nez" : "eqz"; break;
1711 case NE
: op
= inverted
? "eqz" : "nez"; break;
1712 case LT
: op
= inverted
? "gez" : "ltz"; break;
1713 case GE
: op
= inverted
? "ltz" : "gez"; break;
1714 default: gcc_unreachable ();
1718 sprintf (result
, "mov%s%s\t%%0, %%%d, %%1",
1719 op
, isfp
? ".s" : "", inverted
? 3 : 2);
1725 xtensa_emit_call (int callop
, rtx
*operands
)
1727 static char result
[64];
1728 rtx tgt
= operands
[callop
];
1730 if (GET_CODE (tgt
) == CONST_INT
)
1731 sprintf (result
, "call8\t0x%lx", INTVAL (tgt
));
1732 else if (register_operand (tgt
, VOIDmode
))
1733 sprintf (result
, "callx8\t%%%d", callop
);
1735 sprintf (result
, "call8\t%%%d", callop
);
1742 xtensa_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
1744 /* Allow constant pool addresses. */
1745 if (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
1746 && ! TARGET_CONST16
&& constantpool_address_p (addr
)
1747 && ! xtensa_tls_referenced_p (addr
))
1750 while (GET_CODE (addr
) == SUBREG
)
1751 addr
= SUBREG_REG (addr
);
1753 /* Allow base registers. */
1754 if (GET_CODE (addr
) == REG
&& BASE_REG_P (addr
, strict
))
1757 /* Check for "register + offset" addressing. */
1758 if (GET_CODE (addr
) == PLUS
)
1760 rtx xplus0
= XEXP (addr
, 0);
1761 rtx xplus1
= XEXP (addr
, 1);
1762 enum rtx_code code0
;
1763 enum rtx_code code1
;
1765 while (GET_CODE (xplus0
) == SUBREG
)
1766 xplus0
= SUBREG_REG (xplus0
);
1767 code0
= GET_CODE (xplus0
);
1769 while (GET_CODE (xplus1
) == SUBREG
)
1770 xplus1
= SUBREG_REG (xplus1
);
1771 code1
= GET_CODE (xplus1
);
1773 /* Swap operands if necessary so the register is first. */
1774 if (code0
!= REG
&& code1
== REG
)
1776 xplus0
= XEXP (addr
, 1);
1777 xplus1
= XEXP (addr
, 0);
1778 code0
= GET_CODE (xplus0
);
1779 code1
= GET_CODE (xplus1
);
1782 if (code0
== REG
&& BASE_REG_P (xplus0
, strict
)
1783 && code1
== CONST_INT
1784 && xtensa_mem_offset (INTVAL (xplus1
), mode
))
1792 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1794 static GTY(()) rtx xtensa_tls_module_base_symbol
;
1797 xtensa_tls_module_base (void)
1799 if (! xtensa_tls_module_base_symbol
)
1801 xtensa_tls_module_base_symbol
=
1802 gen_rtx_SYMBOL_REF (Pmode
, "_TLS_MODULE_BASE_");
1803 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol
)
1804 |= TLS_MODEL_GLOBAL_DYNAMIC
<< SYMBOL_FLAG_TLS_SHIFT
;
1807 return xtensa_tls_module_base_symbol
;
1812 xtensa_call_tls_desc (rtx sym
, rtx
*retp
)
1814 rtx fn
, arg
, a10
, call_insn
, insns
;
1817 fn
= gen_reg_rtx (Pmode
);
1818 arg
= gen_reg_rtx (Pmode
);
1819 a10
= gen_rtx_REG (Pmode
, 10);
1821 emit_insn (gen_tls_func (fn
, sym
));
1822 emit_insn (gen_tls_arg (arg
, sym
));
1823 emit_move_insn (a10
, arg
);
1824 call_insn
= emit_call_insn (gen_tls_call (a10
, fn
, sym
, const1_rtx
));
1825 CALL_INSN_FUNCTION_USAGE (call_insn
)
1826 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, a10
),
1827 CALL_INSN_FUNCTION_USAGE (call_insn
));
1828 insns
= get_insns ();
1837 xtensa_legitimize_tls_address (rtx x
)
1839 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
1840 rtx dest
, tp
, ret
, modbase
, base
, addend
, insns
;
1842 dest
= gen_reg_rtx (Pmode
);
1845 case TLS_MODEL_GLOBAL_DYNAMIC
:
1846 insns
= xtensa_call_tls_desc (x
, &ret
);
1847 emit_libcall_block (insns
, dest
, ret
, x
);
1850 case TLS_MODEL_LOCAL_DYNAMIC
:
1851 base
= gen_reg_rtx (Pmode
);
1852 modbase
= xtensa_tls_module_base ();
1853 insns
= xtensa_call_tls_desc (modbase
, &ret
);
1854 emit_libcall_block (insns
, base
, ret
, modbase
);
1855 addend
= force_reg (SImode
, gen_sym_DTPOFF (x
));
1856 emit_insn (gen_addsi3 (dest
, base
, addend
));
1859 case TLS_MODEL_INITIAL_EXEC
:
1860 case TLS_MODEL_LOCAL_EXEC
:
1861 tp
= gen_reg_rtx (SImode
);
1862 emit_insn (gen_load_tp (tp
));
1863 addend
= force_reg (SImode
, gen_sym_TPOFF (x
));
1864 emit_insn (gen_addsi3 (dest
, tp
, addend
));
1876 xtensa_legitimize_address (rtx x
,
1877 rtx oldx ATTRIBUTE_UNUSED
,
1878 enum machine_mode mode
)
1880 if (xtensa_tls_symbol_p (x
))
1881 return xtensa_legitimize_tls_address (x
);
1883 if (GET_CODE (x
) == PLUS
)
1885 rtx plus0
= XEXP (x
, 0);
1886 rtx plus1
= XEXP (x
, 1);
1888 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1890 plus0
= XEXP (x
, 1);
1891 plus1
= XEXP (x
, 0);
1894 /* Try to split up the offset to use an ADDMI instruction. */
1895 if (GET_CODE (plus0
) == REG
1896 && GET_CODE (plus1
) == CONST_INT
1897 && !xtensa_mem_offset (INTVAL (plus1
), mode
)
1898 && !xtensa_simm8 (INTVAL (plus1
))
1899 && xtensa_mem_offset (INTVAL (plus1
) & 0xff, mode
)
1900 && xtensa_simm8x256 (INTVAL (plus1
) & ~0xff))
1902 rtx temp
= gen_reg_rtx (Pmode
);
1903 rtx addmi_offset
= GEN_INT (INTVAL (plus1
) & ~0xff);
1904 emit_insn (gen_rtx_SET (Pmode
, temp
,
1905 gen_rtx_PLUS (Pmode
, plus0
, addmi_offset
)));
1906 return gen_rtx_PLUS (Pmode
, temp
, GEN_INT (INTVAL (plus1
) & 0xff));
1914 /* Helper for xtensa_tls_referenced_p. */
1917 xtensa_tls_referenced_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1919 if (GET_CODE (*x
) == SYMBOL_REF
)
1920 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
1922 /* Ignore TLS references that have already been legitimized. */
1923 if (GET_CODE (*x
) == UNSPEC
)
1925 switch (XINT (*x
, 1))
1929 case UNSPEC_TLS_FUNC
:
1930 case UNSPEC_TLS_ARG
:
1931 case UNSPEC_TLS_CALL
:
1942 /* Return TRUE if X contains any TLS symbol references. */
1945 xtensa_tls_referenced_p (rtx x
)
1947 if (! TARGET_HAVE_TLS
)
1950 return for_each_rtx (&x
, xtensa_tls_referenced_p_1
, NULL
);
1954 /* Return the debugger register number to use for 'regno'. */
1957 xtensa_dbx_register_number (int regno
)
1961 if (GP_REG_P (regno
))
1963 regno
-= GP_REG_FIRST
;
1966 else if (BR_REG_P (regno
))
1968 regno
-= BR_REG_FIRST
;
1971 else if (FP_REG_P (regno
))
1973 regno
-= FP_REG_FIRST
;
1976 else if (ACC_REG_P (regno
))
1978 first
= 0x200; /* Start of Xtensa special registers. */
1979 regno
= 16; /* ACCLO is special register 16. */
1982 /* When optimizing, we sometimes get asked about pseudo-registers
1983 that don't represent hard registers. Return 0 for these. */
1987 return first
+ regno
;
1991 /* Argument support functions. */
1993 /* Initialize CUMULATIVE_ARGS for a function. */
1996 init_cumulative_args (CUMULATIVE_ARGS
*cum
, int incoming
)
1999 cum
->incoming
= incoming
;
2003 /* Advance the argument to the next argument position. */
2006 xtensa_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
2007 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2012 arg_words
= &cum
->arg_words
;
2013 max
= MAX_ARGS_IN_REGISTERS
;
2015 words
= (((mode
!= BLKmode
)
2016 ? (int) GET_MODE_SIZE (mode
)
2017 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2019 if (*arg_words
< max
2020 && (targetm
.calls
.must_pass_in_stack (mode
, type
)
2021 || *arg_words
+ words
> max
))
2024 *arg_words
+= words
;
2028 /* Return an RTL expression containing the register for the given mode,
2029 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2030 if this is an incoming argument to the current function. */
2033 xtensa_function_arg_1 (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
2034 const_tree type
, bool incoming_p
)
2036 int regbase
, words
, max
;
2040 arg_words
= &cum
->arg_words
;
2041 regbase
= (incoming_p
? GP_ARG_FIRST
: GP_OUTGOING_ARG_FIRST
);
2042 max
= MAX_ARGS_IN_REGISTERS
;
2044 words
= (((mode
!= BLKmode
)
2045 ? (int) GET_MODE_SIZE (mode
)
2046 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2048 if (type
&& (TYPE_ALIGN (type
) > BITS_PER_WORD
))
2050 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_WORD
;
2051 *arg_words
= (*arg_words
+ align
- 1) & -align
;
2054 if (*arg_words
+ words
> max
)
2057 regno
= regbase
+ *arg_words
;
2059 if (cum
->incoming
&& regno
<= A7_REG
&& regno
+ words
> A7_REG
)
2060 cfun
->machine
->need_a7_copy
= true;
2062 return gen_rtx_REG (mode
, regno
);
2065 /* Implement TARGET_FUNCTION_ARG. */
2068 xtensa_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
2069 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2071 return xtensa_function_arg_1 (cum
, mode
, type
, false);
2074 /* Implement TARGET_FUNCTION_INCOMING_ARG. */
2077 xtensa_function_incoming_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
2078 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2080 return xtensa_function_arg_1 (cum
, mode
, type
, true);
2084 function_arg_boundary (enum machine_mode mode
, tree type
)
2086 unsigned int alignment
;
2088 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2089 if (alignment
< PARM_BOUNDARY
)
2090 alignment
= PARM_BOUNDARY
;
2091 if (alignment
> STACK_BOUNDARY
)
2092 alignment
= STACK_BOUNDARY
;
2098 xtensa_return_in_msb (const_tree valtype
)
2100 return (TARGET_BIG_ENDIAN
2101 && AGGREGATE_TYPE_P (valtype
)
2102 && int_size_in_bytes (valtype
) >= UNITS_PER_WORD
);
2107 xtensa_option_override (void)
2110 enum machine_mode mode
;
2112 if (!TARGET_BOOLEANS
&& TARGET_HARD_FLOAT
)
2113 error ("boolean registers required for the floating-point option");
2115 /* Set up array giving whether a given register can hold a given mode. */
2116 for (mode
= VOIDmode
;
2117 mode
!= MAX_MACHINE_MODE
;
2118 mode
= (enum machine_mode
) ((int) mode
+ 1))
2120 int size
= GET_MODE_SIZE (mode
);
2121 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2123 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2127 if (ACC_REG_P (regno
))
2128 temp
= (TARGET_MAC16
2129 && (mclass
== MODE_INT
) && (size
<= UNITS_PER_WORD
));
2130 else if (GP_REG_P (regno
))
2131 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
2132 else if (FP_REG_P (regno
))
2133 temp
= (TARGET_HARD_FLOAT
&& (mode
== SFmode
));
2134 else if (BR_REG_P (regno
))
2135 temp
= (TARGET_BOOLEANS
&& (mode
== CCmode
));
2139 xtensa_hard_regno_mode_ok
[(int) mode
][regno
] = temp
;
2143 init_machine_status
= xtensa_init_machine_status
;
2145 /* Check PIC settings. PIC is only supported when using L32R
2146 instructions, and some targets need to always use PIC. */
2147 if (flag_pic
&& TARGET_CONST16
)
2148 error ("-f%s is not supported with CONST16 instructions",
2149 (flag_pic
> 1 ? "PIC" : "pic"));
2150 else if (TARGET_FORCE_NO_PIC
)
2152 else if (XTENSA_ALWAYS_PIC
)
2155 error ("PIC is required but not supported with CONST16 instructions");
2158 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2161 if (flag_pic
&& !flag_pie
)
2164 /* Hot/cold partitioning does not work on this architecture, because of
2165 constant pools (the load instruction cannot necessarily reach that far).
2166 Therefore disable it on this architecture. */
2167 if (flag_reorder_blocks_and_partition
)
2169 flag_reorder_blocks_and_partition
= 0;
2170 flag_reorder_blocks
= 1;
2174 /* Implement TARGET_OPTION_OPTIMIZATION. */
2177 xtensa_option_optimization (int level ATTRIBUTE_UNUSED
,
2178 int size ATTRIBUTE_UNUSED
)
2180 /* Reordering blocks for Xtensa is not a good idea unless the
2181 compiler understands the range of conditional branches.
2182 Currently all branch relaxation for Xtensa is handled in the
2183 assembler, so GCC cannot do a good job of reordering blocks. Do
2184 not enable reordering unless it is explicitly requested. */
2185 flag_reorder_blocks
= 0;
2188 /* A C compound statement to output to stdio stream STREAM the
2189 assembler syntax for an instruction operand X. X is an RTL
2192 CODE is a value that can be used to specify one of several ways
2193 of printing the operand. It is used when identical operands
2194 must be printed differently depending on the context. CODE
2195 comes from the '%' specification that was used to request
2196 printing of the operand. If the specification was just '%DIGIT'
2197 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2198 is the ASCII code for LTR.
2200 If X is a register, this macro should print the register's name.
2201 The names can be found in an array 'reg_names' whose type is
2202 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2204 When the machine description has a specification '%PUNCT' (a '%'
2205 followed by a punctuation character), this macro is called with
2206 a null pointer for X and the punctuation character for CODE.
2208 'a', 'c', 'l', and 'n' are reserved.
2210 The Xtensa specific codes are:
2212 'd' CONST_INT, print as signed decimal
2213 'x' CONST_INT, print as signed hexadecimal
2214 'K' CONST_INT, print number of bits in mask for EXTUI
2215 'R' CONST_INT, print (X & 0x1f)
2216 'L' CONST_INT, print ((32 - X) & 0x1f)
2217 'D' REG, print second register of double-word register operand
2218 'N' MEM, print address of next word following a memory operand
2219 'v' MEM, if memory reference is volatile, output a MEMW before it
2220 't' any constant, add "@h" suffix for top 16 bits
2221 'b' any constant, add "@l" suffix for bottom 16 bits
2225 printx (FILE *file
, signed int val
)
2227 /* Print a hexadecimal value in a nice way. */
2228 if ((val
> -0xa) && (val
< 0xa))
2229 fprintf (file
, "%d", val
);
2231 fprintf (file
, "-0x%x", -val
);
2233 fprintf (file
, "0x%x", val
);
2238 print_operand (FILE *file
, rtx x
, int letter
)
2241 error ("PRINT_OPERAND null pointer");
2246 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2247 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
) + 1]);
2249 output_operand_lossage ("invalid %%D value");
2253 if (GET_CODE (x
) == MEM
)
2255 /* For a volatile memory reference, emit a MEMW before the
2257 if (MEM_VOLATILE_P (x
) && TARGET_SERIALIZE_VOLATILE
)
2258 fprintf (file
, "memw\n\t");
2261 output_operand_lossage ("invalid %%v value");
2265 if (GET_CODE (x
) == MEM
2266 && (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DImode
))
2268 x
= adjust_address (x
, GET_MODE (x
) == DFmode
? SFmode
: SImode
, 4);
2269 output_address (XEXP (x
, 0));
2272 output_operand_lossage ("invalid %%N value");
2276 if (GET_CODE (x
) == CONST_INT
)
2279 unsigned val
= INTVAL (x
);
2285 if ((val
!= 0) || (num_bits
== 0) || (num_bits
> 16))
2286 fatal_insn ("invalid mask", x
);
2288 fprintf (file
, "%d", num_bits
);
2291 output_operand_lossage ("invalid %%K value");
2295 if (GET_CODE (x
) == CONST_INT
)
2296 fprintf (file
, "%ld", (32 - INTVAL (x
)) & 0x1f);
2298 output_operand_lossage ("invalid %%L value");
2302 if (GET_CODE (x
) == CONST_INT
)
2303 fprintf (file
, "%ld", INTVAL (x
) & 0x1f);
2305 output_operand_lossage ("invalid %%R value");
2309 if (GET_CODE (x
) == CONST_INT
)
2310 printx (file
, INTVAL (x
));
2312 output_operand_lossage ("invalid %%x value");
2316 if (GET_CODE (x
) == CONST_INT
)
2317 fprintf (file
, "%ld", INTVAL (x
));
2319 output_operand_lossage ("invalid %%d value");
2324 if (GET_CODE (x
) == CONST_INT
)
2326 printx (file
, INTVAL (x
));
2327 fputs (letter
== 't' ? "@h" : "@l", file
);
2329 else if (GET_CODE (x
) == CONST_DOUBLE
)
2332 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2333 if (GET_MODE (x
) == SFmode
)
2336 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
2337 fprintf (file
, "0x%08lx@%c", l
, letter
== 't' ? 'h' : 'l');
2340 output_operand_lossage ("invalid %%t/%%b value");
2342 else if (GET_CODE (x
) == CONST
)
2344 /* X must be a symbolic constant on ELF. Write an expression
2345 suitable for 'const16' that sets the high or low 16 bits. */
2346 if (GET_CODE (XEXP (x
, 0)) != PLUS
2347 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
2348 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
2349 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
2350 output_operand_lossage ("invalid %%t/%%b value");
2351 print_operand (file
, XEXP (XEXP (x
, 0), 0), 0);
2352 fputs (letter
== 't' ? "@h" : "@l", file
);
2353 /* There must be a non-alphanumeric character between 'h' or 'l'
2354 and the number. The '-' is added by print_operand() already. */
2355 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
2357 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
2361 output_addr_const (file
, x
);
2362 fputs (letter
== 't' ? "@h" : "@l", file
);
2367 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2368 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
)]);
2369 else if (GET_CODE (x
) == MEM
)
2370 output_address (XEXP (x
, 0));
2371 else if (GET_CODE (x
) == CONST_INT
)
2372 fprintf (file
, "%ld", INTVAL (x
));
2374 output_addr_const (file
, x
);
2379 /* A C compound statement to output to stdio stream STREAM the
2380 assembler syntax for an instruction operand that is a memory
2381 reference whose address is ADDR. ADDR is an RTL expression. */
2384 print_operand_address (FILE *file
, rtx addr
)
2387 error ("PRINT_OPERAND_ADDRESS, null pointer");
2389 switch (GET_CODE (addr
))
2392 fatal_insn ("invalid address", addr
);
2396 fprintf (file
, "%s, 0", reg_names
[REGNO (addr
)]);
2402 rtx offset
= (rtx
)0;
2403 rtx arg0
= XEXP (addr
, 0);
2404 rtx arg1
= XEXP (addr
, 1);
2406 if (GET_CODE (arg0
) == REG
)
2411 else if (GET_CODE (arg1
) == REG
)
2417 fatal_insn ("no register in address", addr
);
2419 if (CONSTANT_P (offset
))
2421 fprintf (file
, "%s, ", reg_names
[REGNO (reg
)]);
2422 output_addr_const (file
, offset
);
2425 fatal_insn ("address offset not a constant", addr
);
2433 output_addr_const (file
, addr
);
2440 xtensa_output_addr_const_extra (FILE *fp
, rtx x
)
2442 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
2444 switch (XINT (x
, 1))
2447 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2448 fputs ("@TPOFF", fp
);
2451 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2452 fputs ("@DTPOFF", fp
);
2457 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2471 xtensa_output_literal (FILE *file
, rtx x
, enum machine_mode mode
, int labelno
)
2478 fprintf (file
, "\t.literal .LC%u, ", (unsigned) labelno
);
2480 switch (GET_MODE_CLASS (mode
))
2483 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
);
2485 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2489 REAL_VALUE_TO_TARGET_SINGLE (r
, value_long
[0]);
2490 if (HOST_BITS_PER_LONG
> 32)
2491 value_long
[0] &= 0xffffffff;
2492 fprintf (file
, "0x%08lx\n", value_long
[0]);
2496 REAL_VALUE_TO_TARGET_DOUBLE (r
, value_long
);
2497 if (HOST_BITS_PER_LONG
> 32)
2499 value_long
[0] &= 0xffffffff;
2500 value_long
[1] &= 0xffffffff;
2502 fprintf (file
, "0x%08lx, 0x%08lx\n",
2503 value_long
[0], value_long
[1]);
2513 case MODE_PARTIAL_INT
:
2514 size
= GET_MODE_SIZE (mode
);
2518 output_addr_const (file
, x
);
2523 split_double (x
, &first
, &second
);
2524 output_addr_const (file
, first
);
2526 output_addr_const (file
, second
);
2541 /* Return the bytes needed to compute the frame pointer from the current
2544 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2545 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2548 compute_frame_size (int size
)
2550 /* Add space for the incoming static chain value. */
2551 if (cfun
->static_chain_decl
!= NULL
)
2552 size
+= (1 * UNITS_PER_WORD
);
2554 xtensa_current_frame_size
=
2555 XTENSA_STACK_ALIGN (size
2556 + crtl
->outgoing_args_size
2557 + (WINDOW_SIZE
* UNITS_PER_WORD
));
2558 return xtensa_current_frame_size
;
2563 xtensa_frame_pointer_required (void)
2565 /* The code to expand builtin_frame_addr and builtin_return_addr
2566 currently uses the hard_frame_pointer instead of frame_pointer.
2567 This seems wrong but maybe it's necessary for other architectures.
2568 This function is derived from the i386 code. */
2570 if (cfun
->machine
->accesses_prev_frame
)
2577 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2578 and the total number of words must be a multiple of 128 bits. */
2579 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2582 xtensa_expand_prologue (void)
2584 HOST_WIDE_INT total_size
;
2588 total_size
= compute_frame_size (get_frame_size ());
2589 size_rtx
= GEN_INT (total_size
);
2591 if (total_size
< (1 << (12+3)))
2592 insn
= emit_insn (gen_entry (size_rtx
));
2595 /* Use a8 as a temporary since a0-a7 may be live. */
2596 rtx tmp_reg
= gen_rtx_REG (Pmode
, A8_REG
);
2597 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE
)));
2598 emit_move_insn (tmp_reg
, GEN_INT (total_size
- MIN_FRAME_SIZE
));
2599 emit_insn (gen_subsi3 (tmp_reg
, stack_pointer_rtx
, tmp_reg
));
2600 insn
= emit_insn (gen_movsi (stack_pointer_rtx
, tmp_reg
));
2603 if (frame_pointer_needed
)
2605 if (cfun
->machine
->set_frame_ptr_insn
)
2609 push_topmost_sequence ();
2610 first
= get_insns ();
2611 pop_topmost_sequence ();
2613 /* For all instructions prior to set_frame_ptr_insn, replace
2614 hard_frame_pointer references with stack_pointer. */
2616 insn
!= cfun
->machine
->set_frame_ptr_insn
;
2617 insn
= NEXT_INSN (insn
))
2621 PATTERN (insn
) = replace_rtx (copy_rtx (PATTERN (insn
)),
2622 hard_frame_pointer_rtx
,
2624 df_insn_rescan (insn
);
2629 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
2630 stack_pointer_rtx
));
2633 /* Create a note to describe the CFA. Because this is only used to set
2634 DW_AT_frame_base for debug info, don't bother tracking changes through
2635 each instruction in the prologue. It just takes up space. */
2636 note_rtx
= gen_rtx_SET (VOIDmode
, (frame_pointer_needed
2637 ? hard_frame_pointer_rtx
2638 : stack_pointer_rtx
),
2639 plus_constant (stack_pointer_rtx
, -total_size
));
2640 RTX_FRAME_RELATED_P (insn
) = 1;
2641 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2642 note_rtx
, REG_NOTES (insn
));
2646 /* Clear variables at function end. */
2649 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
2650 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
2652 xtensa_current_frame_size
= 0;
2657 xtensa_return_addr (int count
, rtx frame
)
2659 rtx result
, retaddr
, curaddr
, label
;
2662 retaddr
= gen_rtx_REG (Pmode
, A0_REG
);
2665 rtx addr
= plus_constant (frame
, -4 * UNITS_PER_WORD
);
2666 addr
= memory_address (Pmode
, addr
);
2667 retaddr
= gen_reg_rtx (Pmode
);
2668 emit_move_insn (retaddr
, gen_rtx_MEM (Pmode
, addr
));
2671 /* The 2 most-significant bits of the return address on Xtensa hold
2672 the register window size. To get the real return address, these
2673 bits must be replaced with the high bits from some address in the
2676 /* Get the 2 high bits of a local label in the code. */
2677 curaddr
= gen_reg_rtx (Pmode
);
2678 label
= gen_label_rtx ();
2680 LABEL_PRESERVE_P (label
) = 1;
2681 emit_move_insn (curaddr
, gen_rtx_LABEL_REF (Pmode
, label
));
2682 emit_insn (gen_lshrsi3 (curaddr
, curaddr
, GEN_INT (30)));
2683 emit_insn (gen_ashlsi3 (curaddr
, curaddr
, GEN_INT (30)));
2685 /* Clear the 2 high bits of the return address. */
2686 result
= gen_reg_rtx (Pmode
);
2687 emit_insn (gen_ashlsi3 (result
, retaddr
, GEN_INT (2)));
2688 emit_insn (gen_lshrsi3 (result
, result
, GEN_INT (2)));
2690 /* Combine them to get the result. */
2691 emit_insn (gen_iorsi3 (result
, result
, curaddr
));
2696 /* Create the va_list data type.
2698 This structure is set up by __builtin_saveregs. The __va_reg field
2699 points to a stack-allocated region holding the contents of the
2700 incoming argument registers. The __va_ndx field is an index
2701 initialized to the position of the first unnamed (variable)
2702 argument. This same index is also used to address the arguments
2703 passed in memory. Thus, the __va_stk field is initialized to point
2704 to the position of the first argument in memory offset to account
2705 for the arguments passed in registers and to account for the size
2706 of the argument registers not being 16-byte aligned. E.G., there
2707 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2708 for the first stack argument to have the maximal alignment of 16
2709 bytes, so we offset the __va_stk address by 32 bytes so that
2710 __va_stk[32] references the first argument on the stack. */
2713 xtensa_build_builtin_va_list (void)
2715 tree f_stk
, f_reg
, f_ndx
, record
, type_decl
;
2717 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
2718 type_decl
= build_decl (BUILTINS_LOCATION
,
2719 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
2721 f_stk
= build_decl (BUILTINS_LOCATION
,
2722 FIELD_DECL
, get_identifier ("__va_stk"),
2724 f_reg
= build_decl (BUILTINS_LOCATION
,
2725 FIELD_DECL
, get_identifier ("__va_reg"),
2727 f_ndx
= build_decl (BUILTINS_LOCATION
,
2728 FIELD_DECL
, get_identifier ("__va_ndx"),
2731 DECL_FIELD_CONTEXT (f_stk
) = record
;
2732 DECL_FIELD_CONTEXT (f_reg
) = record
;
2733 DECL_FIELD_CONTEXT (f_ndx
) = record
;
2735 TYPE_STUB_DECL (record
) = type_decl
;
2736 TYPE_NAME (record
) = type_decl
;
2737 TYPE_FIELDS (record
) = f_stk
;
2738 DECL_CHAIN (f_stk
) = f_reg
;
2739 DECL_CHAIN (f_reg
) = f_ndx
;
2741 layout_type (record
);
2746 /* Save the incoming argument registers on the stack. Returns the
2747 address of the saved registers. */
2750 xtensa_builtin_saveregs (void)
2753 int arg_words
= crtl
->args
.info
.arg_words
;
2754 int gp_left
= MAX_ARGS_IN_REGISTERS
- arg_words
;
2759 /* Allocate the general-purpose register space. */
2760 gp_regs
= assign_stack_local
2761 (BLKmode
, MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
, -1);
2762 set_mem_alias_set (gp_regs
, get_varargs_alias_set ());
2764 /* Now store the incoming registers. */
2765 cfun
->machine
->need_a7_copy
= true;
2766 cfun
->machine
->vararg_a7
= true;
2767 move_block_from_reg (GP_ARG_FIRST
+ arg_words
,
2768 adjust_address (gp_regs
, BLKmode
,
2769 arg_words
* UNITS_PER_WORD
),
2771 gcc_assert (cfun
->machine
->vararg_a7_copy
!= 0);
2772 emit_insn_before (cfun
->machine
->vararg_a7_copy
, get_insns ());
2774 return XEXP (gp_regs
, 0);
2778 /* Implement `va_start' for varargs and stdarg. We look at the
2779 current function to fill in an initial va_list. */
2782 xtensa_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
2790 arg_words
= crtl
->args
.info
.arg_words
;
2792 f_stk
= TYPE_FIELDS (va_list_type_node
);
2793 f_reg
= DECL_CHAIN (f_stk
);
2794 f_ndx
= DECL_CHAIN (f_reg
);
2796 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
2797 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), unshare_expr (valist
),
2799 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), unshare_expr (valist
),
2802 /* Call __builtin_saveregs; save the result in __va_reg */
2803 u
= make_tree (sizetype
, expand_builtin_saveregs ());
2804 u
= fold_convert (ptr_type_node
, u
);
2805 t
= build2 (MODIFY_EXPR
, ptr_type_node
, reg
, u
);
2806 TREE_SIDE_EFFECTS (t
) = 1;
2807 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2809 /* Set the __va_stk member to ($arg_ptr - 32). */
2810 u
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
2811 u
= fold_build2 (POINTER_PLUS_EXPR
, ptr_type_node
, u
, size_int (-32));
2812 t
= build2 (MODIFY_EXPR
, ptr_type_node
, stk
, u
);
2813 TREE_SIDE_EFFECTS (t
) = 1;
2814 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2816 /* Set the __va_ndx member. If the first variable argument is on
2817 the stack, adjust __va_ndx by 2 words to account for the extra
2818 alignment offset for __va_stk. */
2819 if (arg_words
>= MAX_ARGS_IN_REGISTERS
)
2821 t
= build2 (MODIFY_EXPR
, integer_type_node
, ndx
,
2822 build_int_cst (integer_type_node
, arg_words
* UNITS_PER_WORD
));
2823 TREE_SIDE_EFFECTS (t
) = 1;
2824 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2828 /* Implement `va_arg'. */
2831 xtensa_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
2832 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
2837 tree type_size
, array
, orig_ndx
, addr
, size
, va_size
, t
;
2838 tree lab_false
, lab_over
, lab_false2
;
2841 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
2843 type
= build_pointer_type (type
);
2845 /* Handle complex values as separate real and imaginary parts. */
2846 if (TREE_CODE (type
) == COMPLEX_TYPE
)
2848 tree real_part
, imag_part
;
2850 real_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
2852 real_part
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
2854 imag_part
= xtensa_gimplify_va_arg_expr (unshare_expr (valist
),
2857 imag_part
= get_initialized_tmp_var (imag_part
, pre_p
, NULL
);
2859 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
2862 f_stk
= TYPE_FIELDS (va_list_type_node
);
2863 f_reg
= DECL_CHAIN (f_stk
);
2864 f_ndx
= DECL_CHAIN (f_reg
);
2866 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
,
2868 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), unshare_expr (valist
),
2870 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), unshare_expr (valist
),
2873 type_size
= size_in_bytes (type
);
2874 va_size
= round_up (type_size
, UNITS_PER_WORD
);
2875 gimplify_expr (&va_size
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
2878 /* First align __va_ndx if necessary for this arg:
2880 orig_ndx = (AP).__va_ndx;
2881 if (__alignof__ (TYPE) > 4 )
2882 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2883 & -__alignof__ (TYPE)); */
2885 orig_ndx
= get_initialized_tmp_var (ndx
, pre_p
, NULL
);
2887 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
2889 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_UNIT
;
2891 t
= build2 (PLUS_EXPR
, integer_type_node
, unshare_expr (orig_ndx
),
2892 build_int_cst (integer_type_node
, align
- 1));
2893 t
= build2 (BIT_AND_EXPR
, integer_type_node
, t
,
2894 build_int_cst (integer_type_node
, -align
));
2895 gimplify_assign (unshare_expr (orig_ndx
), t
, pre_p
);
2899 /* Increment __va_ndx to point past the argument:
2901 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2903 t
= fold_convert (integer_type_node
, va_size
);
2904 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
, t
);
2905 gimplify_assign (unshare_expr (ndx
), t
, pre_p
);
2908 /* Check if the argument is in registers:
2910 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2911 && !must_pass_in_stack (type))
2912 __array = (AP).__va_reg; */
2914 array
= create_tmp_var (ptr_type_node
, NULL
);
2917 if (!targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
2919 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
2920 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
2922 t
= build2 (GT_EXPR
, boolean_type_node
, unshare_expr (ndx
),
2923 build_int_cst (integer_type_node
,
2924 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
2925 t
= build3 (COND_EXPR
, void_type_node
, t
,
2926 build1 (GOTO_EXPR
, void_type_node
, lab_false
),
2928 gimplify_and_add (t
, pre_p
);
2930 gimplify_assign (unshare_expr (array
), reg
, pre_p
);
2932 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
2933 gimplify_and_add (t
, pre_p
);
2935 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
2936 gimplify_and_add (t
, pre_p
);
2940 /* ...otherwise, the argument is on the stack (never split between
2941 registers and the stack -- change __va_ndx if necessary):
2945 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2946 (AP).__va_ndx = 32 + __va_size (TYPE);
2947 __array = (AP).__va_stk;
2950 lab_false2
= create_artificial_label (UNKNOWN_LOCATION
);
2952 t
= build2 (GT_EXPR
, boolean_type_node
, unshare_expr (orig_ndx
),
2953 build_int_cst (integer_type_node
,
2954 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
2955 t
= build3 (COND_EXPR
, void_type_node
, t
,
2956 build1 (GOTO_EXPR
, void_type_node
, lab_false2
),
2958 gimplify_and_add (t
, pre_p
);
2960 t
= size_binop (PLUS_EXPR
, unshare_expr (va_size
), size_int (32));
2961 t
= fold_convert (integer_type_node
, t
);
2962 gimplify_assign (unshare_expr (ndx
), t
, pre_p
);
2964 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false2
);
2965 gimplify_and_add (t
, pre_p
);
2967 gimplify_assign (array
, stk
, pre_p
);
2971 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
2972 gimplify_and_add (t
, pre_p
);
2976 /* Given the base array pointer (__array) and index to the subsequent
2977 argument (__va_ndx), find the address:
2979 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2983 The results are endian-dependent because values smaller than one word
2984 are aligned differently. */
2987 if (BYTES_BIG_ENDIAN
&& TREE_CODE (type_size
) == INTEGER_CST
)
2989 t
= fold_build2 (GE_EXPR
, boolean_type_node
, unshare_expr (type_size
),
2990 size_int (PARM_BOUNDARY
/ BITS_PER_UNIT
));
2991 t
= fold_build3 (COND_EXPR
, sizetype
, t
, unshare_expr (va_size
),
2992 unshare_expr (type_size
));
2996 size
= unshare_expr (va_size
);
2998 t
= fold_convert (sizetype
, unshare_expr (ndx
));
2999 t
= build2 (MINUS_EXPR
, sizetype
, t
, size
);
3000 addr
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, unshare_expr (array
), t
);
3002 addr
= fold_convert (build_pointer_type (type
), addr
);
3004 addr
= build_va_arg_indirect_ref (addr
);
3005 return build_va_arg_indirect_ref (addr
);
3013 XTENSA_BUILTIN_UMULSIDI3
,
3014 XTENSA_BUILTIN_THREAD_POINTER
,
3015 XTENSA_BUILTIN_SET_THREAD_POINTER
,
3021 xtensa_init_builtins (void)
3025 ftype
= build_function_type_list (unsigned_intDI_type_node
,
3026 unsigned_intSI_type_node
,
3027 unsigned_intSI_type_node
, NULL_TREE
);
3029 decl
= add_builtin_function ("__builtin_umulsidi3", ftype
,
3030 XTENSA_BUILTIN_UMULSIDI3
, BUILT_IN_MD
,
3031 "__umulsidi3", NULL_TREE
);
3032 TREE_NOTHROW (decl
) = 1;
3033 TREE_READONLY (decl
) = 1;
3035 if (TARGET_THREADPTR
)
3037 ftype
= build_function_type (ptr_type_node
, void_list_node
);
3038 decl
= add_builtin_function ("__builtin_thread_pointer", ftype
,
3039 XTENSA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
3041 TREE_READONLY (decl
) = 1;
3042 TREE_NOTHROW (decl
) = 1;
3044 ftype
= build_function_type_list (void_type_node
, ptr_type_node
,
3046 decl
= add_builtin_function ("__builtin_set_thread_pointer", ftype
,
3047 XTENSA_BUILTIN_SET_THREAD_POINTER
,
3048 BUILT_IN_MD
, NULL
, NULL_TREE
);
3049 TREE_NOTHROW (decl
) = 1;
3055 xtensa_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
, tree
*args
,
3056 bool ignore ATTRIBUTE_UNUSED
)
3058 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
3063 case XTENSA_BUILTIN_UMULSIDI3
:
3066 if ((TREE_CODE (arg0
) == INTEGER_CST
&& TREE_CODE (arg1
) == INTEGER_CST
)
3067 || TARGET_MUL32_HIGH
)
3068 return fold_build2 (MULT_EXPR
, unsigned_intDI_type_node
,
3069 fold_convert (unsigned_intDI_type_node
, arg0
),
3070 fold_convert (unsigned_intDI_type_node
, arg1
));
3073 case XTENSA_BUILTIN_THREAD_POINTER
:
3074 case XTENSA_BUILTIN_SET_THREAD_POINTER
:
3078 internal_error ("bad builtin code");
3087 xtensa_expand_builtin (tree exp
, rtx target
,
3088 rtx subtarget ATTRIBUTE_UNUSED
,
3089 enum machine_mode mode ATTRIBUTE_UNUSED
,
3092 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
3093 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
3098 case XTENSA_BUILTIN_UMULSIDI3
:
3099 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3100 __umulsidi3 function when the Xtensa configuration can directly
3101 implement it. If not, just call the function. */
3102 return expand_call (exp
, target
, ignore
);
3104 case XTENSA_BUILTIN_THREAD_POINTER
:
3105 if (!target
|| !register_operand (target
, Pmode
))
3106 target
= gen_reg_rtx (Pmode
);
3107 emit_insn (gen_load_tp (target
));
3110 case XTENSA_BUILTIN_SET_THREAD_POINTER
:
3111 arg
= expand_normal (CALL_EXPR_ARG (exp
, 0));
3112 if (!register_operand (arg
, Pmode
))
3113 arg
= copy_to_mode_reg (Pmode
, arg
);
3114 emit_insn (gen_set_tp (arg
));
3118 internal_error ("bad builtin code");
3125 xtensa_preferred_reload_class (rtx x
, enum reg_class rclass
, int isoutput
)
3127 if (!isoutput
&& CONSTANT_P (x
) && GET_CODE (x
) == CONST_DOUBLE
)
3130 /* Don't use the stack pointer or hard frame pointer for reloads!
3131 The hard frame pointer would normally be OK except that it may
3132 briefly hold an incoming argument in the prologue, and reload
3133 won't know that it is live because the hard frame pointer is
3134 treated specially. */
3136 if (rclass
== AR_REGS
|| rclass
== GR_REGS
)
3144 xtensa_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass
,
3145 enum machine_mode mode
, secondary_reload_info
*sri
)
3149 if (in_p
&& constantpool_mem_p (x
))
3151 if (rclass
== FP_REGS
)
3155 sri
->icode
= CODE_FOR_reloadqi_literal
;
3156 else if (mode
== HImode
)
3157 sri
->icode
= CODE_FOR_reloadhi_literal
;
3160 regno
= xt_true_regnum (x
);
3161 if (ACC_REG_P (regno
))
3162 return ((rclass
== GR_REGS
|| rclass
== RL_REGS
) ? NO_REGS
: RL_REGS
);
3163 if (rclass
== ACC_REG
)
3164 return (GP_REG_P (regno
) ? NO_REGS
: RL_REGS
);
3171 order_regs_for_local_alloc (void)
3173 if (!leaf_function_p ())
3175 memcpy (reg_alloc_order
, reg_nonleaf_alloc_order
,
3176 FIRST_PSEUDO_REGISTER
* sizeof (int));
3180 int i
, num_arg_regs
;
3183 /* Use the AR registers in increasing order (skipping a0 and a1)
3184 but save the incoming argument registers for a last resort. */
3185 num_arg_regs
= crtl
->args
.info
.arg_words
;
3186 if (num_arg_regs
> MAX_ARGS_IN_REGISTERS
)
3187 num_arg_regs
= MAX_ARGS_IN_REGISTERS
;
3188 for (i
= GP_ARG_FIRST
; i
< 16 - num_arg_regs
; i
++)
3189 reg_alloc_order
[nxt
++] = i
+ num_arg_regs
;
3190 for (i
= 0; i
< num_arg_regs
; i
++)
3191 reg_alloc_order
[nxt
++] = GP_ARG_FIRST
+ i
;
3193 /* List the coprocessor registers in order. */
3194 for (i
= 0; i
< BR_REG_NUM
; i
++)
3195 reg_alloc_order
[nxt
++] = BR_REG_FIRST
+ i
;
3197 /* List the FP registers in order for now. */
3198 for (i
= 0; i
< 16; i
++)
3199 reg_alloc_order
[nxt
++] = FP_REG_FIRST
+ i
;
3201 /* GCC requires that we list *all* the registers.... */
3202 reg_alloc_order
[nxt
++] = 0; /* a0 = return address */
3203 reg_alloc_order
[nxt
++] = 1; /* a1 = stack pointer */
3204 reg_alloc_order
[nxt
++] = 16; /* pseudo frame pointer */
3205 reg_alloc_order
[nxt
++] = 17; /* pseudo arg pointer */
3207 reg_alloc_order
[nxt
++] = ACC_REG_FIRST
; /* MAC16 accumulator */
3212 /* Some Xtensa targets support multiple bss sections. If the section
3213 name ends with ".bss", add SECTION_BSS to the flags. */
3216 xtensa_multibss_section_type_flags (tree decl
, const char *name
, int reloc
)
3218 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
3221 suffix
= strrchr (name
, '.');
3222 if (suffix
&& strcmp (suffix
, ".bss") == 0)
3224 if (!decl
|| (TREE_CODE (decl
) == VAR_DECL
3225 && DECL_INITIAL (decl
) == NULL_TREE
))
3226 flags
|= SECTION_BSS
; /* @nobits */
3228 warning (0, "only uninitialized variables can be placed in a "
3236 /* The literal pool stays with the function. */
3239 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED
,
3240 rtx x ATTRIBUTE_UNUSED
,
3241 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
3243 return function_section (current_function_decl
);
3247 /* Compute a (partial) cost for rtx X. Return true if the complete
3248 cost has been computed, and false if subexpressions should be
3249 scanned. In either case, *TOTAL contains the cost result. */
3252 xtensa_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
3253 bool speed ATTRIBUTE_UNUSED
)
3261 if (xtensa_simm12b (INTVAL (x
)))
3268 if (xtensa_simm8 (INTVAL (x
))
3269 || xtensa_simm8x256 (INTVAL (x
)))
3276 if (xtensa_mask_immediate (INTVAL (x
)))
3283 if ((INTVAL (x
) == 0) || xtensa_b4const (INTVAL (x
)))
3294 /* No way to tell if X is the 2nd operand so be conservative. */
3297 if (xtensa_simm12b (INTVAL (x
)))
3299 else if (TARGET_CONST16
)
3300 *total
= COSTS_N_INSNS (2);
3309 *total
= COSTS_N_INSNS (2);
3316 *total
= COSTS_N_INSNS (4);
3324 (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
) ? 2 : 1;
3326 if (memory_address_p (GET_MODE (x
), XEXP ((x
), 0)))
3327 *total
= COSTS_N_INSNS (num_words
);
3329 *total
= COSTS_N_INSNS (2*num_words
);
3335 *total
= COSTS_N_INSNS (TARGET_NSA
? 5 : 50);
3339 *total
= COSTS_N_INSNS (TARGET_NSA
? 1 : 50);
3343 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 3 : 2);
3349 if (GET_MODE (x
) == DImode
)
3350 *total
= COSTS_N_INSNS (2);
3352 *total
= COSTS_N_INSNS (1);
3358 if (GET_MODE (x
) == DImode
)
3359 *total
= COSTS_N_INSNS (50);
3361 *total
= COSTS_N_INSNS (1);
3366 enum machine_mode xmode
= GET_MODE (x
);
3367 if (xmode
== SFmode
)
3368 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3369 else if (xmode
== DFmode
)
3370 *total
= COSTS_N_INSNS (50);
3372 *total
= COSTS_N_INSNS (4);
3379 enum machine_mode xmode
= GET_MODE (x
);
3380 if (xmode
== SFmode
)
3381 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3382 else if (xmode
== DFmode
|| xmode
== DImode
)
3383 *total
= COSTS_N_INSNS (50);
3385 *total
= COSTS_N_INSNS (1);
3390 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 4 : 2);
3395 enum machine_mode xmode
= GET_MODE (x
);
3396 if (xmode
== SFmode
)
3397 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 4 : 50);
3398 else if (xmode
== DFmode
)
3399 *total
= COSTS_N_INSNS (50);
3400 else if (xmode
== DImode
)
3401 *total
= COSTS_N_INSNS (TARGET_MUL32_HIGH
? 10 : 50);
3402 else if (TARGET_MUL32
)
3403 *total
= COSTS_N_INSNS (4);
3404 else if (TARGET_MAC16
)
3405 *total
= COSTS_N_INSNS (16);
3406 else if (TARGET_MUL16
)
3407 *total
= COSTS_N_INSNS (12);
3409 *total
= COSTS_N_INSNS (50);
3416 enum machine_mode xmode
= GET_MODE (x
);
3417 if (xmode
== SFmode
)
3419 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV
? 8 : 50);
3422 else if (xmode
== DFmode
)
3424 *total
= COSTS_N_INSNS (50);
3433 enum machine_mode xmode
= GET_MODE (x
);
3434 if (xmode
== DImode
)
3435 *total
= COSTS_N_INSNS (50);
3436 else if (TARGET_DIV32
)
3437 *total
= COSTS_N_INSNS (32);
3439 *total
= COSTS_N_INSNS (50);
3444 if (GET_MODE (x
) == SFmode
)
3445 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT
? 8 : 50);
3447 *total
= COSTS_N_INSNS (50);
3454 *total
= COSTS_N_INSNS (TARGET_MINMAX
? 1 : 50);
3459 *total
= COSTS_N_INSNS (TARGET_SEXT
? 1 : 2);
3464 *total
= COSTS_N_INSNS (1);
3472 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3475 xtensa_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3477 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)
3478 > 4 * UNITS_PER_WORD
);
3481 /* Worker function for TARGET_FUNCTION_VALUE. */
3484 xtensa_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
3487 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype
)
3488 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
3489 ? SImode
: TYPE_MODE (valtype
),
3490 outgoing
? GP_OUTGOING_RETURN
: GP_RETURN
);
3493 /* The static chain is passed in memory. Provide rtx giving 'mem'
3494 expressions that denote where they are stored. */
3497 xtensa_static_chain (const_tree
ARG_UNUSED (fndecl
), bool incoming_p
)
3499 rtx base
= incoming_p
? arg_pointer_rtx
: stack_pointer_rtx
;
3500 return gen_frame_mem (Pmode
, plus_constant (base
, -5 * UNITS_PER_WORD
));
3504 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3505 instruction with a minimal stack frame in order to get some free
3506 registers. Once the actual call target is known, the proper stack frame
3507 size is extracted from the ENTRY instruction at the target and the
3508 current frame is adjusted to match. The trampoline then transfers
3509 control to the instruction following the ENTRY at the target. Note:
3510 this assumes that the target begins with an ENTRY instruction. */
3513 xtensa_asm_trampoline_template (FILE *stream
)
3515 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3517 fprintf (stream
, "\t.begin no-transform\n");
3518 fprintf (stream
, "\tentry\tsp, %d\n", MIN_FRAME_SIZE
);
3522 /* Save the return address. */
3523 fprintf (stream
, "\tmov\ta10, a0\n");
3525 /* Use a CALL0 instruction to skip past the constants and in the
3526 process get the PC into A0. This allows PC-relative access to
3527 the constants without relying on L32R. */
3528 fprintf (stream
, "\tcall0\t.Lskipconsts\n");
3531 fprintf (stream
, "\tj\t.Lskipconsts\n");
3533 fprintf (stream
, "\t.align\t4\n");
3534 fprintf (stream
, ".Lchainval:%s0\n", integer_asm_op (4, TRUE
));
3535 fprintf (stream
, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE
));
3536 fprintf (stream
, ".Lskipconsts:\n");
3538 /* Load the static chain and function address from the trampoline. */
3541 fprintf (stream
, "\taddi\ta0, a0, 3\n");
3542 fprintf (stream
, "\tl32i\ta9, a0, 0\n");
3543 fprintf (stream
, "\tl32i\ta8, a0, 4\n");
3547 fprintf (stream
, "\tl32r\ta9, .Lchainval\n");
3548 fprintf (stream
, "\tl32r\ta8, .Lfnaddr\n");
3551 /* Store the static chain. */
3552 fprintf (stream
, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE
- 20);
3554 /* Set the proper stack pointer value. */
3555 fprintf (stream
, "\tl32i\ta9, a8, 0\n");
3556 fprintf (stream
, "\textui\ta9, a9, %d, 12\n",
3557 TARGET_BIG_ENDIAN
? 8 : 12);
3558 fprintf (stream
, "\tslli\ta9, a9, 3\n");
3559 fprintf (stream
, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE
);
3560 fprintf (stream
, "\tsub\ta9, sp, a9\n");
3561 fprintf (stream
, "\tmovsp\tsp, a9\n");
3564 /* Restore the return address. */
3565 fprintf (stream
, "\tmov\ta0, a10\n");
3567 /* Jump to the instruction following the ENTRY. */
3568 fprintf (stream
, "\taddi\ta8, a8, 3\n");
3569 fprintf (stream
, "\tjx\ta8\n");
3571 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3573 fprintf (stream
, "\t.byte\t0\n");
3575 fprintf (stream
, "\tnop\n");
3577 fprintf (stream
, "\t.end no-transform\n");
3581 xtensa_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain
)
3583 rtx func
= XEXP (DECL_RTL (fndecl
), 0);
3584 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3585 int chain_off
= use_call0
? 12 : 8;
3586 int func_off
= use_call0
? 16 : 12;
3588 emit_block_move (m_tramp
, assemble_trampoline_template (),
3589 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
3591 emit_move_insn (adjust_address (m_tramp
, SImode
, chain_off
), chain
);
3592 emit_move_insn (adjust_address (m_tramp
, SImode
, func_off
), func
);
3593 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_sync_caches"),
3594 0, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
3598 #include "gt-xtensa.h"