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xtensa-config.h (XCHAL_HAVE_THREADPTR): New.
[gcc.git] / gcc / config / xtensa / xtensa.c
1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
11 version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "tm.h"
27 #include "rtl.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "basic-block.h"
31 #include "real.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-flags.h"
35 #include "insn-attr.h"
36 #include "insn-codes.h"
37 #include "recog.h"
38 #include "output.h"
39 #include "tree.h"
40 #include "expr.h"
41 #include "flags.h"
42 #include "reload.h"
43 #include "tm_p.h"
44 #include "function.h"
45 #include "toplev.h"
46 #include "optabs.h"
47 #include "libfuncs.h"
48 #include "ggc.h"
49 #include "target.h"
50 #include "target-def.h"
51 #include "langhooks.h"
52 #include "tree-gimple.h"
53 #include "df.h"
54
55
56 /* Enumeration for all of the relational tests, so that we can build
57 arrays indexed by the test type, and not worry about the order
58 of EQ, NE, etc. */
59
60 enum internal_test
61 {
62 ITEST_EQ,
63 ITEST_NE,
64 ITEST_GT,
65 ITEST_GE,
66 ITEST_LT,
67 ITEST_LE,
68 ITEST_GTU,
69 ITEST_GEU,
70 ITEST_LTU,
71 ITEST_LEU,
72 ITEST_MAX
73 };
74
75 /* Cached operands, and operator to compare for use in set/branch on
76 condition codes. */
77 rtx branch_cmp[2];
78
79 /* what type of branch to use */
80 enum cmp_type branch_type;
81
82 /* Array giving truth value on whether or not a given hard register
83 can support a given mode. */
84 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
85
86 /* Current frame size calculated by compute_frame_size. */
87 unsigned xtensa_current_frame_size;
88
89 /* Largest block move to handle in-line. */
90 #define LARGEST_MOVE_RATIO 15
91
92 /* Define the structure for the machine field in struct function. */
93 struct machine_function GTY(())
94 {
95 int accesses_prev_frame;
96 bool need_a7_copy;
97 bool vararg_a7;
98 rtx set_frame_ptr_insn;
99 };
100
101 /* Vector, indexed by hard register number, which contains 1 for a
102 register that is allowable in a candidate for leaf function
103 treatment. */
104
105 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
106 {
107 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
108 1, 1, 1,
109 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
110 1
111 };
112
113 /* Map hard register number to register class */
114 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
115 {
116 RL_REGS, SP_REG, RL_REGS, RL_REGS,
117 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
118 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
119 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
120 AR_REGS, AR_REGS, BR_REGS,
121 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
122 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
123 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
124 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
125 ACC_REG,
126 };
127
128 static enum internal_test map_test_to_internal_test (enum rtx_code);
129 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
130 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
131 static rtx gen_conditional_move (rtx);
132 static rtx fixup_subreg_mem (rtx);
133 static struct machine_function * xtensa_init_machine_status (void);
134 static bool xtensa_return_in_msb (tree);
135 static void printx (FILE *, signed int);
136 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
137 static rtx xtensa_builtin_saveregs (void);
138 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
139 int) ATTRIBUTE_UNUSED;
140 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
141 unsigned HOST_WIDE_INT);
142 static bool xtensa_rtx_costs (rtx, int, int, int *);
143 static tree xtensa_build_builtin_va_list (void);
144 static bool xtensa_return_in_memory (tree, tree);
145 static tree xtensa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
146 static void xtensa_init_builtins (void);
147 static tree xtensa_fold_builtin (tree, tree, bool);
148 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
149
150 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
151 REG_ALLOC_ORDER;
152 \f
153
154 /* This macro generates the assembly code for function exit,
155 on machines that need it. If FUNCTION_EPILOGUE is not defined
156 then individual return instructions are generated for each
157 return statement. Args are same as for FUNCTION_PROLOGUE. */
158
159 #undef TARGET_ASM_FUNCTION_EPILOGUE
160 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
161
162 /* These hooks specify assembly directives for creating certain kinds
163 of integer object. */
164
165 #undef TARGET_ASM_ALIGNED_SI_OP
166 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
167
168 #undef TARGET_ASM_SELECT_RTX_SECTION
169 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
170
171 #undef TARGET_DEFAULT_TARGET_FLAGS
172 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
173
174 #undef TARGET_RTX_COSTS
175 #define TARGET_RTX_COSTS xtensa_rtx_costs
176 #undef TARGET_ADDRESS_COST
177 #define TARGET_ADDRESS_COST hook_int_rtx_0
178
179 #undef TARGET_BUILD_BUILTIN_VA_LIST
180 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
181
182 #undef TARGET_PROMOTE_FUNCTION_ARGS
183 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
184 #undef TARGET_PROMOTE_FUNCTION_RETURN
185 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
186 #undef TARGET_PROMOTE_PROTOTYPES
187 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
188
189 #undef TARGET_RETURN_IN_MEMORY
190 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
191 #undef TARGET_SPLIT_COMPLEX_ARG
192 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
193 #undef TARGET_MUST_PASS_IN_STACK
194 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
195
196 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
197 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
198 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
199 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
200
201 #undef TARGET_RETURN_IN_MSB
202 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
203
204 #undef TARGET_INIT_BUILTINS
205 #define TARGET_INIT_BUILTINS xtensa_init_builtins
206 #undef TARGET_FOLD_BUILTIN
207 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
208 #undef TARGET_EXPAND_BUILTIN
209 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
210
211 struct gcc_target targetm = TARGET_INITIALIZER;
212
213 \f
214 /* Functions to test Xtensa immediate operand validity. */
215
216 bool
217 xtensa_simm8 (HOST_WIDE_INT v)
218 {
219 return v >= -128 && v <= 127;
220 }
221
222
223 bool
224 xtensa_simm8x256 (HOST_WIDE_INT v)
225 {
226 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
227 }
228
229
230 bool
231 xtensa_simm12b (HOST_WIDE_INT v)
232 {
233 return v >= -2048 && v <= 2047;
234 }
235
236
237 static bool
238 xtensa_uimm8 (HOST_WIDE_INT v)
239 {
240 return v >= 0 && v <= 255;
241 }
242
243
244 static bool
245 xtensa_uimm8x2 (HOST_WIDE_INT v)
246 {
247 return (v & 1) == 0 && (v >= 0 && v <= 510);
248 }
249
250
251 static bool
252 xtensa_uimm8x4 (HOST_WIDE_INT v)
253 {
254 return (v & 3) == 0 && (v >= 0 && v <= 1020);
255 }
256
257
258 static bool
259 xtensa_b4const (HOST_WIDE_INT v)
260 {
261 switch (v)
262 {
263 case -1:
264 case 1:
265 case 2:
266 case 3:
267 case 4:
268 case 5:
269 case 6:
270 case 7:
271 case 8:
272 case 10:
273 case 12:
274 case 16:
275 case 32:
276 case 64:
277 case 128:
278 case 256:
279 return true;
280 }
281 return false;
282 }
283
284
285 bool
286 xtensa_b4const_or_zero (HOST_WIDE_INT v)
287 {
288 if (v == 0)
289 return true;
290 return xtensa_b4const (v);
291 }
292
293
294 bool
295 xtensa_b4constu (HOST_WIDE_INT v)
296 {
297 switch (v)
298 {
299 case 32768:
300 case 65536:
301 case 2:
302 case 3:
303 case 4:
304 case 5:
305 case 6:
306 case 7:
307 case 8:
308 case 10:
309 case 12:
310 case 16:
311 case 32:
312 case 64:
313 case 128:
314 case 256:
315 return true;
316 }
317 return false;
318 }
319
320
321 bool
322 xtensa_mask_immediate (HOST_WIDE_INT v)
323 {
324 #define MAX_MASK_SIZE 16
325 int mask_size;
326
327 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
328 {
329 if ((v & 1) == 0)
330 return false;
331 v = v >> 1;
332 if (v == 0)
333 return true;
334 }
335
336 return false;
337 }
338
339
340 /* This is just like the standard true_regnum() function except that it
341 works even when reg_renumber is not initialized. */
342
343 int
344 xt_true_regnum (rtx x)
345 {
346 if (GET_CODE (x) == REG)
347 {
348 if (reg_renumber
349 && REGNO (x) >= FIRST_PSEUDO_REGISTER
350 && reg_renumber[REGNO (x)] >= 0)
351 return reg_renumber[REGNO (x)];
352 return REGNO (x);
353 }
354 if (GET_CODE (x) == SUBREG)
355 {
356 int base = xt_true_regnum (SUBREG_REG (x));
357 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
358 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
359 GET_MODE (SUBREG_REG (x)),
360 SUBREG_BYTE (x), GET_MODE (x));
361 }
362 return -1;
363 }
364
365
366 int
367 xtensa_valid_move (enum machine_mode mode, rtx *operands)
368 {
369 /* Either the destination or source must be a register, and the
370 MAC16 accumulator doesn't count. */
371
372 if (register_operand (operands[0], mode))
373 {
374 int dst_regnum = xt_true_regnum (operands[0]);
375
376 /* The stack pointer can only be assigned with a MOVSP opcode. */
377 if (dst_regnum == STACK_POINTER_REGNUM)
378 return (mode == SImode
379 && register_operand (operands[1], mode)
380 && !ACC_REG_P (xt_true_regnum (operands[1])));
381
382 if (!ACC_REG_P (dst_regnum))
383 return true;
384 }
385 if (register_operand (operands[1], mode))
386 {
387 int src_regnum = xt_true_regnum (operands[1]);
388 if (!ACC_REG_P (src_regnum))
389 return true;
390 }
391 return FALSE;
392 }
393
394
395 int
396 smalloffset_mem_p (rtx op)
397 {
398 if (GET_CODE (op) == MEM)
399 {
400 rtx addr = XEXP (op, 0);
401 if (GET_CODE (addr) == REG)
402 return BASE_REG_P (addr, 0);
403 if (GET_CODE (addr) == PLUS)
404 {
405 rtx offset = XEXP (addr, 0);
406 HOST_WIDE_INT val;
407 if (GET_CODE (offset) != CONST_INT)
408 offset = XEXP (addr, 1);
409 if (GET_CODE (offset) != CONST_INT)
410 return FALSE;
411
412 val = INTVAL (offset);
413 return (val & 3) == 0 && (val >= 0 && val <= 60);
414 }
415 }
416 return FALSE;
417 }
418
419
420 int
421 constantpool_address_p (rtx addr)
422 {
423 rtx sym = addr;
424
425 if (GET_CODE (addr) == CONST)
426 {
427 rtx offset;
428
429 /* Only handle (PLUS (SYM, OFFSET)) form. */
430 addr = XEXP (addr, 0);
431 if (GET_CODE (addr) != PLUS)
432 return FALSE;
433
434 /* Make sure the address is word aligned. */
435 offset = XEXP (addr, 1);
436 if ((GET_CODE (offset) != CONST_INT)
437 || ((INTVAL (offset) & 3) != 0))
438 return FALSE;
439
440 sym = XEXP (addr, 0);
441 }
442
443 if ((GET_CODE (sym) == SYMBOL_REF)
444 && CONSTANT_POOL_ADDRESS_P (sym))
445 return TRUE;
446 return FALSE;
447 }
448
449
450 int
451 constantpool_mem_p (rtx op)
452 {
453 if (GET_CODE (op) == SUBREG)
454 op = SUBREG_REG (op);
455 if (GET_CODE (op) == MEM)
456 return constantpool_address_p (XEXP (op, 0));
457 return FALSE;
458 }
459
460
461 void
462 xtensa_extend_reg (rtx dst, rtx src)
463 {
464 rtx temp = gen_reg_rtx (SImode);
465 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
466
467 /* Generate paradoxical subregs as needed so that the modes match. */
468 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
469 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
470
471 emit_insn (gen_ashlsi3 (temp, src, shift));
472 emit_insn (gen_ashrsi3 (dst, temp, shift));
473 }
474
475
476 bool
477 xtensa_mem_offset (unsigned v, enum machine_mode mode)
478 {
479 switch (mode)
480 {
481 case BLKmode:
482 /* Handle the worst case for block moves. See xtensa_expand_block_move
483 where we emit an optimized block move operation if the block can be
484 moved in < "move_ratio" pieces. The worst case is when the block is
485 aligned but has a size of (3 mod 4) (does this happen?) so that the
486 last piece requires a byte load/store. */
487 return (xtensa_uimm8 (v)
488 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
489
490 case QImode:
491 return xtensa_uimm8 (v);
492
493 case HImode:
494 return xtensa_uimm8x2 (v);
495
496 case DFmode:
497 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
498
499 default:
500 break;
501 }
502
503 return xtensa_uimm8x4 (v);
504 }
505
506
507 /* Make normal rtx_code into something we can index from an array. */
508
509 static enum internal_test
510 map_test_to_internal_test (enum rtx_code test_code)
511 {
512 enum internal_test test = ITEST_MAX;
513
514 switch (test_code)
515 {
516 default: break;
517 case EQ: test = ITEST_EQ; break;
518 case NE: test = ITEST_NE; break;
519 case GT: test = ITEST_GT; break;
520 case GE: test = ITEST_GE; break;
521 case LT: test = ITEST_LT; break;
522 case LE: test = ITEST_LE; break;
523 case GTU: test = ITEST_GTU; break;
524 case GEU: test = ITEST_GEU; break;
525 case LTU: test = ITEST_LTU; break;
526 case LEU: test = ITEST_LEU; break;
527 }
528
529 return test;
530 }
531
532
533 /* Generate the code to compare two integer values. The return value is
534 the comparison expression. */
535
536 static rtx
537 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
538 rtx cmp0, /* first operand to compare */
539 rtx cmp1, /* second operand to compare */
540 int *p_invert /* whether branch needs to reverse test */)
541 {
542 struct cmp_info
543 {
544 enum rtx_code test_code; /* test code to use in insn */
545 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
546 int const_add; /* constant to add (convert LE -> LT) */
547 int reverse_regs; /* reverse registers in test */
548 int invert_const; /* != 0 if invert value if cmp1 is constant */
549 int invert_reg; /* != 0 if invert value if cmp1 is register */
550 int unsignedp; /* != 0 for unsigned comparisons. */
551 };
552
553 static struct cmp_info info[ (int)ITEST_MAX ] = {
554
555 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
556 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
557
558 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
559 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
560 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
561 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
562
563 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
564 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
565 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
566 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
567 };
568
569 enum internal_test test;
570 enum machine_mode mode;
571 struct cmp_info *p_info;
572
573 test = map_test_to_internal_test (test_code);
574 gcc_assert (test != ITEST_MAX);
575
576 p_info = &info[ (int)test ];
577
578 mode = GET_MODE (cmp0);
579 if (mode == VOIDmode)
580 mode = GET_MODE (cmp1);
581
582 /* Make sure we can handle any constants given to us. */
583 if (GET_CODE (cmp1) == CONST_INT)
584 {
585 HOST_WIDE_INT value = INTVAL (cmp1);
586 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
587
588 /* if the immediate overflows or does not fit in the immediate field,
589 spill it to a register */
590
591 if ((p_info->unsignedp ?
592 (uvalue + p_info->const_add > uvalue) :
593 (value + p_info->const_add > value)) != (p_info->const_add > 0))
594 {
595 cmp1 = force_reg (mode, cmp1);
596 }
597 else if (!(p_info->const_range_p) (value + p_info->const_add))
598 {
599 cmp1 = force_reg (mode, cmp1);
600 }
601 }
602 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
603 {
604 cmp1 = force_reg (mode, cmp1);
605 }
606
607 /* See if we need to invert the result. */
608 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
609 ? p_info->invert_const
610 : p_info->invert_reg);
611
612 /* Comparison to constants, may involve adding 1 to change a LT into LE.
613 Comparison between two registers, may involve switching operands. */
614 if (GET_CODE (cmp1) == CONST_INT)
615 {
616 if (p_info->const_add != 0)
617 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
618
619 }
620 else if (p_info->reverse_regs)
621 {
622 rtx temp = cmp0;
623 cmp0 = cmp1;
624 cmp1 = temp;
625 }
626
627 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
628 }
629
630
631 /* Generate the code to compare two float values. The return value is
632 the comparison expression. */
633
634 static rtx
635 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
636 rtx cmp0, /* first operand to compare */
637 rtx cmp1 /* second operand to compare */)
638 {
639 rtx (*gen_fn) (rtx, rtx, rtx);
640 rtx brtmp;
641 int reverse_regs, invert;
642
643 switch (test_code)
644 {
645 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
646 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
647 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
648 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
649 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
650 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
651 default:
652 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
653 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
654 }
655
656 if (reverse_regs)
657 {
658 rtx temp = cmp0;
659 cmp0 = cmp1;
660 cmp1 = temp;
661 }
662
663 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
664 emit_insn (gen_fn (brtmp, cmp0, cmp1));
665
666 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
667 }
668
669
670 void
671 xtensa_expand_conditional_branch (rtx *operands, enum rtx_code test_code)
672 {
673 enum cmp_type type = branch_type;
674 rtx cmp0 = branch_cmp[0];
675 rtx cmp1 = branch_cmp[1];
676 rtx cmp;
677 int invert;
678 rtx label1, label2;
679
680 switch (type)
681 {
682 case CMP_DF:
683 default:
684 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
685
686 case CMP_SI:
687 invert = FALSE;
688 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
689 break;
690
691 case CMP_SF:
692 if (!TARGET_HARD_FLOAT)
693 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
694 cmp0, cmp1));
695 invert = FALSE;
696 cmp = gen_float_relational (test_code, cmp0, cmp1);
697 break;
698 }
699
700 /* Generate the branch. */
701
702 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
703 label2 = pc_rtx;
704
705 if (invert)
706 {
707 label2 = label1;
708 label1 = pc_rtx;
709 }
710
711 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
712 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
713 label1,
714 label2)));
715 }
716
717
718 static rtx
719 gen_conditional_move (rtx cmp)
720 {
721 enum rtx_code code = GET_CODE (cmp);
722 rtx op0 = branch_cmp[0];
723 rtx op1 = branch_cmp[1];
724
725 if (branch_type == CMP_SI)
726 {
727 /* Jump optimization calls get_condition() which canonicalizes
728 comparisons like (GE x <const>) to (GT x <const-1>).
729 Transform those comparisons back to GE, since that is the
730 comparison supported in Xtensa. We shouldn't have to
731 transform <LE x const> comparisons, because neither
732 xtensa_expand_conditional_branch() nor get_condition() will
733 produce them. */
734
735 if ((code == GT) && (op1 == constm1_rtx))
736 {
737 code = GE;
738 op1 = const0_rtx;
739 }
740 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
741
742 if (boolean_operator (cmp, VOIDmode))
743 {
744 /* Swap the operands to make const0 second. */
745 if (op0 == const0_rtx)
746 {
747 op0 = op1;
748 op1 = const0_rtx;
749 }
750
751 /* If not comparing against zero, emit a comparison (subtract). */
752 if (op1 != const0_rtx)
753 {
754 op0 = expand_binop (SImode, sub_optab, op0, op1,
755 0, 0, OPTAB_LIB_WIDEN);
756 op1 = const0_rtx;
757 }
758 }
759 else if (branch_operator (cmp, VOIDmode))
760 {
761 /* Swap the operands to make const0 second. */
762 if (op0 == const0_rtx)
763 {
764 op0 = op1;
765 op1 = const0_rtx;
766
767 switch (code)
768 {
769 case LT: code = GE; break;
770 case GE: code = LT; break;
771 default: gcc_unreachable ();
772 }
773 }
774
775 if (op1 != const0_rtx)
776 return 0;
777 }
778 else
779 return 0;
780
781 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
782 }
783
784 if (TARGET_HARD_FLOAT && (branch_type == CMP_SF))
785 return gen_float_relational (code, op0, op1);
786
787 return 0;
788 }
789
790
791 int
792 xtensa_expand_conditional_move (rtx *operands, int isflt)
793 {
794 rtx cmp;
795 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
796
797 if (!(cmp = gen_conditional_move (operands[1])))
798 return 0;
799
800 if (isflt)
801 gen_fn = (branch_type == CMP_SI
802 ? gen_movsfcc_internal0
803 : gen_movsfcc_internal1);
804 else
805 gen_fn = (branch_type == CMP_SI
806 ? gen_movsicc_internal0
807 : gen_movsicc_internal1);
808
809 emit_insn (gen_fn (operands[0], XEXP (cmp, 0),
810 operands[2], operands[3], cmp));
811 return 1;
812 }
813
814
815 int
816 xtensa_expand_scc (rtx *operands)
817 {
818 rtx dest = operands[0];
819 rtx cmp = operands[1];
820 rtx one_tmp, zero_tmp;
821 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
822
823 if (!(cmp = gen_conditional_move (cmp)))
824 return 0;
825
826 one_tmp = gen_reg_rtx (SImode);
827 zero_tmp = gen_reg_rtx (SImode);
828 emit_insn (gen_movsi (one_tmp, const_true_rtx));
829 emit_insn (gen_movsi (zero_tmp, const0_rtx));
830
831 gen_fn = (branch_type == CMP_SI
832 ? gen_movsicc_internal0
833 : gen_movsicc_internal1);
834 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
835 return 1;
836 }
837
838
839 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
840 for the output, i.e., the input operands are twice as big as MODE. */
841
842 void
843 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
844 {
845 switch (GET_CODE (operands[1]))
846 {
847 case REG:
848 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
849 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
850 break;
851
852 case MEM:
853 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
854 operands[2] = adjust_address (operands[1], mode, 0);
855 break;
856
857 case CONST_INT:
858 case CONST_DOUBLE:
859 split_double (operands[1], &operands[2], &operands[3]);
860 break;
861
862 default:
863 gcc_unreachable ();
864 }
865
866 switch (GET_CODE (operands[0]))
867 {
868 case REG:
869 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
870 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
871 break;
872
873 case MEM:
874 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
875 operands[0] = adjust_address (operands[0], mode, 0);
876 break;
877
878 default:
879 gcc_unreachable ();
880 }
881 }
882
883
884 /* Emit insns to move operands[1] into operands[0].
885 Return 1 if we have written out everything that needs to be done to
886 do the move. Otherwise, return 0 and the caller will emit the move
887 normally. */
888
889 int
890 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
891 {
892 if (CONSTANT_P (operands[1])
893 && (GET_CODE (operands[1]) != CONST_INT
894 || !xtensa_simm12b (INTVAL (operands[1]))))
895 {
896 if (!TARGET_CONST16)
897 operands[1] = force_const_mem (SImode, operands[1]);
898
899 /* PC-relative loads are always SImode, and CONST16 is only
900 supported in the movsi pattern, so add a SUBREG for any other
901 (smaller) mode. */
902
903 if (mode != SImode)
904 {
905 if (register_operand (operands[0], mode))
906 {
907 operands[0] = simplify_gen_subreg (SImode, operands[0], mode, 0);
908 emit_move_insn (operands[0], operands[1]);
909 return 1;
910 }
911 else
912 {
913 operands[1] = force_reg (SImode, operands[1]);
914 operands[1] = gen_lowpart_SUBREG (mode, operands[1]);
915 }
916 }
917 }
918
919 if (!(reload_in_progress | reload_completed)
920 && !xtensa_valid_move (mode, operands))
921 operands[1] = force_reg (mode, operands[1]);
922
923 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
924
925 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
926 instruction won't be recognized after reload, so we remove the
927 subreg and adjust mem accordingly. */
928 if (reload_in_progress)
929 {
930 operands[0] = fixup_subreg_mem (operands[0]);
931 operands[1] = fixup_subreg_mem (operands[1]);
932 }
933 return 0;
934 }
935
936
937 static rtx
938 fixup_subreg_mem (rtx x)
939 {
940 if (GET_CODE (x) == SUBREG
941 && GET_CODE (SUBREG_REG (x)) == REG
942 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
943 {
944 rtx temp =
945 gen_rtx_SUBREG (GET_MODE (x),
946 reg_equiv_mem [REGNO (SUBREG_REG (x))],
947 SUBREG_BYTE (x));
948 x = alter_subreg (&temp);
949 }
950 return x;
951 }
952
953
954 /* Check if an incoming argument in a7 is expected to be used soon and
955 if OPND is a register or register pair that includes a7. If so,
956 create a new pseudo and copy a7 into that pseudo at the very
957 beginning of the function, followed by the special "set_frame_ptr"
958 unspec_volatile insn. The return value is either the original
959 operand, if it is not a7, or the new pseudo containing a copy of
960 the incoming argument. This is necessary because the register
961 allocator will ignore conflicts with a7 and may either assign some
962 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
963 the incoming argument in a7. By copying the argument out of a7 as
964 the very first thing, and then immediately following that with an
965 unspec_volatile to keep the scheduler away, we should avoid any
966 problems. Putting the set_frame_ptr insn at the beginning, with
967 only the a7 copy before it, also makes it easier for the prologue
968 expander to initialize the frame pointer after the a7 copy and to
969 fix up the a7 copy to use the stack pointer instead of the frame
970 pointer. */
971
972 rtx
973 xtensa_copy_incoming_a7 (rtx opnd)
974 {
975 rtx entry_insns = 0;
976 rtx reg, tmp;
977 enum machine_mode mode;
978
979 if (!cfun->machine->need_a7_copy)
980 return opnd;
981
982 /* This function should never be called again once a7 has been copied. */
983 gcc_assert (!cfun->machine->set_frame_ptr_insn);
984
985 mode = GET_MODE (opnd);
986
987 /* The operand using a7 may come in a later instruction, so just return
988 the original operand if it doesn't use a7. */
989 reg = opnd;
990 if (GET_CODE (reg) == SUBREG)
991 {
992 gcc_assert (SUBREG_BYTE (reg) == 0);
993 reg = SUBREG_REG (reg);
994 }
995 if (GET_CODE (reg) != REG
996 || REGNO (reg) > A7_REG
997 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
998 return opnd;
999
1000 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1001 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1002
1003 cfun->machine->need_a7_copy = false;
1004
1005 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1006 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1007
1008 push_to_sequence (entry_insns);
1009 tmp = gen_reg_rtx (mode);
1010
1011 switch (mode)
1012 {
1013 case DFmode:
1014 case DImode:
1015 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1016 gen_rtx_REG (SImode, A7_REG - 1)));
1017 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1018 gen_raw_REG (SImode, A7_REG)));
1019 break;
1020 case SFmode:
1021 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1022 break;
1023 case SImode:
1024 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1025 break;
1026 case HImode:
1027 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1028 break;
1029 case QImode:
1030 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1031 break;
1032 default:
1033 gcc_unreachable ();
1034 }
1035
1036 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1037 entry_insns = get_insns ();
1038 end_sequence ();
1039
1040 if (cfun->machine->vararg_a7)
1041 {
1042 /* This is called from within builtin_savereg, so we're already
1043 inside a start_sequence that will be placed at the start of
1044 the function. */
1045 emit_insn (entry_insns);
1046 }
1047 else
1048 {
1049 /* Put entry_insns after the NOTE that starts the function. If
1050 this is inside a start_sequence, make the outer-level insn
1051 chain current, so the code is placed at the start of the
1052 function. */
1053 push_topmost_sequence ();
1054 emit_insn_after (entry_insns, get_insns ());
1055 pop_topmost_sequence ();
1056 }
1057
1058 return tmp;
1059 }
1060
1061
1062 /* Try to expand a block move operation to a sequence of RTL move
1063 instructions. If not optimizing, or if the block size is not a
1064 constant, or if the block is too large, the expansion fails and GCC
1065 falls back to calling memcpy().
1066
1067 operands[0] is the destination
1068 operands[1] is the source
1069 operands[2] is the length
1070 operands[3] is the alignment */
1071
1072 int
1073 xtensa_expand_block_move (rtx *operands)
1074 {
1075 static const enum machine_mode mode_from_align[] =
1076 {
1077 VOIDmode, QImode, HImode, VOIDmode, SImode,
1078 };
1079
1080 rtx dst_mem = operands[0];
1081 rtx src_mem = operands[1];
1082 HOST_WIDE_INT bytes, align;
1083 int num_pieces, move_ratio;
1084 rtx temp[2];
1085 enum machine_mode mode[2];
1086 int amount[2];
1087 bool active[2];
1088 int phase = 0;
1089 int next;
1090 int offset_ld = 0;
1091 int offset_st = 0;
1092 rtx x;
1093
1094 /* If this is not a fixed size move, just call memcpy. */
1095 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1096 return 0;
1097
1098 bytes = INTVAL (operands[2]);
1099 align = INTVAL (operands[3]);
1100
1101 /* Anything to move? */
1102 if (bytes <= 0)
1103 return 0;
1104
1105 if (align > MOVE_MAX)
1106 align = MOVE_MAX;
1107
1108 /* Decide whether to expand inline based on the optimization level. */
1109 move_ratio = 4;
1110 if (optimize > 2)
1111 move_ratio = LARGEST_MOVE_RATIO;
1112 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1113 if (num_pieces > move_ratio)
1114 return 0;
1115
1116 x = XEXP (dst_mem, 0);
1117 if (!REG_P (x))
1118 {
1119 x = force_reg (Pmode, x);
1120 dst_mem = replace_equiv_address (dst_mem, x);
1121 }
1122
1123 x = XEXP (src_mem, 0);
1124 if (!REG_P (x))
1125 {
1126 x = force_reg (Pmode, x);
1127 src_mem = replace_equiv_address (src_mem, x);
1128 }
1129
1130 active[0] = active[1] = false;
1131
1132 do
1133 {
1134 next = phase;
1135 phase ^= 1;
1136
1137 if (bytes > 0)
1138 {
1139 int next_amount;
1140
1141 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1142 next_amount = MIN (next_amount, align);
1143
1144 amount[next] = next_amount;
1145 mode[next] = mode_from_align[next_amount];
1146 temp[next] = gen_reg_rtx (mode[next]);
1147
1148 x = adjust_address (src_mem, mode[next], offset_ld);
1149 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1150
1151 offset_ld += next_amount;
1152 bytes -= next_amount;
1153 active[next] = true;
1154 }
1155
1156 if (active[phase])
1157 {
1158 active[phase] = false;
1159
1160 x = adjust_address (dst_mem, mode[phase], offset_st);
1161 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1162
1163 offset_st += amount[phase];
1164 }
1165 }
1166 while (active[next]);
1167
1168 return 1;
1169 }
1170
1171
1172 void
1173 xtensa_expand_nonlocal_goto (rtx *operands)
1174 {
1175 rtx goto_handler = operands[1];
1176 rtx containing_fp = operands[3];
1177
1178 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1179 is too big to generate in-line. */
1180
1181 if (GET_CODE (containing_fp) != REG)
1182 containing_fp = force_reg (Pmode, containing_fp);
1183
1184 goto_handler = copy_rtx (goto_handler);
1185 validate_replace_rtx (virtual_stack_vars_rtx, containing_fp, goto_handler);
1186
1187 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1188 0, VOIDmode, 2,
1189 containing_fp, Pmode,
1190 goto_handler, Pmode);
1191 }
1192
1193
1194 static struct machine_function *
1195 xtensa_init_machine_status (void)
1196 {
1197 return ggc_alloc_cleared (sizeof (struct machine_function));
1198 }
1199
1200
1201 /* Shift VAL of mode MODE left by COUNT bits. */
1202
1203 static inline rtx
1204 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1205 {
1206 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1207 NULL_RTX, 1, OPTAB_DIRECT);
1208 return expand_simple_binop (SImode, ASHIFT, val, count,
1209 NULL_RTX, 1, OPTAB_DIRECT);
1210 }
1211
1212
1213 /* Structure to hold the initial parameters for a compare_and_swap operation
1214 in HImode and QImode. */
1215
1216 struct alignment_context
1217 {
1218 rtx memsi; /* SI aligned memory location. */
1219 rtx shift; /* Bit offset with regard to lsb. */
1220 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1221 rtx modemaski; /* ~modemask */
1222 };
1223
1224
1225 /* Initialize structure AC for word access to HI and QI mode memory. */
1226
1227 static void
1228 init_alignment_context (struct alignment_context *ac, rtx mem)
1229 {
1230 enum machine_mode mode = GET_MODE (mem);
1231 rtx byteoffset = NULL_RTX;
1232 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1233
1234 if (aligned)
1235 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1236 else
1237 {
1238 /* Alignment is unknown. */
1239 rtx addr, align;
1240
1241 /* Force the address into a register. */
1242 addr = force_reg (Pmode, XEXP (mem, 0));
1243
1244 /* Align it to SImode. */
1245 align = expand_simple_binop (Pmode, AND, addr,
1246 GEN_INT (-GET_MODE_SIZE (SImode)),
1247 NULL_RTX, 1, OPTAB_DIRECT);
1248 /* Generate MEM. */
1249 ac->memsi = gen_rtx_MEM (SImode, align);
1250 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1251 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1252 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1253
1254 byteoffset = expand_simple_binop (Pmode, AND, addr,
1255 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1256 NULL_RTX, 1, OPTAB_DIRECT);
1257 }
1258
1259 /* Calculate shiftcount. */
1260 if (TARGET_BIG_ENDIAN)
1261 {
1262 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1263 if (!aligned)
1264 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1265 NULL_RTX, 1, OPTAB_DIRECT);
1266 }
1267 else
1268 {
1269 if (aligned)
1270 ac->shift = NULL_RTX;
1271 else
1272 ac->shift = byteoffset;
1273 }
1274
1275 if (ac->shift != NULL_RTX)
1276 {
1277 /* Shift is the byte count, but we need the bitcount. */
1278 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1279 GEN_INT (BITS_PER_UNIT),
1280 NULL_RTX, 1, OPTAB_DIRECT);
1281 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1282 GEN_INT (GET_MODE_MASK (mode)),
1283 ac->shift,
1284 NULL_RTX, 1, OPTAB_DIRECT);
1285 }
1286 else
1287 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1288
1289 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1290 }
1291
1292
1293 /* Expand an atomic compare and swap operation for HImode and QImode.
1294 MEM is the memory location, CMP the old value to compare MEM with
1295 and NEW the value to set if CMP == MEM. */
1296
1297 void
1298 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new)
1299 {
1300 enum machine_mode mode = GET_MODE (mem);
1301 struct alignment_context ac;
1302 rtx tmp, cmpv, newv, val;
1303 rtx oldval = gen_reg_rtx (SImode);
1304 rtx res = gen_reg_rtx (SImode);
1305 rtx csloop = gen_label_rtx ();
1306 rtx csend = gen_label_rtx ();
1307
1308 init_alignment_context (&ac, mem);
1309
1310 if (ac.shift != NULL_RTX)
1311 {
1312 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1313 new = xtensa_expand_mask_and_shift (new, mode, ac.shift);
1314 }
1315
1316 /* Load the surrounding word into VAL with the MEM value masked out. */
1317 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1318 ac.modemaski, NULL_RTX, 1,
1319 OPTAB_DIRECT));
1320 emit_label (csloop);
1321
1322 /* Patch CMP and NEW into VAL at correct position. */
1323 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1324 NULL_RTX, 1, OPTAB_DIRECT));
1325 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
1326 NULL_RTX, 1, OPTAB_DIRECT));
1327
1328 /* Jump to end if we're done. */
1329 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1330 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1331
1332 /* Check for changes outside mode. */
1333 emit_move_insn (oldval, val);
1334 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1335 val, 1, OPTAB_DIRECT);
1336 if (tmp != val)
1337 emit_move_insn (val, tmp);
1338
1339 /* Loop internal if so. */
1340 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1341
1342 emit_label (csend);
1343
1344 /* Return the correct part of the bitfield. */
1345 convert_move (target,
1346 (ac.shift == NULL_RTX ? res
1347 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1348 NULL_RTX, 1, OPTAB_DIRECT)),
1349 1);
1350 }
1351
1352
1353 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1354 the default expansion works fine for SImode). MEM is the memory location
1355 and VAL the value to play with. If AFTER is true then store the value
1356 MEM holds after the operation, if AFTER is false then store the value MEM
1357 holds before the operation. If TARGET is zero then discard that value, else
1358 store it to TARGET. */
1359
1360 void
1361 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1362 bool after)
1363 {
1364 enum machine_mode mode = GET_MODE (mem);
1365 struct alignment_context ac;
1366 rtx csloop = gen_label_rtx ();
1367 rtx cmp, tmp;
1368 rtx old = gen_reg_rtx (SImode);
1369 rtx new = gen_reg_rtx (SImode);
1370 rtx orig = NULL_RTX;
1371
1372 init_alignment_context (&ac, mem);
1373
1374 /* Prepare values before the compare-and-swap loop. */
1375 if (ac.shift != NULL_RTX)
1376 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1377 switch (code)
1378 {
1379 case PLUS:
1380 case MINUS:
1381 orig = gen_reg_rtx (SImode);
1382 convert_move (orig, val, 1);
1383 break;
1384
1385 case SET:
1386 case IOR:
1387 case XOR:
1388 break;
1389
1390 case MULT: /* NAND */
1391 case AND:
1392 /* val = "11..1<val>11..1" */
1393 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1394 NULL_RTX, 1, OPTAB_DIRECT);
1395 break;
1396
1397 default:
1398 gcc_unreachable ();
1399 }
1400
1401 /* Load full word. Subsequent loads are performed by S32C1I. */
1402 cmp = force_reg (SImode, ac.memsi);
1403
1404 emit_label (csloop);
1405 emit_move_insn (old, cmp);
1406
1407 switch (code)
1408 {
1409 case PLUS:
1410 case MINUS:
1411 val = expand_simple_binop (SImode, code, old, orig,
1412 NULL_RTX, 1, OPTAB_DIRECT);
1413 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1414 NULL_RTX, 1, OPTAB_DIRECT);
1415 /* FALLTHRU */
1416 case SET:
1417 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1418 NULL_RTX, 1, OPTAB_DIRECT);
1419 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1420 new, 1, OPTAB_DIRECT);
1421 break;
1422
1423 case AND:
1424 case IOR:
1425 case XOR:
1426 tmp = expand_simple_binop (SImode, code, old, val,
1427 new, 1, OPTAB_DIRECT);
1428 break;
1429
1430 case MULT: /* NAND */
1431 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1432 NULL_RTX, 1, OPTAB_DIRECT);
1433 tmp = expand_simple_binop (SImode, AND, tmp, val,
1434 new, 1, OPTAB_DIRECT);
1435 break;
1436
1437 default:
1438 gcc_unreachable ();
1439 }
1440
1441 if (tmp != new)
1442 emit_move_insn (new, tmp);
1443 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new));
1444 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1445
1446 if (target)
1447 {
1448 tmp = (after ? new : cmp);
1449 convert_move (target,
1450 (ac.shift == NULL_RTX ? tmp
1451 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1452 NULL_RTX, 1, OPTAB_DIRECT)),
1453 1);
1454 }
1455 }
1456
1457
1458 void
1459 xtensa_setup_frame_addresses (void)
1460 {
1461 /* Set flag to cause FRAME_POINTER_REQUIRED to be set. */
1462 cfun->machine->accesses_prev_frame = 1;
1463
1464 emit_library_call
1465 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1466 0, VOIDmode, 0);
1467 }
1468
1469
1470 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1471 a comment showing where the end of the loop is. However, if there is a
1472 label or a branch at the end of the loop then we need to place a nop
1473 there. If the loop ends with a label we need the nop so that branches
1474 targeting that label will target the nop (and thus remain in the loop),
1475 instead of targeting the instruction after the loop (and thus exiting
1476 the loop). If the loop ends with a branch, we need the nop in case the
1477 branch is targeting a location inside the loop. When the branch
1478 executes it will cause the loop count to be decremented even if it is
1479 taken (because it is the last instruction in the loop), so we need to
1480 nop after the branch to prevent the loop count from being decremented
1481 when the branch is taken. */
1482
1483 void
1484 xtensa_emit_loop_end (rtx insn, rtx *operands)
1485 {
1486 char done = 0;
1487
1488 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1489 {
1490 switch (GET_CODE (insn))
1491 {
1492 case NOTE:
1493 case BARRIER:
1494 break;
1495
1496 case CODE_LABEL:
1497 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1498 done = 1;
1499 break;
1500
1501 default:
1502 {
1503 rtx body = PATTERN (insn);
1504
1505 if (GET_CODE (body) == JUMP_INSN)
1506 {
1507 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1508 done = 1;
1509 }
1510 else if ((GET_CODE (body) != USE)
1511 && (GET_CODE (body) != CLOBBER))
1512 done = 1;
1513 }
1514 break;
1515 }
1516 }
1517
1518 output_asm_insn ("# loop end for %0", operands);
1519 }
1520
1521
1522 char *
1523 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1524 {
1525 static char result[64];
1526 enum rtx_code code;
1527 const char *op;
1528
1529 code = GET_CODE (operands[3]);
1530 switch (code)
1531 {
1532 case EQ: op = inverted ? "ne" : "eq"; break;
1533 case NE: op = inverted ? "eq" : "ne"; break;
1534 case LT: op = inverted ? "ge" : "lt"; break;
1535 case GE: op = inverted ? "lt" : "ge"; break;
1536 case LTU: op = inverted ? "geu" : "ltu"; break;
1537 case GEU: op = inverted ? "ltu" : "geu"; break;
1538 default: gcc_unreachable ();
1539 }
1540
1541 if (immed)
1542 {
1543 if (INTVAL (operands[1]) == 0)
1544 sprintf (result, "b%sz%s\t%%0, %%2", op,
1545 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1546 else
1547 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1548 }
1549 else
1550 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1551
1552 return result;
1553 }
1554
1555
1556 char *
1557 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1558 {
1559 static char result[64];
1560 const char *op;
1561
1562 switch (GET_CODE (operands[3]))
1563 {
1564 case EQ: op = inverted ? "bs" : "bc"; break;
1565 case NE: op = inverted ? "bc" : "bs"; break;
1566 default: gcc_unreachable ();
1567 }
1568
1569 if (immed)
1570 {
1571 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1572 operands[1] = GEN_INT (bitnum);
1573 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1574 }
1575 else
1576 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1577
1578 return result;
1579 }
1580
1581
1582 char *
1583 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1584 {
1585 static char result[64];
1586 enum rtx_code code;
1587 const char *op;
1588
1589 code = GET_CODE (operands[4]);
1590 if (isbool)
1591 {
1592 switch (code)
1593 {
1594 case EQ: op = inverted ? "t" : "f"; break;
1595 case NE: op = inverted ? "f" : "t"; break;
1596 default: gcc_unreachable ();
1597 }
1598 }
1599 else
1600 {
1601 switch (code)
1602 {
1603 case EQ: op = inverted ? "nez" : "eqz"; break;
1604 case NE: op = inverted ? "eqz" : "nez"; break;
1605 case LT: op = inverted ? "gez" : "ltz"; break;
1606 case GE: op = inverted ? "ltz" : "gez"; break;
1607 default: gcc_unreachable ();
1608 }
1609 }
1610
1611 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1612 op, isfp ? ".s" : "", inverted ? 3 : 2);
1613 return result;
1614 }
1615
1616
1617 char *
1618 xtensa_emit_call (int callop, rtx *operands)
1619 {
1620 static char result[64];
1621 rtx tgt = operands[callop];
1622
1623 if (GET_CODE (tgt) == CONST_INT)
1624 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1625 else if (register_operand (tgt, VOIDmode))
1626 sprintf (result, "callx8\t%%%d", callop);
1627 else
1628 sprintf (result, "call8\t%%%d", callop);
1629
1630 return result;
1631 }
1632
1633
1634 bool
1635 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1636 {
1637 /* Allow constant pool addresses. */
1638 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1639 && ! TARGET_CONST16 && constantpool_address_p (addr))
1640 return true;
1641
1642 while (GET_CODE (addr) == SUBREG)
1643 addr = SUBREG_REG (addr);
1644
1645 /* Allow base registers. */
1646 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1647 return true;
1648
1649 /* Check for "register + offset" addressing. */
1650 if (GET_CODE (addr) == PLUS)
1651 {
1652 rtx xplus0 = XEXP (addr, 0);
1653 rtx xplus1 = XEXP (addr, 1);
1654 enum rtx_code code0;
1655 enum rtx_code code1;
1656
1657 while (GET_CODE (xplus0) == SUBREG)
1658 xplus0 = SUBREG_REG (xplus0);
1659 code0 = GET_CODE (xplus0);
1660
1661 while (GET_CODE (xplus1) == SUBREG)
1662 xplus1 = SUBREG_REG (xplus1);
1663 code1 = GET_CODE (xplus1);
1664
1665 /* Swap operands if necessary so the register is first. */
1666 if (code0 != REG && code1 == REG)
1667 {
1668 xplus0 = XEXP (addr, 1);
1669 xplus1 = XEXP (addr, 0);
1670 code0 = GET_CODE (xplus0);
1671 code1 = GET_CODE (xplus1);
1672 }
1673
1674 if (code0 == REG && BASE_REG_P (xplus0, strict)
1675 && code1 == CONST_INT
1676 && xtensa_mem_offset (INTVAL (xplus1), mode))
1677 return true;
1678 }
1679
1680 return false;
1681 }
1682
1683
1684 rtx
1685 xtensa_legitimize_address (rtx x,
1686 rtx oldx ATTRIBUTE_UNUSED,
1687 enum machine_mode mode)
1688 {
1689 if (GET_CODE (x) == PLUS)
1690 {
1691 rtx plus0 = XEXP (x, 0);
1692 rtx plus1 = XEXP (x, 1);
1693
1694 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1695 {
1696 plus0 = XEXP (x, 1);
1697 plus1 = XEXP (x, 0);
1698 }
1699
1700 /* Try to split up the offset to use an ADDMI instruction. */
1701 if (GET_CODE (plus0) == REG
1702 && GET_CODE (plus1) == CONST_INT
1703 && !xtensa_mem_offset (INTVAL (plus1), mode)
1704 && !xtensa_simm8 (INTVAL (plus1))
1705 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1706 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1707 {
1708 rtx temp = gen_reg_rtx (Pmode);
1709 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1710 emit_insn (gen_rtx_SET (Pmode, temp,
1711 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1712 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1713 }
1714 }
1715
1716 return NULL_RTX;
1717 }
1718
1719
1720 /* Return the debugger register number to use for 'regno'. */
1721
1722 int
1723 xtensa_dbx_register_number (int regno)
1724 {
1725 int first = -1;
1726
1727 if (GP_REG_P (regno))
1728 {
1729 regno -= GP_REG_FIRST;
1730 first = 0;
1731 }
1732 else if (BR_REG_P (regno))
1733 {
1734 regno -= BR_REG_FIRST;
1735 first = 16;
1736 }
1737 else if (FP_REG_P (regno))
1738 {
1739 regno -= FP_REG_FIRST;
1740 first = 48;
1741 }
1742 else if (ACC_REG_P (regno))
1743 {
1744 first = 0x200; /* Start of Xtensa special registers. */
1745 regno = 16; /* ACCLO is special register 16. */
1746 }
1747
1748 /* When optimizing, we sometimes get asked about pseudo-registers
1749 that don't represent hard registers. Return 0 for these. */
1750 if (first == -1)
1751 return 0;
1752
1753 return first + regno;
1754 }
1755
1756
1757 /* Argument support functions. */
1758
1759 /* Initialize CUMULATIVE_ARGS for a function. */
1760
1761 void
1762 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
1763 {
1764 cum->arg_words = 0;
1765 cum->incoming = incoming;
1766 }
1767
1768
1769 /* Advance the argument to the next argument position. */
1770
1771 void
1772 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type)
1773 {
1774 int words, max;
1775 int *arg_words;
1776
1777 arg_words = &cum->arg_words;
1778 max = MAX_ARGS_IN_REGISTERS;
1779
1780 words = (((mode != BLKmode)
1781 ? (int) GET_MODE_SIZE (mode)
1782 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1783
1784 if (*arg_words < max
1785 && (targetm.calls.must_pass_in_stack (mode, type)
1786 || *arg_words + words > max))
1787 *arg_words = max;
1788
1789 *arg_words += words;
1790 }
1791
1792
1793 /* Return an RTL expression containing the register for the given mode,
1794 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
1795 if this is an incoming argument to the current function. */
1796
1797 rtx
1798 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
1799 int incoming_p)
1800 {
1801 int regbase, words, max;
1802 int *arg_words;
1803 int regno;
1804
1805 arg_words = &cum->arg_words;
1806 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
1807 max = MAX_ARGS_IN_REGISTERS;
1808
1809 words = (((mode != BLKmode)
1810 ? (int) GET_MODE_SIZE (mode)
1811 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1812
1813 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
1814 {
1815 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
1816 *arg_words = (*arg_words + align - 1) & -align;
1817 }
1818
1819 if (*arg_words + words > max)
1820 return (rtx)0;
1821
1822 regno = regbase + *arg_words;
1823
1824 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
1825 cfun->machine->need_a7_copy = true;
1826
1827 return gen_rtx_REG (mode, regno);
1828 }
1829
1830
1831 int
1832 function_arg_boundary (enum machine_mode mode, tree type)
1833 {
1834 unsigned int alignment;
1835
1836 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
1837 if (alignment < PARM_BOUNDARY)
1838 alignment = PARM_BOUNDARY;
1839 if (alignment > STACK_BOUNDARY)
1840 alignment = STACK_BOUNDARY;
1841 return alignment;
1842 }
1843
1844
1845 static bool
1846 xtensa_return_in_msb (tree valtype)
1847 {
1848 return (TARGET_BIG_ENDIAN
1849 && AGGREGATE_TYPE_P (valtype)
1850 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
1851 }
1852
1853
1854 void
1855 override_options (void)
1856 {
1857 int regno;
1858 enum machine_mode mode;
1859
1860 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
1861 error ("boolean registers required for the floating-point option");
1862
1863 /* Set up array giving whether a given register can hold a given mode. */
1864 for (mode = VOIDmode;
1865 mode != MAX_MACHINE_MODE;
1866 mode = (enum machine_mode) ((int) mode + 1))
1867 {
1868 int size = GET_MODE_SIZE (mode);
1869 enum mode_class class = GET_MODE_CLASS (mode);
1870
1871 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1872 {
1873 int temp;
1874
1875 if (ACC_REG_P (regno))
1876 temp = (TARGET_MAC16
1877 && (class == MODE_INT) && (size <= UNITS_PER_WORD));
1878 else if (GP_REG_P (regno))
1879 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
1880 else if (FP_REG_P (regno))
1881 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
1882 else if (BR_REG_P (regno))
1883 temp = (TARGET_BOOLEANS && (mode == CCmode));
1884 else
1885 temp = FALSE;
1886
1887 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
1888 }
1889 }
1890
1891 init_machine_status = xtensa_init_machine_status;
1892
1893 /* Check PIC settings. PIC is only supported when using L32R
1894 instructions, and some targets need to always use PIC. */
1895 if (flag_pic && TARGET_CONST16)
1896 error ("-f%s is not supported with CONST16 instructions",
1897 (flag_pic > 1 ? "PIC" : "pic"));
1898 else if (XTENSA_ALWAYS_PIC)
1899 {
1900 if (TARGET_CONST16)
1901 error ("PIC is required but not supported with CONST16 instructions");
1902 flag_pic = 1;
1903 }
1904 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
1905 if (flag_pic > 1)
1906 flag_pic = 1;
1907
1908 /* Hot/cold partitioning does not work on this architecture, because of
1909 constant pools (the load instruction cannot necessarily reach that far).
1910 Therefore disable it on this architecture. */
1911 if (flag_reorder_blocks_and_partition)
1912 {
1913 flag_reorder_blocks_and_partition = 0;
1914 flag_reorder_blocks = 1;
1915 }
1916 }
1917
1918
1919 /* A C compound statement to output to stdio stream STREAM the
1920 assembler syntax for an instruction operand X. X is an RTL
1921 expression.
1922
1923 CODE is a value that can be used to specify one of several ways
1924 of printing the operand. It is used when identical operands
1925 must be printed differently depending on the context. CODE
1926 comes from the '%' specification that was used to request
1927 printing of the operand. If the specification was just '%DIGIT'
1928 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
1929 is the ASCII code for LTR.
1930
1931 If X is a register, this macro should print the register's name.
1932 The names can be found in an array 'reg_names' whose type is
1933 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
1934
1935 When the machine description has a specification '%PUNCT' (a '%'
1936 followed by a punctuation character), this macro is called with
1937 a null pointer for X and the punctuation character for CODE.
1938
1939 'a', 'c', 'l', and 'n' are reserved.
1940
1941 The Xtensa specific codes are:
1942
1943 'd' CONST_INT, print as signed decimal
1944 'x' CONST_INT, print as signed hexadecimal
1945 'K' CONST_INT, print number of bits in mask for EXTUI
1946 'R' CONST_INT, print (X & 0x1f)
1947 'L' CONST_INT, print ((32 - X) & 0x1f)
1948 'D' REG, print second register of double-word register operand
1949 'N' MEM, print address of next word following a memory operand
1950 'v' MEM, if memory reference is volatile, output a MEMW before it
1951 't' any constant, add "@h" suffix for top 16 bits
1952 'b' any constant, add "@l" suffix for bottom 16 bits
1953 */
1954
1955 static void
1956 printx (FILE *file, signed int val)
1957 {
1958 /* Print a hexadecimal value in a nice way. */
1959 if ((val > -0xa) && (val < 0xa))
1960 fprintf (file, "%d", val);
1961 else if (val < 0)
1962 fprintf (file, "-0x%x", -val);
1963 else
1964 fprintf (file, "0x%x", val);
1965 }
1966
1967
1968 void
1969 print_operand (FILE *file, rtx x, int letter)
1970 {
1971 if (!x)
1972 error ("PRINT_OPERAND null pointer");
1973
1974 switch (letter)
1975 {
1976 case 'D':
1977 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
1978 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
1979 else
1980 output_operand_lossage ("invalid %%D value");
1981 break;
1982
1983 case 'v':
1984 if (GET_CODE (x) == MEM)
1985 {
1986 /* For a volatile memory reference, emit a MEMW before the
1987 load or store. */
1988 if (MEM_VOLATILE_P (x))
1989 fprintf (file, "memw\n\t");
1990 }
1991 else
1992 output_operand_lossage ("invalid %%v value");
1993 break;
1994
1995 case 'N':
1996 if (GET_CODE (x) == MEM
1997 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
1998 {
1999 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2000 output_address (XEXP (x, 0));
2001 }
2002 else
2003 output_operand_lossage ("invalid %%N value");
2004 break;
2005
2006 case 'K':
2007 if (GET_CODE (x) == CONST_INT)
2008 {
2009 int num_bits = 0;
2010 unsigned val = INTVAL (x);
2011 while (val & 1)
2012 {
2013 num_bits += 1;
2014 val = val >> 1;
2015 }
2016 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2017 fatal_insn ("invalid mask", x);
2018
2019 fprintf (file, "%d", num_bits);
2020 }
2021 else
2022 output_operand_lossage ("invalid %%K value");
2023 break;
2024
2025 case 'L':
2026 if (GET_CODE (x) == CONST_INT)
2027 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2028 else
2029 output_operand_lossage ("invalid %%L value");
2030 break;
2031
2032 case 'R':
2033 if (GET_CODE (x) == CONST_INT)
2034 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2035 else
2036 output_operand_lossage ("invalid %%R value");
2037 break;
2038
2039 case 'x':
2040 if (GET_CODE (x) == CONST_INT)
2041 printx (file, INTVAL (x));
2042 else
2043 output_operand_lossage ("invalid %%x value");
2044 break;
2045
2046 case 'd':
2047 if (GET_CODE (x) == CONST_INT)
2048 fprintf (file, "%ld", INTVAL (x));
2049 else
2050 output_operand_lossage ("invalid %%d value");
2051 break;
2052
2053 case 't':
2054 case 'b':
2055 if (GET_CODE (x) == CONST_INT)
2056 {
2057 printx (file, INTVAL (x));
2058 fputs (letter == 't' ? "@h" : "@l", file);
2059 }
2060 else if (GET_CODE (x) == CONST_DOUBLE)
2061 {
2062 REAL_VALUE_TYPE r;
2063 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2064 if (GET_MODE (x) == SFmode)
2065 {
2066 long l;
2067 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2068 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2069 }
2070 else
2071 output_operand_lossage ("invalid %%t/%%b value");
2072 }
2073 else if (GET_CODE (x) == CONST)
2074 {
2075 /* X must be a symbolic constant on ELF. Write an expression
2076 suitable for 'const16' that sets the high or low 16 bits. */
2077 if (GET_CODE (XEXP (x, 0)) != PLUS
2078 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2079 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2080 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2081 output_operand_lossage ("invalid %%t/%%b value");
2082 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2083 fputs (letter == 't' ? "@h" : "@l", file);
2084 /* There must be a non-alphanumeric character between 'h' or 'l'
2085 and the number. The '-' is added by print_operand() already. */
2086 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2087 fputs ("+", file);
2088 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2089 }
2090 else
2091 {
2092 output_addr_const (file, x);
2093 fputs (letter == 't' ? "@h" : "@l", file);
2094 }
2095 break;
2096
2097 default:
2098 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2099 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2100 else if (GET_CODE (x) == MEM)
2101 output_address (XEXP (x, 0));
2102 else if (GET_CODE (x) == CONST_INT)
2103 fprintf (file, "%ld", INTVAL (x));
2104 else
2105 output_addr_const (file, x);
2106 }
2107 }
2108
2109
2110 /* A C compound statement to output to stdio stream STREAM the
2111 assembler syntax for an instruction operand that is a memory
2112 reference whose address is ADDR. ADDR is an RTL expression. */
2113
2114 void
2115 print_operand_address (FILE *file, rtx addr)
2116 {
2117 if (!addr)
2118 error ("PRINT_OPERAND_ADDRESS, null pointer");
2119
2120 switch (GET_CODE (addr))
2121 {
2122 default:
2123 fatal_insn ("invalid address", addr);
2124 break;
2125
2126 case REG:
2127 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2128 break;
2129
2130 case PLUS:
2131 {
2132 rtx reg = (rtx)0;
2133 rtx offset = (rtx)0;
2134 rtx arg0 = XEXP (addr, 0);
2135 rtx arg1 = XEXP (addr, 1);
2136
2137 if (GET_CODE (arg0) == REG)
2138 {
2139 reg = arg0;
2140 offset = arg1;
2141 }
2142 else if (GET_CODE (arg1) == REG)
2143 {
2144 reg = arg1;
2145 offset = arg0;
2146 }
2147 else
2148 fatal_insn ("no register in address", addr);
2149
2150 if (CONSTANT_P (offset))
2151 {
2152 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2153 output_addr_const (file, offset);
2154 }
2155 else
2156 fatal_insn ("address offset not a constant", addr);
2157 }
2158 break;
2159
2160 case LABEL_REF:
2161 case SYMBOL_REF:
2162 case CONST_INT:
2163 case CONST:
2164 output_addr_const (file, addr);
2165 break;
2166 }
2167 }
2168
2169
2170 bool
2171 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2172 {
2173 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2174 {
2175 switch (XINT (x, 1))
2176 {
2177 case UNSPEC_PLT:
2178 if (flag_pic)
2179 {
2180 output_addr_const (fp, XVECEXP (x, 0, 0));
2181 fputs ("@PLT", fp);
2182 return true;
2183 }
2184 break;
2185 default:
2186 break;
2187 }
2188 }
2189 return false;
2190 }
2191
2192
2193 void
2194 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2195 {
2196 long value_long[2];
2197 REAL_VALUE_TYPE r;
2198 int size;
2199 rtx first, second;
2200
2201 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2202
2203 switch (GET_MODE_CLASS (mode))
2204 {
2205 case MODE_FLOAT:
2206 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2207
2208 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2209 switch (mode)
2210 {
2211 case SFmode:
2212 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2213 if (HOST_BITS_PER_LONG > 32)
2214 value_long[0] &= 0xffffffff;
2215 fprintf (file, "0x%08lx\n", value_long[0]);
2216 break;
2217
2218 case DFmode:
2219 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2220 if (HOST_BITS_PER_LONG > 32)
2221 {
2222 value_long[0] &= 0xffffffff;
2223 value_long[1] &= 0xffffffff;
2224 }
2225 fprintf (file, "0x%08lx, 0x%08lx\n",
2226 value_long[0], value_long[1]);
2227 break;
2228
2229 default:
2230 gcc_unreachable ();
2231 }
2232
2233 break;
2234
2235 case MODE_INT:
2236 case MODE_PARTIAL_INT:
2237 size = GET_MODE_SIZE (mode);
2238 switch (size)
2239 {
2240 case 4:
2241 output_addr_const (file, x);
2242 fputs ("\n", file);
2243 break;
2244
2245 case 8:
2246 split_double (x, &first, &second);
2247 output_addr_const (file, first);
2248 fputs (", ", file);
2249 output_addr_const (file, second);
2250 fputs ("\n", file);
2251 break;
2252
2253 default:
2254 gcc_unreachable ();
2255 }
2256 break;
2257
2258 default:
2259 gcc_unreachable ();
2260 }
2261 }
2262
2263
2264 /* Return the bytes needed to compute the frame pointer from the current
2265 stack pointer. */
2266
2267 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2268 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2269
2270 long
2271 compute_frame_size (int size)
2272 {
2273 /* Add space for the incoming static chain value. */
2274 if (cfun->static_chain_decl != NULL)
2275 size += (1 * UNITS_PER_WORD);
2276
2277 xtensa_current_frame_size =
2278 XTENSA_STACK_ALIGN (size
2279 + current_function_outgoing_args_size
2280 + (WINDOW_SIZE * UNITS_PER_WORD));
2281 return xtensa_current_frame_size;
2282 }
2283
2284
2285 int
2286 xtensa_frame_pointer_required (void)
2287 {
2288 /* The code to expand builtin_frame_addr and builtin_return_addr
2289 currently uses the hard_frame_pointer instead of frame_pointer.
2290 This seems wrong but maybe it's necessary for other architectures.
2291 This function is derived from the i386 code. */
2292
2293 if (cfun->machine->accesses_prev_frame)
2294 return 1;
2295
2296 return 0;
2297 }
2298
2299
2300 void
2301 xtensa_expand_prologue (void)
2302 {
2303 HOST_WIDE_INT total_size;
2304 rtx size_rtx;
2305
2306 total_size = compute_frame_size (get_frame_size ());
2307 size_rtx = GEN_INT (total_size);
2308
2309 if (total_size < (1 << (12+3)))
2310 emit_insn (gen_entry (size_rtx, size_rtx));
2311 else
2312 {
2313 /* Use a8 as a temporary since a0-a7 may be live. */
2314 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2315 emit_insn (gen_entry (size_rtx, GEN_INT (MIN_FRAME_SIZE)));
2316 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2317 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2318 emit_move_insn (stack_pointer_rtx, tmp_reg);
2319 }
2320
2321 if (frame_pointer_needed)
2322 {
2323 if (cfun->machine->set_frame_ptr_insn)
2324 {
2325 rtx first, insn;
2326
2327 push_topmost_sequence ();
2328 first = get_insns ();
2329 pop_topmost_sequence ();
2330
2331 /* For all instructions prior to set_frame_ptr_insn, replace
2332 hard_frame_pointer references with stack_pointer. */
2333 for (insn = first;
2334 insn != cfun->machine->set_frame_ptr_insn;
2335 insn = NEXT_INSN (insn))
2336 {
2337 if (INSN_P (insn))
2338 {
2339 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2340 hard_frame_pointer_rtx,
2341 stack_pointer_rtx);
2342 df_insn_rescan (insn);
2343 }
2344 }
2345 }
2346 else
2347 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
2348 }
2349 }
2350
2351
2352 /* Clear variables at function end. */
2353
2354 void
2355 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2356 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2357 {
2358 xtensa_current_frame_size = 0;
2359 }
2360
2361
2362 rtx
2363 xtensa_return_addr (int count, rtx frame)
2364 {
2365 rtx result, retaddr;
2366
2367 if (count == -1)
2368 retaddr = gen_rtx_REG (Pmode, A0_REG);
2369 else
2370 {
2371 rtx addr = plus_constant (frame, -4 * UNITS_PER_WORD);
2372 addr = memory_address (Pmode, addr);
2373 retaddr = gen_reg_rtx (Pmode);
2374 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2375 }
2376
2377 /* The 2 most-significant bits of the return address on Xtensa hold
2378 the register window size. To get the real return address, these
2379 bits must be replaced with the high bits from the current PC. */
2380
2381 result = gen_reg_rtx (Pmode);
2382 emit_insn (gen_fix_return_addr (result, retaddr));
2383 return result;
2384 }
2385
2386
2387 /* Create the va_list data type.
2388
2389 This structure is set up by __builtin_saveregs. The __va_reg field
2390 points to a stack-allocated region holding the contents of the
2391 incoming argument registers. The __va_ndx field is an index
2392 initialized to the position of the first unnamed (variable)
2393 argument. This same index is also used to address the arguments
2394 passed in memory. Thus, the __va_stk field is initialized to point
2395 to the position of the first argument in memory offset to account
2396 for the arguments passed in registers and to account for the size
2397 of the argument registers not being 16-byte aligned. E.G., there
2398 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2399 for the first stack argument to have the maximal alignment of 16
2400 bytes, so we offset the __va_stk address by 32 bytes so that
2401 __va_stk[32] references the first argument on the stack. */
2402
2403 static tree
2404 xtensa_build_builtin_va_list (void)
2405 {
2406 tree f_stk, f_reg, f_ndx, record, type_decl;
2407
2408 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2409 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
2410
2411 f_stk = build_decl (FIELD_DECL, get_identifier ("__va_stk"),
2412 ptr_type_node);
2413 f_reg = build_decl (FIELD_DECL, get_identifier ("__va_reg"),
2414 ptr_type_node);
2415 f_ndx = build_decl (FIELD_DECL, get_identifier ("__va_ndx"),
2416 integer_type_node);
2417
2418 DECL_FIELD_CONTEXT (f_stk) = record;
2419 DECL_FIELD_CONTEXT (f_reg) = record;
2420 DECL_FIELD_CONTEXT (f_ndx) = record;
2421
2422 TREE_CHAIN (record) = type_decl;
2423 TYPE_NAME (record) = type_decl;
2424 TYPE_FIELDS (record) = f_stk;
2425 TREE_CHAIN (f_stk) = f_reg;
2426 TREE_CHAIN (f_reg) = f_ndx;
2427
2428 layout_type (record);
2429 return record;
2430 }
2431
2432
2433 /* Save the incoming argument registers on the stack. Returns the
2434 address of the saved registers. */
2435
2436 static rtx
2437 xtensa_builtin_saveregs (void)
2438 {
2439 rtx gp_regs;
2440 int arg_words = current_function_args_info.arg_words;
2441 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2442
2443 if (gp_left <= 0)
2444 return const0_rtx;
2445
2446 /* Allocate the general-purpose register space. */
2447 gp_regs = assign_stack_local
2448 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2449 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2450
2451 /* Now store the incoming registers. */
2452 cfun->machine->need_a7_copy = true;
2453 cfun->machine->vararg_a7 = true;
2454 move_block_from_reg (GP_ARG_FIRST + arg_words,
2455 adjust_address (gp_regs, BLKmode,
2456 arg_words * UNITS_PER_WORD),
2457 gp_left);
2458
2459 return XEXP (gp_regs, 0);
2460 }
2461
2462
2463 /* Implement `va_start' for varargs and stdarg. We look at the
2464 current function to fill in an initial va_list. */
2465
2466 void
2467 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2468 {
2469 tree f_stk, stk;
2470 tree f_reg, reg;
2471 tree f_ndx, ndx;
2472 tree t, u;
2473 int arg_words;
2474
2475 arg_words = current_function_args_info.arg_words;
2476
2477 f_stk = TYPE_FIELDS (va_list_type_node);
2478 f_reg = TREE_CHAIN (f_stk);
2479 f_ndx = TREE_CHAIN (f_reg);
2480
2481 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2482 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), valist, f_reg, NULL_TREE);
2483 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), valist, f_ndx, NULL_TREE);
2484
2485 /* Call __builtin_saveregs; save the result in __va_reg */
2486 u = make_tree (sizetype, expand_builtin_saveregs ());
2487 u = fold_convert (ptr_type_node, u);
2488 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, reg, u);
2489 TREE_SIDE_EFFECTS (t) = 1;
2490 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2491
2492 /* Set the __va_stk member to ($arg_ptr - 32). */
2493 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2494 u = fold_build2 (POINTER_PLUS_EXPR, ptr_type_node, u, size_int (-32));
2495 t = build2 (GIMPLE_MODIFY_STMT, ptr_type_node, stk, u);
2496 TREE_SIDE_EFFECTS (t) = 1;
2497 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2498
2499 /* Set the __va_ndx member. If the first variable argument is on
2500 the stack, adjust __va_ndx by 2 words to account for the extra
2501 alignment offset for __va_stk. */
2502 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2503 arg_words += 2;
2504 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, ndx,
2505 size_int (arg_words * UNITS_PER_WORD));
2506 TREE_SIDE_EFFECTS (t) = 1;
2507 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2508 }
2509
2510
2511 /* Implement `va_arg'. */
2512
2513 static tree
2514 xtensa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p,
2515 tree *post_p ATTRIBUTE_UNUSED)
2516 {
2517 tree f_stk, stk;
2518 tree f_reg, reg;
2519 tree f_ndx, ndx;
2520 tree type_size, array, orig_ndx, addr, size, va_size, t;
2521 tree lab_false, lab_over, lab_false2;
2522 bool indirect;
2523
2524 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2525 if (indirect)
2526 type = build_pointer_type (type);
2527
2528 /* Handle complex values as separate real and imaginary parts. */
2529 if (TREE_CODE (type) == COMPLEX_TYPE)
2530 {
2531 tree real_part, imag_part;
2532
2533 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2534 pre_p, NULL);
2535 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2536
2537 imag_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2538 pre_p, NULL);
2539 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2540
2541 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2542 }
2543
2544 f_stk = TYPE_FIELDS (va_list_type_node);
2545 f_reg = TREE_CHAIN (f_stk);
2546 f_ndx = TREE_CHAIN (f_reg);
2547
2548 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2549 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), valist, f_reg, NULL_TREE);
2550 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), valist, f_ndx, NULL_TREE);
2551
2552 type_size = size_in_bytes (type);
2553 va_size = round_up (type_size, UNITS_PER_WORD);
2554 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2555
2556
2557 /* First align __va_ndx if necessary for this arg:
2558
2559 orig_ndx = (AP).__va_ndx;
2560 if (__alignof__ (TYPE) > 4 )
2561 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2562 & -__alignof__ (TYPE)); */
2563
2564 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2565
2566 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2567 {
2568 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2569
2570 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, size_int (align - 1));
2571 t = build2 (BIT_AND_EXPR, integer_type_node, t, size_int (-align));
2572 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, orig_ndx, t);
2573 gimplify_and_add (t, pre_p);
2574 }
2575
2576
2577 /* Increment __va_ndx to point past the argument:
2578
2579 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2580
2581 t = fold_convert (integer_type_node, va_size);
2582 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2583 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, ndx, t);
2584 gimplify_and_add (t, pre_p);
2585
2586
2587 /* Check if the argument is in registers:
2588
2589 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2590 && !must_pass_in_stack (type))
2591 __array = (AP).__va_reg; */
2592
2593 array = create_tmp_var (ptr_type_node, NULL);
2594
2595 lab_over = NULL;
2596 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2597 {
2598 lab_false = create_artificial_label ();
2599 lab_over = create_artificial_label ();
2600
2601 t = build2 (GT_EXPR, boolean_type_node, ndx,
2602 size_int (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2603 t = build3 (COND_EXPR, void_type_node, t,
2604 build1 (GOTO_EXPR, void_type_node, lab_false),
2605 NULL_TREE);
2606 gimplify_and_add (t, pre_p);
2607
2608 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, array, reg);
2609 gimplify_and_add (t, pre_p);
2610
2611 t = build1 (GOTO_EXPR, void_type_node, lab_over);
2612 gimplify_and_add (t, pre_p);
2613
2614 t = build1 (LABEL_EXPR, void_type_node, lab_false);
2615 gimplify_and_add (t, pre_p);
2616 }
2617
2618
2619 /* ...otherwise, the argument is on the stack (never split between
2620 registers and the stack -- change __va_ndx if necessary):
2621
2622 else
2623 {
2624 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2625 (AP).__va_ndx = 32 + __va_size (TYPE);
2626 __array = (AP).__va_stk;
2627 } */
2628
2629 lab_false2 = create_artificial_label ();
2630
2631 t = build2 (GT_EXPR, boolean_type_node, orig_ndx,
2632 size_int (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2633 t = build3 (COND_EXPR, void_type_node, t,
2634 build1 (GOTO_EXPR, void_type_node, lab_false2),
2635 NULL_TREE);
2636 gimplify_and_add (t, pre_p);
2637
2638 t = size_binop (PLUS_EXPR, va_size, size_int (32));
2639 t = fold_convert (integer_type_node, t);
2640 t = build2 (GIMPLE_MODIFY_STMT, integer_type_node, ndx, t);
2641 gimplify_and_add (t, pre_p);
2642
2643 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
2644 gimplify_and_add (t, pre_p);
2645
2646 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, array, stk);
2647 gimplify_and_add (t, pre_p);
2648
2649 if (lab_over)
2650 {
2651 t = build1 (LABEL_EXPR, void_type_node, lab_over);
2652 gimplify_and_add (t, pre_p);
2653 }
2654
2655
2656 /* Given the base array pointer (__array) and index to the subsequent
2657 argument (__va_ndx), find the address:
2658
2659 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2660 ? sizeof (TYPE)
2661 : __va_size (TYPE))
2662
2663 The results are endian-dependent because values smaller than one word
2664 are aligned differently. */
2665
2666
2667 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
2668 {
2669 t = fold_build2 (GE_EXPR, boolean_type_node, type_size,
2670 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
2671 t = fold_build3 (COND_EXPR, sizetype, t, va_size, type_size);
2672 size = t;
2673 }
2674 else
2675 size = va_size;
2676
2677 t = build2 (MINUS_EXPR, sizetype, ndx, size);
2678 addr = build2 (POINTER_PLUS_EXPR, ptr_type_node, array, t);
2679
2680 addr = fold_convert (build_pointer_type (type), addr);
2681 if (indirect)
2682 addr = build_va_arg_indirect_ref (addr);
2683 return build_va_arg_indirect_ref (addr);
2684 }
2685
2686
2687 /* Builtins. */
2688
2689 enum xtensa_builtin
2690 {
2691 XTENSA_BUILTIN_UMULSIDI3,
2692 XTENSA_BUILTIN_max
2693 };
2694
2695
2696 static void
2697 xtensa_init_builtins (void)
2698 {
2699 tree ftype;
2700
2701 ftype = build_function_type_list (unsigned_intDI_type_node,
2702 unsigned_intSI_type_node,
2703 unsigned_intSI_type_node, NULL_TREE);
2704
2705 add_builtin_function ("__builtin_umulsidi3", ftype,
2706 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
2707 "__umulsidi3", NULL_TREE);
2708 }
2709
2710
2711 static tree
2712 xtensa_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED)
2713 {
2714 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2715 tree arg0, arg1;
2716
2717 if (fcode == XTENSA_BUILTIN_UMULSIDI3)
2718 {
2719 arg0 = TREE_VALUE (arglist);
2720 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
2721 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
2722 || TARGET_MUL32_HIGH)
2723 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
2724 fold_convert (unsigned_intDI_type_node, arg0),
2725 fold_convert (unsigned_intDI_type_node, arg1));
2726 else
2727 return NULL;
2728 }
2729
2730 internal_error ("bad builtin code");
2731 return NULL;
2732 }
2733
2734
2735 static rtx
2736 xtensa_expand_builtin (tree exp, rtx target,
2737 rtx subtarget ATTRIBUTE_UNUSED,
2738 enum machine_mode mode ATTRIBUTE_UNUSED,
2739 int ignore)
2740 {
2741 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
2742 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2743
2744 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
2745 __umulsidi3 function when the Xtensa configuration can directly
2746 implement it. If not, just call the function. */
2747 if (fcode == XTENSA_BUILTIN_UMULSIDI3)
2748 return expand_call (exp, target, ignore);
2749
2750 internal_error ("bad builtin code");
2751 return NULL_RTX;
2752 }
2753
2754
2755 enum reg_class
2756 xtensa_preferred_reload_class (rtx x, enum reg_class class, int isoutput)
2757 {
2758 if (!isoutput && CONSTANT_P (x) && GET_CODE (x) == CONST_DOUBLE)
2759 return NO_REGS;
2760
2761 /* Don't use the stack pointer or hard frame pointer for reloads!
2762 The hard frame pointer would normally be OK except that it may
2763 briefly hold an incoming argument in the prologue, and reload
2764 won't know that it is live because the hard frame pointer is
2765 treated specially. */
2766
2767 if (class == AR_REGS || class == GR_REGS)
2768 return RL_REGS;
2769
2770 return class;
2771 }
2772
2773
2774 enum reg_class
2775 xtensa_secondary_reload_class (enum reg_class class,
2776 enum machine_mode mode ATTRIBUTE_UNUSED,
2777 rtx x, int isoutput)
2778 {
2779 int regno;
2780
2781 if (GET_CODE (x) == SIGN_EXTEND)
2782 x = XEXP (x, 0);
2783 regno = xt_true_regnum (x);
2784
2785 if (!isoutput)
2786 {
2787 if (class == FP_REGS && constantpool_mem_p (x))
2788 return RL_REGS;
2789 }
2790
2791 if (ACC_REG_P (regno))
2792 return ((class == GR_REGS || class == RL_REGS) ? NO_REGS : RL_REGS);
2793 if (class == ACC_REG)
2794 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
2795
2796 return NO_REGS;
2797 }
2798
2799
2800 void
2801 order_regs_for_local_alloc (void)
2802 {
2803 if (!leaf_function_p ())
2804 {
2805 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
2806 FIRST_PSEUDO_REGISTER * sizeof (int));
2807 }
2808 else
2809 {
2810 int i, num_arg_regs;
2811 int nxt = 0;
2812
2813 /* Use the AR registers in increasing order (skipping a0 and a1)
2814 but save the incoming argument registers for a last resort. */
2815 num_arg_regs = current_function_args_info.arg_words;
2816 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
2817 num_arg_regs = MAX_ARGS_IN_REGISTERS;
2818 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
2819 reg_alloc_order[nxt++] = i + num_arg_regs;
2820 for (i = 0; i < num_arg_regs; i++)
2821 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
2822
2823 /* List the coprocessor registers in order. */
2824 for (i = 0; i < BR_REG_NUM; i++)
2825 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
2826
2827 /* List the FP registers in order for now. */
2828 for (i = 0; i < 16; i++)
2829 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
2830
2831 /* GCC requires that we list *all* the registers.... */
2832 reg_alloc_order[nxt++] = 0; /* a0 = return address */
2833 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
2834 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
2835 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
2836
2837 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
2838 }
2839 }
2840
2841
2842 /* Some Xtensa targets support multiple bss sections. If the section
2843 name ends with ".bss", add SECTION_BSS to the flags. */
2844
2845 static unsigned int
2846 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
2847 {
2848 unsigned int flags = default_section_type_flags (decl, name, reloc);
2849 const char *suffix;
2850
2851 suffix = strrchr (name, '.');
2852 if (suffix && strcmp (suffix, ".bss") == 0)
2853 {
2854 if (!decl || (TREE_CODE (decl) == VAR_DECL
2855 && DECL_INITIAL (decl) == NULL_TREE))
2856 flags |= SECTION_BSS; /* @nobits */
2857 else
2858 warning (0, "only uninitialized variables can be placed in a "
2859 ".bss section");
2860 }
2861
2862 return flags;
2863 }
2864
2865
2866 /* The literal pool stays with the function. */
2867
2868 static section *
2869 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
2870 rtx x ATTRIBUTE_UNUSED,
2871 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
2872 {
2873 return function_section (current_function_decl);
2874 }
2875
2876
2877 /* Compute a (partial) cost for rtx X. Return true if the complete
2878 cost has been computed, and false if subexpressions should be
2879 scanned. In either case, *TOTAL contains the cost result. */
2880
2881 static bool
2882 xtensa_rtx_costs (rtx x, int code, int outer_code, int *total)
2883 {
2884 switch (code)
2885 {
2886 case CONST_INT:
2887 switch (outer_code)
2888 {
2889 case SET:
2890 if (xtensa_simm12b (INTVAL (x)))
2891 {
2892 *total = 4;
2893 return true;
2894 }
2895 break;
2896 case PLUS:
2897 if (xtensa_simm8 (INTVAL (x))
2898 || xtensa_simm8x256 (INTVAL (x)))
2899 {
2900 *total = 0;
2901 return true;
2902 }
2903 break;
2904 case AND:
2905 if (xtensa_mask_immediate (INTVAL (x)))
2906 {
2907 *total = 0;
2908 return true;
2909 }
2910 break;
2911 case COMPARE:
2912 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
2913 {
2914 *total = 0;
2915 return true;
2916 }
2917 break;
2918 case ASHIFT:
2919 case ASHIFTRT:
2920 case LSHIFTRT:
2921 case ROTATE:
2922 case ROTATERT:
2923 /* No way to tell if X is the 2nd operand so be conservative. */
2924 default: break;
2925 }
2926 if (xtensa_simm12b (INTVAL (x)))
2927 *total = 5;
2928 else if (TARGET_CONST16)
2929 *total = COSTS_N_INSNS (2);
2930 else
2931 *total = 6;
2932 return true;
2933
2934 case CONST:
2935 case LABEL_REF:
2936 case SYMBOL_REF:
2937 if (TARGET_CONST16)
2938 *total = COSTS_N_INSNS (2);
2939 else
2940 *total = 5;
2941 return true;
2942
2943 case CONST_DOUBLE:
2944 if (TARGET_CONST16)
2945 *total = COSTS_N_INSNS (4);
2946 else
2947 *total = 7;
2948 return true;
2949
2950 case MEM:
2951 {
2952 int num_words =
2953 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
2954
2955 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
2956 *total = COSTS_N_INSNS (num_words);
2957 else
2958 *total = COSTS_N_INSNS (2*num_words);
2959 return true;
2960 }
2961
2962 case FFS:
2963 case CTZ:
2964 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
2965 return true;
2966
2967 case CLZ:
2968 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
2969 return true;
2970
2971 case NOT:
2972 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
2973 return true;
2974
2975 case AND:
2976 case IOR:
2977 case XOR:
2978 if (GET_MODE (x) == DImode)
2979 *total = COSTS_N_INSNS (2);
2980 else
2981 *total = COSTS_N_INSNS (1);
2982 return true;
2983
2984 case ASHIFT:
2985 case ASHIFTRT:
2986 case LSHIFTRT:
2987 if (GET_MODE (x) == DImode)
2988 *total = COSTS_N_INSNS (50);
2989 else
2990 *total = COSTS_N_INSNS (1);
2991 return true;
2992
2993 case ABS:
2994 {
2995 enum machine_mode xmode = GET_MODE (x);
2996 if (xmode == SFmode)
2997 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
2998 else if (xmode == DFmode)
2999 *total = COSTS_N_INSNS (50);
3000 else
3001 *total = COSTS_N_INSNS (4);
3002 return true;
3003 }
3004
3005 case PLUS:
3006 case MINUS:
3007 {
3008 enum machine_mode xmode = GET_MODE (x);
3009 if (xmode == SFmode)
3010 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3011 else if (xmode == DFmode || xmode == DImode)
3012 *total = COSTS_N_INSNS (50);
3013 else
3014 *total = COSTS_N_INSNS (1);
3015 return true;
3016 }
3017
3018 case NEG:
3019 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3020 return true;
3021
3022 case MULT:
3023 {
3024 enum machine_mode xmode = GET_MODE (x);
3025 if (xmode == SFmode)
3026 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3027 else if (xmode == DFmode)
3028 *total = COSTS_N_INSNS (50);
3029 else if (xmode == DImode)
3030 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3031 else if (TARGET_MUL32)
3032 *total = COSTS_N_INSNS (4);
3033 else if (TARGET_MAC16)
3034 *total = COSTS_N_INSNS (16);
3035 else if (TARGET_MUL16)
3036 *total = COSTS_N_INSNS (12);
3037 else
3038 *total = COSTS_N_INSNS (50);
3039 return true;
3040 }
3041
3042 case DIV:
3043 case MOD:
3044 {
3045 enum machine_mode xmode = GET_MODE (x);
3046 if (xmode == SFmode)
3047 {
3048 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3049 return true;
3050 }
3051 else if (xmode == DFmode)
3052 {
3053 *total = COSTS_N_INSNS (50);
3054 return true;
3055 }
3056 }
3057 /* Fall through. */
3058
3059 case UDIV:
3060 case UMOD:
3061 {
3062 enum machine_mode xmode = GET_MODE (x);
3063 if (xmode == DImode)
3064 *total = COSTS_N_INSNS (50);
3065 else if (TARGET_DIV32)
3066 *total = COSTS_N_INSNS (32);
3067 else
3068 *total = COSTS_N_INSNS (50);
3069 return true;
3070 }
3071
3072 case SQRT:
3073 if (GET_MODE (x) == SFmode)
3074 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3075 else
3076 *total = COSTS_N_INSNS (50);
3077 return true;
3078
3079 case SMIN:
3080 case UMIN:
3081 case SMAX:
3082 case UMAX:
3083 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3084 return true;
3085
3086 case SIGN_EXTRACT:
3087 case SIGN_EXTEND:
3088 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3089 return true;
3090
3091 case ZERO_EXTRACT:
3092 case ZERO_EXTEND:
3093 *total = COSTS_N_INSNS (1);
3094 return true;
3095
3096 default:
3097 return false;
3098 }
3099 }
3100
3101 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3102
3103 static bool
3104 xtensa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3105 {
3106 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3107 > 4 * UNITS_PER_WORD);
3108 }
3109
3110 #include "gt-xtensa.h"