1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright (C) 2001-2014 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "basic-block.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
32 #include "insn-attr.h"
33 #include "insn-codes.h"
37 #include "stringpool.h"
38 #include "stor-layout.h"
46 #include "diagnostic-core.h"
51 #include "target-def.h"
52 #include "langhooks.h"
53 #include "pointer-set.h"
54 #include "hash-table.h"
55 #include "tree-ssa-alias.h"
56 #include "internal-fn.h"
57 #include "gimple-fold.h"
59 #include "gimple-expr.h"
67 /* Enumeration for all of the relational tests, so that we can build
68 arrays indexed by the test type, and not worry about the order
86 /* Array giving truth value on whether or not a given hard register
87 can support a given mode. */
88 char xtensa_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
90 /* Current frame size calculated by compute_frame_size. */
91 unsigned xtensa_current_frame_size
;
93 /* Largest block move to handle in-line. */
94 #define LARGEST_MOVE_RATIO 15
96 /* Define the structure for the machine field in struct function. */
97 struct GTY(()) machine_function
99 int accesses_prev_frame
;
103 rtx set_frame_ptr_insn
;
106 /* Vector, indexed by hard register number, which contains 1 for a
107 register that is allowable in a candidate for leaf function
110 const char xtensa_leaf_regs
[FIRST_PSEUDO_REGISTER
] =
112 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
118 /* Map hard register number to register class */
119 const enum reg_class xtensa_regno_to_class
[FIRST_PSEUDO_REGISTER
] =
121 RL_REGS
, SP_REG
, RL_REGS
, RL_REGS
,
122 RL_REGS
, RL_REGS
, RL_REGS
, GR_REGS
,
123 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
124 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
125 AR_REGS
, AR_REGS
, BR_REGS
,
126 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
127 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
128 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
129 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
133 static void xtensa_option_override (void);
134 static enum internal_test
map_test_to_internal_test (enum rtx_code
);
135 static rtx
gen_int_relational (enum rtx_code
, rtx
, rtx
, int *);
136 static rtx
gen_float_relational (enum rtx_code
, rtx
, rtx
);
137 static rtx
gen_conditional_move (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
138 static rtx
fixup_subreg_mem (rtx
);
139 static struct machine_function
* xtensa_init_machine_status (void);
140 static rtx
xtensa_legitimize_tls_address (rtx
);
141 static rtx
xtensa_legitimize_address (rtx
, rtx
, enum machine_mode
);
142 static bool xtensa_mode_dependent_address_p (const_rtx
, addr_space_t
);
143 static bool xtensa_return_in_msb (const_tree
);
144 static void printx (FILE *, signed int);
145 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT
);
146 static rtx
xtensa_builtin_saveregs (void);
147 static bool xtensa_legitimate_address_p (enum machine_mode
, rtx
, bool);
148 static unsigned int xtensa_multibss_section_type_flags (tree
, const char *,
149 int) ATTRIBUTE_UNUSED
;
150 static section
*xtensa_select_rtx_section (enum machine_mode
, rtx
,
151 unsigned HOST_WIDE_INT
);
152 static bool xtensa_rtx_costs (rtx
, int, int, int, int *, bool);
153 static int xtensa_register_move_cost (enum machine_mode
, reg_class_t
,
155 static int xtensa_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
156 static tree
xtensa_build_builtin_va_list (void);
157 static bool xtensa_return_in_memory (const_tree
, const_tree
);
158 static tree
xtensa_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*,
160 static void xtensa_function_arg_advance (cumulative_args_t
, enum machine_mode
,
162 static rtx
xtensa_function_arg (cumulative_args_t
, enum machine_mode
,
164 static rtx
xtensa_function_incoming_arg (cumulative_args_t
,
165 enum machine_mode
, const_tree
, bool);
166 static rtx
xtensa_function_value (const_tree
, const_tree
, bool);
167 static rtx
xtensa_libcall_value (enum machine_mode
, const_rtx
);
168 static bool xtensa_function_value_regno_p (const unsigned int);
169 static unsigned int xtensa_function_arg_boundary (enum machine_mode
,
171 static void xtensa_init_builtins (void);
172 static tree
xtensa_fold_builtin (tree
, int, tree
*, bool);
173 static rtx
xtensa_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
174 static void xtensa_va_start (tree
, rtx
);
175 static bool xtensa_frame_pointer_required (void);
176 static rtx
xtensa_static_chain (const_tree
, bool);
177 static void xtensa_asm_trampoline_template (FILE *);
178 static void xtensa_trampoline_init (rtx
, tree
, rtx
);
179 static bool xtensa_output_addr_const_extra (FILE *, rtx
);
180 static bool xtensa_cannot_force_const_mem (enum machine_mode
, rtx
);
182 static reg_class_t
xtensa_preferred_reload_class (rtx
, reg_class_t
);
183 static reg_class_t
xtensa_preferred_output_reload_class (rtx
, reg_class_t
);
184 static reg_class_t
xtensa_secondary_reload (bool, rtx
, reg_class_t
,
186 struct secondary_reload_info
*);
188 static bool constantpool_address_p (const_rtx addr
);
189 static bool xtensa_legitimate_constant_p (enum machine_mode
, rtx
);
191 static bool xtensa_member_type_forces_blk (const_tree
,
192 enum machine_mode mode
);
194 static const int reg_nonleaf_alloc_order
[FIRST_PSEUDO_REGISTER
] =
198 /* This macro generates the assembly code for function exit,
199 on machines that need it. If FUNCTION_EPILOGUE is not defined
200 then individual return instructions are generated for each
201 return statement. Args are same as for FUNCTION_PROLOGUE. */
203 #undef TARGET_ASM_FUNCTION_EPILOGUE
204 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
206 /* These hooks specify assembly directives for creating certain kinds
207 of integer object. */
209 #undef TARGET_ASM_ALIGNED_SI_OP
210 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
212 #undef TARGET_ASM_SELECT_RTX_SECTION
213 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
215 #undef TARGET_LEGITIMIZE_ADDRESS
216 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
217 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
218 #define TARGET_MODE_DEPENDENT_ADDRESS_P xtensa_mode_dependent_address_p
220 #undef TARGET_REGISTER_MOVE_COST
221 #define TARGET_REGISTER_MOVE_COST xtensa_register_move_cost
222 #undef TARGET_MEMORY_MOVE_COST
223 #define TARGET_MEMORY_MOVE_COST xtensa_memory_move_cost
224 #undef TARGET_RTX_COSTS
225 #define TARGET_RTX_COSTS xtensa_rtx_costs
226 #undef TARGET_ADDRESS_COST
227 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
229 #undef TARGET_MEMBER_TYPE_FORCES_BLK
230 #define TARGET_MEMBER_TYPE_FORCES_BLK xtensa_member_type_forces_blk
232 #undef TARGET_BUILD_BUILTIN_VA_LIST
233 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
235 #undef TARGET_EXPAND_BUILTIN_VA_START
236 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
238 #undef TARGET_PROMOTE_FUNCTION_MODE
239 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
240 #undef TARGET_PROMOTE_PROTOTYPES
241 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
243 #undef TARGET_RETURN_IN_MEMORY
244 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
245 #undef TARGET_FUNCTION_VALUE
246 #define TARGET_FUNCTION_VALUE xtensa_function_value
247 #undef TARGET_LIBCALL_VALUE
248 #define TARGET_LIBCALL_VALUE xtensa_libcall_value
249 #undef TARGET_FUNCTION_VALUE_REGNO_P
250 #define TARGET_FUNCTION_VALUE_REGNO_P xtensa_function_value_regno_p
252 #undef TARGET_SPLIT_COMPLEX_ARG
253 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
254 #undef TARGET_MUST_PASS_IN_STACK
255 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
256 #undef TARGET_FUNCTION_ARG_ADVANCE
257 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance
258 #undef TARGET_FUNCTION_ARG
259 #define TARGET_FUNCTION_ARG xtensa_function_arg
260 #undef TARGET_FUNCTION_INCOMING_ARG
261 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg
262 #undef TARGET_FUNCTION_ARG_BOUNDARY
263 #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary
265 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
266 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
267 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
268 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
270 #undef TARGET_RETURN_IN_MSB
271 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
273 #undef TARGET_INIT_BUILTINS
274 #define TARGET_INIT_BUILTINS xtensa_init_builtins
275 #undef TARGET_FOLD_BUILTIN
276 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
277 #undef TARGET_EXPAND_BUILTIN
278 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
280 #undef TARGET_PREFERRED_RELOAD_CLASS
281 #define TARGET_PREFERRED_RELOAD_CLASS xtensa_preferred_reload_class
282 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
283 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xtensa_preferred_output_reload_class
285 #undef TARGET_SECONDARY_RELOAD
286 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
288 #undef TARGET_HAVE_TLS
289 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
291 #undef TARGET_CANNOT_FORCE_CONST_MEM
292 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem
294 #undef TARGET_LEGITIMATE_ADDRESS_P
295 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
297 #undef TARGET_FRAME_POINTER_REQUIRED
298 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
300 #undef TARGET_STATIC_CHAIN
301 #define TARGET_STATIC_CHAIN xtensa_static_chain
302 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
303 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template
304 #undef TARGET_TRAMPOLINE_INIT
305 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init
307 #undef TARGET_OPTION_OVERRIDE
308 #define TARGET_OPTION_OVERRIDE xtensa_option_override
310 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
311 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra
313 #undef TARGET_LEGITIMATE_CONSTANT_P
314 #define TARGET_LEGITIMATE_CONSTANT_P xtensa_legitimate_constant_p
316 struct gcc_target targetm
= TARGET_INITIALIZER
;
319 /* Functions to test Xtensa immediate operand validity. */
322 xtensa_simm8 (HOST_WIDE_INT v
)
324 return v
>= -128 && v
<= 127;
329 xtensa_simm8x256 (HOST_WIDE_INT v
)
331 return (v
& 255) == 0 && (v
>= -32768 && v
<= 32512);
336 xtensa_simm12b (HOST_WIDE_INT v
)
338 return v
>= -2048 && v
<= 2047;
343 xtensa_uimm8 (HOST_WIDE_INT v
)
345 return v
>= 0 && v
<= 255;
350 xtensa_uimm8x2 (HOST_WIDE_INT v
)
352 return (v
& 1) == 0 && (v
>= 0 && v
<= 510);
357 xtensa_uimm8x4 (HOST_WIDE_INT v
)
359 return (v
& 3) == 0 && (v
>= 0 && v
<= 1020);
364 xtensa_b4const (HOST_WIDE_INT v
)
391 xtensa_b4const_or_zero (HOST_WIDE_INT v
)
395 return xtensa_b4const (v
);
400 xtensa_b4constu (HOST_WIDE_INT v
)
427 xtensa_mask_immediate (HOST_WIDE_INT v
)
429 #define MAX_MASK_SIZE 16
432 for (mask_size
= 1; mask_size
<= MAX_MASK_SIZE
; mask_size
++)
445 /* This is just like the standard true_regnum() function except that it
446 works even when reg_renumber is not initialized. */
449 xt_true_regnum (rtx x
)
451 if (GET_CODE (x
) == REG
)
454 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
455 && reg_renumber
[REGNO (x
)] >= 0)
456 return reg_renumber
[REGNO (x
)];
459 if (GET_CODE (x
) == SUBREG
)
461 int base
= xt_true_regnum (SUBREG_REG (x
));
462 if (base
>= 0 && base
< FIRST_PSEUDO_REGISTER
)
463 return base
+ subreg_regno_offset (REGNO (SUBREG_REG (x
)),
464 GET_MODE (SUBREG_REG (x
)),
465 SUBREG_BYTE (x
), GET_MODE (x
));
472 xtensa_valid_move (enum machine_mode mode
, rtx
*operands
)
474 /* Either the destination or source must be a register, and the
475 MAC16 accumulator doesn't count. */
477 if (register_operand (operands
[0], mode
))
479 int dst_regnum
= xt_true_regnum (operands
[0]);
481 /* The stack pointer can only be assigned with a MOVSP opcode. */
482 if (dst_regnum
== STACK_POINTER_REGNUM
)
483 return (mode
== SImode
484 && register_operand (operands
[1], mode
)
485 && !ACC_REG_P (xt_true_regnum (operands
[1])));
487 if (!ACC_REG_P (dst_regnum
))
490 if (register_operand (operands
[1], mode
))
492 int src_regnum
= xt_true_regnum (operands
[1]);
493 if (!ACC_REG_P (src_regnum
))
501 smalloffset_mem_p (rtx op
)
503 if (GET_CODE (op
) == MEM
)
505 rtx addr
= XEXP (op
, 0);
506 if (GET_CODE (addr
) == REG
)
507 return BASE_REG_P (addr
, 0);
508 if (GET_CODE (addr
) == PLUS
)
510 rtx offset
= XEXP (addr
, 0);
512 if (GET_CODE (offset
) != CONST_INT
)
513 offset
= XEXP (addr
, 1);
514 if (GET_CODE (offset
) != CONST_INT
)
517 val
= INTVAL (offset
);
518 return (val
& 3) == 0 && (val
>= 0 && val
<= 60);
526 constantpool_address_p (const_rtx addr
)
528 const_rtx sym
= addr
;
530 if (GET_CODE (addr
) == CONST
)
534 /* Only handle (PLUS (SYM, OFFSET)) form. */
535 addr
= XEXP (addr
, 0);
536 if (GET_CODE (addr
) != PLUS
)
539 /* Make sure the address is word aligned. */
540 offset
= XEXP (addr
, 1);
541 if ((!CONST_INT_P (offset
))
542 || ((INTVAL (offset
) & 3) != 0))
545 sym
= XEXP (addr
, 0);
548 if ((GET_CODE (sym
) == SYMBOL_REF
)
549 && CONSTANT_POOL_ADDRESS_P (sym
))
556 constantpool_mem_p (rtx op
)
558 if (GET_CODE (op
) == SUBREG
)
559 op
= SUBREG_REG (op
);
560 if (GET_CODE (op
) == MEM
)
561 return constantpool_address_p (XEXP (op
, 0));
566 /* Return TRUE if X is a thread-local symbol. */
569 xtensa_tls_symbol_p (rtx x
)
571 if (! TARGET_HAVE_TLS
)
574 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
579 xtensa_extend_reg (rtx dst
, rtx src
)
581 rtx temp
= gen_reg_rtx (SImode
);
582 rtx shift
= GEN_INT (BITS_PER_WORD
- GET_MODE_BITSIZE (GET_MODE (src
)));
584 /* Generate paradoxical subregs as needed so that the modes match. */
585 src
= simplify_gen_subreg (SImode
, src
, GET_MODE (src
), 0);
586 dst
= simplify_gen_subreg (SImode
, dst
, GET_MODE (dst
), 0);
588 emit_insn (gen_ashlsi3 (temp
, src
, shift
));
589 emit_insn (gen_ashrsi3 (dst
, temp
, shift
));
594 xtensa_mem_offset (unsigned v
, enum machine_mode mode
)
599 /* Handle the worst case for block moves. See xtensa_expand_block_move
600 where we emit an optimized block move operation if the block can be
601 moved in < "move_ratio" pieces. The worst case is when the block is
602 aligned but has a size of (3 mod 4) (does this happen?) so that the
603 last piece requires a byte load/store. */
604 return (xtensa_uimm8 (v
)
605 && xtensa_uimm8 (v
+ MOVE_MAX
* LARGEST_MOVE_RATIO
));
608 return xtensa_uimm8 (v
);
611 return xtensa_uimm8x2 (v
);
614 return (xtensa_uimm8x4 (v
) && xtensa_uimm8x4 (v
+ 4));
620 return xtensa_uimm8x4 (v
);
624 /* Make normal rtx_code into something we can index from an array. */
626 static enum internal_test
627 map_test_to_internal_test (enum rtx_code test_code
)
629 enum internal_test test
= ITEST_MAX
;
634 case EQ
: test
= ITEST_EQ
; break;
635 case NE
: test
= ITEST_NE
; break;
636 case GT
: test
= ITEST_GT
; break;
637 case GE
: test
= ITEST_GE
; break;
638 case LT
: test
= ITEST_LT
; break;
639 case LE
: test
= ITEST_LE
; break;
640 case GTU
: test
= ITEST_GTU
; break;
641 case GEU
: test
= ITEST_GEU
; break;
642 case LTU
: test
= ITEST_LTU
; break;
643 case LEU
: test
= ITEST_LEU
; break;
650 /* Generate the code to compare two integer values. The return value is
651 the comparison expression. */
654 gen_int_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
655 rtx cmp0
, /* first operand to compare */
656 rtx cmp1
, /* second operand to compare */
657 int *p_invert
/* whether branch needs to reverse test */)
661 enum rtx_code test_code
; /* test code to use in insn */
662 bool (*const_range_p
) (HOST_WIDE_INT
); /* range check function */
663 int const_add
; /* constant to add (convert LE -> LT) */
664 int reverse_regs
; /* reverse registers in test */
665 int invert_const
; /* != 0 if invert value if cmp1 is constant */
666 int invert_reg
; /* != 0 if invert value if cmp1 is register */
667 int unsignedp
; /* != 0 for unsigned comparisons. */
670 static struct cmp_info info
[ (int)ITEST_MAX
] = {
672 { EQ
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* EQ */
673 { NE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* NE */
675 { LT
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* GT */
676 { GE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* GE */
677 { LT
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* LT */
678 { GE
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* LE */
680 { LTU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* GTU */
681 { GEU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* GEU */
682 { LTU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* LTU */
683 { GEU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* LEU */
686 enum internal_test test
;
687 enum machine_mode mode
;
688 struct cmp_info
*p_info
;
690 test
= map_test_to_internal_test (test_code
);
691 gcc_assert (test
!= ITEST_MAX
);
693 p_info
= &info
[ (int)test
];
695 mode
= GET_MODE (cmp0
);
696 if (mode
== VOIDmode
)
697 mode
= GET_MODE (cmp1
);
699 /* Make sure we can handle any constants given to us. */
700 if (GET_CODE (cmp1
) == CONST_INT
)
702 HOST_WIDE_INT value
= INTVAL (cmp1
);
703 unsigned HOST_WIDE_INT uvalue
= (unsigned HOST_WIDE_INT
)value
;
705 /* if the immediate overflows or does not fit in the immediate field,
706 spill it to a register */
708 if ((p_info
->unsignedp
?
709 (uvalue
+ p_info
->const_add
> uvalue
) :
710 (value
+ p_info
->const_add
> value
)) != (p_info
->const_add
> 0))
712 cmp1
= force_reg (mode
, cmp1
);
714 else if (!(p_info
->const_range_p
) (value
+ p_info
->const_add
))
716 cmp1
= force_reg (mode
, cmp1
);
719 else if ((GET_CODE (cmp1
) != REG
) && (GET_CODE (cmp1
) != SUBREG
))
721 cmp1
= force_reg (mode
, cmp1
);
724 /* See if we need to invert the result. */
725 *p_invert
= ((GET_CODE (cmp1
) == CONST_INT
)
726 ? p_info
->invert_const
727 : p_info
->invert_reg
);
729 /* Comparison to constants, may involve adding 1 to change a LT into LE.
730 Comparison between two registers, may involve switching operands. */
731 if (GET_CODE (cmp1
) == CONST_INT
)
733 if (p_info
->const_add
!= 0)
734 cmp1
= GEN_INT (INTVAL (cmp1
) + p_info
->const_add
);
737 else if (p_info
->reverse_regs
)
744 return gen_rtx_fmt_ee (p_info
->test_code
, VOIDmode
, cmp0
, cmp1
);
748 /* Generate the code to compare two float values. The return value is
749 the comparison expression. */
752 gen_float_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
753 rtx cmp0
, /* first operand to compare */
754 rtx cmp1
/* second operand to compare */)
756 rtx (*gen_fn
) (rtx
, rtx
, rtx
);
758 int reverse_regs
, invert
;
762 case EQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_seq_sf
; break;
763 case NE
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_seq_sf
; break;
764 case LE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sle_sf
; break;
765 case GT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_slt_sf
; break;
766 case LT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_slt_sf
; break;
767 case GE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sle_sf
; break;
768 case UNEQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_suneq_sf
; break;
769 case LTGT
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_suneq_sf
; break;
770 case UNLE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunle_sf
; break;
771 case UNGT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
772 case UNLT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
773 case UNGE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunle_sf
; break;
775 reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunordered_sf
; break;
777 reverse_regs
= 0; invert
= 1; gen_fn
= gen_sunordered_sf
; break;
779 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
780 reverse_regs
= 0; invert
= 0; gen_fn
= 0; /* avoid compiler warnings */
790 brtmp
= gen_rtx_REG (CCmode
, FPCC_REGNUM
);
791 emit_insn (gen_fn (brtmp
, cmp0
, cmp1
));
793 return gen_rtx_fmt_ee (invert
? EQ
: NE
, VOIDmode
, brtmp
, const0_rtx
);
798 xtensa_expand_conditional_branch (rtx
*operands
, enum machine_mode mode
)
800 enum rtx_code test_code
= GET_CODE (operands
[0]);
801 rtx cmp0
= operands
[1];
802 rtx cmp1
= operands
[2];
811 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
815 cmp
= gen_int_relational (test_code
, cmp0
, cmp1
, &invert
);
819 if (!TARGET_HARD_FLOAT
)
820 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
,
823 cmp
= gen_float_relational (test_code
, cmp0
, cmp1
);
827 /* Generate the branch. */
829 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
838 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
839 gen_rtx_IF_THEN_ELSE (VOIDmode
, cmp
,
846 gen_conditional_move (enum rtx_code code
, enum machine_mode mode
,
853 /* Jump optimization calls get_condition() which canonicalizes
854 comparisons like (GE x <const>) to (GT x <const-1>).
855 Transform those comparisons back to GE, since that is the
856 comparison supported in Xtensa. We shouldn't have to
857 transform <LE x const> comparisons, because neither
858 xtensa_expand_conditional_branch() nor get_condition() will
861 if ((code
== GT
) && (op1
== constm1_rtx
))
866 cmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
868 if (boolean_operator (cmp
, VOIDmode
))
870 /* Swap the operands to make const0 second. */
871 if (op0
== const0_rtx
)
877 /* If not comparing against zero, emit a comparison (subtract). */
878 if (op1
!= const0_rtx
)
880 op0
= expand_binop (SImode
, sub_optab
, op0
, op1
,
881 0, 0, OPTAB_LIB_WIDEN
);
885 else if (branch_operator (cmp
, VOIDmode
))
887 /* Swap the operands to make const0 second. */
888 if (op0
== const0_rtx
)
895 case LT
: code
= GE
; break;
896 case GE
: code
= LT
; break;
897 default: gcc_unreachable ();
901 if (op1
!= const0_rtx
)
907 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
910 if (TARGET_HARD_FLOAT
&& mode
== SFmode
)
911 return gen_float_relational (code
, op0
, op1
);
918 xtensa_expand_conditional_move (rtx
*operands
, int isflt
)
920 rtx dest
= operands
[0];
921 rtx cmp
= operands
[1];
922 enum machine_mode cmp_mode
= GET_MODE (XEXP (cmp
, 0));
923 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
925 if (!(cmp
= gen_conditional_move (GET_CODE (cmp
), cmp_mode
,
926 XEXP (cmp
, 0), XEXP (cmp
, 1))))
930 gen_fn
= (cmp_mode
== SImode
931 ? gen_movsfcc_internal0
932 : gen_movsfcc_internal1
);
934 gen_fn
= (cmp_mode
== SImode
935 ? gen_movsicc_internal0
936 : gen_movsicc_internal1
);
938 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), operands
[2], operands
[3], cmp
));
944 xtensa_expand_scc (rtx operands
[4], enum machine_mode cmp_mode
)
946 rtx dest
= operands
[0];
948 rtx one_tmp
, zero_tmp
;
949 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
951 if (!(cmp
= gen_conditional_move (GET_CODE (operands
[1]), cmp_mode
,
952 operands
[2], operands
[3])))
955 one_tmp
= gen_reg_rtx (SImode
);
956 zero_tmp
= gen_reg_rtx (SImode
);
957 emit_insn (gen_movsi (one_tmp
, const_true_rtx
));
958 emit_insn (gen_movsi (zero_tmp
, const0_rtx
));
960 gen_fn
= (cmp_mode
== SImode
961 ? gen_movsicc_internal0
962 : gen_movsicc_internal1
);
963 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), one_tmp
, zero_tmp
, cmp
));
968 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
969 for the output, i.e., the input operands are twice as big as MODE. */
972 xtensa_split_operand_pair (rtx operands
[4], enum machine_mode mode
)
974 switch (GET_CODE (operands
[1]))
977 operands
[3] = gen_rtx_REG (mode
, REGNO (operands
[1]) + 1);
978 operands
[2] = gen_rtx_REG (mode
, REGNO (operands
[1]));
982 operands
[3] = adjust_address (operands
[1], mode
, GET_MODE_SIZE (mode
));
983 operands
[2] = adjust_address (operands
[1], mode
, 0);
988 split_double (operands
[1], &operands
[2], &operands
[3]);
995 switch (GET_CODE (operands
[0]))
998 operands
[1] = gen_rtx_REG (mode
, REGNO (operands
[0]) + 1);
999 operands
[0] = gen_rtx_REG (mode
, REGNO (operands
[0]));
1003 operands
[1] = adjust_address (operands
[0], mode
, GET_MODE_SIZE (mode
));
1004 operands
[0] = adjust_address (operands
[0], mode
, 0);
1013 /* Emit insns to move operands[1] into operands[0].
1014 Return 1 if we have written out everything that needs to be done to
1015 do the move. Otherwise, return 0 and the caller will emit the move
1019 xtensa_emit_move_sequence (rtx
*operands
, enum machine_mode mode
)
1021 rtx src
= operands
[1];
1023 if (CONSTANT_P (src
)
1024 && (GET_CODE (src
) != CONST_INT
|| ! xtensa_simm12b (INTVAL (src
))))
1026 rtx dst
= operands
[0];
1028 if (xtensa_tls_referenced_p (src
))
1032 if (GET_CODE (src
) == CONST
&& GET_CODE (XEXP (src
, 0)) == PLUS
)
1034 addend
= XEXP (XEXP (src
, 0), 1);
1035 src
= XEXP (XEXP (src
, 0), 0);
1038 src
= xtensa_legitimize_tls_address (src
);
1041 src
= gen_rtx_PLUS (mode
, src
, addend
);
1042 src
= force_operand (src
, dst
);
1044 emit_move_insn (dst
, src
);
1048 if (! TARGET_CONST16
)
1050 src
= force_const_mem (SImode
, src
);
1054 /* PC-relative loads are always SImode, and CONST16 is only
1055 supported in the movsi pattern, so add a SUBREG for any other
1060 if (register_operand (dst
, mode
))
1062 emit_move_insn (simplify_gen_subreg (SImode
, dst
, mode
, 0), src
);
1067 src
= force_reg (SImode
, src
);
1068 src
= gen_lowpart_SUBREG (mode
, src
);
1074 if (!(reload_in_progress
| reload_completed
)
1075 && !xtensa_valid_move (mode
, operands
))
1076 operands
[1] = force_reg (mode
, operands
[1]);
1078 operands
[1] = xtensa_copy_incoming_a7 (operands
[1]);
1080 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
1081 instruction won't be recognized after reload, so we remove the
1082 subreg and adjust mem accordingly. */
1083 if (reload_in_progress
)
1085 operands
[0] = fixup_subreg_mem (operands
[0]);
1086 operands
[1] = fixup_subreg_mem (operands
[1]);
1093 fixup_subreg_mem (rtx x
)
1095 if (GET_CODE (x
) == SUBREG
1096 && GET_CODE (SUBREG_REG (x
)) == REG
1097 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
)
1100 gen_rtx_SUBREG (GET_MODE (x
),
1101 reg_equiv_mem (REGNO (SUBREG_REG (x
))),
1103 x
= alter_subreg (&temp
, true);
1109 /* Check if an incoming argument in a7 is expected to be used soon and
1110 if OPND is a register or register pair that includes a7. If so,
1111 create a new pseudo and copy a7 into that pseudo at the very
1112 beginning of the function, followed by the special "set_frame_ptr"
1113 unspec_volatile insn. The return value is either the original
1114 operand, if it is not a7, or the new pseudo containing a copy of
1115 the incoming argument. This is necessary because the register
1116 allocator will ignore conflicts with a7 and may either assign some
1117 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1118 the incoming argument in a7. By copying the argument out of a7 as
1119 the very first thing, and then immediately following that with an
1120 unspec_volatile to keep the scheduler away, we should avoid any
1121 problems. Putting the set_frame_ptr insn at the beginning, with
1122 only the a7 copy before it, also makes it easier for the prologue
1123 expander to initialize the frame pointer after the a7 copy and to
1124 fix up the a7 copy to use the stack pointer instead of the frame
1128 xtensa_copy_incoming_a7 (rtx opnd
)
1130 rtx entry_insns
= 0;
1132 enum machine_mode mode
;
1134 if (!cfun
->machine
->need_a7_copy
)
1137 /* This function should never be called again once a7 has been copied. */
1138 gcc_assert (!cfun
->machine
->set_frame_ptr_insn
);
1140 mode
= GET_MODE (opnd
);
1142 /* The operand using a7 may come in a later instruction, so just return
1143 the original operand if it doesn't use a7. */
1145 if (GET_CODE (reg
) == SUBREG
)
1147 gcc_assert (SUBREG_BYTE (reg
) == 0);
1148 reg
= SUBREG_REG (reg
);
1150 if (GET_CODE (reg
) != REG
1151 || REGNO (reg
) > A7_REG
1152 || REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) <= A7_REG
)
1155 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1156 gcc_assert (REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) - 1 == A7_REG
);
1158 cfun
->machine
->need_a7_copy
= false;
1160 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1161 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1164 tmp
= gen_reg_rtx (mode
);
1170 /* Copy the value out of A7 here but keep the first word in A6 until
1171 after the set_frame_ptr insn. Otherwise, the register allocator
1172 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1174 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 4),
1175 gen_raw_REG (SImode
, A7_REG
)));
1178 emit_insn (gen_movsf_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1181 emit_insn (gen_movsi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1184 emit_insn (gen_movhi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1187 emit_insn (gen_movqi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1193 cfun
->machine
->set_frame_ptr_insn
= emit_insn (gen_set_frame_ptr ());
1195 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1196 if (mode
== DFmode
|| mode
== DImode
)
1197 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 0),
1198 gen_rtx_REG (SImode
, A7_REG
- 1)));
1199 entry_insns
= get_insns ();
1202 if (cfun
->machine
->vararg_a7
)
1204 /* This is called from within builtin_saveregs, which will insert the
1205 saveregs code at the function entry, ahead of anything placed at
1206 the function entry now. Instead, save the sequence to be inserted
1207 at the beginning of the saveregs code. */
1208 cfun
->machine
->vararg_a7_copy
= entry_insns
;
1212 /* Put entry_insns after the NOTE that starts the function. If
1213 this is inside a start_sequence, make the outer-level insn
1214 chain current, so the code is placed at the start of the
1216 push_topmost_sequence ();
1217 /* Do not use entry_of_function() here. This is called from within
1218 expand_function_start, when the CFG still holds GIMPLE. */
1219 emit_insn_after (entry_insns
, get_insns ());
1220 pop_topmost_sequence ();
1227 /* Try to expand a block move operation to a sequence of RTL move
1228 instructions. If not optimizing, or if the block size is not a
1229 constant, or if the block is too large, the expansion fails and GCC
1230 falls back to calling memcpy().
1232 operands[0] is the destination
1233 operands[1] is the source
1234 operands[2] is the length
1235 operands[3] is the alignment */
1238 xtensa_expand_block_move (rtx
*operands
)
1240 static const enum machine_mode mode_from_align
[] =
1242 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1245 rtx dst_mem
= operands
[0];
1246 rtx src_mem
= operands
[1];
1247 HOST_WIDE_INT bytes
, align
;
1248 int num_pieces
, move_ratio
;
1250 enum machine_mode mode
[2];
1259 /* If this is not a fixed size move, just call memcpy. */
1260 if (!optimize
|| (GET_CODE (operands
[2]) != CONST_INT
))
1263 bytes
= INTVAL (operands
[2]);
1264 align
= INTVAL (operands
[3]);
1266 /* Anything to move? */
1270 if (align
> MOVE_MAX
)
1273 /* Decide whether to expand inline based on the optimization level. */
1276 move_ratio
= LARGEST_MOVE_RATIO
;
1277 num_pieces
= (bytes
/ align
) + (bytes
% align
); /* Close enough anyway. */
1278 if (num_pieces
> move_ratio
)
1281 x
= XEXP (dst_mem
, 0);
1284 x
= force_reg (Pmode
, x
);
1285 dst_mem
= replace_equiv_address (dst_mem
, x
);
1288 x
= XEXP (src_mem
, 0);
1291 x
= force_reg (Pmode
, x
);
1292 src_mem
= replace_equiv_address (src_mem
, x
);
1295 active
[0] = active
[1] = false;
1306 next_amount
= (bytes
>= 4 ? 4 : (bytes
>= 2 ? 2 : 1));
1307 next_amount
= MIN (next_amount
, align
);
1309 amount
[next
] = next_amount
;
1310 mode
[next
] = mode_from_align
[next_amount
];
1311 temp
[next
] = gen_reg_rtx (mode
[next
]);
1313 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1314 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1316 offset_ld
+= next_amount
;
1317 bytes
-= next_amount
;
1318 active
[next
] = true;
1323 active
[phase
] = false;
1325 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1326 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1328 offset_st
+= amount
[phase
];
1331 while (active
[next
]);
1338 xtensa_expand_nonlocal_goto (rtx
*operands
)
1340 rtx goto_handler
= operands
[1];
1341 rtx containing_fp
= operands
[3];
1343 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1344 is too big to generate in-line. */
1346 if (GET_CODE (containing_fp
) != REG
)
1347 containing_fp
= force_reg (Pmode
, containing_fp
);
1349 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_nonlocal_goto"),
1350 LCT_NORMAL
, VOIDmode
, 2,
1351 containing_fp
, Pmode
,
1352 goto_handler
, Pmode
);
1356 static struct machine_function
*
1357 xtensa_init_machine_status (void)
1359 return ggc_cleared_alloc
<machine_function
> ();
1363 /* Shift VAL of mode MODE left by COUNT bits. */
1366 xtensa_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
1368 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
1369 NULL_RTX
, 1, OPTAB_DIRECT
);
1370 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
1371 NULL_RTX
, 1, OPTAB_DIRECT
);
1375 /* Structure to hold the initial parameters for a compare_and_swap operation
1376 in HImode and QImode. */
1378 struct alignment_context
1380 rtx memsi
; /* SI aligned memory location. */
1381 rtx shift
; /* Bit offset with regard to lsb. */
1382 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
1383 rtx modemaski
; /* ~modemask */
1387 /* Initialize structure AC for word access to HI and QI mode memory. */
1390 init_alignment_context (struct alignment_context
*ac
, rtx mem
)
1392 enum machine_mode mode
= GET_MODE (mem
);
1393 rtx byteoffset
= NULL_RTX
;
1394 bool aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
1397 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
1400 /* Alignment is unknown. */
1403 /* Force the address into a register. */
1404 addr
= force_reg (Pmode
, XEXP (mem
, 0));
1406 /* Align it to SImode. */
1407 align
= expand_simple_binop (Pmode
, AND
, addr
,
1408 GEN_INT (-GET_MODE_SIZE (SImode
)),
1409 NULL_RTX
, 1, OPTAB_DIRECT
);
1411 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
1412 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
1413 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
1414 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
1416 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
1417 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
1418 NULL_RTX
, 1, OPTAB_DIRECT
);
1421 /* Calculate shiftcount. */
1422 if (TARGET_BIG_ENDIAN
)
1424 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
1426 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
1427 NULL_RTX
, 1, OPTAB_DIRECT
);
1432 ac
->shift
= NULL_RTX
;
1434 ac
->shift
= byteoffset
;
1437 if (ac
->shift
!= NULL_RTX
)
1439 /* Shift is the byte count, but we need the bitcount. */
1440 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
,
1441 GEN_INT (BITS_PER_UNIT
),
1442 NULL_RTX
, 1, OPTAB_DIRECT
);
1443 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
1444 GEN_INT (GET_MODE_MASK (mode
)),
1446 NULL_RTX
, 1, OPTAB_DIRECT
);
1449 ac
->modemask
= GEN_INT (GET_MODE_MASK (mode
));
1451 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
1455 /* Expand an atomic compare and swap operation for HImode and QImode.
1456 MEM is the memory location, CMP the old value to compare MEM with
1457 and NEW_RTX the value to set if CMP == MEM. */
1460 xtensa_expand_compare_and_swap (rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
1462 enum machine_mode mode
= GET_MODE (mem
);
1463 struct alignment_context ac
;
1464 rtx tmp
, cmpv
, newv
, val
;
1465 rtx oldval
= gen_reg_rtx (SImode
);
1466 rtx res
= gen_reg_rtx (SImode
);
1467 rtx csloop
= gen_label_rtx ();
1468 rtx csend
= gen_label_rtx ();
1470 init_alignment_context (&ac
, mem
);
1472 if (ac
.shift
!= NULL_RTX
)
1474 cmp
= xtensa_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
1475 new_rtx
= xtensa_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
1478 /* Load the surrounding word into VAL with the MEM value masked out. */
1479 val
= force_reg (SImode
, expand_simple_binop (SImode
, AND
, ac
.memsi
,
1480 ac
.modemaski
, NULL_RTX
, 1,
1482 emit_label (csloop
);
1484 /* Patch CMP and NEW_RTX into VAL at correct position. */
1485 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
1486 NULL_RTX
, 1, OPTAB_DIRECT
));
1487 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
1488 NULL_RTX
, 1, OPTAB_DIRECT
));
1490 /* Jump to end if we're done. */
1491 emit_insn (gen_sync_compare_and_swapsi (res
, ac
.memsi
, cmpv
, newv
));
1492 emit_cmp_and_jump_insns (res
, cmpv
, EQ
, const0_rtx
, SImode
, true, csend
);
1494 /* Check for changes outside mode. */
1495 emit_move_insn (oldval
, val
);
1496 tmp
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
1497 val
, 1, OPTAB_DIRECT
);
1499 emit_move_insn (val
, tmp
);
1501 /* Loop internal if so. */
1502 emit_cmp_and_jump_insns (oldval
, val
, NE
, const0_rtx
, SImode
, true, csloop
);
1506 /* Return the correct part of the bitfield. */
1507 convert_move (target
,
1508 (ac
.shift
== NULL_RTX
? res
1509 : expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
1510 NULL_RTX
, 1, OPTAB_DIRECT
)),
1515 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1516 the default expansion works fine for SImode). MEM is the memory location
1517 and VAL the value to play with. If AFTER is true then store the value
1518 MEM holds after the operation, if AFTER is false then store the value MEM
1519 holds before the operation. If TARGET is zero then discard that value, else
1520 store it to TARGET. */
1523 xtensa_expand_atomic (enum rtx_code code
, rtx target
, rtx mem
, rtx val
,
1526 enum machine_mode mode
= GET_MODE (mem
);
1527 struct alignment_context ac
;
1528 rtx csloop
= gen_label_rtx ();
1530 rtx old
= gen_reg_rtx (SImode
);
1531 rtx new_rtx
= gen_reg_rtx (SImode
);
1532 rtx orig
= NULL_RTX
;
1534 init_alignment_context (&ac
, mem
);
1536 /* Prepare values before the compare-and-swap loop. */
1537 if (ac
.shift
!= NULL_RTX
)
1538 val
= xtensa_expand_mask_and_shift (val
, mode
, ac
.shift
);
1543 orig
= gen_reg_rtx (SImode
);
1544 convert_move (orig
, val
, 1);
1552 case MULT
: /* NAND */
1554 /* val = "11..1<val>11..1" */
1555 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
1556 NULL_RTX
, 1, OPTAB_DIRECT
);
1563 /* Load full word. Subsequent loads are performed by S32C1I. */
1564 cmp
= force_reg (SImode
, ac
.memsi
);
1566 emit_label (csloop
);
1567 emit_move_insn (old
, cmp
);
1573 val
= expand_simple_binop (SImode
, code
, old
, orig
,
1574 NULL_RTX
, 1, OPTAB_DIRECT
);
1575 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
1576 NULL_RTX
, 1, OPTAB_DIRECT
);
1579 tmp
= expand_simple_binop (SImode
, AND
, old
, ac
.modemaski
,
1580 NULL_RTX
, 1, OPTAB_DIRECT
);
1581 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
,
1582 new_rtx
, 1, OPTAB_DIRECT
);
1588 tmp
= expand_simple_binop (SImode
, code
, old
, val
,
1589 new_rtx
, 1, OPTAB_DIRECT
);
1592 case MULT
: /* NAND */
1593 tmp
= expand_simple_binop (SImode
, XOR
, old
, ac
.modemask
,
1594 NULL_RTX
, 1, OPTAB_DIRECT
);
1595 tmp
= expand_simple_binop (SImode
, AND
, tmp
, val
,
1596 new_rtx
, 1, OPTAB_DIRECT
);
1604 emit_move_insn (new_rtx
, tmp
);
1605 emit_insn (gen_sync_compare_and_swapsi (cmp
, ac
.memsi
, old
, new_rtx
));
1606 emit_cmp_and_jump_insns (cmp
, old
, NE
, const0_rtx
, SImode
, true, csloop
);
1610 tmp
= (after
? new_rtx
: cmp
);
1611 convert_move (target
,
1612 (ac
.shift
== NULL_RTX
? tmp
1613 : expand_simple_binop (SImode
, LSHIFTRT
, tmp
, ac
.shift
,
1614 NULL_RTX
, 1, OPTAB_DIRECT
)),
1621 xtensa_setup_frame_addresses (void)
1623 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1624 cfun
->machine
->accesses_prev_frame
= 1;
1627 (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_libgcc_window_spill"),
1628 LCT_NORMAL
, VOIDmode
, 0);
1632 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1633 a comment showing where the end of the loop is. However, if there is a
1634 label or a branch at the end of the loop then we need to place a nop
1635 there. If the loop ends with a label we need the nop so that branches
1636 targeting that label will target the nop (and thus remain in the loop),
1637 instead of targeting the instruction after the loop (and thus exiting
1638 the loop). If the loop ends with a branch, we need the nop in case the
1639 branch is targeting a location inside the loop. When the branch
1640 executes it will cause the loop count to be decremented even if it is
1641 taken (because it is the last instruction in the loop), so we need to
1642 nop after the branch to prevent the loop count from being decremented
1643 when the branch is taken. */
1646 xtensa_emit_loop_end (rtx insn
, rtx
*operands
)
1650 for (insn
= PREV_INSN (insn
); insn
&& !done
; insn
= PREV_INSN (insn
))
1652 switch (GET_CODE (insn
))
1659 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1665 rtx body
= PATTERN (insn
);
1669 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1672 else if ((GET_CODE (body
) != USE
)
1673 && (GET_CODE (body
) != CLOBBER
))
1680 output_asm_insn ("# loop end for %0", operands
);
1685 xtensa_emit_branch (bool inverted
, bool immed
, rtx
*operands
)
1687 static char result
[64];
1691 code
= GET_CODE (operands
[3]);
1694 case EQ
: op
= inverted
? "ne" : "eq"; break;
1695 case NE
: op
= inverted
? "eq" : "ne"; break;
1696 case LT
: op
= inverted
? "ge" : "lt"; break;
1697 case GE
: op
= inverted
? "lt" : "ge"; break;
1698 case LTU
: op
= inverted
? "geu" : "ltu"; break;
1699 case GEU
: op
= inverted
? "ltu" : "geu"; break;
1700 default: gcc_unreachable ();
1705 if (INTVAL (operands
[1]) == 0)
1706 sprintf (result
, "b%sz%s\t%%0, %%2", op
,
1707 (TARGET_DENSITY
&& (code
== EQ
|| code
== NE
)) ? ".n" : "");
1709 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1712 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1719 xtensa_emit_bit_branch (bool inverted
, bool immed
, rtx
*operands
)
1721 static char result
[64];
1724 switch (GET_CODE (operands
[3]))
1726 case EQ
: op
= inverted
? "bs" : "bc"; break;
1727 case NE
: op
= inverted
? "bc" : "bs"; break;
1728 default: gcc_unreachable ();
1733 unsigned bitnum
= INTVAL (operands
[1]) & 0x1f;
1734 operands
[1] = GEN_INT (bitnum
);
1735 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1738 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1745 xtensa_emit_movcc (bool inverted
, bool isfp
, bool isbool
, rtx
*operands
)
1747 static char result
[64];
1751 code
= GET_CODE (operands
[4]);
1756 case EQ
: op
= inverted
? "t" : "f"; break;
1757 case NE
: op
= inverted
? "f" : "t"; break;
1758 default: gcc_unreachable ();
1765 case EQ
: op
= inverted
? "nez" : "eqz"; break;
1766 case NE
: op
= inverted
? "eqz" : "nez"; break;
1767 case LT
: op
= inverted
? "gez" : "ltz"; break;
1768 case GE
: op
= inverted
? "ltz" : "gez"; break;
1769 default: gcc_unreachable ();
1773 sprintf (result
, "mov%s%s\t%%0, %%%d, %%1",
1774 op
, isfp
? ".s" : "", inverted
? 3 : 2);
1780 xtensa_emit_call (int callop
, rtx
*operands
)
1782 static char result
[64];
1783 rtx tgt
= operands
[callop
];
1785 if (GET_CODE (tgt
) == CONST_INT
)
1786 sprintf (result
, "call8\t0x%lx", INTVAL (tgt
));
1787 else if (register_operand (tgt
, VOIDmode
))
1788 sprintf (result
, "callx8\t%%%d", callop
);
1790 sprintf (result
, "call8\t%%%d", callop
);
1797 xtensa_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
1799 /* Allow constant pool addresses. */
1800 if (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
1801 && ! TARGET_CONST16
&& constantpool_address_p (addr
)
1802 && ! xtensa_tls_referenced_p (addr
))
1805 while (GET_CODE (addr
) == SUBREG
)
1806 addr
= SUBREG_REG (addr
);
1808 /* Allow base registers. */
1809 if (GET_CODE (addr
) == REG
&& BASE_REG_P (addr
, strict
))
1812 /* Check for "register + offset" addressing. */
1813 if (GET_CODE (addr
) == PLUS
)
1815 rtx xplus0
= XEXP (addr
, 0);
1816 rtx xplus1
= XEXP (addr
, 1);
1817 enum rtx_code code0
;
1818 enum rtx_code code1
;
1820 while (GET_CODE (xplus0
) == SUBREG
)
1821 xplus0
= SUBREG_REG (xplus0
);
1822 code0
= GET_CODE (xplus0
);
1824 while (GET_CODE (xplus1
) == SUBREG
)
1825 xplus1
= SUBREG_REG (xplus1
);
1826 code1
= GET_CODE (xplus1
);
1828 /* Swap operands if necessary so the register is first. */
1829 if (code0
!= REG
&& code1
== REG
)
1831 xplus0
= XEXP (addr
, 1);
1832 xplus1
= XEXP (addr
, 0);
1833 code0
= GET_CODE (xplus0
);
1834 code1
= GET_CODE (xplus1
);
1837 if (code0
== REG
&& BASE_REG_P (xplus0
, strict
)
1838 && code1
== CONST_INT
1839 && xtensa_mem_offset (INTVAL (xplus1
), mode
))
1847 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1849 static GTY(()) rtx xtensa_tls_module_base_symbol
;
1852 xtensa_tls_module_base (void)
1854 if (! xtensa_tls_module_base_symbol
)
1856 xtensa_tls_module_base_symbol
=
1857 gen_rtx_SYMBOL_REF (Pmode
, "_TLS_MODULE_BASE_");
1858 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol
)
1859 |= TLS_MODEL_GLOBAL_DYNAMIC
<< SYMBOL_FLAG_TLS_SHIFT
;
1862 return xtensa_tls_module_base_symbol
;
1867 xtensa_call_tls_desc (rtx sym
, rtx
*retp
)
1869 rtx fn
, arg
, a10
, call_insn
, insns
;
1872 fn
= gen_reg_rtx (Pmode
);
1873 arg
= gen_reg_rtx (Pmode
);
1874 a10
= gen_rtx_REG (Pmode
, 10);
1876 emit_insn (gen_tls_func (fn
, sym
));
1877 emit_insn (gen_tls_arg (arg
, sym
));
1878 emit_move_insn (a10
, arg
);
1879 call_insn
= emit_call_insn (gen_tls_call (a10
, fn
, sym
, const1_rtx
));
1880 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
), a10
);
1881 insns
= get_insns ();
1890 xtensa_legitimize_tls_address (rtx x
)
1892 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
1893 rtx dest
, tp
, ret
, modbase
, base
, addend
, insns
;
1895 dest
= gen_reg_rtx (Pmode
);
1898 case TLS_MODEL_GLOBAL_DYNAMIC
:
1899 insns
= xtensa_call_tls_desc (x
, &ret
);
1900 emit_libcall_block (insns
, dest
, ret
, x
);
1903 case TLS_MODEL_LOCAL_DYNAMIC
:
1904 base
= gen_reg_rtx (Pmode
);
1905 modbase
= xtensa_tls_module_base ();
1906 insns
= xtensa_call_tls_desc (modbase
, &ret
);
1907 emit_libcall_block (insns
, base
, ret
, modbase
);
1908 addend
= force_reg (SImode
, gen_sym_DTPOFF (x
));
1909 emit_insn (gen_addsi3 (dest
, base
, addend
));
1912 case TLS_MODEL_INITIAL_EXEC
:
1913 case TLS_MODEL_LOCAL_EXEC
:
1914 tp
= gen_reg_rtx (SImode
);
1915 emit_insn (gen_get_thread_pointersi (tp
));
1916 addend
= force_reg (SImode
, gen_sym_TPOFF (x
));
1917 emit_insn (gen_addsi3 (dest
, tp
, addend
));
1929 xtensa_legitimize_address (rtx x
,
1930 rtx oldx ATTRIBUTE_UNUSED
,
1931 enum machine_mode mode
)
1933 if (xtensa_tls_symbol_p (x
))
1934 return xtensa_legitimize_tls_address (x
);
1936 if (GET_CODE (x
) == PLUS
)
1938 rtx plus0
= XEXP (x
, 0);
1939 rtx plus1
= XEXP (x
, 1);
1941 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1943 plus0
= XEXP (x
, 1);
1944 plus1
= XEXP (x
, 0);
1947 /* Try to split up the offset to use an ADDMI instruction. */
1948 if (GET_CODE (plus0
) == REG
1949 && GET_CODE (plus1
) == CONST_INT
1950 && !xtensa_mem_offset (INTVAL (plus1
), mode
)
1951 && !xtensa_simm8 (INTVAL (plus1
))
1952 && xtensa_mem_offset (INTVAL (plus1
) & 0xff, mode
)
1953 && xtensa_simm8x256 (INTVAL (plus1
) & ~0xff))
1955 rtx temp
= gen_reg_rtx (Pmode
);
1956 rtx addmi_offset
= GEN_INT (INTVAL (plus1
) & ~0xff);
1957 emit_insn (gen_rtx_SET (Pmode
, temp
,
1958 gen_rtx_PLUS (Pmode
, plus0
, addmi_offset
)));
1959 return gen_rtx_PLUS (Pmode
, temp
, GEN_INT (INTVAL (plus1
) & 0xff));
1966 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
1968 Treat constant-pool references as "mode dependent" since they can
1969 only be accessed with SImode loads. This works around a bug in the
1970 combiner where a constant pool reference is temporarily converted
1971 to an HImode load, which is then assumed to zero-extend based on
1972 our definition of LOAD_EXTEND_OP. This is wrong because the high
1973 bits of a 16-bit value in the constant pool are now sign-extended
1977 xtensa_mode_dependent_address_p (const_rtx addr
,
1978 addr_space_t as ATTRIBUTE_UNUSED
)
1980 return constantpool_address_p (addr
);
1983 /* Helper for xtensa_tls_referenced_p. */
1986 xtensa_tls_referenced_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1988 if (GET_CODE (*x
) == SYMBOL_REF
)
1989 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
1991 /* Ignore TLS references that have already been legitimized. */
1992 if (GET_CODE (*x
) == UNSPEC
)
1994 switch (XINT (*x
, 1))
1998 case UNSPEC_TLS_FUNC
:
1999 case UNSPEC_TLS_ARG
:
2000 case UNSPEC_TLS_CALL
:
2011 /* Return TRUE if X contains any TLS symbol references. */
2014 xtensa_tls_referenced_p (rtx x
)
2016 if (! TARGET_HAVE_TLS
)
2019 return for_each_rtx (&x
, xtensa_tls_referenced_p_1
, NULL
);
2023 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2026 xtensa_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2028 return xtensa_tls_referenced_p (x
);
2032 /* Return the debugger register number to use for 'regno'. */
2035 xtensa_dbx_register_number (int regno
)
2039 if (GP_REG_P (regno
))
2041 regno
-= GP_REG_FIRST
;
2044 else if (BR_REG_P (regno
))
2046 regno
-= BR_REG_FIRST
;
2049 else if (FP_REG_P (regno
))
2051 regno
-= FP_REG_FIRST
;
2054 else if (ACC_REG_P (regno
))
2056 first
= 0x200; /* Start of Xtensa special registers. */
2057 regno
= 16; /* ACCLO is special register 16. */
2060 /* When optimizing, we sometimes get asked about pseudo-registers
2061 that don't represent hard registers. Return 0 for these. */
2065 return first
+ regno
;
2069 /* Argument support functions. */
2071 /* Initialize CUMULATIVE_ARGS for a function. */
2074 init_cumulative_args (CUMULATIVE_ARGS
*cum
, int incoming
)
2077 cum
->incoming
= incoming
;
2081 /* Advance the argument to the next argument position. */
2084 xtensa_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
2085 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2090 arg_words
= &get_cumulative_args (cum
)->arg_words
;
2091 max
= MAX_ARGS_IN_REGISTERS
;
2093 words
= (((mode
!= BLKmode
)
2094 ? (int) GET_MODE_SIZE (mode
)
2095 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2097 if (*arg_words
< max
2098 && (targetm
.calls
.must_pass_in_stack (mode
, type
)
2099 || *arg_words
+ words
> max
))
2102 *arg_words
+= words
;
2106 /* Return an RTL expression containing the register for the given mode,
2107 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2108 if this is an incoming argument to the current function. */
2111 xtensa_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
2112 const_tree type
, bool incoming_p
)
2114 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2115 int regbase
, words
, max
;
2119 arg_words
= &cum
->arg_words
;
2120 regbase
= (incoming_p
? GP_ARG_FIRST
: GP_OUTGOING_ARG_FIRST
);
2121 max
= MAX_ARGS_IN_REGISTERS
;
2123 words
= (((mode
!= BLKmode
)
2124 ? (int) GET_MODE_SIZE (mode
)
2125 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2127 if (type
&& (TYPE_ALIGN (type
) > BITS_PER_WORD
))
2129 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_WORD
;
2130 *arg_words
= (*arg_words
+ align
- 1) & -align
;
2133 if (*arg_words
+ words
> max
)
2136 regno
= regbase
+ *arg_words
;
2138 if (cum
->incoming
&& regno
<= A7_REG
&& regno
+ words
> A7_REG
)
2139 cfun
->machine
->need_a7_copy
= true;
2141 return gen_rtx_REG (mode
, regno
);
2144 /* Implement TARGET_FUNCTION_ARG. */
2147 xtensa_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
2148 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2150 return xtensa_function_arg_1 (cum
, mode
, type
, false);
2153 /* Implement TARGET_FUNCTION_INCOMING_ARG. */
2156 xtensa_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
2157 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2159 return xtensa_function_arg_1 (cum
, mode
, type
, true);
2163 xtensa_function_arg_boundary (enum machine_mode mode
, const_tree type
)
2165 unsigned int alignment
;
2167 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2168 if (alignment
< PARM_BOUNDARY
)
2169 alignment
= PARM_BOUNDARY
;
2170 if (alignment
> STACK_BOUNDARY
)
2171 alignment
= STACK_BOUNDARY
;
2177 xtensa_return_in_msb (const_tree valtype
)
2179 return (TARGET_BIG_ENDIAN
2180 && AGGREGATE_TYPE_P (valtype
)
2181 && int_size_in_bytes (valtype
) >= UNITS_PER_WORD
);
2186 xtensa_option_override (void)
2189 enum machine_mode mode
;
2191 if (!TARGET_BOOLEANS
&& TARGET_HARD_FLOAT
)
2192 error ("boolean registers required for the floating-point option");
2194 /* Set up array giving whether a given register can hold a given mode. */
2195 for (mode
= VOIDmode
;
2196 mode
!= MAX_MACHINE_MODE
;
2197 mode
= (enum machine_mode
) ((int) mode
+ 1))
2199 int size
= GET_MODE_SIZE (mode
);
2200 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2202 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2206 if (ACC_REG_P (regno
))
2207 temp
= (TARGET_MAC16
2208 && (mclass
== MODE_INT
) && (size
<= UNITS_PER_WORD
));
2209 else if (GP_REG_P (regno
))
2210 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
2211 else if (FP_REG_P (regno
))
2212 temp
= (TARGET_HARD_FLOAT
&& (mode
== SFmode
));
2213 else if (BR_REG_P (regno
))
2214 temp
= (TARGET_BOOLEANS
&& (mode
== CCmode
));
2218 xtensa_hard_regno_mode_ok
[(int) mode
][regno
] = temp
;
2222 init_machine_status
= xtensa_init_machine_status
;
2224 /* Check PIC settings. PIC is only supported when using L32R
2225 instructions, and some targets need to always use PIC. */
2226 if (flag_pic
&& TARGET_CONST16
)
2227 error ("-f%s is not supported with CONST16 instructions",
2228 (flag_pic
> 1 ? "PIC" : "pic"));
2229 else if (TARGET_FORCE_NO_PIC
)
2231 else if (XTENSA_ALWAYS_PIC
)
2234 error ("PIC is required but not supported with CONST16 instructions");
2237 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2240 if (flag_pic
&& !flag_pie
)
2243 /* Hot/cold partitioning does not work on this architecture, because of
2244 constant pools (the load instruction cannot necessarily reach that far).
2245 Therefore disable it on this architecture. */
2246 if (flag_reorder_blocks_and_partition
)
2248 flag_reorder_blocks_and_partition
= 0;
2249 flag_reorder_blocks
= 1;
2253 /* A C compound statement to output to stdio stream STREAM the
2254 assembler syntax for an instruction operand X. X is an RTL
2257 CODE is a value that can be used to specify one of several ways
2258 of printing the operand. It is used when identical operands
2259 must be printed differently depending on the context. CODE
2260 comes from the '%' specification that was used to request
2261 printing of the operand. If the specification was just '%DIGIT'
2262 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2263 is the ASCII code for LTR.
2265 If X is a register, this macro should print the register's name.
2266 The names can be found in an array 'reg_names' whose type is
2267 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2269 When the machine description has a specification '%PUNCT' (a '%'
2270 followed by a punctuation character), this macro is called with
2271 a null pointer for X and the punctuation character for CODE.
2273 'a', 'c', 'l', and 'n' are reserved.
2275 The Xtensa specific codes are:
2277 'd' CONST_INT, print as signed decimal
2278 'x' CONST_INT, print as signed hexadecimal
2279 'K' CONST_INT, print number of bits in mask for EXTUI
2280 'R' CONST_INT, print (X & 0x1f)
2281 'L' CONST_INT, print ((32 - X) & 0x1f)
2282 'D' REG, print second register of double-word register operand
2283 'N' MEM, print address of next word following a memory operand
2284 'v' MEM, if memory reference is volatile, output a MEMW before it
2285 't' any constant, add "@h" suffix for top 16 bits
2286 'b' any constant, add "@l" suffix for bottom 16 bits
2290 printx (FILE *file
, signed int val
)
2292 /* Print a hexadecimal value in a nice way. */
2293 if ((val
> -0xa) && (val
< 0xa))
2294 fprintf (file
, "%d", val
);
2296 fprintf (file
, "-0x%x", -val
);
2298 fprintf (file
, "0x%x", val
);
2303 print_operand (FILE *file
, rtx x
, int letter
)
2306 error ("PRINT_OPERAND null pointer");
2311 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2312 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
) + 1]);
2314 output_operand_lossage ("invalid %%D value");
2318 if (GET_CODE (x
) == MEM
)
2320 /* For a volatile memory reference, emit a MEMW before the
2322 if (MEM_VOLATILE_P (x
) && TARGET_SERIALIZE_VOLATILE
)
2323 fprintf (file
, "memw\n\t");
2326 output_operand_lossage ("invalid %%v value");
2330 if (GET_CODE (x
) == MEM
2331 && (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DImode
))
2333 x
= adjust_address (x
, GET_MODE (x
) == DFmode
? SFmode
: SImode
, 4);
2334 output_address (XEXP (x
, 0));
2337 output_operand_lossage ("invalid %%N value");
2341 if (GET_CODE (x
) == CONST_INT
)
2344 unsigned val
= INTVAL (x
);
2350 if ((val
!= 0) || (num_bits
== 0) || (num_bits
> 16))
2351 fatal_insn ("invalid mask", x
);
2353 fprintf (file
, "%d", num_bits
);
2356 output_operand_lossage ("invalid %%K value");
2360 if (GET_CODE (x
) == CONST_INT
)
2361 fprintf (file
, "%ld", (32 - INTVAL (x
)) & 0x1f);
2363 output_operand_lossage ("invalid %%L value");
2367 if (GET_CODE (x
) == CONST_INT
)
2368 fprintf (file
, "%ld", INTVAL (x
) & 0x1f);
2370 output_operand_lossage ("invalid %%R value");
2374 if (GET_CODE (x
) == CONST_INT
)
2375 printx (file
, INTVAL (x
));
2377 output_operand_lossage ("invalid %%x value");
2381 if (GET_CODE (x
) == CONST_INT
)
2382 fprintf (file
, "%ld", INTVAL (x
));
2384 output_operand_lossage ("invalid %%d value");
2389 if (GET_CODE (x
) == CONST_INT
)
2391 printx (file
, INTVAL (x
));
2392 fputs (letter
== 't' ? "@h" : "@l", file
);
2394 else if (GET_CODE (x
) == CONST_DOUBLE
)
2397 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2398 if (GET_MODE (x
) == SFmode
)
2401 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
2402 fprintf (file
, "0x%08lx@%c", l
, letter
== 't' ? 'h' : 'l');
2405 output_operand_lossage ("invalid %%t/%%b value");
2407 else if (GET_CODE (x
) == CONST
)
2409 /* X must be a symbolic constant on ELF. Write an expression
2410 suitable for 'const16' that sets the high or low 16 bits. */
2411 if (GET_CODE (XEXP (x
, 0)) != PLUS
2412 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
2413 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
2414 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
2415 output_operand_lossage ("invalid %%t/%%b value");
2416 print_operand (file
, XEXP (XEXP (x
, 0), 0), 0);
2417 fputs (letter
== 't' ? "@h" : "@l", file
);
2418 /* There must be a non-alphanumeric character between 'h' or 'l'
2419 and the number. The '-' is added by print_operand() already. */
2420 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
2422 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
2426 output_addr_const (file
, x
);
2427 fputs (letter
== 't' ? "@h" : "@l", file
);
2432 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2433 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
)]);
2434 else if (GET_CODE (x
) == MEM
)
2435 output_address (XEXP (x
, 0));
2436 else if (GET_CODE (x
) == CONST_INT
)
2437 fprintf (file
, "%ld", INTVAL (x
));
2439 output_addr_const (file
, x
);
2444 /* A C compound statement to output to stdio stream STREAM the
2445 assembler syntax for an instruction operand that is a memory
2446 reference whose address is ADDR. ADDR is an RTL expression. */
2449 print_operand_address (FILE *file
, rtx addr
)
2452 error ("PRINT_OPERAND_ADDRESS, null pointer");
2454 switch (GET_CODE (addr
))
2457 fatal_insn ("invalid address", addr
);
2461 fprintf (file
, "%s, 0", reg_names
[REGNO (addr
)]);
2467 rtx offset
= (rtx
)0;
2468 rtx arg0
= XEXP (addr
, 0);
2469 rtx arg1
= XEXP (addr
, 1);
2471 if (GET_CODE (arg0
) == REG
)
2476 else if (GET_CODE (arg1
) == REG
)
2482 fatal_insn ("no register in address", addr
);
2484 if (CONSTANT_P (offset
))
2486 fprintf (file
, "%s, ", reg_names
[REGNO (reg
)]);
2487 output_addr_const (file
, offset
);
2490 fatal_insn ("address offset not a constant", addr
);
2498 output_addr_const (file
, addr
);
2503 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
2506 xtensa_output_addr_const_extra (FILE *fp
, rtx x
)
2508 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
2510 switch (XINT (x
, 1))
2513 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2514 fputs ("@TPOFF", fp
);
2517 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2518 fputs ("@DTPOFF", fp
);
2523 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2537 xtensa_output_literal (FILE *file
, rtx x
, enum machine_mode mode
, int labelno
)
2544 fprintf (file
, "\t.literal .LC%u, ", (unsigned) labelno
);
2546 switch (GET_MODE_CLASS (mode
))
2549 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
);
2551 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2555 REAL_VALUE_TO_TARGET_SINGLE (r
, value_long
[0]);
2556 if (HOST_BITS_PER_LONG
> 32)
2557 value_long
[0] &= 0xffffffff;
2558 fprintf (file
, "0x%08lx\n", value_long
[0]);
2562 REAL_VALUE_TO_TARGET_DOUBLE (r
, value_long
);
2563 if (HOST_BITS_PER_LONG
> 32)
2565 value_long
[0] &= 0xffffffff;
2566 value_long
[1] &= 0xffffffff;
2568 fprintf (file
, "0x%08lx, 0x%08lx\n",
2569 value_long
[0], value_long
[1]);
2579 case MODE_PARTIAL_INT
:
2580 size
= GET_MODE_SIZE (mode
);
2584 output_addr_const (file
, x
);
2589 split_double (x
, &first
, &second
);
2590 output_addr_const (file
, first
);
2592 output_addr_const (file
, second
);
2607 /* Return the bytes needed to compute the frame pointer from the current
2610 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2611 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2614 compute_frame_size (int size
)
2616 /* Add space for the incoming static chain value. */
2617 if (cfun
->static_chain_decl
!= NULL
)
2618 size
+= (1 * UNITS_PER_WORD
);
2620 xtensa_current_frame_size
=
2621 XTENSA_STACK_ALIGN (size
2622 + crtl
->outgoing_args_size
2623 + (WINDOW_SIZE
* UNITS_PER_WORD
));
2624 return xtensa_current_frame_size
;
2629 xtensa_frame_pointer_required (void)
2631 /* The code to expand builtin_frame_addr and builtin_return_addr
2632 currently uses the hard_frame_pointer instead of frame_pointer.
2633 This seems wrong but maybe it's necessary for other architectures.
2634 This function is derived from the i386 code. */
2636 if (cfun
->machine
->accesses_prev_frame
)
2643 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2644 and the total number of words must be a multiple of 128 bits. */
2645 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2648 xtensa_expand_prologue (void)
2650 HOST_WIDE_INT total_size
;
2654 total_size
= compute_frame_size (get_frame_size ());
2655 size_rtx
= GEN_INT (total_size
);
2657 if (total_size
< (1 << (12+3)))
2658 insn
= emit_insn (gen_entry (size_rtx
));
2661 /* Use a8 as a temporary since a0-a7 may be live. */
2662 rtx tmp_reg
= gen_rtx_REG (Pmode
, A8_REG
);
2663 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE
)));
2664 emit_move_insn (tmp_reg
, GEN_INT (total_size
- MIN_FRAME_SIZE
));
2665 emit_insn (gen_subsi3 (tmp_reg
, stack_pointer_rtx
, tmp_reg
));
2666 insn
= emit_insn (gen_movsi (stack_pointer_rtx
, tmp_reg
));
2669 if (frame_pointer_needed
)
2671 if (cfun
->machine
->set_frame_ptr_insn
)
2675 push_topmost_sequence ();
2676 first
= get_insns ();
2677 pop_topmost_sequence ();
2679 /* For all instructions prior to set_frame_ptr_insn, replace
2680 hard_frame_pointer references with stack_pointer. */
2682 insn
!= cfun
->machine
->set_frame_ptr_insn
;
2683 insn
= NEXT_INSN (insn
))
2687 PATTERN (insn
) = replace_rtx (copy_rtx (PATTERN (insn
)),
2688 hard_frame_pointer_rtx
,
2690 df_insn_rescan (insn
);
2695 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
2696 stack_pointer_rtx
));
2699 /* Create a note to describe the CFA. Because this is only used to set
2700 DW_AT_frame_base for debug info, don't bother tracking changes through
2701 each instruction in the prologue. It just takes up space. */
2702 note_rtx
= gen_rtx_SET (VOIDmode
, (frame_pointer_needed
2703 ? hard_frame_pointer_rtx
2704 : stack_pointer_rtx
),
2705 plus_constant (Pmode
, stack_pointer_rtx
,
2707 RTX_FRAME_RELATED_P (insn
) = 1;
2708 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note_rtx
);
2712 /* Clear variables at function end. */
2715 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
2716 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
2718 xtensa_current_frame_size
= 0;
2723 xtensa_return_addr (int count
, rtx frame
)
2725 rtx result
, retaddr
, curaddr
, label
;
2728 retaddr
= gen_rtx_REG (Pmode
, A0_REG
);
2731 rtx addr
= plus_constant (Pmode
, frame
, -4 * UNITS_PER_WORD
);
2732 addr
= memory_address (Pmode
, addr
);
2733 retaddr
= gen_reg_rtx (Pmode
);
2734 emit_move_insn (retaddr
, gen_rtx_MEM (Pmode
, addr
));
2737 /* The 2 most-significant bits of the return address on Xtensa hold
2738 the register window size. To get the real return address, these
2739 bits must be replaced with the high bits from some address in the
2742 /* Get the 2 high bits of a local label in the code. */
2743 curaddr
= gen_reg_rtx (Pmode
);
2744 label
= gen_label_rtx ();
2746 LABEL_PRESERVE_P (label
) = 1;
2747 emit_move_insn (curaddr
, gen_rtx_LABEL_REF (Pmode
, label
));
2748 emit_insn (gen_lshrsi3 (curaddr
, curaddr
, GEN_INT (30)));
2749 emit_insn (gen_ashlsi3 (curaddr
, curaddr
, GEN_INT (30)));
2751 /* Clear the 2 high bits of the return address. */
2752 result
= gen_reg_rtx (Pmode
);
2753 emit_insn (gen_ashlsi3 (result
, retaddr
, GEN_INT (2)));
2754 emit_insn (gen_lshrsi3 (result
, result
, GEN_INT (2)));
2756 /* Combine them to get the result. */
2757 emit_insn (gen_iorsi3 (result
, result
, curaddr
));
2761 /* Disable the use of word-sized or smaller complex modes for structures,
2762 and for function arguments in particular, where they cause problems with
2763 register a7. The xtensa_copy_incoming_a7 function assumes that there is
2764 a single reference to an argument in a7, but with small complex modes the
2765 real and imaginary components may be extracted separately, leading to two
2766 uses of the register, only one of which would be replaced. */
2769 xtensa_member_type_forces_blk (const_tree
, enum machine_mode mode
)
2771 return mode
== CQImode
|| mode
== CHImode
;
2774 /* Create the va_list data type.
2776 This structure is set up by __builtin_saveregs. The __va_reg field
2777 points to a stack-allocated region holding the contents of the
2778 incoming argument registers. The __va_ndx field is an index
2779 initialized to the position of the first unnamed (variable)
2780 argument. This same index is also used to address the arguments
2781 passed in memory. Thus, the __va_stk field is initialized to point
2782 to the position of the first argument in memory offset to account
2783 for the arguments passed in registers and to account for the size
2784 of the argument registers not being 16-byte aligned. E.G., there
2785 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2786 for the first stack argument to have the maximal alignment of 16
2787 bytes, so we offset the __va_stk address by 32 bytes so that
2788 __va_stk[32] references the first argument on the stack. */
2791 xtensa_build_builtin_va_list (void)
2793 tree f_stk
, f_reg
, f_ndx
, record
, type_decl
;
2795 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
2796 type_decl
= build_decl (BUILTINS_LOCATION
,
2797 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
2799 f_stk
= build_decl (BUILTINS_LOCATION
,
2800 FIELD_DECL
, get_identifier ("__va_stk"),
2802 f_reg
= build_decl (BUILTINS_LOCATION
,
2803 FIELD_DECL
, get_identifier ("__va_reg"),
2805 f_ndx
= build_decl (BUILTINS_LOCATION
,
2806 FIELD_DECL
, get_identifier ("__va_ndx"),
2809 DECL_FIELD_CONTEXT (f_stk
) = record
;
2810 DECL_FIELD_CONTEXT (f_reg
) = record
;
2811 DECL_FIELD_CONTEXT (f_ndx
) = record
;
2813 TYPE_STUB_DECL (record
) = type_decl
;
2814 TYPE_NAME (record
) = type_decl
;
2815 TYPE_FIELDS (record
) = f_stk
;
2816 DECL_CHAIN (f_stk
) = f_reg
;
2817 DECL_CHAIN (f_reg
) = f_ndx
;
2819 layout_type (record
);
2824 /* Save the incoming argument registers on the stack. Returns the
2825 address of the saved registers. */
2828 xtensa_builtin_saveregs (void)
2831 int arg_words
= crtl
->args
.info
.arg_words
;
2832 int gp_left
= MAX_ARGS_IN_REGISTERS
- arg_words
;
2837 /* Allocate the general-purpose register space. */
2838 gp_regs
= assign_stack_local
2839 (BLKmode
, MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
, -1);
2840 set_mem_alias_set (gp_regs
, get_varargs_alias_set ());
2842 /* Now store the incoming registers. */
2843 cfun
->machine
->need_a7_copy
= true;
2844 cfun
->machine
->vararg_a7
= true;
2845 move_block_from_reg (GP_ARG_FIRST
+ arg_words
,
2846 adjust_address (gp_regs
, BLKmode
,
2847 arg_words
* UNITS_PER_WORD
),
2849 gcc_assert (cfun
->machine
->vararg_a7_copy
!= 0);
2850 emit_insn_before (cfun
->machine
->vararg_a7_copy
, get_insns ());
2852 return XEXP (gp_regs
, 0);
2856 /* Implement `va_start' for varargs and stdarg. We look at the
2857 current function to fill in an initial va_list. */
2860 xtensa_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
2868 arg_words
= crtl
->args
.info
.arg_words
;
2870 f_stk
= TYPE_FIELDS (va_list_type_node
);
2871 f_reg
= DECL_CHAIN (f_stk
);
2872 f_ndx
= DECL_CHAIN (f_reg
);
2874 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
2875 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), unshare_expr (valist
),
2877 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), unshare_expr (valist
),
2880 /* Call __builtin_saveregs; save the result in __va_reg */
2881 u
= make_tree (sizetype
, expand_builtin_saveregs ());
2882 u
= fold_convert (ptr_type_node
, u
);
2883 t
= build2 (MODIFY_EXPR
, ptr_type_node
, reg
, u
);
2884 TREE_SIDE_EFFECTS (t
) = 1;
2885 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2887 /* Set the __va_stk member to ($arg_ptr - 32). */
2888 u
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
2889 u
= fold_build_pointer_plus_hwi (u
, -32);
2890 t
= build2 (MODIFY_EXPR
, ptr_type_node
, stk
, u
);
2891 TREE_SIDE_EFFECTS (t
) = 1;
2892 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2894 /* Set the __va_ndx member. If the first variable argument is on
2895 the stack, adjust __va_ndx by 2 words to account for the extra
2896 alignment offset for __va_stk. */
2897 if (arg_words
>= MAX_ARGS_IN_REGISTERS
)
2899 t
= build2 (MODIFY_EXPR
, integer_type_node
, ndx
,
2900 build_int_cst (integer_type_node
, arg_words
* UNITS_PER_WORD
));
2901 TREE_SIDE_EFFECTS (t
) = 1;
2902 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2906 /* Implement `va_arg'. */
2909 xtensa_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
2910 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
2915 tree type_size
, array
, orig_ndx
, addr
, size
, va_size
, t
;
2916 tree lab_false
, lab_over
, lab_false2
;
2919 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
2921 type
= build_pointer_type (type
);
2923 /* Handle complex values as separate real and imaginary parts. */
2924 if (TREE_CODE (type
) == COMPLEX_TYPE
)
2926 tree real_part
, imag_part
;
2928 real_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
2930 real_part
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
2932 imag_part
= xtensa_gimplify_va_arg_expr (unshare_expr (valist
),
2935 imag_part
= get_initialized_tmp_var (imag_part
, pre_p
, NULL
);
2937 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
2940 f_stk
= TYPE_FIELDS (va_list_type_node
);
2941 f_reg
= DECL_CHAIN (f_stk
);
2942 f_ndx
= DECL_CHAIN (f_reg
);
2944 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
,
2946 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), unshare_expr (valist
),
2948 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), unshare_expr (valist
),
2951 type_size
= size_in_bytes (type
);
2952 va_size
= round_up (type_size
, UNITS_PER_WORD
);
2953 gimplify_expr (&va_size
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
2956 /* First align __va_ndx if necessary for this arg:
2958 orig_ndx = (AP).__va_ndx;
2959 if (__alignof__ (TYPE) > 4 )
2960 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2961 & -__alignof__ (TYPE)); */
2963 orig_ndx
= get_initialized_tmp_var (ndx
, pre_p
, NULL
);
2965 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
2967 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_UNIT
;
2969 t
= build2 (PLUS_EXPR
, integer_type_node
, unshare_expr (orig_ndx
),
2970 build_int_cst (integer_type_node
, align
- 1));
2971 t
= build2 (BIT_AND_EXPR
, integer_type_node
, t
,
2972 build_int_cst (integer_type_node
, -align
));
2973 gimplify_assign (unshare_expr (orig_ndx
), t
, pre_p
);
2977 /* Increment __va_ndx to point past the argument:
2979 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2981 t
= fold_convert (integer_type_node
, va_size
);
2982 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
, t
);
2983 gimplify_assign (unshare_expr (ndx
), t
, pre_p
);
2986 /* Check if the argument is in registers:
2988 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2989 && !must_pass_in_stack (type))
2990 __array = (AP).__va_reg; */
2992 array
= create_tmp_var (ptr_type_node
, NULL
);
2995 if (!targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
2997 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
2998 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
3000 t
= build2 (GT_EXPR
, boolean_type_node
, unshare_expr (ndx
),
3001 build_int_cst (integer_type_node
,
3002 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
3003 t
= build3 (COND_EXPR
, void_type_node
, t
,
3004 build1 (GOTO_EXPR
, void_type_node
, lab_false
),
3006 gimplify_and_add (t
, pre_p
);
3008 gimplify_assign (unshare_expr (array
), reg
, pre_p
);
3010 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
3011 gimplify_and_add (t
, pre_p
);
3013 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
3014 gimplify_and_add (t
, pre_p
);
3018 /* ...otherwise, the argument is on the stack (never split between
3019 registers and the stack -- change __va_ndx if necessary):
3023 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
3024 (AP).__va_ndx = 32 + __va_size (TYPE);
3025 __array = (AP).__va_stk;
3028 lab_false2
= create_artificial_label (UNKNOWN_LOCATION
);
3030 t
= build2 (GT_EXPR
, boolean_type_node
, unshare_expr (orig_ndx
),
3031 build_int_cst (integer_type_node
,
3032 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
3033 t
= build3 (COND_EXPR
, void_type_node
, t
,
3034 build1 (GOTO_EXPR
, void_type_node
, lab_false2
),
3036 gimplify_and_add (t
, pre_p
);
3038 t
= size_binop (PLUS_EXPR
, unshare_expr (va_size
), size_int (32));
3039 t
= fold_convert (integer_type_node
, t
);
3040 gimplify_assign (unshare_expr (ndx
), t
, pre_p
);
3042 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false2
);
3043 gimplify_and_add (t
, pre_p
);
3045 gimplify_assign (array
, stk
, pre_p
);
3049 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
3050 gimplify_and_add (t
, pre_p
);
3054 /* Given the base array pointer (__array) and index to the subsequent
3055 argument (__va_ndx), find the address:
3057 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
3061 The results are endian-dependent because values smaller than one word
3062 are aligned differently. */
3065 if (BYTES_BIG_ENDIAN
&& TREE_CODE (type_size
) == INTEGER_CST
)
3067 t
= fold_build2 (GE_EXPR
, boolean_type_node
, unshare_expr (type_size
),
3068 size_int (PARM_BOUNDARY
/ BITS_PER_UNIT
));
3069 t
= fold_build3 (COND_EXPR
, sizetype
, t
, unshare_expr (va_size
),
3070 unshare_expr (type_size
));
3074 size
= unshare_expr (va_size
);
3076 t
= fold_convert (sizetype
, unshare_expr (ndx
));
3077 t
= build2 (MINUS_EXPR
, sizetype
, t
, size
);
3078 addr
= fold_build_pointer_plus (unshare_expr (array
), t
);
3080 addr
= fold_convert (build_pointer_type (type
), addr
);
3082 addr
= build_va_arg_indirect_ref (addr
);
3083 return build_va_arg_indirect_ref (addr
);
3091 XTENSA_BUILTIN_UMULSIDI3
,
3097 xtensa_init_builtins (void)
3101 ftype
= build_function_type_list (unsigned_intDI_type_node
,
3102 unsigned_intSI_type_node
,
3103 unsigned_intSI_type_node
, NULL_TREE
);
3105 decl
= add_builtin_function ("__builtin_umulsidi3", ftype
,
3106 XTENSA_BUILTIN_UMULSIDI3
, BUILT_IN_MD
,
3107 "__umulsidi3", NULL_TREE
);
3108 TREE_NOTHROW (decl
) = 1;
3109 TREE_READONLY (decl
) = 1;
3114 xtensa_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
, tree
*args
,
3115 bool ignore ATTRIBUTE_UNUSED
)
3117 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
3122 case XTENSA_BUILTIN_UMULSIDI3
:
3125 if ((TREE_CODE (arg0
) == INTEGER_CST
&& TREE_CODE (arg1
) == INTEGER_CST
)
3126 || TARGET_MUL32_HIGH
)
3127 return fold_build2 (MULT_EXPR
, unsigned_intDI_type_node
,
3128 fold_convert (unsigned_intDI_type_node
, arg0
),
3129 fold_convert (unsigned_intDI_type_node
, arg1
));
3133 internal_error ("bad builtin code");
3142 xtensa_expand_builtin (tree exp
, rtx target
,
3143 rtx subtarget ATTRIBUTE_UNUSED
,
3144 enum machine_mode mode ATTRIBUTE_UNUSED
,
3147 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
3148 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
3152 case XTENSA_BUILTIN_UMULSIDI3
:
3153 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3154 __umulsidi3 function when the Xtensa configuration can directly
3155 implement it. If not, just call the function. */
3156 return expand_call (exp
, target
, ignore
);
3159 internal_error ("bad builtin code");
3164 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. */
3167 xtensa_preferred_reload_class (rtx x
, reg_class_t rclass
)
3169 if (CONSTANT_P (x
) && CONST_DOUBLE_P (x
))
3172 /* Don't use the stack pointer or hard frame pointer for reloads!
3173 The hard frame pointer would normally be OK except that it may
3174 briefly hold an incoming argument in the prologue, and reload
3175 won't know that it is live because the hard frame pointer is
3176 treated specially. */
3178 if (rclass
== AR_REGS
|| rclass
== GR_REGS
)
3184 /* Worker function for TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
3187 xtensa_preferred_output_reload_class (rtx x ATTRIBUTE_UNUSED
,
3190 /* Don't use the stack pointer or hard frame pointer for reloads!
3191 The hard frame pointer would normally be OK except that it may
3192 briefly hold an incoming argument in the prologue, and reload
3193 won't know that it is live because the hard frame pointer is
3194 treated specially. */
3196 if (rclass
== AR_REGS
|| rclass
== GR_REGS
)
3202 /* Worker function for TARGET_SECONDARY_RELOAD. */
3205 xtensa_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass
,
3206 enum machine_mode mode
, secondary_reload_info
*sri
)
3210 if (in_p
&& constantpool_mem_p (x
))
3212 if (rclass
== FP_REGS
)
3216 sri
->icode
= CODE_FOR_reloadqi_literal
;
3217 else if (mode
== HImode
)
3218 sri
->icode
= CODE_FOR_reloadhi_literal
;
3221 regno
= xt_true_regnum (x
);
3222 if (ACC_REG_P (regno
))
3223 return ((rclass
== GR_REGS
|| rclass
== RL_REGS
) ? NO_REGS
: RL_REGS
);
3224 if (rclass
== ACC_REG
)
3225 return (GP_REG_P (regno
) ? NO_REGS
: RL_REGS
);
3232 order_regs_for_local_alloc (void)
3234 if (!leaf_function_p ())
3236 memcpy (reg_alloc_order
, reg_nonleaf_alloc_order
,
3237 FIRST_PSEUDO_REGISTER
* sizeof (int));
3241 int i
, num_arg_regs
;
3244 /* Use the AR registers in increasing order (skipping a0 and a1)
3245 but save the incoming argument registers for a last resort. */
3246 num_arg_regs
= crtl
->args
.info
.arg_words
;
3247 if (num_arg_regs
> MAX_ARGS_IN_REGISTERS
)
3248 num_arg_regs
= MAX_ARGS_IN_REGISTERS
;
3249 for (i
= GP_ARG_FIRST
; i
< 16 - num_arg_regs
; i
++)
3250 reg_alloc_order
[nxt
++] = i
+ num_arg_regs
;
3251 for (i
= 0; i
< num_arg_regs
; i
++)
3252 reg_alloc_order
[nxt
++] = GP_ARG_FIRST
+ i
;
3254 /* List the coprocessor registers in order. */
3255 for (i
= 0; i
< BR_REG_NUM
; i
++)
3256 reg_alloc_order
[nxt
++] = BR_REG_FIRST
+ i
;
3258 /* List the FP registers in order for now. */
3259 for (i
= 0; i
< 16; i
++)
3260 reg_alloc_order
[nxt
++] = FP_REG_FIRST
+ i
;
3262 /* GCC requires that we list *all* the registers.... */
3263 reg_alloc_order
[nxt
++] = 0; /* a0 = return address */
3264 reg_alloc_order
[nxt
++] = 1; /* a1 = stack pointer */
3265 reg_alloc_order
[nxt
++] = 16; /* pseudo frame pointer */
3266 reg_alloc_order
[nxt
++] = 17; /* pseudo arg pointer */
3268 reg_alloc_order
[nxt
++] = ACC_REG_FIRST
; /* MAC16 accumulator */
3273 /* Some Xtensa targets support multiple bss sections. If the section
3274 name ends with ".bss", add SECTION_BSS to the flags. */
3277 xtensa_multibss_section_type_flags (tree decl
, const char *name
, int reloc
)
3279 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
3282 suffix
= strrchr (name
, '.');
3283 if (suffix
&& strcmp (suffix
, ".bss") == 0)
3285 if (!decl
|| (TREE_CODE (decl
) == VAR_DECL
3286 && DECL_INITIAL (decl
) == NULL_TREE
))
3287 flags
|= SECTION_BSS
; /* @nobits */
3289 warning (0, "only uninitialized variables can be placed in a "
3297 /* The literal pool stays with the function. */
3300 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED
,
3301 rtx x ATTRIBUTE_UNUSED
,
3302 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
3304 return function_section (current_function_decl
);
3307 /* Worker function for TARGET_REGISTER_MOVE_COST. */
3310 xtensa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
3311 reg_class_t from
, reg_class_t to
)
3313 if (from
== to
&& from
!= BR_REGS
&& to
!= BR_REGS
)
3315 else if (reg_class_subset_p (from
, AR_REGS
)
3316 && reg_class_subset_p (to
, AR_REGS
))
3318 else if (reg_class_subset_p (from
, AR_REGS
) && to
== ACC_REG
)
3320 else if (from
== ACC_REG
&& reg_class_subset_p (to
, AR_REGS
))
3326 /* Worker function for TARGET_MEMORY_MOVE_COST. */
3329 xtensa_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
3330 reg_class_t rclass ATTRIBUTE_UNUSED
,
3331 bool in ATTRIBUTE_UNUSED
)
3336 /* Compute a (partial) cost for rtx X. Return true if the complete
3337 cost has been computed, and false if subexpressions should be
3338 scanned. In either case, *TOTAL contains the cost result. */
3341 xtensa_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3342 int *total
, bool speed ATTRIBUTE_UNUSED
)
3350 if (xtensa_simm12b (INTVAL (x
)))
3357 if (xtensa_simm8 (INTVAL (x
))
3358 || xtensa_simm8x256 (INTVAL (x
)))
3365 if (xtensa_mask_immediate (INTVAL (x
)))
3372 if ((INTVAL (x
) == 0) || xtensa_b4const (INTVAL (x
)))
3383 /* No way to tell if X is the 2nd operand so be conservative. */
3386 if (xtensa_simm12b (INTVAL (x
)))
3388 else if (TARGET_CONST16
)
3389 *total
= COSTS_N_INSNS (2);
3398 *total
= COSTS_N_INSNS (2);
3405 *total
= COSTS_N_INSNS (4);
3413 (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
) ? 2 : 1;
3415 if (memory_address_p (GET_MODE (x
), XEXP ((x
), 0)))
3416 *total
= COSTS_N_INSNS (num_words
);
3418 *total
= COSTS_N_INSNS (2*num_words
);
3424 *total
= COSTS_N_INSNS (TARGET_NSA
? 5 : 50);
3428 *total
= COSTS_N_INSNS (TARGET_NSA
? 1 : 50);
3432 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 3 : 2);
3438 if (GET_MODE (x
) == DImode
)
3439 *total
= COSTS_N_INSNS (2);
3441 *total
= COSTS_N_INSNS (1);
3447 if (GET_MODE (x
) == DImode
)
3448 *total
= COSTS_N_INSNS (50);
3450 *total
= COSTS_N_INSNS (1);
3455 enum machine_mode xmode
= GET_MODE (x
);
3456 if (xmode
== SFmode
)
3457 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3458 else if (xmode
== DFmode
)
3459 *total
= COSTS_N_INSNS (50);
3461 *total
= COSTS_N_INSNS (4);
3468 enum machine_mode xmode
= GET_MODE (x
);
3469 if (xmode
== SFmode
)
3470 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3471 else if (xmode
== DFmode
|| xmode
== DImode
)
3472 *total
= COSTS_N_INSNS (50);
3474 *total
= COSTS_N_INSNS (1);
3479 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 4 : 2);
3484 enum machine_mode xmode
= GET_MODE (x
);
3485 if (xmode
== SFmode
)
3486 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 4 : 50);
3487 else if (xmode
== DFmode
)
3488 *total
= COSTS_N_INSNS (50);
3489 else if (xmode
== DImode
)
3490 *total
= COSTS_N_INSNS (TARGET_MUL32_HIGH
? 10 : 50);
3491 else if (TARGET_MUL32
)
3492 *total
= COSTS_N_INSNS (4);
3493 else if (TARGET_MAC16
)
3494 *total
= COSTS_N_INSNS (16);
3495 else if (TARGET_MUL16
)
3496 *total
= COSTS_N_INSNS (12);
3498 *total
= COSTS_N_INSNS (50);
3505 enum machine_mode xmode
= GET_MODE (x
);
3506 if (xmode
== SFmode
)
3508 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV
? 8 : 50);
3511 else if (xmode
== DFmode
)
3513 *total
= COSTS_N_INSNS (50);
3522 enum machine_mode xmode
= GET_MODE (x
);
3523 if (xmode
== DImode
)
3524 *total
= COSTS_N_INSNS (50);
3525 else if (TARGET_DIV32
)
3526 *total
= COSTS_N_INSNS (32);
3528 *total
= COSTS_N_INSNS (50);
3533 if (GET_MODE (x
) == SFmode
)
3534 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT
? 8 : 50);
3536 *total
= COSTS_N_INSNS (50);
3543 *total
= COSTS_N_INSNS (TARGET_MINMAX
? 1 : 50);
3548 *total
= COSTS_N_INSNS (TARGET_SEXT
? 1 : 2);
3553 *total
= COSTS_N_INSNS (1);
3561 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3564 xtensa_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3566 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)
3567 > 4 * UNITS_PER_WORD
);
3570 /* Worker function for TARGET_FUNCTION_VALUE. */
3573 xtensa_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
3576 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype
)
3577 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
3578 ? SImode
: TYPE_MODE (valtype
),
3579 outgoing
? GP_OUTGOING_RETURN
: GP_RETURN
);
3582 /* Worker function for TARGET_LIBCALL_VALUE. */
3585 xtensa_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
3587 return gen_rtx_REG ((GET_MODE_CLASS (mode
) == MODE_INT
3588 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3589 ? SImode
: mode
, GP_RETURN
);
3592 /* Worker function TARGET_FUNCTION_VALUE_REGNO_P. */
3595 xtensa_function_value_regno_p (const unsigned int regno
)
3597 return (regno
== GP_RETURN
);
3600 /* The static chain is passed in memory. Provide rtx giving 'mem'
3601 expressions that denote where they are stored. */
3604 xtensa_static_chain (const_tree
ARG_UNUSED (fndecl
), bool incoming_p
)
3606 rtx base
= incoming_p
? arg_pointer_rtx
: stack_pointer_rtx
;
3607 return gen_frame_mem (Pmode
, plus_constant (Pmode
, base
,
3608 -5 * UNITS_PER_WORD
));
3612 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3613 instruction with a minimal stack frame in order to get some free
3614 registers. Once the actual call target is known, the proper stack frame
3615 size is extracted from the ENTRY instruction at the target and the
3616 current frame is adjusted to match. The trampoline then transfers
3617 control to the instruction following the ENTRY at the target. Note:
3618 this assumes that the target begins with an ENTRY instruction. */
3621 xtensa_asm_trampoline_template (FILE *stream
)
3623 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3625 fprintf (stream
, "\t.begin no-transform\n");
3626 fprintf (stream
, "\tentry\tsp, %d\n", MIN_FRAME_SIZE
);
3630 /* Save the return address. */
3631 fprintf (stream
, "\tmov\ta10, a0\n");
3633 /* Use a CALL0 instruction to skip past the constants and in the
3634 process get the PC into A0. This allows PC-relative access to
3635 the constants without relying on L32R. */
3636 fprintf (stream
, "\tcall0\t.Lskipconsts\n");
3639 fprintf (stream
, "\tj\t.Lskipconsts\n");
3641 fprintf (stream
, "\t.align\t4\n");
3642 fprintf (stream
, ".Lchainval:%s0\n", integer_asm_op (4, TRUE
));
3643 fprintf (stream
, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE
));
3644 fprintf (stream
, ".Lskipconsts:\n");
3646 /* Load the static chain and function address from the trampoline. */
3649 fprintf (stream
, "\taddi\ta0, a0, 3\n");
3650 fprintf (stream
, "\tl32i\ta9, a0, 0\n");
3651 fprintf (stream
, "\tl32i\ta8, a0, 4\n");
3655 fprintf (stream
, "\tl32r\ta9, .Lchainval\n");
3656 fprintf (stream
, "\tl32r\ta8, .Lfnaddr\n");
3659 /* Store the static chain. */
3660 fprintf (stream
, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE
- 20);
3662 /* Set the proper stack pointer value. */
3663 fprintf (stream
, "\tl32i\ta9, a8, 0\n");
3664 fprintf (stream
, "\textui\ta9, a9, %d, 12\n",
3665 TARGET_BIG_ENDIAN
? 8 : 12);
3666 fprintf (stream
, "\tslli\ta9, a9, 3\n");
3667 fprintf (stream
, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE
);
3668 fprintf (stream
, "\tsub\ta9, sp, a9\n");
3669 fprintf (stream
, "\tmovsp\tsp, a9\n");
3672 /* Restore the return address. */
3673 fprintf (stream
, "\tmov\ta0, a10\n");
3675 /* Jump to the instruction following the ENTRY. */
3676 fprintf (stream
, "\taddi\ta8, a8, 3\n");
3677 fprintf (stream
, "\tjx\ta8\n");
3679 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3681 fprintf (stream
, "\t.byte\t0\n");
3683 fprintf (stream
, "\tnop\n");
3685 fprintf (stream
, "\t.end no-transform\n");
3689 xtensa_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain
)
3691 rtx func
= XEXP (DECL_RTL (fndecl
), 0);
3692 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3693 int chain_off
= use_call0
? 12 : 8;
3694 int func_off
= use_call0
? 16 : 12;
3696 emit_block_move (m_tramp
, assemble_trampoline_template (),
3697 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
3699 emit_move_insn (adjust_address (m_tramp
, SImode
, chain_off
), chain
);
3700 emit_move_insn (adjust_address (m_tramp
, SImode
, func_off
), func
);
3701 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_sync_caches"),
3702 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
3705 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
3708 xtensa_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3710 return !xtensa_tls_referenced_p (x
);
3713 #include "gt-xtensa.h"