1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
34 #include "insn-attr.h"
35 #include "insn-codes.h"
49 #include "target-def.h"
50 #include "langhooks.h"
55 /* Enumeration for all of the relational tests, so that we can build
56 arrays indexed by the test type, and not worry about the order
74 /* Array giving truth value on whether or not a given hard register
75 can support a given mode. */
76 char xtensa_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
78 /* Current frame size calculated by compute_frame_size. */
79 unsigned xtensa_current_frame_size
;
81 /* Largest block move to handle in-line. */
82 #define LARGEST_MOVE_RATIO 15
84 /* Define the structure for the machine field in struct function. */
85 struct GTY(()) machine_function
87 int accesses_prev_frame
;
91 rtx set_frame_ptr_insn
;
94 /* Vector, indexed by hard register number, which contains 1 for a
95 register that is allowable in a candidate for leaf function
98 const char xtensa_leaf_regs
[FIRST_PSEUDO_REGISTER
] =
100 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
102 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
106 /* Map hard register number to register class */
107 const enum reg_class xtensa_regno_to_class
[FIRST_PSEUDO_REGISTER
] =
109 RL_REGS
, SP_REG
, RL_REGS
, RL_REGS
,
110 RL_REGS
, RL_REGS
, RL_REGS
, GR_REGS
,
111 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
112 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
113 AR_REGS
, AR_REGS
, BR_REGS
,
114 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
115 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
116 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
117 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
121 static enum internal_test
map_test_to_internal_test (enum rtx_code
);
122 static rtx
gen_int_relational (enum rtx_code
, rtx
, rtx
, int *);
123 static rtx
gen_float_relational (enum rtx_code
, rtx
, rtx
);
124 static rtx
gen_conditional_move (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
125 static rtx
fixup_subreg_mem (rtx
);
126 static struct machine_function
* xtensa_init_machine_status (void);
127 static rtx
xtensa_legitimize_tls_address (rtx
);
128 static rtx
xtensa_legitimize_address (rtx
, rtx
, enum machine_mode
);
129 static bool xtensa_return_in_msb (const_tree
);
130 static void printx (FILE *, signed int);
131 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT
);
132 static rtx
xtensa_builtin_saveregs (void);
133 static bool xtensa_legitimate_address_p (enum machine_mode
, rtx
, bool);
134 static unsigned int xtensa_multibss_section_type_flags (tree
, const char *,
135 int) ATTRIBUTE_UNUSED
;
136 static section
*xtensa_select_rtx_section (enum machine_mode
, rtx
,
137 unsigned HOST_WIDE_INT
);
138 static bool xtensa_rtx_costs (rtx
, int, int, int *, bool);
139 static tree
xtensa_build_builtin_va_list (void);
140 static bool xtensa_return_in_memory (const_tree
, const_tree
);
141 static tree
xtensa_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*,
143 static rtx
xtensa_function_value (const_tree
, const_tree
, bool);
144 static void xtensa_init_builtins (void);
145 static tree
xtensa_fold_builtin (tree
, tree
, bool);
146 static rtx
xtensa_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
147 static void xtensa_va_start (tree
, rtx
);
148 static bool xtensa_frame_pointer_required (void);
150 static const int reg_nonleaf_alloc_order
[FIRST_PSEUDO_REGISTER
] =
154 /* This macro generates the assembly code for function exit,
155 on machines that need it. If FUNCTION_EPILOGUE is not defined
156 then individual return instructions are generated for each
157 return statement. Args are same as for FUNCTION_PROLOGUE. */
159 #undef TARGET_ASM_FUNCTION_EPILOGUE
160 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
162 /* These hooks specify assembly directives for creating certain kinds
163 of integer object. */
165 #undef TARGET_ASM_ALIGNED_SI_OP
166 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
168 #undef TARGET_ASM_SELECT_RTX_SECTION
169 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
171 #undef TARGET_DEFAULT_TARGET_FLAGS
172 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
174 #undef TARGET_LEGITIMIZE_ADDRESS
175 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
177 #undef TARGET_RTX_COSTS
178 #define TARGET_RTX_COSTS xtensa_rtx_costs
179 #undef TARGET_ADDRESS_COST
180 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
182 #undef TARGET_BUILD_BUILTIN_VA_LIST
183 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
185 #undef TARGET_EXPAND_BUILTIN_VA_START
186 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
188 #undef TARGET_PROMOTE_FUNCTION_ARGS
189 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
190 #undef TARGET_PROMOTE_FUNCTION_RETURN
191 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
192 #undef TARGET_PROMOTE_PROTOTYPES
193 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
195 #undef TARGET_RETURN_IN_MEMORY
196 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
197 #undef TARGET_FUNCTION_VALUE
198 #define TARGET_FUNCTION_VALUE xtensa_function_value
199 #undef TARGET_SPLIT_COMPLEX_ARG
200 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
201 #undef TARGET_MUST_PASS_IN_STACK
202 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
204 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
205 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
206 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
207 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
209 #undef TARGET_RETURN_IN_MSB
210 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
212 #undef TARGET_INIT_BUILTINS
213 #define TARGET_INIT_BUILTINS xtensa_init_builtins
214 #undef TARGET_FOLD_BUILTIN
215 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
216 #undef TARGET_EXPAND_BUILTIN
217 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
219 #undef TARGET_SECONDARY_RELOAD
220 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
222 #undef TARGET_HAVE_TLS
223 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
225 #undef TARGET_CANNOT_FORCE_CONST_MEM
226 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_tls_referenced_p
228 #undef TARGET_LEGITIMATE_ADDRESS_P
229 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
231 #undef TARGET_FRAME_POINTER_REQUIRED
232 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
234 struct gcc_target targetm
= TARGET_INITIALIZER
;
237 /* Functions to test Xtensa immediate operand validity. */
240 xtensa_simm8 (HOST_WIDE_INT v
)
242 return v
>= -128 && v
<= 127;
247 xtensa_simm8x256 (HOST_WIDE_INT v
)
249 return (v
& 255) == 0 && (v
>= -32768 && v
<= 32512);
254 xtensa_simm12b (HOST_WIDE_INT v
)
256 return v
>= -2048 && v
<= 2047;
261 xtensa_uimm8 (HOST_WIDE_INT v
)
263 return v
>= 0 && v
<= 255;
268 xtensa_uimm8x2 (HOST_WIDE_INT v
)
270 return (v
& 1) == 0 && (v
>= 0 && v
<= 510);
275 xtensa_uimm8x4 (HOST_WIDE_INT v
)
277 return (v
& 3) == 0 && (v
>= 0 && v
<= 1020);
282 xtensa_b4const (HOST_WIDE_INT v
)
309 xtensa_b4const_or_zero (HOST_WIDE_INT v
)
313 return xtensa_b4const (v
);
318 xtensa_b4constu (HOST_WIDE_INT v
)
345 xtensa_mask_immediate (HOST_WIDE_INT v
)
347 #define MAX_MASK_SIZE 16
350 for (mask_size
= 1; mask_size
<= MAX_MASK_SIZE
; mask_size
++)
363 /* This is just like the standard true_regnum() function except that it
364 works even when reg_renumber is not initialized. */
367 xt_true_regnum (rtx x
)
369 if (GET_CODE (x
) == REG
)
372 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
373 && reg_renumber
[REGNO (x
)] >= 0)
374 return reg_renumber
[REGNO (x
)];
377 if (GET_CODE (x
) == SUBREG
)
379 int base
= xt_true_regnum (SUBREG_REG (x
));
380 if (base
>= 0 && base
< FIRST_PSEUDO_REGISTER
)
381 return base
+ subreg_regno_offset (REGNO (SUBREG_REG (x
)),
382 GET_MODE (SUBREG_REG (x
)),
383 SUBREG_BYTE (x
), GET_MODE (x
));
390 xtensa_valid_move (enum machine_mode mode
, rtx
*operands
)
392 /* Either the destination or source must be a register, and the
393 MAC16 accumulator doesn't count. */
395 if (register_operand (operands
[0], mode
))
397 int dst_regnum
= xt_true_regnum (operands
[0]);
399 /* The stack pointer can only be assigned with a MOVSP opcode. */
400 if (dst_regnum
== STACK_POINTER_REGNUM
)
401 return (mode
== SImode
402 && register_operand (operands
[1], mode
)
403 && !ACC_REG_P (xt_true_regnum (operands
[1])));
405 if (!ACC_REG_P (dst_regnum
))
408 if (register_operand (operands
[1], mode
))
410 int src_regnum
= xt_true_regnum (operands
[1]);
411 if (!ACC_REG_P (src_regnum
))
419 smalloffset_mem_p (rtx op
)
421 if (GET_CODE (op
) == MEM
)
423 rtx addr
= XEXP (op
, 0);
424 if (GET_CODE (addr
) == REG
)
425 return BASE_REG_P (addr
, 0);
426 if (GET_CODE (addr
) == PLUS
)
428 rtx offset
= XEXP (addr
, 0);
430 if (GET_CODE (offset
) != CONST_INT
)
431 offset
= XEXP (addr
, 1);
432 if (GET_CODE (offset
) != CONST_INT
)
435 val
= INTVAL (offset
);
436 return (val
& 3) == 0 && (val
>= 0 && val
<= 60);
444 constantpool_address_p (rtx addr
)
448 if (GET_CODE (addr
) == CONST
)
452 /* Only handle (PLUS (SYM, OFFSET)) form. */
453 addr
= XEXP (addr
, 0);
454 if (GET_CODE (addr
) != PLUS
)
457 /* Make sure the address is word aligned. */
458 offset
= XEXP (addr
, 1);
459 if ((GET_CODE (offset
) != CONST_INT
)
460 || ((INTVAL (offset
) & 3) != 0))
463 sym
= XEXP (addr
, 0);
466 if ((GET_CODE (sym
) == SYMBOL_REF
)
467 && CONSTANT_POOL_ADDRESS_P (sym
))
474 constantpool_mem_p (rtx op
)
476 if (GET_CODE (op
) == SUBREG
)
477 op
= SUBREG_REG (op
);
478 if (GET_CODE (op
) == MEM
)
479 return constantpool_address_p (XEXP (op
, 0));
484 /* Return TRUE if X is a thread-local symbol. */
487 xtensa_tls_symbol_p (rtx x
)
489 if (! TARGET_HAVE_TLS
)
492 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
497 xtensa_extend_reg (rtx dst
, rtx src
)
499 rtx temp
= gen_reg_rtx (SImode
);
500 rtx shift
= GEN_INT (BITS_PER_WORD
- GET_MODE_BITSIZE (GET_MODE (src
)));
502 /* Generate paradoxical subregs as needed so that the modes match. */
503 src
= simplify_gen_subreg (SImode
, src
, GET_MODE (src
), 0);
504 dst
= simplify_gen_subreg (SImode
, dst
, GET_MODE (dst
), 0);
506 emit_insn (gen_ashlsi3 (temp
, src
, shift
));
507 emit_insn (gen_ashrsi3 (dst
, temp
, shift
));
512 xtensa_mem_offset (unsigned v
, enum machine_mode mode
)
517 /* Handle the worst case for block moves. See xtensa_expand_block_move
518 where we emit an optimized block move operation if the block can be
519 moved in < "move_ratio" pieces. The worst case is when the block is
520 aligned but has a size of (3 mod 4) (does this happen?) so that the
521 last piece requires a byte load/store. */
522 return (xtensa_uimm8 (v
)
523 && xtensa_uimm8 (v
+ MOVE_MAX
* LARGEST_MOVE_RATIO
));
526 return xtensa_uimm8 (v
);
529 return xtensa_uimm8x2 (v
);
532 return (xtensa_uimm8x4 (v
) && xtensa_uimm8x4 (v
+ 4));
538 return xtensa_uimm8x4 (v
);
542 /* Make normal rtx_code into something we can index from an array. */
544 static enum internal_test
545 map_test_to_internal_test (enum rtx_code test_code
)
547 enum internal_test test
= ITEST_MAX
;
552 case EQ
: test
= ITEST_EQ
; break;
553 case NE
: test
= ITEST_NE
; break;
554 case GT
: test
= ITEST_GT
; break;
555 case GE
: test
= ITEST_GE
; break;
556 case LT
: test
= ITEST_LT
; break;
557 case LE
: test
= ITEST_LE
; break;
558 case GTU
: test
= ITEST_GTU
; break;
559 case GEU
: test
= ITEST_GEU
; break;
560 case LTU
: test
= ITEST_LTU
; break;
561 case LEU
: test
= ITEST_LEU
; break;
568 /* Generate the code to compare two integer values. The return value is
569 the comparison expression. */
572 gen_int_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
573 rtx cmp0
, /* first operand to compare */
574 rtx cmp1
, /* second operand to compare */
575 int *p_invert
/* whether branch needs to reverse test */)
579 enum rtx_code test_code
; /* test code to use in insn */
580 bool (*const_range_p
) (HOST_WIDE_INT
); /* range check function */
581 int const_add
; /* constant to add (convert LE -> LT) */
582 int reverse_regs
; /* reverse registers in test */
583 int invert_const
; /* != 0 if invert value if cmp1 is constant */
584 int invert_reg
; /* != 0 if invert value if cmp1 is register */
585 int unsignedp
; /* != 0 for unsigned comparisons. */
588 static struct cmp_info info
[ (int)ITEST_MAX
] = {
590 { EQ
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* EQ */
591 { NE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* NE */
593 { LT
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* GT */
594 { GE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* GE */
595 { LT
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* LT */
596 { GE
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* LE */
598 { LTU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* GTU */
599 { GEU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* GEU */
600 { LTU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* LTU */
601 { GEU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* LEU */
604 enum internal_test test
;
605 enum machine_mode mode
;
606 struct cmp_info
*p_info
;
608 test
= map_test_to_internal_test (test_code
);
609 gcc_assert (test
!= ITEST_MAX
);
611 p_info
= &info
[ (int)test
];
613 mode
= GET_MODE (cmp0
);
614 if (mode
== VOIDmode
)
615 mode
= GET_MODE (cmp1
);
617 /* Make sure we can handle any constants given to us. */
618 if (GET_CODE (cmp1
) == CONST_INT
)
620 HOST_WIDE_INT value
= INTVAL (cmp1
);
621 unsigned HOST_WIDE_INT uvalue
= (unsigned HOST_WIDE_INT
)value
;
623 /* if the immediate overflows or does not fit in the immediate field,
624 spill it to a register */
626 if ((p_info
->unsignedp
?
627 (uvalue
+ p_info
->const_add
> uvalue
) :
628 (value
+ p_info
->const_add
> value
)) != (p_info
->const_add
> 0))
630 cmp1
= force_reg (mode
, cmp1
);
632 else if (!(p_info
->const_range_p
) (value
+ p_info
->const_add
))
634 cmp1
= force_reg (mode
, cmp1
);
637 else if ((GET_CODE (cmp1
) != REG
) && (GET_CODE (cmp1
) != SUBREG
))
639 cmp1
= force_reg (mode
, cmp1
);
642 /* See if we need to invert the result. */
643 *p_invert
= ((GET_CODE (cmp1
) == CONST_INT
)
644 ? p_info
->invert_const
645 : p_info
->invert_reg
);
647 /* Comparison to constants, may involve adding 1 to change a LT into LE.
648 Comparison between two registers, may involve switching operands. */
649 if (GET_CODE (cmp1
) == CONST_INT
)
651 if (p_info
->const_add
!= 0)
652 cmp1
= GEN_INT (INTVAL (cmp1
) + p_info
->const_add
);
655 else if (p_info
->reverse_regs
)
662 return gen_rtx_fmt_ee (p_info
->test_code
, VOIDmode
, cmp0
, cmp1
);
666 /* Generate the code to compare two float values. The return value is
667 the comparison expression. */
670 gen_float_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
671 rtx cmp0
, /* first operand to compare */
672 rtx cmp1
/* second operand to compare */)
674 rtx (*gen_fn
) (rtx
, rtx
, rtx
);
676 int reverse_regs
, invert
;
680 case EQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_seq_sf
; break;
681 case NE
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_seq_sf
; break;
682 case LE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sle_sf
; break;
683 case GT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_slt_sf
; break;
684 case LT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_slt_sf
; break;
685 case GE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sle_sf
; break;
686 case UNEQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_suneq_sf
; break;
687 case LTGT
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_suneq_sf
; break;
688 case UNLE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunle_sf
; break;
689 case UNGT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
690 case UNLT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
691 case UNGE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunle_sf
; break;
693 reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunordered_sf
; break;
695 reverse_regs
= 0; invert
= 1; gen_fn
= gen_sunordered_sf
; break;
697 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
698 reverse_regs
= 0; invert
= 0; gen_fn
= 0; /* avoid compiler warnings */
708 brtmp
= gen_rtx_REG (CCmode
, FPCC_REGNUM
);
709 emit_insn (gen_fn (brtmp
, cmp0
, cmp1
));
711 return gen_rtx_fmt_ee (invert
? EQ
: NE
, VOIDmode
, brtmp
, const0_rtx
);
716 xtensa_expand_conditional_branch (rtx
*operands
, enum machine_mode mode
)
718 enum rtx_code test_code
= GET_CODE (operands
[0]);
719 rtx cmp0
= operands
[1];
720 rtx cmp1
= operands
[2];
729 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
733 cmp
= gen_int_relational (test_code
, cmp0
, cmp1
, &invert
);
737 if (!TARGET_HARD_FLOAT
)
738 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
,
741 cmp
= gen_float_relational (test_code
, cmp0
, cmp1
);
745 /* Generate the branch. */
747 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
756 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
757 gen_rtx_IF_THEN_ELSE (VOIDmode
, cmp
,
764 gen_conditional_move (enum rtx_code code
, enum machine_mode mode
,
771 /* Jump optimization calls get_condition() which canonicalizes
772 comparisons like (GE x <const>) to (GT x <const-1>).
773 Transform those comparisons back to GE, since that is the
774 comparison supported in Xtensa. We shouldn't have to
775 transform <LE x const> comparisons, because neither
776 xtensa_expand_conditional_branch() nor get_condition() will
779 if ((code
== GT
) && (op1
== constm1_rtx
))
784 cmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
786 if (boolean_operator (cmp
, VOIDmode
))
788 /* Swap the operands to make const0 second. */
789 if (op0
== const0_rtx
)
795 /* If not comparing against zero, emit a comparison (subtract). */
796 if (op1
!= const0_rtx
)
798 op0
= expand_binop (SImode
, sub_optab
, op0
, op1
,
799 0, 0, OPTAB_LIB_WIDEN
);
803 else if (branch_operator (cmp
, VOIDmode
))
805 /* Swap the operands to make const0 second. */
806 if (op0
== const0_rtx
)
813 case LT
: code
= GE
; break;
814 case GE
: code
= LT
; break;
815 default: gcc_unreachable ();
819 if (op1
!= const0_rtx
)
825 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
828 if (TARGET_HARD_FLOAT
&& mode
== SFmode
)
829 return gen_float_relational (code
, op0
, op1
);
836 xtensa_expand_conditional_move (rtx
*operands
, int isflt
)
838 rtx dest
= operands
[0];
839 rtx cmp
= operands
[1];
840 enum machine_mode cmp_mode
= GET_MODE (XEXP (cmp
, 0));
841 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
843 if (!(cmp
= gen_conditional_move (GET_CODE (cmp
), cmp_mode
,
844 XEXP (cmp
, 0), XEXP (cmp
, 1))))
848 gen_fn
= (cmp_mode
== SImode
849 ? gen_movsfcc_internal0
850 : gen_movsfcc_internal1
);
852 gen_fn
= (cmp_mode
== SImode
853 ? gen_movsicc_internal0
854 : gen_movsicc_internal1
);
856 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), operands
[2], operands
[3], cmp
));
862 xtensa_expand_scc (rtx operands
[4], enum machine_mode cmp_mode
)
864 rtx dest
= operands
[0];
866 rtx one_tmp
, zero_tmp
;
867 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
869 if (!(cmp
= gen_conditional_move (GET_CODE (operands
[1]), cmp_mode
,
870 operands
[2], operands
[3])))
873 one_tmp
= gen_reg_rtx (SImode
);
874 zero_tmp
= gen_reg_rtx (SImode
);
875 emit_insn (gen_movsi (one_tmp
, const_true_rtx
));
876 emit_insn (gen_movsi (zero_tmp
, const0_rtx
));
878 gen_fn
= (cmp_mode
== SImode
879 ? gen_movsicc_internal0
880 : gen_movsicc_internal1
);
881 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), one_tmp
, zero_tmp
, cmp
));
886 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
887 for the output, i.e., the input operands are twice as big as MODE. */
890 xtensa_split_operand_pair (rtx operands
[4], enum machine_mode mode
)
892 switch (GET_CODE (operands
[1]))
895 operands
[3] = gen_rtx_REG (mode
, REGNO (operands
[1]) + 1);
896 operands
[2] = gen_rtx_REG (mode
, REGNO (operands
[1]));
900 operands
[3] = adjust_address (operands
[1], mode
, GET_MODE_SIZE (mode
));
901 operands
[2] = adjust_address (operands
[1], mode
, 0);
906 split_double (operands
[1], &operands
[2], &operands
[3]);
913 switch (GET_CODE (operands
[0]))
916 operands
[1] = gen_rtx_REG (mode
, REGNO (operands
[0]) + 1);
917 operands
[0] = gen_rtx_REG (mode
, REGNO (operands
[0]));
921 operands
[1] = adjust_address (operands
[0], mode
, GET_MODE_SIZE (mode
));
922 operands
[0] = adjust_address (operands
[0], mode
, 0);
931 /* Emit insns to move operands[1] into operands[0].
932 Return 1 if we have written out everything that needs to be done to
933 do the move. Otherwise, return 0 and the caller will emit the move
937 xtensa_emit_move_sequence (rtx
*operands
, enum machine_mode mode
)
939 rtx src
= operands
[1];
942 && (GET_CODE (src
) != CONST_INT
|| ! xtensa_simm12b (INTVAL (src
))))
944 rtx dst
= operands
[0];
946 if (xtensa_tls_referenced_p (src
))
950 if (GET_CODE (src
) == CONST
&& GET_CODE (XEXP (src
, 0)) == PLUS
)
952 addend
= XEXP (XEXP (src
, 0), 1);
953 src
= XEXP (XEXP (src
, 0), 0);
956 src
= xtensa_legitimize_tls_address (src
);
959 src
= gen_rtx_PLUS (mode
, src
, addend
);
960 src
= force_operand (src
, dst
);
962 emit_move_insn (dst
, src
);
966 if (! TARGET_CONST16
)
968 src
= force_const_mem (SImode
, src
);
972 /* PC-relative loads are always SImode, and CONST16 is only
973 supported in the movsi pattern, so add a SUBREG for any other
978 if (register_operand (dst
, mode
))
980 emit_move_insn (simplify_gen_subreg (SImode
, dst
, mode
, 0), src
);
985 src
= force_reg (SImode
, src
);
986 src
= gen_lowpart_SUBREG (mode
, src
);
992 if (!(reload_in_progress
| reload_completed
)
993 && !xtensa_valid_move (mode
, operands
))
994 operands
[1] = force_reg (mode
, operands
[1]);
996 operands
[1] = xtensa_copy_incoming_a7 (operands
[1]);
998 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
999 instruction won't be recognized after reload, so we remove the
1000 subreg and adjust mem accordingly. */
1001 if (reload_in_progress
)
1003 operands
[0] = fixup_subreg_mem (operands
[0]);
1004 operands
[1] = fixup_subreg_mem (operands
[1]);
1011 fixup_subreg_mem (rtx x
)
1013 if (GET_CODE (x
) == SUBREG
1014 && GET_CODE (SUBREG_REG (x
)) == REG
1015 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
)
1018 gen_rtx_SUBREG (GET_MODE (x
),
1019 reg_equiv_mem
[REGNO (SUBREG_REG (x
))],
1021 x
= alter_subreg (&temp
);
1027 /* Check if an incoming argument in a7 is expected to be used soon and
1028 if OPND is a register or register pair that includes a7. If so,
1029 create a new pseudo and copy a7 into that pseudo at the very
1030 beginning of the function, followed by the special "set_frame_ptr"
1031 unspec_volatile insn. The return value is either the original
1032 operand, if it is not a7, or the new pseudo containing a copy of
1033 the incoming argument. This is necessary because the register
1034 allocator will ignore conflicts with a7 and may either assign some
1035 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1036 the incoming argument in a7. By copying the argument out of a7 as
1037 the very first thing, and then immediately following that with an
1038 unspec_volatile to keep the scheduler away, we should avoid any
1039 problems. Putting the set_frame_ptr insn at the beginning, with
1040 only the a7 copy before it, also makes it easier for the prologue
1041 expander to initialize the frame pointer after the a7 copy and to
1042 fix up the a7 copy to use the stack pointer instead of the frame
1046 xtensa_copy_incoming_a7 (rtx opnd
)
1048 rtx entry_insns
= 0;
1050 enum machine_mode mode
;
1052 if (!cfun
->machine
->need_a7_copy
)
1055 /* This function should never be called again once a7 has been copied. */
1056 gcc_assert (!cfun
->machine
->set_frame_ptr_insn
);
1058 mode
= GET_MODE (opnd
);
1060 /* The operand using a7 may come in a later instruction, so just return
1061 the original operand if it doesn't use a7. */
1063 if (GET_CODE (reg
) == SUBREG
)
1065 gcc_assert (SUBREG_BYTE (reg
) == 0);
1066 reg
= SUBREG_REG (reg
);
1068 if (GET_CODE (reg
) != REG
1069 || REGNO (reg
) > A7_REG
1070 || REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) <= A7_REG
)
1073 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1074 gcc_assert (REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) - 1 == A7_REG
);
1076 cfun
->machine
->need_a7_copy
= false;
1078 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1079 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1082 tmp
= gen_reg_rtx (mode
);
1088 /* Copy the value out of A7 here but keep the first word in A6 until
1089 after the set_frame_ptr insn. Otherwise, the register allocator
1090 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1092 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 4),
1093 gen_raw_REG (SImode
, A7_REG
)));
1096 emit_insn (gen_movsf_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1099 emit_insn (gen_movsi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1102 emit_insn (gen_movhi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1105 emit_insn (gen_movqi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1111 cfun
->machine
->set_frame_ptr_insn
= emit_insn (gen_set_frame_ptr ());
1113 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1114 if (mode
== DFmode
|| mode
== DImode
)
1115 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 0),
1116 gen_rtx_REG (SImode
, A7_REG
- 1)));
1117 entry_insns
= get_insns ();
1120 if (cfun
->machine
->vararg_a7
)
1122 /* This is called from within builtin_saveregs, which will insert the
1123 saveregs code at the function entry, ahead of anything placed at
1124 the function entry now. Instead, save the sequence to be inserted
1125 at the beginning of the saveregs code. */
1126 cfun
->machine
->vararg_a7_copy
= entry_insns
;
1130 /* Put entry_insns after the NOTE that starts the function. If
1131 this is inside a start_sequence, make the outer-level insn
1132 chain current, so the code is placed at the start of the
1134 push_topmost_sequence ();
1135 /* Do not use entry_of_function() here. This is called from within
1136 expand_function_start, when the CFG still holds GIMPLE. */
1137 emit_insn_after (entry_insns
, get_insns ());
1138 pop_topmost_sequence ();
1145 /* Try to expand a block move operation to a sequence of RTL move
1146 instructions. If not optimizing, or if the block size is not a
1147 constant, or if the block is too large, the expansion fails and GCC
1148 falls back to calling memcpy().
1150 operands[0] is the destination
1151 operands[1] is the source
1152 operands[2] is the length
1153 operands[3] is the alignment */
1156 xtensa_expand_block_move (rtx
*operands
)
1158 static const enum machine_mode mode_from_align
[] =
1160 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1163 rtx dst_mem
= operands
[0];
1164 rtx src_mem
= operands
[1];
1165 HOST_WIDE_INT bytes
, align
;
1166 int num_pieces
, move_ratio
;
1168 enum machine_mode mode
[2];
1177 /* If this is not a fixed size move, just call memcpy. */
1178 if (!optimize
|| (GET_CODE (operands
[2]) != CONST_INT
))
1181 bytes
= INTVAL (operands
[2]);
1182 align
= INTVAL (operands
[3]);
1184 /* Anything to move? */
1188 if (align
> MOVE_MAX
)
1191 /* Decide whether to expand inline based on the optimization level. */
1194 move_ratio
= LARGEST_MOVE_RATIO
;
1195 num_pieces
= (bytes
/ align
) + (bytes
% align
); /* Close enough anyway. */
1196 if (num_pieces
> move_ratio
)
1199 x
= XEXP (dst_mem
, 0);
1202 x
= force_reg (Pmode
, x
);
1203 dst_mem
= replace_equiv_address (dst_mem
, x
);
1206 x
= XEXP (src_mem
, 0);
1209 x
= force_reg (Pmode
, x
);
1210 src_mem
= replace_equiv_address (src_mem
, x
);
1213 active
[0] = active
[1] = false;
1224 next_amount
= (bytes
>= 4 ? 4 : (bytes
>= 2 ? 2 : 1));
1225 next_amount
= MIN (next_amount
, align
);
1227 amount
[next
] = next_amount
;
1228 mode
[next
] = mode_from_align
[next_amount
];
1229 temp
[next
] = gen_reg_rtx (mode
[next
]);
1231 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1232 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1234 offset_ld
+= next_amount
;
1235 bytes
-= next_amount
;
1236 active
[next
] = true;
1241 active
[phase
] = false;
1243 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1244 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1246 offset_st
+= amount
[phase
];
1249 while (active
[next
]);
1256 xtensa_expand_nonlocal_goto (rtx
*operands
)
1258 rtx goto_handler
= operands
[1];
1259 rtx containing_fp
= operands
[3];
1261 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1262 is too big to generate in-line. */
1264 if (GET_CODE (containing_fp
) != REG
)
1265 containing_fp
= force_reg (Pmode
, containing_fp
);
1267 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_nonlocal_goto"),
1269 containing_fp
, Pmode
,
1270 goto_handler
, Pmode
);
1274 static struct machine_function
*
1275 xtensa_init_machine_status (void)
1277 return GGC_CNEW (struct machine_function
);
1281 /* Shift VAL of mode MODE left by COUNT bits. */
1284 xtensa_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
1286 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
1287 NULL_RTX
, 1, OPTAB_DIRECT
);
1288 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
1289 NULL_RTX
, 1, OPTAB_DIRECT
);
1293 /* Structure to hold the initial parameters for a compare_and_swap operation
1294 in HImode and QImode. */
1296 struct alignment_context
1298 rtx memsi
; /* SI aligned memory location. */
1299 rtx shift
; /* Bit offset with regard to lsb. */
1300 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
1301 rtx modemaski
; /* ~modemask */
1305 /* Initialize structure AC for word access to HI and QI mode memory. */
1308 init_alignment_context (struct alignment_context
*ac
, rtx mem
)
1310 enum machine_mode mode
= GET_MODE (mem
);
1311 rtx byteoffset
= NULL_RTX
;
1312 bool aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
1315 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
1318 /* Alignment is unknown. */
1321 /* Force the address into a register. */
1322 addr
= force_reg (Pmode
, XEXP (mem
, 0));
1324 /* Align it to SImode. */
1325 align
= expand_simple_binop (Pmode
, AND
, addr
,
1326 GEN_INT (-GET_MODE_SIZE (SImode
)),
1327 NULL_RTX
, 1, OPTAB_DIRECT
);
1329 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
1330 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
1331 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
1332 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
1334 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
1335 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
1336 NULL_RTX
, 1, OPTAB_DIRECT
);
1339 /* Calculate shiftcount. */
1340 if (TARGET_BIG_ENDIAN
)
1342 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
1344 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
1345 NULL_RTX
, 1, OPTAB_DIRECT
);
1350 ac
->shift
= NULL_RTX
;
1352 ac
->shift
= byteoffset
;
1355 if (ac
->shift
!= NULL_RTX
)
1357 /* Shift is the byte count, but we need the bitcount. */
1358 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
,
1359 GEN_INT (BITS_PER_UNIT
),
1360 NULL_RTX
, 1, OPTAB_DIRECT
);
1361 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
1362 GEN_INT (GET_MODE_MASK (mode
)),
1364 NULL_RTX
, 1, OPTAB_DIRECT
);
1367 ac
->modemask
= GEN_INT (GET_MODE_MASK (mode
));
1369 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
1373 /* Expand an atomic compare and swap operation for HImode and QImode.
1374 MEM is the memory location, CMP the old value to compare MEM with
1375 and NEW_RTX the value to set if CMP == MEM. */
1378 xtensa_expand_compare_and_swap (rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
1380 enum machine_mode mode
= GET_MODE (mem
);
1381 struct alignment_context ac
;
1382 rtx tmp
, cmpv
, newv
, val
;
1383 rtx oldval
= gen_reg_rtx (SImode
);
1384 rtx res
= gen_reg_rtx (SImode
);
1385 rtx csloop
= gen_label_rtx ();
1386 rtx csend
= gen_label_rtx ();
1388 init_alignment_context (&ac
, mem
);
1390 if (ac
.shift
!= NULL_RTX
)
1392 cmp
= xtensa_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
1393 new_rtx
= xtensa_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
1396 /* Load the surrounding word into VAL with the MEM value masked out. */
1397 val
= force_reg (SImode
, expand_simple_binop (SImode
, AND
, ac
.memsi
,
1398 ac
.modemaski
, NULL_RTX
, 1,
1400 emit_label (csloop
);
1402 /* Patch CMP and NEW_RTX into VAL at correct position. */
1403 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
1404 NULL_RTX
, 1, OPTAB_DIRECT
));
1405 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
1406 NULL_RTX
, 1, OPTAB_DIRECT
));
1408 /* Jump to end if we're done. */
1409 emit_insn (gen_sync_compare_and_swapsi (res
, ac
.memsi
, cmpv
, newv
));
1410 emit_cmp_and_jump_insns (res
, cmpv
, EQ
, const0_rtx
, SImode
, true, csend
);
1412 /* Check for changes outside mode. */
1413 emit_move_insn (oldval
, val
);
1414 tmp
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
1415 val
, 1, OPTAB_DIRECT
);
1417 emit_move_insn (val
, tmp
);
1419 /* Loop internal if so. */
1420 emit_cmp_and_jump_insns (oldval
, val
, NE
, const0_rtx
, SImode
, true, csloop
);
1424 /* Return the correct part of the bitfield. */
1425 convert_move (target
,
1426 (ac
.shift
== NULL_RTX
? res
1427 : expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
1428 NULL_RTX
, 1, OPTAB_DIRECT
)),
1433 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1434 the default expansion works fine for SImode). MEM is the memory location
1435 and VAL the value to play with. If AFTER is true then store the value
1436 MEM holds after the operation, if AFTER is false then store the value MEM
1437 holds before the operation. If TARGET is zero then discard that value, else
1438 store it to TARGET. */
1441 xtensa_expand_atomic (enum rtx_code code
, rtx target
, rtx mem
, rtx val
,
1444 enum machine_mode mode
= GET_MODE (mem
);
1445 struct alignment_context ac
;
1446 rtx csloop
= gen_label_rtx ();
1448 rtx old
= gen_reg_rtx (SImode
);
1449 rtx new_rtx
= gen_reg_rtx (SImode
);
1450 rtx orig
= NULL_RTX
;
1452 init_alignment_context (&ac
, mem
);
1454 /* Prepare values before the compare-and-swap loop. */
1455 if (ac
.shift
!= NULL_RTX
)
1456 val
= xtensa_expand_mask_and_shift (val
, mode
, ac
.shift
);
1461 orig
= gen_reg_rtx (SImode
);
1462 convert_move (orig
, val
, 1);
1470 case MULT
: /* NAND */
1472 /* val = "11..1<val>11..1" */
1473 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
1474 NULL_RTX
, 1, OPTAB_DIRECT
);
1481 /* Load full word. Subsequent loads are performed by S32C1I. */
1482 cmp
= force_reg (SImode
, ac
.memsi
);
1484 emit_label (csloop
);
1485 emit_move_insn (old
, cmp
);
1491 val
= expand_simple_binop (SImode
, code
, old
, orig
,
1492 NULL_RTX
, 1, OPTAB_DIRECT
);
1493 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
1494 NULL_RTX
, 1, OPTAB_DIRECT
);
1497 tmp
= expand_simple_binop (SImode
, AND
, old
, ac
.modemaski
,
1498 NULL_RTX
, 1, OPTAB_DIRECT
);
1499 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
,
1500 new_rtx
, 1, OPTAB_DIRECT
);
1506 tmp
= expand_simple_binop (SImode
, code
, old
, val
,
1507 new_rtx
, 1, OPTAB_DIRECT
);
1510 case MULT
: /* NAND */
1511 tmp
= expand_simple_binop (SImode
, XOR
, old
, ac
.modemask
,
1512 NULL_RTX
, 1, OPTAB_DIRECT
);
1513 tmp
= expand_simple_binop (SImode
, AND
, tmp
, val
,
1514 new_rtx
, 1, OPTAB_DIRECT
);
1522 emit_move_insn (new_rtx
, tmp
);
1523 emit_insn (gen_sync_compare_and_swapsi (cmp
, ac
.memsi
, old
, new_rtx
));
1524 emit_cmp_and_jump_insns (cmp
, old
, NE
, const0_rtx
, SImode
, true, csloop
);
1528 tmp
= (after
? new_rtx
: cmp
);
1529 convert_move (target
,
1530 (ac
.shift
== NULL_RTX
? tmp
1531 : expand_simple_binop (SImode
, LSHIFTRT
, tmp
, ac
.shift
,
1532 NULL_RTX
, 1, OPTAB_DIRECT
)),
1539 xtensa_setup_frame_addresses (void)
1541 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1542 cfun
->machine
->accesses_prev_frame
= 1;
1545 (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_libgcc_window_spill"),
1550 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1551 a comment showing where the end of the loop is. However, if there is a
1552 label or a branch at the end of the loop then we need to place a nop
1553 there. If the loop ends with a label we need the nop so that branches
1554 targeting that label will target the nop (and thus remain in the loop),
1555 instead of targeting the instruction after the loop (and thus exiting
1556 the loop). If the loop ends with a branch, we need the nop in case the
1557 branch is targeting a location inside the loop. When the branch
1558 executes it will cause the loop count to be decremented even if it is
1559 taken (because it is the last instruction in the loop), so we need to
1560 nop after the branch to prevent the loop count from being decremented
1561 when the branch is taken. */
1564 xtensa_emit_loop_end (rtx insn
, rtx
*operands
)
1568 for (insn
= PREV_INSN (insn
); insn
&& !done
; insn
= PREV_INSN (insn
))
1570 switch (GET_CODE (insn
))
1577 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1583 rtx body
= PATTERN (insn
);
1585 if (GET_CODE (body
) == JUMP_INSN
)
1587 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1590 else if ((GET_CODE (body
) != USE
)
1591 && (GET_CODE (body
) != CLOBBER
))
1598 output_asm_insn ("# loop end for %0", operands
);
1603 xtensa_emit_branch (bool inverted
, bool immed
, rtx
*operands
)
1605 static char result
[64];
1609 code
= GET_CODE (operands
[3]);
1612 case EQ
: op
= inverted
? "ne" : "eq"; break;
1613 case NE
: op
= inverted
? "eq" : "ne"; break;
1614 case LT
: op
= inverted
? "ge" : "lt"; break;
1615 case GE
: op
= inverted
? "lt" : "ge"; break;
1616 case LTU
: op
= inverted
? "geu" : "ltu"; break;
1617 case GEU
: op
= inverted
? "ltu" : "geu"; break;
1618 default: gcc_unreachable ();
1623 if (INTVAL (operands
[1]) == 0)
1624 sprintf (result
, "b%sz%s\t%%0, %%2", op
,
1625 (TARGET_DENSITY
&& (code
== EQ
|| code
== NE
)) ? ".n" : "");
1627 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1630 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1637 xtensa_emit_bit_branch (bool inverted
, bool immed
, rtx
*operands
)
1639 static char result
[64];
1642 switch (GET_CODE (operands
[3]))
1644 case EQ
: op
= inverted
? "bs" : "bc"; break;
1645 case NE
: op
= inverted
? "bc" : "bs"; break;
1646 default: gcc_unreachable ();
1651 unsigned bitnum
= INTVAL (operands
[1]) & 0x1f;
1652 operands
[1] = GEN_INT (bitnum
);
1653 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1656 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1663 xtensa_emit_movcc (bool inverted
, bool isfp
, bool isbool
, rtx
*operands
)
1665 static char result
[64];
1669 code
= GET_CODE (operands
[4]);
1674 case EQ
: op
= inverted
? "t" : "f"; break;
1675 case NE
: op
= inverted
? "f" : "t"; break;
1676 default: gcc_unreachable ();
1683 case EQ
: op
= inverted
? "nez" : "eqz"; break;
1684 case NE
: op
= inverted
? "eqz" : "nez"; break;
1685 case LT
: op
= inverted
? "gez" : "ltz"; break;
1686 case GE
: op
= inverted
? "ltz" : "gez"; break;
1687 default: gcc_unreachable ();
1691 sprintf (result
, "mov%s%s\t%%0, %%%d, %%1",
1692 op
, isfp
? ".s" : "", inverted
? 3 : 2);
1698 xtensa_emit_call (int callop
, rtx
*operands
)
1700 static char result
[64];
1701 rtx tgt
= operands
[callop
];
1703 if (GET_CODE (tgt
) == CONST_INT
)
1704 sprintf (result
, "call8\t0x%lx", INTVAL (tgt
));
1705 else if (register_operand (tgt
, VOIDmode
))
1706 sprintf (result
, "callx8\t%%%d", callop
);
1708 sprintf (result
, "call8\t%%%d", callop
);
1715 xtensa_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
1717 /* Allow constant pool addresses. */
1718 if (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
1719 && ! TARGET_CONST16
&& constantpool_address_p (addr
)
1720 && ! xtensa_tls_referenced_p (addr
))
1723 while (GET_CODE (addr
) == SUBREG
)
1724 addr
= SUBREG_REG (addr
);
1726 /* Allow base registers. */
1727 if (GET_CODE (addr
) == REG
&& BASE_REG_P (addr
, strict
))
1730 /* Check for "register + offset" addressing. */
1731 if (GET_CODE (addr
) == PLUS
)
1733 rtx xplus0
= XEXP (addr
, 0);
1734 rtx xplus1
= XEXP (addr
, 1);
1735 enum rtx_code code0
;
1736 enum rtx_code code1
;
1738 while (GET_CODE (xplus0
) == SUBREG
)
1739 xplus0
= SUBREG_REG (xplus0
);
1740 code0
= GET_CODE (xplus0
);
1742 while (GET_CODE (xplus1
) == SUBREG
)
1743 xplus1
= SUBREG_REG (xplus1
);
1744 code1
= GET_CODE (xplus1
);
1746 /* Swap operands if necessary so the register is first. */
1747 if (code0
!= REG
&& code1
== REG
)
1749 xplus0
= XEXP (addr
, 1);
1750 xplus1
= XEXP (addr
, 0);
1751 code0
= GET_CODE (xplus0
);
1752 code1
= GET_CODE (xplus1
);
1755 if (code0
== REG
&& BASE_REG_P (xplus0
, strict
)
1756 && code1
== CONST_INT
1757 && xtensa_mem_offset (INTVAL (xplus1
), mode
))
1765 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1767 static GTY(()) rtx xtensa_tls_module_base_symbol
;
1770 xtensa_tls_module_base (void)
1772 if (! xtensa_tls_module_base_symbol
)
1774 xtensa_tls_module_base_symbol
=
1775 gen_rtx_SYMBOL_REF (Pmode
, "_TLS_MODULE_BASE_");
1776 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol
)
1777 |= TLS_MODEL_GLOBAL_DYNAMIC
<< SYMBOL_FLAG_TLS_SHIFT
;
1780 return xtensa_tls_module_base_symbol
;
1785 xtensa_call_tls_desc (rtx sym
, rtx
*retp
)
1787 rtx fn
, arg
, a10
, call_insn
, insns
;
1790 fn
= gen_reg_rtx (Pmode
);
1791 arg
= gen_reg_rtx (Pmode
);
1792 a10
= gen_rtx_REG (Pmode
, 10);
1794 emit_insn (gen_tls_func (fn
, sym
));
1795 emit_insn (gen_tls_arg (arg
, sym
));
1796 emit_move_insn (a10
, arg
);
1797 call_insn
= emit_call_insn (gen_tls_call (a10
, fn
, sym
, const1_rtx
));
1798 CALL_INSN_FUNCTION_USAGE (call_insn
)
1799 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, a10
),
1800 CALL_INSN_FUNCTION_USAGE (call_insn
));
1801 insns
= get_insns ();
1810 xtensa_legitimize_tls_address (rtx x
)
1812 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
1813 rtx dest
, tp
, ret
, modbase
, base
, addend
, insns
;
1815 dest
= gen_reg_rtx (Pmode
);
1818 case TLS_MODEL_GLOBAL_DYNAMIC
:
1819 insns
= xtensa_call_tls_desc (x
, &ret
);
1820 emit_libcall_block (insns
, dest
, ret
, x
);
1823 case TLS_MODEL_LOCAL_DYNAMIC
:
1824 base
= gen_reg_rtx (Pmode
);
1825 modbase
= xtensa_tls_module_base ();
1826 insns
= xtensa_call_tls_desc (modbase
, &ret
);
1827 emit_libcall_block (insns
, base
, ret
, modbase
);
1828 addend
= force_reg (SImode
, gen_sym_DTPOFF (x
));
1829 emit_insn (gen_addsi3 (dest
, base
, addend
));
1832 case TLS_MODEL_INITIAL_EXEC
:
1833 case TLS_MODEL_LOCAL_EXEC
:
1834 tp
= gen_reg_rtx (SImode
);
1835 emit_insn (gen_load_tp (tp
));
1836 addend
= force_reg (SImode
, gen_sym_TPOFF (x
));
1837 emit_insn (gen_addsi3 (dest
, tp
, addend
));
1849 xtensa_legitimize_address (rtx x
,
1850 rtx oldx ATTRIBUTE_UNUSED
,
1851 enum machine_mode mode
)
1853 if (xtensa_tls_symbol_p (x
))
1854 return xtensa_legitimize_tls_address (x
);
1856 if (GET_CODE (x
) == PLUS
)
1858 rtx plus0
= XEXP (x
, 0);
1859 rtx plus1
= XEXP (x
, 1);
1861 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1863 plus0
= XEXP (x
, 1);
1864 plus1
= XEXP (x
, 0);
1867 /* Try to split up the offset to use an ADDMI instruction. */
1868 if (GET_CODE (plus0
) == REG
1869 && GET_CODE (plus1
) == CONST_INT
1870 && !xtensa_mem_offset (INTVAL (plus1
), mode
)
1871 && !xtensa_simm8 (INTVAL (plus1
))
1872 && xtensa_mem_offset (INTVAL (plus1
) & 0xff, mode
)
1873 && xtensa_simm8x256 (INTVAL (plus1
) & ~0xff))
1875 rtx temp
= gen_reg_rtx (Pmode
);
1876 rtx addmi_offset
= GEN_INT (INTVAL (plus1
) & ~0xff);
1877 emit_insn (gen_rtx_SET (Pmode
, temp
,
1878 gen_rtx_PLUS (Pmode
, plus0
, addmi_offset
)));
1879 return gen_rtx_PLUS (Pmode
, temp
, GEN_INT (INTVAL (plus1
) & 0xff));
1887 /* Helper for xtensa_tls_referenced_p. */
1890 xtensa_tls_referenced_p_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1892 if (GET_CODE (*x
) == SYMBOL_REF
)
1893 return SYMBOL_REF_TLS_MODEL (*x
) != 0;
1895 /* Ignore TLS references that have already been legitimized. */
1896 if (GET_CODE (*x
) == UNSPEC
)
1898 switch (XINT (*x
, 1))
1902 case UNSPEC_TLS_FUNC
:
1903 case UNSPEC_TLS_ARG
:
1904 case UNSPEC_TLS_CALL
:
1915 /* Return TRUE if X contains any TLS symbol references. */
1918 xtensa_tls_referenced_p (rtx x
)
1920 if (! TARGET_HAVE_TLS
)
1923 return for_each_rtx (&x
, xtensa_tls_referenced_p_1
, NULL
);
1927 /* Return the debugger register number to use for 'regno'. */
1930 xtensa_dbx_register_number (int regno
)
1934 if (GP_REG_P (regno
))
1936 regno
-= GP_REG_FIRST
;
1939 else if (BR_REG_P (regno
))
1941 regno
-= BR_REG_FIRST
;
1944 else if (FP_REG_P (regno
))
1946 regno
-= FP_REG_FIRST
;
1949 else if (ACC_REG_P (regno
))
1951 first
= 0x200; /* Start of Xtensa special registers. */
1952 regno
= 16; /* ACCLO is special register 16. */
1955 /* When optimizing, we sometimes get asked about pseudo-registers
1956 that don't represent hard registers. Return 0 for these. */
1960 return first
+ regno
;
1964 /* Argument support functions. */
1966 /* Initialize CUMULATIVE_ARGS for a function. */
1969 init_cumulative_args (CUMULATIVE_ARGS
*cum
, int incoming
)
1972 cum
->incoming
= incoming
;
1976 /* Advance the argument to the next argument position. */
1979 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
)
1984 arg_words
= &cum
->arg_words
;
1985 max
= MAX_ARGS_IN_REGISTERS
;
1987 words
= (((mode
!= BLKmode
)
1988 ? (int) GET_MODE_SIZE (mode
)
1989 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1991 if (*arg_words
< max
1992 && (targetm
.calls
.must_pass_in_stack (mode
, type
)
1993 || *arg_words
+ words
> max
))
1996 *arg_words
+= words
;
2000 /* Return an RTL expression containing the register for the given mode,
2001 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2002 if this is an incoming argument to the current function. */
2005 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
2008 int regbase
, words
, max
;
2012 arg_words
= &cum
->arg_words
;
2013 regbase
= (incoming_p
? GP_ARG_FIRST
: GP_OUTGOING_ARG_FIRST
);
2014 max
= MAX_ARGS_IN_REGISTERS
;
2016 words
= (((mode
!= BLKmode
)
2017 ? (int) GET_MODE_SIZE (mode
)
2018 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2020 if (type
&& (TYPE_ALIGN (type
) > BITS_PER_WORD
))
2022 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_WORD
;
2023 *arg_words
= (*arg_words
+ align
- 1) & -align
;
2026 if (*arg_words
+ words
> max
)
2029 regno
= regbase
+ *arg_words
;
2031 if (cum
->incoming
&& regno
<= A7_REG
&& regno
+ words
> A7_REG
)
2032 cfun
->machine
->need_a7_copy
= true;
2034 return gen_rtx_REG (mode
, regno
);
2039 function_arg_boundary (enum machine_mode mode
, tree type
)
2041 unsigned int alignment
;
2043 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
2044 if (alignment
< PARM_BOUNDARY
)
2045 alignment
= PARM_BOUNDARY
;
2046 if (alignment
> STACK_BOUNDARY
)
2047 alignment
= STACK_BOUNDARY
;
2053 xtensa_return_in_msb (const_tree valtype
)
2055 return (TARGET_BIG_ENDIAN
2056 && AGGREGATE_TYPE_P (valtype
)
2057 && int_size_in_bytes (valtype
) >= UNITS_PER_WORD
);
2062 override_options (void)
2065 enum machine_mode mode
;
2067 if (!TARGET_BOOLEANS
&& TARGET_HARD_FLOAT
)
2068 error ("boolean registers required for the floating-point option");
2070 /* Set up array giving whether a given register can hold a given mode. */
2071 for (mode
= VOIDmode
;
2072 mode
!= MAX_MACHINE_MODE
;
2073 mode
= (enum machine_mode
) ((int) mode
+ 1))
2075 int size
= GET_MODE_SIZE (mode
);
2076 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2078 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2082 if (ACC_REG_P (regno
))
2083 temp
= (TARGET_MAC16
2084 && (mclass
== MODE_INT
) && (size
<= UNITS_PER_WORD
));
2085 else if (GP_REG_P (regno
))
2086 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
2087 else if (FP_REG_P (regno
))
2088 temp
= (TARGET_HARD_FLOAT
&& (mode
== SFmode
));
2089 else if (BR_REG_P (regno
))
2090 temp
= (TARGET_BOOLEANS
&& (mode
== CCmode
));
2094 xtensa_hard_regno_mode_ok
[(int) mode
][regno
] = temp
;
2098 init_machine_status
= xtensa_init_machine_status
;
2100 /* Check PIC settings. PIC is only supported when using L32R
2101 instructions, and some targets need to always use PIC. */
2102 if (flag_pic
&& TARGET_CONST16
)
2103 error ("-f%s is not supported with CONST16 instructions",
2104 (flag_pic
> 1 ? "PIC" : "pic"));
2105 else if (XTENSA_ALWAYS_PIC
)
2108 error ("PIC is required but not supported with CONST16 instructions");
2111 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2114 if (flag_pic
&& !flag_pie
)
2117 /* Hot/cold partitioning does not work on this architecture, because of
2118 constant pools (the load instruction cannot necessarily reach that far).
2119 Therefore disable it on this architecture. */
2120 if (flag_reorder_blocks_and_partition
)
2122 flag_reorder_blocks_and_partition
= 0;
2123 flag_reorder_blocks
= 1;
2128 /* A C compound statement to output to stdio stream STREAM the
2129 assembler syntax for an instruction operand X. X is an RTL
2132 CODE is a value that can be used to specify one of several ways
2133 of printing the operand. It is used when identical operands
2134 must be printed differently depending on the context. CODE
2135 comes from the '%' specification that was used to request
2136 printing of the operand. If the specification was just '%DIGIT'
2137 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2138 is the ASCII code for LTR.
2140 If X is a register, this macro should print the register's name.
2141 The names can be found in an array 'reg_names' whose type is
2142 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2144 When the machine description has a specification '%PUNCT' (a '%'
2145 followed by a punctuation character), this macro is called with
2146 a null pointer for X and the punctuation character for CODE.
2148 'a', 'c', 'l', and 'n' are reserved.
2150 The Xtensa specific codes are:
2152 'd' CONST_INT, print as signed decimal
2153 'x' CONST_INT, print as signed hexadecimal
2154 'K' CONST_INT, print number of bits in mask for EXTUI
2155 'R' CONST_INT, print (X & 0x1f)
2156 'L' CONST_INT, print ((32 - X) & 0x1f)
2157 'D' REG, print second register of double-word register operand
2158 'N' MEM, print address of next word following a memory operand
2159 'v' MEM, if memory reference is volatile, output a MEMW before it
2160 't' any constant, add "@h" suffix for top 16 bits
2161 'b' any constant, add "@l" suffix for bottom 16 bits
2165 printx (FILE *file
, signed int val
)
2167 /* Print a hexadecimal value in a nice way. */
2168 if ((val
> -0xa) && (val
< 0xa))
2169 fprintf (file
, "%d", val
);
2171 fprintf (file
, "-0x%x", -val
);
2173 fprintf (file
, "0x%x", val
);
2178 print_operand (FILE *file
, rtx x
, int letter
)
2181 error ("PRINT_OPERAND null pointer");
2186 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2187 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
) + 1]);
2189 output_operand_lossage ("invalid %%D value");
2193 if (GET_CODE (x
) == MEM
)
2195 /* For a volatile memory reference, emit a MEMW before the
2197 if (MEM_VOLATILE_P (x
) && TARGET_SERIALIZE_VOLATILE
)
2198 fprintf (file
, "memw\n\t");
2201 output_operand_lossage ("invalid %%v value");
2205 if (GET_CODE (x
) == MEM
2206 && (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DImode
))
2208 x
= adjust_address (x
, GET_MODE (x
) == DFmode
? SFmode
: SImode
, 4);
2209 output_address (XEXP (x
, 0));
2212 output_operand_lossage ("invalid %%N value");
2216 if (GET_CODE (x
) == CONST_INT
)
2219 unsigned val
= INTVAL (x
);
2225 if ((val
!= 0) || (num_bits
== 0) || (num_bits
> 16))
2226 fatal_insn ("invalid mask", x
);
2228 fprintf (file
, "%d", num_bits
);
2231 output_operand_lossage ("invalid %%K value");
2235 if (GET_CODE (x
) == CONST_INT
)
2236 fprintf (file
, "%ld", (32 - INTVAL (x
)) & 0x1f);
2238 output_operand_lossage ("invalid %%L value");
2242 if (GET_CODE (x
) == CONST_INT
)
2243 fprintf (file
, "%ld", INTVAL (x
) & 0x1f);
2245 output_operand_lossage ("invalid %%R value");
2249 if (GET_CODE (x
) == CONST_INT
)
2250 printx (file
, INTVAL (x
));
2252 output_operand_lossage ("invalid %%x value");
2256 if (GET_CODE (x
) == CONST_INT
)
2257 fprintf (file
, "%ld", INTVAL (x
));
2259 output_operand_lossage ("invalid %%d value");
2264 if (GET_CODE (x
) == CONST_INT
)
2266 printx (file
, INTVAL (x
));
2267 fputs (letter
== 't' ? "@h" : "@l", file
);
2269 else if (GET_CODE (x
) == CONST_DOUBLE
)
2272 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2273 if (GET_MODE (x
) == SFmode
)
2276 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
2277 fprintf (file
, "0x%08lx@%c", l
, letter
== 't' ? 'h' : 'l');
2280 output_operand_lossage ("invalid %%t/%%b value");
2282 else if (GET_CODE (x
) == CONST
)
2284 /* X must be a symbolic constant on ELF. Write an expression
2285 suitable for 'const16' that sets the high or low 16 bits. */
2286 if (GET_CODE (XEXP (x
, 0)) != PLUS
2287 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
2288 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
2289 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
2290 output_operand_lossage ("invalid %%t/%%b value");
2291 print_operand (file
, XEXP (XEXP (x
, 0), 0), 0);
2292 fputs (letter
== 't' ? "@h" : "@l", file
);
2293 /* There must be a non-alphanumeric character between 'h' or 'l'
2294 and the number. The '-' is added by print_operand() already. */
2295 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
2297 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
2301 output_addr_const (file
, x
);
2302 fputs (letter
== 't' ? "@h" : "@l", file
);
2307 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2308 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
)]);
2309 else if (GET_CODE (x
) == MEM
)
2310 output_address (XEXP (x
, 0));
2311 else if (GET_CODE (x
) == CONST_INT
)
2312 fprintf (file
, "%ld", INTVAL (x
));
2314 output_addr_const (file
, x
);
2319 /* A C compound statement to output to stdio stream STREAM the
2320 assembler syntax for an instruction operand that is a memory
2321 reference whose address is ADDR. ADDR is an RTL expression. */
2324 print_operand_address (FILE *file
, rtx addr
)
2327 error ("PRINT_OPERAND_ADDRESS, null pointer");
2329 switch (GET_CODE (addr
))
2332 fatal_insn ("invalid address", addr
);
2336 fprintf (file
, "%s, 0", reg_names
[REGNO (addr
)]);
2342 rtx offset
= (rtx
)0;
2343 rtx arg0
= XEXP (addr
, 0);
2344 rtx arg1
= XEXP (addr
, 1);
2346 if (GET_CODE (arg0
) == REG
)
2351 else if (GET_CODE (arg1
) == REG
)
2357 fatal_insn ("no register in address", addr
);
2359 if (CONSTANT_P (offset
))
2361 fprintf (file
, "%s, ", reg_names
[REGNO (reg
)]);
2362 output_addr_const (file
, offset
);
2365 fatal_insn ("address offset not a constant", addr
);
2373 output_addr_const (file
, addr
);
2380 xtensa_output_addr_const_extra (FILE *fp
, rtx x
)
2382 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
2384 switch (XINT (x
, 1))
2387 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2388 fputs ("@TPOFF", fp
);
2391 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2392 fputs ("@DTPOFF", fp
);
2397 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2411 xtensa_output_literal (FILE *file
, rtx x
, enum machine_mode mode
, int labelno
)
2418 fprintf (file
, "\t.literal .LC%u, ", (unsigned) labelno
);
2420 switch (GET_MODE_CLASS (mode
))
2423 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
);
2425 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2429 REAL_VALUE_TO_TARGET_SINGLE (r
, value_long
[0]);
2430 if (HOST_BITS_PER_LONG
> 32)
2431 value_long
[0] &= 0xffffffff;
2432 fprintf (file
, "0x%08lx\n", value_long
[0]);
2436 REAL_VALUE_TO_TARGET_DOUBLE (r
, value_long
);
2437 if (HOST_BITS_PER_LONG
> 32)
2439 value_long
[0] &= 0xffffffff;
2440 value_long
[1] &= 0xffffffff;
2442 fprintf (file
, "0x%08lx, 0x%08lx\n",
2443 value_long
[0], value_long
[1]);
2453 case MODE_PARTIAL_INT
:
2454 size
= GET_MODE_SIZE (mode
);
2458 output_addr_const (file
, x
);
2463 split_double (x
, &first
, &second
);
2464 output_addr_const (file
, first
);
2466 output_addr_const (file
, second
);
2481 /* Return the bytes needed to compute the frame pointer from the current
2484 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2485 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2488 compute_frame_size (int size
)
2490 /* Add space for the incoming static chain value. */
2491 if (cfun
->static_chain_decl
!= NULL
)
2492 size
+= (1 * UNITS_PER_WORD
);
2494 xtensa_current_frame_size
=
2495 XTENSA_STACK_ALIGN (size
2496 + crtl
->outgoing_args_size
2497 + (WINDOW_SIZE
* UNITS_PER_WORD
));
2498 return xtensa_current_frame_size
;
2503 xtensa_frame_pointer_required (void)
2505 /* The code to expand builtin_frame_addr and builtin_return_addr
2506 currently uses the hard_frame_pointer instead of frame_pointer.
2507 This seems wrong but maybe it's necessary for other architectures.
2508 This function is derived from the i386 code. */
2510 if (cfun
->machine
->accesses_prev_frame
)
2517 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2518 and the total number of words must be a multiple of 128 bits. */
2519 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2522 xtensa_expand_prologue (void)
2524 HOST_WIDE_INT total_size
;
2528 total_size
= compute_frame_size (get_frame_size ());
2529 size_rtx
= GEN_INT (total_size
);
2531 if (total_size
< (1 << (12+3)))
2532 insn
= emit_insn (gen_entry (size_rtx
));
2535 /* Use a8 as a temporary since a0-a7 may be live. */
2536 rtx tmp_reg
= gen_rtx_REG (Pmode
, A8_REG
);
2537 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE
)));
2538 emit_move_insn (tmp_reg
, GEN_INT (total_size
- MIN_FRAME_SIZE
));
2539 emit_insn (gen_subsi3 (tmp_reg
, stack_pointer_rtx
, tmp_reg
));
2540 insn
= emit_insn (gen_movsi (stack_pointer_rtx
, tmp_reg
));
2543 if (frame_pointer_needed
)
2545 if (cfun
->machine
->set_frame_ptr_insn
)
2549 push_topmost_sequence ();
2550 first
= get_insns ();
2551 pop_topmost_sequence ();
2553 /* For all instructions prior to set_frame_ptr_insn, replace
2554 hard_frame_pointer references with stack_pointer. */
2556 insn
!= cfun
->machine
->set_frame_ptr_insn
;
2557 insn
= NEXT_INSN (insn
))
2561 PATTERN (insn
) = replace_rtx (copy_rtx (PATTERN (insn
)),
2562 hard_frame_pointer_rtx
,
2564 df_insn_rescan (insn
);
2569 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
2570 stack_pointer_rtx
));
2573 /* Create a note to describe the CFA. Because this is only used to set
2574 DW_AT_frame_base for debug info, don't bother tracking changes through
2575 each instruction in the prologue. It just takes up space. */
2576 note_rtx
= gen_rtx_SET (VOIDmode
, (frame_pointer_needed
2577 ? hard_frame_pointer_rtx
2578 : stack_pointer_rtx
),
2579 plus_constant (stack_pointer_rtx
, -total_size
));
2580 RTX_FRAME_RELATED_P (insn
) = 1;
2581 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2582 note_rtx
, REG_NOTES (insn
));
2586 /* Clear variables at function end. */
2589 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
2590 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
2592 xtensa_current_frame_size
= 0;
2597 xtensa_return_addr (int count
, rtx frame
)
2599 rtx result
, retaddr
, curaddr
, label
;
2602 retaddr
= gen_rtx_REG (Pmode
, A0_REG
);
2605 rtx addr
= plus_constant (frame
, -4 * UNITS_PER_WORD
);
2606 addr
= memory_address (Pmode
, addr
);
2607 retaddr
= gen_reg_rtx (Pmode
);
2608 emit_move_insn (retaddr
, gen_rtx_MEM (Pmode
, addr
));
2611 /* The 2 most-significant bits of the return address on Xtensa hold
2612 the register window size. To get the real return address, these
2613 bits must be replaced with the high bits from some address in the
2616 /* Get the 2 high bits of a local label in the code. */
2617 curaddr
= gen_reg_rtx (Pmode
);
2618 label
= gen_label_rtx ();
2620 LABEL_PRESERVE_P (label
) = 1;
2621 emit_move_insn (curaddr
, gen_rtx_LABEL_REF (Pmode
, label
));
2622 emit_insn (gen_lshrsi3 (curaddr
, curaddr
, GEN_INT (30)));
2623 emit_insn (gen_ashlsi3 (curaddr
, curaddr
, GEN_INT (30)));
2625 /* Clear the 2 high bits of the return address. */
2626 result
= gen_reg_rtx (Pmode
);
2627 emit_insn (gen_ashlsi3 (result
, retaddr
, GEN_INT (2)));
2628 emit_insn (gen_lshrsi3 (result
, result
, GEN_INT (2)));
2630 /* Combine them to get the result. */
2631 emit_insn (gen_iorsi3 (result
, result
, curaddr
));
2636 /* Create the va_list data type.
2638 This structure is set up by __builtin_saveregs. The __va_reg field
2639 points to a stack-allocated region holding the contents of the
2640 incoming argument registers. The __va_ndx field is an index
2641 initialized to the position of the first unnamed (variable)
2642 argument. This same index is also used to address the arguments
2643 passed in memory. Thus, the __va_stk field is initialized to point
2644 to the position of the first argument in memory offset to account
2645 for the arguments passed in registers and to account for the size
2646 of the argument registers not being 16-byte aligned. E.G., there
2647 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2648 for the first stack argument to have the maximal alignment of 16
2649 bytes, so we offset the __va_stk address by 32 bytes so that
2650 __va_stk[32] references the first argument on the stack. */
2653 xtensa_build_builtin_va_list (void)
2655 tree f_stk
, f_reg
, f_ndx
, record
, type_decl
;
2657 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
2658 type_decl
= build_decl (BUILTINS_LOCATION
,
2659 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
2661 f_stk
= build_decl (BUILTINS_LOCATION
,
2662 FIELD_DECL
, get_identifier ("__va_stk"),
2664 f_reg
= build_decl (BUILTINS_LOCATION
,
2665 FIELD_DECL
, get_identifier ("__va_reg"),
2667 f_ndx
= build_decl (BUILTINS_LOCATION
,
2668 FIELD_DECL
, get_identifier ("__va_ndx"),
2671 DECL_FIELD_CONTEXT (f_stk
) = record
;
2672 DECL_FIELD_CONTEXT (f_reg
) = record
;
2673 DECL_FIELD_CONTEXT (f_ndx
) = record
;
2675 TREE_CHAIN (record
) = type_decl
;
2676 TYPE_NAME (record
) = type_decl
;
2677 TYPE_FIELDS (record
) = f_stk
;
2678 TREE_CHAIN (f_stk
) = f_reg
;
2679 TREE_CHAIN (f_reg
) = f_ndx
;
2681 layout_type (record
);
2686 /* Save the incoming argument registers on the stack. Returns the
2687 address of the saved registers. */
2690 xtensa_builtin_saveregs (void)
2693 int arg_words
= crtl
->args
.info
.arg_words
;
2694 int gp_left
= MAX_ARGS_IN_REGISTERS
- arg_words
;
2699 /* Allocate the general-purpose register space. */
2700 gp_regs
= assign_stack_local
2701 (BLKmode
, MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
, -1);
2702 set_mem_alias_set (gp_regs
, get_varargs_alias_set ());
2704 /* Now store the incoming registers. */
2705 cfun
->machine
->need_a7_copy
= true;
2706 cfun
->machine
->vararg_a7
= true;
2707 move_block_from_reg (GP_ARG_FIRST
+ arg_words
,
2708 adjust_address (gp_regs
, BLKmode
,
2709 arg_words
* UNITS_PER_WORD
),
2711 gcc_assert (cfun
->machine
->vararg_a7_copy
!= 0);
2712 emit_insn_before (cfun
->machine
->vararg_a7_copy
, get_insns ());
2714 return XEXP (gp_regs
, 0);
2718 /* Implement `va_start' for varargs and stdarg. We look at the
2719 current function to fill in an initial va_list. */
2722 xtensa_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
2730 arg_words
= crtl
->args
.info
.arg_words
;
2732 f_stk
= TYPE_FIELDS (va_list_type_node
);
2733 f_reg
= TREE_CHAIN (f_stk
);
2734 f_ndx
= TREE_CHAIN (f_reg
);
2736 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
2737 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), unshare_expr (valist
),
2739 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), unshare_expr (valist
),
2742 /* Call __builtin_saveregs; save the result in __va_reg */
2743 u
= make_tree (sizetype
, expand_builtin_saveregs ());
2744 u
= fold_convert (ptr_type_node
, u
);
2745 t
= build2 (MODIFY_EXPR
, ptr_type_node
, reg
, u
);
2746 TREE_SIDE_EFFECTS (t
) = 1;
2747 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2749 /* Set the __va_stk member to ($arg_ptr - 32). */
2750 u
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
2751 u
= fold_build2 (POINTER_PLUS_EXPR
, ptr_type_node
, u
, size_int (-32));
2752 t
= build2 (MODIFY_EXPR
, ptr_type_node
, stk
, u
);
2753 TREE_SIDE_EFFECTS (t
) = 1;
2754 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2756 /* Set the __va_ndx member. If the first variable argument is on
2757 the stack, adjust __va_ndx by 2 words to account for the extra
2758 alignment offset for __va_stk. */
2759 if (arg_words
>= MAX_ARGS_IN_REGISTERS
)
2761 t
= build2 (MODIFY_EXPR
, integer_type_node
, ndx
,
2762 build_int_cst (integer_type_node
, arg_words
* UNITS_PER_WORD
));
2763 TREE_SIDE_EFFECTS (t
) = 1;
2764 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2768 /* Implement `va_arg'. */
2771 xtensa_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
2772 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
2777 tree type_size
, array
, orig_ndx
, addr
, size
, va_size
, t
;
2778 tree lab_false
, lab_over
, lab_false2
;
2781 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
2783 type
= build_pointer_type (type
);
2785 /* Handle complex values as separate real and imaginary parts. */
2786 if (TREE_CODE (type
) == COMPLEX_TYPE
)
2788 tree real_part
, imag_part
;
2790 real_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
2792 real_part
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
2794 imag_part
= xtensa_gimplify_va_arg_expr (unshare_expr (valist
),
2797 imag_part
= get_initialized_tmp_var (imag_part
, pre_p
, NULL
);
2799 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
2802 f_stk
= TYPE_FIELDS (va_list_type_node
);
2803 f_reg
= TREE_CHAIN (f_stk
);
2804 f_ndx
= TREE_CHAIN (f_reg
);
2806 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
,
2808 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), unshare_expr (valist
),
2810 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), unshare_expr (valist
),
2813 type_size
= size_in_bytes (type
);
2814 va_size
= round_up (type_size
, UNITS_PER_WORD
);
2815 gimplify_expr (&va_size
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
2818 /* First align __va_ndx if necessary for this arg:
2820 orig_ndx = (AP).__va_ndx;
2821 if (__alignof__ (TYPE) > 4 )
2822 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2823 & -__alignof__ (TYPE)); */
2825 orig_ndx
= get_initialized_tmp_var (ndx
, pre_p
, NULL
);
2827 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
2829 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_UNIT
;
2831 t
= build2 (PLUS_EXPR
, integer_type_node
, unshare_expr (orig_ndx
),
2832 build_int_cst (integer_type_node
, align
- 1));
2833 t
= build2 (BIT_AND_EXPR
, integer_type_node
, t
,
2834 build_int_cst (integer_type_node
, -align
));
2835 gimplify_assign (unshare_expr (orig_ndx
), t
, pre_p
);
2839 /* Increment __va_ndx to point past the argument:
2841 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2843 t
= fold_convert (integer_type_node
, va_size
);
2844 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
, t
);
2845 gimplify_assign (unshare_expr (ndx
), t
, pre_p
);
2848 /* Check if the argument is in registers:
2850 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2851 && !must_pass_in_stack (type))
2852 __array = (AP).__va_reg; */
2854 array
= create_tmp_var (ptr_type_node
, NULL
);
2857 if (!targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
2859 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
2860 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
2862 t
= build2 (GT_EXPR
, boolean_type_node
, unshare_expr (ndx
),
2863 build_int_cst (integer_type_node
,
2864 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
2865 t
= build3 (COND_EXPR
, void_type_node
, t
,
2866 build1 (GOTO_EXPR
, void_type_node
, lab_false
),
2868 gimplify_and_add (t
, pre_p
);
2870 gimplify_assign (unshare_expr (array
), reg
, pre_p
);
2872 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
2873 gimplify_and_add (t
, pre_p
);
2875 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
2876 gimplify_and_add (t
, pre_p
);
2880 /* ...otherwise, the argument is on the stack (never split between
2881 registers and the stack -- change __va_ndx if necessary):
2885 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2886 (AP).__va_ndx = 32 + __va_size (TYPE);
2887 __array = (AP).__va_stk;
2890 lab_false2
= create_artificial_label (UNKNOWN_LOCATION
);
2892 t
= build2 (GT_EXPR
, boolean_type_node
, unshare_expr (orig_ndx
),
2893 build_int_cst (integer_type_node
,
2894 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
2895 t
= build3 (COND_EXPR
, void_type_node
, t
,
2896 build1 (GOTO_EXPR
, void_type_node
, lab_false2
),
2898 gimplify_and_add (t
, pre_p
);
2900 t
= size_binop (PLUS_EXPR
, unshare_expr (va_size
), size_int (32));
2901 t
= fold_convert (integer_type_node
, t
);
2902 gimplify_assign (unshare_expr (ndx
), t
, pre_p
);
2904 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false2
);
2905 gimplify_and_add (t
, pre_p
);
2907 gimplify_assign (array
, stk
, pre_p
);
2911 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
2912 gimplify_and_add (t
, pre_p
);
2916 /* Given the base array pointer (__array) and index to the subsequent
2917 argument (__va_ndx), find the address:
2919 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2923 The results are endian-dependent because values smaller than one word
2924 are aligned differently. */
2927 if (BYTES_BIG_ENDIAN
&& TREE_CODE (type_size
) == INTEGER_CST
)
2929 t
= fold_build2 (GE_EXPR
, boolean_type_node
, unshare_expr (type_size
),
2930 size_int (PARM_BOUNDARY
/ BITS_PER_UNIT
));
2931 t
= fold_build3 (COND_EXPR
, sizetype
, t
, unshare_expr (va_size
),
2932 unshare_expr (type_size
));
2936 size
= unshare_expr (va_size
);
2938 t
= fold_convert (sizetype
, unshare_expr (ndx
));
2939 t
= build2 (MINUS_EXPR
, sizetype
, t
, size
);
2940 addr
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, unshare_expr (array
), t
);
2942 addr
= fold_convert (build_pointer_type (type
), addr
);
2944 addr
= build_va_arg_indirect_ref (addr
);
2945 return build_va_arg_indirect_ref (addr
);
2953 XTENSA_BUILTIN_UMULSIDI3
,
2954 XTENSA_BUILTIN_THREAD_POINTER
,
2955 XTENSA_BUILTIN_SET_THREAD_POINTER
,
2961 xtensa_init_builtins (void)
2965 ftype
= build_function_type_list (unsigned_intDI_type_node
,
2966 unsigned_intSI_type_node
,
2967 unsigned_intSI_type_node
, NULL_TREE
);
2969 decl
= add_builtin_function ("__builtin_umulsidi3", ftype
,
2970 XTENSA_BUILTIN_UMULSIDI3
, BUILT_IN_MD
,
2971 "__umulsidi3", NULL_TREE
);
2972 TREE_NOTHROW (decl
) = 1;
2973 TREE_READONLY (decl
) = 1;
2975 if (TARGET_THREADPTR
)
2977 ftype
= build_function_type (ptr_type_node
, void_list_node
);
2978 decl
= add_builtin_function ("__builtin_thread_pointer", ftype
,
2979 XTENSA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
2981 TREE_READONLY (decl
) = 1;
2982 TREE_NOTHROW (decl
) = 1;
2984 ftype
= build_function_type_list (void_type_node
, ptr_type_node
,
2986 decl
= add_builtin_function ("__builtin_set_thread_pointer", ftype
,
2987 XTENSA_BUILTIN_SET_THREAD_POINTER
,
2988 BUILT_IN_MD
, NULL
, NULL_TREE
);
2989 TREE_NOTHROW (decl
) = 1;
2995 xtensa_fold_builtin (tree fndecl
, tree arglist
, bool ignore ATTRIBUTE_UNUSED
)
2997 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
3002 case XTENSA_BUILTIN_UMULSIDI3
:
3003 arg0
= TREE_VALUE (arglist
);
3004 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
3005 if ((TREE_CODE (arg0
) == INTEGER_CST
&& TREE_CODE (arg1
) == INTEGER_CST
)
3006 || TARGET_MUL32_HIGH
)
3007 return fold_build2 (MULT_EXPR
, unsigned_intDI_type_node
,
3008 fold_convert (unsigned_intDI_type_node
, arg0
),
3009 fold_convert (unsigned_intDI_type_node
, arg1
));
3012 case XTENSA_BUILTIN_THREAD_POINTER
:
3013 case XTENSA_BUILTIN_SET_THREAD_POINTER
:
3017 internal_error ("bad builtin code");
3026 xtensa_expand_builtin (tree exp
, rtx target
,
3027 rtx subtarget ATTRIBUTE_UNUSED
,
3028 enum machine_mode mode ATTRIBUTE_UNUSED
,
3031 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
3032 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
3037 case XTENSA_BUILTIN_UMULSIDI3
:
3038 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3039 __umulsidi3 function when the Xtensa configuration can directly
3040 implement it. If not, just call the function. */
3041 return expand_call (exp
, target
, ignore
);
3043 case XTENSA_BUILTIN_THREAD_POINTER
:
3044 if (!target
|| !register_operand (target
, Pmode
))
3045 target
= gen_reg_rtx (Pmode
);
3046 emit_insn (gen_load_tp (target
));
3049 case XTENSA_BUILTIN_SET_THREAD_POINTER
:
3050 arg
= expand_normal (CALL_EXPR_ARG (exp
, 0));
3051 if (!register_operand (arg
, Pmode
))
3052 arg
= copy_to_mode_reg (Pmode
, arg
);
3053 emit_insn (gen_set_tp (arg
));
3057 internal_error ("bad builtin code");
3064 xtensa_preferred_reload_class (rtx x
, enum reg_class rclass
, int isoutput
)
3066 if (!isoutput
&& CONSTANT_P (x
) && GET_CODE (x
) == CONST_DOUBLE
)
3069 /* Don't use the stack pointer or hard frame pointer for reloads!
3070 The hard frame pointer would normally be OK except that it may
3071 briefly hold an incoming argument in the prologue, and reload
3072 won't know that it is live because the hard frame pointer is
3073 treated specially. */
3075 if (rclass
== AR_REGS
|| rclass
== GR_REGS
)
3083 xtensa_secondary_reload (bool in_p
, rtx x
, enum reg_class rclass
,
3084 enum machine_mode mode
, secondary_reload_info
*sri
)
3088 if (in_p
&& constantpool_mem_p (x
))
3090 if (rclass
== FP_REGS
)
3094 sri
->icode
= CODE_FOR_reloadqi_literal
;
3095 else if (mode
== HImode
)
3096 sri
->icode
= CODE_FOR_reloadhi_literal
;
3099 regno
= xt_true_regnum (x
);
3100 if (ACC_REG_P (regno
))
3101 return ((rclass
== GR_REGS
|| rclass
== RL_REGS
) ? NO_REGS
: RL_REGS
);
3102 if (rclass
== ACC_REG
)
3103 return (GP_REG_P (regno
) ? NO_REGS
: RL_REGS
);
3110 order_regs_for_local_alloc (void)
3112 if (!leaf_function_p ())
3114 memcpy (reg_alloc_order
, reg_nonleaf_alloc_order
,
3115 FIRST_PSEUDO_REGISTER
* sizeof (int));
3119 int i
, num_arg_regs
;
3122 /* Use the AR registers in increasing order (skipping a0 and a1)
3123 but save the incoming argument registers for a last resort. */
3124 num_arg_regs
= crtl
->args
.info
.arg_words
;
3125 if (num_arg_regs
> MAX_ARGS_IN_REGISTERS
)
3126 num_arg_regs
= MAX_ARGS_IN_REGISTERS
;
3127 for (i
= GP_ARG_FIRST
; i
< 16 - num_arg_regs
; i
++)
3128 reg_alloc_order
[nxt
++] = i
+ num_arg_regs
;
3129 for (i
= 0; i
< num_arg_regs
; i
++)
3130 reg_alloc_order
[nxt
++] = GP_ARG_FIRST
+ i
;
3132 /* List the coprocessor registers in order. */
3133 for (i
= 0; i
< BR_REG_NUM
; i
++)
3134 reg_alloc_order
[nxt
++] = BR_REG_FIRST
+ i
;
3136 /* List the FP registers in order for now. */
3137 for (i
= 0; i
< 16; i
++)
3138 reg_alloc_order
[nxt
++] = FP_REG_FIRST
+ i
;
3140 /* GCC requires that we list *all* the registers.... */
3141 reg_alloc_order
[nxt
++] = 0; /* a0 = return address */
3142 reg_alloc_order
[nxt
++] = 1; /* a1 = stack pointer */
3143 reg_alloc_order
[nxt
++] = 16; /* pseudo frame pointer */
3144 reg_alloc_order
[nxt
++] = 17; /* pseudo arg pointer */
3146 reg_alloc_order
[nxt
++] = ACC_REG_FIRST
; /* MAC16 accumulator */
3151 /* Some Xtensa targets support multiple bss sections. If the section
3152 name ends with ".bss", add SECTION_BSS to the flags. */
3155 xtensa_multibss_section_type_flags (tree decl
, const char *name
, int reloc
)
3157 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
3160 suffix
= strrchr (name
, '.');
3161 if (suffix
&& strcmp (suffix
, ".bss") == 0)
3163 if (!decl
|| (TREE_CODE (decl
) == VAR_DECL
3164 && DECL_INITIAL (decl
) == NULL_TREE
))
3165 flags
|= SECTION_BSS
; /* @nobits */
3167 warning (0, "only uninitialized variables can be placed in a "
3175 /* The literal pool stays with the function. */
3178 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED
,
3179 rtx x ATTRIBUTE_UNUSED
,
3180 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
3182 return function_section (current_function_decl
);
3186 /* Compute a (partial) cost for rtx X. Return true if the complete
3187 cost has been computed, and false if subexpressions should be
3188 scanned. In either case, *TOTAL contains the cost result. */
3191 xtensa_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
3192 bool speed ATTRIBUTE_UNUSED
)
3200 if (xtensa_simm12b (INTVAL (x
)))
3207 if (xtensa_simm8 (INTVAL (x
))
3208 || xtensa_simm8x256 (INTVAL (x
)))
3215 if (xtensa_mask_immediate (INTVAL (x
)))
3222 if ((INTVAL (x
) == 0) || xtensa_b4const (INTVAL (x
)))
3233 /* No way to tell if X is the 2nd operand so be conservative. */
3236 if (xtensa_simm12b (INTVAL (x
)))
3238 else if (TARGET_CONST16
)
3239 *total
= COSTS_N_INSNS (2);
3248 *total
= COSTS_N_INSNS (2);
3255 *total
= COSTS_N_INSNS (4);
3263 (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
) ? 2 : 1;
3265 if (memory_address_p (GET_MODE (x
), XEXP ((x
), 0)))
3266 *total
= COSTS_N_INSNS (num_words
);
3268 *total
= COSTS_N_INSNS (2*num_words
);
3274 *total
= COSTS_N_INSNS (TARGET_NSA
? 5 : 50);
3278 *total
= COSTS_N_INSNS (TARGET_NSA
? 1 : 50);
3282 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 3 : 2);
3288 if (GET_MODE (x
) == DImode
)
3289 *total
= COSTS_N_INSNS (2);
3291 *total
= COSTS_N_INSNS (1);
3297 if (GET_MODE (x
) == DImode
)
3298 *total
= COSTS_N_INSNS (50);
3300 *total
= COSTS_N_INSNS (1);
3305 enum machine_mode xmode
= GET_MODE (x
);
3306 if (xmode
== SFmode
)
3307 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3308 else if (xmode
== DFmode
)
3309 *total
= COSTS_N_INSNS (50);
3311 *total
= COSTS_N_INSNS (4);
3318 enum machine_mode xmode
= GET_MODE (x
);
3319 if (xmode
== SFmode
)
3320 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3321 else if (xmode
== DFmode
|| xmode
== DImode
)
3322 *total
= COSTS_N_INSNS (50);
3324 *total
= COSTS_N_INSNS (1);
3329 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 4 : 2);
3334 enum machine_mode xmode
= GET_MODE (x
);
3335 if (xmode
== SFmode
)
3336 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 4 : 50);
3337 else if (xmode
== DFmode
)
3338 *total
= COSTS_N_INSNS (50);
3339 else if (xmode
== DImode
)
3340 *total
= COSTS_N_INSNS (TARGET_MUL32_HIGH
? 10 : 50);
3341 else if (TARGET_MUL32
)
3342 *total
= COSTS_N_INSNS (4);
3343 else if (TARGET_MAC16
)
3344 *total
= COSTS_N_INSNS (16);
3345 else if (TARGET_MUL16
)
3346 *total
= COSTS_N_INSNS (12);
3348 *total
= COSTS_N_INSNS (50);
3355 enum machine_mode xmode
= GET_MODE (x
);
3356 if (xmode
== SFmode
)
3358 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV
? 8 : 50);
3361 else if (xmode
== DFmode
)
3363 *total
= COSTS_N_INSNS (50);
3372 enum machine_mode xmode
= GET_MODE (x
);
3373 if (xmode
== DImode
)
3374 *total
= COSTS_N_INSNS (50);
3375 else if (TARGET_DIV32
)
3376 *total
= COSTS_N_INSNS (32);
3378 *total
= COSTS_N_INSNS (50);
3383 if (GET_MODE (x
) == SFmode
)
3384 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT
? 8 : 50);
3386 *total
= COSTS_N_INSNS (50);
3393 *total
= COSTS_N_INSNS (TARGET_MINMAX
? 1 : 50);
3398 *total
= COSTS_N_INSNS (TARGET_SEXT
? 1 : 2);
3403 *total
= COSTS_N_INSNS (1);
3411 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3414 xtensa_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3416 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)
3417 > 4 * UNITS_PER_WORD
);
3420 /* Worker function for TARGET_FUNCTION_VALUE. */
3423 xtensa_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
3426 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype
)
3427 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
3428 ? SImode
: TYPE_MODE (valtype
),
3429 outgoing
? GP_OUTGOING_RETURN
: GP_RETURN
);
3432 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3433 instruction with a minimal stack frame in order to get some free
3434 registers. Once the actual call target is known, the proper stack frame
3435 size is extracted from the ENTRY instruction at the target and the
3436 current frame is adjusted to match. The trampoline then transfers
3437 control to the instruction following the ENTRY at the target. Note:
3438 this assumes that the target begins with an ENTRY instruction. */
3441 xtensa_trampoline_template (FILE *stream
)
3443 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3445 fprintf (stream
, "\t.begin no-transform\n");
3446 fprintf (stream
, "\tentry\tsp, %d\n", MIN_FRAME_SIZE
);
3450 /* Save the return address. */
3451 fprintf (stream
, "\tmov\ta10, a0\n");
3453 /* Use a CALL0 instruction to skip past the constants and in the
3454 process get the PC into A0. This allows PC-relative access to
3455 the constants without relying on L32R. */
3456 fprintf (stream
, "\tcall0\t.Lskipconsts\n");
3459 fprintf (stream
, "\tj\t.Lskipconsts\n");
3461 fprintf (stream
, "\t.align\t4\n");
3462 fprintf (stream
, ".Lchainval:%s0\n", integer_asm_op (4, TRUE
));
3463 fprintf (stream
, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE
));
3464 fprintf (stream
, ".Lskipconsts:\n");
3466 /* Load the static chain and function address from the trampoline. */
3469 fprintf (stream
, "\taddi\ta0, a0, 3\n");
3470 fprintf (stream
, "\tl32i\ta9, a0, 0\n");
3471 fprintf (stream
, "\tl32i\ta8, a0, 4\n");
3475 fprintf (stream
, "\tl32r\ta9, .Lchainval\n");
3476 fprintf (stream
, "\tl32r\ta8, .Lfnaddr\n");
3479 /* Store the static chain. */
3480 fprintf (stream
, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE
- 20);
3482 /* Set the proper stack pointer value. */
3483 fprintf (stream
, "\tl32i\ta9, a8, 0\n");
3484 fprintf (stream
, "\textui\ta9, a9, %d, 12\n",
3485 TARGET_BIG_ENDIAN
? 8 : 12);
3486 fprintf (stream
, "\tslli\ta9, a9, 3\n");
3487 fprintf (stream
, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE
);
3488 fprintf (stream
, "\tsub\ta9, sp, a9\n");
3489 fprintf (stream
, "\tmovsp\tsp, a9\n");
3492 /* Restore the return address. */
3493 fprintf (stream
, "\tmov\ta0, a10\n");
3495 /* Jump to the instruction following the ENTRY. */
3496 fprintf (stream
, "\taddi\ta8, a8, 3\n");
3497 fprintf (stream
, "\tjx\ta8\n");
3499 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3501 fprintf (stream
, "\t.byte\t0\n");
3503 fprintf (stream
, "\tnop\n");
3505 fprintf (stream
, "\t.end no-transform\n");
3510 xtensa_initialize_trampoline (rtx addr
, rtx func
, rtx chain
)
3512 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3513 int chain_off
= use_call0
? 12 : 8;
3514 int func_off
= use_call0
? 16 : 12;
3515 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (addr
, chain_off
)), chain
);
3516 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (addr
, func_off
)), func
);
3517 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_sync_caches"),
3518 0, VOIDmode
, 1, addr
, Pmode
);
3522 #include "gt-xtensa.h"