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Factor unrelated declarations out of tree.h.
[gcc.git] / gcc / config / xtensa / xtensa.c
1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright (C) 2001-2013 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "tm.h"
25 #include "rtl.h"
26 #include "regs.h"
27 #include "hard-reg-set.h"
28 #include "basic-block.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
32 #include "insn-attr.h"
33 #include "insn-codes.h"
34 #include "recog.h"
35 #include "output.h"
36 #include "tree.h"
37 #include "stringpool.h"
38 #include "stor-layout.h"
39 #include "calls.h"
40 #include "varasm.h"
41 #include "expr.h"
42 #include "flags.h"
43 #include "reload.h"
44 #include "tm_p.h"
45 #include "function.h"
46 #include "diagnostic-core.h"
47 #include "optabs.h"
48 #include "libfuncs.h"
49 #include "ggc.h"
50 #include "target.h"
51 #include "target-def.h"
52 #include "langhooks.h"
53 #include "gimple.h"
54 #include "gimplify.h"
55 #include "df.h"
56
57
58 /* Enumeration for all of the relational tests, so that we can build
59 arrays indexed by the test type, and not worry about the order
60 of EQ, NE, etc. */
61
62 enum internal_test
63 {
64 ITEST_EQ,
65 ITEST_NE,
66 ITEST_GT,
67 ITEST_GE,
68 ITEST_LT,
69 ITEST_LE,
70 ITEST_GTU,
71 ITEST_GEU,
72 ITEST_LTU,
73 ITEST_LEU,
74 ITEST_MAX
75 };
76
77 /* Array giving truth value on whether or not a given hard register
78 can support a given mode. */
79 char xtensa_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
80
81 /* Current frame size calculated by compute_frame_size. */
82 unsigned xtensa_current_frame_size;
83
84 /* Largest block move to handle in-line. */
85 #define LARGEST_MOVE_RATIO 15
86
87 /* Define the structure for the machine field in struct function. */
88 struct GTY(()) machine_function
89 {
90 int accesses_prev_frame;
91 bool need_a7_copy;
92 bool vararg_a7;
93 rtx vararg_a7_copy;
94 rtx set_frame_ptr_insn;
95 };
96
97 /* Vector, indexed by hard register number, which contains 1 for a
98 register that is allowable in a candidate for leaf function
99 treatment. */
100
101 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] =
102 {
103 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
104 1, 1, 1,
105 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
106 1
107 };
108
109 /* Map hard register number to register class */
110 const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER] =
111 {
112 RL_REGS, SP_REG, RL_REGS, RL_REGS,
113 RL_REGS, RL_REGS, RL_REGS, GR_REGS,
114 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
115 RL_REGS, RL_REGS, RL_REGS, RL_REGS,
116 AR_REGS, AR_REGS, BR_REGS,
117 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
118 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
119 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
120 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
121 ACC_REG,
122 };
123
124 static void xtensa_option_override (void);
125 static enum internal_test map_test_to_internal_test (enum rtx_code);
126 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *);
127 static rtx gen_float_relational (enum rtx_code, rtx, rtx);
128 static rtx gen_conditional_move (enum rtx_code, enum machine_mode, rtx, rtx);
129 static rtx fixup_subreg_mem (rtx);
130 static struct machine_function * xtensa_init_machine_status (void);
131 static rtx xtensa_legitimize_tls_address (rtx);
132 static rtx xtensa_legitimize_address (rtx, rtx, enum machine_mode);
133 static bool xtensa_mode_dependent_address_p (const_rtx, addr_space_t);
134 static bool xtensa_return_in_msb (const_tree);
135 static void printx (FILE *, signed int);
136 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT);
137 static rtx xtensa_builtin_saveregs (void);
138 static bool xtensa_legitimate_address_p (enum machine_mode, rtx, bool);
139 static unsigned int xtensa_multibss_section_type_flags (tree, const char *,
140 int) ATTRIBUTE_UNUSED;
141 static section *xtensa_select_rtx_section (enum machine_mode, rtx,
142 unsigned HOST_WIDE_INT);
143 static bool xtensa_rtx_costs (rtx, int, int, int, int *, bool);
144 static int xtensa_register_move_cost (enum machine_mode, reg_class_t,
145 reg_class_t);
146 static int xtensa_memory_move_cost (enum machine_mode, reg_class_t, bool);
147 static tree xtensa_build_builtin_va_list (void);
148 static bool xtensa_return_in_memory (const_tree, const_tree);
149 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *,
150 gimple_seq *);
151 static void xtensa_function_arg_advance (cumulative_args_t, enum machine_mode,
152 const_tree, bool);
153 static rtx xtensa_function_arg (cumulative_args_t, enum machine_mode,
154 const_tree, bool);
155 static rtx xtensa_function_incoming_arg (cumulative_args_t,
156 enum machine_mode, const_tree, bool);
157 static rtx xtensa_function_value (const_tree, const_tree, bool);
158 static rtx xtensa_libcall_value (enum machine_mode, const_rtx);
159 static bool xtensa_function_value_regno_p (const unsigned int);
160 static unsigned int xtensa_function_arg_boundary (enum machine_mode,
161 const_tree);
162 static void xtensa_init_builtins (void);
163 static tree xtensa_fold_builtin (tree, int, tree *, bool);
164 static rtx xtensa_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
165 static void xtensa_va_start (tree, rtx);
166 static bool xtensa_frame_pointer_required (void);
167 static rtx xtensa_static_chain (const_tree, bool);
168 static void xtensa_asm_trampoline_template (FILE *);
169 static void xtensa_trampoline_init (rtx, tree, rtx);
170 static bool xtensa_output_addr_const_extra (FILE *, rtx);
171 static bool xtensa_cannot_force_const_mem (enum machine_mode, rtx);
172
173 static reg_class_t xtensa_preferred_reload_class (rtx, reg_class_t);
174 static reg_class_t xtensa_preferred_output_reload_class (rtx, reg_class_t);
175 static reg_class_t xtensa_secondary_reload (bool, rtx, reg_class_t,
176 enum machine_mode,
177 struct secondary_reload_info *);
178
179 static bool constantpool_address_p (const_rtx addr);
180 static bool xtensa_legitimate_constant_p (enum machine_mode, rtx);
181
182 static bool xtensa_member_type_forces_blk (const_tree,
183 enum machine_mode mode);
184
185 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] =
186 REG_ALLOC_ORDER;
187 \f
188
189 /* This macro generates the assembly code for function exit,
190 on machines that need it. If FUNCTION_EPILOGUE is not defined
191 then individual return instructions are generated for each
192 return statement. Args are same as for FUNCTION_PROLOGUE. */
193
194 #undef TARGET_ASM_FUNCTION_EPILOGUE
195 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
196
197 /* These hooks specify assembly directives for creating certain kinds
198 of integer object. */
199
200 #undef TARGET_ASM_ALIGNED_SI_OP
201 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
202
203 #undef TARGET_ASM_SELECT_RTX_SECTION
204 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
205
206 #undef TARGET_LEGITIMIZE_ADDRESS
207 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address
208 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
209 #define TARGET_MODE_DEPENDENT_ADDRESS_P xtensa_mode_dependent_address_p
210
211 #undef TARGET_REGISTER_MOVE_COST
212 #define TARGET_REGISTER_MOVE_COST xtensa_register_move_cost
213 #undef TARGET_MEMORY_MOVE_COST
214 #define TARGET_MEMORY_MOVE_COST xtensa_memory_move_cost
215 #undef TARGET_RTX_COSTS
216 #define TARGET_RTX_COSTS xtensa_rtx_costs
217 #undef TARGET_ADDRESS_COST
218 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
219
220 #undef TARGET_MEMBER_TYPE_FORCES_BLK
221 #define TARGET_MEMBER_TYPE_FORCES_BLK xtensa_member_type_forces_blk
222
223 #undef TARGET_BUILD_BUILTIN_VA_LIST
224 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
225
226 #undef TARGET_EXPAND_BUILTIN_VA_START
227 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
228
229 #undef TARGET_PROMOTE_FUNCTION_MODE
230 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
231 #undef TARGET_PROMOTE_PROTOTYPES
232 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
233
234 #undef TARGET_RETURN_IN_MEMORY
235 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
236 #undef TARGET_FUNCTION_VALUE
237 #define TARGET_FUNCTION_VALUE xtensa_function_value
238 #undef TARGET_LIBCALL_VALUE
239 #define TARGET_LIBCALL_VALUE xtensa_libcall_value
240 #undef TARGET_FUNCTION_VALUE_REGNO_P
241 #define TARGET_FUNCTION_VALUE_REGNO_P xtensa_function_value_regno_p
242
243 #undef TARGET_SPLIT_COMPLEX_ARG
244 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
245 #undef TARGET_MUST_PASS_IN_STACK
246 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
247 #undef TARGET_FUNCTION_ARG_ADVANCE
248 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance
249 #undef TARGET_FUNCTION_ARG
250 #define TARGET_FUNCTION_ARG xtensa_function_arg
251 #undef TARGET_FUNCTION_INCOMING_ARG
252 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg
253 #undef TARGET_FUNCTION_ARG_BOUNDARY
254 #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary
255
256 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
257 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
258 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
259 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
260
261 #undef TARGET_RETURN_IN_MSB
262 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
263
264 #undef TARGET_INIT_BUILTINS
265 #define TARGET_INIT_BUILTINS xtensa_init_builtins
266 #undef TARGET_FOLD_BUILTIN
267 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
268 #undef TARGET_EXPAND_BUILTIN
269 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
270
271 #undef TARGET_PREFERRED_RELOAD_CLASS
272 #define TARGET_PREFERRED_RELOAD_CLASS xtensa_preferred_reload_class
273 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
274 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xtensa_preferred_output_reload_class
275
276 #undef TARGET_SECONDARY_RELOAD
277 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload
278
279 #undef TARGET_HAVE_TLS
280 #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS)
281
282 #undef TARGET_CANNOT_FORCE_CONST_MEM
283 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem
284
285 #undef TARGET_LEGITIMATE_ADDRESS_P
286 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p
287
288 #undef TARGET_FRAME_POINTER_REQUIRED
289 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required
290
291 #undef TARGET_STATIC_CHAIN
292 #define TARGET_STATIC_CHAIN xtensa_static_chain
293 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
294 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template
295 #undef TARGET_TRAMPOLINE_INIT
296 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init
297
298 #undef TARGET_OPTION_OVERRIDE
299 #define TARGET_OPTION_OVERRIDE xtensa_option_override
300
301 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
302 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra
303
304 #undef TARGET_LEGITIMATE_CONSTANT_P
305 #define TARGET_LEGITIMATE_CONSTANT_P xtensa_legitimate_constant_p
306
307 struct gcc_target targetm = TARGET_INITIALIZER;
308
309 \f
310 /* Functions to test Xtensa immediate operand validity. */
311
312 bool
313 xtensa_simm8 (HOST_WIDE_INT v)
314 {
315 return v >= -128 && v <= 127;
316 }
317
318
319 bool
320 xtensa_simm8x256 (HOST_WIDE_INT v)
321 {
322 return (v & 255) == 0 && (v >= -32768 && v <= 32512);
323 }
324
325
326 bool
327 xtensa_simm12b (HOST_WIDE_INT v)
328 {
329 return v >= -2048 && v <= 2047;
330 }
331
332
333 static bool
334 xtensa_uimm8 (HOST_WIDE_INT v)
335 {
336 return v >= 0 && v <= 255;
337 }
338
339
340 static bool
341 xtensa_uimm8x2 (HOST_WIDE_INT v)
342 {
343 return (v & 1) == 0 && (v >= 0 && v <= 510);
344 }
345
346
347 static bool
348 xtensa_uimm8x4 (HOST_WIDE_INT v)
349 {
350 return (v & 3) == 0 && (v >= 0 && v <= 1020);
351 }
352
353
354 static bool
355 xtensa_b4const (HOST_WIDE_INT v)
356 {
357 switch (v)
358 {
359 case -1:
360 case 1:
361 case 2:
362 case 3:
363 case 4:
364 case 5:
365 case 6:
366 case 7:
367 case 8:
368 case 10:
369 case 12:
370 case 16:
371 case 32:
372 case 64:
373 case 128:
374 case 256:
375 return true;
376 }
377 return false;
378 }
379
380
381 bool
382 xtensa_b4const_or_zero (HOST_WIDE_INT v)
383 {
384 if (v == 0)
385 return true;
386 return xtensa_b4const (v);
387 }
388
389
390 bool
391 xtensa_b4constu (HOST_WIDE_INT v)
392 {
393 switch (v)
394 {
395 case 32768:
396 case 65536:
397 case 2:
398 case 3:
399 case 4:
400 case 5:
401 case 6:
402 case 7:
403 case 8:
404 case 10:
405 case 12:
406 case 16:
407 case 32:
408 case 64:
409 case 128:
410 case 256:
411 return true;
412 }
413 return false;
414 }
415
416
417 bool
418 xtensa_mask_immediate (HOST_WIDE_INT v)
419 {
420 #define MAX_MASK_SIZE 16
421 int mask_size;
422
423 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++)
424 {
425 if ((v & 1) == 0)
426 return false;
427 v = v >> 1;
428 if (v == 0)
429 return true;
430 }
431
432 return false;
433 }
434
435
436 /* This is just like the standard true_regnum() function except that it
437 works even when reg_renumber is not initialized. */
438
439 int
440 xt_true_regnum (rtx x)
441 {
442 if (GET_CODE (x) == REG)
443 {
444 if (reg_renumber
445 && REGNO (x) >= FIRST_PSEUDO_REGISTER
446 && reg_renumber[REGNO (x)] >= 0)
447 return reg_renumber[REGNO (x)];
448 return REGNO (x);
449 }
450 if (GET_CODE (x) == SUBREG)
451 {
452 int base = xt_true_regnum (SUBREG_REG (x));
453 if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
454 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)),
455 GET_MODE (SUBREG_REG (x)),
456 SUBREG_BYTE (x), GET_MODE (x));
457 }
458 return -1;
459 }
460
461
462 int
463 xtensa_valid_move (enum machine_mode mode, rtx *operands)
464 {
465 /* Either the destination or source must be a register, and the
466 MAC16 accumulator doesn't count. */
467
468 if (register_operand (operands[0], mode))
469 {
470 int dst_regnum = xt_true_regnum (operands[0]);
471
472 /* The stack pointer can only be assigned with a MOVSP opcode. */
473 if (dst_regnum == STACK_POINTER_REGNUM)
474 return (mode == SImode
475 && register_operand (operands[1], mode)
476 && !ACC_REG_P (xt_true_regnum (operands[1])));
477
478 if (!ACC_REG_P (dst_regnum))
479 return true;
480 }
481 if (register_operand (operands[1], mode))
482 {
483 int src_regnum = xt_true_regnum (operands[1]);
484 if (!ACC_REG_P (src_regnum))
485 return true;
486 }
487 return FALSE;
488 }
489
490
491 int
492 smalloffset_mem_p (rtx op)
493 {
494 if (GET_CODE (op) == MEM)
495 {
496 rtx addr = XEXP (op, 0);
497 if (GET_CODE (addr) == REG)
498 return BASE_REG_P (addr, 0);
499 if (GET_CODE (addr) == PLUS)
500 {
501 rtx offset = XEXP (addr, 0);
502 HOST_WIDE_INT val;
503 if (GET_CODE (offset) != CONST_INT)
504 offset = XEXP (addr, 1);
505 if (GET_CODE (offset) != CONST_INT)
506 return FALSE;
507
508 val = INTVAL (offset);
509 return (val & 3) == 0 && (val >= 0 && val <= 60);
510 }
511 }
512 return FALSE;
513 }
514
515
516 static bool
517 constantpool_address_p (const_rtx addr)
518 {
519 const_rtx sym = addr;
520
521 if (GET_CODE (addr) == CONST)
522 {
523 rtx offset;
524
525 /* Only handle (PLUS (SYM, OFFSET)) form. */
526 addr = XEXP (addr, 0);
527 if (GET_CODE (addr) != PLUS)
528 return false;
529
530 /* Make sure the address is word aligned. */
531 offset = XEXP (addr, 1);
532 if ((!CONST_INT_P (offset))
533 || ((INTVAL (offset) & 3) != 0))
534 return false;
535
536 sym = XEXP (addr, 0);
537 }
538
539 if ((GET_CODE (sym) == SYMBOL_REF)
540 && CONSTANT_POOL_ADDRESS_P (sym))
541 return true;
542 return false;
543 }
544
545
546 int
547 constantpool_mem_p (rtx op)
548 {
549 if (GET_CODE (op) == SUBREG)
550 op = SUBREG_REG (op);
551 if (GET_CODE (op) == MEM)
552 return constantpool_address_p (XEXP (op, 0));
553 return FALSE;
554 }
555
556
557 /* Return TRUE if X is a thread-local symbol. */
558
559 static bool
560 xtensa_tls_symbol_p (rtx x)
561 {
562 if (! TARGET_HAVE_TLS)
563 return false;
564
565 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
566 }
567
568
569 void
570 xtensa_extend_reg (rtx dst, rtx src)
571 {
572 rtx temp = gen_reg_rtx (SImode);
573 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src)));
574
575 /* Generate paradoxical subregs as needed so that the modes match. */
576 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0);
577 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0);
578
579 emit_insn (gen_ashlsi3 (temp, src, shift));
580 emit_insn (gen_ashrsi3 (dst, temp, shift));
581 }
582
583
584 bool
585 xtensa_mem_offset (unsigned v, enum machine_mode mode)
586 {
587 switch (mode)
588 {
589 case BLKmode:
590 /* Handle the worst case for block moves. See xtensa_expand_block_move
591 where we emit an optimized block move operation if the block can be
592 moved in < "move_ratio" pieces. The worst case is when the block is
593 aligned but has a size of (3 mod 4) (does this happen?) so that the
594 last piece requires a byte load/store. */
595 return (xtensa_uimm8 (v)
596 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO));
597
598 case QImode:
599 return xtensa_uimm8 (v);
600
601 case HImode:
602 return xtensa_uimm8x2 (v);
603
604 case DFmode:
605 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4));
606
607 default:
608 break;
609 }
610
611 return xtensa_uimm8x4 (v);
612 }
613
614
615 /* Make normal rtx_code into something we can index from an array. */
616
617 static enum internal_test
618 map_test_to_internal_test (enum rtx_code test_code)
619 {
620 enum internal_test test = ITEST_MAX;
621
622 switch (test_code)
623 {
624 default: break;
625 case EQ: test = ITEST_EQ; break;
626 case NE: test = ITEST_NE; break;
627 case GT: test = ITEST_GT; break;
628 case GE: test = ITEST_GE; break;
629 case LT: test = ITEST_LT; break;
630 case LE: test = ITEST_LE; break;
631 case GTU: test = ITEST_GTU; break;
632 case GEU: test = ITEST_GEU; break;
633 case LTU: test = ITEST_LTU; break;
634 case LEU: test = ITEST_LEU; break;
635 }
636
637 return test;
638 }
639
640
641 /* Generate the code to compare two integer values. The return value is
642 the comparison expression. */
643
644 static rtx
645 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
646 rtx cmp0, /* first operand to compare */
647 rtx cmp1, /* second operand to compare */
648 int *p_invert /* whether branch needs to reverse test */)
649 {
650 struct cmp_info
651 {
652 enum rtx_code test_code; /* test code to use in insn */
653 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */
654 int const_add; /* constant to add (convert LE -> LT) */
655 int reverse_regs; /* reverse registers in test */
656 int invert_const; /* != 0 if invert value if cmp1 is constant */
657 int invert_reg; /* != 0 if invert value if cmp1 is register */
658 int unsignedp; /* != 0 for unsigned comparisons. */
659 };
660
661 static struct cmp_info info[ (int)ITEST_MAX ] = {
662
663 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */
664 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */
665
666 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */
667 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */
668 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */
669 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */
670
671 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */
672 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */
673 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */
674 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */
675 };
676
677 enum internal_test test;
678 enum machine_mode mode;
679 struct cmp_info *p_info;
680
681 test = map_test_to_internal_test (test_code);
682 gcc_assert (test != ITEST_MAX);
683
684 p_info = &info[ (int)test ];
685
686 mode = GET_MODE (cmp0);
687 if (mode == VOIDmode)
688 mode = GET_MODE (cmp1);
689
690 /* Make sure we can handle any constants given to us. */
691 if (GET_CODE (cmp1) == CONST_INT)
692 {
693 HOST_WIDE_INT value = INTVAL (cmp1);
694 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
695
696 /* if the immediate overflows or does not fit in the immediate field,
697 spill it to a register */
698
699 if ((p_info->unsignedp ?
700 (uvalue + p_info->const_add > uvalue) :
701 (value + p_info->const_add > value)) != (p_info->const_add > 0))
702 {
703 cmp1 = force_reg (mode, cmp1);
704 }
705 else if (!(p_info->const_range_p) (value + p_info->const_add))
706 {
707 cmp1 = force_reg (mode, cmp1);
708 }
709 }
710 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
711 {
712 cmp1 = force_reg (mode, cmp1);
713 }
714
715 /* See if we need to invert the result. */
716 *p_invert = ((GET_CODE (cmp1) == CONST_INT)
717 ? p_info->invert_const
718 : p_info->invert_reg);
719
720 /* Comparison to constants, may involve adding 1 to change a LT into LE.
721 Comparison between two registers, may involve switching operands. */
722 if (GET_CODE (cmp1) == CONST_INT)
723 {
724 if (p_info->const_add != 0)
725 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
726
727 }
728 else if (p_info->reverse_regs)
729 {
730 rtx temp = cmp0;
731 cmp0 = cmp1;
732 cmp1 = temp;
733 }
734
735 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1);
736 }
737
738
739 /* Generate the code to compare two float values. The return value is
740 the comparison expression. */
741
742 static rtx
743 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
744 rtx cmp0, /* first operand to compare */
745 rtx cmp1 /* second operand to compare */)
746 {
747 rtx (*gen_fn) (rtx, rtx, rtx);
748 rtx brtmp;
749 int reverse_regs, invert;
750
751 switch (test_code)
752 {
753 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break;
754 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break;
755 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break;
756 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break;
757 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break;
758 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break;
759 case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break;
760 case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break;
761 case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break;
762 case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break;
763 case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break;
764 case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break;
765 case UNORDERED:
766 reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break;
767 case ORDERED:
768 reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break;
769 default:
770 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
771 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */
772 }
773
774 if (reverse_regs)
775 {
776 rtx temp = cmp0;
777 cmp0 = cmp1;
778 cmp1 = temp;
779 }
780
781 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM);
782 emit_insn (gen_fn (brtmp, cmp0, cmp1));
783
784 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx);
785 }
786
787
788 void
789 xtensa_expand_conditional_branch (rtx *operands, enum machine_mode mode)
790 {
791 enum rtx_code test_code = GET_CODE (operands[0]);
792 rtx cmp0 = operands[1];
793 rtx cmp1 = operands[2];
794 rtx cmp;
795 int invert;
796 rtx label1, label2;
797
798 switch (mode)
799 {
800 case DFmode:
801 default:
802 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
803
804 case SImode:
805 invert = FALSE;
806 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert);
807 break;
808
809 case SFmode:
810 if (!TARGET_HARD_FLOAT)
811 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode,
812 cmp0, cmp1));
813 invert = FALSE;
814 cmp = gen_float_relational (test_code, cmp0, cmp1);
815 break;
816 }
817
818 /* Generate the branch. */
819
820 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
821 label2 = pc_rtx;
822
823 if (invert)
824 {
825 label2 = label1;
826 label1 = pc_rtx;
827 }
828
829 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
830 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
831 label1,
832 label2)));
833 }
834
835
836 static rtx
837 gen_conditional_move (enum rtx_code code, enum machine_mode mode,
838 rtx op0, rtx op1)
839 {
840 if (mode == SImode)
841 {
842 rtx cmp;
843
844 /* Jump optimization calls get_condition() which canonicalizes
845 comparisons like (GE x <const>) to (GT x <const-1>).
846 Transform those comparisons back to GE, since that is the
847 comparison supported in Xtensa. We shouldn't have to
848 transform <LE x const> comparisons, because neither
849 xtensa_expand_conditional_branch() nor get_condition() will
850 produce them. */
851
852 if ((code == GT) && (op1 == constm1_rtx))
853 {
854 code = GE;
855 op1 = const0_rtx;
856 }
857 cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
858
859 if (boolean_operator (cmp, VOIDmode))
860 {
861 /* Swap the operands to make const0 second. */
862 if (op0 == const0_rtx)
863 {
864 op0 = op1;
865 op1 = const0_rtx;
866 }
867
868 /* If not comparing against zero, emit a comparison (subtract). */
869 if (op1 != const0_rtx)
870 {
871 op0 = expand_binop (SImode, sub_optab, op0, op1,
872 0, 0, OPTAB_LIB_WIDEN);
873 op1 = const0_rtx;
874 }
875 }
876 else if (branch_operator (cmp, VOIDmode))
877 {
878 /* Swap the operands to make const0 second. */
879 if (op0 == const0_rtx)
880 {
881 op0 = op1;
882 op1 = const0_rtx;
883
884 switch (code)
885 {
886 case LT: code = GE; break;
887 case GE: code = LT; break;
888 default: gcc_unreachable ();
889 }
890 }
891
892 if (op1 != const0_rtx)
893 return 0;
894 }
895 else
896 return 0;
897
898 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
899 }
900
901 if (TARGET_HARD_FLOAT && mode == SFmode)
902 return gen_float_relational (code, op0, op1);
903
904 return 0;
905 }
906
907
908 int
909 xtensa_expand_conditional_move (rtx *operands, int isflt)
910 {
911 rtx dest = operands[0];
912 rtx cmp = operands[1];
913 enum machine_mode cmp_mode = GET_MODE (XEXP (cmp, 0));
914 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
915
916 if (!(cmp = gen_conditional_move (GET_CODE (cmp), cmp_mode,
917 XEXP (cmp, 0), XEXP (cmp, 1))))
918 return 0;
919
920 if (isflt)
921 gen_fn = (cmp_mode == SImode
922 ? gen_movsfcc_internal0
923 : gen_movsfcc_internal1);
924 else
925 gen_fn = (cmp_mode == SImode
926 ? gen_movsicc_internal0
927 : gen_movsicc_internal1);
928
929 emit_insn (gen_fn (dest, XEXP (cmp, 0), operands[2], operands[3], cmp));
930 return 1;
931 }
932
933
934 int
935 xtensa_expand_scc (rtx operands[4], enum machine_mode cmp_mode)
936 {
937 rtx dest = operands[0];
938 rtx cmp;
939 rtx one_tmp, zero_tmp;
940 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
941
942 if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode,
943 operands[2], operands[3])))
944 return 0;
945
946 one_tmp = gen_reg_rtx (SImode);
947 zero_tmp = gen_reg_rtx (SImode);
948 emit_insn (gen_movsi (one_tmp, const_true_rtx));
949 emit_insn (gen_movsi (zero_tmp, const0_rtx));
950
951 gen_fn = (cmp_mode == SImode
952 ? gen_movsicc_internal0
953 : gen_movsicc_internal1);
954 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp));
955 return 1;
956 }
957
958
959 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
960 for the output, i.e., the input operands are twice as big as MODE. */
961
962 void
963 xtensa_split_operand_pair (rtx operands[4], enum machine_mode mode)
964 {
965 switch (GET_CODE (operands[1]))
966 {
967 case REG:
968 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1);
969 operands[2] = gen_rtx_REG (mode, REGNO (operands[1]));
970 break;
971
972 case MEM:
973 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode));
974 operands[2] = adjust_address (operands[1], mode, 0);
975 break;
976
977 case CONST_INT:
978 case CONST_DOUBLE:
979 split_double (operands[1], &operands[2], &operands[3]);
980 break;
981
982 default:
983 gcc_unreachable ();
984 }
985
986 switch (GET_CODE (operands[0]))
987 {
988 case REG:
989 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1);
990 operands[0] = gen_rtx_REG (mode, REGNO (operands[0]));
991 break;
992
993 case MEM:
994 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode));
995 operands[0] = adjust_address (operands[0], mode, 0);
996 break;
997
998 default:
999 gcc_unreachable ();
1000 }
1001 }
1002
1003
1004 /* Emit insns to move operands[1] into operands[0].
1005 Return 1 if we have written out everything that needs to be done to
1006 do the move. Otherwise, return 0 and the caller will emit the move
1007 normally. */
1008
1009 int
1010 xtensa_emit_move_sequence (rtx *operands, enum machine_mode mode)
1011 {
1012 rtx src = operands[1];
1013
1014 if (CONSTANT_P (src)
1015 && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src))))
1016 {
1017 rtx dst = operands[0];
1018
1019 if (xtensa_tls_referenced_p (src))
1020 {
1021 rtx addend = NULL;
1022
1023 if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS)
1024 {
1025 addend = XEXP (XEXP (src, 0), 1);
1026 src = XEXP (XEXP (src, 0), 0);
1027 }
1028
1029 src = xtensa_legitimize_tls_address (src);
1030 if (addend)
1031 {
1032 src = gen_rtx_PLUS (mode, src, addend);
1033 src = force_operand (src, dst);
1034 }
1035 emit_move_insn (dst, src);
1036 return 1;
1037 }
1038
1039 if (! TARGET_CONST16)
1040 {
1041 src = force_const_mem (SImode, src);
1042 operands[1] = src;
1043 }
1044
1045 /* PC-relative loads are always SImode, and CONST16 is only
1046 supported in the movsi pattern, so add a SUBREG for any other
1047 (smaller) mode. */
1048
1049 if (mode != SImode)
1050 {
1051 if (register_operand (dst, mode))
1052 {
1053 emit_move_insn (simplify_gen_subreg (SImode, dst, mode, 0), src);
1054 return 1;
1055 }
1056 else
1057 {
1058 src = force_reg (SImode, src);
1059 src = gen_lowpart_SUBREG (mode, src);
1060 operands[1] = src;
1061 }
1062 }
1063 }
1064
1065 if (!(reload_in_progress | reload_completed)
1066 && !xtensa_valid_move (mode, operands))
1067 operands[1] = force_reg (mode, operands[1]);
1068
1069 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
1070
1071 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
1072 instruction won't be recognized after reload, so we remove the
1073 subreg and adjust mem accordingly. */
1074 if (reload_in_progress)
1075 {
1076 operands[0] = fixup_subreg_mem (operands[0]);
1077 operands[1] = fixup_subreg_mem (operands[1]);
1078 }
1079 return 0;
1080 }
1081
1082
1083 static rtx
1084 fixup_subreg_mem (rtx x)
1085 {
1086 if (GET_CODE (x) == SUBREG
1087 && GET_CODE (SUBREG_REG (x)) == REG
1088 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
1089 {
1090 rtx temp =
1091 gen_rtx_SUBREG (GET_MODE (x),
1092 reg_equiv_mem (REGNO (SUBREG_REG (x))),
1093 SUBREG_BYTE (x));
1094 x = alter_subreg (&temp, true);
1095 }
1096 return x;
1097 }
1098
1099
1100 /* Check if an incoming argument in a7 is expected to be used soon and
1101 if OPND is a register or register pair that includes a7. If so,
1102 create a new pseudo and copy a7 into that pseudo at the very
1103 beginning of the function, followed by the special "set_frame_ptr"
1104 unspec_volatile insn. The return value is either the original
1105 operand, if it is not a7, or the new pseudo containing a copy of
1106 the incoming argument. This is necessary because the register
1107 allocator will ignore conflicts with a7 and may either assign some
1108 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
1109 the incoming argument in a7. By copying the argument out of a7 as
1110 the very first thing, and then immediately following that with an
1111 unspec_volatile to keep the scheduler away, we should avoid any
1112 problems. Putting the set_frame_ptr insn at the beginning, with
1113 only the a7 copy before it, also makes it easier for the prologue
1114 expander to initialize the frame pointer after the a7 copy and to
1115 fix up the a7 copy to use the stack pointer instead of the frame
1116 pointer. */
1117
1118 rtx
1119 xtensa_copy_incoming_a7 (rtx opnd)
1120 {
1121 rtx entry_insns = 0;
1122 rtx reg, tmp;
1123 enum machine_mode mode;
1124
1125 if (!cfun->machine->need_a7_copy)
1126 return opnd;
1127
1128 /* This function should never be called again once a7 has been copied. */
1129 gcc_assert (!cfun->machine->set_frame_ptr_insn);
1130
1131 mode = GET_MODE (opnd);
1132
1133 /* The operand using a7 may come in a later instruction, so just return
1134 the original operand if it doesn't use a7. */
1135 reg = opnd;
1136 if (GET_CODE (reg) == SUBREG)
1137 {
1138 gcc_assert (SUBREG_BYTE (reg) == 0);
1139 reg = SUBREG_REG (reg);
1140 }
1141 if (GET_CODE (reg) != REG
1142 || REGNO (reg) > A7_REG
1143 || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
1144 return opnd;
1145
1146 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1147 gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
1148
1149 cfun->machine->need_a7_copy = false;
1150
1151 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1152 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1153
1154 start_sequence ();
1155 tmp = gen_reg_rtx (mode);
1156
1157 switch (mode)
1158 {
1159 case DFmode:
1160 case DImode:
1161 /* Copy the value out of A7 here but keep the first word in A6 until
1162 after the set_frame_ptr insn. Otherwise, the register allocator
1163 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming
1164 value. */
1165 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4),
1166 gen_raw_REG (SImode, A7_REG)));
1167 break;
1168 case SFmode:
1169 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG)));
1170 break;
1171 case SImode:
1172 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1173 break;
1174 case HImode:
1175 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1176 break;
1177 case QImode:
1178 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG)));
1179 break;
1180 default:
1181 gcc_unreachable ();
1182 }
1183
1184 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ());
1185
1186 /* For DF and DI mode arguments, copy the incoming value in A6 now. */
1187 if (mode == DFmode || mode == DImode)
1188 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0),
1189 gen_rtx_REG (SImode, A7_REG - 1)));
1190 entry_insns = get_insns ();
1191 end_sequence ();
1192
1193 if (cfun->machine->vararg_a7)
1194 {
1195 /* This is called from within builtin_saveregs, which will insert the
1196 saveregs code at the function entry, ahead of anything placed at
1197 the function entry now. Instead, save the sequence to be inserted
1198 at the beginning of the saveregs code. */
1199 cfun->machine->vararg_a7_copy = entry_insns;
1200 }
1201 else
1202 {
1203 /* Put entry_insns after the NOTE that starts the function. If
1204 this is inside a start_sequence, make the outer-level insn
1205 chain current, so the code is placed at the start of the
1206 function. */
1207 push_topmost_sequence ();
1208 /* Do not use entry_of_function() here. This is called from within
1209 expand_function_start, when the CFG still holds GIMPLE. */
1210 emit_insn_after (entry_insns, get_insns ());
1211 pop_topmost_sequence ();
1212 }
1213
1214 return tmp;
1215 }
1216
1217
1218 /* Try to expand a block move operation to a sequence of RTL move
1219 instructions. If not optimizing, or if the block size is not a
1220 constant, or if the block is too large, the expansion fails and GCC
1221 falls back to calling memcpy().
1222
1223 operands[0] is the destination
1224 operands[1] is the source
1225 operands[2] is the length
1226 operands[3] is the alignment */
1227
1228 int
1229 xtensa_expand_block_move (rtx *operands)
1230 {
1231 static const enum machine_mode mode_from_align[] =
1232 {
1233 VOIDmode, QImode, HImode, VOIDmode, SImode,
1234 };
1235
1236 rtx dst_mem = operands[0];
1237 rtx src_mem = operands[1];
1238 HOST_WIDE_INT bytes, align;
1239 int num_pieces, move_ratio;
1240 rtx temp[2];
1241 enum machine_mode mode[2];
1242 int amount[2];
1243 bool active[2];
1244 int phase = 0;
1245 int next;
1246 int offset_ld = 0;
1247 int offset_st = 0;
1248 rtx x;
1249
1250 /* If this is not a fixed size move, just call memcpy. */
1251 if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
1252 return 0;
1253
1254 bytes = INTVAL (operands[2]);
1255 align = INTVAL (operands[3]);
1256
1257 /* Anything to move? */
1258 if (bytes <= 0)
1259 return 0;
1260
1261 if (align > MOVE_MAX)
1262 align = MOVE_MAX;
1263
1264 /* Decide whether to expand inline based on the optimization level. */
1265 move_ratio = 4;
1266 if (optimize > 2)
1267 move_ratio = LARGEST_MOVE_RATIO;
1268 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */
1269 if (num_pieces > move_ratio)
1270 return 0;
1271
1272 x = XEXP (dst_mem, 0);
1273 if (!REG_P (x))
1274 {
1275 x = force_reg (Pmode, x);
1276 dst_mem = replace_equiv_address (dst_mem, x);
1277 }
1278
1279 x = XEXP (src_mem, 0);
1280 if (!REG_P (x))
1281 {
1282 x = force_reg (Pmode, x);
1283 src_mem = replace_equiv_address (src_mem, x);
1284 }
1285
1286 active[0] = active[1] = false;
1287
1288 do
1289 {
1290 next = phase;
1291 phase ^= 1;
1292
1293 if (bytes > 0)
1294 {
1295 int next_amount;
1296
1297 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1));
1298 next_amount = MIN (next_amount, align);
1299
1300 amount[next] = next_amount;
1301 mode[next] = mode_from_align[next_amount];
1302 temp[next] = gen_reg_rtx (mode[next]);
1303
1304 x = adjust_address (src_mem, mode[next], offset_ld);
1305 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1306
1307 offset_ld += next_amount;
1308 bytes -= next_amount;
1309 active[next] = true;
1310 }
1311
1312 if (active[phase])
1313 {
1314 active[phase] = false;
1315
1316 x = adjust_address (dst_mem, mode[phase], offset_st);
1317 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1318
1319 offset_st += amount[phase];
1320 }
1321 }
1322 while (active[next]);
1323
1324 return 1;
1325 }
1326
1327
1328 void
1329 xtensa_expand_nonlocal_goto (rtx *operands)
1330 {
1331 rtx goto_handler = operands[1];
1332 rtx containing_fp = operands[3];
1333
1334 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1335 is too big to generate in-line. */
1336
1337 if (GET_CODE (containing_fp) != REG)
1338 containing_fp = force_reg (Pmode, containing_fp);
1339
1340 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
1341 LCT_NORMAL, VOIDmode, 2,
1342 containing_fp, Pmode,
1343 goto_handler, Pmode);
1344 }
1345
1346
1347 static struct machine_function *
1348 xtensa_init_machine_status (void)
1349 {
1350 return ggc_alloc_cleared_machine_function ();
1351 }
1352
1353
1354 /* Shift VAL of mode MODE left by COUNT bits. */
1355
1356 static inline rtx
1357 xtensa_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
1358 {
1359 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
1360 NULL_RTX, 1, OPTAB_DIRECT);
1361 return expand_simple_binop (SImode, ASHIFT, val, count,
1362 NULL_RTX, 1, OPTAB_DIRECT);
1363 }
1364
1365
1366 /* Structure to hold the initial parameters for a compare_and_swap operation
1367 in HImode and QImode. */
1368
1369 struct alignment_context
1370 {
1371 rtx memsi; /* SI aligned memory location. */
1372 rtx shift; /* Bit offset with regard to lsb. */
1373 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
1374 rtx modemaski; /* ~modemask */
1375 };
1376
1377
1378 /* Initialize structure AC for word access to HI and QI mode memory. */
1379
1380 static void
1381 init_alignment_context (struct alignment_context *ac, rtx mem)
1382 {
1383 enum machine_mode mode = GET_MODE (mem);
1384 rtx byteoffset = NULL_RTX;
1385 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
1386
1387 if (aligned)
1388 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
1389 else
1390 {
1391 /* Alignment is unknown. */
1392 rtx addr, align;
1393
1394 /* Force the address into a register. */
1395 addr = force_reg (Pmode, XEXP (mem, 0));
1396
1397 /* Align it to SImode. */
1398 align = expand_simple_binop (Pmode, AND, addr,
1399 GEN_INT (-GET_MODE_SIZE (SImode)),
1400 NULL_RTX, 1, OPTAB_DIRECT);
1401 /* Generate MEM. */
1402 ac->memsi = gen_rtx_MEM (SImode, align);
1403 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
1404 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
1405 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
1406
1407 byteoffset = expand_simple_binop (Pmode, AND, addr,
1408 GEN_INT (GET_MODE_SIZE (SImode) - 1),
1409 NULL_RTX, 1, OPTAB_DIRECT);
1410 }
1411
1412 /* Calculate shiftcount. */
1413 if (TARGET_BIG_ENDIAN)
1414 {
1415 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
1416 if (!aligned)
1417 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
1418 NULL_RTX, 1, OPTAB_DIRECT);
1419 }
1420 else
1421 {
1422 if (aligned)
1423 ac->shift = NULL_RTX;
1424 else
1425 ac->shift = byteoffset;
1426 }
1427
1428 if (ac->shift != NULL_RTX)
1429 {
1430 /* Shift is the byte count, but we need the bitcount. */
1431 ac->shift = expand_simple_binop (SImode, MULT, ac->shift,
1432 GEN_INT (BITS_PER_UNIT),
1433 NULL_RTX, 1, OPTAB_DIRECT);
1434 ac->modemask = expand_simple_binop (SImode, ASHIFT,
1435 GEN_INT (GET_MODE_MASK (mode)),
1436 ac->shift,
1437 NULL_RTX, 1, OPTAB_DIRECT);
1438 }
1439 else
1440 ac->modemask = GEN_INT (GET_MODE_MASK (mode));
1441
1442 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
1443 }
1444
1445
1446 /* Expand an atomic compare and swap operation for HImode and QImode.
1447 MEM is the memory location, CMP the old value to compare MEM with
1448 and NEW_RTX the value to set if CMP == MEM. */
1449
1450 void
1451 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx)
1452 {
1453 enum machine_mode mode = GET_MODE (mem);
1454 struct alignment_context ac;
1455 rtx tmp, cmpv, newv, val;
1456 rtx oldval = gen_reg_rtx (SImode);
1457 rtx res = gen_reg_rtx (SImode);
1458 rtx csloop = gen_label_rtx ();
1459 rtx csend = gen_label_rtx ();
1460
1461 init_alignment_context (&ac, mem);
1462
1463 if (ac.shift != NULL_RTX)
1464 {
1465 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift);
1466 new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift);
1467 }
1468
1469 /* Load the surrounding word into VAL with the MEM value masked out. */
1470 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi,
1471 ac.modemaski, NULL_RTX, 1,
1472 OPTAB_DIRECT));
1473 emit_label (csloop);
1474
1475 /* Patch CMP and NEW_RTX into VAL at correct position. */
1476 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
1477 NULL_RTX, 1, OPTAB_DIRECT));
1478 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
1479 NULL_RTX, 1, OPTAB_DIRECT));
1480
1481 /* Jump to end if we're done. */
1482 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv));
1483 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend);
1484
1485 /* Check for changes outside mode. */
1486 emit_move_insn (oldval, val);
1487 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski,
1488 val, 1, OPTAB_DIRECT);
1489 if (tmp != val)
1490 emit_move_insn (val, tmp);
1491
1492 /* Loop internal if so. */
1493 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop);
1494
1495 emit_label (csend);
1496
1497 /* Return the correct part of the bitfield. */
1498 convert_move (target,
1499 (ac.shift == NULL_RTX ? res
1500 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
1501 NULL_RTX, 1, OPTAB_DIRECT)),
1502 1);
1503 }
1504
1505
1506 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1507 the default expansion works fine for SImode). MEM is the memory location
1508 and VAL the value to play with. If AFTER is true then store the value
1509 MEM holds after the operation, if AFTER is false then store the value MEM
1510 holds before the operation. If TARGET is zero then discard that value, else
1511 store it to TARGET. */
1512
1513 void
1514 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val,
1515 bool after)
1516 {
1517 enum machine_mode mode = GET_MODE (mem);
1518 struct alignment_context ac;
1519 rtx csloop = gen_label_rtx ();
1520 rtx cmp, tmp;
1521 rtx old = gen_reg_rtx (SImode);
1522 rtx new_rtx = gen_reg_rtx (SImode);
1523 rtx orig = NULL_RTX;
1524
1525 init_alignment_context (&ac, mem);
1526
1527 /* Prepare values before the compare-and-swap loop. */
1528 if (ac.shift != NULL_RTX)
1529 val = xtensa_expand_mask_and_shift (val, mode, ac.shift);
1530 switch (code)
1531 {
1532 case PLUS:
1533 case MINUS:
1534 orig = gen_reg_rtx (SImode);
1535 convert_move (orig, val, 1);
1536 break;
1537
1538 case SET:
1539 case IOR:
1540 case XOR:
1541 break;
1542
1543 case MULT: /* NAND */
1544 case AND:
1545 /* val = "11..1<val>11..1" */
1546 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
1547 NULL_RTX, 1, OPTAB_DIRECT);
1548 break;
1549
1550 default:
1551 gcc_unreachable ();
1552 }
1553
1554 /* Load full word. Subsequent loads are performed by S32C1I. */
1555 cmp = force_reg (SImode, ac.memsi);
1556
1557 emit_label (csloop);
1558 emit_move_insn (old, cmp);
1559
1560 switch (code)
1561 {
1562 case PLUS:
1563 case MINUS:
1564 val = expand_simple_binop (SImode, code, old, orig,
1565 NULL_RTX, 1, OPTAB_DIRECT);
1566 val = expand_simple_binop (SImode, AND, val, ac.modemask,
1567 NULL_RTX, 1, OPTAB_DIRECT);
1568 /* FALLTHRU */
1569 case SET:
1570 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski,
1571 NULL_RTX, 1, OPTAB_DIRECT);
1572 tmp = expand_simple_binop (SImode, IOR, tmp, val,
1573 new_rtx, 1, OPTAB_DIRECT);
1574 break;
1575
1576 case AND:
1577 case IOR:
1578 case XOR:
1579 tmp = expand_simple_binop (SImode, code, old, val,
1580 new_rtx, 1, OPTAB_DIRECT);
1581 break;
1582
1583 case MULT: /* NAND */
1584 tmp = expand_simple_binop (SImode, XOR, old, ac.modemask,
1585 NULL_RTX, 1, OPTAB_DIRECT);
1586 tmp = expand_simple_binop (SImode, AND, tmp, val,
1587 new_rtx, 1, OPTAB_DIRECT);
1588 break;
1589
1590 default:
1591 gcc_unreachable ();
1592 }
1593
1594 if (tmp != new_rtx)
1595 emit_move_insn (new_rtx, tmp);
1596 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx));
1597 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop);
1598
1599 if (target)
1600 {
1601 tmp = (after ? new_rtx : cmp);
1602 convert_move (target,
1603 (ac.shift == NULL_RTX ? tmp
1604 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift,
1605 NULL_RTX, 1, OPTAB_DIRECT)),
1606 1);
1607 }
1608 }
1609
1610
1611 void
1612 xtensa_setup_frame_addresses (void)
1613 {
1614 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */
1615 cfun->machine->accesses_prev_frame = 1;
1616
1617 emit_library_call
1618 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"),
1619 LCT_NORMAL, VOIDmode, 0);
1620 }
1621
1622
1623 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1624 a comment showing where the end of the loop is. However, if there is a
1625 label or a branch at the end of the loop then we need to place a nop
1626 there. If the loop ends with a label we need the nop so that branches
1627 targeting that label will target the nop (and thus remain in the loop),
1628 instead of targeting the instruction after the loop (and thus exiting
1629 the loop). If the loop ends with a branch, we need the nop in case the
1630 branch is targeting a location inside the loop. When the branch
1631 executes it will cause the loop count to be decremented even if it is
1632 taken (because it is the last instruction in the loop), so we need to
1633 nop after the branch to prevent the loop count from being decremented
1634 when the branch is taken. */
1635
1636 void
1637 xtensa_emit_loop_end (rtx insn, rtx *operands)
1638 {
1639 char done = 0;
1640
1641 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn))
1642 {
1643 switch (GET_CODE (insn))
1644 {
1645 case NOTE:
1646 case BARRIER:
1647 break;
1648
1649 case CODE_LABEL:
1650 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1651 done = 1;
1652 break;
1653
1654 default:
1655 {
1656 rtx body = PATTERN (insn);
1657
1658 if (JUMP_P (body))
1659 {
1660 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands);
1661 done = 1;
1662 }
1663 else if ((GET_CODE (body) != USE)
1664 && (GET_CODE (body) != CLOBBER))
1665 done = 1;
1666 }
1667 break;
1668 }
1669 }
1670
1671 output_asm_insn ("# loop end for %0", operands);
1672 }
1673
1674
1675 char *
1676 xtensa_emit_branch (bool inverted, bool immed, rtx *operands)
1677 {
1678 static char result[64];
1679 enum rtx_code code;
1680 const char *op;
1681
1682 code = GET_CODE (operands[3]);
1683 switch (code)
1684 {
1685 case EQ: op = inverted ? "ne" : "eq"; break;
1686 case NE: op = inverted ? "eq" : "ne"; break;
1687 case LT: op = inverted ? "ge" : "lt"; break;
1688 case GE: op = inverted ? "lt" : "ge"; break;
1689 case LTU: op = inverted ? "geu" : "ltu"; break;
1690 case GEU: op = inverted ? "ltu" : "geu"; break;
1691 default: gcc_unreachable ();
1692 }
1693
1694 if (immed)
1695 {
1696 if (INTVAL (operands[1]) == 0)
1697 sprintf (result, "b%sz%s\t%%0, %%2", op,
1698 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : "");
1699 else
1700 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1701 }
1702 else
1703 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1704
1705 return result;
1706 }
1707
1708
1709 char *
1710 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands)
1711 {
1712 static char result[64];
1713 const char *op;
1714
1715 switch (GET_CODE (operands[3]))
1716 {
1717 case EQ: op = inverted ? "bs" : "bc"; break;
1718 case NE: op = inverted ? "bc" : "bs"; break;
1719 default: gcc_unreachable ();
1720 }
1721
1722 if (immed)
1723 {
1724 unsigned bitnum = INTVAL (operands[1]) & 0x1f;
1725 operands[1] = GEN_INT (bitnum);
1726 sprintf (result, "b%si\t%%0, %%d1, %%2", op);
1727 }
1728 else
1729 sprintf (result, "b%s\t%%0, %%1, %%2", op);
1730
1731 return result;
1732 }
1733
1734
1735 char *
1736 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands)
1737 {
1738 static char result[64];
1739 enum rtx_code code;
1740 const char *op;
1741
1742 code = GET_CODE (operands[4]);
1743 if (isbool)
1744 {
1745 switch (code)
1746 {
1747 case EQ: op = inverted ? "t" : "f"; break;
1748 case NE: op = inverted ? "f" : "t"; break;
1749 default: gcc_unreachable ();
1750 }
1751 }
1752 else
1753 {
1754 switch (code)
1755 {
1756 case EQ: op = inverted ? "nez" : "eqz"; break;
1757 case NE: op = inverted ? "eqz" : "nez"; break;
1758 case LT: op = inverted ? "gez" : "ltz"; break;
1759 case GE: op = inverted ? "ltz" : "gez"; break;
1760 default: gcc_unreachable ();
1761 }
1762 }
1763
1764 sprintf (result, "mov%s%s\t%%0, %%%d, %%1",
1765 op, isfp ? ".s" : "", inverted ? 3 : 2);
1766 return result;
1767 }
1768
1769
1770 char *
1771 xtensa_emit_call (int callop, rtx *operands)
1772 {
1773 static char result[64];
1774 rtx tgt = operands[callop];
1775
1776 if (GET_CODE (tgt) == CONST_INT)
1777 sprintf (result, "call8\t0x%lx", INTVAL (tgt));
1778 else if (register_operand (tgt, VOIDmode))
1779 sprintf (result, "callx8\t%%%d", callop);
1780 else
1781 sprintf (result, "call8\t%%%d", callop);
1782
1783 return result;
1784 }
1785
1786
1787 bool
1788 xtensa_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
1789 {
1790 /* Allow constant pool addresses. */
1791 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
1792 && ! TARGET_CONST16 && constantpool_address_p (addr)
1793 && ! xtensa_tls_referenced_p (addr))
1794 return true;
1795
1796 while (GET_CODE (addr) == SUBREG)
1797 addr = SUBREG_REG (addr);
1798
1799 /* Allow base registers. */
1800 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
1801 return true;
1802
1803 /* Check for "register + offset" addressing. */
1804 if (GET_CODE (addr) == PLUS)
1805 {
1806 rtx xplus0 = XEXP (addr, 0);
1807 rtx xplus1 = XEXP (addr, 1);
1808 enum rtx_code code0;
1809 enum rtx_code code1;
1810
1811 while (GET_CODE (xplus0) == SUBREG)
1812 xplus0 = SUBREG_REG (xplus0);
1813 code0 = GET_CODE (xplus0);
1814
1815 while (GET_CODE (xplus1) == SUBREG)
1816 xplus1 = SUBREG_REG (xplus1);
1817 code1 = GET_CODE (xplus1);
1818
1819 /* Swap operands if necessary so the register is first. */
1820 if (code0 != REG && code1 == REG)
1821 {
1822 xplus0 = XEXP (addr, 1);
1823 xplus1 = XEXP (addr, 0);
1824 code0 = GET_CODE (xplus0);
1825 code1 = GET_CODE (xplus1);
1826 }
1827
1828 if (code0 == REG && BASE_REG_P (xplus0, strict)
1829 && code1 == CONST_INT
1830 && xtensa_mem_offset (INTVAL (xplus1), mode))
1831 return true;
1832 }
1833
1834 return false;
1835 }
1836
1837
1838 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
1839
1840 static GTY(()) rtx xtensa_tls_module_base_symbol;
1841
1842 static rtx
1843 xtensa_tls_module_base (void)
1844 {
1845 if (! xtensa_tls_module_base_symbol)
1846 {
1847 xtensa_tls_module_base_symbol =
1848 gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_");
1849 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol)
1850 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
1851 }
1852
1853 return xtensa_tls_module_base_symbol;
1854 }
1855
1856
1857 static rtx
1858 xtensa_call_tls_desc (rtx sym, rtx *retp)
1859 {
1860 rtx fn, arg, a10, call_insn, insns;
1861
1862 start_sequence ();
1863 fn = gen_reg_rtx (Pmode);
1864 arg = gen_reg_rtx (Pmode);
1865 a10 = gen_rtx_REG (Pmode, 10);
1866
1867 emit_insn (gen_tls_func (fn, sym));
1868 emit_insn (gen_tls_arg (arg, sym));
1869 emit_move_insn (a10, arg);
1870 call_insn = emit_call_insn (gen_tls_call (a10, fn, sym, const1_rtx));
1871 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), a10);
1872 insns = get_insns ();
1873 end_sequence ();
1874
1875 *retp = a10;
1876 return insns;
1877 }
1878
1879
1880 static rtx
1881 xtensa_legitimize_tls_address (rtx x)
1882 {
1883 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
1884 rtx dest, tp, ret, modbase, base, addend, insns;
1885
1886 dest = gen_reg_rtx (Pmode);
1887 switch (model)
1888 {
1889 case TLS_MODEL_GLOBAL_DYNAMIC:
1890 insns = xtensa_call_tls_desc (x, &ret);
1891 emit_libcall_block (insns, dest, ret, x);
1892 break;
1893
1894 case TLS_MODEL_LOCAL_DYNAMIC:
1895 base = gen_reg_rtx (Pmode);
1896 modbase = xtensa_tls_module_base ();
1897 insns = xtensa_call_tls_desc (modbase, &ret);
1898 emit_libcall_block (insns, base, ret, modbase);
1899 addend = force_reg (SImode, gen_sym_DTPOFF (x));
1900 emit_insn (gen_addsi3 (dest, base, addend));
1901 break;
1902
1903 case TLS_MODEL_INITIAL_EXEC:
1904 case TLS_MODEL_LOCAL_EXEC:
1905 tp = gen_reg_rtx (SImode);
1906 emit_insn (gen_get_thread_pointersi (tp));
1907 addend = force_reg (SImode, gen_sym_TPOFF (x));
1908 emit_insn (gen_addsi3 (dest, tp, addend));
1909 break;
1910
1911 default:
1912 gcc_unreachable ();
1913 }
1914
1915 return dest;
1916 }
1917
1918
1919 rtx
1920 xtensa_legitimize_address (rtx x,
1921 rtx oldx ATTRIBUTE_UNUSED,
1922 enum machine_mode mode)
1923 {
1924 if (xtensa_tls_symbol_p (x))
1925 return xtensa_legitimize_tls_address (x);
1926
1927 if (GET_CODE (x) == PLUS)
1928 {
1929 rtx plus0 = XEXP (x, 0);
1930 rtx plus1 = XEXP (x, 1);
1931
1932 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
1933 {
1934 plus0 = XEXP (x, 1);
1935 plus1 = XEXP (x, 0);
1936 }
1937
1938 /* Try to split up the offset to use an ADDMI instruction. */
1939 if (GET_CODE (plus0) == REG
1940 && GET_CODE (plus1) == CONST_INT
1941 && !xtensa_mem_offset (INTVAL (plus1), mode)
1942 && !xtensa_simm8 (INTVAL (plus1))
1943 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
1944 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff))
1945 {
1946 rtx temp = gen_reg_rtx (Pmode);
1947 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff);
1948 emit_insn (gen_rtx_SET (Pmode, temp,
1949 gen_rtx_PLUS (Pmode, plus0, addmi_offset)));
1950 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff));
1951 }
1952 }
1953
1954 return x;
1955 }
1956
1957 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
1958
1959 Treat constant-pool references as "mode dependent" since they can
1960 only be accessed with SImode loads. This works around a bug in the
1961 combiner where a constant pool reference is temporarily converted
1962 to an HImode load, which is then assumed to zero-extend based on
1963 our definition of LOAD_EXTEND_OP. This is wrong because the high
1964 bits of a 16-bit value in the constant pool are now sign-extended
1965 by default. */
1966
1967 static bool
1968 xtensa_mode_dependent_address_p (const_rtx addr,
1969 addr_space_t as ATTRIBUTE_UNUSED)
1970 {
1971 return constantpool_address_p (addr);
1972 }
1973
1974 /* Helper for xtensa_tls_referenced_p. */
1975
1976 static int
1977 xtensa_tls_referenced_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1978 {
1979 if (GET_CODE (*x) == SYMBOL_REF)
1980 return SYMBOL_REF_TLS_MODEL (*x) != 0;
1981
1982 /* Ignore TLS references that have already been legitimized. */
1983 if (GET_CODE (*x) == UNSPEC)
1984 {
1985 switch (XINT (*x, 1))
1986 {
1987 case UNSPEC_TPOFF:
1988 case UNSPEC_DTPOFF:
1989 case UNSPEC_TLS_FUNC:
1990 case UNSPEC_TLS_ARG:
1991 case UNSPEC_TLS_CALL:
1992 return -1;
1993 default:
1994 break;
1995 }
1996 }
1997
1998 return 0;
1999 }
2000
2001
2002 /* Return TRUE if X contains any TLS symbol references. */
2003
2004 bool
2005 xtensa_tls_referenced_p (rtx x)
2006 {
2007 if (! TARGET_HAVE_TLS)
2008 return false;
2009
2010 return for_each_rtx (&x, xtensa_tls_referenced_p_1, NULL);
2011 }
2012
2013
2014 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2015
2016 static bool
2017 xtensa_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2018 {
2019 return xtensa_tls_referenced_p (x);
2020 }
2021
2022
2023 /* Return the debugger register number to use for 'regno'. */
2024
2025 int
2026 xtensa_dbx_register_number (int regno)
2027 {
2028 int first = -1;
2029
2030 if (GP_REG_P (regno))
2031 {
2032 regno -= GP_REG_FIRST;
2033 first = 0;
2034 }
2035 else if (BR_REG_P (regno))
2036 {
2037 regno -= BR_REG_FIRST;
2038 first = 16;
2039 }
2040 else if (FP_REG_P (regno))
2041 {
2042 regno -= FP_REG_FIRST;
2043 first = 48;
2044 }
2045 else if (ACC_REG_P (regno))
2046 {
2047 first = 0x200; /* Start of Xtensa special registers. */
2048 regno = 16; /* ACCLO is special register 16. */
2049 }
2050
2051 /* When optimizing, we sometimes get asked about pseudo-registers
2052 that don't represent hard registers. Return 0 for these. */
2053 if (first == -1)
2054 return 0;
2055
2056 return first + regno;
2057 }
2058
2059
2060 /* Argument support functions. */
2061
2062 /* Initialize CUMULATIVE_ARGS for a function. */
2063
2064 void
2065 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming)
2066 {
2067 cum->arg_words = 0;
2068 cum->incoming = incoming;
2069 }
2070
2071
2072 /* Advance the argument to the next argument position. */
2073
2074 static void
2075 xtensa_function_arg_advance (cumulative_args_t cum, enum machine_mode mode,
2076 const_tree type, bool named ATTRIBUTE_UNUSED)
2077 {
2078 int words, max;
2079 int *arg_words;
2080
2081 arg_words = &get_cumulative_args (cum)->arg_words;
2082 max = MAX_ARGS_IN_REGISTERS;
2083
2084 words = (((mode != BLKmode)
2085 ? (int) GET_MODE_SIZE (mode)
2086 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2087
2088 if (*arg_words < max
2089 && (targetm.calls.must_pass_in_stack (mode, type)
2090 || *arg_words + words > max))
2091 *arg_words = max;
2092
2093 *arg_words += words;
2094 }
2095
2096
2097 /* Return an RTL expression containing the register for the given mode,
2098 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
2099 if this is an incoming argument to the current function. */
2100
2101 static rtx
2102 xtensa_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode,
2103 const_tree type, bool incoming_p)
2104 {
2105 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
2106 int regbase, words, max;
2107 int *arg_words;
2108 int regno;
2109
2110 arg_words = &cum->arg_words;
2111 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST);
2112 max = MAX_ARGS_IN_REGISTERS;
2113
2114 words = (((mode != BLKmode)
2115 ? (int) GET_MODE_SIZE (mode)
2116 : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2117
2118 if (type && (TYPE_ALIGN (type) > BITS_PER_WORD))
2119 {
2120 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD;
2121 *arg_words = (*arg_words + align - 1) & -align;
2122 }
2123
2124 if (*arg_words + words > max)
2125 return (rtx)0;
2126
2127 regno = regbase + *arg_words;
2128
2129 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG)
2130 cfun->machine->need_a7_copy = true;
2131
2132 return gen_rtx_REG (mode, regno);
2133 }
2134
2135 /* Implement TARGET_FUNCTION_ARG. */
2136
2137 static rtx
2138 xtensa_function_arg (cumulative_args_t cum, enum machine_mode mode,
2139 const_tree type, bool named ATTRIBUTE_UNUSED)
2140 {
2141 return xtensa_function_arg_1 (cum, mode, type, false);
2142 }
2143
2144 /* Implement TARGET_FUNCTION_INCOMING_ARG. */
2145
2146 static rtx
2147 xtensa_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode,
2148 const_tree type, bool named ATTRIBUTE_UNUSED)
2149 {
2150 return xtensa_function_arg_1 (cum, mode, type, true);
2151 }
2152
2153 static unsigned int
2154 xtensa_function_arg_boundary (enum machine_mode mode, const_tree type)
2155 {
2156 unsigned int alignment;
2157
2158 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
2159 if (alignment < PARM_BOUNDARY)
2160 alignment = PARM_BOUNDARY;
2161 if (alignment > STACK_BOUNDARY)
2162 alignment = STACK_BOUNDARY;
2163 return alignment;
2164 }
2165
2166
2167 static bool
2168 xtensa_return_in_msb (const_tree valtype)
2169 {
2170 return (TARGET_BIG_ENDIAN
2171 && AGGREGATE_TYPE_P (valtype)
2172 && int_size_in_bytes (valtype) >= UNITS_PER_WORD);
2173 }
2174
2175
2176 static void
2177 xtensa_option_override (void)
2178 {
2179 int regno;
2180 enum machine_mode mode;
2181
2182 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT)
2183 error ("boolean registers required for the floating-point option");
2184
2185 /* Set up array giving whether a given register can hold a given mode. */
2186 for (mode = VOIDmode;
2187 mode != MAX_MACHINE_MODE;
2188 mode = (enum machine_mode) ((int) mode + 1))
2189 {
2190 int size = GET_MODE_SIZE (mode);
2191 enum mode_class mclass = GET_MODE_CLASS (mode);
2192
2193 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2194 {
2195 int temp;
2196
2197 if (ACC_REG_P (regno))
2198 temp = (TARGET_MAC16
2199 && (mclass == MODE_INT) && (size <= UNITS_PER_WORD));
2200 else if (GP_REG_P (regno))
2201 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
2202 else if (FP_REG_P (regno))
2203 temp = (TARGET_HARD_FLOAT && (mode == SFmode));
2204 else if (BR_REG_P (regno))
2205 temp = (TARGET_BOOLEANS && (mode == CCmode));
2206 else
2207 temp = FALSE;
2208
2209 xtensa_hard_regno_mode_ok[(int) mode][regno] = temp;
2210 }
2211 }
2212
2213 init_machine_status = xtensa_init_machine_status;
2214
2215 /* Check PIC settings. PIC is only supported when using L32R
2216 instructions, and some targets need to always use PIC. */
2217 if (flag_pic && TARGET_CONST16)
2218 error ("-f%s is not supported with CONST16 instructions",
2219 (flag_pic > 1 ? "PIC" : "pic"));
2220 else if (TARGET_FORCE_NO_PIC)
2221 flag_pic = 0;
2222 else if (XTENSA_ALWAYS_PIC)
2223 {
2224 if (TARGET_CONST16)
2225 error ("PIC is required but not supported with CONST16 instructions");
2226 flag_pic = 1;
2227 }
2228 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
2229 if (flag_pic > 1)
2230 flag_pic = 1;
2231 if (flag_pic && !flag_pie)
2232 flag_shlib = 1;
2233
2234 /* Hot/cold partitioning does not work on this architecture, because of
2235 constant pools (the load instruction cannot necessarily reach that far).
2236 Therefore disable it on this architecture. */
2237 if (flag_reorder_blocks_and_partition)
2238 {
2239 flag_reorder_blocks_and_partition = 0;
2240 flag_reorder_blocks = 1;
2241 }
2242 }
2243
2244 /* A C compound statement to output to stdio stream STREAM the
2245 assembler syntax for an instruction operand X. X is an RTL
2246 expression.
2247
2248 CODE is a value that can be used to specify one of several ways
2249 of printing the operand. It is used when identical operands
2250 must be printed differently depending on the context. CODE
2251 comes from the '%' specification that was used to request
2252 printing of the operand. If the specification was just '%DIGIT'
2253 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
2254 is the ASCII code for LTR.
2255
2256 If X is a register, this macro should print the register's name.
2257 The names can be found in an array 'reg_names' whose type is
2258 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
2259
2260 When the machine description has a specification '%PUNCT' (a '%'
2261 followed by a punctuation character), this macro is called with
2262 a null pointer for X and the punctuation character for CODE.
2263
2264 'a', 'c', 'l', and 'n' are reserved.
2265
2266 The Xtensa specific codes are:
2267
2268 'd' CONST_INT, print as signed decimal
2269 'x' CONST_INT, print as signed hexadecimal
2270 'K' CONST_INT, print number of bits in mask for EXTUI
2271 'R' CONST_INT, print (X & 0x1f)
2272 'L' CONST_INT, print ((32 - X) & 0x1f)
2273 'D' REG, print second register of double-word register operand
2274 'N' MEM, print address of next word following a memory operand
2275 'v' MEM, if memory reference is volatile, output a MEMW before it
2276 't' any constant, add "@h" suffix for top 16 bits
2277 'b' any constant, add "@l" suffix for bottom 16 bits
2278 */
2279
2280 static void
2281 printx (FILE *file, signed int val)
2282 {
2283 /* Print a hexadecimal value in a nice way. */
2284 if ((val > -0xa) && (val < 0xa))
2285 fprintf (file, "%d", val);
2286 else if (val < 0)
2287 fprintf (file, "-0x%x", -val);
2288 else
2289 fprintf (file, "0x%x", val);
2290 }
2291
2292
2293 void
2294 print_operand (FILE *file, rtx x, int letter)
2295 {
2296 if (!x)
2297 error ("PRINT_OPERAND null pointer");
2298
2299 switch (letter)
2300 {
2301 case 'D':
2302 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2303 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
2304 else
2305 output_operand_lossage ("invalid %%D value");
2306 break;
2307
2308 case 'v':
2309 if (GET_CODE (x) == MEM)
2310 {
2311 /* For a volatile memory reference, emit a MEMW before the
2312 load or store. */
2313 if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE)
2314 fprintf (file, "memw\n\t");
2315 }
2316 else
2317 output_operand_lossage ("invalid %%v value");
2318 break;
2319
2320 case 'N':
2321 if (GET_CODE (x) == MEM
2322 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
2323 {
2324 x = adjust_address (x, GET_MODE (x) == DFmode ? SFmode : SImode, 4);
2325 output_address (XEXP (x, 0));
2326 }
2327 else
2328 output_operand_lossage ("invalid %%N value");
2329 break;
2330
2331 case 'K':
2332 if (GET_CODE (x) == CONST_INT)
2333 {
2334 int num_bits = 0;
2335 unsigned val = INTVAL (x);
2336 while (val & 1)
2337 {
2338 num_bits += 1;
2339 val = val >> 1;
2340 }
2341 if ((val != 0) || (num_bits == 0) || (num_bits > 16))
2342 fatal_insn ("invalid mask", x);
2343
2344 fprintf (file, "%d", num_bits);
2345 }
2346 else
2347 output_operand_lossage ("invalid %%K value");
2348 break;
2349
2350 case 'L':
2351 if (GET_CODE (x) == CONST_INT)
2352 fprintf (file, "%ld", (32 - INTVAL (x)) & 0x1f);
2353 else
2354 output_operand_lossage ("invalid %%L value");
2355 break;
2356
2357 case 'R':
2358 if (GET_CODE (x) == CONST_INT)
2359 fprintf (file, "%ld", INTVAL (x) & 0x1f);
2360 else
2361 output_operand_lossage ("invalid %%R value");
2362 break;
2363
2364 case 'x':
2365 if (GET_CODE (x) == CONST_INT)
2366 printx (file, INTVAL (x));
2367 else
2368 output_operand_lossage ("invalid %%x value");
2369 break;
2370
2371 case 'd':
2372 if (GET_CODE (x) == CONST_INT)
2373 fprintf (file, "%ld", INTVAL (x));
2374 else
2375 output_operand_lossage ("invalid %%d value");
2376 break;
2377
2378 case 't':
2379 case 'b':
2380 if (GET_CODE (x) == CONST_INT)
2381 {
2382 printx (file, INTVAL (x));
2383 fputs (letter == 't' ? "@h" : "@l", file);
2384 }
2385 else if (GET_CODE (x) == CONST_DOUBLE)
2386 {
2387 REAL_VALUE_TYPE r;
2388 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2389 if (GET_MODE (x) == SFmode)
2390 {
2391 long l;
2392 REAL_VALUE_TO_TARGET_SINGLE (r, l);
2393 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l');
2394 }
2395 else
2396 output_operand_lossage ("invalid %%t/%%b value");
2397 }
2398 else if (GET_CODE (x) == CONST)
2399 {
2400 /* X must be a symbolic constant on ELF. Write an expression
2401 suitable for 'const16' that sets the high or low 16 bits. */
2402 if (GET_CODE (XEXP (x, 0)) != PLUS
2403 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
2404 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
2405 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
2406 output_operand_lossage ("invalid %%t/%%b value");
2407 print_operand (file, XEXP (XEXP (x, 0), 0), 0);
2408 fputs (letter == 't' ? "@h" : "@l", file);
2409 /* There must be a non-alphanumeric character between 'h' or 'l'
2410 and the number. The '-' is added by print_operand() already. */
2411 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
2412 fputs ("+", file);
2413 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
2414 }
2415 else
2416 {
2417 output_addr_const (file, x);
2418 fputs (letter == 't' ? "@h" : "@l", file);
2419 }
2420 break;
2421
2422 default:
2423 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
2424 fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
2425 else if (GET_CODE (x) == MEM)
2426 output_address (XEXP (x, 0));
2427 else if (GET_CODE (x) == CONST_INT)
2428 fprintf (file, "%ld", INTVAL (x));
2429 else
2430 output_addr_const (file, x);
2431 }
2432 }
2433
2434
2435 /* A C compound statement to output to stdio stream STREAM the
2436 assembler syntax for an instruction operand that is a memory
2437 reference whose address is ADDR. ADDR is an RTL expression. */
2438
2439 void
2440 print_operand_address (FILE *file, rtx addr)
2441 {
2442 if (!addr)
2443 error ("PRINT_OPERAND_ADDRESS, null pointer");
2444
2445 switch (GET_CODE (addr))
2446 {
2447 default:
2448 fatal_insn ("invalid address", addr);
2449 break;
2450
2451 case REG:
2452 fprintf (file, "%s, 0", reg_names [REGNO (addr)]);
2453 break;
2454
2455 case PLUS:
2456 {
2457 rtx reg = (rtx)0;
2458 rtx offset = (rtx)0;
2459 rtx arg0 = XEXP (addr, 0);
2460 rtx arg1 = XEXP (addr, 1);
2461
2462 if (GET_CODE (arg0) == REG)
2463 {
2464 reg = arg0;
2465 offset = arg1;
2466 }
2467 else if (GET_CODE (arg1) == REG)
2468 {
2469 reg = arg1;
2470 offset = arg0;
2471 }
2472 else
2473 fatal_insn ("no register in address", addr);
2474
2475 if (CONSTANT_P (offset))
2476 {
2477 fprintf (file, "%s, ", reg_names [REGNO (reg)]);
2478 output_addr_const (file, offset);
2479 }
2480 else
2481 fatal_insn ("address offset not a constant", addr);
2482 }
2483 break;
2484
2485 case LABEL_REF:
2486 case SYMBOL_REF:
2487 case CONST_INT:
2488 case CONST:
2489 output_addr_const (file, addr);
2490 break;
2491 }
2492 }
2493
2494 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
2495
2496 static bool
2497 xtensa_output_addr_const_extra (FILE *fp, rtx x)
2498 {
2499 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
2500 {
2501 switch (XINT (x, 1))
2502 {
2503 case UNSPEC_TPOFF:
2504 output_addr_const (fp, XVECEXP (x, 0, 0));
2505 fputs ("@TPOFF", fp);
2506 return true;
2507 case UNSPEC_DTPOFF:
2508 output_addr_const (fp, XVECEXP (x, 0, 0));
2509 fputs ("@DTPOFF", fp);
2510 return true;
2511 case UNSPEC_PLT:
2512 if (flag_pic)
2513 {
2514 output_addr_const (fp, XVECEXP (x, 0, 0));
2515 fputs ("@PLT", fp);
2516 return true;
2517 }
2518 break;
2519 default:
2520 break;
2521 }
2522 }
2523 return false;
2524 }
2525
2526
2527 void
2528 xtensa_output_literal (FILE *file, rtx x, enum machine_mode mode, int labelno)
2529 {
2530 long value_long[2];
2531 REAL_VALUE_TYPE r;
2532 int size;
2533 rtx first, second;
2534
2535 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno);
2536
2537 switch (GET_MODE_CLASS (mode))
2538 {
2539 case MODE_FLOAT:
2540 gcc_assert (GET_CODE (x) == CONST_DOUBLE);
2541
2542 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2543 switch (mode)
2544 {
2545 case SFmode:
2546 REAL_VALUE_TO_TARGET_SINGLE (r, value_long[0]);
2547 if (HOST_BITS_PER_LONG > 32)
2548 value_long[0] &= 0xffffffff;
2549 fprintf (file, "0x%08lx\n", value_long[0]);
2550 break;
2551
2552 case DFmode:
2553 REAL_VALUE_TO_TARGET_DOUBLE (r, value_long);
2554 if (HOST_BITS_PER_LONG > 32)
2555 {
2556 value_long[0] &= 0xffffffff;
2557 value_long[1] &= 0xffffffff;
2558 }
2559 fprintf (file, "0x%08lx, 0x%08lx\n",
2560 value_long[0], value_long[1]);
2561 break;
2562
2563 default:
2564 gcc_unreachable ();
2565 }
2566
2567 break;
2568
2569 case MODE_INT:
2570 case MODE_PARTIAL_INT:
2571 size = GET_MODE_SIZE (mode);
2572 switch (size)
2573 {
2574 case 4:
2575 output_addr_const (file, x);
2576 fputs ("\n", file);
2577 break;
2578
2579 case 8:
2580 split_double (x, &first, &second);
2581 output_addr_const (file, first);
2582 fputs (", ", file);
2583 output_addr_const (file, second);
2584 fputs ("\n", file);
2585 break;
2586
2587 default:
2588 gcc_unreachable ();
2589 }
2590 break;
2591
2592 default:
2593 gcc_unreachable ();
2594 }
2595 }
2596
2597
2598 /* Return the bytes needed to compute the frame pointer from the current
2599 stack pointer. */
2600
2601 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2602 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2603
2604 long
2605 compute_frame_size (int size)
2606 {
2607 /* Add space for the incoming static chain value. */
2608 if (cfun->static_chain_decl != NULL)
2609 size += (1 * UNITS_PER_WORD);
2610
2611 xtensa_current_frame_size =
2612 XTENSA_STACK_ALIGN (size
2613 + crtl->outgoing_args_size
2614 + (WINDOW_SIZE * UNITS_PER_WORD));
2615 return xtensa_current_frame_size;
2616 }
2617
2618
2619 bool
2620 xtensa_frame_pointer_required (void)
2621 {
2622 /* The code to expand builtin_frame_addr and builtin_return_addr
2623 currently uses the hard_frame_pointer instead of frame_pointer.
2624 This seems wrong but maybe it's necessary for other architectures.
2625 This function is derived from the i386 code. */
2626
2627 if (cfun->machine->accesses_prev_frame)
2628 return true;
2629
2630 return false;
2631 }
2632
2633
2634 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2635 and the total number of words must be a multiple of 128 bits. */
2636 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2637
2638 void
2639 xtensa_expand_prologue (void)
2640 {
2641 HOST_WIDE_INT total_size;
2642 rtx size_rtx;
2643 rtx insn, note_rtx;
2644
2645 total_size = compute_frame_size (get_frame_size ());
2646 size_rtx = GEN_INT (total_size);
2647
2648 if (total_size < (1 << (12+3)))
2649 insn = emit_insn (gen_entry (size_rtx));
2650 else
2651 {
2652 /* Use a8 as a temporary since a0-a7 may be live. */
2653 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG);
2654 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE)));
2655 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE));
2656 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg));
2657 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg));
2658 }
2659
2660 if (frame_pointer_needed)
2661 {
2662 if (cfun->machine->set_frame_ptr_insn)
2663 {
2664 rtx first;
2665
2666 push_topmost_sequence ();
2667 first = get_insns ();
2668 pop_topmost_sequence ();
2669
2670 /* For all instructions prior to set_frame_ptr_insn, replace
2671 hard_frame_pointer references with stack_pointer. */
2672 for (insn = first;
2673 insn != cfun->machine->set_frame_ptr_insn;
2674 insn = NEXT_INSN (insn))
2675 {
2676 if (INSN_P (insn))
2677 {
2678 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)),
2679 hard_frame_pointer_rtx,
2680 stack_pointer_rtx);
2681 df_insn_rescan (insn);
2682 }
2683 }
2684 }
2685 else
2686 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
2687 stack_pointer_rtx));
2688 }
2689
2690 /* Create a note to describe the CFA. Because this is only used to set
2691 DW_AT_frame_base for debug info, don't bother tracking changes through
2692 each instruction in the prologue. It just takes up space. */
2693 note_rtx = gen_rtx_SET (VOIDmode, (frame_pointer_needed
2694 ? hard_frame_pointer_rtx
2695 : stack_pointer_rtx),
2696 plus_constant (Pmode, stack_pointer_rtx,
2697 -total_size));
2698 RTX_FRAME_RELATED_P (insn) = 1;
2699 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx);
2700 }
2701
2702
2703 /* Clear variables at function end. */
2704
2705 void
2706 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
2707 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
2708 {
2709 xtensa_current_frame_size = 0;
2710 }
2711
2712
2713 rtx
2714 xtensa_return_addr (int count, rtx frame)
2715 {
2716 rtx result, retaddr, curaddr, label;
2717
2718 if (count == -1)
2719 retaddr = gen_rtx_REG (Pmode, A0_REG);
2720 else
2721 {
2722 rtx addr = plus_constant (Pmode, frame, -4 * UNITS_PER_WORD);
2723 addr = memory_address (Pmode, addr);
2724 retaddr = gen_reg_rtx (Pmode);
2725 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr));
2726 }
2727
2728 /* The 2 most-significant bits of the return address on Xtensa hold
2729 the register window size. To get the real return address, these
2730 bits must be replaced with the high bits from some address in the
2731 code. */
2732
2733 /* Get the 2 high bits of a local label in the code. */
2734 curaddr = gen_reg_rtx (Pmode);
2735 label = gen_label_rtx ();
2736 emit_label (label);
2737 LABEL_PRESERVE_P (label) = 1;
2738 emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label));
2739 emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30)));
2740 emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30)));
2741
2742 /* Clear the 2 high bits of the return address. */
2743 result = gen_reg_rtx (Pmode);
2744 emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2)));
2745 emit_insn (gen_lshrsi3 (result, result, GEN_INT (2)));
2746
2747 /* Combine them to get the result. */
2748 emit_insn (gen_iorsi3 (result, result, curaddr));
2749 return result;
2750 }
2751
2752 /* Disable the use of word-sized or smaller complex modes for structures,
2753 and for function arguments in particular, where they cause problems with
2754 register a7. The xtensa_copy_incoming_a7 function assumes that there is
2755 a single reference to an argument in a7, but with small complex modes the
2756 real and imaginary components may be extracted separately, leading to two
2757 uses of the register, only one of which would be replaced. */
2758
2759 static bool
2760 xtensa_member_type_forces_blk (const_tree, enum machine_mode mode)
2761 {
2762 return mode == CQImode || mode == CHImode;
2763 }
2764
2765 /* Create the va_list data type.
2766
2767 This structure is set up by __builtin_saveregs. The __va_reg field
2768 points to a stack-allocated region holding the contents of the
2769 incoming argument registers. The __va_ndx field is an index
2770 initialized to the position of the first unnamed (variable)
2771 argument. This same index is also used to address the arguments
2772 passed in memory. Thus, the __va_stk field is initialized to point
2773 to the position of the first argument in memory offset to account
2774 for the arguments passed in registers and to account for the size
2775 of the argument registers not being 16-byte aligned. E.G., there
2776 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2777 for the first stack argument to have the maximal alignment of 16
2778 bytes, so we offset the __va_stk address by 32 bytes so that
2779 __va_stk[32] references the first argument on the stack. */
2780
2781 static tree
2782 xtensa_build_builtin_va_list (void)
2783 {
2784 tree f_stk, f_reg, f_ndx, record, type_decl;
2785
2786 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
2787 type_decl = build_decl (BUILTINS_LOCATION,
2788 TYPE_DECL, get_identifier ("__va_list_tag"), record);
2789
2790 f_stk = build_decl (BUILTINS_LOCATION,
2791 FIELD_DECL, get_identifier ("__va_stk"),
2792 ptr_type_node);
2793 f_reg = build_decl (BUILTINS_LOCATION,
2794 FIELD_DECL, get_identifier ("__va_reg"),
2795 ptr_type_node);
2796 f_ndx = build_decl (BUILTINS_LOCATION,
2797 FIELD_DECL, get_identifier ("__va_ndx"),
2798 integer_type_node);
2799
2800 DECL_FIELD_CONTEXT (f_stk) = record;
2801 DECL_FIELD_CONTEXT (f_reg) = record;
2802 DECL_FIELD_CONTEXT (f_ndx) = record;
2803
2804 TYPE_STUB_DECL (record) = type_decl;
2805 TYPE_NAME (record) = type_decl;
2806 TYPE_FIELDS (record) = f_stk;
2807 DECL_CHAIN (f_stk) = f_reg;
2808 DECL_CHAIN (f_reg) = f_ndx;
2809
2810 layout_type (record);
2811 return record;
2812 }
2813
2814
2815 /* Save the incoming argument registers on the stack. Returns the
2816 address of the saved registers. */
2817
2818 static rtx
2819 xtensa_builtin_saveregs (void)
2820 {
2821 rtx gp_regs;
2822 int arg_words = crtl->args.info.arg_words;
2823 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words;
2824
2825 if (gp_left <= 0)
2826 return const0_rtx;
2827
2828 /* Allocate the general-purpose register space. */
2829 gp_regs = assign_stack_local
2830 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1);
2831 set_mem_alias_set (gp_regs, get_varargs_alias_set ());
2832
2833 /* Now store the incoming registers. */
2834 cfun->machine->need_a7_copy = true;
2835 cfun->machine->vararg_a7 = true;
2836 move_block_from_reg (GP_ARG_FIRST + arg_words,
2837 adjust_address (gp_regs, BLKmode,
2838 arg_words * UNITS_PER_WORD),
2839 gp_left);
2840 gcc_assert (cfun->machine->vararg_a7_copy != 0);
2841 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ());
2842
2843 return XEXP (gp_regs, 0);
2844 }
2845
2846
2847 /* Implement `va_start' for varargs and stdarg. We look at the
2848 current function to fill in an initial va_list. */
2849
2850 static void
2851 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
2852 {
2853 tree f_stk, stk;
2854 tree f_reg, reg;
2855 tree f_ndx, ndx;
2856 tree t, u;
2857 int arg_words;
2858
2859 arg_words = crtl->args.info.arg_words;
2860
2861 f_stk = TYPE_FIELDS (va_list_type_node);
2862 f_reg = DECL_CHAIN (f_stk);
2863 f_ndx = DECL_CHAIN (f_reg);
2864
2865 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE);
2866 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2867 f_reg, NULL_TREE);
2868 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2869 f_ndx, NULL_TREE);
2870
2871 /* Call __builtin_saveregs; save the result in __va_reg */
2872 u = make_tree (sizetype, expand_builtin_saveregs ());
2873 u = fold_convert (ptr_type_node, u);
2874 t = build2 (MODIFY_EXPR, ptr_type_node, reg, u);
2875 TREE_SIDE_EFFECTS (t) = 1;
2876 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2877
2878 /* Set the __va_stk member to ($arg_ptr - 32). */
2879 u = make_tree (ptr_type_node, virtual_incoming_args_rtx);
2880 u = fold_build_pointer_plus_hwi (u, -32);
2881 t = build2 (MODIFY_EXPR, ptr_type_node, stk, u);
2882 TREE_SIDE_EFFECTS (t) = 1;
2883 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2884
2885 /* Set the __va_ndx member. If the first variable argument is on
2886 the stack, adjust __va_ndx by 2 words to account for the extra
2887 alignment offset for __va_stk. */
2888 if (arg_words >= MAX_ARGS_IN_REGISTERS)
2889 arg_words += 2;
2890 t = build2 (MODIFY_EXPR, integer_type_node, ndx,
2891 build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD));
2892 TREE_SIDE_EFFECTS (t) = 1;
2893 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2894 }
2895
2896
2897 /* Implement `va_arg'. */
2898
2899 static tree
2900 xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
2901 gimple_seq *post_p ATTRIBUTE_UNUSED)
2902 {
2903 tree f_stk, stk;
2904 tree f_reg, reg;
2905 tree f_ndx, ndx;
2906 tree type_size, array, orig_ndx, addr, size, va_size, t;
2907 tree lab_false, lab_over, lab_false2;
2908 bool indirect;
2909
2910 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
2911 if (indirect)
2912 type = build_pointer_type (type);
2913
2914 /* Handle complex values as separate real and imaginary parts. */
2915 if (TREE_CODE (type) == COMPLEX_TYPE)
2916 {
2917 tree real_part, imag_part;
2918
2919 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type),
2920 pre_p, NULL);
2921 real_part = get_initialized_tmp_var (real_part, pre_p, NULL);
2922
2923 imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist),
2924 TREE_TYPE (type),
2925 pre_p, NULL);
2926 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL);
2927
2928 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
2929 }
2930
2931 f_stk = TYPE_FIELDS (va_list_type_node);
2932 f_reg = DECL_CHAIN (f_stk);
2933 f_ndx = DECL_CHAIN (f_reg);
2934
2935 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist,
2936 f_stk, NULL_TREE);
2937 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist),
2938 f_reg, NULL_TREE);
2939 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist),
2940 f_ndx, NULL_TREE);
2941
2942 type_size = size_in_bytes (type);
2943 va_size = round_up (type_size, UNITS_PER_WORD);
2944 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue);
2945
2946
2947 /* First align __va_ndx if necessary for this arg:
2948
2949 orig_ndx = (AP).__va_ndx;
2950 if (__alignof__ (TYPE) > 4 )
2951 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2952 & -__alignof__ (TYPE)); */
2953
2954 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL);
2955
2956 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2957 {
2958 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT;
2959
2960 t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx),
2961 build_int_cst (integer_type_node, align - 1));
2962 t = build2 (BIT_AND_EXPR, integer_type_node, t,
2963 build_int_cst (integer_type_node, -align));
2964 gimplify_assign (unshare_expr (orig_ndx), t, pre_p);
2965 }
2966
2967
2968 /* Increment __va_ndx to point past the argument:
2969
2970 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2971
2972 t = fold_convert (integer_type_node, va_size);
2973 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t);
2974 gimplify_assign (unshare_expr (ndx), t, pre_p);
2975
2976
2977 /* Check if the argument is in registers:
2978
2979 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2980 && !must_pass_in_stack (type))
2981 __array = (AP).__va_reg; */
2982
2983 array = create_tmp_var (ptr_type_node, NULL);
2984
2985 lab_over = NULL;
2986 if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
2987 {
2988 lab_false = create_artificial_label (UNKNOWN_LOCATION);
2989 lab_over = create_artificial_label (UNKNOWN_LOCATION);
2990
2991 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx),
2992 build_int_cst (integer_type_node,
2993 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
2994 t = build3 (COND_EXPR, void_type_node, t,
2995 build1 (GOTO_EXPR, void_type_node, lab_false),
2996 NULL_TREE);
2997 gimplify_and_add (t, pre_p);
2998
2999 gimplify_assign (unshare_expr (array), reg, pre_p);
3000
3001 t = build1 (GOTO_EXPR, void_type_node, lab_over);
3002 gimplify_and_add (t, pre_p);
3003
3004 t = build1 (LABEL_EXPR, void_type_node, lab_false);
3005 gimplify_and_add (t, pre_p);
3006 }
3007
3008
3009 /* ...otherwise, the argument is on the stack (never split between
3010 registers and the stack -- change __va_ndx if necessary):
3011
3012 else
3013 {
3014 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
3015 (AP).__va_ndx = 32 + __va_size (TYPE);
3016 __array = (AP).__va_stk;
3017 } */
3018
3019 lab_false2 = create_artificial_label (UNKNOWN_LOCATION);
3020
3021 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx),
3022 build_int_cst (integer_type_node,
3023 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD));
3024 t = build3 (COND_EXPR, void_type_node, t,
3025 build1 (GOTO_EXPR, void_type_node, lab_false2),
3026 NULL_TREE);
3027 gimplify_and_add (t, pre_p);
3028
3029 t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32));
3030 t = fold_convert (integer_type_node, t);
3031 gimplify_assign (unshare_expr (ndx), t, pre_p);
3032
3033 t = build1 (LABEL_EXPR, void_type_node, lab_false2);
3034 gimplify_and_add (t, pre_p);
3035
3036 gimplify_assign (array, stk, pre_p);
3037
3038 if (lab_over)
3039 {
3040 t = build1 (LABEL_EXPR, void_type_node, lab_over);
3041 gimplify_and_add (t, pre_p);
3042 }
3043
3044
3045 /* Given the base array pointer (__array) and index to the subsequent
3046 argument (__va_ndx), find the address:
3047
3048 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
3049 ? sizeof (TYPE)
3050 : __va_size (TYPE))
3051
3052 The results are endian-dependent because values smaller than one word
3053 are aligned differently. */
3054
3055
3056 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST)
3057 {
3058 t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size),
3059 size_int (PARM_BOUNDARY / BITS_PER_UNIT));
3060 t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size),
3061 unshare_expr (type_size));
3062 size = t;
3063 }
3064 else
3065 size = unshare_expr (va_size);
3066
3067 t = fold_convert (sizetype, unshare_expr (ndx));
3068 t = build2 (MINUS_EXPR, sizetype, t, size);
3069 addr = fold_build_pointer_plus (unshare_expr (array), t);
3070
3071 addr = fold_convert (build_pointer_type (type), addr);
3072 if (indirect)
3073 addr = build_va_arg_indirect_ref (addr);
3074 return build_va_arg_indirect_ref (addr);
3075 }
3076
3077
3078 /* Builtins. */
3079
3080 enum xtensa_builtin
3081 {
3082 XTENSA_BUILTIN_UMULSIDI3,
3083 XTENSA_BUILTIN_max
3084 };
3085
3086
3087 static void
3088 xtensa_init_builtins (void)
3089 {
3090 tree ftype, decl;
3091
3092 ftype = build_function_type_list (unsigned_intDI_type_node,
3093 unsigned_intSI_type_node,
3094 unsigned_intSI_type_node, NULL_TREE);
3095
3096 decl = add_builtin_function ("__builtin_umulsidi3", ftype,
3097 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD,
3098 "__umulsidi3", NULL_TREE);
3099 TREE_NOTHROW (decl) = 1;
3100 TREE_READONLY (decl) = 1;
3101 }
3102
3103
3104 static tree
3105 xtensa_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args,
3106 bool ignore ATTRIBUTE_UNUSED)
3107 {
3108 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3109 tree arg0, arg1;
3110
3111 switch (fcode)
3112 {
3113 case XTENSA_BUILTIN_UMULSIDI3:
3114 arg0 = args[0];
3115 arg1 = args[1];
3116 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST)
3117 || TARGET_MUL32_HIGH)
3118 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node,
3119 fold_convert (unsigned_intDI_type_node, arg0),
3120 fold_convert (unsigned_intDI_type_node, arg1));
3121 break;
3122
3123 default:
3124 internal_error ("bad builtin code");
3125 break;
3126 }
3127
3128 return NULL;
3129 }
3130
3131
3132 static rtx
3133 xtensa_expand_builtin (tree exp, rtx target,
3134 rtx subtarget ATTRIBUTE_UNUSED,
3135 enum machine_mode mode ATTRIBUTE_UNUSED,
3136 int ignore)
3137 {
3138 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
3139 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3140
3141 switch (fcode)
3142 {
3143 case XTENSA_BUILTIN_UMULSIDI3:
3144 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
3145 __umulsidi3 function when the Xtensa configuration can directly
3146 implement it. If not, just call the function. */
3147 return expand_call (exp, target, ignore);
3148
3149 default:
3150 internal_error ("bad builtin code");
3151 }
3152 return NULL_RTX;
3153 }
3154
3155 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. */
3156
3157 static reg_class_t
3158 xtensa_preferred_reload_class (rtx x, reg_class_t rclass)
3159 {
3160 if (CONSTANT_P (x) && CONST_DOUBLE_P (x))
3161 return NO_REGS;
3162
3163 /* Don't use the stack pointer or hard frame pointer for reloads!
3164 The hard frame pointer would normally be OK except that it may
3165 briefly hold an incoming argument in the prologue, and reload
3166 won't know that it is live because the hard frame pointer is
3167 treated specially. */
3168
3169 if (rclass == AR_REGS || rclass == GR_REGS)
3170 return RL_REGS;
3171
3172 return rclass;
3173 }
3174
3175 /* Worker function for TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
3176
3177 static reg_class_t
3178 xtensa_preferred_output_reload_class (rtx x ATTRIBUTE_UNUSED,
3179 reg_class_t rclass)
3180 {
3181 /* Don't use the stack pointer or hard frame pointer for reloads!
3182 The hard frame pointer would normally be OK except that it may
3183 briefly hold an incoming argument in the prologue, and reload
3184 won't know that it is live because the hard frame pointer is
3185 treated specially. */
3186
3187 if (rclass == AR_REGS || rclass == GR_REGS)
3188 return RL_REGS;
3189
3190 return rclass;
3191 }
3192
3193 /* Worker function for TARGET_SECONDARY_RELOAD. */
3194
3195 static reg_class_t
3196 xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
3197 enum machine_mode mode, secondary_reload_info *sri)
3198 {
3199 int regno;
3200
3201 if (in_p && constantpool_mem_p (x))
3202 {
3203 if (rclass == FP_REGS)
3204 return RL_REGS;
3205
3206 if (mode == QImode)
3207 sri->icode = CODE_FOR_reloadqi_literal;
3208 else if (mode == HImode)
3209 sri->icode = CODE_FOR_reloadhi_literal;
3210 }
3211
3212 regno = xt_true_regnum (x);
3213 if (ACC_REG_P (regno))
3214 return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS);
3215 if (rclass == ACC_REG)
3216 return (GP_REG_P (regno) ? NO_REGS : RL_REGS);
3217
3218 return NO_REGS;
3219 }
3220
3221
3222 void
3223 order_regs_for_local_alloc (void)
3224 {
3225 if (!leaf_function_p ())
3226 {
3227 memcpy (reg_alloc_order, reg_nonleaf_alloc_order,
3228 FIRST_PSEUDO_REGISTER * sizeof (int));
3229 }
3230 else
3231 {
3232 int i, num_arg_regs;
3233 int nxt = 0;
3234
3235 /* Use the AR registers in increasing order (skipping a0 and a1)
3236 but save the incoming argument registers for a last resort. */
3237 num_arg_regs = crtl->args.info.arg_words;
3238 if (num_arg_regs > MAX_ARGS_IN_REGISTERS)
3239 num_arg_regs = MAX_ARGS_IN_REGISTERS;
3240 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++)
3241 reg_alloc_order[nxt++] = i + num_arg_regs;
3242 for (i = 0; i < num_arg_regs; i++)
3243 reg_alloc_order[nxt++] = GP_ARG_FIRST + i;
3244
3245 /* List the coprocessor registers in order. */
3246 for (i = 0; i < BR_REG_NUM; i++)
3247 reg_alloc_order[nxt++] = BR_REG_FIRST + i;
3248
3249 /* List the FP registers in order for now. */
3250 for (i = 0; i < 16; i++)
3251 reg_alloc_order[nxt++] = FP_REG_FIRST + i;
3252
3253 /* GCC requires that we list *all* the registers.... */
3254 reg_alloc_order[nxt++] = 0; /* a0 = return address */
3255 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */
3256 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */
3257 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */
3258
3259 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */
3260 }
3261 }
3262
3263
3264 /* Some Xtensa targets support multiple bss sections. If the section
3265 name ends with ".bss", add SECTION_BSS to the flags. */
3266
3267 static unsigned int
3268 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc)
3269 {
3270 unsigned int flags = default_section_type_flags (decl, name, reloc);
3271 const char *suffix;
3272
3273 suffix = strrchr (name, '.');
3274 if (suffix && strcmp (suffix, ".bss") == 0)
3275 {
3276 if (!decl || (TREE_CODE (decl) == VAR_DECL
3277 && DECL_INITIAL (decl) == NULL_TREE))
3278 flags |= SECTION_BSS; /* @nobits */
3279 else
3280 warning (0, "only uninitialized variables can be placed in a "
3281 ".bss section");
3282 }
3283
3284 return flags;
3285 }
3286
3287
3288 /* The literal pool stays with the function. */
3289
3290 static section *
3291 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
3292 rtx x ATTRIBUTE_UNUSED,
3293 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
3294 {
3295 return function_section (current_function_decl);
3296 }
3297
3298 /* Worker function for TARGET_REGISTER_MOVE_COST. */
3299
3300 static int
3301 xtensa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
3302 reg_class_t from, reg_class_t to)
3303 {
3304 if (from == to && from != BR_REGS && to != BR_REGS)
3305 return 2;
3306 else if (reg_class_subset_p (from, AR_REGS)
3307 && reg_class_subset_p (to, AR_REGS))
3308 return 2;
3309 else if (reg_class_subset_p (from, AR_REGS) && to == ACC_REG)
3310 return 3;
3311 else if (from == ACC_REG && reg_class_subset_p (to, AR_REGS))
3312 return 3;
3313 else
3314 return 10;
3315 }
3316
3317 /* Worker function for TARGET_MEMORY_MOVE_COST. */
3318
3319 static int
3320 xtensa_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
3321 reg_class_t rclass ATTRIBUTE_UNUSED,
3322 bool in ATTRIBUTE_UNUSED)
3323 {
3324 return 4;
3325 }
3326
3327 /* Compute a (partial) cost for rtx X. Return true if the complete
3328 cost has been computed, and false if subexpressions should be
3329 scanned. In either case, *TOTAL contains the cost result. */
3330
3331 static bool
3332 xtensa_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3333 int *total, bool speed ATTRIBUTE_UNUSED)
3334 {
3335 switch (code)
3336 {
3337 case CONST_INT:
3338 switch (outer_code)
3339 {
3340 case SET:
3341 if (xtensa_simm12b (INTVAL (x)))
3342 {
3343 *total = 4;
3344 return true;
3345 }
3346 break;
3347 case PLUS:
3348 if (xtensa_simm8 (INTVAL (x))
3349 || xtensa_simm8x256 (INTVAL (x)))
3350 {
3351 *total = 0;
3352 return true;
3353 }
3354 break;
3355 case AND:
3356 if (xtensa_mask_immediate (INTVAL (x)))
3357 {
3358 *total = 0;
3359 return true;
3360 }
3361 break;
3362 case COMPARE:
3363 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x)))
3364 {
3365 *total = 0;
3366 return true;
3367 }
3368 break;
3369 case ASHIFT:
3370 case ASHIFTRT:
3371 case LSHIFTRT:
3372 case ROTATE:
3373 case ROTATERT:
3374 /* No way to tell if X is the 2nd operand so be conservative. */
3375 default: break;
3376 }
3377 if (xtensa_simm12b (INTVAL (x)))
3378 *total = 5;
3379 else if (TARGET_CONST16)
3380 *total = COSTS_N_INSNS (2);
3381 else
3382 *total = 6;
3383 return true;
3384
3385 case CONST:
3386 case LABEL_REF:
3387 case SYMBOL_REF:
3388 if (TARGET_CONST16)
3389 *total = COSTS_N_INSNS (2);
3390 else
3391 *total = 5;
3392 return true;
3393
3394 case CONST_DOUBLE:
3395 if (TARGET_CONST16)
3396 *total = COSTS_N_INSNS (4);
3397 else
3398 *total = 7;
3399 return true;
3400
3401 case MEM:
3402 {
3403 int num_words =
3404 (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) ? 2 : 1;
3405
3406 if (memory_address_p (GET_MODE (x), XEXP ((x), 0)))
3407 *total = COSTS_N_INSNS (num_words);
3408 else
3409 *total = COSTS_N_INSNS (2*num_words);
3410 return true;
3411 }
3412
3413 case FFS:
3414 case CTZ:
3415 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50);
3416 return true;
3417
3418 case CLZ:
3419 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50);
3420 return true;
3421
3422 case NOT:
3423 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 3 : 2);
3424 return true;
3425
3426 case AND:
3427 case IOR:
3428 case XOR:
3429 if (GET_MODE (x) == DImode)
3430 *total = COSTS_N_INSNS (2);
3431 else
3432 *total = COSTS_N_INSNS (1);
3433 return true;
3434
3435 case ASHIFT:
3436 case ASHIFTRT:
3437 case LSHIFTRT:
3438 if (GET_MODE (x) == DImode)
3439 *total = COSTS_N_INSNS (50);
3440 else
3441 *total = COSTS_N_INSNS (1);
3442 return true;
3443
3444 case ABS:
3445 {
3446 enum machine_mode xmode = GET_MODE (x);
3447 if (xmode == SFmode)
3448 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3449 else if (xmode == DFmode)
3450 *total = COSTS_N_INSNS (50);
3451 else
3452 *total = COSTS_N_INSNS (4);
3453 return true;
3454 }
3455
3456 case PLUS:
3457 case MINUS:
3458 {
3459 enum machine_mode xmode = GET_MODE (x);
3460 if (xmode == SFmode)
3461 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50);
3462 else if (xmode == DFmode || xmode == DImode)
3463 *total = COSTS_N_INSNS (50);
3464 else
3465 *total = COSTS_N_INSNS (1);
3466 return true;
3467 }
3468
3469 case NEG:
3470 *total = COSTS_N_INSNS ((GET_MODE (x) == DImode) ? 4 : 2);
3471 return true;
3472
3473 case MULT:
3474 {
3475 enum machine_mode xmode = GET_MODE (x);
3476 if (xmode == SFmode)
3477 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50);
3478 else if (xmode == DFmode)
3479 *total = COSTS_N_INSNS (50);
3480 else if (xmode == DImode)
3481 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50);
3482 else if (TARGET_MUL32)
3483 *total = COSTS_N_INSNS (4);
3484 else if (TARGET_MAC16)
3485 *total = COSTS_N_INSNS (16);
3486 else if (TARGET_MUL16)
3487 *total = COSTS_N_INSNS (12);
3488 else
3489 *total = COSTS_N_INSNS (50);
3490 return true;
3491 }
3492
3493 case DIV:
3494 case MOD:
3495 {
3496 enum machine_mode xmode = GET_MODE (x);
3497 if (xmode == SFmode)
3498 {
3499 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50);
3500 return true;
3501 }
3502 else if (xmode == DFmode)
3503 {
3504 *total = COSTS_N_INSNS (50);
3505 return true;
3506 }
3507 }
3508 /* Fall through. */
3509
3510 case UDIV:
3511 case UMOD:
3512 {
3513 enum machine_mode xmode = GET_MODE (x);
3514 if (xmode == DImode)
3515 *total = COSTS_N_INSNS (50);
3516 else if (TARGET_DIV32)
3517 *total = COSTS_N_INSNS (32);
3518 else
3519 *total = COSTS_N_INSNS (50);
3520 return true;
3521 }
3522
3523 case SQRT:
3524 if (GET_MODE (x) == SFmode)
3525 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50);
3526 else
3527 *total = COSTS_N_INSNS (50);
3528 return true;
3529
3530 case SMIN:
3531 case UMIN:
3532 case SMAX:
3533 case UMAX:
3534 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50);
3535 return true;
3536
3537 case SIGN_EXTRACT:
3538 case SIGN_EXTEND:
3539 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2);
3540 return true;
3541
3542 case ZERO_EXTRACT:
3543 case ZERO_EXTEND:
3544 *total = COSTS_N_INSNS (1);
3545 return true;
3546
3547 default:
3548 return false;
3549 }
3550 }
3551
3552 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3553
3554 static bool
3555 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3556 {
3557 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)
3558 > 4 * UNITS_PER_WORD);
3559 }
3560
3561 /* Worker function for TARGET_FUNCTION_VALUE. */
3562
3563 rtx
3564 xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
3565 bool outgoing)
3566 {
3567 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype)
3568 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
3569 ? SImode : TYPE_MODE (valtype),
3570 outgoing ? GP_OUTGOING_RETURN : GP_RETURN);
3571 }
3572
3573 /* Worker function for TARGET_LIBCALL_VALUE. */
3574
3575 static rtx
3576 xtensa_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
3577 {
3578 return gen_rtx_REG ((GET_MODE_CLASS (mode) == MODE_INT
3579 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3580 ? SImode : mode, GP_RETURN);
3581 }
3582
3583 /* Worker function TARGET_FUNCTION_VALUE_REGNO_P. */
3584
3585 static bool
3586 xtensa_function_value_regno_p (const unsigned int regno)
3587 {
3588 return (regno == GP_RETURN);
3589 }
3590
3591 /* The static chain is passed in memory. Provide rtx giving 'mem'
3592 expressions that denote where they are stored. */
3593
3594 static rtx
3595 xtensa_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p)
3596 {
3597 rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx;
3598 return gen_frame_mem (Pmode, plus_constant (Pmode, base,
3599 -5 * UNITS_PER_WORD));
3600 }
3601
3602
3603 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3604 instruction with a minimal stack frame in order to get some free
3605 registers. Once the actual call target is known, the proper stack frame
3606 size is extracted from the ENTRY instruction at the target and the
3607 current frame is adjusted to match. The trampoline then transfers
3608 control to the instruction following the ENTRY at the target. Note:
3609 this assumes that the target begins with an ENTRY instruction. */
3610
3611 static void
3612 xtensa_asm_trampoline_template (FILE *stream)
3613 {
3614 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3615
3616 fprintf (stream, "\t.begin no-transform\n");
3617 fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE);
3618
3619 if (use_call0)
3620 {
3621 /* Save the return address. */
3622 fprintf (stream, "\tmov\ta10, a0\n");
3623
3624 /* Use a CALL0 instruction to skip past the constants and in the
3625 process get the PC into A0. This allows PC-relative access to
3626 the constants without relying on L32R. */
3627 fprintf (stream, "\tcall0\t.Lskipconsts\n");
3628 }
3629 else
3630 fprintf (stream, "\tj\t.Lskipconsts\n");
3631
3632 fprintf (stream, "\t.align\t4\n");
3633 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE));
3634 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE));
3635 fprintf (stream, ".Lskipconsts:\n");
3636
3637 /* Load the static chain and function address from the trampoline. */
3638 if (use_call0)
3639 {
3640 fprintf (stream, "\taddi\ta0, a0, 3\n");
3641 fprintf (stream, "\tl32i\ta9, a0, 0\n");
3642 fprintf (stream, "\tl32i\ta8, a0, 4\n");
3643 }
3644 else
3645 {
3646 fprintf (stream, "\tl32r\ta9, .Lchainval\n");
3647 fprintf (stream, "\tl32r\ta8, .Lfnaddr\n");
3648 }
3649
3650 /* Store the static chain. */
3651 fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20);
3652
3653 /* Set the proper stack pointer value. */
3654 fprintf (stream, "\tl32i\ta9, a8, 0\n");
3655 fprintf (stream, "\textui\ta9, a9, %d, 12\n",
3656 TARGET_BIG_ENDIAN ? 8 : 12);
3657 fprintf (stream, "\tslli\ta9, a9, 3\n");
3658 fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE);
3659 fprintf (stream, "\tsub\ta9, sp, a9\n");
3660 fprintf (stream, "\tmovsp\tsp, a9\n");
3661
3662 if (use_call0)
3663 /* Restore the return address. */
3664 fprintf (stream, "\tmov\ta0, a10\n");
3665
3666 /* Jump to the instruction following the ENTRY. */
3667 fprintf (stream, "\taddi\ta8, a8, 3\n");
3668 fprintf (stream, "\tjx\ta8\n");
3669
3670 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3671 if (use_call0)
3672 fprintf (stream, "\t.byte\t0\n");
3673 else
3674 fprintf (stream, "\tnop\n");
3675
3676 fprintf (stream, "\t.end no-transform\n");
3677 }
3678
3679 static void
3680 xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain)
3681 {
3682 rtx func = XEXP (DECL_RTL (fndecl), 0);
3683 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS);
3684 int chain_off = use_call0 ? 12 : 8;
3685 int func_off = use_call0 ? 16 : 12;
3686
3687 emit_block_move (m_tramp, assemble_trampoline_template (),
3688 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
3689
3690 emit_move_insn (adjust_address (m_tramp, SImode, chain_off), chain);
3691 emit_move_insn (adjust_address (m_tramp, SImode, func_off), func);
3692 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"),
3693 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
3694 }
3695
3696 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
3697
3698 static bool
3699 xtensa_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
3700 {
3701 return !xtensa_tls_referenced_p (x);
3702 }
3703
3704 #include "gt-xtensa.h"