1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
3 @c This is part of the GCC manual.
4 @c For copying conditions, see the file gcc.texi.
8 @chapter Machine Descriptions
9 @cindex machine descriptions
11 A machine description has two parts: a file of instruction patterns
12 (@file{.md} file) and a C header file of macro definitions.
14 The @file{.md} file for a target machine contains a pattern for each
15 instruction that the target machine supports (or at least each instruction
16 that is worth telling the compiler about). It may also contain comments.
17 A semicolon causes the rest of the line to be a comment, unless the semicolon
18 is inside a quoted string.
20 See the next chapter for information on the C header file.
23 * Overview:: How the machine description is used.
24 * Patterns:: How to write instruction patterns.
25 * Example:: An explained example of a @code{define_insn} pattern.
26 * RTL Template:: The RTL template defines what insns match a pattern.
27 * Output Template:: The output template says how to make assembler code
29 * Output Statement:: For more generality, write C code to output
31 * Predicates:: Controlling what kinds of operands can be used
33 * Constraints:: Fine-tuning operand selection.
34 * Standard Names:: Names mark patterns to use for code generation.
35 * Pattern Ordering:: When the order of patterns makes a difference.
36 * Dependent Patterns:: Having one pattern may make you need another.
37 * Jump Patterns:: Special considerations for patterns for jump insns.
38 * Looping Patterns:: How to define patterns for special looping insns.
39 * Insn Canonicalizations::Canonicalization of Instructions
40 * Expander Definitions::Generating a sequence of several RTL insns
41 for a standard operation.
42 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
43 * Including Patterns:: Including Patterns in Machine Descriptions.
44 * Peephole Definitions::Defining machine-specific peephole optimizations.
45 * Insn Attributes:: Specifying the value of attributes for generated insns.
46 * Conditional Execution::Generating @code{define_insn} patterns for
48 * Constant Definitions::Defining symbolic constants that can be used in the
50 * Macros:: Using macros to generate patterns from a template.
54 @section Overview of How the Machine Description is Used
56 There are three main conversions that happen in the compiler:
61 The front end reads the source code and builds a parse tree.
64 The parse tree is used to generate an RTL insn list based on named
68 The insn list is matched against the RTL templates to produce assembler
73 For the generate pass, only the names of the insns matter, from either a
74 named @code{define_insn} or a @code{define_expand}. The compiler will
75 choose the pattern with the right name and apply the operands according
76 to the documentation later in this chapter, without regard for the RTL
77 template or operand constraints. Note that the names the compiler looks
78 for are hard-coded in the compiler---it will ignore unnamed patterns and
79 patterns with names it doesn't know about, but if you don't provide a
80 named pattern it needs, it will abort.
82 If a @code{define_insn} is used, the template given is inserted into the
83 insn list. If a @code{define_expand} is used, one of three things
84 happens, based on the condition logic. The condition logic may manually
85 create new insns for the insn list, say via @code{emit_insn()}, and
86 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
87 compiler to use an alternate way of performing that task. If it invokes
88 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
89 is inserted, as if the @code{define_expand} were a @code{define_insn}.
91 Once the insn list is generated, various optimization passes convert,
92 replace, and rearrange the insns in the insn list. This is where the
93 @code{define_split} and @code{define_peephole} patterns get used, for
96 Finally, the insn list's RTL is matched up with the RTL templates in the
97 @code{define_insn} patterns, and those patterns are used to emit the
98 final assembly code. For this purpose, each named @code{define_insn}
99 acts like it's unnamed, since the names are ignored.
102 @section Everything about Instruction Patterns
104 @cindex instruction patterns
107 Each instruction pattern contains an incomplete RTL expression, with pieces
108 to be filled in later, operand constraints that restrict how the pieces can
109 be filled in, and an output pattern or C code to generate the assembler
110 output, all wrapped up in a @code{define_insn} expression.
112 A @code{define_insn} is an RTL expression containing four or five operands:
116 An optional name. The presence of a name indicate that this instruction
117 pattern can perform a certain standard job for the RTL-generation
118 pass of the compiler. This pass knows certain names and will use
119 the instruction patterns with those names, if the names are defined
120 in the machine description.
122 The absence of a name is indicated by writing an empty string
123 where the name should go. Nameless instruction patterns are never
124 used for generating RTL code, but they may permit several simpler insns
125 to be combined later on.
127 Names that are not thus known and used in RTL-generation have no
128 effect; they are equivalent to no name at all.
130 For the purpose of debugging the compiler, you may also specify a
131 name beginning with the @samp{*} character. Such a name is used only
132 for identifying the instruction in RTL dumps; it is entirely equivalent
133 to having a nameless pattern for all other purposes.
136 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
137 RTL expressions which show what the instruction should look like. It is
138 incomplete because it may contain @code{match_operand},
139 @code{match_operator}, and @code{match_dup} expressions that stand for
140 operands of the instruction.
142 If the vector has only one element, that element is the template for the
143 instruction pattern. If the vector has multiple elements, then the
144 instruction pattern is a @code{parallel} expression containing the
148 @cindex pattern conditions
149 @cindex conditions, in patterns
150 A condition. This is a string which contains a C expression that is
151 the final test to decide whether an insn body matches this pattern.
153 @cindex named patterns and conditions
154 For a named pattern, the condition (if present) may not depend on
155 the data in the insn being matched, but only the target-machine-type
156 flags. The compiler needs to test these conditions during
157 initialization in order to learn exactly which named instructions are
158 available in a particular run.
161 For nameless patterns, the condition is applied only when matching an
162 individual insn, and only after the insn has matched the pattern's
163 recognition template. The insn's operands may be found in the vector
164 @code{operands}. For an insn where the condition has once matched, it
165 can't be used to control register allocation, for example by excluding
166 certain hard registers or hard register combinations.
169 The @dfn{output template}: a string that says how to output matching
170 insns as assembler code. @samp{%} in this string specifies where
171 to substitute the value of an operand. @xref{Output Template}.
173 When simple substitution isn't general enough, you can specify a piece
174 of C code to compute the output. @xref{Output Statement}.
177 Optionally, a vector containing the values of attributes for insns matching
178 this pattern. @xref{Insn Attributes}.
182 @section Example of @code{define_insn}
183 @cindex @code{define_insn} example
185 Here is an actual example of an instruction pattern, for the 68000/68020.
190 (match_operand:SI 0 "general_operand" "rm"))]
194 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
196 return \"cmpl #0,%0\";
201 This can also be written using braced strings:
206 (match_operand:SI 0 "general_operand" "rm"))]
209 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
215 This is an instruction that sets the condition codes based on the value of
216 a general operand. It has no condition, so any insn whose RTL description
217 has the form shown may be handled according to this pattern. The name
218 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
219 pass that, when it is necessary to test such a value, an insn to do so
220 can be constructed using this pattern.
222 The output control string is a piece of C code which chooses which
223 output template to return based on the kind of operand and the specific
224 type of CPU for which code is being generated.
226 @samp{"rm"} is an operand constraint. Its meaning is explained below.
229 @section RTL Template
230 @cindex RTL insn template
231 @cindex generating insns
232 @cindex insns, generating
233 @cindex recognizing insns
234 @cindex insns, recognizing
236 The RTL template is used to define which insns match the particular pattern
237 and how to find their operands. For named patterns, the RTL template also
238 says how to construct an insn from specified operands.
240 Construction involves substituting specified operands into a copy of the
241 template. Matching involves determining the values that serve as the
242 operands in the insn being matched. Both of these activities are
243 controlled by special expression types that direct matching and
244 substitution of the operands.
247 @findex match_operand
248 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
249 This expression is a placeholder for operand number @var{n} of
250 the insn. When constructing an insn, operand number @var{n}
251 will be substituted at this point. When matching an insn, whatever
252 appears at this position in the insn will be taken as operand
253 number @var{n}; but it must satisfy @var{predicate} or this instruction
254 pattern will not match at all.
256 Operand numbers must be chosen consecutively counting from zero in
257 each instruction pattern. There may be only one @code{match_operand}
258 expression in the pattern for each operand number. Usually operands
259 are numbered in the order of appearance in @code{match_operand}
260 expressions. In the case of a @code{define_expand}, any operand numbers
261 used only in @code{match_dup} expressions have higher values than all
262 other operand numbers.
264 @var{predicate} is a string that is the name of a function that
265 accepts two arguments, an expression and a machine mode.
266 @xref{Predicates}. During matching, the function will be called with
267 the putative operand as the expression and @var{m} as the mode
268 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
269 which normally causes @var{predicate} to accept any mode). If it
270 returns zero, this instruction pattern fails to match.
271 @var{predicate} may be an empty string; then it means no test is to be
272 done on the operand, so anything which occurs in this position is
275 Most of the time, @var{predicate} will reject modes other than @var{m}---but
276 not always. For example, the predicate @code{address_operand} uses
277 @var{m} as the mode of memory ref that the address should be valid for.
278 Many predicates accept @code{const_int} nodes even though their mode is
281 @var{constraint} controls reloading and the choice of the best register
282 class to use for a value, as explained later (@pxref{Constraints}).
283 If the constraint would be an empty string, it can be omitted.
285 People are often unclear on the difference between the constraint and the
286 predicate. The predicate helps decide whether a given insn matches the
287 pattern. The constraint plays no role in this decision; instead, it
288 controls various decisions in the case of an insn which does match.
290 @findex match_scratch
291 @item (match_scratch:@var{m} @var{n} @var{constraint})
292 This expression is also a placeholder for operand number @var{n}
293 and indicates that operand must be a @code{scratch} or @code{reg}
296 When matching patterns, this is equivalent to
299 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
302 but, when generating RTL, it produces a (@code{scratch}:@var{m})
305 If the last few expressions in a @code{parallel} are @code{clobber}
306 expressions whose operands are either a hard register or
307 @code{match_scratch}, the combiner can add or delete them when
308 necessary. @xref{Side Effects}.
311 @item (match_dup @var{n})
312 This expression is also a placeholder for operand number @var{n}.
313 It is used when the operand needs to appear more than once in the
316 In construction, @code{match_dup} acts just like @code{match_operand}:
317 the operand is substituted into the insn being constructed. But in
318 matching, @code{match_dup} behaves differently. It assumes that operand
319 number @var{n} has already been determined by a @code{match_operand}
320 appearing earlier in the recognition template, and it matches only an
321 identical-looking expression.
323 Note that @code{match_dup} should not be used to tell the compiler that
324 a particular register is being used for two operands (example:
325 @code{add} that adds one register to another; the second register is
326 both an input operand and the output operand). Use a matching
327 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
328 operand is used in two places in the template, such as an instruction
329 that computes both a quotient and a remainder, where the opcode takes
330 two input operands but the RTL template has to refer to each of those
331 twice; once for the quotient pattern and once for the remainder pattern.
333 @findex match_operator
334 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
335 This pattern is a kind of placeholder for a variable RTL expression
338 When constructing an insn, it stands for an RTL expression whose
339 expression code is taken from that of operand @var{n}, and whose
340 operands are constructed from the patterns @var{operands}.
342 When matching an expression, it matches an expression if the function
343 @var{predicate} returns nonzero on that expression @emph{and} the
344 patterns @var{operands} match the operands of the expression.
346 Suppose that the function @code{commutative_operator} is defined as
347 follows, to match any expression whose operator is one of the
348 commutative arithmetic operators of RTL and whose mode is @var{mode}:
352 commutative_integer_operator (x, mode)
354 enum machine_mode mode;
356 enum rtx_code code = GET_CODE (x);
357 if (GET_MODE (x) != mode)
359 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
360 || code == EQ || code == NE);
364 Then the following pattern will match any RTL expression consisting
365 of a commutative operator applied to two general operands:
368 (match_operator:SI 3 "commutative_operator"
369 [(match_operand:SI 1 "general_operand" "g")
370 (match_operand:SI 2 "general_operand" "g")])
373 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
374 because the expressions to be matched all contain two operands.
376 When this pattern does match, the two operands of the commutative
377 operator are recorded as operands 1 and 2 of the insn. (This is done
378 by the two instances of @code{match_operand}.) Operand 3 of the insn
379 will be the entire commutative expression: use @code{GET_CODE
380 (operands[3])} to see which commutative operator was used.
382 The machine mode @var{m} of @code{match_operator} works like that of
383 @code{match_operand}: it is passed as the second argument to the
384 predicate function, and that function is solely responsible for
385 deciding whether the expression to be matched ``has'' that mode.
387 When constructing an insn, argument 3 of the gen-function will specify
388 the operation (i.e.@: the expression code) for the expression to be
389 made. It should be an RTL expression, whose expression code is copied
390 into a new expression whose operands are arguments 1 and 2 of the
391 gen-function. The subexpressions of argument 3 are not used;
392 only its expression code matters.
394 When @code{match_operator} is used in a pattern for matching an insn,
395 it usually best if the operand number of the @code{match_operator}
396 is higher than that of the actual operands of the insn. This improves
397 register allocation because the register allocator often looks at
398 operands 1 and 2 of insns to see if it can do register tying.
400 There is no way to specify constraints in @code{match_operator}. The
401 operand of the insn which corresponds to the @code{match_operator}
402 never has any constraints because it is never reloaded as a whole.
403 However, if parts of its @var{operands} are matched by
404 @code{match_operand} patterns, those parts may have constraints of
408 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
409 Like @code{match_dup}, except that it applies to operators instead of
410 operands. When constructing an insn, operand number @var{n} will be
411 substituted at this point. But in matching, @code{match_op_dup} behaves
412 differently. It assumes that operand number @var{n} has already been
413 determined by a @code{match_operator} appearing earlier in the
414 recognition template, and it matches only an identical-looking
417 @findex match_parallel
418 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
419 This pattern is a placeholder for an insn that consists of a
420 @code{parallel} expression with a variable number of elements. This
421 expression should only appear at the top level of an insn pattern.
423 When constructing an insn, operand number @var{n} will be substituted at
424 this point. When matching an insn, it matches if the body of the insn
425 is a @code{parallel} expression with at least as many elements as the
426 vector of @var{subpat} expressions in the @code{match_parallel}, if each
427 @var{subpat} matches the corresponding element of the @code{parallel},
428 @emph{and} the function @var{predicate} returns nonzero on the
429 @code{parallel} that is the body of the insn. It is the responsibility
430 of the predicate to validate elements of the @code{parallel} beyond
431 those listed in the @code{match_parallel}.
433 A typical use of @code{match_parallel} is to match load and store
434 multiple expressions, which can contain a variable number of elements
435 in a @code{parallel}. For example,
439 [(match_parallel 0 "load_multiple_operation"
440 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
441 (match_operand:SI 2 "memory_operand" "m"))
443 (clobber (reg:SI 179))])]
448 This example comes from @file{a29k.md}. The function
449 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
450 that subsequent elements in the @code{parallel} are the same as the
451 @code{set} in the pattern, except that they are referencing subsequent
452 registers and memory locations.
454 An insn that matches this pattern might look like:
458 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
460 (clobber (reg:SI 179))
462 (mem:SI (plus:SI (reg:SI 100)
465 (mem:SI (plus:SI (reg:SI 100)
469 @findex match_par_dup
470 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
471 Like @code{match_op_dup}, but for @code{match_parallel} instead of
472 @code{match_operator}.
476 @node Output Template
477 @section Output Templates and Operand Substitution
478 @cindex output templates
479 @cindex operand substitution
481 @cindex @samp{%} in template
483 The @dfn{output template} is a string which specifies how to output the
484 assembler code for an instruction pattern. Most of the template is a
485 fixed string which is output literally. The character @samp{%} is used
486 to specify where to substitute an operand; it can also be used to
487 identify places where different variants of the assembler require
490 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
491 operand @var{n} at that point in the string.
493 @samp{%} followed by a letter and a digit says to output an operand in an
494 alternate fashion. Four letters have standard, built-in meanings described
495 below. The machine description macro @code{PRINT_OPERAND} can define
496 additional letters with nonstandard meanings.
498 @samp{%c@var{digit}} can be used to substitute an operand that is a
499 constant value without the syntax that normally indicates an immediate
502 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
503 the constant is negated before printing.
505 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
506 memory reference, with the actual operand treated as the address. This may
507 be useful when outputting a ``load address'' instruction, because often the
508 assembler syntax for such an instruction requires you to write the operand
509 as if it were a memory reference.
511 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
514 @samp{%=} outputs a number which is unique to each instruction in the
515 entire compilation. This is useful for making local labels to be
516 referred to more than once in a single template that generates multiple
517 assembler instructions.
519 @samp{%} followed by a punctuation character specifies a substitution that
520 does not use an operand. Only one case is standard: @samp{%%} outputs a
521 @samp{%} into the assembler code. Other nonstandard cases can be
522 defined in the @code{PRINT_OPERAND} macro. You must also define
523 which punctuation characters are valid with the
524 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
528 The template may generate multiple assembler instructions. Write the text
529 for the instructions, with @samp{\;} between them.
531 @cindex matching operands
532 When the RTL contains two operands which are required by constraint to match
533 each other, the output template must refer only to the lower-numbered operand.
534 Matching operands are not always identical, and the rest of the compiler
535 arranges to put the proper RTL expression for printing into the lower-numbered
538 One use of nonstandard letters or punctuation following @samp{%} is to
539 distinguish between different assembler languages for the same machine; for
540 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
541 requires periods in most opcode names, while MIT syntax does not. For
542 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
543 syntax. The same file of patterns is used for both kinds of output syntax,
544 but the character sequence @samp{%.} is used in each place where Motorola
545 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
546 defines the sequence to output a period; the macro for MIT syntax defines
549 @cindex @code{#} in template
550 As a special case, a template consisting of the single character @code{#}
551 instructs the compiler to first split the insn, and then output the
552 resulting instructions separately. This helps eliminate redundancy in the
553 output templates. If you have a @code{define_insn} that needs to emit
554 multiple assembler instructions, and there is an matching @code{define_split}
555 already defined, then you can simply use @code{#} as the output template
556 instead of writing an output template that emits the multiple assembler
559 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
560 of the form @samp{@{option0|option1|option2@}} in the templates. These
561 describe multiple variants of assembler language syntax.
562 @xref{Instruction Output}.
564 @node Output Statement
565 @section C Statements for Assembler Output
566 @cindex output statements
567 @cindex C statements for assembler output
568 @cindex generating assembler output
570 Often a single fixed template string cannot produce correct and efficient
571 assembler code for all the cases that are recognized by a single
572 instruction pattern. For example, the opcodes may depend on the kinds of
573 operands; or some unfortunate combinations of operands may require extra
574 machine instructions.
576 If the output control string starts with a @samp{@@}, then it is actually
577 a series of templates, each on a separate line. (Blank lines and
578 leading spaces and tabs are ignored.) The templates correspond to the
579 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
580 if a target machine has a two-address add instruction @samp{addr} to add
581 into a register and another @samp{addm} to add a register to memory, you
582 might write this pattern:
585 (define_insn "addsi3"
586 [(set (match_operand:SI 0 "general_operand" "=r,m")
587 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
588 (match_operand:SI 2 "general_operand" "g,r")))]
595 @cindex @code{*} in template
596 @cindex asterisk in template
597 If the output control string starts with a @samp{*}, then it is not an
598 output template but rather a piece of C program that should compute a
599 template. It should execute a @code{return} statement to return the
600 template-string you want. Most such templates use C string literals, which
601 require doublequote characters to delimit them. To include these
602 doublequote characters in the string, prefix each one with @samp{\}.
604 If the output control string is written as a brace block instead of a
605 double-quoted string, it is automatically assumed to be C code. In that
606 case, it is not necessary to put in a leading asterisk, or to escape the
607 doublequotes surrounding C string literals.
609 The operands may be found in the array @code{operands}, whose C data type
612 It is very common to select different ways of generating assembler code
613 based on whether an immediate operand is within a certain range. Be
614 careful when doing this, because the result of @code{INTVAL} is an
615 integer on the host machine. If the host machine has more bits in an
616 @code{int} than the target machine has in the mode in which the constant
617 will be used, then some of the bits you get from @code{INTVAL} will be
618 superfluous. For proper results, you must carefully disregard the
619 values of those bits.
621 @findex output_asm_insn
622 It is possible to output an assembler instruction and then go on to output
623 or compute more of them, using the subroutine @code{output_asm_insn}. This
624 receives two arguments: a template-string and a vector of operands. The
625 vector may be @code{operands}, or it may be another array of @code{rtx}
626 that you declare locally and initialize yourself.
628 @findex which_alternative
629 When an insn pattern has multiple alternatives in its constraints, often
630 the appearance of the assembler code is determined mostly by which alternative
631 was matched. When this is so, the C code can test the variable
632 @code{which_alternative}, which is the ordinal number of the alternative
633 that was actually satisfied (0 for the first, 1 for the second alternative,
636 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
637 for registers and @samp{clrmem} for memory locations. Here is how
638 a pattern could use @code{which_alternative} to choose between them:
642 [(set (match_operand:SI 0 "general_operand" "=r,m")
646 return (which_alternative == 0
647 ? "clrreg %0" : "clrmem %0");
651 The example above, where the assembler code to generate was
652 @emph{solely} determined by the alternative, could also have been specified
653 as follows, having the output control string start with a @samp{@@}:
658 [(set (match_operand:SI 0 "general_operand" "=r,m")
670 @cindex operand predicates
671 @cindex operator predicates
673 A predicate determines whether a @code{match_operand} or
674 @code{match_operator} expression matches, and therefore whether the
675 surrounding instruction pattern will be used for that combination of
676 operands. GCC has a number of machine-independent predicates, and you
677 can define machine-specific predicates as needed. By convention,
678 predicates used with @code{match_operand} have names that end in
679 @samp{_operand}, and those used with @code{match_operator} have names
680 that end in @samp{_operator}.
682 All predicates are Boolean functions (in the mathematical sense) of
683 two arguments: the RTL expression that is being considered at that
684 position in the instruction pattern, and the machine mode that the
685 @code{match_operand} or @code{match_operator} specifies. In this
686 section, the first argument is called @var{op} and the second argument
687 @var{mode}. Predicates can be called from C as ordinary two-argument
688 functions; this can be useful in output templates or other
689 machine-specific code.
691 Operand predicates can allow operands that are not actually acceptable
692 to the hardware, as long as the constraints give reload the ability to
693 fix them up (@pxref{Constraints}). However, GCC will usually generate
694 better code if the predicates specify the requirements of the machine
695 instructions as closely as possible. Reload cannot fix up operands
696 that must be constants (``immediate operands''); you must use a
697 predicate that allows only constants, or else enforce the requirement
698 in the extra condition.
700 @cindex predicates and machine modes
701 @cindex normal predicates
702 @cindex special predicates
703 Most predicates handle their @var{mode} argument in a uniform manner.
704 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
705 any mode. If @var{mode} is anything else, then @var{op} must have the
706 same mode, unless @var{op} is a @code{CONST_INT} or integer
707 @code{CONST_DOUBLE}. These RTL expressions always have
708 @code{VOIDmode}, so it would be counterproductive to check that their
709 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
710 integer @code{CONST_DOUBLE} check that the value stored in the
711 constant will fit in the requested mode.
713 Predicates with this behavior are called @dfn{normal}.
714 @command{genrecog} can optimize the instruction recognizer based on
715 knowledge of how normal predicates treat modes. It can also diagnose
716 certain kinds of common errors in the use of normal predicates; for
717 instance, it is almost always an error to use a normal predicate
718 without specifying a mode.
720 Predicates that do something different with their @var{mode} argument
721 are called @dfn{special}. The generic predicates
722 @code{address_operand} and @code{pmode_register_operand} are special
723 predicates. @command{genrecog} does not do any optimizations or
724 diagnosis when special predicates are used.
727 * Machine-Independent Predicates:: Predicates available to all back ends.
728 * Defining Predicates:: How to write machine-specific predicate
732 @node Machine-Independent Predicates
733 @subsection Machine-Independent Predicates
734 @cindex machine-independent predicates
735 @cindex generic predicates
737 These are the generic predicates available to all back ends. They are
738 defined in @file{recog.c}. The first category of predicates allow
739 only constant, or @dfn{immediate}, operands.
741 @defun immediate_operand
742 This predicate allows any sort of constant that fits in @var{mode}.
743 It is an appropriate choice for instructions that take operands that
747 @defun const_int_operand
748 This predicate allows any @code{CONST_INT} expression that fits in
749 @var{mode}. It is an appropriate choice for an immediate operand that
750 does not allow a symbol or label.
753 @defun const_double_operand
754 This predicate accepts any @code{CONST_DOUBLE} expression that has
755 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
756 accept @code{CONST_INT}. It is intended for immediate floating point
761 The second category of predicates allow only some kind of machine
764 @defun register_operand
765 This predicate allows any @code{REG} or @code{SUBREG} expression that
766 is valid for @var{mode}. It is often suitable for arithmetic
767 instruction operands on a RISC machine.
770 @defun pmode_register_operand
771 This is a slight variant on @code{register_operand} which works around
772 a limitation in the machine-description reader.
775 (match_operand @var{n} "pmode_register_operand" @var{constraint})
782 (match_operand:P @var{n} "register_operand" @var{constraint})
786 would mean, if the machine-description reader accepted @samp{:P}
787 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
788 alias for some other mode, and might vary with machine-specific
789 options. @xref{Misc}.
792 @defun scratch_operand
793 This predicate allows hard registers and @code{SCRATCH} expressions,
794 but not pseudo-registers. It is used internally by @code{match_scratch};
795 it should not be used directly.
799 The third category of predicates allow only some kind of memory reference.
801 @defun memory_operand
802 This predicate allows any valid reference to a quantity of mode
803 @var{mode} in memory, as determined by the weak form of
804 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
807 @defun address_operand
808 This predicate is a little unusual; it allows any operand that is a
809 valid expression for the @emph{address} of a quantity of mode
810 @var{mode}, again determined by the weak form of
811 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
812 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
813 @code{memory_operand}, then @var{exp} is acceptable to
814 @code{address_operand}. Note that @var{exp} does not necessarily have
818 @defun indirect_operand
819 This is a stricter form of @code{memory_operand} which allows only
820 memory references with a @code{general_operand} as the address
821 expression. New uses of this predicate are discouraged, because
822 @code{general_operand} is very permissive, so it's hard to tell what
823 an @code{indirect_operand} does or does not allow. If a target has
824 different requirements for memory operands for different instructions,
825 it is better to define target-specific predicates which enforce the
826 hardware's requirements explicitly.
830 This predicate allows a memory reference suitable for pushing a value
831 onto the stack. This will be a @code{MEM} which refers to
832 @code{stack_pointer_rtx}, with a side-effect in its address expression
833 (@pxref{Incdec}); which one is determined by the
834 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
838 This predicate allows a memory reference suitable for popping a value
839 off the stack. Again, this will be a @code{MEM} referring to
840 @code{stack_pointer_rtx}, with a side-effect in its address
841 expression. However, this time @code{STACK_POP_CODE} is expected.
845 The fourth category of predicates allow some combination of the above
848 @defun nonmemory_operand
849 This predicate allows any immediate or register operand valid for @var{mode}.
852 @defun nonimmediate_operand
853 This predicate allows any register or memory operand valid for @var{mode}.
856 @defun general_operand
857 This predicate allows any immediate, register, or memory operand
858 valid for @var{mode}.
862 Finally, there is one generic operator predicate.
864 @defun comparison_operator
865 This predicate matches any expression which performs an arithmetic
866 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
870 @node Defining Predicates
871 @subsection Defining Machine-Specific Predicates
872 @cindex defining predicates
873 @findex define_predicate
874 @findex define_special_predicate
876 Many machines have requirements for their operands that cannot be
877 expressed precisely using the generic predicates. You can define
878 additional predicates using @code{define_predicate} and
879 @code{define_special_predicate} expressions. These expressions have
884 The name of the predicate, as it will be referred to in
885 @code{match_operand} or @code{match_operator} expressions.
888 An RTL expression which evaluates to true if the predicate allows the
889 operand @var{op}, false if it does not. This expression can only use
890 the following RTL codes:
894 When written inside a predicate expression, a @code{MATCH_OPERAND}
895 expression evaluates to true if the predicate it names would allow
896 @var{op}. The operand number and constraint are ignored. Due to
897 limitations in @command{genrecog}, you can only refer to generic
898 predicates and predicates that have already been defined.
901 This expression evaluates to true if @var{op} or a specified
902 subexpression of @var{op} has one of a given list of RTX codes.
904 The first operand of this expression is a string constant containing a
905 comma-separated list of RTX code names (in lower case). These are the
906 codes for which the @code{MATCH_CODE} will be true.
908 The second operand is a string constant which indicates what
909 subexpression of @var{op} to examine. If it is absent or the empty
910 string, @var{op} itself is examined. Otherwise, the string constant
911 must be a sequence of digits and/or lowercase letters. Each character
912 indicates a subexpression to extract from the current expression; for
913 the first character this is @var{op}, for the second and subsequent
914 characters it is the result of the previous character. A digit
915 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
916 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
917 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
918 @code{MATCH_CODE} then examines the RTX code of the subexpression
919 extracted by the complete string. It is not possible to extract
920 components of an @code{rtvec} that is not at position 0 within its RTX
924 This expression has one operand, a string constant containing a C
925 expression. The predicate's arguments, @var{op} and @var{mode}, are
926 available with those names in the C expression. The @code{MATCH_TEST}
927 evaluates to true if the C expression evaluates to a nonzero value.
928 @code{MATCH_TEST} expressions must not have side effects.
934 The basic @samp{MATCH_} expressions can be combined using these
935 logical operators, which have the semantics of the C operators
936 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
937 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
938 arbitrary number of arguments; this has exactly the same effect as
939 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
943 An optional block of C code, which should execute
944 @samp{@w{return true}} if the predicate is found to match and
945 @samp{@w{return false}} if it does not. It must not have any side
946 effects. The predicate arguments, @var{op} and @var{mode}, are
947 available with those names.
949 If a code block is present in a predicate definition, then the RTL
950 expression must evaluate to true @emph{and} the code block must
951 execute @samp{@w{return true}} for the predicate to allow the operand.
952 The RTL expression is evaluated first; do not re-check anything in the
953 code block that was checked in the RTL expression.
956 The program @command{genrecog} scans @code{define_predicate} and
957 @code{define_special_predicate} expressions to determine which RTX
958 codes are possibly allowed. You should always make this explicit in
959 the RTL predicate expression, using @code{MATCH_OPERAND} and
962 Here is an example of a simple predicate definition, from the IA64
967 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
968 (define_predicate "small_addr_symbolic_operand"
969 (and (match_code "symbol_ref")
970 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
975 And here is another, showing the use of the C block.
979 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
980 (define_predicate "gr_register_operand"
981 (match_operand 0 "register_operand")
984 if (GET_CODE (op) == SUBREG)
985 op = SUBREG_REG (op);
988 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
993 Predicates written with @code{define_predicate} automatically include
994 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
995 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
996 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
997 integer @code{CONST_DOUBLE}, nor do they test that the value of either
998 kind of constant fits in the requested mode. This is because
999 target-specific predicates that take constants usually have to do more
1000 stringent value checks anyway. If you need the exact same treatment
1001 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1002 provide, use a @code{MATCH_OPERAND} subexpression to call
1003 @code{const_int_operand}, @code{const_double_operand}, or
1004 @code{immediate_operand}.
1006 Predicates written with @code{define_special_predicate} do not get any
1007 automatic mode checks, and are treated as having special mode handling
1008 by @command{genrecog}.
1010 The program @command{genpreds} is responsible for generating code to
1011 test predicates. It also writes a header file containing function
1012 declarations for all machine-specific predicates. It is not necessary
1013 to declare these predicates in @file{@var{cpu}-protos.h}.
1016 @c Most of this node appears by itself (in a different place) even
1017 @c when the INTERNALS flag is clear. Passages that require the internals
1018 @c manual's context are conditionalized to appear only in the internals manual.
1021 @section Operand Constraints
1022 @cindex operand constraints
1025 Each @code{match_operand} in an instruction pattern can specify
1026 constraints for the operands allowed. The constraints allow you to
1027 fine-tune matching within the set of operands allowed by the
1033 @section Constraints for @code{asm} Operands
1034 @cindex operand constraints, @code{asm}
1035 @cindex constraints, @code{asm}
1036 @cindex @code{asm} constraints
1038 Here are specific details on what constraint letters you can use with
1039 @code{asm} operands.
1041 Constraints can say whether
1042 an operand may be in a register, and which kinds of register; whether the
1043 operand can be a memory reference, and which kinds of address; whether the
1044 operand may be an immediate constant, and which possible values it may
1045 have. Constraints can also require two operands to match.
1049 * Simple Constraints:: Basic use of constraints.
1050 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1051 * Class Preferences:: Constraints guide which hard register to put things in.
1052 * Modifiers:: More precise control over effects of constraints.
1053 * Machine Constraints:: Existing constraints for some particular machines.
1054 * Define Constraints:: How to define machine-specific constraints.
1055 * C Constraint Interface:: How to test constraints from C code.
1061 * Simple Constraints:: Basic use of constraints.
1062 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1063 * Modifiers:: More precise control over effects of constraints.
1064 * Machine Constraints:: Special constraints for some particular machines.
1068 @node Simple Constraints
1069 @subsection Simple Constraints
1070 @cindex simple constraints
1072 The simplest kind of constraint is a string full of letters, each of
1073 which describes one kind of operand that is permitted. Here are
1074 the letters that are allowed:
1078 Whitespace characters are ignored and can be inserted at any position
1079 except the first. This enables each alternative for different operands to
1080 be visually aligned in the machine description even if they have different
1081 number of constraints and modifiers.
1083 @cindex @samp{m} in constraint
1084 @cindex memory references in constraints
1086 A memory operand is allowed, with any kind of address that the machine
1087 supports in general.
1089 @cindex offsettable address
1090 @cindex @samp{o} in constraint
1092 A memory operand is allowed, but only if the address is
1093 @dfn{offsettable}. This means that adding a small integer (actually,
1094 the width in bytes of the operand, as determined by its machine mode)
1095 may be added to the address and the result is also a valid memory
1098 @cindex autoincrement/decrement addressing
1099 For example, an address which is constant is offsettable; so is an
1100 address that is the sum of a register and a constant (as long as a
1101 slightly larger constant is also within the range of address-offsets
1102 supported by the machine); but an autoincrement or autodecrement
1103 address is not offsettable. More complicated indirect/indexed
1104 addresses may or may not be offsettable depending on the other
1105 addressing modes that the machine supports.
1107 Note that in an output operand which can be matched by another
1108 operand, the constraint letter @samp{o} is valid only when accompanied
1109 by both @samp{<} (if the target machine has predecrement addressing)
1110 and @samp{>} (if the target machine has preincrement addressing).
1112 @cindex @samp{V} in constraint
1114 A memory operand that is not offsettable. In other words, anything that
1115 would fit the @samp{m} constraint but not the @samp{o} constraint.
1117 @cindex @samp{<} in constraint
1119 A memory operand with autodecrement addressing (either predecrement or
1120 postdecrement) is allowed.
1122 @cindex @samp{>} in constraint
1124 A memory operand with autoincrement addressing (either preincrement or
1125 postincrement) is allowed.
1127 @cindex @samp{r} in constraint
1128 @cindex registers in constraints
1130 A register operand is allowed provided that it is in a general
1133 @cindex constants in constraints
1134 @cindex @samp{i} in constraint
1136 An immediate integer operand (one with constant value) is allowed.
1137 This includes symbolic constants whose values will be known only at
1138 assembly time or later.
1140 @cindex @samp{n} in constraint
1142 An immediate integer operand with a known numeric value is allowed.
1143 Many systems cannot support assembly-time constants for operands less
1144 than a word wide. Constraints for these operands should use @samp{n}
1145 rather than @samp{i}.
1147 @cindex @samp{I} in constraint
1148 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1149 Other letters in the range @samp{I} through @samp{P} may be defined in
1150 a machine-dependent fashion to permit immediate integer operands with
1151 explicit integer values in specified ranges. For example, on the
1152 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1153 This is the range permitted as a shift count in the shift
1156 @cindex @samp{E} in constraint
1158 An immediate floating operand (expression code @code{const_double}) is
1159 allowed, but only if the target floating point format is the same as
1160 that of the host machine (on which the compiler is running).
1162 @cindex @samp{F} in constraint
1164 An immediate floating operand (expression code @code{const_double} or
1165 @code{const_vector}) is allowed.
1167 @cindex @samp{G} in constraint
1168 @cindex @samp{H} in constraint
1169 @item @samp{G}, @samp{H}
1170 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1171 permit immediate floating operands in particular ranges of values.
1173 @cindex @samp{s} in constraint
1175 An immediate integer operand whose value is not an explicit integer is
1178 This might appear strange; if an insn allows a constant operand with a
1179 value not known at compile time, it certainly must allow any known
1180 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1181 better code to be generated.
1183 For example, on the 68000 in a fullword instruction it is possible to
1184 use an immediate operand; but if the immediate value is between @minus{}128
1185 and 127, better code results from loading the value into a register and
1186 using the register. This is because the load into the register can be
1187 done with a @samp{moveq} instruction. We arrange for this to happen
1188 by defining the letter @samp{K} to mean ``any integer outside the
1189 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1192 @cindex @samp{g} in constraint
1194 Any register, memory or immediate integer operand is allowed, except for
1195 registers that are not general registers.
1197 @cindex @samp{X} in constraint
1200 Any operand whatsoever is allowed, even if it does not satisfy
1201 @code{general_operand}. This is normally used in the constraint of
1202 a @code{match_scratch} when certain alternatives will not actually
1203 require a scratch register.
1206 Any operand whatsoever is allowed.
1209 @cindex @samp{0} in constraint
1210 @cindex digits in constraint
1211 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1212 An operand that matches the specified operand number is allowed. If a
1213 digit is used together with letters within the same alternative, the
1214 digit should come last.
1216 This number is allowed to be more than a single digit. If multiple
1217 digits are encountered consecutively, they are interpreted as a single
1218 decimal integer. There is scant chance for ambiguity, since to-date
1219 it has never been desirable that @samp{10} be interpreted as matching
1220 either operand 1 @emph{or} operand 0. Should this be desired, one
1221 can use multiple alternatives instead.
1223 @cindex matching constraint
1224 @cindex constraint, matching
1225 This is called a @dfn{matching constraint} and what it really means is
1226 that the assembler has only a single operand that fills two roles
1228 considered separate in the RTL insn. For example, an add insn has two
1229 input operands and one output operand in the RTL, but on most CISC
1232 which @code{asm} distinguishes. For example, an add instruction uses
1233 two input operands and an output operand, but on most CISC
1235 machines an add instruction really has only two operands, one of them an
1236 input-output operand:
1242 Matching constraints are used in these circumstances.
1243 More precisely, the two operands that match must include one input-only
1244 operand and one output-only operand. Moreover, the digit must be a
1245 smaller number than the number of the operand that uses it in the
1249 For operands to match in a particular case usually means that they
1250 are identical-looking RTL expressions. But in a few special cases
1251 specific kinds of dissimilarity are allowed. For example, @code{*x}
1252 as an input operand will match @code{*x++} as an output operand.
1253 For proper results in such cases, the output template should always
1254 use the output-operand's number when printing the operand.
1257 @cindex load address instruction
1258 @cindex push address instruction
1259 @cindex address constraints
1260 @cindex @samp{p} in constraint
1262 An operand that is a valid memory address is allowed. This is
1263 for ``load address'' and ``push address'' instructions.
1265 @findex address_operand
1266 @samp{p} in the constraint must be accompanied by @code{address_operand}
1267 as the predicate in the @code{match_operand}. This predicate interprets
1268 the mode specified in the @code{match_operand} as the mode of the memory
1269 reference for which the address would be valid.
1271 @cindex other register constraints
1272 @cindex extensible constraints
1273 @item @var{other-letters}
1274 Other letters can be defined in machine-dependent fashion to stand for
1275 particular classes of registers or other arbitrary operand types.
1276 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1277 for data, address and floating point registers.
1281 In order to have valid assembler code, each operand must satisfy
1282 its constraint. But a failure to do so does not prevent the pattern
1283 from applying to an insn. Instead, it directs the compiler to modify
1284 the code so that the constraint will be satisfied. Usually this is
1285 done by copying an operand into a register.
1287 Contrast, therefore, the two instruction patterns that follow:
1291 [(set (match_operand:SI 0 "general_operand" "=r")
1292 (plus:SI (match_dup 0)
1293 (match_operand:SI 1 "general_operand" "r")))]
1299 which has two operands, one of which must appear in two places, and
1303 [(set (match_operand:SI 0 "general_operand" "=r")
1304 (plus:SI (match_operand:SI 1 "general_operand" "0")
1305 (match_operand:SI 2 "general_operand" "r")))]
1311 which has three operands, two of which are required by a constraint to be
1312 identical. If we are considering an insn of the form
1315 (insn @var{n} @var{prev} @var{next}
1317 (plus:SI (reg:SI 6) (reg:SI 109)))
1322 the first pattern would not apply at all, because this insn does not
1323 contain two identical subexpressions in the right place. The pattern would
1324 say, ``That does not look like an add instruction; try other patterns''.
1325 The second pattern would say, ``Yes, that's an add instruction, but there
1326 is something wrong with it''. It would direct the reload pass of the
1327 compiler to generate additional insns to make the constraint true. The
1328 results might look like this:
1331 (insn @var{n2} @var{prev} @var{n}
1332 (set (reg:SI 3) (reg:SI 6))
1335 (insn @var{n} @var{n2} @var{next}
1337 (plus:SI (reg:SI 3) (reg:SI 109)))
1341 It is up to you to make sure that each operand, in each pattern, has
1342 constraints that can handle any RTL expression that could be present for
1343 that operand. (When multiple alternatives are in use, each pattern must,
1344 for each possible combination of operand expressions, have at least one
1345 alternative which can handle that combination of operands.) The
1346 constraints don't need to @emph{allow} any possible operand---when this is
1347 the case, they do not constrain---but they must at least point the way to
1348 reloading any possible operand so that it will fit.
1352 If the constraint accepts whatever operands the predicate permits,
1353 there is no problem: reloading is never necessary for this operand.
1355 For example, an operand whose constraints permit everything except
1356 registers is safe provided its predicate rejects registers.
1358 An operand whose predicate accepts only constant values is safe
1359 provided its constraints include the letter @samp{i}. If any possible
1360 constant value is accepted, then nothing less than @samp{i} will do;
1361 if the predicate is more selective, then the constraints may also be
1365 Any operand expression can be reloaded by copying it into a register.
1366 So if an operand's constraints allow some kind of register, it is
1367 certain to be safe. It need not permit all classes of registers; the
1368 compiler knows how to copy a register into another register of the
1369 proper class in order to make an instruction valid.
1371 @cindex nonoffsettable memory reference
1372 @cindex memory reference, nonoffsettable
1374 A nonoffsettable memory reference can be reloaded by copying the
1375 address into a register. So if the constraint uses the letter
1376 @samp{o}, all memory references are taken care of.
1379 A constant operand can be reloaded by allocating space in memory to
1380 hold it as preinitialized data. Then the memory reference can be used
1381 in place of the constant. So if the constraint uses the letters
1382 @samp{o} or @samp{m}, constant operands are not a problem.
1385 If the constraint permits a constant and a pseudo register used in an insn
1386 was not allocated to a hard register and is equivalent to a constant,
1387 the register will be replaced with the constant. If the predicate does
1388 not permit a constant and the insn is re-recognized for some reason, the
1389 compiler will crash. Thus the predicate must always recognize any
1390 objects allowed by the constraint.
1393 If the operand's predicate can recognize registers, but the constraint does
1394 not permit them, it can make the compiler crash. When this operand happens
1395 to be a register, the reload pass will be stymied, because it does not know
1396 how to copy a register temporarily into memory.
1398 If the predicate accepts a unary operator, the constraint applies to the
1399 operand. For example, the MIPS processor at ISA level 3 supports an
1400 instruction which adds two registers in @code{SImode} to produce a
1401 @code{DImode} result, but only if the registers are correctly sign
1402 extended. This predicate for the input operands accepts a
1403 @code{sign_extend} of an @code{SImode} register. Write the constraint
1404 to indicate the type of register that is required for the operand of the
1408 @node Multi-Alternative
1409 @subsection Multiple Alternative Constraints
1410 @cindex multiple alternative constraints
1412 Sometimes a single instruction has multiple alternative sets of possible
1413 operands. For example, on the 68000, a logical-or instruction can combine
1414 register or an immediate value into memory, or it can combine any kind of
1415 operand into a register; but it cannot combine one memory location into
1418 These constraints are represented as multiple alternatives. An alternative
1419 can be described by a series of letters for each operand. The overall
1420 constraint for an operand is made from the letters for this operand
1421 from the first alternative, a comma, the letters for this operand from
1422 the second alternative, a comma, and so on until the last alternative.
1424 Here is how it is done for fullword logical-or on the 68000:
1427 (define_insn "iorsi3"
1428 [(set (match_operand:SI 0 "general_operand" "=m,d")
1429 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1430 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1434 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1435 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1436 2. The second alternative has @samp{d} (data register) for operand 0,
1437 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1438 @samp{%} in the constraints apply to all the alternatives; their
1439 meaning is explained in the next section (@pxref{Class Preferences}).
1442 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1443 If all the operands fit any one alternative, the instruction is valid.
1444 Otherwise, for each alternative, the compiler counts how many instructions
1445 must be added to copy the operands so that that alternative applies.
1446 The alternative requiring the least copying is chosen. If two alternatives
1447 need the same amount of copying, the one that comes first is chosen.
1448 These choices can be altered with the @samp{?} and @samp{!} characters:
1451 @cindex @samp{?} in constraint
1452 @cindex question mark
1454 Disparage slightly the alternative that the @samp{?} appears in,
1455 as a choice when no alternative applies exactly. The compiler regards
1456 this alternative as one unit more costly for each @samp{?} that appears
1459 @cindex @samp{!} in constraint
1460 @cindex exclamation point
1462 Disparage severely the alternative that the @samp{!} appears in.
1463 This alternative can still be used if it fits without reloading,
1464 but if reloading is needed, some other alternative will be used.
1468 When an insn pattern has multiple alternatives in its constraints, often
1469 the appearance of the assembler code is determined mostly by which
1470 alternative was matched. When this is so, the C code for writing the
1471 assembler code can use the variable @code{which_alternative}, which is
1472 the ordinal number of the alternative that was actually satisfied (0 for
1473 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1477 @node Class Preferences
1478 @subsection Register Class Preferences
1479 @cindex class preference constraints
1480 @cindex register class preference constraints
1482 @cindex voting between constraint alternatives
1483 The operand constraints have another function: they enable the compiler
1484 to decide which kind of hardware register a pseudo register is best
1485 allocated to. The compiler examines the constraints that apply to the
1486 insns that use the pseudo register, looking for the machine-dependent
1487 letters such as @samp{d} and @samp{a} that specify classes of registers.
1488 The pseudo register is put in whichever class gets the most ``votes''.
1489 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1490 favor of a general register. The machine description says which registers
1491 are considered general.
1493 Of course, on some machines all registers are equivalent, and no register
1494 classes are defined. Then none of this complexity is relevant.
1498 @subsection Constraint Modifier Characters
1499 @cindex modifiers in constraints
1500 @cindex constraint modifier characters
1502 @c prevent bad page break with this line
1503 Here are constraint modifier characters.
1506 @cindex @samp{=} in constraint
1508 Means that this operand is write-only for this instruction: the previous
1509 value is discarded and replaced by output data.
1511 @cindex @samp{+} in constraint
1513 Means that this operand is both read and written by the instruction.
1515 When the compiler fixes up the operands to satisfy the constraints,
1516 it needs to know which operands are inputs to the instruction and
1517 which are outputs from it. @samp{=} identifies an output; @samp{+}
1518 identifies an operand that is both input and output; all other operands
1519 are assumed to be input only.
1521 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1522 first character of the constraint string.
1524 @cindex @samp{&} in constraint
1525 @cindex earlyclobber operand
1527 Means (in a particular alternative) that this operand is an
1528 @dfn{earlyclobber} operand, which is modified before the instruction is
1529 finished using the input operands. Therefore, this operand may not lie
1530 in a register that is used as an input operand or as part of any memory
1533 @samp{&} applies only to the alternative in which it is written. In
1534 constraints with multiple alternatives, sometimes one alternative
1535 requires @samp{&} while others do not. See, for example, the
1536 @samp{movdf} insn of the 68000.
1538 An input operand can be tied to an earlyclobber operand if its only
1539 use as an input occurs before the early result is written. Adding
1540 alternatives of this form often allows GCC to produce better code
1541 when only some of the inputs can be affected by the earlyclobber.
1542 See, for example, the @samp{mulsi3} insn of the ARM@.
1544 @samp{&} does not obviate the need to write @samp{=}.
1546 @cindex @samp{%} in constraint
1548 Declares the instruction to be commutative for this operand and the
1549 following operand. This means that the compiler may interchange the
1550 two operands if that is the cheapest way to make all operands fit the
1553 This is often used in patterns for addition instructions
1554 that really have only two operands: the result must go in one of the
1555 arguments. Here for example, is how the 68000 halfword-add
1556 instruction is defined:
1559 (define_insn "addhi3"
1560 [(set (match_operand:HI 0 "general_operand" "=m,r")
1561 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1562 (match_operand:HI 2 "general_operand" "di,g")))]
1566 GCC can only handle one commutative pair in an asm; if you use more,
1567 the compiler may fail. Note that you need not use the modifier if
1568 the two alternatives are strictly identical; this would only waste
1569 time in the reload pass. The modifier is not operational after
1570 register allocation, so the result of @code{define_peephole2}
1571 and @code{define_split}s performed after reload cannot rely on
1572 @samp{%} to make the intended insn match.
1574 @cindex @samp{#} in constraint
1576 Says that all following characters, up to the next comma, are to be
1577 ignored as a constraint. They are significant only for choosing
1578 register preferences.
1580 @cindex @samp{*} in constraint
1582 Says that the following character should be ignored when choosing
1583 register preferences. @samp{*} has no effect on the meaning of the
1584 constraint as a constraint, and no effect on reloading.
1587 Here is an example: the 68000 has an instruction to sign-extend a
1588 halfword in a data register, and can also sign-extend a value by
1589 copying it into an address register. While either kind of register is
1590 acceptable, the constraints on an address-register destination are
1591 less strict, so it is best if register allocation makes an address
1592 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1593 constraint letter (for data register) is ignored when computing
1594 register preferences.
1597 (define_insn "extendhisi2"
1598 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1600 (match_operand:HI 1 "general_operand" "0,g")))]
1606 @node Machine Constraints
1607 @subsection Constraints for Particular Machines
1608 @cindex machine specific constraints
1609 @cindex constraints, machine specific
1611 Whenever possible, you should use the general-purpose constraint letters
1612 in @code{asm} arguments, since they will convey meaning more readily to
1613 people reading your code. Failing that, use the constraint letters
1614 that usually have very similar meanings across architectures. The most
1615 commonly used constraints are @samp{m} and @samp{r} (for memory and
1616 general-purpose registers respectively; @pxref{Simple Constraints}), and
1617 @samp{I}, usually the letter indicating the most common
1618 immediate-constant format.
1620 Each architecture defines additional constraints. These constraints
1621 are used by the compiler itself for instruction generation, as well as
1622 for @code{asm} statements; therefore, some of the constraints are not
1623 particularly useful for @code{asm}. Here is a summary of some of the
1624 machine-dependent constraints available on some particular machines;
1625 it includes both constraints that are useful for @code{asm} and
1626 constraints that aren't. The compiler source file mentioned in the
1627 table heading for each architecture is the definitive reference for
1628 the meanings of that architecture's constraints.
1631 @item ARM family---@file{config/arm/arm.h}
1634 Floating-point register
1637 VFP floating-point register
1640 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1644 Floating-point constant that would satisfy the constraint @samp{F} if it
1648 Integer that is valid as an immediate operand in a data processing
1649 instruction. That is, an integer in the range 0 to 255 rotated by a
1653 Integer in the range @minus{}4095 to 4095
1656 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1659 Integer that satisfies constraint @samp{I} when negated (twos complement)
1662 Integer in the range 0 to 32
1665 A memory reference where the exact address is in a single register
1666 (`@samp{m}' is preferable for @code{asm} statements)
1669 An item in the constant pool
1672 A symbol in the text segment of the current file
1675 A memory reference suitable for VFP load/store insns (reg+constant offset)
1678 A memory reference suitable for iWMMXt load/store instructions.
1681 A memory reference suitable for the ARMv4 ldrsb instruction.
1684 @item AVR family---@file{config/avr/constraints.md}
1687 Registers from r0 to r15
1690 Registers from r16 to r23
1693 Registers from r16 to r31
1696 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1699 Pointer register (r26--r31)
1702 Base pointer register (r28--r31)
1705 Stack pointer register (SPH:SPL)
1708 Temporary register r0
1711 Register pair X (r27:r26)
1714 Register pair Y (r29:r28)
1717 Register pair Z (r31:r30)
1720 Constant greater than @minus{}1, less than 64
1723 Constant greater than @minus{}64, less than 1
1732 Constant that fits in 8 bits
1735 Constant integer @minus{}1
1738 Constant integer 8, 16, or 24
1744 A floating point constant 0.0
1747 @item CRX Architecture---@file{config/crx/crx.h}
1751 Registers from r0 to r14 (registers without stack pointer)
1754 Register r16 (64-bit accumulator lo register)
1757 Register r17 (64-bit accumulator hi register)
1760 Register pair r16-r17. (64-bit accumulator lo-hi pair)
1763 Constant that fits in 3 bits
1766 Constant that fits in 4 bits
1769 Constant that fits in 5 bits
1772 Constant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48
1775 Floating point constant that is legal for store immediate
1778 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1781 Address base register
1784 Floating point register
1790 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1799 @samp{LINK} register
1802 @samp{CR} register (condition register) number 0
1805 @samp{CR} register (condition register)
1808 @samp{FPMEM} stack memory for FPR-GPR transfers
1811 Signed 16-bit constant
1814 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
1815 @code{SImode} constants)
1818 Unsigned 16-bit constant
1821 Signed 16-bit constant shifted left 16 bits
1824 Constant larger than 31
1833 Constant whose negation is a signed 16-bit constant
1836 Floating point constant that can be loaded into a register with one
1837 instruction per word
1840 Memory operand that is an offset from a register (@samp{m} is preferable
1841 for @code{asm} statements)
1847 Constant suitable as a 64-bit mask operand
1850 Constant suitable as a 32-bit mask operand
1853 System V Release 4 small data area reference
1856 @item MorphoTech family---@file{config/mt/mt.h}
1859 Constant for an arithmetic insn (16-bit signed integer).
1865 Constant for a logical insn (16-bit zero-extended integer).
1868 A constant that can be loaded with @code{lui} (i.e.@: the bottom 16
1872 A constant that takes two words to load (i.e.@: not matched by
1873 @code{I}, @code{K}, or @code{L}).
1876 Negative 16-bit constants other than -65536.
1879 A 15-bit signed integer constant.
1882 A positive 16-bit constant.
1885 @item Intel 386---@file{config/i386/constraints.md}
1888 Legacy register---the eight integer registers available on all
1889 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
1890 @code{si}, @code{di}, @code{bp}, @code{sp}).
1893 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
1894 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
1897 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
1898 @code{c}, and @code{d}.
1902 Any register that can be used as the index in a base+index memory
1903 access: that is, any general register except the stack pointer.
1907 The @code{a} register.
1910 The @code{b} register.
1913 The @code{c} register.
1916 The @code{d} register.
1919 The @code{si} register.
1922 The @code{di} register.
1925 The @code{a} and @code{d} registers, as a pair (for instructions that
1926 return half the result in one and half in the other).
1929 Any 80387 floating-point (stack) register.
1932 Top of 80387 floating-point stack (@code{%st(0)}).
1935 Second from top of 80387 floating-point stack (@code{%st(1)}).
1949 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
1952 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
1955 Signed 8-bit integer constant.
1958 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
1961 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
1964 Unsigned 8-bit integer constant (for @code{in} and @code{out}
1969 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
1973 Standard 80387 floating point constant.
1976 Standard SSE floating point constant.
1979 32-bit signed integer constant, or a symbolic reference known
1980 to fit that range (for immediate operands in sign-extending x86-64
1984 32-bit unsigned integer constant, or a symbolic reference known
1985 to fit that range (for immediate operands in zero-extending x86-64
1990 @item Intel IA-64---@file{config/ia64/ia64.h}
1993 General register @code{r0} to @code{r3} for @code{addl} instruction
1999 Predicate register (@samp{c} as in ``conditional'')
2002 Application register residing in M-unit
2005 Application register residing in I-unit
2008 Floating-point register
2012 Remember that @samp{m} allows postincrement and postdecrement which
2013 require printing with @samp{%Pn} on IA-64.
2014 Use @samp{S} to disallow postincrement and postdecrement.
2017 Floating-point constant 0.0 or 1.0
2020 14-bit signed integer constant
2023 22-bit signed integer constant
2026 8-bit signed integer constant for logical instructions
2029 8-bit adjusted signed integer constant for compare pseudo-ops
2032 6-bit unsigned integer constant for shift counts
2035 9-bit signed integer constant for load and store postincrements
2041 0 or @minus{}1 for @code{dep} instruction
2044 Non-volatile memory for floating-point loads and stores
2047 Integer constant in the range 1 to 4 for @code{shladd} instruction
2050 Memory operand except postincrement and postdecrement
2053 @item FRV---@file{config/frv/frv.h}
2056 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2059 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2062 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2063 @code{icc0} to @code{icc3}).
2066 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2069 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2070 Odd registers are excluded not in the class but through the use of a machine
2071 mode larger than 4 bytes.
2074 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2077 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2078 Odd registers are excluded not in the class but through the use of a machine
2079 mode larger than 4 bytes.
2082 Register in the class @code{LR_REG} (the @code{lr} register).
2085 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2086 Register numbers not divisible by 4 are excluded not in the class but through
2087 the use of a machine mode larger than 8 bytes.
2090 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2093 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2096 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2099 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2102 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2103 Register numbers not divisible by 4 are excluded not in the class but through
2104 the use of a machine mode larger than 8 bytes.
2107 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2110 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2113 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2116 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2119 Floating point constant zero
2122 6-bit signed integer constant
2125 10-bit signed integer constant
2128 16-bit signed integer constant
2131 16-bit unsigned integer constant
2134 12-bit signed integer constant that is negative---i.e.@: in the
2135 range of @minus{}2048 to @minus{}1
2141 12-bit signed integer constant that is greater than zero---i.e.@: in the
2146 @item Blackfin family---@file{config/bfin/bfin.h}
2155 A call clobbered P register.
2158 Even-numbered D register
2161 Odd-numbered D register
2164 Accumulator register.
2167 Even-numbered accumulator register.
2170 Odd-numbered accumulator register.
2182 Registers used for circular buffering, i.e. I, B, or L registers.
2197 Any D, P, B, M, I or L register.
2200 Additional registers typically used only in prologues and epilogues: RETS,
2201 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2204 Any register except accumulators or CC.
2207 Signed 16 bit integer (in the range -32768 to 32767)
2210 Unsigned 16 bit integer (in the range 0 to 65535)
2213 Signed 7 bit integer (in the range -64 to 63)
2216 Unsigned 7 bit integer (in the range 0 to 127)
2219 Unsigned 5 bit integer (in the range 0 to 31)
2222 Signed 4 bit integer (in the range -8 to 7)
2225 Signed 3 bit integer (in the range -3 to 4)
2228 Unsigned 3 bit integer (in the range 0 to 7)
2231 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2240 An integer constant with exactly a single bit set.
2243 An integer constant with all bits set except exactly one.
2251 @item M32C---@file{config/m32c/m32c.c}
2256 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2259 Any control register, when they're 16 bits wide (nothing if control
2260 registers are 24 bits wide)
2263 Any control register, when they're 24 bits wide.
2272 $r0 or $r2, or $r2r0 for 32 bit values.
2275 $r1 or $r3, or $r3r1 for 32 bit values.
2278 A register that can hold a 64 bit value.
2281 $r0 or $r1 (registers with addressable high/low bytes)
2290 Address registers when they're 16 bits wide.
2293 Address registers when they're 24 bits wide.
2296 Registers that can hold QI values.
2299 Registers that can be used with displacements ($a0, $a1, $sb).
2302 Registers that can hold 32 bit values.
2305 Registers that can hold 16 bit values.
2308 Registers chat can hold 16 bit values, including all control
2312 $r0 through R1, plus $a0 and $a1.
2318 The memory-based pseudo-registers $mem0 through $mem15.
2321 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2322 bit registers for m32cm, m32c).
2325 Matches multiple registers in a PARALLEL to form a larger register.
2326 Used to match function return values.
2335 -32768 @dots{} 32767
2341 -8 @dots{} -1 or 1 @dots{} 8
2344 -16 @dots{} -1 or 1 @dots{} 16
2347 -32 @dots{} -1 or 1 @dots{} 32
2353 An 8 bit value with exactly one bit set.
2356 A 16 bit value with exactly one bit set.
2359 The common src/dest memory addressing modes.
2362 Memory addressed using $a0 or $a1.
2365 Memory addressed with immediate addresses.
2368 Memory addressed using the stack pointer ($sp).
2371 Memory addressed using the frame base register ($fb).
2374 Memory addressed using the small base register ($sb).
2380 @item MIPS---@file{config/mips/constraints.md}
2383 An address register. This is equivalent to @code{r} unless
2384 generating MIPS16 code.
2387 A floating-point register (if available).
2390 The @code{hi} register.
2393 The @code{lo} register.
2396 The @code{hi} and @code{lo} registers.
2399 A register suitable for use in an indirect jump. This will always be
2400 @code{$25} for @option{-mabicalls}.
2403 Equivalent to @code{r}; retained for backwards compatibility.
2406 A floating-point condition code register.
2409 A signed 16-bit constant (for arithmetic instructions).
2415 An unsigned 16-bit constant (for logic instructions).
2418 A signed 32-bit constant in which the lower 16 bits are zero.
2419 Such constants can be loaded using @code{lui}.
2422 A constant that cannot be loaded using @code{lui}, @code{addiu}
2426 A constant in the range -65535 to -1 (inclusive).
2429 A signed 15-bit constant.
2432 A constant in the range 1 to 65535 (inclusive).
2435 Floating-point zero.
2438 An address that can be used in a non-macro load or store.
2441 @item Motorola 680x0---@file{config/m68k/m68k.h}
2450 68881 floating-point register, if available
2453 Integer in the range 1 to 8
2456 16-bit signed number
2459 Signed number whose magnitude is greater than 0x80
2462 Integer in the range @minus{}8 to @minus{}1
2465 Signed number whose magnitude is greater than 0x100
2468 Floating point constant that is not a 68881 constant
2471 @item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h}
2486 Temporary soft register _.tmp
2489 A soft register _.d1 to _.d31
2492 Stack pointer register
2501 Pseudo register `z' (replaced by `x' or `y' at the end)
2504 An address register: x, y or z
2507 An address register: x or y
2510 Register pair (x:d) to form a 32-bit value
2513 Constants in the range @minus{}65536 to 65535
2516 Constants whose 16-bit low part is zero
2519 Constant integer 1 or @minus{}1
2525 Constants in the range @minus{}8 to 2
2530 @item SPARC---@file{config/sparc/sparc.h}
2533 Floating-point register on the SPARC-V8 architecture and
2534 lower floating-point register on the SPARC-V9 architecture.
2537 Floating-point register. It is equivalent to @samp{f} on the
2538 SPARC-V8 architecture and contains both lower and upper
2539 floating-point registers on the SPARC-V9 architecture.
2542 Floating-point condition code register.
2545 Lower floating-point register. It is only valid on the SPARC-V9
2546 architecture when the Visual Instruction Set is available.
2549 Floating-point register. It is only valid on the SPARC-V9 architecture
2550 when the Visual Instruction Set is available.
2553 64-bit global or out register for the SPARC-V8+ architecture.
2556 Signed 13-bit constant
2562 32-bit constant with the low 12 bits clear (a constant that can be
2563 loaded with the @code{sethi} instruction)
2566 A constant in the range supported by @code{movcc} instructions
2569 A constant in the range supported by @code{movrcc} instructions
2572 Same as @samp{K}, except that it verifies that bits that are not in the
2573 lower 32-bit range are all zero. Must be used instead of @samp{K} for
2574 modes wider than @code{SImode}
2583 Signed 13-bit constant, sign-extended to 32 or 64 bits
2586 Floating-point constant whose integral representation can
2587 be moved into an integer register using a single sethi
2591 Floating-point constant whose integral representation can
2592 be moved into an integer register using a single mov
2596 Floating-point constant whose integral representation can
2597 be moved into an integer register using a high/lo_sum
2598 instruction sequence
2601 Memory address aligned to an 8-byte boundary
2607 Memory address for @samp{e} constraint registers
2614 @item TMS320C3x/C4x---@file{config/c4x/c4x.h}
2617 Auxiliary (address) register (ar0-ar7)
2620 Stack pointer register (sp)
2623 Standard (32-bit) precision integer register
2626 Extended (40-bit) precision register (r0-r11)
2629 Block count register (bk)
2632 Extended (40-bit) precision low register (r0-r7)
2635 Extended (40-bit) precision register (r0-r1)
2638 Extended (40-bit) precision register (r2-r3)
2641 Repeat count register (rc)
2644 Index register (ir0-ir1)
2647 Status (condition code) register (st)
2650 Data page register (dp)
2656 Immediate 16-bit floating-point constant
2659 Signed 16-bit constant
2662 Signed 8-bit constant
2665 Signed 5-bit constant
2668 Unsigned 16-bit constant
2671 Unsigned 8-bit constant
2674 Ones complement of unsigned 16-bit constant
2677 High 16-bit constant (32-bit constant with 16 LSBs zero)
2680 Indirect memory reference with signed 8-bit or index register displacement
2683 Indirect memory reference with unsigned 5-bit displacement
2686 Indirect memory reference with 1 bit or index register displacement
2689 Direct memory reference
2696 @item S/390 and zSeries---@file{config/s390/s390.h}
2699 Address register (general purpose register except r0)
2702 Condition code register
2705 Data register (arbitrary general purpose register)
2708 Floating-point register
2711 Unsigned 8-bit constant (0--255)
2714 Unsigned 12-bit constant (0--4095)
2717 Signed 16-bit constant (@minus{}32768--32767)
2720 Value appropriate as displacement.
2723 for short displacement
2724 @item (-524288..524287)
2725 for long displacement
2729 Constant integer with a value of 0x7fffffff.
2732 Multiple letter constraint followed by 4 parameter letters.
2735 number of the part counting from most to least significant
2739 mode of the containing operand
2741 value of the other parts (F---all bits set)
2743 The constraint matches if the specified part of a constant
2744 has a value different from it's other parts.
2747 Memory reference without index register and with short displacement.
2750 Memory reference with index register and short displacement.
2753 Memory reference without index register but with long displacement.
2756 Memory reference with index register and long displacement.
2759 Pointer with short displacement.
2762 Pointer with long displacement.
2765 Shift count operand.
2769 @item Score family---@file{config/score/score.h}
2772 Registers from r0 to r32.
2775 Registers from r0 to r16.
2778 r8---r11 or r22---r27 registers.
2799 cnt + lcb + scb register.
2802 cr0---cr15 register.
2814 cp1 + cp2 + cp3 registers.
2817 Unsigned 15 bit integer (in the range 0 to 32767).
2820 Unsigned 5 bit integer (in the range 0 to 31).
2823 Unsigned 16 bit integer (in the range 0 to 65535).
2826 Signed 16 bit integer (in the range @minus{}32768 to 32767).
2829 Unsigned 14 bit integer (in the range 0 to 16383).
2832 Signed 14 bit integer (in the range @minus{}8192 to 8191).
2835 Signed 15 bit integer (in the range @minus{}16384 to 16383).
2838 Signed 12 bit integer (in the range @minus{}2048 to 2047).
2841 An integer constant with exactly a single bit set.
2844 An integer constant.
2850 @item Xstormy16---@file{config/stormy16/stormy16.h}
2865 Registers r0 through r7.
2868 Registers r0 and r1.
2874 Registers r8 and r9.
2877 A constant between 0 and 3 inclusive.
2880 A constant that has exactly one bit set.
2883 A constant that has exactly one bit clear.
2886 A constant between 0 and 255 inclusive.
2889 A constant between @minus{}255 and 0 inclusive.
2892 A constant between @minus{}3 and 0 inclusive.
2895 A constant between 1 and 4 inclusive.
2898 A constant between @minus{}4 and @minus{}1 inclusive.
2901 A memory reference that is a stack push.
2904 A memory reference that is a stack pop.
2907 A memory reference that refers to a constant address of known value.
2910 The register indicated by Rx (not implemented yet).
2913 A constant that is not between 2 and 15 inclusive.
2920 @item Xtensa---@file{config/xtensa/xtensa.h}
2923 General-purpose 32-bit register
2926 One-bit boolean register
2929 MAC16 40-bit accumulator register
2932 Signed 12-bit integer constant, for use in MOVI instructions
2935 Signed 8-bit integer constant, for use in ADDI instructions
2938 Integer constant valid for BccI instructions
2941 Unsigned constant valid for BccUI instructions
2948 @node Define Constraints
2949 @subsection Defining Machine-Specific Constraints
2950 @cindex defining constraints
2951 @cindex constraints, defining
2953 Machine-specific constraints fall into two categories: register and
2954 non-register constraints. Within the latter category, constraints
2955 which allow subsets of all possible memory or address operands should
2956 be specially marked, to give @code{reload} more information.
2958 Machine-specific constraints can be given names of arbitrary length,
2959 but they must be entirely composed of letters, digits, underscores
2960 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
2961 must begin with a letter or underscore.
2963 In order to avoid ambiguity in operand constraint strings, no
2964 constraint can have a name that begins with any other constraint's
2965 name. For example, if @code{x} is defined as a constraint name,
2966 @code{xy} may not be, and vice versa. As a consequence of this rule,
2967 no constraint may begin with one of the generic constraint letters:
2968 @samp{E F V X g i m n o p r s}.
2970 Register constraints correspond directly to register classes.
2971 @xref{Register Classes}. There is thus not much flexibility in their
2974 @deffn {MD Expression} define_register_constraint name regclass docstring
2975 All three arguments are string constants.
2976 @var{name} is the name of the constraint, as it will appear in
2977 @code{match_operand} expressions. @var{regclass} can be either the
2978 name of the corresponding register class (@pxref{Register Classes}),
2979 or a C expression which evaluates to the appropriate register class.
2980 If it is an expression, it must have no side effects, and it cannot
2981 look at the operand. The usual use of expressions is to map some
2982 register constraints to @code{NO_REGS} when the register class
2983 is not available on a given subarchitecture.
2985 @var{docstring} is a sentence documenting the meaning of the
2986 constraint. Docstrings are explained further below.
2989 Non-register constraints are more like predicates: the constraint
2990 definition gives a Boolean expression which indicates whether the
2993 @deffn {MD Expression} define_constraint name docstring exp
2994 The @var{name} and @var{docstring} arguments are the same as for
2995 @code{define_register_constraint}, but note that the docstring comes
2996 immediately after the name for these expressions. @var{exp} is an RTL
2997 expression, obeying the same rules as the RTL expressions in predicate
2998 definitions. @xref{Defining Predicates}, for details. If it
2999 evaluates true, the constraint matches; if it evaluates false, it
3000 doesn't. Constraint expressions should indicate which RTL codes they
3001 might match, just like predicate expressions.
3003 @code{match_test} C expressions have access to the
3004 following variables:
3008 The RTL object defining the operand.
3010 The machine mode of @var{op}.
3012 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3014 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3015 @code{const_double}.
3017 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3018 @code{const_double}.
3020 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3021 @code{const_double}.
3024 The @var{*val} variables should only be used once another piece of the
3025 expression has verified that @var{op} is the appropriate kind of RTL
3029 Most non-register constraints should be defined with
3030 @code{define_constraint}. The remaining two definition expressions
3031 are only appropriate for constraints that should be handled specially
3032 by @code{reload} if they fail to match.
3034 @deffn {MD Expression} define_memory_constraint name docstring exp
3035 Use this expression for constraints that match a subset of all memory
3036 operands: that is, @code{reload} can make them match by converting the
3037 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3038 base register (from the register class specified by
3039 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3041 For example, on the S/390, some instructions do not accept arbitrary
3042 memory references, but only those that do not make use of an index
3043 register. The constraint letter @samp{Q} is defined to represent a
3044 memory address of this type. If @samp{Q} is defined with
3045 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3046 memory operand, because @code{reload} knows it can simply copy the
3047 memory address into a base register if required. This is analogous to
3048 the way a @samp{o} constraint can handle any memory operand.
3050 The syntax and semantics are otherwise identical to
3051 @code{define_constraint}.
3054 @deffn {MD Expression} define_address_constraint name docstring exp
3055 Use this expression for constraints that match a subset of all address
3056 operands: that is, @code{reload} can make the constraint match by
3057 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3058 with @var{X} a base register.
3060 Constraints defined with @code{define_address_constraint} can only be
3061 used with the @code{address_operand} predicate, or machine-specific
3062 predicates that work the same way. They are treated analogously to
3063 the generic @samp{p} constraint.
3065 The syntax and semantics are otherwise identical to
3066 @code{define_constraint}.
3069 For historical reasons, names beginning with the letters @samp{G H}
3070 are reserved for constraints that match only @code{const_double}s, and
3071 names beginning with the letters @samp{I J K L M N O P} are reserved
3072 for constraints that match only @code{const_int}s. This may change in
3073 the future. For the time being, constraints with these names must be
3074 written in a stylized form, so that @code{genpreds} can tell you did
3079 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3081 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3082 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3085 @c the semicolons line up in the formatted manual
3087 It is fine to use names beginning with other letters for constraints
3088 that match @code{const_double}s or @code{const_int}s.
3090 Each docstring in a constraint definition should be one or more complete
3091 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3092 In the future they will be copied into the GCC manual, in @ref{Machine
3093 Constraints}, replacing the hand-maintained tables currently found in
3094 that section. Also, in the future the compiler may use this to give
3095 more helpful diagnostics when poor choice of @code{asm} constraints
3096 causes a reload failure.
3098 If you put the pseudo-Texinfo directive @samp{@@internal} at the
3099 beginning of a docstring, then (in the future) it will appear only in
3100 the internals manual's version of the machine-specific constraint tables.
3101 Use this for constraints that should not appear in @code{asm} statements.
3103 @node C Constraint Interface
3104 @subsection Testing constraints from C
3105 @cindex testing constraints
3106 @cindex constraints, testing
3108 It is occasionally useful to test a constraint from C code rather than
3109 implicitly via the constraint string in a @code{match_operand}. The
3110 generated file @file{tm_p.h} declares a few interfaces for working
3111 with machine-specific constraints. None of these interfaces work with
3112 the generic constraints described in @ref{Simple Constraints}. This
3113 may change in the future.
3115 @strong{Warning:} @file{tm_p.h} may declare other functions that
3116 operate on constraints, besides the ones documented here. Do not use
3117 those functions from machine-dependent code. They exist to implement
3118 the old constraint interface that machine-independent components of
3119 the compiler still expect. They will change or disappear in the
3122 Some valid constraint names are not valid C identifiers, so there is a
3123 mangling scheme for referring to them from C@. Constraint names that
3124 do not contain angle brackets or underscores are left unchanged.
3125 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
3126 each @samp{>} with @samp{_g}. Here are some examples:
3128 @c the @c's prevent double blank lines in the printed manual.
3130 @multitable {Original} {Mangled}
3131 @item @strong{Original} @tab @strong{Mangled} @c
3132 @item @code{x} @tab @code{x} @c
3133 @item @code{P42x} @tab @code{P42x} @c
3134 @item @code{P4_x} @tab @code{P4__x} @c
3135 @item @code{P4>x} @tab @code{P4_gx} @c
3136 @item @code{P4>>} @tab @code{P4_g_g} @c
3137 @item @code{P4_g>} @tab @code{P4__g_g} @c
3141 Throughout this section, the variable @var{c} is either a constraint
3142 in the abstract sense, or a constant from @code{enum constraint_num};
3143 the variable @var{m} is a mangled constraint name (usually as part of
3144 a larger identifier).
3146 @deftp Enum constraint_num
3147 For each machine-specific constraint, there is a corresponding
3148 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
3149 constraint. Functions that take an @code{enum constraint_num} as an
3150 argument expect one of these constants.
3152 Machine-independent constraints do not have associated constants.
3153 This may change in the future.
3156 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
3157 For each machine-specific, non-register constraint @var{m}, there is
3158 one of these functions; it returns @code{true} if @var{exp} satisfies the
3159 constraint. These functions are only visible if @file{rtl.h} was included
3160 before @file{tm_p.h}.
3163 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
3164 Like the @code{satisfies_constraint_@var{m}} functions, but the
3165 constraint to test is given as an argument, @var{c}. If @var{c}
3166 specifies a register constraint, this function will always return
3170 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
3171 Returns the register class associated with @var{c}. If @var{c} is not
3172 a register constraint, or those registers are not available for the
3173 currently selected subtarget, returns @code{NO_REGS}.
3176 Here is an example use of @code{satisfies_constraint_@var{m}}. In
3177 peephole optimizations (@pxref{Peephole Definitions}), operand
3178 constraint strings are ignored, so if there are relevant constraints,
3179 they must be tested in the C condition. In the example, the
3180 optimization is applied if operand 2 does @emph{not} satisfy the
3181 @samp{K} constraint. (This is a simplified version of a peephole
3182 definition from the i386 machine description.)
3186 [(match_scratch:SI 3 "r")
3187 (set (match_operand:SI 0 "register_operand" "")
3188 (mult:SI (match_operand:SI 1 "memory_operand" "")
3189 (match_operand:SI 2 "immediate_operand" "")))]
3191 "!satisfies_constraint_K (operands[2])"
3193 [(set (match_dup 3) (match_dup 1))
3194 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
3199 @node Standard Names
3200 @section Standard Pattern Names For Generation
3201 @cindex standard pattern names
3202 @cindex pattern names
3203 @cindex names, pattern
3205 Here is a table of the instruction names that are meaningful in the RTL
3206 generation pass of the compiler. Giving one of these names to an
3207 instruction pattern tells the RTL generation pass that it can use the
3208 pattern to accomplish a certain task.
3211 @cindex @code{mov@var{m}} instruction pattern
3212 @item @samp{mov@var{m}}
3213 Here @var{m} stands for a two-letter machine mode name, in lowercase.
3214 This instruction pattern moves data with that machine mode from operand
3215 1 to operand 0. For example, @samp{movsi} moves full-word data.
3217 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
3218 own mode is wider than @var{m}, the effect of this instruction is
3219 to store the specified value in the part of the register that corresponds
3220 to mode @var{m}. Bits outside of @var{m}, but which are within the
3221 same target word as the @code{subreg} are undefined. Bits which are
3222 outside the target word are left unchanged.
3224 This class of patterns is special in several ways. First of all, each
3225 of these names up to and including full word size @emph{must} be defined,
3226 because there is no other way to copy a datum from one place to another.
3227 If there are patterns accepting operands in larger modes,
3228 @samp{mov@var{m}} must be defined for integer modes of those sizes.
3230 Second, these patterns are not used solely in the RTL generation pass.
3231 Even the reload pass can generate move insns to copy values from stack
3232 slots into temporary registers. When it does so, one of the operands is
3233 a hard register and the other is an operand that can need to be reloaded
3237 Therefore, when given such a pair of operands, the pattern must generate
3238 RTL which needs no reloading and needs no temporary registers---no
3239 registers other than the operands. For example, if you support the
3240 pattern with a @code{define_expand}, then in such a case the
3241 @code{define_expand} mustn't call @code{force_reg} or any other such
3242 function which might generate new pseudo registers.
3244 This requirement exists even for subword modes on a RISC machine where
3245 fetching those modes from memory normally requires several insns and
3246 some temporary registers.
3248 @findex change_address
3249 During reload a memory reference with an invalid address may be passed
3250 as an operand. Such an address will be replaced with a valid address
3251 later in the reload pass. In this case, nothing may be done with the
3252 address except to use it as it stands. If it is copied, it will not be
3253 replaced with a valid address. No attempt should be made to make such
3254 an address into a valid address and no routine (such as
3255 @code{change_address}) that will do so may be called. Note that
3256 @code{general_operand} will fail when applied to such an address.
3258 @findex reload_in_progress
3259 The global variable @code{reload_in_progress} (which must be explicitly
3260 declared if required) can be used to determine whether such special
3261 handling is required.
3263 The variety of operands that have reloads depends on the rest of the
3264 machine description, but typically on a RISC machine these can only be
3265 pseudo registers that did not get hard registers, while on other
3266 machines explicit memory references will get optional reloads.
3268 If a scratch register is required to move an object to or from memory,
3269 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
3271 If there are cases which need scratch registers during or after reload,
3272 you must provide an appropriate secondary_reload target hook.
3274 @findex no_new_pseudos
3275 The global variable @code{no_new_pseudos} can be used to determine if it
3276 is unsafe to create new pseudo registers. If this variable is nonzero, then
3277 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
3279 The constraints on a @samp{mov@var{m}} must permit moving any hard
3280 register to any other hard register provided that
3281 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
3282 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
3284 It is obligatory to support floating point @samp{mov@var{m}}
3285 instructions into and out of any registers that can hold fixed point
3286 values, because unions and structures (which have modes @code{SImode} or
3287 @code{DImode}) can be in those registers and they may have floating
3290 There may also be a need to support fixed point @samp{mov@var{m}}
3291 instructions in and out of floating point registers. Unfortunately, I
3292 have forgotten why this was so, and I don't know whether it is still
3293 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
3294 floating point registers, then the constraints of the fixed point
3295 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
3296 reload into a floating point register.
3298 @cindex @code{reload_in} instruction pattern
3299 @cindex @code{reload_out} instruction pattern
3300 @item @samp{reload_in@var{m}}
3301 @itemx @samp{reload_out@var{m}}
3302 These named patterns have been obsoleted by the target hook
3303 @code{secondary_reload}.
3305 Like @samp{mov@var{m}}, but used when a scratch register is required to
3306 move between operand 0 and operand 1. Operand 2 describes the scratch
3307 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
3308 macro in @pxref{Register Classes}.
3310 There are special restrictions on the form of the @code{match_operand}s
3311 used in these patterns. First, only the predicate for the reload
3312 operand is examined, i.e., @code{reload_in} examines operand 1, but not
3313 the predicates for operand 0 or 2. Second, there may be only one
3314 alternative in the constraints. Third, only a single register class
3315 letter may be used for the constraint; subsequent constraint letters
3316 are ignored. As a special exception, an empty constraint string
3317 matches the @code{ALL_REGS} register class. This may relieve ports
3318 of the burden of defining an @code{ALL_REGS} constraint letter just
3321 @cindex @code{movstrict@var{m}} instruction pattern
3322 @item @samp{movstrict@var{m}}
3323 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
3324 with mode @var{m} of a register whose natural mode is wider,
3325 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
3326 any of the register except the part which belongs to mode @var{m}.
3328 @cindex @code{movmisalign@var{m}} instruction pattern
3329 @item @samp{movmisalign@var{m}}
3330 This variant of a move pattern is designed to load or store a value
3331 from a memory address that is not naturally aligned for its mode.
3332 For a store, the memory will be in operand 0; for a load, the memory
3333 will be in operand 1. The other operand is guaranteed not to be a
3334 memory, so that it's easy to tell whether this is a load or store.
3336 This pattern is used by the autovectorizer, and when expanding a
3337 @code{MISALIGNED_INDIRECT_REF} expression.
3339 @cindex @code{load_multiple} instruction pattern
3340 @item @samp{load_multiple}
3341 Load several consecutive memory locations into consecutive registers.
3342 Operand 0 is the first of the consecutive registers, operand 1
3343 is the first memory location, and operand 2 is a constant: the
3344 number of consecutive registers.
3346 Define this only if the target machine really has such an instruction;
3347 do not define this if the most efficient way of loading consecutive
3348 registers from memory is to do them one at a time.
3350 On some machines, there are restrictions as to which consecutive
3351 registers can be stored into memory, such as particular starting or
3352 ending register numbers or only a range of valid counts. For those
3353 machines, use a @code{define_expand} (@pxref{Expander Definitions})
3354 and make the pattern fail if the restrictions are not met.
3356 Write the generated insn as a @code{parallel} with elements being a
3357 @code{set} of one register from the appropriate memory location (you may
3358 also need @code{use} or @code{clobber} elements). Use a
3359 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
3360 @file{rs6000.md} for examples of the use of this insn pattern.
3362 @cindex @samp{store_multiple} instruction pattern
3363 @item @samp{store_multiple}
3364 Similar to @samp{load_multiple}, but store several consecutive registers
3365 into consecutive memory locations. Operand 0 is the first of the
3366 consecutive memory locations, operand 1 is the first register, and
3367 operand 2 is a constant: the number of consecutive registers.
3369 @cindex @code{vec_set@var{m}} instruction pattern
3370 @item @samp{vec_set@var{m}}
3371 Set given field in the vector value. Operand 0 is the vector to modify,
3372 operand 1 is new value of field and operand 2 specify the field index.
3374 @cindex @code{vec_extract@var{m}} instruction pattern
3375 @item @samp{vec_extract@var{m}}
3376 Extract given field from the vector value. Operand 1 is the vector, operand 2
3377 specify field index and operand 0 place to store value into.
3379 @cindex @code{vec_init@var{m}} instruction pattern
3380 @item @samp{vec_init@var{m}}
3381 Initialize the vector to given values. Operand 0 is the vector to initialize
3382 and operand 1 is parallel containing values for individual fields.
3384 @cindex @code{push@var{m}1} instruction pattern
3385 @item @samp{push@var{m}1}
3386 Output a push instruction. Operand 0 is value to push. Used only when
3387 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
3388 missing and in such case an @code{mov} expander is used instead, with a
3389 @code{MEM} expression forming the push operation. The @code{mov} expander
3390 method is deprecated.
3392 @cindex @code{add@var{m}3} instruction pattern
3393 @item @samp{add@var{m}3}
3394 Add operand 2 and operand 1, storing the result in operand 0. All operands
3395 must have mode @var{m}. This can be used even on two-address machines, by
3396 means of constraints requiring operands 1 and 0 to be the same location.
3398 @cindex @code{sub@var{m}3} instruction pattern
3399 @cindex @code{mul@var{m}3} instruction pattern
3400 @cindex @code{div@var{m}3} instruction pattern
3401 @cindex @code{udiv@var{m}3} instruction pattern
3402 @cindex @code{mod@var{m}3} instruction pattern
3403 @cindex @code{umod@var{m}3} instruction pattern
3404 @cindex @code{umin@var{m}3} instruction pattern
3405 @cindex @code{umax@var{m}3} instruction pattern
3406 @cindex @code{and@var{m}3} instruction pattern
3407 @cindex @code{ior@var{m}3} instruction pattern
3408 @cindex @code{xor@var{m}3} instruction pattern
3409 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
3410 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}
3411 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
3412 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
3413 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
3414 Similar, for other arithmetic operations.
3416 @cindex @code{min@var{m}3} instruction pattern
3417 @cindex @code{max@var{m}3} instruction pattern
3418 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
3419 Signed minimum and maximum operations. When used with floating point,
3420 if both operands are zeros, or if either operand is @code{NaN}, then
3421 it is unspecified which of the two operands is returned as the result.
3423 @cindex @code{reduc_smin_@var{m}} instruction pattern
3424 @cindex @code{reduc_smax_@var{m}} instruction pattern
3425 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
3426 Find the signed minimum/maximum of the elements of a vector. The vector is
3427 operand 1, and the scalar result is stored in the least significant bits of
3428 operand 0 (also a vector). The output and input vector should have the same
3431 @cindex @code{reduc_umin_@var{m}} instruction pattern
3432 @cindex @code{reduc_umax_@var{m}} instruction pattern
3433 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
3434 Find the unsigned minimum/maximum of the elements of a vector. The vector is
3435 operand 1, and the scalar result is stored in the least significant bits of
3436 operand 0 (also a vector). The output and input vector should have the same
3439 @cindex @code{reduc_splus_@var{m}} instruction pattern
3440 @item @samp{reduc_splus_@var{m}}
3441 Compute the sum of the signed elements of a vector. The vector is operand 1,
3442 and the scalar result is stored in the least significant bits of operand 0
3443 (also a vector). The output and input vector should have the same modes.
3445 @cindex @code{reduc_uplus_@var{m}} instruction pattern
3446 @item @samp{reduc_uplus_@var{m}}
3447 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
3448 and the scalar result is stored in the least significant bits of operand 0
3449 (also a vector). The output and input vector should have the same modes.
3451 @cindex @code{sdot_prod@var{m}} instruction pattern
3452 @item @samp{sdot_prod@var{m}}
3453 @cindex @code{udot_prod@var{m}} instruction pattern
3454 @item @samp{udot_prod@var{m}}
3455 Compute the sum of the products of two signed/unsigned elements.
3456 Operand 1 and operand 2 are of the same mode. Their product, which is of a
3457 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
3458 wider than the mode of the product. The result is placed in operand 0, which
3459 is of the same mode as operand 3.
3461 @cindex @code{ssum_widen@var{m3}} instruction pattern
3462 @item @samp{ssum_widen@var{m3}}
3463 @cindex @code{usum_widen@var{m3}} instruction pattern
3464 @item @samp{usum_widen@var{m3}}
3465 Operands 0 and 2 are of the same mode, which is wider than the mode of
3466 operand 1. Add operand 1 to operand 2 and place the widened result in
3467 operand 0. (This is used express accumulation of elements into an accumulator
3470 @cindex @code{vec_shl_@var{m}} instruction pattern
3471 @cindex @code{vec_shr_@var{m}} instruction pattern
3472 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
3473 Whole vector left/right shift in bits.
3474 Operand 1 is a vector to be shifted.
3475 Operand 2 is an integer shift amount in bits.
3476 Operand 0 is where the resulting shifted vector is stored.
3477 The output and input vectors should have the same modes.
3479 @cindex @code{mulhisi3} instruction pattern
3480 @item @samp{mulhisi3}
3481 Multiply operands 1 and 2, which have mode @code{HImode}, and store
3482 a @code{SImode} product in operand 0.
3484 @cindex @code{mulqihi3} instruction pattern
3485 @cindex @code{mulsidi3} instruction pattern
3486 @item @samp{mulqihi3}, @samp{mulsidi3}
3487 Similar widening-multiplication instructions of other widths.
3489 @cindex @code{umulqihi3} instruction pattern
3490 @cindex @code{umulhisi3} instruction pattern
3491 @cindex @code{umulsidi3} instruction pattern
3492 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
3493 Similar widening-multiplication instructions that do unsigned
3496 @cindex @code{usmulqihi3} instruction pattern
3497 @cindex @code{usmulhisi3} instruction pattern
3498 @cindex @code{usmulsidi3} instruction pattern
3499 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
3500 Similar widening-multiplication instructions that interpret the first
3501 operand as unsigned and the second operand as signed, then do a signed
3504 @cindex @code{smul@var{m}3_highpart} instruction pattern
3505 @item @samp{smul@var{m}3_highpart}
3506 Perform a signed multiplication of operands 1 and 2, which have mode
3507 @var{m}, and store the most significant half of the product in operand 0.
3508 The least significant half of the product is discarded.
3510 @cindex @code{umul@var{m}3_highpart} instruction pattern
3511 @item @samp{umul@var{m}3_highpart}
3512 Similar, but the multiplication is unsigned.
3514 @cindex @code{divmod@var{m}4} instruction pattern
3515 @item @samp{divmod@var{m}4}
3516 Signed division that produces both a quotient and a remainder.
3517 Operand 1 is divided by operand 2 to produce a quotient stored
3518 in operand 0 and a remainder stored in operand 3.
3520 For machines with an instruction that produces both a quotient and a
3521 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
3522 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
3523 allows optimization in the relatively common case when both the quotient
3524 and remainder are computed.
3526 If an instruction that just produces a quotient or just a remainder
3527 exists and is more efficient than the instruction that produces both,
3528 write the output routine of @samp{divmod@var{m}4} to call
3529 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
3530 quotient or remainder and generate the appropriate instruction.
3532 @cindex @code{udivmod@var{m}4} instruction pattern
3533 @item @samp{udivmod@var{m}4}
3534 Similar, but does unsigned division.
3536 @anchor{shift patterns}
3537 @cindex @code{ashl@var{m}3} instruction pattern
3538 @item @samp{ashl@var{m}3}
3539 Arithmetic-shift operand 1 left by a number of bits specified by operand
3540 2, and store the result in operand 0. Here @var{m} is the mode of
3541 operand 0 and operand 1; operand 2's mode is specified by the
3542 instruction pattern, and the compiler will convert the operand to that
3543 mode before generating the instruction. The meaning of out-of-range shift
3544 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
3545 @xref{TARGET_SHIFT_TRUNCATION_MASK}.
3547 @cindex @code{ashr@var{m}3} instruction pattern
3548 @cindex @code{lshr@var{m}3} instruction pattern
3549 @cindex @code{rotl@var{m}3} instruction pattern
3550 @cindex @code{rotr@var{m}3} instruction pattern
3551 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
3552 Other shift and rotate instructions, analogous to the
3553 @code{ashl@var{m}3} instructions.
3555 @cindex @code{neg@var{m}2} instruction pattern
3556 @item @samp{neg@var{m}2}
3557 Negate operand 1 and store the result in operand 0.
3559 @cindex @code{abs@var{m}2} instruction pattern
3560 @item @samp{abs@var{m}2}
3561 Store the absolute value of operand 1 into operand 0.
3563 @cindex @code{sqrt@var{m}2} instruction pattern
3564 @item @samp{sqrt@var{m}2}
3565 Store the square root of operand 1 into operand 0.
3567 The @code{sqrt} built-in function of C always uses the mode which
3568 corresponds to the C data type @code{double} and the @code{sqrtf}
3569 built-in function uses the mode which corresponds to the C data
3572 @cindex @code{cos@var{m}2} instruction pattern
3573 @item @samp{cos@var{m}2}
3574 Store the cosine of operand 1 into operand 0.
3576 The @code{cos} built-in function of C always uses the mode which
3577 corresponds to the C data type @code{double} and the @code{cosf}
3578 built-in function uses the mode which corresponds to the C data
3581 @cindex @code{sin@var{m}2} instruction pattern
3582 @item @samp{sin@var{m}2}
3583 Store the sine of operand 1 into operand 0.
3585 The @code{sin} built-in function of C always uses the mode which
3586 corresponds to the C data type @code{double} and the @code{sinf}
3587 built-in function uses the mode which corresponds to the C data
3590 @cindex @code{exp@var{m}2} instruction pattern
3591 @item @samp{exp@var{m}2}
3592 Store the exponential of operand 1 into operand 0.
3594 The @code{exp} built-in function of C always uses the mode which
3595 corresponds to the C data type @code{double} and the @code{expf}
3596 built-in function uses the mode which corresponds to the C data
3599 @cindex @code{log@var{m}2} instruction pattern
3600 @item @samp{log@var{m}2}
3601 Store the natural logarithm of operand 1 into operand 0.
3603 The @code{log} built-in function of C always uses the mode which
3604 corresponds to the C data type @code{double} and the @code{logf}
3605 built-in function uses the mode which corresponds to the C data
3608 @cindex @code{pow@var{m}3} instruction pattern
3609 @item @samp{pow@var{m}3}
3610 Store the value of operand 1 raised to the exponent operand 2
3613 The @code{pow} built-in function of C always uses the mode which
3614 corresponds to the C data type @code{double} and the @code{powf}
3615 built-in function uses the mode which corresponds to the C data
3618 @cindex @code{atan2@var{m}3} instruction pattern
3619 @item @samp{atan2@var{m}3}
3620 Store the arc tangent (inverse tangent) of operand 1 divided by
3621 operand 2 into operand 0, using the signs of both arguments to
3622 determine the quadrant of the result.
3624 The @code{atan2} built-in function of C always uses the mode which
3625 corresponds to the C data type @code{double} and the @code{atan2f}
3626 built-in function uses the mode which corresponds to the C data
3629 @cindex @code{floor@var{m}2} instruction pattern
3630 @item @samp{floor@var{m}2}
3631 Store the largest integral value not greater than argument.
3633 The @code{floor} built-in function of C always uses the mode which
3634 corresponds to the C data type @code{double} and the @code{floorf}
3635 built-in function uses the mode which corresponds to the C data
3638 @cindex @code{btrunc@var{m}2} instruction pattern
3639 @item @samp{btrunc@var{m}2}
3640 Store the argument rounded to integer towards zero.
3642 The @code{trunc} built-in function of C always uses the mode which
3643 corresponds to the C data type @code{double} and the @code{truncf}
3644 built-in function uses the mode which corresponds to the C data
3647 @cindex @code{round@var{m}2} instruction pattern
3648 @item @samp{round@var{m}2}
3649 Store the argument rounded to integer away from zero.
3651 The @code{round} built-in function of C always uses the mode which
3652 corresponds to the C data type @code{double} and the @code{roundf}
3653 built-in function uses the mode which corresponds to the C data
3656 @cindex @code{ceil@var{m}2} instruction pattern
3657 @item @samp{ceil@var{m}2}
3658 Store the argument rounded to integer away from zero.
3660 The @code{ceil} built-in function of C always uses the mode which
3661 corresponds to the C data type @code{double} and the @code{ceilf}
3662 built-in function uses the mode which corresponds to the C data
3665 @cindex @code{nearbyint@var{m}2} instruction pattern
3666 @item @samp{nearbyint@var{m}2}
3667 Store the argument rounded according to the default rounding mode
3669 The @code{nearbyint} built-in function of C always uses the mode which
3670 corresponds to the C data type @code{double} and the @code{nearbyintf}
3671 built-in function uses the mode which corresponds to the C data
3674 @cindex @code{rint@var{m}2} instruction pattern
3675 @item @samp{rint@var{m}2}
3676 Store the argument rounded according to the default rounding mode and
3677 raise the inexact exception when the result differs in value from
3680 The @code{rint} built-in function of C always uses the mode which
3681 corresponds to the C data type @code{double} and the @code{rintf}
3682 built-in function uses the mode which corresponds to the C data
3685 @cindex @code{copysign@var{m}3} instruction pattern
3686 @item @samp{copysign@var{m}3}
3687 Store a value with the magnitude of operand 1 and the sign of operand
3690 The @code{copysign} built-in function of C always uses the mode which
3691 corresponds to the C data type @code{double} and the @code{copysignf}
3692 built-in function uses the mode which corresponds to the C data
3695 @cindex @code{ffs@var{m}2} instruction pattern
3696 @item @samp{ffs@var{m}2}
3697 Store into operand 0 one plus the index of the least significant 1-bit
3698 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
3699 of operand 0; operand 1's mode is specified by the instruction
3700 pattern, and the compiler will convert the operand to that mode before
3701 generating the instruction.
3703 The @code{ffs} built-in function of C always uses the mode which
3704 corresponds to the C data type @code{int}.
3706 @cindex @code{clz@var{m}2} instruction pattern
3707 @item @samp{clz@var{m}2}
3708 Store into operand 0 the number of leading 0-bits in @var{x}, starting
3709 at the most significant bit position. If @var{x} is 0, the result is
3710 undefined. @var{m} is the mode of operand 0; operand 1's mode is
3711 specified by the instruction pattern, and the compiler will convert the
3712 operand to that mode before generating the instruction.
3714 @cindex @code{ctz@var{m}2} instruction pattern
3715 @item @samp{ctz@var{m}2}
3716 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
3717 at the least significant bit position. If @var{x} is 0, the result is
3718 undefined. @var{m} is the mode of operand 0; operand 1's mode is
3719 specified by the instruction pattern, and the compiler will convert the
3720 operand to that mode before generating the instruction.
3722 @cindex @code{popcount@var{m}2} instruction pattern
3723 @item @samp{popcount@var{m}2}
3724 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
3725 mode of operand 0; operand 1's mode is specified by the instruction
3726 pattern, and the compiler will convert the operand to that mode before
3727 generating the instruction.
3729 @cindex @code{parity@var{m}2} instruction pattern
3730 @item @samp{parity@var{m}2}
3731 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
3732 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
3733 is specified by the instruction pattern, and the compiler will convert
3734 the operand to that mode before generating the instruction.
3736 @cindex @code{one_cmpl@var{m}2} instruction pattern
3737 @item @samp{one_cmpl@var{m}2}
3738 Store the bitwise-complement of operand 1 into operand 0.
3740 @cindex @code{cmp@var{m}} instruction pattern
3741 @item @samp{cmp@var{m}}
3742 Compare operand 0 and operand 1, and set the condition codes.
3743 The RTL pattern should look like this:
3746 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
3747 (match_operand:@var{m} 1 @dots{})))
3750 @cindex @code{tst@var{m}} instruction pattern
3751 @item @samp{tst@var{m}}
3752 Compare operand 0 against zero, and set the condition codes.
3753 The RTL pattern should look like this:
3756 (set (cc0) (match_operand:@var{m} 0 @dots{}))
3759 @samp{tst@var{m}} patterns should not be defined for machines that do
3760 not use @code{(cc0)}. Doing so would confuse the optimizer since it
3761 would no longer be clear which @code{set} operations were comparisons.
3762 The @samp{cmp@var{m}} patterns should be used instead.
3764 @cindex @code{movmem@var{m}} instruction pattern
3765 @item @samp{movmem@var{m}}
3766 Block move instruction. The destination and source blocks of memory
3767 are the first two operands, and both are @code{mem:BLK}s with an
3768 address in mode @code{Pmode}.
3770 The number of bytes to move is the third operand, in mode @var{m}.
3771 Usually, you specify @code{word_mode} for @var{m}. However, if you can
3772 generate better code knowing the range of valid lengths is smaller than
3773 those representable in a full word, you should provide a pattern with a
3774 mode corresponding to the range of values you can handle efficiently
3775 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
3776 that appear negative) and also a pattern with @code{word_mode}.
3778 The fourth operand is the known shared alignment of the source and
3779 destination, in the form of a @code{const_int} rtx. Thus, if the
3780 compiler knows that both source and destination are word-aligned,
3781 it may provide the value 4 for this operand.
3783 Descriptions of multiple @code{movmem@var{m}} patterns can only be
3784 beneficial if the patterns for smaller modes have fewer restrictions
3785 on their first, second and fourth operands. Note that the mode @var{m}
3786 in @code{movmem@var{m}} does not impose any restriction on the mode of
3787 individually moved data units in the block.
3789 These patterns need not give special consideration to the possibility
3790 that the source and destination strings might overlap.
3792 @cindex @code{movstr} instruction pattern
3794 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
3795 an output operand in mode @code{Pmode}. The addresses of the
3796 destination and source strings are operands 1 and 2, and both are
3797 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
3798 the expansion of this pattern should store in operand 0 the address in
3799 which the @code{NUL} terminator was stored in the destination string.
3801 @cindex @code{setmem@var{m}} instruction pattern
3802 @item @samp{setmem@var{m}}
3803 Block set instruction. The destination string is the first operand,
3804 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
3805 number of bytes to set is the second operand, in mode @var{m}. The value to
3806 initialize the memory with is the third operand. Targets that only support the
3807 clearing of memory should reject any value that is not the constant 0. See
3808 @samp{movmem@var{m}} for a discussion of the choice of mode.
3810 The fourth operand is the known alignment of the destination, in the form
3811 of a @code{const_int} rtx. Thus, if the compiler knows that the
3812 destination is word-aligned, it may provide the value 4 for this
3815 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
3817 @cindex @code{cmpstrn@var{m}} instruction pattern
3818 @item @samp{cmpstrn@var{m}}
3819 String compare instruction, with five operands. Operand 0 is the output;
3820 it has mode @var{m}. The remaining four operands are like the operands
3821 of @samp{movmem@var{m}}. The two memory blocks specified are compared
3822 byte by byte in lexicographic order starting at the beginning of each
3823 string. The instruction is not allowed to prefetch more than one byte
3824 at a time since either string may end in the first byte and reading past
3825 that may access an invalid page or segment and cause a fault. The
3826 effect of the instruction is to store a value in operand 0 whose sign
3827 indicates the result of the comparison.
3829 @cindex @code{cmpstr@var{m}} instruction pattern
3830 @item @samp{cmpstr@var{m}}
3831 String compare instruction, without known maximum length. Operand 0 is the
3832 output; it has mode @var{m}. The second and third operand are the blocks of
3833 memory to be compared; both are @code{mem:BLK} with an address in mode
3836 The fourth operand is the known shared alignment of the source and
3837 destination, in the form of a @code{const_int} rtx. Thus, if the
3838 compiler knows that both source and destination are word-aligned,
3839 it may provide the value 4 for this operand.
3841 The two memory blocks specified are compared byte by byte in lexicographic
3842 order starting at the beginning of each string. The instruction is not allowed
3843 to prefetch more than one byte at a time since either string may end in the
3844 first byte and reading past that may access an invalid page or segment and
3845 cause a fault. The effect of the instruction is to store a value in operand 0
3846 whose sign indicates the result of the comparison.
3848 @cindex @code{cmpmem@var{m}} instruction pattern
3849 @item @samp{cmpmem@var{m}}
3850 Block compare instruction, with five operands like the operands
3851 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
3852 byte by byte in lexicographic order starting at the beginning of each
3853 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
3854 any bytes in the two memory blocks. The effect of the instruction is
3855 to store a value in operand 0 whose sign indicates the result of the
3858 @cindex @code{strlen@var{m}} instruction pattern
3859 @item @samp{strlen@var{m}}
3860 Compute the length of a string, with three operands.
3861 Operand 0 is the result (of mode @var{m}), operand 1 is
3862 a @code{mem} referring to the first character of the string,
3863 operand 2 is the character to search for (normally zero),
3864 and operand 3 is a constant describing the known alignment
3865 of the beginning of the string.
3867 @cindex @code{float@var{mn}2} instruction pattern
3868 @item @samp{float@var{m}@var{n}2}
3869 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
3870 floating point mode @var{n} and store in operand 0 (which has mode
3873 @cindex @code{floatuns@var{mn}2} instruction pattern
3874 @item @samp{floatuns@var{m}@var{n}2}
3875 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
3876 to floating point mode @var{n} and store in operand 0 (which has mode
3879 @cindex @code{fix@var{mn}2} instruction pattern
3880 @item @samp{fix@var{m}@var{n}2}
3881 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3882 point mode @var{n} as a signed number and store in operand 0 (which
3883 has mode @var{n}). This instruction's result is defined only when
3884 the value of operand 1 is an integer.
3886 If the machine description defines this pattern, it also needs to
3887 define the @code{ftrunc} pattern.
3889 @cindex @code{fixuns@var{mn}2} instruction pattern
3890 @item @samp{fixuns@var{m}@var{n}2}
3891 Convert operand 1 (valid for floating point mode @var{m}) to fixed
3892 point mode @var{n} as an unsigned number and store in operand 0 (which
3893 has mode @var{n}). This instruction's result is defined only when the
3894 value of operand 1 is an integer.
3896 @cindex @code{ftrunc@var{m}2} instruction pattern
3897 @item @samp{ftrunc@var{m}2}
3898 Convert operand 1 (valid for floating point mode @var{m}) to an
3899 integer value, still represented in floating point mode @var{m}, and
3900 store it in operand 0 (valid for floating point mode @var{m}).
3902 @cindex @code{fix_trunc@var{mn}2} instruction pattern
3903 @item @samp{fix_trunc@var{m}@var{n}2}
3904 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
3905 of mode @var{m} by converting the value to an integer.
3907 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
3908 @item @samp{fixuns_trunc@var{m}@var{n}2}
3909 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
3910 value of mode @var{m} by converting the value to an integer.
3912 @cindex @code{trunc@var{mn}2} instruction pattern
3913 @item @samp{trunc@var{m}@var{n}2}
3914 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
3915 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3916 point or both floating point.
3918 @cindex @code{extend@var{mn}2} instruction pattern
3919 @item @samp{extend@var{m}@var{n}2}
3920 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
3921 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3922 point or both floating point.
3924 @cindex @code{zero_extend@var{mn}2} instruction pattern
3925 @item @samp{zero_extend@var{m}@var{n}2}
3926 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
3927 store in operand 0 (which has mode @var{n}). Both modes must be fixed
3930 @cindex @code{extv} instruction pattern
3932 Extract a bit-field from operand 1 (a register or memory operand), where
3933 operand 2 specifies the width in bits and operand 3 the starting bit,
3934 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
3935 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
3936 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
3937 be valid for @code{word_mode}.
3939 The RTL generation pass generates this instruction only with constants
3940 for operands 2 and 3 and the constant is never zero for operand 2.
3942 The bit-field value is sign-extended to a full word integer
3943 before it is stored in operand 0.
3945 @cindex @code{extzv} instruction pattern
3947 Like @samp{extv} except that the bit-field value is zero-extended.
3949 @cindex @code{insv} instruction pattern
3951 Store operand 3 (which must be valid for @code{word_mode}) into a
3952 bit-field in operand 0, where operand 1 specifies the width in bits and
3953 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
3954 @code{word_mode}; often @code{word_mode} is allowed only for registers.
3955 Operands 1 and 2 must be valid for @code{word_mode}.
3957 The RTL generation pass generates this instruction only with constants
3958 for operands 1 and 2 and the constant is never zero for operand 1.
3960 @cindex @code{mov@var{mode}cc} instruction pattern
3961 @item @samp{mov@var{mode}cc}
3962 Conditionally move operand 2 or operand 3 into operand 0 according to the
3963 comparison in operand 1. If the comparison is true, operand 2 is moved
3964 into operand 0, otherwise operand 3 is moved.
3966 The mode of the operands being compared need not be the same as the operands
3967 being moved. Some machines, sparc64 for example, have instructions that
3968 conditionally move an integer value based on the floating point condition
3969 codes and vice versa.
3971 If the machine does not have conditional move instructions, do not
3972 define these patterns.
3974 @cindex @code{add@var{mode}cc} instruction pattern
3975 @item @samp{add@var{mode}cc}
3976 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
3977 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
3978 comparison in operand 1. If the comparison is true, operand 2 is moved into
3979 operand 0, otherwise (operand 2 + operand 3) is moved.
3981 @cindex @code{s@var{cond}} instruction pattern
3982 @item @samp{s@var{cond}}
3983 Store zero or nonzero in the operand according to the condition codes.
3984 Value stored is nonzero iff the condition @var{cond} is true.
3985 @var{cond} is the name of a comparison operation expression code, such
3986 as @code{eq}, @code{lt} or @code{leu}.
3988 You specify the mode that the operand must have when you write the
3989 @code{match_operand} expression. The compiler automatically sees
3990 which mode you have used and supplies an operand of that mode.
3992 The value stored for a true condition must have 1 as its low bit, or
3993 else must be negative. Otherwise the instruction is not suitable and
3994 you should omit it from the machine description. You describe to the
3995 compiler exactly which value is stored by defining the macro
3996 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
3997 found that can be used for all the @samp{s@var{cond}} patterns, you
3998 should omit those operations from the machine description.
4000 These operations may fail, but should do so only in relatively
4001 uncommon cases; if they would fail for common cases involving
4002 integer comparisons, it is best to omit these patterns.
4004 If these operations are omitted, the compiler will usually generate code
4005 that copies the constant one to the target and branches around an
4006 assignment of zero to the target. If this code is more efficient than
4007 the potential instructions used for the @samp{s@var{cond}} pattern
4008 followed by those required to convert the result into a 1 or a zero in
4009 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
4010 the machine description.
4012 @cindex @code{b@var{cond}} instruction pattern
4013 @item @samp{b@var{cond}}
4014 Conditional branch instruction. Operand 0 is a @code{label_ref} that
4015 refers to the label to jump to. Jump if the condition codes meet
4016 condition @var{cond}.
4018 Some machines do not follow the model assumed here where a comparison
4019 instruction is followed by a conditional branch instruction. In that
4020 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
4021 simply store the operands away and generate all the required insns in a
4022 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
4023 branch operations. All calls to expand @samp{b@var{cond}} patterns are
4024 immediately preceded by calls to expand either a @samp{cmp@var{m}}
4025 pattern or a @samp{tst@var{m}} pattern.
4027 Machines that use a pseudo register for the condition code value, or
4028 where the mode used for the comparison depends on the condition being
4029 tested, should also use the above mechanism. @xref{Jump Patterns}.
4031 The above discussion also applies to the @samp{mov@var{mode}cc} and
4032 @samp{s@var{cond}} patterns.
4034 @cindex @code{cbranch@var{mode}4} instruction pattern
4035 @item @samp{cbranch@var{mode}4}
4036 Conditional branch instruction combined with a compare instruction.
4037 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
4038 first and second operands of the comparison, respectively. Operand 3
4039 is a @code{label_ref} that refers to the label to jump to.
4041 @cindex @code{jump} instruction pattern
4043 A jump inside a function; an unconditional branch. Operand 0 is the
4044 @code{label_ref} of the label to jump to. This pattern name is mandatory
4047 @cindex @code{call} instruction pattern
4049 Subroutine call instruction returning no value. Operand 0 is the
4050 function to call; operand 1 is the number of bytes of arguments pushed
4051 as a @code{const_int}; operand 2 is the number of registers used as
4054 On most machines, operand 2 is not actually stored into the RTL
4055 pattern. It is supplied for the sake of some RISC machines which need
4056 to put this information into the assembler code; they can put it in
4057 the RTL instead of operand 1.
4059 Operand 0 should be a @code{mem} RTX whose address is the address of the
4060 function. Note, however, that this address can be a @code{symbol_ref}
4061 expression even if it would not be a legitimate memory address on the
4062 target machine. If it is also not a valid argument for a call
4063 instruction, the pattern for this operation should be a
4064 @code{define_expand} (@pxref{Expander Definitions}) that places the
4065 address into a register and uses that register in the call instruction.
4067 @cindex @code{call_value} instruction pattern
4068 @item @samp{call_value}
4069 Subroutine call instruction returning a value. Operand 0 is the hard
4070 register in which the value is returned. There are three more
4071 operands, the same as the three operands of the @samp{call}
4072 instruction (but with numbers increased by one).
4074 Subroutines that return @code{BLKmode} objects use the @samp{call}
4077 @cindex @code{call_pop} instruction pattern
4078 @cindex @code{call_value_pop} instruction pattern
4079 @item @samp{call_pop}, @samp{call_value_pop}
4080 Similar to @samp{call} and @samp{call_value}, except used if defined and
4081 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
4082 that contains both the function call and a @code{set} to indicate the
4083 adjustment made to the frame pointer.
4085 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
4086 patterns increases the number of functions for which the frame pointer
4087 can be eliminated, if desired.
4089 @cindex @code{untyped_call} instruction pattern
4090 @item @samp{untyped_call}
4091 Subroutine call instruction returning a value of any type. Operand 0 is
4092 the function to call; operand 1 is a memory location where the result of
4093 calling the function is to be stored; operand 2 is a @code{parallel}
4094 expression where each element is a @code{set} expression that indicates
4095 the saving of a function return value into the result block.
4097 This instruction pattern should be defined to support
4098 @code{__builtin_apply} on machines where special instructions are needed
4099 to call a subroutine with arbitrary arguments or to save the value
4100 returned. This instruction pattern is required on machines that have
4101 multiple registers that can hold a return value
4102 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
4104 @cindex @code{return} instruction pattern
4106 Subroutine return instruction. This instruction pattern name should be
4107 defined only if a single instruction can do all the work of returning
4110 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
4111 RTL generation phase. In this case it is to support machines where
4112 multiple instructions are usually needed to return from a function, but
4113 some class of functions only requires one instruction to implement a
4114 return. Normally, the applicable functions are those which do not need
4115 to save any registers or allocate stack space.
4117 @findex reload_completed
4118 @findex leaf_function_p
4119 For such machines, the condition specified in this pattern should only
4120 be true when @code{reload_completed} is nonzero and the function's
4121 epilogue would only be a single instruction. For machines with register
4122 windows, the routine @code{leaf_function_p} may be used to determine if
4123 a register window push is required.
4125 Machines that have conditional return instructions should define patterns
4131 (if_then_else (match_operator
4132 0 "comparison_operator"
4133 [(cc0) (const_int 0)])
4140 where @var{condition} would normally be the same condition specified on the
4141 named @samp{return} pattern.
4143 @cindex @code{untyped_return} instruction pattern
4144 @item @samp{untyped_return}
4145 Untyped subroutine return instruction. This instruction pattern should
4146 be defined to support @code{__builtin_return} on machines where special
4147 instructions are needed to return a value of any type.
4149 Operand 0 is a memory location where the result of calling a function
4150 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
4151 expression where each element is a @code{set} expression that indicates
4152 the restoring of a function return value from the result block.
4154 @cindex @code{nop} instruction pattern
4156 No-op instruction. This instruction pattern name should always be defined
4157 to output a no-op in assembler code. @code{(const_int 0)} will do as an
4160 @cindex @code{indirect_jump} instruction pattern
4161 @item @samp{indirect_jump}
4162 An instruction to jump to an address which is operand zero.
4163 This pattern name is mandatory on all machines.
4165 @cindex @code{casesi} instruction pattern
4167 Instruction to jump through a dispatch table, including bounds checking.
4168 This instruction takes five operands:
4172 The index to dispatch on, which has mode @code{SImode}.
4175 The lower bound for indices in the table, an integer constant.
4178 The total range of indices in the table---the largest index
4179 minus the smallest one (both inclusive).
4182 A label that precedes the table itself.
4185 A label to jump to if the index has a value outside the bounds.
4188 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
4189 @code{jump_insn}. The number of elements in the table is one plus the
4190 difference between the upper bound and the lower bound.
4192 @cindex @code{tablejump} instruction pattern
4193 @item @samp{tablejump}
4194 Instruction to jump to a variable address. This is a low-level
4195 capability which can be used to implement a dispatch table when there
4196 is no @samp{casesi} pattern.
4198 This pattern requires two operands: the address or offset, and a label
4199 which should immediately precede the jump table. If the macro
4200 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
4201 operand is an offset which counts from the address of the table; otherwise,
4202 it is an absolute address to jump to. In either case, the first operand has
4205 The @samp{tablejump} insn is always the last insn before the jump
4206 table it uses. Its assembler code normally has no need to use the
4207 second operand, but you should incorporate it in the RTL pattern so
4208 that the jump optimizer will not delete the table as unreachable code.
4211 @cindex @code{decrement_and_branch_until_zero} instruction pattern
4212 @item @samp{decrement_and_branch_until_zero}
4213 Conditional branch instruction that decrements a register and
4214 jumps if the register is nonzero. Operand 0 is the register to
4215 decrement and test; operand 1 is the label to jump to if the
4216 register is nonzero. @xref{Looping Patterns}.
4218 This optional instruction pattern is only used by the combiner,
4219 typically for loops reversed by the loop optimizer when strength
4220 reduction is enabled.
4222 @cindex @code{doloop_end} instruction pattern
4223 @item @samp{doloop_end}
4224 Conditional branch instruction that decrements a register and jumps if
4225 the register is nonzero. This instruction takes five operands: Operand
4226 0 is the register to decrement and test; operand 1 is the number of loop
4227 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
4228 determined until run-time; operand 2 is the actual or estimated maximum
4229 number of iterations as a @code{const_int}; operand 3 is the number of
4230 enclosed loops as a @code{const_int} (an innermost loop has a value of
4231 1); operand 4 is the label to jump to if the register is nonzero.
4232 @xref{Looping Patterns}.
4234 This optional instruction pattern should be defined for machines with
4235 low-overhead looping instructions as the loop optimizer will try to
4236 modify suitable loops to utilize it. If nested low-overhead looping is
4237 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
4238 and make the pattern fail if operand 3 is not @code{const1_rtx}.
4239 Similarly, if the actual or estimated maximum number of iterations is
4240 too large for this instruction, make it fail.
4242 @cindex @code{doloop_begin} instruction pattern
4243 @item @samp{doloop_begin}
4244 Companion instruction to @code{doloop_end} required for machines that
4245 need to perform some initialization, such as loading special registers
4246 used by a low-overhead looping instruction. If initialization insns do
4247 not always need to be emitted, use a @code{define_expand}
4248 (@pxref{Expander Definitions}) and make it fail.
4251 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
4252 @item @samp{canonicalize_funcptr_for_compare}
4253 Canonicalize the function pointer in operand 1 and store the result
4256 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
4257 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
4258 and also has mode @code{Pmode}.
4260 Canonicalization of a function pointer usually involves computing
4261 the address of the function which would be called if the function
4262 pointer were used in an indirect call.
4264 Only define this pattern if function pointers on the target machine
4265 can have different values but still call the same function when
4266 used in an indirect call.
4268 @cindex @code{save_stack_block} instruction pattern
4269 @cindex @code{save_stack_function} instruction pattern
4270 @cindex @code{save_stack_nonlocal} instruction pattern
4271 @cindex @code{restore_stack_block} instruction pattern
4272 @cindex @code{restore_stack_function} instruction pattern
4273 @cindex @code{restore_stack_nonlocal} instruction pattern
4274 @item @samp{save_stack_block}
4275 @itemx @samp{save_stack_function}
4276 @itemx @samp{save_stack_nonlocal}
4277 @itemx @samp{restore_stack_block}
4278 @itemx @samp{restore_stack_function}
4279 @itemx @samp{restore_stack_nonlocal}
4280 Most machines save and restore the stack pointer by copying it to or
4281 from an object of mode @code{Pmode}. Do not define these patterns on
4284 Some machines require special handling for stack pointer saves and
4285 restores. On those machines, define the patterns corresponding to the
4286 non-standard cases by using a @code{define_expand} (@pxref{Expander
4287 Definitions}) that produces the required insns. The three types of
4288 saves and restores are:
4292 @samp{save_stack_block} saves the stack pointer at the start of a block
4293 that allocates a variable-sized object, and @samp{restore_stack_block}
4294 restores the stack pointer when the block is exited.
4297 @samp{save_stack_function} and @samp{restore_stack_function} do a
4298 similar job for the outermost block of a function and are used when the
4299 function allocates variable-sized objects or calls @code{alloca}. Only
4300 the epilogue uses the restored stack pointer, allowing a simpler save or
4301 restore sequence on some machines.
4304 @samp{save_stack_nonlocal} is used in functions that contain labels
4305 branched to by nested functions. It saves the stack pointer in such a
4306 way that the inner function can use @samp{restore_stack_nonlocal} to
4307 restore the stack pointer. The compiler generates code to restore the
4308 frame and argument pointer registers, but some machines require saving
4309 and restoring additional data such as register window information or
4310 stack backchains. Place insns in these patterns to save and restore any
4314 When saving the stack pointer, operand 0 is the save area and operand 1
4315 is the stack pointer. The mode used to allocate the save area defaults
4316 to @code{Pmode} but you can override that choice by defining the
4317 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
4318 specify an integral mode, or @code{VOIDmode} if no save area is needed
4319 for a particular type of save (either because no save is needed or
4320 because a machine-specific save area can be used). Operand 0 is the
4321 stack pointer and operand 1 is the save area for restore operations. If
4322 @samp{save_stack_block} is defined, operand 0 must not be
4323 @code{VOIDmode} since these saves can be arbitrarily nested.
4325 A save area is a @code{mem} that is at a constant offset from
4326 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
4327 nonlocal gotos and a @code{reg} in the other two cases.
4329 @cindex @code{allocate_stack} instruction pattern
4330 @item @samp{allocate_stack}
4331 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
4332 the stack pointer to create space for dynamically allocated data.
4334 Store the resultant pointer to this space into operand 0. If you
4335 are allocating space from the main stack, do this by emitting a
4336 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
4337 If you are allocating the space elsewhere, generate code to copy the
4338 location of the space to operand 0. In the latter case, you must
4339 ensure this space gets freed when the corresponding space on the main
4342 Do not define this pattern if all that must be done is the subtraction.
4343 Some machines require other operations such as stack probes or
4344 maintaining the back chain. Define this pattern to emit those
4345 operations in addition to updating the stack pointer.
4347 @cindex @code{check_stack} instruction pattern
4348 @item @samp{check_stack}
4349 If stack checking cannot be done on your system by probing the stack with
4350 a load or store instruction (@pxref{Stack Checking}), define this pattern
4351 to perform the needed check and signaling an error if the stack
4352 has overflowed. The single operand is the location in the stack furthest
4353 from the current stack pointer that you need to validate. Normally,
4354 on machines where this pattern is needed, you would obtain the stack
4355 limit from a global or thread-specific variable or register.
4357 @cindex @code{nonlocal_goto} instruction pattern
4358 @item @samp{nonlocal_goto}
4359 Emit code to generate a non-local goto, e.g., a jump from one function
4360 to a label in an outer function. This pattern has four arguments,
4361 each representing a value to be used in the jump. The first
4362 argument is to be loaded into the frame pointer, the second is
4363 the address to branch to (code to dispatch to the actual label),
4364 the third is the address of a location where the stack is saved,
4365 and the last is the address of the label, to be placed in the
4366 location for the incoming static chain.
4368 On most machines you need not define this pattern, since GCC will
4369 already generate the correct code, which is to load the frame pointer
4370 and static chain, restore the stack (using the
4371 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
4372 to the dispatcher. You need only define this pattern if this code will
4373 not work on your machine.
4375 @cindex @code{nonlocal_goto_receiver} instruction pattern
4376 @item @samp{nonlocal_goto_receiver}
4377 This pattern, if defined, contains code needed at the target of a
4378 nonlocal goto after the code already generated by GCC@. You will not
4379 normally need to define this pattern. A typical reason why you might
4380 need this pattern is if some value, such as a pointer to a global table,
4381 must be restored when the frame pointer is restored. Note that a nonlocal
4382 goto only occurs within a unit-of-translation, so a global table pointer
4383 that is shared by all functions of a given module need not be restored.
4384 There are no arguments.
4386 @cindex @code{exception_receiver} instruction pattern
4387 @item @samp{exception_receiver}
4388 This pattern, if defined, contains code needed at the site of an
4389 exception handler that isn't needed at the site of a nonlocal goto. You
4390 will not normally need to define this pattern. A typical reason why you
4391 might need this pattern is if some value, such as a pointer to a global
4392 table, must be restored after control flow is branched to the handler of
4393 an exception. There are no arguments.
4395 @cindex @code{builtin_setjmp_setup} instruction pattern
4396 @item @samp{builtin_setjmp_setup}
4397 This pattern, if defined, contains additional code needed to initialize
4398 the @code{jmp_buf}. You will not normally need to define this pattern.
4399 A typical reason why you might need this pattern is if some value, such
4400 as a pointer to a global table, must be restored. Though it is
4401 preferred that the pointer value be recalculated if possible (given the
4402 address of a label for instance). The single argument is a pointer to
4403 the @code{jmp_buf}. Note that the buffer is five words long and that
4404 the first three are normally used by the generic mechanism.
4406 @cindex @code{builtin_setjmp_receiver} instruction pattern
4407 @item @samp{builtin_setjmp_receiver}
4408 This pattern, if defined, contains code needed at the site of an
4409 built-in setjmp that isn't needed at the site of a nonlocal goto. You
4410 will not normally need to define this pattern. A typical reason why you
4411 might need this pattern is if some value, such as a pointer to a global
4412 table, must be restored. It takes one argument, which is the label
4413 to which builtin_longjmp transfered control; this pattern may be emitted
4414 at a small offset from that label.
4416 @cindex @code{builtin_longjmp} instruction pattern
4417 @item @samp{builtin_longjmp}
4418 This pattern, if defined, performs the entire action of the longjmp.
4419 You will not normally need to define this pattern unless you also define
4420 @code{builtin_setjmp_setup}. The single argument is a pointer to the
4423 @cindex @code{eh_return} instruction pattern
4424 @item @samp{eh_return}
4425 This pattern, if defined, affects the way @code{__builtin_eh_return},
4426 and thence the call frame exception handling library routines, are
4427 built. It is intended to handle non-trivial actions needed along
4428 the abnormal return path.
4430 The address of the exception handler to which the function should return
4431 is passed as operand to this pattern. It will normally need to copied by
4432 the pattern to some special register or memory location.
4433 If the pattern needs to determine the location of the target call
4434 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
4435 if defined; it will have already been assigned.
4437 If this pattern is not defined, the default action will be to simply
4438 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
4439 that macro or this pattern needs to be defined if call frame exception
4440 handling is to be used.
4442 @cindex @code{prologue} instruction pattern
4443 @anchor{prologue instruction pattern}
4444 @item @samp{prologue}
4445 This pattern, if defined, emits RTL for entry to a function. The function
4446 entry is responsible for setting up the stack frame, initializing the frame
4447 pointer register, saving callee saved registers, etc.
4449 Using a prologue pattern is generally preferred over defining
4450 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
4452 The @code{prologue} pattern is particularly useful for targets which perform
4453 instruction scheduling.
4455 @cindex @code{epilogue} instruction pattern
4456 @anchor{epilogue instruction pattern}
4457 @item @samp{epilogue}
4458 This pattern emits RTL for exit from a function. The function
4459 exit is responsible for deallocating the stack frame, restoring callee saved
4460 registers and emitting the return instruction.
4462 Using an epilogue pattern is generally preferred over defining
4463 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
4465 The @code{epilogue} pattern is particularly useful for targets which perform
4466 instruction scheduling or which have delay slots for their return instruction.
4468 @cindex @code{sibcall_epilogue} instruction pattern
4469 @item @samp{sibcall_epilogue}
4470 This pattern, if defined, emits RTL for exit from a function without the final
4471 branch back to the calling function. This pattern will be emitted before any
4472 sibling call (aka tail call) sites.
4474 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
4475 parameter passing or any stack slots for arguments passed to the current
4478 @cindex @code{trap} instruction pattern
4480 This pattern, if defined, signals an error, typically by causing some
4481 kind of signal to be raised. Among other places, it is used by the Java
4482 front end to signal `invalid array index' exceptions.
4484 @cindex @code{conditional_trap} instruction pattern
4485 @item @samp{conditional_trap}
4486 Conditional trap instruction. Operand 0 is a piece of RTL which
4487 performs a comparison. Operand 1 is the trap code, an integer.
4489 A typical @code{conditional_trap} pattern looks like
4492 (define_insn "conditional_trap"
4493 [(trap_if (match_operator 0 "trap_operator"
4494 [(cc0) (const_int 0)])
4495 (match_operand 1 "const_int_operand" "i"))]
4500 @cindex @code{prefetch} instruction pattern
4501 @item @samp{prefetch}
4503 This pattern, if defined, emits code for a non-faulting data prefetch
4504 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
4505 is a constant 1 if the prefetch is preparing for a write to the memory
4506 address, or a constant 0 otherwise. Operand 2 is the expected degree of
4507 temporal locality of the data and is a value between 0 and 3, inclusive; 0
4508 means that the data has no temporal locality, so it need not be left in the
4509 cache after the access; 3 means that the data has a high degree of temporal
4510 locality and should be left in all levels of cache possible; 1 and 2 mean,
4511 respectively, a low or moderate degree of temporal locality.
4513 Targets that do not support write prefetches or locality hints can ignore
4514 the values of operands 1 and 2.
4516 @cindex @code{memory_barrier} instruction pattern
4517 @item @samp{memory_barrier}
4519 If the target memory model is not fully synchronous, then this pattern
4520 should be defined to an instruction that orders both loads and stores
4521 before the instruction with respect to loads and stores after the instruction.
4522 This pattern has no operands.
4524 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
4525 @item @samp{sync_compare_and_swap@var{mode}}
4527 This pattern, if defined, emits code for an atomic compare-and-swap
4528 operation. Operand 1 is the memory on which the atomic operation is
4529 performed. Operand 2 is the ``old'' value to be compared against the
4530 current contents of the memory location. Operand 3 is the ``new'' value
4531 to store in the memory if the compare succeeds. Operand 0 is the result
4532 of the operation; it should contain the contents of the memory
4533 before the operation. If the compare succeeds, this should obviously be
4534 a copy of operand 2.
4536 This pattern must show that both operand 0 and operand 1 are modified.
4538 This pattern must issue any memory barrier instructions such that all
4539 memory operations before the atomic operation occur before the atomic
4540 operation and all memory operations after the atomic operation occur
4541 after the atomic operation.
4543 @cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern
4544 @item @samp{sync_compare_and_swap_cc@var{mode}}
4546 This pattern is just like @code{sync_compare_and_swap@var{mode}}, except
4547 it should act as if compare part of the compare-and-swap were issued via
4548 @code{cmp@var{m}}. This comparison will only be used with @code{EQ} and
4549 @code{NE} branches and @code{setcc} operations.
4551 Some targets do expose the success or failure of the compare-and-swap
4552 operation via the status flags. Ideally we wouldn't need a separate
4553 named pattern in order to take advantage of this, but the combine pass
4554 does not handle patterns with multiple sets, which is required by
4555 definition for @code{sync_compare_and_swap@var{mode}}.
4557 @cindex @code{sync_add@var{mode}} instruction pattern
4558 @cindex @code{sync_sub@var{mode}} instruction pattern
4559 @cindex @code{sync_ior@var{mode}} instruction pattern
4560 @cindex @code{sync_and@var{mode}} instruction pattern
4561 @cindex @code{sync_xor@var{mode}} instruction pattern
4562 @cindex @code{sync_nand@var{mode}} instruction pattern
4563 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
4564 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
4565 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
4567 These patterns emit code for an atomic operation on memory.
4568 Operand 0 is the memory on which the atomic operation is performed.
4569 Operand 1 is the second operand to the binary operator.
4571 The ``nand'' operation is @code{~op0 & op1}.
4573 This pattern must issue any memory barrier instructions such that all
4574 memory operations before the atomic operation occur before the atomic
4575 operation and all memory operations after the atomic operation occur
4576 after the atomic operation.
4578 If these patterns are not defined, the operation will be constructed
4579 from a compare-and-swap operation, if defined.
4581 @cindex @code{sync_old_add@var{mode}} instruction pattern
4582 @cindex @code{sync_old_sub@var{mode}} instruction pattern
4583 @cindex @code{sync_old_ior@var{mode}} instruction pattern
4584 @cindex @code{sync_old_and@var{mode}} instruction pattern
4585 @cindex @code{sync_old_xor@var{mode}} instruction pattern
4586 @cindex @code{sync_old_nand@var{mode}} instruction pattern
4587 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
4588 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
4589 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
4591 These patterns are emit code for an atomic operation on memory,
4592 and return the value that the memory contained before the operation.
4593 Operand 0 is the result value, operand 1 is the memory on which the
4594 atomic operation is performed, and operand 2 is the second operand
4595 to the binary operator.
4597 This pattern must issue any memory barrier instructions such that all
4598 memory operations before the atomic operation occur before the atomic
4599 operation and all memory operations after the atomic operation occur
4600 after the atomic operation.
4602 If these patterns are not defined, the operation will be constructed
4603 from a compare-and-swap operation, if defined.
4605 @cindex @code{sync_new_add@var{mode}} instruction pattern
4606 @cindex @code{sync_new_sub@var{mode}} instruction pattern
4607 @cindex @code{sync_new_ior@var{mode}} instruction pattern
4608 @cindex @code{sync_new_and@var{mode}} instruction pattern
4609 @cindex @code{sync_new_xor@var{mode}} instruction pattern
4610 @cindex @code{sync_new_nand@var{mode}} instruction pattern
4611 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
4612 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
4613 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
4615 These patterns are like their @code{sync_old_@var{op}} counterparts,
4616 except that they return the value that exists in the memory location
4617 after the operation, rather than before the operation.
4619 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
4620 @item @samp{sync_lock_test_and_set@var{mode}}
4622 This pattern takes two forms, based on the capabilities of the target.
4623 In either case, operand 0 is the result of the operand, operand 1 is
4624 the memory on which the atomic operation is performed, and operand 2
4625 is the value to set in the lock.
4627 In the ideal case, this operation is an atomic exchange operation, in
4628 which the previous value in memory operand is copied into the result
4629 operand, and the value operand is stored in the memory operand.
4631 For less capable targets, any value operand that is not the constant 1
4632 should be rejected with @code{FAIL}. In this case the target may use
4633 an atomic test-and-set bit operation. The result operand should contain
4634 1 if the bit was previously set and 0 if the bit was previously clear.
4635 The true contents of the memory operand are implementation defined.
4637 This pattern must issue any memory barrier instructions such that the
4638 pattern as a whole acts as an acquire barrier, that is all memory
4639 operations after the pattern do not occur until the lock is acquired.
4641 If this pattern is not defined, the operation will be constructed from
4642 a compare-and-swap operation, if defined.
4644 @cindex @code{sync_lock_release@var{mode}} instruction pattern
4645 @item @samp{sync_lock_release@var{mode}}
4647 This pattern, if defined, releases a lock set by
4648 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
4649 that contains the lock; operand 1 is the value to store in the lock.
4651 If the target doesn't implement full semantics for
4652 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
4653 the constant 0 should be rejected with @code{FAIL}, and the true contents
4654 of the memory operand are implementation defined.
4656 This pattern must issue any memory barrier instructions such that the
4657 pattern as a whole acts as a release barrier, that is the lock is
4658 released only after all previous memory operations have completed.
4660 If this pattern is not defined, then a @code{memory_barrier} pattern
4661 will be emitted, followed by a store of the value to the memory operand.
4663 @cindex @code{stack_protect_set} instruction pattern
4664 @item @samp{stack_protect_set}
4666 This pattern, if defined, moves a @code{Pmode} value from the memory
4667 in operand 1 to the memory in operand 0 without leaving the value in
4668 a register afterward. This is to avoid leaking the value some place
4669 that an attacker might use to rewrite the stack guard slot after
4670 having clobbered it.
4672 If this pattern is not defined, then a plain move pattern is generated.
4674 @cindex @code{stack_protect_test} instruction pattern
4675 @item @samp{stack_protect_test}
4677 This pattern, if defined, compares a @code{Pmode} value from the
4678 memory in operand 1 with the memory in operand 0 without leaving the
4679 value in a register afterward and branches to operand 2 if the values
4682 If this pattern is not defined, then a plain compare pattern and
4683 conditional branch pattern is used.
4688 @c Each of the following nodes are wrapped in separate
4689 @c "@ifset INTERNALS" to work around memory limits for the default
4690 @c configuration in older tetex distributions. Known to not work:
4691 @c tetex-1.0.7, known to work: tetex-2.0.2.
4693 @node Pattern Ordering
4694 @section When the Order of Patterns Matters
4695 @cindex Pattern Ordering
4696 @cindex Ordering of Patterns
4698 Sometimes an insn can match more than one instruction pattern. Then the
4699 pattern that appears first in the machine description is the one used.
4700 Therefore, more specific patterns (patterns that will match fewer things)
4701 and faster instructions (those that will produce better code when they
4702 do match) should usually go first in the description.
4704 In some cases the effect of ordering the patterns can be used to hide
4705 a pattern when it is not valid. For example, the 68000 has an
4706 instruction for converting a fullword to floating point and another
4707 for converting a byte to floating point. An instruction converting
4708 an integer to floating point could match either one. We put the
4709 pattern to convert the fullword first to make sure that one will
4710 be used rather than the other. (Otherwise a large integer might
4711 be generated as a single-byte immediate quantity, which would not work.)
4712 Instead of using this pattern ordering it would be possible to make the
4713 pattern for convert-a-byte smart enough to deal properly with any
4718 @node Dependent Patterns
4719 @section Interdependence of Patterns
4720 @cindex Dependent Patterns
4721 @cindex Interdependence of Patterns
4723 Every machine description must have a named pattern for each of the
4724 conditional branch names @samp{b@var{cond}}. The recognition template
4725 must always have the form
4729 (if_then_else (@var{cond} (cc0) (const_int 0))
4730 (label_ref (match_operand 0 "" ""))
4735 In addition, every machine description must have an anonymous pattern
4736 for each of the possible reverse-conditional branches. Their templates
4741 (if_then_else (@var{cond} (cc0) (const_int 0))
4743 (label_ref (match_operand 0 "" ""))))
4747 They are necessary because jump optimization can turn direct-conditional
4748 branches into reverse-conditional branches.
4750 It is often convenient to use the @code{match_operator} construct to
4751 reduce the number of patterns that must be specified for branches. For
4757 (if_then_else (match_operator 0 "comparison_operator"
4758 [(cc0) (const_int 0)])
4760 (label_ref (match_operand 1 "" ""))))]
4765 In some cases machines support instructions identical except for the
4766 machine mode of one or more operands. For example, there may be
4767 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
4771 (set (match_operand:SI 0 @dots{})
4772 (extend:SI (match_operand:HI 1 @dots{})))
4774 (set (match_operand:SI 0 @dots{})
4775 (extend:SI (match_operand:QI 1 @dots{})))
4779 Constant integers do not specify a machine mode, so an instruction to
4780 extend a constant value could match either pattern. The pattern it
4781 actually will match is the one that appears first in the file. For correct
4782 results, this must be the one for the widest possible mode (@code{HImode},
4783 here). If the pattern matches the @code{QImode} instruction, the results
4784 will be incorrect if the constant value does not actually fit that mode.
4786 Such instructions to extend constants are rarely generated because they are
4787 optimized away, but they do occasionally happen in nonoptimized
4790 If a constraint in a pattern allows a constant, the reload pass may
4791 replace a register with a constant permitted by the constraint in some
4792 cases. Similarly for memory references. Because of this substitution,
4793 you should not provide separate patterns for increment and decrement
4794 instructions. Instead, they should be generated from the same pattern
4795 that supports register-register add insns by examining the operands and
4796 generating the appropriate machine instruction.
4801 @section Defining Jump Instruction Patterns
4802 @cindex jump instruction patterns
4803 @cindex defining jump instruction patterns
4805 For most machines, GCC assumes that the machine has a condition code.
4806 A comparison insn sets the condition code, recording the results of both
4807 signed and unsigned comparison of the given operands. A separate branch
4808 insn tests the condition code and branches or not according its value.
4809 The branch insns come in distinct signed and unsigned flavors. Many
4810 common machines, such as the VAX, the 68000 and the 32000, work this
4813 Some machines have distinct signed and unsigned compare instructions, and
4814 only one set of conditional branch instructions. The easiest way to handle
4815 these machines is to treat them just like the others until the final stage
4816 where assembly code is written. At this time, when outputting code for the
4817 compare instruction, peek ahead at the following branch using
4818 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
4819 being output, in the output-writing code in an instruction pattern.) If
4820 the RTL says that is an unsigned branch, output an unsigned compare;
4821 otherwise output a signed compare. When the branch itself is output, you
4822 can treat signed and unsigned branches identically.
4824 The reason you can do this is that GCC always generates a pair of
4825 consecutive RTL insns, possibly separated by @code{note} insns, one to
4826 set the condition code and one to test it, and keeps the pair inviolate
4829 To go with this technique, you must define the machine-description macro
4830 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
4831 compare instruction is superfluous.
4833 Some machines have compare-and-branch instructions and no condition code.
4834 A similar technique works for them. When it is time to ``output'' a
4835 compare instruction, record its operands in two static variables. When
4836 outputting the branch-on-condition-code instruction that follows, actually
4837 output a compare-and-branch instruction that uses the remembered operands.
4839 It also works to define patterns for compare-and-branch instructions.
4840 In optimizing compilation, the pair of compare and branch instructions
4841 will be combined according to these patterns. But this does not happen
4842 if optimization is not requested. So you must use one of the solutions
4843 above in addition to any special patterns you define.
4845 In many RISC machines, most instructions do not affect the condition
4846 code and there may not even be a separate condition code register. On
4847 these machines, the restriction that the definition and use of the
4848 condition code be adjacent insns is not necessary and can prevent
4849 important optimizations. For example, on the IBM RS/6000, there is a
4850 delay for taken branches unless the condition code register is set three
4851 instructions earlier than the conditional branch. The instruction
4852 scheduler cannot perform this optimization if it is not permitted to
4853 separate the definition and use of the condition code register.
4855 On these machines, do not use @code{(cc0)}, but instead use a register
4856 to represent the condition code. If there is a specific condition code
4857 register in the machine, use a hard register. If the condition code or
4858 comparison result can be placed in any general register, or if there are
4859 multiple condition registers, use a pseudo register.
4861 @findex prev_cc0_setter
4862 @findex next_cc0_user
4863 On some machines, the type of branch instruction generated may depend on
4864 the way the condition code was produced; for example, on the 68k and
4865 SPARC, setting the condition code directly from an add or subtract
4866 instruction does not clear the overflow bit the way that a test
4867 instruction does, so a different branch instruction must be used for
4868 some conditional branches. For machines that use @code{(cc0)}, the set
4869 and use of the condition code must be adjacent (separated only by
4870 @code{note} insns) allowing flags in @code{cc_status} to be used.
4871 (@xref{Condition Code}.) Also, the comparison and branch insns can be
4872 located from each other by using the functions @code{prev_cc0_setter}
4873 and @code{next_cc0_user}.
4875 However, this is not true on machines that do not use @code{(cc0)}. On
4876 those machines, no assumptions can be made about the adjacency of the
4877 compare and branch insns and the above methods cannot be used. Instead,
4878 we use the machine mode of the condition code register to record
4879 different formats of the condition code register.
4881 Registers used to store the condition code value should have a mode that
4882 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
4883 additional modes are required (as for the add example mentioned above in
4884 the SPARC), define them in @file{@var{machine}-modes.def}
4885 (@pxref{Condition Code}). Also define @code{SELECT_CC_MODE} to choose
4886 a mode given an operand of a compare.
4888 If it is known during RTL generation that a different mode will be
4889 required (for example, if the machine has separate compare instructions
4890 for signed and unsigned quantities, like most IBM processors), they can
4891 be specified at that time.
4893 If the cases that require different modes would be made by instruction
4894 combination, the macro @code{SELECT_CC_MODE} determines which machine
4895 mode should be used for the comparison result. The patterns should be
4896 written using that mode. To support the case of the add on the SPARC
4897 discussed above, we have the pattern
4901 [(set (reg:CC_NOOV 0)
4903 (plus:SI (match_operand:SI 0 "register_operand" "%r")
4904 (match_operand:SI 1 "arith_operand" "rI"))
4910 The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
4911 for comparisons whose argument is a @code{plus}.
4915 @node Looping Patterns
4916 @section Defining Looping Instruction Patterns
4917 @cindex looping instruction patterns
4918 @cindex defining looping instruction patterns
4920 Some machines have special jump instructions that can be utilized to
4921 make loops more efficient. A common example is the 68000 @samp{dbra}
4922 instruction which performs a decrement of a register and a branch if the
4923 result was greater than zero. Other machines, in particular digital
4924 signal processors (DSPs), have special block repeat instructions to
4925 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
4926 DSPs have a block repeat instruction that loads special registers to
4927 mark the top and end of a loop and to count the number of loop
4928 iterations. This avoids the need for fetching and executing a
4929 @samp{dbra}-like instruction and avoids pipeline stalls associated with
4932 GCC has three special named patterns to support low overhead looping.
4933 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
4934 and @samp{doloop_end}. The first pattern,
4935 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
4936 generation but may be emitted during the instruction combination phase.
4937 This requires the assistance of the loop optimizer, using information
4938 collected during strength reduction, to reverse a loop to count down to
4939 zero. Some targets also require the loop optimizer to add a
4940 @code{REG_NONNEG} note to indicate that the iteration count is always
4941 positive. This is needed if the target performs a signed loop
4942 termination test. For example, the 68000 uses a pattern similar to the
4943 following for its @code{dbra} instruction:
4947 (define_insn "decrement_and_branch_until_zero"
4950 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
4953 (label_ref (match_operand 1 "" ""))
4956 (plus:SI (match_dup 0)
4958 "find_reg_note (insn, REG_NONNEG, 0)"
4963 Note that since the insn is both a jump insn and has an output, it must
4964 deal with its own reloads, hence the `m' constraints. Also note that
4965 since this insn is generated by the instruction combination phase
4966 combining two sequential insns together into an implicit parallel insn,
4967 the iteration counter needs to be biased by the same amount as the
4968 decrement operation, in this case @minus{}1. Note that the following similar
4969 pattern will not be matched by the combiner.
4973 (define_insn "decrement_and_branch_until_zero"
4976 (ge (match_operand:SI 0 "general_operand" "+d*am")
4978 (label_ref (match_operand 1 "" ""))
4981 (plus:SI (match_dup 0)
4983 "find_reg_note (insn, REG_NONNEG, 0)"
4988 The other two special looping patterns, @samp{doloop_begin} and
4989 @samp{doloop_end}, are emitted by the loop optimizer for certain
4990 well-behaved loops with a finite number of loop iterations using
4991 information collected during strength reduction.
4993 The @samp{doloop_end} pattern describes the actual looping instruction
4994 (or the implicit looping operation) and the @samp{doloop_begin} pattern
4995 is an optional companion pattern that can be used for initialization
4996 needed for some low-overhead looping instructions.
4998 Note that some machines require the actual looping instruction to be
4999 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
5000 the true RTL for a looping instruction at the top of the loop can cause
5001 problems with flow analysis. So instead, a dummy @code{doloop} insn is
5002 emitted at the end of the loop. The machine dependent reorg pass checks
5003 for the presence of this @code{doloop} insn and then searches back to
5004 the top of the loop, where it inserts the true looping insn (provided
5005 there are no instructions in the loop which would cause problems). Any
5006 additional labels can be emitted at this point. In addition, if the
5007 desired special iteration counter register was not allocated, this
5008 machine dependent reorg pass could emit a traditional compare and jump
5011 The essential difference between the
5012 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
5013 patterns is that the loop optimizer allocates an additional pseudo
5014 register for the latter as an iteration counter. This pseudo register
5015 cannot be used within the loop (i.e., general induction variables cannot
5016 be derived from it), however, in many cases the loop induction variable
5017 may become redundant and removed by the flow pass.
5022 @node Insn Canonicalizations
5023 @section Canonicalization of Instructions
5024 @cindex canonicalization of instructions
5025 @cindex insn canonicalization
5027 There are often cases where multiple RTL expressions could represent an
5028 operation performed by a single machine instruction. This situation is
5029 most commonly encountered with logical, branch, and multiply-accumulate
5030 instructions. In such cases, the compiler attempts to convert these
5031 multiple RTL expressions into a single canonical form to reduce the
5032 number of insn patterns required.
5034 In addition to algebraic simplifications, following canonicalizations
5039 For commutative and comparison operators, a constant is always made the
5040 second operand. If a machine only supports a constant as the second
5041 operand, only patterns that match a constant in the second operand need
5045 For associative operators, a sequence of operators will always chain
5046 to the left; for instance, only the left operand of an integer @code{plus}
5047 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
5048 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
5049 @code{umax} are associative when applied to integers, and sometimes to
5053 @cindex @code{neg}, canonicalization of
5054 @cindex @code{not}, canonicalization of
5055 @cindex @code{mult}, canonicalization of
5056 @cindex @code{plus}, canonicalization of
5057 @cindex @code{minus}, canonicalization of
5058 For these operators, if only one operand is a @code{neg}, @code{not},
5059 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
5063 In combinations of @code{neg}, @code{mult}, @code{plus}, and
5064 @code{minus}, the @code{neg} operations (if any) will be moved inside
5065 the operations as far as possible. For instance,
5066 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
5067 @code{(plus (mult (neg A) B) C)} is canonicalized as
5068 @code{(minus A (mult B C))}.
5070 @cindex @code{compare}, canonicalization of
5072 For the @code{compare} operator, a constant is always the second operand
5073 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
5074 machines, there are rare cases where the compiler might want to construct
5075 a @code{compare} with a constant as the first operand. However, these
5076 cases are not common enough for it to be worthwhile to provide a pattern
5077 matching a constant as the first operand unless the machine actually has
5078 such an instruction.
5080 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
5081 @code{minus} is made the first operand under the same conditions as
5085 @code{(minus @var{x} (const_int @var{n}))} is converted to
5086 @code{(plus @var{x} (const_int @var{-n}))}.
5089 Within address computations (i.e., inside @code{mem}), a left shift is
5090 converted into the appropriate multiplication by a power of two.
5092 @cindex @code{ior}, canonicalization of
5093 @cindex @code{and}, canonicalization of
5094 @cindex De Morgan's law
5096 De Morgan's Law is used to move bitwise negation inside a bitwise
5097 logical-and or logical-or operation. If this results in only one
5098 operand being a @code{not} expression, it will be the first one.
5100 A machine that has an instruction that performs a bitwise logical-and of one
5101 operand with the bitwise negation of the other should specify the pattern
5102 for that instruction as
5106 [(set (match_operand:@var{m} 0 @dots{})
5107 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5108 (match_operand:@var{m} 2 @dots{})))]
5114 Similarly, a pattern for a ``NAND'' instruction should be written
5118 [(set (match_operand:@var{m} 0 @dots{})
5119 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
5120 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
5125 In both cases, it is not necessary to include patterns for the many
5126 logically equivalent RTL expressions.
5128 @cindex @code{xor}, canonicalization of
5130 The only possible RTL expressions involving both bitwise exclusive-or
5131 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
5132 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
5135 The sum of three items, one of which is a constant, will only appear in
5139 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
5143 On machines that do not use @code{cc0},
5144 @code{(compare @var{x} (const_int 0))} will be converted to
5147 @cindex @code{zero_extract}, canonicalization of
5148 @cindex @code{sign_extract}, canonicalization of
5150 Equality comparisons of a group of bits (usually a single bit) with zero
5151 will be written using @code{zero_extract} rather than the equivalent
5152 @code{and} or @code{sign_extract} operations.
5156 Further canonicalization rules are defined in the function
5157 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
5161 @node Expander Definitions
5162 @section Defining RTL Sequences for Code Generation
5163 @cindex expander definitions
5164 @cindex code generation RTL sequences
5165 @cindex defining RTL sequences for code generation
5167 On some target machines, some standard pattern names for RTL generation
5168 cannot be handled with single insn, but a sequence of RTL insns can
5169 represent them. For these target machines, you can write a
5170 @code{define_expand} to specify how to generate the sequence of RTL@.
5172 @findex define_expand
5173 A @code{define_expand} is an RTL expression that looks almost like a
5174 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
5175 only for RTL generation and it can produce more than one RTL insn.
5177 A @code{define_expand} RTX has four operands:
5181 The name. Each @code{define_expand} must have a name, since the only
5182 use for it is to refer to it by name.
5185 The RTL template. This is a vector of RTL expressions representing
5186 a sequence of separate instructions. Unlike @code{define_insn}, there
5187 is no implicit surrounding @code{PARALLEL}.
5190 The condition, a string containing a C expression. This expression is
5191 used to express how the availability of this pattern depends on
5192 subclasses of target machine, selected by command-line options when GCC
5193 is run. This is just like the condition of a @code{define_insn} that
5194 has a standard name. Therefore, the condition (if present) may not
5195 depend on the data in the insn being matched, but only the
5196 target-machine-type flags. The compiler needs to test these conditions
5197 during initialization in order to learn exactly which named instructions
5198 are available in a particular run.
5201 The preparation statements, a string containing zero or more C
5202 statements which are to be executed before RTL code is generated from
5205 Usually these statements prepare temporary registers for use as
5206 internal operands in the RTL template, but they can also generate RTL
5207 insns directly by calling routines such as @code{emit_insn}, etc.
5208 Any such insns precede the ones that come from the RTL template.
5211 Every RTL insn emitted by a @code{define_expand} must match some
5212 @code{define_insn} in the machine description. Otherwise, the compiler
5213 will crash when trying to generate code for the insn or trying to optimize
5216 The RTL template, in addition to controlling generation of RTL insns,
5217 also describes the operands that need to be specified when this pattern
5218 is used. In particular, it gives a predicate for each operand.
5220 A true operand, which needs to be specified in order to generate RTL from
5221 the pattern, should be described with a @code{match_operand} in its first
5222 occurrence in the RTL template. This enters information on the operand's
5223 predicate into the tables that record such things. GCC uses the
5224 information to preload the operand into a register if that is required for
5225 valid RTL code. If the operand is referred to more than once, subsequent
5226 references should use @code{match_dup}.
5228 The RTL template may also refer to internal ``operands'' which are
5229 temporary registers or labels used only within the sequence made by the
5230 @code{define_expand}. Internal operands are substituted into the RTL
5231 template with @code{match_dup}, never with @code{match_operand}. The
5232 values of the internal operands are not passed in as arguments by the
5233 compiler when it requests use of this pattern. Instead, they are computed
5234 within the pattern, in the preparation statements. These statements
5235 compute the values and store them into the appropriate elements of
5236 @code{operands} so that @code{match_dup} can find them.
5238 There are two special macros defined for use in the preparation statements:
5239 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
5246 Use the @code{DONE} macro to end RTL generation for the pattern. The
5247 only RTL insns resulting from the pattern on this occasion will be
5248 those already emitted by explicit calls to @code{emit_insn} within the
5249 preparation statements; the RTL template will not be generated.
5253 Make the pattern fail on this occasion. When a pattern fails, it means
5254 that the pattern was not truly available. The calling routines in the
5255 compiler will try other strategies for code generation using other patterns.
5257 Failure is currently supported only for binary (addition, multiplication,
5258 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
5262 If the preparation falls through (invokes neither @code{DONE} nor
5263 @code{FAIL}), then the @code{define_expand} acts like a
5264 @code{define_insn} in that the RTL template is used to generate the
5267 The RTL template is not used for matching, only for generating the
5268 initial insn list. If the preparation statement always invokes
5269 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
5270 list of operands, such as this example:
5274 (define_expand "addsi3"
5275 [(match_operand:SI 0 "register_operand" "")
5276 (match_operand:SI 1 "register_operand" "")
5277 (match_operand:SI 2 "register_operand" "")]
5283 handle_add (operands[0], operands[1], operands[2]);
5289 Here is an example, the definition of left-shift for the SPUR chip:
5293 (define_expand "ashlsi3"
5294 [(set (match_operand:SI 0 "register_operand" "")
5298 (match_operand:SI 1 "register_operand" "")
5299 (match_operand:SI 2 "nonmemory_operand" "")))]
5308 if (GET_CODE (operands[2]) != CONST_INT
5309 || (unsigned) INTVAL (operands[2]) > 3)
5316 This example uses @code{define_expand} so that it can generate an RTL insn
5317 for shifting when the shift-count is in the supported range of 0 to 3 but
5318 fail in other cases where machine insns aren't available. When it fails,
5319 the compiler tries another strategy using different patterns (such as, a
5322 If the compiler were able to handle nontrivial condition-strings in
5323 patterns with names, then it would be possible to use a
5324 @code{define_insn} in that case. Here is another case (zero-extension
5325 on the 68000) which makes more use of the power of @code{define_expand}:
5328 (define_expand "zero_extendhisi2"
5329 [(set (match_operand:SI 0 "general_operand" "")
5331 (set (strict_low_part
5335 (match_operand:HI 1 "general_operand" ""))]
5337 "operands[1] = make_safe_from (operands[1], operands[0]);")
5341 @findex make_safe_from
5342 Here two RTL insns are generated, one to clear the entire output operand
5343 and the other to copy the input operand into its low half. This sequence
5344 is incorrect if the input operand refers to [the old value of] the output
5345 operand, so the preparation statement makes sure this isn't so. The
5346 function @code{make_safe_from} copies the @code{operands[1]} into a
5347 temporary register if it refers to @code{operands[0]}. It does this
5348 by emitting another RTL insn.
5350 Finally, a third example shows the use of an internal operand.
5351 Zero-extension on the SPUR chip is done by @code{and}-ing the result
5352 against a halfword mask. But this mask cannot be represented by a
5353 @code{const_int} because the constant value is too large to be legitimate
5354 on this machine. So it must be copied into a register with
5355 @code{force_reg} and then the register used in the @code{and}.
5358 (define_expand "zero_extendhisi2"
5359 [(set (match_operand:SI 0 "register_operand" "")
5361 (match_operand:HI 1 "register_operand" "")
5366 = force_reg (SImode, GEN_INT (65535)); ")
5369 @emph{Note:} If the @code{define_expand} is used to serve a
5370 standard binary or unary arithmetic operation or a bit-field operation,
5371 then the last insn it generates must not be a @code{code_label},
5372 @code{barrier} or @code{note}. It must be an @code{insn},
5373 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
5374 at the end, emit an insn to copy the result of the operation into
5375 itself. Such an insn will generate no code, but it can avoid problems
5380 @node Insn Splitting
5381 @section Defining How to Split Instructions
5382 @cindex insn splitting
5383 @cindex instruction splitting
5384 @cindex splitting instructions
5386 There are two cases where you should specify how to split a pattern
5387 into multiple insns. On machines that have instructions requiring
5388 delay slots (@pxref{Delay Slots}) or that have instructions whose
5389 output is not available for multiple cycles (@pxref{Processor pipeline
5390 description}), the compiler phases that optimize these cases need to
5391 be able to move insns into one-instruction delay slots. However, some
5392 insns may generate more than one machine instruction. These insns
5393 cannot be placed into a delay slot.
5395 Often you can rewrite the single insn as a list of individual insns,
5396 each corresponding to one machine instruction. The disadvantage of
5397 doing so is that it will cause the compilation to be slower and require
5398 more space. If the resulting insns are too complex, it may also
5399 suppress some optimizations. The compiler splits the insn if there is a
5400 reason to believe that it might improve instruction or delay slot
5403 The insn combiner phase also splits putative insns. If three insns are
5404 merged into one insn with a complex expression that cannot be matched by
5405 some @code{define_insn} pattern, the combiner phase attempts to split
5406 the complex pattern into two insns that are recognized. Usually it can
5407 break the complex pattern into two patterns by splitting out some
5408 subexpression. However, in some other cases, such as performing an
5409 addition of a large constant in two insns on a RISC machine, the way to
5410 split the addition into two insns is machine-dependent.
5412 @findex define_split
5413 The @code{define_split} definition tells the compiler how to split a
5414 complex insn into several simpler insns. It looks like this:
5418 [@var{insn-pattern}]
5420 [@var{new-insn-pattern-1}
5421 @var{new-insn-pattern-2}
5423 "@var{preparation-statements}")
5426 @var{insn-pattern} is a pattern that needs to be split and
5427 @var{condition} is the final condition to be tested, as in a
5428 @code{define_insn}. When an insn matching @var{insn-pattern} and
5429 satisfying @var{condition} is found, it is replaced in the insn list
5430 with the insns given by @var{new-insn-pattern-1},
5431 @var{new-insn-pattern-2}, etc.
5433 The @var{preparation-statements} are similar to those statements that
5434 are specified for @code{define_expand} (@pxref{Expander Definitions})
5435 and are executed before the new RTL is generated to prepare for the
5436 generated code or emit some insns whose pattern is not fixed. Unlike
5437 those in @code{define_expand}, however, these statements must not
5438 generate any new pseudo-registers. Once reload has completed, they also
5439 must not allocate any space in the stack frame.
5441 Patterns are matched against @var{insn-pattern} in two different
5442 circumstances. If an insn needs to be split for delay slot scheduling
5443 or insn scheduling, the insn is already known to be valid, which means
5444 that it must have been matched by some @code{define_insn} and, if
5445 @code{reload_completed} is nonzero, is known to satisfy the constraints
5446 of that @code{define_insn}. In that case, the new insn patterns must
5447 also be insns that are matched by some @code{define_insn} and, if
5448 @code{reload_completed} is nonzero, must also satisfy the constraints
5449 of those definitions.
5451 As an example of this usage of @code{define_split}, consider the following
5452 example from @file{a29k.md}, which splits a @code{sign_extend} from
5453 @code{HImode} to @code{SImode} into a pair of shift insns:
5457 [(set (match_operand:SI 0 "gen_reg_operand" "")
5458 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
5461 (ashift:SI (match_dup 1)
5464 (ashiftrt:SI (match_dup 0)
5467 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
5470 When the combiner phase tries to split an insn pattern, it is always the
5471 case that the pattern is @emph{not} matched by any @code{define_insn}.
5472 The combiner pass first tries to split a single @code{set} expression
5473 and then the same @code{set} expression inside a @code{parallel}, but
5474 followed by a @code{clobber} of a pseudo-reg to use as a scratch
5475 register. In these cases, the combiner expects exactly two new insn
5476 patterns to be generated. It will verify that these patterns match some
5477 @code{define_insn} definitions, so you need not do this test in the
5478 @code{define_split} (of course, there is no point in writing a
5479 @code{define_split} that will never produce insns that match).
5481 Here is an example of this use of @code{define_split}, taken from
5486 [(set (match_operand:SI 0 "gen_reg_operand" "")
5487 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
5488 (match_operand:SI 2 "non_add_cint_operand" "")))]
5490 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
5491 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
5494 int low = INTVAL (operands[2]) & 0xffff;
5495 int high = (unsigned) INTVAL (operands[2]) >> 16;
5498 high++, low |= 0xffff0000;
5500 operands[3] = GEN_INT (high << 16);
5501 operands[4] = GEN_INT (low);
5505 Here the predicate @code{non_add_cint_operand} matches any
5506 @code{const_int} that is @emph{not} a valid operand of a single add
5507 insn. The add with the smaller displacement is written so that it
5508 can be substituted into the address of a subsequent operation.
5510 An example that uses a scratch register, from the same file, generates
5511 an equality comparison of a register and a large constant:
5515 [(set (match_operand:CC 0 "cc_reg_operand" "")
5516 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
5517 (match_operand:SI 2 "non_short_cint_operand" "")))
5518 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
5519 "find_single_use (operands[0], insn, 0)
5520 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
5521 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
5522 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
5523 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
5526 /* @r{Get the constant we are comparing against, C, and see what it
5527 looks like sign-extended to 16 bits. Then see what constant
5528 could be XOR'ed with C to get the sign-extended value.} */
5530 int c = INTVAL (operands[2]);
5531 int sextc = (c << 16) >> 16;
5532 int xorv = c ^ sextc;
5534 operands[4] = GEN_INT (xorv);
5535 operands[5] = GEN_INT (sextc);
5539 To avoid confusion, don't write a single @code{define_split} that
5540 accepts some insns that match some @code{define_insn} as well as some
5541 insns that don't. Instead, write two separate @code{define_split}
5542 definitions, one for the insns that are valid and one for the insns that
5545 The splitter is allowed to split jump instructions into sequence of
5546 jumps or create new jumps in while splitting non-jump instructions. As
5547 the central flowgraph and branch prediction information needs to be updated,
5548 several restriction apply.
5550 Splitting of jump instruction into sequence that over by another jump
5551 instruction is always valid, as compiler expect identical behavior of new
5552 jump. When new sequence contains multiple jump instructions or new labels,
5553 more assistance is needed. Splitter is required to create only unconditional
5554 jumps, or simple conditional jump instructions. Additionally it must attach a
5555 @code{REG_BR_PROB} note to each conditional jump. A global variable
5556 @code{split_branch_probability} holds the probability of the original branch in case
5557 it was an simple conditional jump, @minus{}1 otherwise. To simplify
5558 recomputing of edge frequencies, the new sequence is required to have only
5559 forward jumps to the newly created labels.
5561 @findex define_insn_and_split
5562 For the common case where the pattern of a define_split exactly matches the
5563 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
5567 (define_insn_and_split
5568 [@var{insn-pattern}]
5570 "@var{output-template}"
5571 "@var{split-condition}"
5572 [@var{new-insn-pattern-1}
5573 @var{new-insn-pattern-2}
5575 "@var{preparation-statements}"
5576 [@var{insn-attributes}])
5580 @var{insn-pattern}, @var{condition}, @var{output-template}, and
5581 @var{insn-attributes} are used as in @code{define_insn}. The
5582 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
5583 in a @code{define_split}. The @var{split-condition} is also used as in
5584 @code{define_split}, with the additional behavior that if the condition starts
5585 with @samp{&&}, the condition used for the split will be the constructed as a
5586 logical ``and'' of the split condition with the insn condition. For example,
5590 (define_insn_and_split "zero_extendhisi2_and"
5591 [(set (match_operand:SI 0 "register_operand" "=r")
5592 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
5593 (clobber (reg:CC 17))]
5594 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
5596 "&& reload_completed"
5597 [(parallel [(set (match_dup 0)
5598 (and:SI (match_dup 0) (const_int 65535)))
5599 (clobber (reg:CC 17))])]
5601 [(set_attr "type" "alu1")])
5605 In this case, the actual split condition will be
5606 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
5608 The @code{define_insn_and_split} construction provides exactly the same
5609 functionality as two separate @code{define_insn} and @code{define_split}
5610 patterns. It exists for compactness, and as a maintenance tool to prevent
5611 having to ensure the two patterns' templates match.
5615 @node Including Patterns
5616 @section Including Patterns in Machine Descriptions.
5617 @cindex insn includes
5620 The @code{include} pattern tells the compiler tools where to
5621 look for patterns that are in files other than in the file
5622 @file{.md}. This is used only at build time and there is no preprocessing allowed.
5636 (include "filestuff")
5640 Where @var{pathname} is a string that specifies the location of the file,
5641 specifies the include file to be in @file{gcc/config/target/filestuff}. The
5642 directory @file{gcc/config/target} is regarded as the default directory.
5645 Machine descriptions may be split up into smaller more manageable subsections
5646 and placed into subdirectories.
5652 (include "BOGUS/filestuff")
5656 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
5658 Specifying an absolute path for the include file such as;
5661 (include "/u2/BOGUS/filestuff")
5664 is permitted but is not encouraged.
5666 @subsection RTL Generation Tool Options for Directory Search
5667 @cindex directory options .md
5668 @cindex options, directory search
5669 @cindex search options
5671 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
5676 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
5681 Add the directory @var{dir} to the head of the list of directories to be
5682 searched for header files. This can be used to override a system machine definition
5683 file, substituting your own version, since these directories are
5684 searched before the default machine description file directories. If you use more than
5685 one @option{-I} option, the directories are scanned in left-to-right
5686 order; the standard default directory come after.
5691 @node Peephole Definitions
5692 @section Machine-Specific Peephole Optimizers
5693 @cindex peephole optimizer definitions
5694 @cindex defining peephole optimizers
5696 In addition to instruction patterns the @file{md} file may contain
5697 definitions of machine-specific peephole optimizations.
5699 The combiner does not notice certain peephole optimizations when the data
5700 flow in the program does not suggest that it should try them. For example,
5701 sometimes two consecutive insns related in purpose can be combined even
5702 though the second one does not appear to use a register computed in the
5703 first one. A machine-specific peephole optimizer can detect such
5706 There are two forms of peephole definitions that may be used. The
5707 original @code{define_peephole} is run at assembly output time to
5708 match insns and substitute assembly text. Use of @code{define_peephole}
5711 A newer @code{define_peephole2} matches insns and substitutes new
5712 insns. The @code{peephole2} pass is run after register allocation
5713 but before scheduling, which may result in much better code for
5714 targets that do scheduling.
5717 * define_peephole:: RTL to Text Peephole Optimizers
5718 * define_peephole2:: RTL to RTL Peephole Optimizers
5723 @node define_peephole
5724 @subsection RTL to Text Peephole Optimizers
5725 @findex define_peephole
5728 A definition looks like this:
5732 [@var{insn-pattern-1}
5733 @var{insn-pattern-2}
5737 "@var{optional-insn-attributes}")
5741 The last string operand may be omitted if you are not using any
5742 machine-specific information in this machine description. If present,
5743 it must obey the same rules as in a @code{define_insn}.
5745 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
5746 consecutive insns. The optimization applies to a sequence of insns when
5747 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
5748 the next, and so on.
5750 Each of the insns matched by a peephole must also match a
5751 @code{define_insn}. Peepholes are checked only at the last stage just
5752 before code generation, and only optionally. Therefore, any insn which
5753 would match a peephole but no @code{define_insn} will cause a crash in code
5754 generation in an unoptimized compilation, or at various optimization
5757 The operands of the insns are matched with @code{match_operands},
5758 @code{match_operator}, and @code{match_dup}, as usual. What is not
5759 usual is that the operand numbers apply to all the insn patterns in the
5760 definition. So, you can check for identical operands in two insns by
5761 using @code{match_operand} in one insn and @code{match_dup} in the
5764 The operand constraints used in @code{match_operand} patterns do not have
5765 any direct effect on the applicability of the peephole, but they will
5766 be validated afterward, so make sure your constraints are general enough
5767 to apply whenever the peephole matches. If the peephole matches
5768 but the constraints are not satisfied, the compiler will crash.
5770 It is safe to omit constraints in all the operands of the peephole; or
5771 you can write constraints which serve as a double-check on the criteria
5774 Once a sequence of insns matches the patterns, the @var{condition} is
5775 checked. This is a C expression which makes the final decision whether to
5776 perform the optimization (we do so if the expression is nonzero). If
5777 @var{condition} is omitted (in other words, the string is empty) then the
5778 optimization is applied to every sequence of insns that matches the
5781 The defined peephole optimizations are applied after register allocation
5782 is complete. Therefore, the peephole definition can check which
5783 operands have ended up in which kinds of registers, just by looking at
5786 @findex prev_active_insn
5787 The way to refer to the operands in @var{condition} is to write
5788 @code{operands[@var{i}]} for operand number @var{i} (as matched by
5789 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
5790 to refer to the last of the insns being matched; use
5791 @code{prev_active_insn} to find the preceding insns.
5793 @findex dead_or_set_p
5794 When optimizing computations with intermediate results, you can use
5795 @var{condition} to match only when the intermediate results are not used
5796 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
5797 @var{op})}, where @var{insn} is the insn in which you expect the value
5798 to be used for the last time (from the value of @code{insn}, together
5799 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
5800 value (from @code{operands[@var{i}]}).
5802 Applying the optimization means replacing the sequence of insns with one
5803 new insn. The @var{template} controls ultimate output of assembler code
5804 for this combined insn. It works exactly like the template of a
5805 @code{define_insn}. Operand numbers in this template are the same ones
5806 used in matching the original sequence of insns.
5808 The result of a defined peephole optimizer does not need to match any of
5809 the insn patterns in the machine description; it does not even have an
5810 opportunity to match them. The peephole optimizer definition itself serves
5811 as the insn pattern to control how the insn is output.
5813 Defined peephole optimizers are run as assembler code is being output,
5814 so the insns they produce are never combined or rearranged in any way.
5816 Here is an example, taken from the 68000 machine description:
5820 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
5821 (set (match_operand:DF 0 "register_operand" "=f")
5822 (match_operand:DF 1 "register_operand" "ad"))]
5823 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
5826 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
5828 output_asm_insn ("move.l %1,(sp)", xoperands);
5829 output_asm_insn ("move.l %1,-(sp)", operands);
5830 return "fmove.d (sp)+,%0";
5832 output_asm_insn ("movel %1,sp@@", xoperands);
5833 output_asm_insn ("movel %1,sp@@-", operands);
5834 return "fmoved sp@@+,%0";
5840 The effect of this optimization is to change
5866 If a peephole matches a sequence including one or more jump insns, you must
5867 take account of the flags such as @code{CC_REVERSED} which specify that the
5868 condition codes are represented in an unusual manner. The compiler
5869 automatically alters any ordinary conditional jumps which occur in such
5870 situations, but the compiler cannot alter jumps which have been replaced by
5871 peephole optimizations. So it is up to you to alter the assembler code
5872 that the peephole produces. Supply C code to write the assembler output,
5873 and in this C code check the condition code status flags and change the
5874 assembler code as appropriate.
5877 @var{insn-pattern-1} and so on look @emph{almost} like the second
5878 operand of @code{define_insn}. There is one important difference: the
5879 second operand of @code{define_insn} consists of one or more RTX's
5880 enclosed in square brackets. Usually, there is only one: then the same
5881 action can be written as an element of a @code{define_peephole}. But
5882 when there are multiple actions in a @code{define_insn}, they are
5883 implicitly enclosed in a @code{parallel}. Then you must explicitly
5884 write the @code{parallel}, and the square brackets within it, in the
5885 @code{define_peephole}. Thus, if an insn pattern looks like this,
5888 (define_insn "divmodsi4"
5889 [(set (match_operand:SI 0 "general_operand" "=d")
5890 (div:SI (match_operand:SI 1 "general_operand" "0")
5891 (match_operand:SI 2 "general_operand" "dmsK")))
5892 (set (match_operand:SI 3 "general_operand" "=d")
5893 (mod:SI (match_dup 1) (match_dup 2)))]
5895 "divsl%.l %2,%3:%0")
5899 then the way to mention this insn in a peephole is as follows:
5905 [(set (match_operand:SI 0 "general_operand" "=d")
5906 (div:SI (match_operand:SI 1 "general_operand" "0")
5907 (match_operand:SI 2 "general_operand" "dmsK")))
5908 (set (match_operand:SI 3 "general_operand" "=d")
5909 (mod:SI (match_dup 1) (match_dup 2)))])
5916 @node define_peephole2
5917 @subsection RTL to RTL Peephole Optimizers
5918 @findex define_peephole2
5920 The @code{define_peephole2} definition tells the compiler how to
5921 substitute one sequence of instructions for another sequence,
5922 what additional scratch registers may be needed and what their
5927 [@var{insn-pattern-1}
5928 @var{insn-pattern-2}
5931 [@var{new-insn-pattern-1}
5932 @var{new-insn-pattern-2}
5934 "@var{preparation-statements}")
5937 The definition is almost identical to @code{define_split}
5938 (@pxref{Insn Splitting}) except that the pattern to match is not a
5939 single instruction, but a sequence of instructions.
5941 It is possible to request additional scratch registers for use in the
5942 output template. If appropriate registers are not free, the pattern
5943 will simply not match.
5945 @findex match_scratch
5947 Scratch registers are requested with a @code{match_scratch} pattern at
5948 the top level of the input pattern. The allocated register (initially) will
5949 be dead at the point requested within the original sequence. If the scratch
5950 is used at more than a single point, a @code{match_dup} pattern at the
5951 top level of the input pattern marks the last position in the input sequence
5952 at which the register must be available.
5954 Here is an example from the IA-32 machine description:
5958 [(match_scratch:SI 2 "r")
5959 (parallel [(set (match_operand:SI 0 "register_operand" "")
5960 (match_operator:SI 3 "arith_or_logical_operator"
5962 (match_operand:SI 1 "memory_operand" "")]))
5963 (clobber (reg:CC 17))])]
5964 "! optimize_size && ! TARGET_READ_MODIFY"
5965 [(set (match_dup 2) (match_dup 1))
5966 (parallel [(set (match_dup 0)
5967 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
5968 (clobber (reg:CC 17))])]
5973 This pattern tries to split a load from its use in the hopes that we'll be
5974 able to schedule around the memory load latency. It allocates a single
5975 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
5976 to be live only at the point just before the arithmetic.
5978 A real example requiring extended scratch lifetimes is harder to come by,
5979 so here's a silly made-up example:
5983 [(match_scratch:SI 4 "r")
5984 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
5985 (set (match_operand:SI 2 "" "") (match_dup 1))
5987 (set (match_operand:SI 3 "" "") (match_dup 1))]
5988 "/* @r{determine 1 does not overlap 0 and 2} */"
5989 [(set (match_dup 4) (match_dup 1))
5990 (set (match_dup 0) (match_dup 4))
5991 (set (match_dup 2) (match_dup 4))]
5992 (set (match_dup 3) (match_dup 4))]
5997 If we had not added the @code{(match_dup 4)} in the middle of the input
5998 sequence, it might have been the case that the register we chose at the
5999 beginning of the sequence is killed by the first or second @code{set}.
6003 @node Insn Attributes
6004 @section Instruction Attributes
6005 @cindex insn attributes
6006 @cindex instruction attributes
6008 In addition to describing the instruction supported by the target machine,
6009 the @file{md} file also defines a group of @dfn{attributes} and a set of
6010 values for each. Every generated insn is assigned a value for each attribute.
6011 One possible attribute would be the effect that the insn has on the machine's
6012 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
6013 to track the condition codes.
6016 * Defining Attributes:: Specifying attributes and their values.
6017 * Expressions:: Valid expressions for attribute values.
6018 * Tagging Insns:: Assigning attribute values to insns.
6019 * Attr Example:: An example of assigning attributes.
6020 * Insn Lengths:: Computing the length of insns.
6021 * Constant Attributes:: Defining attributes that are constant.
6022 * Delay Slots:: Defining delay slots required for a machine.
6023 * Processor pipeline description:: Specifying information for insn scheduling.
6028 @node Defining Attributes
6029 @subsection Defining Attributes and their Values
6030 @cindex defining attributes and their values
6031 @cindex attributes, defining
6034 The @code{define_attr} expression is used to define each attribute required
6035 by the target machine. It looks like:
6038 (define_attr @var{name} @var{list-of-values} @var{default})
6041 @var{name} is a string specifying the name of the attribute being defined.
6043 @var{list-of-values} is either a string that specifies a comma-separated
6044 list of values that can be assigned to the attribute, or a null string to
6045 indicate that the attribute takes numeric values.
6047 @var{default} is an attribute expression that gives the value of this
6048 attribute for insns that match patterns whose definition does not include
6049 an explicit value for this attribute. @xref{Attr Example}, for more
6050 information on the handling of defaults. @xref{Constant Attributes},
6051 for information on attributes that do not depend on any particular insn.
6054 For each defined attribute, a number of definitions are written to the
6055 @file{insn-attr.h} file. For cases where an explicit set of values is
6056 specified for an attribute, the following are defined:
6060 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
6063 An enumerated class is defined for @samp{attr_@var{name}} with
6064 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
6065 the attribute name and value are first converted to uppercase.
6068 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
6069 returns the attribute value for that insn.
6072 For example, if the following is present in the @file{md} file:
6075 (define_attr "type" "branch,fp,load,store,arith" @dots{})
6079 the following lines will be written to the file @file{insn-attr.h}.
6082 #define HAVE_ATTR_type
6083 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
6084 TYPE_STORE, TYPE_ARITH@};
6085 extern enum attr_type get_attr_type ();
6088 If the attribute takes numeric values, no @code{enum} type will be
6089 defined and the function to obtain the attribute's value will return
6095 @subsection Attribute Expressions
6096 @cindex attribute expressions
6098 RTL expressions used to define attributes use the codes described above
6099 plus a few specific to attribute definitions, to be discussed below.
6100 Attribute value expressions must have one of the following forms:
6103 @cindex @code{const_int} and attributes
6104 @item (const_int @var{i})
6105 The integer @var{i} specifies the value of a numeric attribute. @var{i}
6106 must be non-negative.
6108 The value of a numeric attribute can be specified either with a
6109 @code{const_int}, or as an integer represented as a string in
6110 @code{const_string}, @code{eq_attr} (see below), @code{attr},
6111 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
6112 overrides on specific instructions (@pxref{Tagging Insns}).
6114 @cindex @code{const_string} and attributes
6115 @item (const_string @var{value})
6116 The string @var{value} specifies a constant attribute value.
6117 If @var{value} is specified as @samp{"*"}, it means that the default value of
6118 the attribute is to be used for the insn containing this expression.
6119 @samp{"*"} obviously cannot be used in the @var{default} expression
6120 of a @code{define_attr}.
6122 If the attribute whose value is being specified is numeric, @var{value}
6123 must be a string containing a non-negative integer (normally
6124 @code{const_int} would be used in this case). Otherwise, it must
6125 contain one of the valid values for the attribute.
6127 @cindex @code{if_then_else} and attributes
6128 @item (if_then_else @var{test} @var{true-value} @var{false-value})
6129 @var{test} specifies an attribute test, whose format is defined below.
6130 The value of this expression is @var{true-value} if @var{test} is true,
6131 otherwise it is @var{false-value}.
6133 @cindex @code{cond} and attributes
6134 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
6135 The first operand of this expression is a vector containing an even
6136 number of expressions and consisting of pairs of @var{test} and @var{value}
6137 expressions. The value of the @code{cond} expression is that of the
6138 @var{value} corresponding to the first true @var{test} expression. If
6139 none of the @var{test} expressions are true, the value of the @code{cond}
6140 expression is that of the @var{default} expression.
6143 @var{test} expressions can have one of the following forms:
6146 @cindex @code{const_int} and attribute tests
6147 @item (const_int @var{i})
6148 This test is true if @var{i} is nonzero and false otherwise.
6150 @cindex @code{not} and attributes
6151 @cindex @code{ior} and attributes
6152 @cindex @code{and} and attributes
6153 @item (not @var{test})
6154 @itemx (ior @var{test1} @var{test2})
6155 @itemx (and @var{test1} @var{test2})
6156 These tests are true if the indicated logical function is true.
6158 @cindex @code{match_operand} and attributes
6159 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
6160 This test is true if operand @var{n} of the insn whose attribute value
6161 is being determined has mode @var{m} (this part of the test is ignored
6162 if @var{m} is @code{VOIDmode}) and the function specified by the string
6163 @var{pred} returns a nonzero value when passed operand @var{n} and mode
6164 @var{m} (this part of the test is ignored if @var{pred} is the null
6167 The @var{constraints} operand is ignored and should be the null string.
6169 @cindex @code{le} and attributes
6170 @cindex @code{leu} and attributes
6171 @cindex @code{lt} and attributes
6172 @cindex @code{gt} and attributes
6173 @cindex @code{gtu} and attributes
6174 @cindex @code{ge} and attributes
6175 @cindex @code{geu} and attributes
6176 @cindex @code{ne} and attributes
6177 @cindex @code{eq} and attributes
6178 @cindex @code{plus} and attributes
6179 @cindex @code{minus} and attributes
6180 @cindex @code{mult} and attributes
6181 @cindex @code{div} and attributes
6182 @cindex @code{mod} and attributes
6183 @cindex @code{abs} and attributes
6184 @cindex @code{neg} and attributes
6185 @cindex @code{ashift} and attributes
6186 @cindex @code{lshiftrt} and attributes
6187 @cindex @code{ashiftrt} and attributes
6188 @item (le @var{arith1} @var{arith2})
6189 @itemx (leu @var{arith1} @var{arith2})
6190 @itemx (lt @var{arith1} @var{arith2})
6191 @itemx (ltu @var{arith1} @var{arith2})
6192 @itemx (gt @var{arith1} @var{arith2})
6193 @itemx (gtu @var{arith1} @var{arith2})
6194 @itemx (ge @var{arith1} @var{arith2})
6195 @itemx (geu @var{arith1} @var{arith2})
6196 @itemx (ne @var{arith1} @var{arith2})
6197 @itemx (eq @var{arith1} @var{arith2})
6198 These tests are true if the indicated comparison of the two arithmetic
6199 expressions is true. Arithmetic expressions are formed with
6200 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
6201 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
6202 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
6205 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
6206 Lengths},for additional forms). @code{symbol_ref} is a string
6207 denoting a C expression that yields an @code{int} when evaluated by the
6208 @samp{get_attr_@dots{}} routine. It should normally be a global
6212 @item (eq_attr @var{name} @var{value})
6213 @var{name} is a string specifying the name of an attribute.
6215 @var{value} is a string that is either a valid value for attribute
6216 @var{name}, a comma-separated list of values, or @samp{!} followed by a
6217 value or list. If @var{value} does not begin with a @samp{!}, this
6218 test is true if the value of the @var{name} attribute of the current
6219 insn is in the list specified by @var{value}. If @var{value} begins
6220 with a @samp{!}, this test is true if the attribute's value is
6221 @emph{not} in the specified list.
6226 (eq_attr "type" "load,store")
6233 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
6236 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
6237 value of the compiler variable @code{which_alternative}
6238 (@pxref{Output Statement}) and the values must be small integers. For
6242 (eq_attr "alternative" "2,3")
6249 (ior (eq (symbol_ref "which_alternative") (const_int 2))
6250 (eq (symbol_ref "which_alternative") (const_int 3)))
6253 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
6254 where the value of the attribute being tested is known for all insns matching
6255 a particular pattern. This is by far the most common case.
6258 @item (attr_flag @var{name})
6259 The value of an @code{attr_flag} expression is true if the flag
6260 specified by @var{name} is true for the @code{insn} currently being
6263 @var{name} is a string specifying one of a fixed set of flags to test.
6264 Test the flags @code{forward} and @code{backward} to determine the
6265 direction of a conditional branch. Test the flags @code{very_likely},
6266 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
6267 if a conditional branch is expected to be taken.
6269 If the @code{very_likely} flag is true, then the @code{likely} flag is also
6270 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
6272 This example describes a conditional branch delay slot which
6273 can be nullified for forward branches that are taken (annul-true) or
6274 for backward branches which are not taken (annul-false).
6277 (define_delay (eq_attr "type" "cbranch")
6278 [(eq_attr "in_branch_delay" "true")
6279 (and (eq_attr "in_branch_delay" "true")
6280 (attr_flag "forward"))
6281 (and (eq_attr "in_branch_delay" "true")
6282 (attr_flag "backward"))])
6285 The @code{forward} and @code{backward} flags are false if the current
6286 @code{insn} being scheduled is not a conditional branch.
6288 The @code{very_likely} and @code{likely} flags are true if the
6289 @code{insn} being scheduled is not a conditional branch.
6290 The @code{very_unlikely} and @code{unlikely} flags are false if the
6291 @code{insn} being scheduled is not a conditional branch.
6293 @code{attr_flag} is only used during delay slot scheduling and has no
6294 meaning to other passes of the compiler.
6297 @item (attr @var{name})
6298 The value of another attribute is returned. This is most useful
6299 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
6300 produce more efficient code for non-numeric attributes.
6306 @subsection Assigning Attribute Values to Insns
6307 @cindex tagging insns
6308 @cindex assigning attribute values to insns
6310 The value assigned to an attribute of an insn is primarily determined by
6311 which pattern is matched by that insn (or which @code{define_peephole}
6312 generated it). Every @code{define_insn} and @code{define_peephole} can
6313 have an optional last argument to specify the values of attributes for
6314 matching insns. The value of any attribute not specified in a particular
6315 insn is set to the default value for that attribute, as specified in its
6316 @code{define_attr}. Extensive use of default values for attributes
6317 permits the specification of the values for only one or two attributes
6318 in the definition of most insn patterns, as seen in the example in the
6321 The optional last argument of @code{define_insn} and
6322 @code{define_peephole} is a vector of expressions, each of which defines
6323 the value for a single attribute. The most general way of assigning an
6324 attribute's value is to use a @code{set} expression whose first operand is an
6325 @code{attr} expression giving the name of the attribute being set. The
6326 second operand of the @code{set} is an attribute expression
6327 (@pxref{Expressions}) giving the value of the attribute.
6329 When the attribute value depends on the @samp{alternative} attribute
6330 (i.e., which is the applicable alternative in the constraint of the
6331 insn), the @code{set_attr_alternative} expression can be used. It
6332 allows the specification of a vector of attribute expressions, one for
6336 When the generality of arbitrary attribute expressions is not required,
6337 the simpler @code{set_attr} expression can be used, which allows
6338 specifying a string giving either a single attribute value or a list
6339 of attribute values, one for each alternative.
6341 The form of each of the above specifications is shown below. In each case,
6342 @var{name} is a string specifying the attribute to be set.
6345 @item (set_attr @var{name} @var{value-string})
6346 @var{value-string} is either a string giving the desired attribute value,
6347 or a string containing a comma-separated list giving the values for
6348 succeeding alternatives. The number of elements must match the number
6349 of alternatives in the constraint of the insn pattern.
6351 Note that it may be useful to specify @samp{*} for some alternative, in
6352 which case the attribute will assume its default value for insns matching
6355 @findex set_attr_alternative
6356 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
6357 Depending on the alternative of the insn, the value will be one of the
6358 specified values. This is a shorthand for using a @code{cond} with
6359 tests on the @samp{alternative} attribute.
6362 @item (set (attr @var{name}) @var{value})
6363 The first operand of this @code{set} must be the special RTL expression
6364 @code{attr}, whose sole operand is a string giving the name of the
6365 attribute being set. @var{value} is the value of the attribute.
6368 The following shows three different ways of representing the same
6369 attribute value specification:
6372 (set_attr "type" "load,store,arith")
6374 (set_attr_alternative "type"
6375 [(const_string "load") (const_string "store")
6376 (const_string "arith")])
6379 (cond [(eq_attr "alternative" "1") (const_string "load")
6380 (eq_attr "alternative" "2") (const_string "store")]
6381 (const_string "arith")))
6385 @findex define_asm_attributes
6386 The @code{define_asm_attributes} expression provides a mechanism to
6387 specify the attributes assigned to insns produced from an @code{asm}
6388 statement. It has the form:
6391 (define_asm_attributes [@var{attr-sets}])
6395 where @var{attr-sets} is specified the same as for both the
6396 @code{define_insn} and the @code{define_peephole} expressions.
6398 These values will typically be the ``worst case'' attribute values. For
6399 example, they might indicate that the condition code will be clobbered.
6401 A specification for a @code{length} attribute is handled specially. The
6402 way to compute the length of an @code{asm} insn is to multiply the
6403 length specified in the expression @code{define_asm_attributes} by the
6404 number of machine instructions specified in the @code{asm} statement,
6405 determined by counting the number of semicolons and newlines in the
6406 string. Therefore, the value of the @code{length} attribute specified
6407 in a @code{define_asm_attributes} should be the maximum possible length
6408 of a single machine instruction.
6413 @subsection Example of Attribute Specifications
6414 @cindex attribute specifications example
6415 @cindex attribute specifications
6417 The judicious use of defaulting is important in the efficient use of
6418 insn attributes. Typically, insns are divided into @dfn{types} and an
6419 attribute, customarily called @code{type}, is used to represent this
6420 value. This attribute is normally used only to define the default value
6421 for other attributes. An example will clarify this usage.
6423 Assume we have a RISC machine with a condition code and in which only
6424 full-word operations are performed in registers. Let us assume that we
6425 can divide all insns into loads, stores, (integer) arithmetic
6426 operations, floating point operations, and branches.
6428 Here we will concern ourselves with determining the effect of an insn on
6429 the condition code and will limit ourselves to the following possible
6430 effects: The condition code can be set unpredictably (clobbered), not
6431 be changed, be set to agree with the results of the operation, or only
6432 changed if the item previously set into the condition code has been
6435 Here is part of a sample @file{md} file for such a machine:
6438 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
6440 (define_attr "cc" "clobber,unchanged,set,change0"
6441 (cond [(eq_attr "type" "load")
6442 (const_string "change0")
6443 (eq_attr "type" "store,branch")
6444 (const_string "unchanged")
6445 (eq_attr "type" "arith")
6446 (if_then_else (match_operand:SI 0 "" "")
6447 (const_string "set")
6448 (const_string "clobber"))]
6449 (const_string "clobber")))
6452 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
6453 (match_operand:SI 1 "general_operand" "r,m,r"))]
6459 [(set_attr "type" "arith,load,store")])
6462 Note that we assume in the above example that arithmetic operations
6463 performed on quantities smaller than a machine word clobber the condition
6464 code since they will set the condition code to a value corresponding to the
6470 @subsection Computing the Length of an Insn
6471 @cindex insn lengths, computing
6472 @cindex computing the length of an insn
6474 For many machines, multiple types of branch instructions are provided, each
6475 for different length branch displacements. In most cases, the assembler
6476 will choose the correct instruction to use. However, when the assembler
6477 cannot do so, GCC can when a special attribute, the @code{length}
6478 attribute, is defined. This attribute must be defined to have numeric
6479 values by specifying a null string in its @code{define_attr}.
6481 In the case of the @code{length} attribute, two additional forms of
6482 arithmetic terms are allowed in test expressions:
6485 @cindex @code{match_dup} and attributes
6486 @item (match_dup @var{n})
6487 This refers to the address of operand @var{n} of the current insn, which
6488 must be a @code{label_ref}.
6490 @cindex @code{pc} and attributes
6492 This refers to the address of the @emph{current} insn. It might have
6493 been more consistent with other usage to make this the address of the
6494 @emph{next} insn but this would be confusing because the length of the
6495 current insn is to be computed.
6498 @cindex @code{addr_vec}, length of
6499 @cindex @code{addr_diff_vec}, length of
6500 For normal insns, the length will be determined by value of the
6501 @code{length} attribute. In the case of @code{addr_vec} and
6502 @code{addr_diff_vec} insn patterns, the length is computed as
6503 the number of vectors multiplied by the size of each vector.
6505 Lengths are measured in addressable storage units (bytes).
6507 The following macros can be used to refine the length computation:
6510 @findex ADJUST_INSN_LENGTH
6511 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
6512 If defined, modifies the length assigned to instruction @var{insn} as a
6513 function of the context in which it is used. @var{length} is an lvalue
6514 that contains the initially computed length of the insn and should be
6515 updated with the correct length of the insn.
6517 This macro will normally not be required. A case in which it is
6518 required is the ROMP@. On this machine, the size of an @code{addr_vec}
6519 insn must be increased by two to compensate for the fact that alignment
6523 @findex get_attr_length
6524 The routine that returns @code{get_attr_length} (the value of the
6525 @code{length} attribute) can be used by the output routine to
6526 determine the form of the branch instruction to be written, as the
6527 example below illustrates.
6529 As an example of the specification of variable-length branches, consider
6530 the IBM 360. If we adopt the convention that a register will be set to
6531 the starting address of a function, we can jump to labels within 4k of
6532 the start using a four-byte instruction. Otherwise, we need a six-byte
6533 sequence to load the address from memory and then branch to it.
6535 On such a machine, a pattern for a branch instruction might be specified
6541 (label_ref (match_operand 0 "" "")))]
6544 return (get_attr_length (insn) == 4
6545 ? "b %l0" : "l r15,=a(%l0); br r15");
6547 [(set (attr "length")
6548 (if_then_else (lt (match_dup 0) (const_int 4096))
6555 @node Constant Attributes
6556 @subsection Constant Attributes
6557 @cindex constant attributes
6559 A special form of @code{define_attr}, where the expression for the
6560 default value is a @code{const} expression, indicates an attribute that
6561 is constant for a given run of the compiler. Constant attributes may be
6562 used to specify which variety of processor is used. For example,
6565 (define_attr "cpu" "m88100,m88110,m88000"
6567 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
6568 (symbol_ref "TARGET_88110") (const_string "m88110")]
6569 (const_string "m88000"))))
6571 (define_attr "memory" "fast,slow"
6573 (if_then_else (symbol_ref "TARGET_FAST_MEM")
6574 (const_string "fast")
6575 (const_string "slow"))))
6578 The routine generated for constant attributes has no parameters as it
6579 does not depend on any particular insn. RTL expressions used to define
6580 the value of a constant attribute may use the @code{symbol_ref} form,
6581 but may not use either the @code{match_operand} form or @code{eq_attr}
6582 forms involving insn attributes.
6587 @subsection Delay Slot Scheduling
6588 @cindex delay slots, defining
6590 The insn attribute mechanism can be used to specify the requirements for
6591 delay slots, if any, on a target machine. An instruction is said to
6592 require a @dfn{delay slot} if some instructions that are physically
6593 after the instruction are executed as if they were located before it.
6594 Classic examples are branch and call instructions, which often execute
6595 the following instruction before the branch or call is performed.
6597 On some machines, conditional branch instructions can optionally
6598 @dfn{annul} instructions in the delay slot. This means that the
6599 instruction will not be executed for certain branch outcomes. Both
6600 instructions that annul if the branch is true and instructions that
6601 annul if the branch is false are supported.
6603 Delay slot scheduling differs from instruction scheduling in that
6604 determining whether an instruction needs a delay slot is dependent only
6605 on the type of instruction being generated, not on data flow between the
6606 instructions. See the next section for a discussion of data-dependent
6607 instruction scheduling.
6609 @findex define_delay
6610 The requirement of an insn needing one or more delay slots is indicated
6611 via the @code{define_delay} expression. It has the following form:
6614 (define_delay @var{test}
6615 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
6616 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
6620 @var{test} is an attribute test that indicates whether this
6621 @code{define_delay} applies to a particular insn. If so, the number of
6622 required delay slots is determined by the length of the vector specified
6623 as the second argument. An insn placed in delay slot @var{n} must
6624 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
6625 attribute test that specifies which insns may be annulled if the branch
6626 is true. Similarly, @var{annul-false-n} specifies which insns in the
6627 delay slot may be annulled if the branch is false. If annulling is not
6628 supported for that delay slot, @code{(nil)} should be coded.
6630 For example, in the common case where branch and call insns require
6631 a single delay slot, which may contain any insn other than a branch or
6632 call, the following would be placed in the @file{md} file:
6635 (define_delay (eq_attr "type" "branch,call")
6636 [(eq_attr "type" "!branch,call") (nil) (nil)])
6639 Multiple @code{define_delay} expressions may be specified. In this
6640 case, each such expression specifies different delay slot requirements
6641 and there must be no insn for which tests in two @code{define_delay}
6642 expressions are both true.
6644 For example, if we have a machine that requires one delay slot for branches
6645 but two for calls, no delay slot can contain a branch or call insn,
6646 and any valid insn in the delay slot for the branch can be annulled if the
6647 branch is true, we might represent this as follows:
6650 (define_delay (eq_attr "type" "branch")
6651 [(eq_attr "type" "!branch,call")
6652 (eq_attr "type" "!branch,call")
6655 (define_delay (eq_attr "type" "call")
6656 [(eq_attr "type" "!branch,call") (nil) (nil)
6657 (eq_attr "type" "!branch,call") (nil) (nil)])
6659 @c the above is *still* too long. --mew 4feb93
6663 @node Processor pipeline description
6664 @subsection Specifying processor pipeline description
6665 @cindex processor pipeline description
6666 @cindex processor functional units
6667 @cindex instruction latency time
6668 @cindex interlock delays
6669 @cindex data dependence delays
6670 @cindex reservation delays
6671 @cindex pipeline hazard recognizer
6672 @cindex automaton based pipeline description
6673 @cindex regular expressions
6674 @cindex deterministic finite state automaton
6675 @cindex automaton based scheduler
6679 To achieve better performance, most modern processors
6680 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
6681 processors) have many @dfn{functional units} on which several
6682 instructions can be executed simultaneously. An instruction starts
6683 execution if its issue conditions are satisfied. If not, the
6684 instruction is stalled until its conditions are satisfied. Such
6685 @dfn{interlock (pipeline) delay} causes interruption of the fetching
6686 of successor instructions (or demands nop instructions, e.g.@: for some
6689 There are two major kinds of interlock delays in modern processors.
6690 The first one is a data dependence delay determining @dfn{instruction
6691 latency time}. The instruction execution is not started until all
6692 source data have been evaluated by prior instructions (there are more
6693 complex cases when the instruction execution starts even when the data
6694 are not available but will be ready in given time after the
6695 instruction execution start). Taking the data dependence delays into
6696 account is simple. The data dependence (true, output, and
6697 anti-dependence) delay between two instructions is given by a
6698 constant. In most cases this approach is adequate. The second kind
6699 of interlock delays is a reservation delay. The reservation delay
6700 means that two instructions under execution will be in need of shared
6701 processors resources, i.e.@: buses, internal registers, and/or
6702 functional units, which are reserved for some time. Taking this kind
6703 of delay into account is complex especially for modern @acronym{RISC}
6706 The task of exploiting more processor parallelism is solved by an
6707 instruction scheduler. For a better solution to this problem, the
6708 instruction scheduler has to have an adequate description of the
6709 processor parallelism (or @dfn{pipeline description}). GCC
6710 machine descriptions describe processor parallelism and functional
6711 unit reservations for groups of instructions with the aid of
6712 @dfn{regular expressions}.
6714 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
6715 figure out the possibility of the instruction issue by the processor
6716 on a given simulated processor cycle. The pipeline hazard recognizer is
6717 automatically generated from the processor pipeline description. The
6718 pipeline hazard recognizer generated from the machine description
6719 is based on a deterministic finite state automaton (@acronym{DFA}):
6720 the instruction issue is possible if there is a transition from one
6721 automaton state to another one. This algorithm is very fast, and
6722 furthermore, its speed is not dependent on processor
6723 complexity@footnote{However, the size of the automaton depends on
6724 processor complexity. To limit this effect, machine descriptions
6725 can split orthogonal parts of the machine description among several
6726 automata: but then, since each of these must be stepped independently,
6727 this does cause a small decrease in the algorithm's performance.}.
6729 @cindex automaton based pipeline description
6730 The rest of this section describes the directives that constitute
6731 an automaton-based processor pipeline description. The order of
6732 these constructions within the machine description file is not
6735 @findex define_automaton
6736 @cindex pipeline hazard recognizer
6737 The following optional construction describes names of automata
6738 generated and used for the pipeline hazards recognition. Sometimes
6739 the generated finite state automaton used by the pipeline hazard
6740 recognizer is large. If we use more than one automaton and bind functional
6741 units to the automata, the total size of the automata is usually
6742 less than the size of the single automaton. If there is no one such
6743 construction, only one finite state automaton is generated.
6746 (define_automaton @var{automata-names})
6749 @var{automata-names} is a string giving names of the automata. The
6750 names are separated by commas. All the automata should have unique names.
6751 The automaton name is used in the constructions @code{define_cpu_unit} and
6752 @code{define_query_cpu_unit}.
6754 @findex define_cpu_unit
6755 @cindex processor functional units
6756 Each processor functional unit used in the description of instruction
6757 reservations should be described by the following construction.
6760 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
6763 @var{unit-names} is a string giving the names of the functional units
6764 separated by commas. Don't use name @samp{nothing}, it is reserved
6767 @var{automaton-name} is a string giving the name of the automaton with
6768 which the unit is bound. The automaton should be described in
6769 construction @code{define_automaton}. You should give
6770 @dfn{automaton-name}, if there is a defined automaton.
6772 The assignment of units to automata are constrained by the uses of the
6773 units in insn reservations. The most important constraint is: if a
6774 unit reservation is present on a particular cycle of an alternative
6775 for an insn reservation, then some unit from the same automaton must
6776 be present on the same cycle for the other alternatives of the insn
6777 reservation. The rest of the constraints are mentioned in the
6778 description of the subsequent constructions.
6780 @findex define_query_cpu_unit
6781 @cindex querying function unit reservations
6782 The following construction describes CPU functional units analogously
6783 to @code{define_cpu_unit}. The reservation of such units can be
6784 queried for an automaton state. The instruction scheduler never
6785 queries reservation of functional units for given automaton state. So
6786 as a rule, you don't need this construction. This construction could
6787 be used for future code generation goals (e.g.@: to generate
6788 @acronym{VLIW} insn templates).
6791 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
6794 @var{unit-names} is a string giving names of the functional units
6795 separated by commas.
6797 @var{automaton-name} is a string giving the name of the automaton with
6798 which the unit is bound.
6800 @findex define_insn_reservation
6801 @cindex instruction latency time
6802 @cindex regular expressions
6804 The following construction is the major one to describe pipeline
6805 characteristics of an instruction.
6808 (define_insn_reservation @var{insn-name} @var{default_latency}
6809 @var{condition} @var{regexp})
6812 @var{default_latency} is a number giving latency time of the
6813 instruction. There is an important difference between the old
6814 description and the automaton based pipeline description. The latency
6815 time is used for all dependencies when we use the old description. In
6816 the automaton based pipeline description, the given latency time is only
6817 used for true dependencies. The cost of anti-dependencies is always
6818 zero and the cost of output dependencies is the difference between
6819 latency times of the producing and consuming insns (if the difference
6820 is negative, the cost is considered to be zero). You can always
6821 change the default costs for any description by using the target hook
6822 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
6824 @var{insn-name} is a string giving the internal name of the insn. The
6825 internal names are used in constructions @code{define_bypass} and in
6826 the automaton description file generated for debugging. The internal
6827 name has nothing in common with the names in @code{define_insn}. It is a
6828 good practice to use insn classes described in the processor manual.
6830 @var{condition} defines what RTL insns are described by this
6831 construction. You should remember that you will be in trouble if
6832 @var{condition} for two or more different
6833 @code{define_insn_reservation} constructions is TRUE for an insn. In
6834 this case what reservation will be used for the insn is not defined.
6835 Such cases are not checked during generation of the pipeline hazards
6836 recognizer because in general recognizing that two conditions may have
6837 the same value is quite difficult (especially if the conditions
6838 contain @code{symbol_ref}). It is also not checked during the
6839 pipeline hazard recognizer work because it would slow down the
6840 recognizer considerably.
6842 @var{regexp} is a string describing the reservation of the cpu's functional
6843 units by the instruction. The reservations are described by a regular
6844 expression according to the following syntax:
6847 regexp = regexp "," oneof
6850 oneof = oneof "|" allof
6853 allof = allof "+" repeat
6856 repeat = element "*" number
6859 element = cpu_function_unit_name
6868 @samp{,} is used for describing the start of the next cycle in
6872 @samp{|} is used for describing a reservation described by the first
6873 regular expression @strong{or} a reservation described by the second
6874 regular expression @strong{or} etc.
6877 @samp{+} is used for describing a reservation described by the first
6878 regular expression @strong{and} a reservation described by the
6879 second regular expression @strong{and} etc.
6882 @samp{*} is used for convenience and simply means a sequence in which
6883 the regular expression are repeated @var{number} times with cycle
6884 advancing (see @samp{,}).
6887 @samp{cpu_function_unit_name} denotes reservation of the named
6891 @samp{reservation_name} --- see description of construction
6892 @samp{define_reservation}.
6895 @samp{nothing} denotes no unit reservations.
6898 @findex define_reservation
6899 Sometimes unit reservations for different insns contain common parts.
6900 In such case, you can simplify the pipeline description by describing
6901 the common part by the following construction
6904 (define_reservation @var{reservation-name} @var{regexp})
6907 @var{reservation-name} is a string giving name of @var{regexp}.
6908 Functional unit names and reservation names are in the same name
6909 space. So the reservation names should be different from the
6910 functional unit names and can not be the reserved name @samp{nothing}.
6912 @findex define_bypass
6913 @cindex instruction latency time
6915 The following construction is used to describe exceptions in the
6916 latency time for given instruction pair. This is so called bypasses.
6919 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
6923 @var{number} defines when the result generated by the instructions
6924 given in string @var{out_insn_names} will be ready for the
6925 instructions given in string @var{in_insn_names}. The instructions in
6926 the string are separated by commas.
6928 @var{guard} is an optional string giving the name of a C function which
6929 defines an additional guard for the bypass. The function will get the
6930 two insns as parameters. If the function returns zero the bypass will
6931 be ignored for this case. The additional guard is necessary to
6932 recognize complicated bypasses, e.g.@: when the consumer is only an address
6933 of insn @samp{store} (not a stored value).
6935 @findex exclusion_set
6936 @findex presence_set
6937 @findex final_presence_set
6939 @findex final_absence_set
6942 The following five constructions are usually used to describe
6943 @acronym{VLIW} processors, or more precisely, to describe a placement
6944 of small instructions into @acronym{VLIW} instruction slots. They
6945 can be used for @acronym{RISC} processors, too.
6948 (exclusion_set @var{unit-names} @var{unit-names})
6949 (presence_set @var{unit-names} @var{patterns})
6950 (final_presence_set @var{unit-names} @var{patterns})
6951 (absence_set @var{unit-names} @var{patterns})
6952 (final_absence_set @var{unit-names} @var{patterns})
6955 @var{unit-names} is a string giving names of functional units
6956 separated by commas.
6958 @var{patterns} is a string giving patterns of functional units
6959 separated by comma. Currently pattern is one unit or units
6960 separated by white-spaces.
6962 The first construction (@samp{exclusion_set}) means that each
6963 functional unit in the first string can not be reserved simultaneously
6964 with a unit whose name is in the second string and vice versa. For
6965 example, the construction is useful for describing processors
6966 (e.g.@: some SPARC processors) with a fully pipelined floating point
6967 functional unit which can execute simultaneously only single floating
6968 point insns or only double floating point insns.
6970 The second construction (@samp{presence_set}) means that each
6971 functional unit in the first string can not be reserved unless at
6972 least one of pattern of units whose names are in the second string is
6973 reserved. This is an asymmetric relation. For example, it is useful
6974 for description that @acronym{VLIW} @samp{slot1} is reserved after
6975 @samp{slot0} reservation. We could describe it by the following
6979 (presence_set "slot1" "slot0")
6982 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
6983 reservation. In this case we could write
6986 (presence_set "slot1" "slot0 b0")
6989 The third construction (@samp{final_presence_set}) is analogous to
6990 @samp{presence_set}. The difference between them is when checking is
6991 done. When an instruction is issued in given automaton state
6992 reflecting all current and planned unit reservations, the automaton
6993 state is changed. The first state is a source state, the second one
6994 is a result state. Checking for @samp{presence_set} is done on the
6995 source state reservation, checking for @samp{final_presence_set} is
6996 done on the result reservation. This construction is useful to
6997 describe a reservation which is actually two subsequent reservations.
6998 For example, if we use
7001 (presence_set "slot1" "slot0")
7004 the following insn will be never issued (because @samp{slot1} requires
7005 @samp{slot0} which is absent in the source state).
7008 (define_reservation "insn_and_nop" "slot0 + slot1")
7011 but it can be issued if we use analogous @samp{final_presence_set}.
7013 The forth construction (@samp{absence_set}) means that each functional
7014 unit in the first string can be reserved only if each pattern of units
7015 whose names are in the second string is not reserved. This is an
7016 asymmetric relation (actually @samp{exclusion_set} is analogous to
7017 this one but it is symmetric). For example it might be useful in a
7018 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
7019 after either @samp{slot1} or @samp{slot2} have been reserved. This
7020 can be described as:
7023 (absence_set "slot0" "slot1, slot2")
7026 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
7027 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
7028 this case we could write
7031 (absence_set "slot2" "slot0 b0, slot1 b1")
7034 All functional units mentioned in a set should belong to the same
7037 The last construction (@samp{final_absence_set}) is analogous to
7038 @samp{absence_set} but checking is done on the result (state)
7039 reservation. See comments for @samp{final_presence_set}.
7041 @findex automata_option
7042 @cindex deterministic finite state automaton
7043 @cindex nondeterministic finite state automaton
7044 @cindex finite state automaton minimization
7045 You can control the generator of the pipeline hazard recognizer with
7046 the following construction.
7049 (automata_option @var{options})
7052 @var{options} is a string giving options which affect the generated
7053 code. Currently there are the following options:
7057 @dfn{no-minimization} makes no minimization of the automaton. This is
7058 only worth to do when we are debugging the description and need to
7059 look more accurately at reservations of states.
7062 @dfn{time} means printing additional time statistics about
7063 generation of automata.
7066 @dfn{v} means a generation of the file describing the result automata.
7067 The file has suffix @samp{.dfa} and can be used for the description
7068 verification and debugging.
7071 @dfn{w} means a generation of warning instead of error for
7072 non-critical errors.
7075 @dfn{ndfa} makes nondeterministic finite state automata. This affects
7076 the treatment of operator @samp{|} in the regular expressions. The
7077 usual treatment of the operator is to try the first alternative and,
7078 if the reservation is not possible, the second alternative. The
7079 nondeterministic treatment means trying all alternatives, some of them
7080 may be rejected by reservations in the subsequent insns.
7083 @dfn{progress} means output of a progress bar showing how many states
7084 were generated so far for automaton being processed. This is useful
7085 during debugging a @acronym{DFA} description. If you see too many
7086 generated states, you could interrupt the generator of the pipeline
7087 hazard recognizer and try to figure out a reason for generation of the
7091 As an example, consider a superscalar @acronym{RISC} machine which can
7092 issue three insns (two integer insns and one floating point insn) on
7093 the cycle but can finish only two insns. To describe this, we define
7094 the following functional units.
7097 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
7098 (define_cpu_unit "port0, port1")
7101 All simple integer insns can be executed in any integer pipeline and
7102 their result is ready in two cycles. The simple integer insns are
7103 issued into the first pipeline unless it is reserved, otherwise they
7104 are issued into the second pipeline. Integer division and
7105 multiplication insns can be executed only in the second integer
7106 pipeline and their results are ready correspondingly in 8 and 4
7107 cycles. The integer division is not pipelined, i.e.@: the subsequent
7108 integer division insn can not be issued until the current division
7109 insn finished. Floating point insns are fully pipelined and their
7110 results are ready in 3 cycles. Where the result of a floating point
7111 insn is used by an integer insn, an additional delay of one cycle is
7112 incurred. To describe all of this we could specify
7115 (define_cpu_unit "div")
7117 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7118 "(i0_pipeline | i1_pipeline), (port0 | port1)")
7120 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
7121 "i1_pipeline, nothing*2, (port0 | port1)")
7123 (define_insn_reservation "div" 8 (eq_attr "type" "div")
7124 "i1_pipeline, div*7, div + (port0 | port1)")
7126 (define_insn_reservation "float" 3 (eq_attr "type" "float")
7127 "f_pipeline, nothing, (port0 | port1))
7129 (define_bypass 4 "float" "simple,mult,div")
7132 To simplify the description we could describe the following reservation
7135 (define_reservation "finish" "port0|port1")
7138 and use it in all @code{define_insn_reservation} as in the following
7142 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
7143 "(i0_pipeline | i1_pipeline), finish")
7149 @node Conditional Execution
7150 @section Conditional Execution
7151 @cindex conditional execution
7154 A number of architectures provide for some form of conditional
7155 execution, or predication. The hallmark of this feature is the
7156 ability to nullify most of the instructions in the instruction set.
7157 When the instruction set is large and not entirely symmetric, it
7158 can be quite tedious to describe these forms directly in the
7159 @file{.md} file. An alternative is the @code{define_cond_exec} template.
7161 @findex define_cond_exec
7164 [@var{predicate-pattern}]
7166 "@var{output-template}")
7169 @var{predicate-pattern} is the condition that must be true for the
7170 insn to be executed at runtime and should match a relational operator.
7171 One can use @code{match_operator} to match several relational operators
7172 at once. Any @code{match_operand} operands must have no more than one
7175 @var{condition} is a C expression that must be true for the generated
7178 @findex current_insn_predicate
7179 @var{output-template} is a string similar to the @code{define_insn}
7180 output template (@pxref{Output Template}), except that the @samp{*}
7181 and @samp{@@} special cases do not apply. This is only useful if the
7182 assembly text for the predicate is a simple prefix to the main insn.
7183 In order to handle the general case, there is a global variable
7184 @code{current_insn_predicate} that will contain the entire predicate
7185 if the current insn is predicated, and will otherwise be @code{NULL}.
7187 When @code{define_cond_exec} is used, an implicit reference to
7188 the @code{predicable} instruction attribute is made.
7189 @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have
7190 exactly two elements in its @var{list-of-values}). Further, it must
7191 not be used with complex expressions. That is, the default and all
7192 uses in the insns must be a simple constant, not dependent on the
7193 alternative or anything else.
7195 For each @code{define_insn} for which the @code{predicable}
7196 attribute is true, a new @code{define_insn} pattern will be
7197 generated that matches a predicated version of the instruction.
7201 (define_insn "addsi"
7202 [(set (match_operand:SI 0 "register_operand" "r")
7203 (plus:SI (match_operand:SI 1 "register_operand" "r")
7204 (match_operand:SI 2 "register_operand" "r")))]
7209 [(ne (match_operand:CC 0 "register_operand" "c")
7216 generates a new pattern
7221 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
7222 (set (match_operand:SI 0 "register_operand" "r")
7223 (plus:SI (match_operand:SI 1 "register_operand" "r")
7224 (match_operand:SI 2 "register_operand" "r"))))]
7225 "(@var{test2}) && (@var{test1})"
7226 "(%3) add %2,%1,%0")
7231 @node Constant Definitions
7232 @section Constant Definitions
7233 @cindex constant definitions
7234 @findex define_constants
7236 Using literal constants inside instruction patterns reduces legibility and
7237 can be a maintenance problem.
7239 To overcome this problem, you may use the @code{define_constants}
7240 expression. It contains a vector of name-value pairs. From that
7241 point on, wherever any of the names appears in the MD file, it is as
7242 if the corresponding value had been written instead. You may use
7243 @code{define_constants} multiple times; each appearance adds more
7244 constants to the table. It is an error to redefine a constant with
7247 To come back to the a29k load multiple example, instead of
7251 [(match_parallel 0 "load_multiple_operation"
7252 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7253 (match_operand:SI 2 "memory_operand" "m"))
7255 (clobber (reg:SI 179))])]
7271 [(match_parallel 0 "load_multiple_operation"
7272 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
7273 (match_operand:SI 2 "memory_operand" "m"))
7275 (clobber (reg:SI R_CR))])]
7280 The constants that are defined with a define_constant are also output
7281 in the insn-codes.h header file as #defines.
7286 @cindex macros in @file{.md} files
7288 Ports often need to define similar patterns for more than one machine
7289 mode or for more than one rtx code. GCC provides some simple macro
7290 facilities to make this process easier.
7293 * Mode Macros:: Generating variations of patterns for different modes.
7294 * Code Macros:: Doing the same for codes.
7298 @subsection Mode Macros
7299 @cindex mode macros in @file{.md} files
7301 Ports often need to define similar patterns for two or more different modes.
7306 If a processor has hardware support for both single and double
7307 floating-point arithmetic, the @code{SFmode} patterns tend to be
7308 very similar to the @code{DFmode} ones.
7311 If a port uses @code{SImode} pointers in one configuration and
7312 @code{DImode} pointers in another, it will usually have very similar
7313 @code{SImode} and @code{DImode} patterns for manipulating pointers.
7316 Mode macros allow several patterns to be instantiated from one
7317 @file{.md} file template. They can be used with any type of
7318 rtx-based construct, such as a @code{define_insn},
7319 @code{define_split}, or @code{define_peephole2}.
7322 * Defining Mode Macros:: Defining a new mode macro.
7323 * Substitutions:: Combining mode macros with substitutions
7324 * Examples:: Examples
7327 @node Defining Mode Macros
7328 @subsubsection Defining Mode Macros
7329 @findex define_mode_macro
7331 The syntax for defining a mode macro is:
7334 (define_mode_macro @var{name} [(@var{mode1} "@var{cond1}") ... (@var{moden} "@var{condn}")])
7337 This allows subsequent @file{.md} file constructs to use the mode suffix
7338 @code{:@var{name}}. Every construct that does so will be expanded
7339 @var{n} times, once with every use of @code{:@var{name}} replaced by
7340 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
7341 and so on. In the expansion for a particular @var{modei}, every
7342 C condition will also require that @var{condi} be true.
7347 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7350 defines a new mode suffix @code{:P}. Every construct that uses
7351 @code{:P} will be expanded twice, once with every @code{:P} replaced
7352 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
7353 The @code{:SI} version will only apply if @code{Pmode == SImode} and
7354 the @code{:DI} version will only apply if @code{Pmode == DImode}.
7356 As with other @file{.md} conditions, an empty string is treated
7357 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
7358 to @code{@var{mode}}. For example:
7361 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
7364 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
7365 but that the @code{:SI} expansion has no such constraint.
7367 Macros are applied in the order they are defined. This can be
7368 significant if two macros are used in a construct that requires
7369 substitutions. @xref{Substitutions}.
7372 @subsubsection Substitution in Mode Macros
7373 @findex define_mode_attr
7375 If an @file{.md} file construct uses mode macros, each version of the
7376 construct will often need slightly different strings or modes. For
7381 When a @code{define_expand} defines several @code{add@var{m}3} patterns
7382 (@pxref{Standard Names}), each expander will need to use the
7383 appropriate mode name for @var{m}.
7386 When a @code{define_insn} defines several instruction patterns,
7387 each instruction will often use a different assembler mnemonic.
7390 When a @code{define_insn} requires operands with different modes,
7391 using a macro for one of the operand modes usually requires a specific
7392 mode for the other operand(s).
7395 GCC supports such variations through a system of ``mode attributes''.
7396 There are two standard attributes: @code{mode}, which is the name of
7397 the mode in lower case, and @code{MODE}, which is the same thing in
7398 upper case. You can define other attributes using:
7401 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") ... (@var{moden} "@var{valuen}")])
7404 where @var{name} is the name of the attribute and @var{valuei}
7405 is the value associated with @var{modei}.
7407 When GCC replaces some @var{:macro} with @var{:mode}, it will scan
7408 each string and mode in the pattern for sequences of the form
7409 @code{<@var{macro}:@var{attr}>}, where @var{attr} is the name of a
7410 mode attribute. If the attribute is defined for @var{mode}, the whole
7411 @code{<...>} sequence will be replaced by the appropriate attribute
7414 For example, suppose an @file{.md} file has:
7417 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
7418 (define_mode_attr load [(SI "lw") (DI "ld")])
7421 If one of the patterns that uses @code{:P} contains the string
7422 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
7423 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
7426 Here is an example of using an attribute for a mode:
7429 (define_mode_macro LONG [SI DI])
7430 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
7432 (sign_extend:LONG (match_operand:<LONG:SHORT> ...)) ...)
7435 The @code{@var{macro}:} prefix may be omitted, in which case the
7436 substitution will be attempted for every macro expansion.
7439 @subsubsection Mode Macro Examples
7441 Here is an example from the MIPS port. It defines the following
7442 modes and attributes (among others):
7445 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
7446 (define_mode_attr d [(SI "") (DI "d")])
7449 and uses the following template to define both @code{subsi3}
7453 (define_insn "sub<mode>3"
7454 [(set (match_operand:GPR 0 "register_operand" "=d")
7455 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
7456 (match_operand:GPR 2 "register_operand" "d")))]
7459 [(set_attr "type" "arith")
7460 (set_attr "mode" "<MODE>")])
7463 This is exactly equivalent to:
7466 (define_insn "subsi3"
7467 [(set (match_operand:SI 0 "register_operand" "=d")
7468 (minus:SI (match_operand:SI 1 "register_operand" "d")
7469 (match_operand:SI 2 "register_operand" "d")))]
7472 [(set_attr "type" "arith")
7473 (set_attr "mode" "SI")])
7475 (define_insn "subdi3"
7476 [(set (match_operand:DI 0 "register_operand" "=d")
7477 (minus:DI (match_operand:DI 1 "register_operand" "d")
7478 (match_operand:DI 2 "register_operand" "d")))]
7481 [(set_attr "type" "arith")
7482 (set_attr "mode" "DI")])
7486 @subsection Code Macros
7487 @cindex code macros in @file{.md} files
7488 @findex define_code_macro
7489 @findex define_code_attr
7491 Code macros operate in a similar way to mode macros. @xref{Mode Macros}.
7496 (define_code_macro @var{name} [(@var{code1} "@var{cond1}") ... (@var{coden} "@var{condn}")])
7499 defines a pseudo rtx code @var{name} that can be instantiated as
7500 @var{codei} if condition @var{condi} is true. Each @var{codei}
7501 must have the same rtx format. @xref{RTL Classes}.
7503 As with mode macros, each pattern that uses @var{name} will be
7504 expanded @var{n} times, once with all uses of @var{name} replaced by
7505 @var{code1}, once with all uses replaced by @var{code2}, and so on.
7506 @xref{Defining Mode Macros}.
7508 It is possible to define attributes for codes as well as for modes.
7509 There are two standard code attributes: @code{code}, the name of the
7510 code in lower case, and @code{CODE}, the name of the code in upper case.
7511 Other attributes are defined using:
7514 (define_code_attr @var{name} [(@var{code1} "@var{value1}") ... (@var{coden} "@var{valuen}")])
7517 Here's an example of code macros in action, taken from the MIPS port:
7520 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
7521 eq ne gt ge lt le gtu geu ltu leu])
7523 (define_expand "b<code>"
7525 (if_then_else (any_cond:CC (cc0)
7527 (label_ref (match_operand 0 ""))
7531 gen_conditional_branch (operands, <CODE>);
7536 This is equivalent to:
7539 (define_expand "bunordered"
7541 (if_then_else (unordered:CC (cc0)
7543 (label_ref (match_operand 0 ""))
7547 gen_conditional_branch (operands, UNORDERED);
7551 (define_expand "bordered"
7553 (if_then_else (ordered:CC (cc0)
7555 (label_ref (match_operand 0 ""))
7559 gen_conditional_branch (operands, ORDERED);