1 @c Copyright (C) 1988-2018 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 A @code{define_insn} expression is used to define instruction patterns
109 to which insns may be matched. A @code{define_insn} expression contains
110 an incomplete RTL expression, with pieces to be filled in later, operand
111 constraints that restrict how the pieces can be filled in, and an output
112 template or C code to generate the assembler output.
114 A @code{define_insn} is an RTL expression containing four or five operands:
118 An optional name. The presence of a name indicates that this instruction
119 pattern can perform a certain standard job for the RTL-generation
120 pass of the compiler. This pass knows certain names and will use
121 the instruction patterns with those names, if the names are defined
122 in the machine description.
124 The absence of a name is indicated by writing an empty string
125 where the name should go. Nameless instruction patterns are never
126 used for generating RTL code, but they may permit several simpler insns
127 to be combined later on.
129 Names that are not thus known and used in RTL-generation have no
130 effect; they are equivalent to no name at all.
132 For the purpose of debugging the compiler, you may also specify a
133 name beginning with the @samp{*} character. Such a name is used only
134 for identifying the instruction in RTL dumps; it is equivalent to having
135 a nameless pattern for all other purposes. Names beginning with the
136 @samp{*} character are not required to be unique.
139 The @dfn{RTL template}: This is a vector of incomplete RTL expressions
140 which describe the semantics of the instruction (@pxref{RTL Template}).
141 It is incomplete because it may contain @code{match_operand},
142 @code{match_operator}, and @code{match_dup} expressions that stand for
143 operands of the instruction.
145 If the vector has multiple elements, the RTL template is treated as a
146 @code{parallel} expression.
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 The condition: This is a string which contains a C expression. When the
152 compiler attempts to match RTL against a pattern, the condition is
153 evaluated. If the condition evaluates to @code{true}, the match is
154 permitted. The condition may be an empty string, which is treated
155 as always @code{true}.
157 @cindex named patterns and conditions
158 For a named pattern, the condition may not depend on the data in the
159 insn being matched, but only the target-machine-type flags. The compiler
160 needs to test these conditions during initialization in order to learn
161 exactly which named instructions are available in a particular run.
164 For nameless patterns, the condition is applied only when matching an
165 individual insn, and only after the insn has matched the pattern's
166 recognition template. The insn's operands may be found in the vector
169 An instruction condition cannot become more restrictive as compilation
170 progresses. If the condition accepts a particular RTL instruction at
171 one stage of compilation, it must continue to accept that instruction
172 until the final pass. For example, @samp{!reload_completed} and
173 @samp{can_create_pseudo_p ()} are both invalid instruction conditions,
174 because they are true during the earlier RTL passes and false during
175 the later ones. For the same reason, if a condition accepts an
176 instruction before register allocation, it cannot later try to control
177 register allocation by excluding certain register or value combinations.
179 Although a condition cannot become more restrictive as compilation
180 progresses, the condition for a nameless pattern @emph{can} become
181 more permissive. For example, a nameless instruction can require
182 @samp{reload_completed} to be true, in which case it only matches
183 after register allocation.
186 The @dfn{output template} or @dfn{output statement}: This is either
187 a string, or a fragment of C code which returns a string.
189 When simple substitution isn't general enough, you can specify a piece
190 of C code to compute the output. @xref{Output Statement}.
193 The @dfn{insn attributes}: This is an optional vector containing the values of
194 attributes for insns matching this pattern (@pxref{Insn Attributes}).
198 @section Example of @code{define_insn}
199 @cindex @code{define_insn} example
201 Here is an example of an instruction pattern, taken from the machine
202 description for the 68000/68020.
207 (match_operand:SI 0 "general_operand" "rm"))]
211 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
213 return \"cmpl #0,%0\";
218 This can also be written using braced strings:
223 (match_operand:SI 0 "general_operand" "rm"))]
226 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
232 This describes an instruction which sets the condition codes based on the
233 value of a general operand. It has no condition, so any insn with an RTL
234 description of the form shown may be matched to this pattern. The name
235 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL
236 generation pass that, when it is necessary to test such a value, an insn
237 to do so can be constructed using this pattern.
239 The output control string is a piece of C code which chooses which
240 output template to return based on the kind of operand and the specific
241 type of CPU for which code is being generated.
243 @samp{"rm"} is an operand constraint. Its meaning is explained below.
246 @section RTL Template
247 @cindex RTL insn template
248 @cindex generating insns
249 @cindex insns, generating
250 @cindex recognizing insns
251 @cindex insns, recognizing
253 The RTL template is used to define which insns match the particular pattern
254 and how to find their operands. For named patterns, the RTL template also
255 says how to construct an insn from specified operands.
257 Construction involves substituting specified operands into a copy of the
258 template. Matching involves determining the values that serve as the
259 operands in the insn being matched. Both of these activities are
260 controlled by special expression types that direct matching and
261 substitution of the operands.
264 @findex match_operand
265 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
266 This expression is a placeholder for operand number @var{n} of
267 the insn. When constructing an insn, operand number @var{n}
268 will be substituted at this point. When matching an insn, whatever
269 appears at this position in the insn will be taken as operand
270 number @var{n}; but it must satisfy @var{predicate} or this instruction
271 pattern will not match at all.
273 Operand numbers must be chosen consecutively counting from zero in
274 each instruction pattern. There may be only one @code{match_operand}
275 expression in the pattern for each operand number. Usually operands
276 are numbered in the order of appearance in @code{match_operand}
277 expressions. In the case of a @code{define_expand}, any operand numbers
278 used only in @code{match_dup} expressions have higher values than all
279 other operand numbers.
281 @var{predicate} is a string that is the name of a function that
282 accepts two arguments, an expression and a machine mode.
283 @xref{Predicates}. During matching, the function will be called with
284 the putative operand as the expression and @var{m} as the mode
285 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
286 which normally causes @var{predicate} to accept any mode). If it
287 returns zero, this instruction pattern fails to match.
288 @var{predicate} may be an empty string; then it means no test is to be
289 done on the operand, so anything which occurs in this position is
292 Most of the time, @var{predicate} will reject modes other than @var{m}---but
293 not always. For example, the predicate @code{address_operand} uses
294 @var{m} as the mode of memory ref that the address should be valid for.
295 Many predicates accept @code{const_int} nodes even though their mode is
298 @var{constraint} controls reloading and the choice of the best register
299 class to use for a value, as explained later (@pxref{Constraints}).
300 If the constraint would be an empty string, it can be omitted.
302 People are often unclear on the difference between the constraint and the
303 predicate. The predicate helps decide whether a given insn matches the
304 pattern. The constraint plays no role in this decision; instead, it
305 controls various decisions in the case of an insn which does match.
307 @findex match_scratch
308 @item (match_scratch:@var{m} @var{n} @var{constraint})
309 This expression is also a placeholder for operand number @var{n}
310 and indicates that operand must be a @code{scratch} or @code{reg}
313 When matching patterns, this is equivalent to
316 (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint})
319 but, when generating RTL, it produces a (@code{scratch}:@var{m})
322 If the last few expressions in a @code{parallel} are @code{clobber}
323 expressions whose operands are either a hard register or
324 @code{match_scratch}, the combiner can add or delete them when
325 necessary. @xref{Side Effects}.
328 @item (match_dup @var{n})
329 This expression is also a placeholder for operand number @var{n}.
330 It is used when the operand needs to appear more than once in the
333 In construction, @code{match_dup} acts just like @code{match_operand}:
334 the operand is substituted into the insn being constructed. But in
335 matching, @code{match_dup} behaves differently. It assumes that operand
336 number @var{n} has already been determined by a @code{match_operand}
337 appearing earlier in the recognition template, and it matches only an
338 identical-looking expression.
340 Note that @code{match_dup} should not be used to tell the compiler that
341 a particular register is being used for two operands (example:
342 @code{add} that adds one register to another; the second register is
343 both an input operand and the output operand). Use a matching
344 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
345 operand is used in two places in the template, such as an instruction
346 that computes both a quotient and a remainder, where the opcode takes
347 two input operands but the RTL template has to refer to each of those
348 twice; once for the quotient pattern and once for the remainder pattern.
350 @findex match_operator
351 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
352 This pattern is a kind of placeholder for a variable RTL expression
355 When constructing an insn, it stands for an RTL expression whose
356 expression code is taken from that of operand @var{n}, and whose
357 operands are constructed from the patterns @var{operands}.
359 When matching an expression, it matches an expression if the function
360 @var{predicate} returns nonzero on that expression @emph{and} the
361 patterns @var{operands} match the operands of the expression.
363 Suppose that the function @code{commutative_operator} is defined as
364 follows, to match any expression whose operator is one of the
365 commutative arithmetic operators of RTL and whose mode is @var{mode}:
369 commutative_integer_operator (x, mode)
373 enum rtx_code code = GET_CODE (x);
374 if (GET_MODE (x) != mode)
376 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
377 || code == EQ || code == NE);
381 Then the following pattern will match any RTL expression consisting
382 of a commutative operator applied to two general operands:
385 (match_operator:SI 3 "commutative_operator"
386 [(match_operand:SI 1 "general_operand" "g")
387 (match_operand:SI 2 "general_operand" "g")])
390 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
391 because the expressions to be matched all contain two operands.
393 When this pattern does match, the two operands of the commutative
394 operator are recorded as operands 1 and 2 of the insn. (This is done
395 by the two instances of @code{match_operand}.) Operand 3 of the insn
396 will be the entire commutative expression: use @code{GET_CODE
397 (operands[3])} to see which commutative operator was used.
399 The machine mode @var{m} of @code{match_operator} works like that of
400 @code{match_operand}: it is passed as the second argument to the
401 predicate function, and that function is solely responsible for
402 deciding whether the expression to be matched ``has'' that mode.
404 When constructing an insn, argument 3 of the gen-function will specify
405 the operation (i.e.@: the expression code) for the expression to be
406 made. It should be an RTL expression, whose expression code is copied
407 into a new expression whose operands are arguments 1 and 2 of the
408 gen-function. The subexpressions of argument 3 are not used;
409 only its expression code matters.
411 When @code{match_operator} is used in a pattern for matching an insn,
412 it usually best if the operand number of the @code{match_operator}
413 is higher than that of the actual operands of the insn. This improves
414 register allocation because the register allocator often looks at
415 operands 1 and 2 of insns to see if it can do register tying.
417 There is no way to specify constraints in @code{match_operator}. The
418 operand of the insn which corresponds to the @code{match_operator}
419 never has any constraints because it is never reloaded as a whole.
420 However, if parts of its @var{operands} are matched by
421 @code{match_operand} patterns, those parts may have constraints of
425 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
426 Like @code{match_dup}, except that it applies to operators instead of
427 operands. When constructing an insn, operand number @var{n} will be
428 substituted at this point. But in matching, @code{match_op_dup} behaves
429 differently. It assumes that operand number @var{n} has already been
430 determined by a @code{match_operator} appearing earlier in the
431 recognition template, and it matches only an identical-looking
434 @findex match_parallel
435 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
436 This pattern is a placeholder for an insn that consists of a
437 @code{parallel} expression with a variable number of elements. This
438 expression should only appear at the top level of an insn pattern.
440 When constructing an insn, operand number @var{n} will be substituted at
441 this point. When matching an insn, it matches if the body of the insn
442 is a @code{parallel} expression with at least as many elements as the
443 vector of @var{subpat} expressions in the @code{match_parallel}, if each
444 @var{subpat} matches the corresponding element of the @code{parallel},
445 @emph{and} the function @var{predicate} returns nonzero on the
446 @code{parallel} that is the body of the insn. It is the responsibility
447 of the predicate to validate elements of the @code{parallel} beyond
448 those listed in the @code{match_parallel}.
450 A typical use of @code{match_parallel} is to match load and store
451 multiple expressions, which can contain a variable number of elements
452 in a @code{parallel}. For example,
456 [(match_parallel 0 "load_multiple_operation"
457 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
458 (match_operand:SI 2 "memory_operand" "m"))
460 (clobber (reg:SI 179))])]
465 This example comes from @file{a29k.md}. The function
466 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
467 that subsequent elements in the @code{parallel} are the same as the
468 @code{set} in the pattern, except that they are referencing subsequent
469 registers and memory locations.
471 An insn that matches this pattern might look like:
475 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
477 (clobber (reg:SI 179))
479 (mem:SI (plus:SI (reg:SI 100)
482 (mem:SI (plus:SI (reg:SI 100)
486 @findex match_par_dup
487 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
488 Like @code{match_op_dup}, but for @code{match_parallel} instead of
489 @code{match_operator}.
493 @node Output Template
494 @section Output Templates and Operand Substitution
495 @cindex output templates
496 @cindex operand substitution
498 @cindex @samp{%} in template
500 The @dfn{output template} is a string which specifies how to output the
501 assembler code for an instruction pattern. Most of the template is a
502 fixed string which is output literally. The character @samp{%} is used
503 to specify where to substitute an operand; it can also be used to
504 identify places where different variants of the assembler require
507 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
508 operand @var{n} at that point in the string.
510 @samp{%} followed by a letter and a digit says to output an operand in an
511 alternate fashion. Four letters have standard, built-in meanings described
512 below. The machine description macro @code{PRINT_OPERAND} can define
513 additional letters with nonstandard meanings.
515 @samp{%c@var{digit}} can be used to substitute an operand that is a
516 constant value without the syntax that normally indicates an immediate
519 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
520 the constant is negated before printing.
522 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
523 memory reference, with the actual operand treated as the address. This may
524 be useful when outputting a ``load address'' instruction, because often the
525 assembler syntax for such an instruction requires you to write the operand
526 as if it were a memory reference.
528 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
531 @samp{%=} outputs a number which is unique to each instruction in the
532 entire compilation. This is useful for making local labels to be
533 referred to more than once in a single template that generates multiple
534 assembler instructions.
536 @samp{%} followed by a punctuation character specifies a substitution that
537 does not use an operand. Only one case is standard: @samp{%%} outputs a
538 @samp{%} into the assembler code. Other nonstandard cases can be
539 defined in the @code{PRINT_OPERAND} macro. You must also define
540 which punctuation characters are valid with the
541 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
545 The template may generate multiple assembler instructions. Write the text
546 for the instructions, with @samp{\;} between them.
548 @cindex matching operands
549 When the RTL contains two operands which are required by constraint to match
550 each other, the output template must refer only to the lower-numbered operand.
551 Matching operands are not always identical, and the rest of the compiler
552 arranges to put the proper RTL expression for printing into the lower-numbered
555 One use of nonstandard letters or punctuation following @samp{%} is to
556 distinguish between different assembler languages for the same machine; for
557 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
558 requires periods in most opcode names, while MIT syntax does not. For
559 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
560 syntax. The same file of patterns is used for both kinds of output syntax,
561 but the character sequence @samp{%.} is used in each place where Motorola
562 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
563 defines the sequence to output a period; the macro for MIT syntax defines
566 @cindex @code{#} in template
567 As a special case, a template consisting of the single character @code{#}
568 instructs the compiler to first split the insn, and then output the
569 resulting instructions separately. This helps eliminate redundancy in the
570 output templates. If you have a @code{define_insn} that needs to emit
571 multiple assembler instructions, and there is a matching @code{define_split}
572 already defined, then you can simply use @code{#} as the output template
573 instead of writing an output template that emits the multiple assembler
576 Note that @code{#} only has an effect while generating assembly code;
577 it does not affect whether a split occurs earlier. An associated
578 @code{define_split} must exist and it must be suitable for use after
581 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
582 of the form @samp{@{option0|option1|option2@}} in the templates. These
583 describe multiple variants of assembler language syntax.
584 @xref{Instruction Output}.
586 @node Output Statement
587 @section C Statements for Assembler Output
588 @cindex output statements
589 @cindex C statements for assembler output
590 @cindex generating assembler output
592 Often a single fixed template string cannot produce correct and efficient
593 assembler code for all the cases that are recognized by a single
594 instruction pattern. For example, the opcodes may depend on the kinds of
595 operands; or some unfortunate combinations of operands may require extra
596 machine instructions.
598 If the output control string starts with a @samp{@@}, then it is actually
599 a series of templates, each on a separate line. (Blank lines and
600 leading spaces and tabs are ignored.) The templates correspond to the
601 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
602 if a target machine has a two-address add instruction @samp{addr} to add
603 into a register and another @samp{addm} to add a register to memory, you
604 might write this pattern:
607 (define_insn "addsi3"
608 [(set (match_operand:SI 0 "general_operand" "=r,m")
609 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
610 (match_operand:SI 2 "general_operand" "g,r")))]
617 @cindex @code{*} in template
618 @cindex asterisk in template
619 If the output control string starts with a @samp{*}, then it is not an
620 output template but rather a piece of C program that should compute a
621 template. It should execute a @code{return} statement to return the
622 template-string you want. Most such templates use C string literals, which
623 require doublequote characters to delimit them. To include these
624 doublequote characters in the string, prefix each one with @samp{\}.
626 If the output control string is written as a brace block instead of a
627 double-quoted string, it is automatically assumed to be C code. In that
628 case, it is not necessary to put in a leading asterisk, or to escape the
629 doublequotes surrounding C string literals.
631 The operands may be found in the array @code{operands}, whose C data type
634 It is very common to select different ways of generating assembler code
635 based on whether an immediate operand is within a certain range. Be
636 careful when doing this, because the result of @code{INTVAL} is an
637 integer on the host machine. If the host machine has more bits in an
638 @code{int} than the target machine has in the mode in which the constant
639 will be used, then some of the bits you get from @code{INTVAL} will be
640 superfluous. For proper results, you must carefully disregard the
641 values of those bits.
643 @findex output_asm_insn
644 It is possible to output an assembler instruction and then go on to output
645 or compute more of them, using the subroutine @code{output_asm_insn}. This
646 receives two arguments: a template-string and a vector of operands. The
647 vector may be @code{operands}, or it may be another array of @code{rtx}
648 that you declare locally and initialize yourself.
650 @findex which_alternative
651 When an insn pattern has multiple alternatives in its constraints, often
652 the appearance of the assembler code is determined mostly by which alternative
653 was matched. When this is so, the C code can test the variable
654 @code{which_alternative}, which is the ordinal number of the alternative
655 that was actually satisfied (0 for the first, 1 for the second alternative,
658 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
659 for registers and @samp{clrmem} for memory locations. Here is how
660 a pattern could use @code{which_alternative} to choose between them:
664 [(set (match_operand:SI 0 "general_operand" "=r,m")
668 return (which_alternative == 0
669 ? "clrreg %0" : "clrmem %0");
673 The example above, where the assembler code to generate was
674 @emph{solely} determined by the alternative, could also have been specified
675 as follows, having the output control string start with a @samp{@@}:
680 [(set (match_operand:SI 0 "general_operand" "=r,m")
689 If you just need a little bit of C code in one (or a few) alternatives,
690 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
695 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
700 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
708 @cindex operand predicates
709 @cindex operator predicates
711 A predicate determines whether a @code{match_operand} or
712 @code{match_operator} expression matches, and therefore whether the
713 surrounding instruction pattern will be used for that combination of
714 operands. GCC has a number of machine-independent predicates, and you
715 can define machine-specific predicates as needed. By convention,
716 predicates used with @code{match_operand} have names that end in
717 @samp{_operand}, and those used with @code{match_operator} have names
718 that end in @samp{_operator}.
720 All predicates are boolean functions (in the mathematical sense) of
721 two arguments: the RTL expression that is being considered at that
722 position in the instruction pattern, and the machine mode that the
723 @code{match_operand} or @code{match_operator} specifies. In this
724 section, the first argument is called @var{op} and the second argument
725 @var{mode}. Predicates can be called from C as ordinary two-argument
726 functions; this can be useful in output templates or other
727 machine-specific code.
729 Operand predicates can allow operands that are not actually acceptable
730 to the hardware, as long as the constraints give reload the ability to
731 fix them up (@pxref{Constraints}). However, GCC will usually generate
732 better code if the predicates specify the requirements of the machine
733 instructions as closely as possible. Reload cannot fix up operands
734 that must be constants (``immediate operands''); you must use a
735 predicate that allows only constants, or else enforce the requirement
736 in the extra condition.
738 @cindex predicates and machine modes
739 @cindex normal predicates
740 @cindex special predicates
741 Most predicates handle their @var{mode} argument in a uniform manner.
742 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
743 any mode. If @var{mode} is anything else, then @var{op} must have the
744 same mode, unless @var{op} is a @code{CONST_INT} or integer
745 @code{CONST_DOUBLE}. These RTL expressions always have
746 @code{VOIDmode}, so it would be counterproductive to check that their
747 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
748 integer @code{CONST_DOUBLE} check that the value stored in the
749 constant will fit in the requested mode.
751 Predicates with this behavior are called @dfn{normal}.
752 @command{genrecog} can optimize the instruction recognizer based on
753 knowledge of how normal predicates treat modes. It can also diagnose
754 certain kinds of common errors in the use of normal predicates; for
755 instance, it is almost always an error to use a normal predicate
756 without specifying a mode.
758 Predicates that do something different with their @var{mode} argument
759 are called @dfn{special}. The generic predicates
760 @code{address_operand} and @code{pmode_register_operand} are special
761 predicates. @command{genrecog} does not do any optimizations or
762 diagnosis when special predicates are used.
765 * Machine-Independent Predicates:: Predicates available to all back ends.
766 * Defining Predicates:: How to write machine-specific predicate
770 @node Machine-Independent Predicates
771 @subsection Machine-Independent Predicates
772 @cindex machine-independent predicates
773 @cindex generic predicates
775 These are the generic predicates available to all back ends. They are
776 defined in @file{recog.c}. The first category of predicates allow
777 only constant, or @dfn{immediate}, operands.
779 @defun immediate_operand
780 This predicate allows any sort of constant that fits in @var{mode}.
781 It is an appropriate choice for instructions that take operands that
785 @defun const_int_operand
786 This predicate allows any @code{CONST_INT} expression that fits in
787 @var{mode}. It is an appropriate choice for an immediate operand that
788 does not allow a symbol or label.
791 @defun const_double_operand
792 This predicate accepts any @code{CONST_DOUBLE} expression that has
793 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
794 accept @code{CONST_INT}. It is intended for immediate floating point
799 The second category of predicates allow only some kind of machine
802 @defun register_operand
803 This predicate allows any @code{REG} or @code{SUBREG} expression that
804 is valid for @var{mode}. It is often suitable for arithmetic
805 instruction operands on a RISC machine.
808 @defun pmode_register_operand
809 This is a slight variant on @code{register_operand} which works around
810 a limitation in the machine-description reader.
813 (match_operand @var{n} "pmode_register_operand" @var{constraint})
820 (match_operand:P @var{n} "register_operand" @var{constraint})
824 would mean, if the machine-description reader accepted @samp{:P}
825 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
826 alias for some other mode, and might vary with machine-specific
827 options. @xref{Misc}.
830 @defun scratch_operand
831 This predicate allows hard registers and @code{SCRATCH} expressions,
832 but not pseudo-registers. It is used internally by @code{match_scratch};
833 it should not be used directly.
837 The third category of predicates allow only some kind of memory reference.
839 @defun memory_operand
840 This predicate allows any valid reference to a quantity of mode
841 @var{mode} in memory, as determined by the weak form of
842 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
845 @defun address_operand
846 This predicate is a little unusual; it allows any operand that is a
847 valid expression for the @emph{address} of a quantity of mode
848 @var{mode}, again determined by the weak form of
849 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
850 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
851 @code{memory_operand}, then @var{exp} is acceptable to
852 @code{address_operand}. Note that @var{exp} does not necessarily have
856 @defun indirect_operand
857 This is a stricter form of @code{memory_operand} which allows only
858 memory references with a @code{general_operand} as the address
859 expression. New uses of this predicate are discouraged, because
860 @code{general_operand} is very permissive, so it's hard to tell what
861 an @code{indirect_operand} does or does not allow. If a target has
862 different requirements for memory operands for different instructions,
863 it is better to define target-specific predicates which enforce the
864 hardware's requirements explicitly.
868 This predicate allows a memory reference suitable for pushing a value
869 onto the stack. This will be a @code{MEM} which refers to
870 @code{stack_pointer_rtx}, with a side-effect in its address expression
871 (@pxref{Incdec}); which one is determined by the
872 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
876 This predicate allows a memory reference suitable for popping a value
877 off the stack. Again, this will be a @code{MEM} referring to
878 @code{stack_pointer_rtx}, with a side-effect in its address
879 expression. However, this time @code{STACK_POP_CODE} is expected.
883 The fourth category of predicates allow some combination of the above
886 @defun nonmemory_operand
887 This predicate allows any immediate or register operand valid for @var{mode}.
890 @defun nonimmediate_operand
891 This predicate allows any register or memory operand valid for @var{mode}.
894 @defun general_operand
895 This predicate allows any immediate, register, or memory operand
896 valid for @var{mode}.
900 Finally, there are two generic operator predicates.
902 @defun comparison_operator
903 This predicate matches any expression which performs an arithmetic
904 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
908 @defun ordered_comparison_operator
909 This predicate matches any expression which performs an arithmetic
910 comparison in @var{mode} and whose expression code is valid for integer
911 modes; that is, the expression code will be one of @code{eq}, @code{ne},
912 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
913 @code{ge}, @code{geu}.
916 @node Defining Predicates
917 @subsection Defining Machine-Specific Predicates
918 @cindex defining predicates
919 @findex define_predicate
920 @findex define_special_predicate
922 Many machines have requirements for their operands that cannot be
923 expressed precisely using the generic predicates. You can define
924 additional predicates using @code{define_predicate} and
925 @code{define_special_predicate} expressions. These expressions have
930 The name of the predicate, as it will be referred to in
931 @code{match_operand} or @code{match_operator} expressions.
934 An RTL expression which evaluates to true if the predicate allows the
935 operand @var{op}, false if it does not. This expression can only use
936 the following RTL codes:
940 When written inside a predicate expression, a @code{MATCH_OPERAND}
941 expression evaluates to true if the predicate it names would allow
942 @var{op}. The operand number and constraint are ignored. Due to
943 limitations in @command{genrecog}, you can only refer to generic
944 predicates and predicates that have already been defined.
947 This expression evaluates to true if @var{op} or a specified
948 subexpression of @var{op} has one of a given list of RTX codes.
950 The first operand of this expression is a string constant containing a
951 comma-separated list of RTX code names (in lower case). These are the
952 codes for which the @code{MATCH_CODE} will be true.
954 The second operand is a string constant which indicates what
955 subexpression of @var{op} to examine. If it is absent or the empty
956 string, @var{op} itself is examined. Otherwise, the string constant
957 must be a sequence of digits and/or lowercase letters. Each character
958 indicates a subexpression to extract from the current expression; for
959 the first character this is @var{op}, for the second and subsequent
960 characters it is the result of the previous character. A digit
961 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
962 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
963 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
964 @code{MATCH_CODE} then examines the RTX code of the subexpression
965 extracted by the complete string. It is not possible to extract
966 components of an @code{rtvec} that is not at position 0 within its RTX
970 This expression has one operand, a string constant containing a C
971 expression. The predicate's arguments, @var{op} and @var{mode}, are
972 available with those names in the C expression. The @code{MATCH_TEST}
973 evaluates to true if the C expression evaluates to a nonzero value.
974 @code{MATCH_TEST} expressions must not have side effects.
980 The basic @samp{MATCH_} expressions can be combined using these
981 logical operators, which have the semantics of the C operators
982 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
983 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
984 arbitrary number of arguments; this has exactly the same effect as
985 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
989 An optional block of C code, which should execute
990 @samp{@w{return true}} if the predicate is found to match and
991 @samp{@w{return false}} if it does not. It must not have any side
992 effects. The predicate arguments, @var{op} and @var{mode}, are
993 available with those names.
995 If a code block is present in a predicate definition, then the RTL
996 expression must evaluate to true @emph{and} the code block must
997 execute @samp{@w{return true}} for the predicate to allow the operand.
998 The RTL expression is evaluated first; do not re-check anything in the
999 code block that was checked in the RTL expression.
1002 The program @command{genrecog} scans @code{define_predicate} and
1003 @code{define_special_predicate} expressions to determine which RTX
1004 codes are possibly allowed. You should always make this explicit in
1005 the RTL predicate expression, using @code{MATCH_OPERAND} and
1008 Here is an example of a simple predicate definition, from the IA64
1009 machine description:
1013 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
1014 (define_predicate "small_addr_symbolic_operand"
1015 (and (match_code "symbol_ref")
1016 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1021 And here is another, showing the use of the C block.
1025 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1026 (define_predicate "gr_register_operand"
1027 (match_operand 0 "register_operand")
1030 if (GET_CODE (op) == SUBREG)
1031 op = SUBREG_REG (op);
1034 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1039 Predicates written with @code{define_predicate} automatically include
1040 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1041 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1042 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1043 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1044 kind of constant fits in the requested mode. This is because
1045 target-specific predicates that take constants usually have to do more
1046 stringent value checks anyway. If you need the exact same treatment
1047 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1048 provide, use a @code{MATCH_OPERAND} subexpression to call
1049 @code{const_int_operand}, @code{const_double_operand}, or
1050 @code{immediate_operand}.
1052 Predicates written with @code{define_special_predicate} do not get any
1053 automatic mode checks, and are treated as having special mode handling
1054 by @command{genrecog}.
1056 The program @command{genpreds} is responsible for generating code to
1057 test predicates. It also writes a header file containing function
1058 declarations for all machine-specific predicates. It is not necessary
1059 to declare these predicates in @file{@var{cpu}-protos.h}.
1062 @c Most of this node appears by itself (in a different place) even
1063 @c when the INTERNALS flag is clear. Passages that require the internals
1064 @c manual's context are conditionalized to appear only in the internals manual.
1067 @section Operand Constraints
1068 @cindex operand constraints
1071 Each @code{match_operand} in an instruction pattern can specify
1072 constraints for the operands allowed. The constraints allow you to
1073 fine-tune matching within the set of operands allowed by the
1079 @section Constraints for @code{asm} Operands
1080 @cindex operand constraints, @code{asm}
1081 @cindex constraints, @code{asm}
1082 @cindex @code{asm} constraints
1084 Here are specific details on what constraint letters you can use with
1085 @code{asm} operands.
1087 Constraints can say whether
1088 an operand may be in a register, and which kinds of register; whether the
1089 operand can be a memory reference, and which kinds of address; whether the
1090 operand may be an immediate constant, and which possible values it may
1091 have. Constraints can also require two operands to match.
1092 Side-effects aren't allowed in operands of inline @code{asm}, unless
1093 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1094 that the side-effects will happen exactly once in an instruction that can update
1095 the addressing register.
1099 * Simple Constraints:: Basic use of constraints.
1100 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1101 * Class Preferences:: Constraints guide which hard register to put things in.
1102 * Modifiers:: More precise control over effects of constraints.
1103 * Machine Constraints:: Existing constraints for some particular machines.
1104 * Disable Insn Alternatives:: Disable insn alternatives using attributes.
1105 * Define Constraints:: How to define machine-specific constraints.
1106 * C Constraint Interface:: How to test constraints from C code.
1112 * Simple Constraints:: Basic use of constraints.
1113 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1114 * Modifiers:: More precise control over effects of constraints.
1115 * Machine Constraints:: Special constraints for some particular machines.
1119 @node Simple Constraints
1120 @subsection Simple Constraints
1121 @cindex simple constraints
1123 The simplest kind of constraint is a string full of letters, each of
1124 which describes one kind of operand that is permitted. Here are
1125 the letters that are allowed:
1129 Whitespace characters are ignored and can be inserted at any position
1130 except the first. This enables each alternative for different operands to
1131 be visually aligned in the machine description even if they have different
1132 number of constraints and modifiers.
1134 @cindex @samp{m} in constraint
1135 @cindex memory references in constraints
1137 A memory operand is allowed, with any kind of address that the machine
1138 supports in general.
1139 Note that the letter used for the general memory constraint can be
1140 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1142 @cindex offsettable address
1143 @cindex @samp{o} in constraint
1145 A memory operand is allowed, but only if the address is
1146 @dfn{offsettable}. This means that adding a small integer (actually,
1147 the width in bytes of the operand, as determined by its machine mode)
1148 may be added to the address and the result is also a valid memory
1151 @cindex autoincrement/decrement addressing
1152 For example, an address which is constant is offsettable; so is an
1153 address that is the sum of a register and a constant (as long as a
1154 slightly larger constant is also within the range of address-offsets
1155 supported by the machine); but an autoincrement or autodecrement
1156 address is not offsettable. More complicated indirect/indexed
1157 addresses may or may not be offsettable depending on the other
1158 addressing modes that the machine supports.
1160 Note that in an output operand which can be matched by another
1161 operand, the constraint letter @samp{o} is valid only when accompanied
1162 by both @samp{<} (if the target machine has predecrement addressing)
1163 and @samp{>} (if the target machine has preincrement addressing).
1165 @cindex @samp{V} in constraint
1167 A memory operand that is not offsettable. In other words, anything that
1168 would fit the @samp{m} constraint but not the @samp{o} constraint.
1170 @cindex @samp{<} in constraint
1172 A memory operand with autodecrement addressing (either predecrement or
1173 postdecrement) is allowed. In inline @code{asm} this constraint is only
1174 allowed if the operand is used exactly once in an instruction that can
1175 handle the side-effects. Not using an operand with @samp{<} in constraint
1176 string in the inline @code{asm} pattern at all or using it in multiple
1177 instructions isn't valid, because the side-effects wouldn't be performed
1178 or would be performed more than once. Furthermore, on some targets
1179 the operand with @samp{<} in constraint string must be accompanied by
1180 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1181 or @code{%P0} on IA-64.
1183 @cindex @samp{>} in constraint
1185 A memory operand with autoincrement addressing (either preincrement or
1186 postincrement) is allowed. In inline @code{asm} the same restrictions
1187 as for @samp{<} apply.
1189 @cindex @samp{r} in constraint
1190 @cindex registers in constraints
1192 A register operand is allowed provided that it is in a general
1195 @cindex constants in constraints
1196 @cindex @samp{i} in constraint
1198 An immediate integer operand (one with constant value) is allowed.
1199 This includes symbolic constants whose values will be known only at
1200 assembly time or later.
1202 @cindex @samp{n} in constraint
1204 An immediate integer operand with a known numeric value is allowed.
1205 Many systems cannot support assembly-time constants for operands less
1206 than a word wide. Constraints for these operands should use @samp{n}
1207 rather than @samp{i}.
1209 @cindex @samp{I} in constraint
1210 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1211 Other letters in the range @samp{I} through @samp{P} may be defined in
1212 a machine-dependent fashion to permit immediate integer operands with
1213 explicit integer values in specified ranges. For example, on the
1214 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1215 This is the range permitted as a shift count in the shift
1218 @cindex @samp{E} in constraint
1220 An immediate floating operand (expression code @code{const_double}) is
1221 allowed, but only if the target floating point format is the same as
1222 that of the host machine (on which the compiler is running).
1224 @cindex @samp{F} in constraint
1226 An immediate floating operand (expression code @code{const_double} or
1227 @code{const_vector}) is allowed.
1229 @cindex @samp{G} in constraint
1230 @cindex @samp{H} in constraint
1231 @item @samp{G}, @samp{H}
1232 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1233 permit immediate floating operands in particular ranges of values.
1235 @cindex @samp{s} in constraint
1237 An immediate integer operand whose value is not an explicit integer is
1240 This might appear strange; if an insn allows a constant operand with a
1241 value not known at compile time, it certainly must allow any known
1242 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1243 better code to be generated.
1245 For example, on the 68000 in a fullword instruction it is possible to
1246 use an immediate operand; but if the immediate value is between @minus{}128
1247 and 127, better code results from loading the value into a register and
1248 using the register. This is because the load into the register can be
1249 done with a @samp{moveq} instruction. We arrange for this to happen
1250 by defining the letter @samp{K} to mean ``any integer outside the
1251 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1254 @cindex @samp{g} in constraint
1256 Any register, memory or immediate integer operand is allowed, except for
1257 registers that are not general registers.
1259 @cindex @samp{X} in constraint
1262 Any operand whatsoever is allowed, even if it does not satisfy
1263 @code{general_operand}. This is normally used in the constraint of
1264 a @code{match_scratch} when certain alternatives will not actually
1265 require a scratch register.
1268 Any operand whatsoever is allowed.
1271 @cindex @samp{0} in constraint
1272 @cindex digits in constraint
1273 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1274 An operand that matches the specified operand number is allowed. If a
1275 digit is used together with letters within the same alternative, the
1276 digit should come last.
1278 This number is allowed to be more than a single digit. If multiple
1279 digits are encountered consecutively, they are interpreted as a single
1280 decimal integer. There is scant chance for ambiguity, since to-date
1281 it has never been desirable that @samp{10} be interpreted as matching
1282 either operand 1 @emph{or} operand 0. Should this be desired, one
1283 can use multiple alternatives instead.
1285 @cindex matching constraint
1286 @cindex constraint, matching
1287 This is called a @dfn{matching constraint} and what it really means is
1288 that the assembler has only a single operand that fills two roles
1290 considered separate in the RTL insn. For example, an add insn has two
1291 input operands and one output operand in the RTL, but on most CISC
1294 which @code{asm} distinguishes. For example, an add instruction uses
1295 two input operands and an output operand, but on most CISC
1297 machines an add instruction really has only two operands, one of them an
1298 input-output operand:
1304 Matching constraints are used in these circumstances.
1305 More precisely, the two operands that match must include one input-only
1306 operand and one output-only operand. Moreover, the digit must be a
1307 smaller number than the number of the operand that uses it in the
1311 For operands to match in a particular case usually means that they
1312 are identical-looking RTL expressions. But in a few special cases
1313 specific kinds of dissimilarity are allowed. For example, @code{*x}
1314 as an input operand will match @code{*x++} as an output operand.
1315 For proper results in such cases, the output template should always
1316 use the output-operand's number when printing the operand.
1319 @cindex load address instruction
1320 @cindex push address instruction
1321 @cindex address constraints
1322 @cindex @samp{p} in constraint
1324 An operand that is a valid memory address is allowed. This is
1325 for ``load address'' and ``push address'' instructions.
1327 @findex address_operand
1328 @samp{p} in the constraint must be accompanied by @code{address_operand}
1329 as the predicate in the @code{match_operand}. This predicate interprets
1330 the mode specified in the @code{match_operand} as the mode of the memory
1331 reference for which the address would be valid.
1333 @cindex other register constraints
1334 @cindex extensible constraints
1335 @item @var{other-letters}
1336 Other letters can be defined in machine-dependent fashion to stand for
1337 particular classes of registers or other arbitrary operand types.
1338 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1339 for data, address and floating point registers.
1343 In order to have valid assembler code, each operand must satisfy
1344 its constraint. But a failure to do so does not prevent the pattern
1345 from applying to an insn. Instead, it directs the compiler to modify
1346 the code so that the constraint will be satisfied. Usually this is
1347 done by copying an operand into a register.
1349 Contrast, therefore, the two instruction patterns that follow:
1353 [(set (match_operand:SI 0 "general_operand" "=r")
1354 (plus:SI (match_dup 0)
1355 (match_operand:SI 1 "general_operand" "r")))]
1361 which has two operands, one of which must appear in two places, and
1365 [(set (match_operand:SI 0 "general_operand" "=r")
1366 (plus:SI (match_operand:SI 1 "general_operand" "0")
1367 (match_operand:SI 2 "general_operand" "r")))]
1373 which has three operands, two of which are required by a constraint to be
1374 identical. If we are considering an insn of the form
1377 (insn @var{n} @var{prev} @var{next}
1379 (plus:SI (reg:SI 6) (reg:SI 109)))
1384 the first pattern would not apply at all, because this insn does not
1385 contain two identical subexpressions in the right place. The pattern would
1386 say, ``That does not look like an add instruction; try other patterns''.
1387 The second pattern would say, ``Yes, that's an add instruction, but there
1388 is something wrong with it''. It would direct the reload pass of the
1389 compiler to generate additional insns to make the constraint true. The
1390 results might look like this:
1393 (insn @var{n2} @var{prev} @var{n}
1394 (set (reg:SI 3) (reg:SI 6))
1397 (insn @var{n} @var{n2} @var{next}
1399 (plus:SI (reg:SI 3) (reg:SI 109)))
1403 It is up to you to make sure that each operand, in each pattern, has
1404 constraints that can handle any RTL expression that could be present for
1405 that operand. (When multiple alternatives are in use, each pattern must,
1406 for each possible combination of operand expressions, have at least one
1407 alternative which can handle that combination of operands.) The
1408 constraints don't need to @emph{allow} any possible operand---when this is
1409 the case, they do not constrain---but they must at least point the way to
1410 reloading any possible operand so that it will fit.
1414 If the constraint accepts whatever operands the predicate permits,
1415 there is no problem: reloading is never necessary for this operand.
1417 For example, an operand whose constraints permit everything except
1418 registers is safe provided its predicate rejects registers.
1420 An operand whose predicate accepts only constant values is safe
1421 provided its constraints include the letter @samp{i}. If any possible
1422 constant value is accepted, then nothing less than @samp{i} will do;
1423 if the predicate is more selective, then the constraints may also be
1427 Any operand expression can be reloaded by copying it into a register.
1428 So if an operand's constraints allow some kind of register, it is
1429 certain to be safe. It need not permit all classes of registers; the
1430 compiler knows how to copy a register into another register of the
1431 proper class in order to make an instruction valid.
1433 @cindex nonoffsettable memory reference
1434 @cindex memory reference, nonoffsettable
1436 A nonoffsettable memory reference can be reloaded by copying the
1437 address into a register. So if the constraint uses the letter
1438 @samp{o}, all memory references are taken care of.
1441 A constant operand can be reloaded by allocating space in memory to
1442 hold it as preinitialized data. Then the memory reference can be used
1443 in place of the constant. So if the constraint uses the letters
1444 @samp{o} or @samp{m}, constant operands are not a problem.
1447 If the constraint permits a constant and a pseudo register used in an insn
1448 was not allocated to a hard register and is equivalent to a constant,
1449 the register will be replaced with the constant. If the predicate does
1450 not permit a constant and the insn is re-recognized for some reason, the
1451 compiler will crash. Thus the predicate must always recognize any
1452 objects allowed by the constraint.
1455 If the operand's predicate can recognize registers, but the constraint does
1456 not permit them, it can make the compiler crash. When this operand happens
1457 to be a register, the reload pass will be stymied, because it does not know
1458 how to copy a register temporarily into memory.
1460 If the predicate accepts a unary operator, the constraint applies to the
1461 operand. For example, the MIPS processor at ISA level 3 supports an
1462 instruction which adds two registers in @code{SImode} to produce a
1463 @code{DImode} result, but only if the registers are correctly sign
1464 extended. This predicate for the input operands accepts a
1465 @code{sign_extend} of an @code{SImode} register. Write the constraint
1466 to indicate the type of register that is required for the operand of the
1470 @node Multi-Alternative
1471 @subsection Multiple Alternative Constraints
1472 @cindex multiple alternative constraints
1474 Sometimes a single instruction has multiple alternative sets of possible
1475 operands. For example, on the 68000, a logical-or instruction can combine
1476 register or an immediate value into memory, or it can combine any kind of
1477 operand into a register; but it cannot combine one memory location into
1480 These constraints are represented as multiple alternatives. An alternative
1481 can be described by a series of letters for each operand. The overall
1482 constraint for an operand is made from the letters for this operand
1483 from the first alternative, a comma, the letters for this operand from
1484 the second alternative, a comma, and so on until the last alternative.
1485 All operands for a single instruction must have the same number of
1488 Here is how it is done for fullword logical-or on the 68000:
1491 (define_insn "iorsi3"
1492 [(set (match_operand:SI 0 "general_operand" "=m,d")
1493 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1494 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1498 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1499 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1500 2. The second alternative has @samp{d} (data register) for operand 0,
1501 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1502 @samp{%} in the constraints apply to all the alternatives; their
1503 meaning is explained in the next section (@pxref{Class Preferences}).
1505 If all the operands fit any one alternative, the instruction is valid.
1506 Otherwise, for each alternative, the compiler counts how many instructions
1507 must be added to copy the operands so that that alternative applies.
1508 The alternative requiring the least copying is chosen. If two alternatives
1509 need the same amount of copying, the one that comes first is chosen.
1510 These choices can be altered with the @samp{?} and @samp{!} characters:
1513 @cindex @samp{?} in constraint
1514 @cindex question mark
1516 Disparage slightly the alternative that the @samp{?} appears in,
1517 as a choice when no alternative applies exactly. The compiler regards
1518 this alternative as one unit more costly for each @samp{?} that appears
1521 @cindex @samp{!} in constraint
1522 @cindex exclamation point
1524 Disparage severely the alternative that the @samp{!} appears in.
1525 This alternative can still be used if it fits without reloading,
1526 but if reloading is needed, some other alternative will be used.
1528 @cindex @samp{^} in constraint
1531 This constraint is analogous to @samp{?} but it disparages slightly
1532 the alternative only if the operand with the @samp{^} needs a reload.
1534 @cindex @samp{$} in constraint
1537 This constraint is analogous to @samp{!} but it disparages severely
1538 the alternative only if the operand with the @samp{$} needs a reload.
1541 When an insn pattern has multiple alternatives in its constraints, often
1542 the appearance of the assembler code is determined mostly by which
1543 alternative was matched. When this is so, the C code for writing the
1544 assembler code can use the variable @code{which_alternative}, which is
1545 the ordinal number of the alternative that was actually satisfied (0 for
1546 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1550 So the first alternative for the 68000's logical-or could be written as
1551 @code{"+m" (output) : "ir" (input)}. The second could be @code{"+r"
1552 (output): "irm" (input)}. However, the fact that two memory locations
1553 cannot be used in a single instruction prevents simply using @code{"+rm"
1554 (output) : "irm" (input)}. Using multi-alternatives, this might be
1555 written as @code{"+m,r" (output) : "ir,irm" (input)}. This describes
1556 all the available alternatives to the compiler, allowing it to choose
1557 the most efficient one for the current conditions.
1559 There is no way within the template to determine which alternative was
1560 chosen. However you may be able to wrap your @code{asm} statements with
1561 builtins such as @code{__builtin_constant_p} to achieve the desired results.
1565 @node Class Preferences
1566 @subsection Register Class Preferences
1567 @cindex class preference constraints
1568 @cindex register class preference constraints
1570 @cindex voting between constraint alternatives
1571 The operand constraints have another function: they enable the compiler
1572 to decide which kind of hardware register a pseudo register is best
1573 allocated to. The compiler examines the constraints that apply to the
1574 insns that use the pseudo register, looking for the machine-dependent
1575 letters such as @samp{d} and @samp{a} that specify classes of registers.
1576 The pseudo register is put in whichever class gets the most ``votes''.
1577 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1578 favor of a general register. The machine description says which registers
1579 are considered general.
1581 Of course, on some machines all registers are equivalent, and no register
1582 classes are defined. Then none of this complexity is relevant.
1586 @subsection Constraint Modifier Characters
1587 @cindex modifiers in constraints
1588 @cindex constraint modifier characters
1590 @c prevent bad page break with this line
1591 Here are constraint modifier characters.
1594 @cindex @samp{=} in constraint
1596 Means that this operand is written to by this instruction:
1597 the previous value is discarded and replaced by new data.
1599 @cindex @samp{+} in constraint
1601 Means that this operand is both read and written by the instruction.
1603 When the compiler fixes up the operands to satisfy the constraints,
1604 it needs to know which operands are read by the instruction and
1605 which are written by it. @samp{=} identifies an operand which is only
1606 written; @samp{+} identifies an operand that is both read and written; all
1607 other operands are assumed to only be read.
1609 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1610 first character of the constraint string.
1612 @cindex @samp{&} in constraint
1613 @cindex earlyclobber operand
1615 Means (in a particular alternative) that this operand is an
1616 @dfn{earlyclobber} operand, which is written before the instruction is
1617 finished using the input operands. Therefore, this operand may not lie
1618 in a register that is read by the instruction or as part of any memory
1621 @samp{&} applies only to the alternative in which it is written. In
1622 constraints with multiple alternatives, sometimes one alternative
1623 requires @samp{&} while others do not. See, for example, the
1624 @samp{movdf} insn of the 68000.
1626 A operand which is read by the instruction can be tied to an earlyclobber
1627 operand if its only use as an input occurs before the early result is
1628 written. Adding alternatives of this form often allows GCC to produce
1629 better code when only some of the read operands can be affected by the
1630 earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@.
1632 Furthermore, if the @dfn{earlyclobber} operand is also a read/write
1633 operand, then that operand is written only after it's used.
1635 @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As
1636 @dfn{earlyclobber} operands are always written, a read-only
1637 @dfn{earlyclobber} operand is ill-formed and will be rejected by the
1640 @cindex @samp{%} in constraint
1642 Declares the instruction to be commutative for this operand and the
1643 following operand. This means that the compiler may interchange the
1644 two operands if that is the cheapest way to make all operands fit the
1645 constraints. @samp{%} applies to all alternatives and must appear as
1646 the first character in the constraint. Only read-only operands can use
1650 This is often used in patterns for addition instructions
1651 that really have only two operands: the result must go in one of the
1652 arguments. Here for example, is how the 68000 halfword-add
1653 instruction is defined:
1656 (define_insn "addhi3"
1657 [(set (match_operand:HI 0 "general_operand" "=m,r")
1658 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1659 (match_operand:HI 2 "general_operand" "di,g")))]
1663 GCC can only handle one commutative pair in an asm; if you use more,
1664 the compiler may fail. Note that you need not use the modifier if
1665 the two alternatives are strictly identical; this would only waste
1666 time in the reload pass.
1668 The modifier is not operational after
1669 register allocation, so the result of @code{define_peephole2}
1670 and @code{define_split}s performed after reload cannot rely on
1671 @samp{%} to make the intended insn match.
1673 @cindex @samp{#} in constraint
1675 Says that all following characters, up to the next comma, are to be
1676 ignored as a constraint. They are significant only for choosing
1677 register preferences.
1679 @cindex @samp{*} in constraint
1681 Says that the following character should be ignored when choosing
1682 register preferences. @samp{*} has no effect on the meaning of the
1683 constraint as a constraint, and no effect on reloading. For LRA
1684 @samp{*} additionally disparages slightly the alternative if the
1685 following character matches the operand.
1687 Here is an example: the 68000 has an instruction to sign-extend a
1688 halfword in a data register, and can also sign-extend a value by
1689 copying it into an address register. While either kind of register is
1690 acceptable, the constraints on an address-register destination are
1691 less strict, so it is best if register allocation makes an address
1692 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1693 constraint letter (for data register) is ignored when computing
1694 register preferences.
1697 (define_insn "extendhisi2"
1698 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1700 (match_operand:HI 1 "general_operand" "0,g")))]
1706 @node Machine Constraints
1707 @subsection Constraints for Particular Machines
1708 @cindex machine specific constraints
1709 @cindex constraints, machine specific
1711 Whenever possible, you should use the general-purpose constraint letters
1712 in @code{asm} arguments, since they will convey meaning more readily to
1713 people reading your code. Failing that, use the constraint letters
1714 that usually have very similar meanings across architectures. The most
1715 commonly used constraints are @samp{m} and @samp{r} (for memory and
1716 general-purpose registers respectively; @pxref{Simple Constraints}), and
1717 @samp{I}, usually the letter indicating the most common
1718 immediate-constant format.
1720 Each architecture defines additional constraints. These constraints
1721 are used by the compiler itself for instruction generation, as well as
1722 for @code{asm} statements; therefore, some of the constraints are not
1723 particularly useful for @code{asm}. Here is a summary of some of the
1724 machine-dependent constraints available on some particular machines;
1725 it includes both constraints that are useful for @code{asm} and
1726 constraints that aren't. The compiler source file mentioned in the
1727 table heading for each architecture is the definitive reference for
1728 the meanings of that architecture's constraints.
1730 @c Please keep this table alphabetized by target!
1732 @item AArch64 family---@file{config/aarch64/constraints.md}
1735 The stack pointer register (@code{SP})
1738 Floating point register, Advanced SIMD vector register or SVE vector register
1741 One of the low eight SVE predicate registers (@code{P0} to @code{P7})
1744 Any of the SVE predicate registers (@code{P0} to @code{P15})
1747 Integer constant that is valid as an immediate operand in an @code{ADD}
1751 Integer constant that is valid as an immediate operand in a @code{SUB}
1752 instruction (once negated)
1755 Integer constant that can be used with a 32-bit logical instruction
1758 Integer constant that can be used with a 64-bit logical instruction
1761 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1762 pseudo instruction. The @code{MOV} may be assembled to one of several different
1763 machine instructions depending on the value
1766 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1770 An absolute symbolic address or a label reference
1773 Floating point constant zero
1776 Integer constant zero
1779 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1780 within 4GB of the instruction
1783 A memory address which uses a single base register with no offset
1786 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1792 @item ARC ---@file{config/arc/constraints.md}
1795 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1796 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1797 option is in effect.
1800 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1801 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1802 This constraint can only match when the @option{-mq}
1803 option is in effect.
1805 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1808 A signed 12-bit integer constant.
1811 constant for arithmetic/logical operations. This might be any constant
1812 that can be put into a long immediate by the assmbler or linker without
1813 involving a PIC relocation.
1816 A 3-bit unsigned integer constant.
1819 A 6-bit unsigned integer constant.
1822 One's complement of a 6-bit unsigned integer constant.
1825 Two's complement of a 6-bit unsigned integer constant.
1828 A 5-bit unsigned integer constant.
1831 A 7-bit unsigned integer constant.
1834 A 8-bit unsigned integer constant.
1837 Any const_double value.
1840 @item ARM family---@file{config/arm/constraints.md}
1844 In Thumb state, the core registers @code{r8}-@code{r15}.
1847 The stack pointer register.
1850 In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this
1851 is an alias for the @code{r} constraint.
1854 VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values.
1857 VFP floating-point registers @code{d0}-@code{d31} and the appropriate
1858 subset @code{d0}-@code{d15} based on command line options.
1859 Used for 64 bit values only. Not valid for Thumb1.
1862 The iWMMX co-processor registers.
1865 The iWMMX GR registers.
1868 The floating-point constant 0.0
1871 Integer that is valid as an immediate operand in a data processing
1872 instruction. That is, an integer in the range 0 to 255 rotated by a
1876 Integer in the range @minus{}4095 to 4095
1879 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1882 Integer that satisfies constraint @samp{I} when negated (twos complement)
1885 Integer in the range 0 to 32
1888 A memory reference where the exact address is in a single register
1889 (`@samp{m}' is preferable for @code{asm} statements)
1892 An item in the constant pool
1895 A symbol in the text segment of the current file
1898 A memory reference suitable for VFP load/store insns (reg+constant offset)
1901 A memory reference suitable for iWMMXt load/store instructions.
1904 A memory reference suitable for the ARMv4 ldrsb instruction.
1907 @item AVR family---@file{config/avr/constraints.md}
1910 Registers from r0 to r15
1913 Registers from r16 to r23
1916 Registers from r16 to r31
1919 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1922 Pointer register (r26--r31)
1925 Base pointer register (r28--r31)
1928 Stack pointer register (SPH:SPL)
1931 Temporary register r0
1934 Register pair X (r27:r26)
1937 Register pair Y (r29:r28)
1940 Register pair Z (r31:r30)
1943 Constant greater than @minus{}1, less than 64
1946 Constant greater than @minus{}64, less than 1
1955 Constant that fits in 8 bits
1958 Constant integer @minus{}1
1961 Constant integer 8, 16, or 24
1967 A floating point constant 0.0
1970 A memory address based on Y or Z pointer with displacement.
1973 @item Blackfin family---@file{config/bfin/constraints.md}
1982 A call clobbered P register.
1985 A single register. If @var{n} is in the range 0 to 7, the corresponding D
1986 register. If it is @code{A}, then the register P0.
1989 Even-numbered D register
1992 Odd-numbered D register
1995 Accumulator register.
1998 Even-numbered accumulator register.
2001 Odd-numbered accumulator register.
2013 Registers used for circular buffering, i.e. I, B, or L registers.
2028 Any D, P, B, M, I or L register.
2031 Additional registers typically used only in prologues and epilogues: RETS,
2032 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2035 Any register except accumulators or CC.
2038 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2041 Unsigned 16 bit integer (in the range 0 to 65535)
2044 Signed 7 bit integer (in the range @minus{}64 to 63)
2047 Unsigned 7 bit integer (in the range 0 to 127)
2050 Unsigned 5 bit integer (in the range 0 to 31)
2053 Signed 4 bit integer (in the range @minus{}8 to 7)
2056 Signed 3 bit integer (in the range @minus{}3 to 4)
2059 Unsigned 3 bit integer (in the range 0 to 7)
2062 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2065 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2066 use with either accumulator.
2069 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2070 use only with accumulator A1.
2079 An integer constant with exactly a single bit set.
2082 An integer constant with all bits set except exactly one.
2090 @item CR16 Architecture---@file{config/cr16/cr16.h}
2094 Registers from r0 to r14 (registers without stack pointer)
2097 Register from r0 to r11 (all 16-bit registers)
2100 Register from r12 to r15 (all 32-bit registers)
2103 Signed constant that fits in 4 bits
2106 Signed constant that fits in 5 bits
2109 Signed constant that fits in 6 bits
2112 Unsigned constant that fits in 4 bits
2115 Signed constant that fits in 32 bits
2118 Check for 64 bits wide constants for add/sub instructions
2121 Floating point constant that is legal for store immediate
2124 @item Epiphany---@file{config/epiphany/constraints.md}
2127 An unsigned 16-bit constant.
2130 An unsigned 5-bit constant.
2133 A signed 11-bit constant.
2136 A signed 11-bit constant added to @minus{}1.
2137 Can only match when the @option{-m1reg-@var{reg}} option is active.
2140 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
2141 being a block of trailing zeroes.
2142 Can only match when the @option{-m1reg-@var{reg}} option is active.
2145 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
2146 rest being zeroes. Or to put it another way, one less than a power of two.
2147 Can only match when the @option{-m1reg-@var{reg}} option is active.
2150 Constant for arithmetic/logical operations.
2151 This is like @code{i}, except that for position independent code,
2152 no symbols / expressions needing relocations are allowed.
2155 Symbolic constant for call/jump instruction.
2158 The register class usable in short insns. This is a register class
2159 constraint, and can thus drive register allocation.
2160 This constraint won't match unless @option{-mprefer-short-insn-regs} is
2164 The the register class of registers that can be used to hold a
2165 sibcall call address. I.e., a caller-saved register.
2168 Core control register class.
2171 The register group usable in short insns.
2172 This constraint does not use a register class, so that it only
2173 passively matches suitable registers, and doesn't drive register allocation.
2177 Constant suitable for the addsi3_r pattern. This is a valid offset
2178 For byte, halfword, or word addressing.
2182 Matches the return address if it can be replaced with the link register.
2185 Matches the integer condition code register.
2188 Matches the return address if it is in a stack slot.
2191 Matches control register values to switch fp mode, which are encapsulated in
2192 @code{UNSPEC_FP_MODE}.
2195 @item FRV---@file{config/frv/frv.h}
2198 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2201 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2204 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2205 @code{icc0} to @code{icc3}).
2208 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2211 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2212 Odd registers are excluded not in the class but through the use of a machine
2213 mode larger than 4 bytes.
2216 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2219 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2220 Odd registers are excluded not in the class but through the use of a machine
2221 mode larger than 4 bytes.
2224 Register in the class @code{LR_REG} (the @code{lr} register).
2227 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2228 Register numbers not divisible by 4 are excluded not in the class but through
2229 the use of a machine mode larger than 8 bytes.
2232 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2235 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2238 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2241 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2244 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2245 Register numbers not divisible by 4 are excluded not in the class but through
2246 the use of a machine mode larger than 8 bytes.
2249 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2252 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2255 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2258 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2261 Floating point constant zero
2264 6-bit signed integer constant
2267 10-bit signed integer constant
2270 16-bit signed integer constant
2273 16-bit unsigned integer constant
2276 12-bit signed integer constant that is negative---i.e.@: in the
2277 range of @minus{}2048 to @minus{}1
2283 12-bit signed integer constant that is greater than zero---i.e.@: in the
2288 @item FT32---@file{config/ft32/constraints.md}
2297 A register indirect memory operand
2306 The constant zero or one
2309 A 16-bit signed constant (@minus{}32768 @dots{} 32767)
2312 A bitfield mask suitable for bext or bins
2315 An inverted bitfield mask suitable for bext or bins
2318 A 16-bit unsigned constant, multiple of 4 (0 @dots{} 65532)
2321 A 20-bit signed constant (@minus{}524288 @dots{} 524287)
2324 A constant for a bitfield width (1 @dots{} 16)
2327 A 10-bit signed constant (@minus{}512 @dots{} 511)
2331 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2337 Floating point register
2340 Shift amount register
2343 Floating point register (deprecated)
2346 Upper floating point register (32-bit), floating point register (64-bit)
2352 Signed 11-bit integer constant
2355 Signed 14-bit integer constant
2358 Integer constant that can be deposited with a @code{zdepi} instruction
2361 Signed 5-bit integer constant
2367 Integer constant that can be loaded with a @code{ldil} instruction
2370 Integer constant whose value plus one is a power of 2
2373 Integer constant that can be used for @code{and} operations in @code{depi}
2374 and @code{extru} instructions
2383 Floating-point constant 0.0
2386 A @code{lo_sum} data-linkage-table memory operand
2389 A memory operand that can be used as the destination operand of an
2390 integer store instruction
2393 A scaled or unscaled indexed memory operand
2396 A memory operand for floating-point loads and stores
2399 A register indirect memory operand
2402 @item Intel IA-64---@file{config/ia64/ia64.h}
2405 General register @code{r0} to @code{r3} for @code{addl} instruction
2411 Predicate register (@samp{c} as in ``conditional'')
2414 Application register residing in M-unit
2417 Application register residing in I-unit
2420 Floating-point register
2423 Memory operand. If used together with @samp{<} or @samp{>},
2424 the operand can have postincrement and postdecrement which
2425 require printing with @samp{%Pn} on IA-64.
2428 Floating-point constant 0.0 or 1.0
2431 14-bit signed integer constant
2434 22-bit signed integer constant
2437 8-bit signed integer constant for logical instructions
2440 8-bit adjusted signed integer constant for compare pseudo-ops
2443 6-bit unsigned integer constant for shift counts
2446 9-bit signed integer constant for load and store postincrements
2452 0 or @minus{}1 for @code{dep} instruction
2455 Non-volatile memory for floating-point loads and stores
2458 Integer constant in the range 1 to 4 for @code{shladd} instruction
2461 Memory operand except postincrement and postdecrement. This is
2462 now roughly the same as @samp{m} when not used together with @samp{<}
2466 @item M32C---@file{config/m32c/m32c.c}
2471 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2474 Any control register, when they're 16 bits wide (nothing if control
2475 registers are 24 bits wide)
2478 Any control register, when they're 24 bits wide.
2487 $r0 or $r2, or $r2r0 for 32 bit values.
2490 $r1 or $r3, or $r3r1 for 32 bit values.
2493 A register that can hold a 64 bit value.
2496 $r0 or $r1 (registers with addressable high/low bytes)
2505 Address registers when they're 16 bits wide.
2508 Address registers when they're 24 bits wide.
2511 Registers that can hold QI values.
2514 Registers that can be used with displacements ($a0, $a1, $sb).
2517 Registers that can hold 32 bit values.
2520 Registers that can hold 16 bit values.
2523 Registers chat can hold 16 bit values, including all control
2527 $r0 through R1, plus $a0 and $a1.
2533 The memory-based pseudo-registers $mem0 through $mem15.
2536 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2537 bit registers for m32cm, m32c).
2540 Matches multiple registers in a PARALLEL to form a larger register.
2541 Used to match function return values.
2547 @minus{}128 @dots{} 127
2550 @minus{}32768 @dots{} 32767
2556 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2559 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2562 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2565 @minus{}65536 @dots{} @minus{}1
2568 An 8 bit value with exactly one bit set.
2571 A 16 bit value with exactly one bit set.
2574 The common src/dest memory addressing modes.
2577 Memory addressed using $a0 or $a1.
2580 Memory addressed with immediate addresses.
2583 Memory addressed using the stack pointer ($sp).
2586 Memory addressed using the frame base register ($fb).
2589 Memory addressed using the small base register ($sb).
2595 @item MicroBlaze---@file{config/microblaze/constraints.md}
2598 A general register (@code{r0} to @code{r31}).
2601 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2605 @item MIPS---@file{config/mips/constraints.md}
2608 A general-purpose register. This is equivalent to @code{r} unless
2609 generating MIPS16 code, in which case the MIPS16 register set is used.
2612 A floating-point register (if available).
2615 Formerly the @code{hi} register. This constraint is no longer supported.
2618 The @code{lo} register. Use this register to store values that are
2619 no bigger than a word.
2622 The concatenated @code{hi} and @code{lo} registers. Use this register
2623 to store doubleword values.
2626 A register suitable for use in an indirect jump. This will always be
2627 @code{$25} for @option{-mabicalls}.
2630 Register @code{$3}. Do not use this constraint in new code;
2631 it is retained only for compatibility with glibc.
2634 Equivalent to @code{r}; retained for backwards compatibility.
2637 A floating-point condition code register.
2640 A signed 16-bit constant (for arithmetic instructions).
2646 An unsigned 16-bit constant (for logic instructions).
2649 A signed 32-bit constant in which the lower 16 bits are zero.
2650 Such constants can be loaded using @code{lui}.
2653 A constant that cannot be loaded using @code{lui}, @code{addiu}
2657 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2660 A signed 15-bit constant.
2663 A constant in the range 1 to 65535 (inclusive).
2666 Floating-point zero.
2669 An address that can be used in a non-macro load or store.
2672 A memory operand whose address is formed by a base register and offset
2673 that is suitable for use in instructions with the same addressing mode
2674 as @code{ll} and @code{sc}.
2677 An address suitable for a @code{prefetch} instruction, or for any other
2678 instruction with the same addressing mode as @code{prefetch}.
2681 @item Motorola 680x0---@file{config/m68k/constraints.md}
2690 68881 floating-point register, if available
2693 Integer in the range 1 to 8
2696 16-bit signed number
2699 Signed number whose magnitude is greater than 0x80
2702 Integer in the range @minus{}8 to @minus{}1
2705 Signed number whose magnitude is greater than 0x100
2708 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2711 16 (for rotate using swap)
2714 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2717 Numbers that mov3q can handle
2720 Floating point constant that is not a 68881 constant
2723 Operands that satisfy 'm' when -mpcrel is in effect
2726 Operands that satisfy 's' when -mpcrel is not in effect
2729 Address register indirect addressing mode
2732 Register offset addressing
2747 Range of signed numbers that don't fit in 16 bits
2750 Integers valid for mvq
2753 Integers valid for a moveq followed by a swap
2756 Integers valid for mvz
2759 Integers valid for mvs
2765 Non-register operands allowed in clr
2769 @item Moxie---@file{config/moxie/constraints.md}
2778 A register indirect memory operand
2781 A constant in the range of 0 to 255.
2784 A constant in the range of 0 to @minus{}255.
2788 @item MSP430--@file{config/msp430/constraints.md}
2801 Integer constant -1^20..1^19.
2804 Integer constant 1-4.
2807 Memory references which do not require an extended MOVX instruction.
2810 Memory reference, labels only.
2813 Memory reference, stack only.
2817 @item NDS32---@file{config/nds32/constraints.md}
2820 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
2822 LOW register class $r0 to $r7.
2824 MIDDLE register class $r0 to $r11, $r16 to $r19.
2826 HIGH register class $r12 to $r14, $r20 to $r31.
2828 Temporary assist register $ta (i.e.@: $r15).
2832 Unsigned immediate 3-bit value.
2834 Negative immediate 3-bit value in the range of @minus{}7--0.
2836 Unsigned immediate 4-bit value.
2838 Signed immediate 5-bit value.
2840 Unsigned immediate 5-bit value.
2842 Negative immediate 5-bit value in the range of @minus{}31--0.
2844 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
2846 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
2848 Unsigned immediate 8-bit value.
2850 Unsigned immediate 9-bit value.
2852 Signed immediate 10-bit value.
2854 Signed immediate 11-bit value.
2856 Signed immediate 15-bit value.
2858 Unsigned immediate 15-bit value.
2860 A constant which is not in the range of imm15u but ok for bclr instruction.
2862 A constant which is not in the range of imm15u but ok for bset instruction.
2864 A constant which is not in the range of imm15u but ok for btgl instruction.
2866 A constant whose compliment value is in the range of imm15u
2867 and ok for bitci instruction.
2869 Signed immediate 16-bit value.
2871 Signed immediate 17-bit value.
2873 Signed immediate 19-bit value.
2875 Signed immediate 20-bit value.
2877 The immediate value that can be simply set high 20-bit.
2879 The immediate value 0xff.
2881 The immediate value 0xffff.
2883 The immediate value 0x01.
2885 The immediate value 0x7ff.
2887 The immediate value with power of 2.
2889 The immediate value with power of 2 minus 1.
2891 Memory constraint for 333 format.
2893 Memory constraint for 45 format.
2895 Memory constraint for 37 format.
2898 @item Nios II family---@file{config/nios2/constraints.md}
2902 Integer that is valid as an immediate operand in an
2903 instruction taking a signed 16-bit number. Range
2904 @minus{}32768 to 32767.
2907 Integer that is valid as an immediate operand in an
2908 instruction taking an unsigned 16-bit number. Range
2912 Integer that is valid as an immediate operand in an
2913 instruction taking only the upper 16-bits of a
2914 32-bit number. Range 32-bit numbers with the lower
2918 Integer that is valid as an immediate operand for a
2919 shift instruction. Range 0 to 31.
2922 Integer that is valid as an immediate operand for
2923 only the value 0. Can be used in conjunction with
2924 the format modifier @code{z} to use @code{r0}
2925 instead of @code{0} in the assembly output.
2928 Integer that is valid as an immediate operand for
2929 a custom instruction opcode. Range 0 to 255.
2932 An immediate operand for R2 andchi/andci instructions.
2935 Matches immediates which are addresses in the small
2936 data section and therefore can be added to @code{gp}
2937 as a 16-bit immediate to re-create their 32-bit value.
2940 Matches constants suitable as an operand for the rdprs and
2944 A memory operand suitable for Nios II R2 load/store
2945 exclusive instructions.
2948 A memory operand suitable for load/store IO and cache
2953 A @code{const} wrapped @code{UNSPEC} expression,
2954 representing a supported PIC or TLS relocation.
2959 @item PDP-11---@file{config/pdp11/constraints.md}
2962 Floating point registers AC0 through AC3. These can be loaded from/to
2963 memory with a single instruction.
2966 Odd numbered general registers (R1, R3, R5). These are used for
2967 16-bit multiply operations.
2970 Any of the floating point registers (AC0 through AC5).
2973 Floating point constant 0.
2976 An integer constant that fits in 16 bits.
2979 An integer constant whose low order 16 bits are zero.
2982 An integer constant that does not meet the constraints for codes
2983 @samp{I} or @samp{J}.
2986 The integer constant 1.
2989 The integer constant @minus{}1.
2992 The integer constant 0.
2995 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
2996 amounts are handled as multiple single-bit shifts rather than a single
2997 variable-length shift.
3000 A memory reference which requires an additional word (address or
3001 offset) after the opcode.
3004 A memory reference that is encoded within the opcode.
3008 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
3011 Address base register
3014 Floating point register (containing 64-bit value)
3017 Floating point register (containing 32-bit value)
3020 Altivec vector register
3023 Any VSX register if the @option{-mvsx} option was used or NO_REGS.
3025 When using any of the register constraints (@code{wa}, @code{wd},
3026 @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
3027 @code{wl}, @code{wm}, @code{wo}, @code{wp}, @code{wq}, @code{ws},
3028 @code{wt}, @code{wu}, @code{wv}, @code{ww}, or @code{wy})
3029 that take VSX registers, you must use @code{%x<n>} in the template so
3030 that the correct register is used. Otherwise the register number
3031 output in the assembly file will be incorrect if an Altivec register
3032 is an operand of a VSX instruction that expects VSX register
3036 asm ("xvadddp %x0,%x1,%x2"
3038 : "wa" (v2), "wa" (v3));
3045 asm ("xvadddp %0,%1,%2"
3047 : "wa" (v2), "wa" (v3));
3053 If an instruction only takes Altivec registers, you do not want to use
3057 asm ("xsaddqp %0,%1,%2"
3059 : "v" (v2), "v" (v3));
3063 is correct because the @code{xsaddqp} instruction only takes Altivec
3067 asm ("xsaddqp %x0,%x1,%x2"
3069 : "v" (v2), "v" (v3));
3076 Altivec register if @option{-mcpu=power9} is used or NO_REGS.
3079 VSX vector register to hold vector double data or NO_REGS.
3082 VSX register if the @option{-mcpu=power9} and @option{-m64} options
3083 were used or NO_REGS.
3086 VSX vector register to hold vector float data or NO_REGS.
3089 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
3092 Floating point register if direct moves are available, or NO_REGS.
3095 FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
3098 FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
3101 FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
3104 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
3107 VSX register if direct move instructions are enabled, or NO_REGS.
3110 No register (NO_REGS).
3113 VSX register to use for ISA 3.0 vector instructions, or NO_REGS.
3116 VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS.
3119 VSX register to use for IEEE 128-bit floating point, or NO_REGS.
3122 General purpose register if 64-bit instructions are enabled or NO_REGS.
3125 VSX vector register to hold scalar double values or NO_REGS.
3128 VSX vector register to hold 128 bit integer or NO_REGS.
3131 Altivec register to use for float/32-bit int loads/stores or NO_REGS.
3134 Altivec register to use for double loads/stores or NO_REGS.
3137 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
3140 Floating point register if the STFIWX instruction is enabled or NO_REGS.
3143 FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
3146 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
3149 Address base register if 64-bit instructions are enabled or NO_REGS.
3152 Signed 5-bit constant integer that can be loaded into an altivec register.
3155 Int constant that is the element number of the 64-bit scalar in a vector.
3158 Vector constant that can be loaded with the XXSPLTIB instruction.
3161 Memory operand suitable for power9 fusion load/stores.
3164 Memory operand suitable for TOC fusion memory references.
3167 Altivec register if @option{-mvsx-small-integer}.
3170 Floating point register if @option{-mvsx-small-integer}.
3173 FP register if @option{-mvsx-small-integer} and @option{-mpower9-vector}.
3176 Altivec register if @option{-mvsx-small-integer} and @option{-mpower9-vector}.
3179 Int constant that is the element number that the MFVSRLD instruction.
3183 Match vector constant with all 1's if the XXLORC instruction is available.
3186 A memory operand suitable for the ISA 3.0 vector d-form instructions.
3189 A memory address that will work with the @code{lq} and @code{stq}
3193 Vector constant that can be loaded with XXSPLTIB & sign extension.
3196 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
3202 @samp{LINK} register
3205 @samp{CR} register (condition register) number 0
3208 @samp{CR} register (condition register)
3211 @samp{XER[CA]} carry bit (part of the XER register)
3214 Signed 16-bit constant
3217 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
3218 @code{SImode} constants)
3221 Unsigned 16-bit constant
3224 Signed 16-bit constant shifted left 16 bits
3227 Constant larger than 31
3236 Constant whose negation is a signed 16-bit constant
3239 Floating point constant that can be loaded into a register with one
3240 instruction per word
3243 Integer/Floating point constant that can be loaded into a register using
3248 Normally, @code{m} does not allow addresses that update the base register.
3249 If @samp{<} or @samp{>} constraint is also used, they are allowed and
3250 therefore on PowerPC targets in that case it is only safe
3251 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
3252 accesses the operand exactly once. The @code{asm} statement must also
3253 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
3254 corresponding load or store instruction. For example:
3257 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
3263 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
3269 A ``stable'' memory operand; that is, one which does not include any
3270 automodification of the base register. This used to be useful when
3271 @samp{m} allowed automodification of the base register, but as those are now only
3272 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
3273 as @samp{m} without @samp{<} and @samp{>}.
3276 Memory operand that is an offset from a register (it is usually better
3277 to use @samp{m} or @samp{es} in @code{asm} statements)
3280 Memory operand that is an indexed or indirect from a register (it is
3281 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
3287 Address operand that is an indexed or indirect from a register (@samp{p} is
3288 preferable for @code{asm} statements)
3291 System V Release 4 small data area reference
3294 Vector constant that does not require memory
3297 Vector constant that is all zeros.
3301 @item RL78---@file{config/rl78/constraints.md}
3305 An integer constant in the range 1 @dots{} 7.
3307 An integer constant in the range 0 @dots{} 255.
3309 An integer constant in the range @minus{}255 @dots{} 0
3311 The integer constant 1.
3313 The integer constant -1.
3315 The integer constant 0.
3317 The integer constant 2.
3319 The integer constant -2.
3321 An integer constant in the range 1 @dots{} 15.
3323 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3325 The synthetic compare types--gt, lt, ge, and le.
3327 A memory reference with an absolute address.
3329 A memory reference using @code{BC} as a base register, with an optional offset.
3331 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3333 A memory reference using any 16-bit register pair for the address, for calls.
3335 A memory reference using @code{DE} as a base register, with an optional offset.
3337 A memory reference using @code{DE} as a base register, without any offset.
3339 Any memory reference to an address in the far address space.
3341 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3343 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3345 A memory reference using @code{HL} as a base register, without any offset.
3347 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3349 Any memory reference to an address in the near address space.
3351 The @code{AX} register.
3353 The @code{BC} register.
3355 The @code{DE} register.
3357 @code{A} through @code{L} registers.
3359 The @code{SP} register.
3361 The @code{HL} register.
3363 The 16-bit @code{R8} register.
3365 The 16-bit @code{R10} register.
3367 The registers reserved for interrupts (@code{R24} to @code{R31}).
3369 The @code{A} register.
3371 The @code{B} register.
3373 The @code{C} register.
3375 The @code{D} register.
3377 The @code{E} register.
3379 The @code{H} register.
3381 The @code{L} register.
3383 The virtual registers.
3385 The @code{PSW} register.
3387 The @code{X} register.
3391 @item RISC-V---@file{config/riscv/constraints.md}
3395 A floating-point register (if availiable).
3398 An I-type 12-bit signed immediate.
3404 A 5-bit unsigned immediate for CSR access instructions.
3407 An address that is held in a general-purpose register.
3411 @item RX---@file{config/rx/constraints.md}
3414 An address which does not involve register indirect addressing or
3415 pre/post increment/decrement addressing.
3421 A constant in the range @minus{}256 to 255, inclusive.
3424 A constant in the range @minus{}128 to 127, inclusive.
3427 A constant in the range @minus{}32768 to 32767, inclusive.
3430 A constant in the range @minus{}8388608 to 8388607, inclusive.
3433 A constant in the range 0 to 15, inclusive.
3437 @item S/390 and zSeries---@file{config/s390/s390.h}
3440 Address register (general purpose register except r0)
3443 Condition code register
3446 Data register (arbitrary general purpose register)
3449 Floating-point register
3452 Unsigned 8-bit constant (0--255)
3455 Unsigned 12-bit constant (0--4095)
3458 Signed 16-bit constant (@minus{}32768--32767)
3461 Value appropriate as displacement.
3464 for short displacement
3465 @item (@minus{}524288..524287)
3466 for long displacement
3470 Constant integer with a value of 0x7fffffff.
3473 Multiple letter constraint followed by 4 parameter letters.
3476 number of the part counting from most to least significant
3480 mode of the containing operand
3482 value of the other parts (F---all bits set)
3484 The constraint matches if the specified part of a constant
3485 has a value different from its other parts.
3488 Memory reference without index register and with short displacement.
3491 Memory reference with index register and short displacement.
3494 Memory reference without index register but with long displacement.
3497 Memory reference with index register and long displacement.
3500 Pointer with short displacement.
3503 Pointer with long displacement.
3506 Shift count operand.
3511 @item SPARC---@file{config/sparc/sparc.h}
3514 Floating-point register on the SPARC-V8 architecture and
3515 lower floating-point register on the SPARC-V9 architecture.
3518 Floating-point register. It is equivalent to @samp{f} on the
3519 SPARC-V8 architecture and contains both lower and upper
3520 floating-point registers on the SPARC-V9 architecture.
3523 Floating-point condition code register.
3526 Lower floating-point register. It is only valid on the SPARC-V9
3527 architecture when the Visual Instruction Set is available.
3530 Floating-point register. It is only valid on the SPARC-V9 architecture
3531 when the Visual Instruction Set is available.
3534 64-bit global or out register for the SPARC-V8+ architecture.
3537 The constant all-ones, for floating-point.
3540 Signed 5-bit constant
3546 Signed 13-bit constant
3552 32-bit constant with the low 12 bits clear (a constant that can be
3553 loaded with the @code{sethi} instruction)
3556 A constant in the range supported by @code{movcc} instructions (11-bit
3560 A constant in the range supported by @code{movrcc} instructions (10-bit
3564 Same as @samp{K}, except that it verifies that bits that are not in the
3565 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3566 modes wider than @code{SImode}
3575 Signed 13-bit constant, sign-extended to 32 or 64 bits
3581 Floating-point constant whose integral representation can
3582 be moved into an integer register using a single sethi
3586 Floating-point constant whose integral representation can
3587 be moved into an integer register using a single mov
3591 Floating-point constant whose integral representation can
3592 be moved into an integer register using a high/lo_sum
3593 instruction sequence
3596 Memory address aligned to an 8-byte boundary
3602 Memory address for @samp{e} constraint registers
3605 Memory address with only a base register
3612 @item SPU---@file{config/spu/spu.h}
3615 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3618 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3621 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3624 An immediate which can be loaded with @code{fsmbi}.
3627 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3630 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3633 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3636 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3639 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3642 An unsigned 7-bit constant for conversion/nop/channel instructions.
3645 A signed 10-bit constant for most arithmetic instructions.
3648 A signed 16 bit immediate for @code{stop}.
3651 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3654 An unsigned 7-bit constant whose 3 least significant bits are 0.
3657 An unsigned 3-bit constant for 16-byte rotates and shifts
3660 Call operand, reg, for indirect calls
3663 Call operand, symbol, for relative calls.
3666 Call operand, const_int, for absolute calls.
3669 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3672 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3675 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3678 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3682 @item TI C6X family---@file{config/c6x/constraints.md}
3685 Register file A (A0--A31).
3688 Register file B (B0--B31).
3691 Predicate registers in register file A (A0--A2 on C64X and
3692 higher, A1 and A2 otherwise).
3695 Predicate registers in register file B (B0--B2).
3698 A call-used register in register file B (B0--B9, B16--B31).
3701 Register file A, excluding predicate registers (A3--A31,
3702 plus A0 if not C64X or higher).
3705 Register file B, excluding predicate registers (B3--B31).
3708 Integer constant in the range 0 @dots{} 15.
3711 Integer constant in the range 0 @dots{} 31.
3714 Integer constant in the range @minus{}31 @dots{} 0.
3717 Integer constant in the range @minus{}16 @dots{} 15.
3720 Integer constant that can be the operand of an ADDA or a SUBA insn.
3723 Integer constant in the range 0 @dots{} 65535.
3726 Integer constant in the range @minus{}32768 @dots{} 32767.
3729 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3732 Integer constant that is a valid mask for the clr instruction.
3735 Integer constant that is a valid mask for the set instruction.
3738 Memory location with A base register.
3741 Memory location with B base register.
3745 On C64x+ targets, a GP-relative small data reference.
3748 Any kind of @code{SYMBOL_REF}, for use in a call address.
3751 Any kind of immediate operand, unless it matches the S0 constraint.
3754 Memory location with B base register, but not using a long offset.
3757 A memory operand with an address that cannot be used in an unaligned access.
3761 Register B14 (aka DP).
3765 @item TILE-Gx---@file{config/tilegx/constraints.md}
3778 Each of these represents a register constraint for an individual
3779 register, from r0 to r10.
3782 Signed 8-bit integer constant.
3785 Signed 16-bit integer constant.
3788 Unsigned 16-bit integer constant.
3791 Integer constant that fits in one signed byte when incremented by one
3792 (@minus{}129 @dots{} 126).
3795 Memory operand. If used together with @samp{<} or @samp{>}, the
3796 operand can have postincrement which requires printing with @samp{%In}
3797 and @samp{%in} on TILE-Gx. For example:
3800 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3804 A bit mask suitable for the BFINS instruction.
3807 Integer constant that is a byte tiled out eight times.
3810 The integer zero constant.
3813 Integer constant that is a sign-extended byte tiled out as four shorts.
3816 Integer constant that fits in one signed byte when incremented
3817 (@minus{}129 @dots{} 126), but excluding -1.
3820 Integer constant that has all 1 bits consecutive and starting at bit 0.
3823 A 16-bit fragment of a got, tls, or pc-relative reference.
3826 Memory operand except postincrement. This is roughly the same as
3827 @samp{m} when not used together with @samp{<} or @samp{>}.
3830 An 8-element vector constant with identical elements.
3833 A 4-element vector constant with identical elements.
3836 The integer constant 0xffffffff.
3839 The integer constant 0xffffffff00000000.
3843 @item TILEPro---@file{config/tilepro/constraints.md}
3856 Each of these represents a register constraint for an individual
3857 register, from r0 to r10.
3860 Signed 8-bit integer constant.
3863 Signed 16-bit integer constant.
3866 Nonzero integer constant with low 16 bits zero.
3869 Integer constant that fits in one signed byte when incremented by one
3870 (@minus{}129 @dots{} 126).
3873 Memory operand. If used together with @samp{<} or @samp{>}, the
3874 operand can have postincrement which requires printing with @samp{%In}
3875 and @samp{%in} on TILEPro. For example:
3878 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
3882 A bit mask suitable for the MM instruction.
3885 Integer constant that is a byte tiled out four times.
3888 The integer zero constant.
3891 Integer constant that is a sign-extended byte tiled out as two shorts.
3894 Integer constant that fits in one signed byte when incremented
3895 (@minus{}129 @dots{} 126), but excluding -1.
3898 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
3902 Memory operand except postincrement. This is roughly the same as
3903 @samp{m} when not used together with @samp{<} or @samp{>}.
3906 A 4-element vector constant with identical elements.
3909 A 2-element vector constant with identical elements.
3913 @item Visium---@file{config/visium/constraints.md}
3916 EAM register @code{mdb}
3919 EAM register @code{mdc}
3922 Floating point register
3926 Register for sibcall optimization
3930 General register, but not @code{r29}, @code{r30} and @code{r31}
3942 Floating-point constant 0.0
3945 Integer constant in the range 0 .. 65535 (16-bit immediate)
3948 Integer constant in the range 1 .. 31 (5-bit immediate)
3951 Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
3954 Integer constant @minus{}1
3963 @item x86 family---@file{config/i386/constraints.md}
3966 Legacy register---the eight integer registers available on all
3967 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
3968 @code{si}, @code{di}, @code{bp}, @code{sp}).
3971 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
3972 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
3975 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
3976 @code{c}, and @code{d}.
3980 Any register that can be used as the index in a base+index memory
3981 access: that is, any general register except the stack pointer.
3985 The @code{a} register.
3988 The @code{b} register.
3991 The @code{c} register.
3994 The @code{d} register.
3997 The @code{si} register.
4000 The @code{di} register.
4003 The @code{a} and @code{d} registers. This class is used for instructions
4004 that return double word results in the @code{ax:dx} register pair. Single
4005 word values will be allocated either in @code{ax} or @code{dx}.
4006 For example on i386 the following implements @code{rdtsc}:
4009 unsigned long long rdtsc (void)
4011 unsigned long long tick;
4012 __asm__ __volatile__("rdtsc":"=A"(tick));
4017 This is not correct on x86-64 as it would allocate tick in either @code{ax}
4018 or @code{dx}. You have to use the following variant instead:
4021 unsigned long long rdtsc (void)
4023 unsigned int tickl, tickh;
4024 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
4025 return ((unsigned long long)tickh << 32)|tickl;
4030 The call-clobbered integer registers.
4033 Any 80387 floating-point (stack) register.
4036 Top of 80387 floating-point stack (@code{%st(0)}).
4039 Second from top of 80387 floating-point stack (@code{%st(1)}).
4043 Any mask register that can be used as a predicate, i.e. @code{k1-k7}.
4056 Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).
4064 First SSE register (@code{%xmm0}).
4068 Any SSE register, when SSE2 and inter-unit moves are enabled.
4071 Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.
4074 Any MMX register, when inter-unit moves are enabled.
4077 Any MMX register, when inter-unit moves from vector registers are enabled.
4080 Any integer register when @code{TARGET_PARTIAL_REG_STALL} is disabled.
4083 Any integer register when zero extensions with @code{AND} are disabled.
4086 Any register that can be used as the GOT base when calling@*
4087 @code{___tls_get_addr}: that is, any general register except @code{a}
4088 and @code{sp} registers, for @option{-fno-plt} if linker supports it.
4089 Otherwise, @code{b} register.
4092 Any x87 register when 80387 floating-point arithmetic is enabled.
4095 Lower SSE register when avoiding REX prefix and all SSE registers otherwise.
4098 For AVX512VL, any EVEX-encodable SSE register (@code{%xmm0-%xmm31}),
4099 otherwise any SSE register.
4102 Any EVEX-encodable SSE register, that has number factor of four.
4105 Flags register operand.
4111 Vector memory operand.
4114 Constant memory operand.
4117 Memory operand without REX prefix.
4120 Sibcall memory operand.
4123 Call memory operand.
4126 Constant call address operand.
4129 SSE constant -1 operand.
4133 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
4136 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
4139 Signed 8-bit integer constant.
4142 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
4145 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
4148 Unsigned 8-bit integer constant (for @code{in} and @code{out}
4153 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
4157 Standard 80387 floating point constant.
4160 SSE constant zero operand.
4163 32-bit signed integer constant, or a symbolic reference known
4164 to fit that range (for immediate operands in sign-extending x86-64
4168 32-bit signed integer constant, or a symbolic reference known
4169 to fit that range (for sign-extending conversion operations that
4170 require non-@code{VOIDmode} immediate operands).
4173 32-bit unsigned integer constant, or a symbolic reference known
4174 to fit that range (for zero-extending conversion operations that
4175 require non-@code{VOIDmode} immediate operands).
4178 128-bit integer constant where both the high and low 64-bit word
4179 satisfy the @code{e} constraint.
4182 32-bit unsigned integer constant, or a symbolic reference known
4183 to fit that range (for immediate operands in zero-extending x86-64
4187 VSIB address operand.
4190 Address operand without segment register.
4193 MPX address operand without index.
4196 MPX address operand without base.
4200 @item Xstormy16---@file{config/stormy16/stormy16.h}
4215 Registers r0 through r7.
4218 Registers r0 and r1.
4224 Registers r8 and r9.
4227 A constant between 0 and 3 inclusive.
4230 A constant that has exactly one bit set.
4233 A constant that has exactly one bit clear.
4236 A constant between 0 and 255 inclusive.
4239 A constant between @minus{}255 and 0 inclusive.
4242 A constant between @minus{}3 and 0 inclusive.
4245 A constant between 1 and 4 inclusive.
4248 A constant between @minus{}4 and @minus{}1 inclusive.
4251 A memory reference that is a stack push.
4254 A memory reference that is a stack pop.
4257 A memory reference that refers to a constant address of known value.
4260 The register indicated by Rx (not implemented yet).
4263 A constant that is not between 2 and 15 inclusive.
4270 @item Xtensa---@file{config/xtensa/constraints.md}
4273 General-purpose 32-bit register
4276 One-bit boolean register
4279 MAC16 40-bit accumulator register
4282 Signed 12-bit integer constant, for use in MOVI instructions
4285 Signed 8-bit integer constant, for use in ADDI instructions
4288 Integer constant valid for BccI instructions
4291 Unsigned constant valid for BccUI instructions
4298 @node Disable Insn Alternatives
4299 @subsection Disable insn alternatives using the @code{enabled} attribute
4302 There are three insn attributes that may be used to selectively disable
4303 instruction alternatives:
4307 Says whether an alternative is available on the current subtarget.
4309 @item preferred_for_size
4310 Says whether an enabled alternative should be used in code that is
4313 @item preferred_for_speed
4314 Says whether an enabled alternative should be used in code that is
4315 optimized for speed.
4318 All these attributes should use @code{(const_int 1)} to allow an alternative
4319 or @code{(const_int 0)} to disallow it. The attributes must be a static
4320 property of the subtarget; they cannot for example depend on the
4321 current operands, on the current optimization level, on the location
4322 of the insn within the body of a loop, on whether register allocation
4323 has finished, or on the current compiler pass.
4325 The @code{enabled} attribute is a correctness property. It tells GCC to act
4326 as though the disabled alternatives were never defined in the first place.
4327 This is useful when adding new instructions to an existing pattern in
4328 cases where the new instructions are only available for certain cpu
4329 architecture levels (typically mapped to the @code{-march=} command-line
4332 In contrast, the @code{preferred_for_size} and @code{preferred_for_speed}
4333 attributes are strong optimization hints rather than correctness properties.
4334 @code{preferred_for_size} tells GCC which alternatives to consider when
4335 adding or modifying an instruction that GCC wants to optimize for size.
4336 @code{preferred_for_speed} does the same thing for speed. Note that things
4337 like code motion can lead to cases where code optimized for size uses
4338 alternatives that are not preferred for size, and similarly for speed.
4340 Although @code{define_insn}s can in principle specify the @code{enabled}
4341 attribute directly, it is often clearer to have subsiduary attributes
4342 for each architectural feature of interest. The @code{define_insn}s
4343 can then use these subsiduary attributes to say which alternatives
4344 require which features. The example below does this for @code{cpu_facility}.
4346 E.g. the following two patterns could easily be merged using the @code{enabled}
4351 (define_insn "*movdi_old"
4352 [(set (match_operand:DI 0 "register_operand" "=d")
4353 (match_operand:DI 1 "register_operand" " d"))]
4357 (define_insn "*movdi_new"
4358 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4359 (match_operand:DI 1 "register_operand" " d,d,f"))]
4372 (define_insn "*movdi_combined"
4373 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4374 (match_operand:DI 1 "register_operand" " d,d,f"))]
4380 [(set_attr "cpu_facility" "*,new,new")])
4384 with the @code{enabled} attribute defined like this:
4388 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4390 (define_attr "enabled" ""
4391 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4392 (and (eq_attr "cpu_facility" "new")
4393 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4402 @node Define Constraints
4403 @subsection Defining Machine-Specific Constraints
4404 @cindex defining constraints
4405 @cindex constraints, defining
4407 Machine-specific constraints fall into two categories: register and
4408 non-register constraints. Within the latter category, constraints
4409 which allow subsets of all possible memory or address operands should
4410 be specially marked, to give @code{reload} more information.
4412 Machine-specific constraints can be given names of arbitrary length,
4413 but they must be entirely composed of letters, digits, underscores
4414 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4415 must begin with a letter or underscore.
4417 In order to avoid ambiguity in operand constraint strings, no
4418 constraint can have a name that begins with any other constraint's
4419 name. For example, if @code{x} is defined as a constraint name,
4420 @code{xy} may not be, and vice versa. As a consequence of this rule,
4421 no constraint may begin with one of the generic constraint letters:
4422 @samp{E F V X g i m n o p r s}.
4424 Register constraints correspond directly to register classes.
4425 @xref{Register Classes}. There is thus not much flexibility in their
4428 @deffn {MD Expression} define_register_constraint name regclass docstring
4429 All three arguments are string constants.
4430 @var{name} is the name of the constraint, as it will appear in
4431 @code{match_operand} expressions. If @var{name} is a multi-letter
4432 constraint its length shall be the same for all constraints starting
4433 with the same letter. @var{regclass} can be either the
4434 name of the corresponding register class (@pxref{Register Classes}),
4435 or a C expression which evaluates to the appropriate register class.
4436 If it is an expression, it must have no side effects, and it cannot
4437 look at the operand. The usual use of expressions is to map some
4438 register constraints to @code{NO_REGS} when the register class
4439 is not available on a given subarchitecture.
4441 @var{docstring} is a sentence documenting the meaning of the
4442 constraint. Docstrings are explained further below.
4445 Non-register constraints are more like predicates: the constraint
4446 definition gives a boolean expression which indicates whether the
4449 @deffn {MD Expression} define_constraint name docstring exp
4450 The @var{name} and @var{docstring} arguments are the same as for
4451 @code{define_register_constraint}, but note that the docstring comes
4452 immediately after the name for these expressions. @var{exp} is an RTL
4453 expression, obeying the same rules as the RTL expressions in predicate
4454 definitions. @xref{Defining Predicates}, for details. If it
4455 evaluates true, the constraint matches; if it evaluates false, it
4456 doesn't. Constraint expressions should indicate which RTL codes they
4457 might match, just like predicate expressions.
4459 @code{match_test} C expressions have access to the
4460 following variables:
4464 The RTL object defining the operand.
4466 The machine mode of @var{op}.
4468 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4470 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4471 @code{const_double}.
4473 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4474 @code{const_double}.
4476 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4477 @code{const_double}.
4480 The @var{*val} variables should only be used once another piece of the
4481 expression has verified that @var{op} is the appropriate kind of RTL
4485 Most non-register constraints should be defined with
4486 @code{define_constraint}. The remaining two definition expressions
4487 are only appropriate for constraints that should be handled specially
4488 by @code{reload} if they fail to match.
4490 @deffn {MD Expression} define_memory_constraint name docstring exp
4491 Use this expression for constraints that match a subset of all memory
4492 operands: that is, @code{reload} can make them match by converting the
4493 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4494 base register (from the register class specified by
4495 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4497 For example, on the S/390, some instructions do not accept arbitrary
4498 memory references, but only those that do not make use of an index
4499 register. The constraint letter @samp{Q} is defined to represent a
4500 memory address of this type. If @samp{Q} is defined with
4501 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4502 memory operand, because @code{reload} knows it can simply copy the
4503 memory address into a base register if required. This is analogous to
4504 the way an @samp{o} constraint can handle any memory operand.
4506 The syntax and semantics are otherwise identical to
4507 @code{define_constraint}.
4510 @deffn {MD Expression} define_special_memory_constraint name docstring exp
4511 Use this expression for constraints that match a subset of all memory
4512 operands: that is, @code{reload} can not make them match by reloading
4513 the address as it is described for @code{define_memory_constraint} or
4514 such address reload is undesirable with the performance point of view.
4516 For example, @code{define_special_memory_constraint} can be useful if
4517 specifically aligned memory is necessary or desirable for some insn
4520 The syntax and semantics are otherwise identical to
4521 @code{define_constraint}.
4524 @deffn {MD Expression} define_address_constraint name docstring exp
4525 Use this expression for constraints that match a subset of all address
4526 operands: that is, @code{reload} can make the constraint match by
4527 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4528 with @var{X} a base register.
4530 Constraints defined with @code{define_address_constraint} can only be
4531 used with the @code{address_operand} predicate, or machine-specific
4532 predicates that work the same way. They are treated analogously to
4533 the generic @samp{p} constraint.
4535 The syntax and semantics are otherwise identical to
4536 @code{define_constraint}.
4539 For historical reasons, names beginning with the letters @samp{G H}
4540 are reserved for constraints that match only @code{const_double}s, and
4541 names beginning with the letters @samp{I J K L M N O P} are reserved
4542 for constraints that match only @code{const_int}s. This may change in
4543 the future. For the time being, constraints with these names must be
4544 written in a stylized form, so that @code{genpreds} can tell you did
4549 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4551 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4552 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4555 @c the semicolons line up in the formatted manual
4557 It is fine to use names beginning with other letters for constraints
4558 that match @code{const_double}s or @code{const_int}s.
4560 Each docstring in a constraint definition should be one or more complete
4561 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4562 In the future they will be copied into the GCC manual, in @ref{Machine
4563 Constraints}, replacing the hand-maintained tables currently found in
4564 that section. Also, in the future the compiler may use this to give
4565 more helpful diagnostics when poor choice of @code{asm} constraints
4566 causes a reload failure.
4568 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4569 beginning of a docstring, then (in the future) it will appear only in
4570 the internals manual's version of the machine-specific constraint tables.
4571 Use this for constraints that should not appear in @code{asm} statements.
4573 @node C Constraint Interface
4574 @subsection Testing constraints from C
4575 @cindex testing constraints
4576 @cindex constraints, testing
4578 It is occasionally useful to test a constraint from C code rather than
4579 implicitly via the constraint string in a @code{match_operand}. The
4580 generated file @file{tm_p.h} declares a few interfaces for working
4581 with constraints. At present these are defined for all constraints
4582 except @code{g} (which is equivalent to @code{general_operand}).
4584 Some valid constraint names are not valid C identifiers, so there is a
4585 mangling scheme for referring to them from C@. Constraint names that
4586 do not contain angle brackets or underscores are left unchanged.
4587 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4588 each @samp{>} with @samp{_g}. Here are some examples:
4590 @c the @c's prevent double blank lines in the printed manual.
4592 @multitable {Original} {Mangled}
4593 @item @strong{Original} @tab @strong{Mangled} @c
4594 @item @code{x} @tab @code{x} @c
4595 @item @code{P42x} @tab @code{P42x} @c
4596 @item @code{P4_x} @tab @code{P4__x} @c
4597 @item @code{P4>x} @tab @code{P4_gx} @c
4598 @item @code{P4>>} @tab @code{P4_g_g} @c
4599 @item @code{P4_g>} @tab @code{P4__g_g} @c
4603 Throughout this section, the variable @var{c} is either a constraint
4604 in the abstract sense, or a constant from @code{enum constraint_num};
4605 the variable @var{m} is a mangled constraint name (usually as part of
4606 a larger identifier).
4608 @deftp Enum constraint_num
4609 For each constraint except @code{g}, there is a corresponding
4610 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4611 constraint. Functions that take an @code{enum constraint_num} as an
4612 argument expect one of these constants.
4615 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4616 For each non-register constraint @var{m} except @code{g}, there is
4617 one of these functions; it returns @code{true} if @var{exp} satisfies the
4618 constraint. These functions are only visible if @file{rtl.h} was included
4619 before @file{tm_p.h}.
4622 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4623 Like the @code{satisfies_constraint_@var{m}} functions, but the
4624 constraint to test is given as an argument, @var{c}. If @var{c}
4625 specifies a register constraint, this function will always return
4629 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4630 Returns the register class associated with @var{c}. If @var{c} is not
4631 a register constraint, or those registers are not available for the
4632 currently selected subtarget, returns @code{NO_REGS}.
4635 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4636 peephole optimizations (@pxref{Peephole Definitions}), operand
4637 constraint strings are ignored, so if there are relevant constraints,
4638 they must be tested in the C condition. In the example, the
4639 optimization is applied if operand 2 does @emph{not} satisfy the
4640 @samp{K} constraint. (This is a simplified version of a peephole
4641 definition from the i386 machine description.)
4645 [(match_scratch:SI 3 "r")
4646 (set (match_operand:SI 0 "register_operand" "")
4647 (mult:SI (match_operand:SI 1 "memory_operand" "")
4648 (match_operand:SI 2 "immediate_operand" "")))]
4650 "!satisfies_constraint_K (operands[2])"
4652 [(set (match_dup 3) (match_dup 1))
4653 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4658 @node Standard Names
4659 @section Standard Pattern Names For Generation
4660 @cindex standard pattern names
4661 @cindex pattern names
4662 @cindex names, pattern
4664 Here is a table of the instruction names that are meaningful in the RTL
4665 generation pass of the compiler. Giving one of these names to an
4666 instruction pattern tells the RTL generation pass that it can use the
4667 pattern to accomplish a certain task.
4670 @cindex @code{mov@var{m}} instruction pattern
4671 @item @samp{mov@var{m}}
4672 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4673 This instruction pattern moves data with that machine mode from operand
4674 1 to operand 0. For example, @samp{movsi} moves full-word data.
4676 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4677 own mode is wider than @var{m}, the effect of this instruction is
4678 to store the specified value in the part of the register that corresponds
4679 to mode @var{m}. Bits outside of @var{m}, but which are within the
4680 same target word as the @code{subreg} are undefined. Bits which are
4681 outside the target word are left unchanged.
4683 This class of patterns is special in several ways. First of all, each
4684 of these names up to and including full word size @emph{must} be defined,
4685 because there is no other way to copy a datum from one place to another.
4686 If there are patterns accepting operands in larger modes,
4687 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4689 Second, these patterns are not used solely in the RTL generation pass.
4690 Even the reload pass can generate move insns to copy values from stack
4691 slots into temporary registers. When it does so, one of the operands is
4692 a hard register and the other is an operand that can need to be reloaded
4696 Therefore, when given such a pair of operands, the pattern must generate
4697 RTL which needs no reloading and needs no temporary registers---no
4698 registers other than the operands. For example, if you support the
4699 pattern with a @code{define_expand}, then in such a case the
4700 @code{define_expand} mustn't call @code{force_reg} or any other such
4701 function which might generate new pseudo registers.
4703 This requirement exists even for subword modes on a RISC machine where
4704 fetching those modes from memory normally requires several insns and
4705 some temporary registers.
4707 @findex change_address
4708 During reload a memory reference with an invalid address may be passed
4709 as an operand. Such an address will be replaced with a valid address
4710 later in the reload pass. In this case, nothing may be done with the
4711 address except to use it as it stands. If it is copied, it will not be
4712 replaced with a valid address. No attempt should be made to make such
4713 an address into a valid address and no routine (such as
4714 @code{change_address}) that will do so may be called. Note that
4715 @code{general_operand} will fail when applied to such an address.
4717 @findex reload_in_progress
4718 The global variable @code{reload_in_progress} (which must be explicitly
4719 declared if required) can be used to determine whether such special
4720 handling is required.
4722 The variety of operands that have reloads depends on the rest of the
4723 machine description, but typically on a RISC machine these can only be
4724 pseudo registers that did not get hard registers, while on other
4725 machines explicit memory references will get optional reloads.
4727 If a scratch register is required to move an object to or from memory,
4728 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4730 If there are cases which need scratch registers during or after reload,
4731 you must provide an appropriate secondary_reload target hook.
4733 @findex can_create_pseudo_p
4734 The macro @code{can_create_pseudo_p} can be used to determine if it
4735 is unsafe to create new pseudo registers. If this variable is nonzero, then
4736 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4738 The constraints on a @samp{mov@var{m}} must permit moving any hard
4739 register to any other hard register provided that
4740 @code{TARGET_HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4741 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4744 It is obligatory to support floating point @samp{mov@var{m}}
4745 instructions into and out of any registers that can hold fixed point
4746 values, because unions and structures (which have modes @code{SImode} or
4747 @code{DImode}) can be in those registers and they may have floating
4750 There may also be a need to support fixed point @samp{mov@var{m}}
4751 instructions in and out of floating point registers. Unfortunately, I
4752 have forgotten why this was so, and I don't know whether it is still
4753 true. If @code{TARGET_HARD_REGNO_MODE_OK} rejects fixed point values in
4754 floating point registers, then the constraints of the fixed point
4755 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4756 reload into a floating point register.
4758 @cindex @code{reload_in} instruction pattern
4759 @cindex @code{reload_out} instruction pattern
4760 @item @samp{reload_in@var{m}}
4761 @itemx @samp{reload_out@var{m}}
4762 These named patterns have been obsoleted by the target hook
4763 @code{secondary_reload}.
4765 Like @samp{mov@var{m}}, but used when a scratch register is required to
4766 move between operand 0 and operand 1. Operand 2 describes the scratch
4767 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4768 macro in @pxref{Register Classes}.
4770 There are special restrictions on the form of the @code{match_operand}s
4771 used in these patterns. First, only the predicate for the reload
4772 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4773 the predicates for operand 0 or 2. Second, there may be only one
4774 alternative in the constraints. Third, only a single register class
4775 letter may be used for the constraint; subsequent constraint letters
4776 are ignored. As a special exception, an empty constraint string
4777 matches the @code{ALL_REGS} register class. This may relieve ports
4778 of the burden of defining an @code{ALL_REGS} constraint letter just
4781 @cindex @code{movstrict@var{m}} instruction pattern
4782 @item @samp{movstrict@var{m}}
4783 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4784 with mode @var{m} of a register whose natural mode is wider,
4785 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4786 any of the register except the part which belongs to mode @var{m}.
4788 @cindex @code{movmisalign@var{m}} instruction pattern
4789 @item @samp{movmisalign@var{m}}
4790 This variant of a move pattern is designed to load or store a value
4791 from a memory address that is not naturally aligned for its mode.
4792 For a store, the memory will be in operand 0; for a load, the memory
4793 will be in operand 1. The other operand is guaranteed not to be a
4794 memory, so that it's easy to tell whether this is a load or store.
4796 This pattern is used by the autovectorizer, and when expanding a
4797 @code{MISALIGNED_INDIRECT_REF} expression.
4799 @cindex @code{load_multiple} instruction pattern
4800 @item @samp{load_multiple}
4801 Load several consecutive memory locations into consecutive registers.
4802 Operand 0 is the first of the consecutive registers, operand 1
4803 is the first memory location, and operand 2 is a constant: the
4804 number of consecutive registers.
4806 Define this only if the target machine really has such an instruction;
4807 do not define this if the most efficient way of loading consecutive
4808 registers from memory is to do them one at a time.
4810 On some machines, there are restrictions as to which consecutive
4811 registers can be stored into memory, such as particular starting or
4812 ending register numbers or only a range of valid counts. For those
4813 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4814 and make the pattern fail if the restrictions are not met.
4816 Write the generated insn as a @code{parallel} with elements being a
4817 @code{set} of one register from the appropriate memory location (you may
4818 also need @code{use} or @code{clobber} elements). Use a
4819 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4820 @file{rs6000.md} for examples of the use of this insn pattern.
4822 @cindex @samp{store_multiple} instruction pattern
4823 @item @samp{store_multiple}
4824 Similar to @samp{load_multiple}, but store several consecutive registers
4825 into consecutive memory locations. Operand 0 is the first of the
4826 consecutive memory locations, operand 1 is the first register, and
4827 operand 2 is a constant: the number of consecutive registers.
4829 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4830 @item @samp{vec_load_lanes@var{m}@var{n}}
4831 Perform an interleaved load of several vectors from memory operand 1
4832 into register operand 0. Both operands have mode @var{m}. The register
4833 operand is viewed as holding consecutive vectors of mode @var{n},
4834 while the memory operand is a flat array that contains the same number
4835 of elements. The operation is equivalent to:
4838 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4839 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4840 for (i = 0; i < c; i++)
4841 operand0[i][j] = operand1[j * c + i];
4844 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4845 from memory into a register of mode @samp{TI}@. The register
4846 contains two consecutive vectors of mode @samp{V4HI}@.
4848 This pattern can only be used if:
4850 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4852 is true. GCC assumes that, if a target supports this kind of
4853 instruction for some mode @var{n}, it also supports unaligned
4854 loads for vectors of mode @var{n}.
4856 This pattern is not allowed to @code{FAIL}.
4858 @cindex @code{vec_mask_load_lanes@var{m}@var{n}} instruction pattern
4859 @item @samp{vec_mask_load_lanes@var{m}@var{n}}
4860 Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional
4861 mask operand (operand 2) that specifies which elements of the destination
4862 vectors should be loaded. Other elements of the destination
4863 vectors are set to zero. The operation is equivalent to:
4866 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4867 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4869 for (i = 0; i < c; i++)
4870 operand0[i][j] = operand1[j * c + i];
4872 for (i = 0; i < c; i++)
4876 This pattern is not allowed to @code{FAIL}.
4878 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4879 @item @samp{vec_store_lanes@var{m}@var{n}}
4880 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4881 and register operands reversed. That is, the instruction is
4885 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4886 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4887 for (i = 0; i < c; i++)
4888 operand0[j * c + i] = operand1[i][j];
4891 for a memory operand 0 and register operand 1.
4893 This pattern is not allowed to @code{FAIL}.
4895 @cindex @code{vec_mask_store_lanes@var{m}@var{n}} instruction pattern
4896 @item @samp{vec_mask_store_lanes@var{m}@var{n}}
4897 Like @samp{vec_store_lanes@var{m}@var{n}}, but takes an additional
4898 mask operand (operand 2) that specifies which elements of the source
4899 vectors should be stored. The operation is equivalent to:
4902 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4903 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4905 for (i = 0; i < c; i++)
4906 operand0[j * c + i] = operand1[i][j];
4909 This pattern is not allowed to @code{FAIL}.
4911 @cindex @code{vec_set@var{m}} instruction pattern
4912 @item @samp{vec_set@var{m}}
4913 Set given field in the vector value. Operand 0 is the vector to modify,
4914 operand 1 is new value of field and operand 2 specify the field index.
4916 @cindex @code{vec_extract@var{m}@var{n}} instruction pattern
4917 @item @samp{vec_extract@var{m}@var{n}}
4918 Extract given field from the vector value. Operand 1 is the vector, operand 2
4919 specify field index and operand 0 place to store value into. The
4920 @var{n} mode is the mode of the field or vector of fields that should be
4921 extracted, should be either element mode of the vector mode @var{m}, or
4922 a vector mode with the same element mode and smaller number of elements.
4923 If @var{n} is a vector mode, the index is counted in units of that mode.
4925 @cindex @code{vec_init@var{m}@var{n}} instruction pattern
4926 @item @samp{vec_init@var{m}@var{n}}
4927 Initialize the vector to given values. Operand 0 is the vector to initialize
4928 and operand 1 is parallel containing values for individual fields. The
4929 @var{n} mode is the mode of the elements, should be either element mode of
4930 the vector mode @var{m}, or a vector mode with the same element mode and
4931 smaller number of elements.
4933 @cindex @code{vec_duplicate@var{m}} instruction pattern
4934 @item @samp{vec_duplicate@var{m}}
4935 Initialize vector output operand 0 so that each element has the value given
4936 by scalar input operand 1. The vector has mode @var{m} and the scalar has
4937 the mode appropriate for one element of @var{m}.
4939 This pattern only handles duplicates of non-constant inputs. Constant
4940 vectors go through the @code{mov@var{m}} pattern instead.
4942 This pattern is not allowed to @code{FAIL}.
4944 @cindex @code{vec_series@var{m}} instruction pattern
4945 @item @samp{vec_series@var{m}}
4946 Initialize vector output operand 0 so that element @var{i} is equal to
4947 operand 1 plus @var{i} times operand 2. In other words, create a linear
4948 series whose base value is operand 1 and whose step is operand 2.
4950 The vector output has mode @var{m} and the scalar inputs have the mode
4951 appropriate for one element of @var{m}. This pattern is not used for
4952 floating-point vectors, in order to avoid having to specify the
4953 rounding behavior for @var{i} > 1.
4955 This pattern is not allowed to @code{FAIL}.
4957 @cindex @code{while_ult@var{m}@var{n}} instruction pattern
4958 @item @code{while_ult@var{m}@var{n}}
4959 Set operand 0 to a mask that is true while incrementing operand 1
4960 gives a value that is less than operand 2. Operand 0 has mode @var{n}
4961 and operands 1 and 2 are scalar integers of mode @var{m}.
4962 The operation is equivalent to:
4965 operand0[0] = operand1 < operand2;
4966 for (i = 1; i < GET_MODE_NUNITS (@var{n}); i++)
4967 operand0[i] = operand0[i - 1] && (operand1 + i < operand2);
4970 @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern
4971 @item @samp{vec_cmp@var{m}@var{n}}
4972 Output a vector comparison. Operand 0 of mode @var{n} is the destination for
4973 predicate in operand 1 which is a signed vector comparison with operands of
4974 mode @var{m} in operands 2 and 3. Predicate is computed by element-wise
4975 evaluation of the vector comparison with a truth value of all-ones and a false
4978 @cindex @code{vec_cmpu@var{m}@var{n}} instruction pattern
4979 @item @samp{vec_cmpu@var{m}@var{n}}
4980 Similar to @code{vec_cmp@var{m}@var{n}} but perform unsigned vector comparison.
4982 @cindex @code{vec_cmpeq@var{m}@var{n}} instruction pattern
4983 @item @samp{vec_cmpeq@var{m}@var{n}}
4984 Similar to @code{vec_cmp@var{m}@var{n}} but perform equality or non-equality
4985 vector comparison only. If @code{vec_cmp@var{m}@var{n}}
4986 or @code{vec_cmpu@var{m}@var{n}} instruction pattern is supported,
4987 it will be preferred over @code{vec_cmpeq@var{m}@var{n}}, so there is
4988 no need to define this instruction pattern if the others are supported.
4990 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4991 @item @samp{vcond@var{m}@var{n}}
4992 Output a conditional vector move. Operand 0 is the destination to
4993 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4994 dependent on the outcome of the predicate in operand 3 which is a signed
4995 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4996 modes @var{m} and @var{n} should have the same size. Operand 0
4997 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4998 where @var{msk} is computed by element-wise evaluation of the vector
4999 comparison with a truth value of all-ones and a false value of all-zeros.
5001 @cindex @code{vcondu@var{m}@var{n}} instruction pattern
5002 @item @samp{vcondu@var{m}@var{n}}
5003 Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector
5006 @cindex @code{vcondeq@var{m}@var{n}} instruction pattern
5007 @item @samp{vcondeq@var{m}@var{n}}
5008 Similar to @code{vcond@var{m}@var{n}} but performs equality or
5009 non-equality vector comparison only. If @code{vcond@var{m}@var{n}}
5010 or @code{vcondu@var{m}@var{n}} instruction pattern is supported,
5011 it will be preferred over @code{vcondeq@var{m}@var{n}}, so there is
5012 no need to define this instruction pattern if the others are supported.
5014 @cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern
5015 @item @samp{vcond_mask_@var{m}@var{n}}
5016 Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed
5017 result of vector comparison.
5019 @cindex @code{maskload@var{m}@var{n}} instruction pattern
5020 @item @samp{maskload@var{m}@var{n}}
5021 Perform a masked load of vector from memory operand 1 of mode @var{m}
5022 into register operand 0. Mask is provided in register operand 2 of
5025 This pattern is not allowed to @code{FAIL}.
5027 @cindex @code{maskstore@var{m}@var{n}} instruction pattern
5028 @item @samp{maskstore@var{m}@var{n}}
5029 Perform a masked store of vector from register operand 1 of mode @var{m}
5030 into memory operand 0. Mask is provided in register operand 2 of
5033 This pattern is not allowed to @code{FAIL}.
5035 @cindex @code{vec_perm@var{m}} instruction pattern
5036 @item @samp{vec_perm@var{m}}
5037 Output a (variable) vector permutation. Operand 0 is the destination
5038 to receive elements from operand 1 and operand 2, which are of mode
5039 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
5040 vector of the same width and number of elements as mode @var{m}.
5042 The input elements are numbered from 0 in operand 1 through
5043 @math{2*@var{N}-1} in operand 2. The elements of the selector must
5044 be computed modulo @math{2*@var{N}}. Note that if
5045 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
5046 with just operand 1 and selector elements modulo @var{N}.
5048 In order to make things easy for a number of targets, if there is no
5049 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
5050 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
5051 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
5054 See also @code{TARGET_VECTORIZER_VEC_PERM_CONST}, which performs
5055 the analogous operation for constant selectors.
5057 @cindex @code{push@var{m}1} instruction pattern
5058 @item @samp{push@var{m}1}
5059 Output a push instruction. Operand 0 is value to push. Used only when
5060 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
5061 missing and in such case an @code{mov} expander is used instead, with a
5062 @code{MEM} expression forming the push operation. The @code{mov} expander
5063 method is deprecated.
5065 @cindex @code{add@var{m}3} instruction pattern
5066 @item @samp{add@var{m}3}
5067 Add operand 2 and operand 1, storing the result in operand 0. All operands
5068 must have mode @var{m}. This can be used even on two-address machines, by
5069 means of constraints requiring operands 1 and 0 to be the same location.
5071 @cindex @code{ssadd@var{m}3} instruction pattern
5072 @cindex @code{usadd@var{m}3} instruction pattern
5073 @cindex @code{sub@var{m}3} instruction pattern
5074 @cindex @code{sssub@var{m}3} instruction pattern
5075 @cindex @code{ussub@var{m}3} instruction pattern
5076 @cindex @code{mul@var{m}3} instruction pattern
5077 @cindex @code{ssmul@var{m}3} instruction pattern
5078 @cindex @code{usmul@var{m}3} instruction pattern
5079 @cindex @code{div@var{m}3} instruction pattern
5080 @cindex @code{ssdiv@var{m}3} instruction pattern
5081 @cindex @code{udiv@var{m}3} instruction pattern
5082 @cindex @code{usdiv@var{m}3} instruction pattern
5083 @cindex @code{mod@var{m}3} instruction pattern
5084 @cindex @code{umod@var{m}3} instruction pattern
5085 @cindex @code{umin@var{m}3} instruction pattern
5086 @cindex @code{umax@var{m}3} instruction pattern
5087 @cindex @code{and@var{m}3} instruction pattern
5088 @cindex @code{ior@var{m}3} instruction pattern
5089 @cindex @code{xor@var{m}3} instruction pattern
5090 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
5091 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
5092 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
5093 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
5094 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
5095 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
5096 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
5097 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
5098 Similar, for other arithmetic operations.
5100 @cindex @code{addv@var{m}4} instruction pattern
5101 @item @samp{addv@var{m}4}
5102 Like @code{add@var{m}3} but takes a @code{code_label} as operand 3 and
5103 emits code to jump to it if signed overflow occurs during the addition.
5104 This pattern is used to implement the built-in functions performing
5105 signed integer addition with overflow checking.
5107 @cindex @code{subv@var{m}4} instruction pattern
5108 @cindex @code{mulv@var{m}4} instruction pattern
5109 @item @samp{subv@var{m}4}, @samp{mulv@var{m}4}
5110 Similar, for other signed arithmetic operations.
5112 @cindex @code{uaddv@var{m}4} instruction pattern
5113 @item @samp{uaddv@var{m}4}
5114 Like @code{addv@var{m}4} but for unsigned addition. That is to
5115 say, the operation is the same as signed addition but the jump
5116 is taken only on unsigned overflow.
5118 @cindex @code{usubv@var{m}4} instruction pattern
5119 @cindex @code{umulv@var{m}4} instruction pattern
5120 @item @samp{usubv@var{m}4}, @samp{umulv@var{m}4}
5121 Similar, for other unsigned arithmetic operations.
5123 @cindex @code{addptr@var{m}3} instruction pattern
5124 @item @samp{addptr@var{m}3}
5125 Like @code{add@var{m}3} but is guaranteed to only be used for address
5126 calculations. The expanded code is not allowed to clobber the
5127 condition code. It only needs to be defined if @code{add@var{m}3}
5128 sets the condition code. If adds used for address calculations and
5129 normal adds are not compatible it is required to expand a distinct
5130 pattern (e.g. using an unspec). The pattern is used by LRA to emit
5131 address calculations. @code{add@var{m}3} is used if
5132 @code{addptr@var{m}3} is not defined.
5134 @cindex @code{fma@var{m}4} instruction pattern
5135 @item @samp{fma@var{m}4}
5136 Multiply operand 2 and operand 1, then add operand 3, storing the
5137 result in operand 0 without doing an intermediate rounding step. All
5138 operands must have mode @var{m}. This pattern is used to implement
5139 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
5140 the ISO C99 standard.
5142 @cindex @code{fms@var{m}4} instruction pattern
5143 @item @samp{fms@var{m}4}
5144 Like @code{fma@var{m}4}, except operand 3 subtracted from the
5145 product instead of added to the product. This is represented
5149 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
5152 @cindex @code{fnma@var{m}4} instruction pattern
5153 @item @samp{fnma@var{m}4}
5154 Like @code{fma@var{m}4} except that the intermediate product
5155 is negated before being added to operand 3. This is represented
5159 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
5162 @cindex @code{fnms@var{m}4} instruction pattern
5163 @item @samp{fnms@var{m}4}
5164 Like @code{fms@var{m}4} except that the intermediate product
5165 is negated before subtracting operand 3. This is represented
5169 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
5172 @cindex @code{min@var{m}3} instruction pattern
5173 @cindex @code{max@var{m}3} instruction pattern
5174 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
5175 Signed minimum and maximum operations. When used with floating point,
5176 if both operands are zeros, or if either operand is @code{NaN}, then
5177 it is unspecified which of the two operands is returned as the result.
5179 @cindex @code{fmin@var{m}3} instruction pattern
5180 @cindex @code{fmax@var{m}3} instruction pattern
5181 @item @samp{fmin@var{m}3}, @samp{fmax@var{m}3}
5182 IEEE-conformant minimum and maximum operations. If one operand is a quiet
5183 @code{NaN}, then the other operand is returned. If both operands are quiet
5184 @code{NaN}, then a quiet @code{NaN} is returned. In the case when gcc supports
5185 signaling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
5186 raised and a quiet @code{NaN} is returned.
5188 All operands have mode @var{m}, which is a scalar or vector
5189 floating-point mode. These patterns are not allowed to @code{FAIL}.
5191 @cindex @code{reduc_smin_scal_@var{m}} instruction pattern
5192 @cindex @code{reduc_smax_scal_@var{m}} instruction pattern
5193 @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}}
5194 Find the signed minimum/maximum of the elements of a vector. The vector is
5195 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5196 the elements of the input vector.
5198 @cindex @code{reduc_umin_scal_@var{m}} instruction pattern
5199 @cindex @code{reduc_umax_scal_@var{m}} instruction pattern
5200 @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}}
5201 Find the unsigned minimum/maximum of the elements of a vector. The vector is
5202 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5203 the elements of the input vector.
5205 @cindex @code{reduc_plus_scal_@var{m}} instruction pattern
5206 @item @samp{reduc_plus_scal_@var{m}}
5207 Compute the sum of the elements of a vector. The vector is operand 1, and
5208 operand 0 is the scalar result, with mode equal to the mode of the elements of
5211 @cindex @code{reduc_and_scal_@var{m}} instruction pattern
5212 @item @samp{reduc_and_scal_@var{m}}
5213 @cindex @code{reduc_ior_scal_@var{m}} instruction pattern
5214 @itemx @samp{reduc_ior_scal_@var{m}}
5215 @cindex @code{reduc_xor_scal_@var{m}} instruction pattern
5216 @itemx @samp{reduc_xor_scal_@var{m}}
5217 Compute the bitwise @code{AND}/@code{IOR}/@code{XOR} reduction of the elements
5218 of a vector of mode @var{m}. Operand 1 is the vector input and operand 0
5219 is the scalar result. The mode of the scalar result is the same as one
5222 @cindex @code{extract_last_@var{m}} instruction pattern
5223 @item @code{extract_last_@var{m}}
5224 Find the last set bit in mask operand 1 and extract the associated element
5225 of vector operand 2. Store the result in scalar operand 0. Operand 2
5226 has vector mode @var{m} while operand 0 has the mode appropriate for one
5227 element of @var{m}. Operand 1 has the usual mask mode for vectors of mode
5228 @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5230 @cindex @code{fold_extract_last_@var{m}} instruction pattern
5231 @item @code{fold_extract_last_@var{m}}
5232 If any bits of mask operand 2 are set, find the last set bit, extract
5233 the associated element from vector operand 3, and store the result
5234 in operand 0. Store operand 1 in operand 0 otherwise. Operand 3
5235 has mode @var{m} and operands 0 and 1 have the mode appropriate for
5236 one element of @var{m}. Operand 2 has the usual mask mode for vectors
5237 of mode @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5239 @cindex @code{fold_left_plus_@var{m}} instruction pattern
5240 @item @code{fold_left_plus_@var{m}}
5241 Take scalar operand 1 and successively add each element from vector
5242 operand 2. Store the result in scalar operand 0. The vector has
5243 mode @var{m} and the scalars have the mode appropriate for one
5244 element of @var{m}. The operation is strictly in-order: there is
5247 @cindex @code{sdot_prod@var{m}} instruction pattern
5248 @item @samp{sdot_prod@var{m}}
5249 @cindex @code{udot_prod@var{m}} instruction pattern
5250 @itemx @samp{udot_prod@var{m}}
5251 Compute the sum of the products of two signed/unsigned elements.
5252 Operand 1 and operand 2 are of the same mode. Their product, which is of a
5253 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
5254 wider than the mode of the product. The result is placed in operand 0, which
5255 is of the same mode as operand 3.
5257 @cindex @code{ssad@var{m}} instruction pattern
5258 @item @samp{ssad@var{m}}
5259 @cindex @code{usad@var{m}} instruction pattern
5260 @item @samp{usad@var{m}}
5261 Compute the sum of absolute differences of two signed/unsigned elements.
5262 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
5263 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
5264 equal or wider than the mode of the absolute difference. The result is placed
5265 in operand 0, which is of the same mode as operand 3.
5267 @cindex @code{widen_ssum@var{m3}} instruction pattern
5268 @item @samp{widen_ssum@var{m3}}
5269 @cindex @code{widen_usum@var{m3}} instruction pattern
5270 @itemx @samp{widen_usum@var{m3}}
5271 Operands 0 and 2 are of the same mode, which is wider than the mode of
5272 operand 1. Add operand 1 to operand 2 and place the widened result in
5273 operand 0. (This is used express accumulation of elements into an accumulator
5276 @cindex @code{vec_shl_insert_@var{m}} instruction pattern
5277 @item @samp{vec_shl_insert_@var{m}}
5278 Shift the elements in vector input operand 1 left one element (i.e.
5279 away from element 0) and fill the vacated element 0 with the scalar
5280 in operand 2. Store the result in vector output operand 0. Operands
5281 0 and 1 have mode @var{m} and operand 2 has the mode appropriate for
5282 one element of @var{m}.
5284 @cindex @code{vec_shr_@var{m}} instruction pattern
5285 @item @samp{vec_shr_@var{m}}
5286 Whole vector right shift in bits, i.e. towards element 0.
5287 Operand 1 is a vector to be shifted.
5288 Operand 2 is an integer shift amount in bits.
5289 Operand 0 is where the resulting shifted vector is stored.
5290 The output and input vectors should have the same modes.
5292 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
5293 @item @samp{vec_pack_trunc_@var{m}}
5294 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5295 are vectors of the same mode having N integral or floating point elements
5296 of size S@. Operand 0 is the resulting vector in which 2*N elements of
5297 size N/2 are concatenated after narrowing them down using truncation.
5299 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
5300 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
5301 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
5302 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5303 are vectors of the same mode having N integral elements of size S.
5304 Operand 0 is the resulting vector in which the elements of the two input
5305 vectors are concatenated after narrowing them down using signed/unsigned
5306 saturating arithmetic.
5308 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
5309 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
5310 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
5311 Narrow, convert to signed/unsigned integral type and merge the elements
5312 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5313 floating point elements of size S@. Operand 0 is the resulting vector
5314 in which 2*N elements of size N/2 are concatenated.
5316 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
5317 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
5318 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
5319 Extract and widen (promote) the high/low part of a vector of signed
5320 integral or floating point elements. The input vector (operand 1) has N
5321 elements of size S@. Widen (promote) the high/low elements of the vector
5322 using signed or floating point extension and place the resulting N/2
5323 values of size 2*S in the output vector (operand 0).
5325 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
5326 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
5327 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
5328 Extract and widen (promote) the high/low part of a vector of unsigned
5329 integral elements. The input vector (operand 1) has N elements of size S.
5330 Widen (promote) the high/low elements of the vector using zero extension and
5331 place the resulting N/2 values of size 2*S in the output vector (operand 0).
5333 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
5334 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
5335 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
5336 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
5337 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
5338 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
5339 Extract, convert to floating point type and widen the high/low part of a
5340 vector of signed/unsigned integral elements. The input vector (operand 1)
5341 has N elements of size S@. Convert the high/low elements of the vector using
5342 floating point conversion and place the resulting N/2 values of size 2*S in
5343 the output vector (operand 0).
5345 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
5346 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
5347 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
5348 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
5349 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
5350 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
5351 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
5352 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
5353 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
5354 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
5355 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
5356 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
5357 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
5358 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
5359 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
5360 in the output vector (operand 0). A target shouldn't implement even/odd pattern
5361 pair if it is less efficient than lo/hi one.
5363 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
5364 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
5365 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
5366 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
5367 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
5368 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
5369 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
5370 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
5371 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
5372 output vector (operand 0).
5374 @cindex @code{mulhisi3} instruction pattern
5375 @item @samp{mulhisi3}
5376 Multiply operands 1 and 2, which have mode @code{HImode}, and store
5377 a @code{SImode} product in operand 0.
5379 @cindex @code{mulqihi3} instruction pattern
5380 @cindex @code{mulsidi3} instruction pattern
5381 @item @samp{mulqihi3}, @samp{mulsidi3}
5382 Similar widening-multiplication instructions of other widths.
5384 @cindex @code{umulqihi3} instruction pattern
5385 @cindex @code{umulhisi3} instruction pattern
5386 @cindex @code{umulsidi3} instruction pattern
5387 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
5388 Similar widening-multiplication instructions that do unsigned
5391 @cindex @code{usmulqihi3} instruction pattern
5392 @cindex @code{usmulhisi3} instruction pattern
5393 @cindex @code{usmulsidi3} instruction pattern
5394 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
5395 Similar widening-multiplication instructions that interpret the first
5396 operand as unsigned and the second operand as signed, then do a signed
5399 @cindex @code{smul@var{m}3_highpart} instruction pattern
5400 @item @samp{smul@var{m}3_highpart}
5401 Perform a signed multiplication of operands 1 and 2, which have mode
5402 @var{m}, and store the most significant half of the product in operand 0.
5403 The least significant half of the product is discarded.
5405 @cindex @code{umul@var{m}3_highpart} instruction pattern
5406 @item @samp{umul@var{m}3_highpart}
5407 Similar, but the multiplication is unsigned.
5409 @cindex @code{madd@var{m}@var{n}4} instruction pattern
5410 @item @samp{madd@var{m}@var{n}4}
5411 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
5412 operand 3, and store the result in operand 0. Operands 1 and 2
5413 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5414 Both modes must be integer or fixed-point modes and @var{n} must be twice
5415 the size of @var{m}.
5417 In other words, @code{madd@var{m}@var{n}4} is like
5418 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
5420 These instructions are not allowed to @code{FAIL}.
5422 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
5423 @item @samp{umadd@var{m}@var{n}4}
5424 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5425 operands instead of sign-extending them.
5427 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5428 @item @samp{ssmadd@var{m}@var{n}4}
5429 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5432 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5433 @item @samp{usmadd@var{m}@var{n}4}
5434 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5435 unsigned-saturating.
5437 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5438 @item @samp{msub@var{m}@var{n}4}
5439 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5440 result from operand 3, and store the result in operand 0. Operands 1 and 2
5441 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5442 Both modes must be integer or fixed-point modes and @var{n} must be twice
5443 the size of @var{m}.
5445 In other words, @code{msub@var{m}@var{n}4} is like
5446 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5449 These instructions are not allowed to @code{FAIL}.
5451 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5452 @item @samp{umsub@var{m}@var{n}4}
5453 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5454 operands instead of sign-extending them.
5456 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5457 @item @samp{ssmsub@var{m}@var{n}4}
5458 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5461 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5462 @item @samp{usmsub@var{m}@var{n}4}
5463 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5464 unsigned-saturating.
5466 @cindex @code{divmod@var{m}4} instruction pattern
5467 @item @samp{divmod@var{m}4}
5468 Signed division that produces both a quotient and a remainder.
5469 Operand 1 is divided by operand 2 to produce a quotient stored
5470 in operand 0 and a remainder stored in operand 3.
5472 For machines with an instruction that produces both a quotient and a
5473 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5474 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5475 allows optimization in the relatively common case when both the quotient
5476 and remainder are computed.
5478 If an instruction that just produces a quotient or just a remainder
5479 exists and is more efficient than the instruction that produces both,
5480 write the output routine of @samp{divmod@var{m}4} to call
5481 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5482 quotient or remainder and generate the appropriate instruction.
5484 @cindex @code{udivmod@var{m}4} instruction pattern
5485 @item @samp{udivmod@var{m}4}
5486 Similar, but does unsigned division.
5488 @anchor{shift patterns}
5489 @cindex @code{ashl@var{m}3} instruction pattern
5490 @cindex @code{ssashl@var{m}3} instruction pattern
5491 @cindex @code{usashl@var{m}3} instruction pattern
5492 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5493 Arithmetic-shift operand 1 left by a number of bits specified by operand
5494 2, and store the result in operand 0. Here @var{m} is the mode of
5495 operand 0 and operand 1; operand 2's mode is specified by the
5496 instruction pattern, and the compiler will convert the operand to that
5497 mode before generating the instruction. The shift or rotate expander
5498 or instruction pattern should explicitly specify the mode of the operand 2,
5499 it should never be @code{VOIDmode}. The meaning of out-of-range shift
5500 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5501 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5503 @cindex @code{ashr@var{m}3} instruction pattern
5504 @cindex @code{lshr@var{m}3} instruction pattern
5505 @cindex @code{rotl@var{m}3} instruction pattern
5506 @cindex @code{rotr@var{m}3} instruction pattern
5507 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5508 Other shift and rotate instructions, analogous to the
5509 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5511 @cindex @code{vashl@var{m}3} instruction pattern
5512 @cindex @code{vashr@var{m}3} instruction pattern
5513 @cindex @code{vlshr@var{m}3} instruction pattern
5514 @cindex @code{vrotl@var{m}3} instruction pattern
5515 @cindex @code{vrotr@var{m}3} instruction pattern
5516 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5517 Vector shift and rotate instructions that take vectors as operand 2
5518 instead of a scalar type.
5520 @cindex @code{bswap@var{m}2} instruction pattern
5521 @item @samp{bswap@var{m}2}
5522 Reverse the order of bytes of operand 1 and store the result in operand 0.
5524 @cindex @code{neg@var{m}2} instruction pattern
5525 @cindex @code{ssneg@var{m}2} instruction pattern
5526 @cindex @code{usneg@var{m}2} instruction pattern
5527 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5528 Negate operand 1 and store the result in operand 0.
5530 @cindex @code{negv@var{m}3} instruction pattern
5531 @item @samp{negv@var{m}3}
5532 Like @code{neg@var{m}2} but takes a @code{code_label} as operand 2 and
5533 emits code to jump to it if signed overflow occurs during the negation.
5535 @cindex @code{abs@var{m}2} instruction pattern
5536 @item @samp{abs@var{m}2}
5537 Store the absolute value of operand 1 into operand 0.
5539 @cindex @code{sqrt@var{m}2} instruction pattern
5540 @item @samp{sqrt@var{m}2}
5541 Store the square root of operand 1 into operand 0. Both operands have
5542 mode @var{m}, which is a scalar or vector floating-point mode.
5544 This pattern is not allowed to @code{FAIL}.
5546 @cindex @code{rsqrt@var{m}2} instruction pattern
5547 @item @samp{rsqrt@var{m}2}
5548 Store the reciprocal of the square root of operand 1 into operand 0.
5549 Both operands have mode @var{m}, which is a scalar or vector
5550 floating-point mode.
5552 On most architectures this pattern is only approximate, so either
5553 its C condition or the @code{TARGET_OPTAB_SUPPORTED_P} hook should
5554 check for the appropriate math flags. (Using the C condition is
5555 more direct, but using @code{TARGET_OPTAB_SUPPORTED_P} can be useful
5556 if a target-specific built-in also uses the @samp{rsqrt@var{m}2}
5559 This pattern is not allowed to @code{FAIL}.
5561 @cindex @code{fmod@var{m}3} instruction pattern
5562 @item @samp{fmod@var{m}3}
5563 Store the remainder of dividing operand 1 by operand 2 into
5564 operand 0, rounded towards zero to an integer. All operands have
5565 mode @var{m}, which is a scalar or vector floating-point mode.
5567 This pattern is not allowed to @code{FAIL}.
5569 @cindex @code{remainder@var{m}3} instruction pattern
5570 @item @samp{remainder@var{m}3}
5571 Store the remainder of dividing operand 1 by operand 2 into
5572 operand 0, rounded to the nearest integer. All operands have
5573 mode @var{m}, which is a scalar or vector floating-point mode.
5575 This pattern is not allowed to @code{FAIL}.
5577 @cindex @code{scalb@var{m}3} instruction pattern
5578 @item @samp{scalb@var{m}3}
5579 Raise @code{FLT_RADIX} to the power of operand 2, multiply it by
5580 operand 1, and store the result in operand 0. All operands have
5581 mode @var{m}, which is a scalar or vector floating-point mode.
5583 This pattern is not allowed to @code{FAIL}.
5585 @cindex @code{ldexp@var{m}3} instruction pattern
5586 @item @samp{ldexp@var{m}3}
5587 Raise 2 to the power of operand 2, multiply it by operand 1, and store
5588 the result in operand 0. Operands 0 and 1 have mode @var{m}, which is
5589 a scalar or vector floating-point mode. Operand 2's mode has
5590 the same number of elements as @var{m} and each element is wide
5591 enough to store an @code{int}. The integers are signed.
5593 This pattern is not allowed to @code{FAIL}.
5595 @cindex @code{cos@var{m}2} instruction pattern
5596 @item @samp{cos@var{m}2}
5597 Store the cosine of operand 1 into operand 0. Both operands have
5598 mode @var{m}, which is a scalar or vector floating-point mode.
5600 This pattern is not allowed to @code{FAIL}.
5602 @cindex @code{sin@var{m}2} instruction pattern
5603 @item @samp{sin@var{m}2}
5604 Store the sine of operand 1 into operand 0. Both operands have
5605 mode @var{m}, which is a scalar or vector floating-point mode.
5607 This pattern is not allowed to @code{FAIL}.
5609 @cindex @code{sincos@var{m}3} instruction pattern
5610 @item @samp{sincos@var{m}3}
5611 Store the cosine of operand 2 into operand 0 and the sine of
5612 operand 2 into operand 1. All operands have mode @var{m},
5613 which is a scalar or vector floating-point mode.
5615 Targets that can calculate the sine and cosine simultaneously can
5616 implement this pattern as opposed to implementing individual
5617 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5618 and @code{cos} built-in functions will then be expanded to the
5619 @code{sincos@var{m}3} pattern, with one of the output values
5622 @cindex @code{tan@var{m}2} instruction pattern
5623 @item @samp{tan@var{m}2}
5624 Store the tangent of operand 1 into operand 0. Both operands have
5625 mode @var{m}, which is a scalar or vector floating-point mode.
5627 This pattern is not allowed to @code{FAIL}.
5629 @cindex @code{asin@var{m}2} instruction pattern
5630 @item @samp{asin@var{m}2}
5631 Store the arc sine of operand 1 into operand 0. Both operands have
5632 mode @var{m}, which is a scalar or vector floating-point mode.
5634 This pattern is not allowed to @code{FAIL}.
5636 @cindex @code{acos@var{m}2} instruction pattern
5637 @item @samp{acos@var{m}2}
5638 Store the arc cosine of operand 1 into operand 0. Both operands have
5639 mode @var{m}, which is a scalar or vector floating-point mode.
5641 This pattern is not allowed to @code{FAIL}.
5643 @cindex @code{atan@var{m}2} instruction pattern
5644 @item @samp{atan@var{m}2}
5645 Store the arc tangent of operand 1 into operand 0. Both operands have
5646 mode @var{m}, which is a scalar or vector floating-point mode.
5648 This pattern is not allowed to @code{FAIL}.
5650 @cindex @code{exp@var{m}2} instruction pattern
5651 @item @samp{exp@var{m}2}
5652 Raise e (the base of natural logarithms) to the power of operand 1
5653 and store the result in operand 0. Both operands have mode @var{m},
5654 which is a scalar or vector floating-point mode.
5656 This pattern is not allowed to @code{FAIL}.
5658 @cindex @code{expm1@var{m}2} instruction pattern
5659 @item @samp{expm1@var{m}2}
5660 Raise e (the base of natural logarithms) to the power of operand 1,
5661 subtract 1, and store the result in operand 0. Both operands have
5662 mode @var{m}, which is a scalar or vector floating-point mode.
5664 For inputs close to zero, the pattern is expected to be more
5665 accurate than a separate @code{exp@var{m}2} and @code{sub@var{m}3}
5668 This pattern is not allowed to @code{FAIL}.
5670 @cindex @code{exp10@var{m}2} instruction pattern
5671 @item @samp{exp10@var{m}2}
5672 Raise 10 to the power of operand 1 and store the result in operand 0.
5673 Both operands have mode @var{m}, which is a scalar or vector
5674 floating-point mode.
5676 This pattern is not allowed to @code{FAIL}.
5678 @cindex @code{exp2@var{m}2} instruction pattern
5679 @item @samp{exp2@var{m}2}
5680 Raise 2 to the power of operand 1 and store the result in operand 0.
5681 Both operands have mode @var{m}, which is a scalar or vector
5682 floating-point mode.
5684 This pattern is not allowed to @code{FAIL}.
5686 @cindex @code{log@var{m}2} instruction pattern
5687 @item @samp{log@var{m}2}
5688 Store the natural logarithm of operand 1 into operand 0. Both operands
5689 have mode @var{m}, which is a scalar or vector floating-point mode.
5691 This pattern is not allowed to @code{FAIL}.
5693 @cindex @code{log1p@var{m}2} instruction pattern
5694 @item @samp{log1p@var{m}2}
5695 Add 1 to operand 1, compute the natural logarithm, and store
5696 the result in operand 0. Both operands have mode @var{m}, which is
5697 a scalar or vector floating-point mode.
5699 For inputs close to zero, the pattern is expected to be more
5700 accurate than a separate @code{add@var{m}3} and @code{log@var{m}2}
5703 This pattern is not allowed to @code{FAIL}.
5705 @cindex @code{log10@var{m}2} instruction pattern
5706 @item @samp{log10@var{m}2}
5707 Store the base-10 logarithm of operand 1 into operand 0. Both operands
5708 have mode @var{m}, which is a scalar or vector floating-point mode.
5710 This pattern is not allowed to @code{FAIL}.
5712 @cindex @code{log2@var{m}2} instruction pattern
5713 @item @samp{log2@var{m}2}
5714 Store the base-2 logarithm of operand 1 into operand 0. Both operands
5715 have mode @var{m}, which is a scalar or vector floating-point mode.
5717 This pattern is not allowed to @code{FAIL}.
5719 @cindex @code{logb@var{m}2} instruction pattern
5720 @item @samp{logb@var{m}2}
5721 Store the base-@code{FLT_RADIX} logarithm of operand 1 into operand 0.
5722 Both operands have mode @var{m}, which is a scalar or vector
5723 floating-point mode.
5725 This pattern is not allowed to @code{FAIL}.
5727 @cindex @code{significand@var{m}2} instruction pattern
5728 @item @samp{significand@var{m}2}
5729 Store the significand of floating-point operand 1 in operand 0.
5730 Both operands have mode @var{m}, which is a scalar or vector
5731 floating-point mode.
5733 This pattern is not allowed to @code{FAIL}.
5735 @cindex @code{pow@var{m}3} instruction pattern
5736 @item @samp{pow@var{m}3}
5737 Store the value of operand 1 raised to the exponent operand 2
5738 into operand 0. All operands have mode @var{m}, which is a scalar
5739 or vector floating-point mode.
5741 This pattern is not allowed to @code{FAIL}.
5743 @cindex @code{atan2@var{m}3} instruction pattern
5744 @item @samp{atan2@var{m}3}
5745 Store the arc tangent (inverse tangent) of operand 1 divided by
5746 operand 2 into operand 0, using the signs of both arguments to
5747 determine the quadrant of the result. All operands have mode
5748 @var{m}, which is a scalar or vector floating-point mode.
5750 This pattern is not allowed to @code{FAIL}.
5752 @cindex @code{floor@var{m}2} instruction pattern
5753 @item @samp{floor@var{m}2}
5754 Store the largest integral value not greater than operand 1 in operand 0.
5755 Both operands have mode @var{m}, which is a scalar or vector
5756 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
5757 effect, the ``inexact'' exception may be raised for noninteger
5758 operands; otherwise, it may not.
5760 This pattern is not allowed to @code{FAIL}.
5762 @cindex @code{btrunc@var{m}2} instruction pattern
5763 @item @samp{btrunc@var{m}2}
5764 Round operand 1 to an integer, towards zero, and store the result in
5765 operand 0. Both operands have mode @var{m}, which is a scalar or
5766 vector floating-point mode. If @option{-ffp-int-builtin-inexact} is
5767 in effect, the ``inexact'' exception may be raised for noninteger
5768 operands; otherwise, it may not.
5770 This pattern is not allowed to @code{FAIL}.
5772 @cindex @code{round@var{m}2} instruction pattern
5773 @item @samp{round@var{m}2}
5774 Round operand 1 to the nearest integer, rounding away from zero in the
5775 event of a tie, and store the result in operand 0. Both operands have
5776 mode @var{m}, which is a scalar or vector floating-point mode. If
5777 @option{-ffp-int-builtin-inexact} is in effect, the ``inexact''
5778 exception may be raised for noninteger operands; otherwise, it may
5781 This pattern is not allowed to @code{FAIL}.
5783 @cindex @code{ceil@var{m}2} instruction pattern
5784 @item @samp{ceil@var{m}2}
5785 Store the smallest integral value not less than operand 1 in operand 0.
5786 Both operands have mode @var{m}, which is a scalar or vector
5787 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
5788 effect, the ``inexact'' exception may be raised for noninteger
5789 operands; otherwise, it may not.
5791 This pattern is not allowed to @code{FAIL}.
5793 @cindex @code{nearbyint@var{m}2} instruction pattern
5794 @item @samp{nearbyint@var{m}2}
5795 Round operand 1 to an integer, using the current rounding mode, and
5796 store the result in operand 0. Do not raise an inexact condition when
5797 the result is different from the argument. Both operands have mode
5798 @var{m}, which is a scalar or vector floating-point mode.
5800 This pattern is not allowed to @code{FAIL}.
5802 @cindex @code{rint@var{m}2} instruction pattern
5803 @item @samp{rint@var{m}2}
5804 Round operand 1 to an integer, using the current rounding mode, and
5805 store the result in operand 0. Raise an inexact condition when
5806 the result is different from the argument. Both operands have mode
5807 @var{m}, which is a scalar or vector floating-point mode.
5809 This pattern is not allowed to @code{FAIL}.
5811 @cindex @code{lrint@var{m}@var{n}2}
5812 @item @samp{lrint@var{m}@var{n}2}
5813 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5814 point mode @var{n} as a signed number according to the current
5815 rounding mode and store in operand 0 (which has mode @var{n}).
5817 @cindex @code{lround@var{m}@var{n}2}
5818 @item @samp{lround@var{m}@var{n}2}
5819 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5820 point mode @var{n} as a signed number rounding to nearest and away
5821 from zero and store in operand 0 (which has mode @var{n}).
5823 @cindex @code{lfloor@var{m}@var{n}2}
5824 @item @samp{lfloor@var{m}@var{n}2}
5825 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5826 point mode @var{n} as a signed number rounding down and store in
5827 operand 0 (which has mode @var{n}).
5829 @cindex @code{lceil@var{m}@var{n}2}
5830 @item @samp{lceil@var{m}@var{n}2}
5831 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5832 point mode @var{n} as a signed number rounding up and store in
5833 operand 0 (which has mode @var{n}).
5835 @cindex @code{copysign@var{m}3} instruction pattern
5836 @item @samp{copysign@var{m}3}
5837 Store a value with the magnitude of operand 1 and the sign of operand
5838 2 into operand 0. All operands have mode @var{m}, which is a scalar or
5839 vector floating-point mode.
5841 This pattern is not allowed to @code{FAIL}.
5843 @cindex @code{ffs@var{m}2} instruction pattern
5844 @item @samp{ffs@var{m}2}
5845 Store into operand 0 one plus the index of the least significant 1-bit
5846 of operand 1. If operand 1 is zero, store zero.
5848 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5849 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5850 integer mode is suitable for the target. The compiler will insert
5851 conversion instructions as necessary (typically to convert the result
5852 to the same width as @code{int}). When @var{m} is a vector, both
5853 operands must have mode @var{m}.
5855 This pattern is not allowed to @code{FAIL}.
5857 @cindex @code{clrsb@var{m}2} instruction pattern
5858 @item @samp{clrsb@var{m}2}
5859 Count leading redundant sign bits.
5860 Store into operand 0 the number of redundant sign bits in operand 1, starting
5861 at the most significant bit position.
5862 A redundant sign bit is defined as any sign bit after the first. As such,
5863 this count will be one less than the count of leading sign bits.
5865 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5866 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5867 integer mode is suitable for the target. The compiler will insert
5868 conversion instructions as necessary (typically to convert the result
5869 to the same width as @code{int}). When @var{m} is a vector, both
5870 operands must have mode @var{m}.
5872 This pattern is not allowed to @code{FAIL}.
5874 @cindex @code{clz@var{m}2} instruction pattern
5875 @item @samp{clz@var{m}2}
5876 Store into operand 0 the number of leading 0-bits in operand 1, starting
5877 at the most significant bit position. If operand 1 is 0, the
5878 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5879 the result is undefined or has a useful value.
5881 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5882 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5883 integer mode is suitable for the target. The compiler will insert
5884 conversion instructions as necessary (typically to convert the result
5885 to the same width as @code{int}). When @var{m} is a vector, both
5886 operands must have mode @var{m}.
5888 This pattern is not allowed to @code{FAIL}.
5890 @cindex @code{ctz@var{m}2} instruction pattern
5891 @item @samp{ctz@var{m}2}
5892 Store into operand 0 the number of trailing 0-bits in operand 1, starting
5893 at the least significant bit position. If operand 1 is 0, the
5894 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5895 the result is undefined or has a useful value.
5897 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5898 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5899 integer mode is suitable for the target. The compiler will insert
5900 conversion instructions as necessary (typically to convert the result
5901 to the same width as @code{int}). When @var{m} is a vector, both
5902 operands must have mode @var{m}.
5904 This pattern is not allowed to @code{FAIL}.
5906 @cindex @code{popcount@var{m}2} instruction pattern
5907 @item @samp{popcount@var{m}2}
5908 Store into operand 0 the number of 1-bits in operand 1.
5910 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5911 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5912 integer mode is suitable for the target. The compiler will insert
5913 conversion instructions as necessary (typically to convert the result
5914 to the same width as @code{int}). When @var{m} is a vector, both
5915 operands must have mode @var{m}.
5917 This pattern is not allowed to @code{FAIL}.
5919 @cindex @code{parity@var{m}2} instruction pattern
5920 @item @samp{parity@var{m}2}
5921 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
5922 in operand 1 modulo 2.
5924 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5925 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5926 integer mode is suitable for the target. The compiler will insert
5927 conversion instructions as necessary (typically to convert the result
5928 to the same width as @code{int}). When @var{m} is a vector, both
5929 operands must have mode @var{m}.
5931 This pattern is not allowed to @code{FAIL}.
5933 @cindex @code{one_cmpl@var{m}2} instruction pattern
5934 @item @samp{one_cmpl@var{m}2}
5935 Store the bitwise-complement of operand 1 into operand 0.
5937 @cindex @code{movmem@var{m}} instruction pattern
5938 @item @samp{movmem@var{m}}
5939 Block move instruction. The destination and source blocks of memory
5940 are the first two operands, and both are @code{mem:BLK}s with an
5941 address in mode @code{Pmode}.
5943 The number of bytes to move is the third operand, in mode @var{m}.
5944 Usually, you specify @code{Pmode} for @var{m}. However, if you can
5945 generate better code knowing the range of valid lengths is smaller than
5946 those representable in a full Pmode pointer, you should provide
5948 mode corresponding to the range of values you can handle efficiently
5949 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
5950 that appear negative) and also a pattern with @code{Pmode}.
5952 The fourth operand is the known shared alignment of the source and
5953 destination, in the form of a @code{const_int} rtx. Thus, if the
5954 compiler knows that both source and destination are word-aligned,
5955 it may provide the value 4 for this operand.
5957 Optional operands 5 and 6 specify expected alignment and size of block
5958 respectively. The expected alignment differs from alignment in operand 4
5959 in a way that the blocks are not required to be aligned according to it in
5960 all cases. This expected alignment is also in bytes, just like operand 4.
5961 Expected size, when unknown, is set to @code{(const_int -1)}.
5963 Descriptions of multiple @code{movmem@var{m}} patterns can only be
5964 beneficial if the patterns for smaller modes have fewer restrictions
5965 on their first, second and fourth operands. Note that the mode @var{m}
5966 in @code{movmem@var{m}} does not impose any restriction on the mode of
5967 individually moved data units in the block.
5969 These patterns need not give special consideration to the possibility
5970 that the source and destination strings might overlap.
5972 @cindex @code{movstr} instruction pattern
5974 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
5975 an output operand in mode @code{Pmode}. The addresses of the
5976 destination and source strings are operands 1 and 2, and both are
5977 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
5978 the expansion of this pattern should store in operand 0 the address in
5979 which the @code{NUL} terminator was stored in the destination string.
5981 This patern has also several optional operands that are same as in
5984 @cindex @code{setmem@var{m}} instruction pattern
5985 @item @samp{setmem@var{m}}
5986 Block set instruction. The destination string is the first operand,
5987 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
5988 number of bytes to set is the second operand, in mode @var{m}. The value to
5989 initialize the memory with is the third operand. Targets that only support the
5990 clearing of memory should reject any value that is not the constant 0. See
5991 @samp{movmem@var{m}} for a discussion of the choice of mode.
5993 The fourth operand is the known alignment of the destination, in the form
5994 of a @code{const_int} rtx. Thus, if the compiler knows that the
5995 destination is word-aligned, it may provide the value 4 for this
5998 Optional operands 5 and 6 specify expected alignment and size of block
5999 respectively. The expected alignment differs from alignment in operand 4
6000 in a way that the blocks are not required to be aligned according to it in
6001 all cases. This expected alignment is also in bytes, just like operand 4.
6002 Expected size, when unknown, is set to @code{(const_int -1)}.
6003 Operand 7 is the minimal size of the block and operand 8 is the
6004 maximal size of the block (NULL if it can not be represented as CONST_INT).
6005 Operand 9 is the probable maximal size (i.e. we can not rely on it for correctness,
6006 but it can be used for choosing proper code sequence for a given size).
6008 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
6010 @cindex @code{cmpstrn@var{m}} instruction pattern
6011 @item @samp{cmpstrn@var{m}}
6012 String compare instruction, with five operands. Operand 0 is the output;
6013 it has mode @var{m}. The remaining four operands are like the operands
6014 of @samp{movmem@var{m}}. The two memory blocks specified are compared
6015 byte by byte in lexicographic order starting at the beginning of each
6016 string. The instruction is not allowed to prefetch more than one byte
6017 at a time since either string may end in the first byte and reading past
6018 that may access an invalid page or segment and cause a fault. The
6019 comparison terminates early if the fetched bytes are different or if
6020 they are equal to zero. The effect of the instruction is to store a
6021 value in operand 0 whose sign indicates the result of the comparison.
6023 @cindex @code{cmpstr@var{m}} instruction pattern
6024 @item @samp{cmpstr@var{m}}
6025 String compare instruction, without known maximum length. Operand 0 is the
6026 output; it has mode @var{m}. The second and third operand are the blocks of
6027 memory to be compared; both are @code{mem:BLK} with an address in mode
6030 The fourth operand is the known shared alignment of the source and
6031 destination, in the form of a @code{const_int} rtx. Thus, if the
6032 compiler knows that both source and destination are word-aligned,
6033 it may provide the value 4 for this operand.
6035 The two memory blocks specified are compared byte by byte in lexicographic
6036 order starting at the beginning of each string. The instruction is not allowed
6037 to prefetch more than one byte at a time since either string may end in the
6038 first byte and reading past that may access an invalid page or segment and
6039 cause a fault. The comparison will terminate when the fetched bytes
6040 are different or if they are equal to zero. The effect of the
6041 instruction is to store a value in operand 0 whose sign indicates the
6042 result of the comparison.
6044 @cindex @code{cmpmem@var{m}} instruction pattern
6045 @item @samp{cmpmem@var{m}}
6046 Block compare instruction, with five operands like the operands
6047 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
6048 byte by byte in lexicographic order starting at the beginning of each
6049 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
6050 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
6051 the comparison will not stop if both bytes are zero. The effect of
6052 the instruction is to store a value in operand 0 whose sign indicates
6053 the result of the comparison.
6055 @cindex @code{strlen@var{m}} instruction pattern
6056 @item @samp{strlen@var{m}}
6057 Compute the length of a string, with three operands.
6058 Operand 0 is the result (of mode @var{m}), operand 1 is
6059 a @code{mem} referring to the first character of the string,
6060 operand 2 is the character to search for (normally zero),
6061 and operand 3 is a constant describing the known alignment
6062 of the beginning of the string.
6064 @cindex @code{float@var{m}@var{n}2} instruction pattern
6065 @item @samp{float@var{m}@var{n}2}
6066 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
6067 floating point mode @var{n} and store in operand 0 (which has mode
6070 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
6071 @item @samp{floatuns@var{m}@var{n}2}
6072 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
6073 to floating point mode @var{n} and store in operand 0 (which has mode
6076 @cindex @code{fix@var{m}@var{n}2} instruction pattern
6077 @item @samp{fix@var{m}@var{n}2}
6078 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6079 point mode @var{n} as a signed number and store in operand 0 (which
6080 has mode @var{n}). This instruction's result is defined only when
6081 the value of operand 1 is an integer.
6083 If the machine description defines this pattern, it also needs to
6084 define the @code{ftrunc} pattern.
6086 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
6087 @item @samp{fixuns@var{m}@var{n}2}
6088 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6089 point mode @var{n} as an unsigned number and store in operand 0 (which
6090 has mode @var{n}). This instruction's result is defined only when the
6091 value of operand 1 is an integer.
6093 @cindex @code{ftrunc@var{m}2} instruction pattern
6094 @item @samp{ftrunc@var{m}2}
6095 Convert operand 1 (valid for floating point mode @var{m}) to an
6096 integer value, still represented in floating point mode @var{m}, and
6097 store it in operand 0 (valid for floating point mode @var{m}).
6099 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
6100 @item @samp{fix_trunc@var{m}@var{n}2}
6101 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
6102 of mode @var{m} by converting the value to an integer.
6104 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
6105 @item @samp{fixuns_trunc@var{m}@var{n}2}
6106 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
6107 value of mode @var{m} by converting the value to an integer.
6109 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
6110 @item @samp{trunc@var{m}@var{n}2}
6111 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
6112 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6113 point or both floating point.
6115 @cindex @code{extend@var{m}@var{n}2} instruction pattern
6116 @item @samp{extend@var{m}@var{n}2}
6117 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6118 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6119 point or both floating point.
6121 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
6122 @item @samp{zero_extend@var{m}@var{n}2}
6123 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6124 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6127 @cindex @code{fract@var{m}@var{n}2} instruction pattern
6128 @item @samp{fract@var{m}@var{n}2}
6129 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6130 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6131 could be fixed-point to fixed-point, signed integer to fixed-point,
6132 fixed-point to signed integer, floating-point to fixed-point,
6133 or fixed-point to floating-point.
6134 When overflows or underflows happen, the results are undefined.
6136 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
6137 @item @samp{satfract@var{m}@var{n}2}
6138 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6139 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6140 could be fixed-point to fixed-point, signed integer to fixed-point,
6141 or floating-point to fixed-point.
6142 When overflows or underflows happen, the instruction saturates the
6143 results to the maximum or the minimum.
6145 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
6146 @item @samp{fractuns@var{m}@var{n}2}
6147 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6148 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6149 could be unsigned integer to fixed-point, or
6150 fixed-point to unsigned integer.
6151 When overflows or underflows happen, the results are undefined.
6153 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
6154 @item @samp{satfractuns@var{m}@var{n}2}
6155 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
6156 @var{n} and store in operand 0 (which has mode @var{n}).
6157 When overflows or underflows happen, the instruction saturates the
6158 results to the maximum or the minimum.
6160 @cindex @code{extv@var{m}} instruction pattern
6161 @item @samp{extv@var{m}}
6162 Extract a bit-field from register operand 1, sign-extend it, and store
6163 it in operand 0. Operand 2 specifies the width of the field in bits
6164 and operand 3 the starting bit, which counts from the most significant
6165 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
6168 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
6169 target-specific mode.
6171 @cindex @code{extvmisalign@var{m}} instruction pattern
6172 @item @samp{extvmisalign@var{m}}
6173 Extract a bit-field from memory operand 1, sign extend it, and store
6174 it in operand 0. Operand 2 specifies the width in bits and operand 3
6175 the starting bit. The starting bit is always somewhere in the first byte of
6176 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6177 is true and from the least significant bit otherwise.
6179 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
6180 Operands 2 and 3 have a target-specific mode.
6182 The instruction must not read beyond the last byte of the bit-field.
6184 @cindex @code{extzv@var{m}} instruction pattern
6185 @item @samp{extzv@var{m}}
6186 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
6188 @cindex @code{extzvmisalign@var{m}} instruction pattern
6189 @item @samp{extzvmisalign@var{m}}
6190 Like @samp{extvmisalign@var{m}} except that the bit-field value is
6193 @cindex @code{insv@var{m}} instruction pattern
6194 @item @samp{insv@var{m}}
6195 Insert operand 3 into a bit-field of register operand 0. Operand 1
6196 specifies the width of the field in bits and operand 2 the starting bit,
6197 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6198 is true and from the least significant bit otherwise.
6200 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
6201 target-specific mode.
6203 @cindex @code{insvmisalign@var{m}} instruction pattern
6204 @item @samp{insvmisalign@var{m}}
6205 Insert operand 3 into a bit-field of memory operand 0. Operand 1
6206 specifies the width of the field in bits and operand 2 the starting bit.
6207 The starting bit is always somewhere in the first byte of operand 0;
6208 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6209 is true and from the least significant bit otherwise.
6211 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
6212 Operands 1 and 2 have a target-specific mode.
6214 The instruction must not read or write beyond the last byte of the bit-field.
6216 @cindex @code{extv} instruction pattern
6218 Extract a bit-field from operand 1 (a register or memory operand), where
6219 operand 2 specifies the width in bits and operand 3 the starting bit,
6220 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
6221 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
6222 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
6223 be valid for @code{word_mode}.
6225 The RTL generation pass generates this instruction only with constants
6226 for operands 2 and 3 and the constant is never zero for operand 2.
6228 The bit-field value is sign-extended to a full word integer
6229 before it is stored in operand 0.
6231 This pattern is deprecated; please use @samp{extv@var{m}} and
6232 @code{extvmisalign@var{m}} instead.
6234 @cindex @code{extzv} instruction pattern
6236 Like @samp{extv} except that the bit-field value is zero-extended.
6238 This pattern is deprecated; please use @samp{extzv@var{m}} and
6239 @code{extzvmisalign@var{m}} instead.
6241 @cindex @code{insv} instruction pattern
6243 Store operand 3 (which must be valid for @code{word_mode}) into a
6244 bit-field in operand 0, where operand 1 specifies the width in bits and
6245 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
6246 @code{word_mode}; often @code{word_mode} is allowed only for registers.
6247 Operands 1 and 2 must be valid for @code{word_mode}.
6249 The RTL generation pass generates this instruction only with constants
6250 for operands 1 and 2 and the constant is never zero for operand 1.
6252 This pattern is deprecated; please use @samp{insv@var{m}} and
6253 @code{insvmisalign@var{m}} instead.
6255 @cindex @code{mov@var{mode}cc} instruction pattern
6256 @item @samp{mov@var{mode}cc}
6257 Conditionally move operand 2 or operand 3 into operand 0 according to the
6258 comparison in operand 1. If the comparison is true, operand 2 is moved
6259 into operand 0, otherwise operand 3 is moved.
6261 The mode of the operands being compared need not be the same as the operands
6262 being moved. Some machines, sparc64 for example, have instructions that
6263 conditionally move an integer value based on the floating point condition
6264 codes and vice versa.
6266 If the machine does not have conditional move instructions, do not
6267 define these patterns.
6269 @cindex @code{add@var{mode}cc} instruction pattern
6270 @item @samp{add@var{mode}cc}
6271 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
6272 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
6273 comparison in operand 1. If the comparison is false, operand 2 is moved into
6274 operand 0, otherwise (operand 2 + operand 3) is moved.
6276 @cindex @code{cond_add@var{mode}} instruction pattern
6277 @cindex @code{cond_sub@var{mode}} instruction pattern
6278 @cindex @code{cond_and@var{mode}} instruction pattern
6279 @cindex @code{cond_ior@var{mode}} instruction pattern
6280 @cindex @code{cond_xor@var{mode}} instruction pattern
6281 @cindex @code{cond_smin@var{mode}} instruction pattern
6282 @cindex @code{cond_smax@var{mode}} instruction pattern
6283 @cindex @code{cond_umin@var{mode}} instruction pattern
6284 @cindex @code{cond_umax@var{mode}} instruction pattern
6285 @item @samp{cond_add@var{mode}}
6286 @itemx @samp{cond_sub@var{mode}}
6287 @itemx @samp{cond_and@var{mode}}
6288 @itemx @samp{cond_ior@var{mode}}
6289 @itemx @samp{cond_xor@var{mode}}
6290 @itemx @samp{cond_smin@var{mode}}
6291 @itemx @samp{cond_smax@var{mode}}
6292 @itemx @samp{cond_umin@var{mode}}
6293 @itemx @samp{cond_umax@var{mode}}
6294 Perform an elementwise operation on vector operands 2 and 3,
6295 under the control of the vector mask in operand 1, and store the result
6296 in operand 0. This is equivalent to:
6299 for (i = 0; i < GET_MODE_NUNITS (@var{n}); i++)
6300 op0[i] = op1[i] ? op2[i] @var{op} op3[i] : op2[i];
6303 where, for example, @var{op} is @code{+} for @samp{cond_add@var{mode}}.
6305 When defined for floating-point modes, the contents of @samp{op3[i]}
6306 are not interpreted if @var{op1[i]} is false, just like they would not
6307 be in a normal C @samp{?:} condition.
6309 Operands 0, 2 and 3 all have mode @var{m}, while operand 1 has the mode
6310 returned by @code{TARGET_VECTORIZE_GET_MASK_MODE}.
6312 @cindex @code{neg@var{mode}cc} instruction pattern
6313 @item @samp{neg@var{mode}cc}
6314 Similar to @samp{mov@var{mode}cc} but for conditional negation. Conditionally
6315 move the negation of operand 2 or the unchanged operand 3 into operand 0
6316 according to the comparison in operand 1. If the comparison is true, the negation
6317 of operand 2 is moved into operand 0, otherwise operand 3 is moved.
6319 @cindex @code{not@var{mode}cc} instruction pattern
6320 @item @samp{not@var{mode}cc}
6321 Similar to @samp{neg@var{mode}cc} but for conditional complement.
6322 Conditionally move the bitwise complement of operand 2 or the unchanged
6323 operand 3 into operand 0 according to the comparison in operand 1.
6324 If the comparison is true, the complement of operand 2 is moved into
6325 operand 0, otherwise operand 3 is moved.
6327 @cindex @code{cstore@var{mode}4} instruction pattern
6328 @item @samp{cstore@var{mode}4}
6329 Store zero or nonzero in operand 0 according to whether a comparison
6330 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
6331 are the first and second operand of the comparison, respectively.
6332 You specify the mode that operand 0 must have when you write the
6333 @code{match_operand} expression. The compiler automatically sees which
6334 mode you have used and supplies an operand of that mode.
6336 The value stored for a true condition must have 1 as its low bit, or
6337 else must be negative. Otherwise the instruction is not suitable and
6338 you should omit it from the machine description. You describe to the
6339 compiler exactly which value is stored by defining the macro
6340 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
6341 found that can be used for all the possible comparison operators, you
6342 should pick one and use a @code{define_expand} to map all results
6343 onto the one you chose.
6345 These operations may @code{FAIL}, but should do so only in relatively
6346 uncommon cases; if they would @code{FAIL} for common cases involving
6347 integer comparisons, it is best to restrict the predicates to not
6348 allow these operands. Likewise if a given comparison operator will
6349 always fail, independent of the operands (for floating-point modes, the
6350 @code{ordered_comparison_operator} predicate is often useful in this case).
6352 If this pattern is omitted, the compiler will generate a conditional
6353 branch---for example, it may copy a constant one to the target and branching
6354 around an assignment of zero to the target---or a libcall. If the predicate
6355 for operand 1 only rejects some operators, it will also try reordering the
6356 operands and/or inverting the result value (e.g.@: by an exclusive OR).
6357 These possibilities could be cheaper or equivalent to the instructions
6358 used for the @samp{cstore@var{mode}4} pattern followed by those required
6359 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
6360 case, you can and should make operand 1's predicate reject some operators
6361 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
6362 from the machine description.
6364 @cindex @code{cbranch@var{mode}4} instruction pattern
6365 @item @samp{cbranch@var{mode}4}
6366 Conditional branch instruction combined with a compare instruction.
6367 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
6368 first and second operands of the comparison, respectively. Operand 3
6369 is the @code{code_label} to jump to.
6371 @cindex @code{jump} instruction pattern
6373 A jump inside a function; an unconditional branch. Operand 0 is the
6374 @code{code_label} to jump to. This pattern name is mandatory on all
6377 @cindex @code{call} instruction pattern
6379 Subroutine call instruction returning no value. Operand 0 is the
6380 function to call; operand 1 is the number of bytes of arguments pushed
6381 as a @code{const_int}; operand 2 is the number of registers used as
6384 On most machines, operand 2 is not actually stored into the RTL
6385 pattern. It is supplied for the sake of some RISC machines which need
6386 to put this information into the assembler code; they can put it in
6387 the RTL instead of operand 1.
6389 Operand 0 should be a @code{mem} RTX whose address is the address of the
6390 function. Note, however, that this address can be a @code{symbol_ref}
6391 expression even if it would not be a legitimate memory address on the
6392 target machine. If it is also not a valid argument for a call
6393 instruction, the pattern for this operation should be a
6394 @code{define_expand} (@pxref{Expander Definitions}) that places the
6395 address into a register and uses that register in the call instruction.
6397 @cindex @code{call_value} instruction pattern
6398 @item @samp{call_value}
6399 Subroutine call instruction returning a value. Operand 0 is the hard
6400 register in which the value is returned. There are three more
6401 operands, the same as the three operands of the @samp{call}
6402 instruction (but with numbers increased by one).
6404 Subroutines that return @code{BLKmode} objects use the @samp{call}
6407 @cindex @code{call_pop} instruction pattern
6408 @cindex @code{call_value_pop} instruction pattern
6409 @item @samp{call_pop}, @samp{call_value_pop}
6410 Similar to @samp{call} and @samp{call_value}, except used if defined and
6411 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
6412 that contains both the function call and a @code{set} to indicate the
6413 adjustment made to the frame pointer.
6415 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
6416 patterns increases the number of functions for which the frame pointer
6417 can be eliminated, if desired.
6419 @cindex @code{untyped_call} instruction pattern
6420 @item @samp{untyped_call}
6421 Subroutine call instruction returning a value of any type. Operand 0 is
6422 the function to call; operand 1 is a memory location where the result of
6423 calling the function is to be stored; operand 2 is a @code{parallel}
6424 expression where each element is a @code{set} expression that indicates
6425 the saving of a function return value into the result block.
6427 This instruction pattern should be defined to support
6428 @code{__builtin_apply} on machines where special instructions are needed
6429 to call a subroutine with arbitrary arguments or to save the value
6430 returned. This instruction pattern is required on machines that have
6431 multiple registers that can hold a return value
6432 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
6434 @cindex @code{return} instruction pattern
6436 Subroutine return instruction. This instruction pattern name should be
6437 defined only if a single instruction can do all the work of returning
6440 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
6441 RTL generation phase. In this case it is to support machines where
6442 multiple instructions are usually needed to return from a function, but
6443 some class of functions only requires one instruction to implement a
6444 return. Normally, the applicable functions are those which do not need
6445 to save any registers or allocate stack space.
6447 It is valid for this pattern to expand to an instruction using
6448 @code{simple_return} if no epilogue is required.
6450 @cindex @code{simple_return} instruction pattern
6451 @item @samp{simple_return}
6452 Subroutine return instruction. This instruction pattern name should be
6453 defined only if a single instruction can do all the work of returning
6454 from a function on a path where no epilogue is required. This pattern
6455 is very similar to the @code{return} instruction pattern, but it is emitted
6456 only by the shrink-wrapping optimization on paths where the function
6457 prologue has not been executed, and a function return should occur without
6458 any of the effects of the epilogue. Additional uses may be introduced on
6459 paths where both the prologue and the epilogue have executed.
6461 @findex reload_completed
6462 @findex leaf_function_p
6463 For such machines, the condition specified in this pattern should only
6464 be true when @code{reload_completed} is nonzero and the function's
6465 epilogue would only be a single instruction. For machines with register
6466 windows, the routine @code{leaf_function_p} may be used to determine if
6467 a register window push is required.
6469 Machines that have conditional return instructions should define patterns
6475 (if_then_else (match_operator
6476 0 "comparison_operator"
6477 [(cc0) (const_int 0)])
6484 where @var{condition} would normally be the same condition specified on the
6485 named @samp{return} pattern.
6487 @cindex @code{untyped_return} instruction pattern
6488 @item @samp{untyped_return}
6489 Untyped subroutine return instruction. This instruction pattern should
6490 be defined to support @code{__builtin_return} on machines where special
6491 instructions are needed to return a value of any type.
6493 Operand 0 is a memory location where the result of calling a function
6494 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
6495 expression where each element is a @code{set} expression that indicates
6496 the restoring of a function return value from the result block.
6498 @cindex @code{nop} instruction pattern
6500 No-op instruction. This instruction pattern name should always be defined
6501 to output a no-op in assembler code. @code{(const_int 0)} will do as an
6504 @cindex @code{indirect_jump} instruction pattern
6505 @item @samp{indirect_jump}
6506 An instruction to jump to an address which is operand zero.
6507 This pattern name is mandatory on all machines.
6509 @cindex @code{casesi} instruction pattern
6511 Instruction to jump through a dispatch table, including bounds checking.
6512 This instruction takes five operands:
6516 The index to dispatch on, which has mode @code{SImode}.
6519 The lower bound for indices in the table, an integer constant.
6522 The total range of indices in the table---the largest index
6523 minus the smallest one (both inclusive).
6526 A label that precedes the table itself.
6529 A label to jump to if the index has a value outside the bounds.
6532 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
6533 @code{jump_table_data}. The number of elements in the table is one plus the
6534 difference between the upper bound and the lower bound.
6536 @cindex @code{tablejump} instruction pattern
6537 @item @samp{tablejump}
6538 Instruction to jump to a variable address. This is a low-level
6539 capability which can be used to implement a dispatch table when there
6540 is no @samp{casesi} pattern.
6542 This pattern requires two operands: the address or offset, and a label
6543 which should immediately precede the jump table. If the macro
6544 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
6545 operand is an offset which counts from the address of the table; otherwise,
6546 it is an absolute address to jump to. In either case, the first operand has
6549 The @samp{tablejump} insn is always the last insn before the jump
6550 table it uses. Its assembler code normally has no need to use the
6551 second operand, but you should incorporate it in the RTL pattern so
6552 that the jump optimizer will not delete the table as unreachable code.
6555 @cindex @code{decrement_and_branch_until_zero} instruction pattern
6556 @item @samp{decrement_and_branch_until_zero}
6557 Conditional branch instruction that decrements a register and
6558 jumps if the register is nonzero. Operand 0 is the register to
6559 decrement and test; operand 1 is the label to jump to if the
6560 register is nonzero. @xref{Looping Patterns}.
6562 This optional instruction pattern is only used by the combiner,
6563 typically for loops reversed by the loop optimizer when strength
6564 reduction is enabled.
6566 @cindex @code{doloop_end} instruction pattern
6567 @item @samp{doloop_end}
6568 Conditional branch instruction that decrements a register and
6569 jumps if the register is nonzero. Operand 0 is the register to
6570 decrement and test; operand 1 is the label to jump to if the
6571 register is nonzero.
6572 @xref{Looping Patterns}.
6574 This optional instruction pattern should be defined for machines with
6575 low-overhead looping instructions as the loop optimizer will try to
6576 modify suitable loops to utilize it. The target hook
6577 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
6578 low-overhead loops can be used.
6580 @cindex @code{doloop_begin} instruction pattern
6581 @item @samp{doloop_begin}
6582 Companion instruction to @code{doloop_end} required for machines that
6583 need to perform some initialization, such as loading a special counter
6584 register. Operand 1 is the associated @code{doloop_end} pattern and
6585 operand 0 is the register that it decrements.
6587 If initialization insns do not always need to be emitted, use a
6588 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
6590 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
6591 @item @samp{canonicalize_funcptr_for_compare}
6592 Canonicalize the function pointer in operand 1 and store the result
6595 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
6596 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
6597 and also has mode @code{Pmode}.
6599 Canonicalization of a function pointer usually involves computing
6600 the address of the function which would be called if the function
6601 pointer were used in an indirect call.
6603 Only define this pattern if function pointers on the target machine
6604 can have different values but still call the same function when
6605 used in an indirect call.
6607 @cindex @code{save_stack_block} instruction pattern
6608 @cindex @code{save_stack_function} instruction pattern
6609 @cindex @code{save_stack_nonlocal} instruction pattern
6610 @cindex @code{restore_stack_block} instruction pattern
6611 @cindex @code{restore_stack_function} instruction pattern
6612 @cindex @code{restore_stack_nonlocal} instruction pattern
6613 @item @samp{save_stack_block}
6614 @itemx @samp{save_stack_function}
6615 @itemx @samp{save_stack_nonlocal}
6616 @itemx @samp{restore_stack_block}
6617 @itemx @samp{restore_stack_function}
6618 @itemx @samp{restore_stack_nonlocal}
6619 Most machines save and restore the stack pointer by copying it to or
6620 from an object of mode @code{Pmode}. Do not define these patterns on
6623 Some machines require special handling for stack pointer saves and
6624 restores. On those machines, define the patterns corresponding to the
6625 non-standard cases by using a @code{define_expand} (@pxref{Expander
6626 Definitions}) that produces the required insns. The three types of
6627 saves and restores are:
6631 @samp{save_stack_block} saves the stack pointer at the start of a block
6632 that allocates a variable-sized object, and @samp{restore_stack_block}
6633 restores the stack pointer when the block is exited.
6636 @samp{save_stack_function} and @samp{restore_stack_function} do a
6637 similar job for the outermost block of a function and are used when the
6638 function allocates variable-sized objects or calls @code{alloca}. Only
6639 the epilogue uses the restored stack pointer, allowing a simpler save or
6640 restore sequence on some machines.
6643 @samp{save_stack_nonlocal} is used in functions that contain labels
6644 branched to by nested functions. It saves the stack pointer in such a
6645 way that the inner function can use @samp{restore_stack_nonlocal} to
6646 restore the stack pointer. The compiler generates code to restore the
6647 frame and argument pointer registers, but some machines require saving
6648 and restoring additional data such as register window information or
6649 stack backchains. Place insns in these patterns to save and restore any
6653 When saving the stack pointer, operand 0 is the save area and operand 1
6654 is the stack pointer. The mode used to allocate the save area defaults
6655 to @code{Pmode} but you can override that choice by defining the
6656 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
6657 specify an integral mode, or @code{VOIDmode} if no save area is needed
6658 for a particular type of save (either because no save is needed or
6659 because a machine-specific save area can be used). Operand 0 is the
6660 stack pointer and operand 1 is the save area for restore operations. If
6661 @samp{save_stack_block} is defined, operand 0 must not be
6662 @code{VOIDmode} since these saves can be arbitrarily nested.
6664 A save area is a @code{mem} that is at a constant offset from
6665 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
6666 nonlocal gotos and a @code{reg} in the other two cases.
6668 @cindex @code{allocate_stack} instruction pattern
6669 @item @samp{allocate_stack}
6670 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
6671 the stack pointer to create space for dynamically allocated data.
6673 Store the resultant pointer to this space into operand 0. If you
6674 are allocating space from the main stack, do this by emitting a
6675 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
6676 If you are allocating the space elsewhere, generate code to copy the
6677 location of the space to operand 0. In the latter case, you must
6678 ensure this space gets freed when the corresponding space on the main
6681 Do not define this pattern if all that must be done is the subtraction.
6682 Some machines require other operations such as stack probes or
6683 maintaining the back chain. Define this pattern to emit those
6684 operations in addition to updating the stack pointer.
6686 @cindex @code{check_stack} instruction pattern
6687 @item @samp{check_stack}
6688 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
6689 probing the stack, define this pattern to perform the needed check and signal
6690 an error if the stack has overflowed. The single operand is the address in
6691 the stack farthest from the current stack pointer that you need to validate.
6692 Normally, on platforms where this pattern is needed, you would obtain the
6693 stack limit from a global or thread-specific variable or register.
6695 @cindex @code{probe_stack_address} instruction pattern
6696 @item @samp{probe_stack_address}
6697 If stack checking (@pxref{Stack Checking}) can be done on your system by
6698 probing the stack but without the need to actually access it, define this
6699 pattern and signal an error if the stack has overflowed. The single operand
6700 is the memory address in the stack that needs to be probed.
6702 @cindex @code{probe_stack} instruction pattern
6703 @item @samp{probe_stack}
6704 If stack checking (@pxref{Stack Checking}) can be done on your system by
6705 probing the stack but doing it with a ``store zero'' instruction is not valid
6706 or optimal, define this pattern to do the probing differently and signal an
6707 error if the stack has overflowed. The single operand is the memory reference
6708 in the stack that needs to be probed.
6710 @cindex @code{nonlocal_goto} instruction pattern
6711 @item @samp{nonlocal_goto}
6712 Emit code to generate a non-local goto, e.g., a jump from one function
6713 to a label in an outer function. This pattern has four arguments,
6714 each representing a value to be used in the jump. The first
6715 argument is to be loaded into the frame pointer, the second is
6716 the address to branch to (code to dispatch to the actual label),
6717 the third is the address of a location where the stack is saved,
6718 and the last is the address of the label, to be placed in the
6719 location for the incoming static chain.
6721 On most machines you need not define this pattern, since GCC will
6722 already generate the correct code, which is to load the frame pointer
6723 and static chain, restore the stack (using the
6724 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
6725 to the dispatcher. You need only define this pattern if this code will
6726 not work on your machine.
6728 @cindex @code{nonlocal_goto_receiver} instruction pattern
6729 @item @samp{nonlocal_goto_receiver}
6730 This pattern, if defined, contains code needed at the target of a
6731 nonlocal goto after the code already generated by GCC@. You will not
6732 normally need to define this pattern. A typical reason why you might
6733 need this pattern is if some value, such as a pointer to a global table,
6734 must be restored when the frame pointer is restored. Note that a nonlocal
6735 goto only occurs within a unit-of-translation, so a global table pointer
6736 that is shared by all functions of a given module need not be restored.
6737 There are no arguments.
6739 @cindex @code{exception_receiver} instruction pattern
6740 @item @samp{exception_receiver}
6741 This pattern, if defined, contains code needed at the site of an
6742 exception handler that isn't needed at the site of a nonlocal goto. You
6743 will not normally need to define this pattern. A typical reason why you
6744 might need this pattern is if some value, such as a pointer to a global
6745 table, must be restored after control flow is branched to the handler of
6746 an exception. There are no arguments.
6748 @cindex @code{builtin_setjmp_setup} instruction pattern
6749 @item @samp{builtin_setjmp_setup}
6750 This pattern, if defined, contains additional code needed to initialize
6751 the @code{jmp_buf}. You will not normally need to define this pattern.
6752 A typical reason why you might need this pattern is if some value, such
6753 as a pointer to a global table, must be restored. Though it is
6754 preferred that the pointer value be recalculated if possible (given the
6755 address of a label for instance). The single argument is a pointer to
6756 the @code{jmp_buf}. Note that the buffer is five words long and that
6757 the first three are normally used by the generic mechanism.
6759 @cindex @code{builtin_setjmp_receiver} instruction pattern
6760 @item @samp{builtin_setjmp_receiver}
6761 This pattern, if defined, contains code needed at the site of a
6762 built-in setjmp that isn't needed at the site of a nonlocal goto. You
6763 will not normally need to define this pattern. A typical reason why you
6764 might need this pattern is if some value, such as a pointer to a global
6765 table, must be restored. It takes one argument, which is the label
6766 to which builtin_longjmp transferred control; this pattern may be emitted
6767 at a small offset from that label.
6769 @cindex @code{builtin_longjmp} instruction pattern
6770 @item @samp{builtin_longjmp}
6771 This pattern, if defined, performs the entire action of the longjmp.
6772 You will not normally need to define this pattern unless you also define
6773 @code{builtin_setjmp_setup}. The single argument is a pointer to the
6776 @cindex @code{eh_return} instruction pattern
6777 @item @samp{eh_return}
6778 This pattern, if defined, affects the way @code{__builtin_eh_return},
6779 and thence the call frame exception handling library routines, are
6780 built. It is intended to handle non-trivial actions needed along
6781 the abnormal return path.
6783 The address of the exception handler to which the function should return
6784 is passed as operand to this pattern. It will normally need to copied by
6785 the pattern to some special register or memory location.
6786 If the pattern needs to determine the location of the target call
6787 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
6788 if defined; it will have already been assigned.
6790 If this pattern is not defined, the default action will be to simply
6791 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
6792 that macro or this pattern needs to be defined if call frame exception
6793 handling is to be used.
6795 @cindex @code{prologue} instruction pattern
6796 @anchor{prologue instruction pattern}
6797 @item @samp{prologue}
6798 This pattern, if defined, emits RTL for entry to a function. The function
6799 entry is responsible for setting up the stack frame, initializing the frame
6800 pointer register, saving callee saved registers, etc.
6802 Using a prologue pattern is generally preferred over defining
6803 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
6805 The @code{prologue} pattern is particularly useful for targets which perform
6806 instruction scheduling.
6808 @cindex @code{window_save} instruction pattern
6809 @anchor{window_save instruction pattern}
6810 @item @samp{window_save}
6811 This pattern, if defined, emits RTL for a register window save. It should
6812 be defined if the target machine has register windows but the window events
6813 are decoupled from calls to subroutines. The canonical example is the SPARC
6816 @cindex @code{epilogue} instruction pattern
6817 @anchor{epilogue instruction pattern}
6818 @item @samp{epilogue}
6819 This pattern emits RTL for exit from a function. The function
6820 exit is responsible for deallocating the stack frame, restoring callee saved
6821 registers and emitting the return instruction.
6823 Using an epilogue pattern is generally preferred over defining
6824 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
6826 The @code{epilogue} pattern is particularly useful for targets which perform
6827 instruction scheduling or which have delay slots for their return instruction.
6829 @cindex @code{sibcall_epilogue} instruction pattern
6830 @item @samp{sibcall_epilogue}
6831 This pattern, if defined, emits RTL for exit from a function without the final
6832 branch back to the calling function. This pattern will be emitted before any
6833 sibling call (aka tail call) sites.
6835 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
6836 parameter passing or any stack slots for arguments passed to the current
6839 @cindex @code{trap} instruction pattern
6841 This pattern, if defined, signals an error, typically by causing some
6842 kind of signal to be raised.
6844 @cindex @code{ctrap@var{MM}4} instruction pattern
6845 @item @samp{ctrap@var{MM}4}
6846 Conditional trap instruction. Operand 0 is a piece of RTL which
6847 performs a comparison, and operands 1 and 2 are the arms of the
6848 comparison. Operand 3 is the trap code, an integer.
6850 A typical @code{ctrap} pattern looks like
6853 (define_insn "ctrapsi4"
6854 [(trap_if (match_operator 0 "trap_operator"
6855 [(match_operand 1 "register_operand")
6856 (match_operand 2 "immediate_operand")])
6857 (match_operand 3 "const_int_operand" "i"))]
6862 @cindex @code{prefetch} instruction pattern
6863 @item @samp{prefetch}
6864 This pattern, if defined, emits code for a non-faulting data prefetch
6865 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
6866 is a constant 1 if the prefetch is preparing for a write to the memory
6867 address, or a constant 0 otherwise. Operand 2 is the expected degree of
6868 temporal locality of the data and is a value between 0 and 3, inclusive; 0
6869 means that the data has no temporal locality, so it need not be left in the
6870 cache after the access; 3 means that the data has a high degree of temporal
6871 locality and should be left in all levels of cache possible; 1 and 2 mean,
6872 respectively, a low or moderate degree of temporal locality.
6874 Targets that do not support write prefetches or locality hints can ignore
6875 the values of operands 1 and 2.
6877 @cindex @code{blockage} instruction pattern
6878 @item @samp{blockage}
6879 This pattern defines a pseudo insn that prevents the instruction
6880 scheduler and other passes from moving instructions and using register
6881 equivalences across the boundary defined by the blockage insn.
6882 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
6884 @cindex @code{memory_blockage} instruction pattern
6885 @item @samp{memory_blockage}
6886 This pattern, if defined, represents a compiler memory barrier, and will be
6887 placed at points across which RTL passes may not propagate memory accesses.
6888 This instruction needs to read and write volatile BLKmode memory. It does
6889 not need to generate any machine instruction. If this pattern is not defined,
6890 the compiler falls back to emitting an instruction corresponding
6891 to @code{asm volatile ("" ::: "memory")}.
6893 @cindex @code{memory_barrier} instruction pattern
6894 @item @samp{memory_barrier}
6895 If the target memory model is not fully synchronous, then this pattern
6896 should be defined to an instruction that orders both loads and stores
6897 before the instruction with respect to loads and stores after the instruction.
6898 This pattern has no operands.
6900 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
6901 @item @samp{sync_compare_and_swap@var{mode}}
6902 This pattern, if defined, emits code for an atomic compare-and-swap
6903 operation. Operand 1 is the memory on which the atomic operation is
6904 performed. Operand 2 is the ``old'' value to be compared against the
6905 current contents of the memory location. Operand 3 is the ``new'' value
6906 to store in the memory if the compare succeeds. Operand 0 is the result
6907 of the operation; it should contain the contents of the memory
6908 before the operation. If the compare succeeds, this should obviously be
6909 a copy of operand 2.
6911 This pattern must show that both operand 0 and operand 1 are modified.
6913 This pattern must issue any memory barrier instructions such that all
6914 memory operations before the atomic operation occur before the atomic
6915 operation and all memory operations after the atomic operation occur
6916 after the atomic operation.
6918 For targets where the success or failure of the compare-and-swap
6919 operation is available via the status flags, it is possible to
6920 avoid a separate compare operation and issue the subsequent
6921 branch or store-flag operation immediately after the compare-and-swap.
6922 To this end, GCC will look for a @code{MODE_CC} set in the
6923 output of @code{sync_compare_and_swap@var{mode}}; if the machine
6924 description includes such a set, the target should also define special
6925 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
6926 be able to take the destination of the @code{MODE_CC} set and pass it
6927 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
6928 operand of the comparison (the second will be @code{(const_int 0)}).
6930 For targets where the operating system may provide support for this
6931 operation via library calls, the @code{sync_compare_and_swap_optab}
6932 may be initialized to a function with the same interface as the
6933 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
6934 set of @var{__sync} builtins are supported via library calls, the
6935 target can initialize all of the optabs at once with
6936 @code{init_sync_libfuncs}.
6937 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
6938 assumed that these library calls do @emph{not} use any kind of
6939 interruptable locking.
6941 @cindex @code{sync_add@var{mode}} instruction pattern
6942 @cindex @code{sync_sub@var{mode}} instruction pattern
6943 @cindex @code{sync_ior@var{mode}} instruction pattern
6944 @cindex @code{sync_and@var{mode}} instruction pattern
6945 @cindex @code{sync_xor@var{mode}} instruction pattern
6946 @cindex @code{sync_nand@var{mode}} instruction pattern
6947 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
6948 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
6949 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
6950 These patterns emit code for an atomic operation on memory.
6951 Operand 0 is the memory on which the atomic operation is performed.
6952 Operand 1 is the second operand to the binary operator.
6954 This pattern must issue any memory barrier instructions such that all
6955 memory operations before the atomic operation occur before the atomic
6956 operation and all memory operations after the atomic operation occur
6957 after the atomic operation.
6959 If these patterns are not defined, the operation will be constructed
6960 from a compare-and-swap operation, if defined.
6962 @cindex @code{sync_old_add@var{mode}} instruction pattern
6963 @cindex @code{sync_old_sub@var{mode}} instruction pattern
6964 @cindex @code{sync_old_ior@var{mode}} instruction pattern
6965 @cindex @code{sync_old_and@var{mode}} instruction pattern
6966 @cindex @code{sync_old_xor@var{mode}} instruction pattern
6967 @cindex @code{sync_old_nand@var{mode}} instruction pattern
6968 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
6969 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
6970 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
6971 These patterns emit code for an atomic operation on memory,
6972 and return the value that the memory contained before the operation.
6973 Operand 0 is the result value, operand 1 is the memory on which the
6974 atomic operation is performed, and operand 2 is the second operand
6975 to the binary operator.
6977 This pattern must issue any memory barrier instructions such that all
6978 memory operations before the atomic operation occur before the atomic
6979 operation and all memory operations after the atomic operation occur
6980 after the atomic operation.
6982 If these patterns are not defined, the operation will be constructed
6983 from a compare-and-swap operation, if defined.
6985 @cindex @code{sync_new_add@var{mode}} instruction pattern
6986 @cindex @code{sync_new_sub@var{mode}} instruction pattern
6987 @cindex @code{sync_new_ior@var{mode}} instruction pattern
6988 @cindex @code{sync_new_and@var{mode}} instruction pattern
6989 @cindex @code{sync_new_xor@var{mode}} instruction pattern
6990 @cindex @code{sync_new_nand@var{mode}} instruction pattern
6991 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
6992 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
6993 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
6994 These patterns are like their @code{sync_old_@var{op}} counterparts,
6995 except that they return the value that exists in the memory location
6996 after the operation, rather than before the operation.
6998 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
6999 @item @samp{sync_lock_test_and_set@var{mode}}
7000 This pattern takes two forms, based on the capabilities of the target.
7001 In either case, operand 0 is the result of the operand, operand 1 is
7002 the memory on which the atomic operation is performed, and operand 2
7003 is the value to set in the lock.
7005 In the ideal case, this operation is an atomic exchange operation, in
7006 which the previous value in memory operand is copied into the result
7007 operand, and the value operand is stored in the memory operand.
7009 For less capable targets, any value operand that is not the constant 1
7010 should be rejected with @code{FAIL}. In this case the target may use
7011 an atomic test-and-set bit operation. The result operand should contain
7012 1 if the bit was previously set and 0 if the bit was previously clear.
7013 The true contents of the memory operand are implementation defined.
7015 This pattern must issue any memory barrier instructions such that the
7016 pattern as a whole acts as an acquire barrier, that is all memory
7017 operations after the pattern do not occur until the lock is acquired.
7019 If this pattern is not defined, the operation will be constructed from
7020 a compare-and-swap operation, if defined.
7022 @cindex @code{sync_lock_release@var{mode}} instruction pattern
7023 @item @samp{sync_lock_release@var{mode}}
7024 This pattern, if defined, releases a lock set by
7025 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
7026 that contains the lock; operand 1 is the value to store in the lock.
7028 If the target doesn't implement full semantics for
7029 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
7030 the constant 0 should be rejected with @code{FAIL}, and the true contents
7031 of the memory operand are implementation defined.
7033 This pattern must issue any memory barrier instructions such that the
7034 pattern as a whole acts as a release barrier, that is the lock is
7035 released only after all previous memory operations have completed.
7037 If this pattern is not defined, then a @code{memory_barrier} pattern
7038 will be emitted, followed by a store of the value to the memory operand.
7040 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
7041 @item @samp{atomic_compare_and_swap@var{mode}}
7042 This pattern, if defined, emits code for an atomic compare-and-swap
7043 operation with memory model semantics. Operand 2 is the memory on which
7044 the atomic operation is performed. Operand 0 is an output operand which
7045 is set to true or false based on whether the operation succeeded. Operand
7046 1 is an output operand which is set to the contents of the memory before
7047 the operation was attempted. Operand 3 is the value that is expected to
7048 be in memory. Operand 4 is the value to put in memory if the expected
7049 value is found there. Operand 5 is set to 1 if this compare and swap is to
7050 be treated as a weak operation. Operand 6 is the memory model to be used
7051 if the operation is a success. Operand 7 is the memory model to be used
7052 if the operation fails.
7054 If memory referred to in operand 2 contains the value in operand 3, then
7055 operand 4 is stored in memory pointed to by operand 2 and fencing based on
7056 the memory model in operand 6 is issued.
7058 If memory referred to in operand 2 does not contain the value in operand 3,
7059 then fencing based on the memory model in operand 7 is issued.
7061 If a target does not support weak compare-and-swap operations, or the port
7062 elects not to implement weak operations, the argument in operand 5 can be
7063 ignored. Note a strong implementation must be provided.
7065 If this pattern is not provided, the @code{__atomic_compare_exchange}
7066 built-in functions will utilize the legacy @code{sync_compare_and_swap}
7067 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
7069 @cindex @code{atomic_load@var{mode}} instruction pattern
7070 @item @samp{atomic_load@var{mode}}
7071 This pattern implements an atomic load operation with memory model
7072 semantics. Operand 1 is the memory address being loaded from. Operand 0
7073 is the result of the load. Operand 2 is the memory model to be used for
7076 If not present, the @code{__atomic_load} built-in function will either
7077 resort to a normal load with memory barriers, or a compare-and-swap
7078 operation if a normal load would not be atomic.
7080 @cindex @code{atomic_store@var{mode}} instruction pattern
7081 @item @samp{atomic_store@var{mode}}
7082 This pattern implements an atomic store operation with memory model
7083 semantics. Operand 0 is the memory address being stored to. Operand 1
7084 is the value to be written. Operand 2 is the memory model to be used for
7087 If not present, the @code{__atomic_store} built-in function will attempt to
7088 perform a normal store and surround it with any required memory fences. If
7089 the store would not be atomic, then an @code{__atomic_exchange} is
7090 attempted with the result being ignored.
7092 @cindex @code{atomic_exchange@var{mode}} instruction pattern
7093 @item @samp{atomic_exchange@var{mode}}
7094 This pattern implements an atomic exchange operation with memory model
7095 semantics. Operand 1 is the memory location the operation is performed on.
7096 Operand 0 is an output operand which is set to the original value contained
7097 in the memory pointed to by operand 1. Operand 2 is the value to be
7098 stored. Operand 3 is the memory model to be used.
7100 If this pattern is not present, the built-in function
7101 @code{__atomic_exchange} will attempt to preform the operation with a
7102 compare and swap loop.
7104 @cindex @code{atomic_add@var{mode}} instruction pattern
7105 @cindex @code{atomic_sub@var{mode}} instruction pattern
7106 @cindex @code{atomic_or@var{mode}} instruction pattern
7107 @cindex @code{atomic_and@var{mode}} instruction pattern
7108 @cindex @code{atomic_xor@var{mode}} instruction pattern
7109 @cindex @code{atomic_nand@var{mode}} instruction pattern
7110 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
7111 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
7112 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
7113 These patterns emit code for an atomic operation on memory with memory
7114 model semantics. Operand 0 is the memory on which the atomic operation is
7115 performed. Operand 1 is the second operand to the binary operator.
7116 Operand 2 is the memory model to be used by the operation.
7118 If these patterns are not defined, attempts will be made to use legacy
7119 @code{sync} patterns, or equivalent patterns which return a result. If
7120 none of these are available a compare-and-swap loop will be used.
7122 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
7123 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
7124 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
7125 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
7126 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
7127 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
7128 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
7129 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
7130 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
7131 These patterns emit code for an atomic operation on memory with memory
7132 model semantics, and return the original value. Operand 0 is an output
7133 operand which contains the value of the memory location before the
7134 operation was performed. Operand 1 is the memory on which the atomic
7135 operation is performed. Operand 2 is the second operand to the binary
7136 operator. Operand 3 is the memory model to be used by the operation.
7138 If these patterns are not defined, attempts will be made to use legacy
7139 @code{sync} patterns. If none of these are available a compare-and-swap
7142 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
7143 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
7144 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
7145 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
7146 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
7147 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
7148 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
7149 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
7150 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
7151 These patterns emit code for an atomic operation on memory with memory
7152 model semantics and return the result after the operation is performed.
7153 Operand 0 is an output operand which contains the value after the
7154 operation. Operand 1 is the memory on which the atomic operation is
7155 performed. Operand 2 is the second operand to the binary operator.
7156 Operand 3 is the memory model to be used by the operation.
7158 If these patterns are not defined, attempts will be made to use legacy
7159 @code{sync} patterns, or equivalent patterns which return the result before
7160 the operation followed by the arithmetic operation required to produce the
7161 result. If none of these are available a compare-and-swap loop will be
7164 @cindex @code{atomic_test_and_set} instruction pattern
7165 @item @samp{atomic_test_and_set}
7166 This pattern emits code for @code{__builtin_atomic_test_and_set}.
7167 Operand 0 is an output operand which is set to true if the previous
7168 previous contents of the byte was "set", and false otherwise. Operand 1
7169 is the @code{QImode} memory to be modified. Operand 2 is the memory
7172 The specific value that defines "set" is implementation defined, and
7173 is normally based on what is performed by the native atomic test and set
7176 @cindex @code{atomic_bit_test_and_set@var{mode}} instruction pattern
7177 @cindex @code{atomic_bit_test_and_complement@var{mode}} instruction pattern
7178 @cindex @code{atomic_bit_test_and_reset@var{mode}} instruction pattern
7179 @item @samp{atomic_bit_test_and_set@var{mode}}
7180 @itemx @samp{atomic_bit_test_and_complement@var{mode}}
7181 @itemx @samp{atomic_bit_test_and_reset@var{mode}}
7182 These patterns emit code for an atomic bitwise operation on memory with memory
7183 model semantics, and return the original value of the specified bit.
7184 Operand 0 is an output operand which contains the value of the specified bit
7185 from the memory location before the operation was performed. Operand 1 is the
7186 memory on which the atomic operation is performed. Operand 2 is the bit within
7187 the operand, starting with least significant bit. Operand 3 is the memory model
7188 to be used by the operation. Operand 4 is a flag - it is @code{const1_rtx}
7189 if operand 0 should contain the original value of the specified bit in the
7190 least significant bit of the operand, and @code{const0_rtx} if the bit should
7191 be in its original position in the operand.
7192 @code{atomic_bit_test_and_set@var{mode}} atomically sets the specified bit after
7193 remembering its original value, @code{atomic_bit_test_and_complement@var{mode}}
7194 inverts the specified bit and @code{atomic_bit_test_and_reset@var{mode}} clears
7197 If these patterns are not defined, attempts will be made to use
7198 @code{atomic_fetch_or@var{mode}}, @code{atomic_fetch_xor@var{mode}} or
7199 @code{atomic_fetch_and@var{mode}} instruction patterns, or their @code{sync}
7200 counterparts. If none of these are available a compare-and-swap
7203 @cindex @code{mem_thread_fence} instruction pattern
7204 @item @samp{mem_thread_fence}
7205 This pattern emits code required to implement a thread fence with
7206 memory model semantics. Operand 0 is the memory model to be used.
7208 For the @code{__ATOMIC_RELAXED} model no instructions need to be issued
7209 and this expansion is not invoked.
7211 The compiler always emits a compiler memory barrier regardless of what
7212 expanding this pattern produced.
7214 If this pattern is not defined, the compiler falls back to expanding the
7215 @code{memory_barrier} pattern, then to emitting @code{__sync_synchronize}
7216 library call, and finally to just placing a compiler memory barrier.
7218 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
7219 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
7220 @item @samp{get_thread_pointer@var{mode}}
7221 @itemx @samp{set_thread_pointer@var{mode}}
7222 These patterns emit code that reads/sets the TLS thread pointer. Currently,
7223 these are only needed if the target needs to support the
7224 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
7227 The get/set patterns have a single output/input operand respectively,
7228 with @var{mode} intended to be @code{Pmode}.
7230 @cindex @code{stack_protect_set} instruction pattern
7231 @item @samp{stack_protect_set}
7232 This pattern, if defined, moves a @code{ptr_mode} value from the memory
7233 in operand 1 to the memory in operand 0 without leaving the value in
7234 a register afterward. This is to avoid leaking the value some place
7235 that an attacker might use to rewrite the stack guard slot after
7236 having clobbered it.
7238 If this pattern is not defined, then a plain move pattern is generated.
7240 @cindex @code{stack_protect_test} instruction pattern
7241 @item @samp{stack_protect_test}
7242 This pattern, if defined, compares a @code{ptr_mode} value from the
7243 memory in operand 1 with the memory in operand 0 without leaving the
7244 value in a register afterward and branches to operand 2 if the values
7247 If this pattern is not defined, then a plain compare pattern and
7248 conditional branch pattern is used.
7250 @cindex @code{clear_cache} instruction pattern
7251 @item @samp{clear_cache}
7252 This pattern, if defined, flushes the instruction cache for a region of
7253 memory. The region is bounded to by the Pmode pointers in operand 0
7254 inclusive and operand 1 exclusive.
7256 If this pattern is not defined, a call to the library function
7257 @code{__clear_cache} is used.
7262 @c Each of the following nodes are wrapped in separate
7263 @c "@ifset INTERNALS" to work around memory limits for the default
7264 @c configuration in older tetex distributions. Known to not work:
7265 @c tetex-1.0.7, known to work: tetex-2.0.2.
7267 @node Pattern Ordering
7268 @section When the Order of Patterns Matters
7269 @cindex Pattern Ordering
7270 @cindex Ordering of Patterns
7272 Sometimes an insn can match more than one instruction pattern. Then the
7273 pattern that appears first in the machine description is the one used.
7274 Therefore, more specific patterns (patterns that will match fewer things)
7275 and faster instructions (those that will produce better code when they
7276 do match) should usually go first in the description.
7278 In some cases the effect of ordering the patterns can be used to hide
7279 a pattern when it is not valid. For example, the 68000 has an
7280 instruction for converting a fullword to floating point and another
7281 for converting a byte to floating point. An instruction converting
7282 an integer to floating point could match either one. We put the
7283 pattern to convert the fullword first to make sure that one will
7284 be used rather than the other. (Otherwise a large integer might
7285 be generated as a single-byte immediate quantity, which would not work.)
7286 Instead of using this pattern ordering it would be possible to make the
7287 pattern for convert-a-byte smart enough to deal properly with any
7292 @node Dependent Patterns
7293 @section Interdependence of Patterns
7294 @cindex Dependent Patterns
7295 @cindex Interdependence of Patterns
7297 In some cases machines support instructions identical except for the
7298 machine mode of one or more operands. For example, there may be
7299 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
7303 (set (match_operand:SI 0 @dots{})
7304 (extend:SI (match_operand:HI 1 @dots{})))
7306 (set (match_operand:SI 0 @dots{})
7307 (extend:SI (match_operand:QI 1 @dots{})))
7311 Constant integers do not specify a machine mode, so an instruction to
7312 extend a constant value could match either pattern. The pattern it
7313 actually will match is the one that appears first in the file. For correct
7314 results, this must be the one for the widest possible mode (@code{HImode},
7315 here). If the pattern matches the @code{QImode} instruction, the results
7316 will be incorrect if the constant value does not actually fit that mode.
7318 Such instructions to extend constants are rarely generated because they are
7319 optimized away, but they do occasionally happen in nonoptimized
7322 If a constraint in a pattern allows a constant, the reload pass may
7323 replace a register with a constant permitted by the constraint in some
7324 cases. Similarly for memory references. Because of this substitution,
7325 you should not provide separate patterns for increment and decrement
7326 instructions. Instead, they should be generated from the same pattern
7327 that supports register-register add insns by examining the operands and
7328 generating the appropriate machine instruction.
7333 @section Defining Jump Instruction Patterns
7334 @cindex jump instruction patterns
7335 @cindex defining jump instruction patterns
7337 GCC does not assume anything about how the machine realizes jumps.
7338 The machine description should define a single pattern, usually
7339 a @code{define_expand}, which expands to all the required insns.
7341 Usually, this would be a comparison insn to set the condition code
7342 and a separate branch insn testing the condition code and branching
7343 or not according to its value. For many machines, however,
7344 separating compares and branches is limiting, which is why the
7345 more flexible approach with one @code{define_expand} is used in GCC.
7346 The machine description becomes clearer for architectures that
7347 have compare-and-branch instructions but no condition code. It also
7348 works better when different sets of comparison operators are supported
7349 by different kinds of conditional branches (e.g. integer vs. floating-point),
7350 or by conditional branches with respect to conditional stores.
7352 Two separate insns are always used if the machine description represents
7353 a condition code register using the legacy RTL expression @code{(cc0)},
7354 and on most machines that use a separate condition code register
7355 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
7356 fact, the set and use of the condition code must be separate and
7357 adjacent@footnote{@code{note} insns can separate them, though.}, thus
7358 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
7359 so that the comparison and branch insns could be located from each other
7360 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
7362 Even in this case having a single entry point for conditional branches
7363 is advantageous, because it handles equally well the case where a single
7364 comparison instruction records the results of both signed and unsigned
7365 comparison of the given operands (with the branch insns coming in distinct
7366 signed and unsigned flavors) as in the x86 or SPARC, and the case where
7367 there are distinct signed and unsigned compare instructions and only
7368 one set of conditional branch instructions as in the PowerPC.
7372 @node Looping Patterns
7373 @section Defining Looping Instruction Patterns
7374 @cindex looping instruction patterns
7375 @cindex defining looping instruction patterns
7377 Some machines have special jump instructions that can be utilized to
7378 make loops more efficient. A common example is the 68000 @samp{dbra}
7379 instruction which performs a decrement of a register and a branch if the
7380 result was greater than zero. Other machines, in particular digital
7381 signal processors (DSPs), have special block repeat instructions to
7382 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
7383 DSPs have a block repeat instruction that loads special registers to
7384 mark the top and end of a loop and to count the number of loop
7385 iterations. This avoids the need for fetching and executing a
7386 @samp{dbra}-like instruction and avoids pipeline stalls associated with
7389 GCC has three special named patterns to support low overhead looping.
7390 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
7391 and @samp{doloop_end}. The first pattern,
7392 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
7393 generation but may be emitted during the instruction combination phase.
7394 This requires the assistance of the loop optimizer, using information
7395 collected during strength reduction, to reverse a loop to count down to
7396 zero. Some targets also require the loop optimizer to add a
7397 @code{REG_NONNEG} note to indicate that the iteration count is always
7398 positive. This is needed if the target performs a signed loop
7399 termination test. For example, the 68000 uses a pattern similar to the
7400 following for its @code{dbra} instruction:
7404 (define_insn "decrement_and_branch_until_zero"
7407 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
7410 (label_ref (match_operand 1 "" ""))
7413 (plus:SI (match_dup 0)
7415 "find_reg_note (insn, REG_NONNEG, 0)"
7420 Note that since the insn is both a jump insn and has an output, it must
7421 deal with its own reloads, hence the `m' constraints. Also note that
7422 since this insn is generated by the instruction combination phase
7423 combining two sequential insns together into an implicit parallel insn,
7424 the iteration counter needs to be biased by the same amount as the
7425 decrement operation, in this case @minus{}1. Note that the following similar
7426 pattern will not be matched by the combiner.
7430 (define_insn "decrement_and_branch_until_zero"
7433 (ge (match_operand:SI 0 "general_operand" "+d*am")
7435 (label_ref (match_operand 1 "" ""))
7438 (plus:SI (match_dup 0)
7440 "find_reg_note (insn, REG_NONNEG, 0)"
7445 The other two special looping patterns, @samp{doloop_begin} and
7446 @samp{doloop_end}, are emitted by the loop optimizer for certain
7447 well-behaved loops with a finite number of loop iterations using
7448 information collected during strength reduction.
7450 The @samp{doloop_end} pattern describes the actual looping instruction
7451 (or the implicit looping operation) and the @samp{doloop_begin} pattern
7452 is an optional companion pattern that can be used for initialization
7453 needed for some low-overhead looping instructions.
7455 Note that some machines require the actual looping instruction to be
7456 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
7457 the true RTL for a looping instruction at the top of the loop can cause
7458 problems with flow analysis. So instead, a dummy @code{doloop} insn is
7459 emitted at the end of the loop. The machine dependent reorg pass checks
7460 for the presence of this @code{doloop} insn and then searches back to
7461 the top of the loop, where it inserts the true looping insn (provided
7462 there are no instructions in the loop which would cause problems). Any
7463 additional labels can be emitted at this point. In addition, if the
7464 desired special iteration counter register was not allocated, this
7465 machine dependent reorg pass could emit a traditional compare and jump
7468 The essential difference between the
7469 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
7470 patterns is that the loop optimizer allocates an additional pseudo
7471 register for the latter as an iteration counter. This pseudo register
7472 cannot be used within the loop (i.e., general induction variables cannot
7473 be derived from it), however, in many cases the loop induction variable
7474 may become redundant and removed by the flow pass.
7479 @node Insn Canonicalizations
7480 @section Canonicalization of Instructions
7481 @cindex canonicalization of instructions
7482 @cindex insn canonicalization
7484 There are often cases where multiple RTL expressions could represent an
7485 operation performed by a single machine instruction. This situation is
7486 most commonly encountered with logical, branch, and multiply-accumulate
7487 instructions. In such cases, the compiler attempts to convert these
7488 multiple RTL expressions into a single canonical form to reduce the
7489 number of insn patterns required.
7491 In addition to algebraic simplifications, following canonicalizations
7496 For commutative and comparison operators, a constant is always made the
7497 second operand. If a machine only supports a constant as the second
7498 operand, only patterns that match a constant in the second operand need
7502 For associative operators, a sequence of operators will always chain
7503 to the left; for instance, only the left operand of an integer @code{plus}
7504 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
7505 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
7506 @code{umax} are associative when applied to integers, and sometimes to
7510 @cindex @code{neg}, canonicalization of
7511 @cindex @code{not}, canonicalization of
7512 @cindex @code{mult}, canonicalization of
7513 @cindex @code{plus}, canonicalization of
7514 @cindex @code{minus}, canonicalization of
7515 For these operators, if only one operand is a @code{neg}, @code{not},
7516 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
7520 In combinations of @code{neg}, @code{mult}, @code{plus}, and
7521 @code{minus}, the @code{neg} operations (if any) will be moved inside
7522 the operations as far as possible. For instance,
7523 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
7524 @code{(plus (mult (neg B) C) A)} is canonicalized as
7525 @code{(minus A (mult B C))}.
7527 @cindex @code{compare}, canonicalization of
7529 For the @code{compare} operator, a constant is always the second operand
7530 if the first argument is a condition code register or @code{(cc0)}.
7533 For instructions that inherently set a condition code register, the
7534 @code{compare} operator is always written as the first RTL expression of
7535 the @code{parallel} instruction pattern. For example,
7539 [(set (reg:CCZ FLAGS_REG)
7542 (match_operand:SI 1 "register_operand" "%r")
7543 (match_operand:SI 2 "register_operand" "r"))
7545 (set (match_operand:SI 0 "register_operand" "=r")
7546 (plus:SI (match_dup 1) (match_dup 2)))]
7552 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
7553 @code{minus} is made the first operand under the same conditions as
7557 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
7558 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
7562 @code{(minus @var{x} (const_int @var{n}))} is converted to
7563 @code{(plus @var{x} (const_int @var{-n}))}.
7566 Within address computations (i.e., inside @code{mem}), a left shift is
7567 converted into the appropriate multiplication by a power of two.
7569 @cindex @code{ior}, canonicalization of
7570 @cindex @code{and}, canonicalization of
7571 @cindex De Morgan's law
7573 De Morgan's Law is used to move bitwise negation inside a bitwise
7574 logical-and or logical-or operation. If this results in only one
7575 operand being a @code{not} expression, it will be the first one.
7577 A machine that has an instruction that performs a bitwise logical-and of one
7578 operand with the bitwise negation of the other should specify the pattern
7579 for that instruction as
7583 [(set (match_operand:@var{m} 0 @dots{})
7584 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7585 (match_operand:@var{m} 2 @dots{})))]
7591 Similarly, a pattern for a ``NAND'' instruction should be written
7595 [(set (match_operand:@var{m} 0 @dots{})
7596 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7597 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
7602 In both cases, it is not necessary to include patterns for the many
7603 logically equivalent RTL expressions.
7605 @cindex @code{xor}, canonicalization of
7607 The only possible RTL expressions involving both bitwise exclusive-or
7608 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
7609 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
7612 The sum of three items, one of which is a constant, will only appear in
7616 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
7619 @cindex @code{zero_extract}, canonicalization of
7620 @cindex @code{sign_extract}, canonicalization of
7622 Equality comparisons of a group of bits (usually a single bit) with zero
7623 will be written using @code{zero_extract} rather than the equivalent
7624 @code{and} or @code{sign_extract} operations.
7626 @cindex @code{mult}, canonicalization of
7628 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
7629 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
7630 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
7631 for @code{zero_extend}.
7634 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
7635 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
7636 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
7637 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
7638 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
7639 operand of @code{mult} is also a shift, then that is extended also.
7640 This transformation is only applied when it can be proven that the
7641 original operation had sufficient precision to prevent overflow.
7645 Further canonicalization rules are defined in the function
7646 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
7650 @node Expander Definitions
7651 @section Defining RTL Sequences for Code Generation
7652 @cindex expander definitions
7653 @cindex code generation RTL sequences
7654 @cindex defining RTL sequences for code generation
7656 On some target machines, some standard pattern names for RTL generation
7657 cannot be handled with single insn, but a sequence of RTL insns can
7658 represent them. For these target machines, you can write a
7659 @code{define_expand} to specify how to generate the sequence of RTL@.
7661 @findex define_expand
7662 A @code{define_expand} is an RTL expression that looks almost like a
7663 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
7664 only for RTL generation and it can produce more than one RTL insn.
7666 A @code{define_expand} RTX has four operands:
7670 The name. Each @code{define_expand} must have a name, since the only
7671 use for it is to refer to it by name.
7674 The RTL template. This is a vector of RTL expressions representing
7675 a sequence of separate instructions. Unlike @code{define_insn}, there
7676 is no implicit surrounding @code{PARALLEL}.
7679 The condition, a string containing a C expression. This expression is
7680 used to express how the availability of this pattern depends on
7681 subclasses of target machine, selected by command-line options when GCC
7682 is run. This is just like the condition of a @code{define_insn} that
7683 has a standard name. Therefore, the condition (if present) may not
7684 depend on the data in the insn being matched, but only the
7685 target-machine-type flags. The compiler needs to test these conditions
7686 during initialization in order to learn exactly which named instructions
7687 are available in a particular run.
7690 The preparation statements, a string containing zero or more C
7691 statements which are to be executed before RTL code is generated from
7694 Usually these statements prepare temporary registers for use as
7695 internal operands in the RTL template, but they can also generate RTL
7696 insns directly by calling routines such as @code{emit_insn}, etc.
7697 Any such insns precede the ones that come from the RTL template.
7700 Optionally, a vector containing the values of attributes. @xref{Insn
7704 Every RTL insn emitted by a @code{define_expand} must match some
7705 @code{define_insn} in the machine description. Otherwise, the compiler
7706 will crash when trying to generate code for the insn or trying to optimize
7709 The RTL template, in addition to controlling generation of RTL insns,
7710 also describes the operands that need to be specified when this pattern
7711 is used. In particular, it gives a predicate for each operand.
7713 A true operand, which needs to be specified in order to generate RTL from
7714 the pattern, should be described with a @code{match_operand} in its first
7715 occurrence in the RTL template. This enters information on the operand's
7716 predicate into the tables that record such things. GCC uses the
7717 information to preload the operand into a register if that is required for
7718 valid RTL code. If the operand is referred to more than once, subsequent
7719 references should use @code{match_dup}.
7721 The RTL template may also refer to internal ``operands'' which are
7722 temporary registers or labels used only within the sequence made by the
7723 @code{define_expand}. Internal operands are substituted into the RTL
7724 template with @code{match_dup}, never with @code{match_operand}. The
7725 values of the internal operands are not passed in as arguments by the
7726 compiler when it requests use of this pattern. Instead, they are computed
7727 within the pattern, in the preparation statements. These statements
7728 compute the values and store them into the appropriate elements of
7729 @code{operands} so that @code{match_dup} can find them.
7731 There are two special macros defined for use in the preparation statements:
7732 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
7739 Use the @code{DONE} macro to end RTL generation for the pattern. The
7740 only RTL insns resulting from the pattern on this occasion will be
7741 those already emitted by explicit calls to @code{emit_insn} within the
7742 preparation statements; the RTL template will not be generated.
7746 Make the pattern fail on this occasion. When a pattern fails, it means
7747 that the pattern was not truly available. The calling routines in the
7748 compiler will try other strategies for code generation using other patterns.
7750 Failure is currently supported only for binary (addition, multiplication,
7751 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
7755 If the preparation falls through (invokes neither @code{DONE} nor
7756 @code{FAIL}), then the @code{define_expand} acts like a
7757 @code{define_insn} in that the RTL template is used to generate the
7760 The RTL template is not used for matching, only for generating the
7761 initial insn list. If the preparation statement always invokes
7762 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
7763 list of operands, such as this example:
7767 (define_expand "addsi3"
7768 [(match_operand:SI 0 "register_operand" "")
7769 (match_operand:SI 1 "register_operand" "")
7770 (match_operand:SI 2 "register_operand" "")]
7776 handle_add (operands[0], operands[1], operands[2]);
7782 Here is an example, the definition of left-shift for the SPUR chip:
7786 (define_expand "ashlsi3"
7787 [(set (match_operand:SI 0 "register_operand" "")
7791 (match_operand:SI 1 "register_operand" "")
7792 (match_operand:SI 2 "nonmemory_operand" "")))]
7801 if (GET_CODE (operands[2]) != CONST_INT
7802 || (unsigned) INTVAL (operands[2]) > 3)
7809 This example uses @code{define_expand} so that it can generate an RTL insn
7810 for shifting when the shift-count is in the supported range of 0 to 3 but
7811 fail in other cases where machine insns aren't available. When it fails,
7812 the compiler tries another strategy using different patterns (such as, a
7815 If the compiler were able to handle nontrivial condition-strings in
7816 patterns with names, then it would be possible to use a
7817 @code{define_insn} in that case. Here is another case (zero-extension
7818 on the 68000) which makes more use of the power of @code{define_expand}:
7821 (define_expand "zero_extendhisi2"
7822 [(set (match_operand:SI 0 "general_operand" "")
7824 (set (strict_low_part
7828 (match_operand:HI 1 "general_operand" ""))]
7830 "operands[1] = make_safe_from (operands[1], operands[0]);")
7834 @findex make_safe_from
7835 Here two RTL insns are generated, one to clear the entire output operand
7836 and the other to copy the input operand into its low half. This sequence
7837 is incorrect if the input operand refers to [the old value of] the output
7838 operand, so the preparation statement makes sure this isn't so. The
7839 function @code{make_safe_from} copies the @code{operands[1]} into a
7840 temporary register if it refers to @code{operands[0]}. It does this
7841 by emitting another RTL insn.
7843 Finally, a third example shows the use of an internal operand.
7844 Zero-extension on the SPUR chip is done by @code{and}-ing the result
7845 against a halfword mask. But this mask cannot be represented by a
7846 @code{const_int} because the constant value is too large to be legitimate
7847 on this machine. So it must be copied into a register with
7848 @code{force_reg} and then the register used in the @code{and}.
7851 (define_expand "zero_extendhisi2"
7852 [(set (match_operand:SI 0 "register_operand" "")
7854 (match_operand:HI 1 "register_operand" "")
7859 = force_reg (SImode, GEN_INT (65535)); ")
7862 @emph{Note:} If the @code{define_expand} is used to serve a
7863 standard binary or unary arithmetic operation or a bit-field operation,
7864 then the last insn it generates must not be a @code{code_label},
7865 @code{barrier} or @code{note}. It must be an @code{insn},
7866 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
7867 at the end, emit an insn to copy the result of the operation into
7868 itself. Such an insn will generate no code, but it can avoid problems
7873 @node Insn Splitting
7874 @section Defining How to Split Instructions
7875 @cindex insn splitting
7876 @cindex instruction splitting
7877 @cindex splitting instructions
7879 There are two cases where you should specify how to split a pattern
7880 into multiple insns. On machines that have instructions requiring
7881 delay slots (@pxref{Delay Slots}) or that have instructions whose
7882 output is not available for multiple cycles (@pxref{Processor pipeline
7883 description}), the compiler phases that optimize these cases need to
7884 be able to move insns into one-instruction delay slots. However, some
7885 insns may generate more than one machine instruction. These insns
7886 cannot be placed into a delay slot.
7888 Often you can rewrite the single insn as a list of individual insns,
7889 each corresponding to one machine instruction. The disadvantage of
7890 doing so is that it will cause the compilation to be slower and require
7891 more space. If the resulting insns are too complex, it may also
7892 suppress some optimizations. The compiler splits the insn if there is a
7893 reason to believe that it might improve instruction or delay slot
7896 The insn combiner phase also splits putative insns. If three insns are
7897 merged into one insn with a complex expression that cannot be matched by
7898 some @code{define_insn} pattern, the combiner phase attempts to split
7899 the complex pattern into two insns that are recognized. Usually it can
7900 break the complex pattern into two patterns by splitting out some
7901 subexpression. However, in some other cases, such as performing an
7902 addition of a large constant in two insns on a RISC machine, the way to
7903 split the addition into two insns is machine-dependent.
7905 @findex define_split
7906 The @code{define_split} definition tells the compiler how to split a
7907 complex insn into several simpler insns. It looks like this:
7911 [@var{insn-pattern}]
7913 [@var{new-insn-pattern-1}
7914 @var{new-insn-pattern-2}
7916 "@var{preparation-statements}")
7919 @var{insn-pattern} is a pattern that needs to be split and
7920 @var{condition} is the final condition to be tested, as in a
7921 @code{define_insn}. When an insn matching @var{insn-pattern} and
7922 satisfying @var{condition} is found, it is replaced in the insn list
7923 with the insns given by @var{new-insn-pattern-1},
7924 @var{new-insn-pattern-2}, etc.
7926 The @var{preparation-statements} are similar to those statements that
7927 are specified for @code{define_expand} (@pxref{Expander Definitions})
7928 and are executed before the new RTL is generated to prepare for the
7929 generated code or emit some insns whose pattern is not fixed. Unlike
7930 those in @code{define_expand}, however, these statements must not
7931 generate any new pseudo-registers. Once reload has completed, they also
7932 must not allocate any space in the stack frame.
7934 Patterns are matched against @var{insn-pattern} in two different
7935 circumstances. If an insn needs to be split for delay slot scheduling
7936 or insn scheduling, the insn is already known to be valid, which means
7937 that it must have been matched by some @code{define_insn} and, if
7938 @code{reload_completed} is nonzero, is known to satisfy the constraints
7939 of that @code{define_insn}. In that case, the new insn patterns must
7940 also be insns that are matched by some @code{define_insn} and, if
7941 @code{reload_completed} is nonzero, must also satisfy the constraints
7942 of those definitions.
7944 As an example of this usage of @code{define_split}, consider the following
7945 example from @file{a29k.md}, which splits a @code{sign_extend} from
7946 @code{HImode} to @code{SImode} into a pair of shift insns:
7950 [(set (match_operand:SI 0 "gen_reg_operand" "")
7951 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
7954 (ashift:SI (match_dup 1)
7957 (ashiftrt:SI (match_dup 0)
7960 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
7963 When the combiner phase tries to split an insn pattern, it is always the
7964 case that the pattern is @emph{not} matched by any @code{define_insn}.
7965 The combiner pass first tries to split a single @code{set} expression
7966 and then the same @code{set} expression inside a @code{parallel}, but
7967 followed by a @code{clobber} of a pseudo-reg to use as a scratch
7968 register. In these cases, the combiner expects exactly two new insn
7969 patterns to be generated. It will verify that these patterns match some
7970 @code{define_insn} definitions, so you need not do this test in the
7971 @code{define_split} (of course, there is no point in writing a
7972 @code{define_split} that will never produce insns that match).
7974 Here is an example of this use of @code{define_split}, taken from
7979 [(set (match_operand:SI 0 "gen_reg_operand" "")
7980 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
7981 (match_operand:SI 2 "non_add_cint_operand" "")))]
7983 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
7984 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
7987 int low = INTVAL (operands[2]) & 0xffff;
7988 int high = (unsigned) INTVAL (operands[2]) >> 16;
7991 high++, low |= 0xffff0000;
7993 operands[3] = GEN_INT (high << 16);
7994 operands[4] = GEN_INT (low);
7998 Here the predicate @code{non_add_cint_operand} matches any
7999 @code{const_int} that is @emph{not} a valid operand of a single add
8000 insn. The add with the smaller displacement is written so that it
8001 can be substituted into the address of a subsequent operation.
8003 An example that uses a scratch register, from the same file, generates
8004 an equality comparison of a register and a large constant:
8008 [(set (match_operand:CC 0 "cc_reg_operand" "")
8009 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
8010 (match_operand:SI 2 "non_short_cint_operand" "")))
8011 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
8012 "find_single_use (operands[0], insn, 0)
8013 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
8014 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
8015 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
8016 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
8019 /* @r{Get the constant we are comparing against, C, and see what it
8020 looks like sign-extended to 16 bits. Then see what constant
8021 could be XOR'ed with C to get the sign-extended value.} */
8023 int c = INTVAL (operands[2]);
8024 int sextc = (c << 16) >> 16;
8025 int xorv = c ^ sextc;
8027 operands[4] = GEN_INT (xorv);
8028 operands[5] = GEN_INT (sextc);
8032 To avoid confusion, don't write a single @code{define_split} that
8033 accepts some insns that match some @code{define_insn} as well as some
8034 insns that don't. Instead, write two separate @code{define_split}
8035 definitions, one for the insns that are valid and one for the insns that
8038 The splitter is allowed to split jump instructions into sequence of
8039 jumps or create new jumps in while splitting non-jump instructions. As
8040 the control flow graph and branch prediction information needs to be updated,
8041 several restriction apply.
8043 Splitting of jump instruction into sequence that over by another jump
8044 instruction is always valid, as compiler expect identical behavior of new
8045 jump. When new sequence contains multiple jump instructions or new labels,
8046 more assistance is needed. Splitter is required to create only unconditional
8047 jumps, or simple conditional jump instructions. Additionally it must attach a
8048 @code{REG_BR_PROB} note to each conditional jump. A global variable
8049 @code{split_branch_probability} holds the probability of the original branch in case
8050 it was a simple conditional jump, @minus{}1 otherwise. To simplify
8051 recomputing of edge frequencies, the new sequence is required to have only
8052 forward jumps to the newly created labels.
8054 @findex define_insn_and_split
8055 For the common case where the pattern of a define_split exactly matches the
8056 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
8060 (define_insn_and_split
8061 [@var{insn-pattern}]
8063 "@var{output-template}"
8064 "@var{split-condition}"
8065 [@var{new-insn-pattern-1}
8066 @var{new-insn-pattern-2}
8068 "@var{preparation-statements}"
8069 [@var{insn-attributes}])
8073 @var{insn-pattern}, @var{condition}, @var{output-template}, and
8074 @var{insn-attributes} are used as in @code{define_insn}. The
8075 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
8076 in a @code{define_split}. The @var{split-condition} is also used as in
8077 @code{define_split}, with the additional behavior that if the condition starts
8078 with @samp{&&}, the condition used for the split will be the constructed as a
8079 logical ``and'' of the split condition with the insn condition. For example,
8083 (define_insn_and_split "zero_extendhisi2_and"
8084 [(set (match_operand:SI 0 "register_operand" "=r")
8085 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
8086 (clobber (reg:CC 17))]
8087 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
8089 "&& reload_completed"
8090 [(parallel [(set (match_dup 0)
8091 (and:SI (match_dup 0) (const_int 65535)))
8092 (clobber (reg:CC 17))])]
8094 [(set_attr "type" "alu1")])
8098 In this case, the actual split condition will be
8099 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
8101 The @code{define_insn_and_split} construction provides exactly the same
8102 functionality as two separate @code{define_insn} and @code{define_split}
8103 patterns. It exists for compactness, and as a maintenance tool to prevent
8104 having to ensure the two patterns' templates match.
8108 @node Including Patterns
8109 @section Including Patterns in Machine Descriptions.
8110 @cindex insn includes
8113 The @code{include} pattern tells the compiler tools where to
8114 look for patterns that are in files other than in the file
8115 @file{.md}. This is used only at build time and there is no preprocessing allowed.
8129 (include "filestuff")
8133 Where @var{pathname} is a string that specifies the location of the file,
8134 specifies the include file to be in @file{gcc/config/target/filestuff}. The
8135 directory @file{gcc/config/target} is regarded as the default directory.
8138 Machine descriptions may be split up into smaller more manageable subsections
8139 and placed into subdirectories.
8145 (include "BOGUS/filestuff")
8149 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
8151 Specifying an absolute path for the include file such as;
8154 (include "/u2/BOGUS/filestuff")
8157 is permitted but is not encouraged.
8159 @subsection RTL Generation Tool Options for Directory Search
8160 @cindex directory options .md
8161 @cindex options, directory search
8162 @cindex search options
8164 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
8169 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
8174 Add the directory @var{dir} to the head of the list of directories to be
8175 searched for header files. This can be used to override a system machine definition
8176 file, substituting your own version, since these directories are
8177 searched before the default machine description file directories. If you use more than
8178 one @option{-I} option, the directories are scanned in left-to-right
8179 order; the standard default directory come after.
8184 @node Peephole Definitions
8185 @section Machine-Specific Peephole Optimizers
8186 @cindex peephole optimizer definitions
8187 @cindex defining peephole optimizers
8189 In addition to instruction patterns the @file{md} file may contain
8190 definitions of machine-specific peephole optimizations.
8192 The combiner does not notice certain peephole optimizations when the data
8193 flow in the program does not suggest that it should try them. For example,
8194 sometimes two consecutive insns related in purpose can be combined even
8195 though the second one does not appear to use a register computed in the
8196 first one. A machine-specific peephole optimizer can detect such
8199 There are two forms of peephole definitions that may be used. The
8200 original @code{define_peephole} is run at assembly output time to
8201 match insns and substitute assembly text. Use of @code{define_peephole}
8204 A newer @code{define_peephole2} matches insns and substitutes new
8205 insns. The @code{peephole2} pass is run after register allocation
8206 but before scheduling, which may result in much better code for
8207 targets that do scheduling.
8210 * define_peephole:: RTL to Text Peephole Optimizers
8211 * define_peephole2:: RTL to RTL Peephole Optimizers
8216 @node define_peephole
8217 @subsection RTL to Text Peephole Optimizers
8218 @findex define_peephole
8221 A definition looks like this:
8225 [@var{insn-pattern-1}
8226 @var{insn-pattern-2}
8230 "@var{optional-insn-attributes}")
8234 The last string operand may be omitted if you are not using any
8235 machine-specific information in this machine description. If present,
8236 it must obey the same rules as in a @code{define_insn}.
8238 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
8239 consecutive insns. The optimization applies to a sequence of insns when
8240 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
8241 the next, and so on.
8243 Each of the insns matched by a peephole must also match a
8244 @code{define_insn}. Peepholes are checked only at the last stage just
8245 before code generation, and only optionally. Therefore, any insn which
8246 would match a peephole but no @code{define_insn} will cause a crash in code
8247 generation in an unoptimized compilation, or at various optimization
8250 The operands of the insns are matched with @code{match_operands},
8251 @code{match_operator}, and @code{match_dup}, as usual. What is not
8252 usual is that the operand numbers apply to all the insn patterns in the
8253 definition. So, you can check for identical operands in two insns by
8254 using @code{match_operand} in one insn and @code{match_dup} in the
8257 The operand constraints used in @code{match_operand} patterns do not have
8258 any direct effect on the applicability of the peephole, but they will
8259 be validated afterward, so make sure your constraints are general enough
8260 to apply whenever the peephole matches. If the peephole matches
8261 but the constraints are not satisfied, the compiler will crash.
8263 It is safe to omit constraints in all the operands of the peephole; or
8264 you can write constraints which serve as a double-check on the criteria
8267 Once a sequence of insns matches the patterns, the @var{condition} is
8268 checked. This is a C expression which makes the final decision whether to
8269 perform the optimization (we do so if the expression is nonzero). If
8270 @var{condition} is omitted (in other words, the string is empty) then the
8271 optimization is applied to every sequence of insns that matches the
8274 The defined peephole optimizations are applied after register allocation
8275 is complete. Therefore, the peephole definition can check which
8276 operands have ended up in which kinds of registers, just by looking at
8279 @findex prev_active_insn
8280 The way to refer to the operands in @var{condition} is to write
8281 @code{operands[@var{i}]} for operand number @var{i} (as matched by
8282 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
8283 to refer to the last of the insns being matched; use
8284 @code{prev_active_insn} to find the preceding insns.
8286 @findex dead_or_set_p
8287 When optimizing computations with intermediate results, you can use
8288 @var{condition} to match only when the intermediate results are not used
8289 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
8290 @var{op})}, where @var{insn} is the insn in which you expect the value
8291 to be used for the last time (from the value of @code{insn}, together
8292 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
8293 value (from @code{operands[@var{i}]}).
8295 Applying the optimization means replacing the sequence of insns with one
8296 new insn. The @var{template} controls ultimate output of assembler code
8297 for this combined insn. It works exactly like the template of a
8298 @code{define_insn}. Operand numbers in this template are the same ones
8299 used in matching the original sequence of insns.
8301 The result of a defined peephole optimizer does not need to match any of
8302 the insn patterns in the machine description; it does not even have an
8303 opportunity to match them. The peephole optimizer definition itself serves
8304 as the insn pattern to control how the insn is output.
8306 Defined peephole optimizers are run as assembler code is being output,
8307 so the insns they produce are never combined or rearranged in any way.
8309 Here is an example, taken from the 68000 machine description:
8313 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
8314 (set (match_operand:DF 0 "register_operand" "=f")
8315 (match_operand:DF 1 "register_operand" "ad"))]
8316 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
8319 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8321 output_asm_insn ("move.l %1,(sp)", xoperands);
8322 output_asm_insn ("move.l %1,-(sp)", operands);
8323 return "fmove.d (sp)+,%0";
8325 output_asm_insn ("movel %1,sp@@", xoperands);
8326 output_asm_insn ("movel %1,sp@@-", operands);
8327 return "fmoved sp@@+,%0";
8333 The effect of this optimization is to change
8359 If a peephole matches a sequence including one or more jump insns, you must
8360 take account of the flags such as @code{CC_REVERSED} which specify that the
8361 condition codes are represented in an unusual manner. The compiler
8362 automatically alters any ordinary conditional jumps which occur in such
8363 situations, but the compiler cannot alter jumps which have been replaced by
8364 peephole optimizations. So it is up to you to alter the assembler code
8365 that the peephole produces. Supply C code to write the assembler output,
8366 and in this C code check the condition code status flags and change the
8367 assembler code as appropriate.
8370 @var{insn-pattern-1} and so on look @emph{almost} like the second
8371 operand of @code{define_insn}. There is one important difference: the
8372 second operand of @code{define_insn} consists of one or more RTX's
8373 enclosed in square brackets. Usually, there is only one: then the same
8374 action can be written as an element of a @code{define_peephole}. But
8375 when there are multiple actions in a @code{define_insn}, they are
8376 implicitly enclosed in a @code{parallel}. Then you must explicitly
8377 write the @code{parallel}, and the square brackets within it, in the
8378 @code{define_peephole}. Thus, if an insn pattern looks like this,
8381 (define_insn "divmodsi4"
8382 [(set (match_operand:SI 0 "general_operand" "=d")
8383 (div:SI (match_operand:SI 1 "general_operand" "0")
8384 (match_operand:SI 2 "general_operand" "dmsK")))
8385 (set (match_operand:SI 3 "general_operand" "=d")
8386 (mod:SI (match_dup 1) (match_dup 2)))]
8388 "divsl%.l %2,%3:%0")
8392 then the way to mention this insn in a peephole is as follows:
8398 [(set (match_operand:SI 0 "general_operand" "=d")
8399 (div:SI (match_operand:SI 1 "general_operand" "0")
8400 (match_operand:SI 2 "general_operand" "dmsK")))
8401 (set (match_operand:SI 3 "general_operand" "=d")
8402 (mod:SI (match_dup 1) (match_dup 2)))])
8409 @node define_peephole2
8410 @subsection RTL to RTL Peephole Optimizers
8411 @findex define_peephole2
8413 The @code{define_peephole2} definition tells the compiler how to
8414 substitute one sequence of instructions for another sequence,
8415 what additional scratch registers may be needed and what their
8420 [@var{insn-pattern-1}
8421 @var{insn-pattern-2}
8424 [@var{new-insn-pattern-1}
8425 @var{new-insn-pattern-2}
8427 "@var{preparation-statements}")
8430 The definition is almost identical to @code{define_split}
8431 (@pxref{Insn Splitting}) except that the pattern to match is not a
8432 single instruction, but a sequence of instructions.
8434 It is possible to request additional scratch registers for use in the
8435 output template. If appropriate registers are not free, the pattern
8436 will simply not match.
8438 @findex match_scratch
8440 Scratch registers are requested with a @code{match_scratch} pattern at
8441 the top level of the input pattern. The allocated register (initially) will
8442 be dead at the point requested within the original sequence. If the scratch
8443 is used at more than a single point, a @code{match_dup} pattern at the
8444 top level of the input pattern marks the last position in the input sequence
8445 at which the register must be available.
8447 Here is an example from the IA-32 machine description:
8451 [(match_scratch:SI 2 "r")
8452 (parallel [(set (match_operand:SI 0 "register_operand" "")
8453 (match_operator:SI 3 "arith_or_logical_operator"
8455 (match_operand:SI 1 "memory_operand" "")]))
8456 (clobber (reg:CC 17))])]
8457 "! optimize_size && ! TARGET_READ_MODIFY"
8458 [(set (match_dup 2) (match_dup 1))
8459 (parallel [(set (match_dup 0)
8460 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
8461 (clobber (reg:CC 17))])]
8466 This pattern tries to split a load from its use in the hopes that we'll be
8467 able to schedule around the memory load latency. It allocates a single
8468 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
8469 to be live only at the point just before the arithmetic.
8471 A real example requiring extended scratch lifetimes is harder to come by,
8472 so here's a silly made-up example:
8476 [(match_scratch:SI 4 "r")
8477 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
8478 (set (match_operand:SI 2 "" "") (match_dup 1))
8480 (set (match_operand:SI 3 "" "") (match_dup 1))]
8481 "/* @r{determine 1 does not overlap 0 and 2} */"
8482 [(set (match_dup 4) (match_dup 1))
8483 (set (match_dup 0) (match_dup 4))
8484 (set (match_dup 2) (match_dup 4))
8485 (set (match_dup 3) (match_dup 4))]
8490 If we had not added the @code{(match_dup 4)} in the middle of the input
8491 sequence, it might have been the case that the register we chose at the
8492 beginning of the sequence is killed by the first or second @code{set}.
8496 @node Insn Attributes
8497 @section Instruction Attributes
8498 @cindex insn attributes
8499 @cindex instruction attributes
8501 In addition to describing the instruction supported by the target machine,
8502 the @file{md} file also defines a group of @dfn{attributes} and a set of
8503 values for each. Every generated insn is assigned a value for each attribute.
8504 One possible attribute would be the effect that the insn has on the machine's
8505 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
8506 to track the condition codes.
8509 * Defining Attributes:: Specifying attributes and their values.
8510 * Expressions:: Valid expressions for attribute values.
8511 * Tagging Insns:: Assigning attribute values to insns.
8512 * Attr Example:: An example of assigning attributes.
8513 * Insn Lengths:: Computing the length of insns.
8514 * Constant Attributes:: Defining attributes that are constant.
8515 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
8516 * Delay Slots:: Defining delay slots required for a machine.
8517 * Processor pipeline description:: Specifying information for insn scheduling.
8522 @node Defining Attributes
8523 @subsection Defining Attributes and their Values
8524 @cindex defining attributes and their values
8525 @cindex attributes, defining
8528 The @code{define_attr} expression is used to define each attribute required
8529 by the target machine. It looks like:
8532 (define_attr @var{name} @var{list-of-values} @var{default})
8535 @var{name} is a string specifying the name of the attribute being
8536 defined. Some attributes are used in a special way by the rest of the
8537 compiler. The @code{enabled} attribute can be used to conditionally
8538 enable or disable insn alternatives (@pxref{Disable Insn
8539 Alternatives}). The @code{predicable} attribute, together with a
8540 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
8541 be used to automatically generate conditional variants of instruction
8542 patterns. The @code{mnemonic} attribute can be used to check for the
8543 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
8544 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
8545 so they should not be used elsewhere as alternative names.
8547 @var{list-of-values} is either a string that specifies a comma-separated
8548 list of values that can be assigned to the attribute, or a null string to
8549 indicate that the attribute takes numeric values.
8551 @var{default} is an attribute expression that gives the value of this
8552 attribute for insns that match patterns whose definition does not include
8553 an explicit value for this attribute. @xref{Attr Example}, for more
8554 information on the handling of defaults. @xref{Constant Attributes},
8555 for information on attributes that do not depend on any particular insn.
8558 For each defined attribute, a number of definitions are written to the
8559 @file{insn-attr.h} file. For cases where an explicit set of values is
8560 specified for an attribute, the following are defined:
8564 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
8567 An enumerated class is defined for @samp{attr_@var{name}} with
8568 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
8569 the attribute name and value are first converted to uppercase.
8572 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
8573 returns the attribute value for that insn.
8576 For example, if the following is present in the @file{md} file:
8579 (define_attr "type" "branch,fp,load,store,arith" @dots{})
8583 the following lines will be written to the file @file{insn-attr.h}.
8586 #define HAVE_ATTR_type 1
8587 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
8588 TYPE_STORE, TYPE_ARITH@};
8589 extern enum attr_type get_attr_type ();
8592 If the attribute takes numeric values, no @code{enum} type will be
8593 defined and the function to obtain the attribute's value will return
8596 There are attributes which are tied to a specific meaning. These
8597 attributes are not free to use for other purposes:
8601 The @code{length} attribute is used to calculate the length of emitted
8602 code chunks. This is especially important when verifying branch
8603 distances. @xref{Insn Lengths}.
8606 The @code{enabled} attribute can be defined to prevent certain
8607 alternatives of an insn definition from being used during code
8608 generation. @xref{Disable Insn Alternatives}.
8611 The @code{mnemonic} attribute can be defined to implement instruction
8612 specific checks in e.g. the pipeline description.
8613 @xref{Mnemonic Attribute}.
8616 For each of these special attributes, the corresponding
8617 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
8618 attribute is not defined; in that case, it is defined as @samp{0}.
8620 @findex define_enum_attr
8621 @anchor{define_enum_attr}
8622 Another way of defining an attribute is to use:
8625 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
8628 This works in just the same way as @code{define_attr}, except that
8629 the list of values is taken from a separate enumeration called
8630 @var{enum} (@pxref{define_enum}). This form allows you to use
8631 the same list of values for several attributes without having to
8632 repeat the list each time. For example:
8635 (define_enum "processor" [
8640 (define_enum_attr "arch" "processor"
8641 (const (symbol_ref "target_arch")))
8642 (define_enum_attr "tune" "processor"
8643 (const (symbol_ref "target_tune")))
8646 defines the same attributes as:
8649 (define_attr "arch" "model_a,model_b,@dots{}"
8650 (const (symbol_ref "target_arch")))
8651 (define_attr "tune" "model_a,model_b,@dots{}"
8652 (const (symbol_ref "target_tune")))
8655 but without duplicating the processor list. The second example defines two
8656 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
8657 defines a single C enum (@code{processor}).
8661 @subsection Attribute Expressions
8662 @cindex attribute expressions
8664 RTL expressions used to define attributes use the codes described above
8665 plus a few specific to attribute definitions, to be discussed below.
8666 Attribute value expressions must have one of the following forms:
8669 @cindex @code{const_int} and attributes
8670 @item (const_int @var{i})
8671 The integer @var{i} specifies the value of a numeric attribute. @var{i}
8672 must be non-negative.
8674 The value of a numeric attribute can be specified either with a
8675 @code{const_int}, or as an integer represented as a string in
8676 @code{const_string}, @code{eq_attr} (see below), @code{attr},
8677 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
8678 overrides on specific instructions (@pxref{Tagging Insns}).
8680 @cindex @code{const_string} and attributes
8681 @item (const_string @var{value})
8682 The string @var{value} specifies a constant attribute value.
8683 If @var{value} is specified as @samp{"*"}, it means that the default value of
8684 the attribute is to be used for the insn containing this expression.
8685 @samp{"*"} obviously cannot be used in the @var{default} expression
8686 of a @code{define_attr}.
8688 If the attribute whose value is being specified is numeric, @var{value}
8689 must be a string containing a non-negative integer (normally
8690 @code{const_int} would be used in this case). Otherwise, it must
8691 contain one of the valid values for the attribute.
8693 @cindex @code{if_then_else} and attributes
8694 @item (if_then_else @var{test} @var{true-value} @var{false-value})
8695 @var{test} specifies an attribute test, whose format is defined below.
8696 The value of this expression is @var{true-value} if @var{test} is true,
8697 otherwise it is @var{false-value}.
8699 @cindex @code{cond} and attributes
8700 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
8701 The first operand of this expression is a vector containing an even
8702 number of expressions and consisting of pairs of @var{test} and @var{value}
8703 expressions. The value of the @code{cond} expression is that of the
8704 @var{value} corresponding to the first true @var{test} expression. If
8705 none of the @var{test} expressions are true, the value of the @code{cond}
8706 expression is that of the @var{default} expression.
8709 @var{test} expressions can have one of the following forms:
8712 @cindex @code{const_int} and attribute tests
8713 @item (const_int @var{i})
8714 This test is true if @var{i} is nonzero and false otherwise.
8716 @cindex @code{not} and attributes
8717 @cindex @code{ior} and attributes
8718 @cindex @code{and} and attributes
8719 @item (not @var{test})
8720 @itemx (ior @var{test1} @var{test2})
8721 @itemx (and @var{test1} @var{test2})
8722 These tests are true if the indicated logical function is true.
8724 @cindex @code{match_operand} and attributes
8725 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
8726 This test is true if operand @var{n} of the insn whose attribute value
8727 is being determined has mode @var{m} (this part of the test is ignored
8728 if @var{m} is @code{VOIDmode}) and the function specified by the string
8729 @var{pred} returns a nonzero value when passed operand @var{n} and mode
8730 @var{m} (this part of the test is ignored if @var{pred} is the null
8733 The @var{constraints} operand is ignored and should be the null string.
8735 @cindex @code{match_test} and attributes
8736 @item (match_test @var{c-expr})
8737 The test is true if C expression @var{c-expr} is true. In non-constant
8738 attributes, @var{c-expr} has access to the following variables:
8742 The rtl instruction under test.
8743 @item which_alternative
8744 The @code{define_insn} alternative that @var{insn} matches.
8745 @xref{Output Statement}.
8747 An array of @var{insn}'s rtl operands.
8750 @var{c-expr} behaves like the condition in a C @code{if} statement,
8751 so there is no need to explicitly convert the expression into a boolean
8752 0 or 1 value. For example, the following two tests are equivalent:
8755 (match_test "x & 2")
8756 (match_test "(x & 2) != 0")
8759 @cindex @code{le} and attributes
8760 @cindex @code{leu} and attributes
8761 @cindex @code{lt} and attributes
8762 @cindex @code{gt} and attributes
8763 @cindex @code{gtu} and attributes
8764 @cindex @code{ge} and attributes
8765 @cindex @code{geu} and attributes
8766 @cindex @code{ne} and attributes
8767 @cindex @code{eq} and attributes
8768 @cindex @code{plus} and attributes
8769 @cindex @code{minus} and attributes
8770 @cindex @code{mult} and attributes
8771 @cindex @code{div} and attributes
8772 @cindex @code{mod} and attributes
8773 @cindex @code{abs} and attributes
8774 @cindex @code{neg} and attributes
8775 @cindex @code{ashift} and attributes
8776 @cindex @code{lshiftrt} and attributes
8777 @cindex @code{ashiftrt} and attributes
8778 @item (le @var{arith1} @var{arith2})
8779 @itemx (leu @var{arith1} @var{arith2})
8780 @itemx (lt @var{arith1} @var{arith2})
8781 @itemx (ltu @var{arith1} @var{arith2})
8782 @itemx (gt @var{arith1} @var{arith2})
8783 @itemx (gtu @var{arith1} @var{arith2})
8784 @itemx (ge @var{arith1} @var{arith2})
8785 @itemx (geu @var{arith1} @var{arith2})
8786 @itemx (ne @var{arith1} @var{arith2})
8787 @itemx (eq @var{arith1} @var{arith2})
8788 These tests are true if the indicated comparison of the two arithmetic
8789 expressions is true. Arithmetic expressions are formed with
8790 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
8791 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
8792 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
8795 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
8796 Lengths},for additional forms). @code{symbol_ref} is a string
8797 denoting a C expression that yields an @code{int} when evaluated by the
8798 @samp{get_attr_@dots{}} routine. It should normally be a global
8802 @item (eq_attr @var{name} @var{value})
8803 @var{name} is a string specifying the name of an attribute.
8805 @var{value} is a string that is either a valid value for attribute
8806 @var{name}, a comma-separated list of values, or @samp{!} followed by a
8807 value or list. If @var{value} does not begin with a @samp{!}, this
8808 test is true if the value of the @var{name} attribute of the current
8809 insn is in the list specified by @var{value}. If @var{value} begins
8810 with a @samp{!}, this test is true if the attribute's value is
8811 @emph{not} in the specified list.
8816 (eq_attr "type" "load,store")
8823 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
8826 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
8827 value of the compiler variable @code{which_alternative}
8828 (@pxref{Output Statement}) and the values must be small integers. For
8832 (eq_attr "alternative" "2,3")
8839 (ior (eq (symbol_ref "which_alternative") (const_int 2))
8840 (eq (symbol_ref "which_alternative") (const_int 3)))
8843 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
8844 where the value of the attribute being tested is known for all insns matching
8845 a particular pattern. This is by far the most common case.
8848 @item (attr_flag @var{name})
8849 The value of an @code{attr_flag} expression is true if the flag
8850 specified by @var{name} is true for the @code{insn} currently being
8853 @var{name} is a string specifying one of a fixed set of flags to test.
8854 Test the flags @code{forward} and @code{backward} to determine the
8855 direction of a conditional branch.
8857 This example describes a conditional branch delay slot which
8858 can be nullified for forward branches that are taken (annul-true) or
8859 for backward branches which are not taken (annul-false).
8862 (define_delay (eq_attr "type" "cbranch")
8863 [(eq_attr "in_branch_delay" "true")
8864 (and (eq_attr "in_branch_delay" "true")
8865 (attr_flag "forward"))
8866 (and (eq_attr "in_branch_delay" "true")
8867 (attr_flag "backward"))])
8870 The @code{forward} and @code{backward} flags are false if the current
8871 @code{insn} being scheduled is not a conditional branch.
8873 @code{attr_flag} is only used during delay slot scheduling and has no
8874 meaning to other passes of the compiler.
8877 @item (attr @var{name})
8878 The value of another attribute is returned. This is most useful
8879 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
8880 produce more efficient code for non-numeric attributes.
8886 @subsection Assigning Attribute Values to Insns
8887 @cindex tagging insns
8888 @cindex assigning attribute values to insns
8890 The value assigned to an attribute of an insn is primarily determined by
8891 which pattern is matched by that insn (or which @code{define_peephole}
8892 generated it). Every @code{define_insn} and @code{define_peephole} can
8893 have an optional last argument to specify the values of attributes for
8894 matching insns. The value of any attribute not specified in a particular
8895 insn is set to the default value for that attribute, as specified in its
8896 @code{define_attr}. Extensive use of default values for attributes
8897 permits the specification of the values for only one or two attributes
8898 in the definition of most insn patterns, as seen in the example in the
8901 The optional last argument of @code{define_insn} and
8902 @code{define_peephole} is a vector of expressions, each of which defines
8903 the value for a single attribute. The most general way of assigning an
8904 attribute's value is to use a @code{set} expression whose first operand is an
8905 @code{attr} expression giving the name of the attribute being set. The
8906 second operand of the @code{set} is an attribute expression
8907 (@pxref{Expressions}) giving the value of the attribute.
8909 When the attribute value depends on the @samp{alternative} attribute
8910 (i.e., which is the applicable alternative in the constraint of the
8911 insn), the @code{set_attr_alternative} expression can be used. It
8912 allows the specification of a vector of attribute expressions, one for
8916 When the generality of arbitrary attribute expressions is not required,
8917 the simpler @code{set_attr} expression can be used, which allows
8918 specifying a string giving either a single attribute value or a list
8919 of attribute values, one for each alternative.
8921 The form of each of the above specifications is shown below. In each case,
8922 @var{name} is a string specifying the attribute to be set.
8925 @item (set_attr @var{name} @var{value-string})
8926 @var{value-string} is either a string giving the desired attribute value,
8927 or a string containing a comma-separated list giving the values for
8928 succeeding alternatives. The number of elements must match the number
8929 of alternatives in the constraint of the insn pattern.
8931 Note that it may be useful to specify @samp{*} for some alternative, in
8932 which case the attribute will assume its default value for insns matching
8935 @findex set_attr_alternative
8936 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
8937 Depending on the alternative of the insn, the value will be one of the
8938 specified values. This is a shorthand for using a @code{cond} with
8939 tests on the @samp{alternative} attribute.
8942 @item (set (attr @var{name}) @var{value})
8943 The first operand of this @code{set} must be the special RTL expression
8944 @code{attr}, whose sole operand is a string giving the name of the
8945 attribute being set. @var{value} is the value of the attribute.
8948 The following shows three different ways of representing the same
8949 attribute value specification:
8952 (set_attr "type" "load,store,arith")
8954 (set_attr_alternative "type"
8955 [(const_string "load") (const_string "store")
8956 (const_string "arith")])
8959 (cond [(eq_attr "alternative" "1") (const_string "load")
8960 (eq_attr "alternative" "2") (const_string "store")]
8961 (const_string "arith")))
8965 @findex define_asm_attributes
8966 The @code{define_asm_attributes} expression provides a mechanism to
8967 specify the attributes assigned to insns produced from an @code{asm}
8968 statement. It has the form:
8971 (define_asm_attributes [@var{attr-sets}])
8975 where @var{attr-sets} is specified the same as for both the
8976 @code{define_insn} and the @code{define_peephole} expressions.
8978 These values will typically be the ``worst case'' attribute values. For
8979 example, they might indicate that the condition code will be clobbered.
8981 A specification for a @code{length} attribute is handled specially. The
8982 way to compute the length of an @code{asm} insn is to multiply the
8983 length specified in the expression @code{define_asm_attributes} by the
8984 number of machine instructions specified in the @code{asm} statement,
8985 determined by counting the number of semicolons and newlines in the
8986 string. Therefore, the value of the @code{length} attribute specified
8987 in a @code{define_asm_attributes} should be the maximum possible length
8988 of a single machine instruction.
8993 @subsection Example of Attribute Specifications
8994 @cindex attribute specifications example
8995 @cindex attribute specifications
8997 The judicious use of defaulting is important in the efficient use of
8998 insn attributes. Typically, insns are divided into @dfn{types} and an
8999 attribute, customarily called @code{type}, is used to represent this
9000 value. This attribute is normally used only to define the default value
9001 for other attributes. An example will clarify this usage.
9003 Assume we have a RISC machine with a condition code and in which only
9004 full-word operations are performed in registers. Let us assume that we
9005 can divide all insns into loads, stores, (integer) arithmetic
9006 operations, floating point operations, and branches.
9008 Here we will concern ourselves with determining the effect of an insn on
9009 the condition code and will limit ourselves to the following possible
9010 effects: The condition code can be set unpredictably (clobbered), not
9011 be changed, be set to agree with the results of the operation, or only
9012 changed if the item previously set into the condition code has been
9015 Here is part of a sample @file{md} file for such a machine:
9018 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
9020 (define_attr "cc" "clobber,unchanged,set,change0"
9021 (cond [(eq_attr "type" "load")
9022 (const_string "change0")
9023 (eq_attr "type" "store,branch")
9024 (const_string "unchanged")
9025 (eq_attr "type" "arith")
9026 (if_then_else (match_operand:SI 0 "" "")
9027 (const_string "set")
9028 (const_string "clobber"))]
9029 (const_string "clobber")))
9032 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
9033 (match_operand:SI 1 "general_operand" "r,m,r"))]
9039 [(set_attr "type" "arith,load,store")])
9042 Note that we assume in the above example that arithmetic operations
9043 performed on quantities smaller than a machine word clobber the condition
9044 code since they will set the condition code to a value corresponding to the
9050 @subsection Computing the Length of an Insn
9051 @cindex insn lengths, computing
9052 @cindex computing the length of an insn
9054 For many machines, multiple types of branch instructions are provided, each
9055 for different length branch displacements. In most cases, the assembler
9056 will choose the correct instruction to use. However, when the assembler
9057 cannot do so, GCC can when a special attribute, the @code{length}
9058 attribute, is defined. This attribute must be defined to have numeric
9059 values by specifying a null string in its @code{define_attr}.
9061 In the case of the @code{length} attribute, two additional forms of
9062 arithmetic terms are allowed in test expressions:
9065 @cindex @code{match_dup} and attributes
9066 @item (match_dup @var{n})
9067 This refers to the address of operand @var{n} of the current insn, which
9068 must be a @code{label_ref}.
9070 @cindex @code{pc} and attributes
9072 For non-branch instructions and backward branch instructions, this refers
9073 to the address of the current insn. But for forward branch instructions,
9074 this refers to the address of the next insn, because the length of the
9075 current insn is to be computed.
9078 @cindex @code{addr_vec}, length of
9079 @cindex @code{addr_diff_vec}, length of
9080 For normal insns, the length will be determined by value of the
9081 @code{length} attribute. In the case of @code{addr_vec} and
9082 @code{addr_diff_vec} insn patterns, the length is computed as
9083 the number of vectors multiplied by the size of each vector.
9085 Lengths are measured in addressable storage units (bytes).
9087 Note that it is possible to call functions via the @code{symbol_ref}
9088 mechanism to compute the length of an insn. However, if you use this
9089 mechanism you must provide dummy clauses to express the maximum length
9090 without using the function call. You can an example of this in the
9091 @code{pa} machine description for the @code{call_symref} pattern.
9093 The following macros can be used to refine the length computation:
9096 @findex ADJUST_INSN_LENGTH
9097 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
9098 If defined, modifies the length assigned to instruction @var{insn} as a
9099 function of the context in which it is used. @var{length} is an lvalue
9100 that contains the initially computed length of the insn and should be
9101 updated with the correct length of the insn.
9103 This macro will normally not be required. A case in which it is
9104 required is the ROMP@. On this machine, the size of an @code{addr_vec}
9105 insn must be increased by two to compensate for the fact that alignment
9109 @findex get_attr_length
9110 The routine that returns @code{get_attr_length} (the value of the
9111 @code{length} attribute) can be used by the output routine to
9112 determine the form of the branch instruction to be written, as the
9113 example below illustrates.
9115 As an example of the specification of variable-length branches, consider
9116 the IBM 360. If we adopt the convention that a register will be set to
9117 the starting address of a function, we can jump to labels within 4k of
9118 the start using a four-byte instruction. Otherwise, we need a six-byte
9119 sequence to load the address from memory and then branch to it.
9121 On such a machine, a pattern for a branch instruction might be specified
9127 (label_ref (match_operand 0 "" "")))]
9130 return (get_attr_length (insn) == 4
9131 ? "b %l0" : "l r15,=a(%l0); br r15");
9133 [(set (attr "length")
9134 (if_then_else (lt (match_dup 0) (const_int 4096))
9141 @node Constant Attributes
9142 @subsection Constant Attributes
9143 @cindex constant attributes
9145 A special form of @code{define_attr}, where the expression for the
9146 default value is a @code{const} expression, indicates an attribute that
9147 is constant for a given run of the compiler. Constant attributes may be
9148 used to specify which variety of processor is used. For example,
9151 (define_attr "cpu" "m88100,m88110,m88000"
9153 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
9154 (symbol_ref "TARGET_88110") (const_string "m88110")]
9155 (const_string "m88000"))))
9157 (define_attr "memory" "fast,slow"
9159 (if_then_else (symbol_ref "TARGET_FAST_MEM")
9160 (const_string "fast")
9161 (const_string "slow"))))
9164 The routine generated for constant attributes has no parameters as it
9165 does not depend on any particular insn. RTL expressions used to define
9166 the value of a constant attribute may use the @code{symbol_ref} form,
9167 but may not use either the @code{match_operand} form or @code{eq_attr}
9168 forms involving insn attributes.
9172 @node Mnemonic Attribute
9173 @subsection Mnemonic Attribute
9174 @cindex mnemonic attribute
9176 The @code{mnemonic} attribute is a string type attribute holding the
9177 instruction mnemonic for an insn alternative. The attribute values
9178 will automatically be generated by the machine description parser if
9179 there is an attribute definition in the md file:
9182 (define_attr "mnemonic" "unknown" (const_string "unknown"))
9185 The default value can be freely chosen as long as it does not collide
9186 with any of the instruction mnemonics. This value will be used
9187 whenever the machine description parser is not able to determine the
9188 mnemonic string. This might be the case for output templates
9189 containing more than a single instruction as in
9190 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
9192 The @code{mnemonic} attribute set is not generated automatically if the
9193 instruction string is generated via C code.
9195 An existing @code{mnemonic} attribute set in an insn definition will not
9196 be overriden by the md file parser. That way it is possible to
9197 manually set the instruction mnemonics for the cases where the md file
9198 parser fails to determine it automatically.
9200 The @code{mnemonic} attribute is useful for dealing with instruction
9201 specific properties in the pipeline description without defining
9202 additional insn attributes.
9205 (define_attr "ooo_expanded" ""
9206 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
9214 @subsection Delay Slot Scheduling
9215 @cindex delay slots, defining
9217 The insn attribute mechanism can be used to specify the requirements for
9218 delay slots, if any, on a target machine. An instruction is said to
9219 require a @dfn{delay slot} if some instructions that are physically
9220 after the instruction are executed as if they were located before it.
9221 Classic examples are branch and call instructions, which often execute
9222 the following instruction before the branch or call is performed.
9224 On some machines, conditional branch instructions can optionally
9225 @dfn{annul} instructions in the delay slot. This means that the
9226 instruction will not be executed for certain branch outcomes. Both
9227 instructions that annul if the branch is true and instructions that
9228 annul if the branch is false are supported.
9230 Delay slot scheduling differs from instruction scheduling in that
9231 determining whether an instruction needs a delay slot is dependent only
9232 on the type of instruction being generated, not on data flow between the
9233 instructions. See the next section for a discussion of data-dependent
9234 instruction scheduling.
9236 @findex define_delay
9237 The requirement of an insn needing one or more delay slots is indicated
9238 via the @code{define_delay} expression. It has the following form:
9241 (define_delay @var{test}
9242 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
9243 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
9247 @var{test} is an attribute test that indicates whether this
9248 @code{define_delay} applies to a particular insn. If so, the number of
9249 required delay slots is determined by the length of the vector specified
9250 as the second argument. An insn placed in delay slot @var{n} must
9251 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
9252 attribute test that specifies which insns may be annulled if the branch
9253 is true. Similarly, @var{annul-false-n} specifies which insns in the
9254 delay slot may be annulled if the branch is false. If annulling is not
9255 supported for that delay slot, @code{(nil)} should be coded.
9257 For example, in the common case where branch and call insns require
9258 a single delay slot, which may contain any insn other than a branch or
9259 call, the following would be placed in the @file{md} file:
9262 (define_delay (eq_attr "type" "branch,call")
9263 [(eq_attr "type" "!branch,call") (nil) (nil)])
9266 Multiple @code{define_delay} expressions may be specified. In this
9267 case, each such expression specifies different delay slot requirements
9268 and there must be no insn for which tests in two @code{define_delay}
9269 expressions are both true.
9271 For example, if we have a machine that requires one delay slot for branches
9272 but two for calls, no delay slot can contain a branch or call insn,
9273 and any valid insn in the delay slot for the branch can be annulled if the
9274 branch is true, we might represent this as follows:
9277 (define_delay (eq_attr "type" "branch")
9278 [(eq_attr "type" "!branch,call")
9279 (eq_attr "type" "!branch,call")
9282 (define_delay (eq_attr "type" "call")
9283 [(eq_attr "type" "!branch,call") (nil) (nil)
9284 (eq_attr "type" "!branch,call") (nil) (nil)])
9286 @c the above is *still* too long. --mew 4feb93
9290 @node Processor pipeline description
9291 @subsection Specifying processor pipeline description
9292 @cindex processor pipeline description
9293 @cindex processor functional units
9294 @cindex instruction latency time
9295 @cindex interlock delays
9296 @cindex data dependence delays
9297 @cindex reservation delays
9298 @cindex pipeline hazard recognizer
9299 @cindex automaton based pipeline description
9300 @cindex regular expressions
9301 @cindex deterministic finite state automaton
9302 @cindex automaton based scheduler
9306 To achieve better performance, most modern processors
9307 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
9308 processors) have many @dfn{functional units} on which several
9309 instructions can be executed simultaneously. An instruction starts
9310 execution if its issue conditions are satisfied. If not, the
9311 instruction is stalled until its conditions are satisfied. Such
9312 @dfn{interlock (pipeline) delay} causes interruption of the fetching
9313 of successor instructions (or demands nop instructions, e.g.@: for some
9316 There are two major kinds of interlock delays in modern processors.
9317 The first one is a data dependence delay determining @dfn{instruction
9318 latency time}. The instruction execution is not started until all
9319 source data have been evaluated by prior instructions (there are more
9320 complex cases when the instruction execution starts even when the data
9321 are not available but will be ready in given time after the
9322 instruction execution start). Taking the data dependence delays into
9323 account is simple. The data dependence (true, output, and
9324 anti-dependence) delay between two instructions is given by a
9325 constant. In most cases this approach is adequate. The second kind
9326 of interlock delays is a reservation delay. The reservation delay
9327 means that two instructions under execution will be in need of shared
9328 processors resources, i.e.@: buses, internal registers, and/or
9329 functional units, which are reserved for some time. Taking this kind
9330 of delay into account is complex especially for modern @acronym{RISC}
9333 The task of exploiting more processor parallelism is solved by an
9334 instruction scheduler. For a better solution to this problem, the
9335 instruction scheduler has to have an adequate description of the
9336 processor parallelism (or @dfn{pipeline description}). GCC
9337 machine descriptions describe processor parallelism and functional
9338 unit reservations for groups of instructions with the aid of
9339 @dfn{regular expressions}.
9341 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
9342 figure out the possibility of the instruction issue by the processor
9343 on a given simulated processor cycle. The pipeline hazard recognizer is
9344 automatically generated from the processor pipeline description. The
9345 pipeline hazard recognizer generated from the machine description
9346 is based on a deterministic finite state automaton (@acronym{DFA}):
9347 the instruction issue is possible if there is a transition from one
9348 automaton state to another one. This algorithm is very fast, and
9349 furthermore, its speed is not dependent on processor
9350 complexity@footnote{However, the size of the automaton depends on
9351 processor complexity. To limit this effect, machine descriptions
9352 can split orthogonal parts of the machine description among several
9353 automata: but then, since each of these must be stepped independently,
9354 this does cause a small decrease in the algorithm's performance.}.
9356 @cindex automaton based pipeline description
9357 The rest of this section describes the directives that constitute
9358 an automaton-based processor pipeline description. The order of
9359 these constructions within the machine description file is not
9362 @findex define_automaton
9363 @cindex pipeline hazard recognizer
9364 The following optional construction describes names of automata
9365 generated and used for the pipeline hazards recognition. Sometimes
9366 the generated finite state automaton used by the pipeline hazard
9367 recognizer is large. If we use more than one automaton and bind functional
9368 units to the automata, the total size of the automata is usually
9369 less than the size of the single automaton. If there is no one such
9370 construction, only one finite state automaton is generated.
9373 (define_automaton @var{automata-names})
9376 @var{automata-names} is a string giving names of the automata. The
9377 names are separated by commas. All the automata should have unique names.
9378 The automaton name is used in the constructions @code{define_cpu_unit} and
9379 @code{define_query_cpu_unit}.
9381 @findex define_cpu_unit
9382 @cindex processor functional units
9383 Each processor functional unit used in the description of instruction
9384 reservations should be described by the following construction.
9387 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
9390 @var{unit-names} is a string giving the names of the functional units
9391 separated by commas. Don't use name @samp{nothing}, it is reserved
9394 @var{automaton-name} is a string giving the name of the automaton with
9395 which the unit is bound. The automaton should be described in
9396 construction @code{define_automaton}. You should give
9397 @dfn{automaton-name}, if there is a defined automaton.
9399 The assignment of units to automata are constrained by the uses of the
9400 units in insn reservations. The most important constraint is: if a
9401 unit reservation is present on a particular cycle of an alternative
9402 for an insn reservation, then some unit from the same automaton must
9403 be present on the same cycle for the other alternatives of the insn
9404 reservation. The rest of the constraints are mentioned in the
9405 description of the subsequent constructions.
9407 @findex define_query_cpu_unit
9408 @cindex querying function unit reservations
9409 The following construction describes CPU functional units analogously
9410 to @code{define_cpu_unit}. The reservation of such units can be
9411 queried for an automaton state. The instruction scheduler never
9412 queries reservation of functional units for given automaton state. So
9413 as a rule, you don't need this construction. This construction could
9414 be used for future code generation goals (e.g.@: to generate
9415 @acronym{VLIW} insn templates).
9418 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
9421 @var{unit-names} is a string giving names of the functional units
9422 separated by commas.
9424 @var{automaton-name} is a string giving the name of the automaton with
9425 which the unit is bound.
9427 @findex define_insn_reservation
9428 @cindex instruction latency time
9429 @cindex regular expressions
9431 The following construction is the major one to describe pipeline
9432 characteristics of an instruction.
9435 (define_insn_reservation @var{insn-name} @var{default_latency}
9436 @var{condition} @var{regexp})
9439 @var{default_latency} is a number giving latency time of the
9440 instruction. There is an important difference between the old
9441 description and the automaton based pipeline description. The latency
9442 time is used for all dependencies when we use the old description. In
9443 the automaton based pipeline description, the given latency time is only
9444 used for true dependencies. The cost of anti-dependencies is always
9445 zero and the cost of output dependencies is the difference between
9446 latency times of the producing and consuming insns (if the difference
9447 is negative, the cost is considered to be zero). You can always
9448 change the default costs for any description by using the target hook
9449 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
9451 @var{insn-name} is a string giving the internal name of the insn. The
9452 internal names are used in constructions @code{define_bypass} and in
9453 the automaton description file generated for debugging. The internal
9454 name has nothing in common with the names in @code{define_insn}. It is a
9455 good practice to use insn classes described in the processor manual.
9457 @var{condition} defines what RTL insns are described by this
9458 construction. You should remember that you will be in trouble if
9459 @var{condition} for two or more different
9460 @code{define_insn_reservation} constructions is TRUE for an insn. In
9461 this case what reservation will be used for the insn is not defined.
9462 Such cases are not checked during generation of the pipeline hazards
9463 recognizer because in general recognizing that two conditions may have
9464 the same value is quite difficult (especially if the conditions
9465 contain @code{symbol_ref}). It is also not checked during the
9466 pipeline hazard recognizer work because it would slow down the
9467 recognizer considerably.
9469 @var{regexp} is a string describing the reservation of the cpu's functional
9470 units by the instruction. The reservations are described by a regular
9471 expression according to the following syntax:
9474 regexp = regexp "," oneof
9477 oneof = oneof "|" allof
9480 allof = allof "+" repeat
9483 repeat = element "*" number
9486 element = cpu_function_unit_name
9495 @samp{,} is used for describing the start of the next cycle in
9499 @samp{|} is used for describing a reservation described by the first
9500 regular expression @strong{or} a reservation described by the second
9501 regular expression @strong{or} etc.
9504 @samp{+} is used for describing a reservation described by the first
9505 regular expression @strong{and} a reservation described by the
9506 second regular expression @strong{and} etc.
9509 @samp{*} is used for convenience and simply means a sequence in which
9510 the regular expression are repeated @var{number} times with cycle
9511 advancing (see @samp{,}).
9514 @samp{cpu_function_unit_name} denotes reservation of the named
9518 @samp{reservation_name} --- see description of construction
9519 @samp{define_reservation}.
9522 @samp{nothing} denotes no unit reservations.
9525 @findex define_reservation
9526 Sometimes unit reservations for different insns contain common parts.
9527 In such case, you can simplify the pipeline description by describing
9528 the common part by the following construction
9531 (define_reservation @var{reservation-name} @var{regexp})
9534 @var{reservation-name} is a string giving name of @var{regexp}.
9535 Functional unit names and reservation names are in the same name
9536 space. So the reservation names should be different from the
9537 functional unit names and can not be the reserved name @samp{nothing}.
9539 @findex define_bypass
9540 @cindex instruction latency time
9542 The following construction is used to describe exceptions in the
9543 latency time for given instruction pair. This is so called bypasses.
9546 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
9550 @var{number} defines when the result generated by the instructions
9551 given in string @var{out_insn_names} will be ready for the
9552 instructions given in string @var{in_insn_names}. Each of these
9553 strings is a comma-separated list of filename-style globs and
9554 they refer to the names of @code{define_insn_reservation}s.
9557 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
9559 defines a bypass between instructions that start with
9560 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
9563 @var{guard} is an optional string giving the name of a C function which
9564 defines an additional guard for the bypass. The function will get the
9565 two insns as parameters. If the function returns zero the bypass will
9566 be ignored for this case. The additional guard is necessary to
9567 recognize complicated bypasses, e.g.@: when the consumer is only an address
9568 of insn @samp{store} (not a stored value).
9570 If there are more one bypass with the same output and input insns, the
9571 chosen bypass is the first bypass with a guard in description whose
9572 guard function returns nonzero. If there is no such bypass, then
9573 bypass without the guard function is chosen.
9575 @findex exclusion_set
9576 @findex presence_set
9577 @findex final_presence_set
9579 @findex final_absence_set
9582 The following five constructions are usually used to describe
9583 @acronym{VLIW} processors, or more precisely, to describe a placement
9584 of small instructions into @acronym{VLIW} instruction slots. They
9585 can be used for @acronym{RISC} processors, too.
9588 (exclusion_set @var{unit-names} @var{unit-names})
9589 (presence_set @var{unit-names} @var{patterns})
9590 (final_presence_set @var{unit-names} @var{patterns})
9591 (absence_set @var{unit-names} @var{patterns})
9592 (final_absence_set @var{unit-names} @var{patterns})
9595 @var{unit-names} is a string giving names of functional units
9596 separated by commas.
9598 @var{patterns} is a string giving patterns of functional units
9599 separated by comma. Currently pattern is one unit or units
9600 separated by white-spaces.
9602 The first construction (@samp{exclusion_set}) means that each
9603 functional unit in the first string can not be reserved simultaneously
9604 with a unit whose name is in the second string and vice versa. For
9605 example, the construction is useful for describing processors
9606 (e.g.@: some SPARC processors) with a fully pipelined floating point
9607 functional unit which can execute simultaneously only single floating
9608 point insns or only double floating point insns.
9610 The second construction (@samp{presence_set}) means that each
9611 functional unit in the first string can not be reserved unless at
9612 least one of pattern of units whose names are in the second string is
9613 reserved. This is an asymmetric relation. For example, it is useful
9614 for description that @acronym{VLIW} @samp{slot1} is reserved after
9615 @samp{slot0} reservation. We could describe it by the following
9619 (presence_set "slot1" "slot0")
9622 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
9623 reservation. In this case we could write
9626 (presence_set "slot1" "slot0 b0")
9629 The third construction (@samp{final_presence_set}) is analogous to
9630 @samp{presence_set}. The difference between them is when checking is
9631 done. When an instruction is issued in given automaton state
9632 reflecting all current and planned unit reservations, the automaton
9633 state is changed. The first state is a source state, the second one
9634 is a result state. Checking for @samp{presence_set} is done on the
9635 source state reservation, checking for @samp{final_presence_set} is
9636 done on the result reservation. This construction is useful to
9637 describe a reservation which is actually two subsequent reservations.
9638 For example, if we use
9641 (presence_set "slot1" "slot0")
9644 the following insn will be never issued (because @samp{slot1} requires
9645 @samp{slot0} which is absent in the source state).
9648 (define_reservation "insn_and_nop" "slot0 + slot1")
9651 but it can be issued if we use analogous @samp{final_presence_set}.
9653 The forth construction (@samp{absence_set}) means that each functional
9654 unit in the first string can be reserved only if each pattern of units
9655 whose names are in the second string is not reserved. This is an
9656 asymmetric relation (actually @samp{exclusion_set} is analogous to
9657 this one but it is symmetric). For example it might be useful in a
9658 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
9659 after either @samp{slot1} or @samp{slot2} have been reserved. This
9660 can be described as:
9663 (absence_set "slot0" "slot1, slot2")
9666 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
9667 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
9668 this case we could write
9671 (absence_set "slot2" "slot0 b0, slot1 b1")
9674 All functional units mentioned in a set should belong to the same
9677 The last construction (@samp{final_absence_set}) is analogous to
9678 @samp{absence_set} but checking is done on the result (state)
9679 reservation. See comments for @samp{final_presence_set}.
9681 @findex automata_option
9682 @cindex deterministic finite state automaton
9683 @cindex nondeterministic finite state automaton
9684 @cindex finite state automaton minimization
9685 You can control the generator of the pipeline hazard recognizer with
9686 the following construction.
9689 (automata_option @var{options})
9692 @var{options} is a string giving options which affect the generated
9693 code. Currently there are the following options:
9697 @dfn{no-minimization} makes no minimization of the automaton. This is
9698 only worth to do when we are debugging the description and need to
9699 look more accurately at reservations of states.
9702 @dfn{time} means printing time statistics about the generation of
9706 @dfn{stats} means printing statistics about the generated automata
9707 such as the number of DFA states, NDFA states and arcs.
9710 @dfn{v} means a generation of the file describing the result automata.
9711 The file has suffix @samp{.dfa} and can be used for the description
9712 verification and debugging.
9715 @dfn{w} means a generation of warning instead of error for
9716 non-critical errors.
9719 @dfn{no-comb-vect} prevents the automaton generator from generating
9720 two data structures and comparing them for space efficiency. Using
9721 a comb vector to represent transitions may be better, but it can be
9722 very expensive to construct. This option is useful if the build
9723 process spends an unacceptably long time in genautomata.
9726 @dfn{ndfa} makes nondeterministic finite state automata. This affects
9727 the treatment of operator @samp{|} in the regular expressions. The
9728 usual treatment of the operator is to try the first alternative and,
9729 if the reservation is not possible, the second alternative. The
9730 nondeterministic treatment means trying all alternatives, some of them
9731 may be rejected by reservations in the subsequent insns.
9734 @dfn{collapse-ndfa} modifies the behavior of the generator when
9735 producing an automaton. An additional state transition to collapse a
9736 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
9737 state is generated. It can be triggered by passing @code{const0_rtx} to
9738 state_transition. In such an automaton, cycle advance transitions are
9739 available only for these collapsed states. This option is useful for
9740 ports that want to use the @code{ndfa} option, but also want to use
9741 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
9744 @dfn{progress} means output of a progress bar showing how many states
9745 were generated so far for automaton being processed. This is useful
9746 during debugging a @acronym{DFA} description. If you see too many
9747 generated states, you could interrupt the generator of the pipeline
9748 hazard recognizer and try to figure out a reason for generation of the
9752 As an example, consider a superscalar @acronym{RISC} machine which can
9753 issue three insns (two integer insns and one floating point insn) on
9754 the cycle but can finish only two insns. To describe this, we define
9755 the following functional units.
9758 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
9759 (define_cpu_unit "port0, port1")
9762 All simple integer insns can be executed in any integer pipeline and
9763 their result is ready in two cycles. The simple integer insns are
9764 issued into the first pipeline unless it is reserved, otherwise they
9765 are issued into the second pipeline. Integer division and
9766 multiplication insns can be executed only in the second integer
9767 pipeline and their results are ready correspondingly in 9 and 4
9768 cycles. The integer division is not pipelined, i.e.@: the subsequent
9769 integer division insn can not be issued until the current division
9770 insn finished. Floating point insns are fully pipelined and their
9771 results are ready in 3 cycles. Where the result of a floating point
9772 insn is used by an integer insn, an additional delay of one cycle is
9773 incurred. To describe all of this we could specify
9776 (define_cpu_unit "div")
9778 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9779 "(i0_pipeline | i1_pipeline), (port0 | port1)")
9781 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
9782 "i1_pipeline, nothing*2, (port0 | port1)")
9784 (define_insn_reservation "div" 9 (eq_attr "type" "div")
9785 "i1_pipeline, div*7, div + (port0 | port1)")
9787 (define_insn_reservation "float" 3 (eq_attr "type" "float")
9788 "f_pipeline, nothing, (port0 | port1))
9790 (define_bypass 4 "float" "simple,mult,div")
9793 To simplify the description we could describe the following reservation
9796 (define_reservation "finish" "port0|port1")
9799 and use it in all @code{define_insn_reservation} as in the following
9803 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9804 "(i0_pipeline | i1_pipeline), finish")
9810 @node Conditional Execution
9811 @section Conditional Execution
9812 @cindex conditional execution
9815 A number of architectures provide for some form of conditional
9816 execution, or predication. The hallmark of this feature is the
9817 ability to nullify most of the instructions in the instruction set.
9818 When the instruction set is large and not entirely symmetric, it
9819 can be quite tedious to describe these forms directly in the
9820 @file{.md} file. An alternative is the @code{define_cond_exec} template.
9822 @findex define_cond_exec
9825 [@var{predicate-pattern}]
9827 "@var{output-template}"
9828 "@var{optional-insn-attribues}")
9831 @var{predicate-pattern} is the condition that must be true for the
9832 insn to be executed at runtime and should match a relational operator.
9833 One can use @code{match_operator} to match several relational operators
9834 at once. Any @code{match_operand} operands must have no more than one
9837 @var{condition} is a C expression that must be true for the generated
9840 @findex current_insn_predicate
9841 @var{output-template} is a string similar to the @code{define_insn}
9842 output template (@pxref{Output Template}), except that the @samp{*}
9843 and @samp{@@} special cases do not apply. This is only useful if the
9844 assembly text for the predicate is a simple prefix to the main insn.
9845 In order to handle the general case, there is a global variable
9846 @code{current_insn_predicate} that will contain the entire predicate
9847 if the current insn is predicated, and will otherwise be @code{NULL}.
9849 @var{optional-insn-attributes} is an optional vector of attributes that gets
9850 appended to the insn attributes of the produced cond_exec rtx. It can
9851 be used to add some distinguishing attribute to cond_exec rtxs produced
9852 that way. An example usage would be to use this attribute in conjunction
9853 with attributes on the main pattern to disable particular alternatives under
9856 When @code{define_cond_exec} is used, an implicit reference to
9857 the @code{predicable} instruction attribute is made.
9858 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
9859 exactly two elements in its @var{list-of-values}), with the possible
9860 values being @code{no} and @code{yes}. The default and all uses in
9861 the insns must be a simple constant, not a complex expressions. It
9862 may, however, depend on the alternative, by using a comma-separated
9863 list of values. If that is the case, the port should also define an
9864 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
9865 should also allow only @code{no} and @code{yes} as its values.
9867 For each @code{define_insn} for which the @code{predicable}
9868 attribute is true, a new @code{define_insn} pattern will be
9869 generated that matches a predicated version of the instruction.
9873 (define_insn "addsi"
9874 [(set (match_operand:SI 0 "register_operand" "r")
9875 (plus:SI (match_operand:SI 1 "register_operand" "r")
9876 (match_operand:SI 2 "register_operand" "r")))]
9881 [(ne (match_operand:CC 0 "register_operand" "c")
9888 generates a new pattern
9893 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
9894 (set (match_operand:SI 0 "register_operand" "r")
9895 (plus:SI (match_operand:SI 1 "register_operand" "r")
9896 (match_operand:SI 2 "register_operand" "r"))))]
9897 "(@var{test2}) && (@var{test1})"
9898 "(%3) add %2,%1,%0")
9904 @section RTL Templates Transformations
9905 @cindex define_subst
9907 For some hardware architectures there are common cases when the RTL
9908 templates for the instructions can be derived from the other RTL
9909 templates using simple transformations. E.g., @file{i386.md} contains
9910 an RTL template for the ordinary @code{sub} instruction---
9911 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
9912 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
9913 implemented by a single meta-template capable of generating a modified
9914 case based on the initial one:
9916 @findex define_subst
9918 (define_subst "@var{name}"
9919 [@var{input-template}]
9921 [@var{output-template}])
9923 @var{input-template} is a pattern describing the source RTL template,
9924 which will be transformed.
9926 @var{condition} is a C expression that is conjunct with the condition
9927 from the input-template to generate a condition to be used in the
9930 @var{output-template} is a pattern that will be used in the resulting
9933 @code{define_subst} mechanism is tightly coupled with the notion of the
9934 subst attribute (@pxref{Subst Iterators}). The use of
9935 @code{define_subst} is triggered by a reference to a subst attribute in
9936 the transforming RTL template. This reference initiates duplication of
9937 the source RTL template and substitution of the attributes with their
9938 values. The source RTL template is left unchanged, while the copy is
9939 transformed by @code{define_subst}. This transformation can fail in the
9940 case when the source RTL template is not matched against the
9941 input-template of the @code{define_subst}. In such case the copy is
9944 @code{define_subst} can be used only in @code{define_insn} and
9945 @code{define_expand}, it cannot be used in other expressions (e.g. in
9946 @code{define_insn_and_split}).
9949 * Define Subst Example:: Example of @code{define_subst} work.
9950 * Define Subst Pattern Matching:: Process of template comparison.
9951 * Define Subst Output Template:: Generation of output template.
9954 @node Define Subst Example
9955 @subsection @code{define_subst} Example
9956 @cindex define_subst
9958 To illustrate how @code{define_subst} works, let us examine a simple
9959 template transformation.
9961 Suppose there are two kinds of instructions: one that touches flags and
9962 the other that does not. The instructions of the second type could be
9963 generated with the following @code{define_subst}:
9966 (define_subst "add_clobber_subst"
9967 [(set (match_operand:SI 0 "" "")
9968 (match_operand:SI 1 "" ""))]
9972 (clobber (reg:CC FLAGS_REG))]
9975 This @code{define_subst} can be applied to any RTL pattern containing
9976 @code{set} of mode SI and generates a copy with clobber when it is
9979 Assume there is an RTL template for a @code{max} instruction to be used
9980 in @code{define_subst} mentioned above:
9983 (define_insn "maxsi"
9984 [(set (match_operand:SI 0 "register_operand" "=r")
9986 (match_operand:SI 1 "register_operand" "r")
9987 (match_operand:SI 2 "register_operand" "r")))]
9989 "max\t@{%2, %1, %0|%0, %1, %2@}"
9993 To mark the RTL template for @code{define_subst} application,
9994 subst-attributes are used. They should be declared in advance:
9997 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
10000 Here @samp{add_clobber_name} is the attribute name,
10001 @samp{add_clobber_subst} is the name of the corresponding
10002 @code{define_subst}, the third argument (@samp{_noclobber}) is the
10003 attribute value that would be substituted into the unchanged version of
10004 the source RTL template, and the last argument (@samp{_clobber}) is the
10005 value that would be substituted into the second, transformed,
10006 version of the RTL template.
10008 Once the subst-attribute has been defined, it should be used in RTL
10009 templates which need to be processed by the @code{define_subst}. So,
10010 the original RTL template should be changed:
10013 (define_insn "maxsi<add_clobber_name>"
10014 [(set (match_operand:SI 0 "register_operand" "=r")
10016 (match_operand:SI 1 "register_operand" "r")
10017 (match_operand:SI 2 "register_operand" "r")))]
10019 "max\t@{%2, %1, %0|%0, %1, %2@}"
10023 The result of the @code{define_subst} usage would look like the following:
10026 (define_insn "maxsi_noclobber"
10027 [(set (match_operand:SI 0 "register_operand" "=r")
10029 (match_operand:SI 1 "register_operand" "r")
10030 (match_operand:SI 2 "register_operand" "r")))]
10032 "max\t@{%2, %1, %0|%0, %1, %2@}"
10034 (define_insn "maxsi_clobber"
10035 [(set (match_operand:SI 0 "register_operand" "=r")
10037 (match_operand:SI 1 "register_operand" "r")
10038 (match_operand:SI 2 "register_operand" "r")))
10039 (clobber (reg:CC FLAGS_REG))]
10041 "max\t@{%2, %1, %0|%0, %1, %2@}"
10045 @node Define Subst Pattern Matching
10046 @subsection Pattern Matching in @code{define_subst}
10047 @cindex define_subst
10049 All expressions, allowed in @code{define_insn} or @code{define_expand},
10050 are allowed in the input-template of @code{define_subst}, except
10051 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
10052 meanings of expressions in the input-template were changed:
10054 @code{match_operand} matches any expression (possibly, a subtree in
10055 RTL-template), if modes of the @code{match_operand} and this expression
10056 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
10057 this expression is @code{match_dup}, @code{match_op_dup}. If the
10058 expression is @code{match_operand} too, and predicate of
10059 @code{match_operand} from the input pattern is not empty, then the
10060 predicates are compared. That can be used for more accurate filtering
10061 of accepted RTL-templates.
10063 @code{match_operator} matches common operators (like @code{plus},
10064 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
10065 @code{match_operator}s from the original pattern if the modes match and
10066 @code{match_operator} from the input pattern has the same number of
10067 operands as the operator from the original pattern.
10069 @node Define Subst Output Template
10070 @subsection Generation of output template in @code{define_subst}
10071 @cindex define_subst
10073 If all necessary checks for @code{define_subst} application pass, a new
10074 RTL-pattern, based on the output-template, is created to replace the old
10075 template. Like in input-patterns, meanings of some RTL expressions are
10076 changed when they are used in output-patterns of a @code{define_subst}.
10077 Thus, @code{match_dup} is used for copying the whole expression from the
10078 original pattern, which matched corresponding @code{match_operand} from
10081 @code{match_dup N} is used in the output template to be replaced with
10082 the expression from the original pattern, which matched
10083 @code{match_operand N} from the input pattern. As a consequence,
10084 @code{match_dup} cannot be used to point to @code{match_operand}s from
10085 the output pattern, it should always refer to a @code{match_operand}
10086 from the input pattern.
10088 In the output template one can refer to the expressions from the
10089 original pattern and create new ones. For instance, some operands could
10090 be added by means of standard @code{match_operand}.
10092 After replacing @code{match_dup} with some RTL-subtree from the original
10093 pattern, it could happen that several @code{match_operand}s in the
10094 output pattern have the same indexes. It is unknown, how many and what
10095 indexes would be used in the expression which would replace
10096 @code{match_dup}, so such conflicts in indexes are inevitable. To
10097 overcome this issue, @code{match_operands} and @code{match_operators},
10098 which were introduced into the output pattern, are renumerated when all
10099 @code{match_dup}s are replaced.
10101 Number of alternatives in @code{match_operand}s introduced into the
10102 output template @code{M} could differ from the number of alternatives in
10103 the original pattern @code{N}, so in the resultant pattern there would
10104 be @code{N*M} alternatives. Thus, constraints from the original pattern
10105 would be duplicated @code{N} times, constraints from the output pattern
10106 would be duplicated @code{M} times, producing all possible combinations.
10110 @node Constant Definitions
10111 @section Constant Definitions
10112 @cindex constant definitions
10113 @findex define_constants
10115 Using literal constants inside instruction patterns reduces legibility and
10116 can be a maintenance problem.
10118 To overcome this problem, you may use the @code{define_constants}
10119 expression. It contains a vector of name-value pairs. From that
10120 point on, wherever any of the names appears in the MD file, it is as
10121 if the corresponding value had been written instead. You may use
10122 @code{define_constants} multiple times; each appearance adds more
10123 constants to the table. It is an error to redefine a constant with
10126 To come back to the a29k load multiple example, instead of
10130 [(match_parallel 0 "load_multiple_operation"
10131 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10132 (match_operand:SI 2 "memory_operand" "m"))
10134 (clobber (reg:SI 179))])]
10142 (define_constants [
10150 [(match_parallel 0 "load_multiple_operation"
10151 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10152 (match_operand:SI 2 "memory_operand" "m"))
10153 (use (reg:SI R_CR))
10154 (clobber (reg:SI R_CR))])]
10159 The constants that are defined with a define_constant are also output
10160 in the insn-codes.h header file as #defines.
10162 @cindex enumerations
10163 @findex define_c_enum
10164 You can also use the machine description file to define enumerations.
10165 Like the constants defined by @code{define_constant}, these enumerations
10166 are visible to both the machine description file and the main C code.
10168 The syntax is as follows:
10171 (define_c_enum "@var{name}" [
10179 This definition causes the equivalent of the following C code to appear
10180 in @file{insn-constants.h}:
10187 @var{valuen} = @var{n}
10189 #define NUM_@var{cname}_VALUES (@var{n} + 1)
10192 where @var{cname} is the capitalized form of @var{name}.
10193 It also makes each @var{valuei} available in the machine description
10194 file, just as if it had been declared with:
10197 (define_constants [(@var{valuei} @var{i})])
10200 Each @var{valuei} is usually an upper-case identifier and usually
10201 begins with @var{cname}.
10203 You can split the enumeration definition into as many statements as
10204 you like. The above example is directly equivalent to:
10207 (define_c_enum "@var{name}" [@var{value0}])
10208 (define_c_enum "@var{name}" [@var{value1}])
10210 (define_c_enum "@var{name}" [@var{valuen}])
10213 Splitting the enumeration helps to improve the modularity of each
10214 individual @code{.md} file. For example, if a port defines its
10215 synchronization instructions in a separate @file{sync.md} file,
10216 it is convenient to define all synchronization-specific enumeration
10217 values in @file{sync.md} rather than in the main @file{.md} file.
10219 Some enumeration names have special significance to GCC:
10223 @findex unspec_volatile
10224 If an enumeration called @code{unspecv} is defined, GCC will use it
10225 when printing out @code{unspec_volatile} expressions. For example:
10228 (define_c_enum "unspecv" [
10233 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
10236 (unspec_volatile ... UNSPECV_BLOCKAGE)
10241 If an enumeration called @code{unspec} is defined, GCC will use
10242 it when printing out @code{unspec} expressions. GCC will also use
10243 it when printing out @code{unspec_volatile} expressions unless an
10244 @code{unspecv} enumeration is also defined. You can therefore
10245 decide whether to keep separate enumerations for volatile and
10246 non-volatile expressions or whether to use the same enumeration
10250 @findex define_enum
10251 @anchor{define_enum}
10252 Another way of defining an enumeration is to use @code{define_enum}:
10255 (define_enum "@var{name}" [
10263 This directive implies:
10266 (define_c_enum "@var{name}" [
10267 @var{cname}_@var{cvalue0}
10268 @var{cname}_@var{cvalue1}
10270 @var{cname}_@var{cvaluen}
10274 @findex define_enum_attr
10275 where @var{cvaluei} is the capitalized form of @var{valuei}.
10276 However, unlike @code{define_c_enum}, the enumerations defined
10277 by @code{define_enum} can be used in attribute specifications
10278 (@pxref{define_enum_attr}).
10283 @cindex iterators in @file{.md} files
10285 Ports often need to define similar patterns for more than one machine
10286 mode or for more than one rtx code. GCC provides some simple iterator
10287 facilities to make this process easier.
10290 * Mode Iterators:: Generating variations of patterns for different modes.
10291 * Code Iterators:: Doing the same for codes.
10292 * Int Iterators:: Doing the same for integers.
10293 * Subst Iterators:: Generating variations of patterns for define_subst.
10296 @node Mode Iterators
10297 @subsection Mode Iterators
10298 @cindex mode iterators in @file{.md} files
10300 Ports often need to define similar patterns for two or more different modes.
10305 If a processor has hardware support for both single and double
10306 floating-point arithmetic, the @code{SFmode} patterns tend to be
10307 very similar to the @code{DFmode} ones.
10310 If a port uses @code{SImode} pointers in one configuration and
10311 @code{DImode} pointers in another, it will usually have very similar
10312 @code{SImode} and @code{DImode} patterns for manipulating pointers.
10315 Mode iterators allow several patterns to be instantiated from one
10316 @file{.md} file template. They can be used with any type of
10317 rtx-based construct, such as a @code{define_insn},
10318 @code{define_split}, or @code{define_peephole2}.
10321 * Defining Mode Iterators:: Defining a new mode iterator.
10322 * Substitutions:: Combining mode iterators with substitutions
10323 * Examples:: Examples
10326 @node Defining Mode Iterators
10327 @subsubsection Defining Mode Iterators
10328 @findex define_mode_iterator
10330 The syntax for defining a mode iterator is:
10333 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
10336 This allows subsequent @file{.md} file constructs to use the mode suffix
10337 @code{:@var{name}}. Every construct that does so will be expanded
10338 @var{n} times, once with every use of @code{:@var{name}} replaced by
10339 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
10340 and so on. In the expansion for a particular @var{modei}, every
10341 C condition will also require that @var{condi} be true.
10346 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10349 defines a new mode suffix @code{:P}. Every construct that uses
10350 @code{:P} will be expanded twice, once with every @code{:P} replaced
10351 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
10352 The @code{:SI} version will only apply if @code{Pmode == SImode} and
10353 the @code{:DI} version will only apply if @code{Pmode == DImode}.
10355 As with other @file{.md} conditions, an empty string is treated
10356 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
10357 to @code{@var{mode}}. For example:
10360 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10363 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
10364 but that the @code{:SI} expansion has no such constraint.
10366 Iterators are applied in the order they are defined. This can be
10367 significant if two iterators are used in a construct that requires
10368 substitutions. @xref{Substitutions}.
10370 @node Substitutions
10371 @subsubsection Substitution in Mode Iterators
10372 @findex define_mode_attr
10374 If an @file{.md} file construct uses mode iterators, each version of the
10375 construct will often need slightly different strings or modes. For
10380 When a @code{define_expand} defines several @code{add@var{m}3} patterns
10381 (@pxref{Standard Names}), each expander will need to use the
10382 appropriate mode name for @var{m}.
10385 When a @code{define_insn} defines several instruction patterns,
10386 each instruction will often use a different assembler mnemonic.
10389 When a @code{define_insn} requires operands with different modes,
10390 using an iterator for one of the operand modes usually requires a specific
10391 mode for the other operand(s).
10394 GCC supports such variations through a system of ``mode attributes''.
10395 There are two standard attributes: @code{mode}, which is the name of
10396 the mode in lower case, and @code{MODE}, which is the same thing in
10397 upper case. You can define other attributes using:
10400 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
10403 where @var{name} is the name of the attribute and @var{valuei}
10404 is the value associated with @var{modei}.
10406 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
10407 each string and mode in the pattern for sequences of the form
10408 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
10409 mode attribute. If the attribute is defined for @var{mode}, the whole
10410 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
10413 For example, suppose an @file{.md} file has:
10416 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10417 (define_mode_attr load [(SI "lw") (DI "ld")])
10420 If one of the patterns that uses @code{:P} contains the string
10421 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
10422 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
10423 @code{"ld\t%0,%1"}.
10425 Here is an example of using an attribute for a mode:
10428 (define_mode_iterator LONG [SI DI])
10429 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
10430 (define_insn @dots{}
10431 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
10434 The @code{@var{iterator}:} prefix may be omitted, in which case the
10435 substitution will be attempted for every iterator expansion.
10438 @subsubsection Mode Iterator Examples
10440 Here is an example from the MIPS port. It defines the following
10441 modes and attributes (among others):
10444 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10445 (define_mode_attr d [(SI "") (DI "d")])
10448 and uses the following template to define both @code{subsi3}
10452 (define_insn "sub<mode>3"
10453 [(set (match_operand:GPR 0 "register_operand" "=d")
10454 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
10455 (match_operand:GPR 2 "register_operand" "d")))]
10457 "<d>subu\t%0,%1,%2"
10458 [(set_attr "type" "arith")
10459 (set_attr "mode" "<MODE>")])
10462 This is exactly equivalent to:
10465 (define_insn "subsi3"
10466 [(set (match_operand:SI 0 "register_operand" "=d")
10467 (minus:SI (match_operand:SI 1 "register_operand" "d")
10468 (match_operand:SI 2 "register_operand" "d")))]
10471 [(set_attr "type" "arith")
10472 (set_attr "mode" "SI")])
10474 (define_insn "subdi3"
10475 [(set (match_operand:DI 0 "register_operand" "=d")
10476 (minus:DI (match_operand:DI 1 "register_operand" "d")
10477 (match_operand:DI 2 "register_operand" "d")))]
10480 [(set_attr "type" "arith")
10481 (set_attr "mode" "DI")])
10484 @node Code Iterators
10485 @subsection Code Iterators
10486 @cindex code iterators in @file{.md} files
10487 @findex define_code_iterator
10488 @findex define_code_attr
10490 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
10495 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
10498 defines a pseudo rtx code @var{name} that can be instantiated as
10499 @var{codei} if condition @var{condi} is true. Each @var{codei}
10500 must have the same rtx format. @xref{RTL Classes}.
10502 As with mode iterators, each pattern that uses @var{name} will be
10503 expanded @var{n} times, once with all uses of @var{name} replaced by
10504 @var{code1}, once with all uses replaced by @var{code2}, and so on.
10505 @xref{Defining Mode Iterators}.
10507 It is possible to define attributes for codes as well as for modes.
10508 There are two standard code attributes: @code{code}, the name of the
10509 code in lower case, and @code{CODE}, the name of the code in upper case.
10510 Other attributes are defined using:
10513 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
10516 Here's an example of code iterators in action, taken from the MIPS port:
10519 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
10520 eq ne gt ge lt le gtu geu ltu leu])
10522 (define_expand "b<code>"
10524 (if_then_else (any_cond:CC (cc0)
10526 (label_ref (match_operand 0 ""))
10530 gen_conditional_branch (operands, <CODE>);
10535 This is equivalent to:
10538 (define_expand "bunordered"
10540 (if_then_else (unordered:CC (cc0)
10542 (label_ref (match_operand 0 ""))
10546 gen_conditional_branch (operands, UNORDERED);
10550 (define_expand "bordered"
10552 (if_then_else (ordered:CC (cc0)
10554 (label_ref (match_operand 0 ""))
10558 gen_conditional_branch (operands, ORDERED);
10565 @node Int Iterators
10566 @subsection Int Iterators
10567 @cindex int iterators in @file{.md} files
10568 @findex define_int_iterator
10569 @findex define_int_attr
10571 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
10576 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
10579 defines a pseudo integer constant @var{name} that can be instantiated as
10580 @var{inti} if condition @var{condi} is true. Each @var{int}
10581 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
10582 in only those rtx fields that have 'i' as the specifier. This means that
10583 each @var{int} has to be a constant defined using define_constant or
10586 As with mode and code iterators, each pattern that uses @var{name} will be
10587 expanded @var{n} times, once with all uses of @var{name} replaced by
10588 @var{int1}, once with all uses replaced by @var{int2}, and so on.
10589 @xref{Defining Mode Iterators}.
10591 It is possible to define attributes for ints as well as for codes and modes.
10592 Attributes are defined using:
10595 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
10598 Here's an example of int iterators in action, taken from the ARM port:
10601 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
10603 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
10605 (define_insn "neon_vq<absneg><mode>"
10606 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10607 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10608 (match_operand:SI 2 "immediate_operand" "i")]
10611 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10612 [(set_attr "type" "neon_vqneg_vqabs")]
10617 This is equivalent to:
10620 (define_insn "neon_vqabs<mode>"
10621 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10622 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10623 (match_operand:SI 2 "immediate_operand" "i")]
10626 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10627 [(set_attr "type" "neon_vqneg_vqabs")]
10630 (define_insn "neon_vqneg<mode>"
10631 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10632 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10633 (match_operand:SI 2 "immediate_operand" "i")]
10636 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10637 [(set_attr "type" "neon_vqneg_vqabs")]
10642 @node Subst Iterators
10643 @subsection Subst Iterators
10644 @cindex subst iterators in @file{.md} files
10645 @findex define_subst
10646 @findex define_subst_attr
10648 Subst iterators are special type of iterators with the following
10649 restrictions: they could not be declared explicitly, they always have
10650 only two values, and they do not have explicit dedicated name.
10651 Subst-iterators are triggered only when corresponding subst-attribute is
10652 used in RTL-pattern.
10654 Subst iterators transform templates in the following way: the templates
10655 are duplicated, the subst-attributes in these templates are replaced
10656 with the corresponding values, and a new attribute is implicitly added
10657 to the given @code{define_insn}/@code{define_expand}. The name of the
10658 added attribute matches the name of @code{define_subst}. Such
10659 attributes are declared implicitly, and it is not allowed to have a
10660 @code{define_attr} named as a @code{define_subst}.
10662 Each subst iterator is linked to a @code{define_subst}. It is declared
10663 implicitly by the first appearance of the corresponding
10664 @code{define_subst_attr}, and it is not allowed to define it explicitly.
10666 Declarations of subst-attributes have the following syntax:
10668 @findex define_subst_attr
10670 (define_subst_attr "@var{name}"
10672 "@var{no-subst-value}"
10673 "@var{subst-applied-value}")
10676 @var{name} is a string with which the given subst-attribute could be
10679 @var{subst-name} shows which @code{define_subst} should be applied to an
10680 RTL-template if the given subst-attribute is present in the
10683 @var{no-subst-value} is a value with which subst-attribute would be
10684 replaced in the first copy of the original RTL-template.
10686 @var{subst-applied-value} is a value with which subst-attribute would be
10687 replaced in the second copy of the original RTL-template.