1 @c Copyright (C) 1988-2020 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 A @code{define_insn} expression is used to define instruction patterns
109 to which insns may be matched. A @code{define_insn} expression contains
110 an incomplete RTL expression, with pieces to be filled in later, operand
111 constraints that restrict how the pieces can be filled in, and an output
112 template or C code to generate the assembler output.
114 A @code{define_insn} is an RTL expression containing four or five operands:
118 An optional name @var{n}. When a name is present, the compiler
119 automically generates a C++ function @samp{gen_@var{n}} that takes
120 the operands of the instruction as arguments and returns the instruction's
121 rtx pattern. The compiler also assigns the instruction a unique code
122 @samp{CODE_FOR_@var{n}}, with all such codes belonging to an enum
123 called @code{insn_code}.
125 These names serve one of two purposes. The first is to indicate that the
126 instruction performs a certain standard job for the RTL-generation
127 pass of the compiler, such as a move, an addition, or a conditional
128 jump. The second is to help the target generate certain target-specific
129 operations, such as when implementing target-specific intrinsic functions.
131 It is better to prefix target-specific names with the name of the
132 target, to avoid any clash with current or future standard names.
134 The absence of a name is indicated by writing an empty string
135 where the name should go. Nameless instruction patterns are never
136 used for generating RTL code, but they may permit several simpler insns
137 to be combined later on.
139 For the purpose of debugging the compiler, you may also specify a
140 name beginning with the @samp{*} character. Such a name is used only
141 for identifying the instruction in RTL dumps; it is equivalent to having
142 a nameless pattern for all other purposes. Names beginning with the
143 @samp{*} character are not required to be unique.
145 The name may also have the form @samp{@@@var{n}}. This has the same
146 effect as a name @samp{@var{n}}, but in addition tells the compiler to
147 generate further helper functions; see @ref{Parameterized Names} for details.
150 The @dfn{RTL template}: This is a vector of incomplete RTL expressions
151 which describe the semantics of the instruction (@pxref{RTL Template}).
152 It is incomplete because it may contain @code{match_operand},
153 @code{match_operator}, and @code{match_dup} expressions that stand for
154 operands of the instruction.
156 If the vector has multiple elements, the RTL template is treated as a
157 @code{parallel} expression.
160 @cindex pattern conditions
161 @cindex conditions, in patterns
162 The condition: This is a string which contains a C expression. When the
163 compiler attempts to match RTL against a pattern, the condition is
164 evaluated. If the condition evaluates to @code{true}, the match is
165 permitted. The condition may be an empty string, which is treated
166 as always @code{true}.
168 @cindex named patterns and conditions
169 For a named pattern, the condition may not depend on the data in the
170 insn being matched, but only the target-machine-type flags. The compiler
171 needs to test these conditions during initialization in order to learn
172 exactly which named instructions are available in a particular run.
175 For nameless patterns, the condition is applied only when matching an
176 individual insn, and only after the insn has matched the pattern's
177 recognition template. The insn's operands may be found in the vector
180 An instruction condition cannot become more restrictive as compilation
181 progresses. If the condition accepts a particular RTL instruction at
182 one stage of compilation, it must continue to accept that instruction
183 until the final pass. For example, @samp{!reload_completed} and
184 @samp{can_create_pseudo_p ()} are both invalid instruction conditions,
185 because they are true during the earlier RTL passes and false during
186 the later ones. For the same reason, if a condition accepts an
187 instruction before register allocation, it cannot later try to control
188 register allocation by excluding certain register or value combinations.
190 Although a condition cannot become more restrictive as compilation
191 progresses, the condition for a nameless pattern @emph{can} become
192 more permissive. For example, a nameless instruction can require
193 @samp{reload_completed} to be true, in which case it only matches
194 after register allocation.
197 The @dfn{output template} or @dfn{output statement}: This is either
198 a string, or a fragment of C code which returns a string.
200 When simple substitution isn't general enough, you can specify a piece
201 of C code to compute the output. @xref{Output Statement}.
204 The @dfn{insn attributes}: This is an optional vector containing the values of
205 attributes for insns matching this pattern (@pxref{Insn Attributes}).
209 @section Example of @code{define_insn}
210 @cindex @code{define_insn} example
212 Here is an example of an instruction pattern, taken from the machine
213 description for the 68000/68020.
218 (match_operand:SI 0 "general_operand" "rm"))]
222 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
224 return \"cmpl #0,%0\";
229 This can also be written using braced strings:
234 (match_operand:SI 0 "general_operand" "rm"))]
237 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
243 This describes an instruction which sets the condition codes based on the
244 value of a general operand. It has no condition, so any insn with an RTL
245 description of the form shown may be matched to this pattern. The name
246 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL
247 generation pass that, when it is necessary to test such a value, an insn
248 to do so can be constructed using this pattern.
250 The output control string is a piece of C code which chooses which
251 output template to return based on the kind of operand and the specific
252 type of CPU for which code is being generated.
254 @samp{"rm"} is an operand constraint. Its meaning is explained below.
257 @section RTL Template
258 @cindex RTL insn template
259 @cindex generating insns
260 @cindex insns, generating
261 @cindex recognizing insns
262 @cindex insns, recognizing
264 The RTL template is used to define which insns match the particular pattern
265 and how to find their operands. For named patterns, the RTL template also
266 says how to construct an insn from specified operands.
268 Construction involves substituting specified operands into a copy of the
269 template. Matching involves determining the values that serve as the
270 operands in the insn being matched. Both of these activities are
271 controlled by special expression types that direct matching and
272 substitution of the operands.
275 @findex match_operand
276 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
277 This expression is a placeholder for operand number @var{n} of
278 the insn. When constructing an insn, operand number @var{n}
279 will be substituted at this point. When matching an insn, whatever
280 appears at this position in the insn will be taken as operand
281 number @var{n}; but it must satisfy @var{predicate} or this instruction
282 pattern will not match at all.
284 Operand numbers must be chosen consecutively counting from zero in
285 each instruction pattern. There may be only one @code{match_operand}
286 expression in the pattern for each operand number. Usually operands
287 are numbered in the order of appearance in @code{match_operand}
288 expressions. In the case of a @code{define_expand}, any operand numbers
289 used only in @code{match_dup} expressions have higher values than all
290 other operand numbers.
292 @var{predicate} is a string that is the name of a function that
293 accepts two arguments, an expression and a machine mode.
294 @xref{Predicates}. During matching, the function will be called with
295 the putative operand as the expression and @var{m} as the mode
296 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
297 which normally causes @var{predicate} to accept any mode). If it
298 returns zero, this instruction pattern fails to match.
299 @var{predicate} may be an empty string; then it means no test is to be
300 done on the operand, so anything which occurs in this position is
303 Most of the time, @var{predicate} will reject modes other than @var{m}---but
304 not always. For example, the predicate @code{address_operand} uses
305 @var{m} as the mode of memory ref that the address should be valid for.
306 Many predicates accept @code{const_int} nodes even though their mode is
309 @var{constraint} controls reloading and the choice of the best register
310 class to use for a value, as explained later (@pxref{Constraints}).
311 If the constraint would be an empty string, it can be omitted.
313 People are often unclear on the difference between the constraint and the
314 predicate. The predicate helps decide whether a given insn matches the
315 pattern. The constraint plays no role in this decision; instead, it
316 controls various decisions in the case of an insn which does match.
318 @findex match_scratch
319 @item (match_scratch:@var{m} @var{n} @var{constraint})
320 This expression is also a placeholder for operand number @var{n}
321 and indicates that operand must be a @code{scratch} or @code{reg}
324 When matching patterns, this is equivalent to
327 (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint})
330 but, when generating RTL, it produces a (@code{scratch}:@var{m})
333 If the last few expressions in a @code{parallel} are @code{clobber}
334 expressions whose operands are either a hard register or
335 @code{match_scratch}, the combiner can add or delete them when
336 necessary. @xref{Side Effects}.
339 @item (match_dup @var{n})
340 This expression is also a placeholder for operand number @var{n}.
341 It is used when the operand needs to appear more than once in the
344 In construction, @code{match_dup} acts just like @code{match_operand}:
345 the operand is substituted into the insn being constructed. But in
346 matching, @code{match_dup} behaves differently. It assumes that operand
347 number @var{n} has already been determined by a @code{match_operand}
348 appearing earlier in the recognition template, and it matches only an
349 identical-looking expression.
351 Note that @code{match_dup} should not be used to tell the compiler that
352 a particular register is being used for two operands (example:
353 @code{add} that adds one register to another; the second register is
354 both an input operand and the output operand). Use a matching
355 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
356 operand is used in two places in the template, such as an instruction
357 that computes both a quotient and a remainder, where the opcode takes
358 two input operands but the RTL template has to refer to each of those
359 twice; once for the quotient pattern and once for the remainder pattern.
361 @findex match_operator
362 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
363 This pattern is a kind of placeholder for a variable RTL expression
366 When constructing an insn, it stands for an RTL expression whose
367 expression code is taken from that of operand @var{n}, and whose
368 operands are constructed from the patterns @var{operands}.
370 When matching an expression, it matches an expression if the function
371 @var{predicate} returns nonzero on that expression @emph{and} the
372 patterns @var{operands} match the operands of the expression.
374 Suppose that the function @code{commutative_operator} is defined as
375 follows, to match any expression whose operator is one of the
376 commutative arithmetic operators of RTL and whose mode is @var{mode}:
380 commutative_integer_operator (x, mode)
384 enum rtx_code code = GET_CODE (x);
385 if (GET_MODE (x) != mode)
387 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
388 || code == EQ || code == NE);
392 Then the following pattern will match any RTL expression consisting
393 of a commutative operator applied to two general operands:
396 (match_operator:SI 3 "commutative_operator"
397 [(match_operand:SI 1 "general_operand" "g")
398 (match_operand:SI 2 "general_operand" "g")])
401 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
402 because the expressions to be matched all contain two operands.
404 When this pattern does match, the two operands of the commutative
405 operator are recorded as operands 1 and 2 of the insn. (This is done
406 by the two instances of @code{match_operand}.) Operand 3 of the insn
407 will be the entire commutative expression: use @code{GET_CODE
408 (operands[3])} to see which commutative operator was used.
410 The machine mode @var{m} of @code{match_operator} works like that of
411 @code{match_operand}: it is passed as the second argument to the
412 predicate function, and that function is solely responsible for
413 deciding whether the expression to be matched ``has'' that mode.
415 When constructing an insn, argument 3 of the gen-function will specify
416 the operation (i.e.@: the expression code) for the expression to be
417 made. It should be an RTL expression, whose expression code is copied
418 into a new expression whose operands are arguments 1 and 2 of the
419 gen-function. The subexpressions of argument 3 are not used;
420 only its expression code matters.
422 When @code{match_operator} is used in a pattern for matching an insn,
423 it usually best if the operand number of the @code{match_operator}
424 is higher than that of the actual operands of the insn. This improves
425 register allocation because the register allocator often looks at
426 operands 1 and 2 of insns to see if it can do register tying.
428 There is no way to specify constraints in @code{match_operator}. The
429 operand of the insn which corresponds to the @code{match_operator}
430 never has any constraints because it is never reloaded as a whole.
431 However, if parts of its @var{operands} are matched by
432 @code{match_operand} patterns, those parts may have constraints of
436 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
437 Like @code{match_dup}, except that it applies to operators instead of
438 operands. When constructing an insn, operand number @var{n} will be
439 substituted at this point. But in matching, @code{match_op_dup} behaves
440 differently. It assumes that operand number @var{n} has already been
441 determined by a @code{match_operator} appearing earlier in the
442 recognition template, and it matches only an identical-looking
445 @findex match_parallel
446 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
447 This pattern is a placeholder for an insn that consists of a
448 @code{parallel} expression with a variable number of elements. This
449 expression should only appear at the top level of an insn pattern.
451 When constructing an insn, operand number @var{n} will be substituted at
452 this point. When matching an insn, it matches if the body of the insn
453 is a @code{parallel} expression with at least as many elements as the
454 vector of @var{subpat} expressions in the @code{match_parallel}, if each
455 @var{subpat} matches the corresponding element of the @code{parallel},
456 @emph{and} the function @var{predicate} returns nonzero on the
457 @code{parallel} that is the body of the insn. It is the responsibility
458 of the predicate to validate elements of the @code{parallel} beyond
459 those listed in the @code{match_parallel}.
461 A typical use of @code{match_parallel} is to match load and store
462 multiple expressions, which can contain a variable number of elements
463 in a @code{parallel}. For example,
467 [(match_parallel 0 "load_multiple_operation"
468 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
469 (match_operand:SI 2 "memory_operand" "m"))
471 (clobber (reg:SI 179))])]
476 This example comes from @file{a29k.md}. The function
477 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
478 that subsequent elements in the @code{parallel} are the same as the
479 @code{set} in the pattern, except that they are referencing subsequent
480 registers and memory locations.
482 An insn that matches this pattern might look like:
486 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
488 (clobber (reg:SI 179))
490 (mem:SI (plus:SI (reg:SI 100)
493 (mem:SI (plus:SI (reg:SI 100)
497 @findex match_par_dup
498 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
499 Like @code{match_op_dup}, but for @code{match_parallel} instead of
500 @code{match_operator}.
504 @node Output Template
505 @section Output Templates and Operand Substitution
506 @cindex output templates
507 @cindex operand substitution
509 @cindex @samp{%} in template
511 The @dfn{output template} is a string which specifies how to output the
512 assembler code for an instruction pattern. Most of the template is a
513 fixed string which is output literally. The character @samp{%} is used
514 to specify where to substitute an operand; it can also be used to
515 identify places where different variants of the assembler require
518 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
519 operand @var{n} at that point in the string.
521 @samp{%} followed by a letter and a digit says to output an operand in an
522 alternate fashion. Four letters have standard, built-in meanings described
523 below. The machine description macro @code{PRINT_OPERAND} can define
524 additional letters with nonstandard meanings.
526 @samp{%c@var{digit}} can be used to substitute an operand that is a
527 constant value without the syntax that normally indicates an immediate
530 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
531 the constant is negated before printing.
533 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
534 memory reference, with the actual operand treated as the address. This may
535 be useful when outputting a ``load address'' instruction, because often the
536 assembler syntax for such an instruction requires you to write the operand
537 as if it were a memory reference.
539 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
542 @samp{%=} outputs a number which is unique to each instruction in the
543 entire compilation. This is useful for making local labels to be
544 referred to more than once in a single template that generates multiple
545 assembler instructions.
547 @samp{%} followed by a punctuation character specifies a substitution that
548 does not use an operand. Only one case is standard: @samp{%%} outputs a
549 @samp{%} into the assembler code. Other nonstandard cases can be
550 defined in the @code{PRINT_OPERAND} macro. You must also define
551 which punctuation characters are valid with the
552 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
556 The template may generate multiple assembler instructions. Write the text
557 for the instructions, with @samp{\;} between them.
559 @cindex matching operands
560 When the RTL contains two operands which are required by constraint to match
561 each other, the output template must refer only to the lower-numbered operand.
562 Matching operands are not always identical, and the rest of the compiler
563 arranges to put the proper RTL expression for printing into the lower-numbered
566 One use of nonstandard letters or punctuation following @samp{%} is to
567 distinguish between different assembler languages for the same machine; for
568 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
569 requires periods in most opcode names, while MIT syntax does not. For
570 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
571 syntax. The same file of patterns is used for both kinds of output syntax,
572 but the character sequence @samp{%.} is used in each place where Motorola
573 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
574 defines the sequence to output a period; the macro for MIT syntax defines
577 @cindex @code{#} in template
578 As a special case, a template consisting of the single character @code{#}
579 instructs the compiler to first split the insn, and then output the
580 resulting instructions separately. This helps eliminate redundancy in the
581 output templates. If you have a @code{define_insn} that needs to emit
582 multiple assembler instructions, and there is a matching @code{define_split}
583 already defined, then you can simply use @code{#} as the output template
584 instead of writing an output template that emits the multiple assembler
587 Note that @code{#} only has an effect while generating assembly code;
588 it does not affect whether a split occurs earlier. An associated
589 @code{define_split} must exist and it must be suitable for use after
592 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
593 of the form @samp{@{option0|option1|option2@}} in the templates. These
594 describe multiple variants of assembler language syntax.
595 @xref{Instruction Output}.
597 @node Output Statement
598 @section C Statements for Assembler Output
599 @cindex output statements
600 @cindex C statements for assembler output
601 @cindex generating assembler output
603 Often a single fixed template string cannot produce correct and efficient
604 assembler code for all the cases that are recognized by a single
605 instruction pattern. For example, the opcodes may depend on the kinds of
606 operands; or some unfortunate combinations of operands may require extra
607 machine instructions.
609 If the output control string starts with a @samp{@@}, then it is actually
610 a series of templates, each on a separate line. (Blank lines and
611 leading spaces and tabs are ignored.) The templates correspond to the
612 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
613 if a target machine has a two-address add instruction @samp{addr} to add
614 into a register and another @samp{addm} to add a register to memory, you
615 might write this pattern:
618 (define_insn "addsi3"
619 [(set (match_operand:SI 0 "general_operand" "=r,m")
620 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
621 (match_operand:SI 2 "general_operand" "g,r")))]
628 @cindex @code{*} in template
629 @cindex asterisk in template
630 If the output control string starts with a @samp{*}, then it is not an
631 output template but rather a piece of C program that should compute a
632 template. It should execute a @code{return} statement to return the
633 template-string you want. Most such templates use C string literals, which
634 require doublequote characters to delimit them. To include these
635 doublequote characters in the string, prefix each one with @samp{\}.
637 If the output control string is written as a brace block instead of a
638 double-quoted string, it is automatically assumed to be C code. In that
639 case, it is not necessary to put in a leading asterisk, or to escape the
640 doublequotes surrounding C string literals.
642 The operands may be found in the array @code{operands}, whose C data type
645 It is very common to select different ways of generating assembler code
646 based on whether an immediate operand is within a certain range. Be
647 careful when doing this, because the result of @code{INTVAL} is an
648 integer on the host machine. If the host machine has more bits in an
649 @code{int} than the target machine has in the mode in which the constant
650 will be used, then some of the bits you get from @code{INTVAL} will be
651 superfluous. For proper results, you must carefully disregard the
652 values of those bits.
654 @findex output_asm_insn
655 It is possible to output an assembler instruction and then go on to output
656 or compute more of them, using the subroutine @code{output_asm_insn}. This
657 receives two arguments: a template-string and a vector of operands. The
658 vector may be @code{operands}, or it may be another array of @code{rtx}
659 that you declare locally and initialize yourself.
661 @findex which_alternative
662 When an insn pattern has multiple alternatives in its constraints, often
663 the appearance of the assembler code is determined mostly by which alternative
664 was matched. When this is so, the C code can test the variable
665 @code{which_alternative}, which is the ordinal number of the alternative
666 that was actually satisfied (0 for the first, 1 for the second alternative,
669 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
670 for registers and @samp{clrmem} for memory locations. Here is how
671 a pattern could use @code{which_alternative} to choose between them:
675 [(set (match_operand:SI 0 "general_operand" "=r,m")
679 return (which_alternative == 0
680 ? "clrreg %0" : "clrmem %0");
684 The example above, where the assembler code to generate was
685 @emph{solely} determined by the alternative, could also have been specified
686 as follows, having the output control string start with a @samp{@@}:
691 [(set (match_operand:SI 0 "general_operand" "=r,m")
700 If you just need a little bit of C code in one (or a few) alternatives,
701 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
706 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
711 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
719 @cindex operand predicates
720 @cindex operator predicates
722 A predicate determines whether a @code{match_operand} or
723 @code{match_operator} expression matches, and therefore whether the
724 surrounding instruction pattern will be used for that combination of
725 operands. GCC has a number of machine-independent predicates, and you
726 can define machine-specific predicates as needed. By convention,
727 predicates used with @code{match_operand} have names that end in
728 @samp{_operand}, and those used with @code{match_operator} have names
729 that end in @samp{_operator}.
731 All predicates are boolean functions (in the mathematical sense) of
732 two arguments: the RTL expression that is being considered at that
733 position in the instruction pattern, and the machine mode that the
734 @code{match_operand} or @code{match_operator} specifies. In this
735 section, the first argument is called @var{op} and the second argument
736 @var{mode}. Predicates can be called from C as ordinary two-argument
737 functions; this can be useful in output templates or other
738 machine-specific code.
740 Operand predicates can allow operands that are not actually acceptable
741 to the hardware, as long as the constraints give reload the ability to
742 fix them up (@pxref{Constraints}). However, GCC will usually generate
743 better code if the predicates specify the requirements of the machine
744 instructions as closely as possible. Reload cannot fix up operands
745 that must be constants (``immediate operands''); you must use a
746 predicate that allows only constants, or else enforce the requirement
747 in the extra condition.
749 @cindex predicates and machine modes
750 @cindex normal predicates
751 @cindex special predicates
752 Most predicates handle their @var{mode} argument in a uniform manner.
753 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
754 any mode. If @var{mode} is anything else, then @var{op} must have the
755 same mode, unless @var{op} is a @code{CONST_INT} or integer
756 @code{CONST_DOUBLE}. These RTL expressions always have
757 @code{VOIDmode}, so it would be counterproductive to check that their
758 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
759 integer @code{CONST_DOUBLE} check that the value stored in the
760 constant will fit in the requested mode.
762 Predicates with this behavior are called @dfn{normal}.
763 @command{genrecog} can optimize the instruction recognizer based on
764 knowledge of how normal predicates treat modes. It can also diagnose
765 certain kinds of common errors in the use of normal predicates; for
766 instance, it is almost always an error to use a normal predicate
767 without specifying a mode.
769 Predicates that do something different with their @var{mode} argument
770 are called @dfn{special}. The generic predicates
771 @code{address_operand} and @code{pmode_register_operand} are special
772 predicates. @command{genrecog} does not do any optimizations or
773 diagnosis when special predicates are used.
776 * Machine-Independent Predicates:: Predicates available to all back ends.
777 * Defining Predicates:: How to write machine-specific predicate
781 @node Machine-Independent Predicates
782 @subsection Machine-Independent Predicates
783 @cindex machine-independent predicates
784 @cindex generic predicates
786 These are the generic predicates available to all back ends. They are
787 defined in @file{recog.c}. The first category of predicates allow
788 only constant, or @dfn{immediate}, operands.
790 @defun immediate_operand
791 This predicate allows any sort of constant that fits in @var{mode}.
792 It is an appropriate choice for instructions that take operands that
796 @defun const_int_operand
797 This predicate allows any @code{CONST_INT} expression that fits in
798 @var{mode}. It is an appropriate choice for an immediate operand that
799 does not allow a symbol or label.
802 @defun const_double_operand
803 This predicate accepts any @code{CONST_DOUBLE} expression that has
804 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
805 accept @code{CONST_INT}. It is intended for immediate floating point
810 The second category of predicates allow only some kind of machine
813 @defun register_operand
814 This predicate allows any @code{REG} or @code{SUBREG} expression that
815 is valid for @var{mode}. It is often suitable for arithmetic
816 instruction operands on a RISC machine.
819 @defun pmode_register_operand
820 This is a slight variant on @code{register_operand} which works around
821 a limitation in the machine-description reader.
824 (match_operand @var{n} "pmode_register_operand" @var{constraint})
831 (match_operand:P @var{n} "register_operand" @var{constraint})
835 would mean, if the machine-description reader accepted @samp{:P}
836 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
837 alias for some other mode, and might vary with machine-specific
838 options. @xref{Misc}.
841 @defun scratch_operand
842 This predicate allows hard registers and @code{SCRATCH} expressions,
843 but not pseudo-registers. It is used internally by @code{match_scratch};
844 it should not be used directly.
848 The third category of predicates allow only some kind of memory reference.
850 @defun memory_operand
851 This predicate allows any valid reference to a quantity of mode
852 @var{mode} in memory, as determined by the weak form of
853 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
856 @defun address_operand
857 This predicate is a little unusual; it allows any operand that is a
858 valid expression for the @emph{address} of a quantity of mode
859 @var{mode}, again determined by the weak form of
860 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
861 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
862 @code{memory_operand}, then @var{exp} is acceptable to
863 @code{address_operand}. Note that @var{exp} does not necessarily have
867 @defun indirect_operand
868 This is a stricter form of @code{memory_operand} which allows only
869 memory references with a @code{general_operand} as the address
870 expression. New uses of this predicate are discouraged, because
871 @code{general_operand} is very permissive, so it's hard to tell what
872 an @code{indirect_operand} does or does not allow. If a target has
873 different requirements for memory operands for different instructions,
874 it is better to define target-specific predicates which enforce the
875 hardware's requirements explicitly.
879 This predicate allows a memory reference suitable for pushing a value
880 onto the stack. This will be a @code{MEM} which refers to
881 @code{stack_pointer_rtx}, with a side effect in its address expression
882 (@pxref{Incdec}); which one is determined by the
883 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
887 This predicate allows a memory reference suitable for popping a value
888 off the stack. Again, this will be a @code{MEM} referring to
889 @code{stack_pointer_rtx}, with a side effect in its address
890 expression. However, this time @code{STACK_POP_CODE} is expected.
894 The fourth category of predicates allow some combination of the above
897 @defun nonmemory_operand
898 This predicate allows any immediate or register operand valid for @var{mode}.
901 @defun nonimmediate_operand
902 This predicate allows any register or memory operand valid for @var{mode}.
905 @defun general_operand
906 This predicate allows any immediate, register, or memory operand
907 valid for @var{mode}.
911 Finally, there are two generic operator predicates.
913 @defun comparison_operator
914 This predicate matches any expression which performs an arithmetic
915 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
919 @defun ordered_comparison_operator
920 This predicate matches any expression which performs an arithmetic
921 comparison in @var{mode} and whose expression code is valid for integer
922 modes; that is, the expression code will be one of @code{eq}, @code{ne},
923 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
924 @code{ge}, @code{geu}.
927 @node Defining Predicates
928 @subsection Defining Machine-Specific Predicates
929 @cindex defining predicates
930 @findex define_predicate
931 @findex define_special_predicate
933 Many machines have requirements for their operands that cannot be
934 expressed precisely using the generic predicates. You can define
935 additional predicates using @code{define_predicate} and
936 @code{define_special_predicate} expressions. These expressions have
941 The name of the predicate, as it will be referred to in
942 @code{match_operand} or @code{match_operator} expressions.
945 An RTL expression which evaluates to true if the predicate allows the
946 operand @var{op}, false if it does not. This expression can only use
947 the following RTL codes:
951 When written inside a predicate expression, a @code{MATCH_OPERAND}
952 expression evaluates to true if the predicate it names would allow
953 @var{op}. The operand number and constraint are ignored. Due to
954 limitations in @command{genrecog}, you can only refer to generic
955 predicates and predicates that have already been defined.
958 This expression evaluates to true if @var{op} or a specified
959 subexpression of @var{op} has one of a given list of RTX codes.
961 The first operand of this expression is a string constant containing a
962 comma-separated list of RTX code names (in lower case). These are the
963 codes for which the @code{MATCH_CODE} will be true.
965 The second operand is a string constant which indicates what
966 subexpression of @var{op} to examine. If it is absent or the empty
967 string, @var{op} itself is examined. Otherwise, the string constant
968 must be a sequence of digits and/or lowercase letters. Each character
969 indicates a subexpression to extract from the current expression; for
970 the first character this is @var{op}, for the second and subsequent
971 characters it is the result of the previous character. A digit
972 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
973 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
974 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
975 @code{MATCH_CODE} then examines the RTX code of the subexpression
976 extracted by the complete string. It is not possible to extract
977 components of an @code{rtvec} that is not at position 0 within its RTX
981 This expression has one operand, a string constant containing a C
982 expression. The predicate's arguments, @var{op} and @var{mode}, are
983 available with those names in the C expression. The @code{MATCH_TEST}
984 evaluates to true if the C expression evaluates to a nonzero value.
985 @code{MATCH_TEST} expressions must not have side effects.
991 The basic @samp{MATCH_} expressions can be combined using these
992 logical operators, which have the semantics of the C operators
993 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
994 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
995 arbitrary number of arguments; this has exactly the same effect as
996 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
1000 An optional block of C code, which should execute
1001 @samp{@w{return true}} if the predicate is found to match and
1002 @samp{@w{return false}} if it does not. It must not have any side
1003 effects. The predicate arguments, @var{op} and @var{mode}, are
1004 available with those names.
1006 If a code block is present in a predicate definition, then the RTL
1007 expression must evaluate to true @emph{and} the code block must
1008 execute @samp{@w{return true}} for the predicate to allow the operand.
1009 The RTL expression is evaluated first; do not re-check anything in the
1010 code block that was checked in the RTL expression.
1013 The program @command{genrecog} scans @code{define_predicate} and
1014 @code{define_special_predicate} expressions to determine which RTX
1015 codes are possibly allowed. You should always make this explicit in
1016 the RTL predicate expression, using @code{MATCH_OPERAND} and
1019 Here is an example of a simple predicate definition, from the IA64
1020 machine description:
1024 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
1025 (define_predicate "small_addr_symbolic_operand"
1026 (and (match_code "symbol_ref")
1027 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1032 And here is another, showing the use of the C block.
1036 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1037 (define_predicate "gr_register_operand"
1038 (match_operand 0 "register_operand")
1041 if (GET_CODE (op) == SUBREG)
1042 op = SUBREG_REG (op);
1045 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1050 Predicates written with @code{define_predicate} automatically include
1051 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1052 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1053 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1054 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1055 kind of constant fits in the requested mode. This is because
1056 target-specific predicates that take constants usually have to do more
1057 stringent value checks anyway. If you need the exact same treatment
1058 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1059 provide, use a @code{MATCH_OPERAND} subexpression to call
1060 @code{const_int_operand}, @code{const_double_operand}, or
1061 @code{immediate_operand}.
1063 Predicates written with @code{define_special_predicate} do not get any
1064 automatic mode checks, and are treated as having special mode handling
1065 by @command{genrecog}.
1067 The program @command{genpreds} is responsible for generating code to
1068 test predicates. It also writes a header file containing function
1069 declarations for all machine-specific predicates. It is not necessary
1070 to declare these predicates in @file{@var{cpu}-protos.h}.
1073 @c Most of this node appears by itself (in a different place) even
1074 @c when the INTERNALS flag is clear. Passages that require the internals
1075 @c manual's context are conditionalized to appear only in the internals manual.
1078 @section Operand Constraints
1079 @cindex operand constraints
1082 Each @code{match_operand} in an instruction pattern can specify
1083 constraints for the operands allowed. The constraints allow you to
1084 fine-tune matching within the set of operands allowed by the
1090 @section Constraints for @code{asm} Operands
1091 @cindex operand constraints, @code{asm}
1092 @cindex constraints, @code{asm}
1093 @cindex @code{asm} constraints
1095 Here are specific details on what constraint letters you can use with
1096 @code{asm} operands.
1098 Constraints can say whether
1099 an operand may be in a register, and which kinds of register; whether the
1100 operand can be a memory reference, and which kinds of address; whether the
1101 operand may be an immediate constant, and which possible values it may
1102 have. Constraints can also require two operands to match.
1103 Side-effects aren't allowed in operands of inline @code{asm}, unless
1104 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1105 that the side effects will happen exactly once in an instruction that can update
1106 the addressing register.
1110 * Simple Constraints:: Basic use of constraints.
1111 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1112 * Class Preferences:: Constraints guide which hard register to put things in.
1113 * Modifiers:: More precise control over effects of constraints.
1114 * Machine Constraints:: Existing constraints for some particular machines.
1115 * Disable Insn Alternatives:: Disable insn alternatives using attributes.
1116 * Define Constraints:: How to define machine-specific constraints.
1117 * C Constraint Interface:: How to test constraints from C code.
1123 * Simple Constraints:: Basic use of constraints.
1124 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1125 * Modifiers:: More precise control over effects of constraints.
1126 * Machine Constraints:: Special constraints for some particular machines.
1130 @node Simple Constraints
1131 @subsection Simple Constraints
1132 @cindex simple constraints
1134 The simplest kind of constraint is a string full of letters, each of
1135 which describes one kind of operand that is permitted. Here are
1136 the letters that are allowed:
1140 Whitespace characters are ignored and can be inserted at any position
1141 except the first. This enables each alternative for different operands to
1142 be visually aligned in the machine description even if they have different
1143 number of constraints and modifiers.
1145 @cindex @samp{m} in constraint
1146 @cindex memory references in constraints
1148 A memory operand is allowed, with any kind of address that the machine
1149 supports in general.
1150 Note that the letter used for the general memory constraint can be
1151 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1153 @cindex offsettable address
1154 @cindex @samp{o} in constraint
1156 A memory operand is allowed, but only if the address is
1157 @dfn{offsettable}. This means that adding a small integer (actually,
1158 the width in bytes of the operand, as determined by its machine mode)
1159 may be added to the address and the result is also a valid memory
1162 @cindex autoincrement/decrement addressing
1163 For example, an address which is constant is offsettable; so is an
1164 address that is the sum of a register and a constant (as long as a
1165 slightly larger constant is also within the range of address-offsets
1166 supported by the machine); but an autoincrement or autodecrement
1167 address is not offsettable. More complicated indirect/indexed
1168 addresses may or may not be offsettable depending on the other
1169 addressing modes that the machine supports.
1171 Note that in an output operand which can be matched by another
1172 operand, the constraint letter @samp{o} is valid only when accompanied
1173 by both @samp{<} (if the target machine has predecrement addressing)
1174 and @samp{>} (if the target machine has preincrement addressing).
1176 @cindex @samp{V} in constraint
1178 A memory operand that is not offsettable. In other words, anything that
1179 would fit the @samp{m} constraint but not the @samp{o} constraint.
1181 @cindex @samp{<} in constraint
1183 A memory operand with autodecrement addressing (either predecrement or
1184 postdecrement) is allowed. In inline @code{asm} this constraint is only
1185 allowed if the operand is used exactly once in an instruction that can
1186 handle the side effects. Not using an operand with @samp{<} in constraint
1187 string in the inline @code{asm} pattern at all or using it in multiple
1188 instructions isn't valid, because the side effects wouldn't be performed
1189 or would be performed more than once. Furthermore, on some targets
1190 the operand with @samp{<} in constraint string must be accompanied by
1191 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1192 or @code{%P0} on IA-64.
1194 @cindex @samp{>} in constraint
1196 A memory operand with autoincrement addressing (either preincrement or
1197 postincrement) is allowed. In inline @code{asm} the same restrictions
1198 as for @samp{<} apply.
1200 @cindex @samp{r} in constraint
1201 @cindex registers in constraints
1203 A register operand is allowed provided that it is in a general
1206 @cindex constants in constraints
1207 @cindex @samp{i} in constraint
1209 An immediate integer operand (one with constant value) is allowed.
1210 This includes symbolic constants whose values will be known only at
1211 assembly time or later.
1213 @cindex @samp{n} in constraint
1215 An immediate integer operand with a known numeric value is allowed.
1216 Many systems cannot support assembly-time constants for operands less
1217 than a word wide. Constraints for these operands should use @samp{n}
1218 rather than @samp{i}.
1220 @cindex @samp{I} in constraint
1221 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1222 Other letters in the range @samp{I} through @samp{P} may be defined in
1223 a machine-dependent fashion to permit immediate integer operands with
1224 explicit integer values in specified ranges. For example, on the
1225 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1226 This is the range permitted as a shift count in the shift
1229 @cindex @samp{E} in constraint
1231 An immediate floating operand (expression code @code{const_double}) is
1232 allowed, but only if the target floating point format is the same as
1233 that of the host machine (on which the compiler is running).
1235 @cindex @samp{F} in constraint
1237 An immediate floating operand (expression code @code{const_double} or
1238 @code{const_vector}) is allowed.
1240 @cindex @samp{G} in constraint
1241 @cindex @samp{H} in constraint
1242 @item @samp{G}, @samp{H}
1243 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1244 permit immediate floating operands in particular ranges of values.
1246 @cindex @samp{s} in constraint
1248 An immediate integer operand whose value is not an explicit integer is
1251 This might appear strange; if an insn allows a constant operand with a
1252 value not known at compile time, it certainly must allow any known
1253 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1254 better code to be generated.
1256 For example, on the 68000 in a fullword instruction it is possible to
1257 use an immediate operand; but if the immediate value is between @minus{}128
1258 and 127, better code results from loading the value into a register and
1259 using the register. This is because the load into the register can be
1260 done with a @samp{moveq} instruction. We arrange for this to happen
1261 by defining the letter @samp{K} to mean ``any integer outside the
1262 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1265 @cindex @samp{g} in constraint
1267 Any register, memory or immediate integer operand is allowed, except for
1268 registers that are not general registers.
1270 @cindex @samp{X} in constraint
1273 Any operand whatsoever is allowed, even if it does not satisfy
1274 @code{general_operand}. This is normally used in the constraint of
1275 a @code{match_scratch} when certain alternatives will not actually
1276 require a scratch register.
1279 Any operand whatsoever is allowed.
1282 @cindex @samp{0} in constraint
1283 @cindex digits in constraint
1284 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1285 An operand that matches the specified operand number is allowed. If a
1286 digit is used together with letters within the same alternative, the
1287 digit should come last.
1289 This number is allowed to be more than a single digit. If multiple
1290 digits are encountered consecutively, they are interpreted as a single
1291 decimal integer. There is scant chance for ambiguity, since to-date
1292 it has never been desirable that @samp{10} be interpreted as matching
1293 either operand 1 @emph{or} operand 0. Should this be desired, one
1294 can use multiple alternatives instead.
1296 @cindex matching constraint
1297 @cindex constraint, matching
1298 This is called a @dfn{matching constraint} and what it really means is
1299 that the assembler has only a single operand that fills two roles
1301 considered separate in the RTL insn. For example, an add insn has two
1302 input operands and one output operand in the RTL, but on most CISC
1305 which @code{asm} distinguishes. For example, an add instruction uses
1306 two input operands and an output operand, but on most CISC
1308 machines an add instruction really has only two operands, one of them an
1309 input-output operand:
1315 Matching constraints are used in these circumstances.
1316 More precisely, the two operands that match must include one input-only
1317 operand and one output-only operand. Moreover, the digit must be a
1318 smaller number than the number of the operand that uses it in the
1322 For operands to match in a particular case usually means that they
1323 are identical-looking RTL expressions. But in a few special cases
1324 specific kinds of dissimilarity are allowed. For example, @code{*x}
1325 as an input operand will match @code{*x++} as an output operand.
1326 For proper results in such cases, the output template should always
1327 use the output-operand's number when printing the operand.
1330 @cindex load address instruction
1331 @cindex push address instruction
1332 @cindex address constraints
1333 @cindex @samp{p} in constraint
1335 An operand that is a valid memory address is allowed. This is
1336 for ``load address'' and ``push address'' instructions.
1338 @findex address_operand
1339 @samp{p} in the constraint must be accompanied by @code{address_operand}
1340 as the predicate in the @code{match_operand}. This predicate interprets
1341 the mode specified in the @code{match_operand} as the mode of the memory
1342 reference for which the address would be valid.
1344 @cindex other register constraints
1345 @cindex extensible constraints
1346 @item @var{other-letters}
1347 Other letters can be defined in machine-dependent fashion to stand for
1348 particular classes of registers or other arbitrary operand types.
1349 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1350 for data, address and floating point registers.
1354 In order to have valid assembler code, each operand must satisfy
1355 its constraint. But a failure to do so does not prevent the pattern
1356 from applying to an insn. Instead, it directs the compiler to modify
1357 the code so that the constraint will be satisfied. Usually this is
1358 done by copying an operand into a register.
1360 Contrast, therefore, the two instruction patterns that follow:
1364 [(set (match_operand:SI 0 "general_operand" "=r")
1365 (plus:SI (match_dup 0)
1366 (match_operand:SI 1 "general_operand" "r")))]
1372 which has two operands, one of which must appear in two places, and
1376 [(set (match_operand:SI 0 "general_operand" "=r")
1377 (plus:SI (match_operand:SI 1 "general_operand" "0")
1378 (match_operand:SI 2 "general_operand" "r")))]
1384 which has three operands, two of which are required by a constraint to be
1385 identical. If we are considering an insn of the form
1388 (insn @var{n} @var{prev} @var{next}
1390 (plus:SI (reg:SI 6) (reg:SI 109)))
1395 the first pattern would not apply at all, because this insn does not
1396 contain two identical subexpressions in the right place. The pattern would
1397 say, ``That does not look like an add instruction; try other patterns''.
1398 The second pattern would say, ``Yes, that's an add instruction, but there
1399 is something wrong with it''. It would direct the reload pass of the
1400 compiler to generate additional insns to make the constraint true. The
1401 results might look like this:
1404 (insn @var{n2} @var{prev} @var{n}
1405 (set (reg:SI 3) (reg:SI 6))
1408 (insn @var{n} @var{n2} @var{next}
1410 (plus:SI (reg:SI 3) (reg:SI 109)))
1414 It is up to you to make sure that each operand, in each pattern, has
1415 constraints that can handle any RTL expression that could be present for
1416 that operand. (When multiple alternatives are in use, each pattern must,
1417 for each possible combination of operand expressions, have at least one
1418 alternative which can handle that combination of operands.) The
1419 constraints don't need to @emph{allow} any possible operand---when this is
1420 the case, they do not constrain---but they must at least point the way to
1421 reloading any possible operand so that it will fit.
1425 If the constraint accepts whatever operands the predicate permits,
1426 there is no problem: reloading is never necessary for this operand.
1428 For example, an operand whose constraints permit everything except
1429 registers is safe provided its predicate rejects registers.
1431 An operand whose predicate accepts only constant values is safe
1432 provided its constraints include the letter @samp{i}. If any possible
1433 constant value is accepted, then nothing less than @samp{i} will do;
1434 if the predicate is more selective, then the constraints may also be
1438 Any operand expression can be reloaded by copying it into a register.
1439 So if an operand's constraints allow some kind of register, it is
1440 certain to be safe. It need not permit all classes of registers; the
1441 compiler knows how to copy a register into another register of the
1442 proper class in order to make an instruction valid.
1444 @cindex nonoffsettable memory reference
1445 @cindex memory reference, nonoffsettable
1447 A nonoffsettable memory reference can be reloaded by copying the
1448 address into a register. So if the constraint uses the letter
1449 @samp{o}, all memory references are taken care of.
1452 A constant operand can be reloaded by allocating space in memory to
1453 hold it as preinitialized data. Then the memory reference can be used
1454 in place of the constant. So if the constraint uses the letters
1455 @samp{o} or @samp{m}, constant operands are not a problem.
1458 If the constraint permits a constant and a pseudo register used in an insn
1459 was not allocated to a hard register and is equivalent to a constant,
1460 the register will be replaced with the constant. If the predicate does
1461 not permit a constant and the insn is re-recognized for some reason, the
1462 compiler will crash. Thus the predicate must always recognize any
1463 objects allowed by the constraint.
1466 If the operand's predicate can recognize registers, but the constraint does
1467 not permit them, it can make the compiler crash. When this operand happens
1468 to be a register, the reload pass will be stymied, because it does not know
1469 how to copy a register temporarily into memory.
1471 If the predicate accepts a unary operator, the constraint applies to the
1472 operand. For example, the MIPS processor at ISA level 3 supports an
1473 instruction which adds two registers in @code{SImode} to produce a
1474 @code{DImode} result, but only if the registers are correctly sign
1475 extended. This predicate for the input operands accepts a
1476 @code{sign_extend} of an @code{SImode} register. Write the constraint
1477 to indicate the type of register that is required for the operand of the
1481 @node Multi-Alternative
1482 @subsection Multiple Alternative Constraints
1483 @cindex multiple alternative constraints
1485 Sometimes a single instruction has multiple alternative sets of possible
1486 operands. For example, on the 68000, a logical-or instruction can combine
1487 register or an immediate value into memory, or it can combine any kind of
1488 operand into a register; but it cannot combine one memory location into
1491 These constraints are represented as multiple alternatives. An alternative
1492 can be described by a series of letters for each operand. The overall
1493 constraint for an operand is made from the letters for this operand
1494 from the first alternative, a comma, the letters for this operand from
1495 the second alternative, a comma, and so on until the last alternative.
1496 All operands for a single instruction must have the same number of
1499 Here is how it is done for fullword logical-or on the 68000:
1502 (define_insn "iorsi3"
1503 [(set (match_operand:SI 0 "general_operand" "=m,d")
1504 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1505 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1509 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1510 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1511 2. The second alternative has @samp{d} (data register) for operand 0,
1512 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1513 @samp{%} in the constraints apply to all the alternatives; their
1514 meaning is explained in the next section (@pxref{Class Preferences}).
1516 If all the operands fit any one alternative, the instruction is valid.
1517 Otherwise, for each alternative, the compiler counts how many instructions
1518 must be added to copy the operands so that that alternative applies.
1519 The alternative requiring the least copying is chosen. If two alternatives
1520 need the same amount of copying, the one that comes first is chosen.
1521 These choices can be altered with the @samp{?} and @samp{!} characters:
1524 @cindex @samp{?} in constraint
1525 @cindex question mark
1527 Disparage slightly the alternative that the @samp{?} appears in,
1528 as a choice when no alternative applies exactly. The compiler regards
1529 this alternative as one unit more costly for each @samp{?} that appears
1532 @cindex @samp{!} in constraint
1533 @cindex exclamation point
1535 Disparage severely the alternative that the @samp{!} appears in.
1536 This alternative can still be used if it fits without reloading,
1537 but if reloading is needed, some other alternative will be used.
1539 @cindex @samp{^} in constraint
1542 This constraint is analogous to @samp{?} but it disparages slightly
1543 the alternative only if the operand with the @samp{^} needs a reload.
1545 @cindex @samp{$} in constraint
1548 This constraint is analogous to @samp{!} but it disparages severely
1549 the alternative only if the operand with the @samp{$} needs a reload.
1552 When an insn pattern has multiple alternatives in its constraints, often
1553 the appearance of the assembler code is determined mostly by which
1554 alternative was matched. When this is so, the C code for writing the
1555 assembler code can use the variable @code{which_alternative}, which is
1556 the ordinal number of the alternative that was actually satisfied (0 for
1557 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1561 So the first alternative for the 68000's logical-or could be written as
1562 @code{"+m" (output) : "ir" (input)}. The second could be @code{"+r"
1563 (output): "irm" (input)}. However, the fact that two memory locations
1564 cannot be used in a single instruction prevents simply using @code{"+rm"
1565 (output) : "irm" (input)}. Using multi-alternatives, this might be
1566 written as @code{"+m,r" (output) : "ir,irm" (input)}. This describes
1567 all the available alternatives to the compiler, allowing it to choose
1568 the most efficient one for the current conditions.
1570 There is no way within the template to determine which alternative was
1571 chosen. However you may be able to wrap your @code{asm} statements with
1572 builtins such as @code{__builtin_constant_p} to achieve the desired results.
1576 @node Class Preferences
1577 @subsection Register Class Preferences
1578 @cindex class preference constraints
1579 @cindex register class preference constraints
1581 @cindex voting between constraint alternatives
1582 The operand constraints have another function: they enable the compiler
1583 to decide which kind of hardware register a pseudo register is best
1584 allocated to. The compiler examines the constraints that apply to the
1585 insns that use the pseudo register, looking for the machine-dependent
1586 letters such as @samp{d} and @samp{a} that specify classes of registers.
1587 The pseudo register is put in whichever class gets the most ``votes''.
1588 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1589 favor of a general register. The machine description says which registers
1590 are considered general.
1592 Of course, on some machines all registers are equivalent, and no register
1593 classes are defined. Then none of this complexity is relevant.
1597 @subsection Constraint Modifier Characters
1598 @cindex modifiers in constraints
1599 @cindex constraint modifier characters
1601 @c prevent bad page break with this line
1602 Here are constraint modifier characters.
1605 @cindex @samp{=} in constraint
1607 Means that this operand is written to by this instruction:
1608 the previous value is discarded and replaced by new data.
1610 @cindex @samp{+} in constraint
1612 Means that this operand is both read and written by the instruction.
1614 When the compiler fixes up the operands to satisfy the constraints,
1615 it needs to know which operands are read by the instruction and
1616 which are written by it. @samp{=} identifies an operand which is only
1617 written; @samp{+} identifies an operand that is both read and written; all
1618 other operands are assumed to only be read.
1620 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1621 first character of the constraint string.
1623 @cindex @samp{&} in constraint
1624 @cindex earlyclobber operand
1626 Means (in a particular alternative) that this operand is an
1627 @dfn{earlyclobber} operand, which is written before the instruction is
1628 finished using the input operands. Therefore, this operand may not lie
1629 in a register that is read by the instruction or as part of any memory
1632 @samp{&} applies only to the alternative in which it is written. In
1633 constraints with multiple alternatives, sometimes one alternative
1634 requires @samp{&} while others do not. See, for example, the
1635 @samp{movdf} insn of the 68000.
1637 An operand which is read by the instruction can be tied to an earlyclobber
1638 operand if its only use as an input occurs before the early result is
1639 written. Adding alternatives of this form often allows GCC to produce
1640 better code when only some of the read operands can be affected by the
1641 earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@.
1643 Furthermore, if the @dfn{earlyclobber} operand is also a read/write
1644 operand, then that operand is written only after it's used.
1646 @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As
1647 @dfn{earlyclobber} operands are always written, a read-only
1648 @dfn{earlyclobber} operand is ill-formed and will be rejected by the
1651 @cindex @samp{%} in constraint
1653 Declares the instruction to be commutative for this operand and the
1654 following operand. This means that the compiler may interchange the
1655 two operands if that is the cheapest way to make all operands fit the
1656 constraints. @samp{%} applies to all alternatives and must appear as
1657 the first character in the constraint. Only read-only operands can use
1661 This is often used in patterns for addition instructions
1662 that really have only two operands: the result must go in one of the
1663 arguments. Here for example, is how the 68000 halfword-add
1664 instruction is defined:
1667 (define_insn "addhi3"
1668 [(set (match_operand:HI 0 "general_operand" "=m,r")
1669 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1670 (match_operand:HI 2 "general_operand" "di,g")))]
1674 GCC can only handle one commutative pair in an asm; if you use more,
1675 the compiler may fail. Note that you need not use the modifier if
1676 the two alternatives are strictly identical; this would only waste
1677 time in the reload pass.
1679 The modifier is not operational after
1680 register allocation, so the result of @code{define_peephole2}
1681 and @code{define_split}s performed after reload cannot rely on
1682 @samp{%} to make the intended insn match.
1684 @cindex @samp{#} in constraint
1686 Says that all following characters, up to the next comma, are to be
1687 ignored as a constraint. They are significant only for choosing
1688 register preferences.
1690 @cindex @samp{*} in constraint
1692 Says that the following character should be ignored when choosing
1693 register preferences. @samp{*} has no effect on the meaning of the
1694 constraint as a constraint, and no effect on reloading. For LRA
1695 @samp{*} additionally disparages slightly the alternative if the
1696 following character matches the operand.
1698 Here is an example: the 68000 has an instruction to sign-extend a
1699 halfword in a data register, and can also sign-extend a value by
1700 copying it into an address register. While either kind of register is
1701 acceptable, the constraints on an address-register destination are
1702 less strict, so it is best if register allocation makes an address
1703 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1704 constraint letter (for data register) is ignored when computing
1705 register preferences.
1708 (define_insn "extendhisi2"
1709 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1711 (match_operand:HI 1 "general_operand" "0,g")))]
1717 @node Machine Constraints
1718 @subsection Constraints for Particular Machines
1719 @cindex machine specific constraints
1720 @cindex constraints, machine specific
1722 Whenever possible, you should use the general-purpose constraint letters
1723 in @code{asm} arguments, since they will convey meaning more readily to
1724 people reading your code. Failing that, use the constraint letters
1725 that usually have very similar meanings across architectures. The most
1726 commonly used constraints are @samp{m} and @samp{r} (for memory and
1727 general-purpose registers respectively; @pxref{Simple Constraints}), and
1728 @samp{I}, usually the letter indicating the most common
1729 immediate-constant format.
1731 Each architecture defines additional constraints. These constraints
1732 are used by the compiler itself for instruction generation, as well as
1733 for @code{asm} statements; therefore, some of the constraints are not
1734 particularly useful for @code{asm}. Here is a summary of some of the
1735 machine-dependent constraints available on some particular machines;
1736 it includes both constraints that are useful for @code{asm} and
1737 constraints that aren't. The compiler source file mentioned in the
1738 table heading for each architecture is the definitive reference for
1739 the meanings of that architecture's constraints.
1741 @c Please keep this table alphabetized by target!
1743 @item AArch64 family---@file{config/aarch64/constraints.md}
1746 The stack pointer register (@code{SP})
1749 Floating point register, Advanced SIMD vector register or SVE vector register
1752 Like @code{w}, but restricted to registers 0 to 15 inclusive.
1755 Like @code{w}, but restricted to registers 0 to 7 inclusive.
1758 One of the low eight SVE predicate registers (@code{P0} to @code{P7})
1761 Any of the SVE predicate registers (@code{P0} to @code{P15})
1764 Integer constant that is valid as an immediate operand in an @code{ADD}
1768 Integer constant that is valid as an immediate operand in a @code{SUB}
1769 instruction (once negated)
1772 Integer constant that can be used with a 32-bit logical instruction
1775 Integer constant that can be used with a 64-bit logical instruction
1778 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1779 pseudo instruction. The @code{MOV} may be assembled to one of several different
1780 machine instructions depending on the value
1783 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1787 An absolute symbolic address or a label reference
1790 Floating point constant zero
1793 Integer constant zero
1796 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1797 within 4GB of the instruction
1800 A memory address which uses a single base register with no offset
1803 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1809 @item AMD GCN ---@file{config/gcn/constraints.md}
1812 Immediate integer in the range @minus{}16 to 64
1815 Immediate 16-bit signed integer
1818 Immediate constant @minus{}1
1821 Immediate 15-bit unsigned integer
1824 Immediate constant that can be inlined in an instruction encoding: integer
1825 @minus{}16..64, or float 0.0, +/@minus{}0.5, +/@minus{}1.0, +/@minus{}2.0,
1826 +/@minus{}4.0, 1.0/(2.0*PI)
1829 Immediate 32-bit signed integer that can be attached to an instruction encoding
1832 Immediate 32-bit integer in range @minus{}16..4294967295 (i.e. 32-bit unsigned
1833 integer or @samp{A} constraint)
1836 Immediate 64-bit constant that can be split into two @samp{A} constants
1839 Immediate 64-bit constant that can be split into two @samp{B} constants
1845 Any @code{symbol_ref} or @code{label_ref}
1854 SGPR registers valid for instruction destinations, including VCC, M0 and EXEC
1857 SGPR registers valid for instruction sources, including VCC, M0, EXEC and SCC
1860 SGPR registers valid as a source for scalar memory instructions (excludes M0
1864 SGPR registers valid as a source or destination for vector instructions
1868 All condition registers: SCC, VCCZ, EXECZ
1871 Scalar condition register: SCC
1874 Vector condition register: VCC, VCC_LO, VCC_HI
1877 EXEC register (EXEC_LO and EXEC_HI)
1880 Memory operand with address space suitable for @code{buffer_*} instructions
1883 Memory operand with address space suitable for @code{flat_*} instructions
1886 Memory operand with address space suitable for @code{s_*} instructions
1889 Memory operand with address space suitable for @code{ds_*} LDS instructions
1892 Memory operand with address space suitable for @code{ds_*} GDS instructions
1895 Memory operand with address space suitable for any @code{ds_*} instructions
1898 Memory operand with address space suitable for @code{global_*} instructions
1903 @item ARC ---@file{config/arc/constraints.md}
1906 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1907 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1908 option is in effect.
1911 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1912 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1913 This constraint can only match when the @option{-mq}
1914 option is in effect.
1916 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1919 A signed 12-bit integer constant.
1922 constant for arithmetic/logical operations. This might be any constant
1923 that can be put into a long immediate by the assmbler or linker without
1924 involving a PIC relocation.
1927 A 3-bit unsigned integer constant.
1930 A 6-bit unsigned integer constant.
1933 One's complement of a 6-bit unsigned integer constant.
1936 Two's complement of a 6-bit unsigned integer constant.
1939 A 5-bit unsigned integer constant.
1942 A 7-bit unsigned integer constant.
1945 A 8-bit unsigned integer constant.
1948 Any const_double value.
1951 @item ARM family---@file{config/arm/constraints.md}
1955 In Thumb state, the core registers @code{r8}-@code{r15}.
1958 The stack pointer register.
1961 In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this
1962 is an alias for the @code{r} constraint.
1965 VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values.
1968 VFP floating-point registers @code{d0}-@code{d31} and the appropriate
1969 subset @code{d0}-@code{d15} based on command line options.
1970 Used for 64 bit values only. Not valid for Thumb1.
1973 The iWMMX co-processor registers.
1976 The iWMMX GR registers.
1979 The floating-point constant 0.0
1982 Integer that is valid as an immediate operand in a data processing
1983 instruction. That is, an integer in the range 0 to 255 rotated by a
1987 Integer in the range @minus{}4095 to 4095
1990 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1993 Integer that satisfies constraint @samp{I} when negated (twos complement)
1996 Integer in the range 0 to 32
1999 A memory reference where the exact address is in a single register
2000 (`@samp{m}' is preferable for @code{asm} statements)
2003 An item in the constant pool
2006 A symbol in the text segment of the current file
2009 A memory reference suitable for VFP load/store insns (reg+constant offset)
2012 A memory reference suitable for iWMMXt load/store instructions.
2015 A memory reference suitable for the ARMv4 ldrsb instruction.
2018 @item AVR family---@file{config/avr/constraints.md}
2021 Registers from r0 to r15
2024 Registers from r16 to r23
2027 Registers from r16 to r31
2030 Registers from r24 to r31. These registers can be used in @samp{adiw} command
2033 Pointer register (r26--r31)
2036 Base pointer register (r28--r31)
2039 Stack pointer register (SPH:SPL)
2042 Temporary register r0
2045 Register pair X (r27:r26)
2048 Register pair Y (r29:r28)
2051 Register pair Z (r31:r30)
2054 Constant greater than @minus{}1, less than 64
2057 Constant greater than @minus{}64, less than 1
2066 Constant that fits in 8 bits
2069 Constant integer @minus{}1
2072 Constant integer 8, 16, or 24
2078 A floating point constant 0.0
2081 A memory address based on Y or Z pointer with displacement.
2084 @item Blackfin family---@file{config/bfin/constraints.md}
2093 A call clobbered P register.
2096 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2097 register. If it is @code{A}, then the register P0.
2100 Even-numbered D register
2103 Odd-numbered D register
2106 Accumulator register.
2109 Even-numbered accumulator register.
2112 Odd-numbered accumulator register.
2124 Registers used for circular buffering, i.e.@: I, B, or L registers.
2139 Any D, P, B, M, I or L register.
2142 Additional registers typically used only in prologues and epilogues: RETS,
2143 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2146 Any register except accumulators or CC.
2149 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2152 Unsigned 16 bit integer (in the range 0 to 65535)
2155 Signed 7 bit integer (in the range @minus{}64 to 63)
2158 Unsigned 7 bit integer (in the range 0 to 127)
2161 Unsigned 5 bit integer (in the range 0 to 31)
2164 Signed 4 bit integer (in the range @minus{}8 to 7)
2167 Signed 3 bit integer (in the range @minus{}3 to 4)
2170 Unsigned 3 bit integer (in the range 0 to 7)
2173 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2176 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2177 use with either accumulator.
2180 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2181 use only with accumulator A1.
2190 An integer constant with exactly a single bit set.
2193 An integer constant with all bits set except exactly one.
2201 @item CR16 Architecture---@file{config/cr16/cr16.h}
2205 Registers from r0 to r14 (registers without stack pointer)
2208 Register from r0 to r11 (all 16-bit registers)
2211 Register from r12 to r15 (all 32-bit registers)
2214 Signed constant that fits in 4 bits
2217 Signed constant that fits in 5 bits
2220 Signed constant that fits in 6 bits
2223 Unsigned constant that fits in 4 bits
2226 Signed constant that fits in 32 bits
2229 Check for 64 bits wide constants for add/sub instructions
2232 Floating point constant that is legal for store immediate
2235 @item C-SKY---@file{config/csky/constraints.md}
2239 The mini registers r0 - r7.
2242 The low registers r0 - r15.
2248 HI and LO registers.
2260 Stack pointer register (SP).
2264 The C-SKY back end supports a large set of additional constraints
2265 that are only useful for instruction selection or splitting rather
2266 than inline asm, such as constraints representing constant integer
2267 ranges accepted by particular instruction encodings.
2268 Refer to the source code for details.
2271 @item Epiphany---@file{config/epiphany/constraints.md}
2274 An unsigned 16-bit constant.
2277 An unsigned 5-bit constant.
2280 A signed 11-bit constant.
2283 A signed 11-bit constant added to @minus{}1.
2284 Can only match when the @option{-m1reg-@var{reg}} option is active.
2287 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
2288 being a block of trailing zeroes.
2289 Can only match when the @option{-m1reg-@var{reg}} option is active.
2292 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
2293 rest being zeroes. Or to put it another way, one less than a power of two.
2294 Can only match when the @option{-m1reg-@var{reg}} option is active.
2297 Constant for arithmetic/logical operations.
2298 This is like @code{i}, except that for position independent code,
2299 no symbols / expressions needing relocations are allowed.
2302 Symbolic constant for call/jump instruction.
2305 The register class usable in short insns. This is a register class
2306 constraint, and can thus drive register allocation.
2307 This constraint won't match unless @option{-mprefer-short-insn-regs} is
2311 The the register class of registers that can be used to hold a
2312 sibcall call address. I.e., a caller-saved register.
2315 Core control register class.
2318 The register group usable in short insns.
2319 This constraint does not use a register class, so that it only
2320 passively matches suitable registers, and doesn't drive register allocation.
2324 Constant suitable for the addsi3_r pattern. This is a valid offset
2325 For byte, halfword, or word addressing.
2329 Matches the return address if it can be replaced with the link register.
2332 Matches the integer condition code register.
2335 Matches the return address if it is in a stack slot.
2338 Matches control register values to switch fp mode, which are encapsulated in
2339 @code{UNSPEC_FP_MODE}.
2342 @item FRV---@file{config/frv/frv.h}
2345 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2348 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2351 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2352 @code{icc0} to @code{icc3}).
2355 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2358 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2359 Odd registers are excluded not in the class but through the use of a machine
2360 mode larger than 4 bytes.
2363 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2366 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2367 Odd registers are excluded not in the class but through the use of a machine
2368 mode larger than 4 bytes.
2371 Register in the class @code{LR_REG} (the @code{lr} register).
2374 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2375 Register numbers not divisible by 4 are excluded not in the class but through
2376 the use of a machine mode larger than 8 bytes.
2379 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2382 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2385 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2388 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2391 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2392 Register numbers not divisible by 4 are excluded not in the class but through
2393 the use of a machine mode larger than 8 bytes.
2396 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2399 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2402 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2405 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2408 Floating point constant zero
2411 6-bit signed integer constant
2414 10-bit signed integer constant
2417 16-bit signed integer constant
2420 16-bit unsigned integer constant
2423 12-bit signed integer constant that is negative---i.e.@: in the
2424 range of @minus{}2048 to @minus{}1
2430 12-bit signed integer constant that is greater than zero---i.e.@: in the
2435 @item FT32---@file{config/ft32/constraints.md}
2444 A register indirect memory operand
2453 The constant zero or one
2456 A 16-bit signed constant (@minus{}32768 @dots{} 32767)
2459 A bitfield mask suitable for bext or bins
2462 An inverted bitfield mask suitable for bext or bins
2465 A 16-bit unsigned constant, multiple of 4 (0 @dots{} 65532)
2468 A 20-bit signed constant (@minus{}524288 @dots{} 524287)
2471 A constant for a bitfield width (1 @dots{} 16)
2474 A 10-bit signed constant (@minus{}512 @dots{} 511)
2478 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2484 Floating point register
2487 Shift amount register
2490 Floating point register (deprecated)
2493 Upper floating point register (32-bit), floating point register (64-bit)
2499 Signed 11-bit integer constant
2502 Signed 14-bit integer constant
2505 Integer constant that can be deposited with a @code{zdepi} instruction
2508 Signed 5-bit integer constant
2514 Integer constant that can be loaded with a @code{ldil} instruction
2517 Integer constant whose value plus one is a power of 2
2520 Integer constant that can be used for @code{and} operations in @code{depi}
2521 and @code{extru} instructions
2530 Floating-point constant 0.0
2533 A @code{lo_sum} data-linkage-table memory operand
2536 A memory operand that can be used as the destination operand of an
2537 integer store instruction
2540 A scaled or unscaled indexed memory operand
2543 A memory operand for floating-point loads and stores
2546 A register indirect memory operand
2549 @item Intel IA-64---@file{config/ia64/ia64.h}
2552 General register @code{r0} to @code{r3} for @code{addl} instruction
2558 Predicate register (@samp{c} as in ``conditional'')
2561 Application register residing in M-unit
2564 Application register residing in I-unit
2567 Floating-point register
2570 Memory operand. If used together with @samp{<} or @samp{>},
2571 the operand can have postincrement and postdecrement which
2572 require printing with @samp{%Pn} on IA-64.
2575 Floating-point constant 0.0 or 1.0
2578 14-bit signed integer constant
2581 22-bit signed integer constant
2584 8-bit signed integer constant for logical instructions
2587 8-bit adjusted signed integer constant for compare pseudo-ops
2590 6-bit unsigned integer constant for shift counts
2593 9-bit signed integer constant for load and store postincrements
2599 0 or @minus{}1 for @code{dep} instruction
2602 Non-volatile memory for floating-point loads and stores
2605 Integer constant in the range 1 to 4 for @code{shladd} instruction
2608 Memory operand except postincrement and postdecrement. This is
2609 now roughly the same as @samp{m} when not used together with @samp{<}
2613 @item M32C---@file{config/m32c/m32c.c}
2618 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2621 Any control register, when they're 16 bits wide (nothing if control
2622 registers are 24 bits wide)
2625 Any control register, when they're 24 bits wide.
2634 $r0 or $r2, or $r2r0 for 32 bit values.
2637 $r1 or $r3, or $r3r1 for 32 bit values.
2640 A register that can hold a 64 bit value.
2643 $r0 or $r1 (registers with addressable high/low bytes)
2652 Address registers when they're 16 bits wide.
2655 Address registers when they're 24 bits wide.
2658 Registers that can hold QI values.
2661 Registers that can be used with displacements ($a0, $a1, $sb).
2664 Registers that can hold 32 bit values.
2667 Registers that can hold 16 bit values.
2670 Registers chat can hold 16 bit values, including all control
2674 $r0 through R1, plus $a0 and $a1.
2680 The memory-based pseudo-registers $mem0 through $mem15.
2683 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2684 bit registers for m32cm, m32c).
2687 Matches multiple registers in a PARALLEL to form a larger register.
2688 Used to match function return values.
2694 @minus{}128 @dots{} 127
2697 @minus{}32768 @dots{} 32767
2703 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2706 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2709 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2712 @minus{}65536 @dots{} @minus{}1
2715 An 8 bit value with exactly one bit set.
2718 A 16 bit value with exactly one bit set.
2721 The common src/dest memory addressing modes.
2724 Memory addressed using $a0 or $a1.
2727 Memory addressed with immediate addresses.
2730 Memory addressed using the stack pointer ($sp).
2733 Memory addressed using the frame base register ($fb).
2736 Memory addressed using the small base register ($sb).
2742 @item MicroBlaze---@file{config/microblaze/constraints.md}
2745 A general register (@code{r0} to @code{r31}).
2748 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2752 @item MIPS---@file{config/mips/constraints.md}
2755 A general-purpose register. This is equivalent to @code{r} unless
2756 generating MIPS16 code, in which case the MIPS16 register set is used.
2759 A floating-point register (if available).
2762 Formerly the @code{hi} register. This constraint is no longer supported.
2765 The @code{lo} register. Use this register to store values that are
2766 no bigger than a word.
2769 The concatenated @code{hi} and @code{lo} registers. Use this register
2770 to store doubleword values.
2773 A register suitable for use in an indirect jump. This will always be
2774 @code{$25} for @option{-mabicalls}.
2777 Register @code{$3}. Do not use this constraint in new code;
2778 it is retained only for compatibility with glibc.
2781 Equivalent to @code{r}; retained for backwards compatibility.
2784 A floating-point condition code register.
2787 A signed 16-bit constant (for arithmetic instructions).
2793 An unsigned 16-bit constant (for logic instructions).
2796 A signed 32-bit constant in which the lower 16 bits are zero.
2797 Such constants can be loaded using @code{lui}.
2800 A constant that cannot be loaded using @code{lui}, @code{addiu}
2804 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2807 A signed 15-bit constant.
2810 A constant in the range 1 to 65535 (inclusive).
2813 Floating-point zero.
2816 An address that can be used in a non-macro load or store.
2819 A memory operand whose address is formed by a base register and offset
2820 that is suitable for use in instructions with the same addressing mode
2821 as @code{ll} and @code{sc}.
2824 An address suitable for a @code{prefetch} instruction, or for any other
2825 instruction with the same addressing mode as @code{prefetch}.
2828 @item Motorola 680x0---@file{config/m68k/constraints.md}
2837 68881 floating-point register, if available
2840 Integer in the range 1 to 8
2843 16-bit signed number
2846 Signed number whose magnitude is greater than 0x80
2849 Integer in the range @minus{}8 to @minus{}1
2852 Signed number whose magnitude is greater than 0x100
2855 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2858 16 (for rotate using swap)
2861 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2864 Numbers that mov3q can handle
2867 Floating point constant that is not a 68881 constant
2870 Operands that satisfy 'm' when -mpcrel is in effect
2873 Operands that satisfy 's' when -mpcrel is not in effect
2876 Address register indirect addressing mode
2879 Register offset addressing
2894 Range of signed numbers that don't fit in 16 bits
2897 Integers valid for mvq
2900 Integers valid for a moveq followed by a swap
2903 Integers valid for mvz
2906 Integers valid for mvs
2912 Non-register operands allowed in clr
2916 @item Moxie---@file{config/moxie/constraints.md}
2925 A register indirect memory operand
2928 A constant in the range of 0 to 255.
2931 A constant in the range of 0 to @minus{}255.
2935 @item MSP430--@file{config/msp430/constraints.md}
2948 Integer constant -1^20..1^19.
2951 Integer constant 1-4.
2954 Memory references which do not require an extended MOVX instruction.
2957 Memory reference, labels only.
2960 Memory reference, stack only.
2964 @item NDS32---@file{config/nds32/constraints.md}
2967 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
2969 LOW register class $r0 to $r7.
2971 MIDDLE register class $r0 to $r11, $r16 to $r19.
2973 HIGH register class $r12 to $r14, $r20 to $r31.
2975 Temporary assist register $ta (i.e.@: $r15).
2979 Unsigned immediate 3-bit value.
2981 Negative immediate 3-bit value in the range of @minus{}7--0.
2983 Unsigned immediate 4-bit value.
2985 Signed immediate 5-bit value.
2987 Unsigned immediate 5-bit value.
2989 Negative immediate 5-bit value in the range of @minus{}31--0.
2991 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
2993 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
2995 Unsigned immediate 8-bit value.
2997 Unsigned immediate 9-bit value.
2999 Signed immediate 10-bit value.
3001 Signed immediate 11-bit value.
3003 Signed immediate 15-bit value.
3005 Unsigned immediate 15-bit value.
3007 A constant which is not in the range of imm15u but ok for bclr instruction.
3009 A constant which is not in the range of imm15u but ok for bset instruction.
3011 A constant which is not in the range of imm15u but ok for btgl instruction.
3013 A constant whose compliment value is in the range of imm15u
3014 and ok for bitci instruction.
3016 Signed immediate 16-bit value.
3018 Signed immediate 17-bit value.
3020 Signed immediate 19-bit value.
3022 Signed immediate 20-bit value.
3024 The immediate value that can be simply set high 20-bit.
3026 The immediate value 0xff.
3028 The immediate value 0xffff.
3030 The immediate value 0x01.
3032 The immediate value 0x7ff.
3034 The immediate value with power of 2.
3036 The immediate value with power of 2 minus 1.
3038 Memory constraint for 333 format.
3040 Memory constraint for 45 format.
3042 Memory constraint for 37 format.
3045 @item Nios II family---@file{config/nios2/constraints.md}
3049 Integer that is valid as an immediate operand in an
3050 instruction taking a signed 16-bit number. Range
3051 @minus{}32768 to 32767.
3054 Integer that is valid as an immediate operand in an
3055 instruction taking an unsigned 16-bit number. Range
3059 Integer that is valid as an immediate operand in an
3060 instruction taking only the upper 16-bits of a
3061 32-bit number. Range 32-bit numbers with the lower
3065 Integer that is valid as an immediate operand for a
3066 shift instruction. Range 0 to 31.
3069 Integer that is valid as an immediate operand for
3070 only the value 0. Can be used in conjunction with
3071 the format modifier @code{z} to use @code{r0}
3072 instead of @code{0} in the assembly output.
3075 Integer that is valid as an immediate operand for
3076 a custom instruction opcode. Range 0 to 255.
3079 An immediate operand for R2 andchi/andci instructions.
3082 Matches immediates which are addresses in the small
3083 data section and therefore can be added to @code{gp}
3084 as a 16-bit immediate to re-create their 32-bit value.
3087 Matches constants suitable as an operand for the rdprs and
3091 A memory operand suitable for Nios II R2 load/store
3092 exclusive instructions.
3095 A memory operand suitable for load/store IO and cache
3100 A @code{const} wrapped @code{UNSPEC} expression,
3101 representing a supported PIC or TLS relocation.
3106 @item OpenRISC---@file{config/or1k/constraints.md}
3109 Integer that is valid as an immediate operand in an
3110 instruction taking a signed 16-bit number. Range
3111 @minus{}32768 to 32767.
3114 Integer that is valid as an immediate operand in an
3115 instruction taking an unsigned 16-bit number. Range
3119 Signed 16-bit constant shifted left 16 bits. (Used with @code{l.movhi})
3126 Register usable for sibcalls.
3131 @item PDP-11---@file{config/pdp11/constraints.md}
3134 Floating point registers AC0 through AC3. These can be loaded from/to
3135 memory with a single instruction.
3138 Odd numbered general registers (R1, R3, R5). These are used for
3139 16-bit multiply operations.
3142 A memory reference that is encoded within the opcode, but not
3143 auto-increment or auto-decrement.
3146 Any of the floating point registers (AC0 through AC5).
3149 Floating point constant 0.
3152 Floating point registers AC4 and AC5. These cannot be loaded from/to
3153 memory with a single instruction.
3156 An integer constant that fits in 16 bits.
3159 An integer constant whose low order 16 bits are zero.
3162 An integer constant that does not meet the constraints for codes
3163 @samp{I} or @samp{J}.
3166 The integer constant 1.
3169 The integer constant @minus{}1.
3172 The integer constant 0.
3175 Integer constants 0 through 3; shifts by these
3176 amounts are handled as multiple single-bit shifts rather than a single
3177 variable-length shift.
3180 A memory reference which requires an additional word (address or
3181 offset) after the opcode.
3184 A memory reference that is encoded within the opcode.
3188 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
3191 A general purpose register (GPR), @code{r0}@dots{}@code{r31}.
3194 A base register. Like @code{r}, but @code{r0} is not allowed, so
3195 @code{r1}@dots{}@code{r31}.
3198 A floating point register (FPR), @code{f0}@dots{}@code{f31}.
3201 A floating point register. This is the same as @code{f} nowadays;
3202 historically @code{f} was for single-precision and @code{d} was for
3203 double-precision floating point.
3206 An Altivec vector register (VR), @code{v0}@dots{}@code{v31}.
3209 A VSX register (VSR), @code{vs0}@dots{}@code{vs63}. This is either an
3210 FPR (@code{vs0}@dots{}@code{vs31} are @code{f0}@dots{}@code{f31}) or a VR
3211 (@code{vs32}@dots{}@code{vs63} are @code{v0}@dots{}@code{v31}).
3213 When using @code{wa}, you should use the @code{%x} output modifier, so that
3214 the correct register number is printed. For example:
3217 asm ("xvadddp %x0,%x1,%x2"
3219 : "wa" (v2), "wa" (v3));
3222 You should not use @code{%x} for @code{v} operands:
3225 asm ("xsaddqp %0,%1,%2"
3227 : "v" (v2), "v" (v3));
3232 A special register (@code{vrsave}, @code{ctr}, or @code{lr}).
3236 The count register, @code{ctr}.
3239 The link register, @code{lr}.
3242 Condition register field 0, @code{cr0}.
3245 Any condition register field, @code{cr0}@dots{}@code{cr7}.
3249 The carry bit, @code{XER[CA]}.
3252 Like @code{wa}, if @option{-mpower9-vector} and @option{-m64} are used;
3253 otherwise, @code{NO_REGS}.
3256 No register (@code{NO_REGS}).
3259 Like @code{r}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.
3262 Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, @code{NO_REGS}.
3265 Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.
3268 Signed 5-bit constant integer that can be loaded into an Altivec register.
3271 Int constant that is the element number of the 64-bit scalar in a vector.
3274 Vector constant that can be loaded with the XXSPLTIB instruction.
3277 Memory operand suitable for power8 GPR load fusion.
3280 Int constant that is the element number mfvsrld accesses in a vector.
3283 Match vector constant with all 1's if the XXLORC instruction is available.
3286 Memory operand suitable for the ISA 3.0 vector d-form instructions.
3289 Memory operand suitable for the load/store quad instructions.
3292 Vector constant that can be loaded with XXSPLTIB & sign extension.
3295 A memory operand for a DS-form instruction.
3298 An indexed or indirect memory operand, ignoring the bottom 4 bits.
3302 A signed 16-bit constant.
3305 An unsigned 16-bit constant shifted left 16 bits (use @code{L} instead
3306 for @code{SImode} constants).
3309 An unsigned 16-bit constant.
3312 A signed 16-bit constant shifted left 16 bits.
3316 An integer constant greater than 31.
3319 An exact power of 2.
3322 The integer constant zero.
3325 A constant whose negation is a signed 16-bit constant.
3329 A signed 34-bit integer constant if prefixed instructions are supported.
3333 A floating point constant that can be loaded into a register with one
3334 instruction per word.
3337 A floating point constant that can be loaded into a register using
3343 Normally, @code{m} does not allow addresses that update the base register.
3344 If the @code{<} or @code{>} constraint is also used, they are allowed and
3345 therefore on PowerPC targets in that case it is only safe
3346 to use @code{m<>} in an @code{asm} statement if that @code{asm} statement
3347 accesses the operand exactly once. The @code{asm} statement must also
3348 use @code{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
3349 corresponding load or store instruction. For example:
3352 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
3358 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
3365 A ``stable'' memory operand; that is, one which does not include any
3366 automodification of the base register. This used to be useful when
3367 @code{m} allowed automodification of the base register, but as those
3368 are now only allowed when @code{<} or @code{>} is used, @code{es} is
3369 basically the same as @code{m} without @code{<} and @code{>}.
3373 A memory operand addressed by just a base register.
3377 A memory operand for a DQ-form instruction.
3381 A memory operand accessed with indexed or indirect addressing.
3389 An indexed or indirect address.
3393 A V.4 small data reference.
3396 A vector constant that does not require memory.
3399 The zero vector constant.
3404 @item PRU---@file{config/pru/constraints.md}
3407 An unsigned 8-bit integer constant.
3410 An unsigned 16-bit integer constant.
3413 An unsigned 5-bit integer constant (for shift counts).
3416 A text segment (program memory) constant label.
3419 Integer constant zero.
3423 @item RL78---@file{config/rl78/constraints.md}
3427 An integer constant in the range 1 @dots{} 7.
3429 An integer constant in the range 0 @dots{} 255.
3431 An integer constant in the range @minus{}255 @dots{} 0
3433 The integer constant 1.
3435 The integer constant -1.
3437 The integer constant 0.
3439 The integer constant 2.
3441 The integer constant -2.
3443 An integer constant in the range 1 @dots{} 15.
3445 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3447 The synthetic compare types--gt, lt, ge, and le.
3449 A memory reference with an absolute address.
3451 A memory reference using @code{BC} as a base register, with an optional offset.
3453 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3455 A memory reference using any 16-bit register pair for the address, for calls.
3457 A memory reference using @code{DE} as a base register, with an optional offset.
3459 A memory reference using @code{DE} as a base register, without any offset.
3461 Any memory reference to an address in the far address space.
3463 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3465 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3467 A memory reference using @code{HL} as a base register, without any offset.
3469 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3471 Any memory reference to an address in the near address space.
3473 The @code{AX} register.
3475 The @code{BC} register.
3477 The @code{DE} register.
3479 @code{A} through @code{L} registers.
3481 The @code{SP} register.
3483 The @code{HL} register.
3485 The 16-bit @code{R8} register.
3487 The 16-bit @code{R10} register.
3489 The registers reserved for interrupts (@code{R24} to @code{R31}).
3491 The @code{A} register.
3493 The @code{B} register.
3495 The @code{C} register.
3497 The @code{D} register.
3499 The @code{E} register.
3501 The @code{H} register.
3503 The @code{L} register.
3505 The virtual registers.
3507 The @code{PSW} register.
3509 The @code{X} register.
3513 @item RISC-V---@file{config/riscv/constraints.md}
3517 A floating-point register (if available).
3520 An I-type 12-bit signed immediate.
3526 A 5-bit unsigned immediate for CSR access instructions.
3529 An address that is held in a general-purpose register.
3533 @item RX---@file{config/rx/constraints.md}
3536 An address which does not involve register indirect addressing or
3537 pre/post increment/decrement addressing.
3543 A constant in the range @minus{}256 to 255, inclusive.
3546 A constant in the range @minus{}128 to 127, inclusive.
3549 A constant in the range @minus{}32768 to 32767, inclusive.
3552 A constant in the range @minus{}8388608 to 8388607, inclusive.
3555 A constant in the range 0 to 15, inclusive.
3559 @item S/390 and zSeries---@file{config/s390/s390.h}
3562 Address register (general purpose register except r0)
3565 Condition code register
3568 Data register (arbitrary general purpose register)
3571 Floating-point register
3574 Unsigned 8-bit constant (0--255)
3577 Unsigned 12-bit constant (0--4095)
3580 Signed 16-bit constant (@minus{}32768--32767)
3583 Value appropriate as displacement.
3586 for short displacement
3587 @item (@minus{}524288..524287)
3588 for long displacement
3592 Constant integer with a value of 0x7fffffff.
3595 Multiple letter constraint followed by 4 parameter letters.
3598 number of the part counting from most to least significant
3602 mode of the containing operand
3604 value of the other parts (F---all bits set)
3606 The constraint matches if the specified part of a constant
3607 has a value different from its other parts.
3610 Memory reference without index register and with short displacement.
3613 Memory reference with index register and short displacement.
3616 Memory reference without index register but with long displacement.
3619 Memory reference with index register and long displacement.
3622 Pointer with short displacement.
3625 Pointer with long displacement.
3628 Shift count operand.
3633 @item SPARC---@file{config/sparc/sparc.h}
3636 Floating-point register on the SPARC-V8 architecture and
3637 lower floating-point register on the SPARC-V9 architecture.
3640 Floating-point register. It is equivalent to @samp{f} on the
3641 SPARC-V8 architecture and contains both lower and upper
3642 floating-point registers on the SPARC-V9 architecture.
3645 Floating-point condition code register.
3648 Lower floating-point register. It is only valid on the SPARC-V9
3649 architecture when the Visual Instruction Set is available.
3652 Floating-point register. It is only valid on the SPARC-V9 architecture
3653 when the Visual Instruction Set is available.
3656 64-bit global or out register for the SPARC-V8+ architecture.
3659 The constant all-ones, for floating-point.
3662 Signed 5-bit constant
3668 Signed 13-bit constant
3674 32-bit constant with the low 12 bits clear (a constant that can be
3675 loaded with the @code{sethi} instruction)
3678 A constant in the range supported by @code{movcc} instructions (11-bit
3682 A constant in the range supported by @code{movrcc} instructions (10-bit
3686 Same as @samp{K}, except that it verifies that bits that are not in the
3687 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3688 modes wider than @code{SImode}
3697 Signed 13-bit constant, sign-extended to 32 or 64 bits
3703 Floating-point constant whose integral representation can
3704 be moved into an integer register using a single sethi
3708 Floating-point constant whose integral representation can
3709 be moved into an integer register using a single mov
3713 Floating-point constant whose integral representation can
3714 be moved into an integer register using a high/lo_sum
3715 instruction sequence
3718 Memory address aligned to an 8-byte boundary
3724 Memory address for @samp{e} constraint registers
3727 Memory address with only a base register
3734 @item TI C6X family---@file{config/c6x/constraints.md}
3737 Register file A (A0--A31).
3740 Register file B (B0--B31).
3743 Predicate registers in register file A (A0--A2 on C64X and
3744 higher, A1 and A2 otherwise).
3747 Predicate registers in register file B (B0--B2).
3750 A call-used register in register file B (B0--B9, B16--B31).
3753 Register file A, excluding predicate registers (A3--A31,
3754 plus A0 if not C64X or higher).
3757 Register file B, excluding predicate registers (B3--B31).
3760 Integer constant in the range 0 @dots{} 15.
3763 Integer constant in the range 0 @dots{} 31.
3766 Integer constant in the range @minus{}31 @dots{} 0.
3769 Integer constant in the range @minus{}16 @dots{} 15.
3772 Integer constant that can be the operand of an ADDA or a SUBA insn.
3775 Integer constant in the range 0 @dots{} 65535.
3778 Integer constant in the range @minus{}32768 @dots{} 32767.
3781 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3784 Integer constant that is a valid mask for the clr instruction.
3787 Integer constant that is a valid mask for the set instruction.
3790 Memory location with A base register.
3793 Memory location with B base register.
3797 On C64x+ targets, a GP-relative small data reference.
3800 Any kind of @code{SYMBOL_REF}, for use in a call address.
3803 Any kind of immediate operand, unless it matches the S0 constraint.
3806 Memory location with B base register, but not using a long offset.
3809 A memory operand with an address that cannot be used in an unaligned access.
3813 Register B14 (aka DP).
3817 @item TILE-Gx---@file{config/tilegx/constraints.md}
3830 Each of these represents a register constraint for an individual
3831 register, from r0 to r10.
3834 Signed 8-bit integer constant.
3837 Signed 16-bit integer constant.
3840 Unsigned 16-bit integer constant.
3843 Integer constant that fits in one signed byte when incremented by one
3844 (@minus{}129 @dots{} 126).
3847 Memory operand. If used together with @samp{<} or @samp{>}, the
3848 operand can have postincrement which requires printing with @samp{%In}
3849 and @samp{%in} on TILE-Gx. For example:
3852 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3856 A bit mask suitable for the BFINS instruction.
3859 Integer constant that is a byte tiled out eight times.
3862 The integer zero constant.
3865 Integer constant that is a sign-extended byte tiled out as four shorts.
3868 Integer constant that fits in one signed byte when incremented
3869 (@minus{}129 @dots{} 126), but excluding -1.
3872 Integer constant that has all 1 bits consecutive and starting at bit 0.
3875 A 16-bit fragment of a got, tls, or pc-relative reference.
3878 Memory operand except postincrement. This is roughly the same as
3879 @samp{m} when not used together with @samp{<} or @samp{>}.
3882 An 8-element vector constant with identical elements.
3885 A 4-element vector constant with identical elements.
3888 The integer constant 0xffffffff.
3891 The integer constant 0xffffffff00000000.
3895 @item TILEPro---@file{config/tilepro/constraints.md}
3908 Each of these represents a register constraint for an individual
3909 register, from r0 to r10.
3912 Signed 8-bit integer constant.
3915 Signed 16-bit integer constant.
3918 Nonzero integer constant with low 16 bits zero.
3921 Integer constant that fits in one signed byte when incremented by one
3922 (@minus{}129 @dots{} 126).
3925 Memory operand. If used together with @samp{<} or @samp{>}, the
3926 operand can have postincrement which requires printing with @samp{%In}
3927 and @samp{%in} on TILEPro. For example:
3930 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
3934 A bit mask suitable for the MM instruction.
3937 Integer constant that is a byte tiled out four times.
3940 The integer zero constant.
3943 Integer constant that is a sign-extended byte tiled out as two shorts.
3946 Integer constant that fits in one signed byte when incremented
3947 (@minus{}129 @dots{} 126), but excluding -1.
3950 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
3954 Memory operand except postincrement. This is roughly the same as
3955 @samp{m} when not used together with @samp{<} or @samp{>}.
3958 A 4-element vector constant with identical elements.
3961 A 2-element vector constant with identical elements.
3965 @item Visium---@file{config/visium/constraints.md}
3968 EAM register @code{mdb}
3971 EAM register @code{mdc}
3974 Floating point register
3978 Register for sibcall optimization
3982 General register, but not @code{r29}, @code{r30} and @code{r31}
3994 Floating-point constant 0.0
3997 Integer constant in the range 0 .. 65535 (16-bit immediate)
4000 Integer constant in the range 1 .. 31 (5-bit immediate)
4003 Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
4006 Integer constant @minus{}1
4015 @item x86 family---@file{config/i386/constraints.md}
4018 Legacy register---the eight integer registers available on all
4019 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
4020 @code{si}, @code{di}, @code{bp}, @code{sp}).
4023 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
4024 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
4027 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
4028 @code{c}, and @code{d}.
4032 Any register that can be used as the index in a base+index memory
4033 access: that is, any general register except the stack pointer.
4037 The @code{a} register.
4040 The @code{b} register.
4043 The @code{c} register.
4046 The @code{d} register.
4049 The @code{si} register.
4052 The @code{di} register.
4055 The @code{a} and @code{d} registers. This class is used for instructions
4056 that return double word results in the @code{ax:dx} register pair. Single
4057 word values will be allocated either in @code{ax} or @code{dx}.
4058 For example on i386 the following implements @code{rdtsc}:
4061 unsigned long long rdtsc (void)
4063 unsigned long long tick;
4064 __asm__ __volatile__("rdtsc":"=A"(tick));
4069 This is not correct on x86-64 as it would allocate tick in either @code{ax}
4070 or @code{dx}. You have to use the following variant instead:
4073 unsigned long long rdtsc (void)
4075 unsigned int tickl, tickh;
4076 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
4077 return ((unsigned long long)tickh << 32)|tickl;
4082 The call-clobbered integer registers.
4085 Any 80387 floating-point (stack) register.
4088 Top of 80387 floating-point stack (@code{%st(0)}).
4091 Second from top of 80387 floating-point stack (@code{%st(1)}).
4095 Any mask register that can be used as a predicate, i.e.@: @code{k1-k7}.
4108 Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).
4116 First SSE register (@code{%xmm0}).
4120 Any SSE register, when SSE2 and inter-unit moves are enabled.
4123 Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.
4126 Any MMX register, when inter-unit moves are enabled.
4129 Any MMX register, when inter-unit moves from vector registers are enabled.
4132 Any integer register when @code{TARGET_PARTIAL_REG_STALL} is disabled.
4135 Any integer register when zero extensions with @code{AND} are disabled.
4138 Any register that can be used as the GOT base when calling@*
4139 @code{___tls_get_addr}: that is, any general register except @code{a}
4140 and @code{sp} registers, for @option{-fno-plt} if linker supports it.
4141 Otherwise, @code{b} register.
4144 Any x87 register when 80387 floating-point arithmetic is enabled.
4147 Lower SSE register when avoiding REX prefix and all SSE registers otherwise.
4150 For AVX512VL, any EVEX-encodable SSE register (@code{%xmm0-%xmm31}),
4151 otherwise any SSE register.
4154 Any EVEX-encodable SSE register, that has number factor of four.
4157 Flags register operand.
4163 Vector memory operand.
4166 Constant memory operand.
4169 Memory operand without REX prefix.
4172 Sibcall memory operand.
4175 Call memory operand.
4178 Constant call address operand.
4181 SSE constant -1 operand.
4185 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
4188 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
4191 Signed 8-bit integer constant.
4194 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
4197 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
4200 Unsigned 8-bit integer constant (for @code{in} and @code{out}
4205 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
4209 Standard 80387 floating point constant.
4212 SSE constant zero operand.
4215 32-bit signed integer constant, or a symbolic reference known
4216 to fit that range (for immediate operands in sign-extending x86-64
4220 32-bit signed integer constant, or a symbolic reference known
4221 to fit that range (for sign-extending conversion operations that
4222 require non-@code{VOIDmode} immediate operands).
4225 32-bit unsigned integer constant, or a symbolic reference known
4226 to fit that range (for zero-extending conversion operations that
4227 require non-@code{VOIDmode} immediate operands).
4230 128-bit integer constant where both the high and low 64-bit word
4231 satisfy the @code{e} constraint.
4234 32-bit unsigned integer constant, or a symbolic reference known
4235 to fit that range (for immediate operands in zero-extending x86-64
4239 VSIB address operand.
4242 Address operand without segment register.
4246 @item Xstormy16---@file{config/stormy16/stormy16.h}
4261 Registers r0 through r7.
4264 Registers r0 and r1.
4270 Registers r8 and r9.
4273 A constant between 0 and 3 inclusive.
4276 A constant that has exactly one bit set.
4279 A constant that has exactly one bit clear.
4282 A constant between 0 and 255 inclusive.
4285 A constant between @minus{}255 and 0 inclusive.
4288 A constant between @minus{}3 and 0 inclusive.
4291 A constant between 1 and 4 inclusive.
4294 A constant between @minus{}4 and @minus{}1 inclusive.
4297 A memory reference that is a stack push.
4300 A memory reference that is a stack pop.
4303 A memory reference that refers to a constant address of known value.
4306 The register indicated by Rx (not implemented yet).
4309 A constant that is not between 2 and 15 inclusive.
4316 @item Xtensa---@file{config/xtensa/constraints.md}
4319 General-purpose 32-bit register
4322 One-bit boolean register
4325 MAC16 40-bit accumulator register
4328 Signed 12-bit integer constant, for use in MOVI instructions
4331 Signed 8-bit integer constant, for use in ADDI instructions
4334 Integer constant valid for BccI instructions
4337 Unsigned constant valid for BccUI instructions
4344 @node Disable Insn Alternatives
4345 @subsection Disable insn alternatives using the @code{enabled} attribute
4348 There are three insn attributes that may be used to selectively disable
4349 instruction alternatives:
4353 Says whether an alternative is available on the current subtarget.
4355 @item preferred_for_size
4356 Says whether an enabled alternative should be used in code that is
4359 @item preferred_for_speed
4360 Says whether an enabled alternative should be used in code that is
4361 optimized for speed.
4364 All these attributes should use @code{(const_int 1)} to allow an alternative
4365 or @code{(const_int 0)} to disallow it. The attributes must be a static
4366 property of the subtarget; they cannot for example depend on the
4367 current operands, on the current optimization level, on the location
4368 of the insn within the body of a loop, on whether register allocation
4369 has finished, or on the current compiler pass.
4371 The @code{enabled} attribute is a correctness property. It tells GCC to act
4372 as though the disabled alternatives were never defined in the first place.
4373 This is useful when adding new instructions to an existing pattern in
4374 cases where the new instructions are only available for certain cpu
4375 architecture levels (typically mapped to the @code{-march=} command-line
4378 In contrast, the @code{preferred_for_size} and @code{preferred_for_speed}
4379 attributes are strong optimization hints rather than correctness properties.
4380 @code{preferred_for_size} tells GCC which alternatives to consider when
4381 adding or modifying an instruction that GCC wants to optimize for size.
4382 @code{preferred_for_speed} does the same thing for speed. Note that things
4383 like code motion can lead to cases where code optimized for size uses
4384 alternatives that are not preferred for size, and similarly for speed.
4386 Although @code{define_insn}s can in principle specify the @code{enabled}
4387 attribute directly, it is often clearer to have subsiduary attributes
4388 for each architectural feature of interest. The @code{define_insn}s
4389 can then use these subsiduary attributes to say which alternatives
4390 require which features. The example below does this for @code{cpu_facility}.
4392 E.g. the following two patterns could easily be merged using the @code{enabled}
4397 (define_insn "*movdi_old"
4398 [(set (match_operand:DI 0 "register_operand" "=d")
4399 (match_operand:DI 1 "register_operand" " d"))]
4403 (define_insn "*movdi_new"
4404 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4405 (match_operand:DI 1 "register_operand" " d,d,f"))]
4418 (define_insn "*movdi_combined"
4419 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4420 (match_operand:DI 1 "register_operand" " d,d,f"))]
4426 [(set_attr "cpu_facility" "*,new,new")])
4430 with the @code{enabled} attribute defined like this:
4434 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4436 (define_attr "enabled" ""
4437 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4438 (and (eq_attr "cpu_facility" "new")
4439 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4448 @node Define Constraints
4449 @subsection Defining Machine-Specific Constraints
4450 @cindex defining constraints
4451 @cindex constraints, defining
4453 Machine-specific constraints fall into two categories: register and
4454 non-register constraints. Within the latter category, constraints
4455 which allow subsets of all possible memory or address operands should
4456 be specially marked, to give @code{reload} more information.
4458 Machine-specific constraints can be given names of arbitrary length,
4459 but they must be entirely composed of letters, digits, underscores
4460 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4461 must begin with a letter or underscore.
4463 In order to avoid ambiguity in operand constraint strings, no
4464 constraint can have a name that begins with any other constraint's
4465 name. For example, if @code{x} is defined as a constraint name,
4466 @code{xy} may not be, and vice versa. As a consequence of this rule,
4467 no constraint may begin with one of the generic constraint letters:
4468 @samp{E F V X g i m n o p r s}.
4470 Register constraints correspond directly to register classes.
4471 @xref{Register Classes}. There is thus not much flexibility in their
4474 @deffn {MD Expression} define_register_constraint name regclass docstring
4475 All three arguments are string constants.
4476 @var{name} is the name of the constraint, as it will appear in
4477 @code{match_operand} expressions. If @var{name} is a multi-letter
4478 constraint its length shall be the same for all constraints starting
4479 with the same letter. @var{regclass} can be either the
4480 name of the corresponding register class (@pxref{Register Classes}),
4481 or a C expression which evaluates to the appropriate register class.
4482 If it is an expression, it must have no side effects, and it cannot
4483 look at the operand. The usual use of expressions is to map some
4484 register constraints to @code{NO_REGS} when the register class
4485 is not available on a given subarchitecture.
4487 @var{docstring} is a sentence documenting the meaning of the
4488 constraint. Docstrings are explained further below.
4491 Non-register constraints are more like predicates: the constraint
4492 definition gives a boolean expression which indicates whether the
4495 @deffn {MD Expression} define_constraint name docstring exp
4496 The @var{name} and @var{docstring} arguments are the same as for
4497 @code{define_register_constraint}, but note that the docstring comes
4498 immediately after the name for these expressions. @var{exp} is an RTL
4499 expression, obeying the same rules as the RTL expressions in predicate
4500 definitions. @xref{Defining Predicates}, for details. If it
4501 evaluates true, the constraint matches; if it evaluates false, it
4502 doesn't. Constraint expressions should indicate which RTL codes they
4503 might match, just like predicate expressions.
4505 @code{match_test} C expressions have access to the
4506 following variables:
4510 The RTL object defining the operand.
4512 The machine mode of @var{op}.
4514 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4516 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4517 @code{const_double}.
4519 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4520 @code{const_double}.
4522 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4523 @code{const_double}.
4526 The @var{*val} variables should only be used once another piece of the
4527 expression has verified that @var{op} is the appropriate kind of RTL
4531 Most non-register constraints should be defined with
4532 @code{define_constraint}. The remaining two definition expressions
4533 are only appropriate for constraints that should be handled specially
4534 by @code{reload} if they fail to match.
4536 @deffn {MD Expression} define_memory_constraint name docstring exp
4537 Use this expression for constraints that match a subset of all memory
4538 operands: that is, @code{reload} can make them match by converting the
4539 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4540 base register (from the register class specified by
4541 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4543 For example, on the S/390, some instructions do not accept arbitrary
4544 memory references, but only those that do not make use of an index
4545 register. The constraint letter @samp{Q} is defined to represent a
4546 memory address of this type. If @samp{Q} is defined with
4547 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4548 memory operand, because @code{reload} knows it can simply copy the
4549 memory address into a base register if required. This is analogous to
4550 the way an @samp{o} constraint can handle any memory operand.
4552 The syntax and semantics are otherwise identical to
4553 @code{define_constraint}.
4556 @deffn {MD Expression} define_special_memory_constraint name docstring exp
4557 Use this expression for constraints that match a subset of all memory
4558 operands: that is, @code{reload} cannot make them match by reloading
4559 the address as it is described for @code{define_memory_constraint} or
4560 such address reload is undesirable with the performance point of view.
4562 For example, @code{define_special_memory_constraint} can be useful if
4563 specifically aligned memory is necessary or desirable for some insn
4566 The syntax and semantics are otherwise identical to
4567 @code{define_constraint}.
4570 @deffn {MD Expression} define_address_constraint name docstring exp
4571 Use this expression for constraints that match a subset of all address
4572 operands: that is, @code{reload} can make the constraint match by
4573 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4574 with @var{X} a base register.
4576 Constraints defined with @code{define_address_constraint} can only be
4577 used with the @code{address_operand} predicate, or machine-specific
4578 predicates that work the same way. They are treated analogously to
4579 the generic @samp{p} constraint.
4581 The syntax and semantics are otherwise identical to
4582 @code{define_constraint}.
4585 For historical reasons, names beginning with the letters @samp{G H}
4586 are reserved for constraints that match only @code{const_double}s, and
4587 names beginning with the letters @samp{I J K L M N O P} are reserved
4588 for constraints that match only @code{const_int}s. This may change in
4589 the future. For the time being, constraints with these names must be
4590 written in a stylized form, so that @code{genpreds} can tell you did
4595 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4597 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4598 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4601 @c the semicolons line up in the formatted manual
4603 It is fine to use names beginning with other letters for constraints
4604 that match @code{const_double}s or @code{const_int}s.
4606 Each docstring in a constraint definition should be one or more complete
4607 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4608 In the future they will be copied into the GCC manual, in @ref{Machine
4609 Constraints}, replacing the hand-maintained tables currently found in
4610 that section. Also, in the future the compiler may use this to give
4611 more helpful diagnostics when poor choice of @code{asm} constraints
4612 causes a reload failure.
4614 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4615 beginning of a docstring, then (in the future) it will appear only in
4616 the internals manual's version of the machine-specific constraint tables.
4617 Use this for constraints that should not appear in @code{asm} statements.
4619 @node C Constraint Interface
4620 @subsection Testing constraints from C
4621 @cindex testing constraints
4622 @cindex constraints, testing
4624 It is occasionally useful to test a constraint from C code rather than
4625 implicitly via the constraint string in a @code{match_operand}. The
4626 generated file @file{tm_p.h} declares a few interfaces for working
4627 with constraints. At present these are defined for all constraints
4628 except @code{g} (which is equivalent to @code{general_operand}).
4630 Some valid constraint names are not valid C identifiers, so there is a
4631 mangling scheme for referring to them from C@. Constraint names that
4632 do not contain angle brackets or underscores are left unchanged.
4633 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4634 each @samp{>} with @samp{_g}. Here are some examples:
4636 @c the @c's prevent double blank lines in the printed manual.
4638 @multitable {Original} {Mangled}
4639 @item @strong{Original} @tab @strong{Mangled} @c
4640 @item @code{x} @tab @code{x} @c
4641 @item @code{P42x} @tab @code{P42x} @c
4642 @item @code{P4_x} @tab @code{P4__x} @c
4643 @item @code{P4>x} @tab @code{P4_gx} @c
4644 @item @code{P4>>} @tab @code{P4_g_g} @c
4645 @item @code{P4_g>} @tab @code{P4__g_g} @c
4649 Throughout this section, the variable @var{c} is either a constraint
4650 in the abstract sense, or a constant from @code{enum constraint_num};
4651 the variable @var{m} is a mangled constraint name (usually as part of
4652 a larger identifier).
4654 @deftp Enum constraint_num
4655 For each constraint except @code{g}, there is a corresponding
4656 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4657 constraint. Functions that take an @code{enum constraint_num} as an
4658 argument expect one of these constants.
4661 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4662 For each non-register constraint @var{m} except @code{g}, there is
4663 one of these functions; it returns @code{true} if @var{exp} satisfies the
4664 constraint. These functions are only visible if @file{rtl.h} was included
4665 before @file{tm_p.h}.
4668 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4669 Like the @code{satisfies_constraint_@var{m}} functions, but the
4670 constraint to test is given as an argument, @var{c}. If @var{c}
4671 specifies a register constraint, this function will always return
4675 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4676 Returns the register class associated with @var{c}. If @var{c} is not
4677 a register constraint, or those registers are not available for the
4678 currently selected subtarget, returns @code{NO_REGS}.
4681 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4682 peephole optimizations (@pxref{Peephole Definitions}), operand
4683 constraint strings are ignored, so if there are relevant constraints,
4684 they must be tested in the C condition. In the example, the
4685 optimization is applied if operand 2 does @emph{not} satisfy the
4686 @samp{K} constraint. (This is a simplified version of a peephole
4687 definition from the i386 machine description.)
4691 [(match_scratch:SI 3 "r")
4692 (set (match_operand:SI 0 "register_operand" "")
4693 (mult:SI (match_operand:SI 1 "memory_operand" "")
4694 (match_operand:SI 2 "immediate_operand" "")))]
4696 "!satisfies_constraint_K (operands[2])"
4698 [(set (match_dup 3) (match_dup 1))
4699 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4704 @node Standard Names
4705 @section Standard Pattern Names For Generation
4706 @cindex standard pattern names
4707 @cindex pattern names
4708 @cindex names, pattern
4710 Here is a table of the instruction names that are meaningful in the RTL
4711 generation pass of the compiler. Giving one of these names to an
4712 instruction pattern tells the RTL generation pass that it can use the
4713 pattern to accomplish a certain task.
4716 @cindex @code{mov@var{m}} instruction pattern
4717 @item @samp{mov@var{m}}
4718 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4719 This instruction pattern moves data with that machine mode from operand
4720 1 to operand 0. For example, @samp{movsi} moves full-word data.
4722 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4723 own mode is wider than @var{m}, the effect of this instruction is
4724 to store the specified value in the part of the register that corresponds
4725 to mode @var{m}. Bits outside of @var{m}, but which are within the
4726 same target word as the @code{subreg} are undefined. Bits which are
4727 outside the target word are left unchanged.
4729 This class of patterns is special in several ways. First of all, each
4730 of these names up to and including full word size @emph{must} be defined,
4731 because there is no other way to copy a datum from one place to another.
4732 If there are patterns accepting operands in larger modes,
4733 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4735 Second, these patterns are not used solely in the RTL generation pass.
4736 Even the reload pass can generate move insns to copy values from stack
4737 slots into temporary registers. When it does so, one of the operands is
4738 a hard register and the other is an operand that can need to be reloaded
4742 Therefore, when given such a pair of operands, the pattern must generate
4743 RTL which needs no reloading and needs no temporary registers---no
4744 registers other than the operands. For example, if you support the
4745 pattern with a @code{define_expand}, then in such a case the
4746 @code{define_expand} mustn't call @code{force_reg} or any other such
4747 function which might generate new pseudo registers.
4749 This requirement exists even for subword modes on a RISC machine where
4750 fetching those modes from memory normally requires several insns and
4751 some temporary registers.
4753 @findex change_address
4754 During reload a memory reference with an invalid address may be passed
4755 as an operand. Such an address will be replaced with a valid address
4756 later in the reload pass. In this case, nothing may be done with the
4757 address except to use it as it stands. If it is copied, it will not be
4758 replaced with a valid address. No attempt should be made to make such
4759 an address into a valid address and no routine (such as
4760 @code{change_address}) that will do so may be called. Note that
4761 @code{general_operand} will fail when applied to such an address.
4763 @findex reload_in_progress
4764 The global variable @code{reload_in_progress} (which must be explicitly
4765 declared if required) can be used to determine whether such special
4766 handling is required.
4768 The variety of operands that have reloads depends on the rest of the
4769 machine description, but typically on a RISC machine these can only be
4770 pseudo registers that did not get hard registers, while on other
4771 machines explicit memory references will get optional reloads.
4773 If a scratch register is required to move an object to or from memory,
4774 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4776 If there are cases which need scratch registers during or after reload,
4777 you must provide an appropriate secondary_reload target hook.
4779 @findex can_create_pseudo_p
4780 The macro @code{can_create_pseudo_p} can be used to determine if it
4781 is unsafe to create new pseudo registers. If this variable is nonzero, then
4782 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4784 The constraints on a @samp{mov@var{m}} must permit moving any hard
4785 register to any other hard register provided that
4786 @code{TARGET_HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4787 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4790 It is obligatory to support floating point @samp{mov@var{m}}
4791 instructions into and out of any registers that can hold fixed point
4792 values, because unions and structures (which have modes @code{SImode} or
4793 @code{DImode}) can be in those registers and they may have floating
4796 There may also be a need to support fixed point @samp{mov@var{m}}
4797 instructions in and out of floating point registers. Unfortunately, I
4798 have forgotten why this was so, and I don't know whether it is still
4799 true. If @code{TARGET_HARD_REGNO_MODE_OK} rejects fixed point values in
4800 floating point registers, then the constraints of the fixed point
4801 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4802 reload into a floating point register.
4804 @cindex @code{reload_in} instruction pattern
4805 @cindex @code{reload_out} instruction pattern
4806 @item @samp{reload_in@var{m}}
4807 @itemx @samp{reload_out@var{m}}
4808 These named patterns have been obsoleted by the target hook
4809 @code{secondary_reload}.
4811 Like @samp{mov@var{m}}, but used when a scratch register is required to
4812 move between operand 0 and operand 1. Operand 2 describes the scratch
4813 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4814 macro in @pxref{Register Classes}.
4816 There are special restrictions on the form of the @code{match_operand}s
4817 used in these patterns. First, only the predicate for the reload
4818 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4819 the predicates for operand 0 or 2. Second, there may be only one
4820 alternative in the constraints. Third, only a single register class
4821 letter may be used for the constraint; subsequent constraint letters
4822 are ignored. As a special exception, an empty constraint string
4823 matches the @code{ALL_REGS} register class. This may relieve ports
4824 of the burden of defining an @code{ALL_REGS} constraint letter just
4827 @cindex @code{movstrict@var{m}} instruction pattern
4828 @item @samp{movstrict@var{m}}
4829 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4830 with mode @var{m} of a register whose natural mode is wider,
4831 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4832 any of the register except the part which belongs to mode @var{m}.
4834 @cindex @code{movmisalign@var{m}} instruction pattern
4835 @item @samp{movmisalign@var{m}}
4836 This variant of a move pattern is designed to load or store a value
4837 from a memory address that is not naturally aligned for its mode.
4838 For a store, the memory will be in operand 0; for a load, the memory
4839 will be in operand 1. The other operand is guaranteed not to be a
4840 memory, so that it's easy to tell whether this is a load or store.
4842 This pattern is used by the autovectorizer, and when expanding a
4843 @code{MISALIGNED_INDIRECT_REF} expression.
4845 @cindex @code{load_multiple} instruction pattern
4846 @item @samp{load_multiple}
4847 Load several consecutive memory locations into consecutive registers.
4848 Operand 0 is the first of the consecutive registers, operand 1
4849 is the first memory location, and operand 2 is a constant: the
4850 number of consecutive registers.
4852 Define this only if the target machine really has such an instruction;
4853 do not define this if the most efficient way of loading consecutive
4854 registers from memory is to do them one at a time.
4856 On some machines, there are restrictions as to which consecutive
4857 registers can be stored into memory, such as particular starting or
4858 ending register numbers or only a range of valid counts. For those
4859 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4860 and make the pattern fail if the restrictions are not met.
4862 Write the generated insn as a @code{parallel} with elements being a
4863 @code{set} of one register from the appropriate memory location (you may
4864 also need @code{use} or @code{clobber} elements). Use a
4865 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4866 @file{rs6000.md} for examples of the use of this insn pattern.
4868 @cindex @samp{store_multiple} instruction pattern
4869 @item @samp{store_multiple}
4870 Similar to @samp{load_multiple}, but store several consecutive registers
4871 into consecutive memory locations. Operand 0 is the first of the
4872 consecutive memory locations, operand 1 is the first register, and
4873 operand 2 is a constant: the number of consecutive registers.
4875 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4876 @item @samp{vec_load_lanes@var{m}@var{n}}
4877 Perform an interleaved load of several vectors from memory operand 1
4878 into register operand 0. Both operands have mode @var{m}. The register
4879 operand is viewed as holding consecutive vectors of mode @var{n},
4880 while the memory operand is a flat array that contains the same number
4881 of elements. The operation is equivalent to:
4884 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4885 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4886 for (i = 0; i < c; i++)
4887 operand0[i][j] = operand1[j * c + i];
4890 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4891 from memory into a register of mode @samp{TI}@. The register
4892 contains two consecutive vectors of mode @samp{V4HI}@.
4894 This pattern can only be used if:
4896 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4898 is true. GCC assumes that, if a target supports this kind of
4899 instruction for some mode @var{n}, it also supports unaligned
4900 loads for vectors of mode @var{n}.
4902 This pattern is not allowed to @code{FAIL}.
4904 @cindex @code{vec_mask_load_lanes@var{m}@var{n}} instruction pattern
4905 @item @samp{vec_mask_load_lanes@var{m}@var{n}}
4906 Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional
4907 mask operand (operand 2) that specifies which elements of the destination
4908 vectors should be loaded. Other elements of the destination
4909 vectors are set to zero. The operation is equivalent to:
4912 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4913 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4915 for (i = 0; i < c; i++)
4916 operand0[i][j] = operand1[j * c + i];
4918 for (i = 0; i < c; i++)
4922 This pattern is not allowed to @code{FAIL}.
4924 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4925 @item @samp{vec_store_lanes@var{m}@var{n}}
4926 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4927 and register operands reversed. That is, the instruction is
4931 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4932 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4933 for (i = 0; i < c; i++)
4934 operand0[j * c + i] = operand1[i][j];
4937 for a memory operand 0 and register operand 1.
4939 This pattern is not allowed to @code{FAIL}.
4941 @cindex @code{vec_mask_store_lanes@var{m}@var{n}} instruction pattern
4942 @item @samp{vec_mask_store_lanes@var{m}@var{n}}
4943 Like @samp{vec_store_lanes@var{m}@var{n}}, but takes an additional
4944 mask operand (operand 2) that specifies which elements of the source
4945 vectors should be stored. The operation is equivalent to:
4948 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4949 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4951 for (i = 0; i < c; i++)
4952 operand0[j * c + i] = operand1[i][j];
4955 This pattern is not allowed to @code{FAIL}.
4957 @cindex @code{gather_load@var{m}@var{n}} instruction pattern
4958 @item @samp{gather_load@var{m}@var{n}}
4959 Load several separate memory locations into a vector of mode @var{m}.
4960 Operand 1 is a scalar base address and operand 2 is a vector of mode @var{n}
4961 containing offsets from that base. Operand 0 is a destination vector with
4962 the same number of elements as @var{n}. For each element index @var{i}:
4966 extend the offset element @var{i} to address width, using zero
4967 extension if operand 3 is 1 and sign extension if operand 3 is zero;
4969 multiply the extended offset by operand 4;
4971 add the result to the base; and
4973 load the value at that address into element @var{i} of operand 0.
4976 The value of operand 3 does not matter if the offsets are already
4979 @cindex @code{mask_gather_load@var{m}@var{n}} instruction pattern
4980 @item @samp{mask_gather_load@var{m}@var{n}}
4981 Like @samp{gather_load@var{m}@var{n}}, but takes an extra mask operand as
4982 operand 5. Bit @var{i} of the mask is set if element @var{i}
4983 of the result should be loaded from memory and clear if element @var{i}
4984 of the result should be set to zero.
4986 @cindex @code{scatter_store@var{m}@var{n}} instruction pattern
4987 @item @samp{scatter_store@var{m}@var{n}}
4988 Store a vector of mode @var{m} into several distinct memory locations.
4989 Operand 0 is a scalar base address and operand 1 is a vector of mode
4990 @var{n} containing offsets from that base. Operand 4 is the vector of
4991 values that should be stored, which has the same number of elements as
4992 @var{n}. For each element index @var{i}:
4996 extend the offset element @var{i} to address width, using zero
4997 extension if operand 2 is 1 and sign extension if operand 2 is zero;
4999 multiply the extended offset by operand 3;
5001 add the result to the base; and
5003 store element @var{i} of operand 4 to that address.
5006 The value of operand 2 does not matter if the offsets are already
5009 @cindex @code{mask_scatter_store@var{m}@var{n}} instruction pattern
5010 @item @samp{mask_scatter_store@var{m}@var{n}}
5011 Like @samp{scatter_store@var{m}@var{n}}, but takes an extra mask operand as
5012 operand 5. Bit @var{i} of the mask is set if element @var{i}
5013 of the result should be stored to memory.
5015 @cindex @code{vec_set@var{m}} instruction pattern
5016 @item @samp{vec_set@var{m}}
5017 Set given field in the vector value. Operand 0 is the vector to modify,
5018 operand 1 is new value of field and operand 2 specify the field index.
5020 @cindex @code{vec_extract@var{m}@var{n}} instruction pattern
5021 @item @samp{vec_extract@var{m}@var{n}}
5022 Extract given field from the vector value. Operand 1 is the vector, operand 2
5023 specify field index and operand 0 place to store value into. The
5024 @var{n} mode is the mode of the field or vector of fields that should be
5025 extracted, should be either element mode of the vector mode @var{m}, or
5026 a vector mode with the same element mode and smaller number of elements.
5027 If @var{n} is a vector mode, the index is counted in units of that mode.
5029 @cindex @code{vec_init@var{m}@var{n}} instruction pattern
5030 @item @samp{vec_init@var{m}@var{n}}
5031 Initialize the vector to given values. Operand 0 is the vector to initialize
5032 and operand 1 is parallel containing values for individual fields. The
5033 @var{n} mode is the mode of the elements, should be either element mode of
5034 the vector mode @var{m}, or a vector mode with the same element mode and
5035 smaller number of elements.
5037 @cindex @code{vec_duplicate@var{m}} instruction pattern
5038 @item @samp{vec_duplicate@var{m}}
5039 Initialize vector output operand 0 so that each element has the value given
5040 by scalar input operand 1. The vector has mode @var{m} and the scalar has
5041 the mode appropriate for one element of @var{m}.
5043 This pattern only handles duplicates of non-constant inputs. Constant
5044 vectors go through the @code{mov@var{m}} pattern instead.
5046 This pattern is not allowed to @code{FAIL}.
5048 @cindex @code{vec_series@var{m}} instruction pattern
5049 @item @samp{vec_series@var{m}}
5050 Initialize vector output operand 0 so that element @var{i} is equal to
5051 operand 1 plus @var{i} times operand 2. In other words, create a linear
5052 series whose base value is operand 1 and whose step is operand 2.
5054 The vector output has mode @var{m} and the scalar inputs have the mode
5055 appropriate for one element of @var{m}. This pattern is not used for
5056 floating-point vectors, in order to avoid having to specify the
5057 rounding behavior for @var{i} > 1.
5059 This pattern is not allowed to @code{FAIL}.
5061 @cindex @code{while_ult@var{m}@var{n}} instruction pattern
5062 @item @code{while_ult@var{m}@var{n}}
5063 Set operand 0 to a mask that is true while incrementing operand 1
5064 gives a value that is less than operand 2. Operand 0 has mode @var{n}
5065 and operands 1 and 2 are scalar integers of mode @var{m}.
5066 The operation is equivalent to:
5069 operand0[0] = operand1 < operand2;
5070 for (i = 1; i < GET_MODE_NUNITS (@var{n}); i++)
5071 operand0[i] = operand0[i - 1] && (operand1 + i < operand2);
5074 @cindex @code{check_raw_ptrs@var{m}} instruction pattern
5075 @item @samp{check_raw_ptrs@var{m}}
5076 Check whether, given two pointers @var{a} and @var{b} and a length @var{len},
5077 a write of @var{len} bytes at @var{a} followed by a read of @var{len} bytes
5078 at @var{b} can be split into interleaved byte accesses
5079 @samp{@var{a}[0], @var{b}[0], @var{a}[1], @var{b}[1], @dots{}}
5080 without affecting the dependencies between the bytes. Set operand 0
5081 to true if the split is possible and false otherwise.
5083 Operands 1, 2 and 3 provide the values of @var{a}, @var{b} and @var{len}
5084 respectively. Operand 4 is a constant integer that provides the known
5085 common alignment of @var{a} and @var{b}. All inputs have mode @var{m}.
5087 This split is possible if:
5090 @var{a} == @var{b} || @var{a} + @var{len} <= @var{b} || @var{b} + @var{len} <= @var{a}
5093 You should only define this pattern if the target has a way of accelerating
5094 the test without having to do the individual comparisons.
5096 @cindex @code{check_war_ptrs@var{m}} instruction pattern
5097 @item @samp{check_war_ptrs@var{m}}
5098 Like @samp{check_raw_ptrs@var{m}}, but with the read and write swapped round.
5099 The split is possible in this case if:
5102 @var{b} <= @var{a} || @var{a} + @var{len} <= @var{b}
5105 @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern
5106 @item @samp{vec_cmp@var{m}@var{n}}
5107 Output a vector comparison. Operand 0 of mode @var{n} is the destination for
5108 predicate in operand 1 which is a signed vector comparison with operands of
5109 mode @var{m} in operands 2 and 3. Predicate is computed by element-wise
5110 evaluation of the vector comparison with a truth value of all-ones and a false
5113 @cindex @code{vec_cmpu@var{m}@var{n}} instruction pattern
5114 @item @samp{vec_cmpu@var{m}@var{n}}
5115 Similar to @code{vec_cmp@var{m}@var{n}} but perform unsigned vector comparison.
5117 @cindex @code{vec_cmpeq@var{m}@var{n}} instruction pattern
5118 @item @samp{vec_cmpeq@var{m}@var{n}}
5119 Similar to @code{vec_cmp@var{m}@var{n}} but perform equality or non-equality
5120 vector comparison only. If @code{vec_cmp@var{m}@var{n}}
5121 or @code{vec_cmpu@var{m}@var{n}} instruction pattern is supported,
5122 it will be preferred over @code{vec_cmpeq@var{m}@var{n}}, so there is
5123 no need to define this instruction pattern if the others are supported.
5125 @cindex @code{vcond@var{m}@var{n}} instruction pattern
5126 @item @samp{vcond@var{m}@var{n}}
5127 Output a conditional vector move. Operand 0 is the destination to
5128 receive a combination of operand 1 and operand 2, which are of mode @var{m},
5129 dependent on the outcome of the predicate in operand 3 which is a signed
5130 vector comparison with operands of mode @var{n} in operands 4 and 5. The
5131 modes @var{m} and @var{n} should have the same size. Operand 0
5132 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
5133 where @var{msk} is computed by element-wise evaluation of the vector
5134 comparison with a truth value of all-ones and a false value of all-zeros.
5136 @cindex @code{vcondu@var{m}@var{n}} instruction pattern
5137 @item @samp{vcondu@var{m}@var{n}}
5138 Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector
5141 @cindex @code{vcondeq@var{m}@var{n}} instruction pattern
5142 @item @samp{vcondeq@var{m}@var{n}}
5143 Similar to @code{vcond@var{m}@var{n}} but performs equality or
5144 non-equality vector comparison only. If @code{vcond@var{m}@var{n}}
5145 or @code{vcondu@var{m}@var{n}} instruction pattern is supported,
5146 it will be preferred over @code{vcondeq@var{m}@var{n}}, so there is
5147 no need to define this instruction pattern if the others are supported.
5149 @cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern
5150 @item @samp{vcond_mask_@var{m}@var{n}}
5151 Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed
5152 result of vector comparison.
5154 @cindex @code{maskload@var{m}@var{n}} instruction pattern
5155 @item @samp{maskload@var{m}@var{n}}
5156 Perform a masked load of vector from memory operand 1 of mode @var{m}
5157 into register operand 0. Mask is provided in register operand 2 of
5160 This pattern is not allowed to @code{FAIL}.
5162 @cindex @code{maskstore@var{m}@var{n}} instruction pattern
5163 @item @samp{maskstore@var{m}@var{n}}
5164 Perform a masked store of vector from register operand 1 of mode @var{m}
5165 into memory operand 0. Mask is provided in register operand 2 of
5168 This pattern is not allowed to @code{FAIL}.
5170 @cindex @code{len_load_@var{m}} instruction pattern
5171 @item @samp{len_load_@var{m}}
5172 Load the number of vector elements specified by operand 2 from memory
5173 operand 1 into vector register operand 0, setting the other elements of
5174 operand 0 to undefined values. Operands 0 and 1 have mode @var{m},
5175 which must be a vector mode. Operand 2 has whichever integer mode the
5176 target prefers. If operand 2 exceeds the number of elements in mode
5177 @var{m}, the behavior is undefined. If the target prefers the length
5178 to be measured in bytes rather than elements, it should only implement
5179 this pattern for vectors of @code{QI} elements.
5181 This pattern is not allowed to @code{FAIL}.
5183 @cindex @code{len_store_@var{m}} instruction pattern
5184 @item @samp{len_store_@var{m}}
5185 Store the number of vector elements specified by operand 2 from vector
5186 register operand 1 into memory operand 0, leaving the other elements of
5187 operand 0 unchanged. Operands 0 and 1 have mode @var{m}, which must be
5188 a vector mode. Operand 2 has whichever integer mode the target prefers.
5189 If operand 2 exceeds the number of elements in mode @var{m}, the behavior
5190 is undefined. If the target prefers the length to be measured in bytes
5191 rather than elements, it should only implement this pattern for vectors
5192 of @code{QI} elements.
5194 This pattern is not allowed to @code{FAIL}.
5196 @cindex @code{vec_perm@var{m}} instruction pattern
5197 @item @samp{vec_perm@var{m}}
5198 Output a (variable) vector permutation. Operand 0 is the destination
5199 to receive elements from operand 1 and operand 2, which are of mode
5200 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
5201 vector of the same width and number of elements as mode @var{m}.
5203 The input elements are numbered from 0 in operand 1 through
5204 @math{2*@var{N}-1} in operand 2. The elements of the selector must
5205 be computed modulo @math{2*@var{N}}. Note that if
5206 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
5207 with just operand 1 and selector elements modulo @var{N}.
5209 In order to make things easy for a number of targets, if there is no
5210 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
5211 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
5212 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
5215 See also @code{TARGET_VECTORIZER_VEC_PERM_CONST}, which performs
5216 the analogous operation for constant selectors.
5218 @cindex @code{push@var{m}1} instruction pattern
5219 @item @samp{push@var{m}1}
5220 Output a push instruction. Operand 0 is value to push. Used only when
5221 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
5222 missing and in such case an @code{mov} expander is used instead, with a
5223 @code{MEM} expression forming the push operation. The @code{mov} expander
5224 method is deprecated.
5226 @cindex @code{add@var{m}3} instruction pattern
5227 @item @samp{add@var{m}3}
5228 Add operand 2 and operand 1, storing the result in operand 0. All operands
5229 must have mode @var{m}. This can be used even on two-address machines, by
5230 means of constraints requiring operands 1 and 0 to be the same location.
5232 @cindex @code{ssadd@var{m}3} instruction pattern
5233 @cindex @code{usadd@var{m}3} instruction pattern
5234 @cindex @code{sub@var{m}3} instruction pattern
5235 @cindex @code{sssub@var{m}3} instruction pattern
5236 @cindex @code{ussub@var{m}3} instruction pattern
5237 @cindex @code{mul@var{m}3} instruction pattern
5238 @cindex @code{ssmul@var{m}3} instruction pattern
5239 @cindex @code{usmul@var{m}3} instruction pattern
5240 @cindex @code{div@var{m}3} instruction pattern
5241 @cindex @code{ssdiv@var{m}3} instruction pattern
5242 @cindex @code{udiv@var{m}3} instruction pattern
5243 @cindex @code{usdiv@var{m}3} instruction pattern
5244 @cindex @code{mod@var{m}3} instruction pattern
5245 @cindex @code{umod@var{m}3} instruction pattern
5246 @cindex @code{umin@var{m}3} instruction pattern
5247 @cindex @code{umax@var{m}3} instruction pattern
5248 @cindex @code{and@var{m}3} instruction pattern
5249 @cindex @code{ior@var{m}3} instruction pattern
5250 @cindex @code{xor@var{m}3} instruction pattern
5251 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
5252 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
5253 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
5254 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
5255 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
5256 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
5257 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
5258 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
5259 Similar, for other arithmetic operations.
5261 @cindex @code{addv@var{m}4} instruction pattern
5262 @item @samp{addv@var{m}4}
5263 Like @code{add@var{m}3} but takes a @code{code_label} as operand 3 and
5264 emits code to jump to it if signed overflow occurs during the addition.
5265 This pattern is used to implement the built-in functions performing
5266 signed integer addition with overflow checking.
5268 @cindex @code{subv@var{m}4} instruction pattern
5269 @cindex @code{mulv@var{m}4} instruction pattern
5270 @item @samp{subv@var{m}4}, @samp{mulv@var{m}4}
5271 Similar, for other signed arithmetic operations.
5273 @cindex @code{uaddv@var{m}4} instruction pattern
5274 @item @samp{uaddv@var{m}4}
5275 Like @code{addv@var{m}4} but for unsigned addition. That is to
5276 say, the operation is the same as signed addition but the jump
5277 is taken only on unsigned overflow.
5279 @cindex @code{usubv@var{m}4} instruction pattern
5280 @cindex @code{umulv@var{m}4} instruction pattern
5281 @item @samp{usubv@var{m}4}, @samp{umulv@var{m}4}
5282 Similar, for other unsigned arithmetic operations.
5284 @cindex @code{addptr@var{m}3} instruction pattern
5285 @item @samp{addptr@var{m}3}
5286 Like @code{add@var{m}3} but is guaranteed to only be used for address
5287 calculations. The expanded code is not allowed to clobber the
5288 condition code. It only needs to be defined if @code{add@var{m}3}
5289 sets the condition code. If adds used for address calculations and
5290 normal adds are not compatible it is required to expand a distinct
5291 pattern (e.g.@: using an unspec). The pattern is used by LRA to emit
5292 address calculations. @code{add@var{m}3} is used if
5293 @code{addptr@var{m}3} is not defined.
5295 @cindex @code{fma@var{m}4} instruction pattern
5296 @item @samp{fma@var{m}4}
5297 Multiply operand 2 and operand 1, then add operand 3, storing the
5298 result in operand 0 without doing an intermediate rounding step. All
5299 operands must have mode @var{m}. This pattern is used to implement
5300 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
5301 the ISO C99 standard.
5303 @cindex @code{fms@var{m}4} instruction pattern
5304 @item @samp{fms@var{m}4}
5305 Like @code{fma@var{m}4}, except operand 3 subtracted from the
5306 product instead of added to the product. This is represented
5310 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
5313 @cindex @code{fnma@var{m}4} instruction pattern
5314 @item @samp{fnma@var{m}4}
5315 Like @code{fma@var{m}4} except that the intermediate product
5316 is negated before being added to operand 3. This is represented
5320 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
5323 @cindex @code{fnms@var{m}4} instruction pattern
5324 @item @samp{fnms@var{m}4}
5325 Like @code{fms@var{m}4} except that the intermediate product
5326 is negated before subtracting operand 3. This is represented
5330 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
5333 @cindex @code{min@var{m}3} instruction pattern
5334 @cindex @code{max@var{m}3} instruction pattern
5335 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
5336 Signed minimum and maximum operations. When used with floating point,
5337 if both operands are zeros, or if either operand is @code{NaN}, then
5338 it is unspecified which of the two operands is returned as the result.
5340 @cindex @code{fmin@var{m}3} instruction pattern
5341 @cindex @code{fmax@var{m}3} instruction pattern
5342 @item @samp{fmin@var{m}3}, @samp{fmax@var{m}3}
5343 IEEE-conformant minimum and maximum operations. If one operand is a quiet
5344 @code{NaN}, then the other operand is returned. If both operands are quiet
5345 @code{NaN}, then a quiet @code{NaN} is returned. In the case when gcc supports
5346 signaling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
5347 raised and a quiet @code{NaN} is returned.
5349 All operands have mode @var{m}, which is a scalar or vector
5350 floating-point mode. These patterns are not allowed to @code{FAIL}.
5352 @cindex @code{reduc_smin_scal_@var{m}} instruction pattern
5353 @cindex @code{reduc_smax_scal_@var{m}} instruction pattern
5354 @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}}
5355 Find the signed minimum/maximum of the elements of a vector. The vector is
5356 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5357 the elements of the input vector.
5359 @cindex @code{reduc_umin_scal_@var{m}} instruction pattern
5360 @cindex @code{reduc_umax_scal_@var{m}} instruction pattern
5361 @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}}
5362 Find the unsigned minimum/maximum of the elements of a vector. The vector is
5363 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5364 the elements of the input vector.
5366 @cindex @code{reduc_plus_scal_@var{m}} instruction pattern
5367 @item @samp{reduc_plus_scal_@var{m}}
5368 Compute the sum of the elements of a vector. The vector is operand 1, and
5369 operand 0 is the scalar result, with mode equal to the mode of the elements of
5372 @cindex @code{reduc_and_scal_@var{m}} instruction pattern
5373 @item @samp{reduc_and_scal_@var{m}}
5374 @cindex @code{reduc_ior_scal_@var{m}} instruction pattern
5375 @itemx @samp{reduc_ior_scal_@var{m}}
5376 @cindex @code{reduc_xor_scal_@var{m}} instruction pattern
5377 @itemx @samp{reduc_xor_scal_@var{m}}
5378 Compute the bitwise @code{AND}/@code{IOR}/@code{XOR} reduction of the elements
5379 of a vector of mode @var{m}. Operand 1 is the vector input and operand 0
5380 is the scalar result. The mode of the scalar result is the same as one
5383 @cindex @code{extract_last_@var{m}} instruction pattern
5384 @item @code{extract_last_@var{m}}
5385 Find the last set bit in mask operand 1 and extract the associated element
5386 of vector operand 2. Store the result in scalar operand 0. Operand 2
5387 has vector mode @var{m} while operand 0 has the mode appropriate for one
5388 element of @var{m}. Operand 1 has the usual mask mode for vectors of mode
5389 @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5391 @cindex @code{fold_extract_last_@var{m}} instruction pattern
5392 @item @code{fold_extract_last_@var{m}}
5393 If any bits of mask operand 2 are set, find the last set bit, extract
5394 the associated element from vector operand 3, and store the result
5395 in operand 0. Store operand 1 in operand 0 otherwise. Operand 3
5396 has mode @var{m} and operands 0 and 1 have the mode appropriate for
5397 one element of @var{m}. Operand 2 has the usual mask mode for vectors
5398 of mode @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5400 @cindex @code{fold_left_plus_@var{m}} instruction pattern
5401 @item @code{fold_left_plus_@var{m}}
5402 Take scalar operand 1 and successively add each element from vector
5403 operand 2. Store the result in scalar operand 0. The vector has
5404 mode @var{m} and the scalars have the mode appropriate for one
5405 element of @var{m}. The operation is strictly in-order: there is
5408 @cindex @code{mask_fold_left_plus_@var{m}} instruction pattern
5409 @item @code{mask_fold_left_plus_@var{m}}
5410 Like @samp{fold_left_plus_@var{m}}, but takes an additional mask operand
5411 (operand 3) that specifies which elements of the source vector should be added.
5413 @cindex @code{sdot_prod@var{m}} instruction pattern
5414 @item @samp{sdot_prod@var{m}}
5415 @cindex @code{udot_prod@var{m}} instruction pattern
5416 @itemx @samp{udot_prod@var{m}}
5417 Compute the sum of the products of two signed/unsigned elements.
5418 Operand 1 and operand 2 are of the same mode. Their product, which is of a
5419 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
5420 wider than the mode of the product. The result is placed in operand 0, which
5421 is of the same mode as operand 3.
5423 @cindex @code{ssad@var{m}} instruction pattern
5424 @item @samp{ssad@var{m}}
5425 @cindex @code{usad@var{m}} instruction pattern
5426 @item @samp{usad@var{m}}
5427 Compute the sum of absolute differences of two signed/unsigned elements.
5428 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
5429 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
5430 equal or wider than the mode of the absolute difference. The result is placed
5431 in operand 0, which is of the same mode as operand 3.
5433 @cindex @code{widen_ssum@var{m3}} instruction pattern
5434 @item @samp{widen_ssum@var{m3}}
5435 @cindex @code{widen_usum@var{m3}} instruction pattern
5436 @itemx @samp{widen_usum@var{m3}}
5437 Operands 0 and 2 are of the same mode, which is wider than the mode of
5438 operand 1. Add operand 1 to operand 2 and place the widened result in
5439 operand 0. (This is used express accumulation of elements into an accumulator
5442 @cindex @code{smulhs@var{m3}} instruction pattern
5443 @item @samp{smulhs@var{m3}}
5444 @cindex @code{umulhs@var{m3}} instruction pattern
5445 @itemx @samp{umulhs@var{m3}}
5446 Signed/unsigned multiply high with scale. This is equivalent to the C code:
5448 narrow op0, op1, op2;
5450 op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1));
5452 where the sign of @samp{narrow} determines whether this is a signed
5453 or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
5455 @cindex @code{smulhrs@var{m3}} instruction pattern
5456 @item @samp{smulhrs@var{m3}}
5457 @cindex @code{umulhrs@var{m3}} instruction pattern
5458 @itemx @samp{umulhrs@var{m3}}
5459 Signed/unsigned multiply high with round and scale. This is
5460 equivalent to the C code:
5462 narrow op0, op1, op2;
5464 op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1);
5466 where the sign of @samp{narrow} determines whether this is a signed
5467 or unsigned operation, and @var{N} is the size of @samp{wide} in bits.
5469 @cindex @code{sdiv_pow2@var{m3}} instruction pattern
5470 @item @samp{sdiv_pow2@var{m3}}
5471 @cindex @code{sdiv_pow2@var{m3}} instruction pattern
5472 @itemx @samp{sdiv_pow2@var{m3}}
5473 Signed division by power-of-2 immediate. Equivalent to:
5477 op0 = op1 / (1 << imm);
5480 @cindex @code{vec_shl_insert_@var{m}} instruction pattern
5481 @item @samp{vec_shl_insert_@var{m}}
5482 Shift the elements in vector input operand 1 left one element (i.e.@:
5483 away from element 0) and fill the vacated element 0 with the scalar
5484 in operand 2. Store the result in vector output operand 0. Operands
5485 0 and 1 have mode @var{m} and operand 2 has the mode appropriate for
5486 one element of @var{m}.
5488 @cindex @code{vec_shl_@var{m}} instruction pattern
5489 @item @samp{vec_shl_@var{m}}
5490 Whole vector left shift in bits, i.e.@: away from element 0.
5491 Operand 1 is a vector to be shifted.
5492 Operand 2 is an integer shift amount in bits.
5493 Operand 0 is where the resulting shifted vector is stored.
5494 The output and input vectors should have the same modes.
5496 @cindex @code{vec_shr_@var{m}} instruction pattern
5497 @item @samp{vec_shr_@var{m}}
5498 Whole vector right shift in bits, i.e.@: towards element 0.
5499 Operand 1 is a vector to be shifted.
5500 Operand 2 is an integer shift amount in bits.
5501 Operand 0 is where the resulting shifted vector is stored.
5502 The output and input vectors should have the same modes.
5504 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
5505 @item @samp{vec_pack_trunc_@var{m}}
5506 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5507 are vectors of the same mode having N integral or floating point elements
5508 of size S@. Operand 0 is the resulting vector in which 2*N elements of
5509 size S/2 are concatenated after narrowing them down using truncation.
5511 @cindex @code{vec_pack_sbool_trunc_@var{m}} instruction pattern
5512 @item @samp{vec_pack_sbool_trunc_@var{m}}
5513 Narrow and merge the elements of two vectors. Operands 1 and 2 are vectors
5514 of the same type having N boolean elements. Operand 0 is the resulting
5515 vector in which 2*N elements are concatenated. The last operand (operand 3)
5516 is the number of elements in the output vector 2*N as a @code{CONST_INT}.
5517 This instruction pattern is used when all the vector input and output
5518 operands have the same scalar mode @var{m} and thus using
5519 @code{vec_pack_trunc_@var{m}} would be ambiguous.
5521 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
5522 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
5523 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
5524 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5525 are vectors of the same mode having N integral elements of size S.
5526 Operand 0 is the resulting vector in which the elements of the two input
5527 vectors are concatenated after narrowing them down using signed/unsigned
5528 saturating arithmetic.
5530 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
5531 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
5532 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
5533 Narrow, convert to signed/unsigned integral type and merge the elements
5534 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5535 floating point elements of size S@. Operand 0 is the resulting vector
5536 in which 2*N elements of size S/2 are concatenated.
5538 @cindex @code{vec_packs_float_@var{m}} instruction pattern
5539 @cindex @code{vec_packu_float_@var{m}} instruction pattern
5540 @item @samp{vec_packs_float_@var{m}}, @samp{vec_packu_float_@var{m}}
5541 Narrow, convert to floating point type and merge the elements
5542 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5543 signed/unsigned integral elements of size S@. Operand 0 is the resulting vector
5544 in which 2*N elements of size S/2 are concatenated.
5546 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
5547 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
5548 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
5549 Extract and widen (promote) the high/low part of a vector of signed
5550 integral or floating point elements. The input vector (operand 1) has N
5551 elements of size S@. Widen (promote) the high/low elements of the vector
5552 using signed or floating point extension and place the resulting N/2
5553 values of size 2*S in the output vector (operand 0).
5555 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
5556 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
5557 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
5558 Extract and widen (promote) the high/low part of a vector of unsigned
5559 integral elements. The input vector (operand 1) has N elements of size S.
5560 Widen (promote) the high/low elements of the vector using zero extension and
5561 place the resulting N/2 values of size 2*S in the output vector (operand 0).
5563 @cindex @code{vec_unpacks_sbool_hi_@var{m}} instruction pattern
5564 @cindex @code{vec_unpacks_sbool_lo_@var{m}} instruction pattern
5565 @item @samp{vec_unpacks_sbool_hi_@var{m}}, @samp{vec_unpacks_sbool_lo_@var{m}}
5566 Extract the high/low part of a vector of boolean elements that have scalar
5567 mode @var{m}. The input vector (operand 1) has N elements, the output
5568 vector (operand 0) has N/2 elements. The last operand (operand 2) is the
5569 number of elements of the input vector N as a @code{CONST_INT}. These
5570 patterns are used if both the input and output vectors have the same scalar
5571 mode @var{m} and thus using @code{vec_unpacks_hi_@var{m}} or
5572 @code{vec_unpacks_lo_@var{m}} would be ambiguous.
5574 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
5575 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
5576 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
5577 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
5578 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
5579 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
5580 Extract, convert to floating point type and widen the high/low part of a
5581 vector of signed/unsigned integral elements. The input vector (operand 1)
5582 has N elements of size S@. Convert the high/low elements of the vector using
5583 floating point conversion and place the resulting N/2 values of size 2*S in
5584 the output vector (operand 0).
5586 @cindex @code{vec_unpack_sfix_trunc_hi_@var{m}} instruction pattern
5587 @cindex @code{vec_unpack_sfix_trunc_lo_@var{m}} instruction pattern
5588 @cindex @code{vec_unpack_ufix_trunc_hi_@var{m}} instruction pattern
5589 @cindex @code{vec_unpack_ufix_trunc_lo_@var{m}} instruction pattern
5590 @item @samp{vec_unpack_sfix_trunc_hi_@var{m}},
5591 @itemx @samp{vec_unpack_sfix_trunc_lo_@var{m}}
5592 @itemx @samp{vec_unpack_ufix_trunc_hi_@var{m}}
5593 @itemx @samp{vec_unpack_ufix_trunc_lo_@var{m}}
5594 Extract, convert to signed/unsigned integer type and widen the high/low part of a
5595 vector of floating point elements. The input vector (operand 1)
5596 has N elements of size S@. Convert the high/low elements of the vector
5597 to integers and place the resulting N/2 values of size 2*S in
5598 the output vector (operand 0).
5600 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
5601 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
5602 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
5603 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
5604 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
5605 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
5606 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
5607 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
5608 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
5609 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
5610 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
5611 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
5612 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
5613 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
5614 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
5615 in the output vector (operand 0). A target shouldn't implement even/odd pattern
5616 pair if it is less efficient than lo/hi one.
5618 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
5619 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
5620 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
5621 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
5622 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
5623 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
5624 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
5625 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
5626 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
5627 output vector (operand 0).
5629 @cindex @code{vec_widen_saddl_hi_@var{m}} instruction pattern
5630 @cindex @code{vec_widen_saddl_lo_@var{m}} instruction pattern
5631 @cindex @code{vec_widen_uaddl_hi_@var{m}} instruction pattern
5632 @cindex @code{vec_widen_uaddl_lo_@var{m}} instruction pattern
5633 @item @samp{vec_widen_uaddl_hi_@var{m}}, @samp{vec_widen_uaddl_lo_@var{m}}
5634 @itemx @samp{vec_widen_saddl_hi_@var{m}}, @samp{vec_widen_saddl_lo_@var{m}}
5635 Signed/Unsigned widening add long. Operands 1 and 2 are vectors with N
5636 signed/unsigned elements of size S@. Add the high/low elements of 1 and 2
5637 together, widen the resulting elements and put the N/2 results of size 2*S in
5638 the output vector (operand 0).
5640 @cindex @code{vec_widen_ssubl_hi_@var{m}} instruction pattern
5641 @cindex @code{vec_widen_ssubl_lo_@var{m}} instruction pattern
5642 @cindex @code{vec_widen_usubl_hi_@var{m}} instruction pattern
5643 @cindex @code{vec_widen_usubl_lo_@var{m}} instruction pattern
5644 @item @samp{vec_widen_usubl_hi_@var{m}}, @samp{vec_widen_usubl_lo_@var{m}}
5645 @itemx @samp{vec_widen_ssubl_hi_@var{m}}, @samp{vec_widen_ssubl_lo_@var{m}}
5646 Signed/Unsigned widening subtract long. Operands 1 and 2 are vectors with N
5647 signed/unsigned elements of size S@. Subtract the high/low elements of 2 from
5648 1 and widen the resulting elements. Put the N/2 results of size 2*S in the
5649 output vector (operand 0).
5651 @cindex @code{mulhisi3} instruction pattern
5652 @item @samp{mulhisi3}
5653 Multiply operands 1 and 2, which have mode @code{HImode}, and store
5654 a @code{SImode} product in operand 0.
5656 @cindex @code{mulqihi3} instruction pattern
5657 @cindex @code{mulsidi3} instruction pattern
5658 @item @samp{mulqihi3}, @samp{mulsidi3}
5659 Similar widening-multiplication instructions of other widths.
5661 @cindex @code{umulqihi3} instruction pattern
5662 @cindex @code{umulhisi3} instruction pattern
5663 @cindex @code{umulsidi3} instruction pattern
5664 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
5665 Similar widening-multiplication instructions that do unsigned
5668 @cindex @code{usmulqihi3} instruction pattern
5669 @cindex @code{usmulhisi3} instruction pattern
5670 @cindex @code{usmulsidi3} instruction pattern
5671 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
5672 Similar widening-multiplication instructions that interpret the first
5673 operand as unsigned and the second operand as signed, then do a signed
5676 @cindex @code{smul@var{m}3_highpart} instruction pattern
5677 @item @samp{smul@var{m}3_highpart}
5678 Perform a signed multiplication of operands 1 and 2, which have mode
5679 @var{m}, and store the most significant half of the product in operand 0.
5680 The least significant half of the product is discarded.
5682 @cindex @code{umul@var{m}3_highpart} instruction pattern
5683 @item @samp{umul@var{m}3_highpart}
5684 Similar, but the multiplication is unsigned.
5686 @cindex @code{madd@var{m}@var{n}4} instruction pattern
5687 @item @samp{madd@var{m}@var{n}4}
5688 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
5689 operand 3, and store the result in operand 0. Operands 1 and 2
5690 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5691 Both modes must be integer or fixed-point modes and @var{n} must be twice
5692 the size of @var{m}.
5694 In other words, @code{madd@var{m}@var{n}4} is like
5695 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
5697 These instructions are not allowed to @code{FAIL}.
5699 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
5700 @item @samp{umadd@var{m}@var{n}4}
5701 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5702 operands instead of sign-extending them.
5704 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5705 @item @samp{ssmadd@var{m}@var{n}4}
5706 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5709 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5710 @item @samp{usmadd@var{m}@var{n}4}
5711 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5712 unsigned-saturating.
5714 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5715 @item @samp{msub@var{m}@var{n}4}
5716 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5717 result from operand 3, and store the result in operand 0. Operands 1 and 2
5718 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5719 Both modes must be integer or fixed-point modes and @var{n} must be twice
5720 the size of @var{m}.
5722 In other words, @code{msub@var{m}@var{n}4} is like
5723 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5726 These instructions are not allowed to @code{FAIL}.
5728 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5729 @item @samp{umsub@var{m}@var{n}4}
5730 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5731 operands instead of sign-extending them.
5733 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5734 @item @samp{ssmsub@var{m}@var{n}4}
5735 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5738 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5739 @item @samp{usmsub@var{m}@var{n}4}
5740 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5741 unsigned-saturating.
5743 @cindex @code{divmod@var{m}4} instruction pattern
5744 @item @samp{divmod@var{m}4}
5745 Signed division that produces both a quotient and a remainder.
5746 Operand 1 is divided by operand 2 to produce a quotient stored
5747 in operand 0 and a remainder stored in operand 3.
5749 For machines with an instruction that produces both a quotient and a
5750 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5751 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5752 allows optimization in the relatively common case when both the quotient
5753 and remainder are computed.
5755 If an instruction that just produces a quotient or just a remainder
5756 exists and is more efficient than the instruction that produces both,
5757 write the output routine of @samp{divmod@var{m}4} to call
5758 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5759 quotient or remainder and generate the appropriate instruction.
5761 @cindex @code{udivmod@var{m}4} instruction pattern
5762 @item @samp{udivmod@var{m}4}
5763 Similar, but does unsigned division.
5765 @anchor{shift patterns}
5766 @cindex @code{ashl@var{m}3} instruction pattern
5767 @cindex @code{ssashl@var{m}3} instruction pattern
5768 @cindex @code{usashl@var{m}3} instruction pattern
5769 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5770 Arithmetic-shift operand 1 left by a number of bits specified by operand
5771 2, and store the result in operand 0. Here @var{m} is the mode of
5772 operand 0 and operand 1; operand 2's mode is specified by the
5773 instruction pattern, and the compiler will convert the operand to that
5774 mode before generating the instruction. The shift or rotate expander
5775 or instruction pattern should explicitly specify the mode of the operand 2,
5776 it should never be @code{VOIDmode}. The meaning of out-of-range shift
5777 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5778 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5780 @cindex @code{ashr@var{m}3} instruction pattern
5781 @cindex @code{lshr@var{m}3} instruction pattern
5782 @cindex @code{rotl@var{m}3} instruction pattern
5783 @cindex @code{rotr@var{m}3} instruction pattern
5784 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5785 Other shift and rotate instructions, analogous to the
5786 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5788 @cindex @code{vashl@var{m}3} instruction pattern
5789 @cindex @code{vashr@var{m}3} instruction pattern
5790 @cindex @code{vlshr@var{m}3} instruction pattern
5791 @cindex @code{vrotl@var{m}3} instruction pattern
5792 @cindex @code{vrotr@var{m}3} instruction pattern
5793 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5794 Vector shift and rotate instructions that take vectors as operand 2
5795 instead of a scalar type.
5797 @cindex @code{avg@var{m}3_floor} instruction pattern
5798 @cindex @code{uavg@var{m}3_floor} instruction pattern
5799 @item @samp{avg@var{m}3_floor}
5800 @itemx @samp{uavg@var{m}3_floor}
5801 Signed and unsigned average instructions. These instructions add
5802 operands 1 and 2 without truncation, divide the result by 2,
5803 round towards -Inf, and store the result in operand 0. This is
5804 equivalent to the C code:
5806 narrow op0, op1, op2;
5808 op0 = (narrow) (((wide) op1 + (wide) op2) >> 1);
5810 where the sign of @samp{narrow} determines whether this is a signed
5811 or unsigned operation.
5813 @cindex @code{avg@var{m}3_ceil} instruction pattern
5814 @cindex @code{uavg@var{m}3_ceil} instruction pattern
5815 @item @samp{avg@var{m}3_ceil}
5816 @itemx @samp{uavg@var{m}3_ceil}
5817 Like @samp{avg@var{m}3_floor} and @samp{uavg@var{m}3_floor}, but round
5818 towards +Inf. This is equivalent to the C code:
5820 narrow op0, op1, op2;
5822 op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1);
5825 @cindex @code{bswap@var{m}2} instruction pattern
5826 @item @samp{bswap@var{m}2}
5827 Reverse the order of bytes of operand 1 and store the result in operand 0.
5829 @cindex @code{neg@var{m}2} instruction pattern
5830 @cindex @code{ssneg@var{m}2} instruction pattern
5831 @cindex @code{usneg@var{m}2} instruction pattern
5832 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5833 Negate operand 1 and store the result in operand 0.
5835 @cindex @code{negv@var{m}3} instruction pattern
5836 @item @samp{negv@var{m}3}
5837 Like @code{neg@var{m}2} but takes a @code{code_label} as operand 2 and
5838 emits code to jump to it if signed overflow occurs during the negation.
5840 @cindex @code{abs@var{m}2} instruction pattern
5841 @item @samp{abs@var{m}2}
5842 Store the absolute value of operand 1 into operand 0.
5844 @cindex @code{sqrt@var{m}2} instruction pattern
5845 @item @samp{sqrt@var{m}2}
5846 Store the square root of operand 1 into operand 0. Both operands have
5847 mode @var{m}, which is a scalar or vector floating-point mode.
5849 This pattern is not allowed to @code{FAIL}.
5851 @cindex @code{rsqrt@var{m}2} instruction pattern
5852 @item @samp{rsqrt@var{m}2}
5853 Store the reciprocal of the square root of operand 1 into operand 0.
5854 Both operands have mode @var{m}, which is a scalar or vector
5855 floating-point mode.
5857 On most architectures this pattern is only approximate, so either
5858 its C condition or the @code{TARGET_OPTAB_SUPPORTED_P} hook should
5859 check for the appropriate math flags. (Using the C condition is
5860 more direct, but using @code{TARGET_OPTAB_SUPPORTED_P} can be useful
5861 if a target-specific built-in also uses the @samp{rsqrt@var{m}2}
5864 This pattern is not allowed to @code{FAIL}.
5866 @cindex @code{fmod@var{m}3} instruction pattern
5867 @item @samp{fmod@var{m}3}
5868 Store the remainder of dividing operand 1 by operand 2 into
5869 operand 0, rounded towards zero to an integer. All operands have
5870 mode @var{m}, which is a scalar or vector floating-point mode.
5872 This pattern is not allowed to @code{FAIL}.
5874 @cindex @code{remainder@var{m}3} instruction pattern
5875 @item @samp{remainder@var{m}3}
5876 Store the remainder of dividing operand 1 by operand 2 into
5877 operand 0, rounded to the nearest integer. All operands have
5878 mode @var{m}, which is a scalar or vector floating-point mode.
5880 This pattern is not allowed to @code{FAIL}.
5882 @cindex @code{scalb@var{m}3} instruction pattern
5883 @item @samp{scalb@var{m}3}
5884 Raise @code{FLT_RADIX} to the power of operand 2, multiply it by
5885 operand 1, and store the result in operand 0. All operands have
5886 mode @var{m}, which is a scalar or vector floating-point mode.
5888 This pattern is not allowed to @code{FAIL}.
5890 @cindex @code{ldexp@var{m}3} instruction pattern
5891 @item @samp{ldexp@var{m}3}
5892 Raise 2 to the power of operand 2, multiply it by operand 1, and store
5893 the result in operand 0. Operands 0 and 1 have mode @var{m}, which is
5894 a scalar or vector floating-point mode. Operand 2's mode has
5895 the same number of elements as @var{m} and each element is wide
5896 enough to store an @code{int}. The integers are signed.
5898 This pattern is not allowed to @code{FAIL}.
5900 @cindex @code{cos@var{m}2} instruction pattern
5901 @item @samp{cos@var{m}2}
5902 Store the cosine of operand 1 into operand 0. Both operands have
5903 mode @var{m}, which is a scalar or vector floating-point mode.
5905 This pattern is not allowed to @code{FAIL}.
5907 @cindex @code{sin@var{m}2} instruction pattern
5908 @item @samp{sin@var{m}2}
5909 Store the sine of operand 1 into operand 0. Both operands have
5910 mode @var{m}, which is a scalar or vector floating-point mode.
5912 This pattern is not allowed to @code{FAIL}.
5914 @cindex @code{sincos@var{m}3} instruction pattern
5915 @item @samp{sincos@var{m}3}
5916 Store the cosine of operand 2 into operand 0 and the sine of
5917 operand 2 into operand 1. All operands have mode @var{m},
5918 which is a scalar or vector floating-point mode.
5920 Targets that can calculate the sine and cosine simultaneously can
5921 implement this pattern as opposed to implementing individual
5922 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5923 and @code{cos} built-in functions will then be expanded to the
5924 @code{sincos@var{m}3} pattern, with one of the output values
5927 @cindex @code{tan@var{m}2} instruction pattern
5928 @item @samp{tan@var{m}2}
5929 Store the tangent of operand 1 into operand 0. Both operands have
5930 mode @var{m}, which is a scalar or vector floating-point mode.
5932 This pattern is not allowed to @code{FAIL}.
5934 @cindex @code{asin@var{m}2} instruction pattern
5935 @item @samp{asin@var{m}2}
5936 Store the arc sine of operand 1 into operand 0. Both operands have
5937 mode @var{m}, which is a scalar or vector floating-point mode.
5939 This pattern is not allowed to @code{FAIL}.
5941 @cindex @code{acos@var{m}2} instruction pattern
5942 @item @samp{acos@var{m}2}
5943 Store the arc cosine of operand 1 into operand 0. Both operands have
5944 mode @var{m}, which is a scalar or vector floating-point mode.
5946 This pattern is not allowed to @code{FAIL}.
5948 @cindex @code{atan@var{m}2} instruction pattern
5949 @item @samp{atan@var{m}2}
5950 Store the arc tangent of operand 1 into operand 0. Both operands have
5951 mode @var{m}, which is a scalar or vector floating-point mode.
5953 This pattern is not allowed to @code{FAIL}.
5955 @cindex @code{exp@var{m}2} instruction pattern
5956 @item @samp{exp@var{m}2}
5957 Raise e (the base of natural logarithms) to the power of operand 1
5958 and store the result in operand 0. Both operands have mode @var{m},
5959 which is a scalar or vector floating-point mode.
5961 This pattern is not allowed to @code{FAIL}.
5963 @cindex @code{expm1@var{m}2} instruction pattern
5964 @item @samp{expm1@var{m}2}
5965 Raise e (the base of natural logarithms) to the power of operand 1,
5966 subtract 1, and store the result in operand 0. Both operands have
5967 mode @var{m}, which is a scalar or vector floating-point mode.
5969 For inputs close to zero, the pattern is expected to be more
5970 accurate than a separate @code{exp@var{m}2} and @code{sub@var{m}3}
5973 This pattern is not allowed to @code{FAIL}.
5975 @cindex @code{exp10@var{m}2} instruction pattern
5976 @item @samp{exp10@var{m}2}
5977 Raise 10 to the power of operand 1 and store the result in operand 0.
5978 Both operands have mode @var{m}, which is a scalar or vector
5979 floating-point mode.
5981 This pattern is not allowed to @code{FAIL}.
5983 @cindex @code{exp2@var{m}2} instruction pattern
5984 @item @samp{exp2@var{m}2}
5985 Raise 2 to the power of operand 1 and store the result in operand 0.
5986 Both operands have mode @var{m}, which is a scalar or vector
5987 floating-point mode.
5989 This pattern is not allowed to @code{FAIL}.
5991 @cindex @code{log@var{m}2} instruction pattern
5992 @item @samp{log@var{m}2}
5993 Store the natural logarithm of operand 1 into operand 0. Both operands
5994 have mode @var{m}, which is a scalar or vector floating-point mode.
5996 This pattern is not allowed to @code{FAIL}.
5998 @cindex @code{log1p@var{m}2} instruction pattern
5999 @item @samp{log1p@var{m}2}
6000 Add 1 to operand 1, compute the natural logarithm, and store
6001 the result in operand 0. Both operands have mode @var{m}, which is
6002 a scalar or vector floating-point mode.
6004 For inputs close to zero, the pattern is expected to be more
6005 accurate than a separate @code{add@var{m}3} and @code{log@var{m}2}
6008 This pattern is not allowed to @code{FAIL}.
6010 @cindex @code{log10@var{m}2} instruction pattern
6011 @item @samp{log10@var{m}2}
6012 Store the base-10 logarithm of operand 1 into operand 0. Both operands
6013 have mode @var{m}, which is a scalar or vector floating-point mode.
6015 This pattern is not allowed to @code{FAIL}.
6017 @cindex @code{log2@var{m}2} instruction pattern
6018 @item @samp{log2@var{m}2}
6019 Store the base-2 logarithm of operand 1 into operand 0. Both operands
6020 have mode @var{m}, which is a scalar or vector floating-point mode.
6022 This pattern is not allowed to @code{FAIL}.
6024 @cindex @code{logb@var{m}2} instruction pattern
6025 @item @samp{logb@var{m}2}
6026 Store the base-@code{FLT_RADIX} logarithm of operand 1 into operand 0.
6027 Both operands have mode @var{m}, which is a scalar or vector
6028 floating-point mode.
6030 This pattern is not allowed to @code{FAIL}.
6032 @cindex @code{significand@var{m}2} instruction pattern
6033 @item @samp{significand@var{m}2}
6034 Store the significand of floating-point operand 1 in operand 0.
6035 Both operands have mode @var{m}, which is a scalar or vector
6036 floating-point mode.
6038 This pattern is not allowed to @code{FAIL}.
6040 @cindex @code{pow@var{m}3} instruction pattern
6041 @item @samp{pow@var{m}3}
6042 Store the value of operand 1 raised to the exponent operand 2
6043 into operand 0. All operands have mode @var{m}, which is a scalar
6044 or vector floating-point mode.
6046 This pattern is not allowed to @code{FAIL}.
6048 @cindex @code{atan2@var{m}3} instruction pattern
6049 @item @samp{atan2@var{m}3}
6050 Store the arc tangent (inverse tangent) of operand 1 divided by
6051 operand 2 into operand 0, using the signs of both arguments to
6052 determine the quadrant of the result. All operands have mode
6053 @var{m}, which is a scalar or vector floating-point mode.
6055 This pattern is not allowed to @code{FAIL}.
6057 @cindex @code{floor@var{m}2} instruction pattern
6058 @item @samp{floor@var{m}2}
6059 Store the largest integral value not greater than operand 1 in operand 0.
6060 Both operands have mode @var{m}, which is a scalar or vector
6061 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
6062 effect, the ``inexact'' exception may be raised for noninteger
6063 operands; otherwise, it may not.
6065 This pattern is not allowed to @code{FAIL}.
6067 @cindex @code{btrunc@var{m}2} instruction pattern
6068 @item @samp{btrunc@var{m}2}
6069 Round operand 1 to an integer, towards zero, and store the result in
6070 operand 0. Both operands have mode @var{m}, which is a scalar or
6071 vector floating-point mode. If @option{-ffp-int-builtin-inexact} is
6072 in effect, the ``inexact'' exception may be raised for noninteger
6073 operands; otherwise, it may not.
6075 This pattern is not allowed to @code{FAIL}.
6077 @cindex @code{round@var{m}2} instruction pattern
6078 @item @samp{round@var{m}2}
6079 Round operand 1 to the nearest integer, rounding away from zero in the
6080 event of a tie, and store the result in operand 0. Both operands have
6081 mode @var{m}, which is a scalar or vector floating-point mode. If
6082 @option{-ffp-int-builtin-inexact} is in effect, the ``inexact''
6083 exception may be raised for noninteger operands; otherwise, it may
6086 This pattern is not allowed to @code{FAIL}.
6088 @cindex @code{ceil@var{m}2} instruction pattern
6089 @item @samp{ceil@var{m}2}
6090 Store the smallest integral value not less than operand 1 in operand 0.
6091 Both operands have mode @var{m}, which is a scalar or vector
6092 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
6093 effect, the ``inexact'' exception may be raised for noninteger
6094 operands; otherwise, it may not.
6096 This pattern is not allowed to @code{FAIL}.
6098 @cindex @code{nearbyint@var{m}2} instruction pattern
6099 @item @samp{nearbyint@var{m}2}
6100 Round operand 1 to an integer, using the current rounding mode, and
6101 store the result in operand 0. Do not raise an inexact condition when
6102 the result is different from the argument. Both operands have mode
6103 @var{m}, which is a scalar or vector floating-point mode.
6105 This pattern is not allowed to @code{FAIL}.
6107 @cindex @code{rint@var{m}2} instruction pattern
6108 @item @samp{rint@var{m}2}
6109 Round operand 1 to an integer, using the current rounding mode, and
6110 store the result in operand 0. Raise an inexact condition when
6111 the result is different from the argument. Both operands have mode
6112 @var{m}, which is a scalar or vector floating-point mode.
6114 This pattern is not allowed to @code{FAIL}.
6116 @cindex @code{lrint@var{m}@var{n}2}
6117 @item @samp{lrint@var{m}@var{n}2}
6118 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6119 point mode @var{n} as a signed number according to the current
6120 rounding mode and store in operand 0 (which has mode @var{n}).
6122 @cindex @code{lround@var{m}@var{n}2}
6123 @item @samp{lround@var{m}@var{n}2}
6124 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6125 point mode @var{n} as a signed number rounding to nearest and away
6126 from zero and store in operand 0 (which has mode @var{n}).
6128 @cindex @code{lfloor@var{m}@var{n}2}
6129 @item @samp{lfloor@var{m}@var{n}2}
6130 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6131 point mode @var{n} as a signed number rounding down and store in
6132 operand 0 (which has mode @var{n}).
6134 @cindex @code{lceil@var{m}@var{n}2}
6135 @item @samp{lceil@var{m}@var{n}2}
6136 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6137 point mode @var{n} as a signed number rounding up and store in
6138 operand 0 (which has mode @var{n}).
6140 @cindex @code{copysign@var{m}3} instruction pattern
6141 @item @samp{copysign@var{m}3}
6142 Store a value with the magnitude of operand 1 and the sign of operand
6143 2 into operand 0. All operands have mode @var{m}, which is a scalar or
6144 vector floating-point mode.
6146 This pattern is not allowed to @code{FAIL}.
6148 @cindex @code{xorsign@var{m}3} instruction pattern
6149 @item @samp{xorsign@var{m}3}
6150 Equivalent to @samp{op0 = op1 * copysign (1.0, op2)}: store a value with
6151 the magnitude of operand 1 and the sign of operand 2 into operand 0.
6152 All operands have mode @var{m}, which is a scalar or vector
6153 floating-point mode.
6155 This pattern is not allowed to @code{FAIL}.
6157 @cindex @code{ffs@var{m}2} instruction pattern
6158 @item @samp{ffs@var{m}2}
6159 Store into operand 0 one plus the index of the least significant 1-bit
6160 of operand 1. If operand 1 is zero, store zero.
6162 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6163 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6164 integer mode is suitable for the target. The compiler will insert
6165 conversion instructions as necessary (typically to convert the result
6166 to the same width as @code{int}). When @var{m} is a vector, both
6167 operands must have mode @var{m}.
6169 This pattern is not allowed to @code{FAIL}.
6171 @cindex @code{clrsb@var{m}2} instruction pattern
6172 @item @samp{clrsb@var{m}2}
6173 Count leading redundant sign bits.
6174 Store into operand 0 the number of redundant sign bits in operand 1, starting
6175 at the most significant bit position.
6176 A redundant sign bit is defined as any sign bit after the first. As such,
6177 this count will be one less than the count of leading sign bits.
6179 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6180 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6181 integer mode is suitable for the target. The compiler will insert
6182 conversion instructions as necessary (typically to convert the result
6183 to the same width as @code{int}). When @var{m} is a vector, both
6184 operands must have mode @var{m}.
6186 This pattern is not allowed to @code{FAIL}.
6188 @cindex @code{clz@var{m}2} instruction pattern
6189 @item @samp{clz@var{m}2}
6190 Store into operand 0 the number of leading 0-bits in operand 1, starting
6191 at the most significant bit position. If operand 1 is 0, the
6192 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
6193 the result is undefined or has a useful value.
6195 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6196 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6197 integer mode is suitable for the target. The compiler will insert
6198 conversion instructions as necessary (typically to convert the result
6199 to the same width as @code{int}). When @var{m} is a vector, both
6200 operands must have mode @var{m}.
6202 This pattern is not allowed to @code{FAIL}.
6204 @cindex @code{ctz@var{m}2} instruction pattern
6205 @item @samp{ctz@var{m}2}
6206 Store into operand 0 the number of trailing 0-bits in operand 1, starting
6207 at the least significant bit position. If operand 1 is 0, the
6208 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
6209 the result is undefined or has a useful value.
6211 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6212 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6213 integer mode is suitable for the target. The compiler will insert
6214 conversion instructions as necessary (typically to convert the result
6215 to the same width as @code{int}). When @var{m} is a vector, both
6216 operands must have mode @var{m}.
6218 This pattern is not allowed to @code{FAIL}.
6220 @cindex @code{popcount@var{m}2} instruction pattern
6221 @item @samp{popcount@var{m}2}
6222 Store into operand 0 the number of 1-bits in operand 1.
6224 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6225 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6226 integer mode is suitable for the target. The compiler will insert
6227 conversion instructions as necessary (typically to convert the result
6228 to the same width as @code{int}). When @var{m} is a vector, both
6229 operands must have mode @var{m}.
6231 This pattern is not allowed to @code{FAIL}.
6233 @cindex @code{parity@var{m}2} instruction pattern
6234 @item @samp{parity@var{m}2}
6235 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
6236 in operand 1 modulo 2.
6238 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6239 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6240 integer mode is suitable for the target. The compiler will insert
6241 conversion instructions as necessary (typically to convert the result
6242 to the same width as @code{int}). When @var{m} is a vector, both
6243 operands must have mode @var{m}.
6245 This pattern is not allowed to @code{FAIL}.
6247 @cindex @code{one_cmpl@var{m}2} instruction pattern
6248 @item @samp{one_cmpl@var{m}2}
6249 Store the bitwise-complement of operand 1 into operand 0.
6251 @cindex @code{cpymem@var{m}} instruction pattern
6252 @item @samp{cpymem@var{m}}
6253 Block copy instruction. The destination and source blocks of memory
6254 are the first two operands, and both are @code{mem:BLK}s with an
6255 address in mode @code{Pmode}.
6257 The number of bytes to copy is the third operand, in mode @var{m}.
6258 Usually, you specify @code{Pmode} for @var{m}. However, if you can
6259 generate better code knowing the range of valid lengths is smaller than
6260 those representable in a full Pmode pointer, you should provide
6262 mode corresponding to the range of values you can handle efficiently
6263 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
6264 that appear negative) and also a pattern with @code{Pmode}.
6266 The fourth operand is the known shared alignment of the source and
6267 destination, in the form of a @code{const_int} rtx. Thus, if the
6268 compiler knows that both source and destination are word-aligned,
6269 it may provide the value 4 for this operand.
6271 Optional operands 5 and 6 specify expected alignment and size of block
6272 respectively. The expected alignment differs from alignment in operand 4
6273 in a way that the blocks are not required to be aligned according to it in
6274 all cases. This expected alignment is also in bytes, just like operand 4.
6275 Expected size, when unknown, is set to @code{(const_int -1)}.
6277 Descriptions of multiple @code{cpymem@var{m}} patterns can only be
6278 beneficial if the patterns for smaller modes have fewer restrictions
6279 on their first, second and fourth operands. Note that the mode @var{m}
6280 in @code{cpymem@var{m}} does not impose any restriction on the mode of
6281 individually copied data units in the block.
6283 The @code{cpymem@var{m}} patterns need not give special consideration
6284 to the possibility that the source and destination strings might
6285 overlap. These patterns are used to do inline expansion of
6286 @code{__builtin_memcpy}.
6288 @cindex @code{movmem@var{m}} instruction pattern
6289 @item @samp{movmem@var{m}}
6290 Block move instruction. The destination and source blocks of memory
6291 are the first two operands, and both are @code{mem:BLK}s with an
6292 address in mode @code{Pmode}.
6294 The number of bytes to copy is the third operand, in mode @var{m}.
6295 Usually, you specify @code{Pmode} for @var{m}. However, if you can
6296 generate better code knowing the range of valid lengths is smaller than
6297 those representable in a full Pmode pointer, you should provide
6299 mode corresponding to the range of values you can handle efficiently
6300 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
6301 that appear negative) and also a pattern with @code{Pmode}.
6303 The fourth operand is the known shared alignment of the source and
6304 destination, in the form of a @code{const_int} rtx. Thus, if the
6305 compiler knows that both source and destination are word-aligned,
6306 it may provide the value 4 for this operand.
6308 Optional operands 5 and 6 specify expected alignment and size of block
6309 respectively. The expected alignment differs from alignment in operand 4
6310 in a way that the blocks are not required to be aligned according to it in
6311 all cases. This expected alignment is also in bytes, just like operand 4.
6312 Expected size, when unknown, is set to @code{(const_int -1)}.
6314 Descriptions of multiple @code{movmem@var{m}} patterns can only be
6315 beneficial if the patterns for smaller modes have fewer restrictions
6316 on their first, second and fourth operands. Note that the mode @var{m}
6317 in @code{movmem@var{m}} does not impose any restriction on the mode of
6318 individually copied data units in the block.
6320 The @code{movmem@var{m}} patterns must correctly handle the case where
6321 the source and destination strings overlap. These patterns are used to
6322 do inline expansion of @code{__builtin_memmove}.
6324 @cindex @code{movstr} instruction pattern
6326 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
6327 an output operand in mode @code{Pmode}. The addresses of the
6328 destination and source strings are operands 1 and 2, and both are
6329 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
6330 the expansion of this pattern should store in operand 0 the address in
6331 which the @code{NUL} terminator was stored in the destination string.
6333 This pattern has also several optional operands that are same as in
6336 @cindex @code{setmem@var{m}} instruction pattern
6337 @item @samp{setmem@var{m}}
6338 Block set instruction. The destination string is the first operand,
6339 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
6340 number of bytes to set is the second operand, in mode @var{m}. The value to
6341 initialize the memory with is the third operand. Targets that only support the
6342 clearing of memory should reject any value that is not the constant 0. See
6343 @samp{cpymem@var{m}} for a discussion of the choice of mode.
6345 The fourth operand is the known alignment of the destination, in the form
6346 of a @code{const_int} rtx. Thus, if the compiler knows that the
6347 destination is word-aligned, it may provide the value 4 for this
6350 Optional operands 5 and 6 specify expected alignment and size of block
6351 respectively. The expected alignment differs from alignment in operand 4
6352 in a way that the blocks are not required to be aligned according to it in
6353 all cases. This expected alignment is also in bytes, just like operand 4.
6354 Expected size, when unknown, is set to @code{(const_int -1)}.
6355 Operand 7 is the minimal size of the block and operand 8 is the
6356 maximal size of the block (NULL if it cannot be represented as CONST_INT).
6357 Operand 9 is the probable maximal size (i.e.@: we cannot rely on it for
6358 correctness, but it can be used for choosing proper code sequence for a
6361 The use for multiple @code{setmem@var{m}} is as for @code{cpymem@var{m}}.
6363 @cindex @code{cmpstrn@var{m}} instruction pattern
6364 @item @samp{cmpstrn@var{m}}
6365 String compare instruction, with five operands. Operand 0 is the output;
6366 it has mode @var{m}. The remaining four operands are like the operands
6367 of @samp{cpymem@var{m}}. The two memory blocks specified are compared
6368 byte by byte in lexicographic order starting at the beginning of each
6369 string. The instruction is not allowed to prefetch more than one byte
6370 at a time since either string may end in the first byte and reading past
6371 that may access an invalid page or segment and cause a fault. The
6372 comparison terminates early if the fetched bytes are different or if
6373 they are equal to zero. The effect of the instruction is to store a
6374 value in operand 0 whose sign indicates the result of the comparison.
6376 @cindex @code{cmpstr@var{m}} instruction pattern
6377 @item @samp{cmpstr@var{m}}
6378 String compare instruction, without known maximum length. Operand 0 is the
6379 output; it has mode @var{m}. The second and third operand are the blocks of
6380 memory to be compared; both are @code{mem:BLK} with an address in mode
6383 The fourth operand is the known shared alignment of the source and
6384 destination, in the form of a @code{const_int} rtx. Thus, if the
6385 compiler knows that both source and destination are word-aligned,
6386 it may provide the value 4 for this operand.
6388 The two memory blocks specified are compared byte by byte in lexicographic
6389 order starting at the beginning of each string. The instruction is not allowed
6390 to prefetch more than one byte at a time since either string may end in the
6391 first byte and reading past that may access an invalid page or segment and
6392 cause a fault. The comparison will terminate when the fetched bytes
6393 are different or if they are equal to zero. The effect of the
6394 instruction is to store a value in operand 0 whose sign indicates the
6395 result of the comparison.
6397 @cindex @code{cmpmem@var{m}} instruction pattern
6398 @item @samp{cmpmem@var{m}}
6399 Block compare instruction, with five operands like the operands
6400 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
6401 byte by byte in lexicographic order starting at the beginning of each
6402 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
6403 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
6404 the comparison will not stop if both bytes are zero. The effect of
6405 the instruction is to store a value in operand 0 whose sign indicates
6406 the result of the comparison.
6408 @cindex @code{strlen@var{m}} instruction pattern
6409 @item @samp{strlen@var{m}}
6410 Compute the length of a string, with three operands.
6411 Operand 0 is the result (of mode @var{m}), operand 1 is
6412 a @code{mem} referring to the first character of the string,
6413 operand 2 is the character to search for (normally zero),
6414 and operand 3 is a constant describing the known alignment
6415 of the beginning of the string.
6417 @cindex @code{float@var{m}@var{n}2} instruction pattern
6418 @item @samp{float@var{m}@var{n}2}
6419 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
6420 floating point mode @var{n} and store in operand 0 (which has mode
6423 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
6424 @item @samp{floatuns@var{m}@var{n}2}
6425 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
6426 to floating point mode @var{n} and store in operand 0 (which has mode
6429 @cindex @code{fix@var{m}@var{n}2} instruction pattern
6430 @item @samp{fix@var{m}@var{n}2}
6431 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6432 point mode @var{n} as a signed number and store in operand 0 (which
6433 has mode @var{n}). This instruction's result is defined only when
6434 the value of operand 1 is an integer.
6436 If the machine description defines this pattern, it also needs to
6437 define the @code{ftrunc} pattern.
6439 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
6440 @item @samp{fixuns@var{m}@var{n}2}
6441 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6442 point mode @var{n} as an unsigned number and store in operand 0 (which
6443 has mode @var{n}). This instruction's result is defined only when the
6444 value of operand 1 is an integer.
6446 @cindex @code{ftrunc@var{m}2} instruction pattern
6447 @item @samp{ftrunc@var{m}2}
6448 Convert operand 1 (valid for floating point mode @var{m}) to an
6449 integer value, still represented in floating point mode @var{m}, and
6450 store it in operand 0 (valid for floating point mode @var{m}).
6452 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
6453 @item @samp{fix_trunc@var{m}@var{n}2}
6454 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
6455 of mode @var{m} by converting the value to an integer.
6457 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
6458 @item @samp{fixuns_trunc@var{m}@var{n}2}
6459 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
6460 value of mode @var{m} by converting the value to an integer.
6462 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
6463 @item @samp{trunc@var{m}@var{n}2}
6464 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
6465 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6466 point or both floating point.
6468 @cindex @code{extend@var{m}@var{n}2} instruction pattern
6469 @item @samp{extend@var{m}@var{n}2}
6470 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6471 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6472 point or both floating point.
6474 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
6475 @item @samp{zero_extend@var{m}@var{n}2}
6476 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6477 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6480 @cindex @code{fract@var{m}@var{n}2} instruction pattern
6481 @item @samp{fract@var{m}@var{n}2}
6482 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6483 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6484 could be fixed-point to fixed-point, signed integer to fixed-point,
6485 fixed-point to signed integer, floating-point to fixed-point,
6486 or fixed-point to floating-point.
6487 When overflows or underflows happen, the results are undefined.
6489 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
6490 @item @samp{satfract@var{m}@var{n}2}
6491 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6492 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6493 could be fixed-point to fixed-point, signed integer to fixed-point,
6494 or floating-point to fixed-point.
6495 When overflows or underflows happen, the instruction saturates the
6496 results to the maximum or the minimum.
6498 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
6499 @item @samp{fractuns@var{m}@var{n}2}
6500 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6501 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6502 could be unsigned integer to fixed-point, or
6503 fixed-point to unsigned integer.
6504 When overflows or underflows happen, the results are undefined.
6506 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
6507 @item @samp{satfractuns@var{m}@var{n}2}
6508 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
6509 @var{n} and store in operand 0 (which has mode @var{n}).
6510 When overflows or underflows happen, the instruction saturates the
6511 results to the maximum or the minimum.
6513 @cindex @code{extv@var{m}} instruction pattern
6514 @item @samp{extv@var{m}}
6515 Extract a bit-field from register operand 1, sign-extend it, and store
6516 it in operand 0. Operand 2 specifies the width of the field in bits
6517 and operand 3 the starting bit, which counts from the most significant
6518 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
6521 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
6522 target-specific mode.
6524 @cindex @code{extvmisalign@var{m}} instruction pattern
6525 @item @samp{extvmisalign@var{m}}
6526 Extract a bit-field from memory operand 1, sign extend it, and store
6527 it in operand 0. Operand 2 specifies the width in bits and operand 3
6528 the starting bit. The starting bit is always somewhere in the first byte of
6529 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6530 is true and from the least significant bit otherwise.
6532 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
6533 Operands 2 and 3 have a target-specific mode.
6535 The instruction must not read beyond the last byte of the bit-field.
6537 @cindex @code{extzv@var{m}} instruction pattern
6538 @item @samp{extzv@var{m}}
6539 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
6541 @cindex @code{extzvmisalign@var{m}} instruction pattern
6542 @item @samp{extzvmisalign@var{m}}
6543 Like @samp{extvmisalign@var{m}} except that the bit-field value is
6546 @cindex @code{insv@var{m}} instruction pattern
6547 @item @samp{insv@var{m}}
6548 Insert operand 3 into a bit-field of register operand 0. Operand 1
6549 specifies the width of the field in bits and operand 2 the starting bit,
6550 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6551 is true and from the least significant bit otherwise.
6553 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
6554 target-specific mode.
6556 @cindex @code{insvmisalign@var{m}} instruction pattern
6557 @item @samp{insvmisalign@var{m}}
6558 Insert operand 3 into a bit-field of memory operand 0. Operand 1
6559 specifies the width of the field in bits and operand 2 the starting bit.
6560 The starting bit is always somewhere in the first byte of operand 0;
6561 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6562 is true and from the least significant bit otherwise.
6564 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
6565 Operands 1 and 2 have a target-specific mode.
6567 The instruction must not read or write beyond the last byte of the bit-field.
6569 @cindex @code{extv} instruction pattern
6571 Extract a bit-field from operand 1 (a register or memory operand), where
6572 operand 2 specifies the width in bits and operand 3 the starting bit,
6573 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
6574 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
6575 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
6576 be valid for @code{word_mode}.
6578 The RTL generation pass generates this instruction only with constants
6579 for operands 2 and 3 and the constant is never zero for operand 2.
6581 The bit-field value is sign-extended to a full word integer
6582 before it is stored in operand 0.
6584 This pattern is deprecated; please use @samp{extv@var{m}} and
6585 @code{extvmisalign@var{m}} instead.
6587 @cindex @code{extzv} instruction pattern
6589 Like @samp{extv} except that the bit-field value is zero-extended.
6591 This pattern is deprecated; please use @samp{extzv@var{m}} and
6592 @code{extzvmisalign@var{m}} instead.
6594 @cindex @code{insv} instruction pattern
6596 Store operand 3 (which must be valid for @code{word_mode}) into a
6597 bit-field in operand 0, where operand 1 specifies the width in bits and
6598 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
6599 @code{word_mode}; often @code{word_mode} is allowed only for registers.
6600 Operands 1 and 2 must be valid for @code{word_mode}.
6602 The RTL generation pass generates this instruction only with constants
6603 for operands 1 and 2 and the constant is never zero for operand 1.
6605 This pattern is deprecated; please use @samp{insv@var{m}} and
6606 @code{insvmisalign@var{m}} instead.
6608 @cindex @code{mov@var{mode}cc} instruction pattern
6609 @item @samp{mov@var{mode}cc}
6610 Conditionally move operand 2 or operand 3 into operand 0 according to the
6611 comparison in operand 1. If the comparison is true, operand 2 is moved
6612 into operand 0, otherwise operand 3 is moved.
6614 The mode of the operands being compared need not be the same as the operands
6615 being moved. Some machines, sparc64 for example, have instructions that
6616 conditionally move an integer value based on the floating point condition
6617 codes and vice versa.
6619 If the machine does not have conditional move instructions, do not
6620 define these patterns.
6622 @cindex @code{add@var{mode}cc} instruction pattern
6623 @item @samp{add@var{mode}cc}
6624 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
6625 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
6626 comparison in operand 1. If the comparison is false, operand 2 is moved into
6627 operand 0, otherwise (operand 2 + operand 3) is moved.
6629 @cindex @code{cond_add@var{mode}} instruction pattern
6630 @cindex @code{cond_sub@var{mode}} instruction pattern
6631 @cindex @code{cond_mul@var{mode}} instruction pattern
6632 @cindex @code{cond_div@var{mode}} instruction pattern
6633 @cindex @code{cond_udiv@var{mode}} instruction pattern
6634 @cindex @code{cond_mod@var{mode}} instruction pattern
6635 @cindex @code{cond_umod@var{mode}} instruction pattern
6636 @cindex @code{cond_and@var{mode}} instruction pattern
6637 @cindex @code{cond_ior@var{mode}} instruction pattern
6638 @cindex @code{cond_xor@var{mode}} instruction pattern
6639 @cindex @code{cond_smin@var{mode}} instruction pattern
6640 @cindex @code{cond_smax@var{mode}} instruction pattern
6641 @cindex @code{cond_umin@var{mode}} instruction pattern
6642 @cindex @code{cond_umax@var{mode}} instruction pattern
6643 @item @samp{cond_add@var{mode}}
6644 @itemx @samp{cond_sub@var{mode}}
6645 @itemx @samp{cond_mul@var{mode}}
6646 @itemx @samp{cond_div@var{mode}}
6647 @itemx @samp{cond_udiv@var{mode}}
6648 @itemx @samp{cond_mod@var{mode}}
6649 @itemx @samp{cond_umod@var{mode}}
6650 @itemx @samp{cond_and@var{mode}}
6651 @itemx @samp{cond_ior@var{mode}}
6652 @itemx @samp{cond_xor@var{mode}}
6653 @itemx @samp{cond_smin@var{mode}}
6654 @itemx @samp{cond_smax@var{mode}}
6655 @itemx @samp{cond_umin@var{mode}}
6656 @itemx @samp{cond_umax@var{mode}}
6657 When operand 1 is true, perform an operation on operands 2 and 3 and
6658 store the result in operand 0, otherwise store operand 4 in operand 0.
6659 The operation works elementwise if the operands are vectors.
6661 The scalar case is equivalent to:
6664 op0 = op1 ? op2 @var{op} op3 : op4;
6667 while the vector case is equivalent to:
6670 for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
6671 op0[i] = op1[i] ? op2[i] @var{op} op3[i] : op4[i];
6674 where, for example, @var{op} is @code{+} for @samp{cond_add@var{mode}}.
6676 When defined for floating-point modes, the contents of @samp{op3[i]}
6677 are not interpreted if @samp{op1[i]} is false, just like they would not
6678 be in a normal C @samp{?:} condition.
6680 Operands 0, 2, 3 and 4 all have mode @var{m}. Operand 1 is a scalar
6681 integer if @var{m} is scalar, otherwise it has the mode returned by
6682 @code{TARGET_VECTORIZE_GET_MASK_MODE}.
6684 @cindex @code{cond_fma@var{mode}} instruction pattern
6685 @cindex @code{cond_fms@var{mode}} instruction pattern
6686 @cindex @code{cond_fnma@var{mode}} instruction pattern
6687 @cindex @code{cond_fnms@var{mode}} instruction pattern
6688 @item @samp{cond_fma@var{mode}}
6689 @itemx @samp{cond_fms@var{mode}}
6690 @itemx @samp{cond_fnma@var{mode}}
6691 @itemx @samp{cond_fnms@var{mode}}
6692 Like @samp{cond_add@var{m}}, except that the conditional operation
6693 takes 3 operands rather than two. For example, the vector form of
6694 @samp{cond_fma@var{mode}} is equivalent to:
6697 for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
6698 op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i];
6701 @cindex @code{neg@var{mode}cc} instruction pattern
6702 @item @samp{neg@var{mode}cc}
6703 Similar to @samp{mov@var{mode}cc} but for conditional negation. Conditionally
6704 move the negation of operand 2 or the unchanged operand 3 into operand 0
6705 according to the comparison in operand 1. If the comparison is true, the negation
6706 of operand 2 is moved into operand 0, otherwise operand 3 is moved.
6708 @cindex @code{not@var{mode}cc} instruction pattern
6709 @item @samp{not@var{mode}cc}
6710 Similar to @samp{neg@var{mode}cc} but for conditional complement.
6711 Conditionally move the bitwise complement of operand 2 or the unchanged
6712 operand 3 into operand 0 according to the comparison in operand 1.
6713 If the comparison is true, the complement of operand 2 is moved into
6714 operand 0, otherwise operand 3 is moved.
6716 @cindex @code{cstore@var{mode}4} instruction pattern
6717 @item @samp{cstore@var{mode}4}
6718 Store zero or nonzero in operand 0 according to whether a comparison
6719 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
6720 are the first and second operand of the comparison, respectively.
6721 You specify the mode that operand 0 must have when you write the
6722 @code{match_operand} expression. The compiler automatically sees which
6723 mode you have used and supplies an operand of that mode.
6725 The value stored for a true condition must have 1 as its low bit, or
6726 else must be negative. Otherwise the instruction is not suitable and
6727 you should omit it from the machine description. You describe to the
6728 compiler exactly which value is stored by defining the macro
6729 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
6730 found that can be used for all the possible comparison operators, you
6731 should pick one and use a @code{define_expand} to map all results
6732 onto the one you chose.
6734 These operations may @code{FAIL}, but should do so only in relatively
6735 uncommon cases; if they would @code{FAIL} for common cases involving
6736 integer comparisons, it is best to restrict the predicates to not
6737 allow these operands. Likewise if a given comparison operator will
6738 always fail, independent of the operands (for floating-point modes, the
6739 @code{ordered_comparison_operator} predicate is often useful in this case).
6741 If this pattern is omitted, the compiler will generate a conditional
6742 branch---for example, it may copy a constant one to the target and branching
6743 around an assignment of zero to the target---or a libcall. If the predicate
6744 for operand 1 only rejects some operators, it will also try reordering the
6745 operands and/or inverting the result value (e.g.@: by an exclusive OR).
6746 These possibilities could be cheaper or equivalent to the instructions
6747 used for the @samp{cstore@var{mode}4} pattern followed by those required
6748 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
6749 case, you can and should make operand 1's predicate reject some operators
6750 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
6751 from the machine description.
6753 @cindex @code{cbranch@var{mode}4} instruction pattern
6754 @item @samp{cbranch@var{mode}4}
6755 Conditional branch instruction combined with a compare instruction.
6756 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
6757 first and second operands of the comparison, respectively. Operand 3
6758 is the @code{code_label} to jump to.
6760 @cindex @code{jump} instruction pattern
6762 A jump inside a function; an unconditional branch. Operand 0 is the
6763 @code{code_label} to jump to. This pattern name is mandatory on all
6766 @cindex @code{call} instruction pattern
6768 Subroutine call instruction returning no value. Operand 0 is the
6769 function to call; operand 1 is the number of bytes of arguments pushed
6770 as a @code{const_int}; operand 2 is the number of registers used as
6773 On most machines, operand 2 is not actually stored into the RTL
6774 pattern. It is supplied for the sake of some RISC machines which need
6775 to put this information into the assembler code; they can put it in
6776 the RTL instead of operand 1.
6778 Operand 0 should be a @code{mem} RTX whose address is the address of the
6779 function. Note, however, that this address can be a @code{symbol_ref}
6780 expression even if it would not be a legitimate memory address on the
6781 target machine. If it is also not a valid argument for a call
6782 instruction, the pattern for this operation should be a
6783 @code{define_expand} (@pxref{Expander Definitions}) that places the
6784 address into a register and uses that register in the call instruction.
6786 @cindex @code{call_value} instruction pattern
6787 @item @samp{call_value}
6788 Subroutine call instruction returning a value. Operand 0 is the hard
6789 register in which the value is returned. There are three more
6790 operands, the same as the three operands of the @samp{call}
6791 instruction (but with numbers increased by one).
6793 Subroutines that return @code{BLKmode} objects use the @samp{call}
6796 @cindex @code{call_pop} instruction pattern
6797 @cindex @code{call_value_pop} instruction pattern
6798 @item @samp{call_pop}, @samp{call_value_pop}
6799 Similar to @samp{call} and @samp{call_value}, except used if defined and
6800 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
6801 that contains both the function call and a @code{set} to indicate the
6802 adjustment made to the frame pointer.
6804 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
6805 patterns increases the number of functions for which the frame pointer
6806 can be eliminated, if desired.
6808 @cindex @code{untyped_call} instruction pattern
6809 @item @samp{untyped_call}
6810 Subroutine call instruction returning a value of any type. Operand 0 is
6811 the function to call; operand 1 is a memory location where the result of
6812 calling the function is to be stored; operand 2 is a @code{parallel}
6813 expression where each element is a @code{set} expression that indicates
6814 the saving of a function return value into the result block.
6816 This instruction pattern should be defined to support
6817 @code{__builtin_apply} on machines where special instructions are needed
6818 to call a subroutine with arbitrary arguments or to save the value
6819 returned. This instruction pattern is required on machines that have
6820 multiple registers that can hold a return value
6821 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
6823 @cindex @code{return} instruction pattern
6825 Subroutine return instruction. This instruction pattern name should be
6826 defined only if a single instruction can do all the work of returning
6829 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
6830 RTL generation phase. In this case it is to support machines where
6831 multiple instructions are usually needed to return from a function, but
6832 some class of functions only requires one instruction to implement a
6833 return. Normally, the applicable functions are those which do not need
6834 to save any registers or allocate stack space.
6836 It is valid for this pattern to expand to an instruction using
6837 @code{simple_return} if no epilogue is required.
6839 @cindex @code{simple_return} instruction pattern
6840 @item @samp{simple_return}
6841 Subroutine return instruction. This instruction pattern name should be
6842 defined only if a single instruction can do all the work of returning
6843 from a function on a path where no epilogue is required. This pattern
6844 is very similar to the @code{return} instruction pattern, but it is emitted
6845 only by the shrink-wrapping optimization on paths where the function
6846 prologue has not been executed, and a function return should occur without
6847 any of the effects of the epilogue. Additional uses may be introduced on
6848 paths where both the prologue and the epilogue have executed.
6850 @findex reload_completed
6851 @findex leaf_function_p
6852 For such machines, the condition specified in this pattern should only
6853 be true when @code{reload_completed} is nonzero and the function's
6854 epilogue would only be a single instruction. For machines with register
6855 windows, the routine @code{leaf_function_p} may be used to determine if
6856 a register window push is required.
6858 Machines that have conditional return instructions should define patterns
6864 (if_then_else (match_operator
6865 0 "comparison_operator"
6866 [(cc0) (const_int 0)])
6873 where @var{condition} would normally be the same condition specified on the
6874 named @samp{return} pattern.
6876 @cindex @code{untyped_return} instruction pattern
6877 @item @samp{untyped_return}
6878 Untyped subroutine return instruction. This instruction pattern should
6879 be defined to support @code{__builtin_return} on machines where special
6880 instructions are needed to return a value of any type.
6882 Operand 0 is a memory location where the result of calling a function
6883 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
6884 expression where each element is a @code{set} expression that indicates
6885 the restoring of a function return value from the result block.
6887 @cindex @code{nop} instruction pattern
6889 No-op instruction. This instruction pattern name should always be defined
6890 to output a no-op in assembler code. @code{(const_int 0)} will do as an
6893 @cindex @code{indirect_jump} instruction pattern
6894 @item @samp{indirect_jump}
6895 An instruction to jump to an address which is operand zero.
6896 This pattern name is mandatory on all machines.
6898 @cindex @code{casesi} instruction pattern
6900 Instruction to jump through a dispatch table, including bounds checking.
6901 This instruction takes five operands:
6905 The index to dispatch on, which has mode @code{SImode}.
6908 The lower bound for indices in the table, an integer constant.
6911 The total range of indices in the table---the largest index
6912 minus the smallest one (both inclusive).
6915 A label that precedes the table itself.
6918 A label to jump to if the index has a value outside the bounds.
6921 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
6922 @code{jump_table_data}. The number of elements in the table is one plus the
6923 difference between the upper bound and the lower bound.
6925 @cindex @code{tablejump} instruction pattern
6926 @item @samp{tablejump}
6927 Instruction to jump to a variable address. This is a low-level
6928 capability which can be used to implement a dispatch table when there
6929 is no @samp{casesi} pattern.
6931 This pattern requires two operands: the address or offset, and a label
6932 which should immediately precede the jump table. If the macro
6933 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
6934 operand is an offset which counts from the address of the table; otherwise,
6935 it is an absolute address to jump to. In either case, the first operand has
6938 The @samp{tablejump} insn is always the last insn before the jump
6939 table it uses. Its assembler code normally has no need to use the
6940 second operand, but you should incorporate it in the RTL pattern so
6941 that the jump optimizer will not delete the table as unreachable code.
6944 @cindex @code{doloop_end} instruction pattern
6945 @item @samp{doloop_end}
6946 Conditional branch instruction that decrements a register and
6947 jumps if the register is nonzero. Operand 0 is the register to
6948 decrement and test; operand 1 is the label to jump to if the
6949 register is nonzero.
6950 @xref{Looping Patterns}.
6952 This optional instruction pattern should be defined for machines with
6953 low-overhead looping instructions as the loop optimizer will try to
6954 modify suitable loops to utilize it. The target hook
6955 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
6956 low-overhead loops can be used.
6958 @cindex @code{doloop_begin} instruction pattern
6959 @item @samp{doloop_begin}
6960 Companion instruction to @code{doloop_end} required for machines that
6961 need to perform some initialization, such as loading a special counter
6962 register. Operand 1 is the associated @code{doloop_end} pattern and
6963 operand 0 is the register that it decrements.
6965 If initialization insns do not always need to be emitted, use a
6966 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
6968 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
6969 @item @samp{canonicalize_funcptr_for_compare}
6970 Canonicalize the function pointer in operand 1 and store the result
6973 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
6974 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
6975 and also has mode @code{Pmode}.
6977 Canonicalization of a function pointer usually involves computing
6978 the address of the function which would be called if the function
6979 pointer were used in an indirect call.
6981 Only define this pattern if function pointers on the target machine
6982 can have different values but still call the same function when
6983 used in an indirect call.
6985 @cindex @code{save_stack_block} instruction pattern
6986 @cindex @code{save_stack_function} instruction pattern
6987 @cindex @code{save_stack_nonlocal} instruction pattern
6988 @cindex @code{restore_stack_block} instruction pattern
6989 @cindex @code{restore_stack_function} instruction pattern
6990 @cindex @code{restore_stack_nonlocal} instruction pattern
6991 @item @samp{save_stack_block}
6992 @itemx @samp{save_stack_function}
6993 @itemx @samp{save_stack_nonlocal}
6994 @itemx @samp{restore_stack_block}
6995 @itemx @samp{restore_stack_function}
6996 @itemx @samp{restore_stack_nonlocal}
6997 Most machines save and restore the stack pointer by copying it to or
6998 from an object of mode @code{Pmode}. Do not define these patterns on
7001 Some machines require special handling for stack pointer saves and
7002 restores. On those machines, define the patterns corresponding to the
7003 non-standard cases by using a @code{define_expand} (@pxref{Expander
7004 Definitions}) that produces the required insns. The three types of
7005 saves and restores are:
7009 @samp{save_stack_block} saves the stack pointer at the start of a block
7010 that allocates a variable-sized object, and @samp{restore_stack_block}
7011 restores the stack pointer when the block is exited.
7014 @samp{save_stack_function} and @samp{restore_stack_function} do a
7015 similar job for the outermost block of a function and are used when the
7016 function allocates variable-sized objects or calls @code{alloca}. Only
7017 the epilogue uses the restored stack pointer, allowing a simpler save or
7018 restore sequence on some machines.
7021 @samp{save_stack_nonlocal} is used in functions that contain labels
7022 branched to by nested functions. It saves the stack pointer in such a
7023 way that the inner function can use @samp{restore_stack_nonlocal} to
7024 restore the stack pointer. The compiler generates code to restore the
7025 frame and argument pointer registers, but some machines require saving
7026 and restoring additional data such as register window information or
7027 stack backchains. Place insns in these patterns to save and restore any
7031 When saving the stack pointer, operand 0 is the save area and operand 1
7032 is the stack pointer. The mode used to allocate the save area defaults
7033 to @code{Pmode} but you can override that choice by defining the
7034 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
7035 specify an integral mode, or @code{VOIDmode} if no save area is needed
7036 for a particular type of save (either because no save is needed or
7037 because a machine-specific save area can be used). Operand 0 is the
7038 stack pointer and operand 1 is the save area for restore operations. If
7039 @samp{save_stack_block} is defined, operand 0 must not be
7040 @code{VOIDmode} since these saves can be arbitrarily nested.
7042 A save area is a @code{mem} that is at a constant offset from
7043 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
7044 nonlocal gotos and a @code{reg} in the other two cases.
7046 @cindex @code{allocate_stack} instruction pattern
7047 @item @samp{allocate_stack}
7048 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
7049 the stack pointer to create space for dynamically allocated data.
7051 Store the resultant pointer to this space into operand 0. If you
7052 are allocating space from the main stack, do this by emitting a
7053 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
7054 If you are allocating the space elsewhere, generate code to copy the
7055 location of the space to operand 0. In the latter case, you must
7056 ensure this space gets freed when the corresponding space on the main
7059 Do not define this pattern if all that must be done is the subtraction.
7060 Some machines require other operations such as stack probes or
7061 maintaining the back chain. Define this pattern to emit those
7062 operations in addition to updating the stack pointer.
7064 @cindex @code{check_stack} instruction pattern
7065 @item @samp{check_stack}
7066 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
7067 probing the stack, define this pattern to perform the needed check and signal
7068 an error if the stack has overflowed. The single operand is the address in
7069 the stack farthest from the current stack pointer that you need to validate.
7070 Normally, on platforms where this pattern is needed, you would obtain the
7071 stack limit from a global or thread-specific variable or register.
7073 @cindex @code{probe_stack_address} instruction pattern
7074 @item @samp{probe_stack_address}
7075 If stack checking (@pxref{Stack Checking}) can be done on your system by
7076 probing the stack but without the need to actually access it, define this
7077 pattern and signal an error if the stack has overflowed. The single operand
7078 is the memory address in the stack that needs to be probed.
7080 @cindex @code{probe_stack} instruction pattern
7081 @item @samp{probe_stack}
7082 If stack checking (@pxref{Stack Checking}) can be done on your system by
7083 probing the stack but doing it with a ``store zero'' instruction is not valid
7084 or optimal, define this pattern to do the probing differently and signal an
7085 error if the stack has overflowed. The single operand is the memory reference
7086 in the stack that needs to be probed.
7088 @cindex @code{nonlocal_goto} instruction pattern
7089 @item @samp{nonlocal_goto}
7090 Emit code to generate a non-local goto, e.g., a jump from one function
7091 to a label in an outer function. This pattern has four arguments,
7092 each representing a value to be used in the jump. The first
7093 argument is to be loaded into the frame pointer, the second is
7094 the address to branch to (code to dispatch to the actual label),
7095 the third is the address of a location where the stack is saved,
7096 and the last is the address of the label, to be placed in the
7097 location for the incoming static chain.
7099 On most machines you need not define this pattern, since GCC will
7100 already generate the correct code, which is to load the frame pointer
7101 and static chain, restore the stack (using the
7102 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
7103 to the dispatcher. You need only define this pattern if this code will
7104 not work on your machine.
7106 @cindex @code{nonlocal_goto_receiver} instruction pattern
7107 @item @samp{nonlocal_goto_receiver}
7108 This pattern, if defined, contains code needed at the target of a
7109 nonlocal goto after the code already generated by GCC@. You will not
7110 normally need to define this pattern. A typical reason why you might
7111 need this pattern is if some value, such as a pointer to a global table,
7112 must be restored when the frame pointer is restored. Note that a nonlocal
7113 goto only occurs within a unit-of-translation, so a global table pointer
7114 that is shared by all functions of a given module need not be restored.
7115 There are no arguments.
7117 @cindex @code{exception_receiver} instruction pattern
7118 @item @samp{exception_receiver}
7119 This pattern, if defined, contains code needed at the site of an
7120 exception handler that isn't needed at the site of a nonlocal goto. You
7121 will not normally need to define this pattern. A typical reason why you
7122 might need this pattern is if some value, such as a pointer to a global
7123 table, must be restored after control flow is branched to the handler of
7124 an exception. There are no arguments.
7126 @cindex @code{builtin_setjmp_setup} instruction pattern
7127 @item @samp{builtin_setjmp_setup}
7128 This pattern, if defined, contains additional code needed to initialize
7129 the @code{jmp_buf}. You will not normally need to define this pattern.
7130 A typical reason why you might need this pattern is if some value, such
7131 as a pointer to a global table, must be restored. Though it is
7132 preferred that the pointer value be recalculated if possible (given the
7133 address of a label for instance). The single argument is a pointer to
7134 the @code{jmp_buf}. Note that the buffer is five words long and that
7135 the first three are normally used by the generic mechanism.
7137 @cindex @code{builtin_setjmp_receiver} instruction pattern
7138 @item @samp{builtin_setjmp_receiver}
7139 This pattern, if defined, contains code needed at the site of a
7140 built-in setjmp that isn't needed at the site of a nonlocal goto. You
7141 will not normally need to define this pattern. A typical reason why you
7142 might need this pattern is if some value, such as a pointer to a global
7143 table, must be restored. It takes one argument, which is the label
7144 to which builtin_longjmp transferred control; this pattern may be emitted
7145 at a small offset from that label.
7147 @cindex @code{builtin_longjmp} instruction pattern
7148 @item @samp{builtin_longjmp}
7149 This pattern, if defined, performs the entire action of the longjmp.
7150 You will not normally need to define this pattern unless you also define
7151 @code{builtin_setjmp_setup}. The single argument is a pointer to the
7154 @cindex @code{eh_return} instruction pattern
7155 @item @samp{eh_return}
7156 This pattern, if defined, affects the way @code{__builtin_eh_return},
7157 and thence the call frame exception handling library routines, are
7158 built. It is intended to handle non-trivial actions needed along
7159 the abnormal return path.
7161 The address of the exception handler to which the function should return
7162 is passed as operand to this pattern. It will normally need to copied by
7163 the pattern to some special register or memory location.
7164 If the pattern needs to determine the location of the target call
7165 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
7166 if defined; it will have already been assigned.
7168 If this pattern is not defined, the default action will be to simply
7169 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
7170 that macro or this pattern needs to be defined if call frame exception
7171 handling is to be used.
7173 @cindex @code{prologue} instruction pattern
7174 @anchor{prologue instruction pattern}
7175 @item @samp{prologue}
7176 This pattern, if defined, emits RTL for entry to a function. The function
7177 entry is responsible for setting up the stack frame, initializing the frame
7178 pointer register, saving callee saved registers, etc.
7180 Using a prologue pattern is generally preferred over defining
7181 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
7183 The @code{prologue} pattern is particularly useful for targets which perform
7184 instruction scheduling.
7186 @cindex @code{window_save} instruction pattern
7187 @anchor{window_save instruction pattern}
7188 @item @samp{window_save}
7189 This pattern, if defined, emits RTL for a register window save. It should
7190 be defined if the target machine has register windows but the window events
7191 are decoupled from calls to subroutines. The canonical example is the SPARC
7194 @cindex @code{epilogue} instruction pattern
7195 @anchor{epilogue instruction pattern}
7196 @item @samp{epilogue}
7197 This pattern emits RTL for exit from a function. The function
7198 exit is responsible for deallocating the stack frame, restoring callee saved
7199 registers and emitting the return instruction.
7201 Using an epilogue pattern is generally preferred over defining
7202 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
7204 The @code{epilogue} pattern is particularly useful for targets which perform
7205 instruction scheduling or which have delay slots for their return instruction.
7207 @cindex @code{sibcall_epilogue} instruction pattern
7208 @item @samp{sibcall_epilogue}
7209 This pattern, if defined, emits RTL for exit from a function without the final
7210 branch back to the calling function. This pattern will be emitted before any
7211 sibling call (aka tail call) sites.
7213 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
7214 parameter passing or any stack slots for arguments passed to the current
7217 @cindex @code{trap} instruction pattern
7219 This pattern, if defined, signals an error, typically by causing some
7220 kind of signal to be raised.
7222 @cindex @code{ctrap@var{MM}4} instruction pattern
7223 @item @samp{ctrap@var{MM}4}
7224 Conditional trap instruction. Operand 0 is a piece of RTL which
7225 performs a comparison, and operands 1 and 2 are the arms of the
7226 comparison. Operand 3 is the trap code, an integer.
7228 A typical @code{ctrap} pattern looks like
7231 (define_insn "ctrapsi4"
7232 [(trap_if (match_operator 0 "trap_operator"
7233 [(match_operand 1 "register_operand")
7234 (match_operand 2 "immediate_operand")])
7235 (match_operand 3 "const_int_operand" "i"))]
7240 @cindex @code{prefetch} instruction pattern
7241 @item @samp{prefetch}
7242 This pattern, if defined, emits code for a non-faulting data prefetch
7243 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
7244 is a constant 1 if the prefetch is preparing for a write to the memory
7245 address, or a constant 0 otherwise. Operand 2 is the expected degree of
7246 temporal locality of the data and is a value between 0 and 3, inclusive; 0
7247 means that the data has no temporal locality, so it need not be left in the
7248 cache after the access; 3 means that the data has a high degree of temporal
7249 locality and should be left in all levels of cache possible; 1 and 2 mean,
7250 respectively, a low or moderate degree of temporal locality.
7252 Targets that do not support write prefetches or locality hints can ignore
7253 the values of operands 1 and 2.
7255 @cindex @code{blockage} instruction pattern
7256 @item @samp{blockage}
7257 This pattern defines a pseudo insn that prevents the instruction
7258 scheduler and other passes from moving instructions and using register
7259 equivalences across the boundary defined by the blockage insn.
7260 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
7262 @cindex @code{memory_blockage} instruction pattern
7263 @item @samp{memory_blockage}
7264 This pattern, if defined, represents a compiler memory barrier, and will be
7265 placed at points across which RTL passes may not propagate memory accesses.
7266 This instruction needs to read and write volatile BLKmode memory. It does
7267 not need to generate any machine instruction. If this pattern is not defined,
7268 the compiler falls back to emitting an instruction corresponding
7269 to @code{asm volatile ("" ::: "memory")}.
7271 @cindex @code{memory_barrier} instruction pattern
7272 @item @samp{memory_barrier}
7273 If the target memory model is not fully synchronous, then this pattern
7274 should be defined to an instruction that orders both loads and stores
7275 before the instruction with respect to loads and stores after the instruction.
7276 This pattern has no operands.
7278 @cindex @code{speculation_barrier} instruction pattern
7279 @item @samp{speculation_barrier}
7280 If the target can support speculative execution, then this pattern should
7281 be defined to an instruction that will block subsequent execution until
7282 any prior speculation conditions has been resolved. The pattern must also
7283 ensure that the compiler cannot move memory operations past the barrier,
7284 so it needs to be an UNSPEC_VOLATILE pattern. The pattern has no
7287 If this pattern is not defined then the default expansion of
7288 @code{__builtin_speculation_safe_value} will emit a warning. You can
7289 suppress this warning by defining this pattern with a final condition
7290 of @code{0} (zero), which tells the compiler that a speculation
7291 barrier is not needed for this target.
7293 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
7294 @item @samp{sync_compare_and_swap@var{mode}}
7295 This pattern, if defined, emits code for an atomic compare-and-swap
7296 operation. Operand 1 is the memory on which the atomic operation is
7297 performed. Operand 2 is the ``old'' value to be compared against the
7298 current contents of the memory location. Operand 3 is the ``new'' value
7299 to store in the memory if the compare succeeds. Operand 0 is the result
7300 of the operation; it should contain the contents of the memory
7301 before the operation. If the compare succeeds, this should obviously be
7302 a copy of operand 2.
7304 This pattern must show that both operand 0 and operand 1 are modified.
7306 This pattern must issue any memory barrier instructions such that all
7307 memory operations before the atomic operation occur before the atomic
7308 operation and all memory operations after the atomic operation occur
7309 after the atomic operation.
7311 For targets where the success or failure of the compare-and-swap
7312 operation is available via the status flags, it is possible to
7313 avoid a separate compare operation and issue the subsequent
7314 branch or store-flag operation immediately after the compare-and-swap.
7315 To this end, GCC will look for a @code{MODE_CC} set in the
7316 output of @code{sync_compare_and_swap@var{mode}}; if the machine
7317 description includes such a set, the target should also define special
7318 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
7319 be able to take the destination of the @code{MODE_CC} set and pass it
7320 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
7321 operand of the comparison (the second will be @code{(const_int 0)}).
7323 For targets where the operating system may provide support for this
7324 operation via library calls, the @code{sync_compare_and_swap_optab}
7325 may be initialized to a function with the same interface as the
7326 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
7327 set of @var{__sync} builtins are supported via library calls, the
7328 target can initialize all of the optabs at once with
7329 @code{init_sync_libfuncs}.
7330 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
7331 assumed that these library calls do @emph{not} use any kind of
7332 interruptable locking.
7334 @cindex @code{sync_add@var{mode}} instruction pattern
7335 @cindex @code{sync_sub@var{mode}} instruction pattern
7336 @cindex @code{sync_ior@var{mode}} instruction pattern
7337 @cindex @code{sync_and@var{mode}} instruction pattern
7338 @cindex @code{sync_xor@var{mode}} instruction pattern
7339 @cindex @code{sync_nand@var{mode}} instruction pattern
7340 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
7341 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
7342 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
7343 These patterns emit code for an atomic operation on memory.
7344 Operand 0 is the memory on which the atomic operation is performed.
7345 Operand 1 is the second operand to the binary operator.
7347 This pattern must issue any memory barrier instructions such that all
7348 memory operations before the atomic operation occur before the atomic
7349 operation and all memory operations after the atomic operation occur
7350 after the atomic operation.
7352 If these patterns are not defined, the operation will be constructed
7353 from a compare-and-swap operation, if defined.
7355 @cindex @code{sync_old_add@var{mode}} instruction pattern
7356 @cindex @code{sync_old_sub@var{mode}} instruction pattern
7357 @cindex @code{sync_old_ior@var{mode}} instruction pattern
7358 @cindex @code{sync_old_and@var{mode}} instruction pattern
7359 @cindex @code{sync_old_xor@var{mode}} instruction pattern
7360 @cindex @code{sync_old_nand@var{mode}} instruction pattern
7361 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
7362 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
7363 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
7364 These patterns emit code for an atomic operation on memory,
7365 and return the value that the memory contained before the operation.
7366 Operand 0 is the result value, operand 1 is the memory on which the
7367 atomic operation is performed, and operand 2 is the second operand
7368 to the binary operator.
7370 This pattern must issue any memory barrier instructions such that all
7371 memory operations before the atomic operation occur before the atomic
7372 operation and all memory operations after the atomic operation occur
7373 after the atomic operation.
7375 If these patterns are not defined, the operation will be constructed
7376 from a compare-and-swap operation, if defined.
7378 @cindex @code{sync_new_add@var{mode}} instruction pattern
7379 @cindex @code{sync_new_sub@var{mode}} instruction pattern
7380 @cindex @code{sync_new_ior@var{mode}} instruction pattern
7381 @cindex @code{sync_new_and@var{mode}} instruction pattern
7382 @cindex @code{sync_new_xor@var{mode}} instruction pattern
7383 @cindex @code{sync_new_nand@var{mode}} instruction pattern
7384 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
7385 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
7386 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
7387 These patterns are like their @code{sync_old_@var{op}} counterparts,
7388 except that they return the value that exists in the memory location
7389 after the operation, rather than before the operation.
7391 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
7392 @item @samp{sync_lock_test_and_set@var{mode}}
7393 This pattern takes two forms, based on the capabilities of the target.
7394 In either case, operand 0 is the result of the operand, operand 1 is
7395 the memory on which the atomic operation is performed, and operand 2
7396 is the value to set in the lock.
7398 In the ideal case, this operation is an atomic exchange operation, in
7399 which the previous value in memory operand is copied into the result
7400 operand, and the value operand is stored in the memory operand.
7402 For less capable targets, any value operand that is not the constant 1
7403 should be rejected with @code{FAIL}. In this case the target may use
7404 an atomic test-and-set bit operation. The result operand should contain
7405 1 if the bit was previously set and 0 if the bit was previously clear.
7406 The true contents of the memory operand are implementation defined.
7408 This pattern must issue any memory barrier instructions such that the
7409 pattern as a whole acts as an acquire barrier, that is all memory
7410 operations after the pattern do not occur until the lock is acquired.
7412 If this pattern is not defined, the operation will be constructed from
7413 a compare-and-swap operation, if defined.
7415 @cindex @code{sync_lock_release@var{mode}} instruction pattern
7416 @item @samp{sync_lock_release@var{mode}}
7417 This pattern, if defined, releases a lock set by
7418 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
7419 that contains the lock; operand 1 is the value to store in the lock.
7421 If the target doesn't implement full semantics for
7422 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
7423 the constant 0 should be rejected with @code{FAIL}, and the true contents
7424 of the memory operand are implementation defined.
7426 This pattern must issue any memory barrier instructions such that the
7427 pattern as a whole acts as a release barrier, that is the lock is
7428 released only after all previous memory operations have completed.
7430 If this pattern is not defined, then a @code{memory_barrier} pattern
7431 will be emitted, followed by a store of the value to the memory operand.
7433 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
7434 @item @samp{atomic_compare_and_swap@var{mode}}
7435 This pattern, if defined, emits code for an atomic compare-and-swap
7436 operation with memory model semantics. Operand 2 is the memory on which
7437 the atomic operation is performed. Operand 0 is an output operand which
7438 is set to true or false based on whether the operation succeeded. Operand
7439 1 is an output operand which is set to the contents of the memory before
7440 the operation was attempted. Operand 3 is the value that is expected to
7441 be in memory. Operand 4 is the value to put in memory if the expected
7442 value is found there. Operand 5 is set to 1 if this compare and swap is to
7443 be treated as a weak operation. Operand 6 is the memory model to be used
7444 if the operation is a success. Operand 7 is the memory model to be used
7445 if the operation fails.
7447 If memory referred to in operand 2 contains the value in operand 3, then
7448 operand 4 is stored in memory pointed to by operand 2 and fencing based on
7449 the memory model in operand 6 is issued.
7451 If memory referred to in operand 2 does not contain the value in operand 3,
7452 then fencing based on the memory model in operand 7 is issued.
7454 If a target does not support weak compare-and-swap operations, or the port
7455 elects not to implement weak operations, the argument in operand 5 can be
7456 ignored. Note a strong implementation must be provided.
7458 If this pattern is not provided, the @code{__atomic_compare_exchange}
7459 built-in functions will utilize the legacy @code{sync_compare_and_swap}
7460 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
7462 @cindex @code{atomic_load@var{mode}} instruction pattern
7463 @item @samp{atomic_load@var{mode}}
7464 This pattern implements an atomic load operation with memory model
7465 semantics. Operand 1 is the memory address being loaded from. Operand 0
7466 is the result of the load. Operand 2 is the memory model to be used for
7469 If not present, the @code{__atomic_load} built-in function will either
7470 resort to a normal load with memory barriers, or a compare-and-swap
7471 operation if a normal load would not be atomic.
7473 @cindex @code{atomic_store@var{mode}} instruction pattern
7474 @item @samp{atomic_store@var{mode}}
7475 This pattern implements an atomic store operation with memory model
7476 semantics. Operand 0 is the memory address being stored to. Operand 1
7477 is the value to be written. Operand 2 is the memory model to be used for
7480 If not present, the @code{__atomic_store} built-in function will attempt to
7481 perform a normal store and surround it with any required memory fences. If
7482 the store would not be atomic, then an @code{__atomic_exchange} is
7483 attempted with the result being ignored.
7485 @cindex @code{atomic_exchange@var{mode}} instruction pattern
7486 @item @samp{atomic_exchange@var{mode}}
7487 This pattern implements an atomic exchange operation with memory model
7488 semantics. Operand 1 is the memory location the operation is performed on.
7489 Operand 0 is an output operand which is set to the original value contained
7490 in the memory pointed to by operand 1. Operand 2 is the value to be
7491 stored. Operand 3 is the memory model to be used.
7493 If this pattern is not present, the built-in function
7494 @code{__atomic_exchange} will attempt to preform the operation with a
7495 compare and swap loop.
7497 @cindex @code{atomic_add@var{mode}} instruction pattern
7498 @cindex @code{atomic_sub@var{mode}} instruction pattern
7499 @cindex @code{atomic_or@var{mode}} instruction pattern
7500 @cindex @code{atomic_and@var{mode}} instruction pattern
7501 @cindex @code{atomic_xor@var{mode}} instruction pattern
7502 @cindex @code{atomic_nand@var{mode}} instruction pattern
7503 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
7504 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
7505 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
7506 These patterns emit code for an atomic operation on memory with memory
7507 model semantics. Operand 0 is the memory on which the atomic operation is
7508 performed. Operand 1 is the second operand to the binary operator.
7509 Operand 2 is the memory model to be used by the operation.
7511 If these patterns are not defined, attempts will be made to use legacy
7512 @code{sync} patterns, or equivalent patterns which return a result. If
7513 none of these are available a compare-and-swap loop will be used.
7515 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
7516 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
7517 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
7518 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
7519 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
7520 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
7521 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
7522 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
7523 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
7524 These patterns emit code for an atomic operation on memory with memory
7525 model semantics, and return the original value. Operand 0 is an output
7526 operand which contains the value of the memory location before the
7527 operation was performed. Operand 1 is the memory on which the atomic
7528 operation is performed. Operand 2 is the second operand to the binary
7529 operator. Operand 3 is the memory model to be used by the operation.
7531 If these patterns are not defined, attempts will be made to use legacy
7532 @code{sync} patterns. If none of these are available a compare-and-swap
7535 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
7536 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
7537 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
7538 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
7539 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
7540 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
7541 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
7542 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
7543 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
7544 These patterns emit code for an atomic operation on memory with memory
7545 model semantics and return the result after the operation is performed.
7546 Operand 0 is an output operand which contains the value after the
7547 operation. Operand 1 is the memory on which the atomic operation is
7548 performed. Operand 2 is the second operand to the binary operator.
7549 Operand 3 is the memory model to be used by the operation.
7551 If these patterns are not defined, attempts will be made to use legacy
7552 @code{sync} patterns, or equivalent patterns which return the result before
7553 the operation followed by the arithmetic operation required to produce the
7554 result. If none of these are available a compare-and-swap loop will be
7557 @cindex @code{atomic_test_and_set} instruction pattern
7558 @item @samp{atomic_test_and_set}
7559 This pattern emits code for @code{__builtin_atomic_test_and_set}.
7560 Operand 0 is an output operand which is set to true if the previous
7561 previous contents of the byte was "set", and false otherwise. Operand 1
7562 is the @code{QImode} memory to be modified. Operand 2 is the memory
7565 The specific value that defines "set" is implementation defined, and
7566 is normally based on what is performed by the native atomic test and set
7569 @cindex @code{atomic_bit_test_and_set@var{mode}} instruction pattern
7570 @cindex @code{atomic_bit_test_and_complement@var{mode}} instruction pattern
7571 @cindex @code{atomic_bit_test_and_reset@var{mode}} instruction pattern
7572 @item @samp{atomic_bit_test_and_set@var{mode}}
7573 @itemx @samp{atomic_bit_test_and_complement@var{mode}}
7574 @itemx @samp{atomic_bit_test_and_reset@var{mode}}
7575 These patterns emit code for an atomic bitwise operation on memory with memory
7576 model semantics, and return the original value of the specified bit.
7577 Operand 0 is an output operand which contains the value of the specified bit
7578 from the memory location before the operation was performed. Operand 1 is the
7579 memory on which the atomic operation is performed. Operand 2 is the bit within
7580 the operand, starting with least significant bit. Operand 3 is the memory model
7581 to be used by the operation. Operand 4 is a flag - it is @code{const1_rtx}
7582 if operand 0 should contain the original value of the specified bit in the
7583 least significant bit of the operand, and @code{const0_rtx} if the bit should
7584 be in its original position in the operand.
7585 @code{atomic_bit_test_and_set@var{mode}} atomically sets the specified bit after
7586 remembering its original value, @code{atomic_bit_test_and_complement@var{mode}}
7587 inverts the specified bit and @code{atomic_bit_test_and_reset@var{mode}} clears
7590 If these patterns are not defined, attempts will be made to use
7591 @code{atomic_fetch_or@var{mode}}, @code{atomic_fetch_xor@var{mode}} or
7592 @code{atomic_fetch_and@var{mode}} instruction patterns, or their @code{sync}
7593 counterparts. If none of these are available a compare-and-swap
7596 @cindex @code{mem_thread_fence} instruction pattern
7597 @item @samp{mem_thread_fence}
7598 This pattern emits code required to implement a thread fence with
7599 memory model semantics. Operand 0 is the memory model to be used.
7601 For the @code{__ATOMIC_RELAXED} model no instructions need to be issued
7602 and this expansion is not invoked.
7604 The compiler always emits a compiler memory barrier regardless of what
7605 expanding this pattern produced.
7607 If this pattern is not defined, the compiler falls back to expanding the
7608 @code{memory_barrier} pattern, then to emitting @code{__sync_synchronize}
7609 library call, and finally to just placing a compiler memory barrier.
7611 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
7612 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
7613 @item @samp{get_thread_pointer@var{mode}}
7614 @itemx @samp{set_thread_pointer@var{mode}}
7615 These patterns emit code that reads/sets the TLS thread pointer. Currently,
7616 these are only needed if the target needs to support the
7617 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
7620 The get/set patterns have a single output/input operand respectively,
7621 with @var{mode} intended to be @code{Pmode}.
7623 @cindex @code{stack_protect_combined_set} instruction pattern
7624 @item @samp{stack_protect_combined_set}
7625 This pattern, if defined, moves a @code{ptr_mode} value from an address
7626 whose declaration RTX is given in operand 1 to the memory in operand 0
7627 without leaving the value in a register afterward. If several
7628 instructions are needed by the target to perform the operation (eg. to
7629 load the address from a GOT entry then load the @code{ptr_mode} value
7630 and finally store it), it is the backend's responsibility to ensure no
7631 intermediate result gets spilled. This is to avoid leaking the value
7632 some place that an attacker might use to rewrite the stack guard slot
7633 after having clobbered it.
7635 If this pattern is not defined, then the address declaration is
7636 expanded first in the standard way and a @code{stack_protect_set}
7637 pattern is then generated to move the value from that address to the
7638 address in operand 0.
7640 @cindex @code{stack_protect_set} instruction pattern
7641 @item @samp{stack_protect_set}
7642 This pattern, if defined, moves a @code{ptr_mode} value from the valid
7643 memory location in operand 1 to the memory in operand 0 without leaving
7644 the value in a register afterward. This is to avoid leaking the value
7645 some place that an attacker might use to rewrite the stack guard slot
7646 after having clobbered it.
7648 Note: on targets where the addressing modes do not allow to load
7649 directly from stack guard address, the address is expanded in a standard
7650 way first which could cause some spills.
7652 If this pattern is not defined, then a plain move pattern is generated.
7654 @cindex @code{stack_protect_combined_test} instruction pattern
7655 @item @samp{stack_protect_combined_test}
7656 This pattern, if defined, compares a @code{ptr_mode} value from an
7657 address whose declaration RTX is given in operand 1 with the memory in
7658 operand 0 without leaving the value in a register afterward and
7659 branches to operand 2 if the values were equal. If several
7660 instructions are needed by the target to perform the operation (eg. to
7661 load the address from a GOT entry then load the @code{ptr_mode} value
7662 and finally store it), it is the backend's responsibility to ensure no
7663 intermediate result gets spilled. This is to avoid leaking the value
7664 some place that an attacker might use to rewrite the stack guard slot
7665 after having clobbered it.
7667 If this pattern is not defined, then the address declaration is
7668 expanded first in the standard way and a @code{stack_protect_test}
7669 pattern is then generated to compare the value from that address to the
7670 value at the memory in operand 0.
7672 @cindex @code{stack_protect_test} instruction pattern
7673 @item @samp{stack_protect_test}
7674 This pattern, if defined, compares a @code{ptr_mode} value from the
7675 valid memory location in operand 1 with the memory in operand 0 without
7676 leaving the value in a register afterward and branches to operand 2 if
7677 the values were equal.
7679 If this pattern is not defined, then a plain compare pattern and
7680 conditional branch pattern is used.
7682 @cindex @code{clear_cache} instruction pattern
7683 @item @samp{clear_cache}
7684 This pattern, if defined, flushes the instruction cache for a region of
7685 memory. The region is bounded to by the Pmode pointers in operand 0
7686 inclusive and operand 1 exclusive.
7688 If this pattern is not defined, a call to the library function
7689 @code{__clear_cache} is used.
7694 @c Each of the following nodes are wrapped in separate
7695 @c "@ifset INTERNALS" to work around memory limits for the default
7696 @c configuration in older tetex distributions. Known to not work:
7697 @c tetex-1.0.7, known to work: tetex-2.0.2.
7699 @node Pattern Ordering
7700 @section When the Order of Patterns Matters
7701 @cindex Pattern Ordering
7702 @cindex Ordering of Patterns
7704 Sometimes an insn can match more than one instruction pattern. Then the
7705 pattern that appears first in the machine description is the one used.
7706 Therefore, more specific patterns (patterns that will match fewer things)
7707 and faster instructions (those that will produce better code when they
7708 do match) should usually go first in the description.
7710 In some cases the effect of ordering the patterns can be used to hide
7711 a pattern when it is not valid. For example, the 68000 has an
7712 instruction for converting a fullword to floating point and another
7713 for converting a byte to floating point. An instruction converting
7714 an integer to floating point could match either one. We put the
7715 pattern to convert the fullword first to make sure that one will
7716 be used rather than the other. (Otherwise a large integer might
7717 be generated as a single-byte immediate quantity, which would not work.)
7718 Instead of using this pattern ordering it would be possible to make the
7719 pattern for convert-a-byte smart enough to deal properly with any
7724 @node Dependent Patterns
7725 @section Interdependence of Patterns
7726 @cindex Dependent Patterns
7727 @cindex Interdependence of Patterns
7729 In some cases machines support instructions identical except for the
7730 machine mode of one or more operands. For example, there may be
7731 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
7735 (set (match_operand:SI 0 @dots{})
7736 (extend:SI (match_operand:HI 1 @dots{})))
7738 (set (match_operand:SI 0 @dots{})
7739 (extend:SI (match_operand:QI 1 @dots{})))
7743 Constant integers do not specify a machine mode, so an instruction to
7744 extend a constant value could match either pattern. The pattern it
7745 actually will match is the one that appears first in the file. For correct
7746 results, this must be the one for the widest possible mode (@code{HImode},
7747 here). If the pattern matches the @code{QImode} instruction, the results
7748 will be incorrect if the constant value does not actually fit that mode.
7750 Such instructions to extend constants are rarely generated because they are
7751 optimized away, but they do occasionally happen in nonoptimized
7754 If a constraint in a pattern allows a constant, the reload pass may
7755 replace a register with a constant permitted by the constraint in some
7756 cases. Similarly for memory references. Because of this substitution,
7757 you should not provide separate patterns for increment and decrement
7758 instructions. Instead, they should be generated from the same pattern
7759 that supports register-register add insns by examining the operands and
7760 generating the appropriate machine instruction.
7765 @section Defining Jump Instruction Patterns
7766 @cindex jump instruction patterns
7767 @cindex defining jump instruction patterns
7769 GCC does not assume anything about how the machine realizes jumps.
7770 The machine description should define a single pattern, usually
7771 a @code{define_expand}, which expands to all the required insns.
7773 Usually, this would be a comparison insn to set the condition code
7774 and a separate branch insn testing the condition code and branching
7775 or not according to its value. For many machines, however,
7776 separating compares and branches is limiting, which is why the
7777 more flexible approach with one @code{define_expand} is used in GCC.
7778 The machine description becomes clearer for architectures that
7779 have compare-and-branch instructions but no condition code. It also
7780 works better when different sets of comparison operators are supported
7781 by different kinds of conditional branches (e.g.@: integer vs.@:
7782 floating-point), or by conditional branches with respect to conditional stores.
7784 Two separate insns are always used if the machine description represents
7785 a condition code register using the legacy RTL expression @code{(cc0)},
7786 and on most machines that use a separate condition code register
7787 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
7788 fact, the set and use of the condition code must be separate and
7789 adjacent@footnote{@code{note} insns can separate them, though.}, thus
7790 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
7791 so that the comparison and branch insns could be located from each other
7792 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
7794 Even in this case having a single entry point for conditional branches
7795 is advantageous, because it handles equally well the case where a single
7796 comparison instruction records the results of both signed and unsigned
7797 comparison of the given operands (with the branch insns coming in distinct
7798 signed and unsigned flavors) as in the x86 or SPARC, and the case where
7799 there are distinct signed and unsigned compare instructions and only
7800 one set of conditional branch instructions as in the PowerPC.
7804 @node Looping Patterns
7805 @section Defining Looping Instruction Patterns
7806 @cindex looping instruction patterns
7807 @cindex defining looping instruction patterns
7809 Some machines have special jump instructions that can be utilized to
7810 make loops more efficient. A common example is the 68000 @samp{dbra}
7811 instruction which performs a decrement of a register and a branch if the
7812 result was greater than zero. Other machines, in particular digital
7813 signal processors (DSPs), have special block repeat instructions to
7814 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
7815 DSPs have a block repeat instruction that loads special registers to
7816 mark the top and end of a loop and to count the number of loop
7817 iterations. This avoids the need for fetching and executing a
7818 @samp{dbra}-like instruction and avoids pipeline stalls associated with
7821 GCC has two special named patterns to support low overhead looping.
7822 They are @samp{doloop_begin} and @samp{doloop_end}. These are emitted
7823 by the loop optimizer for certain well-behaved loops with a finite
7824 number of loop iterations using information collected during strength
7827 The @samp{doloop_end} pattern describes the actual looping instruction
7828 (or the implicit looping operation) and the @samp{doloop_begin} pattern
7829 is an optional companion pattern that can be used for initialization
7830 needed for some low-overhead looping instructions.
7832 Note that some machines require the actual looping instruction to be
7833 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
7834 the true RTL for a looping instruction at the top of the loop can cause
7835 problems with flow analysis. So instead, a dummy @code{doloop} insn is
7836 emitted at the end of the loop. The machine dependent reorg pass checks
7837 for the presence of this @code{doloop} insn and then searches back to
7838 the top of the loop, where it inserts the true looping insn (provided
7839 there are no instructions in the loop which would cause problems). Any
7840 additional labels can be emitted at this point. In addition, if the
7841 desired special iteration counter register was not allocated, this
7842 machine dependent reorg pass could emit a traditional compare and jump
7845 For the @samp{doloop_end} pattern, the loop optimizer allocates an
7846 additional pseudo register as an iteration counter. This pseudo
7847 register cannot be used within the loop (i.e., general induction
7848 variables cannot be derived from it), however, in many cases the loop
7849 induction variable may become redundant and removed by the flow pass.
7851 The @samp{doloop_end} pattern must have a specific structure to be
7852 handled correctly by GCC. The example below is taken (slightly
7853 simplified) from the PDP-11 target:
7857 (define_expand "doloop_end"
7858 [(parallel [(set (pc)
7860 (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m")
7862 (label_ref (match_operand 1 "" ""))
7865 (plus:HI (match_dup 0)
7869 if (GET_MODE (operands[0]) != HImode)
7873 (define_insn "doloop_end_insn"
7876 (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m")
7878 (label_ref (match_operand 1 "" ""))
7881 (plus:HI (match_dup 0)
7886 if (which_alternative == 0)
7887 return "sob %0,%l1";
7890 output_asm_insn ("dec %0", operands);
7896 The first part of the pattern describes the branch condition. GCC
7897 supports three cases for the way the target machine handles the loop
7900 @item Loop terminates when the loop register decrements to zero. This
7901 is represented by a @code{ne} comparison of the register (its old value)
7902 with constant 1 (as in the example above).
7903 @item Loop terminates when the loop register decrements to @minus{}1.
7904 This is represented by a @code{ne} comparison of the register with
7906 @item Loop terminates when the loop register decrements to a negative
7907 value. This is represented by a @code{ge} comparison of the register
7908 with constant zero. For this case, GCC will attach a @code{REG_NONNEG}
7909 note to the @code{doloop_end} insn if it can determine that the register
7910 will be non-negative.
7913 Since the @code{doloop_end} insn is a jump insn that also has an output,
7914 the reload pass does not handle the output operand. Therefore, the
7915 constraint must allow for that operand to be in memory rather than a
7916 register. In the example shown above, that is handled (in the
7917 @code{doloop_end_insn} pattern) by using a loop instruction sequence
7918 that can handle memory operands when the memory alternative appears.
7920 GCC does not check the mode of the loop register operand when generating
7921 the @code{doloop_end} pattern. If the pattern is only valid for some
7922 modes but not others, the pattern should be a @code{define_expand}
7923 pattern that checks the operand mode in the preparation code, and issues
7924 @code{FAIL} if an unsupported mode is found. The example above does
7925 this, since the machine instruction to be used only exists for
7928 If the @code{doloop_end} pattern is a @code{define_expand}, there must
7929 also be a @code{define_insn} or @code{define_insn_and_split} matching
7930 the generated pattern. Otherwise, the compiler will fail during loop
7935 @node Insn Canonicalizations
7936 @section Canonicalization of Instructions
7937 @cindex canonicalization of instructions
7938 @cindex insn canonicalization
7940 There are often cases where multiple RTL expressions could represent an
7941 operation performed by a single machine instruction. This situation is
7942 most commonly encountered with logical, branch, and multiply-accumulate
7943 instructions. In such cases, the compiler attempts to convert these
7944 multiple RTL expressions into a single canonical form to reduce the
7945 number of insn patterns required.
7947 In addition to algebraic simplifications, following canonicalizations
7952 For commutative and comparison operators, a constant is always made the
7953 second operand. If a machine only supports a constant as the second
7954 operand, only patterns that match a constant in the second operand need
7958 For associative operators, a sequence of operators will always chain
7959 to the left; for instance, only the left operand of an integer @code{plus}
7960 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
7961 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
7962 @code{umax} are associative when applied to integers, and sometimes to
7966 @cindex @code{neg}, canonicalization of
7967 @cindex @code{not}, canonicalization of
7968 @cindex @code{mult}, canonicalization of
7969 @cindex @code{plus}, canonicalization of
7970 @cindex @code{minus}, canonicalization of
7971 For these operators, if only one operand is a @code{neg}, @code{not},
7972 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
7976 In combinations of @code{neg}, @code{mult}, @code{plus}, and
7977 @code{minus}, the @code{neg} operations (if any) will be moved inside
7978 the operations as far as possible. For instance,
7979 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
7980 @code{(plus (mult (neg B) C) A)} is canonicalized as
7981 @code{(minus A (mult B C))}.
7983 @cindex @code{compare}, canonicalization of
7985 For the @code{compare} operator, a constant is always the second operand
7986 if the first argument is a condition code register or @code{(cc0)}.
7989 For instructions that inherently set a condition code register, the
7990 @code{compare} operator is always written as the first RTL expression of
7991 the @code{parallel} instruction pattern. For example,
7995 [(set (reg:CCZ FLAGS_REG)
7998 (match_operand:SI 1 "register_operand" "%r")
7999 (match_operand:SI 2 "register_operand" "r"))
8001 (set (match_operand:SI 0 "register_operand" "=r")
8002 (plus:SI (match_dup 1) (match_dup 2)))]
8008 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
8009 @code{minus} is made the first operand under the same conditions as
8013 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
8014 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
8018 @code{(minus @var{x} (const_int @var{n}))} is converted to
8019 @code{(plus @var{x} (const_int @var{-n}))}.
8022 Within address computations (i.e., inside @code{mem}), a left shift is
8023 converted into the appropriate multiplication by a power of two.
8025 @cindex @code{ior}, canonicalization of
8026 @cindex @code{and}, canonicalization of
8027 @cindex De Morgan's law
8029 De Morgan's Law is used to move bitwise negation inside a bitwise
8030 logical-and or logical-or operation. If this results in only one
8031 operand being a @code{not} expression, it will be the first one.
8033 A machine that has an instruction that performs a bitwise logical-and of one
8034 operand with the bitwise negation of the other should specify the pattern
8035 for that instruction as
8039 [(set (match_operand:@var{m} 0 @dots{})
8040 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
8041 (match_operand:@var{m} 2 @dots{})))]
8047 Similarly, a pattern for a ``NAND'' instruction should be written
8051 [(set (match_operand:@var{m} 0 @dots{})
8052 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
8053 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
8058 In both cases, it is not necessary to include patterns for the many
8059 logically equivalent RTL expressions.
8061 @cindex @code{xor}, canonicalization of
8063 The only possible RTL expressions involving both bitwise exclusive-or
8064 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
8065 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
8068 The sum of three items, one of which is a constant, will only appear in
8072 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
8075 @cindex @code{zero_extract}, canonicalization of
8076 @cindex @code{sign_extract}, canonicalization of
8078 Equality comparisons of a group of bits (usually a single bit) with zero
8079 will be written using @code{zero_extract} rather than the equivalent
8080 @code{and} or @code{sign_extract} operations.
8082 @cindex @code{mult}, canonicalization of
8084 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
8085 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
8086 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
8087 for @code{zero_extend}.
8090 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
8091 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
8092 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
8093 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
8094 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
8095 operand of @code{mult} is also a shift, then that is extended also.
8096 This transformation is only applied when it can be proven that the
8097 original operation had sufficient precision to prevent overflow.
8101 Further canonicalization rules are defined in the function
8102 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
8106 @node Expander Definitions
8107 @section Defining RTL Sequences for Code Generation
8108 @cindex expander definitions
8109 @cindex code generation RTL sequences
8110 @cindex defining RTL sequences for code generation
8112 On some target machines, some standard pattern names for RTL generation
8113 cannot be handled with single insn, but a sequence of RTL insns can
8114 represent them. For these target machines, you can write a
8115 @code{define_expand} to specify how to generate the sequence of RTL@.
8117 @findex define_expand
8118 A @code{define_expand} is an RTL expression that looks almost like a
8119 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
8120 only for RTL generation and it can produce more than one RTL insn.
8122 A @code{define_expand} RTX has four operands:
8126 The name. Each @code{define_expand} must have a name, since the only
8127 use for it is to refer to it by name.
8130 The RTL template. This is a vector of RTL expressions representing
8131 a sequence of separate instructions. Unlike @code{define_insn}, there
8132 is no implicit surrounding @code{PARALLEL}.
8135 The condition, a string containing a C expression. This expression is
8136 used to express how the availability of this pattern depends on
8137 subclasses of target machine, selected by command-line options when GCC
8138 is run. This is just like the condition of a @code{define_insn} that
8139 has a standard name. Therefore, the condition (if present) may not
8140 depend on the data in the insn being matched, but only the
8141 target-machine-type flags. The compiler needs to test these conditions
8142 during initialization in order to learn exactly which named instructions
8143 are available in a particular run.
8146 The preparation statements, a string containing zero or more C
8147 statements which are to be executed before RTL code is generated from
8150 Usually these statements prepare temporary registers for use as
8151 internal operands in the RTL template, but they can also generate RTL
8152 insns directly by calling routines such as @code{emit_insn}, etc.
8153 Any such insns precede the ones that come from the RTL template.
8156 Optionally, a vector containing the values of attributes. @xref{Insn
8160 Every RTL insn emitted by a @code{define_expand} must match some
8161 @code{define_insn} in the machine description. Otherwise, the compiler
8162 will crash when trying to generate code for the insn or trying to optimize
8165 The RTL template, in addition to controlling generation of RTL insns,
8166 also describes the operands that need to be specified when this pattern
8167 is used. In particular, it gives a predicate for each operand.
8169 A true operand, which needs to be specified in order to generate RTL from
8170 the pattern, should be described with a @code{match_operand} in its first
8171 occurrence in the RTL template. This enters information on the operand's
8172 predicate into the tables that record such things. GCC uses the
8173 information to preload the operand into a register if that is required for
8174 valid RTL code. If the operand is referred to more than once, subsequent
8175 references should use @code{match_dup}.
8177 The RTL template may also refer to internal ``operands'' which are
8178 temporary registers or labels used only within the sequence made by the
8179 @code{define_expand}. Internal operands are substituted into the RTL
8180 template with @code{match_dup}, never with @code{match_operand}. The
8181 values of the internal operands are not passed in as arguments by the
8182 compiler when it requests use of this pattern. Instead, they are computed
8183 within the pattern, in the preparation statements. These statements
8184 compute the values and store them into the appropriate elements of
8185 @code{operands} so that @code{match_dup} can find them.
8187 There are two special macros defined for use in the preparation statements:
8188 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8195 Use the @code{DONE} macro to end RTL generation for the pattern. The
8196 only RTL insns resulting from the pattern on this occasion will be
8197 those already emitted by explicit calls to @code{emit_insn} within the
8198 preparation statements; the RTL template will not be generated.
8202 Make the pattern fail on this occasion. When a pattern fails, it means
8203 that the pattern was not truly available. The calling routines in the
8204 compiler will try other strategies for code generation using other patterns.
8206 Failure is currently supported only for binary (addition, multiplication,
8207 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
8211 If the preparation falls through (invokes neither @code{DONE} nor
8212 @code{FAIL}), then the @code{define_expand} acts like a
8213 @code{define_insn} in that the RTL template is used to generate the
8216 The RTL template is not used for matching, only for generating the
8217 initial insn list. If the preparation statement always invokes
8218 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
8219 list of operands, such as this example:
8223 (define_expand "addsi3"
8224 [(match_operand:SI 0 "register_operand" "")
8225 (match_operand:SI 1 "register_operand" "")
8226 (match_operand:SI 2 "register_operand" "")]
8232 handle_add (operands[0], operands[1], operands[2]);
8238 Here is an example, the definition of left-shift for the SPUR chip:
8242 (define_expand "ashlsi3"
8243 [(set (match_operand:SI 0 "register_operand" "")
8247 (match_operand:SI 1 "register_operand" "")
8248 (match_operand:SI 2 "nonmemory_operand" "")))]
8257 if (GET_CODE (operands[2]) != CONST_INT
8258 || (unsigned) INTVAL (operands[2]) > 3)
8265 This example uses @code{define_expand} so that it can generate an RTL insn
8266 for shifting when the shift-count is in the supported range of 0 to 3 but
8267 fail in other cases where machine insns aren't available. When it fails,
8268 the compiler tries another strategy using different patterns (such as, a
8271 If the compiler were able to handle nontrivial condition-strings in
8272 patterns with names, then it would be possible to use a
8273 @code{define_insn} in that case. Here is another case (zero-extension
8274 on the 68000) which makes more use of the power of @code{define_expand}:
8277 (define_expand "zero_extendhisi2"
8278 [(set (match_operand:SI 0 "general_operand" "")
8280 (set (strict_low_part
8284 (match_operand:HI 1 "general_operand" ""))]
8286 "operands[1] = make_safe_from (operands[1], operands[0]);")
8290 @findex make_safe_from
8291 Here two RTL insns are generated, one to clear the entire output operand
8292 and the other to copy the input operand into its low half. This sequence
8293 is incorrect if the input operand refers to [the old value of] the output
8294 operand, so the preparation statement makes sure this isn't so. The
8295 function @code{make_safe_from} copies the @code{operands[1]} into a
8296 temporary register if it refers to @code{operands[0]}. It does this
8297 by emitting another RTL insn.
8299 Finally, a third example shows the use of an internal operand.
8300 Zero-extension on the SPUR chip is done by @code{and}-ing the result
8301 against a halfword mask. But this mask cannot be represented by a
8302 @code{const_int} because the constant value is too large to be legitimate
8303 on this machine. So it must be copied into a register with
8304 @code{force_reg} and then the register used in the @code{and}.
8307 (define_expand "zero_extendhisi2"
8308 [(set (match_operand:SI 0 "register_operand" "")
8310 (match_operand:HI 1 "register_operand" "")
8315 = force_reg (SImode, GEN_INT (65535)); ")
8318 @emph{Note:} If the @code{define_expand} is used to serve a
8319 standard binary or unary arithmetic operation or a bit-field operation,
8320 then the last insn it generates must not be a @code{code_label},
8321 @code{barrier} or @code{note}. It must be an @code{insn},
8322 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
8323 at the end, emit an insn to copy the result of the operation into
8324 itself. Such an insn will generate no code, but it can avoid problems
8329 @node Insn Splitting
8330 @section Defining How to Split Instructions
8331 @cindex insn splitting
8332 @cindex instruction splitting
8333 @cindex splitting instructions
8335 There are two cases where you should specify how to split a pattern
8336 into multiple insns. On machines that have instructions requiring
8337 delay slots (@pxref{Delay Slots}) or that have instructions whose
8338 output is not available for multiple cycles (@pxref{Processor pipeline
8339 description}), the compiler phases that optimize these cases need to
8340 be able to move insns into one-instruction delay slots. However, some
8341 insns may generate more than one machine instruction. These insns
8342 cannot be placed into a delay slot.
8344 Often you can rewrite the single insn as a list of individual insns,
8345 each corresponding to one machine instruction. The disadvantage of
8346 doing so is that it will cause the compilation to be slower and require
8347 more space. If the resulting insns are too complex, it may also
8348 suppress some optimizations. The compiler splits the insn if there is a
8349 reason to believe that it might improve instruction or delay slot
8352 The insn combiner phase also splits putative insns. If three insns are
8353 merged into one insn with a complex expression that cannot be matched by
8354 some @code{define_insn} pattern, the combiner phase attempts to split
8355 the complex pattern into two insns that are recognized. Usually it can
8356 break the complex pattern into two patterns by splitting out some
8357 subexpression. However, in some other cases, such as performing an
8358 addition of a large constant in two insns on a RISC machine, the way to
8359 split the addition into two insns is machine-dependent.
8361 @findex define_split
8362 The @code{define_split} definition tells the compiler how to split a
8363 complex insn into several simpler insns. It looks like this:
8367 [@var{insn-pattern}]
8369 [@var{new-insn-pattern-1}
8370 @var{new-insn-pattern-2}
8372 "@var{preparation-statements}")
8375 @var{insn-pattern} is a pattern that needs to be split and
8376 @var{condition} is the final condition to be tested, as in a
8377 @code{define_insn}. When an insn matching @var{insn-pattern} and
8378 satisfying @var{condition} is found, it is replaced in the insn list
8379 with the insns given by @var{new-insn-pattern-1},
8380 @var{new-insn-pattern-2}, etc.
8382 The @var{preparation-statements} are similar to those statements that
8383 are specified for @code{define_expand} (@pxref{Expander Definitions})
8384 and are executed before the new RTL is generated to prepare for the
8385 generated code or emit some insns whose pattern is not fixed. Unlike
8386 those in @code{define_expand}, however, these statements must not
8387 generate any new pseudo-registers. Once reload has completed, they also
8388 must not allocate any space in the stack frame.
8390 There are two special macros defined for use in the preparation statements:
8391 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8398 Use the @code{DONE} macro to end RTL generation for the splitter. The
8399 only RTL insns generated as replacement for the matched input insn will
8400 be those already emitted by explicit calls to @code{emit_insn} within
8401 the preparation statements; the replacement pattern is not used.
8405 Make the @code{define_split} fail on this occasion. When a @code{define_split}
8406 fails, it means that the splitter was not truly available for the inputs
8407 it was given, and the input insn will not be split.
8410 If the preparation falls through (invokes neither @code{DONE} nor
8411 @code{FAIL}), then the @code{define_split} uses the replacement
8414 Patterns are matched against @var{insn-pattern} in two different
8415 circumstances. If an insn needs to be split for delay slot scheduling
8416 or insn scheduling, the insn is already known to be valid, which means
8417 that it must have been matched by some @code{define_insn} and, if
8418 @code{reload_completed} is nonzero, is known to satisfy the constraints
8419 of that @code{define_insn}. In that case, the new insn patterns must
8420 also be insns that are matched by some @code{define_insn} and, if
8421 @code{reload_completed} is nonzero, must also satisfy the constraints
8422 of those definitions.
8424 As an example of this usage of @code{define_split}, consider the following
8425 example from @file{a29k.md}, which splits a @code{sign_extend} from
8426 @code{HImode} to @code{SImode} into a pair of shift insns:
8430 [(set (match_operand:SI 0 "gen_reg_operand" "")
8431 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
8434 (ashift:SI (match_dup 1)
8437 (ashiftrt:SI (match_dup 0)
8440 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
8443 When the combiner phase tries to split an insn pattern, it is always the
8444 case that the pattern is @emph{not} matched by any @code{define_insn}.
8445 The combiner pass first tries to split a single @code{set} expression
8446 and then the same @code{set} expression inside a @code{parallel}, but
8447 followed by a @code{clobber} of a pseudo-reg to use as a scratch
8448 register. In these cases, the combiner expects exactly one or two new insn
8449 patterns to be generated. It will verify that these patterns match some
8450 @code{define_insn} definitions, so you need not do this test in the
8451 @code{define_split} (of course, there is no point in writing a
8452 @code{define_split} that will never produce insns that match).
8454 Here is an example of this use of @code{define_split}, taken from
8459 [(set (match_operand:SI 0 "gen_reg_operand" "")
8460 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
8461 (match_operand:SI 2 "non_add_cint_operand" "")))]
8463 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
8464 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
8467 int low = INTVAL (operands[2]) & 0xffff;
8468 int high = (unsigned) INTVAL (operands[2]) >> 16;
8471 high++, low |= 0xffff0000;
8473 operands[3] = GEN_INT (high << 16);
8474 operands[4] = GEN_INT (low);
8478 Here the predicate @code{non_add_cint_operand} matches any
8479 @code{const_int} that is @emph{not} a valid operand of a single add
8480 insn. The add with the smaller displacement is written so that it
8481 can be substituted into the address of a subsequent operation.
8483 An example that uses a scratch register, from the same file, generates
8484 an equality comparison of a register and a large constant:
8488 [(set (match_operand:CC 0 "cc_reg_operand" "")
8489 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
8490 (match_operand:SI 2 "non_short_cint_operand" "")))
8491 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
8492 "find_single_use (operands[0], insn, 0)
8493 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
8494 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
8495 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
8496 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
8499 /* @r{Get the constant we are comparing against, C, and see what it
8500 looks like sign-extended to 16 bits. Then see what constant
8501 could be XOR'ed with C to get the sign-extended value.} */
8503 int c = INTVAL (operands[2]);
8504 int sextc = (c << 16) >> 16;
8505 int xorv = c ^ sextc;
8507 operands[4] = GEN_INT (xorv);
8508 operands[5] = GEN_INT (sextc);
8512 To avoid confusion, don't write a single @code{define_split} that
8513 accepts some insns that match some @code{define_insn} as well as some
8514 insns that don't. Instead, write two separate @code{define_split}
8515 definitions, one for the insns that are valid and one for the insns that
8518 The splitter is allowed to split jump instructions into sequence of
8519 jumps or create new jumps in while splitting non-jump instructions. As
8520 the control flow graph and branch prediction information needs to be updated,
8521 several restriction apply.
8523 Splitting of jump instruction into sequence that over by another jump
8524 instruction is always valid, as compiler expect identical behavior of new
8525 jump. When new sequence contains multiple jump instructions or new labels,
8526 more assistance is needed. Splitter is required to create only unconditional
8527 jumps, or simple conditional jump instructions. Additionally it must attach a
8528 @code{REG_BR_PROB} note to each conditional jump. A global variable
8529 @code{split_branch_probability} holds the probability of the original branch in case
8530 it was a simple conditional jump, @minus{}1 otherwise. To simplify
8531 recomputing of edge frequencies, the new sequence is required to have only
8532 forward jumps to the newly created labels.
8534 @findex define_insn_and_split
8535 For the common case where the pattern of a define_split exactly matches the
8536 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
8540 (define_insn_and_split
8541 [@var{insn-pattern}]
8543 "@var{output-template}"
8544 "@var{split-condition}"
8545 [@var{new-insn-pattern-1}
8546 @var{new-insn-pattern-2}
8548 "@var{preparation-statements}"
8549 [@var{insn-attributes}])
8553 @var{insn-pattern}, @var{condition}, @var{output-template}, and
8554 @var{insn-attributes} are used as in @code{define_insn}. The
8555 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
8556 in a @code{define_split}. The @var{split-condition} is also used as in
8557 @code{define_split}, with the additional behavior that if the condition starts
8558 with @samp{&&}, the condition used for the split will be the constructed as a
8559 logical ``and'' of the split condition with the insn condition. For example,
8563 (define_insn_and_split "zero_extendhisi2_and"
8564 [(set (match_operand:SI 0 "register_operand" "=r")
8565 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
8566 (clobber (reg:CC 17))]
8567 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
8569 "&& reload_completed"
8570 [(parallel [(set (match_dup 0)
8571 (and:SI (match_dup 0) (const_int 65535)))
8572 (clobber (reg:CC 17))])]
8574 [(set_attr "type" "alu1")])
8578 In this case, the actual split condition will be
8579 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
8581 The @code{define_insn_and_split} construction provides exactly the same
8582 functionality as two separate @code{define_insn} and @code{define_split}
8583 patterns. It exists for compactness, and as a maintenance tool to prevent
8584 having to ensure the two patterns' templates match.
8586 @findex define_insn_and_rewrite
8587 It is sometimes useful to have a @code{define_insn_and_split}
8588 that replaces specific operands of an instruction but leaves the
8589 rest of the instruction pattern unchanged. You can do this directly
8590 with a @code{define_insn_and_split}, but it requires a
8591 @var{new-insn-pattern-1} that repeats most of the original @var{insn-pattern}.
8592 There is also the complication that an implicit @code{parallel} in
8593 @var{insn-pattern} must become an explicit @code{parallel} in
8594 @var{new-insn-pattern-1}, which is easy to overlook.
8595 A simpler alternative is to use @code{define_insn_and_rewrite}, which
8596 is a form of @code{define_insn_and_split} that automatically generates
8597 @var{new-insn-pattern-1} by replacing each @code{match_operand}
8598 in @var{insn-pattern} with a corresponding @code{match_dup}, and each
8599 @code{match_operator} in the pattern with a corresponding @code{match_op_dup}.
8600 The arguments are otherwise identical to @code{define_insn_and_split}:
8603 (define_insn_and_rewrite
8604 [@var{insn-pattern}]
8606 "@var{output-template}"
8607 "@var{split-condition}"
8608 "@var{preparation-statements}"
8609 [@var{insn-attributes}])
8612 The @code{match_dup}s and @code{match_op_dup}s in the new
8613 instruction pattern use any new operand values that the
8614 @var{preparation-statements} store in the @code{operands} array,
8615 as for a normal @code{define_insn_and_split}. @var{preparation-statements}
8616 can also emit additional instructions before the new instruction.
8617 They can even emit an entirely different sequence of instructions and
8618 use @code{DONE} to avoid emitting a new form of the original
8621 The split in a @code{define_insn_and_rewrite} is only intended
8622 to apply to existing instructions that match @var{insn-pattern}.
8623 @var{split-condition} must therefore start with @code{&&},
8624 so that the split condition applies on top of @var{condition}.
8626 Here is an example from the AArch64 SVE port, in which operand 1 is
8627 known to be equivalent to an all-true constant and isn't used by the
8631 (define_insn_and_rewrite "*while_ult<GPI:mode><PRED_ALL:mode>_cc"
8632 [(set (reg:CC CC_REGNUM)
8634 (unspec:SI [(match_operand:PRED_ALL 1)
8636 [(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")
8637 (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")]
8641 (set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
8642 (unspec:PRED_ALL [(match_dup 2)
8646 "whilelo\t%0.<PRED_ALL:Vetype>, %<w>2, %<w>3"
8647 ;; Force the compiler to drop the unused predicate operand, so that we
8648 ;; don't have an unnecessary PTRUE.
8649 "&& !CONSTANT_P (operands[1])"
8651 operands[1] = CONSTM1_RTX (<MODE>mode);
8656 The splitter in this case simply replaces operand 1 with the constant
8657 value that it is known to have. The equivalent @code{define_insn_and_split}
8661 (define_insn_and_split "*while_ult<GPI:mode><PRED_ALL:mode>_cc"
8662 [(set (reg:CC CC_REGNUM)
8664 (unspec:SI [(match_operand:PRED_ALL 1)
8666 [(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")
8667 (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")]
8671 (set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
8672 (unspec:PRED_ALL [(match_dup 2)
8676 "whilelo\t%0.<PRED_ALL:Vetype>, %<w>2, %<w>3"
8677 ;; Force the compiler to drop the unused predicate operand, so that we
8678 ;; don't have an unnecessary PTRUE.
8679 "&& !CONSTANT_P (operands[1])"
8681 [(set (reg:CC CC_REGNUM)
8683 (unspec:SI [(match_dup 1)
8684 (unspec:PRED_ALL [(match_dup 2)
8690 (unspec:PRED_ALL [(match_dup 2)
8692 UNSPEC_WHILE_LO))])]
8694 operands[1] = CONSTM1_RTX (<MODE>mode);
8701 @node Including Patterns
8702 @section Including Patterns in Machine Descriptions.
8703 @cindex insn includes
8706 The @code{include} pattern tells the compiler tools where to
8707 look for patterns that are in files other than in the file
8708 @file{.md}. This is used only at build time and there is no preprocessing allowed.
8722 (include "filestuff")
8726 Where @var{pathname} is a string that specifies the location of the file,
8727 specifies the include file to be in @file{gcc/config/target/filestuff}. The
8728 directory @file{gcc/config/target} is regarded as the default directory.
8731 Machine descriptions may be split up into smaller more manageable subsections
8732 and placed into subdirectories.
8738 (include "BOGUS/filestuff")
8742 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
8744 Specifying an absolute path for the include file such as;
8747 (include "/u2/BOGUS/filestuff")
8750 is permitted but is not encouraged.
8752 @subsection RTL Generation Tool Options for Directory Search
8753 @cindex directory options .md
8754 @cindex options, directory search
8755 @cindex search options
8757 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
8762 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
8767 Add the directory @var{dir} to the head of the list of directories to be
8768 searched for header files. This can be used to override a system machine definition
8769 file, substituting your own version, since these directories are
8770 searched before the default machine description file directories. If you use more than
8771 one @option{-I} option, the directories are scanned in left-to-right
8772 order; the standard default directory come after.
8777 @node Peephole Definitions
8778 @section Machine-Specific Peephole Optimizers
8779 @cindex peephole optimizer definitions
8780 @cindex defining peephole optimizers
8782 In addition to instruction patterns the @file{md} file may contain
8783 definitions of machine-specific peephole optimizations.
8785 The combiner does not notice certain peephole optimizations when the data
8786 flow in the program does not suggest that it should try them. For example,
8787 sometimes two consecutive insns related in purpose can be combined even
8788 though the second one does not appear to use a register computed in the
8789 first one. A machine-specific peephole optimizer can detect such
8792 There are two forms of peephole definitions that may be used. The
8793 original @code{define_peephole} is run at assembly output time to
8794 match insns and substitute assembly text. Use of @code{define_peephole}
8797 A newer @code{define_peephole2} matches insns and substitutes new
8798 insns. The @code{peephole2} pass is run after register allocation
8799 but before scheduling, which may result in much better code for
8800 targets that do scheduling.
8803 * define_peephole:: RTL to Text Peephole Optimizers
8804 * define_peephole2:: RTL to RTL Peephole Optimizers
8809 @node define_peephole
8810 @subsection RTL to Text Peephole Optimizers
8811 @findex define_peephole
8814 A definition looks like this:
8818 [@var{insn-pattern-1}
8819 @var{insn-pattern-2}
8823 "@var{optional-insn-attributes}")
8827 The last string operand may be omitted if you are not using any
8828 machine-specific information in this machine description. If present,
8829 it must obey the same rules as in a @code{define_insn}.
8831 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
8832 consecutive insns. The optimization applies to a sequence of insns when
8833 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
8834 the next, and so on.
8836 Each of the insns matched by a peephole must also match a
8837 @code{define_insn}. Peepholes are checked only at the last stage just
8838 before code generation, and only optionally. Therefore, any insn which
8839 would match a peephole but no @code{define_insn} will cause a crash in code
8840 generation in an unoptimized compilation, or at various optimization
8843 The operands of the insns are matched with @code{match_operands},
8844 @code{match_operator}, and @code{match_dup}, as usual. What is not
8845 usual is that the operand numbers apply to all the insn patterns in the
8846 definition. So, you can check for identical operands in two insns by
8847 using @code{match_operand} in one insn and @code{match_dup} in the
8850 The operand constraints used in @code{match_operand} patterns do not have
8851 any direct effect on the applicability of the peephole, but they will
8852 be validated afterward, so make sure your constraints are general enough
8853 to apply whenever the peephole matches. If the peephole matches
8854 but the constraints are not satisfied, the compiler will crash.
8856 It is safe to omit constraints in all the operands of the peephole; or
8857 you can write constraints which serve as a double-check on the criteria
8860 Once a sequence of insns matches the patterns, the @var{condition} is
8861 checked. This is a C expression which makes the final decision whether to
8862 perform the optimization (we do so if the expression is nonzero). If
8863 @var{condition} is omitted (in other words, the string is empty) then the
8864 optimization is applied to every sequence of insns that matches the
8867 The defined peephole optimizations are applied after register allocation
8868 is complete. Therefore, the peephole definition can check which
8869 operands have ended up in which kinds of registers, just by looking at
8872 @findex prev_active_insn
8873 The way to refer to the operands in @var{condition} is to write
8874 @code{operands[@var{i}]} for operand number @var{i} (as matched by
8875 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
8876 to refer to the last of the insns being matched; use
8877 @code{prev_active_insn} to find the preceding insns.
8879 @findex dead_or_set_p
8880 When optimizing computations with intermediate results, you can use
8881 @var{condition} to match only when the intermediate results are not used
8882 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
8883 @var{op})}, where @var{insn} is the insn in which you expect the value
8884 to be used for the last time (from the value of @code{insn}, together
8885 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
8886 value (from @code{operands[@var{i}]}).
8888 Applying the optimization means replacing the sequence of insns with one
8889 new insn. The @var{template} controls ultimate output of assembler code
8890 for this combined insn. It works exactly like the template of a
8891 @code{define_insn}. Operand numbers in this template are the same ones
8892 used in matching the original sequence of insns.
8894 The result of a defined peephole optimizer does not need to match any of
8895 the insn patterns in the machine description; it does not even have an
8896 opportunity to match them. The peephole optimizer definition itself serves
8897 as the insn pattern to control how the insn is output.
8899 Defined peephole optimizers are run as assembler code is being output,
8900 so the insns they produce are never combined or rearranged in any way.
8902 Here is an example, taken from the 68000 machine description:
8906 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
8907 (set (match_operand:DF 0 "register_operand" "=f")
8908 (match_operand:DF 1 "register_operand" "ad"))]
8909 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
8912 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8914 output_asm_insn ("move.l %1,(sp)", xoperands);
8915 output_asm_insn ("move.l %1,-(sp)", operands);
8916 return "fmove.d (sp)+,%0";
8918 output_asm_insn ("movel %1,sp@@", xoperands);
8919 output_asm_insn ("movel %1,sp@@-", operands);
8920 return "fmoved sp@@+,%0";
8926 The effect of this optimization is to change
8952 If a peephole matches a sequence including one or more jump insns, you must
8953 take account of the flags such as @code{CC_REVERSED} which specify that the
8954 condition codes are represented in an unusual manner. The compiler
8955 automatically alters any ordinary conditional jumps which occur in such
8956 situations, but the compiler cannot alter jumps which have been replaced by
8957 peephole optimizations. So it is up to you to alter the assembler code
8958 that the peephole produces. Supply C code to write the assembler output,
8959 and in this C code check the condition code status flags and change the
8960 assembler code as appropriate.
8963 @var{insn-pattern-1} and so on look @emph{almost} like the second
8964 operand of @code{define_insn}. There is one important difference: the
8965 second operand of @code{define_insn} consists of one or more RTX's
8966 enclosed in square brackets. Usually, there is only one: then the same
8967 action can be written as an element of a @code{define_peephole}. But
8968 when there are multiple actions in a @code{define_insn}, they are
8969 implicitly enclosed in a @code{parallel}. Then you must explicitly
8970 write the @code{parallel}, and the square brackets within it, in the
8971 @code{define_peephole}. Thus, if an insn pattern looks like this,
8974 (define_insn "divmodsi4"
8975 [(set (match_operand:SI 0 "general_operand" "=d")
8976 (div:SI (match_operand:SI 1 "general_operand" "0")
8977 (match_operand:SI 2 "general_operand" "dmsK")))
8978 (set (match_operand:SI 3 "general_operand" "=d")
8979 (mod:SI (match_dup 1) (match_dup 2)))]
8981 "divsl%.l %2,%3:%0")
8985 then the way to mention this insn in a peephole is as follows:
8991 [(set (match_operand:SI 0 "general_operand" "=d")
8992 (div:SI (match_operand:SI 1 "general_operand" "0")
8993 (match_operand:SI 2 "general_operand" "dmsK")))
8994 (set (match_operand:SI 3 "general_operand" "=d")
8995 (mod:SI (match_dup 1) (match_dup 2)))])
9002 @node define_peephole2
9003 @subsection RTL to RTL Peephole Optimizers
9004 @findex define_peephole2
9006 The @code{define_peephole2} definition tells the compiler how to
9007 substitute one sequence of instructions for another sequence,
9008 what additional scratch registers may be needed and what their
9013 [@var{insn-pattern-1}
9014 @var{insn-pattern-2}
9017 [@var{new-insn-pattern-1}
9018 @var{new-insn-pattern-2}
9020 "@var{preparation-statements}")
9023 The definition is almost identical to @code{define_split}
9024 (@pxref{Insn Splitting}) except that the pattern to match is not a
9025 single instruction, but a sequence of instructions.
9027 It is possible to request additional scratch registers for use in the
9028 output template. If appropriate registers are not free, the pattern
9029 will simply not match.
9031 @findex match_scratch
9033 Scratch registers are requested with a @code{match_scratch} pattern at
9034 the top level of the input pattern. The allocated register (initially) will
9035 be dead at the point requested within the original sequence. If the scratch
9036 is used at more than a single point, a @code{match_dup} pattern at the
9037 top level of the input pattern marks the last position in the input sequence
9038 at which the register must be available.
9040 Here is an example from the IA-32 machine description:
9044 [(match_scratch:SI 2 "r")
9045 (parallel [(set (match_operand:SI 0 "register_operand" "")
9046 (match_operator:SI 3 "arith_or_logical_operator"
9048 (match_operand:SI 1 "memory_operand" "")]))
9049 (clobber (reg:CC 17))])]
9050 "! optimize_size && ! TARGET_READ_MODIFY"
9051 [(set (match_dup 2) (match_dup 1))
9052 (parallel [(set (match_dup 0)
9053 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
9054 (clobber (reg:CC 17))])]
9059 This pattern tries to split a load from its use in the hopes that we'll be
9060 able to schedule around the memory load latency. It allocates a single
9061 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
9062 to be live only at the point just before the arithmetic.
9064 A real example requiring extended scratch lifetimes is harder to come by,
9065 so here's a silly made-up example:
9069 [(match_scratch:SI 4 "r")
9070 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
9071 (set (match_operand:SI 2 "" "") (match_dup 1))
9073 (set (match_operand:SI 3 "" "") (match_dup 1))]
9074 "/* @r{determine 1 does not overlap 0 and 2} */"
9075 [(set (match_dup 4) (match_dup 1))
9076 (set (match_dup 0) (match_dup 4))
9077 (set (match_dup 2) (match_dup 4))
9078 (set (match_dup 3) (match_dup 4))]
9082 There are two special macros defined for use in the preparation statements:
9083 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
9090 Use the @code{DONE} macro to end RTL generation for the peephole. The
9091 only RTL insns generated as replacement for the matched input insn will
9092 be those already emitted by explicit calls to @code{emit_insn} within
9093 the preparation statements; the replacement pattern is not used.
9097 Make the @code{define_peephole2} fail on this occasion. When a @code{define_peephole2}
9098 fails, it means that the replacement was not truly available for the
9099 particular inputs it was given. In that case, GCC may still apply a
9100 later @code{define_peephole2} that also matches the given insn pattern.
9101 (Note that this is different from @code{define_split}, where @code{FAIL}
9102 prevents the input insn from being split at all.)
9105 If the preparation falls through (invokes neither @code{DONE} nor
9106 @code{FAIL}), then the @code{define_peephole2} uses the replacement
9110 If we had not added the @code{(match_dup 4)} in the middle of the input
9111 sequence, it might have been the case that the register we chose at the
9112 beginning of the sequence is killed by the first or second @code{set}.
9116 @node Insn Attributes
9117 @section Instruction Attributes
9118 @cindex insn attributes
9119 @cindex instruction attributes
9121 In addition to describing the instruction supported by the target machine,
9122 the @file{md} file also defines a group of @dfn{attributes} and a set of
9123 values for each. Every generated insn is assigned a value for each attribute.
9124 One possible attribute would be the effect that the insn has on the machine's
9125 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
9126 to track the condition codes.
9129 * Defining Attributes:: Specifying attributes and their values.
9130 * Expressions:: Valid expressions for attribute values.
9131 * Tagging Insns:: Assigning attribute values to insns.
9132 * Attr Example:: An example of assigning attributes.
9133 * Insn Lengths:: Computing the length of insns.
9134 * Constant Attributes:: Defining attributes that are constant.
9135 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
9136 * Delay Slots:: Defining delay slots required for a machine.
9137 * Processor pipeline description:: Specifying information for insn scheduling.
9142 @node Defining Attributes
9143 @subsection Defining Attributes and their Values
9144 @cindex defining attributes and their values
9145 @cindex attributes, defining
9148 The @code{define_attr} expression is used to define each attribute required
9149 by the target machine. It looks like:
9152 (define_attr @var{name} @var{list-of-values} @var{default})
9155 @var{name} is a string specifying the name of the attribute being
9156 defined. Some attributes are used in a special way by the rest of the
9157 compiler. The @code{enabled} attribute can be used to conditionally
9158 enable or disable insn alternatives (@pxref{Disable Insn
9159 Alternatives}). The @code{predicable} attribute, together with a
9160 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
9161 be used to automatically generate conditional variants of instruction
9162 patterns. The @code{mnemonic} attribute can be used to check for the
9163 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
9164 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
9165 so they should not be used elsewhere as alternative names.
9167 @var{list-of-values} is either a string that specifies a comma-separated
9168 list of values that can be assigned to the attribute, or a null string to
9169 indicate that the attribute takes numeric values.
9171 @var{default} is an attribute expression that gives the value of this
9172 attribute for insns that match patterns whose definition does not include
9173 an explicit value for this attribute. @xref{Attr Example}, for more
9174 information on the handling of defaults. @xref{Constant Attributes},
9175 for information on attributes that do not depend on any particular insn.
9178 For each defined attribute, a number of definitions are written to the
9179 @file{insn-attr.h} file. For cases where an explicit set of values is
9180 specified for an attribute, the following are defined:
9184 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
9187 An enumerated class is defined for @samp{attr_@var{name}} with
9188 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
9189 the attribute name and value are first converted to uppercase.
9192 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
9193 returns the attribute value for that insn.
9196 For example, if the following is present in the @file{md} file:
9199 (define_attr "type" "branch,fp,load,store,arith" @dots{})
9203 the following lines will be written to the file @file{insn-attr.h}.
9206 #define HAVE_ATTR_type 1
9207 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
9208 TYPE_STORE, TYPE_ARITH@};
9209 extern enum attr_type get_attr_type ();
9212 If the attribute takes numeric values, no @code{enum} type will be
9213 defined and the function to obtain the attribute's value will return
9216 There are attributes which are tied to a specific meaning. These
9217 attributes are not free to use for other purposes:
9221 The @code{length} attribute is used to calculate the length of emitted
9222 code chunks. This is especially important when verifying branch
9223 distances. @xref{Insn Lengths}.
9226 The @code{enabled} attribute can be defined to prevent certain
9227 alternatives of an insn definition from being used during code
9228 generation. @xref{Disable Insn Alternatives}.
9231 The @code{mnemonic} attribute can be defined to implement instruction
9232 specific checks in e.g.@: the pipeline description.
9233 @xref{Mnemonic Attribute}.
9236 For each of these special attributes, the corresponding
9237 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
9238 attribute is not defined; in that case, it is defined as @samp{0}.
9240 @findex define_enum_attr
9241 @anchor{define_enum_attr}
9242 Another way of defining an attribute is to use:
9245 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
9248 This works in just the same way as @code{define_attr}, except that
9249 the list of values is taken from a separate enumeration called
9250 @var{enum} (@pxref{define_enum}). This form allows you to use
9251 the same list of values for several attributes without having to
9252 repeat the list each time. For example:
9255 (define_enum "processor" [
9260 (define_enum_attr "arch" "processor"
9261 (const (symbol_ref "target_arch")))
9262 (define_enum_attr "tune" "processor"
9263 (const (symbol_ref "target_tune")))
9266 defines the same attributes as:
9269 (define_attr "arch" "model_a,model_b,@dots{}"
9270 (const (symbol_ref "target_arch")))
9271 (define_attr "tune" "model_a,model_b,@dots{}"
9272 (const (symbol_ref "target_tune")))
9275 but without duplicating the processor list. The second example defines two
9276 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
9277 defines a single C enum (@code{processor}).
9281 @subsection Attribute Expressions
9282 @cindex attribute expressions
9284 RTL expressions used to define attributes use the codes described above
9285 plus a few specific to attribute definitions, to be discussed below.
9286 Attribute value expressions must have one of the following forms:
9289 @cindex @code{const_int} and attributes
9290 @item (const_int @var{i})
9291 The integer @var{i} specifies the value of a numeric attribute. @var{i}
9292 must be non-negative.
9294 The value of a numeric attribute can be specified either with a
9295 @code{const_int}, or as an integer represented as a string in
9296 @code{const_string}, @code{eq_attr} (see below), @code{attr},
9297 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
9298 overrides on specific instructions (@pxref{Tagging Insns}).
9300 @cindex @code{const_string} and attributes
9301 @item (const_string @var{value})
9302 The string @var{value} specifies a constant attribute value.
9303 If @var{value} is specified as @samp{"*"}, it means that the default value of
9304 the attribute is to be used for the insn containing this expression.
9305 @samp{"*"} obviously cannot be used in the @var{default} expression
9306 of a @code{define_attr}.
9308 If the attribute whose value is being specified is numeric, @var{value}
9309 must be a string containing a non-negative integer (normally
9310 @code{const_int} would be used in this case). Otherwise, it must
9311 contain one of the valid values for the attribute.
9313 @cindex @code{if_then_else} and attributes
9314 @item (if_then_else @var{test} @var{true-value} @var{false-value})
9315 @var{test} specifies an attribute test, whose format is defined below.
9316 The value of this expression is @var{true-value} if @var{test} is true,
9317 otherwise it is @var{false-value}.
9319 @cindex @code{cond} and attributes
9320 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
9321 The first operand of this expression is a vector containing an even
9322 number of expressions and consisting of pairs of @var{test} and @var{value}
9323 expressions. The value of the @code{cond} expression is that of the
9324 @var{value} corresponding to the first true @var{test} expression. If
9325 none of the @var{test} expressions are true, the value of the @code{cond}
9326 expression is that of the @var{default} expression.
9329 @var{test} expressions can have one of the following forms:
9332 @cindex @code{const_int} and attribute tests
9333 @item (const_int @var{i})
9334 This test is true if @var{i} is nonzero and false otherwise.
9336 @cindex @code{not} and attributes
9337 @cindex @code{ior} and attributes
9338 @cindex @code{and} and attributes
9339 @item (not @var{test})
9340 @itemx (ior @var{test1} @var{test2})
9341 @itemx (and @var{test1} @var{test2})
9342 These tests are true if the indicated logical function is true.
9344 @cindex @code{match_operand} and attributes
9345 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
9346 This test is true if operand @var{n} of the insn whose attribute value
9347 is being determined has mode @var{m} (this part of the test is ignored
9348 if @var{m} is @code{VOIDmode}) and the function specified by the string
9349 @var{pred} returns a nonzero value when passed operand @var{n} and mode
9350 @var{m} (this part of the test is ignored if @var{pred} is the null
9353 The @var{constraints} operand is ignored and should be the null string.
9355 @cindex @code{match_test} and attributes
9356 @item (match_test @var{c-expr})
9357 The test is true if C expression @var{c-expr} is true. In non-constant
9358 attributes, @var{c-expr} has access to the following variables:
9362 The rtl instruction under test.
9363 @item which_alternative
9364 The @code{define_insn} alternative that @var{insn} matches.
9365 @xref{Output Statement}.
9367 An array of @var{insn}'s rtl operands.
9370 @var{c-expr} behaves like the condition in a C @code{if} statement,
9371 so there is no need to explicitly convert the expression into a boolean
9372 0 or 1 value. For example, the following two tests are equivalent:
9375 (match_test "x & 2")
9376 (match_test "(x & 2) != 0")
9379 @cindex @code{le} and attributes
9380 @cindex @code{leu} and attributes
9381 @cindex @code{lt} and attributes
9382 @cindex @code{gt} and attributes
9383 @cindex @code{gtu} and attributes
9384 @cindex @code{ge} and attributes
9385 @cindex @code{geu} and attributes
9386 @cindex @code{ne} and attributes
9387 @cindex @code{eq} and attributes
9388 @cindex @code{plus} and attributes
9389 @cindex @code{minus} and attributes
9390 @cindex @code{mult} and attributes
9391 @cindex @code{div} and attributes
9392 @cindex @code{mod} and attributes
9393 @cindex @code{abs} and attributes
9394 @cindex @code{neg} and attributes
9395 @cindex @code{ashift} and attributes
9396 @cindex @code{lshiftrt} and attributes
9397 @cindex @code{ashiftrt} and attributes
9398 @item (le @var{arith1} @var{arith2})
9399 @itemx (leu @var{arith1} @var{arith2})
9400 @itemx (lt @var{arith1} @var{arith2})
9401 @itemx (ltu @var{arith1} @var{arith2})
9402 @itemx (gt @var{arith1} @var{arith2})
9403 @itemx (gtu @var{arith1} @var{arith2})
9404 @itemx (ge @var{arith1} @var{arith2})
9405 @itemx (geu @var{arith1} @var{arith2})
9406 @itemx (ne @var{arith1} @var{arith2})
9407 @itemx (eq @var{arith1} @var{arith2})
9408 These tests are true if the indicated comparison of the two arithmetic
9409 expressions is true. Arithmetic expressions are formed with
9410 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
9411 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
9412 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
9415 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
9416 Lengths},for additional forms). @code{symbol_ref} is a string
9417 denoting a C expression that yields an @code{int} when evaluated by the
9418 @samp{get_attr_@dots{}} routine. It should normally be a global
9422 @item (eq_attr @var{name} @var{value})
9423 @var{name} is a string specifying the name of an attribute.
9425 @var{value} is a string that is either a valid value for attribute
9426 @var{name}, a comma-separated list of values, or @samp{!} followed by a
9427 value or list. If @var{value} does not begin with a @samp{!}, this
9428 test is true if the value of the @var{name} attribute of the current
9429 insn is in the list specified by @var{value}. If @var{value} begins
9430 with a @samp{!}, this test is true if the attribute's value is
9431 @emph{not} in the specified list.
9436 (eq_attr "type" "load,store")
9443 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
9446 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
9447 value of the compiler variable @code{which_alternative}
9448 (@pxref{Output Statement}) and the values must be small integers. For
9452 (eq_attr "alternative" "2,3")
9459 (ior (eq (symbol_ref "which_alternative") (const_int 2))
9460 (eq (symbol_ref "which_alternative") (const_int 3)))
9463 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
9464 where the value of the attribute being tested is known for all insns matching
9465 a particular pattern. This is by far the most common case.
9468 @item (attr_flag @var{name})
9469 The value of an @code{attr_flag} expression is true if the flag
9470 specified by @var{name} is true for the @code{insn} currently being
9473 @var{name} is a string specifying one of a fixed set of flags to test.
9474 Test the flags @code{forward} and @code{backward} to determine the
9475 direction of a conditional branch.
9477 This example describes a conditional branch delay slot which
9478 can be nullified for forward branches that are taken (annul-true) or
9479 for backward branches which are not taken (annul-false).
9482 (define_delay (eq_attr "type" "cbranch")
9483 [(eq_attr "in_branch_delay" "true")
9484 (and (eq_attr "in_branch_delay" "true")
9485 (attr_flag "forward"))
9486 (and (eq_attr "in_branch_delay" "true")
9487 (attr_flag "backward"))])
9490 The @code{forward} and @code{backward} flags are false if the current
9491 @code{insn} being scheduled is not a conditional branch.
9493 @code{attr_flag} is only used during delay slot scheduling and has no
9494 meaning to other passes of the compiler.
9497 @item (attr @var{name})
9498 The value of another attribute is returned. This is most useful
9499 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
9500 produce more efficient code for non-numeric attributes.
9506 @subsection Assigning Attribute Values to Insns
9507 @cindex tagging insns
9508 @cindex assigning attribute values to insns
9510 The value assigned to an attribute of an insn is primarily determined by
9511 which pattern is matched by that insn (or which @code{define_peephole}
9512 generated it). Every @code{define_insn} and @code{define_peephole} can
9513 have an optional last argument to specify the values of attributes for
9514 matching insns. The value of any attribute not specified in a particular
9515 insn is set to the default value for that attribute, as specified in its
9516 @code{define_attr}. Extensive use of default values for attributes
9517 permits the specification of the values for only one or two attributes
9518 in the definition of most insn patterns, as seen in the example in the
9521 The optional last argument of @code{define_insn} and
9522 @code{define_peephole} is a vector of expressions, each of which defines
9523 the value for a single attribute. The most general way of assigning an
9524 attribute's value is to use a @code{set} expression whose first operand is an
9525 @code{attr} expression giving the name of the attribute being set. The
9526 second operand of the @code{set} is an attribute expression
9527 (@pxref{Expressions}) giving the value of the attribute.
9529 When the attribute value depends on the @samp{alternative} attribute
9530 (i.e., which is the applicable alternative in the constraint of the
9531 insn), the @code{set_attr_alternative} expression can be used. It
9532 allows the specification of a vector of attribute expressions, one for
9536 When the generality of arbitrary attribute expressions is not required,
9537 the simpler @code{set_attr} expression can be used, which allows
9538 specifying a string giving either a single attribute value or a list
9539 of attribute values, one for each alternative.
9541 The form of each of the above specifications is shown below. In each case,
9542 @var{name} is a string specifying the attribute to be set.
9545 @item (set_attr @var{name} @var{value-string})
9546 @var{value-string} is either a string giving the desired attribute value,
9547 or a string containing a comma-separated list giving the values for
9548 succeeding alternatives. The number of elements must match the number
9549 of alternatives in the constraint of the insn pattern.
9551 Note that it may be useful to specify @samp{*} for some alternative, in
9552 which case the attribute will assume its default value for insns matching
9555 @findex set_attr_alternative
9556 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
9557 Depending on the alternative of the insn, the value will be one of the
9558 specified values. This is a shorthand for using a @code{cond} with
9559 tests on the @samp{alternative} attribute.
9562 @item (set (attr @var{name}) @var{value})
9563 The first operand of this @code{set} must be the special RTL expression
9564 @code{attr}, whose sole operand is a string giving the name of the
9565 attribute being set. @var{value} is the value of the attribute.
9568 The following shows three different ways of representing the same
9569 attribute value specification:
9572 (set_attr "type" "load,store,arith")
9574 (set_attr_alternative "type"
9575 [(const_string "load") (const_string "store")
9576 (const_string "arith")])
9579 (cond [(eq_attr "alternative" "1") (const_string "load")
9580 (eq_attr "alternative" "2") (const_string "store")]
9581 (const_string "arith")))
9585 @findex define_asm_attributes
9586 The @code{define_asm_attributes} expression provides a mechanism to
9587 specify the attributes assigned to insns produced from an @code{asm}
9588 statement. It has the form:
9591 (define_asm_attributes [@var{attr-sets}])
9595 where @var{attr-sets} is specified the same as for both the
9596 @code{define_insn} and the @code{define_peephole} expressions.
9598 These values will typically be the ``worst case'' attribute values. For
9599 example, they might indicate that the condition code will be clobbered.
9601 A specification for a @code{length} attribute is handled specially. The
9602 way to compute the length of an @code{asm} insn is to multiply the
9603 length specified in the expression @code{define_asm_attributes} by the
9604 number of machine instructions specified in the @code{asm} statement,
9605 determined by counting the number of semicolons and newlines in the
9606 string. Therefore, the value of the @code{length} attribute specified
9607 in a @code{define_asm_attributes} should be the maximum possible length
9608 of a single machine instruction.
9613 @subsection Example of Attribute Specifications
9614 @cindex attribute specifications example
9615 @cindex attribute specifications
9617 The judicious use of defaulting is important in the efficient use of
9618 insn attributes. Typically, insns are divided into @dfn{types} and an
9619 attribute, customarily called @code{type}, is used to represent this
9620 value. This attribute is normally used only to define the default value
9621 for other attributes. An example will clarify this usage.
9623 Assume we have a RISC machine with a condition code and in which only
9624 full-word operations are performed in registers. Let us assume that we
9625 can divide all insns into loads, stores, (integer) arithmetic
9626 operations, floating point operations, and branches.
9628 Here we will concern ourselves with determining the effect of an insn on
9629 the condition code and will limit ourselves to the following possible
9630 effects: The condition code can be set unpredictably (clobbered), not
9631 be changed, be set to agree with the results of the operation, or only
9632 changed if the item previously set into the condition code has been
9635 Here is part of a sample @file{md} file for such a machine:
9638 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
9640 (define_attr "cc" "clobber,unchanged,set,change0"
9641 (cond [(eq_attr "type" "load")
9642 (const_string "change0")
9643 (eq_attr "type" "store,branch")
9644 (const_string "unchanged")
9645 (eq_attr "type" "arith")
9646 (if_then_else (match_operand:SI 0 "" "")
9647 (const_string "set")
9648 (const_string "clobber"))]
9649 (const_string "clobber")))
9652 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
9653 (match_operand:SI 1 "general_operand" "r,m,r"))]
9659 [(set_attr "type" "arith,load,store")])
9662 Note that we assume in the above example that arithmetic operations
9663 performed on quantities smaller than a machine word clobber the condition
9664 code since they will set the condition code to a value corresponding to the
9670 @subsection Computing the Length of an Insn
9671 @cindex insn lengths, computing
9672 @cindex computing the length of an insn
9674 For many machines, multiple types of branch instructions are provided, each
9675 for different length branch displacements. In most cases, the assembler
9676 will choose the correct instruction to use. However, when the assembler
9677 cannot do so, GCC can when a special attribute, the @code{length}
9678 attribute, is defined. This attribute must be defined to have numeric
9679 values by specifying a null string in its @code{define_attr}.
9681 In the case of the @code{length} attribute, two additional forms of
9682 arithmetic terms are allowed in test expressions:
9685 @cindex @code{match_dup} and attributes
9686 @item (match_dup @var{n})
9687 This refers to the address of operand @var{n} of the current insn, which
9688 must be a @code{label_ref}.
9690 @cindex @code{pc} and attributes
9692 For non-branch instructions and backward branch instructions, this refers
9693 to the address of the current insn. But for forward branch instructions,
9694 this refers to the address of the next insn, because the length of the
9695 current insn is to be computed.
9698 @cindex @code{addr_vec}, length of
9699 @cindex @code{addr_diff_vec}, length of
9700 For normal insns, the length will be determined by value of the
9701 @code{length} attribute. In the case of @code{addr_vec} and
9702 @code{addr_diff_vec} insn patterns, the length is computed as
9703 the number of vectors multiplied by the size of each vector.
9705 Lengths are measured in addressable storage units (bytes).
9707 Note that it is possible to call functions via the @code{symbol_ref}
9708 mechanism to compute the length of an insn. However, if you use this
9709 mechanism you must provide dummy clauses to express the maximum length
9710 without using the function call. You can an example of this in the
9711 @code{pa} machine description for the @code{call_symref} pattern.
9713 The following macros can be used to refine the length computation:
9716 @findex ADJUST_INSN_LENGTH
9717 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
9718 If defined, modifies the length assigned to instruction @var{insn} as a
9719 function of the context in which it is used. @var{length} is an lvalue
9720 that contains the initially computed length of the insn and should be
9721 updated with the correct length of the insn.
9723 This macro will normally not be required. A case in which it is
9724 required is the ROMP@. On this machine, the size of an @code{addr_vec}
9725 insn must be increased by two to compensate for the fact that alignment
9729 @findex get_attr_length
9730 The routine that returns @code{get_attr_length} (the value of the
9731 @code{length} attribute) can be used by the output routine to
9732 determine the form of the branch instruction to be written, as the
9733 example below illustrates.
9735 As an example of the specification of variable-length branches, consider
9736 the IBM 360. If we adopt the convention that a register will be set to
9737 the starting address of a function, we can jump to labels within 4k of
9738 the start using a four-byte instruction. Otherwise, we need a six-byte
9739 sequence to load the address from memory and then branch to it.
9741 On such a machine, a pattern for a branch instruction might be specified
9747 (label_ref (match_operand 0 "" "")))]
9750 return (get_attr_length (insn) == 4
9751 ? "b %l0" : "l r15,=a(%l0); br r15");
9753 [(set (attr "length")
9754 (if_then_else (lt (match_dup 0) (const_int 4096))
9761 @node Constant Attributes
9762 @subsection Constant Attributes
9763 @cindex constant attributes
9765 A special form of @code{define_attr}, where the expression for the
9766 default value is a @code{const} expression, indicates an attribute that
9767 is constant for a given run of the compiler. Constant attributes may be
9768 used to specify which variety of processor is used. For example,
9771 (define_attr "cpu" "m88100,m88110,m88000"
9773 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
9774 (symbol_ref "TARGET_88110") (const_string "m88110")]
9775 (const_string "m88000"))))
9777 (define_attr "memory" "fast,slow"
9779 (if_then_else (symbol_ref "TARGET_FAST_MEM")
9780 (const_string "fast")
9781 (const_string "slow"))))
9784 The routine generated for constant attributes has no parameters as it
9785 does not depend on any particular insn. RTL expressions used to define
9786 the value of a constant attribute may use the @code{symbol_ref} form,
9787 but may not use either the @code{match_operand} form or @code{eq_attr}
9788 forms involving insn attributes.
9792 @node Mnemonic Attribute
9793 @subsection Mnemonic Attribute
9794 @cindex mnemonic attribute
9796 The @code{mnemonic} attribute is a string type attribute holding the
9797 instruction mnemonic for an insn alternative. The attribute values
9798 will automatically be generated by the machine description parser if
9799 there is an attribute definition in the md file:
9802 (define_attr "mnemonic" "unknown" (const_string "unknown"))
9805 The default value can be freely chosen as long as it does not collide
9806 with any of the instruction mnemonics. This value will be used
9807 whenever the machine description parser is not able to determine the
9808 mnemonic string. This might be the case for output templates
9809 containing more than a single instruction as in
9810 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
9812 The @code{mnemonic} attribute set is not generated automatically if the
9813 instruction string is generated via C code.
9815 An existing @code{mnemonic} attribute set in an insn definition will not
9816 be overriden by the md file parser. That way it is possible to
9817 manually set the instruction mnemonics for the cases where the md file
9818 parser fails to determine it automatically.
9820 The @code{mnemonic} attribute is useful for dealing with instruction
9821 specific properties in the pipeline description without defining
9822 additional insn attributes.
9825 (define_attr "ooo_expanded" ""
9826 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
9834 @subsection Delay Slot Scheduling
9835 @cindex delay slots, defining
9837 The insn attribute mechanism can be used to specify the requirements for
9838 delay slots, if any, on a target machine. An instruction is said to
9839 require a @dfn{delay slot} if some instructions that are physically
9840 after the instruction are executed as if they were located before it.
9841 Classic examples are branch and call instructions, which often execute
9842 the following instruction before the branch or call is performed.
9844 On some machines, conditional branch instructions can optionally
9845 @dfn{annul} instructions in the delay slot. This means that the
9846 instruction will not be executed for certain branch outcomes. Both
9847 instructions that annul if the branch is true and instructions that
9848 annul if the branch is false are supported.
9850 Delay slot scheduling differs from instruction scheduling in that
9851 determining whether an instruction needs a delay slot is dependent only
9852 on the type of instruction being generated, not on data flow between the
9853 instructions. See the next section for a discussion of data-dependent
9854 instruction scheduling.
9856 @findex define_delay
9857 The requirement of an insn needing one or more delay slots is indicated
9858 via the @code{define_delay} expression. It has the following form:
9861 (define_delay @var{test}
9862 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
9863 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
9867 @var{test} is an attribute test that indicates whether this
9868 @code{define_delay} applies to a particular insn. If so, the number of
9869 required delay slots is determined by the length of the vector specified
9870 as the second argument. An insn placed in delay slot @var{n} must
9871 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
9872 attribute test that specifies which insns may be annulled if the branch
9873 is true. Similarly, @var{annul-false-n} specifies which insns in the
9874 delay slot may be annulled if the branch is false. If annulling is not
9875 supported for that delay slot, @code{(nil)} should be coded.
9877 For example, in the common case where branch and call insns require
9878 a single delay slot, which may contain any insn other than a branch or
9879 call, the following would be placed in the @file{md} file:
9882 (define_delay (eq_attr "type" "branch,call")
9883 [(eq_attr "type" "!branch,call") (nil) (nil)])
9886 Multiple @code{define_delay} expressions may be specified. In this
9887 case, each such expression specifies different delay slot requirements
9888 and there must be no insn for which tests in two @code{define_delay}
9889 expressions are both true.
9891 For example, if we have a machine that requires one delay slot for branches
9892 but two for calls, no delay slot can contain a branch or call insn,
9893 and any valid insn in the delay slot for the branch can be annulled if the
9894 branch is true, we might represent this as follows:
9897 (define_delay (eq_attr "type" "branch")
9898 [(eq_attr "type" "!branch,call")
9899 (eq_attr "type" "!branch,call")
9902 (define_delay (eq_attr "type" "call")
9903 [(eq_attr "type" "!branch,call") (nil) (nil)
9904 (eq_attr "type" "!branch,call") (nil) (nil)])
9906 @c the above is *still* too long. --mew 4feb93
9910 @node Processor pipeline description
9911 @subsection Specifying processor pipeline description
9912 @cindex processor pipeline description
9913 @cindex processor functional units
9914 @cindex instruction latency time
9915 @cindex interlock delays
9916 @cindex data dependence delays
9917 @cindex reservation delays
9918 @cindex pipeline hazard recognizer
9919 @cindex automaton based pipeline description
9920 @cindex regular expressions
9921 @cindex deterministic finite state automaton
9922 @cindex automaton based scheduler
9926 To achieve better performance, most modern processors
9927 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
9928 processors) have many @dfn{functional units} on which several
9929 instructions can be executed simultaneously. An instruction starts
9930 execution if its issue conditions are satisfied. If not, the
9931 instruction is stalled until its conditions are satisfied. Such
9932 @dfn{interlock (pipeline) delay} causes interruption of the fetching
9933 of successor instructions (or demands nop instructions, e.g.@: for some
9936 There are two major kinds of interlock delays in modern processors.
9937 The first one is a data dependence delay determining @dfn{instruction
9938 latency time}. The instruction execution is not started until all
9939 source data have been evaluated by prior instructions (there are more
9940 complex cases when the instruction execution starts even when the data
9941 are not available but will be ready in given time after the
9942 instruction execution start). Taking the data dependence delays into
9943 account is simple. The data dependence (true, output, and
9944 anti-dependence) delay between two instructions is given by a
9945 constant. In most cases this approach is adequate. The second kind
9946 of interlock delays is a reservation delay. The reservation delay
9947 means that two instructions under execution will be in need of shared
9948 processors resources, i.e.@: buses, internal registers, and/or
9949 functional units, which are reserved for some time. Taking this kind
9950 of delay into account is complex especially for modern @acronym{RISC}
9953 The task of exploiting more processor parallelism is solved by an
9954 instruction scheduler. For a better solution to this problem, the
9955 instruction scheduler has to have an adequate description of the
9956 processor parallelism (or @dfn{pipeline description}). GCC
9957 machine descriptions describe processor parallelism and functional
9958 unit reservations for groups of instructions with the aid of
9959 @dfn{regular expressions}.
9961 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
9962 figure out the possibility of the instruction issue by the processor
9963 on a given simulated processor cycle. The pipeline hazard recognizer is
9964 automatically generated from the processor pipeline description. The
9965 pipeline hazard recognizer generated from the machine description
9966 is based on a deterministic finite state automaton (@acronym{DFA}):
9967 the instruction issue is possible if there is a transition from one
9968 automaton state to another one. This algorithm is very fast, and
9969 furthermore, its speed is not dependent on processor
9970 complexity@footnote{However, the size of the automaton depends on
9971 processor complexity. To limit this effect, machine descriptions
9972 can split orthogonal parts of the machine description among several
9973 automata: but then, since each of these must be stepped independently,
9974 this does cause a small decrease in the algorithm's performance.}.
9976 @cindex automaton based pipeline description
9977 The rest of this section describes the directives that constitute
9978 an automaton-based processor pipeline description. The order of
9979 these constructions within the machine description file is not
9982 @findex define_automaton
9983 @cindex pipeline hazard recognizer
9984 The following optional construction describes names of automata
9985 generated and used for the pipeline hazards recognition. Sometimes
9986 the generated finite state automaton used by the pipeline hazard
9987 recognizer is large. If we use more than one automaton and bind functional
9988 units to the automata, the total size of the automata is usually
9989 less than the size of the single automaton. If there is no one such
9990 construction, only one finite state automaton is generated.
9993 (define_automaton @var{automata-names})
9996 @var{automata-names} is a string giving names of the automata. The
9997 names are separated by commas. All the automata should have unique names.
9998 The automaton name is used in the constructions @code{define_cpu_unit} and
9999 @code{define_query_cpu_unit}.
10001 @findex define_cpu_unit
10002 @cindex processor functional units
10003 Each processor functional unit used in the description of instruction
10004 reservations should be described by the following construction.
10007 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
10010 @var{unit-names} is a string giving the names of the functional units
10011 separated by commas. Don't use name @samp{nothing}, it is reserved
10014 @var{automaton-name} is a string giving the name of the automaton with
10015 which the unit is bound. The automaton should be described in
10016 construction @code{define_automaton}. You should give
10017 @dfn{automaton-name}, if there is a defined automaton.
10019 The assignment of units to automata are constrained by the uses of the
10020 units in insn reservations. The most important constraint is: if a
10021 unit reservation is present on a particular cycle of an alternative
10022 for an insn reservation, then some unit from the same automaton must
10023 be present on the same cycle for the other alternatives of the insn
10024 reservation. The rest of the constraints are mentioned in the
10025 description of the subsequent constructions.
10027 @findex define_query_cpu_unit
10028 @cindex querying function unit reservations
10029 The following construction describes CPU functional units analogously
10030 to @code{define_cpu_unit}. The reservation of such units can be
10031 queried for an automaton state. The instruction scheduler never
10032 queries reservation of functional units for given automaton state. So
10033 as a rule, you don't need this construction. This construction could
10034 be used for future code generation goals (e.g.@: to generate
10035 @acronym{VLIW} insn templates).
10038 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
10041 @var{unit-names} is a string giving names of the functional units
10042 separated by commas.
10044 @var{automaton-name} is a string giving the name of the automaton with
10045 which the unit is bound.
10047 @findex define_insn_reservation
10048 @cindex instruction latency time
10049 @cindex regular expressions
10050 @cindex data bypass
10051 The following construction is the major one to describe pipeline
10052 characteristics of an instruction.
10055 (define_insn_reservation @var{insn-name} @var{default_latency}
10056 @var{condition} @var{regexp})
10059 @var{default_latency} is a number giving latency time of the
10060 instruction. There is an important difference between the old
10061 description and the automaton based pipeline description. The latency
10062 time is used for all dependencies when we use the old description. In
10063 the automaton based pipeline description, the given latency time is only
10064 used for true dependencies. The cost of anti-dependencies is always
10065 zero and the cost of output dependencies is the difference between
10066 latency times of the producing and consuming insns (if the difference
10067 is negative, the cost is considered to be zero). You can always
10068 change the default costs for any description by using the target hook
10069 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
10071 @var{insn-name} is a string giving the internal name of the insn. The
10072 internal names are used in constructions @code{define_bypass} and in
10073 the automaton description file generated for debugging. The internal
10074 name has nothing in common with the names in @code{define_insn}. It is a
10075 good practice to use insn classes described in the processor manual.
10077 @var{condition} defines what RTL insns are described by this
10078 construction. You should remember that you will be in trouble if
10079 @var{condition} for two or more different
10080 @code{define_insn_reservation} constructions is TRUE for an insn. In
10081 this case what reservation will be used for the insn is not defined.
10082 Such cases are not checked during generation of the pipeline hazards
10083 recognizer because in general recognizing that two conditions may have
10084 the same value is quite difficult (especially if the conditions
10085 contain @code{symbol_ref}). It is also not checked during the
10086 pipeline hazard recognizer work because it would slow down the
10087 recognizer considerably.
10089 @var{regexp} is a string describing the reservation of the cpu's functional
10090 units by the instruction. The reservations are described by a regular
10091 expression according to the following syntax:
10094 regexp = regexp "," oneof
10097 oneof = oneof "|" allof
10100 allof = allof "+" repeat
10103 repeat = element "*" number
10106 element = cpu_function_unit_name
10115 @samp{,} is used for describing the start of the next cycle in
10119 @samp{|} is used for describing a reservation described by the first
10120 regular expression @strong{or} a reservation described by the second
10121 regular expression @strong{or} etc.
10124 @samp{+} is used for describing a reservation described by the first
10125 regular expression @strong{and} a reservation described by the
10126 second regular expression @strong{and} etc.
10129 @samp{*} is used for convenience and simply means a sequence in which
10130 the regular expression are repeated @var{number} times with cycle
10131 advancing (see @samp{,}).
10134 @samp{cpu_function_unit_name} denotes reservation of the named
10138 @samp{reservation_name} --- see description of construction
10139 @samp{define_reservation}.
10142 @samp{nothing} denotes no unit reservations.
10145 @findex define_reservation
10146 Sometimes unit reservations for different insns contain common parts.
10147 In such case, you can simplify the pipeline description by describing
10148 the common part by the following construction
10151 (define_reservation @var{reservation-name} @var{regexp})
10154 @var{reservation-name} is a string giving name of @var{regexp}.
10155 Functional unit names and reservation names are in the same name
10156 space. So the reservation names should be different from the
10157 functional unit names and cannot be the reserved name @samp{nothing}.
10159 @findex define_bypass
10160 @cindex instruction latency time
10161 @cindex data bypass
10162 The following construction is used to describe exceptions in the
10163 latency time for given instruction pair. This is so called bypasses.
10166 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
10170 @var{number} defines when the result generated by the instructions
10171 given in string @var{out_insn_names} will be ready for the
10172 instructions given in string @var{in_insn_names}. Each of these
10173 strings is a comma-separated list of filename-style globs and
10174 they refer to the names of @code{define_insn_reservation}s.
10177 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
10179 defines a bypass between instructions that start with
10180 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
10183 @var{guard} is an optional string giving the name of a C function which
10184 defines an additional guard for the bypass. The function will get the
10185 two insns as parameters. If the function returns zero the bypass will
10186 be ignored for this case. The additional guard is necessary to
10187 recognize complicated bypasses, e.g.@: when the consumer is only an address
10188 of insn @samp{store} (not a stored value).
10190 If there are more one bypass with the same output and input insns, the
10191 chosen bypass is the first bypass with a guard in description whose
10192 guard function returns nonzero. If there is no such bypass, then
10193 bypass without the guard function is chosen.
10195 @findex exclusion_set
10196 @findex presence_set
10197 @findex final_presence_set
10198 @findex absence_set
10199 @findex final_absence_set
10202 The following five constructions are usually used to describe
10203 @acronym{VLIW} processors, or more precisely, to describe a placement
10204 of small instructions into @acronym{VLIW} instruction slots. They
10205 can be used for @acronym{RISC} processors, too.
10208 (exclusion_set @var{unit-names} @var{unit-names})
10209 (presence_set @var{unit-names} @var{patterns})
10210 (final_presence_set @var{unit-names} @var{patterns})
10211 (absence_set @var{unit-names} @var{patterns})
10212 (final_absence_set @var{unit-names} @var{patterns})
10215 @var{unit-names} is a string giving names of functional units
10216 separated by commas.
10218 @var{patterns} is a string giving patterns of functional units
10219 separated by comma. Currently pattern is one unit or units
10220 separated by white-spaces.
10222 The first construction (@samp{exclusion_set}) means that each
10223 functional unit in the first string cannot be reserved simultaneously
10224 with a unit whose name is in the second string and vice versa. For
10225 example, the construction is useful for describing processors
10226 (e.g.@: some SPARC processors) with a fully pipelined floating point
10227 functional unit which can execute simultaneously only single floating
10228 point insns or only double floating point insns.
10230 The second construction (@samp{presence_set}) means that each
10231 functional unit in the first string cannot be reserved unless at
10232 least one of pattern of units whose names are in the second string is
10233 reserved. This is an asymmetric relation. For example, it is useful
10234 for description that @acronym{VLIW} @samp{slot1} is reserved after
10235 @samp{slot0} reservation. We could describe it by the following
10239 (presence_set "slot1" "slot0")
10242 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
10243 reservation. In this case we could write
10246 (presence_set "slot1" "slot0 b0")
10249 The third construction (@samp{final_presence_set}) is analogous to
10250 @samp{presence_set}. The difference between them is when checking is
10251 done. When an instruction is issued in given automaton state
10252 reflecting all current and planned unit reservations, the automaton
10253 state is changed. The first state is a source state, the second one
10254 is a result state. Checking for @samp{presence_set} is done on the
10255 source state reservation, checking for @samp{final_presence_set} is
10256 done on the result reservation. This construction is useful to
10257 describe a reservation which is actually two subsequent reservations.
10258 For example, if we use
10261 (presence_set "slot1" "slot0")
10264 the following insn will be never issued (because @samp{slot1} requires
10265 @samp{slot0} which is absent in the source state).
10268 (define_reservation "insn_and_nop" "slot0 + slot1")
10271 but it can be issued if we use analogous @samp{final_presence_set}.
10273 The forth construction (@samp{absence_set}) means that each functional
10274 unit in the first string can be reserved only if each pattern of units
10275 whose names are in the second string is not reserved. This is an
10276 asymmetric relation (actually @samp{exclusion_set} is analogous to
10277 this one but it is symmetric). For example it might be useful in a
10278 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
10279 after either @samp{slot1} or @samp{slot2} have been reserved. This
10280 can be described as:
10283 (absence_set "slot0" "slot1, slot2")
10286 Or @samp{slot2} cannot be reserved if @samp{slot0} and unit @samp{b0}
10287 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
10288 this case we could write
10291 (absence_set "slot2" "slot0 b0, slot1 b1")
10294 All functional units mentioned in a set should belong to the same
10297 The last construction (@samp{final_absence_set}) is analogous to
10298 @samp{absence_set} but checking is done on the result (state)
10299 reservation. See comments for @samp{final_presence_set}.
10301 @findex automata_option
10302 @cindex deterministic finite state automaton
10303 @cindex nondeterministic finite state automaton
10304 @cindex finite state automaton minimization
10305 You can control the generator of the pipeline hazard recognizer with
10306 the following construction.
10309 (automata_option @var{options})
10312 @var{options} is a string giving options which affect the generated
10313 code. Currently there are the following options:
10317 @dfn{no-minimization} makes no minimization of the automaton. This is
10318 only worth to do when we are debugging the description and need to
10319 look more accurately at reservations of states.
10322 @dfn{time} means printing time statistics about the generation of
10326 @dfn{stats} means printing statistics about the generated automata
10327 such as the number of DFA states, NDFA states and arcs.
10330 @dfn{v} means a generation of the file describing the result automata.
10331 The file has suffix @samp{.dfa} and can be used for the description
10332 verification and debugging.
10335 @dfn{w} means a generation of warning instead of error for
10336 non-critical errors.
10339 @dfn{no-comb-vect} prevents the automaton generator from generating
10340 two data structures and comparing them for space efficiency. Using
10341 a comb vector to represent transitions may be better, but it can be
10342 very expensive to construct. This option is useful if the build
10343 process spends an unacceptably long time in genautomata.
10346 @dfn{ndfa} makes nondeterministic finite state automata. This affects
10347 the treatment of operator @samp{|} in the regular expressions. The
10348 usual treatment of the operator is to try the first alternative and,
10349 if the reservation is not possible, the second alternative. The
10350 nondeterministic treatment means trying all alternatives, some of them
10351 may be rejected by reservations in the subsequent insns.
10354 @dfn{collapse-ndfa} modifies the behavior of the generator when
10355 producing an automaton. An additional state transition to collapse a
10356 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
10357 state is generated. It can be triggered by passing @code{const0_rtx} to
10358 state_transition. In such an automaton, cycle advance transitions are
10359 available only for these collapsed states. This option is useful for
10360 ports that want to use the @code{ndfa} option, but also want to use
10361 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
10364 @dfn{progress} means output of a progress bar showing how many states
10365 were generated so far for automaton being processed. This is useful
10366 during debugging a @acronym{DFA} description. If you see too many
10367 generated states, you could interrupt the generator of the pipeline
10368 hazard recognizer and try to figure out a reason for generation of the
10372 As an example, consider a superscalar @acronym{RISC} machine which can
10373 issue three insns (two integer insns and one floating point insn) on
10374 the cycle but can finish only two insns. To describe this, we define
10375 the following functional units.
10378 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
10379 (define_cpu_unit "port0, port1")
10382 All simple integer insns can be executed in any integer pipeline and
10383 their result is ready in two cycles. The simple integer insns are
10384 issued into the first pipeline unless it is reserved, otherwise they
10385 are issued into the second pipeline. Integer division and
10386 multiplication insns can be executed only in the second integer
10387 pipeline and their results are ready correspondingly in 9 and 4
10388 cycles. The integer division is not pipelined, i.e.@: the subsequent
10389 integer division insn cannot be issued until the current division
10390 insn finished. Floating point insns are fully pipelined and their
10391 results are ready in 3 cycles. Where the result of a floating point
10392 insn is used by an integer insn, an additional delay of one cycle is
10393 incurred. To describe all of this we could specify
10396 (define_cpu_unit "div")
10398 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
10399 "(i0_pipeline | i1_pipeline), (port0 | port1)")
10401 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
10402 "i1_pipeline, nothing*2, (port0 | port1)")
10404 (define_insn_reservation "div" 9 (eq_attr "type" "div")
10405 "i1_pipeline, div*7, div + (port0 | port1)")
10407 (define_insn_reservation "float" 3 (eq_attr "type" "float")
10408 "f_pipeline, nothing, (port0 | port1))
10410 (define_bypass 4 "float" "simple,mult,div")
10413 To simplify the description we could describe the following reservation
10416 (define_reservation "finish" "port0|port1")
10419 and use it in all @code{define_insn_reservation} as in the following
10423 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
10424 "(i0_pipeline | i1_pipeline), finish")
10430 @node Conditional Execution
10431 @section Conditional Execution
10432 @cindex conditional execution
10433 @cindex predication
10435 A number of architectures provide for some form of conditional
10436 execution, or predication. The hallmark of this feature is the
10437 ability to nullify most of the instructions in the instruction set.
10438 When the instruction set is large and not entirely symmetric, it
10439 can be quite tedious to describe these forms directly in the
10440 @file{.md} file. An alternative is the @code{define_cond_exec} template.
10442 @findex define_cond_exec
10445 [@var{predicate-pattern}]
10447 "@var{output-template}"
10448 "@var{optional-insn-attribues}")
10451 @var{predicate-pattern} is the condition that must be true for the
10452 insn to be executed at runtime and should match a relational operator.
10453 One can use @code{match_operator} to match several relational operators
10454 at once. Any @code{match_operand} operands must have no more than one
10457 @var{condition} is a C expression that must be true for the generated
10460 @findex current_insn_predicate
10461 @var{output-template} is a string similar to the @code{define_insn}
10462 output template (@pxref{Output Template}), except that the @samp{*}
10463 and @samp{@@} special cases do not apply. This is only useful if the
10464 assembly text for the predicate is a simple prefix to the main insn.
10465 In order to handle the general case, there is a global variable
10466 @code{current_insn_predicate} that will contain the entire predicate
10467 if the current insn is predicated, and will otherwise be @code{NULL}.
10469 @var{optional-insn-attributes} is an optional vector of attributes that gets
10470 appended to the insn attributes of the produced cond_exec rtx. It can
10471 be used to add some distinguishing attribute to cond_exec rtxs produced
10472 that way. An example usage would be to use this attribute in conjunction
10473 with attributes on the main pattern to disable particular alternatives under
10474 certain conditions.
10476 When @code{define_cond_exec} is used, an implicit reference to
10477 the @code{predicable} instruction attribute is made.
10478 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
10479 exactly two elements in its @var{list-of-values}), with the possible
10480 values being @code{no} and @code{yes}. The default and all uses in
10481 the insns must be a simple constant, not a complex expressions. It
10482 may, however, depend on the alternative, by using a comma-separated
10483 list of values. If that is the case, the port should also define an
10484 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
10485 should also allow only @code{no} and @code{yes} as its values.
10487 For each @code{define_insn} for which the @code{predicable}
10488 attribute is true, a new @code{define_insn} pattern will be
10489 generated that matches a predicated version of the instruction.
10493 (define_insn "addsi"
10494 [(set (match_operand:SI 0 "register_operand" "r")
10495 (plus:SI (match_operand:SI 1 "register_operand" "r")
10496 (match_operand:SI 2 "register_operand" "r")))]
10501 [(ne (match_operand:CC 0 "register_operand" "c")
10508 generates a new pattern
10513 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
10514 (set (match_operand:SI 0 "register_operand" "r")
10515 (plus:SI (match_operand:SI 1 "register_operand" "r")
10516 (match_operand:SI 2 "register_operand" "r"))))]
10517 "(@var{test2}) && (@var{test1})"
10518 "(%3) add %2,%1,%0")
10524 @section RTL Templates Transformations
10525 @cindex define_subst
10527 For some hardware architectures there are common cases when the RTL
10528 templates for the instructions can be derived from the other RTL
10529 templates using simple transformations. E.g., @file{i386.md} contains
10530 an RTL template for the ordinary @code{sub} instruction---
10531 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
10532 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
10533 implemented by a single meta-template capable of generating a modified
10534 case based on the initial one:
10536 @findex define_subst
10538 (define_subst "@var{name}"
10539 [@var{input-template}]
10541 [@var{output-template}])
10543 @var{input-template} is a pattern describing the source RTL template,
10544 which will be transformed.
10546 @var{condition} is a C expression that is conjunct with the condition
10547 from the input-template to generate a condition to be used in the
10550 @var{output-template} is a pattern that will be used in the resulting
10553 @code{define_subst} mechanism is tightly coupled with the notion of the
10554 subst attribute (@pxref{Subst Iterators}). The use of
10555 @code{define_subst} is triggered by a reference to a subst attribute in
10556 the transforming RTL template. This reference initiates duplication of
10557 the source RTL template and substitution of the attributes with their
10558 values. The source RTL template is left unchanged, while the copy is
10559 transformed by @code{define_subst}. This transformation can fail in the
10560 case when the source RTL template is not matched against the
10561 input-template of the @code{define_subst}. In such case the copy is
10564 @code{define_subst} can be used only in @code{define_insn} and
10565 @code{define_expand}, it cannot be used in other expressions (e.g.@: in
10566 @code{define_insn_and_split}).
10569 * Define Subst Example:: Example of @code{define_subst} work.
10570 * Define Subst Pattern Matching:: Process of template comparison.
10571 * Define Subst Output Template:: Generation of output template.
10574 @node Define Subst Example
10575 @subsection @code{define_subst} Example
10576 @cindex define_subst
10578 To illustrate how @code{define_subst} works, let us examine a simple
10579 template transformation.
10581 Suppose there are two kinds of instructions: one that touches flags and
10582 the other that does not. The instructions of the second type could be
10583 generated with the following @code{define_subst}:
10586 (define_subst "add_clobber_subst"
10587 [(set (match_operand:SI 0 "" "")
10588 (match_operand:SI 1 "" ""))]
10590 [(set (match_dup 0)
10592 (clobber (reg:CC FLAGS_REG))])
10595 This @code{define_subst} can be applied to any RTL pattern containing
10596 @code{set} of mode SI and generates a copy with clobber when it is
10599 Assume there is an RTL template for a @code{max} instruction to be used
10600 in @code{define_subst} mentioned above:
10603 (define_insn "maxsi"
10604 [(set (match_operand:SI 0 "register_operand" "=r")
10606 (match_operand:SI 1 "register_operand" "r")
10607 (match_operand:SI 2 "register_operand" "r")))]
10609 "max\t@{%2, %1, %0|%0, %1, %2@}"
10613 To mark the RTL template for @code{define_subst} application,
10614 subst-attributes are used. They should be declared in advance:
10617 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
10620 Here @samp{add_clobber_name} is the attribute name,
10621 @samp{add_clobber_subst} is the name of the corresponding
10622 @code{define_subst}, the third argument (@samp{_noclobber}) is the
10623 attribute value that would be substituted into the unchanged version of
10624 the source RTL template, and the last argument (@samp{_clobber}) is the
10625 value that would be substituted into the second, transformed,
10626 version of the RTL template.
10628 Once the subst-attribute has been defined, it should be used in RTL
10629 templates which need to be processed by the @code{define_subst}. So,
10630 the original RTL template should be changed:
10633 (define_insn "maxsi<add_clobber_name>"
10634 [(set (match_operand:SI 0 "register_operand" "=r")
10636 (match_operand:SI 1 "register_operand" "r")
10637 (match_operand:SI 2 "register_operand" "r")))]
10639 "max\t@{%2, %1, %0|%0, %1, %2@}"
10643 The result of the @code{define_subst} usage would look like the following:
10646 (define_insn "maxsi_noclobber"
10647 [(set (match_operand:SI 0 "register_operand" "=r")
10649 (match_operand:SI 1 "register_operand" "r")
10650 (match_operand:SI 2 "register_operand" "r")))]
10652 "max\t@{%2, %1, %0|%0, %1, %2@}"
10654 (define_insn "maxsi_clobber"
10655 [(set (match_operand:SI 0 "register_operand" "=r")
10657 (match_operand:SI 1 "register_operand" "r")
10658 (match_operand:SI 2 "register_operand" "r")))
10659 (clobber (reg:CC FLAGS_REG))]
10661 "max\t@{%2, %1, %0|%0, %1, %2@}"
10665 @node Define Subst Pattern Matching
10666 @subsection Pattern Matching in @code{define_subst}
10667 @cindex define_subst
10669 All expressions, allowed in @code{define_insn} or @code{define_expand},
10670 are allowed in the input-template of @code{define_subst}, except
10671 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
10672 meanings of expressions in the input-template were changed:
10674 @code{match_operand} matches any expression (possibly, a subtree in
10675 RTL-template), if modes of the @code{match_operand} and this expression
10676 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
10677 this expression is @code{match_dup}, @code{match_op_dup}. If the
10678 expression is @code{match_operand} too, and predicate of
10679 @code{match_operand} from the input pattern is not empty, then the
10680 predicates are compared. That can be used for more accurate filtering
10681 of accepted RTL-templates.
10683 @code{match_operator} matches common operators (like @code{plus},
10684 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
10685 @code{match_operator}s from the original pattern if the modes match and
10686 @code{match_operator} from the input pattern has the same number of
10687 operands as the operator from the original pattern.
10689 @node Define Subst Output Template
10690 @subsection Generation of output template in @code{define_subst}
10691 @cindex define_subst
10693 If all necessary checks for @code{define_subst} application pass, a new
10694 RTL-pattern, based on the output-template, is created to replace the old
10695 template. Like in input-patterns, meanings of some RTL expressions are
10696 changed when they are used in output-patterns of a @code{define_subst}.
10697 Thus, @code{match_dup} is used for copying the whole expression from the
10698 original pattern, which matched corresponding @code{match_operand} from
10701 @code{match_dup N} is used in the output template to be replaced with
10702 the expression from the original pattern, which matched
10703 @code{match_operand N} from the input pattern. As a consequence,
10704 @code{match_dup} cannot be used to point to @code{match_operand}s from
10705 the output pattern, it should always refer to a @code{match_operand}
10706 from the input pattern. If a @code{match_dup N} occurs more than once
10707 in the output template, its first occurrence is replaced with the
10708 expression from the original pattern, and the subsequent expressions
10709 are replaced with @code{match_dup N}, i.e., a reference to the first
10712 In the output template one can refer to the expressions from the
10713 original pattern and create new ones. For instance, some operands could
10714 be added by means of standard @code{match_operand}.
10716 After replacing @code{match_dup} with some RTL-subtree from the original
10717 pattern, it could happen that several @code{match_operand}s in the
10718 output pattern have the same indexes. It is unknown, how many and what
10719 indexes would be used in the expression which would replace
10720 @code{match_dup}, so such conflicts in indexes are inevitable. To
10721 overcome this issue, @code{match_operands} and @code{match_operators},
10722 which were introduced into the output pattern, are renumerated when all
10723 @code{match_dup}s are replaced.
10725 Number of alternatives in @code{match_operand}s introduced into the
10726 output template @code{M} could differ from the number of alternatives in
10727 the original pattern @code{N}, so in the resultant pattern there would
10728 be @code{N*M} alternatives. Thus, constraints from the original pattern
10729 would be duplicated @code{N} times, constraints from the output pattern
10730 would be duplicated @code{M} times, producing all possible combinations.
10734 @node Constant Definitions
10735 @section Constant Definitions
10736 @cindex constant definitions
10737 @findex define_constants
10739 Using literal constants inside instruction patterns reduces legibility and
10740 can be a maintenance problem.
10742 To overcome this problem, you may use the @code{define_constants}
10743 expression. It contains a vector of name-value pairs. From that
10744 point on, wherever any of the names appears in the MD file, it is as
10745 if the corresponding value had been written instead. You may use
10746 @code{define_constants} multiple times; each appearance adds more
10747 constants to the table. It is an error to redefine a constant with
10750 To come back to the a29k load multiple example, instead of
10754 [(match_parallel 0 "load_multiple_operation"
10755 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10756 (match_operand:SI 2 "memory_operand" "m"))
10758 (clobber (reg:SI 179))])]
10766 (define_constants [
10774 [(match_parallel 0 "load_multiple_operation"
10775 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10776 (match_operand:SI 2 "memory_operand" "m"))
10777 (use (reg:SI R_CR))
10778 (clobber (reg:SI R_CR))])]
10783 The constants that are defined with a define_constant are also output
10784 in the insn-codes.h header file as #defines.
10786 @cindex enumerations
10787 @findex define_c_enum
10788 You can also use the machine description file to define enumerations.
10789 Like the constants defined by @code{define_constant}, these enumerations
10790 are visible to both the machine description file and the main C code.
10792 The syntax is as follows:
10795 (define_c_enum "@var{name}" [
10803 This definition causes the equivalent of the following C code to appear
10804 in @file{insn-constants.h}:
10811 @var{valuen} = @var{n}
10813 #define NUM_@var{cname}_VALUES (@var{n} + 1)
10816 where @var{cname} is the capitalized form of @var{name}.
10817 It also makes each @var{valuei} available in the machine description
10818 file, just as if it had been declared with:
10821 (define_constants [(@var{valuei} @var{i})])
10824 Each @var{valuei} is usually an upper-case identifier and usually
10825 begins with @var{cname}.
10827 You can split the enumeration definition into as many statements as
10828 you like. The above example is directly equivalent to:
10831 (define_c_enum "@var{name}" [@var{value0}])
10832 (define_c_enum "@var{name}" [@var{value1}])
10834 (define_c_enum "@var{name}" [@var{valuen}])
10837 Splitting the enumeration helps to improve the modularity of each
10838 individual @code{.md} file. For example, if a port defines its
10839 synchronization instructions in a separate @file{sync.md} file,
10840 it is convenient to define all synchronization-specific enumeration
10841 values in @file{sync.md} rather than in the main @file{.md} file.
10843 Some enumeration names have special significance to GCC:
10847 @findex unspec_volatile
10848 If an enumeration called @code{unspecv} is defined, GCC will use it
10849 when printing out @code{unspec_volatile} expressions. For example:
10852 (define_c_enum "unspecv" [
10857 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
10860 (unspec_volatile ... UNSPECV_BLOCKAGE)
10865 If an enumeration called @code{unspec} is defined, GCC will use
10866 it when printing out @code{unspec} expressions. GCC will also use
10867 it when printing out @code{unspec_volatile} expressions unless an
10868 @code{unspecv} enumeration is also defined. You can therefore
10869 decide whether to keep separate enumerations for volatile and
10870 non-volatile expressions or whether to use the same enumeration
10874 @findex define_enum
10875 @anchor{define_enum}
10876 Another way of defining an enumeration is to use @code{define_enum}:
10879 (define_enum "@var{name}" [
10887 This directive implies:
10890 (define_c_enum "@var{name}" [
10891 @var{cname}_@var{cvalue0}
10892 @var{cname}_@var{cvalue1}
10894 @var{cname}_@var{cvaluen}
10898 @findex define_enum_attr
10899 where @var{cvaluei} is the capitalized form of @var{valuei}.
10900 However, unlike @code{define_c_enum}, the enumerations defined
10901 by @code{define_enum} can be used in attribute specifications
10902 (@pxref{define_enum_attr}).
10907 @cindex iterators in @file{.md} files
10909 Ports often need to define similar patterns for more than one machine
10910 mode or for more than one rtx code. GCC provides some simple iterator
10911 facilities to make this process easier.
10914 * Mode Iterators:: Generating variations of patterns for different modes.
10915 * Code Iterators:: Doing the same for codes.
10916 * Int Iterators:: Doing the same for integers.
10917 * Subst Iterators:: Generating variations of patterns for define_subst.
10918 * Parameterized Names:: Specifying iterator values in C++ code.
10921 @node Mode Iterators
10922 @subsection Mode Iterators
10923 @cindex mode iterators in @file{.md} files
10925 Ports often need to define similar patterns for two or more different modes.
10930 If a processor has hardware support for both single and double
10931 floating-point arithmetic, the @code{SFmode} patterns tend to be
10932 very similar to the @code{DFmode} ones.
10935 If a port uses @code{SImode} pointers in one configuration and
10936 @code{DImode} pointers in another, it will usually have very similar
10937 @code{SImode} and @code{DImode} patterns for manipulating pointers.
10940 Mode iterators allow several patterns to be instantiated from one
10941 @file{.md} file template. They can be used with any type of
10942 rtx-based construct, such as a @code{define_insn},
10943 @code{define_split}, or @code{define_peephole2}.
10946 * Defining Mode Iterators:: Defining a new mode iterator.
10947 * Substitutions:: Combining mode iterators with substitutions
10948 * Examples:: Examples
10951 @node Defining Mode Iterators
10952 @subsubsection Defining Mode Iterators
10953 @findex define_mode_iterator
10955 The syntax for defining a mode iterator is:
10958 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
10961 This allows subsequent @file{.md} file constructs to use the mode suffix
10962 @code{:@var{name}}. Every construct that does so will be expanded
10963 @var{n} times, once with every use of @code{:@var{name}} replaced by
10964 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
10965 and so on. In the expansion for a particular @var{modei}, every
10966 C condition will also require that @var{condi} be true.
10971 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10974 defines a new mode suffix @code{:P}. Every construct that uses
10975 @code{:P} will be expanded twice, once with every @code{:P} replaced
10976 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
10977 The @code{:SI} version will only apply if @code{Pmode == SImode} and
10978 the @code{:DI} version will only apply if @code{Pmode == DImode}.
10980 As with other @file{.md} conditions, an empty string is treated
10981 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
10982 to @code{@var{mode}}. For example:
10985 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10988 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
10989 but that the @code{:SI} expansion has no such constraint.
10991 Iterators are applied in the order they are defined. This can be
10992 significant if two iterators are used in a construct that requires
10993 substitutions. @xref{Substitutions}.
10995 @node Substitutions
10996 @subsubsection Substitution in Mode Iterators
10997 @findex define_mode_attr
10999 If an @file{.md} file construct uses mode iterators, each version of the
11000 construct will often need slightly different strings or modes. For
11005 When a @code{define_expand} defines several @code{add@var{m}3} patterns
11006 (@pxref{Standard Names}), each expander will need to use the
11007 appropriate mode name for @var{m}.
11010 When a @code{define_insn} defines several instruction patterns,
11011 each instruction will often use a different assembler mnemonic.
11014 When a @code{define_insn} requires operands with different modes,
11015 using an iterator for one of the operand modes usually requires a specific
11016 mode for the other operand(s).
11019 GCC supports such variations through a system of ``mode attributes''.
11020 There are two standard attributes: @code{mode}, which is the name of
11021 the mode in lower case, and @code{MODE}, which is the same thing in
11022 upper case. You can define other attributes using:
11025 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
11028 where @var{name} is the name of the attribute and @var{valuei}
11029 is the value associated with @var{modei}.
11031 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
11032 each string and mode in the pattern for sequences of the form
11033 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
11034 mode attribute. If the attribute is defined for @var{mode}, the whole
11035 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
11038 For example, suppose an @file{.md} file has:
11041 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
11042 (define_mode_attr load [(SI "lw") (DI "ld")])
11045 If one of the patterns that uses @code{:P} contains the string
11046 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
11047 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
11048 @code{"ld\t%0,%1"}.
11050 Here is an example of using an attribute for a mode:
11053 (define_mode_iterator LONG [SI DI])
11054 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
11055 (define_insn @dots{}
11056 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
11059 The @code{@var{iterator}:} prefix may be omitted, in which case the
11060 substitution will be attempted for every iterator expansion.
11063 @subsubsection Mode Iterator Examples
11065 Here is an example from the MIPS port. It defines the following
11066 modes and attributes (among others):
11069 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
11070 (define_mode_attr d [(SI "") (DI "d")])
11073 and uses the following template to define both @code{subsi3}
11077 (define_insn "sub<mode>3"
11078 [(set (match_operand:GPR 0 "register_operand" "=d")
11079 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
11080 (match_operand:GPR 2 "register_operand" "d")))]
11082 "<d>subu\t%0,%1,%2"
11083 [(set_attr "type" "arith")
11084 (set_attr "mode" "<MODE>")])
11087 This is exactly equivalent to:
11090 (define_insn "subsi3"
11091 [(set (match_operand:SI 0 "register_operand" "=d")
11092 (minus:SI (match_operand:SI 1 "register_operand" "d")
11093 (match_operand:SI 2 "register_operand" "d")))]
11096 [(set_attr "type" "arith")
11097 (set_attr "mode" "SI")])
11099 (define_insn "subdi3"
11100 [(set (match_operand:DI 0 "register_operand" "=d")
11101 (minus:DI (match_operand:DI 1 "register_operand" "d")
11102 (match_operand:DI 2 "register_operand" "d")))]
11105 [(set_attr "type" "arith")
11106 (set_attr "mode" "DI")])
11109 @node Code Iterators
11110 @subsection Code Iterators
11111 @cindex code iterators in @file{.md} files
11112 @findex define_code_iterator
11113 @findex define_code_attr
11115 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
11120 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
11123 defines a pseudo rtx code @var{name} that can be instantiated as
11124 @var{codei} if condition @var{condi} is true. Each @var{codei}
11125 must have the same rtx format. @xref{RTL Classes}.
11127 As with mode iterators, each pattern that uses @var{name} will be
11128 expanded @var{n} times, once with all uses of @var{name} replaced by
11129 @var{code1}, once with all uses replaced by @var{code2}, and so on.
11130 @xref{Defining Mode Iterators}.
11132 It is possible to define attributes for codes as well as for modes.
11133 There are two standard code attributes: @code{code}, the name of the
11134 code in lower case, and @code{CODE}, the name of the code in upper case.
11135 Other attributes are defined using:
11138 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
11141 Instruction patterns can use code attributes as rtx codes, which can be
11142 useful if two sets of codes act in tandem. For example, the following
11143 @code{define_insn} defines two patterns, one calculating a signed absolute
11144 difference and another calculating an unsigned absolute difference:
11147 (define_code_iterator any_max [smax umax])
11148 (define_code_attr paired_min [(smax "smin") (umax "umin")])
11149 (define_insn @dots{}
11150 [(set (match_operand:SI 0 @dots{})
11151 (minus:SI (any_max:SI (match_operand:SI 1 @dots{})
11152 (match_operand:SI 2 @dots{}))
11153 (<paired_min>:SI (match_dup 1) (match_dup 2))))]
11157 The signed version of the instruction uses @code{smax} and @code{smin}
11158 while the unsigned version uses @code{umax} and @code{umin}. There
11159 are no versions that pair @code{smax} with @code{umin} or @code{umax}
11162 Here's an example of code iterators in action, taken from the MIPS port:
11165 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
11166 eq ne gt ge lt le gtu geu ltu leu])
11168 (define_expand "b<code>"
11170 (if_then_else (any_cond:CC (cc0)
11172 (label_ref (match_operand 0 ""))
11176 gen_conditional_branch (operands, <CODE>);
11181 This is equivalent to:
11184 (define_expand "bunordered"
11186 (if_then_else (unordered:CC (cc0)
11188 (label_ref (match_operand 0 ""))
11192 gen_conditional_branch (operands, UNORDERED);
11196 (define_expand "bordered"
11198 (if_then_else (ordered:CC (cc0)
11200 (label_ref (match_operand 0 ""))
11204 gen_conditional_branch (operands, ORDERED);
11211 @node Int Iterators
11212 @subsection Int Iterators
11213 @cindex int iterators in @file{.md} files
11214 @findex define_int_iterator
11215 @findex define_int_attr
11217 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
11222 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
11225 defines a pseudo integer constant @var{name} that can be instantiated as
11226 @var{inti} if condition @var{condi} is true. Each @var{int} must have the
11227 same rtx format. @xref{RTL Classes}. Int iterators can appear in only
11228 those rtx fields that have 'i', 'n', 'w', or 'p' as the specifier. This
11229 means that each @var{int} has to be a constant defined using define_constant
11232 As with mode and code iterators, each pattern that uses @var{name} will be
11233 expanded @var{n} times, once with all uses of @var{name} replaced by
11234 @var{int1}, once with all uses replaced by @var{int2}, and so on.
11235 @xref{Defining Mode Iterators}.
11237 It is possible to define attributes for ints as well as for codes and modes.
11238 Attributes are defined using:
11241 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
11244 Here's an example of int iterators in action, taken from the ARM port:
11247 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
11249 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
11251 (define_insn "neon_vq<absneg><mode>"
11252 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11253 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11254 (match_operand:SI 2 "immediate_operand" "i")]
11257 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
11258 [(set_attr "type" "neon_vqneg_vqabs")]
11263 This is equivalent to:
11266 (define_insn "neon_vqabs<mode>"
11267 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11268 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11269 (match_operand:SI 2 "immediate_operand" "i")]
11272 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
11273 [(set_attr "type" "neon_vqneg_vqabs")]
11276 (define_insn "neon_vqneg<mode>"
11277 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11278 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11279 (match_operand:SI 2 "immediate_operand" "i")]
11282 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
11283 [(set_attr "type" "neon_vqneg_vqabs")]
11288 @node Subst Iterators
11289 @subsection Subst Iterators
11290 @cindex subst iterators in @file{.md} files
11291 @findex define_subst
11292 @findex define_subst_attr
11294 Subst iterators are special type of iterators with the following
11295 restrictions: they could not be declared explicitly, they always have
11296 only two values, and they do not have explicit dedicated name.
11297 Subst-iterators are triggered only when corresponding subst-attribute is
11298 used in RTL-pattern.
11300 Subst iterators transform templates in the following way: the templates
11301 are duplicated, the subst-attributes in these templates are replaced
11302 with the corresponding values, and a new attribute is implicitly added
11303 to the given @code{define_insn}/@code{define_expand}. The name of the
11304 added attribute matches the name of @code{define_subst}. Such
11305 attributes are declared implicitly, and it is not allowed to have a
11306 @code{define_attr} named as a @code{define_subst}.
11308 Each subst iterator is linked to a @code{define_subst}. It is declared
11309 implicitly by the first appearance of the corresponding
11310 @code{define_subst_attr}, and it is not allowed to define it explicitly.
11312 Declarations of subst-attributes have the following syntax:
11314 @findex define_subst_attr
11316 (define_subst_attr "@var{name}"
11318 "@var{no-subst-value}"
11319 "@var{subst-applied-value}")
11322 @var{name} is a string with which the given subst-attribute could be
11325 @var{subst-name} shows which @code{define_subst} should be applied to an
11326 RTL-template if the given subst-attribute is present in the
11329 @var{no-subst-value} is a value with which subst-attribute would be
11330 replaced in the first copy of the original RTL-template.
11332 @var{subst-applied-value} is a value with which subst-attribute would be
11333 replaced in the second copy of the original RTL-template.
11335 @node Parameterized Names
11336 @subsection Parameterized Names
11337 @cindex @samp{@@} in instruction pattern names
11338 Ports sometimes need to apply iterators using C++ code, in order to
11339 get the code or RTL pattern for a specific instruction. For example,
11340 suppose we have the @samp{neon_vq<absneg><mode>} pattern given above:
11343 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
11345 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
11347 (define_insn "neon_vq<absneg><mode>"
11348 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11349 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11350 (match_operand:SI 2 "immediate_operand" "i")]
11356 A port might need to generate this pattern for a variable
11357 @samp{QABSNEG} value and a variable @samp{VDQIW} mode. There are two
11358 ways of doing this. The first is to build the rtx for the pattern
11359 directly from C++ code; this is a valid technique and avoids any risk
11360 of combinatorial explosion. The second is to prefix the instruction
11361 name with the special character @samp{@@}, which tells GCC to generate
11362 the four additional functions below. In each case, @var{name} is the
11363 name of the instruction without the leading @samp{@@} character,
11364 without the @samp{<@dots{}>} placeholders, and with any underscore
11365 before a @samp{<@dots{}>} placeholder removed if keeping it would
11366 lead to a double or trailing underscore.
11369 @item insn_code maybe_code_for_@var{name} (@var{i1}, @var{i2}, @dots{})
11370 See whether replacing the first @samp{<@dots{}>} placeholder with
11371 iterator value @var{i1}, the second with iterator value @var{i2}, and
11372 so on, gives a valid instruction. Return its code if so, otherwise
11373 return @code{CODE_FOR_nothing}.
11375 @item insn_code code_for_@var{name} (@var{i1}, @var{i2}, @dots{})
11376 Same, but abort the compiler if the requested instruction does not exist.
11378 @item rtx maybe_gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{})
11379 Check for a valid instruction in the same way as
11380 @code{maybe_code_for_@var{name}}. If the instruction exists,
11381 generate an instance of it using the operand values given by @var{op0},
11382 @var{op1}, and so on, otherwise return null.
11384 @item rtx gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{})
11385 Same, but abort the compiler if the requested instruction does not exist,
11386 or if the instruction generator invoked the @code{FAIL} macro.
11389 For example, changing the pattern above to:
11392 (define_insn "@@neon_vq<absneg><mode>"
11393 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11394 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11395 (match_operand:SI 2 "immediate_operand" "i")]
11401 would define the same patterns as before, but in addition would generate
11402 the four functions below:
11405 insn_code maybe_code_for_neon_vq (int, machine_mode);
11406 insn_code code_for_neon_vq (int, machine_mode);
11407 rtx maybe_gen_neon_vq (int, machine_mode, rtx, rtx, rtx);
11408 rtx gen_neon_vq (int, machine_mode, rtx, rtx, rtx);
11411 Calling @samp{code_for_neon_vq (UNSPEC_VQABS, V8QImode)}
11412 would then give @code{CODE_FOR_neon_vqabsv8qi}.
11414 It is possible to have multiple @samp{@@} patterns with the same
11415 name and same types of iterator. For example:
11418 (define_insn "@@some_arithmetic_op<mode>"
11419 [(set (match_operand:INTEGER_MODES 0 "register_operand") @dots{})]
11423 (define_insn "@@some_arithmetic_op<mode>"
11424 [(set (match_operand:FLOAT_MODES 0 "register_operand") @dots{})]
11429 would produce a single set of functions that handles both
11430 @code{INTEGER_MODES} and @code{FLOAT_MODES}.
11432 It is also possible for these @samp{@@} patterns to have different
11433 numbers of operands from each other. For example, patterns with
11434 a binary rtl code might take three operands (one output and two inputs)
11435 while patterns with a ternary rtl code might take four operands (one
11436 output and three inputs). This combination would produce separate
11437 @samp{maybe_gen_@var{name}} and @samp{gen_@var{name}} functions for
11438 each operand count, but it would still produce a single
11439 @samp{maybe_code_for_@var{name}} and a single @samp{code_for_@var{name}}.