1 @c Copyright (C) 1988-2018 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 A @code{define_insn} expression is used to define instruction patterns
109 to which insns may be matched. A @code{define_insn} expression contains
110 an incomplete RTL expression, with pieces to be filled in later, operand
111 constraints that restrict how the pieces can be filled in, and an output
112 template or C code to generate the assembler output.
114 A @code{define_insn} is an RTL expression containing four or five operands:
118 An optional name @var{n}. When a name is present, the compiler
119 automically generates a C++ function @samp{gen_@var{n}} that takes
120 the operands of the instruction as arguments and returns the instruction's
121 rtx pattern. The compiler also assigns the instruction a unique code
122 @samp{CODE_FOR_@var{n}}, with all such codes belonging to an enum
123 called @code{insn_code}.
125 These names serve one of two purposes. The first is to indicate that the
126 instruction performs a certain standard job for the RTL-generation
127 pass of the compiler, such as a move, an addition, or a conditional
128 jump. The second is to help the target generate certain target-specific
129 operations, such as when implementing target-specific intrinsic functions.
131 It is better to prefix target-specific names with the name of the
132 target, to avoid any clash with current or future standard names.
134 The absence of a name is indicated by writing an empty string
135 where the name should go. Nameless instruction patterns are never
136 used for generating RTL code, but they may permit several simpler insns
137 to be combined later on.
139 For the purpose of debugging the compiler, you may also specify a
140 name beginning with the @samp{*} character. Such a name is used only
141 for identifying the instruction in RTL dumps; it is equivalent to having
142 a nameless pattern for all other purposes. Names beginning with the
143 @samp{*} character are not required to be unique.
145 The name may also have the form @samp{@@@var{n}}. This has the same
146 effect as a name @samp{@var{n}}, but in addition tells the compiler to
147 generate further helper functions; see @ref{Parameterized Names} for details.
150 The @dfn{RTL template}: This is a vector of incomplete RTL expressions
151 which describe the semantics of the instruction (@pxref{RTL Template}).
152 It is incomplete because it may contain @code{match_operand},
153 @code{match_operator}, and @code{match_dup} expressions that stand for
154 operands of the instruction.
156 If the vector has multiple elements, the RTL template is treated as a
157 @code{parallel} expression.
160 @cindex pattern conditions
161 @cindex conditions, in patterns
162 The condition: This is a string which contains a C expression. When the
163 compiler attempts to match RTL against a pattern, the condition is
164 evaluated. If the condition evaluates to @code{true}, the match is
165 permitted. The condition may be an empty string, which is treated
166 as always @code{true}.
168 @cindex named patterns and conditions
169 For a named pattern, the condition may not depend on the data in the
170 insn being matched, but only the target-machine-type flags. The compiler
171 needs to test these conditions during initialization in order to learn
172 exactly which named instructions are available in a particular run.
175 For nameless patterns, the condition is applied only when matching an
176 individual insn, and only after the insn has matched the pattern's
177 recognition template. The insn's operands may be found in the vector
180 An instruction condition cannot become more restrictive as compilation
181 progresses. If the condition accepts a particular RTL instruction at
182 one stage of compilation, it must continue to accept that instruction
183 until the final pass. For example, @samp{!reload_completed} and
184 @samp{can_create_pseudo_p ()} are both invalid instruction conditions,
185 because they are true during the earlier RTL passes and false during
186 the later ones. For the same reason, if a condition accepts an
187 instruction before register allocation, it cannot later try to control
188 register allocation by excluding certain register or value combinations.
190 Although a condition cannot become more restrictive as compilation
191 progresses, the condition for a nameless pattern @emph{can} become
192 more permissive. For example, a nameless instruction can require
193 @samp{reload_completed} to be true, in which case it only matches
194 after register allocation.
197 The @dfn{output template} or @dfn{output statement}: This is either
198 a string, or a fragment of C code which returns a string.
200 When simple substitution isn't general enough, you can specify a piece
201 of C code to compute the output. @xref{Output Statement}.
204 The @dfn{insn attributes}: This is an optional vector containing the values of
205 attributes for insns matching this pattern (@pxref{Insn Attributes}).
209 @section Example of @code{define_insn}
210 @cindex @code{define_insn} example
212 Here is an example of an instruction pattern, taken from the machine
213 description for the 68000/68020.
218 (match_operand:SI 0 "general_operand" "rm"))]
222 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
224 return \"cmpl #0,%0\";
229 This can also be written using braced strings:
234 (match_operand:SI 0 "general_operand" "rm"))]
237 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
243 This describes an instruction which sets the condition codes based on the
244 value of a general operand. It has no condition, so any insn with an RTL
245 description of the form shown may be matched to this pattern. The name
246 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL
247 generation pass that, when it is necessary to test such a value, an insn
248 to do so can be constructed using this pattern.
250 The output control string is a piece of C code which chooses which
251 output template to return based on the kind of operand and the specific
252 type of CPU for which code is being generated.
254 @samp{"rm"} is an operand constraint. Its meaning is explained below.
257 @section RTL Template
258 @cindex RTL insn template
259 @cindex generating insns
260 @cindex insns, generating
261 @cindex recognizing insns
262 @cindex insns, recognizing
264 The RTL template is used to define which insns match the particular pattern
265 and how to find their operands. For named patterns, the RTL template also
266 says how to construct an insn from specified operands.
268 Construction involves substituting specified operands into a copy of the
269 template. Matching involves determining the values that serve as the
270 operands in the insn being matched. Both of these activities are
271 controlled by special expression types that direct matching and
272 substitution of the operands.
275 @findex match_operand
276 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
277 This expression is a placeholder for operand number @var{n} of
278 the insn. When constructing an insn, operand number @var{n}
279 will be substituted at this point. When matching an insn, whatever
280 appears at this position in the insn will be taken as operand
281 number @var{n}; but it must satisfy @var{predicate} or this instruction
282 pattern will not match at all.
284 Operand numbers must be chosen consecutively counting from zero in
285 each instruction pattern. There may be only one @code{match_operand}
286 expression in the pattern for each operand number. Usually operands
287 are numbered in the order of appearance in @code{match_operand}
288 expressions. In the case of a @code{define_expand}, any operand numbers
289 used only in @code{match_dup} expressions have higher values than all
290 other operand numbers.
292 @var{predicate} is a string that is the name of a function that
293 accepts two arguments, an expression and a machine mode.
294 @xref{Predicates}. During matching, the function will be called with
295 the putative operand as the expression and @var{m} as the mode
296 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
297 which normally causes @var{predicate} to accept any mode). If it
298 returns zero, this instruction pattern fails to match.
299 @var{predicate} may be an empty string; then it means no test is to be
300 done on the operand, so anything which occurs in this position is
303 Most of the time, @var{predicate} will reject modes other than @var{m}---but
304 not always. For example, the predicate @code{address_operand} uses
305 @var{m} as the mode of memory ref that the address should be valid for.
306 Many predicates accept @code{const_int} nodes even though their mode is
309 @var{constraint} controls reloading and the choice of the best register
310 class to use for a value, as explained later (@pxref{Constraints}).
311 If the constraint would be an empty string, it can be omitted.
313 People are often unclear on the difference between the constraint and the
314 predicate. The predicate helps decide whether a given insn matches the
315 pattern. The constraint plays no role in this decision; instead, it
316 controls various decisions in the case of an insn which does match.
318 @findex match_scratch
319 @item (match_scratch:@var{m} @var{n} @var{constraint})
320 This expression is also a placeholder for operand number @var{n}
321 and indicates that operand must be a @code{scratch} or @code{reg}
324 When matching patterns, this is equivalent to
327 (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint})
330 but, when generating RTL, it produces a (@code{scratch}:@var{m})
333 If the last few expressions in a @code{parallel} are @code{clobber}
334 expressions whose operands are either a hard register or
335 @code{match_scratch}, the combiner can add or delete them when
336 necessary. @xref{Side Effects}.
339 @item (match_dup @var{n})
340 This expression is also a placeholder for operand number @var{n}.
341 It is used when the operand needs to appear more than once in the
344 In construction, @code{match_dup} acts just like @code{match_operand}:
345 the operand is substituted into the insn being constructed. But in
346 matching, @code{match_dup} behaves differently. It assumes that operand
347 number @var{n} has already been determined by a @code{match_operand}
348 appearing earlier in the recognition template, and it matches only an
349 identical-looking expression.
351 Note that @code{match_dup} should not be used to tell the compiler that
352 a particular register is being used for two operands (example:
353 @code{add} that adds one register to another; the second register is
354 both an input operand and the output operand). Use a matching
355 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
356 operand is used in two places in the template, such as an instruction
357 that computes both a quotient and a remainder, where the opcode takes
358 two input operands but the RTL template has to refer to each of those
359 twice; once for the quotient pattern and once for the remainder pattern.
361 @findex match_operator
362 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
363 This pattern is a kind of placeholder for a variable RTL expression
366 When constructing an insn, it stands for an RTL expression whose
367 expression code is taken from that of operand @var{n}, and whose
368 operands are constructed from the patterns @var{operands}.
370 When matching an expression, it matches an expression if the function
371 @var{predicate} returns nonzero on that expression @emph{and} the
372 patterns @var{operands} match the operands of the expression.
374 Suppose that the function @code{commutative_operator} is defined as
375 follows, to match any expression whose operator is one of the
376 commutative arithmetic operators of RTL and whose mode is @var{mode}:
380 commutative_integer_operator (x, mode)
384 enum rtx_code code = GET_CODE (x);
385 if (GET_MODE (x) != mode)
387 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
388 || code == EQ || code == NE);
392 Then the following pattern will match any RTL expression consisting
393 of a commutative operator applied to two general operands:
396 (match_operator:SI 3 "commutative_operator"
397 [(match_operand:SI 1 "general_operand" "g")
398 (match_operand:SI 2 "general_operand" "g")])
401 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
402 because the expressions to be matched all contain two operands.
404 When this pattern does match, the two operands of the commutative
405 operator are recorded as operands 1 and 2 of the insn. (This is done
406 by the two instances of @code{match_operand}.) Operand 3 of the insn
407 will be the entire commutative expression: use @code{GET_CODE
408 (operands[3])} to see which commutative operator was used.
410 The machine mode @var{m} of @code{match_operator} works like that of
411 @code{match_operand}: it is passed as the second argument to the
412 predicate function, and that function is solely responsible for
413 deciding whether the expression to be matched ``has'' that mode.
415 When constructing an insn, argument 3 of the gen-function will specify
416 the operation (i.e.@: the expression code) for the expression to be
417 made. It should be an RTL expression, whose expression code is copied
418 into a new expression whose operands are arguments 1 and 2 of the
419 gen-function. The subexpressions of argument 3 are not used;
420 only its expression code matters.
422 When @code{match_operator} is used in a pattern for matching an insn,
423 it usually best if the operand number of the @code{match_operator}
424 is higher than that of the actual operands of the insn. This improves
425 register allocation because the register allocator often looks at
426 operands 1 and 2 of insns to see if it can do register tying.
428 There is no way to specify constraints in @code{match_operator}. The
429 operand of the insn which corresponds to the @code{match_operator}
430 never has any constraints because it is never reloaded as a whole.
431 However, if parts of its @var{operands} are matched by
432 @code{match_operand} patterns, those parts may have constraints of
436 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
437 Like @code{match_dup}, except that it applies to operators instead of
438 operands. When constructing an insn, operand number @var{n} will be
439 substituted at this point. But in matching, @code{match_op_dup} behaves
440 differently. It assumes that operand number @var{n} has already been
441 determined by a @code{match_operator} appearing earlier in the
442 recognition template, and it matches only an identical-looking
445 @findex match_parallel
446 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
447 This pattern is a placeholder for an insn that consists of a
448 @code{parallel} expression with a variable number of elements. This
449 expression should only appear at the top level of an insn pattern.
451 When constructing an insn, operand number @var{n} will be substituted at
452 this point. When matching an insn, it matches if the body of the insn
453 is a @code{parallel} expression with at least as many elements as the
454 vector of @var{subpat} expressions in the @code{match_parallel}, if each
455 @var{subpat} matches the corresponding element of the @code{parallel},
456 @emph{and} the function @var{predicate} returns nonzero on the
457 @code{parallel} that is the body of the insn. It is the responsibility
458 of the predicate to validate elements of the @code{parallel} beyond
459 those listed in the @code{match_parallel}.
461 A typical use of @code{match_parallel} is to match load and store
462 multiple expressions, which can contain a variable number of elements
463 in a @code{parallel}. For example,
467 [(match_parallel 0 "load_multiple_operation"
468 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
469 (match_operand:SI 2 "memory_operand" "m"))
471 (clobber (reg:SI 179))])]
476 This example comes from @file{a29k.md}. The function
477 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
478 that subsequent elements in the @code{parallel} are the same as the
479 @code{set} in the pattern, except that they are referencing subsequent
480 registers and memory locations.
482 An insn that matches this pattern might look like:
486 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
488 (clobber (reg:SI 179))
490 (mem:SI (plus:SI (reg:SI 100)
493 (mem:SI (plus:SI (reg:SI 100)
497 @findex match_par_dup
498 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
499 Like @code{match_op_dup}, but for @code{match_parallel} instead of
500 @code{match_operator}.
504 @node Output Template
505 @section Output Templates and Operand Substitution
506 @cindex output templates
507 @cindex operand substitution
509 @cindex @samp{%} in template
511 The @dfn{output template} is a string which specifies how to output the
512 assembler code for an instruction pattern. Most of the template is a
513 fixed string which is output literally. The character @samp{%} is used
514 to specify where to substitute an operand; it can also be used to
515 identify places where different variants of the assembler require
518 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
519 operand @var{n} at that point in the string.
521 @samp{%} followed by a letter and a digit says to output an operand in an
522 alternate fashion. Four letters have standard, built-in meanings described
523 below. The machine description macro @code{PRINT_OPERAND} can define
524 additional letters with nonstandard meanings.
526 @samp{%c@var{digit}} can be used to substitute an operand that is a
527 constant value without the syntax that normally indicates an immediate
530 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
531 the constant is negated before printing.
533 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
534 memory reference, with the actual operand treated as the address. This may
535 be useful when outputting a ``load address'' instruction, because often the
536 assembler syntax for such an instruction requires you to write the operand
537 as if it were a memory reference.
539 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
542 @samp{%=} outputs a number which is unique to each instruction in the
543 entire compilation. This is useful for making local labels to be
544 referred to more than once in a single template that generates multiple
545 assembler instructions.
547 @samp{%} followed by a punctuation character specifies a substitution that
548 does not use an operand. Only one case is standard: @samp{%%} outputs a
549 @samp{%} into the assembler code. Other nonstandard cases can be
550 defined in the @code{PRINT_OPERAND} macro. You must also define
551 which punctuation characters are valid with the
552 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
556 The template may generate multiple assembler instructions. Write the text
557 for the instructions, with @samp{\;} between them.
559 @cindex matching operands
560 When the RTL contains two operands which are required by constraint to match
561 each other, the output template must refer only to the lower-numbered operand.
562 Matching operands are not always identical, and the rest of the compiler
563 arranges to put the proper RTL expression for printing into the lower-numbered
566 One use of nonstandard letters or punctuation following @samp{%} is to
567 distinguish between different assembler languages for the same machine; for
568 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
569 requires periods in most opcode names, while MIT syntax does not. For
570 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
571 syntax. The same file of patterns is used for both kinds of output syntax,
572 but the character sequence @samp{%.} is used in each place where Motorola
573 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
574 defines the sequence to output a period; the macro for MIT syntax defines
577 @cindex @code{#} in template
578 As a special case, a template consisting of the single character @code{#}
579 instructs the compiler to first split the insn, and then output the
580 resulting instructions separately. This helps eliminate redundancy in the
581 output templates. If you have a @code{define_insn} that needs to emit
582 multiple assembler instructions, and there is a matching @code{define_split}
583 already defined, then you can simply use @code{#} as the output template
584 instead of writing an output template that emits the multiple assembler
587 Note that @code{#} only has an effect while generating assembly code;
588 it does not affect whether a split occurs earlier. An associated
589 @code{define_split} must exist and it must be suitable for use after
592 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
593 of the form @samp{@{option0|option1|option2@}} in the templates. These
594 describe multiple variants of assembler language syntax.
595 @xref{Instruction Output}.
597 @node Output Statement
598 @section C Statements for Assembler Output
599 @cindex output statements
600 @cindex C statements for assembler output
601 @cindex generating assembler output
603 Often a single fixed template string cannot produce correct and efficient
604 assembler code for all the cases that are recognized by a single
605 instruction pattern. For example, the opcodes may depend on the kinds of
606 operands; or some unfortunate combinations of operands may require extra
607 machine instructions.
609 If the output control string starts with a @samp{@@}, then it is actually
610 a series of templates, each on a separate line. (Blank lines and
611 leading spaces and tabs are ignored.) The templates correspond to the
612 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
613 if a target machine has a two-address add instruction @samp{addr} to add
614 into a register and another @samp{addm} to add a register to memory, you
615 might write this pattern:
618 (define_insn "addsi3"
619 [(set (match_operand:SI 0 "general_operand" "=r,m")
620 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
621 (match_operand:SI 2 "general_operand" "g,r")))]
628 @cindex @code{*} in template
629 @cindex asterisk in template
630 If the output control string starts with a @samp{*}, then it is not an
631 output template but rather a piece of C program that should compute a
632 template. It should execute a @code{return} statement to return the
633 template-string you want. Most such templates use C string literals, which
634 require doublequote characters to delimit them. To include these
635 doublequote characters in the string, prefix each one with @samp{\}.
637 If the output control string is written as a brace block instead of a
638 double-quoted string, it is automatically assumed to be C code. In that
639 case, it is not necessary to put in a leading asterisk, or to escape the
640 doublequotes surrounding C string literals.
642 The operands may be found in the array @code{operands}, whose C data type
645 It is very common to select different ways of generating assembler code
646 based on whether an immediate operand is within a certain range. Be
647 careful when doing this, because the result of @code{INTVAL} is an
648 integer on the host machine. If the host machine has more bits in an
649 @code{int} than the target machine has in the mode in which the constant
650 will be used, then some of the bits you get from @code{INTVAL} will be
651 superfluous. For proper results, you must carefully disregard the
652 values of those bits.
654 @findex output_asm_insn
655 It is possible to output an assembler instruction and then go on to output
656 or compute more of them, using the subroutine @code{output_asm_insn}. This
657 receives two arguments: a template-string and a vector of operands. The
658 vector may be @code{operands}, or it may be another array of @code{rtx}
659 that you declare locally and initialize yourself.
661 @findex which_alternative
662 When an insn pattern has multiple alternatives in its constraints, often
663 the appearance of the assembler code is determined mostly by which alternative
664 was matched. When this is so, the C code can test the variable
665 @code{which_alternative}, which is the ordinal number of the alternative
666 that was actually satisfied (0 for the first, 1 for the second alternative,
669 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
670 for registers and @samp{clrmem} for memory locations. Here is how
671 a pattern could use @code{which_alternative} to choose between them:
675 [(set (match_operand:SI 0 "general_operand" "=r,m")
679 return (which_alternative == 0
680 ? "clrreg %0" : "clrmem %0");
684 The example above, where the assembler code to generate was
685 @emph{solely} determined by the alternative, could also have been specified
686 as follows, having the output control string start with a @samp{@@}:
691 [(set (match_operand:SI 0 "general_operand" "=r,m")
700 If you just need a little bit of C code in one (or a few) alternatives,
701 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
706 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
711 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
719 @cindex operand predicates
720 @cindex operator predicates
722 A predicate determines whether a @code{match_operand} or
723 @code{match_operator} expression matches, and therefore whether the
724 surrounding instruction pattern will be used for that combination of
725 operands. GCC has a number of machine-independent predicates, and you
726 can define machine-specific predicates as needed. By convention,
727 predicates used with @code{match_operand} have names that end in
728 @samp{_operand}, and those used with @code{match_operator} have names
729 that end in @samp{_operator}.
731 All predicates are boolean functions (in the mathematical sense) of
732 two arguments: the RTL expression that is being considered at that
733 position in the instruction pattern, and the machine mode that the
734 @code{match_operand} or @code{match_operator} specifies. In this
735 section, the first argument is called @var{op} and the second argument
736 @var{mode}. Predicates can be called from C as ordinary two-argument
737 functions; this can be useful in output templates or other
738 machine-specific code.
740 Operand predicates can allow operands that are not actually acceptable
741 to the hardware, as long as the constraints give reload the ability to
742 fix them up (@pxref{Constraints}). However, GCC will usually generate
743 better code if the predicates specify the requirements of the machine
744 instructions as closely as possible. Reload cannot fix up operands
745 that must be constants (``immediate operands''); you must use a
746 predicate that allows only constants, or else enforce the requirement
747 in the extra condition.
749 @cindex predicates and machine modes
750 @cindex normal predicates
751 @cindex special predicates
752 Most predicates handle their @var{mode} argument in a uniform manner.
753 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
754 any mode. If @var{mode} is anything else, then @var{op} must have the
755 same mode, unless @var{op} is a @code{CONST_INT} or integer
756 @code{CONST_DOUBLE}. These RTL expressions always have
757 @code{VOIDmode}, so it would be counterproductive to check that their
758 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
759 integer @code{CONST_DOUBLE} check that the value stored in the
760 constant will fit in the requested mode.
762 Predicates with this behavior are called @dfn{normal}.
763 @command{genrecog} can optimize the instruction recognizer based on
764 knowledge of how normal predicates treat modes. It can also diagnose
765 certain kinds of common errors in the use of normal predicates; for
766 instance, it is almost always an error to use a normal predicate
767 without specifying a mode.
769 Predicates that do something different with their @var{mode} argument
770 are called @dfn{special}. The generic predicates
771 @code{address_operand} and @code{pmode_register_operand} are special
772 predicates. @command{genrecog} does not do any optimizations or
773 diagnosis when special predicates are used.
776 * Machine-Independent Predicates:: Predicates available to all back ends.
777 * Defining Predicates:: How to write machine-specific predicate
781 @node Machine-Independent Predicates
782 @subsection Machine-Independent Predicates
783 @cindex machine-independent predicates
784 @cindex generic predicates
786 These are the generic predicates available to all back ends. They are
787 defined in @file{recog.c}. The first category of predicates allow
788 only constant, or @dfn{immediate}, operands.
790 @defun immediate_operand
791 This predicate allows any sort of constant that fits in @var{mode}.
792 It is an appropriate choice for instructions that take operands that
796 @defun const_int_operand
797 This predicate allows any @code{CONST_INT} expression that fits in
798 @var{mode}. It is an appropriate choice for an immediate operand that
799 does not allow a symbol or label.
802 @defun const_double_operand
803 This predicate accepts any @code{CONST_DOUBLE} expression that has
804 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
805 accept @code{CONST_INT}. It is intended for immediate floating point
810 The second category of predicates allow only some kind of machine
813 @defun register_operand
814 This predicate allows any @code{REG} or @code{SUBREG} expression that
815 is valid for @var{mode}. It is often suitable for arithmetic
816 instruction operands on a RISC machine.
819 @defun pmode_register_operand
820 This is a slight variant on @code{register_operand} which works around
821 a limitation in the machine-description reader.
824 (match_operand @var{n} "pmode_register_operand" @var{constraint})
831 (match_operand:P @var{n} "register_operand" @var{constraint})
835 would mean, if the machine-description reader accepted @samp{:P}
836 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
837 alias for some other mode, and might vary with machine-specific
838 options. @xref{Misc}.
841 @defun scratch_operand
842 This predicate allows hard registers and @code{SCRATCH} expressions,
843 but not pseudo-registers. It is used internally by @code{match_scratch};
844 it should not be used directly.
848 The third category of predicates allow only some kind of memory reference.
850 @defun memory_operand
851 This predicate allows any valid reference to a quantity of mode
852 @var{mode} in memory, as determined by the weak form of
853 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
856 @defun address_operand
857 This predicate is a little unusual; it allows any operand that is a
858 valid expression for the @emph{address} of a quantity of mode
859 @var{mode}, again determined by the weak form of
860 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
861 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
862 @code{memory_operand}, then @var{exp} is acceptable to
863 @code{address_operand}. Note that @var{exp} does not necessarily have
867 @defun indirect_operand
868 This is a stricter form of @code{memory_operand} which allows only
869 memory references with a @code{general_operand} as the address
870 expression. New uses of this predicate are discouraged, because
871 @code{general_operand} is very permissive, so it's hard to tell what
872 an @code{indirect_operand} does or does not allow. If a target has
873 different requirements for memory operands for different instructions,
874 it is better to define target-specific predicates which enforce the
875 hardware's requirements explicitly.
879 This predicate allows a memory reference suitable for pushing a value
880 onto the stack. This will be a @code{MEM} which refers to
881 @code{stack_pointer_rtx}, with a side effect in its address expression
882 (@pxref{Incdec}); which one is determined by the
883 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
887 This predicate allows a memory reference suitable for popping a value
888 off the stack. Again, this will be a @code{MEM} referring to
889 @code{stack_pointer_rtx}, with a side effect in its address
890 expression. However, this time @code{STACK_POP_CODE} is expected.
894 The fourth category of predicates allow some combination of the above
897 @defun nonmemory_operand
898 This predicate allows any immediate or register operand valid for @var{mode}.
901 @defun nonimmediate_operand
902 This predicate allows any register or memory operand valid for @var{mode}.
905 @defun general_operand
906 This predicate allows any immediate, register, or memory operand
907 valid for @var{mode}.
911 Finally, there are two generic operator predicates.
913 @defun comparison_operator
914 This predicate matches any expression which performs an arithmetic
915 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
919 @defun ordered_comparison_operator
920 This predicate matches any expression which performs an arithmetic
921 comparison in @var{mode} and whose expression code is valid for integer
922 modes; that is, the expression code will be one of @code{eq}, @code{ne},
923 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
924 @code{ge}, @code{geu}.
927 @node Defining Predicates
928 @subsection Defining Machine-Specific Predicates
929 @cindex defining predicates
930 @findex define_predicate
931 @findex define_special_predicate
933 Many machines have requirements for their operands that cannot be
934 expressed precisely using the generic predicates. You can define
935 additional predicates using @code{define_predicate} and
936 @code{define_special_predicate} expressions. These expressions have
941 The name of the predicate, as it will be referred to in
942 @code{match_operand} or @code{match_operator} expressions.
945 An RTL expression which evaluates to true if the predicate allows the
946 operand @var{op}, false if it does not. This expression can only use
947 the following RTL codes:
951 When written inside a predicate expression, a @code{MATCH_OPERAND}
952 expression evaluates to true if the predicate it names would allow
953 @var{op}. The operand number and constraint are ignored. Due to
954 limitations in @command{genrecog}, you can only refer to generic
955 predicates and predicates that have already been defined.
958 This expression evaluates to true if @var{op} or a specified
959 subexpression of @var{op} has one of a given list of RTX codes.
961 The first operand of this expression is a string constant containing a
962 comma-separated list of RTX code names (in lower case). These are the
963 codes for which the @code{MATCH_CODE} will be true.
965 The second operand is a string constant which indicates what
966 subexpression of @var{op} to examine. If it is absent or the empty
967 string, @var{op} itself is examined. Otherwise, the string constant
968 must be a sequence of digits and/or lowercase letters. Each character
969 indicates a subexpression to extract from the current expression; for
970 the first character this is @var{op}, for the second and subsequent
971 characters it is the result of the previous character. A digit
972 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
973 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
974 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
975 @code{MATCH_CODE} then examines the RTX code of the subexpression
976 extracted by the complete string. It is not possible to extract
977 components of an @code{rtvec} that is not at position 0 within its RTX
981 This expression has one operand, a string constant containing a C
982 expression. The predicate's arguments, @var{op} and @var{mode}, are
983 available with those names in the C expression. The @code{MATCH_TEST}
984 evaluates to true if the C expression evaluates to a nonzero value.
985 @code{MATCH_TEST} expressions must not have side effects.
991 The basic @samp{MATCH_} expressions can be combined using these
992 logical operators, which have the semantics of the C operators
993 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
994 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
995 arbitrary number of arguments; this has exactly the same effect as
996 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
1000 An optional block of C code, which should execute
1001 @samp{@w{return true}} if the predicate is found to match and
1002 @samp{@w{return false}} if it does not. It must not have any side
1003 effects. The predicate arguments, @var{op} and @var{mode}, are
1004 available with those names.
1006 If a code block is present in a predicate definition, then the RTL
1007 expression must evaluate to true @emph{and} the code block must
1008 execute @samp{@w{return true}} for the predicate to allow the operand.
1009 The RTL expression is evaluated first; do not re-check anything in the
1010 code block that was checked in the RTL expression.
1013 The program @command{genrecog} scans @code{define_predicate} and
1014 @code{define_special_predicate} expressions to determine which RTX
1015 codes are possibly allowed. You should always make this explicit in
1016 the RTL predicate expression, using @code{MATCH_OPERAND} and
1019 Here is an example of a simple predicate definition, from the IA64
1020 machine description:
1024 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
1025 (define_predicate "small_addr_symbolic_operand"
1026 (and (match_code "symbol_ref")
1027 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1032 And here is another, showing the use of the C block.
1036 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1037 (define_predicate "gr_register_operand"
1038 (match_operand 0 "register_operand")
1041 if (GET_CODE (op) == SUBREG)
1042 op = SUBREG_REG (op);
1045 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1050 Predicates written with @code{define_predicate} automatically include
1051 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1052 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1053 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1054 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1055 kind of constant fits in the requested mode. This is because
1056 target-specific predicates that take constants usually have to do more
1057 stringent value checks anyway. If you need the exact same treatment
1058 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1059 provide, use a @code{MATCH_OPERAND} subexpression to call
1060 @code{const_int_operand}, @code{const_double_operand}, or
1061 @code{immediate_operand}.
1063 Predicates written with @code{define_special_predicate} do not get any
1064 automatic mode checks, and are treated as having special mode handling
1065 by @command{genrecog}.
1067 The program @command{genpreds} is responsible for generating code to
1068 test predicates. It also writes a header file containing function
1069 declarations for all machine-specific predicates. It is not necessary
1070 to declare these predicates in @file{@var{cpu}-protos.h}.
1073 @c Most of this node appears by itself (in a different place) even
1074 @c when the INTERNALS flag is clear. Passages that require the internals
1075 @c manual's context are conditionalized to appear only in the internals manual.
1078 @section Operand Constraints
1079 @cindex operand constraints
1082 Each @code{match_operand} in an instruction pattern can specify
1083 constraints for the operands allowed. The constraints allow you to
1084 fine-tune matching within the set of operands allowed by the
1090 @section Constraints for @code{asm} Operands
1091 @cindex operand constraints, @code{asm}
1092 @cindex constraints, @code{asm}
1093 @cindex @code{asm} constraints
1095 Here are specific details on what constraint letters you can use with
1096 @code{asm} operands.
1098 Constraints can say whether
1099 an operand may be in a register, and which kinds of register; whether the
1100 operand can be a memory reference, and which kinds of address; whether the
1101 operand may be an immediate constant, and which possible values it may
1102 have. Constraints can also require two operands to match.
1103 Side-effects aren't allowed in operands of inline @code{asm}, unless
1104 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1105 that the side effects will happen exactly once in an instruction that can update
1106 the addressing register.
1110 * Simple Constraints:: Basic use of constraints.
1111 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1112 * Class Preferences:: Constraints guide which hard register to put things in.
1113 * Modifiers:: More precise control over effects of constraints.
1114 * Machine Constraints:: Existing constraints for some particular machines.
1115 * Disable Insn Alternatives:: Disable insn alternatives using attributes.
1116 * Define Constraints:: How to define machine-specific constraints.
1117 * C Constraint Interface:: How to test constraints from C code.
1123 * Simple Constraints:: Basic use of constraints.
1124 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1125 * Modifiers:: More precise control over effects of constraints.
1126 * Machine Constraints:: Special constraints for some particular machines.
1130 @node Simple Constraints
1131 @subsection Simple Constraints
1132 @cindex simple constraints
1134 The simplest kind of constraint is a string full of letters, each of
1135 which describes one kind of operand that is permitted. Here are
1136 the letters that are allowed:
1140 Whitespace characters are ignored and can be inserted at any position
1141 except the first. This enables each alternative for different operands to
1142 be visually aligned in the machine description even if they have different
1143 number of constraints and modifiers.
1145 @cindex @samp{m} in constraint
1146 @cindex memory references in constraints
1148 A memory operand is allowed, with any kind of address that the machine
1149 supports in general.
1150 Note that the letter used for the general memory constraint can be
1151 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1153 @cindex offsettable address
1154 @cindex @samp{o} in constraint
1156 A memory operand is allowed, but only if the address is
1157 @dfn{offsettable}. This means that adding a small integer (actually,
1158 the width in bytes of the operand, as determined by its machine mode)
1159 may be added to the address and the result is also a valid memory
1162 @cindex autoincrement/decrement addressing
1163 For example, an address which is constant is offsettable; so is an
1164 address that is the sum of a register and a constant (as long as a
1165 slightly larger constant is also within the range of address-offsets
1166 supported by the machine); but an autoincrement or autodecrement
1167 address is not offsettable. More complicated indirect/indexed
1168 addresses may or may not be offsettable depending on the other
1169 addressing modes that the machine supports.
1171 Note that in an output operand which can be matched by another
1172 operand, the constraint letter @samp{o} is valid only when accompanied
1173 by both @samp{<} (if the target machine has predecrement addressing)
1174 and @samp{>} (if the target machine has preincrement addressing).
1176 @cindex @samp{V} in constraint
1178 A memory operand that is not offsettable. In other words, anything that
1179 would fit the @samp{m} constraint but not the @samp{o} constraint.
1181 @cindex @samp{<} in constraint
1183 A memory operand with autodecrement addressing (either predecrement or
1184 postdecrement) is allowed. In inline @code{asm} this constraint is only
1185 allowed if the operand is used exactly once in an instruction that can
1186 handle the side effects. Not using an operand with @samp{<} in constraint
1187 string in the inline @code{asm} pattern at all or using it in multiple
1188 instructions isn't valid, because the side effects wouldn't be performed
1189 or would be performed more than once. Furthermore, on some targets
1190 the operand with @samp{<} in constraint string must be accompanied by
1191 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1192 or @code{%P0} on IA-64.
1194 @cindex @samp{>} in constraint
1196 A memory operand with autoincrement addressing (either preincrement or
1197 postincrement) is allowed. In inline @code{asm} the same restrictions
1198 as for @samp{<} apply.
1200 @cindex @samp{r} in constraint
1201 @cindex registers in constraints
1203 A register operand is allowed provided that it is in a general
1206 @cindex constants in constraints
1207 @cindex @samp{i} in constraint
1209 An immediate integer operand (one with constant value) is allowed.
1210 This includes symbolic constants whose values will be known only at
1211 assembly time or later.
1213 @cindex @samp{n} in constraint
1215 An immediate integer operand with a known numeric value is allowed.
1216 Many systems cannot support assembly-time constants for operands less
1217 than a word wide. Constraints for these operands should use @samp{n}
1218 rather than @samp{i}.
1220 @cindex @samp{I} in constraint
1221 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1222 Other letters in the range @samp{I} through @samp{P} may be defined in
1223 a machine-dependent fashion to permit immediate integer operands with
1224 explicit integer values in specified ranges. For example, on the
1225 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1226 This is the range permitted as a shift count in the shift
1229 @cindex @samp{E} in constraint
1231 An immediate floating operand (expression code @code{const_double}) is
1232 allowed, but only if the target floating point format is the same as
1233 that of the host machine (on which the compiler is running).
1235 @cindex @samp{F} in constraint
1237 An immediate floating operand (expression code @code{const_double} or
1238 @code{const_vector}) is allowed.
1240 @cindex @samp{G} in constraint
1241 @cindex @samp{H} in constraint
1242 @item @samp{G}, @samp{H}
1243 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1244 permit immediate floating operands in particular ranges of values.
1246 @cindex @samp{s} in constraint
1248 An immediate integer operand whose value is not an explicit integer is
1251 This might appear strange; if an insn allows a constant operand with a
1252 value not known at compile time, it certainly must allow any known
1253 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1254 better code to be generated.
1256 For example, on the 68000 in a fullword instruction it is possible to
1257 use an immediate operand; but if the immediate value is between @minus{}128
1258 and 127, better code results from loading the value into a register and
1259 using the register. This is because the load into the register can be
1260 done with a @samp{moveq} instruction. We arrange for this to happen
1261 by defining the letter @samp{K} to mean ``any integer outside the
1262 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1265 @cindex @samp{g} in constraint
1267 Any register, memory or immediate integer operand is allowed, except for
1268 registers that are not general registers.
1270 @cindex @samp{X} in constraint
1273 Any operand whatsoever is allowed, even if it does not satisfy
1274 @code{general_operand}. This is normally used in the constraint of
1275 a @code{match_scratch} when certain alternatives will not actually
1276 require a scratch register.
1279 Any operand whatsoever is allowed.
1282 @cindex @samp{0} in constraint
1283 @cindex digits in constraint
1284 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1285 An operand that matches the specified operand number is allowed. If a
1286 digit is used together with letters within the same alternative, the
1287 digit should come last.
1289 This number is allowed to be more than a single digit. If multiple
1290 digits are encountered consecutively, they are interpreted as a single
1291 decimal integer. There is scant chance for ambiguity, since to-date
1292 it has never been desirable that @samp{10} be interpreted as matching
1293 either operand 1 @emph{or} operand 0. Should this be desired, one
1294 can use multiple alternatives instead.
1296 @cindex matching constraint
1297 @cindex constraint, matching
1298 This is called a @dfn{matching constraint} and what it really means is
1299 that the assembler has only a single operand that fills two roles
1301 considered separate in the RTL insn. For example, an add insn has two
1302 input operands and one output operand in the RTL, but on most CISC
1305 which @code{asm} distinguishes. For example, an add instruction uses
1306 two input operands and an output operand, but on most CISC
1308 machines an add instruction really has only two operands, one of them an
1309 input-output operand:
1315 Matching constraints are used in these circumstances.
1316 More precisely, the two operands that match must include one input-only
1317 operand and one output-only operand. Moreover, the digit must be a
1318 smaller number than the number of the operand that uses it in the
1322 For operands to match in a particular case usually means that they
1323 are identical-looking RTL expressions. But in a few special cases
1324 specific kinds of dissimilarity are allowed. For example, @code{*x}
1325 as an input operand will match @code{*x++} as an output operand.
1326 For proper results in such cases, the output template should always
1327 use the output-operand's number when printing the operand.
1330 @cindex load address instruction
1331 @cindex push address instruction
1332 @cindex address constraints
1333 @cindex @samp{p} in constraint
1335 An operand that is a valid memory address is allowed. This is
1336 for ``load address'' and ``push address'' instructions.
1338 @findex address_operand
1339 @samp{p} in the constraint must be accompanied by @code{address_operand}
1340 as the predicate in the @code{match_operand}. This predicate interprets
1341 the mode specified in the @code{match_operand} as the mode of the memory
1342 reference for which the address would be valid.
1344 @cindex other register constraints
1345 @cindex extensible constraints
1346 @item @var{other-letters}
1347 Other letters can be defined in machine-dependent fashion to stand for
1348 particular classes of registers or other arbitrary operand types.
1349 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1350 for data, address and floating point registers.
1354 In order to have valid assembler code, each operand must satisfy
1355 its constraint. But a failure to do so does not prevent the pattern
1356 from applying to an insn. Instead, it directs the compiler to modify
1357 the code so that the constraint will be satisfied. Usually this is
1358 done by copying an operand into a register.
1360 Contrast, therefore, the two instruction patterns that follow:
1364 [(set (match_operand:SI 0 "general_operand" "=r")
1365 (plus:SI (match_dup 0)
1366 (match_operand:SI 1 "general_operand" "r")))]
1372 which has two operands, one of which must appear in two places, and
1376 [(set (match_operand:SI 0 "general_operand" "=r")
1377 (plus:SI (match_operand:SI 1 "general_operand" "0")
1378 (match_operand:SI 2 "general_operand" "r")))]
1384 which has three operands, two of which are required by a constraint to be
1385 identical. If we are considering an insn of the form
1388 (insn @var{n} @var{prev} @var{next}
1390 (plus:SI (reg:SI 6) (reg:SI 109)))
1395 the first pattern would not apply at all, because this insn does not
1396 contain two identical subexpressions in the right place. The pattern would
1397 say, ``That does not look like an add instruction; try other patterns''.
1398 The second pattern would say, ``Yes, that's an add instruction, but there
1399 is something wrong with it''. It would direct the reload pass of the
1400 compiler to generate additional insns to make the constraint true. The
1401 results might look like this:
1404 (insn @var{n2} @var{prev} @var{n}
1405 (set (reg:SI 3) (reg:SI 6))
1408 (insn @var{n} @var{n2} @var{next}
1410 (plus:SI (reg:SI 3) (reg:SI 109)))
1414 It is up to you to make sure that each operand, in each pattern, has
1415 constraints that can handle any RTL expression that could be present for
1416 that operand. (When multiple alternatives are in use, each pattern must,
1417 for each possible combination of operand expressions, have at least one
1418 alternative which can handle that combination of operands.) The
1419 constraints don't need to @emph{allow} any possible operand---when this is
1420 the case, they do not constrain---but they must at least point the way to
1421 reloading any possible operand so that it will fit.
1425 If the constraint accepts whatever operands the predicate permits,
1426 there is no problem: reloading is never necessary for this operand.
1428 For example, an operand whose constraints permit everything except
1429 registers is safe provided its predicate rejects registers.
1431 An operand whose predicate accepts only constant values is safe
1432 provided its constraints include the letter @samp{i}. If any possible
1433 constant value is accepted, then nothing less than @samp{i} will do;
1434 if the predicate is more selective, then the constraints may also be
1438 Any operand expression can be reloaded by copying it into a register.
1439 So if an operand's constraints allow some kind of register, it is
1440 certain to be safe. It need not permit all classes of registers; the
1441 compiler knows how to copy a register into another register of the
1442 proper class in order to make an instruction valid.
1444 @cindex nonoffsettable memory reference
1445 @cindex memory reference, nonoffsettable
1447 A nonoffsettable memory reference can be reloaded by copying the
1448 address into a register. So if the constraint uses the letter
1449 @samp{o}, all memory references are taken care of.
1452 A constant operand can be reloaded by allocating space in memory to
1453 hold it as preinitialized data. Then the memory reference can be used
1454 in place of the constant. So if the constraint uses the letters
1455 @samp{o} or @samp{m}, constant operands are not a problem.
1458 If the constraint permits a constant and a pseudo register used in an insn
1459 was not allocated to a hard register and is equivalent to a constant,
1460 the register will be replaced with the constant. If the predicate does
1461 not permit a constant and the insn is re-recognized for some reason, the
1462 compiler will crash. Thus the predicate must always recognize any
1463 objects allowed by the constraint.
1466 If the operand's predicate can recognize registers, but the constraint does
1467 not permit them, it can make the compiler crash. When this operand happens
1468 to be a register, the reload pass will be stymied, because it does not know
1469 how to copy a register temporarily into memory.
1471 If the predicate accepts a unary operator, the constraint applies to the
1472 operand. For example, the MIPS processor at ISA level 3 supports an
1473 instruction which adds two registers in @code{SImode} to produce a
1474 @code{DImode} result, but only if the registers are correctly sign
1475 extended. This predicate for the input operands accepts a
1476 @code{sign_extend} of an @code{SImode} register. Write the constraint
1477 to indicate the type of register that is required for the operand of the
1481 @node Multi-Alternative
1482 @subsection Multiple Alternative Constraints
1483 @cindex multiple alternative constraints
1485 Sometimes a single instruction has multiple alternative sets of possible
1486 operands. For example, on the 68000, a logical-or instruction can combine
1487 register or an immediate value into memory, or it can combine any kind of
1488 operand into a register; but it cannot combine one memory location into
1491 These constraints are represented as multiple alternatives. An alternative
1492 can be described by a series of letters for each operand. The overall
1493 constraint for an operand is made from the letters for this operand
1494 from the first alternative, a comma, the letters for this operand from
1495 the second alternative, a comma, and so on until the last alternative.
1496 All operands for a single instruction must have the same number of
1499 Here is how it is done for fullword logical-or on the 68000:
1502 (define_insn "iorsi3"
1503 [(set (match_operand:SI 0 "general_operand" "=m,d")
1504 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1505 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1509 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1510 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1511 2. The second alternative has @samp{d} (data register) for operand 0,
1512 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1513 @samp{%} in the constraints apply to all the alternatives; their
1514 meaning is explained in the next section (@pxref{Class Preferences}).
1516 If all the operands fit any one alternative, the instruction is valid.
1517 Otherwise, for each alternative, the compiler counts how many instructions
1518 must be added to copy the operands so that that alternative applies.
1519 The alternative requiring the least copying is chosen. If two alternatives
1520 need the same amount of copying, the one that comes first is chosen.
1521 These choices can be altered with the @samp{?} and @samp{!} characters:
1524 @cindex @samp{?} in constraint
1525 @cindex question mark
1527 Disparage slightly the alternative that the @samp{?} appears in,
1528 as a choice when no alternative applies exactly. The compiler regards
1529 this alternative as one unit more costly for each @samp{?} that appears
1532 @cindex @samp{!} in constraint
1533 @cindex exclamation point
1535 Disparage severely the alternative that the @samp{!} appears in.
1536 This alternative can still be used if it fits without reloading,
1537 but if reloading is needed, some other alternative will be used.
1539 @cindex @samp{^} in constraint
1542 This constraint is analogous to @samp{?} but it disparages slightly
1543 the alternative only if the operand with the @samp{^} needs a reload.
1545 @cindex @samp{$} in constraint
1548 This constraint is analogous to @samp{!} but it disparages severely
1549 the alternative only if the operand with the @samp{$} needs a reload.
1552 When an insn pattern has multiple alternatives in its constraints, often
1553 the appearance of the assembler code is determined mostly by which
1554 alternative was matched. When this is so, the C code for writing the
1555 assembler code can use the variable @code{which_alternative}, which is
1556 the ordinal number of the alternative that was actually satisfied (0 for
1557 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1561 So the first alternative for the 68000's logical-or could be written as
1562 @code{"+m" (output) : "ir" (input)}. The second could be @code{"+r"
1563 (output): "irm" (input)}. However, the fact that two memory locations
1564 cannot be used in a single instruction prevents simply using @code{"+rm"
1565 (output) : "irm" (input)}. Using multi-alternatives, this might be
1566 written as @code{"+m,r" (output) : "ir,irm" (input)}. This describes
1567 all the available alternatives to the compiler, allowing it to choose
1568 the most efficient one for the current conditions.
1570 There is no way within the template to determine which alternative was
1571 chosen. However you may be able to wrap your @code{asm} statements with
1572 builtins such as @code{__builtin_constant_p} to achieve the desired results.
1576 @node Class Preferences
1577 @subsection Register Class Preferences
1578 @cindex class preference constraints
1579 @cindex register class preference constraints
1581 @cindex voting between constraint alternatives
1582 The operand constraints have another function: they enable the compiler
1583 to decide which kind of hardware register a pseudo register is best
1584 allocated to. The compiler examines the constraints that apply to the
1585 insns that use the pseudo register, looking for the machine-dependent
1586 letters such as @samp{d} and @samp{a} that specify classes of registers.
1587 The pseudo register is put in whichever class gets the most ``votes''.
1588 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1589 favor of a general register. The machine description says which registers
1590 are considered general.
1592 Of course, on some machines all registers are equivalent, and no register
1593 classes are defined. Then none of this complexity is relevant.
1597 @subsection Constraint Modifier Characters
1598 @cindex modifiers in constraints
1599 @cindex constraint modifier characters
1601 @c prevent bad page break with this line
1602 Here are constraint modifier characters.
1605 @cindex @samp{=} in constraint
1607 Means that this operand is written to by this instruction:
1608 the previous value is discarded and replaced by new data.
1610 @cindex @samp{+} in constraint
1612 Means that this operand is both read and written by the instruction.
1614 When the compiler fixes up the operands to satisfy the constraints,
1615 it needs to know which operands are read by the instruction and
1616 which are written by it. @samp{=} identifies an operand which is only
1617 written; @samp{+} identifies an operand that is both read and written; all
1618 other operands are assumed to only be read.
1620 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1621 first character of the constraint string.
1623 @cindex @samp{&} in constraint
1624 @cindex earlyclobber operand
1626 Means (in a particular alternative) that this operand is an
1627 @dfn{earlyclobber} operand, which is written before the instruction is
1628 finished using the input operands. Therefore, this operand may not lie
1629 in a register that is read by the instruction or as part of any memory
1632 @samp{&} applies only to the alternative in which it is written. In
1633 constraints with multiple alternatives, sometimes one alternative
1634 requires @samp{&} while others do not. See, for example, the
1635 @samp{movdf} insn of the 68000.
1637 A operand which is read by the instruction can be tied to an earlyclobber
1638 operand if its only use as an input occurs before the early result is
1639 written. Adding alternatives of this form often allows GCC to produce
1640 better code when only some of the read operands can be affected by the
1641 earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@.
1643 Furthermore, if the @dfn{earlyclobber} operand is also a read/write
1644 operand, then that operand is written only after it's used.
1646 @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As
1647 @dfn{earlyclobber} operands are always written, a read-only
1648 @dfn{earlyclobber} operand is ill-formed and will be rejected by the
1651 @cindex @samp{%} in constraint
1653 Declares the instruction to be commutative for this operand and the
1654 following operand. This means that the compiler may interchange the
1655 two operands if that is the cheapest way to make all operands fit the
1656 constraints. @samp{%} applies to all alternatives and must appear as
1657 the first character in the constraint. Only read-only operands can use
1661 This is often used in patterns for addition instructions
1662 that really have only two operands: the result must go in one of the
1663 arguments. Here for example, is how the 68000 halfword-add
1664 instruction is defined:
1667 (define_insn "addhi3"
1668 [(set (match_operand:HI 0 "general_operand" "=m,r")
1669 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1670 (match_operand:HI 2 "general_operand" "di,g")))]
1674 GCC can only handle one commutative pair in an asm; if you use more,
1675 the compiler may fail. Note that you need not use the modifier if
1676 the two alternatives are strictly identical; this would only waste
1677 time in the reload pass.
1679 The modifier is not operational after
1680 register allocation, so the result of @code{define_peephole2}
1681 and @code{define_split}s performed after reload cannot rely on
1682 @samp{%} to make the intended insn match.
1684 @cindex @samp{#} in constraint
1686 Says that all following characters, up to the next comma, are to be
1687 ignored as a constraint. They are significant only for choosing
1688 register preferences.
1690 @cindex @samp{*} in constraint
1692 Says that the following character should be ignored when choosing
1693 register preferences. @samp{*} has no effect on the meaning of the
1694 constraint as a constraint, and no effect on reloading. For LRA
1695 @samp{*} additionally disparages slightly the alternative if the
1696 following character matches the operand.
1698 Here is an example: the 68000 has an instruction to sign-extend a
1699 halfword in a data register, and can also sign-extend a value by
1700 copying it into an address register. While either kind of register is
1701 acceptable, the constraints on an address-register destination are
1702 less strict, so it is best if register allocation makes an address
1703 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1704 constraint letter (for data register) is ignored when computing
1705 register preferences.
1708 (define_insn "extendhisi2"
1709 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1711 (match_operand:HI 1 "general_operand" "0,g")))]
1717 @node Machine Constraints
1718 @subsection Constraints for Particular Machines
1719 @cindex machine specific constraints
1720 @cindex constraints, machine specific
1722 Whenever possible, you should use the general-purpose constraint letters
1723 in @code{asm} arguments, since they will convey meaning more readily to
1724 people reading your code. Failing that, use the constraint letters
1725 that usually have very similar meanings across architectures. The most
1726 commonly used constraints are @samp{m} and @samp{r} (for memory and
1727 general-purpose registers respectively; @pxref{Simple Constraints}), and
1728 @samp{I}, usually the letter indicating the most common
1729 immediate-constant format.
1731 Each architecture defines additional constraints. These constraints
1732 are used by the compiler itself for instruction generation, as well as
1733 for @code{asm} statements; therefore, some of the constraints are not
1734 particularly useful for @code{asm}. Here is a summary of some of the
1735 machine-dependent constraints available on some particular machines;
1736 it includes both constraints that are useful for @code{asm} and
1737 constraints that aren't. The compiler source file mentioned in the
1738 table heading for each architecture is the definitive reference for
1739 the meanings of that architecture's constraints.
1741 @c Please keep this table alphabetized by target!
1743 @item AArch64 family---@file{config/aarch64/constraints.md}
1746 The stack pointer register (@code{SP})
1749 Floating point register, Advanced SIMD vector register or SVE vector register
1752 One of the low eight SVE predicate registers (@code{P0} to @code{P7})
1755 Any of the SVE predicate registers (@code{P0} to @code{P15})
1758 Integer constant that is valid as an immediate operand in an @code{ADD}
1762 Integer constant that is valid as an immediate operand in a @code{SUB}
1763 instruction (once negated)
1766 Integer constant that can be used with a 32-bit logical instruction
1769 Integer constant that can be used with a 64-bit logical instruction
1772 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1773 pseudo instruction. The @code{MOV} may be assembled to one of several different
1774 machine instructions depending on the value
1777 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1781 An absolute symbolic address or a label reference
1784 Floating point constant zero
1787 Integer constant zero
1790 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1791 within 4GB of the instruction
1794 A memory address which uses a single base register with no offset
1797 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1803 @item ARC ---@file{config/arc/constraints.md}
1806 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1807 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1808 option is in effect.
1811 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1812 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1813 This constraint can only match when the @option{-mq}
1814 option is in effect.
1816 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1819 A signed 12-bit integer constant.
1822 constant for arithmetic/logical operations. This might be any constant
1823 that can be put into a long immediate by the assmbler or linker without
1824 involving a PIC relocation.
1827 A 3-bit unsigned integer constant.
1830 A 6-bit unsigned integer constant.
1833 One's complement of a 6-bit unsigned integer constant.
1836 Two's complement of a 6-bit unsigned integer constant.
1839 A 5-bit unsigned integer constant.
1842 A 7-bit unsigned integer constant.
1845 A 8-bit unsigned integer constant.
1848 Any const_double value.
1851 @item ARM family---@file{config/arm/constraints.md}
1855 In Thumb state, the core registers @code{r8}-@code{r15}.
1858 The stack pointer register.
1861 In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this
1862 is an alias for the @code{r} constraint.
1865 VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values.
1868 VFP floating-point registers @code{d0}-@code{d31} and the appropriate
1869 subset @code{d0}-@code{d15} based on command line options.
1870 Used for 64 bit values only. Not valid for Thumb1.
1873 The iWMMX co-processor registers.
1876 The iWMMX GR registers.
1879 The floating-point constant 0.0
1882 Integer that is valid as an immediate operand in a data processing
1883 instruction. That is, an integer in the range 0 to 255 rotated by a
1887 Integer in the range @minus{}4095 to 4095
1890 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1893 Integer that satisfies constraint @samp{I} when negated (twos complement)
1896 Integer in the range 0 to 32
1899 A memory reference where the exact address is in a single register
1900 (`@samp{m}' is preferable for @code{asm} statements)
1903 An item in the constant pool
1906 A symbol in the text segment of the current file
1909 A memory reference suitable for VFP load/store insns (reg+constant offset)
1912 A memory reference suitable for iWMMXt load/store instructions.
1915 A memory reference suitable for the ARMv4 ldrsb instruction.
1918 @item AVR family---@file{config/avr/constraints.md}
1921 Registers from r0 to r15
1924 Registers from r16 to r23
1927 Registers from r16 to r31
1930 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1933 Pointer register (r26--r31)
1936 Base pointer register (r28--r31)
1939 Stack pointer register (SPH:SPL)
1942 Temporary register r0
1945 Register pair X (r27:r26)
1948 Register pair Y (r29:r28)
1951 Register pair Z (r31:r30)
1954 Constant greater than @minus{}1, less than 64
1957 Constant greater than @minus{}64, less than 1
1966 Constant that fits in 8 bits
1969 Constant integer @minus{}1
1972 Constant integer 8, 16, or 24
1978 A floating point constant 0.0
1981 A memory address based on Y or Z pointer with displacement.
1984 @item Blackfin family---@file{config/bfin/constraints.md}
1993 A call clobbered P register.
1996 A single register. If @var{n} is in the range 0 to 7, the corresponding D
1997 register. If it is @code{A}, then the register P0.
2000 Even-numbered D register
2003 Odd-numbered D register
2006 Accumulator register.
2009 Even-numbered accumulator register.
2012 Odd-numbered accumulator register.
2024 Registers used for circular buffering, i.e.@: I, B, or L registers.
2039 Any D, P, B, M, I or L register.
2042 Additional registers typically used only in prologues and epilogues: RETS,
2043 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2046 Any register except accumulators or CC.
2049 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2052 Unsigned 16 bit integer (in the range 0 to 65535)
2055 Signed 7 bit integer (in the range @minus{}64 to 63)
2058 Unsigned 7 bit integer (in the range 0 to 127)
2061 Unsigned 5 bit integer (in the range 0 to 31)
2064 Signed 4 bit integer (in the range @minus{}8 to 7)
2067 Signed 3 bit integer (in the range @minus{}3 to 4)
2070 Unsigned 3 bit integer (in the range 0 to 7)
2073 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2076 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2077 use with either accumulator.
2080 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2081 use only with accumulator A1.
2090 An integer constant with exactly a single bit set.
2093 An integer constant with all bits set except exactly one.
2101 @item CR16 Architecture---@file{config/cr16/cr16.h}
2105 Registers from r0 to r14 (registers without stack pointer)
2108 Register from r0 to r11 (all 16-bit registers)
2111 Register from r12 to r15 (all 32-bit registers)
2114 Signed constant that fits in 4 bits
2117 Signed constant that fits in 5 bits
2120 Signed constant that fits in 6 bits
2123 Unsigned constant that fits in 4 bits
2126 Signed constant that fits in 32 bits
2129 Check for 64 bits wide constants for add/sub instructions
2132 Floating point constant that is legal for store immediate
2135 @item C-SKY---@file{config/csky/constraints.md}
2139 The mini registers r0 - r7.
2142 The low registers r0 - r15.
2148 HI and LO registers.
2160 Stack pointer register (SP).
2164 The C-SKY back end supports a large set of additional constraints
2165 that are only useful for instruction selection or splitting rather
2166 than inline asm, such as constraints representing constant integer
2167 ranges accepted by particular instruction encodings.
2168 Refer to the source code for details.
2171 @item Epiphany---@file{config/epiphany/constraints.md}
2174 An unsigned 16-bit constant.
2177 An unsigned 5-bit constant.
2180 A signed 11-bit constant.
2183 A signed 11-bit constant added to @minus{}1.
2184 Can only match when the @option{-m1reg-@var{reg}} option is active.
2187 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
2188 being a block of trailing zeroes.
2189 Can only match when the @option{-m1reg-@var{reg}} option is active.
2192 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
2193 rest being zeroes. Or to put it another way, one less than a power of two.
2194 Can only match when the @option{-m1reg-@var{reg}} option is active.
2197 Constant for arithmetic/logical operations.
2198 This is like @code{i}, except that for position independent code,
2199 no symbols / expressions needing relocations are allowed.
2202 Symbolic constant for call/jump instruction.
2205 The register class usable in short insns. This is a register class
2206 constraint, and can thus drive register allocation.
2207 This constraint won't match unless @option{-mprefer-short-insn-regs} is
2211 The the register class of registers that can be used to hold a
2212 sibcall call address. I.e., a caller-saved register.
2215 Core control register class.
2218 The register group usable in short insns.
2219 This constraint does not use a register class, so that it only
2220 passively matches suitable registers, and doesn't drive register allocation.
2224 Constant suitable for the addsi3_r pattern. This is a valid offset
2225 For byte, halfword, or word addressing.
2229 Matches the return address if it can be replaced with the link register.
2232 Matches the integer condition code register.
2235 Matches the return address if it is in a stack slot.
2238 Matches control register values to switch fp mode, which are encapsulated in
2239 @code{UNSPEC_FP_MODE}.
2242 @item FRV---@file{config/frv/frv.h}
2245 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2248 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2251 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2252 @code{icc0} to @code{icc3}).
2255 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2258 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2259 Odd registers are excluded not in the class but through the use of a machine
2260 mode larger than 4 bytes.
2263 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2266 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2267 Odd registers are excluded not in the class but through the use of a machine
2268 mode larger than 4 bytes.
2271 Register in the class @code{LR_REG} (the @code{lr} register).
2274 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2275 Register numbers not divisible by 4 are excluded not in the class but through
2276 the use of a machine mode larger than 8 bytes.
2279 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2282 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2285 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2288 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2291 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2292 Register numbers not divisible by 4 are excluded not in the class but through
2293 the use of a machine mode larger than 8 bytes.
2296 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2299 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2302 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2305 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2308 Floating point constant zero
2311 6-bit signed integer constant
2314 10-bit signed integer constant
2317 16-bit signed integer constant
2320 16-bit unsigned integer constant
2323 12-bit signed integer constant that is negative---i.e.@: in the
2324 range of @minus{}2048 to @minus{}1
2330 12-bit signed integer constant that is greater than zero---i.e.@: in the
2335 @item FT32---@file{config/ft32/constraints.md}
2344 A register indirect memory operand
2353 The constant zero or one
2356 A 16-bit signed constant (@minus{}32768 @dots{} 32767)
2359 A bitfield mask suitable for bext or bins
2362 An inverted bitfield mask suitable for bext or bins
2365 A 16-bit unsigned constant, multiple of 4 (0 @dots{} 65532)
2368 A 20-bit signed constant (@minus{}524288 @dots{} 524287)
2371 A constant for a bitfield width (1 @dots{} 16)
2374 A 10-bit signed constant (@minus{}512 @dots{} 511)
2378 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2384 Floating point register
2387 Shift amount register
2390 Floating point register (deprecated)
2393 Upper floating point register (32-bit), floating point register (64-bit)
2399 Signed 11-bit integer constant
2402 Signed 14-bit integer constant
2405 Integer constant that can be deposited with a @code{zdepi} instruction
2408 Signed 5-bit integer constant
2414 Integer constant that can be loaded with a @code{ldil} instruction
2417 Integer constant whose value plus one is a power of 2
2420 Integer constant that can be used for @code{and} operations in @code{depi}
2421 and @code{extru} instructions
2430 Floating-point constant 0.0
2433 A @code{lo_sum} data-linkage-table memory operand
2436 A memory operand that can be used as the destination operand of an
2437 integer store instruction
2440 A scaled or unscaled indexed memory operand
2443 A memory operand for floating-point loads and stores
2446 A register indirect memory operand
2449 @item Intel IA-64---@file{config/ia64/ia64.h}
2452 General register @code{r0} to @code{r3} for @code{addl} instruction
2458 Predicate register (@samp{c} as in ``conditional'')
2461 Application register residing in M-unit
2464 Application register residing in I-unit
2467 Floating-point register
2470 Memory operand. If used together with @samp{<} or @samp{>},
2471 the operand can have postincrement and postdecrement which
2472 require printing with @samp{%Pn} on IA-64.
2475 Floating-point constant 0.0 or 1.0
2478 14-bit signed integer constant
2481 22-bit signed integer constant
2484 8-bit signed integer constant for logical instructions
2487 8-bit adjusted signed integer constant for compare pseudo-ops
2490 6-bit unsigned integer constant for shift counts
2493 9-bit signed integer constant for load and store postincrements
2499 0 or @minus{}1 for @code{dep} instruction
2502 Non-volatile memory for floating-point loads and stores
2505 Integer constant in the range 1 to 4 for @code{shladd} instruction
2508 Memory operand except postincrement and postdecrement. This is
2509 now roughly the same as @samp{m} when not used together with @samp{<}
2513 @item M32C---@file{config/m32c/m32c.c}
2518 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2521 Any control register, when they're 16 bits wide (nothing if control
2522 registers are 24 bits wide)
2525 Any control register, when they're 24 bits wide.
2534 $r0 or $r2, or $r2r0 for 32 bit values.
2537 $r1 or $r3, or $r3r1 for 32 bit values.
2540 A register that can hold a 64 bit value.
2543 $r0 or $r1 (registers with addressable high/low bytes)
2552 Address registers when they're 16 bits wide.
2555 Address registers when they're 24 bits wide.
2558 Registers that can hold QI values.
2561 Registers that can be used with displacements ($a0, $a1, $sb).
2564 Registers that can hold 32 bit values.
2567 Registers that can hold 16 bit values.
2570 Registers chat can hold 16 bit values, including all control
2574 $r0 through R1, plus $a0 and $a1.
2580 The memory-based pseudo-registers $mem0 through $mem15.
2583 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2584 bit registers for m32cm, m32c).
2587 Matches multiple registers in a PARALLEL to form a larger register.
2588 Used to match function return values.
2594 @minus{}128 @dots{} 127
2597 @minus{}32768 @dots{} 32767
2603 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2606 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2609 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2612 @minus{}65536 @dots{} @minus{}1
2615 An 8 bit value with exactly one bit set.
2618 A 16 bit value with exactly one bit set.
2621 The common src/dest memory addressing modes.
2624 Memory addressed using $a0 or $a1.
2627 Memory addressed with immediate addresses.
2630 Memory addressed using the stack pointer ($sp).
2633 Memory addressed using the frame base register ($fb).
2636 Memory addressed using the small base register ($sb).
2642 @item MicroBlaze---@file{config/microblaze/constraints.md}
2645 A general register (@code{r0} to @code{r31}).
2648 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2652 @item MIPS---@file{config/mips/constraints.md}
2655 A general-purpose register. This is equivalent to @code{r} unless
2656 generating MIPS16 code, in which case the MIPS16 register set is used.
2659 A floating-point register (if available).
2662 Formerly the @code{hi} register. This constraint is no longer supported.
2665 The @code{lo} register. Use this register to store values that are
2666 no bigger than a word.
2669 The concatenated @code{hi} and @code{lo} registers. Use this register
2670 to store doubleword values.
2673 A register suitable for use in an indirect jump. This will always be
2674 @code{$25} for @option{-mabicalls}.
2677 Register @code{$3}. Do not use this constraint in new code;
2678 it is retained only for compatibility with glibc.
2681 Equivalent to @code{r}; retained for backwards compatibility.
2684 A floating-point condition code register.
2687 A signed 16-bit constant (for arithmetic instructions).
2693 An unsigned 16-bit constant (for logic instructions).
2696 A signed 32-bit constant in which the lower 16 bits are zero.
2697 Such constants can be loaded using @code{lui}.
2700 A constant that cannot be loaded using @code{lui}, @code{addiu}
2704 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2707 A signed 15-bit constant.
2710 A constant in the range 1 to 65535 (inclusive).
2713 Floating-point zero.
2716 An address that can be used in a non-macro load or store.
2719 A memory operand whose address is formed by a base register and offset
2720 that is suitable for use in instructions with the same addressing mode
2721 as @code{ll} and @code{sc}.
2724 An address suitable for a @code{prefetch} instruction, or for any other
2725 instruction with the same addressing mode as @code{prefetch}.
2728 @item Motorola 680x0---@file{config/m68k/constraints.md}
2737 68881 floating-point register, if available
2740 Integer in the range 1 to 8
2743 16-bit signed number
2746 Signed number whose magnitude is greater than 0x80
2749 Integer in the range @minus{}8 to @minus{}1
2752 Signed number whose magnitude is greater than 0x100
2755 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2758 16 (for rotate using swap)
2761 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2764 Numbers that mov3q can handle
2767 Floating point constant that is not a 68881 constant
2770 Operands that satisfy 'm' when -mpcrel is in effect
2773 Operands that satisfy 's' when -mpcrel is not in effect
2776 Address register indirect addressing mode
2779 Register offset addressing
2794 Range of signed numbers that don't fit in 16 bits
2797 Integers valid for mvq
2800 Integers valid for a moveq followed by a swap
2803 Integers valid for mvz
2806 Integers valid for mvs
2812 Non-register operands allowed in clr
2816 @item Moxie---@file{config/moxie/constraints.md}
2825 A register indirect memory operand
2828 A constant in the range of 0 to 255.
2831 A constant in the range of 0 to @minus{}255.
2835 @item MSP430--@file{config/msp430/constraints.md}
2848 Integer constant -1^20..1^19.
2851 Integer constant 1-4.
2854 Memory references which do not require an extended MOVX instruction.
2857 Memory reference, labels only.
2860 Memory reference, stack only.
2864 @item NDS32---@file{config/nds32/constraints.md}
2867 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
2869 LOW register class $r0 to $r7.
2871 MIDDLE register class $r0 to $r11, $r16 to $r19.
2873 HIGH register class $r12 to $r14, $r20 to $r31.
2875 Temporary assist register $ta (i.e.@: $r15).
2879 Unsigned immediate 3-bit value.
2881 Negative immediate 3-bit value in the range of @minus{}7--0.
2883 Unsigned immediate 4-bit value.
2885 Signed immediate 5-bit value.
2887 Unsigned immediate 5-bit value.
2889 Negative immediate 5-bit value in the range of @minus{}31--0.
2891 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
2893 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
2895 Unsigned immediate 8-bit value.
2897 Unsigned immediate 9-bit value.
2899 Signed immediate 10-bit value.
2901 Signed immediate 11-bit value.
2903 Signed immediate 15-bit value.
2905 Unsigned immediate 15-bit value.
2907 A constant which is not in the range of imm15u but ok for bclr instruction.
2909 A constant which is not in the range of imm15u but ok for bset instruction.
2911 A constant which is not in the range of imm15u but ok for btgl instruction.
2913 A constant whose compliment value is in the range of imm15u
2914 and ok for bitci instruction.
2916 Signed immediate 16-bit value.
2918 Signed immediate 17-bit value.
2920 Signed immediate 19-bit value.
2922 Signed immediate 20-bit value.
2924 The immediate value that can be simply set high 20-bit.
2926 The immediate value 0xff.
2928 The immediate value 0xffff.
2930 The immediate value 0x01.
2932 The immediate value 0x7ff.
2934 The immediate value with power of 2.
2936 The immediate value with power of 2 minus 1.
2938 Memory constraint for 333 format.
2940 Memory constraint for 45 format.
2942 Memory constraint for 37 format.
2945 @item Nios II family---@file{config/nios2/constraints.md}
2949 Integer that is valid as an immediate operand in an
2950 instruction taking a signed 16-bit number. Range
2951 @minus{}32768 to 32767.
2954 Integer that is valid as an immediate operand in an
2955 instruction taking an unsigned 16-bit number. Range
2959 Integer that is valid as an immediate operand in an
2960 instruction taking only the upper 16-bits of a
2961 32-bit number. Range 32-bit numbers with the lower
2965 Integer that is valid as an immediate operand for a
2966 shift instruction. Range 0 to 31.
2969 Integer that is valid as an immediate operand for
2970 only the value 0. Can be used in conjunction with
2971 the format modifier @code{z} to use @code{r0}
2972 instead of @code{0} in the assembly output.
2975 Integer that is valid as an immediate operand for
2976 a custom instruction opcode. Range 0 to 255.
2979 An immediate operand for R2 andchi/andci instructions.
2982 Matches immediates which are addresses in the small
2983 data section and therefore can be added to @code{gp}
2984 as a 16-bit immediate to re-create their 32-bit value.
2987 Matches constants suitable as an operand for the rdprs and
2991 A memory operand suitable for Nios II R2 load/store
2992 exclusive instructions.
2995 A memory operand suitable for load/store IO and cache
3000 A @code{const} wrapped @code{UNSPEC} expression,
3001 representing a supported PIC or TLS relocation.
3006 @item OpenRISC---@file{config/or1k/constraints.md}
3009 Integer that is valid as an immediate operand in an
3010 instruction taking a signed 16-bit number. Range
3011 @minus{}32768 to 32767.
3014 Integer that is valid as an immediate operand in an
3015 instruction taking an unsigned 16-bit number. Range
3019 Signed 16-bit constant shifted left 16 bits. (Used with @code{l.movhi})
3026 Register usable for sibcalls.
3031 @item PDP-11---@file{config/pdp11/constraints.md}
3034 Floating point registers AC0 through AC3. These can be loaded from/to
3035 memory with a single instruction.
3038 Odd numbered general registers (R1, R3, R5). These are used for
3039 16-bit multiply operations.
3042 A memory reference that is encoded within the opcode, but not
3043 auto-increment or auto-decrement.
3046 Any of the floating point registers (AC0 through AC5).
3049 Floating point constant 0.
3052 Floating point registers AC4 and AC5. These cannot be loaded from/to
3053 memory with a single instruction.
3056 An integer constant that fits in 16 bits.
3059 An integer constant whose low order 16 bits are zero.
3062 An integer constant that does not meet the constraints for codes
3063 @samp{I} or @samp{J}.
3066 The integer constant 1.
3069 The integer constant @minus{}1.
3072 The integer constant 0.
3075 Integer constants 0 through 3; shifts by these
3076 amounts are handled as multiple single-bit shifts rather than a single
3077 variable-length shift.
3080 A memory reference which requires an additional word (address or
3081 offset) after the opcode.
3084 A memory reference that is encoded within the opcode.
3088 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
3091 Address base register
3094 Floating point register (containing 64-bit value)
3097 Floating point register (containing 32-bit value)
3100 Altivec vector register
3103 Any VSX register if the @option{-mvsx} option was used or NO_REGS.
3105 When using any of the register constraints (@code{wa}, @code{wd},
3106 @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
3107 @code{wl}, @code{wm}, @code{wo}, @code{wp}, @code{wq}, @code{ws},
3108 @code{wt}, @code{wu}, @code{wv}, @code{ww}, or @code{wy})
3109 that take VSX registers, you must use @code{%x<n>} in the template so
3110 that the correct register is used. Otherwise the register number
3111 output in the assembly file will be incorrect if an Altivec register
3112 is an operand of a VSX instruction that expects VSX register
3116 asm ("xvadddp %x0,%x1,%x2"
3118 : "wa" (v2), "wa" (v3));
3125 asm ("xvadddp %0,%1,%2"
3127 : "wa" (v2), "wa" (v3));
3133 If an instruction only takes Altivec registers, you do not want to use
3137 asm ("xsaddqp %0,%1,%2"
3139 : "v" (v2), "v" (v3));
3143 is correct because the @code{xsaddqp} instruction only takes Altivec
3147 asm ("xsaddqp %x0,%x1,%x2"
3149 : "v" (v2), "v" (v3));
3156 Altivec register if @option{-mcpu=power9} is used or NO_REGS.
3159 VSX vector register to hold vector double data or NO_REGS.
3162 VSX register if the @option{-mcpu=power9} and @option{-m64} options
3163 were used or NO_REGS.
3166 VSX vector register to hold vector float data or NO_REGS.
3169 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
3172 Floating point register if direct moves are available, or NO_REGS.
3175 FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
3178 FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
3181 FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
3184 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
3187 VSX register if direct move instructions are enabled, or NO_REGS.
3190 No register (NO_REGS).
3193 VSX register to use for ISA 3.0 vector instructions, or NO_REGS.
3196 VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS.
3199 VSX register to use for IEEE 128-bit floating point, or NO_REGS.
3202 General purpose register if 64-bit instructions are enabled or NO_REGS.
3205 VSX vector register to hold scalar double values or NO_REGS.
3208 VSX vector register to hold 128 bit integer or NO_REGS.
3211 Altivec register to use for float/32-bit int loads/stores or NO_REGS.
3214 Altivec register to use for double loads/stores or NO_REGS.
3217 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
3220 Floating point register if the STFIWX instruction is enabled or NO_REGS.
3223 FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
3226 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
3229 Address base register if 64-bit instructions are enabled or NO_REGS.
3232 Signed 5-bit constant integer that can be loaded into an altivec register.
3235 Int constant that is the element number of the 64-bit scalar in a vector.
3238 Vector constant that can be loaded with the XXSPLTIB instruction.
3241 Memory operand suitable for power9 fusion load/stores.
3244 Memory operand suitable for TOC fusion memory references.
3247 Altivec register if @option{-mvsx-small-integer}.
3250 Floating point register if @option{-mvsx-small-integer}.
3253 FP register if @option{-mvsx-small-integer} and @option{-mpower9-vector}.
3256 Altivec register if @option{-mvsx-small-integer} and @option{-mpower9-vector}.
3259 Int constant that is the element number that the MFVSRLD instruction.
3263 Match vector constant with all 1's if the XXLORC instruction is available.
3266 A memory operand suitable for the ISA 3.0 vector d-form instructions.
3269 A memory address that will work with the @code{lq} and @code{stq}
3273 Vector constant that can be loaded with XXSPLTIB & sign extension.
3276 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
3282 @samp{LINK} register
3285 @samp{CR} register (condition register) number 0
3288 @samp{CR} register (condition register)
3291 @samp{XER[CA]} carry bit (part of the XER register)
3294 Signed 16-bit constant
3297 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
3298 @code{SImode} constants)
3301 Unsigned 16-bit constant
3304 Signed 16-bit constant shifted left 16 bits
3307 Constant larger than 31
3316 Constant whose negation is a signed 16-bit constant
3319 Floating point constant that can be loaded into a register with one
3320 instruction per word
3323 Integer/Floating point constant that can be loaded into a register using
3328 Normally, @code{m} does not allow addresses that update the base register.
3329 If @samp{<} or @samp{>} constraint is also used, they are allowed and
3330 therefore on PowerPC targets in that case it is only safe
3331 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
3332 accesses the operand exactly once. The @code{asm} statement must also
3333 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
3334 corresponding load or store instruction. For example:
3337 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
3343 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
3349 A ``stable'' memory operand; that is, one which does not include any
3350 automodification of the base register. This used to be useful when
3351 @samp{m} allowed automodification of the base register, but as those are now only
3352 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
3353 as @samp{m} without @samp{<} and @samp{>}.
3356 Memory operand that is an offset from a register (it is usually better
3357 to use @samp{m} or @samp{es} in @code{asm} statements)
3360 Memory operand that is an indexed or indirect from a register (it is
3361 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
3367 Address operand that is an indexed or indirect from a register (@samp{p} is
3368 preferable for @code{asm} statements)
3371 System V Release 4 small data area reference
3374 Vector constant that does not require memory
3377 Vector constant that is all zeros.
3381 @item RL78---@file{config/rl78/constraints.md}
3385 An integer constant in the range 1 @dots{} 7.
3387 An integer constant in the range 0 @dots{} 255.
3389 An integer constant in the range @minus{}255 @dots{} 0
3391 The integer constant 1.
3393 The integer constant -1.
3395 The integer constant 0.
3397 The integer constant 2.
3399 The integer constant -2.
3401 An integer constant in the range 1 @dots{} 15.
3403 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3405 The synthetic compare types--gt, lt, ge, and le.
3407 A memory reference with an absolute address.
3409 A memory reference using @code{BC} as a base register, with an optional offset.
3411 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3413 A memory reference using any 16-bit register pair for the address, for calls.
3415 A memory reference using @code{DE} as a base register, with an optional offset.
3417 A memory reference using @code{DE} as a base register, without any offset.
3419 Any memory reference to an address in the far address space.
3421 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3423 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3425 A memory reference using @code{HL} as a base register, without any offset.
3427 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3429 Any memory reference to an address in the near address space.
3431 The @code{AX} register.
3433 The @code{BC} register.
3435 The @code{DE} register.
3437 @code{A} through @code{L} registers.
3439 The @code{SP} register.
3441 The @code{HL} register.
3443 The 16-bit @code{R8} register.
3445 The 16-bit @code{R10} register.
3447 The registers reserved for interrupts (@code{R24} to @code{R31}).
3449 The @code{A} register.
3451 The @code{B} register.
3453 The @code{C} register.
3455 The @code{D} register.
3457 The @code{E} register.
3459 The @code{H} register.
3461 The @code{L} register.
3463 The virtual registers.
3465 The @code{PSW} register.
3467 The @code{X} register.
3471 @item RISC-V---@file{config/riscv/constraints.md}
3475 A floating-point register (if availiable).
3478 An I-type 12-bit signed immediate.
3484 A 5-bit unsigned immediate for CSR access instructions.
3487 An address that is held in a general-purpose register.
3491 @item RX---@file{config/rx/constraints.md}
3494 An address which does not involve register indirect addressing or
3495 pre/post increment/decrement addressing.
3501 A constant in the range @minus{}256 to 255, inclusive.
3504 A constant in the range @minus{}128 to 127, inclusive.
3507 A constant in the range @minus{}32768 to 32767, inclusive.
3510 A constant in the range @minus{}8388608 to 8388607, inclusive.
3513 A constant in the range 0 to 15, inclusive.
3517 @item S/390 and zSeries---@file{config/s390/s390.h}
3520 Address register (general purpose register except r0)
3523 Condition code register
3526 Data register (arbitrary general purpose register)
3529 Floating-point register
3532 Unsigned 8-bit constant (0--255)
3535 Unsigned 12-bit constant (0--4095)
3538 Signed 16-bit constant (@minus{}32768--32767)
3541 Value appropriate as displacement.
3544 for short displacement
3545 @item (@minus{}524288..524287)
3546 for long displacement
3550 Constant integer with a value of 0x7fffffff.
3553 Multiple letter constraint followed by 4 parameter letters.
3556 number of the part counting from most to least significant
3560 mode of the containing operand
3562 value of the other parts (F---all bits set)
3564 The constraint matches if the specified part of a constant
3565 has a value different from its other parts.
3568 Memory reference without index register and with short displacement.
3571 Memory reference with index register and short displacement.
3574 Memory reference without index register but with long displacement.
3577 Memory reference with index register and long displacement.
3580 Pointer with short displacement.
3583 Pointer with long displacement.
3586 Shift count operand.
3591 @item SPARC---@file{config/sparc/sparc.h}
3594 Floating-point register on the SPARC-V8 architecture and
3595 lower floating-point register on the SPARC-V9 architecture.
3598 Floating-point register. It is equivalent to @samp{f} on the
3599 SPARC-V8 architecture and contains both lower and upper
3600 floating-point registers on the SPARC-V9 architecture.
3603 Floating-point condition code register.
3606 Lower floating-point register. It is only valid on the SPARC-V9
3607 architecture when the Visual Instruction Set is available.
3610 Floating-point register. It is only valid on the SPARC-V9 architecture
3611 when the Visual Instruction Set is available.
3614 64-bit global or out register for the SPARC-V8+ architecture.
3617 The constant all-ones, for floating-point.
3620 Signed 5-bit constant
3626 Signed 13-bit constant
3632 32-bit constant with the low 12 bits clear (a constant that can be
3633 loaded with the @code{sethi} instruction)
3636 A constant in the range supported by @code{movcc} instructions (11-bit
3640 A constant in the range supported by @code{movrcc} instructions (10-bit
3644 Same as @samp{K}, except that it verifies that bits that are not in the
3645 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3646 modes wider than @code{SImode}
3655 Signed 13-bit constant, sign-extended to 32 or 64 bits
3661 Floating-point constant whose integral representation can
3662 be moved into an integer register using a single sethi
3666 Floating-point constant whose integral representation can
3667 be moved into an integer register using a single mov
3671 Floating-point constant whose integral representation can
3672 be moved into an integer register using a high/lo_sum
3673 instruction sequence
3676 Memory address aligned to an 8-byte boundary
3682 Memory address for @samp{e} constraint registers
3685 Memory address with only a base register
3692 @item SPU---@file{config/spu/spu.h}
3695 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3698 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3701 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3704 An immediate which can be loaded with @code{fsmbi}.
3707 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3710 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3713 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3716 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3719 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3722 An unsigned 7-bit constant for conversion/nop/channel instructions.
3725 A signed 10-bit constant for most arithmetic instructions.
3728 A signed 16 bit immediate for @code{stop}.
3731 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3734 An unsigned 7-bit constant whose 3 least significant bits are 0.
3737 An unsigned 3-bit constant for 16-byte rotates and shifts
3740 Call operand, reg, for indirect calls
3743 Call operand, symbol, for relative calls.
3746 Call operand, const_int, for absolute calls.
3749 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3752 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3755 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3758 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3762 @item TI C6X family---@file{config/c6x/constraints.md}
3765 Register file A (A0--A31).
3768 Register file B (B0--B31).
3771 Predicate registers in register file A (A0--A2 on C64X and
3772 higher, A1 and A2 otherwise).
3775 Predicate registers in register file B (B0--B2).
3778 A call-used register in register file B (B0--B9, B16--B31).
3781 Register file A, excluding predicate registers (A3--A31,
3782 plus A0 if not C64X or higher).
3785 Register file B, excluding predicate registers (B3--B31).
3788 Integer constant in the range 0 @dots{} 15.
3791 Integer constant in the range 0 @dots{} 31.
3794 Integer constant in the range @minus{}31 @dots{} 0.
3797 Integer constant in the range @minus{}16 @dots{} 15.
3800 Integer constant that can be the operand of an ADDA or a SUBA insn.
3803 Integer constant in the range 0 @dots{} 65535.
3806 Integer constant in the range @minus{}32768 @dots{} 32767.
3809 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3812 Integer constant that is a valid mask for the clr instruction.
3815 Integer constant that is a valid mask for the set instruction.
3818 Memory location with A base register.
3821 Memory location with B base register.
3825 On C64x+ targets, a GP-relative small data reference.
3828 Any kind of @code{SYMBOL_REF}, for use in a call address.
3831 Any kind of immediate operand, unless it matches the S0 constraint.
3834 Memory location with B base register, but not using a long offset.
3837 A memory operand with an address that cannot be used in an unaligned access.
3841 Register B14 (aka DP).
3845 @item TILE-Gx---@file{config/tilegx/constraints.md}
3858 Each of these represents a register constraint for an individual
3859 register, from r0 to r10.
3862 Signed 8-bit integer constant.
3865 Signed 16-bit integer constant.
3868 Unsigned 16-bit integer constant.
3871 Integer constant that fits in one signed byte when incremented by one
3872 (@minus{}129 @dots{} 126).
3875 Memory operand. If used together with @samp{<} or @samp{>}, the
3876 operand can have postincrement which requires printing with @samp{%In}
3877 and @samp{%in} on TILE-Gx. For example:
3880 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3884 A bit mask suitable for the BFINS instruction.
3887 Integer constant that is a byte tiled out eight times.
3890 The integer zero constant.
3893 Integer constant that is a sign-extended byte tiled out as four shorts.
3896 Integer constant that fits in one signed byte when incremented
3897 (@minus{}129 @dots{} 126), but excluding -1.
3900 Integer constant that has all 1 bits consecutive and starting at bit 0.
3903 A 16-bit fragment of a got, tls, or pc-relative reference.
3906 Memory operand except postincrement. This is roughly the same as
3907 @samp{m} when not used together with @samp{<} or @samp{>}.
3910 An 8-element vector constant with identical elements.
3913 A 4-element vector constant with identical elements.
3916 The integer constant 0xffffffff.
3919 The integer constant 0xffffffff00000000.
3923 @item TILEPro---@file{config/tilepro/constraints.md}
3936 Each of these represents a register constraint for an individual
3937 register, from r0 to r10.
3940 Signed 8-bit integer constant.
3943 Signed 16-bit integer constant.
3946 Nonzero integer constant with low 16 bits zero.
3949 Integer constant that fits in one signed byte when incremented by one
3950 (@minus{}129 @dots{} 126).
3953 Memory operand. If used together with @samp{<} or @samp{>}, the
3954 operand can have postincrement which requires printing with @samp{%In}
3955 and @samp{%in} on TILEPro. For example:
3958 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
3962 A bit mask suitable for the MM instruction.
3965 Integer constant that is a byte tiled out four times.
3968 The integer zero constant.
3971 Integer constant that is a sign-extended byte tiled out as two shorts.
3974 Integer constant that fits in one signed byte when incremented
3975 (@minus{}129 @dots{} 126), but excluding -1.
3978 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
3982 Memory operand except postincrement. This is roughly the same as
3983 @samp{m} when not used together with @samp{<} or @samp{>}.
3986 A 4-element vector constant with identical elements.
3989 A 2-element vector constant with identical elements.
3993 @item Visium---@file{config/visium/constraints.md}
3996 EAM register @code{mdb}
3999 EAM register @code{mdc}
4002 Floating point register
4006 Register for sibcall optimization
4010 General register, but not @code{r29}, @code{r30} and @code{r31}
4022 Floating-point constant 0.0
4025 Integer constant in the range 0 .. 65535 (16-bit immediate)
4028 Integer constant in the range 1 .. 31 (5-bit immediate)
4031 Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
4034 Integer constant @minus{}1
4043 @item x86 family---@file{config/i386/constraints.md}
4046 Legacy register---the eight integer registers available on all
4047 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
4048 @code{si}, @code{di}, @code{bp}, @code{sp}).
4051 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
4052 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
4055 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
4056 @code{c}, and @code{d}.
4060 Any register that can be used as the index in a base+index memory
4061 access: that is, any general register except the stack pointer.
4065 The @code{a} register.
4068 The @code{b} register.
4071 The @code{c} register.
4074 The @code{d} register.
4077 The @code{si} register.
4080 The @code{di} register.
4083 The @code{a} and @code{d} registers. This class is used for instructions
4084 that return double word results in the @code{ax:dx} register pair. Single
4085 word values will be allocated either in @code{ax} or @code{dx}.
4086 For example on i386 the following implements @code{rdtsc}:
4089 unsigned long long rdtsc (void)
4091 unsigned long long tick;
4092 __asm__ __volatile__("rdtsc":"=A"(tick));
4097 This is not correct on x86-64 as it would allocate tick in either @code{ax}
4098 or @code{dx}. You have to use the following variant instead:
4101 unsigned long long rdtsc (void)
4103 unsigned int tickl, tickh;
4104 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
4105 return ((unsigned long long)tickh << 32)|tickl;
4110 The call-clobbered integer registers.
4113 Any 80387 floating-point (stack) register.
4116 Top of 80387 floating-point stack (@code{%st(0)}).
4119 Second from top of 80387 floating-point stack (@code{%st(1)}).
4123 Any mask register that can be used as a predicate, i.e.@: @code{k1-k7}.
4136 Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).
4144 First SSE register (@code{%xmm0}).
4148 Any SSE register, when SSE2 and inter-unit moves are enabled.
4151 Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.
4154 Any MMX register, when inter-unit moves are enabled.
4157 Any MMX register, when inter-unit moves from vector registers are enabled.
4160 Any integer register when @code{TARGET_PARTIAL_REG_STALL} is disabled.
4163 Any integer register when zero extensions with @code{AND} are disabled.
4166 Any register that can be used as the GOT base when calling@*
4167 @code{___tls_get_addr}: that is, any general register except @code{a}
4168 and @code{sp} registers, for @option{-fno-plt} if linker supports it.
4169 Otherwise, @code{b} register.
4172 Any x87 register when 80387 floating-point arithmetic is enabled.
4175 Lower SSE register when avoiding REX prefix and all SSE registers otherwise.
4178 For AVX512VL, any EVEX-encodable SSE register (@code{%xmm0-%xmm31}),
4179 otherwise any SSE register.
4182 Any EVEX-encodable SSE register, that has number factor of four.
4185 Flags register operand.
4191 Vector memory operand.
4194 Constant memory operand.
4197 Memory operand without REX prefix.
4200 Sibcall memory operand.
4203 Call memory operand.
4206 Constant call address operand.
4209 SSE constant -1 operand.
4213 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
4216 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
4219 Signed 8-bit integer constant.
4222 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
4225 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
4228 Unsigned 8-bit integer constant (for @code{in} and @code{out}
4233 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
4237 Standard 80387 floating point constant.
4240 SSE constant zero operand.
4243 32-bit signed integer constant, or a symbolic reference known
4244 to fit that range (for immediate operands in sign-extending x86-64
4248 32-bit signed integer constant, or a symbolic reference known
4249 to fit that range (for sign-extending conversion operations that
4250 require non-@code{VOIDmode} immediate operands).
4253 32-bit unsigned integer constant, or a symbolic reference known
4254 to fit that range (for zero-extending conversion operations that
4255 require non-@code{VOIDmode} immediate operands).
4258 128-bit integer constant where both the high and low 64-bit word
4259 satisfy the @code{e} constraint.
4262 32-bit unsigned integer constant, or a symbolic reference known
4263 to fit that range (for immediate operands in zero-extending x86-64
4267 VSIB address operand.
4270 Address operand without segment register.
4274 @item Xstormy16---@file{config/stormy16/stormy16.h}
4289 Registers r0 through r7.
4292 Registers r0 and r1.
4298 Registers r8 and r9.
4301 A constant between 0 and 3 inclusive.
4304 A constant that has exactly one bit set.
4307 A constant that has exactly one bit clear.
4310 A constant between 0 and 255 inclusive.
4313 A constant between @minus{}255 and 0 inclusive.
4316 A constant between @minus{}3 and 0 inclusive.
4319 A constant between 1 and 4 inclusive.
4322 A constant between @minus{}4 and @minus{}1 inclusive.
4325 A memory reference that is a stack push.
4328 A memory reference that is a stack pop.
4331 A memory reference that refers to a constant address of known value.
4334 The register indicated by Rx (not implemented yet).
4337 A constant that is not between 2 and 15 inclusive.
4344 @item Xtensa---@file{config/xtensa/constraints.md}
4347 General-purpose 32-bit register
4350 One-bit boolean register
4353 MAC16 40-bit accumulator register
4356 Signed 12-bit integer constant, for use in MOVI instructions
4359 Signed 8-bit integer constant, for use in ADDI instructions
4362 Integer constant valid for BccI instructions
4365 Unsigned constant valid for BccUI instructions
4372 @node Disable Insn Alternatives
4373 @subsection Disable insn alternatives using the @code{enabled} attribute
4376 There are three insn attributes that may be used to selectively disable
4377 instruction alternatives:
4381 Says whether an alternative is available on the current subtarget.
4383 @item preferred_for_size
4384 Says whether an enabled alternative should be used in code that is
4387 @item preferred_for_speed
4388 Says whether an enabled alternative should be used in code that is
4389 optimized for speed.
4392 All these attributes should use @code{(const_int 1)} to allow an alternative
4393 or @code{(const_int 0)} to disallow it. The attributes must be a static
4394 property of the subtarget; they cannot for example depend on the
4395 current operands, on the current optimization level, on the location
4396 of the insn within the body of a loop, on whether register allocation
4397 has finished, or on the current compiler pass.
4399 The @code{enabled} attribute is a correctness property. It tells GCC to act
4400 as though the disabled alternatives were never defined in the first place.
4401 This is useful when adding new instructions to an existing pattern in
4402 cases where the new instructions are only available for certain cpu
4403 architecture levels (typically mapped to the @code{-march=} command-line
4406 In contrast, the @code{preferred_for_size} and @code{preferred_for_speed}
4407 attributes are strong optimization hints rather than correctness properties.
4408 @code{preferred_for_size} tells GCC which alternatives to consider when
4409 adding or modifying an instruction that GCC wants to optimize for size.
4410 @code{preferred_for_speed} does the same thing for speed. Note that things
4411 like code motion can lead to cases where code optimized for size uses
4412 alternatives that are not preferred for size, and similarly for speed.
4414 Although @code{define_insn}s can in principle specify the @code{enabled}
4415 attribute directly, it is often clearer to have subsiduary attributes
4416 for each architectural feature of interest. The @code{define_insn}s
4417 can then use these subsiduary attributes to say which alternatives
4418 require which features. The example below does this for @code{cpu_facility}.
4420 E.g. the following two patterns could easily be merged using the @code{enabled}
4425 (define_insn "*movdi_old"
4426 [(set (match_operand:DI 0 "register_operand" "=d")
4427 (match_operand:DI 1 "register_operand" " d"))]
4431 (define_insn "*movdi_new"
4432 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4433 (match_operand:DI 1 "register_operand" " d,d,f"))]
4446 (define_insn "*movdi_combined"
4447 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4448 (match_operand:DI 1 "register_operand" " d,d,f"))]
4454 [(set_attr "cpu_facility" "*,new,new")])
4458 with the @code{enabled} attribute defined like this:
4462 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4464 (define_attr "enabled" ""
4465 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4466 (and (eq_attr "cpu_facility" "new")
4467 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4476 @node Define Constraints
4477 @subsection Defining Machine-Specific Constraints
4478 @cindex defining constraints
4479 @cindex constraints, defining
4481 Machine-specific constraints fall into two categories: register and
4482 non-register constraints. Within the latter category, constraints
4483 which allow subsets of all possible memory or address operands should
4484 be specially marked, to give @code{reload} more information.
4486 Machine-specific constraints can be given names of arbitrary length,
4487 but they must be entirely composed of letters, digits, underscores
4488 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4489 must begin with a letter or underscore.
4491 In order to avoid ambiguity in operand constraint strings, no
4492 constraint can have a name that begins with any other constraint's
4493 name. For example, if @code{x} is defined as a constraint name,
4494 @code{xy} may not be, and vice versa. As a consequence of this rule,
4495 no constraint may begin with one of the generic constraint letters:
4496 @samp{E F V X g i m n o p r s}.
4498 Register constraints correspond directly to register classes.
4499 @xref{Register Classes}. There is thus not much flexibility in their
4502 @deffn {MD Expression} define_register_constraint name regclass docstring
4503 All three arguments are string constants.
4504 @var{name} is the name of the constraint, as it will appear in
4505 @code{match_operand} expressions. If @var{name} is a multi-letter
4506 constraint its length shall be the same for all constraints starting
4507 with the same letter. @var{regclass} can be either the
4508 name of the corresponding register class (@pxref{Register Classes}),
4509 or a C expression which evaluates to the appropriate register class.
4510 If it is an expression, it must have no side effects, and it cannot
4511 look at the operand. The usual use of expressions is to map some
4512 register constraints to @code{NO_REGS} when the register class
4513 is not available on a given subarchitecture.
4515 @var{docstring} is a sentence documenting the meaning of the
4516 constraint. Docstrings are explained further below.
4519 Non-register constraints are more like predicates: the constraint
4520 definition gives a boolean expression which indicates whether the
4523 @deffn {MD Expression} define_constraint name docstring exp
4524 The @var{name} and @var{docstring} arguments are the same as for
4525 @code{define_register_constraint}, but note that the docstring comes
4526 immediately after the name for these expressions. @var{exp} is an RTL
4527 expression, obeying the same rules as the RTL expressions in predicate
4528 definitions. @xref{Defining Predicates}, for details. If it
4529 evaluates true, the constraint matches; if it evaluates false, it
4530 doesn't. Constraint expressions should indicate which RTL codes they
4531 might match, just like predicate expressions.
4533 @code{match_test} C expressions have access to the
4534 following variables:
4538 The RTL object defining the operand.
4540 The machine mode of @var{op}.
4542 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4544 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4545 @code{const_double}.
4547 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4548 @code{const_double}.
4550 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4551 @code{const_double}.
4554 The @var{*val} variables should only be used once another piece of the
4555 expression has verified that @var{op} is the appropriate kind of RTL
4559 Most non-register constraints should be defined with
4560 @code{define_constraint}. The remaining two definition expressions
4561 are only appropriate for constraints that should be handled specially
4562 by @code{reload} if they fail to match.
4564 @deffn {MD Expression} define_memory_constraint name docstring exp
4565 Use this expression for constraints that match a subset of all memory
4566 operands: that is, @code{reload} can make them match by converting the
4567 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4568 base register (from the register class specified by
4569 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4571 For example, on the S/390, some instructions do not accept arbitrary
4572 memory references, but only those that do not make use of an index
4573 register. The constraint letter @samp{Q} is defined to represent a
4574 memory address of this type. If @samp{Q} is defined with
4575 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4576 memory operand, because @code{reload} knows it can simply copy the
4577 memory address into a base register if required. This is analogous to
4578 the way an @samp{o} constraint can handle any memory operand.
4580 The syntax and semantics are otherwise identical to
4581 @code{define_constraint}.
4584 @deffn {MD Expression} define_special_memory_constraint name docstring exp
4585 Use this expression for constraints that match a subset of all memory
4586 operands: that is, @code{reload} can not make them match by reloading
4587 the address as it is described for @code{define_memory_constraint} or
4588 such address reload is undesirable with the performance point of view.
4590 For example, @code{define_special_memory_constraint} can be useful if
4591 specifically aligned memory is necessary or desirable for some insn
4594 The syntax and semantics are otherwise identical to
4595 @code{define_constraint}.
4598 @deffn {MD Expression} define_address_constraint name docstring exp
4599 Use this expression for constraints that match a subset of all address
4600 operands: that is, @code{reload} can make the constraint match by
4601 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4602 with @var{X} a base register.
4604 Constraints defined with @code{define_address_constraint} can only be
4605 used with the @code{address_operand} predicate, or machine-specific
4606 predicates that work the same way. They are treated analogously to
4607 the generic @samp{p} constraint.
4609 The syntax and semantics are otherwise identical to
4610 @code{define_constraint}.
4613 For historical reasons, names beginning with the letters @samp{G H}
4614 are reserved for constraints that match only @code{const_double}s, and
4615 names beginning with the letters @samp{I J K L M N O P} are reserved
4616 for constraints that match only @code{const_int}s. This may change in
4617 the future. For the time being, constraints with these names must be
4618 written in a stylized form, so that @code{genpreds} can tell you did
4623 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4625 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4626 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4629 @c the semicolons line up in the formatted manual
4631 It is fine to use names beginning with other letters for constraints
4632 that match @code{const_double}s or @code{const_int}s.
4634 Each docstring in a constraint definition should be one or more complete
4635 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4636 In the future they will be copied into the GCC manual, in @ref{Machine
4637 Constraints}, replacing the hand-maintained tables currently found in
4638 that section. Also, in the future the compiler may use this to give
4639 more helpful diagnostics when poor choice of @code{asm} constraints
4640 causes a reload failure.
4642 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4643 beginning of a docstring, then (in the future) it will appear only in
4644 the internals manual's version of the machine-specific constraint tables.
4645 Use this for constraints that should not appear in @code{asm} statements.
4647 @node C Constraint Interface
4648 @subsection Testing constraints from C
4649 @cindex testing constraints
4650 @cindex constraints, testing
4652 It is occasionally useful to test a constraint from C code rather than
4653 implicitly via the constraint string in a @code{match_operand}. The
4654 generated file @file{tm_p.h} declares a few interfaces for working
4655 with constraints. At present these are defined for all constraints
4656 except @code{g} (which is equivalent to @code{general_operand}).
4658 Some valid constraint names are not valid C identifiers, so there is a
4659 mangling scheme for referring to them from C@. Constraint names that
4660 do not contain angle brackets or underscores are left unchanged.
4661 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4662 each @samp{>} with @samp{_g}. Here are some examples:
4664 @c the @c's prevent double blank lines in the printed manual.
4666 @multitable {Original} {Mangled}
4667 @item @strong{Original} @tab @strong{Mangled} @c
4668 @item @code{x} @tab @code{x} @c
4669 @item @code{P42x} @tab @code{P42x} @c
4670 @item @code{P4_x} @tab @code{P4__x} @c
4671 @item @code{P4>x} @tab @code{P4_gx} @c
4672 @item @code{P4>>} @tab @code{P4_g_g} @c
4673 @item @code{P4_g>} @tab @code{P4__g_g} @c
4677 Throughout this section, the variable @var{c} is either a constraint
4678 in the abstract sense, or a constant from @code{enum constraint_num};
4679 the variable @var{m} is a mangled constraint name (usually as part of
4680 a larger identifier).
4682 @deftp Enum constraint_num
4683 For each constraint except @code{g}, there is a corresponding
4684 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4685 constraint. Functions that take an @code{enum constraint_num} as an
4686 argument expect one of these constants.
4689 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4690 For each non-register constraint @var{m} except @code{g}, there is
4691 one of these functions; it returns @code{true} if @var{exp} satisfies the
4692 constraint. These functions are only visible if @file{rtl.h} was included
4693 before @file{tm_p.h}.
4696 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4697 Like the @code{satisfies_constraint_@var{m}} functions, but the
4698 constraint to test is given as an argument, @var{c}. If @var{c}
4699 specifies a register constraint, this function will always return
4703 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4704 Returns the register class associated with @var{c}. If @var{c} is not
4705 a register constraint, or those registers are not available for the
4706 currently selected subtarget, returns @code{NO_REGS}.
4709 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4710 peephole optimizations (@pxref{Peephole Definitions}), operand
4711 constraint strings are ignored, so if there are relevant constraints,
4712 they must be tested in the C condition. In the example, the
4713 optimization is applied if operand 2 does @emph{not} satisfy the
4714 @samp{K} constraint. (This is a simplified version of a peephole
4715 definition from the i386 machine description.)
4719 [(match_scratch:SI 3 "r")
4720 (set (match_operand:SI 0 "register_operand" "")
4721 (mult:SI (match_operand:SI 1 "memory_operand" "")
4722 (match_operand:SI 2 "immediate_operand" "")))]
4724 "!satisfies_constraint_K (operands[2])"
4726 [(set (match_dup 3) (match_dup 1))
4727 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4732 @node Standard Names
4733 @section Standard Pattern Names For Generation
4734 @cindex standard pattern names
4735 @cindex pattern names
4736 @cindex names, pattern
4738 Here is a table of the instruction names that are meaningful in the RTL
4739 generation pass of the compiler. Giving one of these names to an
4740 instruction pattern tells the RTL generation pass that it can use the
4741 pattern to accomplish a certain task.
4744 @cindex @code{mov@var{m}} instruction pattern
4745 @item @samp{mov@var{m}}
4746 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4747 This instruction pattern moves data with that machine mode from operand
4748 1 to operand 0. For example, @samp{movsi} moves full-word data.
4750 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4751 own mode is wider than @var{m}, the effect of this instruction is
4752 to store the specified value in the part of the register that corresponds
4753 to mode @var{m}. Bits outside of @var{m}, but which are within the
4754 same target word as the @code{subreg} are undefined. Bits which are
4755 outside the target word are left unchanged.
4757 This class of patterns is special in several ways. First of all, each
4758 of these names up to and including full word size @emph{must} be defined,
4759 because there is no other way to copy a datum from one place to another.
4760 If there are patterns accepting operands in larger modes,
4761 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4763 Second, these patterns are not used solely in the RTL generation pass.
4764 Even the reload pass can generate move insns to copy values from stack
4765 slots into temporary registers. When it does so, one of the operands is
4766 a hard register and the other is an operand that can need to be reloaded
4770 Therefore, when given such a pair of operands, the pattern must generate
4771 RTL which needs no reloading and needs no temporary registers---no
4772 registers other than the operands. For example, if you support the
4773 pattern with a @code{define_expand}, then in such a case the
4774 @code{define_expand} mustn't call @code{force_reg} or any other such
4775 function which might generate new pseudo registers.
4777 This requirement exists even for subword modes on a RISC machine where
4778 fetching those modes from memory normally requires several insns and
4779 some temporary registers.
4781 @findex change_address
4782 During reload a memory reference with an invalid address may be passed
4783 as an operand. Such an address will be replaced with a valid address
4784 later in the reload pass. In this case, nothing may be done with the
4785 address except to use it as it stands. If it is copied, it will not be
4786 replaced with a valid address. No attempt should be made to make such
4787 an address into a valid address and no routine (such as
4788 @code{change_address}) that will do so may be called. Note that
4789 @code{general_operand} will fail when applied to such an address.
4791 @findex reload_in_progress
4792 The global variable @code{reload_in_progress} (which must be explicitly
4793 declared if required) can be used to determine whether such special
4794 handling is required.
4796 The variety of operands that have reloads depends on the rest of the
4797 machine description, but typically on a RISC machine these can only be
4798 pseudo registers that did not get hard registers, while on other
4799 machines explicit memory references will get optional reloads.
4801 If a scratch register is required to move an object to or from memory,
4802 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4804 If there are cases which need scratch registers during or after reload,
4805 you must provide an appropriate secondary_reload target hook.
4807 @findex can_create_pseudo_p
4808 The macro @code{can_create_pseudo_p} can be used to determine if it
4809 is unsafe to create new pseudo registers. If this variable is nonzero, then
4810 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4812 The constraints on a @samp{mov@var{m}} must permit moving any hard
4813 register to any other hard register provided that
4814 @code{TARGET_HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4815 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4818 It is obligatory to support floating point @samp{mov@var{m}}
4819 instructions into and out of any registers that can hold fixed point
4820 values, because unions and structures (which have modes @code{SImode} or
4821 @code{DImode}) can be in those registers and they may have floating
4824 There may also be a need to support fixed point @samp{mov@var{m}}
4825 instructions in and out of floating point registers. Unfortunately, I
4826 have forgotten why this was so, and I don't know whether it is still
4827 true. If @code{TARGET_HARD_REGNO_MODE_OK} rejects fixed point values in
4828 floating point registers, then the constraints of the fixed point
4829 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4830 reload into a floating point register.
4832 @cindex @code{reload_in} instruction pattern
4833 @cindex @code{reload_out} instruction pattern
4834 @item @samp{reload_in@var{m}}
4835 @itemx @samp{reload_out@var{m}}
4836 These named patterns have been obsoleted by the target hook
4837 @code{secondary_reload}.
4839 Like @samp{mov@var{m}}, but used when a scratch register is required to
4840 move between operand 0 and operand 1. Operand 2 describes the scratch
4841 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4842 macro in @pxref{Register Classes}.
4844 There are special restrictions on the form of the @code{match_operand}s
4845 used in these patterns. First, only the predicate for the reload
4846 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4847 the predicates for operand 0 or 2. Second, there may be only one
4848 alternative in the constraints. Third, only a single register class
4849 letter may be used for the constraint; subsequent constraint letters
4850 are ignored. As a special exception, an empty constraint string
4851 matches the @code{ALL_REGS} register class. This may relieve ports
4852 of the burden of defining an @code{ALL_REGS} constraint letter just
4855 @cindex @code{movstrict@var{m}} instruction pattern
4856 @item @samp{movstrict@var{m}}
4857 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4858 with mode @var{m} of a register whose natural mode is wider,
4859 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4860 any of the register except the part which belongs to mode @var{m}.
4862 @cindex @code{movmisalign@var{m}} instruction pattern
4863 @item @samp{movmisalign@var{m}}
4864 This variant of a move pattern is designed to load or store a value
4865 from a memory address that is not naturally aligned for its mode.
4866 For a store, the memory will be in operand 0; for a load, the memory
4867 will be in operand 1. The other operand is guaranteed not to be a
4868 memory, so that it's easy to tell whether this is a load or store.
4870 This pattern is used by the autovectorizer, and when expanding a
4871 @code{MISALIGNED_INDIRECT_REF} expression.
4873 @cindex @code{load_multiple} instruction pattern
4874 @item @samp{load_multiple}
4875 Load several consecutive memory locations into consecutive registers.
4876 Operand 0 is the first of the consecutive registers, operand 1
4877 is the first memory location, and operand 2 is a constant: the
4878 number of consecutive registers.
4880 Define this only if the target machine really has such an instruction;
4881 do not define this if the most efficient way of loading consecutive
4882 registers from memory is to do them one at a time.
4884 On some machines, there are restrictions as to which consecutive
4885 registers can be stored into memory, such as particular starting or
4886 ending register numbers or only a range of valid counts. For those
4887 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4888 and make the pattern fail if the restrictions are not met.
4890 Write the generated insn as a @code{parallel} with elements being a
4891 @code{set} of one register from the appropriate memory location (you may
4892 also need @code{use} or @code{clobber} elements). Use a
4893 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4894 @file{rs6000.md} for examples of the use of this insn pattern.
4896 @cindex @samp{store_multiple} instruction pattern
4897 @item @samp{store_multiple}
4898 Similar to @samp{load_multiple}, but store several consecutive registers
4899 into consecutive memory locations. Operand 0 is the first of the
4900 consecutive memory locations, operand 1 is the first register, and
4901 operand 2 is a constant: the number of consecutive registers.
4903 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4904 @item @samp{vec_load_lanes@var{m}@var{n}}
4905 Perform an interleaved load of several vectors from memory operand 1
4906 into register operand 0. Both operands have mode @var{m}. The register
4907 operand is viewed as holding consecutive vectors of mode @var{n},
4908 while the memory operand is a flat array that contains the same number
4909 of elements. The operation is equivalent to:
4912 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4913 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4914 for (i = 0; i < c; i++)
4915 operand0[i][j] = operand1[j * c + i];
4918 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4919 from memory into a register of mode @samp{TI}@. The register
4920 contains two consecutive vectors of mode @samp{V4HI}@.
4922 This pattern can only be used if:
4924 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4926 is true. GCC assumes that, if a target supports this kind of
4927 instruction for some mode @var{n}, it also supports unaligned
4928 loads for vectors of mode @var{n}.
4930 This pattern is not allowed to @code{FAIL}.
4932 @cindex @code{vec_mask_load_lanes@var{m}@var{n}} instruction pattern
4933 @item @samp{vec_mask_load_lanes@var{m}@var{n}}
4934 Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional
4935 mask operand (operand 2) that specifies which elements of the destination
4936 vectors should be loaded. Other elements of the destination
4937 vectors are set to zero. The operation is equivalent to:
4940 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4941 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4943 for (i = 0; i < c; i++)
4944 operand0[i][j] = operand1[j * c + i];
4946 for (i = 0; i < c; i++)
4950 This pattern is not allowed to @code{FAIL}.
4952 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4953 @item @samp{vec_store_lanes@var{m}@var{n}}
4954 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4955 and register operands reversed. That is, the instruction is
4959 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4960 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4961 for (i = 0; i < c; i++)
4962 operand0[j * c + i] = operand1[i][j];
4965 for a memory operand 0 and register operand 1.
4967 This pattern is not allowed to @code{FAIL}.
4969 @cindex @code{vec_mask_store_lanes@var{m}@var{n}} instruction pattern
4970 @item @samp{vec_mask_store_lanes@var{m}@var{n}}
4971 Like @samp{vec_store_lanes@var{m}@var{n}}, but takes an additional
4972 mask operand (operand 2) that specifies which elements of the source
4973 vectors should be stored. The operation is equivalent to:
4976 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4977 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4979 for (i = 0; i < c; i++)
4980 operand0[j * c + i] = operand1[i][j];
4983 This pattern is not allowed to @code{FAIL}.
4985 @cindex @code{gather_load@var{m}} instruction pattern
4986 @item @samp{gather_load@var{m}}
4987 Load several separate memory locations into a vector of mode @var{m}.
4988 Operand 1 is a scalar base address and operand 2 is a vector of
4989 offsets from that base. Operand 0 is a destination vector with the
4990 same number of elements as the offset. For each element index @var{i}:
4994 extend the offset element @var{i} to address width, using zero
4995 extension if operand 3 is 1 and sign extension if operand 3 is zero;
4997 multiply the extended offset by operand 4;
4999 add the result to the base; and
5001 load the value at that address into element @var{i} of operand 0.
5004 The value of operand 3 does not matter if the offsets are already
5007 @cindex @code{mask_gather_load@var{m}} instruction pattern
5008 @item @samp{mask_gather_load@var{m}}
5009 Like @samp{gather_load@var{m}}, but takes an extra mask operand as
5010 operand 5. Bit @var{i} of the mask is set if element @var{i}
5011 of the result should be loaded from memory and clear if element @var{i}
5012 of the result should be set to zero.
5014 @cindex @code{scatter_store@var{m}} instruction pattern
5015 @item @samp{scatter_store@var{m}}
5016 Store a vector of mode @var{m} into several distinct memory locations.
5017 Operand 0 is a scalar base address and operand 1 is a vector of offsets
5018 from that base. Operand 4 is the vector of values that should be stored,
5019 which has the same number of elements as the offset. For each element
5024 extend the offset element @var{i} to address width, using zero
5025 extension if operand 2 is 1 and sign extension if operand 2 is zero;
5027 multiply the extended offset by operand 3;
5029 add the result to the base; and
5031 store element @var{i} of operand 4 to that address.
5034 The value of operand 2 does not matter if the offsets are already
5037 @cindex @code{mask_scatter_store@var{m}} instruction pattern
5038 @item @samp{mask_scatter_store@var{m}}
5039 Like @samp{scatter_store@var{m}}, but takes an extra mask operand as
5040 operand 5. Bit @var{i} of the mask is set if element @var{i}
5041 of the result should be stored to memory.
5043 @cindex @code{vec_set@var{m}} instruction pattern
5044 @item @samp{vec_set@var{m}}
5045 Set given field in the vector value. Operand 0 is the vector to modify,
5046 operand 1 is new value of field and operand 2 specify the field index.
5048 @cindex @code{vec_extract@var{m}@var{n}} instruction pattern
5049 @item @samp{vec_extract@var{m}@var{n}}
5050 Extract given field from the vector value. Operand 1 is the vector, operand 2
5051 specify field index and operand 0 place to store value into. The
5052 @var{n} mode is the mode of the field or vector of fields that should be
5053 extracted, should be either element mode of the vector mode @var{m}, or
5054 a vector mode with the same element mode and smaller number of elements.
5055 If @var{n} is a vector mode, the index is counted in units of that mode.
5057 @cindex @code{vec_init@var{m}@var{n}} instruction pattern
5058 @item @samp{vec_init@var{m}@var{n}}
5059 Initialize the vector to given values. Operand 0 is the vector to initialize
5060 and operand 1 is parallel containing values for individual fields. The
5061 @var{n} mode is the mode of the elements, should be either element mode of
5062 the vector mode @var{m}, or a vector mode with the same element mode and
5063 smaller number of elements.
5065 @cindex @code{vec_duplicate@var{m}} instruction pattern
5066 @item @samp{vec_duplicate@var{m}}
5067 Initialize vector output operand 0 so that each element has the value given
5068 by scalar input operand 1. The vector has mode @var{m} and the scalar has
5069 the mode appropriate for one element of @var{m}.
5071 This pattern only handles duplicates of non-constant inputs. Constant
5072 vectors go through the @code{mov@var{m}} pattern instead.
5074 This pattern is not allowed to @code{FAIL}.
5076 @cindex @code{vec_series@var{m}} instruction pattern
5077 @item @samp{vec_series@var{m}}
5078 Initialize vector output operand 0 so that element @var{i} is equal to
5079 operand 1 plus @var{i} times operand 2. In other words, create a linear
5080 series whose base value is operand 1 and whose step is operand 2.
5082 The vector output has mode @var{m} and the scalar inputs have the mode
5083 appropriate for one element of @var{m}. This pattern is not used for
5084 floating-point vectors, in order to avoid having to specify the
5085 rounding behavior for @var{i} > 1.
5087 This pattern is not allowed to @code{FAIL}.
5089 @cindex @code{while_ult@var{m}@var{n}} instruction pattern
5090 @item @code{while_ult@var{m}@var{n}}
5091 Set operand 0 to a mask that is true while incrementing operand 1
5092 gives a value that is less than operand 2. Operand 0 has mode @var{n}
5093 and operands 1 and 2 are scalar integers of mode @var{m}.
5094 The operation is equivalent to:
5097 operand0[0] = operand1 < operand2;
5098 for (i = 1; i < GET_MODE_NUNITS (@var{n}); i++)
5099 operand0[i] = operand0[i - 1] && (operand1 + i < operand2);
5102 @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern
5103 @item @samp{vec_cmp@var{m}@var{n}}
5104 Output a vector comparison. Operand 0 of mode @var{n} is the destination for
5105 predicate in operand 1 which is a signed vector comparison with operands of
5106 mode @var{m} in operands 2 and 3. Predicate is computed by element-wise
5107 evaluation of the vector comparison with a truth value of all-ones and a false
5110 @cindex @code{vec_cmpu@var{m}@var{n}} instruction pattern
5111 @item @samp{vec_cmpu@var{m}@var{n}}
5112 Similar to @code{vec_cmp@var{m}@var{n}} but perform unsigned vector comparison.
5114 @cindex @code{vec_cmpeq@var{m}@var{n}} instruction pattern
5115 @item @samp{vec_cmpeq@var{m}@var{n}}
5116 Similar to @code{vec_cmp@var{m}@var{n}} but perform equality or non-equality
5117 vector comparison only. If @code{vec_cmp@var{m}@var{n}}
5118 or @code{vec_cmpu@var{m}@var{n}} instruction pattern is supported,
5119 it will be preferred over @code{vec_cmpeq@var{m}@var{n}}, so there is
5120 no need to define this instruction pattern if the others are supported.
5122 @cindex @code{vcond@var{m}@var{n}} instruction pattern
5123 @item @samp{vcond@var{m}@var{n}}
5124 Output a conditional vector move. Operand 0 is the destination to
5125 receive a combination of operand 1 and operand 2, which are of mode @var{m},
5126 dependent on the outcome of the predicate in operand 3 which is a signed
5127 vector comparison with operands of mode @var{n} in operands 4 and 5. The
5128 modes @var{m} and @var{n} should have the same size. Operand 0
5129 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
5130 where @var{msk} is computed by element-wise evaluation of the vector
5131 comparison with a truth value of all-ones and a false value of all-zeros.
5133 @cindex @code{vcondu@var{m}@var{n}} instruction pattern
5134 @item @samp{vcondu@var{m}@var{n}}
5135 Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector
5138 @cindex @code{vcondeq@var{m}@var{n}} instruction pattern
5139 @item @samp{vcondeq@var{m}@var{n}}
5140 Similar to @code{vcond@var{m}@var{n}} but performs equality or
5141 non-equality vector comparison only. If @code{vcond@var{m}@var{n}}
5142 or @code{vcondu@var{m}@var{n}} instruction pattern is supported,
5143 it will be preferred over @code{vcondeq@var{m}@var{n}}, so there is
5144 no need to define this instruction pattern if the others are supported.
5146 @cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern
5147 @item @samp{vcond_mask_@var{m}@var{n}}
5148 Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed
5149 result of vector comparison.
5151 @cindex @code{maskload@var{m}@var{n}} instruction pattern
5152 @item @samp{maskload@var{m}@var{n}}
5153 Perform a masked load of vector from memory operand 1 of mode @var{m}
5154 into register operand 0. Mask is provided in register operand 2 of
5157 This pattern is not allowed to @code{FAIL}.
5159 @cindex @code{maskstore@var{m}@var{n}} instruction pattern
5160 @item @samp{maskstore@var{m}@var{n}}
5161 Perform a masked store of vector from register operand 1 of mode @var{m}
5162 into memory operand 0. Mask is provided in register operand 2 of
5165 This pattern is not allowed to @code{FAIL}.
5167 @cindex @code{vec_perm@var{m}} instruction pattern
5168 @item @samp{vec_perm@var{m}}
5169 Output a (variable) vector permutation. Operand 0 is the destination
5170 to receive elements from operand 1 and operand 2, which are of mode
5171 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
5172 vector of the same width and number of elements as mode @var{m}.
5174 The input elements are numbered from 0 in operand 1 through
5175 @math{2*@var{N}-1} in operand 2. The elements of the selector must
5176 be computed modulo @math{2*@var{N}}. Note that if
5177 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
5178 with just operand 1 and selector elements modulo @var{N}.
5180 In order to make things easy for a number of targets, if there is no
5181 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
5182 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
5183 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
5186 See also @code{TARGET_VECTORIZER_VEC_PERM_CONST}, which performs
5187 the analogous operation for constant selectors.
5189 @cindex @code{push@var{m}1} instruction pattern
5190 @item @samp{push@var{m}1}
5191 Output a push instruction. Operand 0 is value to push. Used only when
5192 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
5193 missing and in such case an @code{mov} expander is used instead, with a
5194 @code{MEM} expression forming the push operation. The @code{mov} expander
5195 method is deprecated.
5197 @cindex @code{add@var{m}3} instruction pattern
5198 @item @samp{add@var{m}3}
5199 Add operand 2 and operand 1, storing the result in operand 0. All operands
5200 must have mode @var{m}. This can be used even on two-address machines, by
5201 means of constraints requiring operands 1 and 0 to be the same location.
5203 @cindex @code{ssadd@var{m}3} instruction pattern
5204 @cindex @code{usadd@var{m}3} instruction pattern
5205 @cindex @code{sub@var{m}3} instruction pattern
5206 @cindex @code{sssub@var{m}3} instruction pattern
5207 @cindex @code{ussub@var{m}3} instruction pattern
5208 @cindex @code{mul@var{m}3} instruction pattern
5209 @cindex @code{ssmul@var{m}3} instruction pattern
5210 @cindex @code{usmul@var{m}3} instruction pattern
5211 @cindex @code{div@var{m}3} instruction pattern
5212 @cindex @code{ssdiv@var{m}3} instruction pattern
5213 @cindex @code{udiv@var{m}3} instruction pattern
5214 @cindex @code{usdiv@var{m}3} instruction pattern
5215 @cindex @code{mod@var{m}3} instruction pattern
5216 @cindex @code{umod@var{m}3} instruction pattern
5217 @cindex @code{umin@var{m}3} instruction pattern
5218 @cindex @code{umax@var{m}3} instruction pattern
5219 @cindex @code{and@var{m}3} instruction pattern
5220 @cindex @code{ior@var{m}3} instruction pattern
5221 @cindex @code{xor@var{m}3} instruction pattern
5222 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
5223 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
5224 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
5225 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
5226 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
5227 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
5228 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
5229 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
5230 Similar, for other arithmetic operations.
5232 @cindex @code{addv@var{m}4} instruction pattern
5233 @item @samp{addv@var{m}4}
5234 Like @code{add@var{m}3} but takes a @code{code_label} as operand 3 and
5235 emits code to jump to it if signed overflow occurs during the addition.
5236 This pattern is used to implement the built-in functions performing
5237 signed integer addition with overflow checking.
5239 @cindex @code{subv@var{m}4} instruction pattern
5240 @cindex @code{mulv@var{m}4} instruction pattern
5241 @item @samp{subv@var{m}4}, @samp{mulv@var{m}4}
5242 Similar, for other signed arithmetic operations.
5244 @cindex @code{uaddv@var{m}4} instruction pattern
5245 @item @samp{uaddv@var{m}4}
5246 Like @code{addv@var{m}4} but for unsigned addition. That is to
5247 say, the operation is the same as signed addition but the jump
5248 is taken only on unsigned overflow.
5250 @cindex @code{usubv@var{m}4} instruction pattern
5251 @cindex @code{umulv@var{m}4} instruction pattern
5252 @item @samp{usubv@var{m}4}, @samp{umulv@var{m}4}
5253 Similar, for other unsigned arithmetic operations.
5255 @cindex @code{addptr@var{m}3} instruction pattern
5256 @item @samp{addptr@var{m}3}
5257 Like @code{add@var{m}3} but is guaranteed to only be used for address
5258 calculations. The expanded code is not allowed to clobber the
5259 condition code. It only needs to be defined if @code{add@var{m}3}
5260 sets the condition code. If adds used for address calculations and
5261 normal adds are not compatible it is required to expand a distinct
5262 pattern (e.g.@: using an unspec). The pattern is used by LRA to emit
5263 address calculations. @code{add@var{m}3} is used if
5264 @code{addptr@var{m}3} is not defined.
5266 @cindex @code{fma@var{m}4} instruction pattern
5267 @item @samp{fma@var{m}4}
5268 Multiply operand 2 and operand 1, then add operand 3, storing the
5269 result in operand 0 without doing an intermediate rounding step. All
5270 operands must have mode @var{m}. This pattern is used to implement
5271 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
5272 the ISO C99 standard.
5274 @cindex @code{fms@var{m}4} instruction pattern
5275 @item @samp{fms@var{m}4}
5276 Like @code{fma@var{m}4}, except operand 3 subtracted from the
5277 product instead of added to the product. This is represented
5281 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
5284 @cindex @code{fnma@var{m}4} instruction pattern
5285 @item @samp{fnma@var{m}4}
5286 Like @code{fma@var{m}4} except that the intermediate product
5287 is negated before being added to operand 3. This is represented
5291 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
5294 @cindex @code{fnms@var{m}4} instruction pattern
5295 @item @samp{fnms@var{m}4}
5296 Like @code{fms@var{m}4} except that the intermediate product
5297 is negated before subtracting operand 3. This is represented
5301 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
5304 @cindex @code{min@var{m}3} instruction pattern
5305 @cindex @code{max@var{m}3} instruction pattern
5306 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
5307 Signed minimum and maximum operations. When used with floating point,
5308 if both operands are zeros, or if either operand is @code{NaN}, then
5309 it is unspecified which of the two operands is returned as the result.
5311 @cindex @code{fmin@var{m}3} instruction pattern
5312 @cindex @code{fmax@var{m}3} instruction pattern
5313 @item @samp{fmin@var{m}3}, @samp{fmax@var{m}3}
5314 IEEE-conformant minimum and maximum operations. If one operand is a quiet
5315 @code{NaN}, then the other operand is returned. If both operands are quiet
5316 @code{NaN}, then a quiet @code{NaN} is returned. In the case when gcc supports
5317 signaling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
5318 raised and a quiet @code{NaN} is returned.
5320 All operands have mode @var{m}, which is a scalar or vector
5321 floating-point mode. These patterns are not allowed to @code{FAIL}.
5323 @cindex @code{reduc_smin_scal_@var{m}} instruction pattern
5324 @cindex @code{reduc_smax_scal_@var{m}} instruction pattern
5325 @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}}
5326 Find the signed minimum/maximum of the elements of a vector. The vector is
5327 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5328 the elements of the input vector.
5330 @cindex @code{reduc_umin_scal_@var{m}} instruction pattern
5331 @cindex @code{reduc_umax_scal_@var{m}} instruction pattern
5332 @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}}
5333 Find the unsigned minimum/maximum of the elements of a vector. The vector is
5334 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5335 the elements of the input vector.
5337 @cindex @code{reduc_plus_scal_@var{m}} instruction pattern
5338 @item @samp{reduc_plus_scal_@var{m}}
5339 Compute the sum of the elements of a vector. The vector is operand 1, and
5340 operand 0 is the scalar result, with mode equal to the mode of the elements of
5343 @cindex @code{reduc_and_scal_@var{m}} instruction pattern
5344 @item @samp{reduc_and_scal_@var{m}}
5345 @cindex @code{reduc_ior_scal_@var{m}} instruction pattern
5346 @itemx @samp{reduc_ior_scal_@var{m}}
5347 @cindex @code{reduc_xor_scal_@var{m}} instruction pattern
5348 @itemx @samp{reduc_xor_scal_@var{m}}
5349 Compute the bitwise @code{AND}/@code{IOR}/@code{XOR} reduction of the elements
5350 of a vector of mode @var{m}. Operand 1 is the vector input and operand 0
5351 is the scalar result. The mode of the scalar result is the same as one
5354 @cindex @code{extract_last_@var{m}} instruction pattern
5355 @item @code{extract_last_@var{m}}
5356 Find the last set bit in mask operand 1 and extract the associated element
5357 of vector operand 2. Store the result in scalar operand 0. Operand 2
5358 has vector mode @var{m} while operand 0 has the mode appropriate for one
5359 element of @var{m}. Operand 1 has the usual mask mode for vectors of mode
5360 @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5362 @cindex @code{fold_extract_last_@var{m}} instruction pattern
5363 @item @code{fold_extract_last_@var{m}}
5364 If any bits of mask operand 2 are set, find the last set bit, extract
5365 the associated element from vector operand 3, and store the result
5366 in operand 0. Store operand 1 in operand 0 otherwise. Operand 3
5367 has mode @var{m} and operands 0 and 1 have the mode appropriate for
5368 one element of @var{m}. Operand 2 has the usual mask mode for vectors
5369 of mode @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5371 @cindex @code{fold_left_plus_@var{m}} instruction pattern
5372 @item @code{fold_left_plus_@var{m}}
5373 Take scalar operand 1 and successively add each element from vector
5374 operand 2. Store the result in scalar operand 0. The vector has
5375 mode @var{m} and the scalars have the mode appropriate for one
5376 element of @var{m}. The operation is strictly in-order: there is
5379 @cindex @code{sdot_prod@var{m}} instruction pattern
5380 @item @samp{sdot_prod@var{m}}
5381 @cindex @code{udot_prod@var{m}} instruction pattern
5382 @itemx @samp{udot_prod@var{m}}
5383 Compute the sum of the products of two signed/unsigned elements.
5384 Operand 1 and operand 2 are of the same mode. Their product, which is of a
5385 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
5386 wider than the mode of the product. The result is placed in operand 0, which
5387 is of the same mode as operand 3.
5389 @cindex @code{ssad@var{m}} instruction pattern
5390 @item @samp{ssad@var{m}}
5391 @cindex @code{usad@var{m}} instruction pattern
5392 @item @samp{usad@var{m}}
5393 Compute the sum of absolute differences of two signed/unsigned elements.
5394 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
5395 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
5396 equal or wider than the mode of the absolute difference. The result is placed
5397 in operand 0, which is of the same mode as operand 3.
5399 @cindex @code{widen_ssum@var{m3}} instruction pattern
5400 @item @samp{widen_ssum@var{m3}}
5401 @cindex @code{widen_usum@var{m3}} instruction pattern
5402 @itemx @samp{widen_usum@var{m3}}
5403 Operands 0 and 2 are of the same mode, which is wider than the mode of
5404 operand 1. Add operand 1 to operand 2 and place the widened result in
5405 operand 0. (This is used express accumulation of elements into an accumulator
5408 @cindex @code{vec_shl_insert_@var{m}} instruction pattern
5409 @item @samp{vec_shl_insert_@var{m}}
5410 Shift the elements in vector input operand 1 left one element (i.e.@:
5411 away from element 0) and fill the vacated element 0 with the scalar
5412 in operand 2. Store the result in vector output operand 0. Operands
5413 0 and 1 have mode @var{m} and operand 2 has the mode appropriate for
5414 one element of @var{m}.
5416 @cindex @code{vec_shr_@var{m}} instruction pattern
5417 @item @samp{vec_shr_@var{m}}
5418 Whole vector right shift in bits, i.e.@: towards element 0.
5419 Operand 1 is a vector to be shifted.
5420 Operand 2 is an integer shift amount in bits.
5421 Operand 0 is where the resulting shifted vector is stored.
5422 The output and input vectors should have the same modes.
5424 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
5425 @item @samp{vec_pack_trunc_@var{m}}
5426 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5427 are vectors of the same mode having N integral or floating point elements
5428 of size S@. Operand 0 is the resulting vector in which 2*N elements of
5429 size N/2 are concatenated after narrowing them down using truncation.
5431 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
5432 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
5433 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
5434 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5435 are vectors of the same mode having N integral elements of size S.
5436 Operand 0 is the resulting vector in which the elements of the two input
5437 vectors are concatenated after narrowing them down using signed/unsigned
5438 saturating arithmetic.
5440 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
5441 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
5442 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
5443 Narrow, convert to signed/unsigned integral type and merge the elements
5444 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5445 floating point elements of size S@. Operand 0 is the resulting vector
5446 in which 2*N elements of size N/2 are concatenated.
5448 @cindex @code{vec_packs_float_@var{m}} instruction pattern
5449 @cindex @code{vec_packu_float_@var{m}} instruction pattern
5450 @item @samp{vec_packs_float_@var{m}}, @samp{vec_packu_float_@var{m}}
5451 Narrow, convert to floating point type and merge the elements
5452 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5453 signed/unsigned integral elements of size S@. Operand 0 is the resulting vector
5454 in which 2*N elements of size N/2 are concatenated.
5456 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
5457 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
5458 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
5459 Extract and widen (promote) the high/low part of a vector of signed
5460 integral or floating point elements. The input vector (operand 1) has N
5461 elements of size S@. Widen (promote) the high/low elements of the vector
5462 using signed or floating point extension and place the resulting N/2
5463 values of size 2*S in the output vector (operand 0).
5465 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
5466 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
5467 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
5468 Extract and widen (promote) the high/low part of a vector of unsigned
5469 integral elements. The input vector (operand 1) has N elements of size S.
5470 Widen (promote) the high/low elements of the vector using zero extension and
5471 place the resulting N/2 values of size 2*S in the output vector (operand 0).
5473 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
5474 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
5475 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
5476 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
5477 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
5478 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
5479 Extract, convert to floating point type and widen the high/low part of a
5480 vector of signed/unsigned integral elements. The input vector (operand 1)
5481 has N elements of size S@. Convert the high/low elements of the vector using
5482 floating point conversion and place the resulting N/2 values of size 2*S in
5483 the output vector (operand 0).
5485 @cindex @code{vec_unpack_sfix_trunc_hi_@var{m}} instruction pattern
5486 @cindex @code{vec_unpack_sfix_trunc_lo_@var{m}} instruction pattern
5487 @cindex @code{vec_unpack_ufix_trunc_hi_@var{m}} instruction pattern
5488 @cindex @code{vec_unpack_ufix_trunc_lo_@var{m}} instruction pattern
5489 @item @samp{vec_unpack_sfix_trunc_hi_@var{m}},
5490 @itemx @samp{vec_unpack_sfix_trunc_lo_@var{m}}
5491 @itemx @samp{vec_unpack_ufix_trunc_hi_@var{m}}
5492 @itemx @samp{vec_unpack_ufix_trunc_lo_@var{m}}
5493 Extract, convert to signed/unsigned integer type and widen the high/low part of a
5494 vector of floating point elements. The input vector (operand 1)
5495 has N elements of size S@. Convert the high/low elements of the vector
5496 to integers and place the resulting N/2 values of size 2*S in
5497 the output vector (operand 0).
5499 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
5500 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
5501 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
5502 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
5503 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
5504 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
5505 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
5506 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
5507 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
5508 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
5509 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
5510 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
5511 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
5512 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
5513 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
5514 in the output vector (operand 0). A target shouldn't implement even/odd pattern
5515 pair if it is less efficient than lo/hi one.
5517 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
5518 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
5519 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
5520 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
5521 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
5522 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
5523 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
5524 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
5525 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
5526 output vector (operand 0).
5528 @cindex @code{mulhisi3} instruction pattern
5529 @item @samp{mulhisi3}
5530 Multiply operands 1 and 2, which have mode @code{HImode}, and store
5531 a @code{SImode} product in operand 0.
5533 @cindex @code{mulqihi3} instruction pattern
5534 @cindex @code{mulsidi3} instruction pattern
5535 @item @samp{mulqihi3}, @samp{mulsidi3}
5536 Similar widening-multiplication instructions of other widths.
5538 @cindex @code{umulqihi3} instruction pattern
5539 @cindex @code{umulhisi3} instruction pattern
5540 @cindex @code{umulsidi3} instruction pattern
5541 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
5542 Similar widening-multiplication instructions that do unsigned
5545 @cindex @code{usmulqihi3} instruction pattern
5546 @cindex @code{usmulhisi3} instruction pattern
5547 @cindex @code{usmulsidi3} instruction pattern
5548 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
5549 Similar widening-multiplication instructions that interpret the first
5550 operand as unsigned and the second operand as signed, then do a signed
5553 @cindex @code{smul@var{m}3_highpart} instruction pattern
5554 @item @samp{smul@var{m}3_highpart}
5555 Perform a signed multiplication of operands 1 and 2, which have mode
5556 @var{m}, and store the most significant half of the product in operand 0.
5557 The least significant half of the product is discarded.
5559 @cindex @code{umul@var{m}3_highpart} instruction pattern
5560 @item @samp{umul@var{m}3_highpart}
5561 Similar, but the multiplication is unsigned.
5563 @cindex @code{madd@var{m}@var{n}4} instruction pattern
5564 @item @samp{madd@var{m}@var{n}4}
5565 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
5566 operand 3, and store the result in operand 0. Operands 1 and 2
5567 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5568 Both modes must be integer or fixed-point modes and @var{n} must be twice
5569 the size of @var{m}.
5571 In other words, @code{madd@var{m}@var{n}4} is like
5572 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
5574 These instructions are not allowed to @code{FAIL}.
5576 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
5577 @item @samp{umadd@var{m}@var{n}4}
5578 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5579 operands instead of sign-extending them.
5581 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5582 @item @samp{ssmadd@var{m}@var{n}4}
5583 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5586 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5587 @item @samp{usmadd@var{m}@var{n}4}
5588 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5589 unsigned-saturating.
5591 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5592 @item @samp{msub@var{m}@var{n}4}
5593 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5594 result from operand 3, and store the result in operand 0. Operands 1 and 2
5595 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5596 Both modes must be integer or fixed-point modes and @var{n} must be twice
5597 the size of @var{m}.
5599 In other words, @code{msub@var{m}@var{n}4} is like
5600 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5603 These instructions are not allowed to @code{FAIL}.
5605 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5606 @item @samp{umsub@var{m}@var{n}4}
5607 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5608 operands instead of sign-extending them.
5610 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5611 @item @samp{ssmsub@var{m}@var{n}4}
5612 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5615 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5616 @item @samp{usmsub@var{m}@var{n}4}
5617 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5618 unsigned-saturating.
5620 @cindex @code{divmod@var{m}4} instruction pattern
5621 @item @samp{divmod@var{m}4}
5622 Signed division that produces both a quotient and a remainder.
5623 Operand 1 is divided by operand 2 to produce a quotient stored
5624 in operand 0 and a remainder stored in operand 3.
5626 For machines with an instruction that produces both a quotient and a
5627 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5628 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5629 allows optimization in the relatively common case when both the quotient
5630 and remainder are computed.
5632 If an instruction that just produces a quotient or just a remainder
5633 exists and is more efficient than the instruction that produces both,
5634 write the output routine of @samp{divmod@var{m}4} to call
5635 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5636 quotient or remainder and generate the appropriate instruction.
5638 @cindex @code{udivmod@var{m}4} instruction pattern
5639 @item @samp{udivmod@var{m}4}
5640 Similar, but does unsigned division.
5642 @anchor{shift patterns}
5643 @cindex @code{ashl@var{m}3} instruction pattern
5644 @cindex @code{ssashl@var{m}3} instruction pattern
5645 @cindex @code{usashl@var{m}3} instruction pattern
5646 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5647 Arithmetic-shift operand 1 left by a number of bits specified by operand
5648 2, and store the result in operand 0. Here @var{m} is the mode of
5649 operand 0 and operand 1; operand 2's mode is specified by the
5650 instruction pattern, and the compiler will convert the operand to that
5651 mode before generating the instruction. The shift or rotate expander
5652 or instruction pattern should explicitly specify the mode of the operand 2,
5653 it should never be @code{VOIDmode}. The meaning of out-of-range shift
5654 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5655 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5657 @cindex @code{ashr@var{m}3} instruction pattern
5658 @cindex @code{lshr@var{m}3} instruction pattern
5659 @cindex @code{rotl@var{m}3} instruction pattern
5660 @cindex @code{rotr@var{m}3} instruction pattern
5661 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5662 Other shift and rotate instructions, analogous to the
5663 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5665 @cindex @code{vashl@var{m}3} instruction pattern
5666 @cindex @code{vashr@var{m}3} instruction pattern
5667 @cindex @code{vlshr@var{m}3} instruction pattern
5668 @cindex @code{vrotl@var{m}3} instruction pattern
5669 @cindex @code{vrotr@var{m}3} instruction pattern
5670 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5671 Vector shift and rotate instructions that take vectors as operand 2
5672 instead of a scalar type.
5674 @cindex @code{avg@var{m}3_floor} instruction pattern
5675 @cindex @code{uavg@var{m}3_floor} instruction pattern
5676 @item @samp{avg@var{m}3_floor}
5677 @itemx @samp{uavg@var{m}3_floor}
5678 Signed and unsigned average instructions. These instructions add
5679 operands 1 and 2 without truncation, divide the result by 2,
5680 round towards -Inf, and store the result in operand 0. This is
5681 equivalent to the C code:
5683 narrow op0, op1, op2;
5685 op0 = (narrow) (((wide) op1 + (wide) op2) >> 1);
5687 where the sign of @samp{narrow} determines whether this is a signed
5688 or unsigned operation.
5690 @cindex @code{avg@var{m}3_ceil} instruction pattern
5691 @cindex @code{uavg@var{m}3_ceil} instruction pattern
5692 @item @samp{avg@var{m}3_ceil}
5693 @itemx @samp{uavg@var{m}3_ceil}
5694 Like @samp{avg@var{m}3_floor} and @samp{uavg@var{m}3_floor}, but round
5695 towards +Inf. This is equivalent to the C code:
5697 narrow op0, op1, op2;
5699 op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1);
5702 @cindex @code{bswap@var{m}2} instruction pattern
5703 @item @samp{bswap@var{m}2}
5704 Reverse the order of bytes of operand 1 and store the result in operand 0.
5706 @cindex @code{neg@var{m}2} instruction pattern
5707 @cindex @code{ssneg@var{m}2} instruction pattern
5708 @cindex @code{usneg@var{m}2} instruction pattern
5709 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5710 Negate operand 1 and store the result in operand 0.
5712 @cindex @code{negv@var{m}3} instruction pattern
5713 @item @samp{negv@var{m}3}
5714 Like @code{neg@var{m}2} but takes a @code{code_label} as operand 2 and
5715 emits code to jump to it if signed overflow occurs during the negation.
5717 @cindex @code{abs@var{m}2} instruction pattern
5718 @item @samp{abs@var{m}2}
5719 Store the absolute value of operand 1 into operand 0.
5721 @cindex @code{sqrt@var{m}2} instruction pattern
5722 @item @samp{sqrt@var{m}2}
5723 Store the square root of operand 1 into operand 0. Both operands have
5724 mode @var{m}, which is a scalar or vector floating-point mode.
5726 This pattern is not allowed to @code{FAIL}.
5728 @cindex @code{rsqrt@var{m}2} instruction pattern
5729 @item @samp{rsqrt@var{m}2}
5730 Store the reciprocal of the square root of operand 1 into operand 0.
5731 Both operands have mode @var{m}, which is a scalar or vector
5732 floating-point mode.
5734 On most architectures this pattern is only approximate, so either
5735 its C condition or the @code{TARGET_OPTAB_SUPPORTED_P} hook should
5736 check for the appropriate math flags. (Using the C condition is
5737 more direct, but using @code{TARGET_OPTAB_SUPPORTED_P} can be useful
5738 if a target-specific built-in also uses the @samp{rsqrt@var{m}2}
5741 This pattern is not allowed to @code{FAIL}.
5743 @cindex @code{fmod@var{m}3} instruction pattern
5744 @item @samp{fmod@var{m}3}
5745 Store the remainder of dividing operand 1 by operand 2 into
5746 operand 0, rounded towards zero to an integer. All operands have
5747 mode @var{m}, which is a scalar or vector floating-point mode.
5749 This pattern is not allowed to @code{FAIL}.
5751 @cindex @code{remainder@var{m}3} instruction pattern
5752 @item @samp{remainder@var{m}3}
5753 Store the remainder of dividing operand 1 by operand 2 into
5754 operand 0, rounded to the nearest integer. All operands have
5755 mode @var{m}, which is a scalar or vector floating-point mode.
5757 This pattern is not allowed to @code{FAIL}.
5759 @cindex @code{scalb@var{m}3} instruction pattern
5760 @item @samp{scalb@var{m}3}
5761 Raise @code{FLT_RADIX} to the power of operand 2, multiply it by
5762 operand 1, and store the result in operand 0. All operands have
5763 mode @var{m}, which is a scalar or vector floating-point mode.
5765 This pattern is not allowed to @code{FAIL}.
5767 @cindex @code{ldexp@var{m}3} instruction pattern
5768 @item @samp{ldexp@var{m}3}
5769 Raise 2 to the power of operand 2, multiply it by operand 1, and store
5770 the result in operand 0. Operands 0 and 1 have mode @var{m}, which is
5771 a scalar or vector floating-point mode. Operand 2's mode has
5772 the same number of elements as @var{m} and each element is wide
5773 enough to store an @code{int}. The integers are signed.
5775 This pattern is not allowed to @code{FAIL}.
5777 @cindex @code{cos@var{m}2} instruction pattern
5778 @item @samp{cos@var{m}2}
5779 Store the cosine of operand 1 into operand 0. Both operands have
5780 mode @var{m}, which is a scalar or vector floating-point mode.
5782 This pattern is not allowed to @code{FAIL}.
5784 @cindex @code{sin@var{m}2} instruction pattern
5785 @item @samp{sin@var{m}2}
5786 Store the sine of operand 1 into operand 0. Both operands have
5787 mode @var{m}, which is a scalar or vector floating-point mode.
5789 This pattern is not allowed to @code{FAIL}.
5791 @cindex @code{sincos@var{m}3} instruction pattern
5792 @item @samp{sincos@var{m}3}
5793 Store the cosine of operand 2 into operand 0 and the sine of
5794 operand 2 into operand 1. All operands have mode @var{m},
5795 which is a scalar or vector floating-point mode.
5797 Targets that can calculate the sine and cosine simultaneously can
5798 implement this pattern as opposed to implementing individual
5799 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5800 and @code{cos} built-in functions will then be expanded to the
5801 @code{sincos@var{m}3} pattern, with one of the output values
5804 @cindex @code{tan@var{m}2} instruction pattern
5805 @item @samp{tan@var{m}2}
5806 Store the tangent of operand 1 into operand 0. Both operands have
5807 mode @var{m}, which is a scalar or vector floating-point mode.
5809 This pattern is not allowed to @code{FAIL}.
5811 @cindex @code{asin@var{m}2} instruction pattern
5812 @item @samp{asin@var{m}2}
5813 Store the arc sine of operand 1 into operand 0. Both operands have
5814 mode @var{m}, which is a scalar or vector floating-point mode.
5816 This pattern is not allowed to @code{FAIL}.
5818 @cindex @code{acos@var{m}2} instruction pattern
5819 @item @samp{acos@var{m}2}
5820 Store the arc cosine of operand 1 into operand 0. Both operands have
5821 mode @var{m}, which is a scalar or vector floating-point mode.
5823 This pattern is not allowed to @code{FAIL}.
5825 @cindex @code{atan@var{m}2} instruction pattern
5826 @item @samp{atan@var{m}2}
5827 Store the arc tangent of operand 1 into operand 0. Both operands have
5828 mode @var{m}, which is a scalar or vector floating-point mode.
5830 This pattern is not allowed to @code{FAIL}.
5832 @cindex @code{exp@var{m}2} instruction pattern
5833 @item @samp{exp@var{m}2}
5834 Raise e (the base of natural logarithms) to the power of operand 1
5835 and store the result in operand 0. Both operands have mode @var{m},
5836 which is a scalar or vector floating-point mode.
5838 This pattern is not allowed to @code{FAIL}.
5840 @cindex @code{expm1@var{m}2} instruction pattern
5841 @item @samp{expm1@var{m}2}
5842 Raise e (the base of natural logarithms) to the power of operand 1,
5843 subtract 1, and store the result in operand 0. Both operands have
5844 mode @var{m}, which is a scalar or vector floating-point mode.
5846 For inputs close to zero, the pattern is expected to be more
5847 accurate than a separate @code{exp@var{m}2} and @code{sub@var{m}3}
5850 This pattern is not allowed to @code{FAIL}.
5852 @cindex @code{exp10@var{m}2} instruction pattern
5853 @item @samp{exp10@var{m}2}
5854 Raise 10 to the power of operand 1 and store the result in operand 0.
5855 Both operands have mode @var{m}, which is a scalar or vector
5856 floating-point mode.
5858 This pattern is not allowed to @code{FAIL}.
5860 @cindex @code{exp2@var{m}2} instruction pattern
5861 @item @samp{exp2@var{m}2}
5862 Raise 2 to the power of operand 1 and store the result in operand 0.
5863 Both operands have mode @var{m}, which is a scalar or vector
5864 floating-point mode.
5866 This pattern is not allowed to @code{FAIL}.
5868 @cindex @code{log@var{m}2} instruction pattern
5869 @item @samp{log@var{m}2}
5870 Store the natural logarithm of operand 1 into operand 0. Both operands
5871 have mode @var{m}, which is a scalar or vector floating-point mode.
5873 This pattern is not allowed to @code{FAIL}.
5875 @cindex @code{log1p@var{m}2} instruction pattern
5876 @item @samp{log1p@var{m}2}
5877 Add 1 to operand 1, compute the natural logarithm, and store
5878 the result in operand 0. Both operands have mode @var{m}, which is
5879 a scalar or vector floating-point mode.
5881 For inputs close to zero, the pattern is expected to be more
5882 accurate than a separate @code{add@var{m}3} and @code{log@var{m}2}
5885 This pattern is not allowed to @code{FAIL}.
5887 @cindex @code{log10@var{m}2} instruction pattern
5888 @item @samp{log10@var{m}2}
5889 Store the base-10 logarithm of operand 1 into operand 0. Both operands
5890 have mode @var{m}, which is a scalar or vector floating-point mode.
5892 This pattern is not allowed to @code{FAIL}.
5894 @cindex @code{log2@var{m}2} instruction pattern
5895 @item @samp{log2@var{m}2}
5896 Store the base-2 logarithm of operand 1 into operand 0. Both operands
5897 have mode @var{m}, which is a scalar or vector floating-point mode.
5899 This pattern is not allowed to @code{FAIL}.
5901 @cindex @code{logb@var{m}2} instruction pattern
5902 @item @samp{logb@var{m}2}
5903 Store the base-@code{FLT_RADIX} logarithm of operand 1 into operand 0.
5904 Both operands have mode @var{m}, which is a scalar or vector
5905 floating-point mode.
5907 This pattern is not allowed to @code{FAIL}.
5909 @cindex @code{significand@var{m}2} instruction pattern
5910 @item @samp{significand@var{m}2}
5911 Store the significand of floating-point operand 1 in operand 0.
5912 Both operands have mode @var{m}, which is a scalar or vector
5913 floating-point mode.
5915 This pattern is not allowed to @code{FAIL}.
5917 @cindex @code{pow@var{m}3} instruction pattern
5918 @item @samp{pow@var{m}3}
5919 Store the value of operand 1 raised to the exponent operand 2
5920 into operand 0. All operands have mode @var{m}, which is a scalar
5921 or vector floating-point mode.
5923 This pattern is not allowed to @code{FAIL}.
5925 @cindex @code{atan2@var{m}3} instruction pattern
5926 @item @samp{atan2@var{m}3}
5927 Store the arc tangent (inverse tangent) of operand 1 divided by
5928 operand 2 into operand 0, using the signs of both arguments to
5929 determine the quadrant of the result. All operands have mode
5930 @var{m}, which is a scalar or vector floating-point mode.
5932 This pattern is not allowed to @code{FAIL}.
5934 @cindex @code{floor@var{m}2} instruction pattern
5935 @item @samp{floor@var{m}2}
5936 Store the largest integral value not greater than operand 1 in operand 0.
5937 Both operands have mode @var{m}, which is a scalar or vector
5938 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
5939 effect, the ``inexact'' exception may be raised for noninteger
5940 operands; otherwise, it may not.
5942 This pattern is not allowed to @code{FAIL}.
5944 @cindex @code{btrunc@var{m}2} instruction pattern
5945 @item @samp{btrunc@var{m}2}
5946 Round operand 1 to an integer, towards zero, and store the result in
5947 operand 0. Both operands have mode @var{m}, which is a scalar or
5948 vector floating-point mode. If @option{-ffp-int-builtin-inexact} is
5949 in effect, the ``inexact'' exception may be raised for noninteger
5950 operands; otherwise, it may not.
5952 This pattern is not allowed to @code{FAIL}.
5954 @cindex @code{round@var{m}2} instruction pattern
5955 @item @samp{round@var{m}2}
5956 Round operand 1 to the nearest integer, rounding away from zero in the
5957 event of a tie, and store the result in operand 0. Both operands have
5958 mode @var{m}, which is a scalar or vector floating-point mode. If
5959 @option{-ffp-int-builtin-inexact} is in effect, the ``inexact''
5960 exception may be raised for noninteger operands; otherwise, it may
5963 This pattern is not allowed to @code{FAIL}.
5965 @cindex @code{ceil@var{m}2} instruction pattern
5966 @item @samp{ceil@var{m}2}
5967 Store the smallest integral value not less than operand 1 in operand 0.
5968 Both operands have mode @var{m}, which is a scalar or vector
5969 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
5970 effect, the ``inexact'' exception may be raised for noninteger
5971 operands; otherwise, it may not.
5973 This pattern is not allowed to @code{FAIL}.
5975 @cindex @code{nearbyint@var{m}2} instruction pattern
5976 @item @samp{nearbyint@var{m}2}
5977 Round operand 1 to an integer, using the current rounding mode, and
5978 store the result in operand 0. Do not raise an inexact condition when
5979 the result is different from the argument. Both operands have mode
5980 @var{m}, which is a scalar or vector floating-point mode.
5982 This pattern is not allowed to @code{FAIL}.
5984 @cindex @code{rint@var{m}2} instruction pattern
5985 @item @samp{rint@var{m}2}
5986 Round operand 1 to an integer, using the current rounding mode, and
5987 store the result in operand 0. Raise an inexact condition when
5988 the result is different from the argument. Both operands have mode
5989 @var{m}, which is a scalar or vector floating-point mode.
5991 This pattern is not allowed to @code{FAIL}.
5993 @cindex @code{lrint@var{m}@var{n}2}
5994 @item @samp{lrint@var{m}@var{n}2}
5995 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5996 point mode @var{n} as a signed number according to the current
5997 rounding mode and store in operand 0 (which has mode @var{n}).
5999 @cindex @code{lround@var{m}@var{n}2}
6000 @item @samp{lround@var{m}@var{n}2}
6001 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6002 point mode @var{n} as a signed number rounding to nearest and away
6003 from zero and store in operand 0 (which has mode @var{n}).
6005 @cindex @code{lfloor@var{m}@var{n}2}
6006 @item @samp{lfloor@var{m}@var{n}2}
6007 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6008 point mode @var{n} as a signed number rounding down and store in
6009 operand 0 (which has mode @var{n}).
6011 @cindex @code{lceil@var{m}@var{n}2}
6012 @item @samp{lceil@var{m}@var{n}2}
6013 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6014 point mode @var{n} as a signed number rounding up and store in
6015 operand 0 (which has mode @var{n}).
6017 @cindex @code{copysign@var{m}3} instruction pattern
6018 @item @samp{copysign@var{m}3}
6019 Store a value with the magnitude of operand 1 and the sign of operand
6020 2 into operand 0. All operands have mode @var{m}, which is a scalar or
6021 vector floating-point mode.
6023 This pattern is not allowed to @code{FAIL}.
6025 @cindex @code{ffs@var{m}2} instruction pattern
6026 @item @samp{ffs@var{m}2}
6027 Store into operand 0 one plus the index of the least significant 1-bit
6028 of operand 1. If operand 1 is zero, store zero.
6030 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6031 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6032 integer mode is suitable for the target. The compiler will insert
6033 conversion instructions as necessary (typically to convert the result
6034 to the same width as @code{int}). When @var{m} is a vector, both
6035 operands must have mode @var{m}.
6037 This pattern is not allowed to @code{FAIL}.
6039 @cindex @code{clrsb@var{m}2} instruction pattern
6040 @item @samp{clrsb@var{m}2}
6041 Count leading redundant sign bits.
6042 Store into operand 0 the number of redundant sign bits in operand 1, starting
6043 at the most significant bit position.
6044 A redundant sign bit is defined as any sign bit after the first. As such,
6045 this count will be one less than the count of leading sign bits.
6047 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6048 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6049 integer mode is suitable for the target. The compiler will insert
6050 conversion instructions as necessary (typically to convert the result
6051 to the same width as @code{int}). When @var{m} is a vector, both
6052 operands must have mode @var{m}.
6054 This pattern is not allowed to @code{FAIL}.
6056 @cindex @code{clz@var{m}2} instruction pattern
6057 @item @samp{clz@var{m}2}
6058 Store into operand 0 the number of leading 0-bits in operand 1, starting
6059 at the most significant bit position. If operand 1 is 0, the
6060 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
6061 the result is undefined or has a useful value.
6063 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6064 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6065 integer mode is suitable for the target. The compiler will insert
6066 conversion instructions as necessary (typically to convert the result
6067 to the same width as @code{int}). When @var{m} is a vector, both
6068 operands must have mode @var{m}.
6070 This pattern is not allowed to @code{FAIL}.
6072 @cindex @code{ctz@var{m}2} instruction pattern
6073 @item @samp{ctz@var{m}2}
6074 Store into operand 0 the number of trailing 0-bits in operand 1, starting
6075 at the least significant bit position. If operand 1 is 0, the
6076 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
6077 the result is undefined or has a useful value.
6079 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6080 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6081 integer mode is suitable for the target. The compiler will insert
6082 conversion instructions as necessary (typically to convert the result
6083 to the same width as @code{int}). When @var{m} is a vector, both
6084 operands must have mode @var{m}.
6086 This pattern is not allowed to @code{FAIL}.
6088 @cindex @code{popcount@var{m}2} instruction pattern
6089 @item @samp{popcount@var{m}2}
6090 Store into operand 0 the number of 1-bits in operand 1.
6092 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6093 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6094 integer mode is suitable for the target. The compiler will insert
6095 conversion instructions as necessary (typically to convert the result
6096 to the same width as @code{int}). When @var{m} is a vector, both
6097 operands must have mode @var{m}.
6099 This pattern is not allowed to @code{FAIL}.
6101 @cindex @code{parity@var{m}2} instruction pattern
6102 @item @samp{parity@var{m}2}
6103 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
6104 in operand 1 modulo 2.
6106 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6107 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6108 integer mode is suitable for the target. The compiler will insert
6109 conversion instructions as necessary (typically to convert the result
6110 to the same width as @code{int}). When @var{m} is a vector, both
6111 operands must have mode @var{m}.
6113 This pattern is not allowed to @code{FAIL}.
6115 @cindex @code{one_cmpl@var{m}2} instruction pattern
6116 @item @samp{one_cmpl@var{m}2}
6117 Store the bitwise-complement of operand 1 into operand 0.
6119 @cindex @code{movmem@var{m}} instruction pattern
6120 @item @samp{movmem@var{m}}
6121 Block move instruction. The destination and source blocks of memory
6122 are the first two operands, and both are @code{mem:BLK}s with an
6123 address in mode @code{Pmode}.
6125 The number of bytes to move is the third operand, in mode @var{m}.
6126 Usually, you specify @code{Pmode} for @var{m}. However, if you can
6127 generate better code knowing the range of valid lengths is smaller than
6128 those representable in a full Pmode pointer, you should provide
6130 mode corresponding to the range of values you can handle efficiently
6131 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
6132 that appear negative) and also a pattern with @code{Pmode}.
6134 The fourth operand is the known shared alignment of the source and
6135 destination, in the form of a @code{const_int} rtx. Thus, if the
6136 compiler knows that both source and destination are word-aligned,
6137 it may provide the value 4 for this operand.
6139 Optional operands 5 and 6 specify expected alignment and size of block
6140 respectively. The expected alignment differs from alignment in operand 4
6141 in a way that the blocks are not required to be aligned according to it in
6142 all cases. This expected alignment is also in bytes, just like operand 4.
6143 Expected size, when unknown, is set to @code{(const_int -1)}.
6145 Descriptions of multiple @code{movmem@var{m}} patterns can only be
6146 beneficial if the patterns for smaller modes have fewer restrictions
6147 on their first, second and fourth operands. Note that the mode @var{m}
6148 in @code{movmem@var{m}} does not impose any restriction on the mode of
6149 individually moved data units in the block.
6151 These patterns need not give special consideration to the possibility
6152 that the source and destination strings might overlap.
6154 @cindex @code{movstr} instruction pattern
6156 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
6157 an output operand in mode @code{Pmode}. The addresses of the
6158 destination and source strings are operands 1 and 2, and both are
6159 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
6160 the expansion of this pattern should store in operand 0 the address in
6161 which the @code{NUL} terminator was stored in the destination string.
6163 This patern has also several optional operands that are same as in
6166 @cindex @code{setmem@var{m}} instruction pattern
6167 @item @samp{setmem@var{m}}
6168 Block set instruction. The destination string is the first operand,
6169 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
6170 number of bytes to set is the second operand, in mode @var{m}. The value to
6171 initialize the memory with is the third operand. Targets that only support the
6172 clearing of memory should reject any value that is not the constant 0. See
6173 @samp{movmem@var{m}} for a discussion of the choice of mode.
6175 The fourth operand is the known alignment of the destination, in the form
6176 of a @code{const_int} rtx. Thus, if the compiler knows that the
6177 destination is word-aligned, it may provide the value 4 for this
6180 Optional operands 5 and 6 specify expected alignment and size of block
6181 respectively. The expected alignment differs from alignment in operand 4
6182 in a way that the blocks are not required to be aligned according to it in
6183 all cases. This expected alignment is also in bytes, just like operand 4.
6184 Expected size, when unknown, is set to @code{(const_int -1)}.
6185 Operand 7 is the minimal size of the block and operand 8 is the
6186 maximal size of the block (NULL if it can not be represented as CONST_INT).
6187 Operand 9 is the probable maximal size (i.e.@: we can not rely on it for
6188 correctness, but it can be used for choosing proper code sequence for a
6191 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
6193 @cindex @code{cmpstrn@var{m}} instruction pattern
6194 @item @samp{cmpstrn@var{m}}
6195 String compare instruction, with five operands. Operand 0 is the output;
6196 it has mode @var{m}. The remaining four operands are like the operands
6197 of @samp{movmem@var{m}}. The two memory blocks specified are compared
6198 byte by byte in lexicographic order starting at the beginning of each
6199 string. The instruction is not allowed to prefetch more than one byte
6200 at a time since either string may end in the first byte and reading past
6201 that may access an invalid page or segment and cause a fault. The
6202 comparison terminates early if the fetched bytes are different or if
6203 they are equal to zero. The effect of the instruction is to store a
6204 value in operand 0 whose sign indicates the result of the comparison.
6206 @cindex @code{cmpstr@var{m}} instruction pattern
6207 @item @samp{cmpstr@var{m}}
6208 String compare instruction, without known maximum length. Operand 0 is the
6209 output; it has mode @var{m}. The second and third operand are the blocks of
6210 memory to be compared; both are @code{mem:BLK} with an address in mode
6213 The fourth operand is the known shared alignment of the source and
6214 destination, in the form of a @code{const_int} rtx. Thus, if the
6215 compiler knows that both source and destination are word-aligned,
6216 it may provide the value 4 for this operand.
6218 The two memory blocks specified are compared byte by byte in lexicographic
6219 order starting at the beginning of each string. The instruction is not allowed
6220 to prefetch more than one byte at a time since either string may end in the
6221 first byte and reading past that may access an invalid page or segment and
6222 cause a fault. The comparison will terminate when the fetched bytes
6223 are different or if they are equal to zero. The effect of the
6224 instruction is to store a value in operand 0 whose sign indicates the
6225 result of the comparison.
6227 @cindex @code{cmpmem@var{m}} instruction pattern
6228 @item @samp{cmpmem@var{m}}
6229 Block compare instruction, with five operands like the operands
6230 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
6231 byte by byte in lexicographic order starting at the beginning of each
6232 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
6233 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
6234 the comparison will not stop if both bytes are zero. The effect of
6235 the instruction is to store a value in operand 0 whose sign indicates
6236 the result of the comparison.
6238 @cindex @code{strlen@var{m}} instruction pattern
6239 @item @samp{strlen@var{m}}
6240 Compute the length of a string, with three operands.
6241 Operand 0 is the result (of mode @var{m}), operand 1 is
6242 a @code{mem} referring to the first character of the string,
6243 operand 2 is the character to search for (normally zero),
6244 and operand 3 is a constant describing the known alignment
6245 of the beginning of the string.
6247 @cindex @code{float@var{m}@var{n}2} instruction pattern
6248 @item @samp{float@var{m}@var{n}2}
6249 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
6250 floating point mode @var{n} and store in operand 0 (which has mode
6253 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
6254 @item @samp{floatuns@var{m}@var{n}2}
6255 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
6256 to floating point mode @var{n} and store in operand 0 (which has mode
6259 @cindex @code{fix@var{m}@var{n}2} instruction pattern
6260 @item @samp{fix@var{m}@var{n}2}
6261 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6262 point mode @var{n} as a signed number and store in operand 0 (which
6263 has mode @var{n}). This instruction's result is defined only when
6264 the value of operand 1 is an integer.
6266 If the machine description defines this pattern, it also needs to
6267 define the @code{ftrunc} pattern.
6269 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
6270 @item @samp{fixuns@var{m}@var{n}2}
6271 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6272 point mode @var{n} as an unsigned number and store in operand 0 (which
6273 has mode @var{n}). This instruction's result is defined only when the
6274 value of operand 1 is an integer.
6276 @cindex @code{ftrunc@var{m}2} instruction pattern
6277 @item @samp{ftrunc@var{m}2}
6278 Convert operand 1 (valid for floating point mode @var{m}) to an
6279 integer value, still represented in floating point mode @var{m}, and
6280 store it in operand 0 (valid for floating point mode @var{m}).
6282 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
6283 @item @samp{fix_trunc@var{m}@var{n}2}
6284 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
6285 of mode @var{m} by converting the value to an integer.
6287 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
6288 @item @samp{fixuns_trunc@var{m}@var{n}2}
6289 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
6290 value of mode @var{m} by converting the value to an integer.
6292 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
6293 @item @samp{trunc@var{m}@var{n}2}
6294 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
6295 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6296 point or both floating point.
6298 @cindex @code{extend@var{m}@var{n}2} instruction pattern
6299 @item @samp{extend@var{m}@var{n}2}
6300 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6301 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6302 point or both floating point.
6304 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
6305 @item @samp{zero_extend@var{m}@var{n}2}
6306 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6307 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6310 @cindex @code{fract@var{m}@var{n}2} instruction pattern
6311 @item @samp{fract@var{m}@var{n}2}
6312 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6313 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6314 could be fixed-point to fixed-point, signed integer to fixed-point,
6315 fixed-point to signed integer, floating-point to fixed-point,
6316 or fixed-point to floating-point.
6317 When overflows or underflows happen, the results are undefined.
6319 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
6320 @item @samp{satfract@var{m}@var{n}2}
6321 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6322 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6323 could be fixed-point to fixed-point, signed integer to fixed-point,
6324 or floating-point to fixed-point.
6325 When overflows or underflows happen, the instruction saturates the
6326 results to the maximum or the minimum.
6328 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
6329 @item @samp{fractuns@var{m}@var{n}2}
6330 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6331 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6332 could be unsigned integer to fixed-point, or
6333 fixed-point to unsigned integer.
6334 When overflows or underflows happen, the results are undefined.
6336 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
6337 @item @samp{satfractuns@var{m}@var{n}2}
6338 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
6339 @var{n} and store in operand 0 (which has mode @var{n}).
6340 When overflows or underflows happen, the instruction saturates the
6341 results to the maximum or the minimum.
6343 @cindex @code{extv@var{m}} instruction pattern
6344 @item @samp{extv@var{m}}
6345 Extract a bit-field from register operand 1, sign-extend it, and store
6346 it in operand 0. Operand 2 specifies the width of the field in bits
6347 and operand 3 the starting bit, which counts from the most significant
6348 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
6351 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
6352 target-specific mode.
6354 @cindex @code{extvmisalign@var{m}} instruction pattern
6355 @item @samp{extvmisalign@var{m}}
6356 Extract a bit-field from memory operand 1, sign extend it, and store
6357 it in operand 0. Operand 2 specifies the width in bits and operand 3
6358 the starting bit. The starting bit is always somewhere in the first byte of
6359 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6360 is true and from the least significant bit otherwise.
6362 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
6363 Operands 2 and 3 have a target-specific mode.
6365 The instruction must not read beyond the last byte of the bit-field.
6367 @cindex @code{extzv@var{m}} instruction pattern
6368 @item @samp{extzv@var{m}}
6369 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
6371 @cindex @code{extzvmisalign@var{m}} instruction pattern
6372 @item @samp{extzvmisalign@var{m}}
6373 Like @samp{extvmisalign@var{m}} except that the bit-field value is
6376 @cindex @code{insv@var{m}} instruction pattern
6377 @item @samp{insv@var{m}}
6378 Insert operand 3 into a bit-field of register operand 0. Operand 1
6379 specifies the width of the field in bits and operand 2 the starting bit,
6380 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6381 is true and from the least significant bit otherwise.
6383 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
6384 target-specific mode.
6386 @cindex @code{insvmisalign@var{m}} instruction pattern
6387 @item @samp{insvmisalign@var{m}}
6388 Insert operand 3 into a bit-field of memory operand 0. Operand 1
6389 specifies the width of the field in bits and operand 2 the starting bit.
6390 The starting bit is always somewhere in the first byte of operand 0;
6391 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6392 is true and from the least significant bit otherwise.
6394 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
6395 Operands 1 and 2 have a target-specific mode.
6397 The instruction must not read or write beyond the last byte of the bit-field.
6399 @cindex @code{extv} instruction pattern
6401 Extract a bit-field from operand 1 (a register or memory operand), where
6402 operand 2 specifies the width in bits and operand 3 the starting bit,
6403 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
6404 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
6405 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
6406 be valid for @code{word_mode}.
6408 The RTL generation pass generates this instruction only with constants
6409 for operands 2 and 3 and the constant is never zero for operand 2.
6411 The bit-field value is sign-extended to a full word integer
6412 before it is stored in operand 0.
6414 This pattern is deprecated; please use @samp{extv@var{m}} and
6415 @code{extvmisalign@var{m}} instead.
6417 @cindex @code{extzv} instruction pattern
6419 Like @samp{extv} except that the bit-field value is zero-extended.
6421 This pattern is deprecated; please use @samp{extzv@var{m}} and
6422 @code{extzvmisalign@var{m}} instead.
6424 @cindex @code{insv} instruction pattern
6426 Store operand 3 (which must be valid for @code{word_mode}) into a
6427 bit-field in operand 0, where operand 1 specifies the width in bits and
6428 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
6429 @code{word_mode}; often @code{word_mode} is allowed only for registers.
6430 Operands 1 and 2 must be valid for @code{word_mode}.
6432 The RTL generation pass generates this instruction only with constants
6433 for operands 1 and 2 and the constant is never zero for operand 1.
6435 This pattern is deprecated; please use @samp{insv@var{m}} and
6436 @code{insvmisalign@var{m}} instead.
6438 @cindex @code{mov@var{mode}cc} instruction pattern
6439 @item @samp{mov@var{mode}cc}
6440 Conditionally move operand 2 or operand 3 into operand 0 according to the
6441 comparison in operand 1. If the comparison is true, operand 2 is moved
6442 into operand 0, otherwise operand 3 is moved.
6444 The mode of the operands being compared need not be the same as the operands
6445 being moved. Some machines, sparc64 for example, have instructions that
6446 conditionally move an integer value based on the floating point condition
6447 codes and vice versa.
6449 If the machine does not have conditional move instructions, do not
6450 define these patterns.
6452 @cindex @code{add@var{mode}cc} instruction pattern
6453 @item @samp{add@var{mode}cc}
6454 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
6455 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
6456 comparison in operand 1. If the comparison is false, operand 2 is moved into
6457 operand 0, otherwise (operand 2 + operand 3) is moved.
6459 @cindex @code{cond_add@var{mode}} instruction pattern
6460 @cindex @code{cond_sub@var{mode}} instruction pattern
6461 @cindex @code{cond_mul@var{mode}} instruction pattern
6462 @cindex @code{cond_div@var{mode}} instruction pattern
6463 @cindex @code{cond_udiv@var{mode}} instruction pattern
6464 @cindex @code{cond_mod@var{mode}} instruction pattern
6465 @cindex @code{cond_umod@var{mode}} instruction pattern
6466 @cindex @code{cond_and@var{mode}} instruction pattern
6467 @cindex @code{cond_ior@var{mode}} instruction pattern
6468 @cindex @code{cond_xor@var{mode}} instruction pattern
6469 @cindex @code{cond_smin@var{mode}} instruction pattern
6470 @cindex @code{cond_smax@var{mode}} instruction pattern
6471 @cindex @code{cond_umin@var{mode}} instruction pattern
6472 @cindex @code{cond_umax@var{mode}} instruction pattern
6473 @item @samp{cond_add@var{mode}}
6474 @itemx @samp{cond_sub@var{mode}}
6475 @itemx @samp{cond_mul@var{mode}}
6476 @itemx @samp{cond_div@var{mode}}
6477 @itemx @samp{cond_udiv@var{mode}}
6478 @itemx @samp{cond_mod@var{mode}}
6479 @itemx @samp{cond_umod@var{mode}}
6480 @itemx @samp{cond_and@var{mode}}
6481 @itemx @samp{cond_ior@var{mode}}
6482 @itemx @samp{cond_xor@var{mode}}
6483 @itemx @samp{cond_smin@var{mode}}
6484 @itemx @samp{cond_smax@var{mode}}
6485 @itemx @samp{cond_umin@var{mode}}
6486 @itemx @samp{cond_umax@var{mode}}
6487 When operand 1 is true, perform an operation on operands 2 and 3 and
6488 store the result in operand 0, otherwise store operand 4 in operand 0.
6489 The operation works elementwise if the operands are vectors.
6491 The scalar case is equivalent to:
6494 op0 = op1 ? op2 @var{op} op3 : op4;
6497 while the vector case is equivalent to:
6500 for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
6501 op0[i] = op1[i] ? op2[i] @var{op} op3[i] : op4[i];
6504 where, for example, @var{op} is @code{+} for @samp{cond_add@var{mode}}.
6506 When defined for floating-point modes, the contents of @samp{op3[i]}
6507 are not interpreted if @var{op1[i]} is false, just like they would not
6508 be in a normal C @samp{?:} condition.
6510 Operands 0, 2, 3 and 4 all have mode @var{m}. Operand 1 is a scalar
6511 integer if @var{m} is scalar, otherwise it has the mode returned by
6512 @code{TARGET_VECTORIZE_GET_MASK_MODE}.
6514 @cindex @code{cond_fma@var{mode}} instruction pattern
6515 @cindex @code{cond_fms@var{mode}} instruction pattern
6516 @cindex @code{cond_fnma@var{mode}} instruction pattern
6517 @cindex @code{cond_fnms@var{mode}} instruction pattern
6518 @item @samp{cond_fma@var{mode}}
6519 @itemx @samp{cond_fms@var{mode}}
6520 @itemx @samp{cond_fnma@var{mode}}
6521 @itemx @samp{cond_fnms@var{mode}}
6522 Like @samp{cond_add@var{m}}, except that the conditional operation
6523 takes 3 operands rather than two. For example, the vector form of
6524 @samp{cond_fma@var{mode}} is equivalent to:
6527 for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
6528 op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i];
6531 @cindex @code{neg@var{mode}cc} instruction pattern
6532 @item @samp{neg@var{mode}cc}
6533 Similar to @samp{mov@var{mode}cc} but for conditional negation. Conditionally
6534 move the negation of operand 2 or the unchanged operand 3 into operand 0
6535 according to the comparison in operand 1. If the comparison is true, the negation
6536 of operand 2 is moved into operand 0, otherwise operand 3 is moved.
6538 @cindex @code{not@var{mode}cc} instruction pattern
6539 @item @samp{not@var{mode}cc}
6540 Similar to @samp{neg@var{mode}cc} but for conditional complement.
6541 Conditionally move the bitwise complement of operand 2 or the unchanged
6542 operand 3 into operand 0 according to the comparison in operand 1.
6543 If the comparison is true, the complement of operand 2 is moved into
6544 operand 0, otherwise operand 3 is moved.
6546 @cindex @code{cstore@var{mode}4} instruction pattern
6547 @item @samp{cstore@var{mode}4}
6548 Store zero or nonzero in operand 0 according to whether a comparison
6549 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
6550 are the first and second operand of the comparison, respectively.
6551 You specify the mode that operand 0 must have when you write the
6552 @code{match_operand} expression. The compiler automatically sees which
6553 mode you have used and supplies an operand of that mode.
6555 The value stored for a true condition must have 1 as its low bit, or
6556 else must be negative. Otherwise the instruction is not suitable and
6557 you should omit it from the machine description. You describe to the
6558 compiler exactly which value is stored by defining the macro
6559 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
6560 found that can be used for all the possible comparison operators, you
6561 should pick one and use a @code{define_expand} to map all results
6562 onto the one you chose.
6564 These operations may @code{FAIL}, but should do so only in relatively
6565 uncommon cases; if they would @code{FAIL} for common cases involving
6566 integer comparisons, it is best to restrict the predicates to not
6567 allow these operands. Likewise if a given comparison operator will
6568 always fail, independent of the operands (for floating-point modes, the
6569 @code{ordered_comparison_operator} predicate is often useful in this case).
6571 If this pattern is omitted, the compiler will generate a conditional
6572 branch---for example, it may copy a constant one to the target and branching
6573 around an assignment of zero to the target---or a libcall. If the predicate
6574 for operand 1 only rejects some operators, it will also try reordering the
6575 operands and/or inverting the result value (e.g.@: by an exclusive OR).
6576 These possibilities could be cheaper or equivalent to the instructions
6577 used for the @samp{cstore@var{mode}4} pattern followed by those required
6578 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
6579 case, you can and should make operand 1's predicate reject some operators
6580 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
6581 from the machine description.
6583 @cindex @code{cbranch@var{mode}4} instruction pattern
6584 @item @samp{cbranch@var{mode}4}
6585 Conditional branch instruction combined with a compare instruction.
6586 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
6587 first and second operands of the comparison, respectively. Operand 3
6588 is the @code{code_label} to jump to.
6590 @cindex @code{jump} instruction pattern
6592 A jump inside a function; an unconditional branch. Operand 0 is the
6593 @code{code_label} to jump to. This pattern name is mandatory on all
6596 @cindex @code{call} instruction pattern
6598 Subroutine call instruction returning no value. Operand 0 is the
6599 function to call; operand 1 is the number of bytes of arguments pushed
6600 as a @code{const_int}; operand 2 is the number of registers used as
6603 On most machines, operand 2 is not actually stored into the RTL
6604 pattern. It is supplied for the sake of some RISC machines which need
6605 to put this information into the assembler code; they can put it in
6606 the RTL instead of operand 1.
6608 Operand 0 should be a @code{mem} RTX whose address is the address of the
6609 function. Note, however, that this address can be a @code{symbol_ref}
6610 expression even if it would not be a legitimate memory address on the
6611 target machine. If it is also not a valid argument for a call
6612 instruction, the pattern for this operation should be a
6613 @code{define_expand} (@pxref{Expander Definitions}) that places the
6614 address into a register and uses that register in the call instruction.
6616 @cindex @code{call_value} instruction pattern
6617 @item @samp{call_value}
6618 Subroutine call instruction returning a value. Operand 0 is the hard
6619 register in which the value is returned. There are three more
6620 operands, the same as the three operands of the @samp{call}
6621 instruction (but with numbers increased by one).
6623 Subroutines that return @code{BLKmode} objects use the @samp{call}
6626 @cindex @code{call_pop} instruction pattern
6627 @cindex @code{call_value_pop} instruction pattern
6628 @item @samp{call_pop}, @samp{call_value_pop}
6629 Similar to @samp{call} and @samp{call_value}, except used if defined and
6630 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
6631 that contains both the function call and a @code{set} to indicate the
6632 adjustment made to the frame pointer.
6634 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
6635 patterns increases the number of functions for which the frame pointer
6636 can be eliminated, if desired.
6638 @cindex @code{untyped_call} instruction pattern
6639 @item @samp{untyped_call}
6640 Subroutine call instruction returning a value of any type. Operand 0 is
6641 the function to call; operand 1 is a memory location where the result of
6642 calling the function is to be stored; operand 2 is a @code{parallel}
6643 expression where each element is a @code{set} expression that indicates
6644 the saving of a function return value into the result block.
6646 This instruction pattern should be defined to support
6647 @code{__builtin_apply} on machines where special instructions are needed
6648 to call a subroutine with arbitrary arguments or to save the value
6649 returned. This instruction pattern is required on machines that have
6650 multiple registers that can hold a return value
6651 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
6653 @cindex @code{return} instruction pattern
6655 Subroutine return instruction. This instruction pattern name should be
6656 defined only if a single instruction can do all the work of returning
6659 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
6660 RTL generation phase. In this case it is to support machines where
6661 multiple instructions are usually needed to return from a function, but
6662 some class of functions only requires one instruction to implement a
6663 return. Normally, the applicable functions are those which do not need
6664 to save any registers or allocate stack space.
6666 It is valid for this pattern to expand to an instruction using
6667 @code{simple_return} if no epilogue is required.
6669 @cindex @code{simple_return} instruction pattern
6670 @item @samp{simple_return}
6671 Subroutine return instruction. This instruction pattern name should be
6672 defined only if a single instruction can do all the work of returning
6673 from a function on a path where no epilogue is required. This pattern
6674 is very similar to the @code{return} instruction pattern, but it is emitted
6675 only by the shrink-wrapping optimization on paths where the function
6676 prologue has not been executed, and a function return should occur without
6677 any of the effects of the epilogue. Additional uses may be introduced on
6678 paths where both the prologue and the epilogue have executed.
6680 @findex reload_completed
6681 @findex leaf_function_p
6682 For such machines, the condition specified in this pattern should only
6683 be true when @code{reload_completed} is nonzero and the function's
6684 epilogue would only be a single instruction. For machines with register
6685 windows, the routine @code{leaf_function_p} may be used to determine if
6686 a register window push is required.
6688 Machines that have conditional return instructions should define patterns
6694 (if_then_else (match_operator
6695 0 "comparison_operator"
6696 [(cc0) (const_int 0)])
6703 where @var{condition} would normally be the same condition specified on the
6704 named @samp{return} pattern.
6706 @cindex @code{untyped_return} instruction pattern
6707 @item @samp{untyped_return}
6708 Untyped subroutine return instruction. This instruction pattern should
6709 be defined to support @code{__builtin_return} on machines where special
6710 instructions are needed to return a value of any type.
6712 Operand 0 is a memory location where the result of calling a function
6713 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
6714 expression where each element is a @code{set} expression that indicates
6715 the restoring of a function return value from the result block.
6717 @cindex @code{nop} instruction pattern
6719 No-op instruction. This instruction pattern name should always be defined
6720 to output a no-op in assembler code. @code{(const_int 0)} will do as an
6723 @cindex @code{indirect_jump} instruction pattern
6724 @item @samp{indirect_jump}
6725 An instruction to jump to an address which is operand zero.
6726 This pattern name is mandatory on all machines.
6728 @cindex @code{casesi} instruction pattern
6730 Instruction to jump through a dispatch table, including bounds checking.
6731 This instruction takes five operands:
6735 The index to dispatch on, which has mode @code{SImode}.
6738 The lower bound for indices in the table, an integer constant.
6741 The total range of indices in the table---the largest index
6742 minus the smallest one (both inclusive).
6745 A label that precedes the table itself.
6748 A label to jump to if the index has a value outside the bounds.
6751 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
6752 @code{jump_table_data}. The number of elements in the table is one plus the
6753 difference between the upper bound and the lower bound.
6755 @cindex @code{tablejump} instruction pattern
6756 @item @samp{tablejump}
6757 Instruction to jump to a variable address. This is a low-level
6758 capability which can be used to implement a dispatch table when there
6759 is no @samp{casesi} pattern.
6761 This pattern requires two operands: the address or offset, and a label
6762 which should immediately precede the jump table. If the macro
6763 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
6764 operand is an offset which counts from the address of the table; otherwise,
6765 it is an absolute address to jump to. In either case, the first operand has
6768 The @samp{tablejump} insn is always the last insn before the jump
6769 table it uses. Its assembler code normally has no need to use the
6770 second operand, but you should incorporate it in the RTL pattern so
6771 that the jump optimizer will not delete the table as unreachable code.
6774 @cindex @code{doloop_end} instruction pattern
6775 @item @samp{doloop_end}
6776 Conditional branch instruction that decrements a register and
6777 jumps if the register is nonzero. Operand 0 is the register to
6778 decrement and test; operand 1 is the label to jump to if the
6779 register is nonzero.
6780 @xref{Looping Patterns}.
6782 This optional instruction pattern should be defined for machines with
6783 low-overhead looping instructions as the loop optimizer will try to
6784 modify suitable loops to utilize it. The target hook
6785 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
6786 low-overhead loops can be used.
6788 @cindex @code{doloop_begin} instruction pattern
6789 @item @samp{doloop_begin}
6790 Companion instruction to @code{doloop_end} required for machines that
6791 need to perform some initialization, such as loading a special counter
6792 register. Operand 1 is the associated @code{doloop_end} pattern and
6793 operand 0 is the register that it decrements.
6795 If initialization insns do not always need to be emitted, use a
6796 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
6798 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
6799 @item @samp{canonicalize_funcptr_for_compare}
6800 Canonicalize the function pointer in operand 1 and store the result
6803 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
6804 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
6805 and also has mode @code{Pmode}.
6807 Canonicalization of a function pointer usually involves computing
6808 the address of the function which would be called if the function
6809 pointer were used in an indirect call.
6811 Only define this pattern if function pointers on the target machine
6812 can have different values but still call the same function when
6813 used in an indirect call.
6815 @cindex @code{save_stack_block} instruction pattern
6816 @cindex @code{save_stack_function} instruction pattern
6817 @cindex @code{save_stack_nonlocal} instruction pattern
6818 @cindex @code{restore_stack_block} instruction pattern
6819 @cindex @code{restore_stack_function} instruction pattern
6820 @cindex @code{restore_stack_nonlocal} instruction pattern
6821 @item @samp{save_stack_block}
6822 @itemx @samp{save_stack_function}
6823 @itemx @samp{save_stack_nonlocal}
6824 @itemx @samp{restore_stack_block}
6825 @itemx @samp{restore_stack_function}
6826 @itemx @samp{restore_stack_nonlocal}
6827 Most machines save and restore the stack pointer by copying it to or
6828 from an object of mode @code{Pmode}. Do not define these patterns on
6831 Some machines require special handling for stack pointer saves and
6832 restores. On those machines, define the patterns corresponding to the
6833 non-standard cases by using a @code{define_expand} (@pxref{Expander
6834 Definitions}) that produces the required insns. The three types of
6835 saves and restores are:
6839 @samp{save_stack_block} saves the stack pointer at the start of a block
6840 that allocates a variable-sized object, and @samp{restore_stack_block}
6841 restores the stack pointer when the block is exited.
6844 @samp{save_stack_function} and @samp{restore_stack_function} do a
6845 similar job for the outermost block of a function and are used when the
6846 function allocates variable-sized objects or calls @code{alloca}. Only
6847 the epilogue uses the restored stack pointer, allowing a simpler save or
6848 restore sequence on some machines.
6851 @samp{save_stack_nonlocal} is used in functions that contain labels
6852 branched to by nested functions. It saves the stack pointer in such a
6853 way that the inner function can use @samp{restore_stack_nonlocal} to
6854 restore the stack pointer. The compiler generates code to restore the
6855 frame and argument pointer registers, but some machines require saving
6856 and restoring additional data such as register window information or
6857 stack backchains. Place insns in these patterns to save and restore any
6861 When saving the stack pointer, operand 0 is the save area and operand 1
6862 is the stack pointer. The mode used to allocate the save area defaults
6863 to @code{Pmode} but you can override that choice by defining the
6864 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
6865 specify an integral mode, or @code{VOIDmode} if no save area is needed
6866 for a particular type of save (either because no save is needed or
6867 because a machine-specific save area can be used). Operand 0 is the
6868 stack pointer and operand 1 is the save area for restore operations. If
6869 @samp{save_stack_block} is defined, operand 0 must not be
6870 @code{VOIDmode} since these saves can be arbitrarily nested.
6872 A save area is a @code{mem} that is at a constant offset from
6873 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
6874 nonlocal gotos and a @code{reg} in the other two cases.
6876 @cindex @code{allocate_stack} instruction pattern
6877 @item @samp{allocate_stack}
6878 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
6879 the stack pointer to create space for dynamically allocated data.
6881 Store the resultant pointer to this space into operand 0. If you
6882 are allocating space from the main stack, do this by emitting a
6883 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
6884 If you are allocating the space elsewhere, generate code to copy the
6885 location of the space to operand 0. In the latter case, you must
6886 ensure this space gets freed when the corresponding space on the main
6889 Do not define this pattern if all that must be done is the subtraction.
6890 Some machines require other operations such as stack probes or
6891 maintaining the back chain. Define this pattern to emit those
6892 operations in addition to updating the stack pointer.
6894 @cindex @code{check_stack} instruction pattern
6895 @item @samp{check_stack}
6896 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
6897 probing the stack, define this pattern to perform the needed check and signal
6898 an error if the stack has overflowed. The single operand is the address in
6899 the stack farthest from the current stack pointer that you need to validate.
6900 Normally, on platforms where this pattern is needed, you would obtain the
6901 stack limit from a global or thread-specific variable or register.
6903 @cindex @code{probe_stack_address} instruction pattern
6904 @item @samp{probe_stack_address}
6905 If stack checking (@pxref{Stack Checking}) can be done on your system by
6906 probing the stack but without the need to actually access it, define this
6907 pattern and signal an error if the stack has overflowed. The single operand
6908 is the memory address in the stack that needs to be probed.
6910 @cindex @code{probe_stack} instruction pattern
6911 @item @samp{probe_stack}
6912 If stack checking (@pxref{Stack Checking}) can be done on your system by
6913 probing the stack but doing it with a ``store zero'' instruction is not valid
6914 or optimal, define this pattern to do the probing differently and signal an
6915 error if the stack has overflowed. The single operand is the memory reference
6916 in the stack that needs to be probed.
6918 @cindex @code{nonlocal_goto} instruction pattern
6919 @item @samp{nonlocal_goto}
6920 Emit code to generate a non-local goto, e.g., a jump from one function
6921 to a label in an outer function. This pattern has four arguments,
6922 each representing a value to be used in the jump. The first
6923 argument is to be loaded into the frame pointer, the second is
6924 the address to branch to (code to dispatch to the actual label),
6925 the third is the address of a location where the stack is saved,
6926 and the last is the address of the label, to be placed in the
6927 location for the incoming static chain.
6929 On most machines you need not define this pattern, since GCC will
6930 already generate the correct code, which is to load the frame pointer
6931 and static chain, restore the stack (using the
6932 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
6933 to the dispatcher. You need only define this pattern if this code will
6934 not work on your machine.
6936 @cindex @code{nonlocal_goto_receiver} instruction pattern
6937 @item @samp{nonlocal_goto_receiver}
6938 This pattern, if defined, contains code needed at the target of a
6939 nonlocal goto after the code already generated by GCC@. You will not
6940 normally need to define this pattern. A typical reason why you might
6941 need this pattern is if some value, such as a pointer to a global table,
6942 must be restored when the frame pointer is restored. Note that a nonlocal
6943 goto only occurs within a unit-of-translation, so a global table pointer
6944 that is shared by all functions of a given module need not be restored.
6945 There are no arguments.
6947 @cindex @code{exception_receiver} instruction pattern
6948 @item @samp{exception_receiver}
6949 This pattern, if defined, contains code needed at the site of an
6950 exception handler that isn't needed at the site of a nonlocal goto. You
6951 will not normally need to define this pattern. A typical reason why you
6952 might need this pattern is if some value, such as a pointer to a global
6953 table, must be restored after control flow is branched to the handler of
6954 an exception. There are no arguments.
6956 @cindex @code{builtin_setjmp_setup} instruction pattern
6957 @item @samp{builtin_setjmp_setup}
6958 This pattern, if defined, contains additional code needed to initialize
6959 the @code{jmp_buf}. You will not normally need to define this pattern.
6960 A typical reason why you might need this pattern is if some value, such
6961 as a pointer to a global table, must be restored. Though it is
6962 preferred that the pointer value be recalculated if possible (given the
6963 address of a label for instance). The single argument is a pointer to
6964 the @code{jmp_buf}. Note that the buffer is five words long and that
6965 the first three are normally used by the generic mechanism.
6967 @cindex @code{builtin_setjmp_receiver} instruction pattern
6968 @item @samp{builtin_setjmp_receiver}
6969 This pattern, if defined, contains code needed at the site of a
6970 built-in setjmp that isn't needed at the site of a nonlocal goto. You
6971 will not normally need to define this pattern. A typical reason why you
6972 might need this pattern is if some value, such as a pointer to a global
6973 table, must be restored. It takes one argument, which is the label
6974 to which builtin_longjmp transferred control; this pattern may be emitted
6975 at a small offset from that label.
6977 @cindex @code{builtin_longjmp} instruction pattern
6978 @item @samp{builtin_longjmp}
6979 This pattern, if defined, performs the entire action of the longjmp.
6980 You will not normally need to define this pattern unless you also define
6981 @code{builtin_setjmp_setup}. The single argument is a pointer to the
6984 @cindex @code{eh_return} instruction pattern
6985 @item @samp{eh_return}
6986 This pattern, if defined, affects the way @code{__builtin_eh_return},
6987 and thence the call frame exception handling library routines, are
6988 built. It is intended to handle non-trivial actions needed along
6989 the abnormal return path.
6991 The address of the exception handler to which the function should return
6992 is passed as operand to this pattern. It will normally need to copied by
6993 the pattern to some special register or memory location.
6994 If the pattern needs to determine the location of the target call
6995 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
6996 if defined; it will have already been assigned.
6998 If this pattern is not defined, the default action will be to simply
6999 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
7000 that macro or this pattern needs to be defined if call frame exception
7001 handling is to be used.
7003 @cindex @code{prologue} instruction pattern
7004 @anchor{prologue instruction pattern}
7005 @item @samp{prologue}
7006 This pattern, if defined, emits RTL for entry to a function. The function
7007 entry is responsible for setting up the stack frame, initializing the frame
7008 pointer register, saving callee saved registers, etc.
7010 Using a prologue pattern is generally preferred over defining
7011 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
7013 The @code{prologue} pattern is particularly useful for targets which perform
7014 instruction scheduling.
7016 @cindex @code{window_save} instruction pattern
7017 @anchor{window_save instruction pattern}
7018 @item @samp{window_save}
7019 This pattern, if defined, emits RTL for a register window save. It should
7020 be defined if the target machine has register windows but the window events
7021 are decoupled from calls to subroutines. The canonical example is the SPARC
7024 @cindex @code{epilogue} instruction pattern
7025 @anchor{epilogue instruction pattern}
7026 @item @samp{epilogue}
7027 This pattern emits RTL for exit from a function. The function
7028 exit is responsible for deallocating the stack frame, restoring callee saved
7029 registers and emitting the return instruction.
7031 Using an epilogue pattern is generally preferred over defining
7032 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
7034 The @code{epilogue} pattern is particularly useful for targets which perform
7035 instruction scheduling or which have delay slots for their return instruction.
7037 @cindex @code{sibcall_epilogue} instruction pattern
7038 @item @samp{sibcall_epilogue}
7039 This pattern, if defined, emits RTL for exit from a function without the final
7040 branch back to the calling function. This pattern will be emitted before any
7041 sibling call (aka tail call) sites.
7043 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
7044 parameter passing or any stack slots for arguments passed to the current
7047 @cindex @code{trap} instruction pattern
7049 This pattern, if defined, signals an error, typically by causing some
7050 kind of signal to be raised.
7052 @cindex @code{ctrap@var{MM}4} instruction pattern
7053 @item @samp{ctrap@var{MM}4}
7054 Conditional trap instruction. Operand 0 is a piece of RTL which
7055 performs a comparison, and operands 1 and 2 are the arms of the
7056 comparison. Operand 3 is the trap code, an integer.
7058 A typical @code{ctrap} pattern looks like
7061 (define_insn "ctrapsi4"
7062 [(trap_if (match_operator 0 "trap_operator"
7063 [(match_operand 1 "register_operand")
7064 (match_operand 2 "immediate_operand")])
7065 (match_operand 3 "const_int_operand" "i"))]
7070 @cindex @code{prefetch} instruction pattern
7071 @item @samp{prefetch}
7072 This pattern, if defined, emits code for a non-faulting data prefetch
7073 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
7074 is a constant 1 if the prefetch is preparing for a write to the memory
7075 address, or a constant 0 otherwise. Operand 2 is the expected degree of
7076 temporal locality of the data and is a value between 0 and 3, inclusive; 0
7077 means that the data has no temporal locality, so it need not be left in the
7078 cache after the access; 3 means that the data has a high degree of temporal
7079 locality and should be left in all levels of cache possible; 1 and 2 mean,
7080 respectively, a low or moderate degree of temporal locality.
7082 Targets that do not support write prefetches or locality hints can ignore
7083 the values of operands 1 and 2.
7085 @cindex @code{blockage} instruction pattern
7086 @item @samp{blockage}
7087 This pattern defines a pseudo insn that prevents the instruction
7088 scheduler and other passes from moving instructions and using register
7089 equivalences across the boundary defined by the blockage insn.
7090 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
7092 @cindex @code{memory_blockage} instruction pattern
7093 @item @samp{memory_blockage}
7094 This pattern, if defined, represents a compiler memory barrier, and will be
7095 placed at points across which RTL passes may not propagate memory accesses.
7096 This instruction needs to read and write volatile BLKmode memory. It does
7097 not need to generate any machine instruction. If this pattern is not defined,
7098 the compiler falls back to emitting an instruction corresponding
7099 to @code{asm volatile ("" ::: "memory")}.
7101 @cindex @code{memory_barrier} instruction pattern
7102 @item @samp{memory_barrier}
7103 If the target memory model is not fully synchronous, then this pattern
7104 should be defined to an instruction that orders both loads and stores
7105 before the instruction with respect to loads and stores after the instruction.
7106 This pattern has no operands.
7108 @cindex @code{speculation_barrier} instruction pattern
7109 @item @samp{speculation_barrier}
7110 If the target can support speculative execution, then this pattern should
7111 be defined to an instruction that will block subsequent execution until
7112 any prior speculation conditions has been resolved. The pattern must also
7113 ensure that the compiler cannot move memory operations past the barrier,
7114 so it needs to be an UNSPEC_VOLATILE pattern. The pattern has no
7117 If this pattern is not defined then the default expansion of
7118 @code{__builtin_speculation_safe_value} will emit a warning. You can
7119 suppress this warning by defining this pattern with a final condition
7120 of @code{0} (zero), which tells the compiler that a speculation
7121 barrier is not needed for this target.
7123 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
7124 @item @samp{sync_compare_and_swap@var{mode}}
7125 This pattern, if defined, emits code for an atomic compare-and-swap
7126 operation. Operand 1 is the memory on which the atomic operation is
7127 performed. Operand 2 is the ``old'' value to be compared against the
7128 current contents of the memory location. Operand 3 is the ``new'' value
7129 to store in the memory if the compare succeeds. Operand 0 is the result
7130 of the operation; it should contain the contents of the memory
7131 before the operation. If the compare succeeds, this should obviously be
7132 a copy of operand 2.
7134 This pattern must show that both operand 0 and operand 1 are modified.
7136 This pattern must issue any memory barrier instructions such that all
7137 memory operations before the atomic operation occur before the atomic
7138 operation and all memory operations after the atomic operation occur
7139 after the atomic operation.
7141 For targets where the success or failure of the compare-and-swap
7142 operation is available via the status flags, it is possible to
7143 avoid a separate compare operation and issue the subsequent
7144 branch or store-flag operation immediately after the compare-and-swap.
7145 To this end, GCC will look for a @code{MODE_CC} set in the
7146 output of @code{sync_compare_and_swap@var{mode}}; if the machine
7147 description includes such a set, the target should also define special
7148 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
7149 be able to take the destination of the @code{MODE_CC} set and pass it
7150 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
7151 operand of the comparison (the second will be @code{(const_int 0)}).
7153 For targets where the operating system may provide support for this
7154 operation via library calls, the @code{sync_compare_and_swap_optab}
7155 may be initialized to a function with the same interface as the
7156 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
7157 set of @var{__sync} builtins are supported via library calls, the
7158 target can initialize all of the optabs at once with
7159 @code{init_sync_libfuncs}.
7160 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
7161 assumed that these library calls do @emph{not} use any kind of
7162 interruptable locking.
7164 @cindex @code{sync_add@var{mode}} instruction pattern
7165 @cindex @code{sync_sub@var{mode}} instruction pattern
7166 @cindex @code{sync_ior@var{mode}} instruction pattern
7167 @cindex @code{sync_and@var{mode}} instruction pattern
7168 @cindex @code{sync_xor@var{mode}} instruction pattern
7169 @cindex @code{sync_nand@var{mode}} instruction pattern
7170 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
7171 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
7172 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
7173 These patterns emit code for an atomic operation on memory.
7174 Operand 0 is the memory on which the atomic operation is performed.
7175 Operand 1 is the second operand to the binary operator.
7177 This pattern must issue any memory barrier instructions such that all
7178 memory operations before the atomic operation occur before the atomic
7179 operation and all memory operations after the atomic operation occur
7180 after the atomic operation.
7182 If these patterns are not defined, the operation will be constructed
7183 from a compare-and-swap operation, if defined.
7185 @cindex @code{sync_old_add@var{mode}} instruction pattern
7186 @cindex @code{sync_old_sub@var{mode}} instruction pattern
7187 @cindex @code{sync_old_ior@var{mode}} instruction pattern
7188 @cindex @code{sync_old_and@var{mode}} instruction pattern
7189 @cindex @code{sync_old_xor@var{mode}} instruction pattern
7190 @cindex @code{sync_old_nand@var{mode}} instruction pattern
7191 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
7192 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
7193 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
7194 These patterns emit code for an atomic operation on memory,
7195 and return the value that the memory contained before the operation.
7196 Operand 0 is the result value, operand 1 is the memory on which the
7197 atomic operation is performed, and operand 2 is the second operand
7198 to the binary operator.
7200 This pattern must issue any memory barrier instructions such that all
7201 memory operations before the atomic operation occur before the atomic
7202 operation and all memory operations after the atomic operation occur
7203 after the atomic operation.
7205 If these patterns are not defined, the operation will be constructed
7206 from a compare-and-swap operation, if defined.
7208 @cindex @code{sync_new_add@var{mode}} instruction pattern
7209 @cindex @code{sync_new_sub@var{mode}} instruction pattern
7210 @cindex @code{sync_new_ior@var{mode}} instruction pattern
7211 @cindex @code{sync_new_and@var{mode}} instruction pattern
7212 @cindex @code{sync_new_xor@var{mode}} instruction pattern
7213 @cindex @code{sync_new_nand@var{mode}} instruction pattern
7214 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
7215 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
7216 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
7217 These patterns are like their @code{sync_old_@var{op}} counterparts,
7218 except that they return the value that exists in the memory location
7219 after the operation, rather than before the operation.
7221 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
7222 @item @samp{sync_lock_test_and_set@var{mode}}
7223 This pattern takes two forms, based on the capabilities of the target.
7224 In either case, operand 0 is the result of the operand, operand 1 is
7225 the memory on which the atomic operation is performed, and operand 2
7226 is the value to set in the lock.
7228 In the ideal case, this operation is an atomic exchange operation, in
7229 which the previous value in memory operand is copied into the result
7230 operand, and the value operand is stored in the memory operand.
7232 For less capable targets, any value operand that is not the constant 1
7233 should be rejected with @code{FAIL}. In this case the target may use
7234 an atomic test-and-set bit operation. The result operand should contain
7235 1 if the bit was previously set and 0 if the bit was previously clear.
7236 The true contents of the memory operand are implementation defined.
7238 This pattern must issue any memory barrier instructions such that the
7239 pattern as a whole acts as an acquire barrier, that is all memory
7240 operations after the pattern do not occur until the lock is acquired.
7242 If this pattern is not defined, the operation will be constructed from
7243 a compare-and-swap operation, if defined.
7245 @cindex @code{sync_lock_release@var{mode}} instruction pattern
7246 @item @samp{sync_lock_release@var{mode}}
7247 This pattern, if defined, releases a lock set by
7248 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
7249 that contains the lock; operand 1 is the value to store in the lock.
7251 If the target doesn't implement full semantics for
7252 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
7253 the constant 0 should be rejected with @code{FAIL}, and the true contents
7254 of the memory operand are implementation defined.
7256 This pattern must issue any memory barrier instructions such that the
7257 pattern as a whole acts as a release barrier, that is the lock is
7258 released only after all previous memory operations have completed.
7260 If this pattern is not defined, then a @code{memory_barrier} pattern
7261 will be emitted, followed by a store of the value to the memory operand.
7263 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
7264 @item @samp{atomic_compare_and_swap@var{mode}}
7265 This pattern, if defined, emits code for an atomic compare-and-swap
7266 operation with memory model semantics. Operand 2 is the memory on which
7267 the atomic operation is performed. Operand 0 is an output operand which
7268 is set to true or false based on whether the operation succeeded. Operand
7269 1 is an output operand which is set to the contents of the memory before
7270 the operation was attempted. Operand 3 is the value that is expected to
7271 be in memory. Operand 4 is the value to put in memory if the expected
7272 value is found there. Operand 5 is set to 1 if this compare and swap is to
7273 be treated as a weak operation. Operand 6 is the memory model to be used
7274 if the operation is a success. Operand 7 is the memory model to be used
7275 if the operation fails.
7277 If memory referred to in operand 2 contains the value in operand 3, then
7278 operand 4 is stored in memory pointed to by operand 2 and fencing based on
7279 the memory model in operand 6 is issued.
7281 If memory referred to in operand 2 does not contain the value in operand 3,
7282 then fencing based on the memory model in operand 7 is issued.
7284 If a target does not support weak compare-and-swap operations, or the port
7285 elects not to implement weak operations, the argument in operand 5 can be
7286 ignored. Note a strong implementation must be provided.
7288 If this pattern is not provided, the @code{__atomic_compare_exchange}
7289 built-in functions will utilize the legacy @code{sync_compare_and_swap}
7290 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
7292 @cindex @code{atomic_load@var{mode}} instruction pattern
7293 @item @samp{atomic_load@var{mode}}
7294 This pattern implements an atomic load operation with memory model
7295 semantics. Operand 1 is the memory address being loaded from. Operand 0
7296 is the result of the load. Operand 2 is the memory model to be used for
7299 If not present, the @code{__atomic_load} built-in function will either
7300 resort to a normal load with memory barriers, or a compare-and-swap
7301 operation if a normal load would not be atomic.
7303 @cindex @code{atomic_store@var{mode}} instruction pattern
7304 @item @samp{atomic_store@var{mode}}
7305 This pattern implements an atomic store operation with memory model
7306 semantics. Operand 0 is the memory address being stored to. Operand 1
7307 is the value to be written. Operand 2 is the memory model to be used for
7310 If not present, the @code{__atomic_store} built-in function will attempt to
7311 perform a normal store and surround it with any required memory fences. If
7312 the store would not be atomic, then an @code{__atomic_exchange} is
7313 attempted with the result being ignored.
7315 @cindex @code{atomic_exchange@var{mode}} instruction pattern
7316 @item @samp{atomic_exchange@var{mode}}
7317 This pattern implements an atomic exchange operation with memory model
7318 semantics. Operand 1 is the memory location the operation is performed on.
7319 Operand 0 is an output operand which is set to the original value contained
7320 in the memory pointed to by operand 1. Operand 2 is the value to be
7321 stored. Operand 3 is the memory model to be used.
7323 If this pattern is not present, the built-in function
7324 @code{__atomic_exchange} will attempt to preform the operation with a
7325 compare and swap loop.
7327 @cindex @code{atomic_add@var{mode}} instruction pattern
7328 @cindex @code{atomic_sub@var{mode}} instruction pattern
7329 @cindex @code{atomic_or@var{mode}} instruction pattern
7330 @cindex @code{atomic_and@var{mode}} instruction pattern
7331 @cindex @code{atomic_xor@var{mode}} instruction pattern
7332 @cindex @code{atomic_nand@var{mode}} instruction pattern
7333 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
7334 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
7335 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
7336 These patterns emit code for an atomic operation on memory with memory
7337 model semantics. Operand 0 is the memory on which the atomic operation is
7338 performed. Operand 1 is the second operand to the binary operator.
7339 Operand 2 is the memory model to be used by the operation.
7341 If these patterns are not defined, attempts will be made to use legacy
7342 @code{sync} patterns, or equivalent patterns which return a result. If
7343 none of these are available a compare-and-swap loop will be used.
7345 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
7346 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
7347 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
7348 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
7349 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
7350 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
7351 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
7352 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
7353 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
7354 These patterns emit code for an atomic operation on memory with memory
7355 model semantics, and return the original value. Operand 0 is an output
7356 operand which contains the value of the memory location before the
7357 operation was performed. Operand 1 is the memory on which the atomic
7358 operation is performed. Operand 2 is the second operand to the binary
7359 operator. Operand 3 is the memory model to be used by the operation.
7361 If these patterns are not defined, attempts will be made to use legacy
7362 @code{sync} patterns. If none of these are available a compare-and-swap
7365 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
7366 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
7367 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
7368 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
7369 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
7370 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
7371 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
7372 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
7373 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
7374 These patterns emit code for an atomic operation on memory with memory
7375 model semantics and return the result after the operation is performed.
7376 Operand 0 is an output operand which contains the value after the
7377 operation. Operand 1 is the memory on which the atomic operation is
7378 performed. Operand 2 is the second operand to the binary operator.
7379 Operand 3 is the memory model to be used by the operation.
7381 If these patterns are not defined, attempts will be made to use legacy
7382 @code{sync} patterns, or equivalent patterns which return the result before
7383 the operation followed by the arithmetic operation required to produce the
7384 result. If none of these are available a compare-and-swap loop will be
7387 @cindex @code{atomic_test_and_set} instruction pattern
7388 @item @samp{atomic_test_and_set}
7389 This pattern emits code for @code{__builtin_atomic_test_and_set}.
7390 Operand 0 is an output operand which is set to true if the previous
7391 previous contents of the byte was "set", and false otherwise. Operand 1
7392 is the @code{QImode} memory to be modified. Operand 2 is the memory
7395 The specific value that defines "set" is implementation defined, and
7396 is normally based on what is performed by the native atomic test and set
7399 @cindex @code{atomic_bit_test_and_set@var{mode}} instruction pattern
7400 @cindex @code{atomic_bit_test_and_complement@var{mode}} instruction pattern
7401 @cindex @code{atomic_bit_test_and_reset@var{mode}} instruction pattern
7402 @item @samp{atomic_bit_test_and_set@var{mode}}
7403 @itemx @samp{atomic_bit_test_and_complement@var{mode}}
7404 @itemx @samp{atomic_bit_test_and_reset@var{mode}}
7405 These patterns emit code for an atomic bitwise operation on memory with memory
7406 model semantics, and return the original value of the specified bit.
7407 Operand 0 is an output operand which contains the value of the specified bit
7408 from the memory location before the operation was performed. Operand 1 is the
7409 memory on which the atomic operation is performed. Operand 2 is the bit within
7410 the operand, starting with least significant bit. Operand 3 is the memory model
7411 to be used by the operation. Operand 4 is a flag - it is @code{const1_rtx}
7412 if operand 0 should contain the original value of the specified bit in the
7413 least significant bit of the operand, and @code{const0_rtx} if the bit should
7414 be in its original position in the operand.
7415 @code{atomic_bit_test_and_set@var{mode}} atomically sets the specified bit after
7416 remembering its original value, @code{atomic_bit_test_and_complement@var{mode}}
7417 inverts the specified bit and @code{atomic_bit_test_and_reset@var{mode}} clears
7420 If these patterns are not defined, attempts will be made to use
7421 @code{atomic_fetch_or@var{mode}}, @code{atomic_fetch_xor@var{mode}} or
7422 @code{atomic_fetch_and@var{mode}} instruction patterns, or their @code{sync}
7423 counterparts. If none of these are available a compare-and-swap
7426 @cindex @code{mem_thread_fence} instruction pattern
7427 @item @samp{mem_thread_fence}
7428 This pattern emits code required to implement a thread fence with
7429 memory model semantics. Operand 0 is the memory model to be used.
7431 For the @code{__ATOMIC_RELAXED} model no instructions need to be issued
7432 and this expansion is not invoked.
7434 The compiler always emits a compiler memory barrier regardless of what
7435 expanding this pattern produced.
7437 If this pattern is not defined, the compiler falls back to expanding the
7438 @code{memory_barrier} pattern, then to emitting @code{__sync_synchronize}
7439 library call, and finally to just placing a compiler memory barrier.
7441 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
7442 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
7443 @item @samp{get_thread_pointer@var{mode}}
7444 @itemx @samp{set_thread_pointer@var{mode}}
7445 These patterns emit code that reads/sets the TLS thread pointer. Currently,
7446 these are only needed if the target needs to support the
7447 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
7450 The get/set patterns have a single output/input operand respectively,
7451 with @var{mode} intended to be @code{Pmode}.
7453 @cindex @code{stack_protect_set} instruction pattern
7454 @item @samp{stack_protect_set}
7455 This pattern, if defined, moves a @code{ptr_mode} value from the memory
7456 in operand 1 to the memory in operand 0 without leaving the value in
7457 a register afterward. This is to avoid leaking the value some place
7458 that an attacker might use to rewrite the stack guard slot after
7459 having clobbered it.
7461 If this pattern is not defined, then a plain move pattern is generated.
7463 @cindex @code{stack_protect_test} instruction pattern
7464 @item @samp{stack_protect_test}
7465 This pattern, if defined, compares a @code{ptr_mode} value from the
7466 memory in operand 1 with the memory in operand 0 without leaving the
7467 value in a register afterward and branches to operand 2 if the values
7470 If this pattern is not defined, then a plain compare pattern and
7471 conditional branch pattern is used.
7473 @cindex @code{clear_cache} instruction pattern
7474 @item @samp{clear_cache}
7475 This pattern, if defined, flushes the instruction cache for a region of
7476 memory. The region is bounded to by the Pmode pointers in operand 0
7477 inclusive and operand 1 exclusive.
7479 If this pattern is not defined, a call to the library function
7480 @code{__clear_cache} is used.
7485 @c Each of the following nodes are wrapped in separate
7486 @c "@ifset INTERNALS" to work around memory limits for the default
7487 @c configuration in older tetex distributions. Known to not work:
7488 @c tetex-1.0.7, known to work: tetex-2.0.2.
7490 @node Pattern Ordering
7491 @section When the Order of Patterns Matters
7492 @cindex Pattern Ordering
7493 @cindex Ordering of Patterns
7495 Sometimes an insn can match more than one instruction pattern. Then the
7496 pattern that appears first in the machine description is the one used.
7497 Therefore, more specific patterns (patterns that will match fewer things)
7498 and faster instructions (those that will produce better code when they
7499 do match) should usually go first in the description.
7501 In some cases the effect of ordering the patterns can be used to hide
7502 a pattern when it is not valid. For example, the 68000 has an
7503 instruction for converting a fullword to floating point and another
7504 for converting a byte to floating point. An instruction converting
7505 an integer to floating point could match either one. We put the
7506 pattern to convert the fullword first to make sure that one will
7507 be used rather than the other. (Otherwise a large integer might
7508 be generated as a single-byte immediate quantity, which would not work.)
7509 Instead of using this pattern ordering it would be possible to make the
7510 pattern for convert-a-byte smart enough to deal properly with any
7515 @node Dependent Patterns
7516 @section Interdependence of Patterns
7517 @cindex Dependent Patterns
7518 @cindex Interdependence of Patterns
7520 In some cases machines support instructions identical except for the
7521 machine mode of one or more operands. For example, there may be
7522 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
7526 (set (match_operand:SI 0 @dots{})
7527 (extend:SI (match_operand:HI 1 @dots{})))
7529 (set (match_operand:SI 0 @dots{})
7530 (extend:SI (match_operand:QI 1 @dots{})))
7534 Constant integers do not specify a machine mode, so an instruction to
7535 extend a constant value could match either pattern. The pattern it
7536 actually will match is the one that appears first in the file. For correct
7537 results, this must be the one for the widest possible mode (@code{HImode},
7538 here). If the pattern matches the @code{QImode} instruction, the results
7539 will be incorrect if the constant value does not actually fit that mode.
7541 Such instructions to extend constants are rarely generated because they are
7542 optimized away, but they do occasionally happen in nonoptimized
7545 If a constraint in a pattern allows a constant, the reload pass may
7546 replace a register with a constant permitted by the constraint in some
7547 cases. Similarly for memory references. Because of this substitution,
7548 you should not provide separate patterns for increment and decrement
7549 instructions. Instead, they should be generated from the same pattern
7550 that supports register-register add insns by examining the operands and
7551 generating the appropriate machine instruction.
7556 @section Defining Jump Instruction Patterns
7557 @cindex jump instruction patterns
7558 @cindex defining jump instruction patterns
7560 GCC does not assume anything about how the machine realizes jumps.
7561 The machine description should define a single pattern, usually
7562 a @code{define_expand}, which expands to all the required insns.
7564 Usually, this would be a comparison insn to set the condition code
7565 and a separate branch insn testing the condition code and branching
7566 or not according to its value. For many machines, however,
7567 separating compares and branches is limiting, which is why the
7568 more flexible approach with one @code{define_expand} is used in GCC.
7569 The machine description becomes clearer for architectures that
7570 have compare-and-branch instructions but no condition code. It also
7571 works better when different sets of comparison operators are supported
7572 by different kinds of conditional branches (e.g.@: integer vs.@:
7573 floating-point), or by conditional branches with respect to conditional stores.
7575 Two separate insns are always used if the machine description represents
7576 a condition code register using the legacy RTL expression @code{(cc0)},
7577 and on most machines that use a separate condition code register
7578 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
7579 fact, the set and use of the condition code must be separate and
7580 adjacent@footnote{@code{note} insns can separate them, though.}, thus
7581 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
7582 so that the comparison and branch insns could be located from each other
7583 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
7585 Even in this case having a single entry point for conditional branches
7586 is advantageous, because it handles equally well the case where a single
7587 comparison instruction records the results of both signed and unsigned
7588 comparison of the given operands (with the branch insns coming in distinct
7589 signed and unsigned flavors) as in the x86 or SPARC, and the case where
7590 there are distinct signed and unsigned compare instructions and only
7591 one set of conditional branch instructions as in the PowerPC.
7595 @node Looping Patterns
7596 @section Defining Looping Instruction Patterns
7597 @cindex looping instruction patterns
7598 @cindex defining looping instruction patterns
7600 Some machines have special jump instructions that can be utilized to
7601 make loops more efficient. A common example is the 68000 @samp{dbra}
7602 instruction which performs a decrement of a register and a branch if the
7603 result was greater than zero. Other machines, in particular digital
7604 signal processors (DSPs), have special block repeat instructions to
7605 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
7606 DSPs have a block repeat instruction that loads special registers to
7607 mark the top and end of a loop and to count the number of loop
7608 iterations. This avoids the need for fetching and executing a
7609 @samp{dbra}-like instruction and avoids pipeline stalls associated with
7612 GCC has two special named patterns to support low overhead looping.
7613 They are @samp{doloop_begin} and @samp{doloop_end}. These are emitted
7614 by the loop optimizer for certain well-behaved loops with a finite
7615 number of loop iterations using information collected during strength
7618 The @samp{doloop_end} pattern describes the actual looping instruction
7619 (or the implicit looping operation) and the @samp{doloop_begin} pattern
7620 is an optional companion pattern that can be used for initialization
7621 needed for some low-overhead looping instructions.
7623 Note that some machines require the actual looping instruction to be
7624 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
7625 the true RTL for a looping instruction at the top of the loop can cause
7626 problems with flow analysis. So instead, a dummy @code{doloop} insn is
7627 emitted at the end of the loop. The machine dependent reorg pass checks
7628 for the presence of this @code{doloop} insn and then searches back to
7629 the top of the loop, where it inserts the true looping insn (provided
7630 there are no instructions in the loop which would cause problems). Any
7631 additional labels can be emitted at this point. In addition, if the
7632 desired special iteration counter register was not allocated, this
7633 machine dependent reorg pass could emit a traditional compare and jump
7636 For the @samp{doloop_end} pattern, the loop optimizer allocates an
7637 additional pseudo register as an iteration counter. This pseudo
7638 register cannot be used within the loop (i.e., general induction
7639 variables cannot be derived from it), however, in many cases the loop
7640 induction variable may become redundant and removed by the flow pass.
7642 The @samp{doloop_end} pattern must have a specific structure to be
7643 handled correctly by GCC. The example below is taken (slightly
7644 simplified) from the PDP-11 target:
7648 (define_expand "doloop_end"
7649 [(parallel [(set (pc)
7651 (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m")
7653 (label_ref (match_operand 1 "" ""))
7656 (plus:HI (match_dup 0)
7660 if (GET_MODE (operands[0]) != HImode)
7664 (define_insn "doloop_end_insn"
7667 (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m")
7669 (label_ref (match_operand 1 "" ""))
7672 (plus:HI (match_dup 0)
7677 if (which_alternative == 0)
7678 return "sob %0,%l1";
7681 output_asm_insn ("dec %0", operands);
7687 The first part of the pattern describes the branch condition. GCC
7688 supports three cases for the way the target machine handles the loop
7691 @item Loop terminates when the loop register decrements to zero. This
7692 is represented by a @code{ne} comparison of the register (its old value)
7693 with constant 1 (as in the example above).
7694 @item Loop terminates when the loop register decrements to @minus{}1.
7695 This is represented by a @code{ne} comparison of the register with
7697 @item Loop terminates when the loop register decrements to a negative
7698 value. This is represented by a @code{ge} comparison of the register
7699 with constant zero. For this case, GCC will attach a @code{REG_NONNEG}
7700 note to the @code{doloop_end} insn if it can determine that the register
7701 will be non-negative.
7704 Since the @code{doloop_end} insn is a jump insn that also has an output,
7705 the reload pass does not handle the output operand. Therefore, the
7706 constraint must allow for that operand to be in memory rather than a
7707 register. In the example shown above, that is handled (in the
7708 @code{doloop_end_insn} pattern) by using a loop instruction sequence
7709 that can handle memory operands when the memory alternative appears.
7711 GCC does not check the mode of the loop register operand when generating
7712 the @code{doloop_end} pattern. If the pattern is only valid for some
7713 modes but not others, the pattern should be a @code{define_expand}
7714 pattern that checks the operand mode in the preparation code, and issues
7715 @code{FAIL} if an unsupported mode is found. The example above does
7716 this, since the machine instruction to be used only exists for
7719 If the @code{doloop_end} pattern is a @code{define_expand}, there must
7720 also be a @code{define_insn} or @code{define_insn_and_split} matching
7721 the generated pattern. Otherwise, the compiler will fail during loop
7726 @node Insn Canonicalizations
7727 @section Canonicalization of Instructions
7728 @cindex canonicalization of instructions
7729 @cindex insn canonicalization
7731 There are often cases where multiple RTL expressions could represent an
7732 operation performed by a single machine instruction. This situation is
7733 most commonly encountered with logical, branch, and multiply-accumulate
7734 instructions. In such cases, the compiler attempts to convert these
7735 multiple RTL expressions into a single canonical form to reduce the
7736 number of insn patterns required.
7738 In addition to algebraic simplifications, following canonicalizations
7743 For commutative and comparison operators, a constant is always made the
7744 second operand. If a machine only supports a constant as the second
7745 operand, only patterns that match a constant in the second operand need
7749 For associative operators, a sequence of operators will always chain
7750 to the left; for instance, only the left operand of an integer @code{plus}
7751 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
7752 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
7753 @code{umax} are associative when applied to integers, and sometimes to
7757 @cindex @code{neg}, canonicalization of
7758 @cindex @code{not}, canonicalization of
7759 @cindex @code{mult}, canonicalization of
7760 @cindex @code{plus}, canonicalization of
7761 @cindex @code{minus}, canonicalization of
7762 For these operators, if only one operand is a @code{neg}, @code{not},
7763 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
7767 In combinations of @code{neg}, @code{mult}, @code{plus}, and
7768 @code{minus}, the @code{neg} operations (if any) will be moved inside
7769 the operations as far as possible. For instance,
7770 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
7771 @code{(plus (mult (neg B) C) A)} is canonicalized as
7772 @code{(minus A (mult B C))}.
7774 @cindex @code{compare}, canonicalization of
7776 For the @code{compare} operator, a constant is always the second operand
7777 if the first argument is a condition code register or @code{(cc0)}.
7780 For instructions that inherently set a condition code register, the
7781 @code{compare} operator is always written as the first RTL expression of
7782 the @code{parallel} instruction pattern. For example,
7786 [(set (reg:CCZ FLAGS_REG)
7789 (match_operand:SI 1 "register_operand" "%r")
7790 (match_operand:SI 2 "register_operand" "r"))
7792 (set (match_operand:SI 0 "register_operand" "=r")
7793 (plus:SI (match_dup 1) (match_dup 2)))]
7799 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
7800 @code{minus} is made the first operand under the same conditions as
7804 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
7805 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
7809 @code{(minus @var{x} (const_int @var{n}))} is converted to
7810 @code{(plus @var{x} (const_int @var{-n}))}.
7813 Within address computations (i.e., inside @code{mem}), a left shift is
7814 converted into the appropriate multiplication by a power of two.
7816 @cindex @code{ior}, canonicalization of
7817 @cindex @code{and}, canonicalization of
7818 @cindex De Morgan's law
7820 De Morgan's Law is used to move bitwise negation inside a bitwise
7821 logical-and or logical-or operation. If this results in only one
7822 operand being a @code{not} expression, it will be the first one.
7824 A machine that has an instruction that performs a bitwise logical-and of one
7825 operand with the bitwise negation of the other should specify the pattern
7826 for that instruction as
7830 [(set (match_operand:@var{m} 0 @dots{})
7831 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7832 (match_operand:@var{m} 2 @dots{})))]
7838 Similarly, a pattern for a ``NAND'' instruction should be written
7842 [(set (match_operand:@var{m} 0 @dots{})
7843 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7844 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
7849 In both cases, it is not necessary to include patterns for the many
7850 logically equivalent RTL expressions.
7852 @cindex @code{xor}, canonicalization of
7854 The only possible RTL expressions involving both bitwise exclusive-or
7855 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
7856 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
7859 The sum of three items, one of which is a constant, will only appear in
7863 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
7866 @cindex @code{zero_extract}, canonicalization of
7867 @cindex @code{sign_extract}, canonicalization of
7869 Equality comparisons of a group of bits (usually a single bit) with zero
7870 will be written using @code{zero_extract} rather than the equivalent
7871 @code{and} or @code{sign_extract} operations.
7873 @cindex @code{mult}, canonicalization of
7875 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
7876 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
7877 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
7878 for @code{zero_extend}.
7881 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
7882 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
7883 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
7884 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
7885 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
7886 operand of @code{mult} is also a shift, then that is extended also.
7887 This transformation is only applied when it can be proven that the
7888 original operation had sufficient precision to prevent overflow.
7892 Further canonicalization rules are defined in the function
7893 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
7897 @node Expander Definitions
7898 @section Defining RTL Sequences for Code Generation
7899 @cindex expander definitions
7900 @cindex code generation RTL sequences
7901 @cindex defining RTL sequences for code generation
7903 On some target machines, some standard pattern names for RTL generation
7904 cannot be handled with single insn, but a sequence of RTL insns can
7905 represent them. For these target machines, you can write a
7906 @code{define_expand} to specify how to generate the sequence of RTL@.
7908 @findex define_expand
7909 A @code{define_expand} is an RTL expression that looks almost like a
7910 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
7911 only for RTL generation and it can produce more than one RTL insn.
7913 A @code{define_expand} RTX has four operands:
7917 The name. Each @code{define_expand} must have a name, since the only
7918 use for it is to refer to it by name.
7921 The RTL template. This is a vector of RTL expressions representing
7922 a sequence of separate instructions. Unlike @code{define_insn}, there
7923 is no implicit surrounding @code{PARALLEL}.
7926 The condition, a string containing a C expression. This expression is
7927 used to express how the availability of this pattern depends on
7928 subclasses of target machine, selected by command-line options when GCC
7929 is run. This is just like the condition of a @code{define_insn} that
7930 has a standard name. Therefore, the condition (if present) may not
7931 depend on the data in the insn being matched, but only the
7932 target-machine-type flags. The compiler needs to test these conditions
7933 during initialization in order to learn exactly which named instructions
7934 are available in a particular run.
7937 The preparation statements, a string containing zero or more C
7938 statements which are to be executed before RTL code is generated from
7941 Usually these statements prepare temporary registers for use as
7942 internal operands in the RTL template, but they can also generate RTL
7943 insns directly by calling routines such as @code{emit_insn}, etc.
7944 Any such insns precede the ones that come from the RTL template.
7947 Optionally, a vector containing the values of attributes. @xref{Insn
7951 Every RTL insn emitted by a @code{define_expand} must match some
7952 @code{define_insn} in the machine description. Otherwise, the compiler
7953 will crash when trying to generate code for the insn or trying to optimize
7956 The RTL template, in addition to controlling generation of RTL insns,
7957 also describes the operands that need to be specified when this pattern
7958 is used. In particular, it gives a predicate for each operand.
7960 A true operand, which needs to be specified in order to generate RTL from
7961 the pattern, should be described with a @code{match_operand} in its first
7962 occurrence in the RTL template. This enters information on the operand's
7963 predicate into the tables that record such things. GCC uses the
7964 information to preload the operand into a register if that is required for
7965 valid RTL code. If the operand is referred to more than once, subsequent
7966 references should use @code{match_dup}.
7968 The RTL template may also refer to internal ``operands'' which are
7969 temporary registers or labels used only within the sequence made by the
7970 @code{define_expand}. Internal operands are substituted into the RTL
7971 template with @code{match_dup}, never with @code{match_operand}. The
7972 values of the internal operands are not passed in as arguments by the
7973 compiler when it requests use of this pattern. Instead, they are computed
7974 within the pattern, in the preparation statements. These statements
7975 compute the values and store them into the appropriate elements of
7976 @code{operands} so that @code{match_dup} can find them.
7978 There are two special macros defined for use in the preparation statements:
7979 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
7986 Use the @code{DONE} macro to end RTL generation for the pattern. The
7987 only RTL insns resulting from the pattern on this occasion will be
7988 those already emitted by explicit calls to @code{emit_insn} within the
7989 preparation statements; the RTL template will not be generated.
7993 Make the pattern fail on this occasion. When a pattern fails, it means
7994 that the pattern was not truly available. The calling routines in the
7995 compiler will try other strategies for code generation using other patterns.
7997 Failure is currently supported only for binary (addition, multiplication,
7998 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
8002 If the preparation falls through (invokes neither @code{DONE} nor
8003 @code{FAIL}), then the @code{define_expand} acts like a
8004 @code{define_insn} in that the RTL template is used to generate the
8007 The RTL template is not used for matching, only for generating the
8008 initial insn list. If the preparation statement always invokes
8009 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
8010 list of operands, such as this example:
8014 (define_expand "addsi3"
8015 [(match_operand:SI 0 "register_operand" "")
8016 (match_operand:SI 1 "register_operand" "")
8017 (match_operand:SI 2 "register_operand" "")]
8023 handle_add (operands[0], operands[1], operands[2]);
8029 Here is an example, the definition of left-shift for the SPUR chip:
8033 (define_expand "ashlsi3"
8034 [(set (match_operand:SI 0 "register_operand" "")
8038 (match_operand:SI 1 "register_operand" "")
8039 (match_operand:SI 2 "nonmemory_operand" "")))]
8048 if (GET_CODE (operands[2]) != CONST_INT
8049 || (unsigned) INTVAL (operands[2]) > 3)
8056 This example uses @code{define_expand} so that it can generate an RTL insn
8057 for shifting when the shift-count is in the supported range of 0 to 3 but
8058 fail in other cases where machine insns aren't available. When it fails,
8059 the compiler tries another strategy using different patterns (such as, a
8062 If the compiler were able to handle nontrivial condition-strings in
8063 patterns with names, then it would be possible to use a
8064 @code{define_insn} in that case. Here is another case (zero-extension
8065 on the 68000) which makes more use of the power of @code{define_expand}:
8068 (define_expand "zero_extendhisi2"
8069 [(set (match_operand:SI 0 "general_operand" "")
8071 (set (strict_low_part
8075 (match_operand:HI 1 "general_operand" ""))]
8077 "operands[1] = make_safe_from (operands[1], operands[0]);")
8081 @findex make_safe_from
8082 Here two RTL insns are generated, one to clear the entire output operand
8083 and the other to copy the input operand into its low half. This sequence
8084 is incorrect if the input operand refers to [the old value of] the output
8085 operand, so the preparation statement makes sure this isn't so. The
8086 function @code{make_safe_from} copies the @code{operands[1]} into a
8087 temporary register if it refers to @code{operands[0]}. It does this
8088 by emitting another RTL insn.
8090 Finally, a third example shows the use of an internal operand.
8091 Zero-extension on the SPUR chip is done by @code{and}-ing the result
8092 against a halfword mask. But this mask cannot be represented by a
8093 @code{const_int} because the constant value is too large to be legitimate
8094 on this machine. So it must be copied into a register with
8095 @code{force_reg} and then the register used in the @code{and}.
8098 (define_expand "zero_extendhisi2"
8099 [(set (match_operand:SI 0 "register_operand" "")
8101 (match_operand:HI 1 "register_operand" "")
8106 = force_reg (SImode, GEN_INT (65535)); ")
8109 @emph{Note:} If the @code{define_expand} is used to serve a
8110 standard binary or unary arithmetic operation or a bit-field operation,
8111 then the last insn it generates must not be a @code{code_label},
8112 @code{barrier} or @code{note}. It must be an @code{insn},
8113 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
8114 at the end, emit an insn to copy the result of the operation into
8115 itself. Such an insn will generate no code, but it can avoid problems
8120 @node Insn Splitting
8121 @section Defining How to Split Instructions
8122 @cindex insn splitting
8123 @cindex instruction splitting
8124 @cindex splitting instructions
8126 There are two cases where you should specify how to split a pattern
8127 into multiple insns. On machines that have instructions requiring
8128 delay slots (@pxref{Delay Slots}) or that have instructions whose
8129 output is not available for multiple cycles (@pxref{Processor pipeline
8130 description}), the compiler phases that optimize these cases need to
8131 be able to move insns into one-instruction delay slots. However, some
8132 insns may generate more than one machine instruction. These insns
8133 cannot be placed into a delay slot.
8135 Often you can rewrite the single insn as a list of individual insns,
8136 each corresponding to one machine instruction. The disadvantage of
8137 doing so is that it will cause the compilation to be slower and require
8138 more space. If the resulting insns are too complex, it may also
8139 suppress some optimizations. The compiler splits the insn if there is a
8140 reason to believe that it might improve instruction or delay slot
8143 The insn combiner phase also splits putative insns. If three insns are
8144 merged into one insn with a complex expression that cannot be matched by
8145 some @code{define_insn} pattern, the combiner phase attempts to split
8146 the complex pattern into two insns that are recognized. Usually it can
8147 break the complex pattern into two patterns by splitting out some
8148 subexpression. However, in some other cases, such as performing an
8149 addition of a large constant in two insns on a RISC machine, the way to
8150 split the addition into two insns is machine-dependent.
8152 @findex define_split
8153 The @code{define_split} definition tells the compiler how to split a
8154 complex insn into several simpler insns. It looks like this:
8158 [@var{insn-pattern}]
8160 [@var{new-insn-pattern-1}
8161 @var{new-insn-pattern-2}
8163 "@var{preparation-statements}")
8166 @var{insn-pattern} is a pattern that needs to be split and
8167 @var{condition} is the final condition to be tested, as in a
8168 @code{define_insn}. When an insn matching @var{insn-pattern} and
8169 satisfying @var{condition} is found, it is replaced in the insn list
8170 with the insns given by @var{new-insn-pattern-1},
8171 @var{new-insn-pattern-2}, etc.
8173 The @var{preparation-statements} are similar to those statements that
8174 are specified for @code{define_expand} (@pxref{Expander Definitions})
8175 and are executed before the new RTL is generated to prepare for the
8176 generated code or emit some insns whose pattern is not fixed. Unlike
8177 those in @code{define_expand}, however, these statements must not
8178 generate any new pseudo-registers. Once reload has completed, they also
8179 must not allocate any space in the stack frame.
8181 There are two special macros defined for use in the preparation statements:
8182 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8189 Use the @code{DONE} macro to end RTL generation for the splitter. The
8190 only RTL insns generated as replacement for the matched input insn will
8191 be those already emitted by explicit calls to @code{emit_insn} within
8192 the preparation statements; the replacement pattern is not used.
8196 Make the @code{define_split} fail on this occasion. When a @code{define_split}
8197 fails, it means that the splitter was not truly available for the inputs
8198 it was given, and the input insn will not be split.
8201 If the preparation falls through (invokes neither @code{DONE} nor
8202 @code{FAIL}), then the @code{define_split} uses the replacement
8205 Patterns are matched against @var{insn-pattern} in two different
8206 circumstances. If an insn needs to be split for delay slot scheduling
8207 or insn scheduling, the insn is already known to be valid, which means
8208 that it must have been matched by some @code{define_insn} and, if
8209 @code{reload_completed} is nonzero, is known to satisfy the constraints
8210 of that @code{define_insn}. In that case, the new insn patterns must
8211 also be insns that are matched by some @code{define_insn} and, if
8212 @code{reload_completed} is nonzero, must also satisfy the constraints
8213 of those definitions.
8215 As an example of this usage of @code{define_split}, consider the following
8216 example from @file{a29k.md}, which splits a @code{sign_extend} from
8217 @code{HImode} to @code{SImode} into a pair of shift insns:
8221 [(set (match_operand:SI 0 "gen_reg_operand" "")
8222 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
8225 (ashift:SI (match_dup 1)
8228 (ashiftrt:SI (match_dup 0)
8231 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
8234 When the combiner phase tries to split an insn pattern, it is always the
8235 case that the pattern is @emph{not} matched by any @code{define_insn}.
8236 The combiner pass first tries to split a single @code{set} expression
8237 and then the same @code{set} expression inside a @code{parallel}, but
8238 followed by a @code{clobber} of a pseudo-reg to use as a scratch
8239 register. In these cases, the combiner expects exactly two new insn
8240 patterns to be generated. It will verify that these patterns match some
8241 @code{define_insn} definitions, so you need not do this test in the
8242 @code{define_split} (of course, there is no point in writing a
8243 @code{define_split} that will never produce insns that match).
8245 Here is an example of this use of @code{define_split}, taken from
8250 [(set (match_operand:SI 0 "gen_reg_operand" "")
8251 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
8252 (match_operand:SI 2 "non_add_cint_operand" "")))]
8254 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
8255 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
8258 int low = INTVAL (operands[2]) & 0xffff;
8259 int high = (unsigned) INTVAL (operands[2]) >> 16;
8262 high++, low |= 0xffff0000;
8264 operands[3] = GEN_INT (high << 16);
8265 operands[4] = GEN_INT (low);
8269 Here the predicate @code{non_add_cint_operand} matches any
8270 @code{const_int} that is @emph{not} a valid operand of a single add
8271 insn. The add with the smaller displacement is written so that it
8272 can be substituted into the address of a subsequent operation.
8274 An example that uses a scratch register, from the same file, generates
8275 an equality comparison of a register and a large constant:
8279 [(set (match_operand:CC 0 "cc_reg_operand" "")
8280 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
8281 (match_operand:SI 2 "non_short_cint_operand" "")))
8282 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
8283 "find_single_use (operands[0], insn, 0)
8284 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
8285 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
8286 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
8287 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
8290 /* @r{Get the constant we are comparing against, C, and see what it
8291 looks like sign-extended to 16 bits. Then see what constant
8292 could be XOR'ed with C to get the sign-extended value.} */
8294 int c = INTVAL (operands[2]);
8295 int sextc = (c << 16) >> 16;
8296 int xorv = c ^ sextc;
8298 operands[4] = GEN_INT (xorv);
8299 operands[5] = GEN_INT (sextc);
8303 To avoid confusion, don't write a single @code{define_split} that
8304 accepts some insns that match some @code{define_insn} as well as some
8305 insns that don't. Instead, write two separate @code{define_split}
8306 definitions, one for the insns that are valid and one for the insns that
8309 The splitter is allowed to split jump instructions into sequence of
8310 jumps or create new jumps in while splitting non-jump instructions. As
8311 the control flow graph and branch prediction information needs to be updated,
8312 several restriction apply.
8314 Splitting of jump instruction into sequence that over by another jump
8315 instruction is always valid, as compiler expect identical behavior of new
8316 jump. When new sequence contains multiple jump instructions or new labels,
8317 more assistance is needed. Splitter is required to create only unconditional
8318 jumps, or simple conditional jump instructions. Additionally it must attach a
8319 @code{REG_BR_PROB} note to each conditional jump. A global variable
8320 @code{split_branch_probability} holds the probability of the original branch in case
8321 it was a simple conditional jump, @minus{}1 otherwise. To simplify
8322 recomputing of edge frequencies, the new sequence is required to have only
8323 forward jumps to the newly created labels.
8325 @findex define_insn_and_split
8326 For the common case where the pattern of a define_split exactly matches the
8327 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
8331 (define_insn_and_split
8332 [@var{insn-pattern}]
8334 "@var{output-template}"
8335 "@var{split-condition}"
8336 [@var{new-insn-pattern-1}
8337 @var{new-insn-pattern-2}
8339 "@var{preparation-statements}"
8340 [@var{insn-attributes}])
8344 @var{insn-pattern}, @var{condition}, @var{output-template}, and
8345 @var{insn-attributes} are used as in @code{define_insn}. The
8346 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
8347 in a @code{define_split}. The @var{split-condition} is also used as in
8348 @code{define_split}, with the additional behavior that if the condition starts
8349 with @samp{&&}, the condition used for the split will be the constructed as a
8350 logical ``and'' of the split condition with the insn condition. For example,
8354 (define_insn_and_split "zero_extendhisi2_and"
8355 [(set (match_operand:SI 0 "register_operand" "=r")
8356 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
8357 (clobber (reg:CC 17))]
8358 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
8360 "&& reload_completed"
8361 [(parallel [(set (match_dup 0)
8362 (and:SI (match_dup 0) (const_int 65535)))
8363 (clobber (reg:CC 17))])]
8365 [(set_attr "type" "alu1")])
8369 In this case, the actual split condition will be
8370 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
8372 The @code{define_insn_and_split} construction provides exactly the same
8373 functionality as two separate @code{define_insn} and @code{define_split}
8374 patterns. It exists for compactness, and as a maintenance tool to prevent
8375 having to ensure the two patterns' templates match.
8379 @node Including Patterns
8380 @section Including Patterns in Machine Descriptions.
8381 @cindex insn includes
8384 The @code{include} pattern tells the compiler tools where to
8385 look for patterns that are in files other than in the file
8386 @file{.md}. This is used only at build time and there is no preprocessing allowed.
8400 (include "filestuff")
8404 Where @var{pathname} is a string that specifies the location of the file,
8405 specifies the include file to be in @file{gcc/config/target/filestuff}. The
8406 directory @file{gcc/config/target} is regarded as the default directory.
8409 Machine descriptions may be split up into smaller more manageable subsections
8410 and placed into subdirectories.
8416 (include "BOGUS/filestuff")
8420 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
8422 Specifying an absolute path for the include file such as;
8425 (include "/u2/BOGUS/filestuff")
8428 is permitted but is not encouraged.
8430 @subsection RTL Generation Tool Options for Directory Search
8431 @cindex directory options .md
8432 @cindex options, directory search
8433 @cindex search options
8435 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
8440 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
8445 Add the directory @var{dir} to the head of the list of directories to be
8446 searched for header files. This can be used to override a system machine definition
8447 file, substituting your own version, since these directories are
8448 searched before the default machine description file directories. If you use more than
8449 one @option{-I} option, the directories are scanned in left-to-right
8450 order; the standard default directory come after.
8455 @node Peephole Definitions
8456 @section Machine-Specific Peephole Optimizers
8457 @cindex peephole optimizer definitions
8458 @cindex defining peephole optimizers
8460 In addition to instruction patterns the @file{md} file may contain
8461 definitions of machine-specific peephole optimizations.
8463 The combiner does not notice certain peephole optimizations when the data
8464 flow in the program does not suggest that it should try them. For example,
8465 sometimes two consecutive insns related in purpose can be combined even
8466 though the second one does not appear to use a register computed in the
8467 first one. A machine-specific peephole optimizer can detect such
8470 There are two forms of peephole definitions that may be used. The
8471 original @code{define_peephole} is run at assembly output time to
8472 match insns and substitute assembly text. Use of @code{define_peephole}
8475 A newer @code{define_peephole2} matches insns and substitutes new
8476 insns. The @code{peephole2} pass is run after register allocation
8477 but before scheduling, which may result in much better code for
8478 targets that do scheduling.
8481 * define_peephole:: RTL to Text Peephole Optimizers
8482 * define_peephole2:: RTL to RTL Peephole Optimizers
8487 @node define_peephole
8488 @subsection RTL to Text Peephole Optimizers
8489 @findex define_peephole
8492 A definition looks like this:
8496 [@var{insn-pattern-1}
8497 @var{insn-pattern-2}
8501 "@var{optional-insn-attributes}")
8505 The last string operand may be omitted if you are not using any
8506 machine-specific information in this machine description. If present,
8507 it must obey the same rules as in a @code{define_insn}.
8509 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
8510 consecutive insns. The optimization applies to a sequence of insns when
8511 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
8512 the next, and so on.
8514 Each of the insns matched by a peephole must also match a
8515 @code{define_insn}. Peepholes are checked only at the last stage just
8516 before code generation, and only optionally. Therefore, any insn which
8517 would match a peephole but no @code{define_insn} will cause a crash in code
8518 generation in an unoptimized compilation, or at various optimization
8521 The operands of the insns are matched with @code{match_operands},
8522 @code{match_operator}, and @code{match_dup}, as usual. What is not
8523 usual is that the operand numbers apply to all the insn patterns in the
8524 definition. So, you can check for identical operands in two insns by
8525 using @code{match_operand} in one insn and @code{match_dup} in the
8528 The operand constraints used in @code{match_operand} patterns do not have
8529 any direct effect on the applicability of the peephole, but they will
8530 be validated afterward, so make sure your constraints are general enough
8531 to apply whenever the peephole matches. If the peephole matches
8532 but the constraints are not satisfied, the compiler will crash.
8534 It is safe to omit constraints in all the operands of the peephole; or
8535 you can write constraints which serve as a double-check on the criteria
8538 Once a sequence of insns matches the patterns, the @var{condition} is
8539 checked. This is a C expression which makes the final decision whether to
8540 perform the optimization (we do so if the expression is nonzero). If
8541 @var{condition} is omitted (in other words, the string is empty) then the
8542 optimization is applied to every sequence of insns that matches the
8545 The defined peephole optimizations are applied after register allocation
8546 is complete. Therefore, the peephole definition can check which
8547 operands have ended up in which kinds of registers, just by looking at
8550 @findex prev_active_insn
8551 The way to refer to the operands in @var{condition} is to write
8552 @code{operands[@var{i}]} for operand number @var{i} (as matched by
8553 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
8554 to refer to the last of the insns being matched; use
8555 @code{prev_active_insn} to find the preceding insns.
8557 @findex dead_or_set_p
8558 When optimizing computations with intermediate results, you can use
8559 @var{condition} to match only when the intermediate results are not used
8560 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
8561 @var{op})}, where @var{insn} is the insn in which you expect the value
8562 to be used for the last time (from the value of @code{insn}, together
8563 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
8564 value (from @code{operands[@var{i}]}).
8566 Applying the optimization means replacing the sequence of insns with one
8567 new insn. The @var{template} controls ultimate output of assembler code
8568 for this combined insn. It works exactly like the template of a
8569 @code{define_insn}. Operand numbers in this template are the same ones
8570 used in matching the original sequence of insns.
8572 The result of a defined peephole optimizer does not need to match any of
8573 the insn patterns in the machine description; it does not even have an
8574 opportunity to match them. The peephole optimizer definition itself serves
8575 as the insn pattern to control how the insn is output.
8577 Defined peephole optimizers are run as assembler code is being output,
8578 so the insns they produce are never combined or rearranged in any way.
8580 Here is an example, taken from the 68000 machine description:
8584 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
8585 (set (match_operand:DF 0 "register_operand" "=f")
8586 (match_operand:DF 1 "register_operand" "ad"))]
8587 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
8590 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8592 output_asm_insn ("move.l %1,(sp)", xoperands);
8593 output_asm_insn ("move.l %1,-(sp)", operands);
8594 return "fmove.d (sp)+,%0";
8596 output_asm_insn ("movel %1,sp@@", xoperands);
8597 output_asm_insn ("movel %1,sp@@-", operands);
8598 return "fmoved sp@@+,%0";
8604 The effect of this optimization is to change
8630 If a peephole matches a sequence including one or more jump insns, you must
8631 take account of the flags such as @code{CC_REVERSED} which specify that the
8632 condition codes are represented in an unusual manner. The compiler
8633 automatically alters any ordinary conditional jumps which occur in such
8634 situations, but the compiler cannot alter jumps which have been replaced by
8635 peephole optimizations. So it is up to you to alter the assembler code
8636 that the peephole produces. Supply C code to write the assembler output,
8637 and in this C code check the condition code status flags and change the
8638 assembler code as appropriate.
8641 @var{insn-pattern-1} and so on look @emph{almost} like the second
8642 operand of @code{define_insn}. There is one important difference: the
8643 second operand of @code{define_insn} consists of one or more RTX's
8644 enclosed in square brackets. Usually, there is only one: then the same
8645 action can be written as an element of a @code{define_peephole}. But
8646 when there are multiple actions in a @code{define_insn}, they are
8647 implicitly enclosed in a @code{parallel}. Then you must explicitly
8648 write the @code{parallel}, and the square brackets within it, in the
8649 @code{define_peephole}. Thus, if an insn pattern looks like this,
8652 (define_insn "divmodsi4"
8653 [(set (match_operand:SI 0 "general_operand" "=d")
8654 (div:SI (match_operand:SI 1 "general_operand" "0")
8655 (match_operand:SI 2 "general_operand" "dmsK")))
8656 (set (match_operand:SI 3 "general_operand" "=d")
8657 (mod:SI (match_dup 1) (match_dup 2)))]
8659 "divsl%.l %2,%3:%0")
8663 then the way to mention this insn in a peephole is as follows:
8669 [(set (match_operand:SI 0 "general_operand" "=d")
8670 (div:SI (match_operand:SI 1 "general_operand" "0")
8671 (match_operand:SI 2 "general_operand" "dmsK")))
8672 (set (match_operand:SI 3 "general_operand" "=d")
8673 (mod:SI (match_dup 1) (match_dup 2)))])
8680 @node define_peephole2
8681 @subsection RTL to RTL Peephole Optimizers
8682 @findex define_peephole2
8684 The @code{define_peephole2} definition tells the compiler how to
8685 substitute one sequence of instructions for another sequence,
8686 what additional scratch registers may be needed and what their
8691 [@var{insn-pattern-1}
8692 @var{insn-pattern-2}
8695 [@var{new-insn-pattern-1}
8696 @var{new-insn-pattern-2}
8698 "@var{preparation-statements}")
8701 The definition is almost identical to @code{define_split}
8702 (@pxref{Insn Splitting}) except that the pattern to match is not a
8703 single instruction, but a sequence of instructions.
8705 It is possible to request additional scratch registers for use in the
8706 output template. If appropriate registers are not free, the pattern
8707 will simply not match.
8709 @findex match_scratch
8711 Scratch registers are requested with a @code{match_scratch} pattern at
8712 the top level of the input pattern. The allocated register (initially) will
8713 be dead at the point requested within the original sequence. If the scratch
8714 is used at more than a single point, a @code{match_dup} pattern at the
8715 top level of the input pattern marks the last position in the input sequence
8716 at which the register must be available.
8718 Here is an example from the IA-32 machine description:
8722 [(match_scratch:SI 2 "r")
8723 (parallel [(set (match_operand:SI 0 "register_operand" "")
8724 (match_operator:SI 3 "arith_or_logical_operator"
8726 (match_operand:SI 1 "memory_operand" "")]))
8727 (clobber (reg:CC 17))])]
8728 "! optimize_size && ! TARGET_READ_MODIFY"
8729 [(set (match_dup 2) (match_dup 1))
8730 (parallel [(set (match_dup 0)
8731 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
8732 (clobber (reg:CC 17))])]
8737 This pattern tries to split a load from its use in the hopes that we'll be
8738 able to schedule around the memory load latency. It allocates a single
8739 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
8740 to be live only at the point just before the arithmetic.
8742 A real example requiring extended scratch lifetimes is harder to come by,
8743 so here's a silly made-up example:
8747 [(match_scratch:SI 4 "r")
8748 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
8749 (set (match_operand:SI 2 "" "") (match_dup 1))
8751 (set (match_operand:SI 3 "" "") (match_dup 1))]
8752 "/* @r{determine 1 does not overlap 0 and 2} */"
8753 [(set (match_dup 4) (match_dup 1))
8754 (set (match_dup 0) (match_dup 4))
8755 (set (match_dup 2) (match_dup 4))
8756 (set (match_dup 3) (match_dup 4))]
8760 There are two special macros defined for use in the preparation statements:
8761 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8768 Use the @code{DONE} macro to end RTL generation for the peephole. The
8769 only RTL insns generated as replacement for the matched input insn will
8770 be those already emitted by explicit calls to @code{emit_insn} within
8771 the preparation statements; the replacement pattern is not used.
8775 Make the @code{define_peephole2} fail on this occasion. When a @code{define_peephole2}
8776 fails, it means that the replacement was not truly available for the
8777 particular inputs it was given. In that case, GCC may still apply a
8778 later @code{define_peephole2} that also matches the given insn pattern.
8779 (Note that this is different from @code{define_split}, where @code{FAIL}
8780 prevents the input insn from being split at all.)
8783 If the preparation falls through (invokes neither @code{DONE} nor
8784 @code{FAIL}), then the @code{define_peephole2} uses the replacement
8788 If we had not added the @code{(match_dup 4)} in the middle of the input
8789 sequence, it might have been the case that the register we chose at the
8790 beginning of the sequence is killed by the first or second @code{set}.
8794 @node Insn Attributes
8795 @section Instruction Attributes
8796 @cindex insn attributes
8797 @cindex instruction attributes
8799 In addition to describing the instruction supported by the target machine,
8800 the @file{md} file also defines a group of @dfn{attributes} and a set of
8801 values for each. Every generated insn is assigned a value for each attribute.
8802 One possible attribute would be the effect that the insn has on the machine's
8803 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
8804 to track the condition codes.
8807 * Defining Attributes:: Specifying attributes and their values.
8808 * Expressions:: Valid expressions for attribute values.
8809 * Tagging Insns:: Assigning attribute values to insns.
8810 * Attr Example:: An example of assigning attributes.
8811 * Insn Lengths:: Computing the length of insns.
8812 * Constant Attributes:: Defining attributes that are constant.
8813 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
8814 * Delay Slots:: Defining delay slots required for a machine.
8815 * Processor pipeline description:: Specifying information for insn scheduling.
8820 @node Defining Attributes
8821 @subsection Defining Attributes and their Values
8822 @cindex defining attributes and their values
8823 @cindex attributes, defining
8826 The @code{define_attr} expression is used to define each attribute required
8827 by the target machine. It looks like:
8830 (define_attr @var{name} @var{list-of-values} @var{default})
8833 @var{name} is a string specifying the name of the attribute being
8834 defined. Some attributes are used in a special way by the rest of the
8835 compiler. The @code{enabled} attribute can be used to conditionally
8836 enable or disable insn alternatives (@pxref{Disable Insn
8837 Alternatives}). The @code{predicable} attribute, together with a
8838 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
8839 be used to automatically generate conditional variants of instruction
8840 patterns. The @code{mnemonic} attribute can be used to check for the
8841 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
8842 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
8843 so they should not be used elsewhere as alternative names.
8845 @var{list-of-values} is either a string that specifies a comma-separated
8846 list of values that can be assigned to the attribute, or a null string to
8847 indicate that the attribute takes numeric values.
8849 @var{default} is an attribute expression that gives the value of this
8850 attribute for insns that match patterns whose definition does not include
8851 an explicit value for this attribute. @xref{Attr Example}, for more
8852 information on the handling of defaults. @xref{Constant Attributes},
8853 for information on attributes that do not depend on any particular insn.
8856 For each defined attribute, a number of definitions are written to the
8857 @file{insn-attr.h} file. For cases where an explicit set of values is
8858 specified for an attribute, the following are defined:
8862 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
8865 An enumerated class is defined for @samp{attr_@var{name}} with
8866 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
8867 the attribute name and value are first converted to uppercase.
8870 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
8871 returns the attribute value for that insn.
8874 For example, if the following is present in the @file{md} file:
8877 (define_attr "type" "branch,fp,load,store,arith" @dots{})
8881 the following lines will be written to the file @file{insn-attr.h}.
8884 #define HAVE_ATTR_type 1
8885 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
8886 TYPE_STORE, TYPE_ARITH@};
8887 extern enum attr_type get_attr_type ();
8890 If the attribute takes numeric values, no @code{enum} type will be
8891 defined and the function to obtain the attribute's value will return
8894 There are attributes which are tied to a specific meaning. These
8895 attributes are not free to use for other purposes:
8899 The @code{length} attribute is used to calculate the length of emitted
8900 code chunks. This is especially important when verifying branch
8901 distances. @xref{Insn Lengths}.
8904 The @code{enabled} attribute can be defined to prevent certain
8905 alternatives of an insn definition from being used during code
8906 generation. @xref{Disable Insn Alternatives}.
8909 The @code{mnemonic} attribute can be defined to implement instruction
8910 specific checks in e.g.@: the pipeline description.
8911 @xref{Mnemonic Attribute}.
8914 For each of these special attributes, the corresponding
8915 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
8916 attribute is not defined; in that case, it is defined as @samp{0}.
8918 @findex define_enum_attr
8919 @anchor{define_enum_attr}
8920 Another way of defining an attribute is to use:
8923 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
8926 This works in just the same way as @code{define_attr}, except that
8927 the list of values is taken from a separate enumeration called
8928 @var{enum} (@pxref{define_enum}). This form allows you to use
8929 the same list of values for several attributes without having to
8930 repeat the list each time. For example:
8933 (define_enum "processor" [
8938 (define_enum_attr "arch" "processor"
8939 (const (symbol_ref "target_arch")))
8940 (define_enum_attr "tune" "processor"
8941 (const (symbol_ref "target_tune")))
8944 defines the same attributes as:
8947 (define_attr "arch" "model_a,model_b,@dots{}"
8948 (const (symbol_ref "target_arch")))
8949 (define_attr "tune" "model_a,model_b,@dots{}"
8950 (const (symbol_ref "target_tune")))
8953 but without duplicating the processor list. The second example defines two
8954 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
8955 defines a single C enum (@code{processor}).
8959 @subsection Attribute Expressions
8960 @cindex attribute expressions
8962 RTL expressions used to define attributes use the codes described above
8963 plus a few specific to attribute definitions, to be discussed below.
8964 Attribute value expressions must have one of the following forms:
8967 @cindex @code{const_int} and attributes
8968 @item (const_int @var{i})
8969 The integer @var{i} specifies the value of a numeric attribute. @var{i}
8970 must be non-negative.
8972 The value of a numeric attribute can be specified either with a
8973 @code{const_int}, or as an integer represented as a string in
8974 @code{const_string}, @code{eq_attr} (see below), @code{attr},
8975 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
8976 overrides on specific instructions (@pxref{Tagging Insns}).
8978 @cindex @code{const_string} and attributes
8979 @item (const_string @var{value})
8980 The string @var{value} specifies a constant attribute value.
8981 If @var{value} is specified as @samp{"*"}, it means that the default value of
8982 the attribute is to be used for the insn containing this expression.
8983 @samp{"*"} obviously cannot be used in the @var{default} expression
8984 of a @code{define_attr}.
8986 If the attribute whose value is being specified is numeric, @var{value}
8987 must be a string containing a non-negative integer (normally
8988 @code{const_int} would be used in this case). Otherwise, it must
8989 contain one of the valid values for the attribute.
8991 @cindex @code{if_then_else} and attributes
8992 @item (if_then_else @var{test} @var{true-value} @var{false-value})
8993 @var{test} specifies an attribute test, whose format is defined below.
8994 The value of this expression is @var{true-value} if @var{test} is true,
8995 otherwise it is @var{false-value}.
8997 @cindex @code{cond} and attributes
8998 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
8999 The first operand of this expression is a vector containing an even
9000 number of expressions and consisting of pairs of @var{test} and @var{value}
9001 expressions. The value of the @code{cond} expression is that of the
9002 @var{value} corresponding to the first true @var{test} expression. If
9003 none of the @var{test} expressions are true, the value of the @code{cond}
9004 expression is that of the @var{default} expression.
9007 @var{test} expressions can have one of the following forms:
9010 @cindex @code{const_int} and attribute tests
9011 @item (const_int @var{i})
9012 This test is true if @var{i} is nonzero and false otherwise.
9014 @cindex @code{not} and attributes
9015 @cindex @code{ior} and attributes
9016 @cindex @code{and} and attributes
9017 @item (not @var{test})
9018 @itemx (ior @var{test1} @var{test2})
9019 @itemx (and @var{test1} @var{test2})
9020 These tests are true if the indicated logical function is true.
9022 @cindex @code{match_operand} and attributes
9023 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
9024 This test is true if operand @var{n} of the insn whose attribute value
9025 is being determined has mode @var{m} (this part of the test is ignored
9026 if @var{m} is @code{VOIDmode}) and the function specified by the string
9027 @var{pred} returns a nonzero value when passed operand @var{n} and mode
9028 @var{m} (this part of the test is ignored if @var{pred} is the null
9031 The @var{constraints} operand is ignored and should be the null string.
9033 @cindex @code{match_test} and attributes
9034 @item (match_test @var{c-expr})
9035 The test is true if C expression @var{c-expr} is true. In non-constant
9036 attributes, @var{c-expr} has access to the following variables:
9040 The rtl instruction under test.
9041 @item which_alternative
9042 The @code{define_insn} alternative that @var{insn} matches.
9043 @xref{Output Statement}.
9045 An array of @var{insn}'s rtl operands.
9048 @var{c-expr} behaves like the condition in a C @code{if} statement,
9049 so there is no need to explicitly convert the expression into a boolean
9050 0 or 1 value. For example, the following two tests are equivalent:
9053 (match_test "x & 2")
9054 (match_test "(x & 2) != 0")
9057 @cindex @code{le} and attributes
9058 @cindex @code{leu} and attributes
9059 @cindex @code{lt} and attributes
9060 @cindex @code{gt} and attributes
9061 @cindex @code{gtu} and attributes
9062 @cindex @code{ge} and attributes
9063 @cindex @code{geu} and attributes
9064 @cindex @code{ne} and attributes
9065 @cindex @code{eq} and attributes
9066 @cindex @code{plus} and attributes
9067 @cindex @code{minus} and attributes
9068 @cindex @code{mult} and attributes
9069 @cindex @code{div} and attributes
9070 @cindex @code{mod} and attributes
9071 @cindex @code{abs} and attributes
9072 @cindex @code{neg} and attributes
9073 @cindex @code{ashift} and attributes
9074 @cindex @code{lshiftrt} and attributes
9075 @cindex @code{ashiftrt} and attributes
9076 @item (le @var{arith1} @var{arith2})
9077 @itemx (leu @var{arith1} @var{arith2})
9078 @itemx (lt @var{arith1} @var{arith2})
9079 @itemx (ltu @var{arith1} @var{arith2})
9080 @itemx (gt @var{arith1} @var{arith2})
9081 @itemx (gtu @var{arith1} @var{arith2})
9082 @itemx (ge @var{arith1} @var{arith2})
9083 @itemx (geu @var{arith1} @var{arith2})
9084 @itemx (ne @var{arith1} @var{arith2})
9085 @itemx (eq @var{arith1} @var{arith2})
9086 These tests are true if the indicated comparison of the two arithmetic
9087 expressions is true. Arithmetic expressions are formed with
9088 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
9089 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
9090 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
9093 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
9094 Lengths},for additional forms). @code{symbol_ref} is a string
9095 denoting a C expression that yields an @code{int} when evaluated by the
9096 @samp{get_attr_@dots{}} routine. It should normally be a global
9100 @item (eq_attr @var{name} @var{value})
9101 @var{name} is a string specifying the name of an attribute.
9103 @var{value} is a string that is either a valid value for attribute
9104 @var{name}, a comma-separated list of values, or @samp{!} followed by a
9105 value or list. If @var{value} does not begin with a @samp{!}, this
9106 test is true if the value of the @var{name} attribute of the current
9107 insn is in the list specified by @var{value}. If @var{value} begins
9108 with a @samp{!}, this test is true if the attribute's value is
9109 @emph{not} in the specified list.
9114 (eq_attr "type" "load,store")
9121 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
9124 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
9125 value of the compiler variable @code{which_alternative}
9126 (@pxref{Output Statement}) and the values must be small integers. For
9130 (eq_attr "alternative" "2,3")
9137 (ior (eq (symbol_ref "which_alternative") (const_int 2))
9138 (eq (symbol_ref "which_alternative") (const_int 3)))
9141 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
9142 where the value of the attribute being tested is known for all insns matching
9143 a particular pattern. This is by far the most common case.
9146 @item (attr_flag @var{name})
9147 The value of an @code{attr_flag} expression is true if the flag
9148 specified by @var{name} is true for the @code{insn} currently being
9151 @var{name} is a string specifying one of a fixed set of flags to test.
9152 Test the flags @code{forward} and @code{backward} to determine the
9153 direction of a conditional branch.
9155 This example describes a conditional branch delay slot which
9156 can be nullified for forward branches that are taken (annul-true) or
9157 for backward branches which are not taken (annul-false).
9160 (define_delay (eq_attr "type" "cbranch")
9161 [(eq_attr "in_branch_delay" "true")
9162 (and (eq_attr "in_branch_delay" "true")
9163 (attr_flag "forward"))
9164 (and (eq_attr "in_branch_delay" "true")
9165 (attr_flag "backward"))])
9168 The @code{forward} and @code{backward} flags are false if the current
9169 @code{insn} being scheduled is not a conditional branch.
9171 @code{attr_flag} is only used during delay slot scheduling and has no
9172 meaning to other passes of the compiler.
9175 @item (attr @var{name})
9176 The value of another attribute is returned. This is most useful
9177 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
9178 produce more efficient code for non-numeric attributes.
9184 @subsection Assigning Attribute Values to Insns
9185 @cindex tagging insns
9186 @cindex assigning attribute values to insns
9188 The value assigned to an attribute of an insn is primarily determined by
9189 which pattern is matched by that insn (or which @code{define_peephole}
9190 generated it). Every @code{define_insn} and @code{define_peephole} can
9191 have an optional last argument to specify the values of attributes for
9192 matching insns. The value of any attribute not specified in a particular
9193 insn is set to the default value for that attribute, as specified in its
9194 @code{define_attr}. Extensive use of default values for attributes
9195 permits the specification of the values for only one or two attributes
9196 in the definition of most insn patterns, as seen in the example in the
9199 The optional last argument of @code{define_insn} and
9200 @code{define_peephole} is a vector of expressions, each of which defines
9201 the value for a single attribute. The most general way of assigning an
9202 attribute's value is to use a @code{set} expression whose first operand is an
9203 @code{attr} expression giving the name of the attribute being set. The
9204 second operand of the @code{set} is an attribute expression
9205 (@pxref{Expressions}) giving the value of the attribute.
9207 When the attribute value depends on the @samp{alternative} attribute
9208 (i.e., which is the applicable alternative in the constraint of the
9209 insn), the @code{set_attr_alternative} expression can be used. It
9210 allows the specification of a vector of attribute expressions, one for
9214 When the generality of arbitrary attribute expressions is not required,
9215 the simpler @code{set_attr} expression can be used, which allows
9216 specifying a string giving either a single attribute value or a list
9217 of attribute values, one for each alternative.
9219 The form of each of the above specifications is shown below. In each case,
9220 @var{name} is a string specifying the attribute to be set.
9223 @item (set_attr @var{name} @var{value-string})
9224 @var{value-string} is either a string giving the desired attribute value,
9225 or a string containing a comma-separated list giving the values for
9226 succeeding alternatives. The number of elements must match the number
9227 of alternatives in the constraint of the insn pattern.
9229 Note that it may be useful to specify @samp{*} for some alternative, in
9230 which case the attribute will assume its default value for insns matching
9233 @findex set_attr_alternative
9234 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
9235 Depending on the alternative of the insn, the value will be one of the
9236 specified values. This is a shorthand for using a @code{cond} with
9237 tests on the @samp{alternative} attribute.
9240 @item (set (attr @var{name}) @var{value})
9241 The first operand of this @code{set} must be the special RTL expression
9242 @code{attr}, whose sole operand is a string giving the name of the
9243 attribute being set. @var{value} is the value of the attribute.
9246 The following shows three different ways of representing the same
9247 attribute value specification:
9250 (set_attr "type" "load,store,arith")
9252 (set_attr_alternative "type"
9253 [(const_string "load") (const_string "store")
9254 (const_string "arith")])
9257 (cond [(eq_attr "alternative" "1") (const_string "load")
9258 (eq_attr "alternative" "2") (const_string "store")]
9259 (const_string "arith")))
9263 @findex define_asm_attributes
9264 The @code{define_asm_attributes} expression provides a mechanism to
9265 specify the attributes assigned to insns produced from an @code{asm}
9266 statement. It has the form:
9269 (define_asm_attributes [@var{attr-sets}])
9273 where @var{attr-sets} is specified the same as for both the
9274 @code{define_insn} and the @code{define_peephole} expressions.
9276 These values will typically be the ``worst case'' attribute values. For
9277 example, they might indicate that the condition code will be clobbered.
9279 A specification for a @code{length} attribute is handled specially. The
9280 way to compute the length of an @code{asm} insn is to multiply the
9281 length specified in the expression @code{define_asm_attributes} by the
9282 number of machine instructions specified in the @code{asm} statement,
9283 determined by counting the number of semicolons and newlines in the
9284 string. Therefore, the value of the @code{length} attribute specified
9285 in a @code{define_asm_attributes} should be the maximum possible length
9286 of a single machine instruction.
9291 @subsection Example of Attribute Specifications
9292 @cindex attribute specifications example
9293 @cindex attribute specifications
9295 The judicious use of defaulting is important in the efficient use of
9296 insn attributes. Typically, insns are divided into @dfn{types} and an
9297 attribute, customarily called @code{type}, is used to represent this
9298 value. This attribute is normally used only to define the default value
9299 for other attributes. An example will clarify this usage.
9301 Assume we have a RISC machine with a condition code and in which only
9302 full-word operations are performed in registers. Let us assume that we
9303 can divide all insns into loads, stores, (integer) arithmetic
9304 operations, floating point operations, and branches.
9306 Here we will concern ourselves with determining the effect of an insn on
9307 the condition code and will limit ourselves to the following possible
9308 effects: The condition code can be set unpredictably (clobbered), not
9309 be changed, be set to agree with the results of the operation, or only
9310 changed if the item previously set into the condition code has been
9313 Here is part of a sample @file{md} file for such a machine:
9316 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
9318 (define_attr "cc" "clobber,unchanged,set,change0"
9319 (cond [(eq_attr "type" "load")
9320 (const_string "change0")
9321 (eq_attr "type" "store,branch")
9322 (const_string "unchanged")
9323 (eq_attr "type" "arith")
9324 (if_then_else (match_operand:SI 0 "" "")
9325 (const_string "set")
9326 (const_string "clobber"))]
9327 (const_string "clobber")))
9330 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
9331 (match_operand:SI 1 "general_operand" "r,m,r"))]
9337 [(set_attr "type" "arith,load,store")])
9340 Note that we assume in the above example that arithmetic operations
9341 performed on quantities smaller than a machine word clobber the condition
9342 code since they will set the condition code to a value corresponding to the
9348 @subsection Computing the Length of an Insn
9349 @cindex insn lengths, computing
9350 @cindex computing the length of an insn
9352 For many machines, multiple types of branch instructions are provided, each
9353 for different length branch displacements. In most cases, the assembler
9354 will choose the correct instruction to use. However, when the assembler
9355 cannot do so, GCC can when a special attribute, the @code{length}
9356 attribute, is defined. This attribute must be defined to have numeric
9357 values by specifying a null string in its @code{define_attr}.
9359 In the case of the @code{length} attribute, two additional forms of
9360 arithmetic terms are allowed in test expressions:
9363 @cindex @code{match_dup} and attributes
9364 @item (match_dup @var{n})
9365 This refers to the address of operand @var{n} of the current insn, which
9366 must be a @code{label_ref}.
9368 @cindex @code{pc} and attributes
9370 For non-branch instructions and backward branch instructions, this refers
9371 to the address of the current insn. But for forward branch instructions,
9372 this refers to the address of the next insn, because the length of the
9373 current insn is to be computed.
9376 @cindex @code{addr_vec}, length of
9377 @cindex @code{addr_diff_vec}, length of
9378 For normal insns, the length will be determined by value of the
9379 @code{length} attribute. In the case of @code{addr_vec} and
9380 @code{addr_diff_vec} insn patterns, the length is computed as
9381 the number of vectors multiplied by the size of each vector.
9383 Lengths are measured in addressable storage units (bytes).
9385 Note that it is possible to call functions via the @code{symbol_ref}
9386 mechanism to compute the length of an insn. However, if you use this
9387 mechanism you must provide dummy clauses to express the maximum length
9388 without using the function call. You can an example of this in the
9389 @code{pa} machine description for the @code{call_symref} pattern.
9391 The following macros can be used to refine the length computation:
9394 @findex ADJUST_INSN_LENGTH
9395 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
9396 If defined, modifies the length assigned to instruction @var{insn} as a
9397 function of the context in which it is used. @var{length} is an lvalue
9398 that contains the initially computed length of the insn and should be
9399 updated with the correct length of the insn.
9401 This macro will normally not be required. A case in which it is
9402 required is the ROMP@. On this machine, the size of an @code{addr_vec}
9403 insn must be increased by two to compensate for the fact that alignment
9407 @findex get_attr_length
9408 The routine that returns @code{get_attr_length} (the value of the
9409 @code{length} attribute) can be used by the output routine to
9410 determine the form of the branch instruction to be written, as the
9411 example below illustrates.
9413 As an example of the specification of variable-length branches, consider
9414 the IBM 360. If we adopt the convention that a register will be set to
9415 the starting address of a function, we can jump to labels within 4k of
9416 the start using a four-byte instruction. Otherwise, we need a six-byte
9417 sequence to load the address from memory and then branch to it.
9419 On such a machine, a pattern for a branch instruction might be specified
9425 (label_ref (match_operand 0 "" "")))]
9428 return (get_attr_length (insn) == 4
9429 ? "b %l0" : "l r15,=a(%l0); br r15");
9431 [(set (attr "length")
9432 (if_then_else (lt (match_dup 0) (const_int 4096))
9439 @node Constant Attributes
9440 @subsection Constant Attributes
9441 @cindex constant attributes
9443 A special form of @code{define_attr}, where the expression for the
9444 default value is a @code{const} expression, indicates an attribute that
9445 is constant for a given run of the compiler. Constant attributes may be
9446 used to specify which variety of processor is used. For example,
9449 (define_attr "cpu" "m88100,m88110,m88000"
9451 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
9452 (symbol_ref "TARGET_88110") (const_string "m88110")]
9453 (const_string "m88000"))))
9455 (define_attr "memory" "fast,slow"
9457 (if_then_else (symbol_ref "TARGET_FAST_MEM")
9458 (const_string "fast")
9459 (const_string "slow"))))
9462 The routine generated for constant attributes has no parameters as it
9463 does not depend on any particular insn. RTL expressions used to define
9464 the value of a constant attribute may use the @code{symbol_ref} form,
9465 but may not use either the @code{match_operand} form or @code{eq_attr}
9466 forms involving insn attributes.
9470 @node Mnemonic Attribute
9471 @subsection Mnemonic Attribute
9472 @cindex mnemonic attribute
9474 The @code{mnemonic} attribute is a string type attribute holding the
9475 instruction mnemonic for an insn alternative. The attribute values
9476 will automatically be generated by the machine description parser if
9477 there is an attribute definition in the md file:
9480 (define_attr "mnemonic" "unknown" (const_string "unknown"))
9483 The default value can be freely chosen as long as it does not collide
9484 with any of the instruction mnemonics. This value will be used
9485 whenever the machine description parser is not able to determine the
9486 mnemonic string. This might be the case for output templates
9487 containing more than a single instruction as in
9488 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
9490 The @code{mnemonic} attribute set is not generated automatically if the
9491 instruction string is generated via C code.
9493 An existing @code{mnemonic} attribute set in an insn definition will not
9494 be overriden by the md file parser. That way it is possible to
9495 manually set the instruction mnemonics for the cases where the md file
9496 parser fails to determine it automatically.
9498 The @code{mnemonic} attribute is useful for dealing with instruction
9499 specific properties in the pipeline description without defining
9500 additional insn attributes.
9503 (define_attr "ooo_expanded" ""
9504 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
9512 @subsection Delay Slot Scheduling
9513 @cindex delay slots, defining
9515 The insn attribute mechanism can be used to specify the requirements for
9516 delay slots, if any, on a target machine. An instruction is said to
9517 require a @dfn{delay slot} if some instructions that are physically
9518 after the instruction are executed as if they were located before it.
9519 Classic examples are branch and call instructions, which often execute
9520 the following instruction before the branch or call is performed.
9522 On some machines, conditional branch instructions can optionally
9523 @dfn{annul} instructions in the delay slot. This means that the
9524 instruction will not be executed for certain branch outcomes. Both
9525 instructions that annul if the branch is true and instructions that
9526 annul if the branch is false are supported.
9528 Delay slot scheduling differs from instruction scheduling in that
9529 determining whether an instruction needs a delay slot is dependent only
9530 on the type of instruction being generated, not on data flow between the
9531 instructions. See the next section for a discussion of data-dependent
9532 instruction scheduling.
9534 @findex define_delay
9535 The requirement of an insn needing one or more delay slots is indicated
9536 via the @code{define_delay} expression. It has the following form:
9539 (define_delay @var{test}
9540 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
9541 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
9545 @var{test} is an attribute test that indicates whether this
9546 @code{define_delay} applies to a particular insn. If so, the number of
9547 required delay slots is determined by the length of the vector specified
9548 as the second argument. An insn placed in delay slot @var{n} must
9549 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
9550 attribute test that specifies which insns may be annulled if the branch
9551 is true. Similarly, @var{annul-false-n} specifies which insns in the
9552 delay slot may be annulled if the branch is false. If annulling is not
9553 supported for that delay slot, @code{(nil)} should be coded.
9555 For example, in the common case where branch and call insns require
9556 a single delay slot, which may contain any insn other than a branch or
9557 call, the following would be placed in the @file{md} file:
9560 (define_delay (eq_attr "type" "branch,call")
9561 [(eq_attr "type" "!branch,call") (nil) (nil)])
9564 Multiple @code{define_delay} expressions may be specified. In this
9565 case, each such expression specifies different delay slot requirements
9566 and there must be no insn for which tests in two @code{define_delay}
9567 expressions are both true.
9569 For example, if we have a machine that requires one delay slot for branches
9570 but two for calls, no delay slot can contain a branch or call insn,
9571 and any valid insn in the delay slot for the branch can be annulled if the
9572 branch is true, we might represent this as follows:
9575 (define_delay (eq_attr "type" "branch")
9576 [(eq_attr "type" "!branch,call")
9577 (eq_attr "type" "!branch,call")
9580 (define_delay (eq_attr "type" "call")
9581 [(eq_attr "type" "!branch,call") (nil) (nil)
9582 (eq_attr "type" "!branch,call") (nil) (nil)])
9584 @c the above is *still* too long. --mew 4feb93
9588 @node Processor pipeline description
9589 @subsection Specifying processor pipeline description
9590 @cindex processor pipeline description
9591 @cindex processor functional units
9592 @cindex instruction latency time
9593 @cindex interlock delays
9594 @cindex data dependence delays
9595 @cindex reservation delays
9596 @cindex pipeline hazard recognizer
9597 @cindex automaton based pipeline description
9598 @cindex regular expressions
9599 @cindex deterministic finite state automaton
9600 @cindex automaton based scheduler
9604 To achieve better performance, most modern processors
9605 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
9606 processors) have many @dfn{functional units} on which several
9607 instructions can be executed simultaneously. An instruction starts
9608 execution if its issue conditions are satisfied. If not, the
9609 instruction is stalled until its conditions are satisfied. Such
9610 @dfn{interlock (pipeline) delay} causes interruption of the fetching
9611 of successor instructions (or demands nop instructions, e.g.@: for some
9614 There are two major kinds of interlock delays in modern processors.
9615 The first one is a data dependence delay determining @dfn{instruction
9616 latency time}. The instruction execution is not started until all
9617 source data have been evaluated by prior instructions (there are more
9618 complex cases when the instruction execution starts even when the data
9619 are not available but will be ready in given time after the
9620 instruction execution start). Taking the data dependence delays into
9621 account is simple. The data dependence (true, output, and
9622 anti-dependence) delay between two instructions is given by a
9623 constant. In most cases this approach is adequate. The second kind
9624 of interlock delays is a reservation delay. The reservation delay
9625 means that two instructions under execution will be in need of shared
9626 processors resources, i.e.@: buses, internal registers, and/or
9627 functional units, which are reserved for some time. Taking this kind
9628 of delay into account is complex especially for modern @acronym{RISC}
9631 The task of exploiting more processor parallelism is solved by an
9632 instruction scheduler. For a better solution to this problem, the
9633 instruction scheduler has to have an adequate description of the
9634 processor parallelism (or @dfn{pipeline description}). GCC
9635 machine descriptions describe processor parallelism and functional
9636 unit reservations for groups of instructions with the aid of
9637 @dfn{regular expressions}.
9639 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
9640 figure out the possibility of the instruction issue by the processor
9641 on a given simulated processor cycle. The pipeline hazard recognizer is
9642 automatically generated from the processor pipeline description. The
9643 pipeline hazard recognizer generated from the machine description
9644 is based on a deterministic finite state automaton (@acronym{DFA}):
9645 the instruction issue is possible if there is a transition from one
9646 automaton state to another one. This algorithm is very fast, and
9647 furthermore, its speed is not dependent on processor
9648 complexity@footnote{However, the size of the automaton depends on
9649 processor complexity. To limit this effect, machine descriptions
9650 can split orthogonal parts of the machine description among several
9651 automata: but then, since each of these must be stepped independently,
9652 this does cause a small decrease in the algorithm's performance.}.
9654 @cindex automaton based pipeline description
9655 The rest of this section describes the directives that constitute
9656 an automaton-based processor pipeline description. The order of
9657 these constructions within the machine description file is not
9660 @findex define_automaton
9661 @cindex pipeline hazard recognizer
9662 The following optional construction describes names of automata
9663 generated and used for the pipeline hazards recognition. Sometimes
9664 the generated finite state automaton used by the pipeline hazard
9665 recognizer is large. If we use more than one automaton and bind functional
9666 units to the automata, the total size of the automata is usually
9667 less than the size of the single automaton. If there is no one such
9668 construction, only one finite state automaton is generated.
9671 (define_automaton @var{automata-names})
9674 @var{automata-names} is a string giving names of the automata. The
9675 names are separated by commas. All the automata should have unique names.
9676 The automaton name is used in the constructions @code{define_cpu_unit} and
9677 @code{define_query_cpu_unit}.
9679 @findex define_cpu_unit
9680 @cindex processor functional units
9681 Each processor functional unit used in the description of instruction
9682 reservations should be described by the following construction.
9685 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
9688 @var{unit-names} is a string giving the names of the functional units
9689 separated by commas. Don't use name @samp{nothing}, it is reserved
9692 @var{automaton-name} is a string giving the name of the automaton with
9693 which the unit is bound. The automaton should be described in
9694 construction @code{define_automaton}. You should give
9695 @dfn{automaton-name}, if there is a defined automaton.
9697 The assignment of units to automata are constrained by the uses of the
9698 units in insn reservations. The most important constraint is: if a
9699 unit reservation is present on a particular cycle of an alternative
9700 for an insn reservation, then some unit from the same automaton must
9701 be present on the same cycle for the other alternatives of the insn
9702 reservation. The rest of the constraints are mentioned in the
9703 description of the subsequent constructions.
9705 @findex define_query_cpu_unit
9706 @cindex querying function unit reservations
9707 The following construction describes CPU functional units analogously
9708 to @code{define_cpu_unit}. The reservation of such units can be
9709 queried for an automaton state. The instruction scheduler never
9710 queries reservation of functional units for given automaton state. So
9711 as a rule, you don't need this construction. This construction could
9712 be used for future code generation goals (e.g.@: to generate
9713 @acronym{VLIW} insn templates).
9716 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
9719 @var{unit-names} is a string giving names of the functional units
9720 separated by commas.
9722 @var{automaton-name} is a string giving the name of the automaton with
9723 which the unit is bound.
9725 @findex define_insn_reservation
9726 @cindex instruction latency time
9727 @cindex regular expressions
9729 The following construction is the major one to describe pipeline
9730 characteristics of an instruction.
9733 (define_insn_reservation @var{insn-name} @var{default_latency}
9734 @var{condition} @var{regexp})
9737 @var{default_latency} is a number giving latency time of the
9738 instruction. There is an important difference between the old
9739 description and the automaton based pipeline description. The latency
9740 time is used for all dependencies when we use the old description. In
9741 the automaton based pipeline description, the given latency time is only
9742 used for true dependencies. The cost of anti-dependencies is always
9743 zero and the cost of output dependencies is the difference between
9744 latency times of the producing and consuming insns (if the difference
9745 is negative, the cost is considered to be zero). You can always
9746 change the default costs for any description by using the target hook
9747 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
9749 @var{insn-name} is a string giving the internal name of the insn. The
9750 internal names are used in constructions @code{define_bypass} and in
9751 the automaton description file generated for debugging. The internal
9752 name has nothing in common with the names in @code{define_insn}. It is a
9753 good practice to use insn classes described in the processor manual.
9755 @var{condition} defines what RTL insns are described by this
9756 construction. You should remember that you will be in trouble if
9757 @var{condition} for two or more different
9758 @code{define_insn_reservation} constructions is TRUE for an insn. In
9759 this case what reservation will be used for the insn is not defined.
9760 Such cases are not checked during generation of the pipeline hazards
9761 recognizer because in general recognizing that two conditions may have
9762 the same value is quite difficult (especially if the conditions
9763 contain @code{symbol_ref}). It is also not checked during the
9764 pipeline hazard recognizer work because it would slow down the
9765 recognizer considerably.
9767 @var{regexp} is a string describing the reservation of the cpu's functional
9768 units by the instruction. The reservations are described by a regular
9769 expression according to the following syntax:
9772 regexp = regexp "," oneof
9775 oneof = oneof "|" allof
9778 allof = allof "+" repeat
9781 repeat = element "*" number
9784 element = cpu_function_unit_name
9793 @samp{,} is used for describing the start of the next cycle in
9797 @samp{|} is used for describing a reservation described by the first
9798 regular expression @strong{or} a reservation described by the second
9799 regular expression @strong{or} etc.
9802 @samp{+} is used for describing a reservation described by the first
9803 regular expression @strong{and} a reservation described by the
9804 second regular expression @strong{and} etc.
9807 @samp{*} is used for convenience and simply means a sequence in which
9808 the regular expression are repeated @var{number} times with cycle
9809 advancing (see @samp{,}).
9812 @samp{cpu_function_unit_name} denotes reservation of the named
9816 @samp{reservation_name} --- see description of construction
9817 @samp{define_reservation}.
9820 @samp{nothing} denotes no unit reservations.
9823 @findex define_reservation
9824 Sometimes unit reservations for different insns contain common parts.
9825 In such case, you can simplify the pipeline description by describing
9826 the common part by the following construction
9829 (define_reservation @var{reservation-name} @var{regexp})
9832 @var{reservation-name} is a string giving name of @var{regexp}.
9833 Functional unit names and reservation names are in the same name
9834 space. So the reservation names should be different from the
9835 functional unit names and can not be the reserved name @samp{nothing}.
9837 @findex define_bypass
9838 @cindex instruction latency time
9840 The following construction is used to describe exceptions in the
9841 latency time for given instruction pair. This is so called bypasses.
9844 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
9848 @var{number} defines when the result generated by the instructions
9849 given in string @var{out_insn_names} will be ready for the
9850 instructions given in string @var{in_insn_names}. Each of these
9851 strings is a comma-separated list of filename-style globs and
9852 they refer to the names of @code{define_insn_reservation}s.
9855 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
9857 defines a bypass between instructions that start with
9858 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
9861 @var{guard} is an optional string giving the name of a C function which
9862 defines an additional guard for the bypass. The function will get the
9863 two insns as parameters. If the function returns zero the bypass will
9864 be ignored for this case. The additional guard is necessary to
9865 recognize complicated bypasses, e.g.@: when the consumer is only an address
9866 of insn @samp{store} (not a stored value).
9868 If there are more one bypass with the same output and input insns, the
9869 chosen bypass is the first bypass with a guard in description whose
9870 guard function returns nonzero. If there is no such bypass, then
9871 bypass without the guard function is chosen.
9873 @findex exclusion_set
9874 @findex presence_set
9875 @findex final_presence_set
9877 @findex final_absence_set
9880 The following five constructions are usually used to describe
9881 @acronym{VLIW} processors, or more precisely, to describe a placement
9882 of small instructions into @acronym{VLIW} instruction slots. They
9883 can be used for @acronym{RISC} processors, too.
9886 (exclusion_set @var{unit-names} @var{unit-names})
9887 (presence_set @var{unit-names} @var{patterns})
9888 (final_presence_set @var{unit-names} @var{patterns})
9889 (absence_set @var{unit-names} @var{patterns})
9890 (final_absence_set @var{unit-names} @var{patterns})
9893 @var{unit-names} is a string giving names of functional units
9894 separated by commas.
9896 @var{patterns} is a string giving patterns of functional units
9897 separated by comma. Currently pattern is one unit or units
9898 separated by white-spaces.
9900 The first construction (@samp{exclusion_set}) means that each
9901 functional unit in the first string can not be reserved simultaneously
9902 with a unit whose name is in the second string and vice versa. For
9903 example, the construction is useful for describing processors
9904 (e.g.@: some SPARC processors) with a fully pipelined floating point
9905 functional unit which can execute simultaneously only single floating
9906 point insns or only double floating point insns.
9908 The second construction (@samp{presence_set}) means that each
9909 functional unit in the first string can not be reserved unless at
9910 least one of pattern of units whose names are in the second string is
9911 reserved. This is an asymmetric relation. For example, it is useful
9912 for description that @acronym{VLIW} @samp{slot1} is reserved after
9913 @samp{slot0} reservation. We could describe it by the following
9917 (presence_set "slot1" "slot0")
9920 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
9921 reservation. In this case we could write
9924 (presence_set "slot1" "slot0 b0")
9927 The third construction (@samp{final_presence_set}) is analogous to
9928 @samp{presence_set}. The difference between them is when checking is
9929 done. When an instruction is issued in given automaton state
9930 reflecting all current and planned unit reservations, the automaton
9931 state is changed. The first state is a source state, the second one
9932 is a result state. Checking for @samp{presence_set} is done on the
9933 source state reservation, checking for @samp{final_presence_set} is
9934 done on the result reservation. This construction is useful to
9935 describe a reservation which is actually two subsequent reservations.
9936 For example, if we use
9939 (presence_set "slot1" "slot0")
9942 the following insn will be never issued (because @samp{slot1} requires
9943 @samp{slot0} which is absent in the source state).
9946 (define_reservation "insn_and_nop" "slot0 + slot1")
9949 but it can be issued if we use analogous @samp{final_presence_set}.
9951 The forth construction (@samp{absence_set}) means that each functional
9952 unit in the first string can be reserved only if each pattern of units
9953 whose names are in the second string is not reserved. This is an
9954 asymmetric relation (actually @samp{exclusion_set} is analogous to
9955 this one but it is symmetric). For example it might be useful in a
9956 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
9957 after either @samp{slot1} or @samp{slot2} have been reserved. This
9958 can be described as:
9961 (absence_set "slot0" "slot1, slot2")
9964 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
9965 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
9966 this case we could write
9969 (absence_set "slot2" "slot0 b0, slot1 b1")
9972 All functional units mentioned in a set should belong to the same
9975 The last construction (@samp{final_absence_set}) is analogous to
9976 @samp{absence_set} but checking is done on the result (state)
9977 reservation. See comments for @samp{final_presence_set}.
9979 @findex automata_option
9980 @cindex deterministic finite state automaton
9981 @cindex nondeterministic finite state automaton
9982 @cindex finite state automaton minimization
9983 You can control the generator of the pipeline hazard recognizer with
9984 the following construction.
9987 (automata_option @var{options})
9990 @var{options} is a string giving options which affect the generated
9991 code. Currently there are the following options:
9995 @dfn{no-minimization} makes no minimization of the automaton. This is
9996 only worth to do when we are debugging the description and need to
9997 look more accurately at reservations of states.
10000 @dfn{time} means printing time statistics about the generation of
10004 @dfn{stats} means printing statistics about the generated automata
10005 such as the number of DFA states, NDFA states and arcs.
10008 @dfn{v} means a generation of the file describing the result automata.
10009 The file has suffix @samp{.dfa} and can be used for the description
10010 verification and debugging.
10013 @dfn{w} means a generation of warning instead of error for
10014 non-critical errors.
10017 @dfn{no-comb-vect} prevents the automaton generator from generating
10018 two data structures and comparing them for space efficiency. Using
10019 a comb vector to represent transitions may be better, but it can be
10020 very expensive to construct. This option is useful if the build
10021 process spends an unacceptably long time in genautomata.
10024 @dfn{ndfa} makes nondeterministic finite state automata. This affects
10025 the treatment of operator @samp{|} in the regular expressions. The
10026 usual treatment of the operator is to try the first alternative and,
10027 if the reservation is not possible, the second alternative. The
10028 nondeterministic treatment means trying all alternatives, some of them
10029 may be rejected by reservations in the subsequent insns.
10032 @dfn{collapse-ndfa} modifies the behavior of the generator when
10033 producing an automaton. An additional state transition to collapse a
10034 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
10035 state is generated. It can be triggered by passing @code{const0_rtx} to
10036 state_transition. In such an automaton, cycle advance transitions are
10037 available only for these collapsed states. This option is useful for
10038 ports that want to use the @code{ndfa} option, but also want to use
10039 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
10042 @dfn{progress} means output of a progress bar showing how many states
10043 were generated so far for automaton being processed. This is useful
10044 during debugging a @acronym{DFA} description. If you see too many
10045 generated states, you could interrupt the generator of the pipeline
10046 hazard recognizer and try to figure out a reason for generation of the
10050 As an example, consider a superscalar @acronym{RISC} machine which can
10051 issue three insns (two integer insns and one floating point insn) on
10052 the cycle but can finish only two insns. To describe this, we define
10053 the following functional units.
10056 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
10057 (define_cpu_unit "port0, port1")
10060 All simple integer insns can be executed in any integer pipeline and
10061 their result is ready in two cycles. The simple integer insns are
10062 issued into the first pipeline unless it is reserved, otherwise they
10063 are issued into the second pipeline. Integer division and
10064 multiplication insns can be executed only in the second integer
10065 pipeline and their results are ready correspondingly in 9 and 4
10066 cycles. The integer division is not pipelined, i.e.@: the subsequent
10067 integer division insn can not be issued until the current division
10068 insn finished. Floating point insns are fully pipelined and their
10069 results are ready in 3 cycles. Where the result of a floating point
10070 insn is used by an integer insn, an additional delay of one cycle is
10071 incurred. To describe all of this we could specify
10074 (define_cpu_unit "div")
10076 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
10077 "(i0_pipeline | i1_pipeline), (port0 | port1)")
10079 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
10080 "i1_pipeline, nothing*2, (port0 | port1)")
10082 (define_insn_reservation "div" 9 (eq_attr "type" "div")
10083 "i1_pipeline, div*7, div + (port0 | port1)")
10085 (define_insn_reservation "float" 3 (eq_attr "type" "float")
10086 "f_pipeline, nothing, (port0 | port1))
10088 (define_bypass 4 "float" "simple,mult,div")
10091 To simplify the description we could describe the following reservation
10094 (define_reservation "finish" "port0|port1")
10097 and use it in all @code{define_insn_reservation} as in the following
10101 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
10102 "(i0_pipeline | i1_pipeline), finish")
10108 @node Conditional Execution
10109 @section Conditional Execution
10110 @cindex conditional execution
10111 @cindex predication
10113 A number of architectures provide for some form of conditional
10114 execution, or predication. The hallmark of this feature is the
10115 ability to nullify most of the instructions in the instruction set.
10116 When the instruction set is large and not entirely symmetric, it
10117 can be quite tedious to describe these forms directly in the
10118 @file{.md} file. An alternative is the @code{define_cond_exec} template.
10120 @findex define_cond_exec
10123 [@var{predicate-pattern}]
10125 "@var{output-template}"
10126 "@var{optional-insn-attribues}")
10129 @var{predicate-pattern} is the condition that must be true for the
10130 insn to be executed at runtime and should match a relational operator.
10131 One can use @code{match_operator} to match several relational operators
10132 at once. Any @code{match_operand} operands must have no more than one
10135 @var{condition} is a C expression that must be true for the generated
10138 @findex current_insn_predicate
10139 @var{output-template} is a string similar to the @code{define_insn}
10140 output template (@pxref{Output Template}), except that the @samp{*}
10141 and @samp{@@} special cases do not apply. This is only useful if the
10142 assembly text for the predicate is a simple prefix to the main insn.
10143 In order to handle the general case, there is a global variable
10144 @code{current_insn_predicate} that will contain the entire predicate
10145 if the current insn is predicated, and will otherwise be @code{NULL}.
10147 @var{optional-insn-attributes} is an optional vector of attributes that gets
10148 appended to the insn attributes of the produced cond_exec rtx. It can
10149 be used to add some distinguishing attribute to cond_exec rtxs produced
10150 that way. An example usage would be to use this attribute in conjunction
10151 with attributes on the main pattern to disable particular alternatives under
10152 certain conditions.
10154 When @code{define_cond_exec} is used, an implicit reference to
10155 the @code{predicable} instruction attribute is made.
10156 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
10157 exactly two elements in its @var{list-of-values}), with the possible
10158 values being @code{no} and @code{yes}. The default and all uses in
10159 the insns must be a simple constant, not a complex expressions. It
10160 may, however, depend on the alternative, by using a comma-separated
10161 list of values. If that is the case, the port should also define an
10162 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
10163 should also allow only @code{no} and @code{yes} as its values.
10165 For each @code{define_insn} for which the @code{predicable}
10166 attribute is true, a new @code{define_insn} pattern will be
10167 generated that matches a predicated version of the instruction.
10171 (define_insn "addsi"
10172 [(set (match_operand:SI 0 "register_operand" "r")
10173 (plus:SI (match_operand:SI 1 "register_operand" "r")
10174 (match_operand:SI 2 "register_operand" "r")))]
10179 [(ne (match_operand:CC 0 "register_operand" "c")
10186 generates a new pattern
10191 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
10192 (set (match_operand:SI 0 "register_operand" "r")
10193 (plus:SI (match_operand:SI 1 "register_operand" "r")
10194 (match_operand:SI 2 "register_operand" "r"))))]
10195 "(@var{test2}) && (@var{test1})"
10196 "(%3) add %2,%1,%0")
10202 @section RTL Templates Transformations
10203 @cindex define_subst
10205 For some hardware architectures there are common cases when the RTL
10206 templates for the instructions can be derived from the other RTL
10207 templates using simple transformations. E.g., @file{i386.md} contains
10208 an RTL template for the ordinary @code{sub} instruction---
10209 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
10210 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
10211 implemented by a single meta-template capable of generating a modified
10212 case based on the initial one:
10214 @findex define_subst
10216 (define_subst "@var{name}"
10217 [@var{input-template}]
10219 [@var{output-template}])
10221 @var{input-template} is a pattern describing the source RTL template,
10222 which will be transformed.
10224 @var{condition} is a C expression that is conjunct with the condition
10225 from the input-template to generate a condition to be used in the
10228 @var{output-template} is a pattern that will be used in the resulting
10231 @code{define_subst} mechanism is tightly coupled with the notion of the
10232 subst attribute (@pxref{Subst Iterators}). The use of
10233 @code{define_subst} is triggered by a reference to a subst attribute in
10234 the transforming RTL template. This reference initiates duplication of
10235 the source RTL template and substitution of the attributes with their
10236 values. The source RTL template is left unchanged, while the copy is
10237 transformed by @code{define_subst}. This transformation can fail in the
10238 case when the source RTL template is not matched against the
10239 input-template of the @code{define_subst}. In such case the copy is
10242 @code{define_subst} can be used only in @code{define_insn} and
10243 @code{define_expand}, it cannot be used in other expressions (e.g.@: in
10244 @code{define_insn_and_split}).
10247 * Define Subst Example:: Example of @code{define_subst} work.
10248 * Define Subst Pattern Matching:: Process of template comparison.
10249 * Define Subst Output Template:: Generation of output template.
10252 @node Define Subst Example
10253 @subsection @code{define_subst} Example
10254 @cindex define_subst
10256 To illustrate how @code{define_subst} works, let us examine a simple
10257 template transformation.
10259 Suppose there are two kinds of instructions: one that touches flags and
10260 the other that does not. The instructions of the second type could be
10261 generated with the following @code{define_subst}:
10264 (define_subst "add_clobber_subst"
10265 [(set (match_operand:SI 0 "" "")
10266 (match_operand:SI 1 "" ""))]
10268 [(set (match_dup 0)
10270 (clobber (reg:CC FLAGS_REG))]
10273 This @code{define_subst} can be applied to any RTL pattern containing
10274 @code{set} of mode SI and generates a copy with clobber when it is
10277 Assume there is an RTL template for a @code{max} instruction to be used
10278 in @code{define_subst} mentioned above:
10281 (define_insn "maxsi"
10282 [(set (match_operand:SI 0 "register_operand" "=r")
10284 (match_operand:SI 1 "register_operand" "r")
10285 (match_operand:SI 2 "register_operand" "r")))]
10287 "max\t@{%2, %1, %0|%0, %1, %2@}"
10291 To mark the RTL template for @code{define_subst} application,
10292 subst-attributes are used. They should be declared in advance:
10295 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
10298 Here @samp{add_clobber_name} is the attribute name,
10299 @samp{add_clobber_subst} is the name of the corresponding
10300 @code{define_subst}, the third argument (@samp{_noclobber}) is the
10301 attribute value that would be substituted into the unchanged version of
10302 the source RTL template, and the last argument (@samp{_clobber}) is the
10303 value that would be substituted into the second, transformed,
10304 version of the RTL template.
10306 Once the subst-attribute has been defined, it should be used in RTL
10307 templates which need to be processed by the @code{define_subst}. So,
10308 the original RTL template should be changed:
10311 (define_insn "maxsi<add_clobber_name>"
10312 [(set (match_operand:SI 0 "register_operand" "=r")
10314 (match_operand:SI 1 "register_operand" "r")
10315 (match_operand:SI 2 "register_operand" "r")))]
10317 "max\t@{%2, %1, %0|%0, %1, %2@}"
10321 The result of the @code{define_subst} usage would look like the following:
10324 (define_insn "maxsi_noclobber"
10325 [(set (match_operand:SI 0 "register_operand" "=r")
10327 (match_operand:SI 1 "register_operand" "r")
10328 (match_operand:SI 2 "register_operand" "r")))]
10330 "max\t@{%2, %1, %0|%0, %1, %2@}"
10332 (define_insn "maxsi_clobber"
10333 [(set (match_operand:SI 0 "register_operand" "=r")
10335 (match_operand:SI 1 "register_operand" "r")
10336 (match_operand:SI 2 "register_operand" "r")))
10337 (clobber (reg:CC FLAGS_REG))]
10339 "max\t@{%2, %1, %0|%0, %1, %2@}"
10343 @node Define Subst Pattern Matching
10344 @subsection Pattern Matching in @code{define_subst}
10345 @cindex define_subst
10347 All expressions, allowed in @code{define_insn} or @code{define_expand},
10348 are allowed in the input-template of @code{define_subst}, except
10349 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
10350 meanings of expressions in the input-template were changed:
10352 @code{match_operand} matches any expression (possibly, a subtree in
10353 RTL-template), if modes of the @code{match_operand} and this expression
10354 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
10355 this expression is @code{match_dup}, @code{match_op_dup}. If the
10356 expression is @code{match_operand} too, and predicate of
10357 @code{match_operand} from the input pattern is not empty, then the
10358 predicates are compared. That can be used for more accurate filtering
10359 of accepted RTL-templates.
10361 @code{match_operator} matches common operators (like @code{plus},
10362 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
10363 @code{match_operator}s from the original pattern if the modes match and
10364 @code{match_operator} from the input pattern has the same number of
10365 operands as the operator from the original pattern.
10367 @node Define Subst Output Template
10368 @subsection Generation of output template in @code{define_subst}
10369 @cindex define_subst
10371 If all necessary checks for @code{define_subst} application pass, a new
10372 RTL-pattern, based on the output-template, is created to replace the old
10373 template. Like in input-patterns, meanings of some RTL expressions are
10374 changed when they are used in output-patterns of a @code{define_subst}.
10375 Thus, @code{match_dup} is used for copying the whole expression from the
10376 original pattern, which matched corresponding @code{match_operand} from
10379 @code{match_dup N} is used in the output template to be replaced with
10380 the expression from the original pattern, which matched
10381 @code{match_operand N} from the input pattern. As a consequence,
10382 @code{match_dup} cannot be used to point to @code{match_operand}s from
10383 the output pattern, it should always refer to a @code{match_operand}
10384 from the input pattern. If a @code{match_dup N} occurs more than once
10385 in the output template, its first occurrence is replaced with the
10386 expression from the original pattern, and the subsequent expressions
10387 are replaced with @code{match_dup N}, i.e., a reference to the first
10390 In the output template one can refer to the expressions from the
10391 original pattern and create new ones. For instance, some operands could
10392 be added by means of standard @code{match_operand}.
10394 After replacing @code{match_dup} with some RTL-subtree from the original
10395 pattern, it could happen that several @code{match_operand}s in the
10396 output pattern have the same indexes. It is unknown, how many and what
10397 indexes would be used in the expression which would replace
10398 @code{match_dup}, so such conflicts in indexes are inevitable. To
10399 overcome this issue, @code{match_operands} and @code{match_operators},
10400 which were introduced into the output pattern, are renumerated when all
10401 @code{match_dup}s are replaced.
10403 Number of alternatives in @code{match_operand}s introduced into the
10404 output template @code{M} could differ from the number of alternatives in
10405 the original pattern @code{N}, so in the resultant pattern there would
10406 be @code{N*M} alternatives. Thus, constraints from the original pattern
10407 would be duplicated @code{N} times, constraints from the output pattern
10408 would be duplicated @code{M} times, producing all possible combinations.
10412 @node Constant Definitions
10413 @section Constant Definitions
10414 @cindex constant definitions
10415 @findex define_constants
10417 Using literal constants inside instruction patterns reduces legibility and
10418 can be a maintenance problem.
10420 To overcome this problem, you may use the @code{define_constants}
10421 expression. It contains a vector of name-value pairs. From that
10422 point on, wherever any of the names appears in the MD file, it is as
10423 if the corresponding value had been written instead. You may use
10424 @code{define_constants} multiple times; each appearance adds more
10425 constants to the table. It is an error to redefine a constant with
10428 To come back to the a29k load multiple example, instead of
10432 [(match_parallel 0 "load_multiple_operation"
10433 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10434 (match_operand:SI 2 "memory_operand" "m"))
10436 (clobber (reg:SI 179))])]
10444 (define_constants [
10452 [(match_parallel 0 "load_multiple_operation"
10453 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10454 (match_operand:SI 2 "memory_operand" "m"))
10455 (use (reg:SI R_CR))
10456 (clobber (reg:SI R_CR))])]
10461 The constants that are defined with a define_constant are also output
10462 in the insn-codes.h header file as #defines.
10464 @cindex enumerations
10465 @findex define_c_enum
10466 You can also use the machine description file to define enumerations.
10467 Like the constants defined by @code{define_constant}, these enumerations
10468 are visible to both the machine description file and the main C code.
10470 The syntax is as follows:
10473 (define_c_enum "@var{name}" [
10481 This definition causes the equivalent of the following C code to appear
10482 in @file{insn-constants.h}:
10489 @var{valuen} = @var{n}
10491 #define NUM_@var{cname}_VALUES (@var{n} + 1)
10494 where @var{cname} is the capitalized form of @var{name}.
10495 It also makes each @var{valuei} available in the machine description
10496 file, just as if it had been declared with:
10499 (define_constants [(@var{valuei} @var{i})])
10502 Each @var{valuei} is usually an upper-case identifier and usually
10503 begins with @var{cname}.
10505 You can split the enumeration definition into as many statements as
10506 you like. The above example is directly equivalent to:
10509 (define_c_enum "@var{name}" [@var{value0}])
10510 (define_c_enum "@var{name}" [@var{value1}])
10512 (define_c_enum "@var{name}" [@var{valuen}])
10515 Splitting the enumeration helps to improve the modularity of each
10516 individual @code{.md} file. For example, if a port defines its
10517 synchronization instructions in a separate @file{sync.md} file,
10518 it is convenient to define all synchronization-specific enumeration
10519 values in @file{sync.md} rather than in the main @file{.md} file.
10521 Some enumeration names have special significance to GCC:
10525 @findex unspec_volatile
10526 If an enumeration called @code{unspecv} is defined, GCC will use it
10527 when printing out @code{unspec_volatile} expressions. For example:
10530 (define_c_enum "unspecv" [
10535 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
10538 (unspec_volatile ... UNSPECV_BLOCKAGE)
10543 If an enumeration called @code{unspec} is defined, GCC will use
10544 it when printing out @code{unspec} expressions. GCC will also use
10545 it when printing out @code{unspec_volatile} expressions unless an
10546 @code{unspecv} enumeration is also defined. You can therefore
10547 decide whether to keep separate enumerations for volatile and
10548 non-volatile expressions or whether to use the same enumeration
10552 @findex define_enum
10553 @anchor{define_enum}
10554 Another way of defining an enumeration is to use @code{define_enum}:
10557 (define_enum "@var{name}" [
10565 This directive implies:
10568 (define_c_enum "@var{name}" [
10569 @var{cname}_@var{cvalue0}
10570 @var{cname}_@var{cvalue1}
10572 @var{cname}_@var{cvaluen}
10576 @findex define_enum_attr
10577 where @var{cvaluei} is the capitalized form of @var{valuei}.
10578 However, unlike @code{define_c_enum}, the enumerations defined
10579 by @code{define_enum} can be used in attribute specifications
10580 (@pxref{define_enum_attr}).
10585 @cindex iterators in @file{.md} files
10587 Ports often need to define similar patterns for more than one machine
10588 mode or for more than one rtx code. GCC provides some simple iterator
10589 facilities to make this process easier.
10592 * Mode Iterators:: Generating variations of patterns for different modes.
10593 * Code Iterators:: Doing the same for codes.
10594 * Int Iterators:: Doing the same for integers.
10595 * Subst Iterators:: Generating variations of patterns for define_subst.
10596 * Parameterized Names:: Specifying iterator values in C++ code.
10599 @node Mode Iterators
10600 @subsection Mode Iterators
10601 @cindex mode iterators in @file{.md} files
10603 Ports often need to define similar patterns for two or more different modes.
10608 If a processor has hardware support for both single and double
10609 floating-point arithmetic, the @code{SFmode} patterns tend to be
10610 very similar to the @code{DFmode} ones.
10613 If a port uses @code{SImode} pointers in one configuration and
10614 @code{DImode} pointers in another, it will usually have very similar
10615 @code{SImode} and @code{DImode} patterns for manipulating pointers.
10618 Mode iterators allow several patterns to be instantiated from one
10619 @file{.md} file template. They can be used with any type of
10620 rtx-based construct, such as a @code{define_insn},
10621 @code{define_split}, or @code{define_peephole2}.
10624 * Defining Mode Iterators:: Defining a new mode iterator.
10625 * Substitutions:: Combining mode iterators with substitutions
10626 * Examples:: Examples
10629 @node Defining Mode Iterators
10630 @subsubsection Defining Mode Iterators
10631 @findex define_mode_iterator
10633 The syntax for defining a mode iterator is:
10636 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
10639 This allows subsequent @file{.md} file constructs to use the mode suffix
10640 @code{:@var{name}}. Every construct that does so will be expanded
10641 @var{n} times, once with every use of @code{:@var{name}} replaced by
10642 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
10643 and so on. In the expansion for a particular @var{modei}, every
10644 C condition will also require that @var{condi} be true.
10649 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10652 defines a new mode suffix @code{:P}. Every construct that uses
10653 @code{:P} will be expanded twice, once with every @code{:P} replaced
10654 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
10655 The @code{:SI} version will only apply if @code{Pmode == SImode} and
10656 the @code{:DI} version will only apply if @code{Pmode == DImode}.
10658 As with other @file{.md} conditions, an empty string is treated
10659 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
10660 to @code{@var{mode}}. For example:
10663 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10666 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
10667 but that the @code{:SI} expansion has no such constraint.
10669 Iterators are applied in the order they are defined. This can be
10670 significant if two iterators are used in a construct that requires
10671 substitutions. @xref{Substitutions}.
10673 @node Substitutions
10674 @subsubsection Substitution in Mode Iterators
10675 @findex define_mode_attr
10677 If an @file{.md} file construct uses mode iterators, each version of the
10678 construct will often need slightly different strings or modes. For
10683 When a @code{define_expand} defines several @code{add@var{m}3} patterns
10684 (@pxref{Standard Names}), each expander will need to use the
10685 appropriate mode name for @var{m}.
10688 When a @code{define_insn} defines several instruction patterns,
10689 each instruction will often use a different assembler mnemonic.
10692 When a @code{define_insn} requires operands with different modes,
10693 using an iterator for one of the operand modes usually requires a specific
10694 mode for the other operand(s).
10697 GCC supports such variations through a system of ``mode attributes''.
10698 There are two standard attributes: @code{mode}, which is the name of
10699 the mode in lower case, and @code{MODE}, which is the same thing in
10700 upper case. You can define other attributes using:
10703 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
10706 where @var{name} is the name of the attribute and @var{valuei}
10707 is the value associated with @var{modei}.
10709 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
10710 each string and mode in the pattern for sequences of the form
10711 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
10712 mode attribute. If the attribute is defined for @var{mode}, the whole
10713 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
10716 For example, suppose an @file{.md} file has:
10719 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10720 (define_mode_attr load [(SI "lw") (DI "ld")])
10723 If one of the patterns that uses @code{:P} contains the string
10724 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
10725 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
10726 @code{"ld\t%0,%1"}.
10728 Here is an example of using an attribute for a mode:
10731 (define_mode_iterator LONG [SI DI])
10732 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
10733 (define_insn @dots{}
10734 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
10737 The @code{@var{iterator}:} prefix may be omitted, in which case the
10738 substitution will be attempted for every iterator expansion.
10741 @subsubsection Mode Iterator Examples
10743 Here is an example from the MIPS port. It defines the following
10744 modes and attributes (among others):
10747 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10748 (define_mode_attr d [(SI "") (DI "d")])
10751 and uses the following template to define both @code{subsi3}
10755 (define_insn "sub<mode>3"
10756 [(set (match_operand:GPR 0 "register_operand" "=d")
10757 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
10758 (match_operand:GPR 2 "register_operand" "d")))]
10760 "<d>subu\t%0,%1,%2"
10761 [(set_attr "type" "arith")
10762 (set_attr "mode" "<MODE>")])
10765 This is exactly equivalent to:
10768 (define_insn "subsi3"
10769 [(set (match_operand:SI 0 "register_operand" "=d")
10770 (minus:SI (match_operand:SI 1 "register_operand" "d")
10771 (match_operand:SI 2 "register_operand" "d")))]
10774 [(set_attr "type" "arith")
10775 (set_attr "mode" "SI")])
10777 (define_insn "subdi3"
10778 [(set (match_operand:DI 0 "register_operand" "=d")
10779 (minus:DI (match_operand:DI 1 "register_operand" "d")
10780 (match_operand:DI 2 "register_operand" "d")))]
10783 [(set_attr "type" "arith")
10784 (set_attr "mode" "DI")])
10787 @node Code Iterators
10788 @subsection Code Iterators
10789 @cindex code iterators in @file{.md} files
10790 @findex define_code_iterator
10791 @findex define_code_attr
10793 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
10798 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
10801 defines a pseudo rtx code @var{name} that can be instantiated as
10802 @var{codei} if condition @var{condi} is true. Each @var{codei}
10803 must have the same rtx format. @xref{RTL Classes}.
10805 As with mode iterators, each pattern that uses @var{name} will be
10806 expanded @var{n} times, once with all uses of @var{name} replaced by
10807 @var{code1}, once with all uses replaced by @var{code2}, and so on.
10808 @xref{Defining Mode Iterators}.
10810 It is possible to define attributes for codes as well as for modes.
10811 There are two standard code attributes: @code{code}, the name of the
10812 code in lower case, and @code{CODE}, the name of the code in upper case.
10813 Other attributes are defined using:
10816 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
10819 Here's an example of code iterators in action, taken from the MIPS port:
10822 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
10823 eq ne gt ge lt le gtu geu ltu leu])
10825 (define_expand "b<code>"
10827 (if_then_else (any_cond:CC (cc0)
10829 (label_ref (match_operand 0 ""))
10833 gen_conditional_branch (operands, <CODE>);
10838 This is equivalent to:
10841 (define_expand "bunordered"
10843 (if_then_else (unordered:CC (cc0)
10845 (label_ref (match_operand 0 ""))
10849 gen_conditional_branch (operands, UNORDERED);
10853 (define_expand "bordered"
10855 (if_then_else (ordered:CC (cc0)
10857 (label_ref (match_operand 0 ""))
10861 gen_conditional_branch (operands, ORDERED);
10868 @node Int Iterators
10869 @subsection Int Iterators
10870 @cindex int iterators in @file{.md} files
10871 @findex define_int_iterator
10872 @findex define_int_attr
10874 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
10879 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
10882 defines a pseudo integer constant @var{name} that can be instantiated as
10883 @var{inti} if condition @var{condi} is true. Each @var{int}
10884 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
10885 in only those rtx fields that have 'i' as the specifier. This means that
10886 each @var{int} has to be a constant defined using define_constant or
10889 As with mode and code iterators, each pattern that uses @var{name} will be
10890 expanded @var{n} times, once with all uses of @var{name} replaced by
10891 @var{int1}, once with all uses replaced by @var{int2}, and so on.
10892 @xref{Defining Mode Iterators}.
10894 It is possible to define attributes for ints as well as for codes and modes.
10895 Attributes are defined using:
10898 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
10901 Here's an example of int iterators in action, taken from the ARM port:
10904 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
10906 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
10908 (define_insn "neon_vq<absneg><mode>"
10909 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10910 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10911 (match_operand:SI 2 "immediate_operand" "i")]
10914 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10915 [(set_attr "type" "neon_vqneg_vqabs")]
10920 This is equivalent to:
10923 (define_insn "neon_vqabs<mode>"
10924 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10925 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10926 (match_operand:SI 2 "immediate_operand" "i")]
10929 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10930 [(set_attr "type" "neon_vqneg_vqabs")]
10933 (define_insn "neon_vqneg<mode>"
10934 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10935 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10936 (match_operand:SI 2 "immediate_operand" "i")]
10939 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10940 [(set_attr "type" "neon_vqneg_vqabs")]
10945 @node Subst Iterators
10946 @subsection Subst Iterators
10947 @cindex subst iterators in @file{.md} files
10948 @findex define_subst
10949 @findex define_subst_attr
10951 Subst iterators are special type of iterators with the following
10952 restrictions: they could not be declared explicitly, they always have
10953 only two values, and they do not have explicit dedicated name.
10954 Subst-iterators are triggered only when corresponding subst-attribute is
10955 used in RTL-pattern.
10957 Subst iterators transform templates in the following way: the templates
10958 are duplicated, the subst-attributes in these templates are replaced
10959 with the corresponding values, and a new attribute is implicitly added
10960 to the given @code{define_insn}/@code{define_expand}. The name of the
10961 added attribute matches the name of @code{define_subst}. Such
10962 attributes are declared implicitly, and it is not allowed to have a
10963 @code{define_attr} named as a @code{define_subst}.
10965 Each subst iterator is linked to a @code{define_subst}. It is declared
10966 implicitly by the first appearance of the corresponding
10967 @code{define_subst_attr}, and it is not allowed to define it explicitly.
10969 Declarations of subst-attributes have the following syntax:
10971 @findex define_subst_attr
10973 (define_subst_attr "@var{name}"
10975 "@var{no-subst-value}"
10976 "@var{subst-applied-value}")
10979 @var{name} is a string with which the given subst-attribute could be
10982 @var{subst-name} shows which @code{define_subst} should be applied to an
10983 RTL-template if the given subst-attribute is present in the
10986 @var{no-subst-value} is a value with which subst-attribute would be
10987 replaced in the first copy of the original RTL-template.
10989 @var{subst-applied-value} is a value with which subst-attribute would be
10990 replaced in the second copy of the original RTL-template.
10992 @node Parameterized Names
10993 @subsection Parameterized Names
10994 @cindex @samp{@@} in instruction pattern names
10995 Ports sometimes need to apply iterators using C++ code, in order to
10996 get the code or RTL pattern for a specific instruction. For example,
10997 suppose we have the @samp{neon_vq<absneg><mode>} pattern given above:
11000 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
11002 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
11004 (define_insn "neon_vq<absneg><mode>"
11005 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11006 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11007 (match_operand:SI 2 "immediate_operand" "i")]
11013 A port might need to generate this pattern for a variable
11014 @samp{QABSNEG} value and a variable @samp{VDQIW} mode. There are two
11015 ways of doing this. The first is to build the rtx for the pattern
11016 directly from C++ code; this is a valid technique and avoids any risk
11017 of combinatorial explosion. The second is to prefix the instruction
11018 name with the special character @samp{@@}, which tells GCC to generate
11019 the four additional functions below. In each case, @var{name} is the
11020 name of the instruction without the leading @samp{@@} character,
11021 without the @samp{<@dots{}>} placeholders, and with any underscore
11022 before a @samp{<@dots{}>} placeholder removed if keeping it would
11023 lead to a double or trailing underscore.
11026 @item insn_code maybe_code_for_@var{name} (@var{i1}, @var{i2}, @dots{})
11027 See whether replacing the first @samp{<@dots{}>} placeholder with
11028 iterator value @var{i1}, the second with iterator value @var{i2}, and
11029 so on, gives a valid instruction. Return its code if so, otherwise
11030 return @code{CODE_FOR_nothing}.
11032 @item insn_code code_for_@var{name} (@var{i1}, @var{i2}, @dots{})
11033 Same, but abort the compiler if the requested instruction does not exist.
11035 @item rtx maybe_gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{})
11036 Check for a valid instruction in the same way as
11037 @code{maybe_code_for_@var{name}}. If the instruction exists,
11038 generate an instance of it using the operand values given by @var{op0},
11039 @var{op1}, and so on, otherwise return null.
11041 @item rtx gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{})
11042 Same, but abort the compiler if the requested instruction does not exist,
11043 or if the instruction generator invoked the @code{FAIL} macro.
11046 For example, changing the pattern above to:
11049 (define_insn "@@neon_vq<absneg><mode>"
11050 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11051 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11052 (match_operand:SI 2 "immediate_operand" "i")]
11058 would define the same patterns as before, but in addition would generate
11059 the four functions below:
11062 insn_code maybe_code_for_neon_vq (int, machine_mode);
11063 insn_code code_for_neon_vq (int, machine_mode);
11064 rtx maybe_gen_neon_vq (int, machine_mode, rtx, rtx, rtx);
11065 rtx gen_neon_vq (int, machine_mode, rtx, rtx, rtx);
11068 Calling @samp{code_for_neon_vq (UNSPEC_VQABS, V8QImode)}
11069 would then give @code{CODE_FOR_neon_vqabsv8qi}.
11071 It is possible to have multiple @samp{@@} patterns with the same
11072 name and same types of iterator. For example:
11075 (define_insn "@@some_arithmetic_op<mode>"
11076 [(set (match_operand:INTEGER_MODES 0 "register_operand") @dots{})]
11080 (define_insn "@@some_arithmetic_op<mode>"
11081 [(set (match_operand:FLOAT_MODES 0 "register_operand") @dots{})]
11086 would produce a single set of functions that handles both
11087 @code{INTEGER_MODES} and @code{FLOAT_MODES}.