1 @c Copyright (C) 1988-2019 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 A @code{define_insn} expression is used to define instruction patterns
109 to which insns may be matched. A @code{define_insn} expression contains
110 an incomplete RTL expression, with pieces to be filled in later, operand
111 constraints that restrict how the pieces can be filled in, and an output
112 template or C code to generate the assembler output.
114 A @code{define_insn} is an RTL expression containing four or five operands:
118 An optional name @var{n}. When a name is present, the compiler
119 automically generates a C++ function @samp{gen_@var{n}} that takes
120 the operands of the instruction as arguments and returns the instruction's
121 rtx pattern. The compiler also assigns the instruction a unique code
122 @samp{CODE_FOR_@var{n}}, with all such codes belonging to an enum
123 called @code{insn_code}.
125 These names serve one of two purposes. The first is to indicate that the
126 instruction performs a certain standard job for the RTL-generation
127 pass of the compiler, such as a move, an addition, or a conditional
128 jump. The second is to help the target generate certain target-specific
129 operations, such as when implementing target-specific intrinsic functions.
131 It is better to prefix target-specific names with the name of the
132 target, to avoid any clash with current or future standard names.
134 The absence of a name is indicated by writing an empty string
135 where the name should go. Nameless instruction patterns are never
136 used for generating RTL code, but they may permit several simpler insns
137 to be combined later on.
139 For the purpose of debugging the compiler, you may also specify a
140 name beginning with the @samp{*} character. Such a name is used only
141 for identifying the instruction in RTL dumps; it is equivalent to having
142 a nameless pattern for all other purposes. Names beginning with the
143 @samp{*} character are not required to be unique.
145 The name may also have the form @samp{@@@var{n}}. This has the same
146 effect as a name @samp{@var{n}}, but in addition tells the compiler to
147 generate further helper functions; see @ref{Parameterized Names} for details.
150 The @dfn{RTL template}: This is a vector of incomplete RTL expressions
151 which describe the semantics of the instruction (@pxref{RTL Template}).
152 It is incomplete because it may contain @code{match_operand},
153 @code{match_operator}, and @code{match_dup} expressions that stand for
154 operands of the instruction.
156 If the vector has multiple elements, the RTL template is treated as a
157 @code{parallel} expression.
160 @cindex pattern conditions
161 @cindex conditions, in patterns
162 The condition: This is a string which contains a C expression. When the
163 compiler attempts to match RTL against a pattern, the condition is
164 evaluated. If the condition evaluates to @code{true}, the match is
165 permitted. The condition may be an empty string, which is treated
166 as always @code{true}.
168 @cindex named patterns and conditions
169 For a named pattern, the condition may not depend on the data in the
170 insn being matched, but only the target-machine-type flags. The compiler
171 needs to test these conditions during initialization in order to learn
172 exactly which named instructions are available in a particular run.
175 For nameless patterns, the condition is applied only when matching an
176 individual insn, and only after the insn has matched the pattern's
177 recognition template. The insn's operands may be found in the vector
180 An instruction condition cannot become more restrictive as compilation
181 progresses. If the condition accepts a particular RTL instruction at
182 one stage of compilation, it must continue to accept that instruction
183 until the final pass. For example, @samp{!reload_completed} and
184 @samp{can_create_pseudo_p ()} are both invalid instruction conditions,
185 because they are true during the earlier RTL passes and false during
186 the later ones. For the same reason, if a condition accepts an
187 instruction before register allocation, it cannot later try to control
188 register allocation by excluding certain register or value combinations.
190 Although a condition cannot become more restrictive as compilation
191 progresses, the condition for a nameless pattern @emph{can} become
192 more permissive. For example, a nameless instruction can require
193 @samp{reload_completed} to be true, in which case it only matches
194 after register allocation.
197 The @dfn{output template} or @dfn{output statement}: This is either
198 a string, or a fragment of C code which returns a string.
200 When simple substitution isn't general enough, you can specify a piece
201 of C code to compute the output. @xref{Output Statement}.
204 The @dfn{insn attributes}: This is an optional vector containing the values of
205 attributes for insns matching this pattern (@pxref{Insn Attributes}).
209 @section Example of @code{define_insn}
210 @cindex @code{define_insn} example
212 Here is an example of an instruction pattern, taken from the machine
213 description for the 68000/68020.
218 (match_operand:SI 0 "general_operand" "rm"))]
222 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
224 return \"cmpl #0,%0\";
229 This can also be written using braced strings:
234 (match_operand:SI 0 "general_operand" "rm"))]
237 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
243 This describes an instruction which sets the condition codes based on the
244 value of a general operand. It has no condition, so any insn with an RTL
245 description of the form shown may be matched to this pattern. The name
246 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL
247 generation pass that, when it is necessary to test such a value, an insn
248 to do so can be constructed using this pattern.
250 The output control string is a piece of C code which chooses which
251 output template to return based on the kind of operand and the specific
252 type of CPU for which code is being generated.
254 @samp{"rm"} is an operand constraint. Its meaning is explained below.
257 @section RTL Template
258 @cindex RTL insn template
259 @cindex generating insns
260 @cindex insns, generating
261 @cindex recognizing insns
262 @cindex insns, recognizing
264 The RTL template is used to define which insns match the particular pattern
265 and how to find their operands. For named patterns, the RTL template also
266 says how to construct an insn from specified operands.
268 Construction involves substituting specified operands into a copy of the
269 template. Matching involves determining the values that serve as the
270 operands in the insn being matched. Both of these activities are
271 controlled by special expression types that direct matching and
272 substitution of the operands.
275 @findex match_operand
276 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
277 This expression is a placeholder for operand number @var{n} of
278 the insn. When constructing an insn, operand number @var{n}
279 will be substituted at this point. When matching an insn, whatever
280 appears at this position in the insn will be taken as operand
281 number @var{n}; but it must satisfy @var{predicate} or this instruction
282 pattern will not match at all.
284 Operand numbers must be chosen consecutively counting from zero in
285 each instruction pattern. There may be only one @code{match_operand}
286 expression in the pattern for each operand number. Usually operands
287 are numbered in the order of appearance in @code{match_operand}
288 expressions. In the case of a @code{define_expand}, any operand numbers
289 used only in @code{match_dup} expressions have higher values than all
290 other operand numbers.
292 @var{predicate} is a string that is the name of a function that
293 accepts two arguments, an expression and a machine mode.
294 @xref{Predicates}. During matching, the function will be called with
295 the putative operand as the expression and @var{m} as the mode
296 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
297 which normally causes @var{predicate} to accept any mode). If it
298 returns zero, this instruction pattern fails to match.
299 @var{predicate} may be an empty string; then it means no test is to be
300 done on the operand, so anything which occurs in this position is
303 Most of the time, @var{predicate} will reject modes other than @var{m}---but
304 not always. For example, the predicate @code{address_operand} uses
305 @var{m} as the mode of memory ref that the address should be valid for.
306 Many predicates accept @code{const_int} nodes even though their mode is
309 @var{constraint} controls reloading and the choice of the best register
310 class to use for a value, as explained later (@pxref{Constraints}).
311 If the constraint would be an empty string, it can be omitted.
313 People are often unclear on the difference between the constraint and the
314 predicate. The predicate helps decide whether a given insn matches the
315 pattern. The constraint plays no role in this decision; instead, it
316 controls various decisions in the case of an insn which does match.
318 @findex match_scratch
319 @item (match_scratch:@var{m} @var{n} @var{constraint})
320 This expression is also a placeholder for operand number @var{n}
321 and indicates that operand must be a @code{scratch} or @code{reg}
324 When matching patterns, this is equivalent to
327 (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint})
330 but, when generating RTL, it produces a (@code{scratch}:@var{m})
333 If the last few expressions in a @code{parallel} are @code{clobber}
334 expressions whose operands are either a hard register or
335 @code{match_scratch}, the combiner can add or delete them when
336 necessary. @xref{Side Effects}.
339 @item (match_dup @var{n})
340 This expression is also a placeholder for operand number @var{n}.
341 It is used when the operand needs to appear more than once in the
344 In construction, @code{match_dup} acts just like @code{match_operand}:
345 the operand is substituted into the insn being constructed. But in
346 matching, @code{match_dup} behaves differently. It assumes that operand
347 number @var{n} has already been determined by a @code{match_operand}
348 appearing earlier in the recognition template, and it matches only an
349 identical-looking expression.
351 Note that @code{match_dup} should not be used to tell the compiler that
352 a particular register is being used for two operands (example:
353 @code{add} that adds one register to another; the second register is
354 both an input operand and the output operand). Use a matching
355 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
356 operand is used in two places in the template, such as an instruction
357 that computes both a quotient and a remainder, where the opcode takes
358 two input operands but the RTL template has to refer to each of those
359 twice; once for the quotient pattern and once for the remainder pattern.
361 @findex match_operator
362 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
363 This pattern is a kind of placeholder for a variable RTL expression
366 When constructing an insn, it stands for an RTL expression whose
367 expression code is taken from that of operand @var{n}, and whose
368 operands are constructed from the patterns @var{operands}.
370 When matching an expression, it matches an expression if the function
371 @var{predicate} returns nonzero on that expression @emph{and} the
372 patterns @var{operands} match the operands of the expression.
374 Suppose that the function @code{commutative_operator} is defined as
375 follows, to match any expression whose operator is one of the
376 commutative arithmetic operators of RTL and whose mode is @var{mode}:
380 commutative_integer_operator (x, mode)
384 enum rtx_code code = GET_CODE (x);
385 if (GET_MODE (x) != mode)
387 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
388 || code == EQ || code == NE);
392 Then the following pattern will match any RTL expression consisting
393 of a commutative operator applied to two general operands:
396 (match_operator:SI 3 "commutative_operator"
397 [(match_operand:SI 1 "general_operand" "g")
398 (match_operand:SI 2 "general_operand" "g")])
401 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
402 because the expressions to be matched all contain two operands.
404 When this pattern does match, the two operands of the commutative
405 operator are recorded as operands 1 and 2 of the insn. (This is done
406 by the two instances of @code{match_operand}.) Operand 3 of the insn
407 will be the entire commutative expression: use @code{GET_CODE
408 (operands[3])} to see which commutative operator was used.
410 The machine mode @var{m} of @code{match_operator} works like that of
411 @code{match_operand}: it is passed as the second argument to the
412 predicate function, and that function is solely responsible for
413 deciding whether the expression to be matched ``has'' that mode.
415 When constructing an insn, argument 3 of the gen-function will specify
416 the operation (i.e.@: the expression code) for the expression to be
417 made. It should be an RTL expression, whose expression code is copied
418 into a new expression whose operands are arguments 1 and 2 of the
419 gen-function. The subexpressions of argument 3 are not used;
420 only its expression code matters.
422 When @code{match_operator} is used in a pattern for matching an insn,
423 it usually best if the operand number of the @code{match_operator}
424 is higher than that of the actual operands of the insn. This improves
425 register allocation because the register allocator often looks at
426 operands 1 and 2 of insns to see if it can do register tying.
428 There is no way to specify constraints in @code{match_operator}. The
429 operand of the insn which corresponds to the @code{match_operator}
430 never has any constraints because it is never reloaded as a whole.
431 However, if parts of its @var{operands} are matched by
432 @code{match_operand} patterns, those parts may have constraints of
436 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
437 Like @code{match_dup}, except that it applies to operators instead of
438 operands. When constructing an insn, operand number @var{n} will be
439 substituted at this point. But in matching, @code{match_op_dup} behaves
440 differently. It assumes that operand number @var{n} has already been
441 determined by a @code{match_operator} appearing earlier in the
442 recognition template, and it matches only an identical-looking
445 @findex match_parallel
446 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
447 This pattern is a placeholder for an insn that consists of a
448 @code{parallel} expression with a variable number of elements. This
449 expression should only appear at the top level of an insn pattern.
451 When constructing an insn, operand number @var{n} will be substituted at
452 this point. When matching an insn, it matches if the body of the insn
453 is a @code{parallel} expression with at least as many elements as the
454 vector of @var{subpat} expressions in the @code{match_parallel}, if each
455 @var{subpat} matches the corresponding element of the @code{parallel},
456 @emph{and} the function @var{predicate} returns nonzero on the
457 @code{parallel} that is the body of the insn. It is the responsibility
458 of the predicate to validate elements of the @code{parallel} beyond
459 those listed in the @code{match_parallel}.
461 A typical use of @code{match_parallel} is to match load and store
462 multiple expressions, which can contain a variable number of elements
463 in a @code{parallel}. For example,
467 [(match_parallel 0 "load_multiple_operation"
468 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
469 (match_operand:SI 2 "memory_operand" "m"))
471 (clobber (reg:SI 179))])]
476 This example comes from @file{a29k.md}. The function
477 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
478 that subsequent elements in the @code{parallel} are the same as the
479 @code{set} in the pattern, except that they are referencing subsequent
480 registers and memory locations.
482 An insn that matches this pattern might look like:
486 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
488 (clobber (reg:SI 179))
490 (mem:SI (plus:SI (reg:SI 100)
493 (mem:SI (plus:SI (reg:SI 100)
497 @findex match_par_dup
498 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
499 Like @code{match_op_dup}, but for @code{match_parallel} instead of
500 @code{match_operator}.
504 @node Output Template
505 @section Output Templates and Operand Substitution
506 @cindex output templates
507 @cindex operand substitution
509 @cindex @samp{%} in template
511 The @dfn{output template} is a string which specifies how to output the
512 assembler code for an instruction pattern. Most of the template is a
513 fixed string which is output literally. The character @samp{%} is used
514 to specify where to substitute an operand; it can also be used to
515 identify places where different variants of the assembler require
518 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
519 operand @var{n} at that point in the string.
521 @samp{%} followed by a letter and a digit says to output an operand in an
522 alternate fashion. Four letters have standard, built-in meanings described
523 below. The machine description macro @code{PRINT_OPERAND} can define
524 additional letters with nonstandard meanings.
526 @samp{%c@var{digit}} can be used to substitute an operand that is a
527 constant value without the syntax that normally indicates an immediate
530 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
531 the constant is negated before printing.
533 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
534 memory reference, with the actual operand treated as the address. This may
535 be useful when outputting a ``load address'' instruction, because often the
536 assembler syntax for such an instruction requires you to write the operand
537 as if it were a memory reference.
539 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
542 @samp{%=} outputs a number which is unique to each instruction in the
543 entire compilation. This is useful for making local labels to be
544 referred to more than once in a single template that generates multiple
545 assembler instructions.
547 @samp{%} followed by a punctuation character specifies a substitution that
548 does not use an operand. Only one case is standard: @samp{%%} outputs a
549 @samp{%} into the assembler code. Other nonstandard cases can be
550 defined in the @code{PRINT_OPERAND} macro. You must also define
551 which punctuation characters are valid with the
552 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
556 The template may generate multiple assembler instructions. Write the text
557 for the instructions, with @samp{\;} between them.
559 @cindex matching operands
560 When the RTL contains two operands which are required by constraint to match
561 each other, the output template must refer only to the lower-numbered operand.
562 Matching operands are not always identical, and the rest of the compiler
563 arranges to put the proper RTL expression for printing into the lower-numbered
566 One use of nonstandard letters or punctuation following @samp{%} is to
567 distinguish between different assembler languages for the same machine; for
568 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
569 requires periods in most opcode names, while MIT syntax does not. For
570 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
571 syntax. The same file of patterns is used for both kinds of output syntax,
572 but the character sequence @samp{%.} is used in each place where Motorola
573 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
574 defines the sequence to output a period; the macro for MIT syntax defines
577 @cindex @code{#} in template
578 As a special case, a template consisting of the single character @code{#}
579 instructs the compiler to first split the insn, and then output the
580 resulting instructions separately. This helps eliminate redundancy in the
581 output templates. If you have a @code{define_insn} that needs to emit
582 multiple assembler instructions, and there is a matching @code{define_split}
583 already defined, then you can simply use @code{#} as the output template
584 instead of writing an output template that emits the multiple assembler
587 Note that @code{#} only has an effect while generating assembly code;
588 it does not affect whether a split occurs earlier. An associated
589 @code{define_split} must exist and it must be suitable for use after
592 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
593 of the form @samp{@{option0|option1|option2@}} in the templates. These
594 describe multiple variants of assembler language syntax.
595 @xref{Instruction Output}.
597 @node Output Statement
598 @section C Statements for Assembler Output
599 @cindex output statements
600 @cindex C statements for assembler output
601 @cindex generating assembler output
603 Often a single fixed template string cannot produce correct and efficient
604 assembler code for all the cases that are recognized by a single
605 instruction pattern. For example, the opcodes may depend on the kinds of
606 operands; or some unfortunate combinations of operands may require extra
607 machine instructions.
609 If the output control string starts with a @samp{@@}, then it is actually
610 a series of templates, each on a separate line. (Blank lines and
611 leading spaces and tabs are ignored.) The templates correspond to the
612 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
613 if a target machine has a two-address add instruction @samp{addr} to add
614 into a register and another @samp{addm} to add a register to memory, you
615 might write this pattern:
618 (define_insn "addsi3"
619 [(set (match_operand:SI 0 "general_operand" "=r,m")
620 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
621 (match_operand:SI 2 "general_operand" "g,r")))]
628 @cindex @code{*} in template
629 @cindex asterisk in template
630 If the output control string starts with a @samp{*}, then it is not an
631 output template but rather a piece of C program that should compute a
632 template. It should execute a @code{return} statement to return the
633 template-string you want. Most such templates use C string literals, which
634 require doublequote characters to delimit them. To include these
635 doublequote characters in the string, prefix each one with @samp{\}.
637 If the output control string is written as a brace block instead of a
638 double-quoted string, it is automatically assumed to be C code. In that
639 case, it is not necessary to put in a leading asterisk, or to escape the
640 doublequotes surrounding C string literals.
642 The operands may be found in the array @code{operands}, whose C data type
645 It is very common to select different ways of generating assembler code
646 based on whether an immediate operand is within a certain range. Be
647 careful when doing this, because the result of @code{INTVAL} is an
648 integer on the host machine. If the host machine has more bits in an
649 @code{int} than the target machine has in the mode in which the constant
650 will be used, then some of the bits you get from @code{INTVAL} will be
651 superfluous. For proper results, you must carefully disregard the
652 values of those bits.
654 @findex output_asm_insn
655 It is possible to output an assembler instruction and then go on to output
656 or compute more of them, using the subroutine @code{output_asm_insn}. This
657 receives two arguments: a template-string and a vector of operands. The
658 vector may be @code{operands}, or it may be another array of @code{rtx}
659 that you declare locally and initialize yourself.
661 @findex which_alternative
662 When an insn pattern has multiple alternatives in its constraints, often
663 the appearance of the assembler code is determined mostly by which alternative
664 was matched. When this is so, the C code can test the variable
665 @code{which_alternative}, which is the ordinal number of the alternative
666 that was actually satisfied (0 for the first, 1 for the second alternative,
669 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
670 for registers and @samp{clrmem} for memory locations. Here is how
671 a pattern could use @code{which_alternative} to choose between them:
675 [(set (match_operand:SI 0 "general_operand" "=r,m")
679 return (which_alternative == 0
680 ? "clrreg %0" : "clrmem %0");
684 The example above, where the assembler code to generate was
685 @emph{solely} determined by the alternative, could also have been specified
686 as follows, having the output control string start with a @samp{@@}:
691 [(set (match_operand:SI 0 "general_operand" "=r,m")
700 If you just need a little bit of C code in one (or a few) alternatives,
701 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
706 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
711 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
719 @cindex operand predicates
720 @cindex operator predicates
722 A predicate determines whether a @code{match_operand} or
723 @code{match_operator} expression matches, and therefore whether the
724 surrounding instruction pattern will be used for that combination of
725 operands. GCC has a number of machine-independent predicates, and you
726 can define machine-specific predicates as needed. By convention,
727 predicates used with @code{match_operand} have names that end in
728 @samp{_operand}, and those used with @code{match_operator} have names
729 that end in @samp{_operator}.
731 All predicates are boolean functions (in the mathematical sense) of
732 two arguments: the RTL expression that is being considered at that
733 position in the instruction pattern, and the machine mode that the
734 @code{match_operand} or @code{match_operator} specifies. In this
735 section, the first argument is called @var{op} and the second argument
736 @var{mode}. Predicates can be called from C as ordinary two-argument
737 functions; this can be useful in output templates or other
738 machine-specific code.
740 Operand predicates can allow operands that are not actually acceptable
741 to the hardware, as long as the constraints give reload the ability to
742 fix them up (@pxref{Constraints}). However, GCC will usually generate
743 better code if the predicates specify the requirements of the machine
744 instructions as closely as possible. Reload cannot fix up operands
745 that must be constants (``immediate operands''); you must use a
746 predicate that allows only constants, or else enforce the requirement
747 in the extra condition.
749 @cindex predicates and machine modes
750 @cindex normal predicates
751 @cindex special predicates
752 Most predicates handle their @var{mode} argument in a uniform manner.
753 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
754 any mode. If @var{mode} is anything else, then @var{op} must have the
755 same mode, unless @var{op} is a @code{CONST_INT} or integer
756 @code{CONST_DOUBLE}. These RTL expressions always have
757 @code{VOIDmode}, so it would be counterproductive to check that their
758 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
759 integer @code{CONST_DOUBLE} check that the value stored in the
760 constant will fit in the requested mode.
762 Predicates with this behavior are called @dfn{normal}.
763 @command{genrecog} can optimize the instruction recognizer based on
764 knowledge of how normal predicates treat modes. It can also diagnose
765 certain kinds of common errors in the use of normal predicates; for
766 instance, it is almost always an error to use a normal predicate
767 without specifying a mode.
769 Predicates that do something different with their @var{mode} argument
770 are called @dfn{special}. The generic predicates
771 @code{address_operand} and @code{pmode_register_operand} are special
772 predicates. @command{genrecog} does not do any optimizations or
773 diagnosis when special predicates are used.
776 * Machine-Independent Predicates:: Predicates available to all back ends.
777 * Defining Predicates:: How to write machine-specific predicate
781 @node Machine-Independent Predicates
782 @subsection Machine-Independent Predicates
783 @cindex machine-independent predicates
784 @cindex generic predicates
786 These are the generic predicates available to all back ends. They are
787 defined in @file{recog.c}. The first category of predicates allow
788 only constant, or @dfn{immediate}, operands.
790 @defun immediate_operand
791 This predicate allows any sort of constant that fits in @var{mode}.
792 It is an appropriate choice for instructions that take operands that
796 @defun const_int_operand
797 This predicate allows any @code{CONST_INT} expression that fits in
798 @var{mode}. It is an appropriate choice for an immediate operand that
799 does not allow a symbol or label.
802 @defun const_double_operand
803 This predicate accepts any @code{CONST_DOUBLE} expression that has
804 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
805 accept @code{CONST_INT}. It is intended for immediate floating point
810 The second category of predicates allow only some kind of machine
813 @defun register_operand
814 This predicate allows any @code{REG} or @code{SUBREG} expression that
815 is valid for @var{mode}. It is often suitable for arithmetic
816 instruction operands on a RISC machine.
819 @defun pmode_register_operand
820 This is a slight variant on @code{register_operand} which works around
821 a limitation in the machine-description reader.
824 (match_operand @var{n} "pmode_register_operand" @var{constraint})
831 (match_operand:P @var{n} "register_operand" @var{constraint})
835 would mean, if the machine-description reader accepted @samp{:P}
836 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
837 alias for some other mode, and might vary with machine-specific
838 options. @xref{Misc}.
841 @defun scratch_operand
842 This predicate allows hard registers and @code{SCRATCH} expressions,
843 but not pseudo-registers. It is used internally by @code{match_scratch};
844 it should not be used directly.
848 The third category of predicates allow only some kind of memory reference.
850 @defun memory_operand
851 This predicate allows any valid reference to a quantity of mode
852 @var{mode} in memory, as determined by the weak form of
853 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
856 @defun address_operand
857 This predicate is a little unusual; it allows any operand that is a
858 valid expression for the @emph{address} of a quantity of mode
859 @var{mode}, again determined by the weak form of
860 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
861 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
862 @code{memory_operand}, then @var{exp} is acceptable to
863 @code{address_operand}. Note that @var{exp} does not necessarily have
867 @defun indirect_operand
868 This is a stricter form of @code{memory_operand} which allows only
869 memory references with a @code{general_operand} as the address
870 expression. New uses of this predicate are discouraged, because
871 @code{general_operand} is very permissive, so it's hard to tell what
872 an @code{indirect_operand} does or does not allow. If a target has
873 different requirements for memory operands for different instructions,
874 it is better to define target-specific predicates which enforce the
875 hardware's requirements explicitly.
879 This predicate allows a memory reference suitable for pushing a value
880 onto the stack. This will be a @code{MEM} which refers to
881 @code{stack_pointer_rtx}, with a side effect in its address expression
882 (@pxref{Incdec}); which one is determined by the
883 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
887 This predicate allows a memory reference suitable for popping a value
888 off the stack. Again, this will be a @code{MEM} referring to
889 @code{stack_pointer_rtx}, with a side effect in its address
890 expression. However, this time @code{STACK_POP_CODE} is expected.
894 The fourth category of predicates allow some combination of the above
897 @defun nonmemory_operand
898 This predicate allows any immediate or register operand valid for @var{mode}.
901 @defun nonimmediate_operand
902 This predicate allows any register or memory operand valid for @var{mode}.
905 @defun general_operand
906 This predicate allows any immediate, register, or memory operand
907 valid for @var{mode}.
911 Finally, there are two generic operator predicates.
913 @defun comparison_operator
914 This predicate matches any expression which performs an arithmetic
915 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
919 @defun ordered_comparison_operator
920 This predicate matches any expression which performs an arithmetic
921 comparison in @var{mode} and whose expression code is valid for integer
922 modes; that is, the expression code will be one of @code{eq}, @code{ne},
923 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
924 @code{ge}, @code{geu}.
927 @node Defining Predicates
928 @subsection Defining Machine-Specific Predicates
929 @cindex defining predicates
930 @findex define_predicate
931 @findex define_special_predicate
933 Many machines have requirements for their operands that cannot be
934 expressed precisely using the generic predicates. You can define
935 additional predicates using @code{define_predicate} and
936 @code{define_special_predicate} expressions. These expressions have
941 The name of the predicate, as it will be referred to in
942 @code{match_operand} or @code{match_operator} expressions.
945 An RTL expression which evaluates to true if the predicate allows the
946 operand @var{op}, false if it does not. This expression can only use
947 the following RTL codes:
951 When written inside a predicate expression, a @code{MATCH_OPERAND}
952 expression evaluates to true if the predicate it names would allow
953 @var{op}. The operand number and constraint are ignored. Due to
954 limitations in @command{genrecog}, you can only refer to generic
955 predicates and predicates that have already been defined.
958 This expression evaluates to true if @var{op} or a specified
959 subexpression of @var{op} has one of a given list of RTX codes.
961 The first operand of this expression is a string constant containing a
962 comma-separated list of RTX code names (in lower case). These are the
963 codes for which the @code{MATCH_CODE} will be true.
965 The second operand is a string constant which indicates what
966 subexpression of @var{op} to examine. If it is absent or the empty
967 string, @var{op} itself is examined. Otherwise, the string constant
968 must be a sequence of digits and/or lowercase letters. Each character
969 indicates a subexpression to extract from the current expression; for
970 the first character this is @var{op}, for the second and subsequent
971 characters it is the result of the previous character. A digit
972 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
973 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
974 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
975 @code{MATCH_CODE} then examines the RTX code of the subexpression
976 extracted by the complete string. It is not possible to extract
977 components of an @code{rtvec} that is not at position 0 within its RTX
981 This expression has one operand, a string constant containing a C
982 expression. The predicate's arguments, @var{op} and @var{mode}, are
983 available with those names in the C expression. The @code{MATCH_TEST}
984 evaluates to true if the C expression evaluates to a nonzero value.
985 @code{MATCH_TEST} expressions must not have side effects.
991 The basic @samp{MATCH_} expressions can be combined using these
992 logical operators, which have the semantics of the C operators
993 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
994 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
995 arbitrary number of arguments; this has exactly the same effect as
996 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
1000 An optional block of C code, which should execute
1001 @samp{@w{return true}} if the predicate is found to match and
1002 @samp{@w{return false}} if it does not. It must not have any side
1003 effects. The predicate arguments, @var{op} and @var{mode}, are
1004 available with those names.
1006 If a code block is present in a predicate definition, then the RTL
1007 expression must evaluate to true @emph{and} the code block must
1008 execute @samp{@w{return true}} for the predicate to allow the operand.
1009 The RTL expression is evaluated first; do not re-check anything in the
1010 code block that was checked in the RTL expression.
1013 The program @command{genrecog} scans @code{define_predicate} and
1014 @code{define_special_predicate} expressions to determine which RTX
1015 codes are possibly allowed. You should always make this explicit in
1016 the RTL predicate expression, using @code{MATCH_OPERAND} and
1019 Here is an example of a simple predicate definition, from the IA64
1020 machine description:
1024 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
1025 (define_predicate "small_addr_symbolic_operand"
1026 (and (match_code "symbol_ref")
1027 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1032 And here is another, showing the use of the C block.
1036 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1037 (define_predicate "gr_register_operand"
1038 (match_operand 0 "register_operand")
1041 if (GET_CODE (op) == SUBREG)
1042 op = SUBREG_REG (op);
1045 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1050 Predicates written with @code{define_predicate} automatically include
1051 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1052 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1053 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1054 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1055 kind of constant fits in the requested mode. This is because
1056 target-specific predicates that take constants usually have to do more
1057 stringent value checks anyway. If you need the exact same treatment
1058 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1059 provide, use a @code{MATCH_OPERAND} subexpression to call
1060 @code{const_int_operand}, @code{const_double_operand}, or
1061 @code{immediate_operand}.
1063 Predicates written with @code{define_special_predicate} do not get any
1064 automatic mode checks, and are treated as having special mode handling
1065 by @command{genrecog}.
1067 The program @command{genpreds} is responsible for generating code to
1068 test predicates. It also writes a header file containing function
1069 declarations for all machine-specific predicates. It is not necessary
1070 to declare these predicates in @file{@var{cpu}-protos.h}.
1073 @c Most of this node appears by itself (in a different place) even
1074 @c when the INTERNALS flag is clear. Passages that require the internals
1075 @c manual's context are conditionalized to appear only in the internals manual.
1078 @section Operand Constraints
1079 @cindex operand constraints
1082 Each @code{match_operand} in an instruction pattern can specify
1083 constraints for the operands allowed. The constraints allow you to
1084 fine-tune matching within the set of operands allowed by the
1090 @section Constraints for @code{asm} Operands
1091 @cindex operand constraints, @code{asm}
1092 @cindex constraints, @code{asm}
1093 @cindex @code{asm} constraints
1095 Here are specific details on what constraint letters you can use with
1096 @code{asm} operands.
1098 Constraints can say whether
1099 an operand may be in a register, and which kinds of register; whether the
1100 operand can be a memory reference, and which kinds of address; whether the
1101 operand may be an immediate constant, and which possible values it may
1102 have. Constraints can also require two operands to match.
1103 Side-effects aren't allowed in operands of inline @code{asm}, unless
1104 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1105 that the side effects will happen exactly once in an instruction that can update
1106 the addressing register.
1110 * Simple Constraints:: Basic use of constraints.
1111 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1112 * Class Preferences:: Constraints guide which hard register to put things in.
1113 * Modifiers:: More precise control over effects of constraints.
1114 * Machine Constraints:: Existing constraints for some particular machines.
1115 * Disable Insn Alternatives:: Disable insn alternatives using attributes.
1116 * Define Constraints:: How to define machine-specific constraints.
1117 * C Constraint Interface:: How to test constraints from C code.
1123 * Simple Constraints:: Basic use of constraints.
1124 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1125 * Modifiers:: More precise control over effects of constraints.
1126 * Machine Constraints:: Special constraints for some particular machines.
1130 @node Simple Constraints
1131 @subsection Simple Constraints
1132 @cindex simple constraints
1134 The simplest kind of constraint is a string full of letters, each of
1135 which describes one kind of operand that is permitted. Here are
1136 the letters that are allowed:
1140 Whitespace characters are ignored and can be inserted at any position
1141 except the first. This enables each alternative for different operands to
1142 be visually aligned in the machine description even if they have different
1143 number of constraints and modifiers.
1145 @cindex @samp{m} in constraint
1146 @cindex memory references in constraints
1148 A memory operand is allowed, with any kind of address that the machine
1149 supports in general.
1150 Note that the letter used for the general memory constraint can be
1151 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1153 @cindex offsettable address
1154 @cindex @samp{o} in constraint
1156 A memory operand is allowed, but only if the address is
1157 @dfn{offsettable}. This means that adding a small integer (actually,
1158 the width in bytes of the operand, as determined by its machine mode)
1159 may be added to the address and the result is also a valid memory
1162 @cindex autoincrement/decrement addressing
1163 For example, an address which is constant is offsettable; so is an
1164 address that is the sum of a register and a constant (as long as a
1165 slightly larger constant is also within the range of address-offsets
1166 supported by the machine); but an autoincrement or autodecrement
1167 address is not offsettable. More complicated indirect/indexed
1168 addresses may or may not be offsettable depending on the other
1169 addressing modes that the machine supports.
1171 Note that in an output operand which can be matched by another
1172 operand, the constraint letter @samp{o} is valid only when accompanied
1173 by both @samp{<} (if the target machine has predecrement addressing)
1174 and @samp{>} (if the target machine has preincrement addressing).
1176 @cindex @samp{V} in constraint
1178 A memory operand that is not offsettable. In other words, anything that
1179 would fit the @samp{m} constraint but not the @samp{o} constraint.
1181 @cindex @samp{<} in constraint
1183 A memory operand with autodecrement addressing (either predecrement or
1184 postdecrement) is allowed. In inline @code{asm} this constraint is only
1185 allowed if the operand is used exactly once in an instruction that can
1186 handle the side effects. Not using an operand with @samp{<} in constraint
1187 string in the inline @code{asm} pattern at all or using it in multiple
1188 instructions isn't valid, because the side effects wouldn't be performed
1189 or would be performed more than once. Furthermore, on some targets
1190 the operand with @samp{<} in constraint string must be accompanied by
1191 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1192 or @code{%P0} on IA-64.
1194 @cindex @samp{>} in constraint
1196 A memory operand with autoincrement addressing (either preincrement or
1197 postincrement) is allowed. In inline @code{asm} the same restrictions
1198 as for @samp{<} apply.
1200 @cindex @samp{r} in constraint
1201 @cindex registers in constraints
1203 A register operand is allowed provided that it is in a general
1206 @cindex constants in constraints
1207 @cindex @samp{i} in constraint
1209 An immediate integer operand (one with constant value) is allowed.
1210 This includes symbolic constants whose values will be known only at
1211 assembly time or later.
1213 @cindex @samp{n} in constraint
1215 An immediate integer operand with a known numeric value is allowed.
1216 Many systems cannot support assembly-time constants for operands less
1217 than a word wide. Constraints for these operands should use @samp{n}
1218 rather than @samp{i}.
1220 @cindex @samp{I} in constraint
1221 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1222 Other letters in the range @samp{I} through @samp{P} may be defined in
1223 a machine-dependent fashion to permit immediate integer operands with
1224 explicit integer values in specified ranges. For example, on the
1225 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1226 This is the range permitted as a shift count in the shift
1229 @cindex @samp{E} in constraint
1231 An immediate floating operand (expression code @code{const_double}) is
1232 allowed, but only if the target floating point format is the same as
1233 that of the host machine (on which the compiler is running).
1235 @cindex @samp{F} in constraint
1237 An immediate floating operand (expression code @code{const_double} or
1238 @code{const_vector}) is allowed.
1240 @cindex @samp{G} in constraint
1241 @cindex @samp{H} in constraint
1242 @item @samp{G}, @samp{H}
1243 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1244 permit immediate floating operands in particular ranges of values.
1246 @cindex @samp{s} in constraint
1248 An immediate integer operand whose value is not an explicit integer is
1251 This might appear strange; if an insn allows a constant operand with a
1252 value not known at compile time, it certainly must allow any known
1253 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1254 better code to be generated.
1256 For example, on the 68000 in a fullword instruction it is possible to
1257 use an immediate operand; but if the immediate value is between @minus{}128
1258 and 127, better code results from loading the value into a register and
1259 using the register. This is because the load into the register can be
1260 done with a @samp{moveq} instruction. We arrange for this to happen
1261 by defining the letter @samp{K} to mean ``any integer outside the
1262 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1265 @cindex @samp{g} in constraint
1267 Any register, memory or immediate integer operand is allowed, except for
1268 registers that are not general registers.
1270 @cindex @samp{X} in constraint
1273 Any operand whatsoever is allowed, even if it does not satisfy
1274 @code{general_operand}. This is normally used in the constraint of
1275 a @code{match_scratch} when certain alternatives will not actually
1276 require a scratch register.
1279 Any operand whatsoever is allowed.
1282 @cindex @samp{0} in constraint
1283 @cindex digits in constraint
1284 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1285 An operand that matches the specified operand number is allowed. If a
1286 digit is used together with letters within the same alternative, the
1287 digit should come last.
1289 This number is allowed to be more than a single digit. If multiple
1290 digits are encountered consecutively, they are interpreted as a single
1291 decimal integer. There is scant chance for ambiguity, since to-date
1292 it has never been desirable that @samp{10} be interpreted as matching
1293 either operand 1 @emph{or} operand 0. Should this be desired, one
1294 can use multiple alternatives instead.
1296 @cindex matching constraint
1297 @cindex constraint, matching
1298 This is called a @dfn{matching constraint} and what it really means is
1299 that the assembler has only a single operand that fills two roles
1301 considered separate in the RTL insn. For example, an add insn has two
1302 input operands and one output operand in the RTL, but on most CISC
1305 which @code{asm} distinguishes. For example, an add instruction uses
1306 two input operands and an output operand, but on most CISC
1308 machines an add instruction really has only two operands, one of them an
1309 input-output operand:
1315 Matching constraints are used in these circumstances.
1316 More precisely, the two operands that match must include one input-only
1317 operand and one output-only operand. Moreover, the digit must be a
1318 smaller number than the number of the operand that uses it in the
1322 For operands to match in a particular case usually means that they
1323 are identical-looking RTL expressions. But in a few special cases
1324 specific kinds of dissimilarity are allowed. For example, @code{*x}
1325 as an input operand will match @code{*x++} as an output operand.
1326 For proper results in such cases, the output template should always
1327 use the output-operand's number when printing the operand.
1330 @cindex load address instruction
1331 @cindex push address instruction
1332 @cindex address constraints
1333 @cindex @samp{p} in constraint
1335 An operand that is a valid memory address is allowed. This is
1336 for ``load address'' and ``push address'' instructions.
1338 @findex address_operand
1339 @samp{p} in the constraint must be accompanied by @code{address_operand}
1340 as the predicate in the @code{match_operand}. This predicate interprets
1341 the mode specified in the @code{match_operand} as the mode of the memory
1342 reference for which the address would be valid.
1344 @cindex other register constraints
1345 @cindex extensible constraints
1346 @item @var{other-letters}
1347 Other letters can be defined in machine-dependent fashion to stand for
1348 particular classes of registers or other arbitrary operand types.
1349 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1350 for data, address and floating point registers.
1354 In order to have valid assembler code, each operand must satisfy
1355 its constraint. But a failure to do so does not prevent the pattern
1356 from applying to an insn. Instead, it directs the compiler to modify
1357 the code so that the constraint will be satisfied. Usually this is
1358 done by copying an operand into a register.
1360 Contrast, therefore, the two instruction patterns that follow:
1364 [(set (match_operand:SI 0 "general_operand" "=r")
1365 (plus:SI (match_dup 0)
1366 (match_operand:SI 1 "general_operand" "r")))]
1372 which has two operands, one of which must appear in two places, and
1376 [(set (match_operand:SI 0 "general_operand" "=r")
1377 (plus:SI (match_operand:SI 1 "general_operand" "0")
1378 (match_operand:SI 2 "general_operand" "r")))]
1384 which has three operands, two of which are required by a constraint to be
1385 identical. If we are considering an insn of the form
1388 (insn @var{n} @var{prev} @var{next}
1390 (plus:SI (reg:SI 6) (reg:SI 109)))
1395 the first pattern would not apply at all, because this insn does not
1396 contain two identical subexpressions in the right place. The pattern would
1397 say, ``That does not look like an add instruction; try other patterns''.
1398 The second pattern would say, ``Yes, that's an add instruction, but there
1399 is something wrong with it''. It would direct the reload pass of the
1400 compiler to generate additional insns to make the constraint true. The
1401 results might look like this:
1404 (insn @var{n2} @var{prev} @var{n}
1405 (set (reg:SI 3) (reg:SI 6))
1408 (insn @var{n} @var{n2} @var{next}
1410 (plus:SI (reg:SI 3) (reg:SI 109)))
1414 It is up to you to make sure that each operand, in each pattern, has
1415 constraints that can handle any RTL expression that could be present for
1416 that operand. (When multiple alternatives are in use, each pattern must,
1417 for each possible combination of operand expressions, have at least one
1418 alternative which can handle that combination of operands.) The
1419 constraints don't need to @emph{allow} any possible operand---when this is
1420 the case, they do not constrain---but they must at least point the way to
1421 reloading any possible operand so that it will fit.
1425 If the constraint accepts whatever operands the predicate permits,
1426 there is no problem: reloading is never necessary for this operand.
1428 For example, an operand whose constraints permit everything except
1429 registers is safe provided its predicate rejects registers.
1431 An operand whose predicate accepts only constant values is safe
1432 provided its constraints include the letter @samp{i}. If any possible
1433 constant value is accepted, then nothing less than @samp{i} will do;
1434 if the predicate is more selective, then the constraints may also be
1438 Any operand expression can be reloaded by copying it into a register.
1439 So if an operand's constraints allow some kind of register, it is
1440 certain to be safe. It need not permit all classes of registers; the
1441 compiler knows how to copy a register into another register of the
1442 proper class in order to make an instruction valid.
1444 @cindex nonoffsettable memory reference
1445 @cindex memory reference, nonoffsettable
1447 A nonoffsettable memory reference can be reloaded by copying the
1448 address into a register. So if the constraint uses the letter
1449 @samp{o}, all memory references are taken care of.
1452 A constant operand can be reloaded by allocating space in memory to
1453 hold it as preinitialized data. Then the memory reference can be used
1454 in place of the constant. So if the constraint uses the letters
1455 @samp{o} or @samp{m}, constant operands are not a problem.
1458 If the constraint permits a constant and a pseudo register used in an insn
1459 was not allocated to a hard register and is equivalent to a constant,
1460 the register will be replaced with the constant. If the predicate does
1461 not permit a constant and the insn is re-recognized for some reason, the
1462 compiler will crash. Thus the predicate must always recognize any
1463 objects allowed by the constraint.
1466 If the operand's predicate can recognize registers, but the constraint does
1467 not permit them, it can make the compiler crash. When this operand happens
1468 to be a register, the reload pass will be stymied, because it does not know
1469 how to copy a register temporarily into memory.
1471 If the predicate accepts a unary operator, the constraint applies to the
1472 operand. For example, the MIPS processor at ISA level 3 supports an
1473 instruction which adds two registers in @code{SImode} to produce a
1474 @code{DImode} result, but only if the registers are correctly sign
1475 extended. This predicate for the input operands accepts a
1476 @code{sign_extend} of an @code{SImode} register. Write the constraint
1477 to indicate the type of register that is required for the operand of the
1481 @node Multi-Alternative
1482 @subsection Multiple Alternative Constraints
1483 @cindex multiple alternative constraints
1485 Sometimes a single instruction has multiple alternative sets of possible
1486 operands. For example, on the 68000, a logical-or instruction can combine
1487 register or an immediate value into memory, or it can combine any kind of
1488 operand into a register; but it cannot combine one memory location into
1491 These constraints are represented as multiple alternatives. An alternative
1492 can be described by a series of letters for each operand. The overall
1493 constraint for an operand is made from the letters for this operand
1494 from the first alternative, a comma, the letters for this operand from
1495 the second alternative, a comma, and so on until the last alternative.
1496 All operands for a single instruction must have the same number of
1499 Here is how it is done for fullword logical-or on the 68000:
1502 (define_insn "iorsi3"
1503 [(set (match_operand:SI 0 "general_operand" "=m,d")
1504 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1505 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1509 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1510 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1511 2. The second alternative has @samp{d} (data register) for operand 0,
1512 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1513 @samp{%} in the constraints apply to all the alternatives; their
1514 meaning is explained in the next section (@pxref{Class Preferences}).
1516 If all the operands fit any one alternative, the instruction is valid.
1517 Otherwise, for each alternative, the compiler counts how many instructions
1518 must be added to copy the operands so that that alternative applies.
1519 The alternative requiring the least copying is chosen. If two alternatives
1520 need the same amount of copying, the one that comes first is chosen.
1521 These choices can be altered with the @samp{?} and @samp{!} characters:
1524 @cindex @samp{?} in constraint
1525 @cindex question mark
1527 Disparage slightly the alternative that the @samp{?} appears in,
1528 as a choice when no alternative applies exactly. The compiler regards
1529 this alternative as one unit more costly for each @samp{?} that appears
1532 @cindex @samp{!} in constraint
1533 @cindex exclamation point
1535 Disparage severely the alternative that the @samp{!} appears in.
1536 This alternative can still be used if it fits without reloading,
1537 but if reloading is needed, some other alternative will be used.
1539 @cindex @samp{^} in constraint
1542 This constraint is analogous to @samp{?} but it disparages slightly
1543 the alternative only if the operand with the @samp{^} needs a reload.
1545 @cindex @samp{$} in constraint
1548 This constraint is analogous to @samp{!} but it disparages severely
1549 the alternative only if the operand with the @samp{$} needs a reload.
1552 When an insn pattern has multiple alternatives in its constraints, often
1553 the appearance of the assembler code is determined mostly by which
1554 alternative was matched. When this is so, the C code for writing the
1555 assembler code can use the variable @code{which_alternative}, which is
1556 the ordinal number of the alternative that was actually satisfied (0 for
1557 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1561 So the first alternative for the 68000's logical-or could be written as
1562 @code{"+m" (output) : "ir" (input)}. The second could be @code{"+r"
1563 (output): "irm" (input)}. However, the fact that two memory locations
1564 cannot be used in a single instruction prevents simply using @code{"+rm"
1565 (output) : "irm" (input)}. Using multi-alternatives, this might be
1566 written as @code{"+m,r" (output) : "ir,irm" (input)}. This describes
1567 all the available alternatives to the compiler, allowing it to choose
1568 the most efficient one for the current conditions.
1570 There is no way within the template to determine which alternative was
1571 chosen. However you may be able to wrap your @code{asm} statements with
1572 builtins such as @code{__builtin_constant_p} to achieve the desired results.
1576 @node Class Preferences
1577 @subsection Register Class Preferences
1578 @cindex class preference constraints
1579 @cindex register class preference constraints
1581 @cindex voting between constraint alternatives
1582 The operand constraints have another function: they enable the compiler
1583 to decide which kind of hardware register a pseudo register is best
1584 allocated to. The compiler examines the constraints that apply to the
1585 insns that use the pseudo register, looking for the machine-dependent
1586 letters such as @samp{d} and @samp{a} that specify classes of registers.
1587 The pseudo register is put in whichever class gets the most ``votes''.
1588 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1589 favor of a general register. The machine description says which registers
1590 are considered general.
1592 Of course, on some machines all registers are equivalent, and no register
1593 classes are defined. Then none of this complexity is relevant.
1597 @subsection Constraint Modifier Characters
1598 @cindex modifiers in constraints
1599 @cindex constraint modifier characters
1601 @c prevent bad page break with this line
1602 Here are constraint modifier characters.
1605 @cindex @samp{=} in constraint
1607 Means that this operand is written to by this instruction:
1608 the previous value is discarded and replaced by new data.
1610 @cindex @samp{+} in constraint
1612 Means that this operand is both read and written by the instruction.
1614 When the compiler fixes up the operands to satisfy the constraints,
1615 it needs to know which operands are read by the instruction and
1616 which are written by it. @samp{=} identifies an operand which is only
1617 written; @samp{+} identifies an operand that is both read and written; all
1618 other operands are assumed to only be read.
1620 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1621 first character of the constraint string.
1623 @cindex @samp{&} in constraint
1624 @cindex earlyclobber operand
1626 Means (in a particular alternative) that this operand is an
1627 @dfn{earlyclobber} operand, which is written before the instruction is
1628 finished using the input operands. Therefore, this operand may not lie
1629 in a register that is read by the instruction or as part of any memory
1632 @samp{&} applies only to the alternative in which it is written. In
1633 constraints with multiple alternatives, sometimes one alternative
1634 requires @samp{&} while others do not. See, for example, the
1635 @samp{movdf} insn of the 68000.
1637 A operand which is read by the instruction can be tied to an earlyclobber
1638 operand if its only use as an input occurs before the early result is
1639 written. Adding alternatives of this form often allows GCC to produce
1640 better code when only some of the read operands can be affected by the
1641 earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@.
1643 Furthermore, if the @dfn{earlyclobber} operand is also a read/write
1644 operand, then that operand is written only after it's used.
1646 @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As
1647 @dfn{earlyclobber} operands are always written, a read-only
1648 @dfn{earlyclobber} operand is ill-formed and will be rejected by the
1651 @cindex @samp{%} in constraint
1653 Declares the instruction to be commutative for this operand and the
1654 following operand. This means that the compiler may interchange the
1655 two operands if that is the cheapest way to make all operands fit the
1656 constraints. @samp{%} applies to all alternatives and must appear as
1657 the first character in the constraint. Only read-only operands can use
1661 This is often used in patterns for addition instructions
1662 that really have only two operands: the result must go in one of the
1663 arguments. Here for example, is how the 68000 halfword-add
1664 instruction is defined:
1667 (define_insn "addhi3"
1668 [(set (match_operand:HI 0 "general_operand" "=m,r")
1669 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1670 (match_operand:HI 2 "general_operand" "di,g")))]
1674 GCC can only handle one commutative pair in an asm; if you use more,
1675 the compiler may fail. Note that you need not use the modifier if
1676 the two alternatives are strictly identical; this would only waste
1677 time in the reload pass.
1679 The modifier is not operational after
1680 register allocation, so the result of @code{define_peephole2}
1681 and @code{define_split}s performed after reload cannot rely on
1682 @samp{%} to make the intended insn match.
1684 @cindex @samp{#} in constraint
1686 Says that all following characters, up to the next comma, are to be
1687 ignored as a constraint. They are significant only for choosing
1688 register preferences.
1690 @cindex @samp{*} in constraint
1692 Says that the following character should be ignored when choosing
1693 register preferences. @samp{*} has no effect on the meaning of the
1694 constraint as a constraint, and no effect on reloading. For LRA
1695 @samp{*} additionally disparages slightly the alternative if the
1696 following character matches the operand.
1698 Here is an example: the 68000 has an instruction to sign-extend a
1699 halfword in a data register, and can also sign-extend a value by
1700 copying it into an address register. While either kind of register is
1701 acceptable, the constraints on an address-register destination are
1702 less strict, so it is best if register allocation makes an address
1703 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1704 constraint letter (for data register) is ignored when computing
1705 register preferences.
1708 (define_insn "extendhisi2"
1709 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1711 (match_operand:HI 1 "general_operand" "0,g")))]
1717 @node Machine Constraints
1718 @subsection Constraints for Particular Machines
1719 @cindex machine specific constraints
1720 @cindex constraints, machine specific
1722 Whenever possible, you should use the general-purpose constraint letters
1723 in @code{asm} arguments, since they will convey meaning more readily to
1724 people reading your code. Failing that, use the constraint letters
1725 that usually have very similar meanings across architectures. The most
1726 commonly used constraints are @samp{m} and @samp{r} (for memory and
1727 general-purpose registers respectively; @pxref{Simple Constraints}), and
1728 @samp{I}, usually the letter indicating the most common
1729 immediate-constant format.
1731 Each architecture defines additional constraints. These constraints
1732 are used by the compiler itself for instruction generation, as well as
1733 for @code{asm} statements; therefore, some of the constraints are not
1734 particularly useful for @code{asm}. Here is a summary of some of the
1735 machine-dependent constraints available on some particular machines;
1736 it includes both constraints that are useful for @code{asm} and
1737 constraints that aren't. The compiler source file mentioned in the
1738 table heading for each architecture is the definitive reference for
1739 the meanings of that architecture's constraints.
1741 @c Please keep this table alphabetized by target!
1743 @item AArch64 family---@file{config/aarch64/constraints.md}
1746 The stack pointer register (@code{SP})
1749 Floating point register, Advanced SIMD vector register or SVE vector register
1752 One of the low eight SVE predicate registers (@code{P0} to @code{P7})
1755 Any of the SVE predicate registers (@code{P0} to @code{P15})
1758 Integer constant that is valid as an immediate operand in an @code{ADD}
1762 Integer constant that is valid as an immediate operand in a @code{SUB}
1763 instruction (once negated)
1766 Integer constant that can be used with a 32-bit logical instruction
1769 Integer constant that can be used with a 64-bit logical instruction
1772 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1773 pseudo instruction. The @code{MOV} may be assembled to one of several different
1774 machine instructions depending on the value
1777 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1781 An absolute symbolic address or a label reference
1784 Floating point constant zero
1787 Integer constant zero
1790 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1791 within 4GB of the instruction
1794 A memory address which uses a single base register with no offset
1797 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1803 @item AMD GCN ---@file{config/gcn/constraints.md}
1806 Immediate integer in the range @minus{}16 to 64
1809 Immediate 16-bit signed integer
1812 Immediate constant @minus{}1
1815 Immediate 15-bit unsigned integer
1818 Immediate constant that can be inlined in an instruction encoding: integer
1819 @minus{}16..64, or float 0.0, +/@minus{}0.5, +/@minus{}1.0, +/@minus{}2.0,
1820 +/@minus{}4.0, 1.0/(2.0*PI)
1823 Immediate 32-bit signed integer that can be attached to an instruction encoding
1826 Immediate 32-bit integer in range @minus{}16..4294967295 (i.e. 32-bit unsigned
1827 integer or @samp{A} constraint)
1830 Immediate 64-bit constant that can be split into two @samp{A} constants
1833 Immediate 64-bit constant that can be split into two @samp{B} constants
1839 Any @code{symbol_ref} or @code{label_ref}
1848 SGPR registers valid for instruction destinations, including VCC, M0 and EXEC
1851 SGPR registers valid for instruction sources, including VCC, M0, EXEC and SCC
1854 SGPR registers valid as a source for scalar memory instructions (excludes M0
1858 SGPR registers valid as a source or destination for vector instructions
1862 All condition registers: SCC, VCCZ, EXECZ
1865 Scalar condition register: SCC
1868 Vector condition register: VCC, VCC_LO, VCC_HI
1871 EXEC register (EXEC_LO and EXEC_HI)
1874 Memory operand with address space suitable for @code{buffer_*} instructions
1877 Memory operand with address space suitable for @code{flat_*} instructions
1880 Memory operand with address space suitable for @code{s_*} instructions
1883 Memory operand with address space suitable for @code{ds_*} LDS instructions
1886 Memory operand with address space suitable for @code{ds_*} GDS instructions
1889 Memory operand with address space suitable for any @code{ds_*} instructions
1892 Memory operand with address space suitable for @code{global_*} instructions
1897 @item ARC ---@file{config/arc/constraints.md}
1900 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1901 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1902 option is in effect.
1905 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1906 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1907 This constraint can only match when the @option{-mq}
1908 option is in effect.
1910 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1913 A signed 12-bit integer constant.
1916 constant for arithmetic/logical operations. This might be any constant
1917 that can be put into a long immediate by the assmbler or linker without
1918 involving a PIC relocation.
1921 A 3-bit unsigned integer constant.
1924 A 6-bit unsigned integer constant.
1927 One's complement of a 6-bit unsigned integer constant.
1930 Two's complement of a 6-bit unsigned integer constant.
1933 A 5-bit unsigned integer constant.
1936 A 7-bit unsigned integer constant.
1939 A 8-bit unsigned integer constant.
1942 Any const_double value.
1945 @item ARM family---@file{config/arm/constraints.md}
1949 In Thumb state, the core registers @code{r8}-@code{r15}.
1952 The stack pointer register.
1955 In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this
1956 is an alias for the @code{r} constraint.
1959 VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values.
1962 VFP floating-point registers @code{d0}-@code{d31} and the appropriate
1963 subset @code{d0}-@code{d15} based on command line options.
1964 Used for 64 bit values only. Not valid for Thumb1.
1967 The iWMMX co-processor registers.
1970 The iWMMX GR registers.
1973 The floating-point constant 0.0
1976 Integer that is valid as an immediate operand in a data processing
1977 instruction. That is, an integer in the range 0 to 255 rotated by a
1981 Integer in the range @minus{}4095 to 4095
1984 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1987 Integer that satisfies constraint @samp{I} when negated (twos complement)
1990 Integer in the range 0 to 32
1993 A memory reference where the exact address is in a single register
1994 (`@samp{m}' is preferable for @code{asm} statements)
1997 An item in the constant pool
2000 A symbol in the text segment of the current file
2003 A memory reference suitable for VFP load/store insns (reg+constant offset)
2006 A memory reference suitable for iWMMXt load/store instructions.
2009 A memory reference suitable for the ARMv4 ldrsb instruction.
2012 @item AVR family---@file{config/avr/constraints.md}
2015 Registers from r0 to r15
2018 Registers from r16 to r23
2021 Registers from r16 to r31
2024 Registers from r24 to r31. These registers can be used in @samp{adiw} command
2027 Pointer register (r26--r31)
2030 Base pointer register (r28--r31)
2033 Stack pointer register (SPH:SPL)
2036 Temporary register r0
2039 Register pair X (r27:r26)
2042 Register pair Y (r29:r28)
2045 Register pair Z (r31:r30)
2048 Constant greater than @minus{}1, less than 64
2051 Constant greater than @minus{}64, less than 1
2060 Constant that fits in 8 bits
2063 Constant integer @minus{}1
2066 Constant integer 8, 16, or 24
2072 A floating point constant 0.0
2075 A memory address based on Y or Z pointer with displacement.
2078 @item Blackfin family---@file{config/bfin/constraints.md}
2087 A call clobbered P register.
2090 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2091 register. If it is @code{A}, then the register P0.
2094 Even-numbered D register
2097 Odd-numbered D register
2100 Accumulator register.
2103 Even-numbered accumulator register.
2106 Odd-numbered accumulator register.
2118 Registers used for circular buffering, i.e.@: I, B, or L registers.
2133 Any D, P, B, M, I or L register.
2136 Additional registers typically used only in prologues and epilogues: RETS,
2137 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2140 Any register except accumulators or CC.
2143 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2146 Unsigned 16 bit integer (in the range 0 to 65535)
2149 Signed 7 bit integer (in the range @minus{}64 to 63)
2152 Unsigned 7 bit integer (in the range 0 to 127)
2155 Unsigned 5 bit integer (in the range 0 to 31)
2158 Signed 4 bit integer (in the range @minus{}8 to 7)
2161 Signed 3 bit integer (in the range @minus{}3 to 4)
2164 Unsigned 3 bit integer (in the range 0 to 7)
2167 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2170 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2171 use with either accumulator.
2174 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2175 use only with accumulator A1.
2184 An integer constant with exactly a single bit set.
2187 An integer constant with all bits set except exactly one.
2195 @item CR16 Architecture---@file{config/cr16/cr16.h}
2199 Registers from r0 to r14 (registers without stack pointer)
2202 Register from r0 to r11 (all 16-bit registers)
2205 Register from r12 to r15 (all 32-bit registers)
2208 Signed constant that fits in 4 bits
2211 Signed constant that fits in 5 bits
2214 Signed constant that fits in 6 bits
2217 Unsigned constant that fits in 4 bits
2220 Signed constant that fits in 32 bits
2223 Check for 64 bits wide constants for add/sub instructions
2226 Floating point constant that is legal for store immediate
2229 @item C-SKY---@file{config/csky/constraints.md}
2233 The mini registers r0 - r7.
2236 The low registers r0 - r15.
2242 HI and LO registers.
2254 Stack pointer register (SP).
2258 The C-SKY back end supports a large set of additional constraints
2259 that are only useful for instruction selection or splitting rather
2260 than inline asm, such as constraints representing constant integer
2261 ranges accepted by particular instruction encodings.
2262 Refer to the source code for details.
2265 @item Epiphany---@file{config/epiphany/constraints.md}
2268 An unsigned 16-bit constant.
2271 An unsigned 5-bit constant.
2274 A signed 11-bit constant.
2277 A signed 11-bit constant added to @minus{}1.
2278 Can only match when the @option{-m1reg-@var{reg}} option is active.
2281 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
2282 being a block of trailing zeroes.
2283 Can only match when the @option{-m1reg-@var{reg}} option is active.
2286 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
2287 rest being zeroes. Or to put it another way, one less than a power of two.
2288 Can only match when the @option{-m1reg-@var{reg}} option is active.
2291 Constant for arithmetic/logical operations.
2292 This is like @code{i}, except that for position independent code,
2293 no symbols / expressions needing relocations are allowed.
2296 Symbolic constant for call/jump instruction.
2299 The register class usable in short insns. This is a register class
2300 constraint, and can thus drive register allocation.
2301 This constraint won't match unless @option{-mprefer-short-insn-regs} is
2305 The the register class of registers that can be used to hold a
2306 sibcall call address. I.e., a caller-saved register.
2309 Core control register class.
2312 The register group usable in short insns.
2313 This constraint does not use a register class, so that it only
2314 passively matches suitable registers, and doesn't drive register allocation.
2318 Constant suitable for the addsi3_r pattern. This is a valid offset
2319 For byte, halfword, or word addressing.
2323 Matches the return address if it can be replaced with the link register.
2326 Matches the integer condition code register.
2329 Matches the return address if it is in a stack slot.
2332 Matches control register values to switch fp mode, which are encapsulated in
2333 @code{UNSPEC_FP_MODE}.
2336 @item FRV---@file{config/frv/frv.h}
2339 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2342 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2345 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2346 @code{icc0} to @code{icc3}).
2349 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2352 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2353 Odd registers are excluded not in the class but through the use of a machine
2354 mode larger than 4 bytes.
2357 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2360 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2361 Odd registers are excluded not in the class but through the use of a machine
2362 mode larger than 4 bytes.
2365 Register in the class @code{LR_REG} (the @code{lr} register).
2368 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2369 Register numbers not divisible by 4 are excluded not in the class but through
2370 the use of a machine mode larger than 8 bytes.
2373 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2376 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2379 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2382 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2385 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2386 Register numbers not divisible by 4 are excluded not in the class but through
2387 the use of a machine mode larger than 8 bytes.
2390 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2393 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2396 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2399 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2402 Floating point constant zero
2405 6-bit signed integer constant
2408 10-bit signed integer constant
2411 16-bit signed integer constant
2414 16-bit unsigned integer constant
2417 12-bit signed integer constant that is negative---i.e.@: in the
2418 range of @minus{}2048 to @minus{}1
2424 12-bit signed integer constant that is greater than zero---i.e.@: in the
2429 @item FT32---@file{config/ft32/constraints.md}
2438 A register indirect memory operand
2447 The constant zero or one
2450 A 16-bit signed constant (@minus{}32768 @dots{} 32767)
2453 A bitfield mask suitable for bext or bins
2456 An inverted bitfield mask suitable for bext or bins
2459 A 16-bit unsigned constant, multiple of 4 (0 @dots{} 65532)
2462 A 20-bit signed constant (@minus{}524288 @dots{} 524287)
2465 A constant for a bitfield width (1 @dots{} 16)
2468 A 10-bit signed constant (@minus{}512 @dots{} 511)
2472 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2478 Floating point register
2481 Shift amount register
2484 Floating point register (deprecated)
2487 Upper floating point register (32-bit), floating point register (64-bit)
2493 Signed 11-bit integer constant
2496 Signed 14-bit integer constant
2499 Integer constant that can be deposited with a @code{zdepi} instruction
2502 Signed 5-bit integer constant
2508 Integer constant that can be loaded with a @code{ldil} instruction
2511 Integer constant whose value plus one is a power of 2
2514 Integer constant that can be used for @code{and} operations in @code{depi}
2515 and @code{extru} instructions
2524 Floating-point constant 0.0
2527 A @code{lo_sum} data-linkage-table memory operand
2530 A memory operand that can be used as the destination operand of an
2531 integer store instruction
2534 A scaled or unscaled indexed memory operand
2537 A memory operand for floating-point loads and stores
2540 A register indirect memory operand
2543 @item Intel IA-64---@file{config/ia64/ia64.h}
2546 General register @code{r0} to @code{r3} for @code{addl} instruction
2552 Predicate register (@samp{c} as in ``conditional'')
2555 Application register residing in M-unit
2558 Application register residing in I-unit
2561 Floating-point register
2564 Memory operand. If used together with @samp{<} or @samp{>},
2565 the operand can have postincrement and postdecrement which
2566 require printing with @samp{%Pn} on IA-64.
2569 Floating-point constant 0.0 or 1.0
2572 14-bit signed integer constant
2575 22-bit signed integer constant
2578 8-bit signed integer constant for logical instructions
2581 8-bit adjusted signed integer constant for compare pseudo-ops
2584 6-bit unsigned integer constant for shift counts
2587 9-bit signed integer constant for load and store postincrements
2593 0 or @minus{}1 for @code{dep} instruction
2596 Non-volatile memory for floating-point loads and stores
2599 Integer constant in the range 1 to 4 for @code{shladd} instruction
2602 Memory operand except postincrement and postdecrement. This is
2603 now roughly the same as @samp{m} when not used together with @samp{<}
2607 @item M32C---@file{config/m32c/m32c.c}
2612 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2615 Any control register, when they're 16 bits wide (nothing if control
2616 registers are 24 bits wide)
2619 Any control register, when they're 24 bits wide.
2628 $r0 or $r2, or $r2r0 for 32 bit values.
2631 $r1 or $r3, or $r3r1 for 32 bit values.
2634 A register that can hold a 64 bit value.
2637 $r0 or $r1 (registers with addressable high/low bytes)
2646 Address registers when they're 16 bits wide.
2649 Address registers when they're 24 bits wide.
2652 Registers that can hold QI values.
2655 Registers that can be used with displacements ($a0, $a1, $sb).
2658 Registers that can hold 32 bit values.
2661 Registers that can hold 16 bit values.
2664 Registers chat can hold 16 bit values, including all control
2668 $r0 through R1, plus $a0 and $a1.
2674 The memory-based pseudo-registers $mem0 through $mem15.
2677 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2678 bit registers for m32cm, m32c).
2681 Matches multiple registers in a PARALLEL to form a larger register.
2682 Used to match function return values.
2688 @minus{}128 @dots{} 127
2691 @minus{}32768 @dots{} 32767
2697 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2700 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2703 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2706 @minus{}65536 @dots{} @minus{}1
2709 An 8 bit value with exactly one bit set.
2712 A 16 bit value with exactly one bit set.
2715 The common src/dest memory addressing modes.
2718 Memory addressed using $a0 or $a1.
2721 Memory addressed with immediate addresses.
2724 Memory addressed using the stack pointer ($sp).
2727 Memory addressed using the frame base register ($fb).
2730 Memory addressed using the small base register ($sb).
2736 @item MicroBlaze---@file{config/microblaze/constraints.md}
2739 A general register (@code{r0} to @code{r31}).
2742 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2746 @item MIPS---@file{config/mips/constraints.md}
2749 A general-purpose register. This is equivalent to @code{r} unless
2750 generating MIPS16 code, in which case the MIPS16 register set is used.
2753 A floating-point register (if available).
2756 Formerly the @code{hi} register. This constraint is no longer supported.
2759 The @code{lo} register. Use this register to store values that are
2760 no bigger than a word.
2763 The concatenated @code{hi} and @code{lo} registers. Use this register
2764 to store doubleword values.
2767 A register suitable for use in an indirect jump. This will always be
2768 @code{$25} for @option{-mabicalls}.
2771 Register @code{$3}. Do not use this constraint in new code;
2772 it is retained only for compatibility with glibc.
2775 Equivalent to @code{r}; retained for backwards compatibility.
2778 A floating-point condition code register.
2781 A signed 16-bit constant (for arithmetic instructions).
2787 An unsigned 16-bit constant (for logic instructions).
2790 A signed 32-bit constant in which the lower 16 bits are zero.
2791 Such constants can be loaded using @code{lui}.
2794 A constant that cannot be loaded using @code{lui}, @code{addiu}
2798 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2801 A signed 15-bit constant.
2804 A constant in the range 1 to 65535 (inclusive).
2807 Floating-point zero.
2810 An address that can be used in a non-macro load or store.
2813 A memory operand whose address is formed by a base register and offset
2814 that is suitable for use in instructions with the same addressing mode
2815 as @code{ll} and @code{sc}.
2818 An address suitable for a @code{prefetch} instruction, or for any other
2819 instruction with the same addressing mode as @code{prefetch}.
2822 @item Motorola 680x0---@file{config/m68k/constraints.md}
2831 68881 floating-point register, if available
2834 Integer in the range 1 to 8
2837 16-bit signed number
2840 Signed number whose magnitude is greater than 0x80
2843 Integer in the range @minus{}8 to @minus{}1
2846 Signed number whose magnitude is greater than 0x100
2849 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2852 16 (for rotate using swap)
2855 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2858 Numbers that mov3q can handle
2861 Floating point constant that is not a 68881 constant
2864 Operands that satisfy 'm' when -mpcrel is in effect
2867 Operands that satisfy 's' when -mpcrel is not in effect
2870 Address register indirect addressing mode
2873 Register offset addressing
2888 Range of signed numbers that don't fit in 16 bits
2891 Integers valid for mvq
2894 Integers valid for a moveq followed by a swap
2897 Integers valid for mvz
2900 Integers valid for mvs
2906 Non-register operands allowed in clr
2910 @item Moxie---@file{config/moxie/constraints.md}
2919 A register indirect memory operand
2922 A constant in the range of 0 to 255.
2925 A constant in the range of 0 to @minus{}255.
2929 @item MSP430--@file{config/msp430/constraints.md}
2942 Integer constant -1^20..1^19.
2945 Integer constant 1-4.
2948 Memory references which do not require an extended MOVX instruction.
2951 Memory reference, labels only.
2954 Memory reference, stack only.
2958 @item NDS32---@file{config/nds32/constraints.md}
2961 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
2963 LOW register class $r0 to $r7.
2965 MIDDLE register class $r0 to $r11, $r16 to $r19.
2967 HIGH register class $r12 to $r14, $r20 to $r31.
2969 Temporary assist register $ta (i.e.@: $r15).
2973 Unsigned immediate 3-bit value.
2975 Negative immediate 3-bit value in the range of @minus{}7--0.
2977 Unsigned immediate 4-bit value.
2979 Signed immediate 5-bit value.
2981 Unsigned immediate 5-bit value.
2983 Negative immediate 5-bit value in the range of @minus{}31--0.
2985 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
2987 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
2989 Unsigned immediate 8-bit value.
2991 Unsigned immediate 9-bit value.
2993 Signed immediate 10-bit value.
2995 Signed immediate 11-bit value.
2997 Signed immediate 15-bit value.
2999 Unsigned immediate 15-bit value.
3001 A constant which is not in the range of imm15u but ok for bclr instruction.
3003 A constant which is not in the range of imm15u but ok for bset instruction.
3005 A constant which is not in the range of imm15u but ok for btgl instruction.
3007 A constant whose compliment value is in the range of imm15u
3008 and ok for bitci instruction.
3010 Signed immediate 16-bit value.
3012 Signed immediate 17-bit value.
3014 Signed immediate 19-bit value.
3016 Signed immediate 20-bit value.
3018 The immediate value that can be simply set high 20-bit.
3020 The immediate value 0xff.
3022 The immediate value 0xffff.
3024 The immediate value 0x01.
3026 The immediate value 0x7ff.
3028 The immediate value with power of 2.
3030 The immediate value with power of 2 minus 1.
3032 Memory constraint for 333 format.
3034 Memory constraint for 45 format.
3036 Memory constraint for 37 format.
3039 @item Nios II family---@file{config/nios2/constraints.md}
3043 Integer that is valid as an immediate operand in an
3044 instruction taking a signed 16-bit number. Range
3045 @minus{}32768 to 32767.
3048 Integer that is valid as an immediate operand in an
3049 instruction taking an unsigned 16-bit number. Range
3053 Integer that is valid as an immediate operand in an
3054 instruction taking only the upper 16-bits of a
3055 32-bit number. Range 32-bit numbers with the lower
3059 Integer that is valid as an immediate operand for a
3060 shift instruction. Range 0 to 31.
3063 Integer that is valid as an immediate operand for
3064 only the value 0. Can be used in conjunction with
3065 the format modifier @code{z} to use @code{r0}
3066 instead of @code{0} in the assembly output.
3069 Integer that is valid as an immediate operand for
3070 a custom instruction opcode. Range 0 to 255.
3073 An immediate operand for R2 andchi/andci instructions.
3076 Matches immediates which are addresses in the small
3077 data section and therefore can be added to @code{gp}
3078 as a 16-bit immediate to re-create their 32-bit value.
3081 Matches constants suitable as an operand for the rdprs and
3085 A memory operand suitable for Nios II R2 load/store
3086 exclusive instructions.
3089 A memory operand suitable for load/store IO and cache
3094 A @code{const} wrapped @code{UNSPEC} expression,
3095 representing a supported PIC or TLS relocation.
3100 @item OpenRISC---@file{config/or1k/constraints.md}
3103 Integer that is valid as an immediate operand in an
3104 instruction taking a signed 16-bit number. Range
3105 @minus{}32768 to 32767.
3108 Integer that is valid as an immediate operand in an
3109 instruction taking an unsigned 16-bit number. Range
3113 Signed 16-bit constant shifted left 16 bits. (Used with @code{l.movhi})
3120 Register usable for sibcalls.
3125 @item PDP-11---@file{config/pdp11/constraints.md}
3128 Floating point registers AC0 through AC3. These can be loaded from/to
3129 memory with a single instruction.
3132 Odd numbered general registers (R1, R3, R5). These are used for
3133 16-bit multiply operations.
3136 A memory reference that is encoded within the opcode, but not
3137 auto-increment or auto-decrement.
3140 Any of the floating point registers (AC0 through AC5).
3143 Floating point constant 0.
3146 Floating point registers AC4 and AC5. These cannot be loaded from/to
3147 memory with a single instruction.
3150 An integer constant that fits in 16 bits.
3153 An integer constant whose low order 16 bits are zero.
3156 An integer constant that does not meet the constraints for codes
3157 @samp{I} or @samp{J}.
3160 The integer constant 1.
3163 The integer constant @minus{}1.
3166 The integer constant 0.
3169 Integer constants 0 through 3; shifts by these
3170 amounts are handled as multiple single-bit shifts rather than a single
3171 variable-length shift.
3174 A memory reference which requires an additional word (address or
3175 offset) after the opcode.
3178 A memory reference that is encoded within the opcode.
3182 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
3185 Address base register
3188 Floating point register (containing 64-bit value)
3191 Floating point register (containing 32-bit value)
3194 Altivec vector register
3197 Any VSX register if the @option{-mvsx} option was used or NO_REGS.
3199 When using the register constraint @code{wa}
3200 that takes VSX registers, you must use @code{%x<n>} in the template so
3201 that the correct register is used. Otherwise the register number
3202 output in the assembly file will be incorrect if an Altivec register
3203 is an operand of a VSX instruction that expects VSX register
3207 asm ("xvadddp %x0,%x1,%x2"
3209 : "wa" (v2), "wa" (v3));
3216 asm ("xvadddp %0,%1,%2"
3218 : "wa" (v2), "wa" (v3));
3224 If an instruction only takes Altivec registers, you do not want to use
3228 asm ("xsaddqp %0,%1,%2"
3230 : "v" (v2), "v" (v3));
3234 is correct because the @code{xsaddqp} instruction only takes Altivec
3238 asm ("xsaddqp %x0,%x1,%x2"
3240 : "v" (v2), "v" (v3));
3247 VSX register if the @option{-mcpu=power9} and @option{-m64} options
3248 were used or NO_REGS.
3251 No register (NO_REGS).
3254 General purpose register if 64-bit instructions are enabled or NO_REGS.
3257 Floating point register if the STFIWX instruction is enabled or NO_REGS.
3260 Address base register if 64-bit instructions are enabled or NO_REGS.
3263 Signed 5-bit constant integer that can be loaded into an altivec register.
3266 Int constant that is the element number of the 64-bit scalar in a vector.
3269 Vector constant that can be loaded with the XXSPLTIB instruction.
3272 Memory operand suitable for power8 GPR load fusion
3275 Memory operand suitable for TOC fusion memory references.
3278 Int constant that is the element number that the MFVSRLD instruction.
3282 Match vector constant with all 1's if the XXLORC instruction is available.
3285 A memory operand suitable for the ISA 3.0 vector d-form instructions.
3288 A memory address that will work with the @code{lq} and @code{stq}
3292 Vector constant that can be loaded with XXSPLTIB & sign extension.
3295 @samp{VRSAVE}, @samp{CTR}, or @samp{LINK} register
3301 @samp{LINK} register
3304 @samp{CR} register (condition register) number 0
3307 @samp{CR} register (condition register)
3310 @samp{XER[CA]} carry bit (part of the XER register)
3313 Signed 16-bit constant
3316 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
3317 @code{SImode} constants)
3320 Unsigned 16-bit constant
3323 Signed 16-bit constant shifted left 16 bits
3326 Constant larger than 31
3335 Constant whose negation is a signed 16-bit constant
3338 Signed 34-bit integer constant if prefixed instructions are supported.
3341 Floating point constant that can be loaded into a register with one
3342 instruction per word
3345 Integer/Floating point constant that can be loaded into a register using
3350 Normally, @code{m} does not allow addresses that update the base register.
3351 If @samp{<} or @samp{>} constraint is also used, they are allowed and
3352 therefore on PowerPC targets in that case it is only safe
3353 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
3354 accesses the operand exactly once. The @code{asm} statement must also
3355 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
3356 corresponding load or store instruction. For example:
3359 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
3365 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
3371 A ``stable'' memory operand; that is, one which does not include any
3372 automodification of the base register. This used to be useful when
3373 @samp{m} allowed automodification of the base register, but as those are now only
3374 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
3375 as @samp{m} without @samp{<} and @samp{>}.
3378 Memory operand that is an offset from a register (it is usually better
3379 to use @samp{m} or @samp{es} in @code{asm} statements)
3382 Memory operand that is an indexed or indirect from a register (it is
3383 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
3389 Address operand that is an indexed or indirect from a register (@samp{p} is
3390 preferable for @code{asm} statements)
3393 System V Release 4 small data area reference
3396 Vector constant that does not require memory
3399 Vector constant that is all zeros.
3403 @item PRU---@file{config/pru/constraints.md}
3406 An unsigned 8-bit integer constant.
3409 An unsigned 16-bit integer constant.
3412 An unsigned 5-bit integer constant (for shift counts).
3415 A text segment (program memory) constant label.
3418 Integer constant zero.
3422 @item RL78---@file{config/rl78/constraints.md}
3426 An integer constant in the range 1 @dots{} 7.
3428 An integer constant in the range 0 @dots{} 255.
3430 An integer constant in the range @minus{}255 @dots{} 0
3432 The integer constant 1.
3434 The integer constant -1.
3436 The integer constant 0.
3438 The integer constant 2.
3440 The integer constant -2.
3442 An integer constant in the range 1 @dots{} 15.
3444 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3446 The synthetic compare types--gt, lt, ge, and le.
3448 A memory reference with an absolute address.
3450 A memory reference using @code{BC} as a base register, with an optional offset.
3452 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3454 A memory reference using any 16-bit register pair for the address, for calls.
3456 A memory reference using @code{DE} as a base register, with an optional offset.
3458 A memory reference using @code{DE} as a base register, without any offset.
3460 Any memory reference to an address in the far address space.
3462 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3464 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3466 A memory reference using @code{HL} as a base register, without any offset.
3468 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3470 Any memory reference to an address in the near address space.
3472 The @code{AX} register.
3474 The @code{BC} register.
3476 The @code{DE} register.
3478 @code{A} through @code{L} registers.
3480 The @code{SP} register.
3482 The @code{HL} register.
3484 The 16-bit @code{R8} register.
3486 The 16-bit @code{R10} register.
3488 The registers reserved for interrupts (@code{R24} to @code{R31}).
3490 The @code{A} register.
3492 The @code{B} register.
3494 The @code{C} register.
3496 The @code{D} register.
3498 The @code{E} register.
3500 The @code{H} register.
3502 The @code{L} register.
3504 The virtual registers.
3506 The @code{PSW} register.
3508 The @code{X} register.
3512 @item RISC-V---@file{config/riscv/constraints.md}
3516 A floating-point register (if availiable).
3519 An I-type 12-bit signed immediate.
3525 A 5-bit unsigned immediate for CSR access instructions.
3528 An address that is held in a general-purpose register.
3532 @item RX---@file{config/rx/constraints.md}
3535 An address which does not involve register indirect addressing or
3536 pre/post increment/decrement addressing.
3542 A constant in the range @minus{}256 to 255, inclusive.
3545 A constant in the range @minus{}128 to 127, inclusive.
3548 A constant in the range @minus{}32768 to 32767, inclusive.
3551 A constant in the range @minus{}8388608 to 8388607, inclusive.
3554 A constant in the range 0 to 15, inclusive.
3558 @item S/390 and zSeries---@file{config/s390/s390.h}
3561 Address register (general purpose register except r0)
3564 Condition code register
3567 Data register (arbitrary general purpose register)
3570 Floating-point register
3573 Unsigned 8-bit constant (0--255)
3576 Unsigned 12-bit constant (0--4095)
3579 Signed 16-bit constant (@minus{}32768--32767)
3582 Value appropriate as displacement.
3585 for short displacement
3586 @item (@minus{}524288..524287)
3587 for long displacement
3591 Constant integer with a value of 0x7fffffff.
3594 Multiple letter constraint followed by 4 parameter letters.
3597 number of the part counting from most to least significant
3601 mode of the containing operand
3603 value of the other parts (F---all bits set)
3605 The constraint matches if the specified part of a constant
3606 has a value different from its other parts.
3609 Memory reference without index register and with short displacement.
3612 Memory reference with index register and short displacement.
3615 Memory reference without index register but with long displacement.
3618 Memory reference with index register and long displacement.
3621 Pointer with short displacement.
3624 Pointer with long displacement.
3627 Shift count operand.
3632 @item SPARC---@file{config/sparc/sparc.h}
3635 Floating-point register on the SPARC-V8 architecture and
3636 lower floating-point register on the SPARC-V9 architecture.
3639 Floating-point register. It is equivalent to @samp{f} on the
3640 SPARC-V8 architecture and contains both lower and upper
3641 floating-point registers on the SPARC-V9 architecture.
3644 Floating-point condition code register.
3647 Lower floating-point register. It is only valid on the SPARC-V9
3648 architecture when the Visual Instruction Set is available.
3651 Floating-point register. It is only valid on the SPARC-V9 architecture
3652 when the Visual Instruction Set is available.
3655 64-bit global or out register for the SPARC-V8+ architecture.
3658 The constant all-ones, for floating-point.
3661 Signed 5-bit constant
3667 Signed 13-bit constant
3673 32-bit constant with the low 12 bits clear (a constant that can be
3674 loaded with the @code{sethi} instruction)
3677 A constant in the range supported by @code{movcc} instructions (11-bit
3681 A constant in the range supported by @code{movrcc} instructions (10-bit
3685 Same as @samp{K}, except that it verifies that bits that are not in the
3686 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3687 modes wider than @code{SImode}
3696 Signed 13-bit constant, sign-extended to 32 or 64 bits
3702 Floating-point constant whose integral representation can
3703 be moved into an integer register using a single sethi
3707 Floating-point constant whose integral representation can
3708 be moved into an integer register using a single mov
3712 Floating-point constant whose integral representation can
3713 be moved into an integer register using a high/lo_sum
3714 instruction sequence
3717 Memory address aligned to an 8-byte boundary
3723 Memory address for @samp{e} constraint registers
3726 Memory address with only a base register
3733 @item SPU---@file{config/spu/spu.h}
3736 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3739 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3742 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3745 An immediate which can be loaded with @code{fsmbi}.
3748 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3751 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3754 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3757 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3760 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3763 An unsigned 7-bit constant for conversion/nop/channel instructions.
3766 A signed 10-bit constant for most arithmetic instructions.
3769 A signed 16 bit immediate for @code{stop}.
3772 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3775 An unsigned 7-bit constant whose 3 least significant bits are 0.
3778 An unsigned 3-bit constant for 16-byte rotates and shifts
3781 Call operand, reg, for indirect calls
3784 Call operand, symbol, for relative calls.
3787 Call operand, const_int, for absolute calls.
3790 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3793 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3796 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3799 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3803 @item TI C6X family---@file{config/c6x/constraints.md}
3806 Register file A (A0--A31).
3809 Register file B (B0--B31).
3812 Predicate registers in register file A (A0--A2 on C64X and
3813 higher, A1 and A2 otherwise).
3816 Predicate registers in register file B (B0--B2).
3819 A call-used register in register file B (B0--B9, B16--B31).
3822 Register file A, excluding predicate registers (A3--A31,
3823 plus A0 if not C64X or higher).
3826 Register file B, excluding predicate registers (B3--B31).
3829 Integer constant in the range 0 @dots{} 15.
3832 Integer constant in the range 0 @dots{} 31.
3835 Integer constant in the range @minus{}31 @dots{} 0.
3838 Integer constant in the range @minus{}16 @dots{} 15.
3841 Integer constant that can be the operand of an ADDA or a SUBA insn.
3844 Integer constant in the range 0 @dots{} 65535.
3847 Integer constant in the range @minus{}32768 @dots{} 32767.
3850 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3853 Integer constant that is a valid mask for the clr instruction.
3856 Integer constant that is a valid mask for the set instruction.
3859 Memory location with A base register.
3862 Memory location with B base register.
3866 On C64x+ targets, a GP-relative small data reference.
3869 Any kind of @code{SYMBOL_REF}, for use in a call address.
3872 Any kind of immediate operand, unless it matches the S0 constraint.
3875 Memory location with B base register, but not using a long offset.
3878 A memory operand with an address that cannot be used in an unaligned access.
3882 Register B14 (aka DP).
3886 @item TILE-Gx---@file{config/tilegx/constraints.md}
3899 Each of these represents a register constraint for an individual
3900 register, from r0 to r10.
3903 Signed 8-bit integer constant.
3906 Signed 16-bit integer constant.
3909 Unsigned 16-bit integer constant.
3912 Integer constant that fits in one signed byte when incremented by one
3913 (@minus{}129 @dots{} 126).
3916 Memory operand. If used together with @samp{<} or @samp{>}, the
3917 operand can have postincrement which requires printing with @samp{%In}
3918 and @samp{%in} on TILE-Gx. For example:
3921 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3925 A bit mask suitable for the BFINS instruction.
3928 Integer constant that is a byte tiled out eight times.
3931 The integer zero constant.
3934 Integer constant that is a sign-extended byte tiled out as four shorts.
3937 Integer constant that fits in one signed byte when incremented
3938 (@minus{}129 @dots{} 126), but excluding -1.
3941 Integer constant that has all 1 bits consecutive and starting at bit 0.
3944 A 16-bit fragment of a got, tls, or pc-relative reference.
3947 Memory operand except postincrement. This is roughly the same as
3948 @samp{m} when not used together with @samp{<} or @samp{>}.
3951 An 8-element vector constant with identical elements.
3954 A 4-element vector constant with identical elements.
3957 The integer constant 0xffffffff.
3960 The integer constant 0xffffffff00000000.
3964 @item TILEPro---@file{config/tilepro/constraints.md}
3977 Each of these represents a register constraint for an individual
3978 register, from r0 to r10.
3981 Signed 8-bit integer constant.
3984 Signed 16-bit integer constant.
3987 Nonzero integer constant with low 16 bits zero.
3990 Integer constant that fits in one signed byte when incremented by one
3991 (@minus{}129 @dots{} 126).
3994 Memory operand. If used together with @samp{<} or @samp{>}, the
3995 operand can have postincrement which requires printing with @samp{%In}
3996 and @samp{%in} on TILEPro. For example:
3999 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
4003 A bit mask suitable for the MM instruction.
4006 Integer constant that is a byte tiled out four times.
4009 The integer zero constant.
4012 Integer constant that is a sign-extended byte tiled out as two shorts.
4015 Integer constant that fits in one signed byte when incremented
4016 (@minus{}129 @dots{} 126), but excluding -1.
4019 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
4023 Memory operand except postincrement. This is roughly the same as
4024 @samp{m} when not used together with @samp{<} or @samp{>}.
4027 A 4-element vector constant with identical elements.
4030 A 2-element vector constant with identical elements.
4034 @item Visium---@file{config/visium/constraints.md}
4037 EAM register @code{mdb}
4040 EAM register @code{mdc}
4043 Floating point register
4047 Register for sibcall optimization
4051 General register, but not @code{r29}, @code{r30} and @code{r31}
4063 Floating-point constant 0.0
4066 Integer constant in the range 0 .. 65535 (16-bit immediate)
4069 Integer constant in the range 1 .. 31 (5-bit immediate)
4072 Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
4075 Integer constant @minus{}1
4084 @item x86 family---@file{config/i386/constraints.md}
4087 Legacy register---the eight integer registers available on all
4088 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
4089 @code{si}, @code{di}, @code{bp}, @code{sp}).
4092 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
4093 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
4096 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
4097 @code{c}, and @code{d}.
4101 Any register that can be used as the index in a base+index memory
4102 access: that is, any general register except the stack pointer.
4106 The @code{a} register.
4109 The @code{b} register.
4112 The @code{c} register.
4115 The @code{d} register.
4118 The @code{si} register.
4121 The @code{di} register.
4124 The @code{a} and @code{d} registers. This class is used for instructions
4125 that return double word results in the @code{ax:dx} register pair. Single
4126 word values will be allocated either in @code{ax} or @code{dx}.
4127 For example on i386 the following implements @code{rdtsc}:
4130 unsigned long long rdtsc (void)
4132 unsigned long long tick;
4133 __asm__ __volatile__("rdtsc":"=A"(tick));
4138 This is not correct on x86-64 as it would allocate tick in either @code{ax}
4139 or @code{dx}. You have to use the following variant instead:
4142 unsigned long long rdtsc (void)
4144 unsigned int tickl, tickh;
4145 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
4146 return ((unsigned long long)tickh << 32)|tickl;
4151 The call-clobbered integer registers.
4154 Any 80387 floating-point (stack) register.
4157 Top of 80387 floating-point stack (@code{%st(0)}).
4160 Second from top of 80387 floating-point stack (@code{%st(1)}).
4164 Any mask register that can be used as a predicate, i.e.@: @code{k1-k7}.
4177 Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).
4185 First SSE register (@code{%xmm0}).
4189 Any SSE register, when SSE2 and inter-unit moves are enabled.
4192 Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.
4195 Any MMX register, when inter-unit moves are enabled.
4198 Any MMX register, when inter-unit moves from vector registers are enabled.
4201 Any integer register when @code{TARGET_PARTIAL_REG_STALL} is disabled.
4204 Any integer register when zero extensions with @code{AND} are disabled.
4207 Any register that can be used as the GOT base when calling@*
4208 @code{___tls_get_addr}: that is, any general register except @code{a}
4209 and @code{sp} registers, for @option{-fno-plt} if linker supports it.
4210 Otherwise, @code{b} register.
4213 Any x87 register when 80387 floating-point arithmetic is enabled.
4216 Lower SSE register when avoiding REX prefix and all SSE registers otherwise.
4219 For AVX512VL, any EVEX-encodable SSE register (@code{%xmm0-%xmm31}),
4220 otherwise any SSE register.
4223 Any EVEX-encodable SSE register, that has number factor of four.
4226 Flags register operand.
4232 Vector memory operand.
4235 Constant memory operand.
4238 Memory operand without REX prefix.
4241 Sibcall memory operand.
4244 Call memory operand.
4247 Constant call address operand.
4250 SSE constant -1 operand.
4254 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
4257 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
4260 Signed 8-bit integer constant.
4263 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
4266 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
4269 Unsigned 8-bit integer constant (for @code{in} and @code{out}
4274 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
4278 Standard 80387 floating point constant.
4281 SSE constant zero operand.
4284 32-bit signed integer constant, or a symbolic reference known
4285 to fit that range (for immediate operands in sign-extending x86-64
4289 32-bit signed integer constant, or a symbolic reference known
4290 to fit that range (for sign-extending conversion operations that
4291 require non-@code{VOIDmode} immediate operands).
4294 32-bit unsigned integer constant, or a symbolic reference known
4295 to fit that range (for zero-extending conversion operations that
4296 require non-@code{VOIDmode} immediate operands).
4299 128-bit integer constant where both the high and low 64-bit word
4300 satisfy the @code{e} constraint.
4303 32-bit unsigned integer constant, or a symbolic reference known
4304 to fit that range (for immediate operands in zero-extending x86-64
4308 VSIB address operand.
4311 Address operand without segment register.
4315 @item Xstormy16---@file{config/stormy16/stormy16.h}
4330 Registers r0 through r7.
4333 Registers r0 and r1.
4339 Registers r8 and r9.
4342 A constant between 0 and 3 inclusive.
4345 A constant that has exactly one bit set.
4348 A constant that has exactly one bit clear.
4351 A constant between 0 and 255 inclusive.
4354 A constant between @minus{}255 and 0 inclusive.
4357 A constant between @minus{}3 and 0 inclusive.
4360 A constant between 1 and 4 inclusive.
4363 A constant between @minus{}4 and @minus{}1 inclusive.
4366 A memory reference that is a stack push.
4369 A memory reference that is a stack pop.
4372 A memory reference that refers to a constant address of known value.
4375 The register indicated by Rx (not implemented yet).
4378 A constant that is not between 2 and 15 inclusive.
4385 @item Xtensa---@file{config/xtensa/constraints.md}
4388 General-purpose 32-bit register
4391 One-bit boolean register
4394 MAC16 40-bit accumulator register
4397 Signed 12-bit integer constant, for use in MOVI instructions
4400 Signed 8-bit integer constant, for use in ADDI instructions
4403 Integer constant valid for BccI instructions
4406 Unsigned constant valid for BccUI instructions
4413 @node Disable Insn Alternatives
4414 @subsection Disable insn alternatives using the @code{enabled} attribute
4417 There are three insn attributes that may be used to selectively disable
4418 instruction alternatives:
4422 Says whether an alternative is available on the current subtarget.
4424 @item preferred_for_size
4425 Says whether an enabled alternative should be used in code that is
4428 @item preferred_for_speed
4429 Says whether an enabled alternative should be used in code that is
4430 optimized for speed.
4433 All these attributes should use @code{(const_int 1)} to allow an alternative
4434 or @code{(const_int 0)} to disallow it. The attributes must be a static
4435 property of the subtarget; they cannot for example depend on the
4436 current operands, on the current optimization level, on the location
4437 of the insn within the body of a loop, on whether register allocation
4438 has finished, or on the current compiler pass.
4440 The @code{enabled} attribute is a correctness property. It tells GCC to act
4441 as though the disabled alternatives were never defined in the first place.
4442 This is useful when adding new instructions to an existing pattern in
4443 cases where the new instructions are only available for certain cpu
4444 architecture levels (typically mapped to the @code{-march=} command-line
4447 In contrast, the @code{preferred_for_size} and @code{preferred_for_speed}
4448 attributes are strong optimization hints rather than correctness properties.
4449 @code{preferred_for_size} tells GCC which alternatives to consider when
4450 adding or modifying an instruction that GCC wants to optimize for size.
4451 @code{preferred_for_speed} does the same thing for speed. Note that things
4452 like code motion can lead to cases where code optimized for size uses
4453 alternatives that are not preferred for size, and similarly for speed.
4455 Although @code{define_insn}s can in principle specify the @code{enabled}
4456 attribute directly, it is often clearer to have subsiduary attributes
4457 for each architectural feature of interest. The @code{define_insn}s
4458 can then use these subsiduary attributes to say which alternatives
4459 require which features. The example below does this for @code{cpu_facility}.
4461 E.g. the following two patterns could easily be merged using the @code{enabled}
4466 (define_insn "*movdi_old"
4467 [(set (match_operand:DI 0 "register_operand" "=d")
4468 (match_operand:DI 1 "register_operand" " d"))]
4472 (define_insn "*movdi_new"
4473 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4474 (match_operand:DI 1 "register_operand" " d,d,f"))]
4487 (define_insn "*movdi_combined"
4488 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4489 (match_operand:DI 1 "register_operand" " d,d,f"))]
4495 [(set_attr "cpu_facility" "*,new,new")])
4499 with the @code{enabled} attribute defined like this:
4503 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4505 (define_attr "enabled" ""
4506 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4507 (and (eq_attr "cpu_facility" "new")
4508 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4517 @node Define Constraints
4518 @subsection Defining Machine-Specific Constraints
4519 @cindex defining constraints
4520 @cindex constraints, defining
4522 Machine-specific constraints fall into two categories: register and
4523 non-register constraints. Within the latter category, constraints
4524 which allow subsets of all possible memory or address operands should
4525 be specially marked, to give @code{reload} more information.
4527 Machine-specific constraints can be given names of arbitrary length,
4528 but they must be entirely composed of letters, digits, underscores
4529 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4530 must begin with a letter or underscore.
4532 In order to avoid ambiguity in operand constraint strings, no
4533 constraint can have a name that begins with any other constraint's
4534 name. For example, if @code{x} is defined as a constraint name,
4535 @code{xy} may not be, and vice versa. As a consequence of this rule,
4536 no constraint may begin with one of the generic constraint letters:
4537 @samp{E F V X g i m n o p r s}.
4539 Register constraints correspond directly to register classes.
4540 @xref{Register Classes}. There is thus not much flexibility in their
4543 @deffn {MD Expression} define_register_constraint name regclass docstring
4544 All three arguments are string constants.
4545 @var{name} is the name of the constraint, as it will appear in
4546 @code{match_operand} expressions. If @var{name} is a multi-letter
4547 constraint its length shall be the same for all constraints starting
4548 with the same letter. @var{regclass} can be either the
4549 name of the corresponding register class (@pxref{Register Classes}),
4550 or a C expression which evaluates to the appropriate register class.
4551 If it is an expression, it must have no side effects, and it cannot
4552 look at the operand. The usual use of expressions is to map some
4553 register constraints to @code{NO_REGS} when the register class
4554 is not available on a given subarchitecture.
4556 @var{docstring} is a sentence documenting the meaning of the
4557 constraint. Docstrings are explained further below.
4560 Non-register constraints are more like predicates: the constraint
4561 definition gives a boolean expression which indicates whether the
4564 @deffn {MD Expression} define_constraint name docstring exp
4565 The @var{name} and @var{docstring} arguments are the same as for
4566 @code{define_register_constraint}, but note that the docstring comes
4567 immediately after the name for these expressions. @var{exp} is an RTL
4568 expression, obeying the same rules as the RTL expressions in predicate
4569 definitions. @xref{Defining Predicates}, for details. If it
4570 evaluates true, the constraint matches; if it evaluates false, it
4571 doesn't. Constraint expressions should indicate which RTL codes they
4572 might match, just like predicate expressions.
4574 @code{match_test} C expressions have access to the
4575 following variables:
4579 The RTL object defining the operand.
4581 The machine mode of @var{op}.
4583 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4585 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4586 @code{const_double}.
4588 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4589 @code{const_double}.
4591 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4592 @code{const_double}.
4595 The @var{*val} variables should only be used once another piece of the
4596 expression has verified that @var{op} is the appropriate kind of RTL
4600 Most non-register constraints should be defined with
4601 @code{define_constraint}. The remaining two definition expressions
4602 are only appropriate for constraints that should be handled specially
4603 by @code{reload} if they fail to match.
4605 @deffn {MD Expression} define_memory_constraint name docstring exp
4606 Use this expression for constraints that match a subset of all memory
4607 operands: that is, @code{reload} can make them match by converting the
4608 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4609 base register (from the register class specified by
4610 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4612 For example, on the S/390, some instructions do not accept arbitrary
4613 memory references, but only those that do not make use of an index
4614 register. The constraint letter @samp{Q} is defined to represent a
4615 memory address of this type. If @samp{Q} is defined with
4616 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4617 memory operand, because @code{reload} knows it can simply copy the
4618 memory address into a base register if required. This is analogous to
4619 the way an @samp{o} constraint can handle any memory operand.
4621 The syntax and semantics are otherwise identical to
4622 @code{define_constraint}.
4625 @deffn {MD Expression} define_special_memory_constraint name docstring exp
4626 Use this expression for constraints that match a subset of all memory
4627 operands: that is, @code{reload} cannot make them match by reloading
4628 the address as it is described for @code{define_memory_constraint} or
4629 such address reload is undesirable with the performance point of view.
4631 For example, @code{define_special_memory_constraint} can be useful if
4632 specifically aligned memory is necessary or desirable for some insn
4635 The syntax and semantics are otherwise identical to
4636 @code{define_constraint}.
4639 @deffn {MD Expression} define_address_constraint name docstring exp
4640 Use this expression for constraints that match a subset of all address
4641 operands: that is, @code{reload} can make the constraint match by
4642 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4643 with @var{X} a base register.
4645 Constraints defined with @code{define_address_constraint} can only be
4646 used with the @code{address_operand} predicate, or machine-specific
4647 predicates that work the same way. They are treated analogously to
4648 the generic @samp{p} constraint.
4650 The syntax and semantics are otherwise identical to
4651 @code{define_constraint}.
4654 For historical reasons, names beginning with the letters @samp{G H}
4655 are reserved for constraints that match only @code{const_double}s, and
4656 names beginning with the letters @samp{I J K L M N O P} are reserved
4657 for constraints that match only @code{const_int}s. This may change in
4658 the future. For the time being, constraints with these names must be
4659 written in a stylized form, so that @code{genpreds} can tell you did
4664 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4666 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4667 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4670 @c the semicolons line up in the formatted manual
4672 It is fine to use names beginning with other letters for constraints
4673 that match @code{const_double}s or @code{const_int}s.
4675 Each docstring in a constraint definition should be one or more complete
4676 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4677 In the future they will be copied into the GCC manual, in @ref{Machine
4678 Constraints}, replacing the hand-maintained tables currently found in
4679 that section. Also, in the future the compiler may use this to give
4680 more helpful diagnostics when poor choice of @code{asm} constraints
4681 causes a reload failure.
4683 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4684 beginning of a docstring, then (in the future) it will appear only in
4685 the internals manual's version of the machine-specific constraint tables.
4686 Use this for constraints that should not appear in @code{asm} statements.
4688 @node C Constraint Interface
4689 @subsection Testing constraints from C
4690 @cindex testing constraints
4691 @cindex constraints, testing
4693 It is occasionally useful to test a constraint from C code rather than
4694 implicitly via the constraint string in a @code{match_operand}. The
4695 generated file @file{tm_p.h} declares a few interfaces for working
4696 with constraints. At present these are defined for all constraints
4697 except @code{g} (which is equivalent to @code{general_operand}).
4699 Some valid constraint names are not valid C identifiers, so there is a
4700 mangling scheme for referring to them from C@. Constraint names that
4701 do not contain angle brackets or underscores are left unchanged.
4702 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4703 each @samp{>} with @samp{_g}. Here are some examples:
4705 @c the @c's prevent double blank lines in the printed manual.
4707 @multitable {Original} {Mangled}
4708 @item @strong{Original} @tab @strong{Mangled} @c
4709 @item @code{x} @tab @code{x} @c
4710 @item @code{P42x} @tab @code{P42x} @c
4711 @item @code{P4_x} @tab @code{P4__x} @c
4712 @item @code{P4>x} @tab @code{P4_gx} @c
4713 @item @code{P4>>} @tab @code{P4_g_g} @c
4714 @item @code{P4_g>} @tab @code{P4__g_g} @c
4718 Throughout this section, the variable @var{c} is either a constraint
4719 in the abstract sense, or a constant from @code{enum constraint_num};
4720 the variable @var{m} is a mangled constraint name (usually as part of
4721 a larger identifier).
4723 @deftp Enum constraint_num
4724 For each constraint except @code{g}, there is a corresponding
4725 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4726 constraint. Functions that take an @code{enum constraint_num} as an
4727 argument expect one of these constants.
4730 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4731 For each non-register constraint @var{m} except @code{g}, there is
4732 one of these functions; it returns @code{true} if @var{exp} satisfies the
4733 constraint. These functions are only visible if @file{rtl.h} was included
4734 before @file{tm_p.h}.
4737 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4738 Like the @code{satisfies_constraint_@var{m}} functions, but the
4739 constraint to test is given as an argument, @var{c}. If @var{c}
4740 specifies a register constraint, this function will always return
4744 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4745 Returns the register class associated with @var{c}. If @var{c} is not
4746 a register constraint, or those registers are not available for the
4747 currently selected subtarget, returns @code{NO_REGS}.
4750 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4751 peephole optimizations (@pxref{Peephole Definitions}), operand
4752 constraint strings are ignored, so if there are relevant constraints,
4753 they must be tested in the C condition. In the example, the
4754 optimization is applied if operand 2 does @emph{not} satisfy the
4755 @samp{K} constraint. (This is a simplified version of a peephole
4756 definition from the i386 machine description.)
4760 [(match_scratch:SI 3 "r")
4761 (set (match_operand:SI 0 "register_operand" "")
4762 (mult:SI (match_operand:SI 1 "memory_operand" "")
4763 (match_operand:SI 2 "immediate_operand" "")))]
4765 "!satisfies_constraint_K (operands[2])"
4767 [(set (match_dup 3) (match_dup 1))
4768 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4773 @node Standard Names
4774 @section Standard Pattern Names For Generation
4775 @cindex standard pattern names
4776 @cindex pattern names
4777 @cindex names, pattern
4779 Here is a table of the instruction names that are meaningful in the RTL
4780 generation pass of the compiler. Giving one of these names to an
4781 instruction pattern tells the RTL generation pass that it can use the
4782 pattern to accomplish a certain task.
4785 @cindex @code{mov@var{m}} instruction pattern
4786 @item @samp{mov@var{m}}
4787 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4788 This instruction pattern moves data with that machine mode from operand
4789 1 to operand 0. For example, @samp{movsi} moves full-word data.
4791 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4792 own mode is wider than @var{m}, the effect of this instruction is
4793 to store the specified value in the part of the register that corresponds
4794 to mode @var{m}. Bits outside of @var{m}, but which are within the
4795 same target word as the @code{subreg} are undefined. Bits which are
4796 outside the target word are left unchanged.
4798 This class of patterns is special in several ways. First of all, each
4799 of these names up to and including full word size @emph{must} be defined,
4800 because there is no other way to copy a datum from one place to another.
4801 If there are patterns accepting operands in larger modes,
4802 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4804 Second, these patterns are not used solely in the RTL generation pass.
4805 Even the reload pass can generate move insns to copy values from stack
4806 slots into temporary registers. When it does so, one of the operands is
4807 a hard register and the other is an operand that can need to be reloaded
4811 Therefore, when given such a pair of operands, the pattern must generate
4812 RTL which needs no reloading and needs no temporary registers---no
4813 registers other than the operands. For example, if you support the
4814 pattern with a @code{define_expand}, then in such a case the
4815 @code{define_expand} mustn't call @code{force_reg} or any other such
4816 function which might generate new pseudo registers.
4818 This requirement exists even for subword modes on a RISC machine where
4819 fetching those modes from memory normally requires several insns and
4820 some temporary registers.
4822 @findex change_address
4823 During reload a memory reference with an invalid address may be passed
4824 as an operand. Such an address will be replaced with a valid address
4825 later in the reload pass. In this case, nothing may be done with the
4826 address except to use it as it stands. If it is copied, it will not be
4827 replaced with a valid address. No attempt should be made to make such
4828 an address into a valid address and no routine (such as
4829 @code{change_address}) that will do so may be called. Note that
4830 @code{general_operand} will fail when applied to such an address.
4832 @findex reload_in_progress
4833 The global variable @code{reload_in_progress} (which must be explicitly
4834 declared if required) can be used to determine whether such special
4835 handling is required.
4837 The variety of operands that have reloads depends on the rest of the
4838 machine description, but typically on a RISC machine these can only be
4839 pseudo registers that did not get hard registers, while on other
4840 machines explicit memory references will get optional reloads.
4842 If a scratch register is required to move an object to or from memory,
4843 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4845 If there are cases which need scratch registers during or after reload,
4846 you must provide an appropriate secondary_reload target hook.
4848 @findex can_create_pseudo_p
4849 The macro @code{can_create_pseudo_p} can be used to determine if it
4850 is unsafe to create new pseudo registers. If this variable is nonzero, then
4851 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4853 The constraints on a @samp{mov@var{m}} must permit moving any hard
4854 register to any other hard register provided that
4855 @code{TARGET_HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4856 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4859 It is obligatory to support floating point @samp{mov@var{m}}
4860 instructions into and out of any registers that can hold fixed point
4861 values, because unions and structures (which have modes @code{SImode} or
4862 @code{DImode}) can be in those registers and they may have floating
4865 There may also be a need to support fixed point @samp{mov@var{m}}
4866 instructions in and out of floating point registers. Unfortunately, I
4867 have forgotten why this was so, and I don't know whether it is still
4868 true. If @code{TARGET_HARD_REGNO_MODE_OK} rejects fixed point values in
4869 floating point registers, then the constraints of the fixed point
4870 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4871 reload into a floating point register.
4873 @cindex @code{reload_in} instruction pattern
4874 @cindex @code{reload_out} instruction pattern
4875 @item @samp{reload_in@var{m}}
4876 @itemx @samp{reload_out@var{m}}
4877 These named patterns have been obsoleted by the target hook
4878 @code{secondary_reload}.
4880 Like @samp{mov@var{m}}, but used when a scratch register is required to
4881 move between operand 0 and operand 1. Operand 2 describes the scratch
4882 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4883 macro in @pxref{Register Classes}.
4885 There are special restrictions on the form of the @code{match_operand}s
4886 used in these patterns. First, only the predicate for the reload
4887 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4888 the predicates for operand 0 or 2. Second, there may be only one
4889 alternative in the constraints. Third, only a single register class
4890 letter may be used for the constraint; subsequent constraint letters
4891 are ignored. As a special exception, an empty constraint string
4892 matches the @code{ALL_REGS} register class. This may relieve ports
4893 of the burden of defining an @code{ALL_REGS} constraint letter just
4896 @cindex @code{movstrict@var{m}} instruction pattern
4897 @item @samp{movstrict@var{m}}
4898 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4899 with mode @var{m} of a register whose natural mode is wider,
4900 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4901 any of the register except the part which belongs to mode @var{m}.
4903 @cindex @code{movmisalign@var{m}} instruction pattern
4904 @item @samp{movmisalign@var{m}}
4905 This variant of a move pattern is designed to load or store a value
4906 from a memory address that is not naturally aligned for its mode.
4907 For a store, the memory will be in operand 0; for a load, the memory
4908 will be in operand 1. The other operand is guaranteed not to be a
4909 memory, so that it's easy to tell whether this is a load or store.
4911 This pattern is used by the autovectorizer, and when expanding a
4912 @code{MISALIGNED_INDIRECT_REF} expression.
4914 @cindex @code{load_multiple} instruction pattern
4915 @item @samp{load_multiple}
4916 Load several consecutive memory locations into consecutive registers.
4917 Operand 0 is the first of the consecutive registers, operand 1
4918 is the first memory location, and operand 2 is a constant: the
4919 number of consecutive registers.
4921 Define this only if the target machine really has such an instruction;
4922 do not define this if the most efficient way of loading consecutive
4923 registers from memory is to do them one at a time.
4925 On some machines, there are restrictions as to which consecutive
4926 registers can be stored into memory, such as particular starting or
4927 ending register numbers or only a range of valid counts. For those
4928 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4929 and make the pattern fail if the restrictions are not met.
4931 Write the generated insn as a @code{parallel} with elements being a
4932 @code{set} of one register from the appropriate memory location (you may
4933 also need @code{use} or @code{clobber} elements). Use a
4934 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4935 @file{rs6000.md} for examples of the use of this insn pattern.
4937 @cindex @samp{store_multiple} instruction pattern
4938 @item @samp{store_multiple}
4939 Similar to @samp{load_multiple}, but store several consecutive registers
4940 into consecutive memory locations. Operand 0 is the first of the
4941 consecutive memory locations, operand 1 is the first register, and
4942 operand 2 is a constant: the number of consecutive registers.
4944 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4945 @item @samp{vec_load_lanes@var{m}@var{n}}
4946 Perform an interleaved load of several vectors from memory operand 1
4947 into register operand 0. Both operands have mode @var{m}. The register
4948 operand is viewed as holding consecutive vectors of mode @var{n},
4949 while the memory operand is a flat array that contains the same number
4950 of elements. The operation is equivalent to:
4953 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4954 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4955 for (i = 0; i < c; i++)
4956 operand0[i][j] = operand1[j * c + i];
4959 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4960 from memory into a register of mode @samp{TI}@. The register
4961 contains two consecutive vectors of mode @samp{V4HI}@.
4963 This pattern can only be used if:
4965 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4967 is true. GCC assumes that, if a target supports this kind of
4968 instruction for some mode @var{n}, it also supports unaligned
4969 loads for vectors of mode @var{n}.
4971 This pattern is not allowed to @code{FAIL}.
4973 @cindex @code{vec_mask_load_lanes@var{m}@var{n}} instruction pattern
4974 @item @samp{vec_mask_load_lanes@var{m}@var{n}}
4975 Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional
4976 mask operand (operand 2) that specifies which elements of the destination
4977 vectors should be loaded. Other elements of the destination
4978 vectors are set to zero. The operation is equivalent to:
4981 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4982 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4984 for (i = 0; i < c; i++)
4985 operand0[i][j] = operand1[j * c + i];
4987 for (i = 0; i < c; i++)
4991 This pattern is not allowed to @code{FAIL}.
4993 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4994 @item @samp{vec_store_lanes@var{m}@var{n}}
4995 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4996 and register operands reversed. That is, the instruction is
5000 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
5001 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
5002 for (i = 0; i < c; i++)
5003 operand0[j * c + i] = operand1[i][j];
5006 for a memory operand 0 and register operand 1.
5008 This pattern is not allowed to @code{FAIL}.
5010 @cindex @code{vec_mask_store_lanes@var{m}@var{n}} instruction pattern
5011 @item @samp{vec_mask_store_lanes@var{m}@var{n}}
5012 Like @samp{vec_store_lanes@var{m}@var{n}}, but takes an additional
5013 mask operand (operand 2) that specifies which elements of the source
5014 vectors should be stored. The operation is equivalent to:
5017 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
5018 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
5020 for (i = 0; i < c; i++)
5021 operand0[j * c + i] = operand1[i][j];
5024 This pattern is not allowed to @code{FAIL}.
5026 @cindex @code{gather_load@var{m}} instruction pattern
5027 @item @samp{gather_load@var{m}}
5028 Load several separate memory locations into a vector of mode @var{m}.
5029 Operand 1 is a scalar base address and operand 2 is a vector of
5030 offsets from that base. Operand 0 is a destination vector with the
5031 same number of elements as the offset. For each element index @var{i}:
5035 extend the offset element @var{i} to address width, using zero
5036 extension if operand 3 is 1 and sign extension if operand 3 is zero;
5038 multiply the extended offset by operand 4;
5040 add the result to the base; and
5042 load the value at that address into element @var{i} of operand 0.
5045 The value of operand 3 does not matter if the offsets are already
5048 @cindex @code{mask_gather_load@var{m}} instruction pattern
5049 @item @samp{mask_gather_load@var{m}}
5050 Like @samp{gather_load@var{m}}, but takes an extra mask operand as
5051 operand 5. Bit @var{i} of the mask is set if element @var{i}
5052 of the result should be loaded from memory and clear if element @var{i}
5053 of the result should be set to zero.
5055 @cindex @code{scatter_store@var{m}} instruction pattern
5056 @item @samp{scatter_store@var{m}}
5057 Store a vector of mode @var{m} into several distinct memory locations.
5058 Operand 0 is a scalar base address and operand 1 is a vector of offsets
5059 from that base. Operand 4 is the vector of values that should be stored,
5060 which has the same number of elements as the offset. For each element
5065 extend the offset element @var{i} to address width, using zero
5066 extension if operand 2 is 1 and sign extension if operand 2 is zero;
5068 multiply the extended offset by operand 3;
5070 add the result to the base; and
5072 store element @var{i} of operand 4 to that address.
5075 The value of operand 2 does not matter if the offsets are already
5078 @cindex @code{mask_scatter_store@var{m}} instruction pattern
5079 @item @samp{mask_scatter_store@var{m}}
5080 Like @samp{scatter_store@var{m}}, but takes an extra mask operand as
5081 operand 5. Bit @var{i} of the mask is set if element @var{i}
5082 of the result should be stored to memory.
5084 @cindex @code{vec_set@var{m}} instruction pattern
5085 @item @samp{vec_set@var{m}}
5086 Set given field in the vector value. Operand 0 is the vector to modify,
5087 operand 1 is new value of field and operand 2 specify the field index.
5089 @cindex @code{vec_extract@var{m}@var{n}} instruction pattern
5090 @item @samp{vec_extract@var{m}@var{n}}
5091 Extract given field from the vector value. Operand 1 is the vector, operand 2
5092 specify field index and operand 0 place to store value into. The
5093 @var{n} mode is the mode of the field or vector of fields that should be
5094 extracted, should be either element mode of the vector mode @var{m}, or
5095 a vector mode with the same element mode and smaller number of elements.
5096 If @var{n} is a vector mode, the index is counted in units of that mode.
5098 @cindex @code{vec_init@var{m}@var{n}} instruction pattern
5099 @item @samp{vec_init@var{m}@var{n}}
5100 Initialize the vector to given values. Operand 0 is the vector to initialize
5101 and operand 1 is parallel containing values for individual fields. The
5102 @var{n} mode is the mode of the elements, should be either element mode of
5103 the vector mode @var{m}, or a vector mode with the same element mode and
5104 smaller number of elements.
5106 @cindex @code{vec_duplicate@var{m}} instruction pattern
5107 @item @samp{vec_duplicate@var{m}}
5108 Initialize vector output operand 0 so that each element has the value given
5109 by scalar input operand 1. The vector has mode @var{m} and the scalar has
5110 the mode appropriate for one element of @var{m}.
5112 This pattern only handles duplicates of non-constant inputs. Constant
5113 vectors go through the @code{mov@var{m}} pattern instead.
5115 This pattern is not allowed to @code{FAIL}.
5117 @cindex @code{vec_series@var{m}} instruction pattern
5118 @item @samp{vec_series@var{m}}
5119 Initialize vector output operand 0 so that element @var{i} is equal to
5120 operand 1 plus @var{i} times operand 2. In other words, create a linear
5121 series whose base value is operand 1 and whose step is operand 2.
5123 The vector output has mode @var{m} and the scalar inputs have the mode
5124 appropriate for one element of @var{m}. This pattern is not used for
5125 floating-point vectors, in order to avoid having to specify the
5126 rounding behavior for @var{i} > 1.
5128 This pattern is not allowed to @code{FAIL}.
5130 @cindex @code{while_ult@var{m}@var{n}} instruction pattern
5131 @item @code{while_ult@var{m}@var{n}}
5132 Set operand 0 to a mask that is true while incrementing operand 1
5133 gives a value that is less than operand 2. Operand 0 has mode @var{n}
5134 and operands 1 and 2 are scalar integers of mode @var{m}.
5135 The operation is equivalent to:
5138 operand0[0] = operand1 < operand2;
5139 for (i = 1; i < GET_MODE_NUNITS (@var{n}); i++)
5140 operand0[i] = operand0[i - 1] && (operand1 + i < operand2);
5143 @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern
5144 @item @samp{vec_cmp@var{m}@var{n}}
5145 Output a vector comparison. Operand 0 of mode @var{n} is the destination for
5146 predicate in operand 1 which is a signed vector comparison with operands of
5147 mode @var{m} in operands 2 and 3. Predicate is computed by element-wise
5148 evaluation of the vector comparison with a truth value of all-ones and a false
5151 @cindex @code{vec_cmpu@var{m}@var{n}} instruction pattern
5152 @item @samp{vec_cmpu@var{m}@var{n}}
5153 Similar to @code{vec_cmp@var{m}@var{n}} but perform unsigned vector comparison.
5155 @cindex @code{vec_cmpeq@var{m}@var{n}} instruction pattern
5156 @item @samp{vec_cmpeq@var{m}@var{n}}
5157 Similar to @code{vec_cmp@var{m}@var{n}} but perform equality or non-equality
5158 vector comparison only. If @code{vec_cmp@var{m}@var{n}}
5159 or @code{vec_cmpu@var{m}@var{n}} instruction pattern is supported,
5160 it will be preferred over @code{vec_cmpeq@var{m}@var{n}}, so there is
5161 no need to define this instruction pattern if the others are supported.
5163 @cindex @code{vcond@var{m}@var{n}} instruction pattern
5164 @item @samp{vcond@var{m}@var{n}}
5165 Output a conditional vector move. Operand 0 is the destination to
5166 receive a combination of operand 1 and operand 2, which are of mode @var{m},
5167 dependent on the outcome of the predicate in operand 3 which is a signed
5168 vector comparison with operands of mode @var{n} in operands 4 and 5. The
5169 modes @var{m} and @var{n} should have the same size. Operand 0
5170 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
5171 where @var{msk} is computed by element-wise evaluation of the vector
5172 comparison with a truth value of all-ones and a false value of all-zeros.
5174 @cindex @code{vcondu@var{m}@var{n}} instruction pattern
5175 @item @samp{vcondu@var{m}@var{n}}
5176 Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector
5179 @cindex @code{vcondeq@var{m}@var{n}} instruction pattern
5180 @item @samp{vcondeq@var{m}@var{n}}
5181 Similar to @code{vcond@var{m}@var{n}} but performs equality or
5182 non-equality vector comparison only. If @code{vcond@var{m}@var{n}}
5183 or @code{vcondu@var{m}@var{n}} instruction pattern is supported,
5184 it will be preferred over @code{vcondeq@var{m}@var{n}}, so there is
5185 no need to define this instruction pattern if the others are supported.
5187 @cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern
5188 @item @samp{vcond_mask_@var{m}@var{n}}
5189 Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed
5190 result of vector comparison.
5192 @cindex @code{maskload@var{m}@var{n}} instruction pattern
5193 @item @samp{maskload@var{m}@var{n}}
5194 Perform a masked load of vector from memory operand 1 of mode @var{m}
5195 into register operand 0. Mask is provided in register operand 2 of
5198 This pattern is not allowed to @code{FAIL}.
5200 @cindex @code{maskstore@var{m}@var{n}} instruction pattern
5201 @item @samp{maskstore@var{m}@var{n}}
5202 Perform a masked store of vector from register operand 1 of mode @var{m}
5203 into memory operand 0. Mask is provided in register operand 2 of
5206 This pattern is not allowed to @code{FAIL}.
5208 @cindex @code{vec_perm@var{m}} instruction pattern
5209 @item @samp{vec_perm@var{m}}
5210 Output a (variable) vector permutation. Operand 0 is the destination
5211 to receive elements from operand 1 and operand 2, which are of mode
5212 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
5213 vector of the same width and number of elements as mode @var{m}.
5215 The input elements are numbered from 0 in operand 1 through
5216 @math{2*@var{N}-1} in operand 2. The elements of the selector must
5217 be computed modulo @math{2*@var{N}}. Note that if
5218 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
5219 with just operand 1 and selector elements modulo @var{N}.
5221 In order to make things easy for a number of targets, if there is no
5222 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
5223 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
5224 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
5227 See also @code{TARGET_VECTORIZER_VEC_PERM_CONST}, which performs
5228 the analogous operation for constant selectors.
5230 @cindex @code{push@var{m}1} instruction pattern
5231 @item @samp{push@var{m}1}
5232 Output a push instruction. Operand 0 is value to push. Used only when
5233 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
5234 missing and in such case an @code{mov} expander is used instead, with a
5235 @code{MEM} expression forming the push operation. The @code{mov} expander
5236 method is deprecated.
5238 @cindex @code{add@var{m}3} instruction pattern
5239 @item @samp{add@var{m}3}
5240 Add operand 2 and operand 1, storing the result in operand 0. All operands
5241 must have mode @var{m}. This can be used even on two-address machines, by
5242 means of constraints requiring operands 1 and 0 to be the same location.
5244 @cindex @code{ssadd@var{m}3} instruction pattern
5245 @cindex @code{usadd@var{m}3} instruction pattern
5246 @cindex @code{sub@var{m}3} instruction pattern
5247 @cindex @code{sssub@var{m}3} instruction pattern
5248 @cindex @code{ussub@var{m}3} instruction pattern
5249 @cindex @code{mul@var{m}3} instruction pattern
5250 @cindex @code{ssmul@var{m}3} instruction pattern
5251 @cindex @code{usmul@var{m}3} instruction pattern
5252 @cindex @code{div@var{m}3} instruction pattern
5253 @cindex @code{ssdiv@var{m}3} instruction pattern
5254 @cindex @code{udiv@var{m}3} instruction pattern
5255 @cindex @code{usdiv@var{m}3} instruction pattern
5256 @cindex @code{mod@var{m}3} instruction pattern
5257 @cindex @code{umod@var{m}3} instruction pattern
5258 @cindex @code{umin@var{m}3} instruction pattern
5259 @cindex @code{umax@var{m}3} instruction pattern
5260 @cindex @code{and@var{m}3} instruction pattern
5261 @cindex @code{ior@var{m}3} instruction pattern
5262 @cindex @code{xor@var{m}3} instruction pattern
5263 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
5264 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
5265 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
5266 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
5267 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
5268 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
5269 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
5270 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
5271 Similar, for other arithmetic operations.
5273 @cindex @code{addv@var{m}4} instruction pattern
5274 @item @samp{addv@var{m}4}
5275 Like @code{add@var{m}3} but takes a @code{code_label} as operand 3 and
5276 emits code to jump to it if signed overflow occurs during the addition.
5277 This pattern is used to implement the built-in functions performing
5278 signed integer addition with overflow checking.
5280 @cindex @code{subv@var{m}4} instruction pattern
5281 @cindex @code{mulv@var{m}4} instruction pattern
5282 @item @samp{subv@var{m}4}, @samp{mulv@var{m}4}
5283 Similar, for other signed arithmetic operations.
5285 @cindex @code{uaddv@var{m}4} instruction pattern
5286 @item @samp{uaddv@var{m}4}
5287 Like @code{addv@var{m}4} but for unsigned addition. That is to
5288 say, the operation is the same as signed addition but the jump
5289 is taken only on unsigned overflow.
5291 @cindex @code{usubv@var{m}4} instruction pattern
5292 @cindex @code{umulv@var{m}4} instruction pattern
5293 @item @samp{usubv@var{m}4}, @samp{umulv@var{m}4}
5294 Similar, for other unsigned arithmetic operations.
5296 @cindex @code{addptr@var{m}3} instruction pattern
5297 @item @samp{addptr@var{m}3}
5298 Like @code{add@var{m}3} but is guaranteed to only be used for address
5299 calculations. The expanded code is not allowed to clobber the
5300 condition code. It only needs to be defined if @code{add@var{m}3}
5301 sets the condition code. If adds used for address calculations and
5302 normal adds are not compatible it is required to expand a distinct
5303 pattern (e.g.@: using an unspec). The pattern is used by LRA to emit
5304 address calculations. @code{add@var{m}3} is used if
5305 @code{addptr@var{m}3} is not defined.
5307 @cindex @code{fma@var{m}4} instruction pattern
5308 @item @samp{fma@var{m}4}
5309 Multiply operand 2 and operand 1, then add operand 3, storing the
5310 result in operand 0 without doing an intermediate rounding step. All
5311 operands must have mode @var{m}. This pattern is used to implement
5312 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
5313 the ISO C99 standard.
5315 @cindex @code{fms@var{m}4} instruction pattern
5316 @item @samp{fms@var{m}4}
5317 Like @code{fma@var{m}4}, except operand 3 subtracted from the
5318 product instead of added to the product. This is represented
5322 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
5325 @cindex @code{fnma@var{m}4} instruction pattern
5326 @item @samp{fnma@var{m}4}
5327 Like @code{fma@var{m}4} except that the intermediate product
5328 is negated before being added to operand 3. This is represented
5332 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
5335 @cindex @code{fnms@var{m}4} instruction pattern
5336 @item @samp{fnms@var{m}4}
5337 Like @code{fms@var{m}4} except that the intermediate product
5338 is negated before subtracting operand 3. This is represented
5342 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
5345 @cindex @code{min@var{m}3} instruction pattern
5346 @cindex @code{max@var{m}3} instruction pattern
5347 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
5348 Signed minimum and maximum operations. When used with floating point,
5349 if both operands are zeros, or if either operand is @code{NaN}, then
5350 it is unspecified which of the two operands is returned as the result.
5352 @cindex @code{fmin@var{m}3} instruction pattern
5353 @cindex @code{fmax@var{m}3} instruction pattern
5354 @item @samp{fmin@var{m}3}, @samp{fmax@var{m}3}
5355 IEEE-conformant minimum and maximum operations. If one operand is a quiet
5356 @code{NaN}, then the other operand is returned. If both operands are quiet
5357 @code{NaN}, then a quiet @code{NaN} is returned. In the case when gcc supports
5358 signaling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
5359 raised and a quiet @code{NaN} is returned.
5361 All operands have mode @var{m}, which is a scalar or vector
5362 floating-point mode. These patterns are not allowed to @code{FAIL}.
5364 @cindex @code{reduc_smin_scal_@var{m}} instruction pattern
5365 @cindex @code{reduc_smax_scal_@var{m}} instruction pattern
5366 @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}}
5367 Find the signed minimum/maximum of the elements of a vector. The vector is
5368 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5369 the elements of the input vector.
5371 @cindex @code{reduc_umin_scal_@var{m}} instruction pattern
5372 @cindex @code{reduc_umax_scal_@var{m}} instruction pattern
5373 @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}}
5374 Find the unsigned minimum/maximum of the elements of a vector. The vector is
5375 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5376 the elements of the input vector.
5378 @cindex @code{reduc_plus_scal_@var{m}} instruction pattern
5379 @item @samp{reduc_plus_scal_@var{m}}
5380 Compute the sum of the elements of a vector. The vector is operand 1, and
5381 operand 0 is the scalar result, with mode equal to the mode of the elements of
5384 @cindex @code{reduc_and_scal_@var{m}} instruction pattern
5385 @item @samp{reduc_and_scal_@var{m}}
5386 @cindex @code{reduc_ior_scal_@var{m}} instruction pattern
5387 @itemx @samp{reduc_ior_scal_@var{m}}
5388 @cindex @code{reduc_xor_scal_@var{m}} instruction pattern
5389 @itemx @samp{reduc_xor_scal_@var{m}}
5390 Compute the bitwise @code{AND}/@code{IOR}/@code{XOR} reduction of the elements
5391 of a vector of mode @var{m}. Operand 1 is the vector input and operand 0
5392 is the scalar result. The mode of the scalar result is the same as one
5395 @cindex @code{extract_last_@var{m}} instruction pattern
5396 @item @code{extract_last_@var{m}}
5397 Find the last set bit in mask operand 1 and extract the associated element
5398 of vector operand 2. Store the result in scalar operand 0. Operand 2
5399 has vector mode @var{m} while operand 0 has the mode appropriate for one
5400 element of @var{m}. Operand 1 has the usual mask mode for vectors of mode
5401 @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5403 @cindex @code{fold_extract_last_@var{m}} instruction pattern
5404 @item @code{fold_extract_last_@var{m}}
5405 If any bits of mask operand 2 are set, find the last set bit, extract
5406 the associated element from vector operand 3, and store the result
5407 in operand 0. Store operand 1 in operand 0 otherwise. Operand 3
5408 has mode @var{m} and operands 0 and 1 have the mode appropriate for
5409 one element of @var{m}. Operand 2 has the usual mask mode for vectors
5410 of mode @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5412 @cindex @code{fold_left_plus_@var{m}} instruction pattern
5413 @item @code{fold_left_plus_@var{m}}
5414 Take scalar operand 1 and successively add each element from vector
5415 operand 2. Store the result in scalar operand 0. The vector has
5416 mode @var{m} and the scalars have the mode appropriate for one
5417 element of @var{m}. The operation is strictly in-order: there is
5420 @cindex @code{mask_fold_left_plus_@var{m}} instruction pattern
5421 @item @code{mask_fold_left_plus_@var{m}}
5422 Like @samp{fold_left_plus_@var{m}}, but takes an additional mask operand
5423 (operand 3) that specifies which elements of the source vector should be added.
5425 @cindex @code{sdot_prod@var{m}} instruction pattern
5426 @item @samp{sdot_prod@var{m}}
5427 @cindex @code{udot_prod@var{m}} instruction pattern
5428 @itemx @samp{udot_prod@var{m}}
5429 Compute the sum of the products of two signed/unsigned elements.
5430 Operand 1 and operand 2 are of the same mode. Their product, which is of a
5431 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
5432 wider than the mode of the product. The result is placed in operand 0, which
5433 is of the same mode as operand 3.
5435 @cindex @code{ssad@var{m}} instruction pattern
5436 @item @samp{ssad@var{m}}
5437 @cindex @code{usad@var{m}} instruction pattern
5438 @item @samp{usad@var{m}}
5439 Compute the sum of absolute differences of two signed/unsigned elements.
5440 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
5441 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
5442 equal or wider than the mode of the absolute difference. The result is placed
5443 in operand 0, which is of the same mode as operand 3.
5445 @cindex @code{widen_ssum@var{m3}} instruction pattern
5446 @item @samp{widen_ssum@var{m3}}
5447 @cindex @code{widen_usum@var{m3}} instruction pattern
5448 @itemx @samp{widen_usum@var{m3}}
5449 Operands 0 and 2 are of the same mode, which is wider than the mode of
5450 operand 1. Add operand 1 to operand 2 and place the widened result in
5451 operand 0. (This is used express accumulation of elements into an accumulator
5454 @cindex @code{vec_shl_insert_@var{m}} instruction pattern
5455 @item @samp{vec_shl_insert_@var{m}}
5456 Shift the elements in vector input operand 1 left one element (i.e.@:
5457 away from element 0) and fill the vacated element 0 with the scalar
5458 in operand 2. Store the result in vector output operand 0. Operands
5459 0 and 1 have mode @var{m} and operand 2 has the mode appropriate for
5460 one element of @var{m}.
5462 @cindex @code{vec_shl_@var{m}} instruction pattern
5463 @item @samp{vec_shl_@var{m}}
5464 Whole vector left shift in bits, i.e.@: away from element 0.
5465 Operand 1 is a vector to be shifted.
5466 Operand 2 is an integer shift amount in bits.
5467 Operand 0 is where the resulting shifted vector is stored.
5468 The output and input vectors should have the same modes.
5470 @cindex @code{vec_shr_@var{m}} instruction pattern
5471 @item @samp{vec_shr_@var{m}}
5472 Whole vector right shift in bits, i.e.@: towards element 0.
5473 Operand 1 is a vector to be shifted.
5474 Operand 2 is an integer shift amount in bits.
5475 Operand 0 is where the resulting shifted vector is stored.
5476 The output and input vectors should have the same modes.
5478 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
5479 @item @samp{vec_pack_trunc_@var{m}}
5480 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5481 are vectors of the same mode having N integral or floating point elements
5482 of size S@. Operand 0 is the resulting vector in which 2*N elements of
5483 size N/2 are concatenated after narrowing them down using truncation.
5485 @cindex @code{vec_pack_sbool_trunc_@var{m}} instruction pattern
5486 @item @samp{vec_pack_sbool_trunc_@var{m}}
5487 Narrow and merge the elements of two vectors. Operands 1 and 2 are vectors
5488 of the same type having N boolean elements. Operand 0 is the resulting
5489 vector in which 2*N elements are concatenated. The last operand (operand 3)
5490 is the number of elements in the output vector 2*N as a @code{CONST_INT}.
5491 This instruction pattern is used when all the vector input and output
5492 operands have the same scalar mode @var{m} and thus using
5493 @code{vec_pack_trunc_@var{m}} would be ambiguous.
5495 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
5496 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
5497 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
5498 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5499 are vectors of the same mode having N integral elements of size S.
5500 Operand 0 is the resulting vector in which the elements of the two input
5501 vectors are concatenated after narrowing them down using signed/unsigned
5502 saturating arithmetic.
5504 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
5505 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
5506 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
5507 Narrow, convert to signed/unsigned integral type and merge the elements
5508 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5509 floating point elements of size S@. Operand 0 is the resulting vector
5510 in which 2*N elements of size N/2 are concatenated.
5512 @cindex @code{vec_packs_float_@var{m}} instruction pattern
5513 @cindex @code{vec_packu_float_@var{m}} instruction pattern
5514 @item @samp{vec_packs_float_@var{m}}, @samp{vec_packu_float_@var{m}}
5515 Narrow, convert to floating point type and merge the elements
5516 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5517 signed/unsigned integral elements of size S@. Operand 0 is the resulting vector
5518 in which 2*N elements of size N/2 are concatenated.
5520 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
5521 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
5522 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
5523 Extract and widen (promote) the high/low part of a vector of signed
5524 integral or floating point elements. The input vector (operand 1) has N
5525 elements of size S@. Widen (promote) the high/low elements of the vector
5526 using signed or floating point extension and place the resulting N/2
5527 values of size 2*S in the output vector (operand 0).
5529 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
5530 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
5531 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
5532 Extract and widen (promote) the high/low part of a vector of unsigned
5533 integral elements. The input vector (operand 1) has N elements of size S.
5534 Widen (promote) the high/low elements of the vector using zero extension and
5535 place the resulting N/2 values of size 2*S in the output vector (operand 0).
5537 @cindex @code{vec_unpacks_sbool_hi_@var{m}} instruction pattern
5538 @cindex @code{vec_unpacks_sbool_lo_@var{m}} instruction pattern
5539 @item @samp{vec_unpacks_sbool_hi_@var{m}}, @samp{vec_unpacks_sbool_lo_@var{m}}
5540 Extract the high/low part of a vector of boolean elements that have scalar
5541 mode @var{m}. The input vector (operand 1) has N elements, the output
5542 vector (operand 0) has N/2 elements. The last operand (operand 2) is the
5543 number of elements of the input vector N as a @code{CONST_INT}. These
5544 patterns are used if both the input and output vectors have the same scalar
5545 mode @var{m} and thus using @code{vec_unpacks_hi_@var{m}} or
5546 @code{vec_unpacks_lo_@var{m}} would be ambiguous.
5548 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
5549 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
5550 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
5551 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
5552 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
5553 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
5554 Extract, convert to floating point type and widen the high/low part of a
5555 vector of signed/unsigned integral elements. The input vector (operand 1)
5556 has N elements of size S@. Convert the high/low elements of the vector using
5557 floating point conversion and place the resulting N/2 values of size 2*S in
5558 the output vector (operand 0).
5560 @cindex @code{vec_unpack_sfix_trunc_hi_@var{m}} instruction pattern
5561 @cindex @code{vec_unpack_sfix_trunc_lo_@var{m}} instruction pattern
5562 @cindex @code{vec_unpack_ufix_trunc_hi_@var{m}} instruction pattern
5563 @cindex @code{vec_unpack_ufix_trunc_lo_@var{m}} instruction pattern
5564 @item @samp{vec_unpack_sfix_trunc_hi_@var{m}},
5565 @itemx @samp{vec_unpack_sfix_trunc_lo_@var{m}}
5566 @itemx @samp{vec_unpack_ufix_trunc_hi_@var{m}}
5567 @itemx @samp{vec_unpack_ufix_trunc_lo_@var{m}}
5568 Extract, convert to signed/unsigned integer type and widen the high/low part of a
5569 vector of floating point elements. The input vector (operand 1)
5570 has N elements of size S@. Convert the high/low elements of the vector
5571 to integers and place the resulting N/2 values of size 2*S in
5572 the output vector (operand 0).
5574 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
5575 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
5576 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
5577 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
5578 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
5579 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
5580 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
5581 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
5582 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
5583 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
5584 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
5585 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
5586 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
5587 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
5588 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
5589 in the output vector (operand 0). A target shouldn't implement even/odd pattern
5590 pair if it is less efficient than lo/hi one.
5592 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
5593 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
5594 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
5595 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
5596 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
5597 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
5598 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
5599 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
5600 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
5601 output vector (operand 0).
5603 @cindex @code{mulhisi3} instruction pattern
5604 @item @samp{mulhisi3}
5605 Multiply operands 1 and 2, which have mode @code{HImode}, and store
5606 a @code{SImode} product in operand 0.
5608 @cindex @code{mulqihi3} instruction pattern
5609 @cindex @code{mulsidi3} instruction pattern
5610 @item @samp{mulqihi3}, @samp{mulsidi3}
5611 Similar widening-multiplication instructions of other widths.
5613 @cindex @code{umulqihi3} instruction pattern
5614 @cindex @code{umulhisi3} instruction pattern
5615 @cindex @code{umulsidi3} instruction pattern
5616 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
5617 Similar widening-multiplication instructions that do unsigned
5620 @cindex @code{usmulqihi3} instruction pattern
5621 @cindex @code{usmulhisi3} instruction pattern
5622 @cindex @code{usmulsidi3} instruction pattern
5623 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
5624 Similar widening-multiplication instructions that interpret the first
5625 operand as unsigned and the second operand as signed, then do a signed
5628 @cindex @code{smul@var{m}3_highpart} instruction pattern
5629 @item @samp{smul@var{m}3_highpart}
5630 Perform a signed multiplication of operands 1 and 2, which have mode
5631 @var{m}, and store the most significant half of the product in operand 0.
5632 The least significant half of the product is discarded.
5634 @cindex @code{umul@var{m}3_highpart} instruction pattern
5635 @item @samp{umul@var{m}3_highpart}
5636 Similar, but the multiplication is unsigned.
5638 @cindex @code{madd@var{m}@var{n}4} instruction pattern
5639 @item @samp{madd@var{m}@var{n}4}
5640 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
5641 operand 3, and store the result in operand 0. Operands 1 and 2
5642 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5643 Both modes must be integer or fixed-point modes and @var{n} must be twice
5644 the size of @var{m}.
5646 In other words, @code{madd@var{m}@var{n}4} is like
5647 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
5649 These instructions are not allowed to @code{FAIL}.
5651 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
5652 @item @samp{umadd@var{m}@var{n}4}
5653 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5654 operands instead of sign-extending them.
5656 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5657 @item @samp{ssmadd@var{m}@var{n}4}
5658 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5661 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5662 @item @samp{usmadd@var{m}@var{n}4}
5663 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5664 unsigned-saturating.
5666 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5667 @item @samp{msub@var{m}@var{n}4}
5668 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5669 result from operand 3, and store the result in operand 0. Operands 1 and 2
5670 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5671 Both modes must be integer or fixed-point modes and @var{n} must be twice
5672 the size of @var{m}.
5674 In other words, @code{msub@var{m}@var{n}4} is like
5675 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5678 These instructions are not allowed to @code{FAIL}.
5680 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5681 @item @samp{umsub@var{m}@var{n}4}
5682 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5683 operands instead of sign-extending them.
5685 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5686 @item @samp{ssmsub@var{m}@var{n}4}
5687 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5690 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5691 @item @samp{usmsub@var{m}@var{n}4}
5692 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5693 unsigned-saturating.
5695 @cindex @code{divmod@var{m}4} instruction pattern
5696 @item @samp{divmod@var{m}4}
5697 Signed division that produces both a quotient and a remainder.
5698 Operand 1 is divided by operand 2 to produce a quotient stored
5699 in operand 0 and a remainder stored in operand 3.
5701 For machines with an instruction that produces both a quotient and a
5702 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5703 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5704 allows optimization in the relatively common case when both the quotient
5705 and remainder are computed.
5707 If an instruction that just produces a quotient or just a remainder
5708 exists and is more efficient than the instruction that produces both,
5709 write the output routine of @samp{divmod@var{m}4} to call
5710 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5711 quotient or remainder and generate the appropriate instruction.
5713 @cindex @code{udivmod@var{m}4} instruction pattern
5714 @item @samp{udivmod@var{m}4}
5715 Similar, but does unsigned division.
5717 @anchor{shift patterns}
5718 @cindex @code{ashl@var{m}3} instruction pattern
5719 @cindex @code{ssashl@var{m}3} instruction pattern
5720 @cindex @code{usashl@var{m}3} instruction pattern
5721 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5722 Arithmetic-shift operand 1 left by a number of bits specified by operand
5723 2, and store the result in operand 0. Here @var{m} is the mode of
5724 operand 0 and operand 1; operand 2's mode is specified by the
5725 instruction pattern, and the compiler will convert the operand to that
5726 mode before generating the instruction. The shift or rotate expander
5727 or instruction pattern should explicitly specify the mode of the operand 2,
5728 it should never be @code{VOIDmode}. The meaning of out-of-range shift
5729 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5730 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5732 @cindex @code{ashr@var{m}3} instruction pattern
5733 @cindex @code{lshr@var{m}3} instruction pattern
5734 @cindex @code{rotl@var{m}3} instruction pattern
5735 @cindex @code{rotr@var{m}3} instruction pattern
5736 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5737 Other shift and rotate instructions, analogous to the
5738 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5740 @cindex @code{vashl@var{m}3} instruction pattern
5741 @cindex @code{vashr@var{m}3} instruction pattern
5742 @cindex @code{vlshr@var{m}3} instruction pattern
5743 @cindex @code{vrotl@var{m}3} instruction pattern
5744 @cindex @code{vrotr@var{m}3} instruction pattern
5745 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5746 Vector shift and rotate instructions that take vectors as operand 2
5747 instead of a scalar type.
5749 @cindex @code{avg@var{m}3_floor} instruction pattern
5750 @cindex @code{uavg@var{m}3_floor} instruction pattern
5751 @item @samp{avg@var{m}3_floor}
5752 @itemx @samp{uavg@var{m}3_floor}
5753 Signed and unsigned average instructions. These instructions add
5754 operands 1 and 2 without truncation, divide the result by 2,
5755 round towards -Inf, and store the result in operand 0. This is
5756 equivalent to the C code:
5758 narrow op0, op1, op2;
5760 op0 = (narrow) (((wide) op1 + (wide) op2) >> 1);
5762 where the sign of @samp{narrow} determines whether this is a signed
5763 or unsigned operation.
5765 @cindex @code{avg@var{m}3_ceil} instruction pattern
5766 @cindex @code{uavg@var{m}3_ceil} instruction pattern
5767 @item @samp{avg@var{m}3_ceil}
5768 @itemx @samp{uavg@var{m}3_ceil}
5769 Like @samp{avg@var{m}3_floor} and @samp{uavg@var{m}3_floor}, but round
5770 towards +Inf. This is equivalent to the C code:
5772 narrow op0, op1, op2;
5774 op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1);
5777 @cindex @code{bswap@var{m}2} instruction pattern
5778 @item @samp{bswap@var{m}2}
5779 Reverse the order of bytes of operand 1 and store the result in operand 0.
5781 @cindex @code{neg@var{m}2} instruction pattern
5782 @cindex @code{ssneg@var{m}2} instruction pattern
5783 @cindex @code{usneg@var{m}2} instruction pattern
5784 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5785 Negate operand 1 and store the result in operand 0.
5787 @cindex @code{negv@var{m}3} instruction pattern
5788 @item @samp{negv@var{m}3}
5789 Like @code{neg@var{m}2} but takes a @code{code_label} as operand 2 and
5790 emits code to jump to it if signed overflow occurs during the negation.
5792 @cindex @code{abs@var{m}2} instruction pattern
5793 @item @samp{abs@var{m}2}
5794 Store the absolute value of operand 1 into operand 0.
5796 @cindex @code{sqrt@var{m}2} instruction pattern
5797 @item @samp{sqrt@var{m}2}
5798 Store the square root of operand 1 into operand 0. Both operands have
5799 mode @var{m}, which is a scalar or vector floating-point mode.
5801 This pattern is not allowed to @code{FAIL}.
5803 @cindex @code{rsqrt@var{m}2} instruction pattern
5804 @item @samp{rsqrt@var{m}2}
5805 Store the reciprocal of the square root of operand 1 into operand 0.
5806 Both operands have mode @var{m}, which is a scalar or vector
5807 floating-point mode.
5809 On most architectures this pattern is only approximate, so either
5810 its C condition or the @code{TARGET_OPTAB_SUPPORTED_P} hook should
5811 check for the appropriate math flags. (Using the C condition is
5812 more direct, but using @code{TARGET_OPTAB_SUPPORTED_P} can be useful
5813 if a target-specific built-in also uses the @samp{rsqrt@var{m}2}
5816 This pattern is not allowed to @code{FAIL}.
5818 @cindex @code{fmod@var{m}3} instruction pattern
5819 @item @samp{fmod@var{m}3}
5820 Store the remainder of dividing operand 1 by operand 2 into
5821 operand 0, rounded towards zero to an integer. All operands have
5822 mode @var{m}, which is a scalar or vector floating-point mode.
5824 This pattern is not allowed to @code{FAIL}.
5826 @cindex @code{remainder@var{m}3} instruction pattern
5827 @item @samp{remainder@var{m}3}
5828 Store the remainder of dividing operand 1 by operand 2 into
5829 operand 0, rounded to the nearest integer. All operands have
5830 mode @var{m}, which is a scalar or vector floating-point mode.
5832 This pattern is not allowed to @code{FAIL}.
5834 @cindex @code{scalb@var{m}3} instruction pattern
5835 @item @samp{scalb@var{m}3}
5836 Raise @code{FLT_RADIX} to the power of operand 2, multiply it by
5837 operand 1, and store the result in operand 0. All operands have
5838 mode @var{m}, which is a scalar or vector floating-point mode.
5840 This pattern is not allowed to @code{FAIL}.
5842 @cindex @code{ldexp@var{m}3} instruction pattern
5843 @item @samp{ldexp@var{m}3}
5844 Raise 2 to the power of operand 2, multiply it by operand 1, and store
5845 the result in operand 0. Operands 0 and 1 have mode @var{m}, which is
5846 a scalar or vector floating-point mode. Operand 2's mode has
5847 the same number of elements as @var{m} and each element is wide
5848 enough to store an @code{int}. The integers are signed.
5850 This pattern is not allowed to @code{FAIL}.
5852 @cindex @code{cos@var{m}2} instruction pattern
5853 @item @samp{cos@var{m}2}
5854 Store the cosine of operand 1 into operand 0. Both operands have
5855 mode @var{m}, which is a scalar or vector floating-point mode.
5857 This pattern is not allowed to @code{FAIL}.
5859 @cindex @code{sin@var{m}2} instruction pattern
5860 @item @samp{sin@var{m}2}
5861 Store the sine of operand 1 into operand 0. Both operands have
5862 mode @var{m}, which is a scalar or vector floating-point mode.
5864 This pattern is not allowed to @code{FAIL}.
5866 @cindex @code{sincos@var{m}3} instruction pattern
5867 @item @samp{sincos@var{m}3}
5868 Store the cosine of operand 2 into operand 0 and the sine of
5869 operand 2 into operand 1. All operands have mode @var{m},
5870 which is a scalar or vector floating-point mode.
5872 Targets that can calculate the sine and cosine simultaneously can
5873 implement this pattern as opposed to implementing individual
5874 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5875 and @code{cos} built-in functions will then be expanded to the
5876 @code{sincos@var{m}3} pattern, with one of the output values
5879 @cindex @code{tan@var{m}2} instruction pattern
5880 @item @samp{tan@var{m}2}
5881 Store the tangent of operand 1 into operand 0. Both operands have
5882 mode @var{m}, which is a scalar or vector floating-point mode.
5884 This pattern is not allowed to @code{FAIL}.
5886 @cindex @code{asin@var{m}2} instruction pattern
5887 @item @samp{asin@var{m}2}
5888 Store the arc sine of operand 1 into operand 0. Both operands have
5889 mode @var{m}, which is a scalar or vector floating-point mode.
5891 This pattern is not allowed to @code{FAIL}.
5893 @cindex @code{acos@var{m}2} instruction pattern
5894 @item @samp{acos@var{m}2}
5895 Store the arc cosine of operand 1 into operand 0. Both operands have
5896 mode @var{m}, which is a scalar or vector floating-point mode.
5898 This pattern is not allowed to @code{FAIL}.
5900 @cindex @code{atan@var{m}2} instruction pattern
5901 @item @samp{atan@var{m}2}
5902 Store the arc tangent of operand 1 into operand 0. Both operands have
5903 mode @var{m}, which is a scalar or vector floating-point mode.
5905 This pattern is not allowed to @code{FAIL}.
5907 @cindex @code{exp@var{m}2} instruction pattern
5908 @item @samp{exp@var{m}2}
5909 Raise e (the base of natural logarithms) to the power of operand 1
5910 and store the result in operand 0. Both operands have mode @var{m},
5911 which is a scalar or vector floating-point mode.
5913 This pattern is not allowed to @code{FAIL}.
5915 @cindex @code{expm1@var{m}2} instruction pattern
5916 @item @samp{expm1@var{m}2}
5917 Raise e (the base of natural logarithms) to the power of operand 1,
5918 subtract 1, and store the result in operand 0. Both operands have
5919 mode @var{m}, which is a scalar or vector floating-point mode.
5921 For inputs close to zero, the pattern is expected to be more
5922 accurate than a separate @code{exp@var{m}2} and @code{sub@var{m}3}
5925 This pattern is not allowed to @code{FAIL}.
5927 @cindex @code{exp10@var{m}2} instruction pattern
5928 @item @samp{exp10@var{m}2}
5929 Raise 10 to the power of operand 1 and store the result in operand 0.
5930 Both operands have mode @var{m}, which is a scalar or vector
5931 floating-point mode.
5933 This pattern is not allowed to @code{FAIL}.
5935 @cindex @code{exp2@var{m}2} instruction pattern
5936 @item @samp{exp2@var{m}2}
5937 Raise 2 to the power of operand 1 and store the result in operand 0.
5938 Both operands have mode @var{m}, which is a scalar or vector
5939 floating-point mode.
5941 This pattern is not allowed to @code{FAIL}.
5943 @cindex @code{log@var{m}2} instruction pattern
5944 @item @samp{log@var{m}2}
5945 Store the natural logarithm of operand 1 into operand 0. Both operands
5946 have mode @var{m}, which is a scalar or vector floating-point mode.
5948 This pattern is not allowed to @code{FAIL}.
5950 @cindex @code{log1p@var{m}2} instruction pattern
5951 @item @samp{log1p@var{m}2}
5952 Add 1 to operand 1, compute the natural logarithm, and store
5953 the result in operand 0. Both operands have mode @var{m}, which is
5954 a scalar or vector floating-point mode.
5956 For inputs close to zero, the pattern is expected to be more
5957 accurate than a separate @code{add@var{m}3} and @code{log@var{m}2}
5960 This pattern is not allowed to @code{FAIL}.
5962 @cindex @code{log10@var{m}2} instruction pattern
5963 @item @samp{log10@var{m}2}
5964 Store the base-10 logarithm of operand 1 into operand 0. Both operands
5965 have mode @var{m}, which is a scalar or vector floating-point mode.
5967 This pattern is not allowed to @code{FAIL}.
5969 @cindex @code{log2@var{m}2} instruction pattern
5970 @item @samp{log2@var{m}2}
5971 Store the base-2 logarithm of operand 1 into operand 0. Both operands
5972 have mode @var{m}, which is a scalar or vector floating-point mode.
5974 This pattern is not allowed to @code{FAIL}.
5976 @cindex @code{logb@var{m}2} instruction pattern
5977 @item @samp{logb@var{m}2}
5978 Store the base-@code{FLT_RADIX} logarithm of operand 1 into operand 0.
5979 Both operands have mode @var{m}, which is a scalar or vector
5980 floating-point mode.
5982 This pattern is not allowed to @code{FAIL}.
5984 @cindex @code{significand@var{m}2} instruction pattern
5985 @item @samp{significand@var{m}2}
5986 Store the significand of floating-point operand 1 in operand 0.
5987 Both operands have mode @var{m}, which is a scalar or vector
5988 floating-point mode.
5990 This pattern is not allowed to @code{FAIL}.
5992 @cindex @code{pow@var{m}3} instruction pattern
5993 @item @samp{pow@var{m}3}
5994 Store the value of operand 1 raised to the exponent operand 2
5995 into operand 0. All operands have mode @var{m}, which is a scalar
5996 or vector floating-point mode.
5998 This pattern is not allowed to @code{FAIL}.
6000 @cindex @code{atan2@var{m}3} instruction pattern
6001 @item @samp{atan2@var{m}3}
6002 Store the arc tangent (inverse tangent) of operand 1 divided by
6003 operand 2 into operand 0, using the signs of both arguments to
6004 determine the quadrant of the result. All operands have mode
6005 @var{m}, which is a scalar or vector floating-point mode.
6007 This pattern is not allowed to @code{FAIL}.
6009 @cindex @code{floor@var{m}2} instruction pattern
6010 @item @samp{floor@var{m}2}
6011 Store the largest integral value not greater than operand 1 in operand 0.
6012 Both operands have mode @var{m}, which is a scalar or vector
6013 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
6014 effect, the ``inexact'' exception may be raised for noninteger
6015 operands; otherwise, it may not.
6017 This pattern is not allowed to @code{FAIL}.
6019 @cindex @code{btrunc@var{m}2} instruction pattern
6020 @item @samp{btrunc@var{m}2}
6021 Round operand 1 to an integer, towards zero, and store the result in
6022 operand 0. Both operands have mode @var{m}, which is a scalar or
6023 vector floating-point mode. If @option{-ffp-int-builtin-inexact} is
6024 in effect, the ``inexact'' exception may be raised for noninteger
6025 operands; otherwise, it may not.
6027 This pattern is not allowed to @code{FAIL}.
6029 @cindex @code{round@var{m}2} instruction pattern
6030 @item @samp{round@var{m}2}
6031 Round operand 1 to the nearest integer, rounding away from zero in the
6032 event of a tie, and store the result in operand 0. Both operands have
6033 mode @var{m}, which is a scalar or vector floating-point mode. If
6034 @option{-ffp-int-builtin-inexact} is in effect, the ``inexact''
6035 exception may be raised for noninteger operands; otherwise, it may
6038 This pattern is not allowed to @code{FAIL}.
6040 @cindex @code{ceil@var{m}2} instruction pattern
6041 @item @samp{ceil@var{m}2}
6042 Store the smallest integral value not less than operand 1 in operand 0.
6043 Both operands have mode @var{m}, which is a scalar or vector
6044 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
6045 effect, the ``inexact'' exception may be raised for noninteger
6046 operands; otherwise, it may not.
6048 This pattern is not allowed to @code{FAIL}.
6050 @cindex @code{nearbyint@var{m}2} instruction pattern
6051 @item @samp{nearbyint@var{m}2}
6052 Round operand 1 to an integer, using the current rounding mode, and
6053 store the result in operand 0. Do not raise an inexact condition when
6054 the result is different from the argument. Both operands have mode
6055 @var{m}, which is a scalar or vector floating-point mode.
6057 This pattern is not allowed to @code{FAIL}.
6059 @cindex @code{rint@var{m}2} instruction pattern
6060 @item @samp{rint@var{m}2}
6061 Round operand 1 to an integer, using the current rounding mode, and
6062 store the result in operand 0. Raise an inexact condition when
6063 the result is different from the argument. Both operands have mode
6064 @var{m}, which is a scalar or vector floating-point mode.
6066 This pattern is not allowed to @code{FAIL}.
6068 @cindex @code{lrint@var{m}@var{n}2}
6069 @item @samp{lrint@var{m}@var{n}2}
6070 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6071 point mode @var{n} as a signed number according to the current
6072 rounding mode and store in operand 0 (which has mode @var{n}).
6074 @cindex @code{lround@var{m}@var{n}2}
6075 @item @samp{lround@var{m}@var{n}2}
6076 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6077 point mode @var{n} as a signed number rounding to nearest and away
6078 from zero and store in operand 0 (which has mode @var{n}).
6080 @cindex @code{lfloor@var{m}@var{n}2}
6081 @item @samp{lfloor@var{m}@var{n}2}
6082 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6083 point mode @var{n} as a signed number rounding down and store in
6084 operand 0 (which has mode @var{n}).
6086 @cindex @code{lceil@var{m}@var{n}2}
6087 @item @samp{lceil@var{m}@var{n}2}
6088 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6089 point mode @var{n} as a signed number rounding up and store in
6090 operand 0 (which has mode @var{n}).
6092 @cindex @code{copysign@var{m}3} instruction pattern
6093 @item @samp{copysign@var{m}3}
6094 Store a value with the magnitude of operand 1 and the sign of operand
6095 2 into operand 0. All operands have mode @var{m}, which is a scalar or
6096 vector floating-point mode.
6098 This pattern is not allowed to @code{FAIL}.
6100 @cindex @code{xorsign@var{m}3} instruction pattern
6101 @item @samp{xorsign@var{m}3}
6102 Equivalent to @samp{op0 = op1 * copysign (1.0, op2)}: store a value with
6103 the magnitude of operand 1 and the sign of operand 2 into operand 0.
6104 All operands have mode @var{m}, which is a scalar or vector
6105 floating-point mode.
6107 This pattern is not allowed to @code{FAIL}.
6109 @cindex @code{ffs@var{m}2} instruction pattern
6110 @item @samp{ffs@var{m}2}
6111 Store into operand 0 one plus the index of the least significant 1-bit
6112 of operand 1. If operand 1 is zero, store zero.
6114 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6115 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6116 integer mode is suitable for the target. The compiler will insert
6117 conversion instructions as necessary (typically to convert the result
6118 to the same width as @code{int}). When @var{m} is a vector, both
6119 operands must have mode @var{m}.
6121 This pattern is not allowed to @code{FAIL}.
6123 @cindex @code{clrsb@var{m}2} instruction pattern
6124 @item @samp{clrsb@var{m}2}
6125 Count leading redundant sign bits.
6126 Store into operand 0 the number of redundant sign bits in operand 1, starting
6127 at the most significant bit position.
6128 A redundant sign bit is defined as any sign bit after the first. As such,
6129 this count will be one less than the count of leading sign bits.
6131 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6132 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6133 integer mode is suitable for the target. The compiler will insert
6134 conversion instructions as necessary (typically to convert the result
6135 to the same width as @code{int}). When @var{m} is a vector, both
6136 operands must have mode @var{m}.
6138 This pattern is not allowed to @code{FAIL}.
6140 @cindex @code{clz@var{m}2} instruction pattern
6141 @item @samp{clz@var{m}2}
6142 Store into operand 0 the number of leading 0-bits in operand 1, starting
6143 at the most significant bit position. If operand 1 is 0, the
6144 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
6145 the result is undefined or has a useful value.
6147 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6148 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6149 integer mode is suitable for the target. The compiler will insert
6150 conversion instructions as necessary (typically to convert the result
6151 to the same width as @code{int}). When @var{m} is a vector, both
6152 operands must have mode @var{m}.
6154 This pattern is not allowed to @code{FAIL}.
6156 @cindex @code{ctz@var{m}2} instruction pattern
6157 @item @samp{ctz@var{m}2}
6158 Store into operand 0 the number of trailing 0-bits in operand 1, starting
6159 at the least significant bit position. If operand 1 is 0, the
6160 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
6161 the result is undefined or has a useful value.
6163 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6164 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6165 integer mode is suitable for the target. The compiler will insert
6166 conversion instructions as necessary (typically to convert the result
6167 to the same width as @code{int}). When @var{m} is a vector, both
6168 operands must have mode @var{m}.
6170 This pattern is not allowed to @code{FAIL}.
6172 @cindex @code{popcount@var{m}2} instruction pattern
6173 @item @samp{popcount@var{m}2}
6174 Store into operand 0 the number of 1-bits in operand 1.
6176 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6177 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6178 integer mode is suitable for the target. The compiler will insert
6179 conversion instructions as necessary (typically to convert the result
6180 to the same width as @code{int}). When @var{m} is a vector, both
6181 operands must have mode @var{m}.
6183 This pattern is not allowed to @code{FAIL}.
6185 @cindex @code{parity@var{m}2} instruction pattern
6186 @item @samp{parity@var{m}2}
6187 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
6188 in operand 1 modulo 2.
6190 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6191 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6192 integer mode is suitable for the target. The compiler will insert
6193 conversion instructions as necessary (typically to convert the result
6194 to the same width as @code{int}). When @var{m} is a vector, both
6195 operands must have mode @var{m}.
6197 This pattern is not allowed to @code{FAIL}.
6199 @cindex @code{one_cmpl@var{m}2} instruction pattern
6200 @item @samp{one_cmpl@var{m}2}
6201 Store the bitwise-complement of operand 1 into operand 0.
6203 @cindex @code{movmem@var{m}} instruction pattern
6204 @item @samp{movmem@var{m}}
6205 Block move instruction. The destination and source blocks of memory
6206 are the first two operands, and both are @code{mem:BLK}s with an
6207 address in mode @code{Pmode}.
6209 The number of bytes to move is the third operand, in mode @var{m}.
6210 Usually, you specify @code{Pmode} for @var{m}. However, if you can
6211 generate better code knowing the range of valid lengths is smaller than
6212 those representable in a full Pmode pointer, you should provide
6214 mode corresponding to the range of values you can handle efficiently
6215 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
6216 that appear negative) and also a pattern with @code{Pmode}.
6218 The fourth operand is the known shared alignment of the source and
6219 destination, in the form of a @code{const_int} rtx. Thus, if the
6220 compiler knows that both source and destination are word-aligned,
6221 it may provide the value 4 for this operand.
6223 Optional operands 5 and 6 specify expected alignment and size of block
6224 respectively. The expected alignment differs from alignment in operand 4
6225 in a way that the blocks are not required to be aligned according to it in
6226 all cases. This expected alignment is also in bytes, just like operand 4.
6227 Expected size, when unknown, is set to @code{(const_int -1)}.
6229 Descriptions of multiple @code{movmem@var{m}} patterns can only be
6230 beneficial if the patterns for smaller modes have fewer restrictions
6231 on their first, second and fourth operands. Note that the mode @var{m}
6232 in @code{movmem@var{m}} does not impose any restriction on the mode of
6233 individually moved data units in the block.
6235 These patterns need not give special consideration to the possibility
6236 that the source and destination strings might overlap.
6238 @cindex @code{movstr} instruction pattern
6240 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
6241 an output operand in mode @code{Pmode}. The addresses of the
6242 destination and source strings are operands 1 and 2, and both are
6243 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
6244 the expansion of this pattern should store in operand 0 the address in
6245 which the @code{NUL} terminator was stored in the destination string.
6247 This patern has also several optional operands that are same as in
6250 @cindex @code{setmem@var{m}} instruction pattern
6251 @item @samp{setmem@var{m}}
6252 Block set instruction. The destination string is the first operand,
6253 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
6254 number of bytes to set is the second operand, in mode @var{m}. The value to
6255 initialize the memory with is the third operand. Targets that only support the
6256 clearing of memory should reject any value that is not the constant 0. See
6257 @samp{movmem@var{m}} for a discussion of the choice of mode.
6259 The fourth operand is the known alignment of the destination, in the form
6260 of a @code{const_int} rtx. Thus, if the compiler knows that the
6261 destination is word-aligned, it may provide the value 4 for this
6264 Optional operands 5 and 6 specify expected alignment and size of block
6265 respectively. The expected alignment differs from alignment in operand 4
6266 in a way that the blocks are not required to be aligned according to it in
6267 all cases. This expected alignment is also in bytes, just like operand 4.
6268 Expected size, when unknown, is set to @code{(const_int -1)}.
6269 Operand 7 is the minimal size of the block and operand 8 is the
6270 maximal size of the block (NULL if it cannot be represented as CONST_INT).
6271 Operand 9 is the probable maximal size (i.e.@: we cannot rely on it for
6272 correctness, but it can be used for choosing proper code sequence for a
6275 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
6277 @cindex @code{cmpstrn@var{m}} instruction pattern
6278 @item @samp{cmpstrn@var{m}}
6279 String compare instruction, with five operands. Operand 0 is the output;
6280 it has mode @var{m}. The remaining four operands are like the operands
6281 of @samp{movmem@var{m}}. The two memory blocks specified are compared
6282 byte by byte in lexicographic order starting at the beginning of each
6283 string. The instruction is not allowed to prefetch more than one byte
6284 at a time since either string may end in the first byte and reading past
6285 that may access an invalid page or segment and cause a fault. The
6286 comparison terminates early if the fetched bytes are different or if
6287 they are equal to zero. The effect of the instruction is to store a
6288 value in operand 0 whose sign indicates the result of the comparison.
6290 @cindex @code{cmpstr@var{m}} instruction pattern
6291 @item @samp{cmpstr@var{m}}
6292 String compare instruction, without known maximum length. Operand 0 is the
6293 output; it has mode @var{m}. The second and third operand are the blocks of
6294 memory to be compared; both are @code{mem:BLK} with an address in mode
6297 The fourth operand is the known shared alignment of the source and
6298 destination, in the form of a @code{const_int} rtx. Thus, if the
6299 compiler knows that both source and destination are word-aligned,
6300 it may provide the value 4 for this operand.
6302 The two memory blocks specified are compared byte by byte in lexicographic
6303 order starting at the beginning of each string. The instruction is not allowed
6304 to prefetch more than one byte at a time since either string may end in the
6305 first byte and reading past that may access an invalid page or segment and
6306 cause a fault. The comparison will terminate when the fetched bytes
6307 are different or if they are equal to zero. The effect of the
6308 instruction is to store a value in operand 0 whose sign indicates the
6309 result of the comparison.
6311 @cindex @code{cmpmem@var{m}} instruction pattern
6312 @item @samp{cmpmem@var{m}}
6313 Block compare instruction, with five operands like the operands
6314 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
6315 byte by byte in lexicographic order starting at the beginning of each
6316 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
6317 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
6318 the comparison will not stop if both bytes are zero. The effect of
6319 the instruction is to store a value in operand 0 whose sign indicates
6320 the result of the comparison.
6322 @cindex @code{strlen@var{m}} instruction pattern
6323 @item @samp{strlen@var{m}}
6324 Compute the length of a string, with three operands.
6325 Operand 0 is the result (of mode @var{m}), operand 1 is
6326 a @code{mem} referring to the first character of the string,
6327 operand 2 is the character to search for (normally zero),
6328 and operand 3 is a constant describing the known alignment
6329 of the beginning of the string.
6331 @cindex @code{float@var{m}@var{n}2} instruction pattern
6332 @item @samp{float@var{m}@var{n}2}
6333 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
6334 floating point mode @var{n} and store in operand 0 (which has mode
6337 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
6338 @item @samp{floatuns@var{m}@var{n}2}
6339 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
6340 to floating point mode @var{n} and store in operand 0 (which has mode
6343 @cindex @code{fix@var{m}@var{n}2} instruction pattern
6344 @item @samp{fix@var{m}@var{n}2}
6345 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6346 point mode @var{n} as a signed number and store in operand 0 (which
6347 has mode @var{n}). This instruction's result is defined only when
6348 the value of operand 1 is an integer.
6350 If the machine description defines this pattern, it also needs to
6351 define the @code{ftrunc} pattern.
6353 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
6354 @item @samp{fixuns@var{m}@var{n}2}
6355 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6356 point mode @var{n} as an unsigned number and store in operand 0 (which
6357 has mode @var{n}). This instruction's result is defined only when the
6358 value of operand 1 is an integer.
6360 @cindex @code{ftrunc@var{m}2} instruction pattern
6361 @item @samp{ftrunc@var{m}2}
6362 Convert operand 1 (valid for floating point mode @var{m}) to an
6363 integer value, still represented in floating point mode @var{m}, and
6364 store it in operand 0 (valid for floating point mode @var{m}).
6366 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
6367 @item @samp{fix_trunc@var{m}@var{n}2}
6368 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
6369 of mode @var{m} by converting the value to an integer.
6371 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
6372 @item @samp{fixuns_trunc@var{m}@var{n}2}
6373 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
6374 value of mode @var{m} by converting the value to an integer.
6376 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
6377 @item @samp{trunc@var{m}@var{n}2}
6378 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
6379 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6380 point or both floating point.
6382 @cindex @code{extend@var{m}@var{n}2} instruction pattern
6383 @item @samp{extend@var{m}@var{n}2}
6384 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6385 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6386 point or both floating point.
6388 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
6389 @item @samp{zero_extend@var{m}@var{n}2}
6390 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6391 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6394 @cindex @code{fract@var{m}@var{n}2} instruction pattern
6395 @item @samp{fract@var{m}@var{n}2}
6396 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6397 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6398 could be fixed-point to fixed-point, signed integer to fixed-point,
6399 fixed-point to signed integer, floating-point to fixed-point,
6400 or fixed-point to floating-point.
6401 When overflows or underflows happen, the results are undefined.
6403 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
6404 @item @samp{satfract@var{m}@var{n}2}
6405 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6406 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6407 could be fixed-point to fixed-point, signed integer to fixed-point,
6408 or floating-point to fixed-point.
6409 When overflows or underflows happen, the instruction saturates the
6410 results to the maximum or the minimum.
6412 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
6413 @item @samp{fractuns@var{m}@var{n}2}
6414 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6415 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6416 could be unsigned integer to fixed-point, or
6417 fixed-point to unsigned integer.
6418 When overflows or underflows happen, the results are undefined.
6420 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
6421 @item @samp{satfractuns@var{m}@var{n}2}
6422 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
6423 @var{n} and store in operand 0 (which has mode @var{n}).
6424 When overflows or underflows happen, the instruction saturates the
6425 results to the maximum or the minimum.
6427 @cindex @code{extv@var{m}} instruction pattern
6428 @item @samp{extv@var{m}}
6429 Extract a bit-field from register operand 1, sign-extend it, and store
6430 it in operand 0. Operand 2 specifies the width of the field in bits
6431 and operand 3 the starting bit, which counts from the most significant
6432 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
6435 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
6436 target-specific mode.
6438 @cindex @code{extvmisalign@var{m}} instruction pattern
6439 @item @samp{extvmisalign@var{m}}
6440 Extract a bit-field from memory operand 1, sign extend it, and store
6441 it in operand 0. Operand 2 specifies the width in bits and operand 3
6442 the starting bit. The starting bit is always somewhere in the first byte of
6443 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6444 is true and from the least significant bit otherwise.
6446 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
6447 Operands 2 and 3 have a target-specific mode.
6449 The instruction must not read beyond the last byte of the bit-field.
6451 @cindex @code{extzv@var{m}} instruction pattern
6452 @item @samp{extzv@var{m}}
6453 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
6455 @cindex @code{extzvmisalign@var{m}} instruction pattern
6456 @item @samp{extzvmisalign@var{m}}
6457 Like @samp{extvmisalign@var{m}} except that the bit-field value is
6460 @cindex @code{insv@var{m}} instruction pattern
6461 @item @samp{insv@var{m}}
6462 Insert operand 3 into a bit-field of register operand 0. Operand 1
6463 specifies the width of the field in bits and operand 2 the starting bit,
6464 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6465 is true and from the least significant bit otherwise.
6467 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
6468 target-specific mode.
6470 @cindex @code{insvmisalign@var{m}} instruction pattern
6471 @item @samp{insvmisalign@var{m}}
6472 Insert operand 3 into a bit-field of memory operand 0. Operand 1
6473 specifies the width of the field in bits and operand 2 the starting bit.
6474 The starting bit is always somewhere in the first byte of operand 0;
6475 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6476 is true and from the least significant bit otherwise.
6478 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
6479 Operands 1 and 2 have a target-specific mode.
6481 The instruction must not read or write beyond the last byte of the bit-field.
6483 @cindex @code{extv} instruction pattern
6485 Extract a bit-field from operand 1 (a register or memory operand), where
6486 operand 2 specifies the width in bits and operand 3 the starting bit,
6487 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
6488 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
6489 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
6490 be valid for @code{word_mode}.
6492 The RTL generation pass generates this instruction only with constants
6493 for operands 2 and 3 and the constant is never zero for operand 2.
6495 The bit-field value is sign-extended to a full word integer
6496 before it is stored in operand 0.
6498 This pattern is deprecated; please use @samp{extv@var{m}} and
6499 @code{extvmisalign@var{m}} instead.
6501 @cindex @code{extzv} instruction pattern
6503 Like @samp{extv} except that the bit-field value is zero-extended.
6505 This pattern is deprecated; please use @samp{extzv@var{m}} and
6506 @code{extzvmisalign@var{m}} instead.
6508 @cindex @code{insv} instruction pattern
6510 Store operand 3 (which must be valid for @code{word_mode}) into a
6511 bit-field in operand 0, where operand 1 specifies the width in bits and
6512 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
6513 @code{word_mode}; often @code{word_mode} is allowed only for registers.
6514 Operands 1 and 2 must be valid for @code{word_mode}.
6516 The RTL generation pass generates this instruction only with constants
6517 for operands 1 and 2 and the constant is never zero for operand 1.
6519 This pattern is deprecated; please use @samp{insv@var{m}} and
6520 @code{insvmisalign@var{m}} instead.
6522 @cindex @code{mov@var{mode}cc} instruction pattern
6523 @item @samp{mov@var{mode}cc}
6524 Conditionally move operand 2 or operand 3 into operand 0 according to the
6525 comparison in operand 1. If the comparison is true, operand 2 is moved
6526 into operand 0, otherwise operand 3 is moved.
6528 The mode of the operands being compared need not be the same as the operands
6529 being moved. Some machines, sparc64 for example, have instructions that
6530 conditionally move an integer value based on the floating point condition
6531 codes and vice versa.
6533 If the machine does not have conditional move instructions, do not
6534 define these patterns.
6536 @cindex @code{add@var{mode}cc} instruction pattern
6537 @item @samp{add@var{mode}cc}
6538 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
6539 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
6540 comparison in operand 1. If the comparison is false, operand 2 is moved into
6541 operand 0, otherwise (operand 2 + operand 3) is moved.
6543 @cindex @code{cond_add@var{mode}} instruction pattern
6544 @cindex @code{cond_sub@var{mode}} instruction pattern
6545 @cindex @code{cond_mul@var{mode}} instruction pattern
6546 @cindex @code{cond_div@var{mode}} instruction pattern
6547 @cindex @code{cond_udiv@var{mode}} instruction pattern
6548 @cindex @code{cond_mod@var{mode}} instruction pattern
6549 @cindex @code{cond_umod@var{mode}} instruction pattern
6550 @cindex @code{cond_and@var{mode}} instruction pattern
6551 @cindex @code{cond_ior@var{mode}} instruction pattern
6552 @cindex @code{cond_xor@var{mode}} instruction pattern
6553 @cindex @code{cond_smin@var{mode}} instruction pattern
6554 @cindex @code{cond_smax@var{mode}} instruction pattern
6555 @cindex @code{cond_umin@var{mode}} instruction pattern
6556 @cindex @code{cond_umax@var{mode}} instruction pattern
6557 @item @samp{cond_add@var{mode}}
6558 @itemx @samp{cond_sub@var{mode}}
6559 @itemx @samp{cond_mul@var{mode}}
6560 @itemx @samp{cond_div@var{mode}}
6561 @itemx @samp{cond_udiv@var{mode}}
6562 @itemx @samp{cond_mod@var{mode}}
6563 @itemx @samp{cond_umod@var{mode}}
6564 @itemx @samp{cond_and@var{mode}}
6565 @itemx @samp{cond_ior@var{mode}}
6566 @itemx @samp{cond_xor@var{mode}}
6567 @itemx @samp{cond_smin@var{mode}}
6568 @itemx @samp{cond_smax@var{mode}}
6569 @itemx @samp{cond_umin@var{mode}}
6570 @itemx @samp{cond_umax@var{mode}}
6571 When operand 1 is true, perform an operation on operands 2 and 3 and
6572 store the result in operand 0, otherwise store operand 4 in operand 0.
6573 The operation works elementwise if the operands are vectors.
6575 The scalar case is equivalent to:
6578 op0 = op1 ? op2 @var{op} op3 : op4;
6581 while the vector case is equivalent to:
6584 for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
6585 op0[i] = op1[i] ? op2[i] @var{op} op3[i] : op4[i];
6588 where, for example, @var{op} is @code{+} for @samp{cond_add@var{mode}}.
6590 When defined for floating-point modes, the contents of @samp{op3[i]}
6591 are not interpreted if @samp{op1[i]} is false, just like they would not
6592 be in a normal C @samp{?:} condition.
6594 Operands 0, 2, 3 and 4 all have mode @var{m}. Operand 1 is a scalar
6595 integer if @var{m} is scalar, otherwise it has the mode returned by
6596 @code{TARGET_VECTORIZE_GET_MASK_MODE}.
6598 @cindex @code{cond_fma@var{mode}} instruction pattern
6599 @cindex @code{cond_fms@var{mode}} instruction pattern
6600 @cindex @code{cond_fnma@var{mode}} instruction pattern
6601 @cindex @code{cond_fnms@var{mode}} instruction pattern
6602 @item @samp{cond_fma@var{mode}}
6603 @itemx @samp{cond_fms@var{mode}}
6604 @itemx @samp{cond_fnma@var{mode}}
6605 @itemx @samp{cond_fnms@var{mode}}
6606 Like @samp{cond_add@var{m}}, except that the conditional operation
6607 takes 3 operands rather than two. For example, the vector form of
6608 @samp{cond_fma@var{mode}} is equivalent to:
6611 for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
6612 op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i];
6615 @cindex @code{neg@var{mode}cc} instruction pattern
6616 @item @samp{neg@var{mode}cc}
6617 Similar to @samp{mov@var{mode}cc} but for conditional negation. Conditionally
6618 move the negation of operand 2 or the unchanged operand 3 into operand 0
6619 according to the comparison in operand 1. If the comparison is true, the negation
6620 of operand 2 is moved into operand 0, otherwise operand 3 is moved.
6622 @cindex @code{not@var{mode}cc} instruction pattern
6623 @item @samp{not@var{mode}cc}
6624 Similar to @samp{neg@var{mode}cc} but for conditional complement.
6625 Conditionally move the bitwise complement of operand 2 or the unchanged
6626 operand 3 into operand 0 according to the comparison in operand 1.
6627 If the comparison is true, the complement of operand 2 is moved into
6628 operand 0, otherwise operand 3 is moved.
6630 @cindex @code{cstore@var{mode}4} instruction pattern
6631 @item @samp{cstore@var{mode}4}
6632 Store zero or nonzero in operand 0 according to whether a comparison
6633 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
6634 are the first and second operand of the comparison, respectively.
6635 You specify the mode that operand 0 must have when you write the
6636 @code{match_operand} expression. The compiler automatically sees which
6637 mode you have used and supplies an operand of that mode.
6639 The value stored for a true condition must have 1 as its low bit, or
6640 else must be negative. Otherwise the instruction is not suitable and
6641 you should omit it from the machine description. You describe to the
6642 compiler exactly which value is stored by defining the macro
6643 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
6644 found that can be used for all the possible comparison operators, you
6645 should pick one and use a @code{define_expand} to map all results
6646 onto the one you chose.
6648 These operations may @code{FAIL}, but should do so only in relatively
6649 uncommon cases; if they would @code{FAIL} for common cases involving
6650 integer comparisons, it is best to restrict the predicates to not
6651 allow these operands. Likewise if a given comparison operator will
6652 always fail, independent of the operands (for floating-point modes, the
6653 @code{ordered_comparison_operator} predicate is often useful in this case).
6655 If this pattern is omitted, the compiler will generate a conditional
6656 branch---for example, it may copy a constant one to the target and branching
6657 around an assignment of zero to the target---or a libcall. If the predicate
6658 for operand 1 only rejects some operators, it will also try reordering the
6659 operands and/or inverting the result value (e.g.@: by an exclusive OR).
6660 These possibilities could be cheaper or equivalent to the instructions
6661 used for the @samp{cstore@var{mode}4} pattern followed by those required
6662 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
6663 case, you can and should make operand 1's predicate reject some operators
6664 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
6665 from the machine description.
6667 @cindex @code{cbranch@var{mode}4} instruction pattern
6668 @item @samp{cbranch@var{mode}4}
6669 Conditional branch instruction combined with a compare instruction.
6670 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
6671 first and second operands of the comparison, respectively. Operand 3
6672 is the @code{code_label} to jump to.
6674 @cindex @code{jump} instruction pattern
6676 A jump inside a function; an unconditional branch. Operand 0 is the
6677 @code{code_label} to jump to. This pattern name is mandatory on all
6680 @cindex @code{call} instruction pattern
6682 Subroutine call instruction returning no value. Operand 0 is the
6683 function to call; operand 1 is the number of bytes of arguments pushed
6684 as a @code{const_int}; operand 2 is the number of registers used as
6687 On most machines, operand 2 is not actually stored into the RTL
6688 pattern. It is supplied for the sake of some RISC machines which need
6689 to put this information into the assembler code; they can put it in
6690 the RTL instead of operand 1.
6692 Operand 0 should be a @code{mem} RTX whose address is the address of the
6693 function. Note, however, that this address can be a @code{symbol_ref}
6694 expression even if it would not be a legitimate memory address on the
6695 target machine. If it is also not a valid argument for a call
6696 instruction, the pattern for this operation should be a
6697 @code{define_expand} (@pxref{Expander Definitions}) that places the
6698 address into a register and uses that register in the call instruction.
6700 @cindex @code{call_value} instruction pattern
6701 @item @samp{call_value}
6702 Subroutine call instruction returning a value. Operand 0 is the hard
6703 register in which the value is returned. There are three more
6704 operands, the same as the three operands of the @samp{call}
6705 instruction (but with numbers increased by one).
6707 Subroutines that return @code{BLKmode} objects use the @samp{call}
6710 @cindex @code{call_pop} instruction pattern
6711 @cindex @code{call_value_pop} instruction pattern
6712 @item @samp{call_pop}, @samp{call_value_pop}
6713 Similar to @samp{call} and @samp{call_value}, except used if defined and
6714 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
6715 that contains both the function call and a @code{set} to indicate the
6716 adjustment made to the frame pointer.
6718 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
6719 patterns increases the number of functions for which the frame pointer
6720 can be eliminated, if desired.
6722 @cindex @code{untyped_call} instruction pattern
6723 @item @samp{untyped_call}
6724 Subroutine call instruction returning a value of any type. Operand 0 is
6725 the function to call; operand 1 is a memory location where the result of
6726 calling the function is to be stored; operand 2 is a @code{parallel}
6727 expression where each element is a @code{set} expression that indicates
6728 the saving of a function return value into the result block.
6730 This instruction pattern should be defined to support
6731 @code{__builtin_apply} on machines where special instructions are needed
6732 to call a subroutine with arbitrary arguments or to save the value
6733 returned. This instruction pattern is required on machines that have
6734 multiple registers that can hold a return value
6735 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
6737 @cindex @code{return} instruction pattern
6739 Subroutine return instruction. This instruction pattern name should be
6740 defined only if a single instruction can do all the work of returning
6743 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
6744 RTL generation phase. In this case it is to support machines where
6745 multiple instructions are usually needed to return from a function, but
6746 some class of functions only requires one instruction to implement a
6747 return. Normally, the applicable functions are those which do not need
6748 to save any registers or allocate stack space.
6750 It is valid for this pattern to expand to an instruction using
6751 @code{simple_return} if no epilogue is required.
6753 @cindex @code{simple_return} instruction pattern
6754 @item @samp{simple_return}
6755 Subroutine return instruction. This instruction pattern name should be
6756 defined only if a single instruction can do all the work of returning
6757 from a function on a path where no epilogue is required. This pattern
6758 is very similar to the @code{return} instruction pattern, but it is emitted
6759 only by the shrink-wrapping optimization on paths where the function
6760 prologue has not been executed, and a function return should occur without
6761 any of the effects of the epilogue. Additional uses may be introduced on
6762 paths where both the prologue and the epilogue have executed.
6764 @findex reload_completed
6765 @findex leaf_function_p
6766 For such machines, the condition specified in this pattern should only
6767 be true when @code{reload_completed} is nonzero and the function's
6768 epilogue would only be a single instruction. For machines with register
6769 windows, the routine @code{leaf_function_p} may be used to determine if
6770 a register window push is required.
6772 Machines that have conditional return instructions should define patterns
6778 (if_then_else (match_operator
6779 0 "comparison_operator"
6780 [(cc0) (const_int 0)])
6787 where @var{condition} would normally be the same condition specified on the
6788 named @samp{return} pattern.
6790 @cindex @code{untyped_return} instruction pattern
6791 @item @samp{untyped_return}
6792 Untyped subroutine return instruction. This instruction pattern should
6793 be defined to support @code{__builtin_return} on machines where special
6794 instructions are needed to return a value of any type.
6796 Operand 0 is a memory location where the result of calling a function
6797 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
6798 expression where each element is a @code{set} expression that indicates
6799 the restoring of a function return value from the result block.
6801 @cindex @code{nop} instruction pattern
6803 No-op instruction. This instruction pattern name should always be defined
6804 to output a no-op in assembler code. @code{(const_int 0)} will do as an
6807 @cindex @code{indirect_jump} instruction pattern
6808 @item @samp{indirect_jump}
6809 An instruction to jump to an address which is operand zero.
6810 This pattern name is mandatory on all machines.
6812 @cindex @code{casesi} instruction pattern
6814 Instruction to jump through a dispatch table, including bounds checking.
6815 This instruction takes five operands:
6819 The index to dispatch on, which has mode @code{SImode}.
6822 The lower bound for indices in the table, an integer constant.
6825 The total range of indices in the table---the largest index
6826 minus the smallest one (both inclusive).
6829 A label that precedes the table itself.
6832 A label to jump to if the index has a value outside the bounds.
6835 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
6836 @code{jump_table_data}. The number of elements in the table is one plus the
6837 difference between the upper bound and the lower bound.
6839 @cindex @code{tablejump} instruction pattern
6840 @item @samp{tablejump}
6841 Instruction to jump to a variable address. This is a low-level
6842 capability which can be used to implement a dispatch table when there
6843 is no @samp{casesi} pattern.
6845 This pattern requires two operands: the address or offset, and a label
6846 which should immediately precede the jump table. If the macro
6847 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
6848 operand is an offset which counts from the address of the table; otherwise,
6849 it is an absolute address to jump to. In either case, the first operand has
6852 The @samp{tablejump} insn is always the last insn before the jump
6853 table it uses. Its assembler code normally has no need to use the
6854 second operand, but you should incorporate it in the RTL pattern so
6855 that the jump optimizer will not delete the table as unreachable code.
6858 @cindex @code{doloop_end} instruction pattern
6859 @item @samp{doloop_end}
6860 Conditional branch instruction that decrements a register and
6861 jumps if the register is nonzero. Operand 0 is the register to
6862 decrement and test; operand 1 is the label to jump to if the
6863 register is nonzero.
6864 @xref{Looping Patterns}.
6866 This optional instruction pattern should be defined for machines with
6867 low-overhead looping instructions as the loop optimizer will try to
6868 modify suitable loops to utilize it. The target hook
6869 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
6870 low-overhead loops can be used.
6872 @cindex @code{doloop_begin} instruction pattern
6873 @item @samp{doloop_begin}
6874 Companion instruction to @code{doloop_end} required for machines that
6875 need to perform some initialization, such as loading a special counter
6876 register. Operand 1 is the associated @code{doloop_end} pattern and
6877 operand 0 is the register that it decrements.
6879 If initialization insns do not always need to be emitted, use a
6880 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
6882 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
6883 @item @samp{canonicalize_funcptr_for_compare}
6884 Canonicalize the function pointer in operand 1 and store the result
6887 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
6888 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
6889 and also has mode @code{Pmode}.
6891 Canonicalization of a function pointer usually involves computing
6892 the address of the function which would be called if the function
6893 pointer were used in an indirect call.
6895 Only define this pattern if function pointers on the target machine
6896 can have different values but still call the same function when
6897 used in an indirect call.
6899 @cindex @code{save_stack_block} instruction pattern
6900 @cindex @code{save_stack_function} instruction pattern
6901 @cindex @code{save_stack_nonlocal} instruction pattern
6902 @cindex @code{restore_stack_block} instruction pattern
6903 @cindex @code{restore_stack_function} instruction pattern
6904 @cindex @code{restore_stack_nonlocal} instruction pattern
6905 @item @samp{save_stack_block}
6906 @itemx @samp{save_stack_function}
6907 @itemx @samp{save_stack_nonlocal}
6908 @itemx @samp{restore_stack_block}
6909 @itemx @samp{restore_stack_function}
6910 @itemx @samp{restore_stack_nonlocal}
6911 Most machines save and restore the stack pointer by copying it to or
6912 from an object of mode @code{Pmode}. Do not define these patterns on
6915 Some machines require special handling for stack pointer saves and
6916 restores. On those machines, define the patterns corresponding to the
6917 non-standard cases by using a @code{define_expand} (@pxref{Expander
6918 Definitions}) that produces the required insns. The three types of
6919 saves and restores are:
6923 @samp{save_stack_block} saves the stack pointer at the start of a block
6924 that allocates a variable-sized object, and @samp{restore_stack_block}
6925 restores the stack pointer when the block is exited.
6928 @samp{save_stack_function} and @samp{restore_stack_function} do a
6929 similar job for the outermost block of a function and are used when the
6930 function allocates variable-sized objects or calls @code{alloca}. Only
6931 the epilogue uses the restored stack pointer, allowing a simpler save or
6932 restore sequence on some machines.
6935 @samp{save_stack_nonlocal} is used in functions that contain labels
6936 branched to by nested functions. It saves the stack pointer in such a
6937 way that the inner function can use @samp{restore_stack_nonlocal} to
6938 restore the stack pointer. The compiler generates code to restore the
6939 frame and argument pointer registers, but some machines require saving
6940 and restoring additional data such as register window information or
6941 stack backchains. Place insns in these patterns to save and restore any
6945 When saving the stack pointer, operand 0 is the save area and operand 1
6946 is the stack pointer. The mode used to allocate the save area defaults
6947 to @code{Pmode} but you can override that choice by defining the
6948 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
6949 specify an integral mode, or @code{VOIDmode} if no save area is needed
6950 for a particular type of save (either because no save is needed or
6951 because a machine-specific save area can be used). Operand 0 is the
6952 stack pointer and operand 1 is the save area for restore operations. If
6953 @samp{save_stack_block} is defined, operand 0 must not be
6954 @code{VOIDmode} since these saves can be arbitrarily nested.
6956 A save area is a @code{mem} that is at a constant offset from
6957 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
6958 nonlocal gotos and a @code{reg} in the other two cases.
6960 @cindex @code{allocate_stack} instruction pattern
6961 @item @samp{allocate_stack}
6962 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
6963 the stack pointer to create space for dynamically allocated data.
6965 Store the resultant pointer to this space into operand 0. If you
6966 are allocating space from the main stack, do this by emitting a
6967 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
6968 If you are allocating the space elsewhere, generate code to copy the
6969 location of the space to operand 0. In the latter case, you must
6970 ensure this space gets freed when the corresponding space on the main
6973 Do not define this pattern if all that must be done is the subtraction.
6974 Some machines require other operations such as stack probes or
6975 maintaining the back chain. Define this pattern to emit those
6976 operations in addition to updating the stack pointer.
6978 @cindex @code{check_stack} instruction pattern
6979 @item @samp{check_stack}
6980 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
6981 probing the stack, define this pattern to perform the needed check and signal
6982 an error if the stack has overflowed. The single operand is the address in
6983 the stack farthest from the current stack pointer that you need to validate.
6984 Normally, on platforms where this pattern is needed, you would obtain the
6985 stack limit from a global or thread-specific variable or register.
6987 @cindex @code{probe_stack_address} instruction pattern
6988 @item @samp{probe_stack_address}
6989 If stack checking (@pxref{Stack Checking}) can be done on your system by
6990 probing the stack but without the need to actually access it, define this
6991 pattern and signal an error if the stack has overflowed. The single operand
6992 is the memory address in the stack that needs to be probed.
6994 @cindex @code{probe_stack} instruction pattern
6995 @item @samp{probe_stack}
6996 If stack checking (@pxref{Stack Checking}) can be done on your system by
6997 probing the stack but doing it with a ``store zero'' instruction is not valid
6998 or optimal, define this pattern to do the probing differently and signal an
6999 error if the stack has overflowed. The single operand is the memory reference
7000 in the stack that needs to be probed.
7002 @cindex @code{nonlocal_goto} instruction pattern
7003 @item @samp{nonlocal_goto}
7004 Emit code to generate a non-local goto, e.g., a jump from one function
7005 to a label in an outer function. This pattern has four arguments,
7006 each representing a value to be used in the jump. The first
7007 argument is to be loaded into the frame pointer, the second is
7008 the address to branch to (code to dispatch to the actual label),
7009 the third is the address of a location where the stack is saved,
7010 and the last is the address of the label, to be placed in the
7011 location for the incoming static chain.
7013 On most machines you need not define this pattern, since GCC will
7014 already generate the correct code, which is to load the frame pointer
7015 and static chain, restore the stack (using the
7016 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
7017 to the dispatcher. You need only define this pattern if this code will
7018 not work on your machine.
7020 @cindex @code{nonlocal_goto_receiver} instruction pattern
7021 @item @samp{nonlocal_goto_receiver}
7022 This pattern, if defined, contains code needed at the target of a
7023 nonlocal goto after the code already generated by GCC@. You will not
7024 normally need to define this pattern. A typical reason why you might
7025 need this pattern is if some value, such as a pointer to a global table,
7026 must be restored when the frame pointer is restored. Note that a nonlocal
7027 goto only occurs within a unit-of-translation, so a global table pointer
7028 that is shared by all functions of a given module need not be restored.
7029 There are no arguments.
7031 @cindex @code{exception_receiver} instruction pattern
7032 @item @samp{exception_receiver}
7033 This pattern, if defined, contains code needed at the site of an
7034 exception handler that isn't needed at the site of a nonlocal goto. You
7035 will not normally need to define this pattern. A typical reason why you
7036 might need this pattern is if some value, such as a pointer to a global
7037 table, must be restored after control flow is branched to the handler of
7038 an exception. There are no arguments.
7040 @cindex @code{builtin_setjmp_setup} instruction pattern
7041 @item @samp{builtin_setjmp_setup}
7042 This pattern, if defined, contains additional code needed to initialize
7043 the @code{jmp_buf}. You will not normally need to define this pattern.
7044 A typical reason why you might need this pattern is if some value, such
7045 as a pointer to a global table, must be restored. Though it is
7046 preferred that the pointer value be recalculated if possible (given the
7047 address of a label for instance). The single argument is a pointer to
7048 the @code{jmp_buf}. Note that the buffer is five words long and that
7049 the first three are normally used by the generic mechanism.
7051 @cindex @code{builtin_setjmp_receiver} instruction pattern
7052 @item @samp{builtin_setjmp_receiver}
7053 This pattern, if defined, contains code needed at the site of a
7054 built-in setjmp that isn't needed at the site of a nonlocal goto. You
7055 will not normally need to define this pattern. A typical reason why you
7056 might need this pattern is if some value, such as a pointer to a global
7057 table, must be restored. It takes one argument, which is the label
7058 to which builtin_longjmp transferred control; this pattern may be emitted
7059 at a small offset from that label.
7061 @cindex @code{builtin_longjmp} instruction pattern
7062 @item @samp{builtin_longjmp}
7063 This pattern, if defined, performs the entire action of the longjmp.
7064 You will not normally need to define this pattern unless you also define
7065 @code{builtin_setjmp_setup}. The single argument is a pointer to the
7068 @cindex @code{eh_return} instruction pattern
7069 @item @samp{eh_return}
7070 This pattern, if defined, affects the way @code{__builtin_eh_return},
7071 and thence the call frame exception handling library routines, are
7072 built. It is intended to handle non-trivial actions needed along
7073 the abnormal return path.
7075 The address of the exception handler to which the function should return
7076 is passed as operand to this pattern. It will normally need to copied by
7077 the pattern to some special register or memory location.
7078 If the pattern needs to determine the location of the target call
7079 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
7080 if defined; it will have already been assigned.
7082 If this pattern is not defined, the default action will be to simply
7083 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
7084 that macro or this pattern needs to be defined if call frame exception
7085 handling is to be used.
7087 @cindex @code{prologue} instruction pattern
7088 @anchor{prologue instruction pattern}
7089 @item @samp{prologue}
7090 This pattern, if defined, emits RTL for entry to a function. The function
7091 entry is responsible for setting up the stack frame, initializing the frame
7092 pointer register, saving callee saved registers, etc.
7094 Using a prologue pattern is generally preferred over defining
7095 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
7097 The @code{prologue} pattern is particularly useful for targets which perform
7098 instruction scheduling.
7100 @cindex @code{window_save} instruction pattern
7101 @anchor{window_save instruction pattern}
7102 @item @samp{window_save}
7103 This pattern, if defined, emits RTL for a register window save. It should
7104 be defined if the target machine has register windows but the window events
7105 are decoupled from calls to subroutines. The canonical example is the SPARC
7108 @cindex @code{epilogue} instruction pattern
7109 @anchor{epilogue instruction pattern}
7110 @item @samp{epilogue}
7111 This pattern emits RTL for exit from a function. The function
7112 exit is responsible for deallocating the stack frame, restoring callee saved
7113 registers and emitting the return instruction.
7115 Using an epilogue pattern is generally preferred over defining
7116 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
7118 The @code{epilogue} pattern is particularly useful for targets which perform
7119 instruction scheduling or which have delay slots for their return instruction.
7121 @cindex @code{sibcall_epilogue} instruction pattern
7122 @item @samp{sibcall_epilogue}
7123 This pattern, if defined, emits RTL for exit from a function without the final
7124 branch back to the calling function. This pattern will be emitted before any
7125 sibling call (aka tail call) sites.
7127 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
7128 parameter passing or any stack slots for arguments passed to the current
7131 @cindex @code{trap} instruction pattern
7133 This pattern, if defined, signals an error, typically by causing some
7134 kind of signal to be raised.
7136 @cindex @code{ctrap@var{MM}4} instruction pattern
7137 @item @samp{ctrap@var{MM}4}
7138 Conditional trap instruction. Operand 0 is a piece of RTL which
7139 performs a comparison, and operands 1 and 2 are the arms of the
7140 comparison. Operand 3 is the trap code, an integer.
7142 A typical @code{ctrap} pattern looks like
7145 (define_insn "ctrapsi4"
7146 [(trap_if (match_operator 0 "trap_operator"
7147 [(match_operand 1 "register_operand")
7148 (match_operand 2 "immediate_operand")])
7149 (match_operand 3 "const_int_operand" "i"))]
7154 @cindex @code{prefetch} instruction pattern
7155 @item @samp{prefetch}
7156 This pattern, if defined, emits code for a non-faulting data prefetch
7157 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
7158 is a constant 1 if the prefetch is preparing for a write to the memory
7159 address, or a constant 0 otherwise. Operand 2 is the expected degree of
7160 temporal locality of the data and is a value between 0 and 3, inclusive; 0
7161 means that the data has no temporal locality, so it need not be left in the
7162 cache after the access; 3 means that the data has a high degree of temporal
7163 locality and should be left in all levels of cache possible; 1 and 2 mean,
7164 respectively, a low or moderate degree of temporal locality.
7166 Targets that do not support write prefetches or locality hints can ignore
7167 the values of operands 1 and 2.
7169 @cindex @code{blockage} instruction pattern
7170 @item @samp{blockage}
7171 This pattern defines a pseudo insn that prevents the instruction
7172 scheduler and other passes from moving instructions and using register
7173 equivalences across the boundary defined by the blockage insn.
7174 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
7176 @cindex @code{memory_blockage} instruction pattern
7177 @item @samp{memory_blockage}
7178 This pattern, if defined, represents a compiler memory barrier, and will be
7179 placed at points across which RTL passes may not propagate memory accesses.
7180 This instruction needs to read and write volatile BLKmode memory. It does
7181 not need to generate any machine instruction. If this pattern is not defined,
7182 the compiler falls back to emitting an instruction corresponding
7183 to @code{asm volatile ("" ::: "memory")}.
7185 @cindex @code{memory_barrier} instruction pattern
7186 @item @samp{memory_barrier}
7187 If the target memory model is not fully synchronous, then this pattern
7188 should be defined to an instruction that orders both loads and stores
7189 before the instruction with respect to loads and stores after the instruction.
7190 This pattern has no operands.
7192 @cindex @code{speculation_barrier} instruction pattern
7193 @item @samp{speculation_barrier}
7194 If the target can support speculative execution, then this pattern should
7195 be defined to an instruction that will block subsequent execution until
7196 any prior speculation conditions has been resolved. The pattern must also
7197 ensure that the compiler cannot move memory operations past the barrier,
7198 so it needs to be an UNSPEC_VOLATILE pattern. The pattern has no
7201 If this pattern is not defined then the default expansion of
7202 @code{__builtin_speculation_safe_value} will emit a warning. You can
7203 suppress this warning by defining this pattern with a final condition
7204 of @code{0} (zero), which tells the compiler that a speculation
7205 barrier is not needed for this target.
7207 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
7208 @item @samp{sync_compare_and_swap@var{mode}}
7209 This pattern, if defined, emits code for an atomic compare-and-swap
7210 operation. Operand 1 is the memory on which the atomic operation is
7211 performed. Operand 2 is the ``old'' value to be compared against the
7212 current contents of the memory location. Operand 3 is the ``new'' value
7213 to store in the memory if the compare succeeds. Operand 0 is the result
7214 of the operation; it should contain the contents of the memory
7215 before the operation. If the compare succeeds, this should obviously be
7216 a copy of operand 2.
7218 This pattern must show that both operand 0 and operand 1 are modified.
7220 This pattern must issue any memory barrier instructions such that all
7221 memory operations before the atomic operation occur before the atomic
7222 operation and all memory operations after the atomic operation occur
7223 after the atomic operation.
7225 For targets where the success or failure of the compare-and-swap
7226 operation is available via the status flags, it is possible to
7227 avoid a separate compare operation and issue the subsequent
7228 branch or store-flag operation immediately after the compare-and-swap.
7229 To this end, GCC will look for a @code{MODE_CC} set in the
7230 output of @code{sync_compare_and_swap@var{mode}}; if the machine
7231 description includes such a set, the target should also define special
7232 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
7233 be able to take the destination of the @code{MODE_CC} set and pass it
7234 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
7235 operand of the comparison (the second will be @code{(const_int 0)}).
7237 For targets where the operating system may provide support for this
7238 operation via library calls, the @code{sync_compare_and_swap_optab}
7239 may be initialized to a function with the same interface as the
7240 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
7241 set of @var{__sync} builtins are supported via library calls, the
7242 target can initialize all of the optabs at once with
7243 @code{init_sync_libfuncs}.
7244 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
7245 assumed that these library calls do @emph{not} use any kind of
7246 interruptable locking.
7248 @cindex @code{sync_add@var{mode}} instruction pattern
7249 @cindex @code{sync_sub@var{mode}} instruction pattern
7250 @cindex @code{sync_ior@var{mode}} instruction pattern
7251 @cindex @code{sync_and@var{mode}} instruction pattern
7252 @cindex @code{sync_xor@var{mode}} instruction pattern
7253 @cindex @code{sync_nand@var{mode}} instruction pattern
7254 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
7255 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
7256 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
7257 These patterns emit code for an atomic operation on memory.
7258 Operand 0 is the memory on which the atomic operation is performed.
7259 Operand 1 is the second operand to the binary operator.
7261 This pattern must issue any memory barrier instructions such that all
7262 memory operations before the atomic operation occur before the atomic
7263 operation and all memory operations after the atomic operation occur
7264 after the atomic operation.
7266 If these patterns are not defined, the operation will be constructed
7267 from a compare-and-swap operation, if defined.
7269 @cindex @code{sync_old_add@var{mode}} instruction pattern
7270 @cindex @code{sync_old_sub@var{mode}} instruction pattern
7271 @cindex @code{sync_old_ior@var{mode}} instruction pattern
7272 @cindex @code{sync_old_and@var{mode}} instruction pattern
7273 @cindex @code{sync_old_xor@var{mode}} instruction pattern
7274 @cindex @code{sync_old_nand@var{mode}} instruction pattern
7275 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
7276 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
7277 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
7278 These patterns emit code for an atomic operation on memory,
7279 and return the value that the memory contained before the operation.
7280 Operand 0 is the result value, operand 1 is the memory on which the
7281 atomic operation is performed, and operand 2 is the second operand
7282 to the binary operator.
7284 This pattern must issue any memory barrier instructions such that all
7285 memory operations before the atomic operation occur before the atomic
7286 operation and all memory operations after the atomic operation occur
7287 after the atomic operation.
7289 If these patterns are not defined, the operation will be constructed
7290 from a compare-and-swap operation, if defined.
7292 @cindex @code{sync_new_add@var{mode}} instruction pattern
7293 @cindex @code{sync_new_sub@var{mode}} instruction pattern
7294 @cindex @code{sync_new_ior@var{mode}} instruction pattern
7295 @cindex @code{sync_new_and@var{mode}} instruction pattern
7296 @cindex @code{sync_new_xor@var{mode}} instruction pattern
7297 @cindex @code{sync_new_nand@var{mode}} instruction pattern
7298 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
7299 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
7300 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
7301 These patterns are like their @code{sync_old_@var{op}} counterparts,
7302 except that they return the value that exists in the memory location
7303 after the operation, rather than before the operation.
7305 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
7306 @item @samp{sync_lock_test_and_set@var{mode}}
7307 This pattern takes two forms, based on the capabilities of the target.
7308 In either case, operand 0 is the result of the operand, operand 1 is
7309 the memory on which the atomic operation is performed, and operand 2
7310 is the value to set in the lock.
7312 In the ideal case, this operation is an atomic exchange operation, in
7313 which the previous value in memory operand is copied into the result
7314 operand, and the value operand is stored in the memory operand.
7316 For less capable targets, any value operand that is not the constant 1
7317 should be rejected with @code{FAIL}. In this case the target may use
7318 an atomic test-and-set bit operation. The result operand should contain
7319 1 if the bit was previously set and 0 if the bit was previously clear.
7320 The true contents of the memory operand are implementation defined.
7322 This pattern must issue any memory barrier instructions such that the
7323 pattern as a whole acts as an acquire barrier, that is all memory
7324 operations after the pattern do not occur until the lock is acquired.
7326 If this pattern is not defined, the operation will be constructed from
7327 a compare-and-swap operation, if defined.
7329 @cindex @code{sync_lock_release@var{mode}} instruction pattern
7330 @item @samp{sync_lock_release@var{mode}}
7331 This pattern, if defined, releases a lock set by
7332 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
7333 that contains the lock; operand 1 is the value to store in the lock.
7335 If the target doesn't implement full semantics for
7336 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
7337 the constant 0 should be rejected with @code{FAIL}, and the true contents
7338 of the memory operand are implementation defined.
7340 This pattern must issue any memory barrier instructions such that the
7341 pattern as a whole acts as a release barrier, that is the lock is
7342 released only after all previous memory operations have completed.
7344 If this pattern is not defined, then a @code{memory_barrier} pattern
7345 will be emitted, followed by a store of the value to the memory operand.
7347 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
7348 @item @samp{atomic_compare_and_swap@var{mode}}
7349 This pattern, if defined, emits code for an atomic compare-and-swap
7350 operation with memory model semantics. Operand 2 is the memory on which
7351 the atomic operation is performed. Operand 0 is an output operand which
7352 is set to true or false based on whether the operation succeeded. Operand
7353 1 is an output operand which is set to the contents of the memory before
7354 the operation was attempted. Operand 3 is the value that is expected to
7355 be in memory. Operand 4 is the value to put in memory if the expected
7356 value is found there. Operand 5 is set to 1 if this compare and swap is to
7357 be treated as a weak operation. Operand 6 is the memory model to be used
7358 if the operation is a success. Operand 7 is the memory model to be used
7359 if the operation fails.
7361 If memory referred to in operand 2 contains the value in operand 3, then
7362 operand 4 is stored in memory pointed to by operand 2 and fencing based on
7363 the memory model in operand 6 is issued.
7365 If memory referred to in operand 2 does not contain the value in operand 3,
7366 then fencing based on the memory model in operand 7 is issued.
7368 If a target does not support weak compare-and-swap operations, or the port
7369 elects not to implement weak operations, the argument in operand 5 can be
7370 ignored. Note a strong implementation must be provided.
7372 If this pattern is not provided, the @code{__atomic_compare_exchange}
7373 built-in functions will utilize the legacy @code{sync_compare_and_swap}
7374 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
7376 @cindex @code{atomic_load@var{mode}} instruction pattern
7377 @item @samp{atomic_load@var{mode}}
7378 This pattern implements an atomic load operation with memory model
7379 semantics. Operand 1 is the memory address being loaded from. Operand 0
7380 is the result of the load. Operand 2 is the memory model to be used for
7383 If not present, the @code{__atomic_load} built-in function will either
7384 resort to a normal load with memory barriers, or a compare-and-swap
7385 operation if a normal load would not be atomic.
7387 @cindex @code{atomic_store@var{mode}} instruction pattern
7388 @item @samp{atomic_store@var{mode}}
7389 This pattern implements an atomic store operation with memory model
7390 semantics. Operand 0 is the memory address being stored to. Operand 1
7391 is the value to be written. Operand 2 is the memory model to be used for
7394 If not present, the @code{__atomic_store} built-in function will attempt to
7395 perform a normal store and surround it with any required memory fences. If
7396 the store would not be atomic, then an @code{__atomic_exchange} is
7397 attempted with the result being ignored.
7399 @cindex @code{atomic_exchange@var{mode}} instruction pattern
7400 @item @samp{atomic_exchange@var{mode}}
7401 This pattern implements an atomic exchange operation with memory model
7402 semantics. Operand 1 is the memory location the operation is performed on.
7403 Operand 0 is an output operand which is set to the original value contained
7404 in the memory pointed to by operand 1. Operand 2 is the value to be
7405 stored. Operand 3 is the memory model to be used.
7407 If this pattern is not present, the built-in function
7408 @code{__atomic_exchange} will attempt to preform the operation with a
7409 compare and swap loop.
7411 @cindex @code{atomic_add@var{mode}} instruction pattern
7412 @cindex @code{atomic_sub@var{mode}} instruction pattern
7413 @cindex @code{atomic_or@var{mode}} instruction pattern
7414 @cindex @code{atomic_and@var{mode}} instruction pattern
7415 @cindex @code{atomic_xor@var{mode}} instruction pattern
7416 @cindex @code{atomic_nand@var{mode}} instruction pattern
7417 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
7418 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
7419 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
7420 These patterns emit code for an atomic operation on memory with memory
7421 model semantics. Operand 0 is the memory on which the atomic operation is
7422 performed. Operand 1 is the second operand to the binary operator.
7423 Operand 2 is the memory model to be used by the operation.
7425 If these patterns are not defined, attempts will be made to use legacy
7426 @code{sync} patterns, or equivalent patterns which return a result. If
7427 none of these are available a compare-and-swap loop will be used.
7429 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
7430 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
7431 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
7432 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
7433 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
7434 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
7435 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
7436 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
7437 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
7438 These patterns emit code for an atomic operation on memory with memory
7439 model semantics, and return the original value. Operand 0 is an output
7440 operand which contains the value of the memory location before the
7441 operation was performed. Operand 1 is the memory on which the atomic
7442 operation is performed. Operand 2 is the second operand to the binary
7443 operator. Operand 3 is the memory model to be used by the operation.
7445 If these patterns are not defined, attempts will be made to use legacy
7446 @code{sync} patterns. If none of these are available a compare-and-swap
7449 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
7450 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
7451 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
7452 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
7453 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
7454 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
7455 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
7456 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
7457 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
7458 These patterns emit code for an atomic operation on memory with memory
7459 model semantics and return the result after the operation is performed.
7460 Operand 0 is an output operand which contains the value after the
7461 operation. Operand 1 is the memory on which the atomic operation is
7462 performed. Operand 2 is the second operand to the binary operator.
7463 Operand 3 is the memory model to be used by the operation.
7465 If these patterns are not defined, attempts will be made to use legacy
7466 @code{sync} patterns, or equivalent patterns which return the result before
7467 the operation followed by the arithmetic operation required to produce the
7468 result. If none of these are available a compare-and-swap loop will be
7471 @cindex @code{atomic_test_and_set} instruction pattern
7472 @item @samp{atomic_test_and_set}
7473 This pattern emits code for @code{__builtin_atomic_test_and_set}.
7474 Operand 0 is an output operand which is set to true if the previous
7475 previous contents of the byte was "set", and false otherwise. Operand 1
7476 is the @code{QImode} memory to be modified. Operand 2 is the memory
7479 The specific value that defines "set" is implementation defined, and
7480 is normally based on what is performed by the native atomic test and set
7483 @cindex @code{atomic_bit_test_and_set@var{mode}} instruction pattern
7484 @cindex @code{atomic_bit_test_and_complement@var{mode}} instruction pattern
7485 @cindex @code{atomic_bit_test_and_reset@var{mode}} instruction pattern
7486 @item @samp{atomic_bit_test_and_set@var{mode}}
7487 @itemx @samp{atomic_bit_test_and_complement@var{mode}}
7488 @itemx @samp{atomic_bit_test_and_reset@var{mode}}
7489 These patterns emit code for an atomic bitwise operation on memory with memory
7490 model semantics, and return the original value of the specified bit.
7491 Operand 0 is an output operand which contains the value of the specified bit
7492 from the memory location before the operation was performed. Operand 1 is the
7493 memory on which the atomic operation is performed. Operand 2 is the bit within
7494 the operand, starting with least significant bit. Operand 3 is the memory model
7495 to be used by the operation. Operand 4 is a flag - it is @code{const1_rtx}
7496 if operand 0 should contain the original value of the specified bit in the
7497 least significant bit of the operand, and @code{const0_rtx} if the bit should
7498 be in its original position in the operand.
7499 @code{atomic_bit_test_and_set@var{mode}} atomically sets the specified bit after
7500 remembering its original value, @code{atomic_bit_test_and_complement@var{mode}}
7501 inverts the specified bit and @code{atomic_bit_test_and_reset@var{mode}} clears
7504 If these patterns are not defined, attempts will be made to use
7505 @code{atomic_fetch_or@var{mode}}, @code{atomic_fetch_xor@var{mode}} or
7506 @code{atomic_fetch_and@var{mode}} instruction patterns, or their @code{sync}
7507 counterparts. If none of these are available a compare-and-swap
7510 @cindex @code{mem_thread_fence} instruction pattern
7511 @item @samp{mem_thread_fence}
7512 This pattern emits code required to implement a thread fence with
7513 memory model semantics. Operand 0 is the memory model to be used.
7515 For the @code{__ATOMIC_RELAXED} model no instructions need to be issued
7516 and this expansion is not invoked.
7518 The compiler always emits a compiler memory barrier regardless of what
7519 expanding this pattern produced.
7521 If this pattern is not defined, the compiler falls back to expanding the
7522 @code{memory_barrier} pattern, then to emitting @code{__sync_synchronize}
7523 library call, and finally to just placing a compiler memory barrier.
7525 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
7526 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
7527 @item @samp{get_thread_pointer@var{mode}}
7528 @itemx @samp{set_thread_pointer@var{mode}}
7529 These patterns emit code that reads/sets the TLS thread pointer. Currently,
7530 these are only needed if the target needs to support the
7531 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
7534 The get/set patterns have a single output/input operand respectively,
7535 with @var{mode} intended to be @code{Pmode}.
7537 @cindex @code{stack_protect_combined_set} instruction pattern
7538 @item @samp{stack_protect_combined_set}
7539 This pattern, if defined, moves a @code{ptr_mode} value from an address
7540 whose declaration RTX is given in operand 1 to the memory in operand 0
7541 without leaving the value in a register afterward. If several
7542 instructions are needed by the target to perform the operation (eg. to
7543 load the address from a GOT entry then load the @code{ptr_mode} value
7544 and finally store it), it is the backend's responsibility to ensure no
7545 intermediate result gets spilled. This is to avoid leaking the value
7546 some place that an attacker might use to rewrite the stack guard slot
7547 after having clobbered it.
7549 If this pattern is not defined, then the address declaration is
7550 expanded first in the standard way and a @code{stack_protect_set}
7551 pattern is then generated to move the value from that address to the
7552 address in operand 0.
7554 @cindex @code{stack_protect_set} instruction pattern
7555 @item @samp{stack_protect_set}
7556 This pattern, if defined, moves a @code{ptr_mode} value from the valid
7557 memory location in operand 1 to the memory in operand 0 without leaving
7558 the value in a register afterward. This is to avoid leaking the value
7559 some place that an attacker might use to rewrite the stack guard slot
7560 after having clobbered it.
7562 Note: on targets where the addressing modes do not allow to load
7563 directly from stack guard address, the address is expanded in a standard
7564 way first which could cause some spills.
7566 If this pattern is not defined, then a plain move pattern is generated.
7568 @cindex @code{stack_protect_combined_test} instruction pattern
7569 @item @samp{stack_protect_combined_test}
7570 This pattern, if defined, compares a @code{ptr_mode} value from an
7571 address whose declaration RTX is given in operand 1 with the memory in
7572 operand 0 without leaving the value in a register afterward and
7573 branches to operand 2 if the values were equal. If several
7574 instructions are needed by the target to perform the operation (eg. to
7575 load the address from a GOT entry then load the @code{ptr_mode} value
7576 and finally store it), it is the backend's responsibility to ensure no
7577 intermediate result gets spilled. This is to avoid leaking the value
7578 some place that an attacker might use to rewrite the stack guard slot
7579 after having clobbered it.
7581 If this pattern is not defined, then the address declaration is
7582 expanded first in the standard way and a @code{stack_protect_test}
7583 pattern is then generated to compare the value from that address to the
7584 value at the memory in operand 0.
7586 @cindex @code{stack_protect_test} instruction pattern
7587 @item @samp{stack_protect_test}
7588 This pattern, if defined, compares a @code{ptr_mode} value from the
7589 valid memory location in operand 1 with the memory in operand 0 without
7590 leaving the value in a register afterward and branches to operand 2 if
7591 the values were equal.
7593 If this pattern is not defined, then a plain compare pattern and
7594 conditional branch pattern is used.
7596 @cindex @code{clear_cache} instruction pattern
7597 @item @samp{clear_cache}
7598 This pattern, if defined, flushes the instruction cache for a region of
7599 memory. The region is bounded to by the Pmode pointers in operand 0
7600 inclusive and operand 1 exclusive.
7602 If this pattern is not defined, a call to the library function
7603 @code{__clear_cache} is used.
7608 @c Each of the following nodes are wrapped in separate
7609 @c "@ifset INTERNALS" to work around memory limits for the default
7610 @c configuration in older tetex distributions. Known to not work:
7611 @c tetex-1.0.7, known to work: tetex-2.0.2.
7613 @node Pattern Ordering
7614 @section When the Order of Patterns Matters
7615 @cindex Pattern Ordering
7616 @cindex Ordering of Patterns
7618 Sometimes an insn can match more than one instruction pattern. Then the
7619 pattern that appears first in the machine description is the one used.
7620 Therefore, more specific patterns (patterns that will match fewer things)
7621 and faster instructions (those that will produce better code when they
7622 do match) should usually go first in the description.
7624 In some cases the effect of ordering the patterns can be used to hide
7625 a pattern when it is not valid. For example, the 68000 has an
7626 instruction for converting a fullword to floating point and another
7627 for converting a byte to floating point. An instruction converting
7628 an integer to floating point could match either one. We put the
7629 pattern to convert the fullword first to make sure that one will
7630 be used rather than the other. (Otherwise a large integer might
7631 be generated as a single-byte immediate quantity, which would not work.)
7632 Instead of using this pattern ordering it would be possible to make the
7633 pattern for convert-a-byte smart enough to deal properly with any
7638 @node Dependent Patterns
7639 @section Interdependence of Patterns
7640 @cindex Dependent Patterns
7641 @cindex Interdependence of Patterns
7643 In some cases machines support instructions identical except for the
7644 machine mode of one or more operands. For example, there may be
7645 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
7649 (set (match_operand:SI 0 @dots{})
7650 (extend:SI (match_operand:HI 1 @dots{})))
7652 (set (match_operand:SI 0 @dots{})
7653 (extend:SI (match_operand:QI 1 @dots{})))
7657 Constant integers do not specify a machine mode, so an instruction to
7658 extend a constant value could match either pattern. The pattern it
7659 actually will match is the one that appears first in the file. For correct
7660 results, this must be the one for the widest possible mode (@code{HImode},
7661 here). If the pattern matches the @code{QImode} instruction, the results
7662 will be incorrect if the constant value does not actually fit that mode.
7664 Such instructions to extend constants are rarely generated because they are
7665 optimized away, but they do occasionally happen in nonoptimized
7668 If a constraint in a pattern allows a constant, the reload pass may
7669 replace a register with a constant permitted by the constraint in some
7670 cases. Similarly for memory references. Because of this substitution,
7671 you should not provide separate patterns for increment and decrement
7672 instructions. Instead, they should be generated from the same pattern
7673 that supports register-register add insns by examining the operands and
7674 generating the appropriate machine instruction.
7679 @section Defining Jump Instruction Patterns
7680 @cindex jump instruction patterns
7681 @cindex defining jump instruction patterns
7683 GCC does not assume anything about how the machine realizes jumps.
7684 The machine description should define a single pattern, usually
7685 a @code{define_expand}, which expands to all the required insns.
7687 Usually, this would be a comparison insn to set the condition code
7688 and a separate branch insn testing the condition code and branching
7689 or not according to its value. For many machines, however,
7690 separating compares and branches is limiting, which is why the
7691 more flexible approach with one @code{define_expand} is used in GCC.
7692 The machine description becomes clearer for architectures that
7693 have compare-and-branch instructions but no condition code. It also
7694 works better when different sets of comparison operators are supported
7695 by different kinds of conditional branches (e.g.@: integer vs.@:
7696 floating-point), or by conditional branches with respect to conditional stores.
7698 Two separate insns are always used if the machine description represents
7699 a condition code register using the legacy RTL expression @code{(cc0)},
7700 and on most machines that use a separate condition code register
7701 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
7702 fact, the set and use of the condition code must be separate and
7703 adjacent@footnote{@code{note} insns can separate them, though.}, thus
7704 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
7705 so that the comparison and branch insns could be located from each other
7706 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
7708 Even in this case having a single entry point for conditional branches
7709 is advantageous, because it handles equally well the case where a single
7710 comparison instruction records the results of both signed and unsigned
7711 comparison of the given operands (with the branch insns coming in distinct
7712 signed and unsigned flavors) as in the x86 or SPARC, and the case where
7713 there are distinct signed and unsigned compare instructions and only
7714 one set of conditional branch instructions as in the PowerPC.
7718 @node Looping Patterns
7719 @section Defining Looping Instruction Patterns
7720 @cindex looping instruction patterns
7721 @cindex defining looping instruction patterns
7723 Some machines have special jump instructions that can be utilized to
7724 make loops more efficient. A common example is the 68000 @samp{dbra}
7725 instruction which performs a decrement of a register and a branch if the
7726 result was greater than zero. Other machines, in particular digital
7727 signal processors (DSPs), have special block repeat instructions to
7728 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
7729 DSPs have a block repeat instruction that loads special registers to
7730 mark the top and end of a loop and to count the number of loop
7731 iterations. This avoids the need for fetching and executing a
7732 @samp{dbra}-like instruction and avoids pipeline stalls associated with
7735 GCC has two special named patterns to support low overhead looping.
7736 They are @samp{doloop_begin} and @samp{doloop_end}. These are emitted
7737 by the loop optimizer for certain well-behaved loops with a finite
7738 number of loop iterations using information collected during strength
7741 The @samp{doloop_end} pattern describes the actual looping instruction
7742 (or the implicit looping operation) and the @samp{doloop_begin} pattern
7743 is an optional companion pattern that can be used for initialization
7744 needed for some low-overhead looping instructions.
7746 Note that some machines require the actual looping instruction to be
7747 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
7748 the true RTL for a looping instruction at the top of the loop can cause
7749 problems with flow analysis. So instead, a dummy @code{doloop} insn is
7750 emitted at the end of the loop. The machine dependent reorg pass checks
7751 for the presence of this @code{doloop} insn and then searches back to
7752 the top of the loop, where it inserts the true looping insn (provided
7753 there are no instructions in the loop which would cause problems). Any
7754 additional labels can be emitted at this point. In addition, if the
7755 desired special iteration counter register was not allocated, this
7756 machine dependent reorg pass could emit a traditional compare and jump
7759 For the @samp{doloop_end} pattern, the loop optimizer allocates an
7760 additional pseudo register as an iteration counter. This pseudo
7761 register cannot be used within the loop (i.e., general induction
7762 variables cannot be derived from it), however, in many cases the loop
7763 induction variable may become redundant and removed by the flow pass.
7765 The @samp{doloop_end} pattern must have a specific structure to be
7766 handled correctly by GCC. The example below is taken (slightly
7767 simplified) from the PDP-11 target:
7771 (define_expand "doloop_end"
7772 [(parallel [(set (pc)
7774 (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m")
7776 (label_ref (match_operand 1 "" ""))
7779 (plus:HI (match_dup 0)
7783 if (GET_MODE (operands[0]) != HImode)
7787 (define_insn "doloop_end_insn"
7790 (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m")
7792 (label_ref (match_operand 1 "" ""))
7795 (plus:HI (match_dup 0)
7800 if (which_alternative == 0)
7801 return "sob %0,%l1";
7804 output_asm_insn ("dec %0", operands);
7810 The first part of the pattern describes the branch condition. GCC
7811 supports three cases for the way the target machine handles the loop
7814 @item Loop terminates when the loop register decrements to zero. This
7815 is represented by a @code{ne} comparison of the register (its old value)
7816 with constant 1 (as in the example above).
7817 @item Loop terminates when the loop register decrements to @minus{}1.
7818 This is represented by a @code{ne} comparison of the register with
7820 @item Loop terminates when the loop register decrements to a negative
7821 value. This is represented by a @code{ge} comparison of the register
7822 with constant zero. For this case, GCC will attach a @code{REG_NONNEG}
7823 note to the @code{doloop_end} insn if it can determine that the register
7824 will be non-negative.
7827 Since the @code{doloop_end} insn is a jump insn that also has an output,
7828 the reload pass does not handle the output operand. Therefore, the
7829 constraint must allow for that operand to be in memory rather than a
7830 register. In the example shown above, that is handled (in the
7831 @code{doloop_end_insn} pattern) by using a loop instruction sequence
7832 that can handle memory operands when the memory alternative appears.
7834 GCC does not check the mode of the loop register operand when generating
7835 the @code{doloop_end} pattern. If the pattern is only valid for some
7836 modes but not others, the pattern should be a @code{define_expand}
7837 pattern that checks the operand mode in the preparation code, and issues
7838 @code{FAIL} if an unsupported mode is found. The example above does
7839 this, since the machine instruction to be used only exists for
7842 If the @code{doloop_end} pattern is a @code{define_expand}, there must
7843 also be a @code{define_insn} or @code{define_insn_and_split} matching
7844 the generated pattern. Otherwise, the compiler will fail during loop
7849 @node Insn Canonicalizations
7850 @section Canonicalization of Instructions
7851 @cindex canonicalization of instructions
7852 @cindex insn canonicalization
7854 There are often cases where multiple RTL expressions could represent an
7855 operation performed by a single machine instruction. This situation is
7856 most commonly encountered with logical, branch, and multiply-accumulate
7857 instructions. In such cases, the compiler attempts to convert these
7858 multiple RTL expressions into a single canonical form to reduce the
7859 number of insn patterns required.
7861 In addition to algebraic simplifications, following canonicalizations
7866 For commutative and comparison operators, a constant is always made the
7867 second operand. If a machine only supports a constant as the second
7868 operand, only patterns that match a constant in the second operand need
7872 For associative operators, a sequence of operators will always chain
7873 to the left; for instance, only the left operand of an integer @code{plus}
7874 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
7875 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
7876 @code{umax} are associative when applied to integers, and sometimes to
7880 @cindex @code{neg}, canonicalization of
7881 @cindex @code{not}, canonicalization of
7882 @cindex @code{mult}, canonicalization of
7883 @cindex @code{plus}, canonicalization of
7884 @cindex @code{minus}, canonicalization of
7885 For these operators, if only one operand is a @code{neg}, @code{not},
7886 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
7890 In combinations of @code{neg}, @code{mult}, @code{plus}, and
7891 @code{minus}, the @code{neg} operations (if any) will be moved inside
7892 the operations as far as possible. For instance,
7893 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
7894 @code{(plus (mult (neg B) C) A)} is canonicalized as
7895 @code{(minus A (mult B C))}.
7897 @cindex @code{compare}, canonicalization of
7899 For the @code{compare} operator, a constant is always the second operand
7900 if the first argument is a condition code register or @code{(cc0)}.
7903 For instructions that inherently set a condition code register, the
7904 @code{compare} operator is always written as the first RTL expression of
7905 the @code{parallel} instruction pattern. For example,
7909 [(set (reg:CCZ FLAGS_REG)
7912 (match_operand:SI 1 "register_operand" "%r")
7913 (match_operand:SI 2 "register_operand" "r"))
7915 (set (match_operand:SI 0 "register_operand" "=r")
7916 (plus:SI (match_dup 1) (match_dup 2)))]
7922 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
7923 @code{minus} is made the first operand under the same conditions as
7927 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
7928 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
7932 @code{(minus @var{x} (const_int @var{n}))} is converted to
7933 @code{(plus @var{x} (const_int @var{-n}))}.
7936 Within address computations (i.e., inside @code{mem}), a left shift is
7937 converted into the appropriate multiplication by a power of two.
7939 @cindex @code{ior}, canonicalization of
7940 @cindex @code{and}, canonicalization of
7941 @cindex De Morgan's law
7943 De Morgan's Law is used to move bitwise negation inside a bitwise
7944 logical-and or logical-or operation. If this results in only one
7945 operand being a @code{not} expression, it will be the first one.
7947 A machine that has an instruction that performs a bitwise logical-and of one
7948 operand with the bitwise negation of the other should specify the pattern
7949 for that instruction as
7953 [(set (match_operand:@var{m} 0 @dots{})
7954 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7955 (match_operand:@var{m} 2 @dots{})))]
7961 Similarly, a pattern for a ``NAND'' instruction should be written
7965 [(set (match_operand:@var{m} 0 @dots{})
7966 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7967 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
7972 In both cases, it is not necessary to include patterns for the many
7973 logically equivalent RTL expressions.
7975 @cindex @code{xor}, canonicalization of
7977 The only possible RTL expressions involving both bitwise exclusive-or
7978 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
7979 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
7982 The sum of three items, one of which is a constant, will only appear in
7986 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
7989 @cindex @code{zero_extract}, canonicalization of
7990 @cindex @code{sign_extract}, canonicalization of
7992 Equality comparisons of a group of bits (usually a single bit) with zero
7993 will be written using @code{zero_extract} rather than the equivalent
7994 @code{and} or @code{sign_extract} operations.
7996 @cindex @code{mult}, canonicalization of
7998 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
7999 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
8000 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
8001 for @code{zero_extend}.
8004 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
8005 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
8006 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
8007 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
8008 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
8009 operand of @code{mult} is also a shift, then that is extended also.
8010 This transformation is only applied when it can be proven that the
8011 original operation had sufficient precision to prevent overflow.
8015 Further canonicalization rules are defined in the function
8016 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
8020 @node Expander Definitions
8021 @section Defining RTL Sequences for Code Generation
8022 @cindex expander definitions
8023 @cindex code generation RTL sequences
8024 @cindex defining RTL sequences for code generation
8026 On some target machines, some standard pattern names for RTL generation
8027 cannot be handled with single insn, but a sequence of RTL insns can
8028 represent them. For these target machines, you can write a
8029 @code{define_expand} to specify how to generate the sequence of RTL@.
8031 @findex define_expand
8032 A @code{define_expand} is an RTL expression that looks almost like a
8033 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
8034 only for RTL generation and it can produce more than one RTL insn.
8036 A @code{define_expand} RTX has four operands:
8040 The name. Each @code{define_expand} must have a name, since the only
8041 use for it is to refer to it by name.
8044 The RTL template. This is a vector of RTL expressions representing
8045 a sequence of separate instructions. Unlike @code{define_insn}, there
8046 is no implicit surrounding @code{PARALLEL}.
8049 The condition, a string containing a C expression. This expression is
8050 used to express how the availability of this pattern depends on
8051 subclasses of target machine, selected by command-line options when GCC
8052 is run. This is just like the condition of a @code{define_insn} that
8053 has a standard name. Therefore, the condition (if present) may not
8054 depend on the data in the insn being matched, but only the
8055 target-machine-type flags. The compiler needs to test these conditions
8056 during initialization in order to learn exactly which named instructions
8057 are available in a particular run.
8060 The preparation statements, a string containing zero or more C
8061 statements which are to be executed before RTL code is generated from
8064 Usually these statements prepare temporary registers for use as
8065 internal operands in the RTL template, but they can also generate RTL
8066 insns directly by calling routines such as @code{emit_insn}, etc.
8067 Any such insns precede the ones that come from the RTL template.
8070 Optionally, a vector containing the values of attributes. @xref{Insn
8074 Every RTL insn emitted by a @code{define_expand} must match some
8075 @code{define_insn} in the machine description. Otherwise, the compiler
8076 will crash when trying to generate code for the insn or trying to optimize
8079 The RTL template, in addition to controlling generation of RTL insns,
8080 also describes the operands that need to be specified when this pattern
8081 is used. In particular, it gives a predicate for each operand.
8083 A true operand, which needs to be specified in order to generate RTL from
8084 the pattern, should be described with a @code{match_operand} in its first
8085 occurrence in the RTL template. This enters information on the operand's
8086 predicate into the tables that record such things. GCC uses the
8087 information to preload the operand into a register if that is required for
8088 valid RTL code. If the operand is referred to more than once, subsequent
8089 references should use @code{match_dup}.
8091 The RTL template may also refer to internal ``operands'' which are
8092 temporary registers or labels used only within the sequence made by the
8093 @code{define_expand}. Internal operands are substituted into the RTL
8094 template with @code{match_dup}, never with @code{match_operand}. The
8095 values of the internal operands are not passed in as arguments by the
8096 compiler when it requests use of this pattern. Instead, they are computed
8097 within the pattern, in the preparation statements. These statements
8098 compute the values and store them into the appropriate elements of
8099 @code{operands} so that @code{match_dup} can find them.
8101 There are two special macros defined for use in the preparation statements:
8102 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8109 Use the @code{DONE} macro to end RTL generation for the pattern. The
8110 only RTL insns resulting from the pattern on this occasion will be
8111 those already emitted by explicit calls to @code{emit_insn} within the
8112 preparation statements; the RTL template will not be generated.
8116 Make the pattern fail on this occasion. When a pattern fails, it means
8117 that the pattern was not truly available. The calling routines in the
8118 compiler will try other strategies for code generation using other patterns.
8120 Failure is currently supported only for binary (addition, multiplication,
8121 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
8125 If the preparation falls through (invokes neither @code{DONE} nor
8126 @code{FAIL}), then the @code{define_expand} acts like a
8127 @code{define_insn} in that the RTL template is used to generate the
8130 The RTL template is not used for matching, only for generating the
8131 initial insn list. If the preparation statement always invokes
8132 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
8133 list of operands, such as this example:
8137 (define_expand "addsi3"
8138 [(match_operand:SI 0 "register_operand" "")
8139 (match_operand:SI 1 "register_operand" "")
8140 (match_operand:SI 2 "register_operand" "")]
8146 handle_add (operands[0], operands[1], operands[2]);
8152 Here is an example, the definition of left-shift for the SPUR chip:
8156 (define_expand "ashlsi3"
8157 [(set (match_operand:SI 0 "register_operand" "")
8161 (match_operand:SI 1 "register_operand" "")
8162 (match_operand:SI 2 "nonmemory_operand" "")))]
8171 if (GET_CODE (operands[2]) != CONST_INT
8172 || (unsigned) INTVAL (operands[2]) > 3)
8179 This example uses @code{define_expand} so that it can generate an RTL insn
8180 for shifting when the shift-count is in the supported range of 0 to 3 but
8181 fail in other cases where machine insns aren't available. When it fails,
8182 the compiler tries another strategy using different patterns (such as, a
8185 If the compiler were able to handle nontrivial condition-strings in
8186 patterns with names, then it would be possible to use a
8187 @code{define_insn} in that case. Here is another case (zero-extension
8188 on the 68000) which makes more use of the power of @code{define_expand}:
8191 (define_expand "zero_extendhisi2"
8192 [(set (match_operand:SI 0 "general_operand" "")
8194 (set (strict_low_part
8198 (match_operand:HI 1 "general_operand" ""))]
8200 "operands[1] = make_safe_from (operands[1], operands[0]);")
8204 @findex make_safe_from
8205 Here two RTL insns are generated, one to clear the entire output operand
8206 and the other to copy the input operand into its low half. This sequence
8207 is incorrect if the input operand refers to [the old value of] the output
8208 operand, so the preparation statement makes sure this isn't so. The
8209 function @code{make_safe_from} copies the @code{operands[1]} into a
8210 temporary register if it refers to @code{operands[0]}. It does this
8211 by emitting another RTL insn.
8213 Finally, a third example shows the use of an internal operand.
8214 Zero-extension on the SPUR chip is done by @code{and}-ing the result
8215 against a halfword mask. But this mask cannot be represented by a
8216 @code{const_int} because the constant value is too large to be legitimate
8217 on this machine. So it must be copied into a register with
8218 @code{force_reg} and then the register used in the @code{and}.
8221 (define_expand "zero_extendhisi2"
8222 [(set (match_operand:SI 0 "register_operand" "")
8224 (match_operand:HI 1 "register_operand" "")
8229 = force_reg (SImode, GEN_INT (65535)); ")
8232 @emph{Note:} If the @code{define_expand} is used to serve a
8233 standard binary or unary arithmetic operation or a bit-field operation,
8234 then the last insn it generates must not be a @code{code_label},
8235 @code{barrier} or @code{note}. It must be an @code{insn},
8236 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
8237 at the end, emit an insn to copy the result of the operation into
8238 itself. Such an insn will generate no code, but it can avoid problems
8243 @node Insn Splitting
8244 @section Defining How to Split Instructions
8245 @cindex insn splitting
8246 @cindex instruction splitting
8247 @cindex splitting instructions
8249 There are two cases where you should specify how to split a pattern
8250 into multiple insns. On machines that have instructions requiring
8251 delay slots (@pxref{Delay Slots}) or that have instructions whose
8252 output is not available for multiple cycles (@pxref{Processor pipeline
8253 description}), the compiler phases that optimize these cases need to
8254 be able to move insns into one-instruction delay slots. However, some
8255 insns may generate more than one machine instruction. These insns
8256 cannot be placed into a delay slot.
8258 Often you can rewrite the single insn as a list of individual insns,
8259 each corresponding to one machine instruction. The disadvantage of
8260 doing so is that it will cause the compilation to be slower and require
8261 more space. If the resulting insns are too complex, it may also
8262 suppress some optimizations. The compiler splits the insn if there is a
8263 reason to believe that it might improve instruction or delay slot
8266 The insn combiner phase also splits putative insns. If three insns are
8267 merged into one insn with a complex expression that cannot be matched by
8268 some @code{define_insn} pattern, the combiner phase attempts to split
8269 the complex pattern into two insns that are recognized. Usually it can
8270 break the complex pattern into two patterns by splitting out some
8271 subexpression. However, in some other cases, such as performing an
8272 addition of a large constant in two insns on a RISC machine, the way to
8273 split the addition into two insns is machine-dependent.
8275 @findex define_split
8276 The @code{define_split} definition tells the compiler how to split a
8277 complex insn into several simpler insns. It looks like this:
8281 [@var{insn-pattern}]
8283 [@var{new-insn-pattern-1}
8284 @var{new-insn-pattern-2}
8286 "@var{preparation-statements}")
8289 @var{insn-pattern} is a pattern that needs to be split and
8290 @var{condition} is the final condition to be tested, as in a
8291 @code{define_insn}. When an insn matching @var{insn-pattern} and
8292 satisfying @var{condition} is found, it is replaced in the insn list
8293 with the insns given by @var{new-insn-pattern-1},
8294 @var{new-insn-pattern-2}, etc.
8296 The @var{preparation-statements} are similar to those statements that
8297 are specified for @code{define_expand} (@pxref{Expander Definitions})
8298 and are executed before the new RTL is generated to prepare for the
8299 generated code or emit some insns whose pattern is not fixed. Unlike
8300 those in @code{define_expand}, however, these statements must not
8301 generate any new pseudo-registers. Once reload has completed, they also
8302 must not allocate any space in the stack frame.
8304 There are two special macros defined for use in the preparation statements:
8305 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8312 Use the @code{DONE} macro to end RTL generation for the splitter. The
8313 only RTL insns generated as replacement for the matched input insn will
8314 be those already emitted by explicit calls to @code{emit_insn} within
8315 the preparation statements; the replacement pattern is not used.
8319 Make the @code{define_split} fail on this occasion. When a @code{define_split}
8320 fails, it means that the splitter was not truly available for the inputs
8321 it was given, and the input insn will not be split.
8324 If the preparation falls through (invokes neither @code{DONE} nor
8325 @code{FAIL}), then the @code{define_split} uses the replacement
8328 Patterns are matched against @var{insn-pattern} in two different
8329 circumstances. If an insn needs to be split for delay slot scheduling
8330 or insn scheduling, the insn is already known to be valid, which means
8331 that it must have been matched by some @code{define_insn} and, if
8332 @code{reload_completed} is nonzero, is known to satisfy the constraints
8333 of that @code{define_insn}. In that case, the new insn patterns must
8334 also be insns that are matched by some @code{define_insn} and, if
8335 @code{reload_completed} is nonzero, must also satisfy the constraints
8336 of those definitions.
8338 As an example of this usage of @code{define_split}, consider the following
8339 example from @file{a29k.md}, which splits a @code{sign_extend} from
8340 @code{HImode} to @code{SImode} into a pair of shift insns:
8344 [(set (match_operand:SI 0 "gen_reg_operand" "")
8345 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
8348 (ashift:SI (match_dup 1)
8351 (ashiftrt:SI (match_dup 0)
8354 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
8357 When the combiner phase tries to split an insn pattern, it is always the
8358 case that the pattern is @emph{not} matched by any @code{define_insn}.
8359 The combiner pass first tries to split a single @code{set} expression
8360 and then the same @code{set} expression inside a @code{parallel}, but
8361 followed by a @code{clobber} of a pseudo-reg to use as a scratch
8362 register. In these cases, the combiner expects exactly two new insn
8363 patterns to be generated. It will verify that these patterns match some
8364 @code{define_insn} definitions, so you need not do this test in the
8365 @code{define_split} (of course, there is no point in writing a
8366 @code{define_split} that will never produce insns that match).
8368 Here is an example of this use of @code{define_split}, taken from
8373 [(set (match_operand:SI 0 "gen_reg_operand" "")
8374 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
8375 (match_operand:SI 2 "non_add_cint_operand" "")))]
8377 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
8378 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
8381 int low = INTVAL (operands[2]) & 0xffff;
8382 int high = (unsigned) INTVAL (operands[2]) >> 16;
8385 high++, low |= 0xffff0000;
8387 operands[3] = GEN_INT (high << 16);
8388 operands[4] = GEN_INT (low);
8392 Here the predicate @code{non_add_cint_operand} matches any
8393 @code{const_int} that is @emph{not} a valid operand of a single add
8394 insn. The add with the smaller displacement is written so that it
8395 can be substituted into the address of a subsequent operation.
8397 An example that uses a scratch register, from the same file, generates
8398 an equality comparison of a register and a large constant:
8402 [(set (match_operand:CC 0 "cc_reg_operand" "")
8403 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
8404 (match_operand:SI 2 "non_short_cint_operand" "")))
8405 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
8406 "find_single_use (operands[0], insn, 0)
8407 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
8408 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
8409 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
8410 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
8413 /* @r{Get the constant we are comparing against, C, and see what it
8414 looks like sign-extended to 16 bits. Then see what constant
8415 could be XOR'ed with C to get the sign-extended value.} */
8417 int c = INTVAL (operands[2]);
8418 int sextc = (c << 16) >> 16;
8419 int xorv = c ^ sextc;
8421 operands[4] = GEN_INT (xorv);
8422 operands[5] = GEN_INT (sextc);
8426 To avoid confusion, don't write a single @code{define_split} that
8427 accepts some insns that match some @code{define_insn} as well as some
8428 insns that don't. Instead, write two separate @code{define_split}
8429 definitions, one for the insns that are valid and one for the insns that
8432 The splitter is allowed to split jump instructions into sequence of
8433 jumps or create new jumps in while splitting non-jump instructions. As
8434 the control flow graph and branch prediction information needs to be updated,
8435 several restriction apply.
8437 Splitting of jump instruction into sequence that over by another jump
8438 instruction is always valid, as compiler expect identical behavior of new
8439 jump. When new sequence contains multiple jump instructions or new labels,
8440 more assistance is needed. Splitter is required to create only unconditional
8441 jumps, or simple conditional jump instructions. Additionally it must attach a
8442 @code{REG_BR_PROB} note to each conditional jump. A global variable
8443 @code{split_branch_probability} holds the probability of the original branch in case
8444 it was a simple conditional jump, @minus{}1 otherwise. To simplify
8445 recomputing of edge frequencies, the new sequence is required to have only
8446 forward jumps to the newly created labels.
8448 @findex define_insn_and_split
8449 For the common case where the pattern of a define_split exactly matches the
8450 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
8454 (define_insn_and_split
8455 [@var{insn-pattern}]
8457 "@var{output-template}"
8458 "@var{split-condition}"
8459 [@var{new-insn-pattern-1}
8460 @var{new-insn-pattern-2}
8462 "@var{preparation-statements}"
8463 [@var{insn-attributes}])
8467 @var{insn-pattern}, @var{condition}, @var{output-template}, and
8468 @var{insn-attributes} are used as in @code{define_insn}. The
8469 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
8470 in a @code{define_split}. The @var{split-condition} is also used as in
8471 @code{define_split}, with the additional behavior that if the condition starts
8472 with @samp{&&}, the condition used for the split will be the constructed as a
8473 logical ``and'' of the split condition with the insn condition. For example,
8477 (define_insn_and_split "zero_extendhisi2_and"
8478 [(set (match_operand:SI 0 "register_operand" "=r")
8479 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
8480 (clobber (reg:CC 17))]
8481 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
8483 "&& reload_completed"
8484 [(parallel [(set (match_dup 0)
8485 (and:SI (match_dup 0) (const_int 65535)))
8486 (clobber (reg:CC 17))])]
8488 [(set_attr "type" "alu1")])
8492 In this case, the actual split condition will be
8493 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
8495 The @code{define_insn_and_split} construction provides exactly the same
8496 functionality as two separate @code{define_insn} and @code{define_split}
8497 patterns. It exists for compactness, and as a maintenance tool to prevent
8498 having to ensure the two patterns' templates match.
8500 @findex define_insn_and_rewrite
8501 It is sometimes useful to have a @code{define_insn_and_split}
8502 that replaces specific operands of an instruction but leaves the
8503 rest of the instruction pattern unchanged. You can do this directly
8504 with a @code{define_insn_and_split}, but it requires a
8505 @var{new-insn-pattern-1} that repeats most of the original @var{insn-pattern}.
8506 There is also the complication that an implicit @code{parallel} in
8507 @var{insn-pattern} must become an explicit @code{parallel} in
8508 @var{new-insn-pattern-1}, which is easy to overlook.
8509 A simpler alternative is to use @code{define_insn_and_rewrite}, which
8510 is a form of @code{define_insn_and_split} that automatically generates
8511 @var{new-insn-pattern-1} by replacing each @code{match_operand}
8512 in @var{insn-pattern} with a corresponding @code{match_dup}, and each
8513 @code{match_operator} in the pattern with a corresponding @code{match_op_dup}.
8514 The arguments are otherwise identical to @code{define_insn_and_split}:
8517 (define_insn_and_rewrite
8518 [@var{insn-pattern}]
8520 "@var{output-template}"
8521 "@var{split-condition}"
8522 "@var{preparation-statements}"
8523 [@var{insn-attributes}])
8526 The @code{match_dup}s and @code{match_op_dup}s in the new
8527 instruction pattern use any new operand values that the
8528 @var{preparation-statements} store in the @code{operands} array,
8529 as for a normal @code{define_insn_and_split}. @var{preparation-statements}
8530 can also emit additional instructions before the new instruction.
8531 They can even emit an entirely different sequence of instructions and
8532 use @code{DONE} to avoid emitting a new form of the original
8535 The split in a @code{define_insn_and_rewrite} is only intended
8536 to apply to existing instructions that match @var{insn-pattern}.
8537 @var{split-condition} must therefore start with @code{&&},
8538 so that the split condition applies on top of @var{condition}.
8540 Here is an example from the AArch64 SVE port, in which operand 1 is
8541 known to be equivalent to an all-true constant and isn't used by the
8545 (define_insn_and_rewrite "*while_ult<GPI:mode><PRED_ALL:mode>_cc"
8546 [(set (reg:CC CC_REGNUM)
8548 (unspec:SI [(match_operand:PRED_ALL 1)
8550 [(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")
8551 (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")]
8555 (set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
8556 (unspec:PRED_ALL [(match_dup 2)
8560 "whilelo\t%0.<PRED_ALL:Vetype>, %<w>2, %<w>3"
8561 ;; Force the compiler to drop the unused predicate operand, so that we
8562 ;; don't have an unnecessary PTRUE.
8563 "&& !CONSTANT_P (operands[1])"
8565 operands[1] = CONSTM1_RTX (<MODE>mode);
8570 The splitter in this case simply replaces operand 1 with the constant
8571 value that it is known to have. The equivalent @code{define_insn_and_split}
8575 (define_insn_and_split "*while_ult<GPI:mode><PRED_ALL:mode>_cc"
8576 [(set (reg:CC CC_REGNUM)
8578 (unspec:SI [(match_operand:PRED_ALL 1)
8580 [(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")
8581 (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")]
8585 (set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
8586 (unspec:PRED_ALL [(match_dup 2)
8590 "whilelo\t%0.<PRED_ALL:Vetype>, %<w>2, %<w>3"
8591 ;; Force the compiler to drop the unused predicate operand, so that we
8592 ;; don't have an unnecessary PTRUE.
8593 "&& !CONSTANT_P (operands[1])"
8595 [(set (reg:CC CC_REGNUM)
8597 (unspec:SI [(match_dup 1)
8598 (unspec:PRED_ALL [(match_dup 2)
8604 (unspec:PRED_ALL [(match_dup 2)
8606 UNSPEC_WHILE_LO))])]
8608 operands[1] = CONSTM1_RTX (<MODE>mode);
8615 @node Including Patterns
8616 @section Including Patterns in Machine Descriptions.
8617 @cindex insn includes
8620 The @code{include} pattern tells the compiler tools where to
8621 look for patterns that are in files other than in the file
8622 @file{.md}. This is used only at build time and there is no preprocessing allowed.
8636 (include "filestuff")
8640 Where @var{pathname} is a string that specifies the location of the file,
8641 specifies the include file to be in @file{gcc/config/target/filestuff}. The
8642 directory @file{gcc/config/target} is regarded as the default directory.
8645 Machine descriptions may be split up into smaller more manageable subsections
8646 and placed into subdirectories.
8652 (include "BOGUS/filestuff")
8656 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
8658 Specifying an absolute path for the include file such as;
8661 (include "/u2/BOGUS/filestuff")
8664 is permitted but is not encouraged.
8666 @subsection RTL Generation Tool Options for Directory Search
8667 @cindex directory options .md
8668 @cindex options, directory search
8669 @cindex search options
8671 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
8676 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
8681 Add the directory @var{dir} to the head of the list of directories to be
8682 searched for header files. This can be used to override a system machine definition
8683 file, substituting your own version, since these directories are
8684 searched before the default machine description file directories. If you use more than
8685 one @option{-I} option, the directories are scanned in left-to-right
8686 order; the standard default directory come after.
8691 @node Peephole Definitions
8692 @section Machine-Specific Peephole Optimizers
8693 @cindex peephole optimizer definitions
8694 @cindex defining peephole optimizers
8696 In addition to instruction patterns the @file{md} file may contain
8697 definitions of machine-specific peephole optimizations.
8699 The combiner does not notice certain peephole optimizations when the data
8700 flow in the program does not suggest that it should try them. For example,
8701 sometimes two consecutive insns related in purpose can be combined even
8702 though the second one does not appear to use a register computed in the
8703 first one. A machine-specific peephole optimizer can detect such
8706 There are two forms of peephole definitions that may be used. The
8707 original @code{define_peephole} is run at assembly output time to
8708 match insns and substitute assembly text. Use of @code{define_peephole}
8711 A newer @code{define_peephole2} matches insns and substitutes new
8712 insns. The @code{peephole2} pass is run after register allocation
8713 but before scheduling, which may result in much better code for
8714 targets that do scheduling.
8717 * define_peephole:: RTL to Text Peephole Optimizers
8718 * define_peephole2:: RTL to RTL Peephole Optimizers
8723 @node define_peephole
8724 @subsection RTL to Text Peephole Optimizers
8725 @findex define_peephole
8728 A definition looks like this:
8732 [@var{insn-pattern-1}
8733 @var{insn-pattern-2}
8737 "@var{optional-insn-attributes}")
8741 The last string operand may be omitted if you are not using any
8742 machine-specific information in this machine description. If present,
8743 it must obey the same rules as in a @code{define_insn}.
8745 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
8746 consecutive insns. The optimization applies to a sequence of insns when
8747 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
8748 the next, and so on.
8750 Each of the insns matched by a peephole must also match a
8751 @code{define_insn}. Peepholes are checked only at the last stage just
8752 before code generation, and only optionally. Therefore, any insn which
8753 would match a peephole but no @code{define_insn} will cause a crash in code
8754 generation in an unoptimized compilation, or at various optimization
8757 The operands of the insns are matched with @code{match_operands},
8758 @code{match_operator}, and @code{match_dup}, as usual. What is not
8759 usual is that the operand numbers apply to all the insn patterns in the
8760 definition. So, you can check for identical operands in two insns by
8761 using @code{match_operand} in one insn and @code{match_dup} in the
8764 The operand constraints used in @code{match_operand} patterns do not have
8765 any direct effect on the applicability of the peephole, but they will
8766 be validated afterward, so make sure your constraints are general enough
8767 to apply whenever the peephole matches. If the peephole matches
8768 but the constraints are not satisfied, the compiler will crash.
8770 It is safe to omit constraints in all the operands of the peephole; or
8771 you can write constraints which serve as a double-check on the criteria
8774 Once a sequence of insns matches the patterns, the @var{condition} is
8775 checked. This is a C expression which makes the final decision whether to
8776 perform the optimization (we do so if the expression is nonzero). If
8777 @var{condition} is omitted (in other words, the string is empty) then the
8778 optimization is applied to every sequence of insns that matches the
8781 The defined peephole optimizations are applied after register allocation
8782 is complete. Therefore, the peephole definition can check which
8783 operands have ended up in which kinds of registers, just by looking at
8786 @findex prev_active_insn
8787 The way to refer to the operands in @var{condition} is to write
8788 @code{operands[@var{i}]} for operand number @var{i} (as matched by
8789 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
8790 to refer to the last of the insns being matched; use
8791 @code{prev_active_insn} to find the preceding insns.
8793 @findex dead_or_set_p
8794 When optimizing computations with intermediate results, you can use
8795 @var{condition} to match only when the intermediate results are not used
8796 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
8797 @var{op})}, where @var{insn} is the insn in which you expect the value
8798 to be used for the last time (from the value of @code{insn}, together
8799 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
8800 value (from @code{operands[@var{i}]}).
8802 Applying the optimization means replacing the sequence of insns with one
8803 new insn. The @var{template} controls ultimate output of assembler code
8804 for this combined insn. It works exactly like the template of a
8805 @code{define_insn}. Operand numbers in this template are the same ones
8806 used in matching the original sequence of insns.
8808 The result of a defined peephole optimizer does not need to match any of
8809 the insn patterns in the machine description; it does not even have an
8810 opportunity to match them. The peephole optimizer definition itself serves
8811 as the insn pattern to control how the insn is output.
8813 Defined peephole optimizers are run as assembler code is being output,
8814 so the insns they produce are never combined or rearranged in any way.
8816 Here is an example, taken from the 68000 machine description:
8820 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
8821 (set (match_operand:DF 0 "register_operand" "=f")
8822 (match_operand:DF 1 "register_operand" "ad"))]
8823 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
8826 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8828 output_asm_insn ("move.l %1,(sp)", xoperands);
8829 output_asm_insn ("move.l %1,-(sp)", operands);
8830 return "fmove.d (sp)+,%0";
8832 output_asm_insn ("movel %1,sp@@", xoperands);
8833 output_asm_insn ("movel %1,sp@@-", operands);
8834 return "fmoved sp@@+,%0";
8840 The effect of this optimization is to change
8866 If a peephole matches a sequence including one or more jump insns, you must
8867 take account of the flags such as @code{CC_REVERSED} which specify that the
8868 condition codes are represented in an unusual manner. The compiler
8869 automatically alters any ordinary conditional jumps which occur in such
8870 situations, but the compiler cannot alter jumps which have been replaced by
8871 peephole optimizations. So it is up to you to alter the assembler code
8872 that the peephole produces. Supply C code to write the assembler output,
8873 and in this C code check the condition code status flags and change the
8874 assembler code as appropriate.
8877 @var{insn-pattern-1} and so on look @emph{almost} like the second
8878 operand of @code{define_insn}. There is one important difference: the
8879 second operand of @code{define_insn} consists of one or more RTX's
8880 enclosed in square brackets. Usually, there is only one: then the same
8881 action can be written as an element of a @code{define_peephole}. But
8882 when there are multiple actions in a @code{define_insn}, they are
8883 implicitly enclosed in a @code{parallel}. Then you must explicitly
8884 write the @code{parallel}, and the square brackets within it, in the
8885 @code{define_peephole}. Thus, if an insn pattern looks like this,
8888 (define_insn "divmodsi4"
8889 [(set (match_operand:SI 0 "general_operand" "=d")
8890 (div:SI (match_operand:SI 1 "general_operand" "0")
8891 (match_operand:SI 2 "general_operand" "dmsK")))
8892 (set (match_operand:SI 3 "general_operand" "=d")
8893 (mod:SI (match_dup 1) (match_dup 2)))]
8895 "divsl%.l %2,%3:%0")
8899 then the way to mention this insn in a peephole is as follows:
8905 [(set (match_operand:SI 0 "general_operand" "=d")
8906 (div:SI (match_operand:SI 1 "general_operand" "0")
8907 (match_operand:SI 2 "general_operand" "dmsK")))
8908 (set (match_operand:SI 3 "general_operand" "=d")
8909 (mod:SI (match_dup 1) (match_dup 2)))])
8916 @node define_peephole2
8917 @subsection RTL to RTL Peephole Optimizers
8918 @findex define_peephole2
8920 The @code{define_peephole2} definition tells the compiler how to
8921 substitute one sequence of instructions for another sequence,
8922 what additional scratch registers may be needed and what their
8927 [@var{insn-pattern-1}
8928 @var{insn-pattern-2}
8931 [@var{new-insn-pattern-1}
8932 @var{new-insn-pattern-2}
8934 "@var{preparation-statements}")
8937 The definition is almost identical to @code{define_split}
8938 (@pxref{Insn Splitting}) except that the pattern to match is not a
8939 single instruction, but a sequence of instructions.
8941 It is possible to request additional scratch registers for use in the
8942 output template. If appropriate registers are not free, the pattern
8943 will simply not match.
8945 @findex match_scratch
8947 Scratch registers are requested with a @code{match_scratch} pattern at
8948 the top level of the input pattern. The allocated register (initially) will
8949 be dead at the point requested within the original sequence. If the scratch
8950 is used at more than a single point, a @code{match_dup} pattern at the
8951 top level of the input pattern marks the last position in the input sequence
8952 at which the register must be available.
8954 Here is an example from the IA-32 machine description:
8958 [(match_scratch:SI 2 "r")
8959 (parallel [(set (match_operand:SI 0 "register_operand" "")
8960 (match_operator:SI 3 "arith_or_logical_operator"
8962 (match_operand:SI 1 "memory_operand" "")]))
8963 (clobber (reg:CC 17))])]
8964 "! optimize_size && ! TARGET_READ_MODIFY"
8965 [(set (match_dup 2) (match_dup 1))
8966 (parallel [(set (match_dup 0)
8967 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
8968 (clobber (reg:CC 17))])]
8973 This pattern tries to split a load from its use in the hopes that we'll be
8974 able to schedule around the memory load latency. It allocates a single
8975 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
8976 to be live only at the point just before the arithmetic.
8978 A real example requiring extended scratch lifetimes is harder to come by,
8979 so here's a silly made-up example:
8983 [(match_scratch:SI 4 "r")
8984 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
8985 (set (match_operand:SI 2 "" "") (match_dup 1))
8987 (set (match_operand:SI 3 "" "") (match_dup 1))]
8988 "/* @r{determine 1 does not overlap 0 and 2} */"
8989 [(set (match_dup 4) (match_dup 1))
8990 (set (match_dup 0) (match_dup 4))
8991 (set (match_dup 2) (match_dup 4))
8992 (set (match_dup 3) (match_dup 4))]
8996 There are two special macros defined for use in the preparation statements:
8997 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
9004 Use the @code{DONE} macro to end RTL generation for the peephole. The
9005 only RTL insns generated as replacement for the matched input insn will
9006 be those already emitted by explicit calls to @code{emit_insn} within
9007 the preparation statements; the replacement pattern is not used.
9011 Make the @code{define_peephole2} fail on this occasion. When a @code{define_peephole2}
9012 fails, it means that the replacement was not truly available for the
9013 particular inputs it was given. In that case, GCC may still apply a
9014 later @code{define_peephole2} that also matches the given insn pattern.
9015 (Note that this is different from @code{define_split}, where @code{FAIL}
9016 prevents the input insn from being split at all.)
9019 If the preparation falls through (invokes neither @code{DONE} nor
9020 @code{FAIL}), then the @code{define_peephole2} uses the replacement
9024 If we had not added the @code{(match_dup 4)} in the middle of the input
9025 sequence, it might have been the case that the register we chose at the
9026 beginning of the sequence is killed by the first or second @code{set}.
9030 @node Insn Attributes
9031 @section Instruction Attributes
9032 @cindex insn attributes
9033 @cindex instruction attributes
9035 In addition to describing the instruction supported by the target machine,
9036 the @file{md} file also defines a group of @dfn{attributes} and a set of
9037 values for each. Every generated insn is assigned a value for each attribute.
9038 One possible attribute would be the effect that the insn has on the machine's
9039 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
9040 to track the condition codes.
9043 * Defining Attributes:: Specifying attributes and their values.
9044 * Expressions:: Valid expressions for attribute values.
9045 * Tagging Insns:: Assigning attribute values to insns.
9046 * Attr Example:: An example of assigning attributes.
9047 * Insn Lengths:: Computing the length of insns.
9048 * Constant Attributes:: Defining attributes that are constant.
9049 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
9050 * Delay Slots:: Defining delay slots required for a machine.
9051 * Processor pipeline description:: Specifying information for insn scheduling.
9056 @node Defining Attributes
9057 @subsection Defining Attributes and their Values
9058 @cindex defining attributes and their values
9059 @cindex attributes, defining
9062 The @code{define_attr} expression is used to define each attribute required
9063 by the target machine. It looks like:
9066 (define_attr @var{name} @var{list-of-values} @var{default})
9069 @var{name} is a string specifying the name of the attribute being
9070 defined. Some attributes are used in a special way by the rest of the
9071 compiler. The @code{enabled} attribute can be used to conditionally
9072 enable or disable insn alternatives (@pxref{Disable Insn
9073 Alternatives}). The @code{predicable} attribute, together with a
9074 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
9075 be used to automatically generate conditional variants of instruction
9076 patterns. The @code{mnemonic} attribute can be used to check for the
9077 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
9078 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
9079 so they should not be used elsewhere as alternative names.
9081 @var{list-of-values} is either a string that specifies a comma-separated
9082 list of values that can be assigned to the attribute, or a null string to
9083 indicate that the attribute takes numeric values.
9085 @var{default} is an attribute expression that gives the value of this
9086 attribute for insns that match patterns whose definition does not include
9087 an explicit value for this attribute. @xref{Attr Example}, for more
9088 information on the handling of defaults. @xref{Constant Attributes},
9089 for information on attributes that do not depend on any particular insn.
9092 For each defined attribute, a number of definitions are written to the
9093 @file{insn-attr.h} file. For cases where an explicit set of values is
9094 specified for an attribute, the following are defined:
9098 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
9101 An enumerated class is defined for @samp{attr_@var{name}} with
9102 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
9103 the attribute name and value are first converted to uppercase.
9106 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
9107 returns the attribute value for that insn.
9110 For example, if the following is present in the @file{md} file:
9113 (define_attr "type" "branch,fp,load,store,arith" @dots{})
9117 the following lines will be written to the file @file{insn-attr.h}.
9120 #define HAVE_ATTR_type 1
9121 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
9122 TYPE_STORE, TYPE_ARITH@};
9123 extern enum attr_type get_attr_type ();
9126 If the attribute takes numeric values, no @code{enum} type will be
9127 defined and the function to obtain the attribute's value will return
9130 There are attributes which are tied to a specific meaning. These
9131 attributes are not free to use for other purposes:
9135 The @code{length} attribute is used to calculate the length of emitted
9136 code chunks. This is especially important when verifying branch
9137 distances. @xref{Insn Lengths}.
9140 The @code{enabled} attribute can be defined to prevent certain
9141 alternatives of an insn definition from being used during code
9142 generation. @xref{Disable Insn Alternatives}.
9145 The @code{mnemonic} attribute can be defined to implement instruction
9146 specific checks in e.g.@: the pipeline description.
9147 @xref{Mnemonic Attribute}.
9150 For each of these special attributes, the corresponding
9151 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
9152 attribute is not defined; in that case, it is defined as @samp{0}.
9154 @findex define_enum_attr
9155 @anchor{define_enum_attr}
9156 Another way of defining an attribute is to use:
9159 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
9162 This works in just the same way as @code{define_attr}, except that
9163 the list of values is taken from a separate enumeration called
9164 @var{enum} (@pxref{define_enum}). This form allows you to use
9165 the same list of values for several attributes without having to
9166 repeat the list each time. For example:
9169 (define_enum "processor" [
9174 (define_enum_attr "arch" "processor"
9175 (const (symbol_ref "target_arch")))
9176 (define_enum_attr "tune" "processor"
9177 (const (symbol_ref "target_tune")))
9180 defines the same attributes as:
9183 (define_attr "arch" "model_a,model_b,@dots{}"
9184 (const (symbol_ref "target_arch")))
9185 (define_attr "tune" "model_a,model_b,@dots{}"
9186 (const (symbol_ref "target_tune")))
9189 but without duplicating the processor list. The second example defines two
9190 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
9191 defines a single C enum (@code{processor}).
9195 @subsection Attribute Expressions
9196 @cindex attribute expressions
9198 RTL expressions used to define attributes use the codes described above
9199 plus a few specific to attribute definitions, to be discussed below.
9200 Attribute value expressions must have one of the following forms:
9203 @cindex @code{const_int} and attributes
9204 @item (const_int @var{i})
9205 The integer @var{i} specifies the value of a numeric attribute. @var{i}
9206 must be non-negative.
9208 The value of a numeric attribute can be specified either with a
9209 @code{const_int}, or as an integer represented as a string in
9210 @code{const_string}, @code{eq_attr} (see below), @code{attr},
9211 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
9212 overrides on specific instructions (@pxref{Tagging Insns}).
9214 @cindex @code{const_string} and attributes
9215 @item (const_string @var{value})
9216 The string @var{value} specifies a constant attribute value.
9217 If @var{value} is specified as @samp{"*"}, it means that the default value of
9218 the attribute is to be used for the insn containing this expression.
9219 @samp{"*"} obviously cannot be used in the @var{default} expression
9220 of a @code{define_attr}.
9222 If the attribute whose value is being specified is numeric, @var{value}
9223 must be a string containing a non-negative integer (normally
9224 @code{const_int} would be used in this case). Otherwise, it must
9225 contain one of the valid values for the attribute.
9227 @cindex @code{if_then_else} and attributes
9228 @item (if_then_else @var{test} @var{true-value} @var{false-value})
9229 @var{test} specifies an attribute test, whose format is defined below.
9230 The value of this expression is @var{true-value} if @var{test} is true,
9231 otherwise it is @var{false-value}.
9233 @cindex @code{cond} and attributes
9234 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
9235 The first operand of this expression is a vector containing an even
9236 number of expressions and consisting of pairs of @var{test} and @var{value}
9237 expressions. The value of the @code{cond} expression is that of the
9238 @var{value} corresponding to the first true @var{test} expression. If
9239 none of the @var{test} expressions are true, the value of the @code{cond}
9240 expression is that of the @var{default} expression.
9243 @var{test} expressions can have one of the following forms:
9246 @cindex @code{const_int} and attribute tests
9247 @item (const_int @var{i})
9248 This test is true if @var{i} is nonzero and false otherwise.
9250 @cindex @code{not} and attributes
9251 @cindex @code{ior} and attributes
9252 @cindex @code{and} and attributes
9253 @item (not @var{test})
9254 @itemx (ior @var{test1} @var{test2})
9255 @itemx (and @var{test1} @var{test2})
9256 These tests are true if the indicated logical function is true.
9258 @cindex @code{match_operand} and attributes
9259 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
9260 This test is true if operand @var{n} of the insn whose attribute value
9261 is being determined has mode @var{m} (this part of the test is ignored
9262 if @var{m} is @code{VOIDmode}) and the function specified by the string
9263 @var{pred} returns a nonzero value when passed operand @var{n} and mode
9264 @var{m} (this part of the test is ignored if @var{pred} is the null
9267 The @var{constraints} operand is ignored and should be the null string.
9269 @cindex @code{match_test} and attributes
9270 @item (match_test @var{c-expr})
9271 The test is true if C expression @var{c-expr} is true. In non-constant
9272 attributes, @var{c-expr} has access to the following variables:
9276 The rtl instruction under test.
9277 @item which_alternative
9278 The @code{define_insn} alternative that @var{insn} matches.
9279 @xref{Output Statement}.
9281 An array of @var{insn}'s rtl operands.
9284 @var{c-expr} behaves like the condition in a C @code{if} statement,
9285 so there is no need to explicitly convert the expression into a boolean
9286 0 or 1 value. For example, the following two tests are equivalent:
9289 (match_test "x & 2")
9290 (match_test "(x & 2) != 0")
9293 @cindex @code{le} and attributes
9294 @cindex @code{leu} and attributes
9295 @cindex @code{lt} and attributes
9296 @cindex @code{gt} and attributes
9297 @cindex @code{gtu} and attributes
9298 @cindex @code{ge} and attributes
9299 @cindex @code{geu} and attributes
9300 @cindex @code{ne} and attributes
9301 @cindex @code{eq} and attributes
9302 @cindex @code{plus} and attributes
9303 @cindex @code{minus} and attributes
9304 @cindex @code{mult} and attributes
9305 @cindex @code{div} and attributes
9306 @cindex @code{mod} and attributes
9307 @cindex @code{abs} and attributes
9308 @cindex @code{neg} and attributes
9309 @cindex @code{ashift} and attributes
9310 @cindex @code{lshiftrt} and attributes
9311 @cindex @code{ashiftrt} and attributes
9312 @item (le @var{arith1} @var{arith2})
9313 @itemx (leu @var{arith1} @var{arith2})
9314 @itemx (lt @var{arith1} @var{arith2})
9315 @itemx (ltu @var{arith1} @var{arith2})
9316 @itemx (gt @var{arith1} @var{arith2})
9317 @itemx (gtu @var{arith1} @var{arith2})
9318 @itemx (ge @var{arith1} @var{arith2})
9319 @itemx (geu @var{arith1} @var{arith2})
9320 @itemx (ne @var{arith1} @var{arith2})
9321 @itemx (eq @var{arith1} @var{arith2})
9322 These tests are true if the indicated comparison of the two arithmetic
9323 expressions is true. Arithmetic expressions are formed with
9324 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
9325 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
9326 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
9329 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
9330 Lengths},for additional forms). @code{symbol_ref} is a string
9331 denoting a C expression that yields an @code{int} when evaluated by the
9332 @samp{get_attr_@dots{}} routine. It should normally be a global
9336 @item (eq_attr @var{name} @var{value})
9337 @var{name} is a string specifying the name of an attribute.
9339 @var{value} is a string that is either a valid value for attribute
9340 @var{name}, a comma-separated list of values, or @samp{!} followed by a
9341 value or list. If @var{value} does not begin with a @samp{!}, this
9342 test is true if the value of the @var{name} attribute of the current
9343 insn is in the list specified by @var{value}. If @var{value} begins
9344 with a @samp{!}, this test is true if the attribute's value is
9345 @emph{not} in the specified list.
9350 (eq_attr "type" "load,store")
9357 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
9360 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
9361 value of the compiler variable @code{which_alternative}
9362 (@pxref{Output Statement}) and the values must be small integers. For
9366 (eq_attr "alternative" "2,3")
9373 (ior (eq (symbol_ref "which_alternative") (const_int 2))
9374 (eq (symbol_ref "which_alternative") (const_int 3)))
9377 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
9378 where the value of the attribute being tested is known for all insns matching
9379 a particular pattern. This is by far the most common case.
9382 @item (attr_flag @var{name})
9383 The value of an @code{attr_flag} expression is true if the flag
9384 specified by @var{name} is true for the @code{insn} currently being
9387 @var{name} is a string specifying one of a fixed set of flags to test.
9388 Test the flags @code{forward} and @code{backward} to determine the
9389 direction of a conditional branch.
9391 This example describes a conditional branch delay slot which
9392 can be nullified for forward branches that are taken (annul-true) or
9393 for backward branches which are not taken (annul-false).
9396 (define_delay (eq_attr "type" "cbranch")
9397 [(eq_attr "in_branch_delay" "true")
9398 (and (eq_attr "in_branch_delay" "true")
9399 (attr_flag "forward"))
9400 (and (eq_attr "in_branch_delay" "true")
9401 (attr_flag "backward"))])
9404 The @code{forward} and @code{backward} flags are false if the current
9405 @code{insn} being scheduled is not a conditional branch.
9407 @code{attr_flag} is only used during delay slot scheduling and has no
9408 meaning to other passes of the compiler.
9411 @item (attr @var{name})
9412 The value of another attribute is returned. This is most useful
9413 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
9414 produce more efficient code for non-numeric attributes.
9420 @subsection Assigning Attribute Values to Insns
9421 @cindex tagging insns
9422 @cindex assigning attribute values to insns
9424 The value assigned to an attribute of an insn is primarily determined by
9425 which pattern is matched by that insn (or which @code{define_peephole}
9426 generated it). Every @code{define_insn} and @code{define_peephole} can
9427 have an optional last argument to specify the values of attributes for
9428 matching insns. The value of any attribute not specified in a particular
9429 insn is set to the default value for that attribute, as specified in its
9430 @code{define_attr}. Extensive use of default values for attributes
9431 permits the specification of the values for only one or two attributes
9432 in the definition of most insn patterns, as seen in the example in the
9435 The optional last argument of @code{define_insn} and
9436 @code{define_peephole} is a vector of expressions, each of which defines
9437 the value for a single attribute. The most general way of assigning an
9438 attribute's value is to use a @code{set} expression whose first operand is an
9439 @code{attr} expression giving the name of the attribute being set. The
9440 second operand of the @code{set} is an attribute expression
9441 (@pxref{Expressions}) giving the value of the attribute.
9443 When the attribute value depends on the @samp{alternative} attribute
9444 (i.e., which is the applicable alternative in the constraint of the
9445 insn), the @code{set_attr_alternative} expression can be used. It
9446 allows the specification of a vector of attribute expressions, one for
9450 When the generality of arbitrary attribute expressions is not required,
9451 the simpler @code{set_attr} expression can be used, which allows
9452 specifying a string giving either a single attribute value or a list
9453 of attribute values, one for each alternative.
9455 The form of each of the above specifications is shown below. In each case,
9456 @var{name} is a string specifying the attribute to be set.
9459 @item (set_attr @var{name} @var{value-string})
9460 @var{value-string} is either a string giving the desired attribute value,
9461 or a string containing a comma-separated list giving the values for
9462 succeeding alternatives. The number of elements must match the number
9463 of alternatives in the constraint of the insn pattern.
9465 Note that it may be useful to specify @samp{*} for some alternative, in
9466 which case the attribute will assume its default value for insns matching
9469 @findex set_attr_alternative
9470 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
9471 Depending on the alternative of the insn, the value will be one of the
9472 specified values. This is a shorthand for using a @code{cond} with
9473 tests on the @samp{alternative} attribute.
9476 @item (set (attr @var{name}) @var{value})
9477 The first operand of this @code{set} must be the special RTL expression
9478 @code{attr}, whose sole operand is a string giving the name of the
9479 attribute being set. @var{value} is the value of the attribute.
9482 The following shows three different ways of representing the same
9483 attribute value specification:
9486 (set_attr "type" "load,store,arith")
9488 (set_attr_alternative "type"
9489 [(const_string "load") (const_string "store")
9490 (const_string "arith")])
9493 (cond [(eq_attr "alternative" "1") (const_string "load")
9494 (eq_attr "alternative" "2") (const_string "store")]
9495 (const_string "arith")))
9499 @findex define_asm_attributes
9500 The @code{define_asm_attributes} expression provides a mechanism to
9501 specify the attributes assigned to insns produced from an @code{asm}
9502 statement. It has the form:
9505 (define_asm_attributes [@var{attr-sets}])
9509 where @var{attr-sets} is specified the same as for both the
9510 @code{define_insn} and the @code{define_peephole} expressions.
9512 These values will typically be the ``worst case'' attribute values. For
9513 example, they might indicate that the condition code will be clobbered.
9515 A specification for a @code{length} attribute is handled specially. The
9516 way to compute the length of an @code{asm} insn is to multiply the
9517 length specified in the expression @code{define_asm_attributes} by the
9518 number of machine instructions specified in the @code{asm} statement,
9519 determined by counting the number of semicolons and newlines in the
9520 string. Therefore, the value of the @code{length} attribute specified
9521 in a @code{define_asm_attributes} should be the maximum possible length
9522 of a single machine instruction.
9527 @subsection Example of Attribute Specifications
9528 @cindex attribute specifications example
9529 @cindex attribute specifications
9531 The judicious use of defaulting is important in the efficient use of
9532 insn attributes. Typically, insns are divided into @dfn{types} and an
9533 attribute, customarily called @code{type}, is used to represent this
9534 value. This attribute is normally used only to define the default value
9535 for other attributes. An example will clarify this usage.
9537 Assume we have a RISC machine with a condition code and in which only
9538 full-word operations are performed in registers. Let us assume that we
9539 can divide all insns into loads, stores, (integer) arithmetic
9540 operations, floating point operations, and branches.
9542 Here we will concern ourselves with determining the effect of an insn on
9543 the condition code and will limit ourselves to the following possible
9544 effects: The condition code can be set unpredictably (clobbered), not
9545 be changed, be set to agree with the results of the operation, or only
9546 changed if the item previously set into the condition code has been
9549 Here is part of a sample @file{md} file for such a machine:
9552 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
9554 (define_attr "cc" "clobber,unchanged,set,change0"
9555 (cond [(eq_attr "type" "load")
9556 (const_string "change0")
9557 (eq_attr "type" "store,branch")
9558 (const_string "unchanged")
9559 (eq_attr "type" "arith")
9560 (if_then_else (match_operand:SI 0 "" "")
9561 (const_string "set")
9562 (const_string "clobber"))]
9563 (const_string "clobber")))
9566 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
9567 (match_operand:SI 1 "general_operand" "r,m,r"))]
9573 [(set_attr "type" "arith,load,store")])
9576 Note that we assume in the above example that arithmetic operations
9577 performed on quantities smaller than a machine word clobber the condition
9578 code since they will set the condition code to a value corresponding to the
9584 @subsection Computing the Length of an Insn
9585 @cindex insn lengths, computing
9586 @cindex computing the length of an insn
9588 For many machines, multiple types of branch instructions are provided, each
9589 for different length branch displacements. In most cases, the assembler
9590 will choose the correct instruction to use. However, when the assembler
9591 cannot do so, GCC can when a special attribute, the @code{length}
9592 attribute, is defined. This attribute must be defined to have numeric
9593 values by specifying a null string in its @code{define_attr}.
9595 In the case of the @code{length} attribute, two additional forms of
9596 arithmetic terms are allowed in test expressions:
9599 @cindex @code{match_dup} and attributes
9600 @item (match_dup @var{n})
9601 This refers to the address of operand @var{n} of the current insn, which
9602 must be a @code{label_ref}.
9604 @cindex @code{pc} and attributes
9606 For non-branch instructions and backward branch instructions, this refers
9607 to the address of the current insn. But for forward branch instructions,
9608 this refers to the address of the next insn, because the length of the
9609 current insn is to be computed.
9612 @cindex @code{addr_vec}, length of
9613 @cindex @code{addr_diff_vec}, length of
9614 For normal insns, the length will be determined by value of the
9615 @code{length} attribute. In the case of @code{addr_vec} and
9616 @code{addr_diff_vec} insn patterns, the length is computed as
9617 the number of vectors multiplied by the size of each vector.
9619 Lengths are measured in addressable storage units (bytes).
9621 Note that it is possible to call functions via the @code{symbol_ref}
9622 mechanism to compute the length of an insn. However, if you use this
9623 mechanism you must provide dummy clauses to express the maximum length
9624 without using the function call. You can an example of this in the
9625 @code{pa} machine description for the @code{call_symref} pattern.
9627 The following macros can be used to refine the length computation:
9630 @findex ADJUST_INSN_LENGTH
9631 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
9632 If defined, modifies the length assigned to instruction @var{insn} as a
9633 function of the context in which it is used. @var{length} is an lvalue
9634 that contains the initially computed length of the insn and should be
9635 updated with the correct length of the insn.
9637 This macro will normally not be required. A case in which it is
9638 required is the ROMP@. On this machine, the size of an @code{addr_vec}
9639 insn must be increased by two to compensate for the fact that alignment
9643 @findex get_attr_length
9644 The routine that returns @code{get_attr_length} (the value of the
9645 @code{length} attribute) can be used by the output routine to
9646 determine the form of the branch instruction to be written, as the
9647 example below illustrates.
9649 As an example of the specification of variable-length branches, consider
9650 the IBM 360. If we adopt the convention that a register will be set to
9651 the starting address of a function, we can jump to labels within 4k of
9652 the start using a four-byte instruction. Otherwise, we need a six-byte
9653 sequence to load the address from memory and then branch to it.
9655 On such a machine, a pattern for a branch instruction might be specified
9661 (label_ref (match_operand 0 "" "")))]
9664 return (get_attr_length (insn) == 4
9665 ? "b %l0" : "l r15,=a(%l0); br r15");
9667 [(set (attr "length")
9668 (if_then_else (lt (match_dup 0) (const_int 4096))
9675 @node Constant Attributes
9676 @subsection Constant Attributes
9677 @cindex constant attributes
9679 A special form of @code{define_attr}, where the expression for the
9680 default value is a @code{const} expression, indicates an attribute that
9681 is constant for a given run of the compiler. Constant attributes may be
9682 used to specify which variety of processor is used. For example,
9685 (define_attr "cpu" "m88100,m88110,m88000"
9687 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
9688 (symbol_ref "TARGET_88110") (const_string "m88110")]
9689 (const_string "m88000"))))
9691 (define_attr "memory" "fast,slow"
9693 (if_then_else (symbol_ref "TARGET_FAST_MEM")
9694 (const_string "fast")
9695 (const_string "slow"))))
9698 The routine generated for constant attributes has no parameters as it
9699 does not depend on any particular insn. RTL expressions used to define
9700 the value of a constant attribute may use the @code{symbol_ref} form,
9701 but may not use either the @code{match_operand} form or @code{eq_attr}
9702 forms involving insn attributes.
9706 @node Mnemonic Attribute
9707 @subsection Mnemonic Attribute
9708 @cindex mnemonic attribute
9710 The @code{mnemonic} attribute is a string type attribute holding the
9711 instruction mnemonic for an insn alternative. The attribute values
9712 will automatically be generated by the machine description parser if
9713 there is an attribute definition in the md file:
9716 (define_attr "mnemonic" "unknown" (const_string "unknown"))
9719 The default value can be freely chosen as long as it does not collide
9720 with any of the instruction mnemonics. This value will be used
9721 whenever the machine description parser is not able to determine the
9722 mnemonic string. This might be the case for output templates
9723 containing more than a single instruction as in
9724 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
9726 The @code{mnemonic} attribute set is not generated automatically if the
9727 instruction string is generated via C code.
9729 An existing @code{mnemonic} attribute set in an insn definition will not
9730 be overriden by the md file parser. That way it is possible to
9731 manually set the instruction mnemonics for the cases where the md file
9732 parser fails to determine it automatically.
9734 The @code{mnemonic} attribute is useful for dealing with instruction
9735 specific properties in the pipeline description without defining
9736 additional insn attributes.
9739 (define_attr "ooo_expanded" ""
9740 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
9748 @subsection Delay Slot Scheduling
9749 @cindex delay slots, defining
9751 The insn attribute mechanism can be used to specify the requirements for
9752 delay slots, if any, on a target machine. An instruction is said to
9753 require a @dfn{delay slot} if some instructions that are physically
9754 after the instruction are executed as if they were located before it.
9755 Classic examples are branch and call instructions, which often execute
9756 the following instruction before the branch or call is performed.
9758 On some machines, conditional branch instructions can optionally
9759 @dfn{annul} instructions in the delay slot. This means that the
9760 instruction will not be executed for certain branch outcomes. Both
9761 instructions that annul if the branch is true and instructions that
9762 annul if the branch is false are supported.
9764 Delay slot scheduling differs from instruction scheduling in that
9765 determining whether an instruction needs a delay slot is dependent only
9766 on the type of instruction being generated, not on data flow between the
9767 instructions. See the next section for a discussion of data-dependent
9768 instruction scheduling.
9770 @findex define_delay
9771 The requirement of an insn needing one or more delay slots is indicated
9772 via the @code{define_delay} expression. It has the following form:
9775 (define_delay @var{test}
9776 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
9777 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
9781 @var{test} is an attribute test that indicates whether this
9782 @code{define_delay} applies to a particular insn. If so, the number of
9783 required delay slots is determined by the length of the vector specified
9784 as the second argument. An insn placed in delay slot @var{n} must
9785 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
9786 attribute test that specifies which insns may be annulled if the branch
9787 is true. Similarly, @var{annul-false-n} specifies which insns in the
9788 delay slot may be annulled if the branch is false. If annulling is not
9789 supported for that delay slot, @code{(nil)} should be coded.
9791 For example, in the common case where branch and call insns require
9792 a single delay slot, which may contain any insn other than a branch or
9793 call, the following would be placed in the @file{md} file:
9796 (define_delay (eq_attr "type" "branch,call")
9797 [(eq_attr "type" "!branch,call") (nil) (nil)])
9800 Multiple @code{define_delay} expressions may be specified. In this
9801 case, each such expression specifies different delay slot requirements
9802 and there must be no insn for which tests in two @code{define_delay}
9803 expressions are both true.
9805 For example, if we have a machine that requires one delay slot for branches
9806 but two for calls, no delay slot can contain a branch or call insn,
9807 and any valid insn in the delay slot for the branch can be annulled if the
9808 branch is true, we might represent this as follows:
9811 (define_delay (eq_attr "type" "branch")
9812 [(eq_attr "type" "!branch,call")
9813 (eq_attr "type" "!branch,call")
9816 (define_delay (eq_attr "type" "call")
9817 [(eq_attr "type" "!branch,call") (nil) (nil)
9818 (eq_attr "type" "!branch,call") (nil) (nil)])
9820 @c the above is *still* too long. --mew 4feb93
9824 @node Processor pipeline description
9825 @subsection Specifying processor pipeline description
9826 @cindex processor pipeline description
9827 @cindex processor functional units
9828 @cindex instruction latency time
9829 @cindex interlock delays
9830 @cindex data dependence delays
9831 @cindex reservation delays
9832 @cindex pipeline hazard recognizer
9833 @cindex automaton based pipeline description
9834 @cindex regular expressions
9835 @cindex deterministic finite state automaton
9836 @cindex automaton based scheduler
9840 To achieve better performance, most modern processors
9841 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
9842 processors) have many @dfn{functional units} on which several
9843 instructions can be executed simultaneously. An instruction starts
9844 execution if its issue conditions are satisfied. If not, the
9845 instruction is stalled until its conditions are satisfied. Such
9846 @dfn{interlock (pipeline) delay} causes interruption of the fetching
9847 of successor instructions (or demands nop instructions, e.g.@: for some
9850 There are two major kinds of interlock delays in modern processors.
9851 The first one is a data dependence delay determining @dfn{instruction
9852 latency time}. The instruction execution is not started until all
9853 source data have been evaluated by prior instructions (there are more
9854 complex cases when the instruction execution starts even when the data
9855 are not available but will be ready in given time after the
9856 instruction execution start). Taking the data dependence delays into
9857 account is simple. The data dependence (true, output, and
9858 anti-dependence) delay between two instructions is given by a
9859 constant. In most cases this approach is adequate. The second kind
9860 of interlock delays is a reservation delay. The reservation delay
9861 means that two instructions under execution will be in need of shared
9862 processors resources, i.e.@: buses, internal registers, and/or
9863 functional units, which are reserved for some time. Taking this kind
9864 of delay into account is complex especially for modern @acronym{RISC}
9867 The task of exploiting more processor parallelism is solved by an
9868 instruction scheduler. For a better solution to this problem, the
9869 instruction scheduler has to have an adequate description of the
9870 processor parallelism (or @dfn{pipeline description}). GCC
9871 machine descriptions describe processor parallelism and functional
9872 unit reservations for groups of instructions with the aid of
9873 @dfn{regular expressions}.
9875 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
9876 figure out the possibility of the instruction issue by the processor
9877 on a given simulated processor cycle. The pipeline hazard recognizer is
9878 automatically generated from the processor pipeline description. The
9879 pipeline hazard recognizer generated from the machine description
9880 is based on a deterministic finite state automaton (@acronym{DFA}):
9881 the instruction issue is possible if there is a transition from one
9882 automaton state to another one. This algorithm is very fast, and
9883 furthermore, its speed is not dependent on processor
9884 complexity@footnote{However, the size of the automaton depends on
9885 processor complexity. To limit this effect, machine descriptions
9886 can split orthogonal parts of the machine description among several
9887 automata: but then, since each of these must be stepped independently,
9888 this does cause a small decrease in the algorithm's performance.}.
9890 @cindex automaton based pipeline description
9891 The rest of this section describes the directives that constitute
9892 an automaton-based processor pipeline description. The order of
9893 these constructions within the machine description file is not
9896 @findex define_automaton
9897 @cindex pipeline hazard recognizer
9898 The following optional construction describes names of automata
9899 generated and used for the pipeline hazards recognition. Sometimes
9900 the generated finite state automaton used by the pipeline hazard
9901 recognizer is large. If we use more than one automaton and bind functional
9902 units to the automata, the total size of the automata is usually
9903 less than the size of the single automaton. If there is no one such
9904 construction, only one finite state automaton is generated.
9907 (define_automaton @var{automata-names})
9910 @var{automata-names} is a string giving names of the automata. The
9911 names are separated by commas. All the automata should have unique names.
9912 The automaton name is used in the constructions @code{define_cpu_unit} and
9913 @code{define_query_cpu_unit}.
9915 @findex define_cpu_unit
9916 @cindex processor functional units
9917 Each processor functional unit used in the description of instruction
9918 reservations should be described by the following construction.
9921 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
9924 @var{unit-names} is a string giving the names of the functional units
9925 separated by commas. Don't use name @samp{nothing}, it is reserved
9928 @var{automaton-name} is a string giving the name of the automaton with
9929 which the unit is bound. The automaton should be described in
9930 construction @code{define_automaton}. You should give
9931 @dfn{automaton-name}, if there is a defined automaton.
9933 The assignment of units to automata are constrained by the uses of the
9934 units in insn reservations. The most important constraint is: if a
9935 unit reservation is present on a particular cycle of an alternative
9936 for an insn reservation, then some unit from the same automaton must
9937 be present on the same cycle for the other alternatives of the insn
9938 reservation. The rest of the constraints are mentioned in the
9939 description of the subsequent constructions.
9941 @findex define_query_cpu_unit
9942 @cindex querying function unit reservations
9943 The following construction describes CPU functional units analogously
9944 to @code{define_cpu_unit}. The reservation of such units can be
9945 queried for an automaton state. The instruction scheduler never
9946 queries reservation of functional units for given automaton state. So
9947 as a rule, you don't need this construction. This construction could
9948 be used for future code generation goals (e.g.@: to generate
9949 @acronym{VLIW} insn templates).
9952 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
9955 @var{unit-names} is a string giving names of the functional units
9956 separated by commas.
9958 @var{automaton-name} is a string giving the name of the automaton with
9959 which the unit is bound.
9961 @findex define_insn_reservation
9962 @cindex instruction latency time
9963 @cindex regular expressions
9965 The following construction is the major one to describe pipeline
9966 characteristics of an instruction.
9969 (define_insn_reservation @var{insn-name} @var{default_latency}
9970 @var{condition} @var{regexp})
9973 @var{default_latency} is a number giving latency time of the
9974 instruction. There is an important difference between the old
9975 description and the automaton based pipeline description. The latency
9976 time is used for all dependencies when we use the old description. In
9977 the automaton based pipeline description, the given latency time is only
9978 used for true dependencies. The cost of anti-dependencies is always
9979 zero and the cost of output dependencies is the difference between
9980 latency times of the producing and consuming insns (if the difference
9981 is negative, the cost is considered to be zero). You can always
9982 change the default costs for any description by using the target hook
9983 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
9985 @var{insn-name} is a string giving the internal name of the insn. The
9986 internal names are used in constructions @code{define_bypass} and in
9987 the automaton description file generated for debugging. The internal
9988 name has nothing in common with the names in @code{define_insn}. It is a
9989 good practice to use insn classes described in the processor manual.
9991 @var{condition} defines what RTL insns are described by this
9992 construction. You should remember that you will be in trouble if
9993 @var{condition} for two or more different
9994 @code{define_insn_reservation} constructions is TRUE for an insn. In
9995 this case what reservation will be used for the insn is not defined.
9996 Such cases are not checked during generation of the pipeline hazards
9997 recognizer because in general recognizing that two conditions may have
9998 the same value is quite difficult (especially if the conditions
9999 contain @code{symbol_ref}). It is also not checked during the
10000 pipeline hazard recognizer work because it would slow down the
10001 recognizer considerably.
10003 @var{regexp} is a string describing the reservation of the cpu's functional
10004 units by the instruction. The reservations are described by a regular
10005 expression according to the following syntax:
10008 regexp = regexp "," oneof
10011 oneof = oneof "|" allof
10014 allof = allof "+" repeat
10017 repeat = element "*" number
10020 element = cpu_function_unit_name
10029 @samp{,} is used for describing the start of the next cycle in
10033 @samp{|} is used for describing a reservation described by the first
10034 regular expression @strong{or} a reservation described by the second
10035 regular expression @strong{or} etc.
10038 @samp{+} is used for describing a reservation described by the first
10039 regular expression @strong{and} a reservation described by the
10040 second regular expression @strong{and} etc.
10043 @samp{*} is used for convenience and simply means a sequence in which
10044 the regular expression are repeated @var{number} times with cycle
10045 advancing (see @samp{,}).
10048 @samp{cpu_function_unit_name} denotes reservation of the named
10052 @samp{reservation_name} --- see description of construction
10053 @samp{define_reservation}.
10056 @samp{nothing} denotes no unit reservations.
10059 @findex define_reservation
10060 Sometimes unit reservations for different insns contain common parts.
10061 In such case, you can simplify the pipeline description by describing
10062 the common part by the following construction
10065 (define_reservation @var{reservation-name} @var{regexp})
10068 @var{reservation-name} is a string giving name of @var{regexp}.
10069 Functional unit names and reservation names are in the same name
10070 space. So the reservation names should be different from the
10071 functional unit names and cannot be the reserved name @samp{nothing}.
10073 @findex define_bypass
10074 @cindex instruction latency time
10075 @cindex data bypass
10076 The following construction is used to describe exceptions in the
10077 latency time for given instruction pair. This is so called bypasses.
10080 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
10084 @var{number} defines when the result generated by the instructions
10085 given in string @var{out_insn_names} will be ready for the
10086 instructions given in string @var{in_insn_names}. Each of these
10087 strings is a comma-separated list of filename-style globs and
10088 they refer to the names of @code{define_insn_reservation}s.
10091 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
10093 defines a bypass between instructions that start with
10094 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
10097 @var{guard} is an optional string giving the name of a C function which
10098 defines an additional guard for the bypass. The function will get the
10099 two insns as parameters. If the function returns zero the bypass will
10100 be ignored for this case. The additional guard is necessary to
10101 recognize complicated bypasses, e.g.@: when the consumer is only an address
10102 of insn @samp{store} (not a stored value).
10104 If there are more one bypass with the same output and input insns, the
10105 chosen bypass is the first bypass with a guard in description whose
10106 guard function returns nonzero. If there is no such bypass, then
10107 bypass without the guard function is chosen.
10109 @findex exclusion_set
10110 @findex presence_set
10111 @findex final_presence_set
10112 @findex absence_set
10113 @findex final_absence_set
10116 The following five constructions are usually used to describe
10117 @acronym{VLIW} processors, or more precisely, to describe a placement
10118 of small instructions into @acronym{VLIW} instruction slots. They
10119 can be used for @acronym{RISC} processors, too.
10122 (exclusion_set @var{unit-names} @var{unit-names})
10123 (presence_set @var{unit-names} @var{patterns})
10124 (final_presence_set @var{unit-names} @var{patterns})
10125 (absence_set @var{unit-names} @var{patterns})
10126 (final_absence_set @var{unit-names} @var{patterns})
10129 @var{unit-names} is a string giving names of functional units
10130 separated by commas.
10132 @var{patterns} is a string giving patterns of functional units
10133 separated by comma. Currently pattern is one unit or units
10134 separated by white-spaces.
10136 The first construction (@samp{exclusion_set}) means that each
10137 functional unit in the first string cannot be reserved simultaneously
10138 with a unit whose name is in the second string and vice versa. For
10139 example, the construction is useful for describing processors
10140 (e.g.@: some SPARC processors) with a fully pipelined floating point
10141 functional unit which can execute simultaneously only single floating
10142 point insns or only double floating point insns.
10144 The second construction (@samp{presence_set}) means that each
10145 functional unit in the first string cannot be reserved unless at
10146 least one of pattern of units whose names are in the second string is
10147 reserved. This is an asymmetric relation. For example, it is useful
10148 for description that @acronym{VLIW} @samp{slot1} is reserved after
10149 @samp{slot0} reservation. We could describe it by the following
10153 (presence_set "slot1" "slot0")
10156 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
10157 reservation. In this case we could write
10160 (presence_set "slot1" "slot0 b0")
10163 The third construction (@samp{final_presence_set}) is analogous to
10164 @samp{presence_set}. The difference between them is when checking is
10165 done. When an instruction is issued in given automaton state
10166 reflecting all current and planned unit reservations, the automaton
10167 state is changed. The first state is a source state, the second one
10168 is a result state. Checking for @samp{presence_set} is done on the
10169 source state reservation, checking for @samp{final_presence_set} is
10170 done on the result reservation. This construction is useful to
10171 describe a reservation which is actually two subsequent reservations.
10172 For example, if we use
10175 (presence_set "slot1" "slot0")
10178 the following insn will be never issued (because @samp{slot1} requires
10179 @samp{slot0} which is absent in the source state).
10182 (define_reservation "insn_and_nop" "slot0 + slot1")
10185 but it can be issued if we use analogous @samp{final_presence_set}.
10187 The forth construction (@samp{absence_set}) means that each functional
10188 unit in the first string can be reserved only if each pattern of units
10189 whose names are in the second string is not reserved. This is an
10190 asymmetric relation (actually @samp{exclusion_set} is analogous to
10191 this one but it is symmetric). For example it might be useful in a
10192 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
10193 after either @samp{slot1} or @samp{slot2} have been reserved. This
10194 can be described as:
10197 (absence_set "slot0" "slot1, slot2")
10200 Or @samp{slot2} cannot be reserved if @samp{slot0} and unit @samp{b0}
10201 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
10202 this case we could write
10205 (absence_set "slot2" "slot0 b0, slot1 b1")
10208 All functional units mentioned in a set should belong to the same
10211 The last construction (@samp{final_absence_set}) is analogous to
10212 @samp{absence_set} but checking is done on the result (state)
10213 reservation. See comments for @samp{final_presence_set}.
10215 @findex automata_option
10216 @cindex deterministic finite state automaton
10217 @cindex nondeterministic finite state automaton
10218 @cindex finite state automaton minimization
10219 You can control the generator of the pipeline hazard recognizer with
10220 the following construction.
10223 (automata_option @var{options})
10226 @var{options} is a string giving options which affect the generated
10227 code. Currently there are the following options:
10231 @dfn{no-minimization} makes no minimization of the automaton. This is
10232 only worth to do when we are debugging the description and need to
10233 look more accurately at reservations of states.
10236 @dfn{time} means printing time statistics about the generation of
10240 @dfn{stats} means printing statistics about the generated automata
10241 such as the number of DFA states, NDFA states and arcs.
10244 @dfn{v} means a generation of the file describing the result automata.
10245 The file has suffix @samp{.dfa} and can be used for the description
10246 verification and debugging.
10249 @dfn{w} means a generation of warning instead of error for
10250 non-critical errors.
10253 @dfn{no-comb-vect} prevents the automaton generator from generating
10254 two data structures and comparing them for space efficiency. Using
10255 a comb vector to represent transitions may be better, but it can be
10256 very expensive to construct. This option is useful if the build
10257 process spends an unacceptably long time in genautomata.
10260 @dfn{ndfa} makes nondeterministic finite state automata. This affects
10261 the treatment of operator @samp{|} in the regular expressions. The
10262 usual treatment of the operator is to try the first alternative and,
10263 if the reservation is not possible, the second alternative. The
10264 nondeterministic treatment means trying all alternatives, some of them
10265 may be rejected by reservations in the subsequent insns.
10268 @dfn{collapse-ndfa} modifies the behavior of the generator when
10269 producing an automaton. An additional state transition to collapse a
10270 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
10271 state is generated. It can be triggered by passing @code{const0_rtx} to
10272 state_transition. In such an automaton, cycle advance transitions are
10273 available only for these collapsed states. This option is useful for
10274 ports that want to use the @code{ndfa} option, but also want to use
10275 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
10278 @dfn{progress} means output of a progress bar showing how many states
10279 were generated so far for automaton being processed. This is useful
10280 during debugging a @acronym{DFA} description. If you see too many
10281 generated states, you could interrupt the generator of the pipeline
10282 hazard recognizer and try to figure out a reason for generation of the
10286 As an example, consider a superscalar @acronym{RISC} machine which can
10287 issue three insns (two integer insns and one floating point insn) on
10288 the cycle but can finish only two insns. To describe this, we define
10289 the following functional units.
10292 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
10293 (define_cpu_unit "port0, port1")
10296 All simple integer insns can be executed in any integer pipeline and
10297 their result is ready in two cycles. The simple integer insns are
10298 issued into the first pipeline unless it is reserved, otherwise they
10299 are issued into the second pipeline. Integer division and
10300 multiplication insns can be executed only in the second integer
10301 pipeline and their results are ready correspondingly in 9 and 4
10302 cycles. The integer division is not pipelined, i.e.@: the subsequent
10303 integer division insn cannot be issued until the current division
10304 insn finished. Floating point insns are fully pipelined and their
10305 results are ready in 3 cycles. Where the result of a floating point
10306 insn is used by an integer insn, an additional delay of one cycle is
10307 incurred. To describe all of this we could specify
10310 (define_cpu_unit "div")
10312 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
10313 "(i0_pipeline | i1_pipeline), (port0 | port1)")
10315 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
10316 "i1_pipeline, nothing*2, (port0 | port1)")
10318 (define_insn_reservation "div" 9 (eq_attr "type" "div")
10319 "i1_pipeline, div*7, div + (port0 | port1)")
10321 (define_insn_reservation "float" 3 (eq_attr "type" "float")
10322 "f_pipeline, nothing, (port0 | port1))
10324 (define_bypass 4 "float" "simple,mult,div")
10327 To simplify the description we could describe the following reservation
10330 (define_reservation "finish" "port0|port1")
10333 and use it in all @code{define_insn_reservation} as in the following
10337 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
10338 "(i0_pipeline | i1_pipeline), finish")
10344 @node Conditional Execution
10345 @section Conditional Execution
10346 @cindex conditional execution
10347 @cindex predication
10349 A number of architectures provide for some form of conditional
10350 execution, or predication. The hallmark of this feature is the
10351 ability to nullify most of the instructions in the instruction set.
10352 When the instruction set is large and not entirely symmetric, it
10353 can be quite tedious to describe these forms directly in the
10354 @file{.md} file. An alternative is the @code{define_cond_exec} template.
10356 @findex define_cond_exec
10359 [@var{predicate-pattern}]
10361 "@var{output-template}"
10362 "@var{optional-insn-attribues}")
10365 @var{predicate-pattern} is the condition that must be true for the
10366 insn to be executed at runtime and should match a relational operator.
10367 One can use @code{match_operator} to match several relational operators
10368 at once. Any @code{match_operand} operands must have no more than one
10371 @var{condition} is a C expression that must be true for the generated
10374 @findex current_insn_predicate
10375 @var{output-template} is a string similar to the @code{define_insn}
10376 output template (@pxref{Output Template}), except that the @samp{*}
10377 and @samp{@@} special cases do not apply. This is only useful if the
10378 assembly text for the predicate is a simple prefix to the main insn.
10379 In order to handle the general case, there is a global variable
10380 @code{current_insn_predicate} that will contain the entire predicate
10381 if the current insn is predicated, and will otherwise be @code{NULL}.
10383 @var{optional-insn-attributes} is an optional vector of attributes that gets
10384 appended to the insn attributes of the produced cond_exec rtx. It can
10385 be used to add some distinguishing attribute to cond_exec rtxs produced
10386 that way. An example usage would be to use this attribute in conjunction
10387 with attributes on the main pattern to disable particular alternatives under
10388 certain conditions.
10390 When @code{define_cond_exec} is used, an implicit reference to
10391 the @code{predicable} instruction attribute is made.
10392 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
10393 exactly two elements in its @var{list-of-values}), with the possible
10394 values being @code{no} and @code{yes}. The default and all uses in
10395 the insns must be a simple constant, not a complex expressions. It
10396 may, however, depend on the alternative, by using a comma-separated
10397 list of values. If that is the case, the port should also define an
10398 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
10399 should also allow only @code{no} and @code{yes} as its values.
10401 For each @code{define_insn} for which the @code{predicable}
10402 attribute is true, a new @code{define_insn} pattern will be
10403 generated that matches a predicated version of the instruction.
10407 (define_insn "addsi"
10408 [(set (match_operand:SI 0 "register_operand" "r")
10409 (plus:SI (match_operand:SI 1 "register_operand" "r")
10410 (match_operand:SI 2 "register_operand" "r")))]
10415 [(ne (match_operand:CC 0 "register_operand" "c")
10422 generates a new pattern
10427 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
10428 (set (match_operand:SI 0 "register_operand" "r")
10429 (plus:SI (match_operand:SI 1 "register_operand" "r")
10430 (match_operand:SI 2 "register_operand" "r"))))]
10431 "(@var{test2}) && (@var{test1})"
10432 "(%3) add %2,%1,%0")
10438 @section RTL Templates Transformations
10439 @cindex define_subst
10441 For some hardware architectures there are common cases when the RTL
10442 templates for the instructions can be derived from the other RTL
10443 templates using simple transformations. E.g., @file{i386.md} contains
10444 an RTL template for the ordinary @code{sub} instruction---
10445 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
10446 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
10447 implemented by a single meta-template capable of generating a modified
10448 case based on the initial one:
10450 @findex define_subst
10452 (define_subst "@var{name}"
10453 [@var{input-template}]
10455 [@var{output-template}])
10457 @var{input-template} is a pattern describing the source RTL template,
10458 which will be transformed.
10460 @var{condition} is a C expression that is conjunct with the condition
10461 from the input-template to generate a condition to be used in the
10464 @var{output-template} is a pattern that will be used in the resulting
10467 @code{define_subst} mechanism is tightly coupled with the notion of the
10468 subst attribute (@pxref{Subst Iterators}). The use of
10469 @code{define_subst} is triggered by a reference to a subst attribute in
10470 the transforming RTL template. This reference initiates duplication of
10471 the source RTL template and substitution of the attributes with their
10472 values. The source RTL template is left unchanged, while the copy is
10473 transformed by @code{define_subst}. This transformation can fail in the
10474 case when the source RTL template is not matched against the
10475 input-template of the @code{define_subst}. In such case the copy is
10478 @code{define_subst} can be used only in @code{define_insn} and
10479 @code{define_expand}, it cannot be used in other expressions (e.g.@: in
10480 @code{define_insn_and_split}).
10483 * Define Subst Example:: Example of @code{define_subst} work.
10484 * Define Subst Pattern Matching:: Process of template comparison.
10485 * Define Subst Output Template:: Generation of output template.
10488 @node Define Subst Example
10489 @subsection @code{define_subst} Example
10490 @cindex define_subst
10492 To illustrate how @code{define_subst} works, let us examine a simple
10493 template transformation.
10495 Suppose there are two kinds of instructions: one that touches flags and
10496 the other that does not. The instructions of the second type could be
10497 generated with the following @code{define_subst}:
10500 (define_subst "add_clobber_subst"
10501 [(set (match_operand:SI 0 "" "")
10502 (match_operand:SI 1 "" ""))]
10504 [(set (match_dup 0)
10506 (clobber (reg:CC FLAGS_REG))]
10509 This @code{define_subst} can be applied to any RTL pattern containing
10510 @code{set} of mode SI and generates a copy with clobber when it is
10513 Assume there is an RTL template for a @code{max} instruction to be used
10514 in @code{define_subst} mentioned above:
10517 (define_insn "maxsi"
10518 [(set (match_operand:SI 0 "register_operand" "=r")
10520 (match_operand:SI 1 "register_operand" "r")
10521 (match_operand:SI 2 "register_operand" "r")))]
10523 "max\t@{%2, %1, %0|%0, %1, %2@}"
10527 To mark the RTL template for @code{define_subst} application,
10528 subst-attributes are used. They should be declared in advance:
10531 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
10534 Here @samp{add_clobber_name} is the attribute name,
10535 @samp{add_clobber_subst} is the name of the corresponding
10536 @code{define_subst}, the third argument (@samp{_noclobber}) is the
10537 attribute value that would be substituted into the unchanged version of
10538 the source RTL template, and the last argument (@samp{_clobber}) is the
10539 value that would be substituted into the second, transformed,
10540 version of the RTL template.
10542 Once the subst-attribute has been defined, it should be used in RTL
10543 templates which need to be processed by the @code{define_subst}. So,
10544 the original RTL template should be changed:
10547 (define_insn "maxsi<add_clobber_name>"
10548 [(set (match_operand:SI 0 "register_operand" "=r")
10550 (match_operand:SI 1 "register_operand" "r")
10551 (match_operand:SI 2 "register_operand" "r")))]
10553 "max\t@{%2, %1, %0|%0, %1, %2@}"
10557 The result of the @code{define_subst} usage would look like the following:
10560 (define_insn "maxsi_noclobber"
10561 [(set (match_operand:SI 0 "register_operand" "=r")
10563 (match_operand:SI 1 "register_operand" "r")
10564 (match_operand:SI 2 "register_operand" "r")))]
10566 "max\t@{%2, %1, %0|%0, %1, %2@}"
10568 (define_insn "maxsi_clobber"
10569 [(set (match_operand:SI 0 "register_operand" "=r")
10571 (match_operand:SI 1 "register_operand" "r")
10572 (match_operand:SI 2 "register_operand" "r")))
10573 (clobber (reg:CC FLAGS_REG))]
10575 "max\t@{%2, %1, %0|%0, %1, %2@}"
10579 @node Define Subst Pattern Matching
10580 @subsection Pattern Matching in @code{define_subst}
10581 @cindex define_subst
10583 All expressions, allowed in @code{define_insn} or @code{define_expand},
10584 are allowed in the input-template of @code{define_subst}, except
10585 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
10586 meanings of expressions in the input-template were changed:
10588 @code{match_operand} matches any expression (possibly, a subtree in
10589 RTL-template), if modes of the @code{match_operand} and this expression
10590 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
10591 this expression is @code{match_dup}, @code{match_op_dup}. If the
10592 expression is @code{match_operand} too, and predicate of
10593 @code{match_operand} from the input pattern is not empty, then the
10594 predicates are compared. That can be used for more accurate filtering
10595 of accepted RTL-templates.
10597 @code{match_operator} matches common operators (like @code{plus},
10598 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
10599 @code{match_operator}s from the original pattern if the modes match and
10600 @code{match_operator} from the input pattern has the same number of
10601 operands as the operator from the original pattern.
10603 @node Define Subst Output Template
10604 @subsection Generation of output template in @code{define_subst}
10605 @cindex define_subst
10607 If all necessary checks for @code{define_subst} application pass, a new
10608 RTL-pattern, based on the output-template, is created to replace the old
10609 template. Like in input-patterns, meanings of some RTL expressions are
10610 changed when they are used in output-patterns of a @code{define_subst}.
10611 Thus, @code{match_dup} is used for copying the whole expression from the
10612 original pattern, which matched corresponding @code{match_operand} from
10615 @code{match_dup N} is used in the output template to be replaced with
10616 the expression from the original pattern, which matched
10617 @code{match_operand N} from the input pattern. As a consequence,
10618 @code{match_dup} cannot be used to point to @code{match_operand}s from
10619 the output pattern, it should always refer to a @code{match_operand}
10620 from the input pattern. If a @code{match_dup N} occurs more than once
10621 in the output template, its first occurrence is replaced with the
10622 expression from the original pattern, and the subsequent expressions
10623 are replaced with @code{match_dup N}, i.e., a reference to the first
10626 In the output template one can refer to the expressions from the
10627 original pattern and create new ones. For instance, some operands could
10628 be added by means of standard @code{match_operand}.
10630 After replacing @code{match_dup} with some RTL-subtree from the original
10631 pattern, it could happen that several @code{match_operand}s in the
10632 output pattern have the same indexes. It is unknown, how many and what
10633 indexes would be used in the expression which would replace
10634 @code{match_dup}, so such conflicts in indexes are inevitable. To
10635 overcome this issue, @code{match_operands} and @code{match_operators},
10636 which were introduced into the output pattern, are renumerated when all
10637 @code{match_dup}s are replaced.
10639 Number of alternatives in @code{match_operand}s introduced into the
10640 output template @code{M} could differ from the number of alternatives in
10641 the original pattern @code{N}, so in the resultant pattern there would
10642 be @code{N*M} alternatives. Thus, constraints from the original pattern
10643 would be duplicated @code{N} times, constraints from the output pattern
10644 would be duplicated @code{M} times, producing all possible combinations.
10648 @node Constant Definitions
10649 @section Constant Definitions
10650 @cindex constant definitions
10651 @findex define_constants
10653 Using literal constants inside instruction patterns reduces legibility and
10654 can be a maintenance problem.
10656 To overcome this problem, you may use the @code{define_constants}
10657 expression. It contains a vector of name-value pairs. From that
10658 point on, wherever any of the names appears in the MD file, it is as
10659 if the corresponding value had been written instead. You may use
10660 @code{define_constants} multiple times; each appearance adds more
10661 constants to the table. It is an error to redefine a constant with
10664 To come back to the a29k load multiple example, instead of
10668 [(match_parallel 0 "load_multiple_operation"
10669 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10670 (match_operand:SI 2 "memory_operand" "m"))
10672 (clobber (reg:SI 179))])]
10680 (define_constants [
10688 [(match_parallel 0 "load_multiple_operation"
10689 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10690 (match_operand:SI 2 "memory_operand" "m"))
10691 (use (reg:SI R_CR))
10692 (clobber (reg:SI R_CR))])]
10697 The constants that are defined with a define_constant are also output
10698 in the insn-codes.h header file as #defines.
10700 @cindex enumerations
10701 @findex define_c_enum
10702 You can also use the machine description file to define enumerations.
10703 Like the constants defined by @code{define_constant}, these enumerations
10704 are visible to both the machine description file and the main C code.
10706 The syntax is as follows:
10709 (define_c_enum "@var{name}" [
10717 This definition causes the equivalent of the following C code to appear
10718 in @file{insn-constants.h}:
10725 @var{valuen} = @var{n}
10727 #define NUM_@var{cname}_VALUES (@var{n} + 1)
10730 where @var{cname} is the capitalized form of @var{name}.
10731 It also makes each @var{valuei} available in the machine description
10732 file, just as if it had been declared with:
10735 (define_constants [(@var{valuei} @var{i})])
10738 Each @var{valuei} is usually an upper-case identifier and usually
10739 begins with @var{cname}.
10741 You can split the enumeration definition into as many statements as
10742 you like. The above example is directly equivalent to:
10745 (define_c_enum "@var{name}" [@var{value0}])
10746 (define_c_enum "@var{name}" [@var{value1}])
10748 (define_c_enum "@var{name}" [@var{valuen}])
10751 Splitting the enumeration helps to improve the modularity of each
10752 individual @code{.md} file. For example, if a port defines its
10753 synchronization instructions in a separate @file{sync.md} file,
10754 it is convenient to define all synchronization-specific enumeration
10755 values in @file{sync.md} rather than in the main @file{.md} file.
10757 Some enumeration names have special significance to GCC:
10761 @findex unspec_volatile
10762 If an enumeration called @code{unspecv} is defined, GCC will use it
10763 when printing out @code{unspec_volatile} expressions. For example:
10766 (define_c_enum "unspecv" [
10771 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
10774 (unspec_volatile ... UNSPECV_BLOCKAGE)
10779 If an enumeration called @code{unspec} is defined, GCC will use
10780 it when printing out @code{unspec} expressions. GCC will also use
10781 it when printing out @code{unspec_volatile} expressions unless an
10782 @code{unspecv} enumeration is also defined. You can therefore
10783 decide whether to keep separate enumerations for volatile and
10784 non-volatile expressions or whether to use the same enumeration
10788 @findex define_enum
10789 @anchor{define_enum}
10790 Another way of defining an enumeration is to use @code{define_enum}:
10793 (define_enum "@var{name}" [
10801 This directive implies:
10804 (define_c_enum "@var{name}" [
10805 @var{cname}_@var{cvalue0}
10806 @var{cname}_@var{cvalue1}
10808 @var{cname}_@var{cvaluen}
10812 @findex define_enum_attr
10813 where @var{cvaluei} is the capitalized form of @var{valuei}.
10814 However, unlike @code{define_c_enum}, the enumerations defined
10815 by @code{define_enum} can be used in attribute specifications
10816 (@pxref{define_enum_attr}).
10821 @cindex iterators in @file{.md} files
10823 Ports often need to define similar patterns for more than one machine
10824 mode or for more than one rtx code. GCC provides some simple iterator
10825 facilities to make this process easier.
10828 * Mode Iterators:: Generating variations of patterns for different modes.
10829 * Code Iterators:: Doing the same for codes.
10830 * Int Iterators:: Doing the same for integers.
10831 * Subst Iterators:: Generating variations of patterns for define_subst.
10832 * Parameterized Names:: Specifying iterator values in C++ code.
10835 @node Mode Iterators
10836 @subsection Mode Iterators
10837 @cindex mode iterators in @file{.md} files
10839 Ports often need to define similar patterns for two or more different modes.
10844 If a processor has hardware support for both single and double
10845 floating-point arithmetic, the @code{SFmode} patterns tend to be
10846 very similar to the @code{DFmode} ones.
10849 If a port uses @code{SImode} pointers in one configuration and
10850 @code{DImode} pointers in another, it will usually have very similar
10851 @code{SImode} and @code{DImode} patterns for manipulating pointers.
10854 Mode iterators allow several patterns to be instantiated from one
10855 @file{.md} file template. They can be used with any type of
10856 rtx-based construct, such as a @code{define_insn},
10857 @code{define_split}, or @code{define_peephole2}.
10860 * Defining Mode Iterators:: Defining a new mode iterator.
10861 * Substitutions:: Combining mode iterators with substitutions
10862 * Examples:: Examples
10865 @node Defining Mode Iterators
10866 @subsubsection Defining Mode Iterators
10867 @findex define_mode_iterator
10869 The syntax for defining a mode iterator is:
10872 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
10875 This allows subsequent @file{.md} file constructs to use the mode suffix
10876 @code{:@var{name}}. Every construct that does so will be expanded
10877 @var{n} times, once with every use of @code{:@var{name}} replaced by
10878 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
10879 and so on. In the expansion for a particular @var{modei}, every
10880 C condition will also require that @var{condi} be true.
10885 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10888 defines a new mode suffix @code{:P}. Every construct that uses
10889 @code{:P} will be expanded twice, once with every @code{:P} replaced
10890 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
10891 The @code{:SI} version will only apply if @code{Pmode == SImode} and
10892 the @code{:DI} version will only apply if @code{Pmode == DImode}.
10894 As with other @file{.md} conditions, an empty string is treated
10895 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
10896 to @code{@var{mode}}. For example:
10899 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10902 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
10903 but that the @code{:SI} expansion has no such constraint.
10905 Iterators are applied in the order they are defined. This can be
10906 significant if two iterators are used in a construct that requires
10907 substitutions. @xref{Substitutions}.
10909 @node Substitutions
10910 @subsubsection Substitution in Mode Iterators
10911 @findex define_mode_attr
10913 If an @file{.md} file construct uses mode iterators, each version of the
10914 construct will often need slightly different strings or modes. For
10919 When a @code{define_expand} defines several @code{add@var{m}3} patterns
10920 (@pxref{Standard Names}), each expander will need to use the
10921 appropriate mode name for @var{m}.
10924 When a @code{define_insn} defines several instruction patterns,
10925 each instruction will often use a different assembler mnemonic.
10928 When a @code{define_insn} requires operands with different modes,
10929 using an iterator for one of the operand modes usually requires a specific
10930 mode for the other operand(s).
10933 GCC supports such variations through a system of ``mode attributes''.
10934 There are two standard attributes: @code{mode}, which is the name of
10935 the mode in lower case, and @code{MODE}, which is the same thing in
10936 upper case. You can define other attributes using:
10939 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
10942 where @var{name} is the name of the attribute and @var{valuei}
10943 is the value associated with @var{modei}.
10945 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
10946 each string and mode in the pattern for sequences of the form
10947 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
10948 mode attribute. If the attribute is defined for @var{mode}, the whole
10949 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
10952 For example, suppose an @file{.md} file has:
10955 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10956 (define_mode_attr load [(SI "lw") (DI "ld")])
10959 If one of the patterns that uses @code{:P} contains the string
10960 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
10961 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
10962 @code{"ld\t%0,%1"}.
10964 Here is an example of using an attribute for a mode:
10967 (define_mode_iterator LONG [SI DI])
10968 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
10969 (define_insn @dots{}
10970 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
10973 The @code{@var{iterator}:} prefix may be omitted, in which case the
10974 substitution will be attempted for every iterator expansion.
10977 @subsubsection Mode Iterator Examples
10979 Here is an example from the MIPS port. It defines the following
10980 modes and attributes (among others):
10983 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10984 (define_mode_attr d [(SI "") (DI "d")])
10987 and uses the following template to define both @code{subsi3}
10991 (define_insn "sub<mode>3"
10992 [(set (match_operand:GPR 0 "register_operand" "=d")
10993 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
10994 (match_operand:GPR 2 "register_operand" "d")))]
10996 "<d>subu\t%0,%1,%2"
10997 [(set_attr "type" "arith")
10998 (set_attr "mode" "<MODE>")])
11001 This is exactly equivalent to:
11004 (define_insn "subsi3"
11005 [(set (match_operand:SI 0 "register_operand" "=d")
11006 (minus:SI (match_operand:SI 1 "register_operand" "d")
11007 (match_operand:SI 2 "register_operand" "d")))]
11010 [(set_attr "type" "arith")
11011 (set_attr "mode" "SI")])
11013 (define_insn "subdi3"
11014 [(set (match_operand:DI 0 "register_operand" "=d")
11015 (minus:DI (match_operand:DI 1 "register_operand" "d")
11016 (match_operand:DI 2 "register_operand" "d")))]
11019 [(set_attr "type" "arith")
11020 (set_attr "mode" "DI")])
11023 @node Code Iterators
11024 @subsection Code Iterators
11025 @cindex code iterators in @file{.md} files
11026 @findex define_code_iterator
11027 @findex define_code_attr
11029 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
11034 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
11037 defines a pseudo rtx code @var{name} that can be instantiated as
11038 @var{codei} if condition @var{condi} is true. Each @var{codei}
11039 must have the same rtx format. @xref{RTL Classes}.
11041 As with mode iterators, each pattern that uses @var{name} will be
11042 expanded @var{n} times, once with all uses of @var{name} replaced by
11043 @var{code1}, once with all uses replaced by @var{code2}, and so on.
11044 @xref{Defining Mode Iterators}.
11046 It is possible to define attributes for codes as well as for modes.
11047 There are two standard code attributes: @code{code}, the name of the
11048 code in lower case, and @code{CODE}, the name of the code in upper case.
11049 Other attributes are defined using:
11052 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
11055 Instruction patterns can use code attributes as rtx codes, which can be
11056 useful if two sets of codes act in tandem. For example, the following
11057 @code{define_insn} defines two patterns, one calculating a signed absolute
11058 difference and another calculating an unsigned absolute difference:
11061 (define_code_iterator any_max [smax umax])
11062 (define_code_attr paired_min [(smax "smin") (umax "umin")])
11063 (define_insn @dots{}
11064 [(set (match_operand:SI 0 @dots{})
11065 (minus:SI (any_max:SI (match_operand:SI 1 @dots{})
11066 (match_operand:SI 2 @dots{}))
11067 (<paired_min>:SI (match_dup 1) (match_dup 2))))]
11071 The signed version of the instruction uses @code{smax} and @code{smin}
11072 while the unsigned version uses @code{umax} and @code{umin}. There
11073 are no versions that pair @code{smax} with @code{umin} or @code{umax}
11076 Here's an example of code iterators in action, taken from the MIPS port:
11079 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
11080 eq ne gt ge lt le gtu geu ltu leu])
11082 (define_expand "b<code>"
11084 (if_then_else (any_cond:CC (cc0)
11086 (label_ref (match_operand 0 ""))
11090 gen_conditional_branch (operands, <CODE>);
11095 This is equivalent to:
11098 (define_expand "bunordered"
11100 (if_then_else (unordered:CC (cc0)
11102 (label_ref (match_operand 0 ""))
11106 gen_conditional_branch (operands, UNORDERED);
11110 (define_expand "bordered"
11112 (if_then_else (ordered:CC (cc0)
11114 (label_ref (match_operand 0 ""))
11118 gen_conditional_branch (operands, ORDERED);
11125 @node Int Iterators
11126 @subsection Int Iterators
11127 @cindex int iterators in @file{.md} files
11128 @findex define_int_iterator
11129 @findex define_int_attr
11131 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
11136 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
11139 defines a pseudo integer constant @var{name} that can be instantiated as
11140 @var{inti} if condition @var{condi} is true. Each @var{int}
11141 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
11142 in only those rtx fields that have 'i' as the specifier. This means that
11143 each @var{int} has to be a constant defined using define_constant or
11146 As with mode and code iterators, each pattern that uses @var{name} will be
11147 expanded @var{n} times, once with all uses of @var{name} replaced by
11148 @var{int1}, once with all uses replaced by @var{int2}, and so on.
11149 @xref{Defining Mode Iterators}.
11151 It is possible to define attributes for ints as well as for codes and modes.
11152 Attributes are defined using:
11155 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
11158 Here's an example of int iterators in action, taken from the ARM port:
11161 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
11163 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
11165 (define_insn "neon_vq<absneg><mode>"
11166 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11167 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11168 (match_operand:SI 2 "immediate_operand" "i")]
11171 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
11172 [(set_attr "type" "neon_vqneg_vqabs")]
11177 This is equivalent to:
11180 (define_insn "neon_vqabs<mode>"
11181 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11182 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11183 (match_operand:SI 2 "immediate_operand" "i")]
11186 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
11187 [(set_attr "type" "neon_vqneg_vqabs")]
11190 (define_insn "neon_vqneg<mode>"
11191 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11192 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11193 (match_operand:SI 2 "immediate_operand" "i")]
11196 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
11197 [(set_attr "type" "neon_vqneg_vqabs")]
11202 @node Subst Iterators
11203 @subsection Subst Iterators
11204 @cindex subst iterators in @file{.md} files
11205 @findex define_subst
11206 @findex define_subst_attr
11208 Subst iterators are special type of iterators with the following
11209 restrictions: they could not be declared explicitly, they always have
11210 only two values, and they do not have explicit dedicated name.
11211 Subst-iterators are triggered only when corresponding subst-attribute is
11212 used in RTL-pattern.
11214 Subst iterators transform templates in the following way: the templates
11215 are duplicated, the subst-attributes in these templates are replaced
11216 with the corresponding values, and a new attribute is implicitly added
11217 to the given @code{define_insn}/@code{define_expand}. The name of the
11218 added attribute matches the name of @code{define_subst}. Such
11219 attributes are declared implicitly, and it is not allowed to have a
11220 @code{define_attr} named as a @code{define_subst}.
11222 Each subst iterator is linked to a @code{define_subst}. It is declared
11223 implicitly by the first appearance of the corresponding
11224 @code{define_subst_attr}, and it is not allowed to define it explicitly.
11226 Declarations of subst-attributes have the following syntax:
11228 @findex define_subst_attr
11230 (define_subst_attr "@var{name}"
11232 "@var{no-subst-value}"
11233 "@var{subst-applied-value}")
11236 @var{name} is a string with which the given subst-attribute could be
11239 @var{subst-name} shows which @code{define_subst} should be applied to an
11240 RTL-template if the given subst-attribute is present in the
11243 @var{no-subst-value} is a value with which subst-attribute would be
11244 replaced in the first copy of the original RTL-template.
11246 @var{subst-applied-value} is a value with which subst-attribute would be
11247 replaced in the second copy of the original RTL-template.
11249 @node Parameterized Names
11250 @subsection Parameterized Names
11251 @cindex @samp{@@} in instruction pattern names
11252 Ports sometimes need to apply iterators using C++ code, in order to
11253 get the code or RTL pattern for a specific instruction. For example,
11254 suppose we have the @samp{neon_vq<absneg><mode>} pattern given above:
11257 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
11259 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
11261 (define_insn "neon_vq<absneg><mode>"
11262 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11263 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11264 (match_operand:SI 2 "immediate_operand" "i")]
11270 A port might need to generate this pattern for a variable
11271 @samp{QABSNEG} value and a variable @samp{VDQIW} mode. There are two
11272 ways of doing this. The first is to build the rtx for the pattern
11273 directly from C++ code; this is a valid technique and avoids any risk
11274 of combinatorial explosion. The second is to prefix the instruction
11275 name with the special character @samp{@@}, which tells GCC to generate
11276 the four additional functions below. In each case, @var{name} is the
11277 name of the instruction without the leading @samp{@@} character,
11278 without the @samp{<@dots{}>} placeholders, and with any underscore
11279 before a @samp{<@dots{}>} placeholder removed if keeping it would
11280 lead to a double or trailing underscore.
11283 @item insn_code maybe_code_for_@var{name} (@var{i1}, @var{i2}, @dots{})
11284 See whether replacing the first @samp{<@dots{}>} placeholder with
11285 iterator value @var{i1}, the second with iterator value @var{i2}, and
11286 so on, gives a valid instruction. Return its code if so, otherwise
11287 return @code{CODE_FOR_nothing}.
11289 @item insn_code code_for_@var{name} (@var{i1}, @var{i2}, @dots{})
11290 Same, but abort the compiler if the requested instruction does not exist.
11292 @item rtx maybe_gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{})
11293 Check for a valid instruction in the same way as
11294 @code{maybe_code_for_@var{name}}. If the instruction exists,
11295 generate an instance of it using the operand values given by @var{op0},
11296 @var{op1}, and so on, otherwise return null.
11298 @item rtx gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{})
11299 Same, but abort the compiler if the requested instruction does not exist,
11300 or if the instruction generator invoked the @code{FAIL} macro.
11303 For example, changing the pattern above to:
11306 (define_insn "@@neon_vq<absneg><mode>"
11307 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11308 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11309 (match_operand:SI 2 "immediate_operand" "i")]
11315 would define the same patterns as before, but in addition would generate
11316 the four functions below:
11319 insn_code maybe_code_for_neon_vq (int, machine_mode);
11320 insn_code code_for_neon_vq (int, machine_mode);
11321 rtx maybe_gen_neon_vq (int, machine_mode, rtx, rtx, rtx);
11322 rtx gen_neon_vq (int, machine_mode, rtx, rtx, rtx);
11325 Calling @samp{code_for_neon_vq (UNSPEC_VQABS, V8QImode)}
11326 would then give @code{CODE_FOR_neon_vqabsv8qi}.
11328 It is possible to have multiple @samp{@@} patterns with the same
11329 name and same types of iterator. For example:
11332 (define_insn "@@some_arithmetic_op<mode>"
11333 [(set (match_operand:INTEGER_MODES 0 "register_operand") @dots{})]
11337 (define_insn "@@some_arithmetic_op<mode>"
11338 [(set (match_operand:FLOAT_MODES 0 "register_operand") @dots{})]
11343 would produce a single set of functions that handles both
11344 @code{INTEGER_MODES} and @code{FLOAT_MODES}.