1 @c Copyright (C) 1988-2019 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 A @code{define_insn} expression is used to define instruction patterns
109 to which insns may be matched. A @code{define_insn} expression contains
110 an incomplete RTL expression, with pieces to be filled in later, operand
111 constraints that restrict how the pieces can be filled in, and an output
112 template or C code to generate the assembler output.
114 A @code{define_insn} is an RTL expression containing four or five operands:
118 An optional name @var{n}. When a name is present, the compiler
119 automically generates a C++ function @samp{gen_@var{n}} that takes
120 the operands of the instruction as arguments and returns the instruction's
121 rtx pattern. The compiler also assigns the instruction a unique code
122 @samp{CODE_FOR_@var{n}}, with all such codes belonging to an enum
123 called @code{insn_code}.
125 These names serve one of two purposes. The first is to indicate that the
126 instruction performs a certain standard job for the RTL-generation
127 pass of the compiler, such as a move, an addition, or a conditional
128 jump. The second is to help the target generate certain target-specific
129 operations, such as when implementing target-specific intrinsic functions.
131 It is better to prefix target-specific names with the name of the
132 target, to avoid any clash with current or future standard names.
134 The absence of a name is indicated by writing an empty string
135 where the name should go. Nameless instruction patterns are never
136 used for generating RTL code, but they may permit several simpler insns
137 to be combined later on.
139 For the purpose of debugging the compiler, you may also specify a
140 name beginning with the @samp{*} character. Such a name is used only
141 for identifying the instruction in RTL dumps; it is equivalent to having
142 a nameless pattern for all other purposes. Names beginning with the
143 @samp{*} character are not required to be unique.
145 The name may also have the form @samp{@@@var{n}}. This has the same
146 effect as a name @samp{@var{n}}, but in addition tells the compiler to
147 generate further helper functions; see @ref{Parameterized Names} for details.
150 The @dfn{RTL template}: This is a vector of incomplete RTL expressions
151 which describe the semantics of the instruction (@pxref{RTL Template}).
152 It is incomplete because it may contain @code{match_operand},
153 @code{match_operator}, and @code{match_dup} expressions that stand for
154 operands of the instruction.
156 If the vector has multiple elements, the RTL template is treated as a
157 @code{parallel} expression.
160 @cindex pattern conditions
161 @cindex conditions, in patterns
162 The condition: This is a string which contains a C expression. When the
163 compiler attempts to match RTL against a pattern, the condition is
164 evaluated. If the condition evaluates to @code{true}, the match is
165 permitted. The condition may be an empty string, which is treated
166 as always @code{true}.
168 @cindex named patterns and conditions
169 For a named pattern, the condition may not depend on the data in the
170 insn being matched, but only the target-machine-type flags. The compiler
171 needs to test these conditions during initialization in order to learn
172 exactly which named instructions are available in a particular run.
175 For nameless patterns, the condition is applied only when matching an
176 individual insn, and only after the insn has matched the pattern's
177 recognition template. The insn's operands may be found in the vector
180 An instruction condition cannot become more restrictive as compilation
181 progresses. If the condition accepts a particular RTL instruction at
182 one stage of compilation, it must continue to accept that instruction
183 until the final pass. For example, @samp{!reload_completed} and
184 @samp{can_create_pseudo_p ()} are both invalid instruction conditions,
185 because they are true during the earlier RTL passes and false during
186 the later ones. For the same reason, if a condition accepts an
187 instruction before register allocation, it cannot later try to control
188 register allocation by excluding certain register or value combinations.
190 Although a condition cannot become more restrictive as compilation
191 progresses, the condition for a nameless pattern @emph{can} become
192 more permissive. For example, a nameless instruction can require
193 @samp{reload_completed} to be true, in which case it only matches
194 after register allocation.
197 The @dfn{output template} or @dfn{output statement}: This is either
198 a string, or a fragment of C code which returns a string.
200 When simple substitution isn't general enough, you can specify a piece
201 of C code to compute the output. @xref{Output Statement}.
204 The @dfn{insn attributes}: This is an optional vector containing the values of
205 attributes for insns matching this pattern (@pxref{Insn Attributes}).
209 @section Example of @code{define_insn}
210 @cindex @code{define_insn} example
212 Here is an example of an instruction pattern, taken from the machine
213 description for the 68000/68020.
218 (match_operand:SI 0 "general_operand" "rm"))]
222 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
224 return \"cmpl #0,%0\";
229 This can also be written using braced strings:
234 (match_operand:SI 0 "general_operand" "rm"))]
237 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
243 This describes an instruction which sets the condition codes based on the
244 value of a general operand. It has no condition, so any insn with an RTL
245 description of the form shown may be matched to this pattern. The name
246 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL
247 generation pass that, when it is necessary to test such a value, an insn
248 to do so can be constructed using this pattern.
250 The output control string is a piece of C code which chooses which
251 output template to return based on the kind of operand and the specific
252 type of CPU for which code is being generated.
254 @samp{"rm"} is an operand constraint. Its meaning is explained below.
257 @section RTL Template
258 @cindex RTL insn template
259 @cindex generating insns
260 @cindex insns, generating
261 @cindex recognizing insns
262 @cindex insns, recognizing
264 The RTL template is used to define which insns match the particular pattern
265 and how to find their operands. For named patterns, the RTL template also
266 says how to construct an insn from specified operands.
268 Construction involves substituting specified operands into a copy of the
269 template. Matching involves determining the values that serve as the
270 operands in the insn being matched. Both of these activities are
271 controlled by special expression types that direct matching and
272 substitution of the operands.
275 @findex match_operand
276 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
277 This expression is a placeholder for operand number @var{n} of
278 the insn. When constructing an insn, operand number @var{n}
279 will be substituted at this point. When matching an insn, whatever
280 appears at this position in the insn will be taken as operand
281 number @var{n}; but it must satisfy @var{predicate} or this instruction
282 pattern will not match at all.
284 Operand numbers must be chosen consecutively counting from zero in
285 each instruction pattern. There may be only one @code{match_operand}
286 expression in the pattern for each operand number. Usually operands
287 are numbered in the order of appearance in @code{match_operand}
288 expressions. In the case of a @code{define_expand}, any operand numbers
289 used only in @code{match_dup} expressions have higher values than all
290 other operand numbers.
292 @var{predicate} is a string that is the name of a function that
293 accepts two arguments, an expression and a machine mode.
294 @xref{Predicates}. During matching, the function will be called with
295 the putative operand as the expression and @var{m} as the mode
296 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
297 which normally causes @var{predicate} to accept any mode). If it
298 returns zero, this instruction pattern fails to match.
299 @var{predicate} may be an empty string; then it means no test is to be
300 done on the operand, so anything which occurs in this position is
303 Most of the time, @var{predicate} will reject modes other than @var{m}---but
304 not always. For example, the predicate @code{address_operand} uses
305 @var{m} as the mode of memory ref that the address should be valid for.
306 Many predicates accept @code{const_int} nodes even though their mode is
309 @var{constraint} controls reloading and the choice of the best register
310 class to use for a value, as explained later (@pxref{Constraints}).
311 If the constraint would be an empty string, it can be omitted.
313 People are often unclear on the difference between the constraint and the
314 predicate. The predicate helps decide whether a given insn matches the
315 pattern. The constraint plays no role in this decision; instead, it
316 controls various decisions in the case of an insn which does match.
318 @findex match_scratch
319 @item (match_scratch:@var{m} @var{n} @var{constraint})
320 This expression is also a placeholder for operand number @var{n}
321 and indicates that operand must be a @code{scratch} or @code{reg}
324 When matching patterns, this is equivalent to
327 (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint})
330 but, when generating RTL, it produces a (@code{scratch}:@var{m})
333 If the last few expressions in a @code{parallel} are @code{clobber}
334 expressions whose operands are either a hard register or
335 @code{match_scratch}, the combiner can add or delete them when
336 necessary. @xref{Side Effects}.
339 @item (match_dup @var{n})
340 This expression is also a placeholder for operand number @var{n}.
341 It is used when the operand needs to appear more than once in the
344 In construction, @code{match_dup} acts just like @code{match_operand}:
345 the operand is substituted into the insn being constructed. But in
346 matching, @code{match_dup} behaves differently. It assumes that operand
347 number @var{n} has already been determined by a @code{match_operand}
348 appearing earlier in the recognition template, and it matches only an
349 identical-looking expression.
351 Note that @code{match_dup} should not be used to tell the compiler that
352 a particular register is being used for two operands (example:
353 @code{add} that adds one register to another; the second register is
354 both an input operand and the output operand). Use a matching
355 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
356 operand is used in two places in the template, such as an instruction
357 that computes both a quotient and a remainder, where the opcode takes
358 two input operands but the RTL template has to refer to each of those
359 twice; once for the quotient pattern and once for the remainder pattern.
361 @findex match_operator
362 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
363 This pattern is a kind of placeholder for a variable RTL expression
366 When constructing an insn, it stands for an RTL expression whose
367 expression code is taken from that of operand @var{n}, and whose
368 operands are constructed from the patterns @var{operands}.
370 When matching an expression, it matches an expression if the function
371 @var{predicate} returns nonzero on that expression @emph{and} the
372 patterns @var{operands} match the operands of the expression.
374 Suppose that the function @code{commutative_operator} is defined as
375 follows, to match any expression whose operator is one of the
376 commutative arithmetic operators of RTL and whose mode is @var{mode}:
380 commutative_integer_operator (x, mode)
384 enum rtx_code code = GET_CODE (x);
385 if (GET_MODE (x) != mode)
387 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
388 || code == EQ || code == NE);
392 Then the following pattern will match any RTL expression consisting
393 of a commutative operator applied to two general operands:
396 (match_operator:SI 3 "commutative_operator"
397 [(match_operand:SI 1 "general_operand" "g")
398 (match_operand:SI 2 "general_operand" "g")])
401 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
402 because the expressions to be matched all contain two operands.
404 When this pattern does match, the two operands of the commutative
405 operator are recorded as operands 1 and 2 of the insn. (This is done
406 by the two instances of @code{match_operand}.) Operand 3 of the insn
407 will be the entire commutative expression: use @code{GET_CODE
408 (operands[3])} to see which commutative operator was used.
410 The machine mode @var{m} of @code{match_operator} works like that of
411 @code{match_operand}: it is passed as the second argument to the
412 predicate function, and that function is solely responsible for
413 deciding whether the expression to be matched ``has'' that mode.
415 When constructing an insn, argument 3 of the gen-function will specify
416 the operation (i.e.@: the expression code) for the expression to be
417 made. It should be an RTL expression, whose expression code is copied
418 into a new expression whose operands are arguments 1 and 2 of the
419 gen-function. The subexpressions of argument 3 are not used;
420 only its expression code matters.
422 When @code{match_operator} is used in a pattern for matching an insn,
423 it usually best if the operand number of the @code{match_operator}
424 is higher than that of the actual operands of the insn. This improves
425 register allocation because the register allocator often looks at
426 operands 1 and 2 of insns to see if it can do register tying.
428 There is no way to specify constraints in @code{match_operator}. The
429 operand of the insn which corresponds to the @code{match_operator}
430 never has any constraints because it is never reloaded as a whole.
431 However, if parts of its @var{operands} are matched by
432 @code{match_operand} patterns, those parts may have constraints of
436 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
437 Like @code{match_dup}, except that it applies to operators instead of
438 operands. When constructing an insn, operand number @var{n} will be
439 substituted at this point. But in matching, @code{match_op_dup} behaves
440 differently. It assumes that operand number @var{n} has already been
441 determined by a @code{match_operator} appearing earlier in the
442 recognition template, and it matches only an identical-looking
445 @findex match_parallel
446 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
447 This pattern is a placeholder for an insn that consists of a
448 @code{parallel} expression with a variable number of elements. This
449 expression should only appear at the top level of an insn pattern.
451 When constructing an insn, operand number @var{n} will be substituted at
452 this point. When matching an insn, it matches if the body of the insn
453 is a @code{parallel} expression with at least as many elements as the
454 vector of @var{subpat} expressions in the @code{match_parallel}, if each
455 @var{subpat} matches the corresponding element of the @code{parallel},
456 @emph{and} the function @var{predicate} returns nonzero on the
457 @code{parallel} that is the body of the insn. It is the responsibility
458 of the predicate to validate elements of the @code{parallel} beyond
459 those listed in the @code{match_parallel}.
461 A typical use of @code{match_parallel} is to match load and store
462 multiple expressions, which can contain a variable number of elements
463 in a @code{parallel}. For example,
467 [(match_parallel 0 "load_multiple_operation"
468 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
469 (match_operand:SI 2 "memory_operand" "m"))
471 (clobber (reg:SI 179))])]
476 This example comes from @file{a29k.md}. The function
477 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
478 that subsequent elements in the @code{parallel} are the same as the
479 @code{set} in the pattern, except that they are referencing subsequent
480 registers and memory locations.
482 An insn that matches this pattern might look like:
486 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
488 (clobber (reg:SI 179))
490 (mem:SI (plus:SI (reg:SI 100)
493 (mem:SI (plus:SI (reg:SI 100)
497 @findex match_par_dup
498 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
499 Like @code{match_op_dup}, but for @code{match_parallel} instead of
500 @code{match_operator}.
504 @node Output Template
505 @section Output Templates and Operand Substitution
506 @cindex output templates
507 @cindex operand substitution
509 @cindex @samp{%} in template
511 The @dfn{output template} is a string which specifies how to output the
512 assembler code for an instruction pattern. Most of the template is a
513 fixed string which is output literally. The character @samp{%} is used
514 to specify where to substitute an operand; it can also be used to
515 identify places where different variants of the assembler require
518 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
519 operand @var{n} at that point in the string.
521 @samp{%} followed by a letter and a digit says to output an operand in an
522 alternate fashion. Four letters have standard, built-in meanings described
523 below. The machine description macro @code{PRINT_OPERAND} can define
524 additional letters with nonstandard meanings.
526 @samp{%c@var{digit}} can be used to substitute an operand that is a
527 constant value without the syntax that normally indicates an immediate
530 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
531 the constant is negated before printing.
533 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
534 memory reference, with the actual operand treated as the address. This may
535 be useful when outputting a ``load address'' instruction, because often the
536 assembler syntax for such an instruction requires you to write the operand
537 as if it were a memory reference.
539 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
542 @samp{%=} outputs a number which is unique to each instruction in the
543 entire compilation. This is useful for making local labels to be
544 referred to more than once in a single template that generates multiple
545 assembler instructions.
547 @samp{%} followed by a punctuation character specifies a substitution that
548 does not use an operand. Only one case is standard: @samp{%%} outputs a
549 @samp{%} into the assembler code. Other nonstandard cases can be
550 defined in the @code{PRINT_OPERAND} macro. You must also define
551 which punctuation characters are valid with the
552 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
556 The template may generate multiple assembler instructions. Write the text
557 for the instructions, with @samp{\;} between them.
559 @cindex matching operands
560 When the RTL contains two operands which are required by constraint to match
561 each other, the output template must refer only to the lower-numbered operand.
562 Matching operands are not always identical, and the rest of the compiler
563 arranges to put the proper RTL expression for printing into the lower-numbered
566 One use of nonstandard letters or punctuation following @samp{%} is to
567 distinguish between different assembler languages for the same machine; for
568 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
569 requires periods in most opcode names, while MIT syntax does not. For
570 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
571 syntax. The same file of patterns is used for both kinds of output syntax,
572 but the character sequence @samp{%.} is used in each place where Motorola
573 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
574 defines the sequence to output a period; the macro for MIT syntax defines
577 @cindex @code{#} in template
578 As a special case, a template consisting of the single character @code{#}
579 instructs the compiler to first split the insn, and then output the
580 resulting instructions separately. This helps eliminate redundancy in the
581 output templates. If you have a @code{define_insn} that needs to emit
582 multiple assembler instructions, and there is a matching @code{define_split}
583 already defined, then you can simply use @code{#} as the output template
584 instead of writing an output template that emits the multiple assembler
587 Note that @code{#} only has an effect while generating assembly code;
588 it does not affect whether a split occurs earlier. An associated
589 @code{define_split} must exist and it must be suitable for use after
592 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
593 of the form @samp{@{option0|option1|option2@}} in the templates. These
594 describe multiple variants of assembler language syntax.
595 @xref{Instruction Output}.
597 @node Output Statement
598 @section C Statements for Assembler Output
599 @cindex output statements
600 @cindex C statements for assembler output
601 @cindex generating assembler output
603 Often a single fixed template string cannot produce correct and efficient
604 assembler code for all the cases that are recognized by a single
605 instruction pattern. For example, the opcodes may depend on the kinds of
606 operands; or some unfortunate combinations of operands may require extra
607 machine instructions.
609 If the output control string starts with a @samp{@@}, then it is actually
610 a series of templates, each on a separate line. (Blank lines and
611 leading spaces and tabs are ignored.) The templates correspond to the
612 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
613 if a target machine has a two-address add instruction @samp{addr} to add
614 into a register and another @samp{addm} to add a register to memory, you
615 might write this pattern:
618 (define_insn "addsi3"
619 [(set (match_operand:SI 0 "general_operand" "=r,m")
620 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
621 (match_operand:SI 2 "general_operand" "g,r")))]
628 @cindex @code{*} in template
629 @cindex asterisk in template
630 If the output control string starts with a @samp{*}, then it is not an
631 output template but rather a piece of C program that should compute a
632 template. It should execute a @code{return} statement to return the
633 template-string you want. Most such templates use C string literals, which
634 require doublequote characters to delimit them. To include these
635 doublequote characters in the string, prefix each one with @samp{\}.
637 If the output control string is written as a brace block instead of a
638 double-quoted string, it is automatically assumed to be C code. In that
639 case, it is not necessary to put in a leading asterisk, or to escape the
640 doublequotes surrounding C string literals.
642 The operands may be found in the array @code{operands}, whose C data type
645 It is very common to select different ways of generating assembler code
646 based on whether an immediate operand is within a certain range. Be
647 careful when doing this, because the result of @code{INTVAL} is an
648 integer on the host machine. If the host machine has more bits in an
649 @code{int} than the target machine has in the mode in which the constant
650 will be used, then some of the bits you get from @code{INTVAL} will be
651 superfluous. For proper results, you must carefully disregard the
652 values of those bits.
654 @findex output_asm_insn
655 It is possible to output an assembler instruction and then go on to output
656 or compute more of them, using the subroutine @code{output_asm_insn}. This
657 receives two arguments: a template-string and a vector of operands. The
658 vector may be @code{operands}, or it may be another array of @code{rtx}
659 that you declare locally and initialize yourself.
661 @findex which_alternative
662 When an insn pattern has multiple alternatives in its constraints, often
663 the appearance of the assembler code is determined mostly by which alternative
664 was matched. When this is so, the C code can test the variable
665 @code{which_alternative}, which is the ordinal number of the alternative
666 that was actually satisfied (0 for the first, 1 for the second alternative,
669 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
670 for registers and @samp{clrmem} for memory locations. Here is how
671 a pattern could use @code{which_alternative} to choose between them:
675 [(set (match_operand:SI 0 "general_operand" "=r,m")
679 return (which_alternative == 0
680 ? "clrreg %0" : "clrmem %0");
684 The example above, where the assembler code to generate was
685 @emph{solely} determined by the alternative, could also have been specified
686 as follows, having the output control string start with a @samp{@@}:
691 [(set (match_operand:SI 0 "general_operand" "=r,m")
700 If you just need a little bit of C code in one (or a few) alternatives,
701 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
706 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
711 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
719 @cindex operand predicates
720 @cindex operator predicates
722 A predicate determines whether a @code{match_operand} or
723 @code{match_operator} expression matches, and therefore whether the
724 surrounding instruction pattern will be used for that combination of
725 operands. GCC has a number of machine-independent predicates, and you
726 can define machine-specific predicates as needed. By convention,
727 predicates used with @code{match_operand} have names that end in
728 @samp{_operand}, and those used with @code{match_operator} have names
729 that end in @samp{_operator}.
731 All predicates are boolean functions (in the mathematical sense) of
732 two arguments: the RTL expression that is being considered at that
733 position in the instruction pattern, and the machine mode that the
734 @code{match_operand} or @code{match_operator} specifies. In this
735 section, the first argument is called @var{op} and the second argument
736 @var{mode}. Predicates can be called from C as ordinary two-argument
737 functions; this can be useful in output templates or other
738 machine-specific code.
740 Operand predicates can allow operands that are not actually acceptable
741 to the hardware, as long as the constraints give reload the ability to
742 fix them up (@pxref{Constraints}). However, GCC will usually generate
743 better code if the predicates specify the requirements of the machine
744 instructions as closely as possible. Reload cannot fix up operands
745 that must be constants (``immediate operands''); you must use a
746 predicate that allows only constants, or else enforce the requirement
747 in the extra condition.
749 @cindex predicates and machine modes
750 @cindex normal predicates
751 @cindex special predicates
752 Most predicates handle their @var{mode} argument in a uniform manner.
753 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
754 any mode. If @var{mode} is anything else, then @var{op} must have the
755 same mode, unless @var{op} is a @code{CONST_INT} or integer
756 @code{CONST_DOUBLE}. These RTL expressions always have
757 @code{VOIDmode}, so it would be counterproductive to check that their
758 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
759 integer @code{CONST_DOUBLE} check that the value stored in the
760 constant will fit in the requested mode.
762 Predicates with this behavior are called @dfn{normal}.
763 @command{genrecog} can optimize the instruction recognizer based on
764 knowledge of how normal predicates treat modes. It can also diagnose
765 certain kinds of common errors in the use of normal predicates; for
766 instance, it is almost always an error to use a normal predicate
767 without specifying a mode.
769 Predicates that do something different with their @var{mode} argument
770 are called @dfn{special}. The generic predicates
771 @code{address_operand} and @code{pmode_register_operand} are special
772 predicates. @command{genrecog} does not do any optimizations or
773 diagnosis when special predicates are used.
776 * Machine-Independent Predicates:: Predicates available to all back ends.
777 * Defining Predicates:: How to write machine-specific predicate
781 @node Machine-Independent Predicates
782 @subsection Machine-Independent Predicates
783 @cindex machine-independent predicates
784 @cindex generic predicates
786 These are the generic predicates available to all back ends. They are
787 defined in @file{recog.c}. The first category of predicates allow
788 only constant, or @dfn{immediate}, operands.
790 @defun immediate_operand
791 This predicate allows any sort of constant that fits in @var{mode}.
792 It is an appropriate choice for instructions that take operands that
796 @defun const_int_operand
797 This predicate allows any @code{CONST_INT} expression that fits in
798 @var{mode}. It is an appropriate choice for an immediate operand that
799 does not allow a symbol or label.
802 @defun const_double_operand
803 This predicate accepts any @code{CONST_DOUBLE} expression that has
804 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
805 accept @code{CONST_INT}. It is intended for immediate floating point
810 The second category of predicates allow only some kind of machine
813 @defun register_operand
814 This predicate allows any @code{REG} or @code{SUBREG} expression that
815 is valid for @var{mode}. It is often suitable for arithmetic
816 instruction operands on a RISC machine.
819 @defun pmode_register_operand
820 This is a slight variant on @code{register_operand} which works around
821 a limitation in the machine-description reader.
824 (match_operand @var{n} "pmode_register_operand" @var{constraint})
831 (match_operand:P @var{n} "register_operand" @var{constraint})
835 would mean, if the machine-description reader accepted @samp{:P}
836 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
837 alias for some other mode, and might vary with machine-specific
838 options. @xref{Misc}.
841 @defun scratch_operand
842 This predicate allows hard registers and @code{SCRATCH} expressions,
843 but not pseudo-registers. It is used internally by @code{match_scratch};
844 it should not be used directly.
848 The third category of predicates allow only some kind of memory reference.
850 @defun memory_operand
851 This predicate allows any valid reference to a quantity of mode
852 @var{mode} in memory, as determined by the weak form of
853 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
856 @defun address_operand
857 This predicate is a little unusual; it allows any operand that is a
858 valid expression for the @emph{address} of a quantity of mode
859 @var{mode}, again determined by the weak form of
860 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
861 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
862 @code{memory_operand}, then @var{exp} is acceptable to
863 @code{address_operand}. Note that @var{exp} does not necessarily have
867 @defun indirect_operand
868 This is a stricter form of @code{memory_operand} which allows only
869 memory references with a @code{general_operand} as the address
870 expression. New uses of this predicate are discouraged, because
871 @code{general_operand} is very permissive, so it's hard to tell what
872 an @code{indirect_operand} does or does not allow. If a target has
873 different requirements for memory operands for different instructions,
874 it is better to define target-specific predicates which enforce the
875 hardware's requirements explicitly.
879 This predicate allows a memory reference suitable for pushing a value
880 onto the stack. This will be a @code{MEM} which refers to
881 @code{stack_pointer_rtx}, with a side effect in its address expression
882 (@pxref{Incdec}); which one is determined by the
883 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
887 This predicate allows a memory reference suitable for popping a value
888 off the stack. Again, this will be a @code{MEM} referring to
889 @code{stack_pointer_rtx}, with a side effect in its address
890 expression. However, this time @code{STACK_POP_CODE} is expected.
894 The fourth category of predicates allow some combination of the above
897 @defun nonmemory_operand
898 This predicate allows any immediate or register operand valid for @var{mode}.
901 @defun nonimmediate_operand
902 This predicate allows any register or memory operand valid for @var{mode}.
905 @defun general_operand
906 This predicate allows any immediate, register, or memory operand
907 valid for @var{mode}.
911 Finally, there are two generic operator predicates.
913 @defun comparison_operator
914 This predicate matches any expression which performs an arithmetic
915 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
919 @defun ordered_comparison_operator
920 This predicate matches any expression which performs an arithmetic
921 comparison in @var{mode} and whose expression code is valid for integer
922 modes; that is, the expression code will be one of @code{eq}, @code{ne},
923 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
924 @code{ge}, @code{geu}.
927 @node Defining Predicates
928 @subsection Defining Machine-Specific Predicates
929 @cindex defining predicates
930 @findex define_predicate
931 @findex define_special_predicate
933 Many machines have requirements for their operands that cannot be
934 expressed precisely using the generic predicates. You can define
935 additional predicates using @code{define_predicate} and
936 @code{define_special_predicate} expressions. These expressions have
941 The name of the predicate, as it will be referred to in
942 @code{match_operand} or @code{match_operator} expressions.
945 An RTL expression which evaluates to true if the predicate allows the
946 operand @var{op}, false if it does not. This expression can only use
947 the following RTL codes:
951 When written inside a predicate expression, a @code{MATCH_OPERAND}
952 expression evaluates to true if the predicate it names would allow
953 @var{op}. The operand number and constraint are ignored. Due to
954 limitations in @command{genrecog}, you can only refer to generic
955 predicates and predicates that have already been defined.
958 This expression evaluates to true if @var{op} or a specified
959 subexpression of @var{op} has one of a given list of RTX codes.
961 The first operand of this expression is a string constant containing a
962 comma-separated list of RTX code names (in lower case). These are the
963 codes for which the @code{MATCH_CODE} will be true.
965 The second operand is a string constant which indicates what
966 subexpression of @var{op} to examine. If it is absent or the empty
967 string, @var{op} itself is examined. Otherwise, the string constant
968 must be a sequence of digits and/or lowercase letters. Each character
969 indicates a subexpression to extract from the current expression; for
970 the first character this is @var{op}, for the second and subsequent
971 characters it is the result of the previous character. A digit
972 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
973 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
974 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
975 @code{MATCH_CODE} then examines the RTX code of the subexpression
976 extracted by the complete string. It is not possible to extract
977 components of an @code{rtvec} that is not at position 0 within its RTX
981 This expression has one operand, a string constant containing a C
982 expression. The predicate's arguments, @var{op} and @var{mode}, are
983 available with those names in the C expression. The @code{MATCH_TEST}
984 evaluates to true if the C expression evaluates to a nonzero value.
985 @code{MATCH_TEST} expressions must not have side effects.
991 The basic @samp{MATCH_} expressions can be combined using these
992 logical operators, which have the semantics of the C operators
993 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
994 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
995 arbitrary number of arguments; this has exactly the same effect as
996 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
1000 An optional block of C code, which should execute
1001 @samp{@w{return true}} if the predicate is found to match and
1002 @samp{@w{return false}} if it does not. It must not have any side
1003 effects. The predicate arguments, @var{op} and @var{mode}, are
1004 available with those names.
1006 If a code block is present in a predicate definition, then the RTL
1007 expression must evaluate to true @emph{and} the code block must
1008 execute @samp{@w{return true}} for the predicate to allow the operand.
1009 The RTL expression is evaluated first; do not re-check anything in the
1010 code block that was checked in the RTL expression.
1013 The program @command{genrecog} scans @code{define_predicate} and
1014 @code{define_special_predicate} expressions to determine which RTX
1015 codes are possibly allowed. You should always make this explicit in
1016 the RTL predicate expression, using @code{MATCH_OPERAND} and
1019 Here is an example of a simple predicate definition, from the IA64
1020 machine description:
1024 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
1025 (define_predicate "small_addr_symbolic_operand"
1026 (and (match_code "symbol_ref")
1027 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1032 And here is another, showing the use of the C block.
1036 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1037 (define_predicate "gr_register_operand"
1038 (match_operand 0 "register_operand")
1041 if (GET_CODE (op) == SUBREG)
1042 op = SUBREG_REG (op);
1045 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1050 Predicates written with @code{define_predicate} automatically include
1051 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1052 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1053 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1054 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1055 kind of constant fits in the requested mode. This is because
1056 target-specific predicates that take constants usually have to do more
1057 stringent value checks anyway. If you need the exact same treatment
1058 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1059 provide, use a @code{MATCH_OPERAND} subexpression to call
1060 @code{const_int_operand}, @code{const_double_operand}, or
1061 @code{immediate_operand}.
1063 Predicates written with @code{define_special_predicate} do not get any
1064 automatic mode checks, and are treated as having special mode handling
1065 by @command{genrecog}.
1067 The program @command{genpreds} is responsible for generating code to
1068 test predicates. It also writes a header file containing function
1069 declarations for all machine-specific predicates. It is not necessary
1070 to declare these predicates in @file{@var{cpu}-protos.h}.
1073 @c Most of this node appears by itself (in a different place) even
1074 @c when the INTERNALS flag is clear. Passages that require the internals
1075 @c manual's context are conditionalized to appear only in the internals manual.
1078 @section Operand Constraints
1079 @cindex operand constraints
1082 Each @code{match_operand} in an instruction pattern can specify
1083 constraints for the operands allowed. The constraints allow you to
1084 fine-tune matching within the set of operands allowed by the
1090 @section Constraints for @code{asm} Operands
1091 @cindex operand constraints, @code{asm}
1092 @cindex constraints, @code{asm}
1093 @cindex @code{asm} constraints
1095 Here are specific details on what constraint letters you can use with
1096 @code{asm} operands.
1098 Constraints can say whether
1099 an operand may be in a register, and which kinds of register; whether the
1100 operand can be a memory reference, and which kinds of address; whether the
1101 operand may be an immediate constant, and which possible values it may
1102 have. Constraints can also require two operands to match.
1103 Side-effects aren't allowed in operands of inline @code{asm}, unless
1104 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1105 that the side effects will happen exactly once in an instruction that can update
1106 the addressing register.
1110 * Simple Constraints:: Basic use of constraints.
1111 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1112 * Class Preferences:: Constraints guide which hard register to put things in.
1113 * Modifiers:: More precise control over effects of constraints.
1114 * Machine Constraints:: Existing constraints for some particular machines.
1115 * Disable Insn Alternatives:: Disable insn alternatives using attributes.
1116 * Define Constraints:: How to define machine-specific constraints.
1117 * C Constraint Interface:: How to test constraints from C code.
1123 * Simple Constraints:: Basic use of constraints.
1124 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1125 * Modifiers:: More precise control over effects of constraints.
1126 * Machine Constraints:: Special constraints for some particular machines.
1130 @node Simple Constraints
1131 @subsection Simple Constraints
1132 @cindex simple constraints
1134 The simplest kind of constraint is a string full of letters, each of
1135 which describes one kind of operand that is permitted. Here are
1136 the letters that are allowed:
1140 Whitespace characters are ignored and can be inserted at any position
1141 except the first. This enables each alternative for different operands to
1142 be visually aligned in the machine description even if they have different
1143 number of constraints and modifiers.
1145 @cindex @samp{m} in constraint
1146 @cindex memory references in constraints
1148 A memory operand is allowed, with any kind of address that the machine
1149 supports in general.
1150 Note that the letter used for the general memory constraint can be
1151 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1153 @cindex offsettable address
1154 @cindex @samp{o} in constraint
1156 A memory operand is allowed, but only if the address is
1157 @dfn{offsettable}. This means that adding a small integer (actually,
1158 the width in bytes of the operand, as determined by its machine mode)
1159 may be added to the address and the result is also a valid memory
1162 @cindex autoincrement/decrement addressing
1163 For example, an address which is constant is offsettable; so is an
1164 address that is the sum of a register and a constant (as long as a
1165 slightly larger constant is also within the range of address-offsets
1166 supported by the machine); but an autoincrement or autodecrement
1167 address is not offsettable. More complicated indirect/indexed
1168 addresses may or may not be offsettable depending on the other
1169 addressing modes that the machine supports.
1171 Note that in an output operand which can be matched by another
1172 operand, the constraint letter @samp{o} is valid only when accompanied
1173 by both @samp{<} (if the target machine has predecrement addressing)
1174 and @samp{>} (if the target machine has preincrement addressing).
1176 @cindex @samp{V} in constraint
1178 A memory operand that is not offsettable. In other words, anything that
1179 would fit the @samp{m} constraint but not the @samp{o} constraint.
1181 @cindex @samp{<} in constraint
1183 A memory operand with autodecrement addressing (either predecrement or
1184 postdecrement) is allowed. In inline @code{asm} this constraint is only
1185 allowed if the operand is used exactly once in an instruction that can
1186 handle the side effects. Not using an operand with @samp{<} in constraint
1187 string in the inline @code{asm} pattern at all or using it in multiple
1188 instructions isn't valid, because the side effects wouldn't be performed
1189 or would be performed more than once. Furthermore, on some targets
1190 the operand with @samp{<} in constraint string must be accompanied by
1191 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1192 or @code{%P0} on IA-64.
1194 @cindex @samp{>} in constraint
1196 A memory operand with autoincrement addressing (either preincrement or
1197 postincrement) is allowed. In inline @code{asm} the same restrictions
1198 as for @samp{<} apply.
1200 @cindex @samp{r} in constraint
1201 @cindex registers in constraints
1203 A register operand is allowed provided that it is in a general
1206 @cindex constants in constraints
1207 @cindex @samp{i} in constraint
1209 An immediate integer operand (one with constant value) is allowed.
1210 This includes symbolic constants whose values will be known only at
1211 assembly time or later.
1213 @cindex @samp{n} in constraint
1215 An immediate integer operand with a known numeric value is allowed.
1216 Many systems cannot support assembly-time constants for operands less
1217 than a word wide. Constraints for these operands should use @samp{n}
1218 rather than @samp{i}.
1220 @cindex @samp{I} in constraint
1221 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1222 Other letters in the range @samp{I} through @samp{P} may be defined in
1223 a machine-dependent fashion to permit immediate integer operands with
1224 explicit integer values in specified ranges. For example, on the
1225 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1226 This is the range permitted as a shift count in the shift
1229 @cindex @samp{E} in constraint
1231 An immediate floating operand (expression code @code{const_double}) is
1232 allowed, but only if the target floating point format is the same as
1233 that of the host machine (on which the compiler is running).
1235 @cindex @samp{F} in constraint
1237 An immediate floating operand (expression code @code{const_double} or
1238 @code{const_vector}) is allowed.
1240 @cindex @samp{G} in constraint
1241 @cindex @samp{H} in constraint
1242 @item @samp{G}, @samp{H}
1243 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1244 permit immediate floating operands in particular ranges of values.
1246 @cindex @samp{s} in constraint
1248 An immediate integer operand whose value is not an explicit integer is
1251 This might appear strange; if an insn allows a constant operand with a
1252 value not known at compile time, it certainly must allow any known
1253 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1254 better code to be generated.
1256 For example, on the 68000 in a fullword instruction it is possible to
1257 use an immediate operand; but if the immediate value is between @minus{}128
1258 and 127, better code results from loading the value into a register and
1259 using the register. This is because the load into the register can be
1260 done with a @samp{moveq} instruction. We arrange for this to happen
1261 by defining the letter @samp{K} to mean ``any integer outside the
1262 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1265 @cindex @samp{g} in constraint
1267 Any register, memory or immediate integer operand is allowed, except for
1268 registers that are not general registers.
1270 @cindex @samp{X} in constraint
1273 Any operand whatsoever is allowed, even if it does not satisfy
1274 @code{general_operand}. This is normally used in the constraint of
1275 a @code{match_scratch} when certain alternatives will not actually
1276 require a scratch register.
1279 Any operand whatsoever is allowed.
1282 @cindex @samp{0} in constraint
1283 @cindex digits in constraint
1284 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1285 An operand that matches the specified operand number is allowed. If a
1286 digit is used together with letters within the same alternative, the
1287 digit should come last.
1289 This number is allowed to be more than a single digit. If multiple
1290 digits are encountered consecutively, they are interpreted as a single
1291 decimal integer. There is scant chance for ambiguity, since to-date
1292 it has never been desirable that @samp{10} be interpreted as matching
1293 either operand 1 @emph{or} operand 0. Should this be desired, one
1294 can use multiple alternatives instead.
1296 @cindex matching constraint
1297 @cindex constraint, matching
1298 This is called a @dfn{matching constraint} and what it really means is
1299 that the assembler has only a single operand that fills two roles
1301 considered separate in the RTL insn. For example, an add insn has two
1302 input operands and one output operand in the RTL, but on most CISC
1305 which @code{asm} distinguishes. For example, an add instruction uses
1306 two input operands and an output operand, but on most CISC
1308 machines an add instruction really has only two operands, one of them an
1309 input-output operand:
1315 Matching constraints are used in these circumstances.
1316 More precisely, the two operands that match must include one input-only
1317 operand and one output-only operand. Moreover, the digit must be a
1318 smaller number than the number of the operand that uses it in the
1322 For operands to match in a particular case usually means that they
1323 are identical-looking RTL expressions. But in a few special cases
1324 specific kinds of dissimilarity are allowed. For example, @code{*x}
1325 as an input operand will match @code{*x++} as an output operand.
1326 For proper results in such cases, the output template should always
1327 use the output-operand's number when printing the operand.
1330 @cindex load address instruction
1331 @cindex push address instruction
1332 @cindex address constraints
1333 @cindex @samp{p} in constraint
1335 An operand that is a valid memory address is allowed. This is
1336 for ``load address'' and ``push address'' instructions.
1338 @findex address_operand
1339 @samp{p} in the constraint must be accompanied by @code{address_operand}
1340 as the predicate in the @code{match_operand}. This predicate interprets
1341 the mode specified in the @code{match_operand} as the mode of the memory
1342 reference for which the address would be valid.
1344 @cindex other register constraints
1345 @cindex extensible constraints
1346 @item @var{other-letters}
1347 Other letters can be defined in machine-dependent fashion to stand for
1348 particular classes of registers or other arbitrary operand types.
1349 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1350 for data, address and floating point registers.
1354 In order to have valid assembler code, each operand must satisfy
1355 its constraint. But a failure to do so does not prevent the pattern
1356 from applying to an insn. Instead, it directs the compiler to modify
1357 the code so that the constraint will be satisfied. Usually this is
1358 done by copying an operand into a register.
1360 Contrast, therefore, the two instruction patterns that follow:
1364 [(set (match_operand:SI 0 "general_operand" "=r")
1365 (plus:SI (match_dup 0)
1366 (match_operand:SI 1 "general_operand" "r")))]
1372 which has two operands, one of which must appear in two places, and
1376 [(set (match_operand:SI 0 "general_operand" "=r")
1377 (plus:SI (match_operand:SI 1 "general_operand" "0")
1378 (match_operand:SI 2 "general_operand" "r")))]
1384 which has three operands, two of which are required by a constraint to be
1385 identical. If we are considering an insn of the form
1388 (insn @var{n} @var{prev} @var{next}
1390 (plus:SI (reg:SI 6) (reg:SI 109)))
1395 the first pattern would not apply at all, because this insn does not
1396 contain two identical subexpressions in the right place. The pattern would
1397 say, ``That does not look like an add instruction; try other patterns''.
1398 The second pattern would say, ``Yes, that's an add instruction, but there
1399 is something wrong with it''. It would direct the reload pass of the
1400 compiler to generate additional insns to make the constraint true. The
1401 results might look like this:
1404 (insn @var{n2} @var{prev} @var{n}
1405 (set (reg:SI 3) (reg:SI 6))
1408 (insn @var{n} @var{n2} @var{next}
1410 (plus:SI (reg:SI 3) (reg:SI 109)))
1414 It is up to you to make sure that each operand, in each pattern, has
1415 constraints that can handle any RTL expression that could be present for
1416 that operand. (When multiple alternatives are in use, each pattern must,
1417 for each possible combination of operand expressions, have at least one
1418 alternative which can handle that combination of operands.) The
1419 constraints don't need to @emph{allow} any possible operand---when this is
1420 the case, they do not constrain---but they must at least point the way to
1421 reloading any possible operand so that it will fit.
1425 If the constraint accepts whatever operands the predicate permits,
1426 there is no problem: reloading is never necessary for this operand.
1428 For example, an operand whose constraints permit everything except
1429 registers is safe provided its predicate rejects registers.
1431 An operand whose predicate accepts only constant values is safe
1432 provided its constraints include the letter @samp{i}. If any possible
1433 constant value is accepted, then nothing less than @samp{i} will do;
1434 if the predicate is more selective, then the constraints may also be
1438 Any operand expression can be reloaded by copying it into a register.
1439 So if an operand's constraints allow some kind of register, it is
1440 certain to be safe. It need not permit all classes of registers; the
1441 compiler knows how to copy a register into another register of the
1442 proper class in order to make an instruction valid.
1444 @cindex nonoffsettable memory reference
1445 @cindex memory reference, nonoffsettable
1447 A nonoffsettable memory reference can be reloaded by copying the
1448 address into a register. So if the constraint uses the letter
1449 @samp{o}, all memory references are taken care of.
1452 A constant operand can be reloaded by allocating space in memory to
1453 hold it as preinitialized data. Then the memory reference can be used
1454 in place of the constant. So if the constraint uses the letters
1455 @samp{o} or @samp{m}, constant operands are not a problem.
1458 If the constraint permits a constant and a pseudo register used in an insn
1459 was not allocated to a hard register and is equivalent to a constant,
1460 the register will be replaced with the constant. If the predicate does
1461 not permit a constant and the insn is re-recognized for some reason, the
1462 compiler will crash. Thus the predicate must always recognize any
1463 objects allowed by the constraint.
1466 If the operand's predicate can recognize registers, but the constraint does
1467 not permit them, it can make the compiler crash. When this operand happens
1468 to be a register, the reload pass will be stymied, because it does not know
1469 how to copy a register temporarily into memory.
1471 If the predicate accepts a unary operator, the constraint applies to the
1472 operand. For example, the MIPS processor at ISA level 3 supports an
1473 instruction which adds two registers in @code{SImode} to produce a
1474 @code{DImode} result, but only if the registers are correctly sign
1475 extended. This predicate for the input operands accepts a
1476 @code{sign_extend} of an @code{SImode} register. Write the constraint
1477 to indicate the type of register that is required for the operand of the
1481 @node Multi-Alternative
1482 @subsection Multiple Alternative Constraints
1483 @cindex multiple alternative constraints
1485 Sometimes a single instruction has multiple alternative sets of possible
1486 operands. For example, on the 68000, a logical-or instruction can combine
1487 register or an immediate value into memory, or it can combine any kind of
1488 operand into a register; but it cannot combine one memory location into
1491 These constraints are represented as multiple alternatives. An alternative
1492 can be described by a series of letters for each operand. The overall
1493 constraint for an operand is made from the letters for this operand
1494 from the first alternative, a comma, the letters for this operand from
1495 the second alternative, a comma, and so on until the last alternative.
1496 All operands for a single instruction must have the same number of
1499 Here is how it is done for fullword logical-or on the 68000:
1502 (define_insn "iorsi3"
1503 [(set (match_operand:SI 0 "general_operand" "=m,d")
1504 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1505 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1509 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1510 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1511 2. The second alternative has @samp{d} (data register) for operand 0,
1512 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1513 @samp{%} in the constraints apply to all the alternatives; their
1514 meaning is explained in the next section (@pxref{Class Preferences}).
1516 If all the operands fit any one alternative, the instruction is valid.
1517 Otherwise, for each alternative, the compiler counts how many instructions
1518 must be added to copy the operands so that that alternative applies.
1519 The alternative requiring the least copying is chosen. If two alternatives
1520 need the same amount of copying, the one that comes first is chosen.
1521 These choices can be altered with the @samp{?} and @samp{!} characters:
1524 @cindex @samp{?} in constraint
1525 @cindex question mark
1527 Disparage slightly the alternative that the @samp{?} appears in,
1528 as a choice when no alternative applies exactly. The compiler regards
1529 this alternative as one unit more costly for each @samp{?} that appears
1532 @cindex @samp{!} in constraint
1533 @cindex exclamation point
1535 Disparage severely the alternative that the @samp{!} appears in.
1536 This alternative can still be used if it fits without reloading,
1537 but if reloading is needed, some other alternative will be used.
1539 @cindex @samp{^} in constraint
1542 This constraint is analogous to @samp{?} but it disparages slightly
1543 the alternative only if the operand with the @samp{^} needs a reload.
1545 @cindex @samp{$} in constraint
1548 This constraint is analogous to @samp{!} but it disparages severely
1549 the alternative only if the operand with the @samp{$} needs a reload.
1552 When an insn pattern has multiple alternatives in its constraints, often
1553 the appearance of the assembler code is determined mostly by which
1554 alternative was matched. When this is so, the C code for writing the
1555 assembler code can use the variable @code{which_alternative}, which is
1556 the ordinal number of the alternative that was actually satisfied (0 for
1557 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1561 So the first alternative for the 68000's logical-or could be written as
1562 @code{"+m" (output) : "ir" (input)}. The second could be @code{"+r"
1563 (output): "irm" (input)}. However, the fact that two memory locations
1564 cannot be used in a single instruction prevents simply using @code{"+rm"
1565 (output) : "irm" (input)}. Using multi-alternatives, this might be
1566 written as @code{"+m,r" (output) : "ir,irm" (input)}. This describes
1567 all the available alternatives to the compiler, allowing it to choose
1568 the most efficient one for the current conditions.
1570 There is no way within the template to determine which alternative was
1571 chosen. However you may be able to wrap your @code{asm} statements with
1572 builtins such as @code{__builtin_constant_p} to achieve the desired results.
1576 @node Class Preferences
1577 @subsection Register Class Preferences
1578 @cindex class preference constraints
1579 @cindex register class preference constraints
1581 @cindex voting between constraint alternatives
1582 The operand constraints have another function: they enable the compiler
1583 to decide which kind of hardware register a pseudo register is best
1584 allocated to. The compiler examines the constraints that apply to the
1585 insns that use the pseudo register, looking for the machine-dependent
1586 letters such as @samp{d} and @samp{a} that specify classes of registers.
1587 The pseudo register is put in whichever class gets the most ``votes''.
1588 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1589 favor of a general register. The machine description says which registers
1590 are considered general.
1592 Of course, on some machines all registers are equivalent, and no register
1593 classes are defined. Then none of this complexity is relevant.
1597 @subsection Constraint Modifier Characters
1598 @cindex modifiers in constraints
1599 @cindex constraint modifier characters
1601 @c prevent bad page break with this line
1602 Here are constraint modifier characters.
1605 @cindex @samp{=} in constraint
1607 Means that this operand is written to by this instruction:
1608 the previous value is discarded and replaced by new data.
1610 @cindex @samp{+} in constraint
1612 Means that this operand is both read and written by the instruction.
1614 When the compiler fixes up the operands to satisfy the constraints,
1615 it needs to know which operands are read by the instruction and
1616 which are written by it. @samp{=} identifies an operand which is only
1617 written; @samp{+} identifies an operand that is both read and written; all
1618 other operands are assumed to only be read.
1620 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1621 first character of the constraint string.
1623 @cindex @samp{&} in constraint
1624 @cindex earlyclobber operand
1626 Means (in a particular alternative) that this operand is an
1627 @dfn{earlyclobber} operand, which is written before the instruction is
1628 finished using the input operands. Therefore, this operand may not lie
1629 in a register that is read by the instruction or as part of any memory
1632 @samp{&} applies only to the alternative in which it is written. In
1633 constraints with multiple alternatives, sometimes one alternative
1634 requires @samp{&} while others do not. See, for example, the
1635 @samp{movdf} insn of the 68000.
1637 A operand which is read by the instruction can be tied to an earlyclobber
1638 operand if its only use as an input occurs before the early result is
1639 written. Adding alternatives of this form often allows GCC to produce
1640 better code when only some of the read operands can be affected by the
1641 earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@.
1643 Furthermore, if the @dfn{earlyclobber} operand is also a read/write
1644 operand, then that operand is written only after it's used.
1646 @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As
1647 @dfn{earlyclobber} operands are always written, a read-only
1648 @dfn{earlyclobber} operand is ill-formed and will be rejected by the
1651 @cindex @samp{%} in constraint
1653 Declares the instruction to be commutative for this operand and the
1654 following operand. This means that the compiler may interchange the
1655 two operands if that is the cheapest way to make all operands fit the
1656 constraints. @samp{%} applies to all alternatives and must appear as
1657 the first character in the constraint. Only read-only operands can use
1661 This is often used in patterns for addition instructions
1662 that really have only two operands: the result must go in one of the
1663 arguments. Here for example, is how the 68000 halfword-add
1664 instruction is defined:
1667 (define_insn "addhi3"
1668 [(set (match_operand:HI 0 "general_operand" "=m,r")
1669 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1670 (match_operand:HI 2 "general_operand" "di,g")))]
1674 GCC can only handle one commutative pair in an asm; if you use more,
1675 the compiler may fail. Note that you need not use the modifier if
1676 the two alternatives are strictly identical; this would only waste
1677 time in the reload pass.
1679 The modifier is not operational after
1680 register allocation, so the result of @code{define_peephole2}
1681 and @code{define_split}s performed after reload cannot rely on
1682 @samp{%} to make the intended insn match.
1684 @cindex @samp{#} in constraint
1686 Says that all following characters, up to the next comma, are to be
1687 ignored as a constraint. They are significant only for choosing
1688 register preferences.
1690 @cindex @samp{*} in constraint
1692 Says that the following character should be ignored when choosing
1693 register preferences. @samp{*} has no effect on the meaning of the
1694 constraint as a constraint, and no effect on reloading. For LRA
1695 @samp{*} additionally disparages slightly the alternative if the
1696 following character matches the operand.
1698 Here is an example: the 68000 has an instruction to sign-extend a
1699 halfword in a data register, and can also sign-extend a value by
1700 copying it into an address register. While either kind of register is
1701 acceptable, the constraints on an address-register destination are
1702 less strict, so it is best if register allocation makes an address
1703 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1704 constraint letter (for data register) is ignored when computing
1705 register preferences.
1708 (define_insn "extendhisi2"
1709 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1711 (match_operand:HI 1 "general_operand" "0,g")))]
1717 @node Machine Constraints
1718 @subsection Constraints for Particular Machines
1719 @cindex machine specific constraints
1720 @cindex constraints, machine specific
1722 Whenever possible, you should use the general-purpose constraint letters
1723 in @code{asm} arguments, since they will convey meaning more readily to
1724 people reading your code. Failing that, use the constraint letters
1725 that usually have very similar meanings across architectures. The most
1726 commonly used constraints are @samp{m} and @samp{r} (for memory and
1727 general-purpose registers respectively; @pxref{Simple Constraints}), and
1728 @samp{I}, usually the letter indicating the most common
1729 immediate-constant format.
1731 Each architecture defines additional constraints. These constraints
1732 are used by the compiler itself for instruction generation, as well as
1733 for @code{asm} statements; therefore, some of the constraints are not
1734 particularly useful for @code{asm}. Here is a summary of some of the
1735 machine-dependent constraints available on some particular machines;
1736 it includes both constraints that are useful for @code{asm} and
1737 constraints that aren't. The compiler source file mentioned in the
1738 table heading for each architecture is the definitive reference for
1739 the meanings of that architecture's constraints.
1741 @c Please keep this table alphabetized by target!
1743 @item AArch64 family---@file{config/aarch64/constraints.md}
1746 The stack pointer register (@code{SP})
1749 Floating point register, Advanced SIMD vector register or SVE vector register
1752 One of the low eight SVE predicate registers (@code{P0} to @code{P7})
1755 Any of the SVE predicate registers (@code{P0} to @code{P15})
1758 Integer constant that is valid as an immediate operand in an @code{ADD}
1762 Integer constant that is valid as an immediate operand in a @code{SUB}
1763 instruction (once negated)
1766 Integer constant that can be used with a 32-bit logical instruction
1769 Integer constant that can be used with a 64-bit logical instruction
1772 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1773 pseudo instruction. The @code{MOV} may be assembled to one of several different
1774 machine instructions depending on the value
1777 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1781 An absolute symbolic address or a label reference
1784 Floating point constant zero
1787 Integer constant zero
1790 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1791 within 4GB of the instruction
1794 A memory address which uses a single base register with no offset
1797 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1803 @item AMD GCN ---@file{config/gcn/constraints.md}
1806 Immediate integer in the range @minus{}16 to 64
1809 Immediate 16-bit signed integer
1812 Immediate constant @minus{}1
1815 Immediate 15-bit unsigned integer
1818 Immediate constant that can be inlined in an instruction encoding: integer
1819 @minus{}16..64, or float 0.0, +/@minus{}0.5, +/@minus{}1.0, +/@minus{}2.0,
1820 +/@minus{}4.0, 1.0/(2.0*PI)
1823 Immediate 32-bit signed integer that can be attached to an instruction encoding
1826 Immediate 32-bit integer in range @minus{}16..4294967295 (i.e. 32-bit unsigned
1827 integer or @samp{A} constraint)
1830 Immediate 64-bit constant that can be split into two @samp{A} constants
1833 Immediate 64-bit constant that can be split into two @samp{B} constants
1839 Any @code{symbol_ref} or @code{label_ref}
1848 SGPR registers valid for instruction destinations, including VCC, M0 and EXEC
1851 SGPR registers valid for instruction sources, including VCC, M0, EXEC and SCC
1854 SGPR registers valid as a source for scalar memory instructions (excludes M0
1858 SGPR registers valid as a source or destination for vector instructions
1862 All condition registers: SCC, VCCZ, EXECZ
1865 Scalar condition register: SCC
1868 Vector condition register: VCC, VCC_LO, VCC_HI
1871 EXEC register (EXEC_LO and EXEC_HI)
1874 Memory operand with address space suitable for @code{buffer_*} instructions
1877 Memory operand with address space suitable for @code{flat_*} instructions
1880 Memory operand with address space suitable for @code{s_*} instructions
1883 Memory operand with address space suitable for @code{ds_*} LDS instructions
1886 Memory operand with address space suitable for @code{ds_*} GDS instructions
1889 Memory operand with address space suitable for any @code{ds_*} instructions
1892 Memory operand with address space suitable for @code{global_*} instructions
1897 @item ARC ---@file{config/arc/constraints.md}
1900 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1901 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1902 option is in effect.
1905 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1906 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1907 This constraint can only match when the @option{-mq}
1908 option is in effect.
1910 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1913 A signed 12-bit integer constant.
1916 constant for arithmetic/logical operations. This might be any constant
1917 that can be put into a long immediate by the assmbler or linker without
1918 involving a PIC relocation.
1921 A 3-bit unsigned integer constant.
1924 A 6-bit unsigned integer constant.
1927 One's complement of a 6-bit unsigned integer constant.
1930 Two's complement of a 6-bit unsigned integer constant.
1933 A 5-bit unsigned integer constant.
1936 A 7-bit unsigned integer constant.
1939 A 8-bit unsigned integer constant.
1942 Any const_double value.
1945 @item ARM family---@file{config/arm/constraints.md}
1949 In Thumb state, the core registers @code{r8}-@code{r15}.
1952 The stack pointer register.
1955 In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this
1956 is an alias for the @code{r} constraint.
1959 VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values.
1962 VFP floating-point registers @code{d0}-@code{d31} and the appropriate
1963 subset @code{d0}-@code{d15} based on command line options.
1964 Used for 64 bit values only. Not valid for Thumb1.
1967 The iWMMX co-processor registers.
1970 The iWMMX GR registers.
1973 The floating-point constant 0.0
1976 Integer that is valid as an immediate operand in a data processing
1977 instruction. That is, an integer in the range 0 to 255 rotated by a
1981 Integer in the range @minus{}4095 to 4095
1984 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1987 Integer that satisfies constraint @samp{I} when negated (twos complement)
1990 Integer in the range 0 to 32
1993 A memory reference where the exact address is in a single register
1994 (`@samp{m}' is preferable for @code{asm} statements)
1997 An item in the constant pool
2000 A symbol in the text segment of the current file
2003 A memory reference suitable for VFP load/store insns (reg+constant offset)
2006 A memory reference suitable for iWMMXt load/store instructions.
2009 A memory reference suitable for the ARMv4 ldrsb instruction.
2012 @item AVR family---@file{config/avr/constraints.md}
2015 Registers from r0 to r15
2018 Registers from r16 to r23
2021 Registers from r16 to r31
2024 Registers from r24 to r31. These registers can be used in @samp{adiw} command
2027 Pointer register (r26--r31)
2030 Base pointer register (r28--r31)
2033 Stack pointer register (SPH:SPL)
2036 Temporary register r0
2039 Register pair X (r27:r26)
2042 Register pair Y (r29:r28)
2045 Register pair Z (r31:r30)
2048 Constant greater than @minus{}1, less than 64
2051 Constant greater than @minus{}64, less than 1
2060 Constant that fits in 8 bits
2063 Constant integer @minus{}1
2066 Constant integer 8, 16, or 24
2072 A floating point constant 0.0
2075 A memory address based on Y or Z pointer with displacement.
2078 @item Blackfin family---@file{config/bfin/constraints.md}
2087 A call clobbered P register.
2090 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2091 register. If it is @code{A}, then the register P0.
2094 Even-numbered D register
2097 Odd-numbered D register
2100 Accumulator register.
2103 Even-numbered accumulator register.
2106 Odd-numbered accumulator register.
2118 Registers used for circular buffering, i.e.@: I, B, or L registers.
2133 Any D, P, B, M, I or L register.
2136 Additional registers typically used only in prologues and epilogues: RETS,
2137 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2140 Any register except accumulators or CC.
2143 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2146 Unsigned 16 bit integer (in the range 0 to 65535)
2149 Signed 7 bit integer (in the range @minus{}64 to 63)
2152 Unsigned 7 bit integer (in the range 0 to 127)
2155 Unsigned 5 bit integer (in the range 0 to 31)
2158 Signed 4 bit integer (in the range @minus{}8 to 7)
2161 Signed 3 bit integer (in the range @minus{}3 to 4)
2164 Unsigned 3 bit integer (in the range 0 to 7)
2167 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2170 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2171 use with either accumulator.
2174 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2175 use only with accumulator A1.
2184 An integer constant with exactly a single bit set.
2187 An integer constant with all bits set except exactly one.
2195 @item CR16 Architecture---@file{config/cr16/cr16.h}
2199 Registers from r0 to r14 (registers without stack pointer)
2202 Register from r0 to r11 (all 16-bit registers)
2205 Register from r12 to r15 (all 32-bit registers)
2208 Signed constant that fits in 4 bits
2211 Signed constant that fits in 5 bits
2214 Signed constant that fits in 6 bits
2217 Unsigned constant that fits in 4 bits
2220 Signed constant that fits in 32 bits
2223 Check for 64 bits wide constants for add/sub instructions
2226 Floating point constant that is legal for store immediate
2229 @item C-SKY---@file{config/csky/constraints.md}
2233 The mini registers r0 - r7.
2236 The low registers r0 - r15.
2242 HI and LO registers.
2254 Stack pointer register (SP).
2258 The C-SKY back end supports a large set of additional constraints
2259 that are only useful for instruction selection or splitting rather
2260 than inline asm, such as constraints representing constant integer
2261 ranges accepted by particular instruction encodings.
2262 Refer to the source code for details.
2265 @item Epiphany---@file{config/epiphany/constraints.md}
2268 An unsigned 16-bit constant.
2271 An unsigned 5-bit constant.
2274 A signed 11-bit constant.
2277 A signed 11-bit constant added to @minus{}1.
2278 Can only match when the @option{-m1reg-@var{reg}} option is active.
2281 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
2282 being a block of trailing zeroes.
2283 Can only match when the @option{-m1reg-@var{reg}} option is active.
2286 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
2287 rest being zeroes. Or to put it another way, one less than a power of two.
2288 Can only match when the @option{-m1reg-@var{reg}} option is active.
2291 Constant for arithmetic/logical operations.
2292 This is like @code{i}, except that for position independent code,
2293 no symbols / expressions needing relocations are allowed.
2296 Symbolic constant for call/jump instruction.
2299 The register class usable in short insns. This is a register class
2300 constraint, and can thus drive register allocation.
2301 This constraint won't match unless @option{-mprefer-short-insn-regs} is
2305 The the register class of registers that can be used to hold a
2306 sibcall call address. I.e., a caller-saved register.
2309 Core control register class.
2312 The register group usable in short insns.
2313 This constraint does not use a register class, so that it only
2314 passively matches suitable registers, and doesn't drive register allocation.
2318 Constant suitable for the addsi3_r pattern. This is a valid offset
2319 For byte, halfword, or word addressing.
2323 Matches the return address if it can be replaced with the link register.
2326 Matches the integer condition code register.
2329 Matches the return address if it is in a stack slot.
2332 Matches control register values to switch fp mode, which are encapsulated in
2333 @code{UNSPEC_FP_MODE}.
2336 @item FRV---@file{config/frv/frv.h}
2339 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2342 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2345 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2346 @code{icc0} to @code{icc3}).
2349 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2352 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2353 Odd registers are excluded not in the class but through the use of a machine
2354 mode larger than 4 bytes.
2357 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2360 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2361 Odd registers are excluded not in the class but through the use of a machine
2362 mode larger than 4 bytes.
2365 Register in the class @code{LR_REG} (the @code{lr} register).
2368 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2369 Register numbers not divisible by 4 are excluded not in the class but through
2370 the use of a machine mode larger than 8 bytes.
2373 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2376 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2379 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2382 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2385 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2386 Register numbers not divisible by 4 are excluded not in the class but through
2387 the use of a machine mode larger than 8 bytes.
2390 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2393 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2396 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2399 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2402 Floating point constant zero
2405 6-bit signed integer constant
2408 10-bit signed integer constant
2411 16-bit signed integer constant
2414 16-bit unsigned integer constant
2417 12-bit signed integer constant that is negative---i.e.@: in the
2418 range of @minus{}2048 to @minus{}1
2424 12-bit signed integer constant that is greater than zero---i.e.@: in the
2429 @item FT32---@file{config/ft32/constraints.md}
2438 A register indirect memory operand
2447 The constant zero or one
2450 A 16-bit signed constant (@minus{}32768 @dots{} 32767)
2453 A bitfield mask suitable for bext or bins
2456 An inverted bitfield mask suitable for bext or bins
2459 A 16-bit unsigned constant, multiple of 4 (0 @dots{} 65532)
2462 A 20-bit signed constant (@minus{}524288 @dots{} 524287)
2465 A constant for a bitfield width (1 @dots{} 16)
2468 A 10-bit signed constant (@minus{}512 @dots{} 511)
2472 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2478 Floating point register
2481 Shift amount register
2484 Floating point register (deprecated)
2487 Upper floating point register (32-bit), floating point register (64-bit)
2493 Signed 11-bit integer constant
2496 Signed 14-bit integer constant
2499 Integer constant that can be deposited with a @code{zdepi} instruction
2502 Signed 5-bit integer constant
2508 Integer constant that can be loaded with a @code{ldil} instruction
2511 Integer constant whose value plus one is a power of 2
2514 Integer constant that can be used for @code{and} operations in @code{depi}
2515 and @code{extru} instructions
2524 Floating-point constant 0.0
2527 A @code{lo_sum} data-linkage-table memory operand
2530 A memory operand that can be used as the destination operand of an
2531 integer store instruction
2534 A scaled or unscaled indexed memory operand
2537 A memory operand for floating-point loads and stores
2540 A register indirect memory operand
2543 @item Intel IA-64---@file{config/ia64/ia64.h}
2546 General register @code{r0} to @code{r3} for @code{addl} instruction
2552 Predicate register (@samp{c} as in ``conditional'')
2555 Application register residing in M-unit
2558 Application register residing in I-unit
2561 Floating-point register
2564 Memory operand. If used together with @samp{<} or @samp{>},
2565 the operand can have postincrement and postdecrement which
2566 require printing with @samp{%Pn} on IA-64.
2569 Floating-point constant 0.0 or 1.0
2572 14-bit signed integer constant
2575 22-bit signed integer constant
2578 8-bit signed integer constant for logical instructions
2581 8-bit adjusted signed integer constant for compare pseudo-ops
2584 6-bit unsigned integer constant for shift counts
2587 9-bit signed integer constant for load and store postincrements
2593 0 or @minus{}1 for @code{dep} instruction
2596 Non-volatile memory for floating-point loads and stores
2599 Integer constant in the range 1 to 4 for @code{shladd} instruction
2602 Memory operand except postincrement and postdecrement. This is
2603 now roughly the same as @samp{m} when not used together with @samp{<}
2607 @item M32C---@file{config/m32c/m32c.c}
2612 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2615 Any control register, when they're 16 bits wide (nothing if control
2616 registers are 24 bits wide)
2619 Any control register, when they're 24 bits wide.
2628 $r0 or $r2, or $r2r0 for 32 bit values.
2631 $r1 or $r3, or $r3r1 for 32 bit values.
2634 A register that can hold a 64 bit value.
2637 $r0 or $r1 (registers with addressable high/low bytes)
2646 Address registers when they're 16 bits wide.
2649 Address registers when they're 24 bits wide.
2652 Registers that can hold QI values.
2655 Registers that can be used with displacements ($a0, $a1, $sb).
2658 Registers that can hold 32 bit values.
2661 Registers that can hold 16 bit values.
2664 Registers chat can hold 16 bit values, including all control
2668 $r0 through R1, plus $a0 and $a1.
2674 The memory-based pseudo-registers $mem0 through $mem15.
2677 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2678 bit registers for m32cm, m32c).
2681 Matches multiple registers in a PARALLEL to form a larger register.
2682 Used to match function return values.
2688 @minus{}128 @dots{} 127
2691 @minus{}32768 @dots{} 32767
2697 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2700 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2703 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2706 @minus{}65536 @dots{} @minus{}1
2709 An 8 bit value with exactly one bit set.
2712 A 16 bit value with exactly one bit set.
2715 The common src/dest memory addressing modes.
2718 Memory addressed using $a0 or $a1.
2721 Memory addressed with immediate addresses.
2724 Memory addressed using the stack pointer ($sp).
2727 Memory addressed using the frame base register ($fb).
2730 Memory addressed using the small base register ($sb).
2736 @item MicroBlaze---@file{config/microblaze/constraints.md}
2739 A general register (@code{r0} to @code{r31}).
2742 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2746 @item MIPS---@file{config/mips/constraints.md}
2749 A general-purpose register. This is equivalent to @code{r} unless
2750 generating MIPS16 code, in which case the MIPS16 register set is used.
2753 A floating-point register (if available).
2756 Formerly the @code{hi} register. This constraint is no longer supported.
2759 The @code{lo} register. Use this register to store values that are
2760 no bigger than a word.
2763 The concatenated @code{hi} and @code{lo} registers. Use this register
2764 to store doubleword values.
2767 A register suitable for use in an indirect jump. This will always be
2768 @code{$25} for @option{-mabicalls}.
2771 Register @code{$3}. Do not use this constraint in new code;
2772 it is retained only for compatibility with glibc.
2775 Equivalent to @code{r}; retained for backwards compatibility.
2778 A floating-point condition code register.
2781 A signed 16-bit constant (for arithmetic instructions).
2787 An unsigned 16-bit constant (for logic instructions).
2790 A signed 32-bit constant in which the lower 16 bits are zero.
2791 Such constants can be loaded using @code{lui}.
2794 A constant that cannot be loaded using @code{lui}, @code{addiu}
2798 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2801 A signed 15-bit constant.
2804 A constant in the range 1 to 65535 (inclusive).
2807 Floating-point zero.
2810 An address that can be used in a non-macro load or store.
2813 A memory operand whose address is formed by a base register and offset
2814 that is suitable for use in instructions with the same addressing mode
2815 as @code{ll} and @code{sc}.
2818 An address suitable for a @code{prefetch} instruction, or for any other
2819 instruction with the same addressing mode as @code{prefetch}.
2822 @item Motorola 680x0---@file{config/m68k/constraints.md}
2831 68881 floating-point register, if available
2834 Integer in the range 1 to 8
2837 16-bit signed number
2840 Signed number whose magnitude is greater than 0x80
2843 Integer in the range @minus{}8 to @minus{}1
2846 Signed number whose magnitude is greater than 0x100
2849 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2852 16 (for rotate using swap)
2855 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2858 Numbers that mov3q can handle
2861 Floating point constant that is not a 68881 constant
2864 Operands that satisfy 'm' when -mpcrel is in effect
2867 Operands that satisfy 's' when -mpcrel is not in effect
2870 Address register indirect addressing mode
2873 Register offset addressing
2888 Range of signed numbers that don't fit in 16 bits
2891 Integers valid for mvq
2894 Integers valid for a moveq followed by a swap
2897 Integers valid for mvz
2900 Integers valid for mvs
2906 Non-register operands allowed in clr
2910 @item Moxie---@file{config/moxie/constraints.md}
2919 A register indirect memory operand
2922 A constant in the range of 0 to 255.
2925 A constant in the range of 0 to @minus{}255.
2929 @item MSP430--@file{config/msp430/constraints.md}
2942 Integer constant -1^20..1^19.
2945 Integer constant 1-4.
2948 Memory references which do not require an extended MOVX instruction.
2951 Memory reference, labels only.
2954 Memory reference, stack only.
2958 @item NDS32---@file{config/nds32/constraints.md}
2961 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
2963 LOW register class $r0 to $r7.
2965 MIDDLE register class $r0 to $r11, $r16 to $r19.
2967 HIGH register class $r12 to $r14, $r20 to $r31.
2969 Temporary assist register $ta (i.e.@: $r15).
2973 Unsigned immediate 3-bit value.
2975 Negative immediate 3-bit value in the range of @minus{}7--0.
2977 Unsigned immediate 4-bit value.
2979 Signed immediate 5-bit value.
2981 Unsigned immediate 5-bit value.
2983 Negative immediate 5-bit value in the range of @minus{}31--0.
2985 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
2987 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
2989 Unsigned immediate 8-bit value.
2991 Unsigned immediate 9-bit value.
2993 Signed immediate 10-bit value.
2995 Signed immediate 11-bit value.
2997 Signed immediate 15-bit value.
2999 Unsigned immediate 15-bit value.
3001 A constant which is not in the range of imm15u but ok for bclr instruction.
3003 A constant which is not in the range of imm15u but ok for bset instruction.
3005 A constant which is not in the range of imm15u but ok for btgl instruction.
3007 A constant whose compliment value is in the range of imm15u
3008 and ok for bitci instruction.
3010 Signed immediate 16-bit value.
3012 Signed immediate 17-bit value.
3014 Signed immediate 19-bit value.
3016 Signed immediate 20-bit value.
3018 The immediate value that can be simply set high 20-bit.
3020 The immediate value 0xff.
3022 The immediate value 0xffff.
3024 The immediate value 0x01.
3026 The immediate value 0x7ff.
3028 The immediate value with power of 2.
3030 The immediate value with power of 2 minus 1.
3032 Memory constraint for 333 format.
3034 Memory constraint for 45 format.
3036 Memory constraint for 37 format.
3039 @item Nios II family---@file{config/nios2/constraints.md}
3043 Integer that is valid as an immediate operand in an
3044 instruction taking a signed 16-bit number. Range
3045 @minus{}32768 to 32767.
3048 Integer that is valid as an immediate operand in an
3049 instruction taking an unsigned 16-bit number. Range
3053 Integer that is valid as an immediate operand in an
3054 instruction taking only the upper 16-bits of a
3055 32-bit number. Range 32-bit numbers with the lower
3059 Integer that is valid as an immediate operand for a
3060 shift instruction. Range 0 to 31.
3063 Integer that is valid as an immediate operand for
3064 only the value 0. Can be used in conjunction with
3065 the format modifier @code{z} to use @code{r0}
3066 instead of @code{0} in the assembly output.
3069 Integer that is valid as an immediate operand for
3070 a custom instruction opcode. Range 0 to 255.
3073 An immediate operand for R2 andchi/andci instructions.
3076 Matches immediates which are addresses in the small
3077 data section and therefore can be added to @code{gp}
3078 as a 16-bit immediate to re-create their 32-bit value.
3081 Matches constants suitable as an operand for the rdprs and
3085 A memory operand suitable for Nios II R2 load/store
3086 exclusive instructions.
3089 A memory operand suitable for load/store IO and cache
3094 A @code{const} wrapped @code{UNSPEC} expression,
3095 representing a supported PIC or TLS relocation.
3100 @item OpenRISC---@file{config/or1k/constraints.md}
3103 Integer that is valid as an immediate operand in an
3104 instruction taking a signed 16-bit number. Range
3105 @minus{}32768 to 32767.
3108 Integer that is valid as an immediate operand in an
3109 instruction taking an unsigned 16-bit number. Range
3113 Signed 16-bit constant shifted left 16 bits. (Used with @code{l.movhi})
3120 Register usable for sibcalls.
3125 @item PDP-11---@file{config/pdp11/constraints.md}
3128 Floating point registers AC0 through AC3. These can be loaded from/to
3129 memory with a single instruction.
3132 Odd numbered general registers (R1, R3, R5). These are used for
3133 16-bit multiply operations.
3136 A memory reference that is encoded within the opcode, but not
3137 auto-increment or auto-decrement.
3140 Any of the floating point registers (AC0 through AC5).
3143 Floating point constant 0.
3146 Floating point registers AC4 and AC5. These cannot be loaded from/to
3147 memory with a single instruction.
3150 An integer constant that fits in 16 bits.
3153 An integer constant whose low order 16 bits are zero.
3156 An integer constant that does not meet the constraints for codes
3157 @samp{I} or @samp{J}.
3160 The integer constant 1.
3163 The integer constant @minus{}1.
3166 The integer constant 0.
3169 Integer constants 0 through 3; shifts by these
3170 amounts are handled as multiple single-bit shifts rather than a single
3171 variable-length shift.
3174 A memory reference which requires an additional word (address or
3175 offset) after the opcode.
3178 A memory reference that is encoded within the opcode.
3182 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
3185 Address base register
3188 Floating point register (containing 64-bit value)
3191 Floating point register (containing 32-bit value)
3194 Altivec vector register
3197 Any VSX register if the @option{-mvsx} option was used or NO_REGS.
3199 When using any of the register constraints (@code{wa}, @code{wd},
3200 @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
3201 @code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws},
3202 @code{wt}, @code{wv}, @code{ww}, or @code{wy})
3203 that take VSX registers, you must use @code{%x<n>} in the template so
3204 that the correct register is used. Otherwise the register number
3205 output in the assembly file will be incorrect if an Altivec register
3206 is an operand of a VSX instruction that expects VSX register
3210 asm ("xvadddp %x0,%x1,%x2"
3212 : "wa" (v2), "wa" (v3));
3219 asm ("xvadddp %0,%1,%2"
3221 : "wa" (v2), "wa" (v3));
3227 If an instruction only takes Altivec registers, you do not want to use
3231 asm ("xsaddqp %0,%1,%2"
3233 : "v" (v2), "v" (v3));
3237 is correct because the @code{xsaddqp} instruction only takes Altivec
3241 asm ("xsaddqp %x0,%x1,%x2"
3243 : "v" (v2), "v" (v3));
3250 VSX vector register to hold vector double data or NO_REGS.
3253 VSX register if the @option{-mcpu=power9} and @option{-m64} options
3254 were used or NO_REGS.
3257 VSX vector register to hold vector float data or NO_REGS.
3260 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
3263 Floating point register if direct moves are available, or NO_REGS.
3266 FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
3269 FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
3272 FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
3275 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
3278 VSX register if direct move instructions are enabled, or NO_REGS.
3281 No register (NO_REGS).
3284 VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS.
3287 VSX register to use for IEEE 128-bit floating point, or NO_REGS.
3290 General purpose register if 64-bit instructions are enabled or NO_REGS.
3293 VSX vector register to hold scalar double values or NO_REGS.
3296 VSX vector register to hold 128 bit integer or NO_REGS.
3299 Altivec register to use for double loads/stores or NO_REGS.
3302 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
3305 Floating point register if the STFIWX instruction is enabled or NO_REGS.
3308 FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
3311 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
3314 Address base register if 64-bit instructions are enabled or NO_REGS.
3317 Signed 5-bit constant integer that can be loaded into an altivec register.
3320 Int constant that is the element number of the 64-bit scalar in a vector.
3323 Vector constant that can be loaded with the XXSPLTIB instruction.
3326 Memory operand suitable for power8 GPR load fusion
3329 Memory operand suitable for TOC fusion memory references.
3332 Altivec register if @option{-mvsx-small-integer}.
3335 Floating point register if @option{-mvsx-small-integer}.
3338 Int constant that is the element number that the MFVSRLD instruction.
3342 Match vector constant with all 1's if the XXLORC instruction is available.
3345 A memory operand suitable for the ISA 3.0 vector d-form instructions.
3348 A memory address that will work with the @code{lq} and @code{stq}
3352 Vector constant that can be loaded with XXSPLTIB & sign extension.
3355 @samp{VRSAVE}, @samp{CTR}, or @samp{LINK} register
3361 @samp{LINK} register
3364 @samp{CR} register (condition register) number 0
3367 @samp{CR} register (condition register)
3370 @samp{XER[CA]} carry bit (part of the XER register)
3373 Signed 16-bit constant
3376 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
3377 @code{SImode} constants)
3380 Unsigned 16-bit constant
3383 Signed 16-bit constant shifted left 16 bits
3386 Constant larger than 31
3395 Constant whose negation is a signed 16-bit constant
3398 Floating point constant that can be loaded into a register with one
3399 instruction per word
3402 Integer/Floating point constant that can be loaded into a register using
3407 Normally, @code{m} does not allow addresses that update the base register.
3408 If @samp{<} or @samp{>} constraint is also used, they are allowed and
3409 therefore on PowerPC targets in that case it is only safe
3410 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
3411 accesses the operand exactly once. The @code{asm} statement must also
3412 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
3413 corresponding load or store instruction. For example:
3416 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
3422 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
3428 A ``stable'' memory operand; that is, one which does not include any
3429 automodification of the base register. This used to be useful when
3430 @samp{m} allowed automodification of the base register, but as those are now only
3431 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
3432 as @samp{m} without @samp{<} and @samp{>}.
3435 Memory operand that is an offset from a register (it is usually better
3436 to use @samp{m} or @samp{es} in @code{asm} statements)
3439 Memory operand that is an indexed or indirect from a register (it is
3440 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
3446 Address operand that is an indexed or indirect from a register (@samp{p} is
3447 preferable for @code{asm} statements)
3450 System V Release 4 small data area reference
3453 Vector constant that does not require memory
3456 Vector constant that is all zeros.
3460 @item RL78---@file{config/rl78/constraints.md}
3464 An integer constant in the range 1 @dots{} 7.
3466 An integer constant in the range 0 @dots{} 255.
3468 An integer constant in the range @minus{}255 @dots{} 0
3470 The integer constant 1.
3472 The integer constant -1.
3474 The integer constant 0.
3476 The integer constant 2.
3478 The integer constant -2.
3480 An integer constant in the range 1 @dots{} 15.
3482 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3484 The synthetic compare types--gt, lt, ge, and le.
3486 A memory reference with an absolute address.
3488 A memory reference using @code{BC} as a base register, with an optional offset.
3490 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3492 A memory reference using any 16-bit register pair for the address, for calls.
3494 A memory reference using @code{DE} as a base register, with an optional offset.
3496 A memory reference using @code{DE} as a base register, without any offset.
3498 Any memory reference to an address in the far address space.
3500 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3502 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3504 A memory reference using @code{HL} as a base register, without any offset.
3506 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3508 Any memory reference to an address in the near address space.
3510 The @code{AX} register.
3512 The @code{BC} register.
3514 The @code{DE} register.
3516 @code{A} through @code{L} registers.
3518 The @code{SP} register.
3520 The @code{HL} register.
3522 The 16-bit @code{R8} register.
3524 The 16-bit @code{R10} register.
3526 The registers reserved for interrupts (@code{R24} to @code{R31}).
3528 The @code{A} register.
3530 The @code{B} register.
3532 The @code{C} register.
3534 The @code{D} register.
3536 The @code{E} register.
3538 The @code{H} register.
3540 The @code{L} register.
3542 The virtual registers.
3544 The @code{PSW} register.
3546 The @code{X} register.
3550 @item RISC-V---@file{config/riscv/constraints.md}
3554 A floating-point register (if availiable).
3557 An I-type 12-bit signed immediate.
3563 A 5-bit unsigned immediate for CSR access instructions.
3566 An address that is held in a general-purpose register.
3570 @item RX---@file{config/rx/constraints.md}
3573 An address which does not involve register indirect addressing or
3574 pre/post increment/decrement addressing.
3580 A constant in the range @minus{}256 to 255, inclusive.
3583 A constant in the range @minus{}128 to 127, inclusive.
3586 A constant in the range @minus{}32768 to 32767, inclusive.
3589 A constant in the range @minus{}8388608 to 8388607, inclusive.
3592 A constant in the range 0 to 15, inclusive.
3596 @item S/390 and zSeries---@file{config/s390/s390.h}
3599 Address register (general purpose register except r0)
3602 Condition code register
3605 Data register (arbitrary general purpose register)
3608 Floating-point register
3611 Unsigned 8-bit constant (0--255)
3614 Unsigned 12-bit constant (0--4095)
3617 Signed 16-bit constant (@minus{}32768--32767)
3620 Value appropriate as displacement.
3623 for short displacement
3624 @item (@minus{}524288..524287)
3625 for long displacement
3629 Constant integer with a value of 0x7fffffff.
3632 Multiple letter constraint followed by 4 parameter letters.
3635 number of the part counting from most to least significant
3639 mode of the containing operand
3641 value of the other parts (F---all bits set)
3643 The constraint matches if the specified part of a constant
3644 has a value different from its other parts.
3647 Memory reference without index register and with short displacement.
3650 Memory reference with index register and short displacement.
3653 Memory reference without index register but with long displacement.
3656 Memory reference with index register and long displacement.
3659 Pointer with short displacement.
3662 Pointer with long displacement.
3665 Shift count operand.
3670 @item SPARC---@file{config/sparc/sparc.h}
3673 Floating-point register on the SPARC-V8 architecture and
3674 lower floating-point register on the SPARC-V9 architecture.
3677 Floating-point register. It is equivalent to @samp{f} on the
3678 SPARC-V8 architecture and contains both lower and upper
3679 floating-point registers on the SPARC-V9 architecture.
3682 Floating-point condition code register.
3685 Lower floating-point register. It is only valid on the SPARC-V9
3686 architecture when the Visual Instruction Set is available.
3689 Floating-point register. It is only valid on the SPARC-V9 architecture
3690 when the Visual Instruction Set is available.
3693 64-bit global or out register for the SPARC-V8+ architecture.
3696 The constant all-ones, for floating-point.
3699 Signed 5-bit constant
3705 Signed 13-bit constant
3711 32-bit constant with the low 12 bits clear (a constant that can be
3712 loaded with the @code{sethi} instruction)
3715 A constant in the range supported by @code{movcc} instructions (11-bit
3719 A constant in the range supported by @code{movrcc} instructions (10-bit
3723 Same as @samp{K}, except that it verifies that bits that are not in the
3724 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3725 modes wider than @code{SImode}
3734 Signed 13-bit constant, sign-extended to 32 or 64 bits
3740 Floating-point constant whose integral representation can
3741 be moved into an integer register using a single sethi
3745 Floating-point constant whose integral representation can
3746 be moved into an integer register using a single mov
3750 Floating-point constant whose integral representation can
3751 be moved into an integer register using a high/lo_sum
3752 instruction sequence
3755 Memory address aligned to an 8-byte boundary
3761 Memory address for @samp{e} constraint registers
3764 Memory address with only a base register
3771 @item SPU---@file{config/spu/spu.h}
3774 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3777 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3780 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3783 An immediate which can be loaded with @code{fsmbi}.
3786 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3789 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3792 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3795 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3798 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3801 An unsigned 7-bit constant for conversion/nop/channel instructions.
3804 A signed 10-bit constant for most arithmetic instructions.
3807 A signed 16 bit immediate for @code{stop}.
3810 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3813 An unsigned 7-bit constant whose 3 least significant bits are 0.
3816 An unsigned 3-bit constant for 16-byte rotates and shifts
3819 Call operand, reg, for indirect calls
3822 Call operand, symbol, for relative calls.
3825 Call operand, const_int, for absolute calls.
3828 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3831 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3834 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3837 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3841 @item TI C6X family---@file{config/c6x/constraints.md}
3844 Register file A (A0--A31).
3847 Register file B (B0--B31).
3850 Predicate registers in register file A (A0--A2 on C64X and
3851 higher, A1 and A2 otherwise).
3854 Predicate registers in register file B (B0--B2).
3857 A call-used register in register file B (B0--B9, B16--B31).
3860 Register file A, excluding predicate registers (A3--A31,
3861 plus A0 if not C64X or higher).
3864 Register file B, excluding predicate registers (B3--B31).
3867 Integer constant in the range 0 @dots{} 15.
3870 Integer constant in the range 0 @dots{} 31.
3873 Integer constant in the range @minus{}31 @dots{} 0.
3876 Integer constant in the range @minus{}16 @dots{} 15.
3879 Integer constant that can be the operand of an ADDA or a SUBA insn.
3882 Integer constant in the range 0 @dots{} 65535.
3885 Integer constant in the range @minus{}32768 @dots{} 32767.
3888 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3891 Integer constant that is a valid mask for the clr instruction.
3894 Integer constant that is a valid mask for the set instruction.
3897 Memory location with A base register.
3900 Memory location with B base register.
3904 On C64x+ targets, a GP-relative small data reference.
3907 Any kind of @code{SYMBOL_REF}, for use in a call address.
3910 Any kind of immediate operand, unless it matches the S0 constraint.
3913 Memory location with B base register, but not using a long offset.
3916 A memory operand with an address that cannot be used in an unaligned access.
3920 Register B14 (aka DP).
3924 @item TILE-Gx---@file{config/tilegx/constraints.md}
3937 Each of these represents a register constraint for an individual
3938 register, from r0 to r10.
3941 Signed 8-bit integer constant.
3944 Signed 16-bit integer constant.
3947 Unsigned 16-bit integer constant.
3950 Integer constant that fits in one signed byte when incremented by one
3951 (@minus{}129 @dots{} 126).
3954 Memory operand. If used together with @samp{<} or @samp{>}, the
3955 operand can have postincrement which requires printing with @samp{%In}
3956 and @samp{%in} on TILE-Gx. For example:
3959 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3963 A bit mask suitable for the BFINS instruction.
3966 Integer constant that is a byte tiled out eight times.
3969 The integer zero constant.
3972 Integer constant that is a sign-extended byte tiled out as four shorts.
3975 Integer constant that fits in one signed byte when incremented
3976 (@minus{}129 @dots{} 126), but excluding -1.
3979 Integer constant that has all 1 bits consecutive and starting at bit 0.
3982 A 16-bit fragment of a got, tls, or pc-relative reference.
3985 Memory operand except postincrement. This is roughly the same as
3986 @samp{m} when not used together with @samp{<} or @samp{>}.
3989 An 8-element vector constant with identical elements.
3992 A 4-element vector constant with identical elements.
3995 The integer constant 0xffffffff.
3998 The integer constant 0xffffffff00000000.
4002 @item TILEPro---@file{config/tilepro/constraints.md}
4015 Each of these represents a register constraint for an individual
4016 register, from r0 to r10.
4019 Signed 8-bit integer constant.
4022 Signed 16-bit integer constant.
4025 Nonzero integer constant with low 16 bits zero.
4028 Integer constant that fits in one signed byte when incremented by one
4029 (@minus{}129 @dots{} 126).
4032 Memory operand. If used together with @samp{<} or @samp{>}, the
4033 operand can have postincrement which requires printing with @samp{%In}
4034 and @samp{%in} on TILEPro. For example:
4037 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
4041 A bit mask suitable for the MM instruction.
4044 Integer constant that is a byte tiled out four times.
4047 The integer zero constant.
4050 Integer constant that is a sign-extended byte tiled out as two shorts.
4053 Integer constant that fits in one signed byte when incremented
4054 (@minus{}129 @dots{} 126), but excluding -1.
4057 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
4061 Memory operand except postincrement. This is roughly the same as
4062 @samp{m} when not used together with @samp{<} or @samp{>}.
4065 A 4-element vector constant with identical elements.
4068 A 2-element vector constant with identical elements.
4072 @item Visium---@file{config/visium/constraints.md}
4075 EAM register @code{mdb}
4078 EAM register @code{mdc}
4081 Floating point register
4085 Register for sibcall optimization
4089 General register, but not @code{r29}, @code{r30} and @code{r31}
4101 Floating-point constant 0.0
4104 Integer constant in the range 0 .. 65535 (16-bit immediate)
4107 Integer constant in the range 1 .. 31 (5-bit immediate)
4110 Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
4113 Integer constant @minus{}1
4122 @item x86 family---@file{config/i386/constraints.md}
4125 Legacy register---the eight integer registers available on all
4126 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
4127 @code{si}, @code{di}, @code{bp}, @code{sp}).
4130 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
4131 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
4134 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
4135 @code{c}, and @code{d}.
4139 Any register that can be used as the index in a base+index memory
4140 access: that is, any general register except the stack pointer.
4144 The @code{a} register.
4147 The @code{b} register.
4150 The @code{c} register.
4153 The @code{d} register.
4156 The @code{si} register.
4159 The @code{di} register.
4162 The @code{a} and @code{d} registers. This class is used for instructions
4163 that return double word results in the @code{ax:dx} register pair. Single
4164 word values will be allocated either in @code{ax} or @code{dx}.
4165 For example on i386 the following implements @code{rdtsc}:
4168 unsigned long long rdtsc (void)
4170 unsigned long long tick;
4171 __asm__ __volatile__("rdtsc":"=A"(tick));
4176 This is not correct on x86-64 as it would allocate tick in either @code{ax}
4177 or @code{dx}. You have to use the following variant instead:
4180 unsigned long long rdtsc (void)
4182 unsigned int tickl, tickh;
4183 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
4184 return ((unsigned long long)tickh << 32)|tickl;
4189 The call-clobbered integer registers.
4192 Any 80387 floating-point (stack) register.
4195 Top of 80387 floating-point stack (@code{%st(0)}).
4198 Second from top of 80387 floating-point stack (@code{%st(1)}).
4202 Any mask register that can be used as a predicate, i.e.@: @code{k1-k7}.
4215 Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).
4223 First SSE register (@code{%xmm0}).
4227 Any SSE register, when SSE2 and inter-unit moves are enabled.
4230 Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.
4233 Any MMX register, when inter-unit moves are enabled.
4236 Any MMX register, when inter-unit moves from vector registers are enabled.
4239 Any integer register when @code{TARGET_PARTIAL_REG_STALL} is disabled.
4242 Any integer register when zero extensions with @code{AND} are disabled.
4245 Any register that can be used as the GOT base when calling@*
4246 @code{___tls_get_addr}: that is, any general register except @code{a}
4247 and @code{sp} registers, for @option{-fno-plt} if linker supports it.
4248 Otherwise, @code{b} register.
4251 Any x87 register when 80387 floating-point arithmetic is enabled.
4254 Lower SSE register when avoiding REX prefix and all SSE registers otherwise.
4257 For AVX512VL, any EVEX-encodable SSE register (@code{%xmm0-%xmm31}),
4258 otherwise any SSE register.
4261 Any EVEX-encodable SSE register, that has number factor of four.
4264 Flags register operand.
4270 Vector memory operand.
4273 Constant memory operand.
4276 Memory operand without REX prefix.
4279 Sibcall memory operand.
4282 Call memory operand.
4285 Constant call address operand.
4288 SSE constant -1 operand.
4292 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
4295 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
4298 Signed 8-bit integer constant.
4301 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
4304 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
4307 Unsigned 8-bit integer constant (for @code{in} and @code{out}
4312 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
4316 Standard 80387 floating point constant.
4319 SSE constant zero operand.
4322 32-bit signed integer constant, or a symbolic reference known
4323 to fit that range (for immediate operands in sign-extending x86-64
4327 32-bit signed integer constant, or a symbolic reference known
4328 to fit that range (for sign-extending conversion operations that
4329 require non-@code{VOIDmode} immediate operands).
4332 32-bit unsigned integer constant, or a symbolic reference known
4333 to fit that range (for zero-extending conversion operations that
4334 require non-@code{VOIDmode} immediate operands).
4337 128-bit integer constant where both the high and low 64-bit word
4338 satisfy the @code{e} constraint.
4341 32-bit unsigned integer constant, or a symbolic reference known
4342 to fit that range (for immediate operands in zero-extending x86-64
4346 VSIB address operand.
4349 Address operand without segment register.
4353 @item Xstormy16---@file{config/stormy16/stormy16.h}
4368 Registers r0 through r7.
4371 Registers r0 and r1.
4377 Registers r8 and r9.
4380 A constant between 0 and 3 inclusive.
4383 A constant that has exactly one bit set.
4386 A constant that has exactly one bit clear.
4389 A constant between 0 and 255 inclusive.
4392 A constant between @minus{}255 and 0 inclusive.
4395 A constant between @minus{}3 and 0 inclusive.
4398 A constant between 1 and 4 inclusive.
4401 A constant between @minus{}4 and @minus{}1 inclusive.
4404 A memory reference that is a stack push.
4407 A memory reference that is a stack pop.
4410 A memory reference that refers to a constant address of known value.
4413 The register indicated by Rx (not implemented yet).
4416 A constant that is not between 2 and 15 inclusive.
4423 @item Xtensa---@file{config/xtensa/constraints.md}
4426 General-purpose 32-bit register
4429 One-bit boolean register
4432 MAC16 40-bit accumulator register
4435 Signed 12-bit integer constant, for use in MOVI instructions
4438 Signed 8-bit integer constant, for use in ADDI instructions
4441 Integer constant valid for BccI instructions
4444 Unsigned constant valid for BccUI instructions
4451 @node Disable Insn Alternatives
4452 @subsection Disable insn alternatives using the @code{enabled} attribute
4455 There are three insn attributes that may be used to selectively disable
4456 instruction alternatives:
4460 Says whether an alternative is available on the current subtarget.
4462 @item preferred_for_size
4463 Says whether an enabled alternative should be used in code that is
4466 @item preferred_for_speed
4467 Says whether an enabled alternative should be used in code that is
4468 optimized for speed.
4471 All these attributes should use @code{(const_int 1)} to allow an alternative
4472 or @code{(const_int 0)} to disallow it. The attributes must be a static
4473 property of the subtarget; they cannot for example depend on the
4474 current operands, on the current optimization level, on the location
4475 of the insn within the body of a loop, on whether register allocation
4476 has finished, or on the current compiler pass.
4478 The @code{enabled} attribute is a correctness property. It tells GCC to act
4479 as though the disabled alternatives were never defined in the first place.
4480 This is useful when adding new instructions to an existing pattern in
4481 cases where the new instructions are only available for certain cpu
4482 architecture levels (typically mapped to the @code{-march=} command-line
4485 In contrast, the @code{preferred_for_size} and @code{preferred_for_speed}
4486 attributes are strong optimization hints rather than correctness properties.
4487 @code{preferred_for_size} tells GCC which alternatives to consider when
4488 adding or modifying an instruction that GCC wants to optimize for size.
4489 @code{preferred_for_speed} does the same thing for speed. Note that things
4490 like code motion can lead to cases where code optimized for size uses
4491 alternatives that are not preferred for size, and similarly for speed.
4493 Although @code{define_insn}s can in principle specify the @code{enabled}
4494 attribute directly, it is often clearer to have subsiduary attributes
4495 for each architectural feature of interest. The @code{define_insn}s
4496 can then use these subsiduary attributes to say which alternatives
4497 require which features. The example below does this for @code{cpu_facility}.
4499 E.g. the following two patterns could easily be merged using the @code{enabled}
4504 (define_insn "*movdi_old"
4505 [(set (match_operand:DI 0 "register_operand" "=d")
4506 (match_operand:DI 1 "register_operand" " d"))]
4510 (define_insn "*movdi_new"
4511 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4512 (match_operand:DI 1 "register_operand" " d,d,f"))]
4525 (define_insn "*movdi_combined"
4526 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4527 (match_operand:DI 1 "register_operand" " d,d,f"))]
4533 [(set_attr "cpu_facility" "*,new,new")])
4537 with the @code{enabled} attribute defined like this:
4541 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4543 (define_attr "enabled" ""
4544 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4545 (and (eq_attr "cpu_facility" "new")
4546 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4555 @node Define Constraints
4556 @subsection Defining Machine-Specific Constraints
4557 @cindex defining constraints
4558 @cindex constraints, defining
4560 Machine-specific constraints fall into two categories: register and
4561 non-register constraints. Within the latter category, constraints
4562 which allow subsets of all possible memory or address operands should
4563 be specially marked, to give @code{reload} more information.
4565 Machine-specific constraints can be given names of arbitrary length,
4566 but they must be entirely composed of letters, digits, underscores
4567 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4568 must begin with a letter or underscore.
4570 In order to avoid ambiguity in operand constraint strings, no
4571 constraint can have a name that begins with any other constraint's
4572 name. For example, if @code{x} is defined as a constraint name,
4573 @code{xy} may not be, and vice versa. As a consequence of this rule,
4574 no constraint may begin with one of the generic constraint letters:
4575 @samp{E F V X g i m n o p r s}.
4577 Register constraints correspond directly to register classes.
4578 @xref{Register Classes}. There is thus not much flexibility in their
4581 @deffn {MD Expression} define_register_constraint name regclass docstring
4582 All three arguments are string constants.
4583 @var{name} is the name of the constraint, as it will appear in
4584 @code{match_operand} expressions. If @var{name} is a multi-letter
4585 constraint its length shall be the same for all constraints starting
4586 with the same letter. @var{regclass} can be either the
4587 name of the corresponding register class (@pxref{Register Classes}),
4588 or a C expression which evaluates to the appropriate register class.
4589 If it is an expression, it must have no side effects, and it cannot
4590 look at the operand. The usual use of expressions is to map some
4591 register constraints to @code{NO_REGS} when the register class
4592 is not available on a given subarchitecture.
4594 @var{docstring} is a sentence documenting the meaning of the
4595 constraint. Docstrings are explained further below.
4598 Non-register constraints are more like predicates: the constraint
4599 definition gives a boolean expression which indicates whether the
4602 @deffn {MD Expression} define_constraint name docstring exp
4603 The @var{name} and @var{docstring} arguments are the same as for
4604 @code{define_register_constraint}, but note that the docstring comes
4605 immediately after the name for these expressions. @var{exp} is an RTL
4606 expression, obeying the same rules as the RTL expressions in predicate
4607 definitions. @xref{Defining Predicates}, for details. If it
4608 evaluates true, the constraint matches; if it evaluates false, it
4609 doesn't. Constraint expressions should indicate which RTL codes they
4610 might match, just like predicate expressions.
4612 @code{match_test} C expressions have access to the
4613 following variables:
4617 The RTL object defining the operand.
4619 The machine mode of @var{op}.
4621 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4623 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4624 @code{const_double}.
4626 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4627 @code{const_double}.
4629 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4630 @code{const_double}.
4633 The @var{*val} variables should only be used once another piece of the
4634 expression has verified that @var{op} is the appropriate kind of RTL
4638 Most non-register constraints should be defined with
4639 @code{define_constraint}. The remaining two definition expressions
4640 are only appropriate for constraints that should be handled specially
4641 by @code{reload} if they fail to match.
4643 @deffn {MD Expression} define_memory_constraint name docstring exp
4644 Use this expression for constraints that match a subset of all memory
4645 operands: that is, @code{reload} can make them match by converting the
4646 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4647 base register (from the register class specified by
4648 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4650 For example, on the S/390, some instructions do not accept arbitrary
4651 memory references, but only those that do not make use of an index
4652 register. The constraint letter @samp{Q} is defined to represent a
4653 memory address of this type. If @samp{Q} is defined with
4654 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4655 memory operand, because @code{reload} knows it can simply copy the
4656 memory address into a base register if required. This is analogous to
4657 the way an @samp{o} constraint can handle any memory operand.
4659 The syntax and semantics are otherwise identical to
4660 @code{define_constraint}.
4663 @deffn {MD Expression} define_special_memory_constraint name docstring exp
4664 Use this expression for constraints that match a subset of all memory
4665 operands: that is, @code{reload} cannot make them match by reloading
4666 the address as it is described for @code{define_memory_constraint} or
4667 such address reload is undesirable with the performance point of view.
4669 For example, @code{define_special_memory_constraint} can be useful if
4670 specifically aligned memory is necessary or desirable for some insn
4673 The syntax and semantics are otherwise identical to
4674 @code{define_constraint}.
4677 @deffn {MD Expression} define_address_constraint name docstring exp
4678 Use this expression for constraints that match a subset of all address
4679 operands: that is, @code{reload} can make the constraint match by
4680 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4681 with @var{X} a base register.
4683 Constraints defined with @code{define_address_constraint} can only be
4684 used with the @code{address_operand} predicate, or machine-specific
4685 predicates that work the same way. They are treated analogously to
4686 the generic @samp{p} constraint.
4688 The syntax and semantics are otherwise identical to
4689 @code{define_constraint}.
4692 For historical reasons, names beginning with the letters @samp{G H}
4693 are reserved for constraints that match only @code{const_double}s, and
4694 names beginning with the letters @samp{I J K L M N O P} are reserved
4695 for constraints that match only @code{const_int}s. This may change in
4696 the future. For the time being, constraints with these names must be
4697 written in a stylized form, so that @code{genpreds} can tell you did
4702 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4704 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4705 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4708 @c the semicolons line up in the formatted manual
4710 It is fine to use names beginning with other letters for constraints
4711 that match @code{const_double}s or @code{const_int}s.
4713 Each docstring in a constraint definition should be one or more complete
4714 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4715 In the future they will be copied into the GCC manual, in @ref{Machine
4716 Constraints}, replacing the hand-maintained tables currently found in
4717 that section. Also, in the future the compiler may use this to give
4718 more helpful diagnostics when poor choice of @code{asm} constraints
4719 causes a reload failure.
4721 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4722 beginning of a docstring, then (in the future) it will appear only in
4723 the internals manual's version of the machine-specific constraint tables.
4724 Use this for constraints that should not appear in @code{asm} statements.
4726 @node C Constraint Interface
4727 @subsection Testing constraints from C
4728 @cindex testing constraints
4729 @cindex constraints, testing
4731 It is occasionally useful to test a constraint from C code rather than
4732 implicitly via the constraint string in a @code{match_operand}. The
4733 generated file @file{tm_p.h} declares a few interfaces for working
4734 with constraints. At present these are defined for all constraints
4735 except @code{g} (which is equivalent to @code{general_operand}).
4737 Some valid constraint names are not valid C identifiers, so there is a
4738 mangling scheme for referring to them from C@. Constraint names that
4739 do not contain angle brackets or underscores are left unchanged.
4740 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4741 each @samp{>} with @samp{_g}. Here are some examples:
4743 @c the @c's prevent double blank lines in the printed manual.
4745 @multitable {Original} {Mangled}
4746 @item @strong{Original} @tab @strong{Mangled} @c
4747 @item @code{x} @tab @code{x} @c
4748 @item @code{P42x} @tab @code{P42x} @c
4749 @item @code{P4_x} @tab @code{P4__x} @c
4750 @item @code{P4>x} @tab @code{P4_gx} @c
4751 @item @code{P4>>} @tab @code{P4_g_g} @c
4752 @item @code{P4_g>} @tab @code{P4__g_g} @c
4756 Throughout this section, the variable @var{c} is either a constraint
4757 in the abstract sense, or a constant from @code{enum constraint_num};
4758 the variable @var{m} is a mangled constraint name (usually as part of
4759 a larger identifier).
4761 @deftp Enum constraint_num
4762 For each constraint except @code{g}, there is a corresponding
4763 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4764 constraint. Functions that take an @code{enum constraint_num} as an
4765 argument expect one of these constants.
4768 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4769 For each non-register constraint @var{m} except @code{g}, there is
4770 one of these functions; it returns @code{true} if @var{exp} satisfies the
4771 constraint. These functions are only visible if @file{rtl.h} was included
4772 before @file{tm_p.h}.
4775 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4776 Like the @code{satisfies_constraint_@var{m}} functions, but the
4777 constraint to test is given as an argument, @var{c}. If @var{c}
4778 specifies a register constraint, this function will always return
4782 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4783 Returns the register class associated with @var{c}. If @var{c} is not
4784 a register constraint, or those registers are not available for the
4785 currently selected subtarget, returns @code{NO_REGS}.
4788 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4789 peephole optimizations (@pxref{Peephole Definitions}), operand
4790 constraint strings are ignored, so if there are relevant constraints,
4791 they must be tested in the C condition. In the example, the
4792 optimization is applied if operand 2 does @emph{not} satisfy the
4793 @samp{K} constraint. (This is a simplified version of a peephole
4794 definition from the i386 machine description.)
4798 [(match_scratch:SI 3 "r")
4799 (set (match_operand:SI 0 "register_operand" "")
4800 (mult:SI (match_operand:SI 1 "memory_operand" "")
4801 (match_operand:SI 2 "immediate_operand" "")))]
4803 "!satisfies_constraint_K (operands[2])"
4805 [(set (match_dup 3) (match_dup 1))
4806 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4811 @node Standard Names
4812 @section Standard Pattern Names For Generation
4813 @cindex standard pattern names
4814 @cindex pattern names
4815 @cindex names, pattern
4817 Here is a table of the instruction names that are meaningful in the RTL
4818 generation pass of the compiler. Giving one of these names to an
4819 instruction pattern tells the RTL generation pass that it can use the
4820 pattern to accomplish a certain task.
4823 @cindex @code{mov@var{m}} instruction pattern
4824 @item @samp{mov@var{m}}
4825 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4826 This instruction pattern moves data with that machine mode from operand
4827 1 to operand 0. For example, @samp{movsi} moves full-word data.
4829 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4830 own mode is wider than @var{m}, the effect of this instruction is
4831 to store the specified value in the part of the register that corresponds
4832 to mode @var{m}. Bits outside of @var{m}, but which are within the
4833 same target word as the @code{subreg} are undefined. Bits which are
4834 outside the target word are left unchanged.
4836 This class of patterns is special in several ways. First of all, each
4837 of these names up to and including full word size @emph{must} be defined,
4838 because there is no other way to copy a datum from one place to another.
4839 If there are patterns accepting operands in larger modes,
4840 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4842 Second, these patterns are not used solely in the RTL generation pass.
4843 Even the reload pass can generate move insns to copy values from stack
4844 slots into temporary registers. When it does so, one of the operands is
4845 a hard register and the other is an operand that can need to be reloaded
4849 Therefore, when given such a pair of operands, the pattern must generate
4850 RTL which needs no reloading and needs no temporary registers---no
4851 registers other than the operands. For example, if you support the
4852 pattern with a @code{define_expand}, then in such a case the
4853 @code{define_expand} mustn't call @code{force_reg} or any other such
4854 function which might generate new pseudo registers.
4856 This requirement exists even for subword modes on a RISC machine where
4857 fetching those modes from memory normally requires several insns and
4858 some temporary registers.
4860 @findex change_address
4861 During reload a memory reference with an invalid address may be passed
4862 as an operand. Such an address will be replaced with a valid address
4863 later in the reload pass. In this case, nothing may be done with the
4864 address except to use it as it stands. If it is copied, it will not be
4865 replaced with a valid address. No attempt should be made to make such
4866 an address into a valid address and no routine (such as
4867 @code{change_address}) that will do so may be called. Note that
4868 @code{general_operand} will fail when applied to such an address.
4870 @findex reload_in_progress
4871 The global variable @code{reload_in_progress} (which must be explicitly
4872 declared if required) can be used to determine whether such special
4873 handling is required.
4875 The variety of operands that have reloads depends on the rest of the
4876 machine description, but typically on a RISC machine these can only be
4877 pseudo registers that did not get hard registers, while on other
4878 machines explicit memory references will get optional reloads.
4880 If a scratch register is required to move an object to or from memory,
4881 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4883 If there are cases which need scratch registers during or after reload,
4884 you must provide an appropriate secondary_reload target hook.
4886 @findex can_create_pseudo_p
4887 The macro @code{can_create_pseudo_p} can be used to determine if it
4888 is unsafe to create new pseudo registers. If this variable is nonzero, then
4889 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4891 The constraints on a @samp{mov@var{m}} must permit moving any hard
4892 register to any other hard register provided that
4893 @code{TARGET_HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4894 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4897 It is obligatory to support floating point @samp{mov@var{m}}
4898 instructions into and out of any registers that can hold fixed point
4899 values, because unions and structures (which have modes @code{SImode} or
4900 @code{DImode}) can be in those registers and they may have floating
4903 There may also be a need to support fixed point @samp{mov@var{m}}
4904 instructions in and out of floating point registers. Unfortunately, I
4905 have forgotten why this was so, and I don't know whether it is still
4906 true. If @code{TARGET_HARD_REGNO_MODE_OK} rejects fixed point values in
4907 floating point registers, then the constraints of the fixed point
4908 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4909 reload into a floating point register.
4911 @cindex @code{reload_in} instruction pattern
4912 @cindex @code{reload_out} instruction pattern
4913 @item @samp{reload_in@var{m}}
4914 @itemx @samp{reload_out@var{m}}
4915 These named patterns have been obsoleted by the target hook
4916 @code{secondary_reload}.
4918 Like @samp{mov@var{m}}, but used when a scratch register is required to
4919 move between operand 0 and operand 1. Operand 2 describes the scratch
4920 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4921 macro in @pxref{Register Classes}.
4923 There are special restrictions on the form of the @code{match_operand}s
4924 used in these patterns. First, only the predicate for the reload
4925 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4926 the predicates for operand 0 or 2. Second, there may be only one
4927 alternative in the constraints. Third, only a single register class
4928 letter may be used for the constraint; subsequent constraint letters
4929 are ignored. As a special exception, an empty constraint string
4930 matches the @code{ALL_REGS} register class. This may relieve ports
4931 of the burden of defining an @code{ALL_REGS} constraint letter just
4934 @cindex @code{movstrict@var{m}} instruction pattern
4935 @item @samp{movstrict@var{m}}
4936 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4937 with mode @var{m} of a register whose natural mode is wider,
4938 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4939 any of the register except the part which belongs to mode @var{m}.
4941 @cindex @code{movmisalign@var{m}} instruction pattern
4942 @item @samp{movmisalign@var{m}}
4943 This variant of a move pattern is designed to load or store a value
4944 from a memory address that is not naturally aligned for its mode.
4945 For a store, the memory will be in operand 0; for a load, the memory
4946 will be in operand 1. The other operand is guaranteed not to be a
4947 memory, so that it's easy to tell whether this is a load or store.
4949 This pattern is used by the autovectorizer, and when expanding a
4950 @code{MISALIGNED_INDIRECT_REF} expression.
4952 @cindex @code{load_multiple} instruction pattern
4953 @item @samp{load_multiple}
4954 Load several consecutive memory locations into consecutive registers.
4955 Operand 0 is the first of the consecutive registers, operand 1
4956 is the first memory location, and operand 2 is a constant: the
4957 number of consecutive registers.
4959 Define this only if the target machine really has such an instruction;
4960 do not define this if the most efficient way of loading consecutive
4961 registers from memory is to do them one at a time.
4963 On some machines, there are restrictions as to which consecutive
4964 registers can be stored into memory, such as particular starting or
4965 ending register numbers or only a range of valid counts. For those
4966 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4967 and make the pattern fail if the restrictions are not met.
4969 Write the generated insn as a @code{parallel} with elements being a
4970 @code{set} of one register from the appropriate memory location (you may
4971 also need @code{use} or @code{clobber} elements). Use a
4972 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4973 @file{rs6000.md} for examples of the use of this insn pattern.
4975 @cindex @samp{store_multiple} instruction pattern
4976 @item @samp{store_multiple}
4977 Similar to @samp{load_multiple}, but store several consecutive registers
4978 into consecutive memory locations. Operand 0 is the first of the
4979 consecutive memory locations, operand 1 is the first register, and
4980 operand 2 is a constant: the number of consecutive registers.
4982 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4983 @item @samp{vec_load_lanes@var{m}@var{n}}
4984 Perform an interleaved load of several vectors from memory operand 1
4985 into register operand 0. Both operands have mode @var{m}. The register
4986 operand is viewed as holding consecutive vectors of mode @var{n},
4987 while the memory operand is a flat array that contains the same number
4988 of elements. The operation is equivalent to:
4991 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4992 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4993 for (i = 0; i < c; i++)
4994 operand0[i][j] = operand1[j * c + i];
4997 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4998 from memory into a register of mode @samp{TI}@. The register
4999 contains two consecutive vectors of mode @samp{V4HI}@.
5001 This pattern can only be used if:
5003 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
5005 is true. GCC assumes that, if a target supports this kind of
5006 instruction for some mode @var{n}, it also supports unaligned
5007 loads for vectors of mode @var{n}.
5009 This pattern is not allowed to @code{FAIL}.
5011 @cindex @code{vec_mask_load_lanes@var{m}@var{n}} instruction pattern
5012 @item @samp{vec_mask_load_lanes@var{m}@var{n}}
5013 Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional
5014 mask operand (operand 2) that specifies which elements of the destination
5015 vectors should be loaded. Other elements of the destination
5016 vectors are set to zero. The operation is equivalent to:
5019 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
5020 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
5022 for (i = 0; i < c; i++)
5023 operand0[i][j] = operand1[j * c + i];
5025 for (i = 0; i < c; i++)
5029 This pattern is not allowed to @code{FAIL}.
5031 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
5032 @item @samp{vec_store_lanes@var{m}@var{n}}
5033 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
5034 and register operands reversed. That is, the instruction is
5038 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
5039 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
5040 for (i = 0; i < c; i++)
5041 operand0[j * c + i] = operand1[i][j];
5044 for a memory operand 0 and register operand 1.
5046 This pattern is not allowed to @code{FAIL}.
5048 @cindex @code{vec_mask_store_lanes@var{m}@var{n}} instruction pattern
5049 @item @samp{vec_mask_store_lanes@var{m}@var{n}}
5050 Like @samp{vec_store_lanes@var{m}@var{n}}, but takes an additional
5051 mask operand (operand 2) that specifies which elements of the source
5052 vectors should be stored. The operation is equivalent to:
5055 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
5056 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
5058 for (i = 0; i < c; i++)
5059 operand0[j * c + i] = operand1[i][j];
5062 This pattern is not allowed to @code{FAIL}.
5064 @cindex @code{gather_load@var{m}} instruction pattern
5065 @item @samp{gather_load@var{m}}
5066 Load several separate memory locations into a vector of mode @var{m}.
5067 Operand 1 is a scalar base address and operand 2 is a vector of
5068 offsets from that base. Operand 0 is a destination vector with the
5069 same number of elements as the offset. For each element index @var{i}:
5073 extend the offset element @var{i} to address width, using zero
5074 extension if operand 3 is 1 and sign extension if operand 3 is zero;
5076 multiply the extended offset by operand 4;
5078 add the result to the base; and
5080 load the value at that address into element @var{i} of operand 0.
5083 The value of operand 3 does not matter if the offsets are already
5086 @cindex @code{mask_gather_load@var{m}} instruction pattern
5087 @item @samp{mask_gather_load@var{m}}
5088 Like @samp{gather_load@var{m}}, but takes an extra mask operand as
5089 operand 5. Bit @var{i} of the mask is set if element @var{i}
5090 of the result should be loaded from memory and clear if element @var{i}
5091 of the result should be set to zero.
5093 @cindex @code{scatter_store@var{m}} instruction pattern
5094 @item @samp{scatter_store@var{m}}
5095 Store a vector of mode @var{m} into several distinct memory locations.
5096 Operand 0 is a scalar base address and operand 1 is a vector of offsets
5097 from that base. Operand 4 is the vector of values that should be stored,
5098 which has the same number of elements as the offset. For each element
5103 extend the offset element @var{i} to address width, using zero
5104 extension if operand 2 is 1 and sign extension if operand 2 is zero;
5106 multiply the extended offset by operand 3;
5108 add the result to the base; and
5110 store element @var{i} of operand 4 to that address.
5113 The value of operand 2 does not matter if the offsets are already
5116 @cindex @code{mask_scatter_store@var{m}} instruction pattern
5117 @item @samp{mask_scatter_store@var{m}}
5118 Like @samp{scatter_store@var{m}}, but takes an extra mask operand as
5119 operand 5. Bit @var{i} of the mask is set if element @var{i}
5120 of the result should be stored to memory.
5122 @cindex @code{vec_set@var{m}} instruction pattern
5123 @item @samp{vec_set@var{m}}
5124 Set given field in the vector value. Operand 0 is the vector to modify,
5125 operand 1 is new value of field and operand 2 specify the field index.
5127 @cindex @code{vec_extract@var{m}@var{n}} instruction pattern
5128 @item @samp{vec_extract@var{m}@var{n}}
5129 Extract given field from the vector value. Operand 1 is the vector, operand 2
5130 specify field index and operand 0 place to store value into. The
5131 @var{n} mode is the mode of the field or vector of fields that should be
5132 extracted, should be either element mode of the vector mode @var{m}, or
5133 a vector mode with the same element mode and smaller number of elements.
5134 If @var{n} is a vector mode, the index is counted in units of that mode.
5136 @cindex @code{vec_init@var{m}@var{n}} instruction pattern
5137 @item @samp{vec_init@var{m}@var{n}}
5138 Initialize the vector to given values. Operand 0 is the vector to initialize
5139 and operand 1 is parallel containing values for individual fields. The
5140 @var{n} mode is the mode of the elements, should be either element mode of
5141 the vector mode @var{m}, or a vector mode with the same element mode and
5142 smaller number of elements.
5144 @cindex @code{vec_duplicate@var{m}} instruction pattern
5145 @item @samp{vec_duplicate@var{m}}
5146 Initialize vector output operand 0 so that each element has the value given
5147 by scalar input operand 1. The vector has mode @var{m} and the scalar has
5148 the mode appropriate for one element of @var{m}.
5150 This pattern only handles duplicates of non-constant inputs. Constant
5151 vectors go through the @code{mov@var{m}} pattern instead.
5153 This pattern is not allowed to @code{FAIL}.
5155 @cindex @code{vec_series@var{m}} instruction pattern
5156 @item @samp{vec_series@var{m}}
5157 Initialize vector output operand 0 so that element @var{i} is equal to
5158 operand 1 plus @var{i} times operand 2. In other words, create a linear
5159 series whose base value is operand 1 and whose step is operand 2.
5161 The vector output has mode @var{m} and the scalar inputs have the mode
5162 appropriate for one element of @var{m}. This pattern is not used for
5163 floating-point vectors, in order to avoid having to specify the
5164 rounding behavior for @var{i} > 1.
5166 This pattern is not allowed to @code{FAIL}.
5168 @cindex @code{while_ult@var{m}@var{n}} instruction pattern
5169 @item @code{while_ult@var{m}@var{n}}
5170 Set operand 0 to a mask that is true while incrementing operand 1
5171 gives a value that is less than operand 2. Operand 0 has mode @var{n}
5172 and operands 1 and 2 are scalar integers of mode @var{m}.
5173 The operation is equivalent to:
5176 operand0[0] = operand1 < operand2;
5177 for (i = 1; i < GET_MODE_NUNITS (@var{n}); i++)
5178 operand0[i] = operand0[i - 1] && (operand1 + i < operand2);
5181 @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern
5182 @item @samp{vec_cmp@var{m}@var{n}}
5183 Output a vector comparison. Operand 0 of mode @var{n} is the destination for
5184 predicate in operand 1 which is a signed vector comparison with operands of
5185 mode @var{m} in operands 2 and 3. Predicate is computed by element-wise
5186 evaluation of the vector comparison with a truth value of all-ones and a false
5189 @cindex @code{vec_cmpu@var{m}@var{n}} instruction pattern
5190 @item @samp{vec_cmpu@var{m}@var{n}}
5191 Similar to @code{vec_cmp@var{m}@var{n}} but perform unsigned vector comparison.
5193 @cindex @code{vec_cmpeq@var{m}@var{n}} instruction pattern
5194 @item @samp{vec_cmpeq@var{m}@var{n}}
5195 Similar to @code{vec_cmp@var{m}@var{n}} but perform equality or non-equality
5196 vector comparison only. If @code{vec_cmp@var{m}@var{n}}
5197 or @code{vec_cmpu@var{m}@var{n}} instruction pattern is supported,
5198 it will be preferred over @code{vec_cmpeq@var{m}@var{n}}, so there is
5199 no need to define this instruction pattern if the others are supported.
5201 @cindex @code{vcond@var{m}@var{n}} instruction pattern
5202 @item @samp{vcond@var{m}@var{n}}
5203 Output a conditional vector move. Operand 0 is the destination to
5204 receive a combination of operand 1 and operand 2, which are of mode @var{m},
5205 dependent on the outcome of the predicate in operand 3 which is a signed
5206 vector comparison with operands of mode @var{n} in operands 4 and 5. The
5207 modes @var{m} and @var{n} should have the same size. Operand 0
5208 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
5209 where @var{msk} is computed by element-wise evaluation of the vector
5210 comparison with a truth value of all-ones and a false value of all-zeros.
5212 @cindex @code{vcondu@var{m}@var{n}} instruction pattern
5213 @item @samp{vcondu@var{m}@var{n}}
5214 Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector
5217 @cindex @code{vcondeq@var{m}@var{n}} instruction pattern
5218 @item @samp{vcondeq@var{m}@var{n}}
5219 Similar to @code{vcond@var{m}@var{n}} but performs equality or
5220 non-equality vector comparison only. If @code{vcond@var{m}@var{n}}
5221 or @code{vcondu@var{m}@var{n}} instruction pattern is supported,
5222 it will be preferred over @code{vcondeq@var{m}@var{n}}, so there is
5223 no need to define this instruction pattern if the others are supported.
5225 @cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern
5226 @item @samp{vcond_mask_@var{m}@var{n}}
5227 Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed
5228 result of vector comparison.
5230 @cindex @code{maskload@var{m}@var{n}} instruction pattern
5231 @item @samp{maskload@var{m}@var{n}}
5232 Perform a masked load of vector from memory operand 1 of mode @var{m}
5233 into register operand 0. Mask is provided in register operand 2 of
5236 This pattern is not allowed to @code{FAIL}.
5238 @cindex @code{maskstore@var{m}@var{n}} instruction pattern
5239 @item @samp{maskstore@var{m}@var{n}}
5240 Perform a masked store of vector from register operand 1 of mode @var{m}
5241 into memory operand 0. Mask is provided in register operand 2 of
5244 This pattern is not allowed to @code{FAIL}.
5246 @cindex @code{vec_perm@var{m}} instruction pattern
5247 @item @samp{vec_perm@var{m}}
5248 Output a (variable) vector permutation. Operand 0 is the destination
5249 to receive elements from operand 1 and operand 2, which are of mode
5250 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
5251 vector of the same width and number of elements as mode @var{m}.
5253 The input elements are numbered from 0 in operand 1 through
5254 @math{2*@var{N}-1} in operand 2. The elements of the selector must
5255 be computed modulo @math{2*@var{N}}. Note that if
5256 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
5257 with just operand 1 and selector elements modulo @var{N}.
5259 In order to make things easy for a number of targets, if there is no
5260 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
5261 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
5262 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
5265 See also @code{TARGET_VECTORIZER_VEC_PERM_CONST}, which performs
5266 the analogous operation for constant selectors.
5268 @cindex @code{push@var{m}1} instruction pattern
5269 @item @samp{push@var{m}1}
5270 Output a push instruction. Operand 0 is value to push. Used only when
5271 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
5272 missing and in such case an @code{mov} expander is used instead, with a
5273 @code{MEM} expression forming the push operation. The @code{mov} expander
5274 method is deprecated.
5276 @cindex @code{add@var{m}3} instruction pattern
5277 @item @samp{add@var{m}3}
5278 Add operand 2 and operand 1, storing the result in operand 0. All operands
5279 must have mode @var{m}. This can be used even on two-address machines, by
5280 means of constraints requiring operands 1 and 0 to be the same location.
5282 @cindex @code{ssadd@var{m}3} instruction pattern
5283 @cindex @code{usadd@var{m}3} instruction pattern
5284 @cindex @code{sub@var{m}3} instruction pattern
5285 @cindex @code{sssub@var{m}3} instruction pattern
5286 @cindex @code{ussub@var{m}3} instruction pattern
5287 @cindex @code{mul@var{m}3} instruction pattern
5288 @cindex @code{ssmul@var{m}3} instruction pattern
5289 @cindex @code{usmul@var{m}3} instruction pattern
5290 @cindex @code{div@var{m}3} instruction pattern
5291 @cindex @code{ssdiv@var{m}3} instruction pattern
5292 @cindex @code{udiv@var{m}3} instruction pattern
5293 @cindex @code{usdiv@var{m}3} instruction pattern
5294 @cindex @code{mod@var{m}3} instruction pattern
5295 @cindex @code{umod@var{m}3} instruction pattern
5296 @cindex @code{umin@var{m}3} instruction pattern
5297 @cindex @code{umax@var{m}3} instruction pattern
5298 @cindex @code{and@var{m}3} instruction pattern
5299 @cindex @code{ior@var{m}3} instruction pattern
5300 @cindex @code{xor@var{m}3} instruction pattern
5301 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
5302 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
5303 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
5304 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
5305 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
5306 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
5307 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
5308 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
5309 Similar, for other arithmetic operations.
5311 @cindex @code{addv@var{m}4} instruction pattern
5312 @item @samp{addv@var{m}4}
5313 Like @code{add@var{m}3} but takes a @code{code_label} as operand 3 and
5314 emits code to jump to it if signed overflow occurs during the addition.
5315 This pattern is used to implement the built-in functions performing
5316 signed integer addition with overflow checking.
5318 @cindex @code{subv@var{m}4} instruction pattern
5319 @cindex @code{mulv@var{m}4} instruction pattern
5320 @item @samp{subv@var{m}4}, @samp{mulv@var{m}4}
5321 Similar, for other signed arithmetic operations.
5323 @cindex @code{uaddv@var{m}4} instruction pattern
5324 @item @samp{uaddv@var{m}4}
5325 Like @code{addv@var{m}4} but for unsigned addition. That is to
5326 say, the operation is the same as signed addition but the jump
5327 is taken only on unsigned overflow.
5329 @cindex @code{usubv@var{m}4} instruction pattern
5330 @cindex @code{umulv@var{m}4} instruction pattern
5331 @item @samp{usubv@var{m}4}, @samp{umulv@var{m}4}
5332 Similar, for other unsigned arithmetic operations.
5334 @cindex @code{addptr@var{m}3} instruction pattern
5335 @item @samp{addptr@var{m}3}
5336 Like @code{add@var{m}3} but is guaranteed to only be used for address
5337 calculations. The expanded code is not allowed to clobber the
5338 condition code. It only needs to be defined if @code{add@var{m}3}
5339 sets the condition code. If adds used for address calculations and
5340 normal adds are not compatible it is required to expand a distinct
5341 pattern (e.g.@: using an unspec). The pattern is used by LRA to emit
5342 address calculations. @code{add@var{m}3} is used if
5343 @code{addptr@var{m}3} is not defined.
5345 @cindex @code{fma@var{m}4} instruction pattern
5346 @item @samp{fma@var{m}4}
5347 Multiply operand 2 and operand 1, then add operand 3, storing the
5348 result in operand 0 without doing an intermediate rounding step. All
5349 operands must have mode @var{m}. This pattern is used to implement
5350 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
5351 the ISO C99 standard.
5353 @cindex @code{fms@var{m}4} instruction pattern
5354 @item @samp{fms@var{m}4}
5355 Like @code{fma@var{m}4}, except operand 3 subtracted from the
5356 product instead of added to the product. This is represented
5360 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
5363 @cindex @code{fnma@var{m}4} instruction pattern
5364 @item @samp{fnma@var{m}4}
5365 Like @code{fma@var{m}4} except that the intermediate product
5366 is negated before being added to operand 3. This is represented
5370 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
5373 @cindex @code{fnms@var{m}4} instruction pattern
5374 @item @samp{fnms@var{m}4}
5375 Like @code{fms@var{m}4} except that the intermediate product
5376 is negated before subtracting operand 3. This is represented
5380 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
5383 @cindex @code{min@var{m}3} instruction pattern
5384 @cindex @code{max@var{m}3} instruction pattern
5385 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
5386 Signed minimum and maximum operations. When used with floating point,
5387 if both operands are zeros, or if either operand is @code{NaN}, then
5388 it is unspecified which of the two operands is returned as the result.
5390 @cindex @code{fmin@var{m}3} instruction pattern
5391 @cindex @code{fmax@var{m}3} instruction pattern
5392 @item @samp{fmin@var{m}3}, @samp{fmax@var{m}3}
5393 IEEE-conformant minimum and maximum operations. If one operand is a quiet
5394 @code{NaN}, then the other operand is returned. If both operands are quiet
5395 @code{NaN}, then a quiet @code{NaN} is returned. In the case when gcc supports
5396 signaling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
5397 raised and a quiet @code{NaN} is returned.
5399 All operands have mode @var{m}, which is a scalar or vector
5400 floating-point mode. These patterns are not allowed to @code{FAIL}.
5402 @cindex @code{reduc_smin_scal_@var{m}} instruction pattern
5403 @cindex @code{reduc_smax_scal_@var{m}} instruction pattern
5404 @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}}
5405 Find the signed minimum/maximum of the elements of a vector. The vector is
5406 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5407 the elements of the input vector.
5409 @cindex @code{reduc_umin_scal_@var{m}} instruction pattern
5410 @cindex @code{reduc_umax_scal_@var{m}} instruction pattern
5411 @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}}
5412 Find the unsigned minimum/maximum of the elements of a vector. The vector is
5413 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5414 the elements of the input vector.
5416 @cindex @code{reduc_plus_scal_@var{m}} instruction pattern
5417 @item @samp{reduc_plus_scal_@var{m}}
5418 Compute the sum of the elements of a vector. The vector is operand 1, and
5419 operand 0 is the scalar result, with mode equal to the mode of the elements of
5422 @cindex @code{reduc_and_scal_@var{m}} instruction pattern
5423 @item @samp{reduc_and_scal_@var{m}}
5424 @cindex @code{reduc_ior_scal_@var{m}} instruction pattern
5425 @itemx @samp{reduc_ior_scal_@var{m}}
5426 @cindex @code{reduc_xor_scal_@var{m}} instruction pattern
5427 @itemx @samp{reduc_xor_scal_@var{m}}
5428 Compute the bitwise @code{AND}/@code{IOR}/@code{XOR} reduction of the elements
5429 of a vector of mode @var{m}. Operand 1 is the vector input and operand 0
5430 is the scalar result. The mode of the scalar result is the same as one
5433 @cindex @code{extract_last_@var{m}} instruction pattern
5434 @item @code{extract_last_@var{m}}
5435 Find the last set bit in mask operand 1 and extract the associated element
5436 of vector operand 2. Store the result in scalar operand 0. Operand 2
5437 has vector mode @var{m} while operand 0 has the mode appropriate for one
5438 element of @var{m}. Operand 1 has the usual mask mode for vectors of mode
5439 @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5441 @cindex @code{fold_extract_last_@var{m}} instruction pattern
5442 @item @code{fold_extract_last_@var{m}}
5443 If any bits of mask operand 2 are set, find the last set bit, extract
5444 the associated element from vector operand 3, and store the result
5445 in operand 0. Store operand 1 in operand 0 otherwise. Operand 3
5446 has mode @var{m} and operands 0 and 1 have the mode appropriate for
5447 one element of @var{m}. Operand 2 has the usual mask mode for vectors
5448 of mode @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}.
5450 @cindex @code{fold_left_plus_@var{m}} instruction pattern
5451 @item @code{fold_left_plus_@var{m}}
5452 Take scalar operand 1 and successively add each element from vector
5453 operand 2. Store the result in scalar operand 0. The vector has
5454 mode @var{m} and the scalars have the mode appropriate for one
5455 element of @var{m}. The operation is strictly in-order: there is
5458 @cindex @code{sdot_prod@var{m}} instruction pattern
5459 @item @samp{sdot_prod@var{m}}
5460 @cindex @code{udot_prod@var{m}} instruction pattern
5461 @itemx @samp{udot_prod@var{m}}
5462 Compute the sum of the products of two signed/unsigned elements.
5463 Operand 1 and operand 2 are of the same mode. Their product, which is of a
5464 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
5465 wider than the mode of the product. The result is placed in operand 0, which
5466 is of the same mode as operand 3.
5468 @cindex @code{ssad@var{m}} instruction pattern
5469 @item @samp{ssad@var{m}}
5470 @cindex @code{usad@var{m}} instruction pattern
5471 @item @samp{usad@var{m}}
5472 Compute the sum of absolute differences of two signed/unsigned elements.
5473 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
5474 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
5475 equal or wider than the mode of the absolute difference. The result is placed
5476 in operand 0, which is of the same mode as operand 3.
5478 @cindex @code{widen_ssum@var{m3}} instruction pattern
5479 @item @samp{widen_ssum@var{m3}}
5480 @cindex @code{widen_usum@var{m3}} instruction pattern
5481 @itemx @samp{widen_usum@var{m3}}
5482 Operands 0 and 2 are of the same mode, which is wider than the mode of
5483 operand 1. Add operand 1 to operand 2 and place the widened result in
5484 operand 0. (This is used express accumulation of elements into an accumulator
5487 @cindex @code{vec_shl_insert_@var{m}} instruction pattern
5488 @item @samp{vec_shl_insert_@var{m}}
5489 Shift the elements in vector input operand 1 left one element (i.e.@:
5490 away from element 0) and fill the vacated element 0 with the scalar
5491 in operand 2. Store the result in vector output operand 0. Operands
5492 0 and 1 have mode @var{m} and operand 2 has the mode appropriate for
5493 one element of @var{m}.
5495 @cindex @code{vec_shr_@var{m}} instruction pattern
5496 @item @samp{vec_shr_@var{m}}
5497 Whole vector right shift in bits, i.e.@: towards element 0.
5498 Operand 1 is a vector to be shifted.
5499 Operand 2 is an integer shift amount in bits.
5500 Operand 0 is where the resulting shifted vector is stored.
5501 The output and input vectors should have the same modes.
5503 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
5504 @item @samp{vec_pack_trunc_@var{m}}
5505 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5506 are vectors of the same mode having N integral or floating point elements
5507 of size S@. Operand 0 is the resulting vector in which 2*N elements of
5508 size N/2 are concatenated after narrowing them down using truncation.
5510 @cindex @code{vec_pack_sbool_trunc_@var{m}} instruction pattern
5511 @item @samp{vec_pack_sbool_trunc_@var{m}}
5512 Narrow and merge the elements of two vectors. Operands 1 and 2 are vectors
5513 of the same type having N boolean elements. Operand 0 is the resulting
5514 vector in which 2*N elements are concatenated. The last operand (operand 3)
5515 is the number of elements in the output vector 2*N as a @code{CONST_INT}.
5516 This instruction pattern is used when all the vector input and output
5517 operands have the same scalar mode @var{m} and thus using
5518 @code{vec_pack_trunc_@var{m}} would be ambiguous.
5520 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
5521 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
5522 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
5523 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5524 are vectors of the same mode having N integral elements of size S.
5525 Operand 0 is the resulting vector in which the elements of the two input
5526 vectors are concatenated after narrowing them down using signed/unsigned
5527 saturating arithmetic.
5529 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
5530 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
5531 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
5532 Narrow, convert to signed/unsigned integral type and merge the elements
5533 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5534 floating point elements of size S@. Operand 0 is the resulting vector
5535 in which 2*N elements of size N/2 are concatenated.
5537 @cindex @code{vec_packs_float_@var{m}} instruction pattern
5538 @cindex @code{vec_packu_float_@var{m}} instruction pattern
5539 @item @samp{vec_packs_float_@var{m}}, @samp{vec_packu_float_@var{m}}
5540 Narrow, convert to floating point type and merge the elements
5541 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5542 signed/unsigned integral elements of size S@. Operand 0 is the resulting vector
5543 in which 2*N elements of size N/2 are concatenated.
5545 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
5546 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
5547 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
5548 Extract and widen (promote) the high/low part of a vector of signed
5549 integral or floating point elements. The input vector (operand 1) has N
5550 elements of size S@. Widen (promote) the high/low elements of the vector
5551 using signed or floating point extension and place the resulting N/2
5552 values of size 2*S in the output vector (operand 0).
5554 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
5555 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
5556 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
5557 Extract and widen (promote) the high/low part of a vector of unsigned
5558 integral elements. The input vector (operand 1) has N elements of size S.
5559 Widen (promote) the high/low elements of the vector using zero extension and
5560 place the resulting N/2 values of size 2*S in the output vector (operand 0).
5562 @cindex @code{vec_unpacks_sbool_hi_@var{m}} instruction pattern
5563 @cindex @code{vec_unpacks_sbool_lo_@var{m}} instruction pattern
5564 @item @samp{vec_unpacks_sbool_hi_@var{m}}, @samp{vec_unpacks_sbool_lo_@var{m}}
5565 Extract the high/low part of a vector of boolean elements that have scalar
5566 mode @var{m}. The input vector (operand 1) has N elements, the output
5567 vector (operand 0) has N/2 elements. The last operand (operand 2) is the
5568 number of elements of the input vector N as a @code{CONST_INT}. These
5569 patterns are used if both the input and output vectors have the same scalar
5570 mode @var{m} and thus using @code{vec_unpacks_hi_@var{m}} or
5571 @code{vec_unpacks_lo_@var{m}} would be ambiguous.
5573 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
5574 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
5575 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
5576 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
5577 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
5578 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
5579 Extract, convert to floating point type and widen the high/low part of a
5580 vector of signed/unsigned integral elements. The input vector (operand 1)
5581 has N elements of size S@. Convert the high/low elements of the vector using
5582 floating point conversion and place the resulting N/2 values of size 2*S in
5583 the output vector (operand 0).
5585 @cindex @code{vec_unpack_sfix_trunc_hi_@var{m}} instruction pattern
5586 @cindex @code{vec_unpack_sfix_trunc_lo_@var{m}} instruction pattern
5587 @cindex @code{vec_unpack_ufix_trunc_hi_@var{m}} instruction pattern
5588 @cindex @code{vec_unpack_ufix_trunc_lo_@var{m}} instruction pattern
5589 @item @samp{vec_unpack_sfix_trunc_hi_@var{m}},
5590 @itemx @samp{vec_unpack_sfix_trunc_lo_@var{m}}
5591 @itemx @samp{vec_unpack_ufix_trunc_hi_@var{m}}
5592 @itemx @samp{vec_unpack_ufix_trunc_lo_@var{m}}
5593 Extract, convert to signed/unsigned integer type and widen the high/low part of a
5594 vector of floating point elements. The input vector (operand 1)
5595 has N elements of size S@. Convert the high/low elements of the vector
5596 to integers and place the resulting N/2 values of size 2*S in
5597 the output vector (operand 0).
5599 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
5600 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
5601 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
5602 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
5603 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
5604 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
5605 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
5606 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
5607 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
5608 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
5609 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
5610 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
5611 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
5612 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
5613 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
5614 in the output vector (operand 0). A target shouldn't implement even/odd pattern
5615 pair if it is less efficient than lo/hi one.
5617 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
5618 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
5619 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
5620 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
5621 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
5622 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
5623 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
5624 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
5625 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
5626 output vector (operand 0).
5628 @cindex @code{mulhisi3} instruction pattern
5629 @item @samp{mulhisi3}
5630 Multiply operands 1 and 2, which have mode @code{HImode}, and store
5631 a @code{SImode} product in operand 0.
5633 @cindex @code{mulqihi3} instruction pattern
5634 @cindex @code{mulsidi3} instruction pattern
5635 @item @samp{mulqihi3}, @samp{mulsidi3}
5636 Similar widening-multiplication instructions of other widths.
5638 @cindex @code{umulqihi3} instruction pattern
5639 @cindex @code{umulhisi3} instruction pattern
5640 @cindex @code{umulsidi3} instruction pattern
5641 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
5642 Similar widening-multiplication instructions that do unsigned
5645 @cindex @code{usmulqihi3} instruction pattern
5646 @cindex @code{usmulhisi3} instruction pattern
5647 @cindex @code{usmulsidi3} instruction pattern
5648 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
5649 Similar widening-multiplication instructions that interpret the first
5650 operand as unsigned and the second operand as signed, then do a signed
5653 @cindex @code{smul@var{m}3_highpart} instruction pattern
5654 @item @samp{smul@var{m}3_highpart}
5655 Perform a signed multiplication of operands 1 and 2, which have mode
5656 @var{m}, and store the most significant half of the product in operand 0.
5657 The least significant half of the product is discarded.
5659 @cindex @code{umul@var{m}3_highpart} instruction pattern
5660 @item @samp{umul@var{m}3_highpart}
5661 Similar, but the multiplication is unsigned.
5663 @cindex @code{madd@var{m}@var{n}4} instruction pattern
5664 @item @samp{madd@var{m}@var{n}4}
5665 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
5666 operand 3, and store the result in operand 0. Operands 1 and 2
5667 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5668 Both modes must be integer or fixed-point modes and @var{n} must be twice
5669 the size of @var{m}.
5671 In other words, @code{madd@var{m}@var{n}4} is like
5672 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
5674 These instructions are not allowed to @code{FAIL}.
5676 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
5677 @item @samp{umadd@var{m}@var{n}4}
5678 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5679 operands instead of sign-extending them.
5681 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5682 @item @samp{ssmadd@var{m}@var{n}4}
5683 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5686 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5687 @item @samp{usmadd@var{m}@var{n}4}
5688 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5689 unsigned-saturating.
5691 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5692 @item @samp{msub@var{m}@var{n}4}
5693 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5694 result from operand 3, and store the result in operand 0. Operands 1 and 2
5695 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5696 Both modes must be integer or fixed-point modes and @var{n} must be twice
5697 the size of @var{m}.
5699 In other words, @code{msub@var{m}@var{n}4} is like
5700 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5703 These instructions are not allowed to @code{FAIL}.
5705 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5706 @item @samp{umsub@var{m}@var{n}4}
5707 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5708 operands instead of sign-extending them.
5710 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5711 @item @samp{ssmsub@var{m}@var{n}4}
5712 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5715 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5716 @item @samp{usmsub@var{m}@var{n}4}
5717 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5718 unsigned-saturating.
5720 @cindex @code{divmod@var{m}4} instruction pattern
5721 @item @samp{divmod@var{m}4}
5722 Signed division that produces both a quotient and a remainder.
5723 Operand 1 is divided by operand 2 to produce a quotient stored
5724 in operand 0 and a remainder stored in operand 3.
5726 For machines with an instruction that produces both a quotient and a
5727 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5728 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5729 allows optimization in the relatively common case when both the quotient
5730 and remainder are computed.
5732 If an instruction that just produces a quotient or just a remainder
5733 exists and is more efficient than the instruction that produces both,
5734 write the output routine of @samp{divmod@var{m}4} to call
5735 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5736 quotient or remainder and generate the appropriate instruction.
5738 @cindex @code{udivmod@var{m}4} instruction pattern
5739 @item @samp{udivmod@var{m}4}
5740 Similar, but does unsigned division.
5742 @anchor{shift patterns}
5743 @cindex @code{ashl@var{m}3} instruction pattern
5744 @cindex @code{ssashl@var{m}3} instruction pattern
5745 @cindex @code{usashl@var{m}3} instruction pattern
5746 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5747 Arithmetic-shift operand 1 left by a number of bits specified by operand
5748 2, and store the result in operand 0. Here @var{m} is the mode of
5749 operand 0 and operand 1; operand 2's mode is specified by the
5750 instruction pattern, and the compiler will convert the operand to that
5751 mode before generating the instruction. The shift or rotate expander
5752 or instruction pattern should explicitly specify the mode of the operand 2,
5753 it should never be @code{VOIDmode}. The meaning of out-of-range shift
5754 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5755 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5757 @cindex @code{ashr@var{m}3} instruction pattern
5758 @cindex @code{lshr@var{m}3} instruction pattern
5759 @cindex @code{rotl@var{m}3} instruction pattern
5760 @cindex @code{rotr@var{m}3} instruction pattern
5761 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5762 Other shift and rotate instructions, analogous to the
5763 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5765 @cindex @code{vashl@var{m}3} instruction pattern
5766 @cindex @code{vashr@var{m}3} instruction pattern
5767 @cindex @code{vlshr@var{m}3} instruction pattern
5768 @cindex @code{vrotl@var{m}3} instruction pattern
5769 @cindex @code{vrotr@var{m}3} instruction pattern
5770 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5771 Vector shift and rotate instructions that take vectors as operand 2
5772 instead of a scalar type.
5774 @cindex @code{avg@var{m}3_floor} instruction pattern
5775 @cindex @code{uavg@var{m}3_floor} instruction pattern
5776 @item @samp{avg@var{m}3_floor}
5777 @itemx @samp{uavg@var{m}3_floor}
5778 Signed and unsigned average instructions. These instructions add
5779 operands 1 and 2 without truncation, divide the result by 2,
5780 round towards -Inf, and store the result in operand 0. This is
5781 equivalent to the C code:
5783 narrow op0, op1, op2;
5785 op0 = (narrow) (((wide) op1 + (wide) op2) >> 1);
5787 where the sign of @samp{narrow} determines whether this is a signed
5788 or unsigned operation.
5790 @cindex @code{avg@var{m}3_ceil} instruction pattern
5791 @cindex @code{uavg@var{m}3_ceil} instruction pattern
5792 @item @samp{avg@var{m}3_ceil}
5793 @itemx @samp{uavg@var{m}3_ceil}
5794 Like @samp{avg@var{m}3_floor} and @samp{uavg@var{m}3_floor}, but round
5795 towards +Inf. This is equivalent to the C code:
5797 narrow op0, op1, op2;
5799 op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1);
5802 @cindex @code{bswap@var{m}2} instruction pattern
5803 @item @samp{bswap@var{m}2}
5804 Reverse the order of bytes of operand 1 and store the result in operand 0.
5806 @cindex @code{neg@var{m}2} instruction pattern
5807 @cindex @code{ssneg@var{m}2} instruction pattern
5808 @cindex @code{usneg@var{m}2} instruction pattern
5809 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5810 Negate operand 1 and store the result in operand 0.
5812 @cindex @code{negv@var{m}3} instruction pattern
5813 @item @samp{negv@var{m}3}
5814 Like @code{neg@var{m}2} but takes a @code{code_label} as operand 2 and
5815 emits code to jump to it if signed overflow occurs during the negation.
5817 @cindex @code{abs@var{m}2} instruction pattern
5818 @item @samp{abs@var{m}2}
5819 Store the absolute value of operand 1 into operand 0.
5821 @cindex @code{sqrt@var{m}2} instruction pattern
5822 @item @samp{sqrt@var{m}2}
5823 Store the square root of operand 1 into operand 0. Both operands have
5824 mode @var{m}, which is a scalar or vector floating-point mode.
5826 This pattern is not allowed to @code{FAIL}.
5828 @cindex @code{rsqrt@var{m}2} instruction pattern
5829 @item @samp{rsqrt@var{m}2}
5830 Store the reciprocal of the square root of operand 1 into operand 0.
5831 Both operands have mode @var{m}, which is a scalar or vector
5832 floating-point mode.
5834 On most architectures this pattern is only approximate, so either
5835 its C condition or the @code{TARGET_OPTAB_SUPPORTED_P} hook should
5836 check for the appropriate math flags. (Using the C condition is
5837 more direct, but using @code{TARGET_OPTAB_SUPPORTED_P} can be useful
5838 if a target-specific built-in also uses the @samp{rsqrt@var{m}2}
5841 This pattern is not allowed to @code{FAIL}.
5843 @cindex @code{fmod@var{m}3} instruction pattern
5844 @item @samp{fmod@var{m}3}
5845 Store the remainder of dividing operand 1 by operand 2 into
5846 operand 0, rounded towards zero to an integer. All operands have
5847 mode @var{m}, which is a scalar or vector floating-point mode.
5849 This pattern is not allowed to @code{FAIL}.
5851 @cindex @code{remainder@var{m}3} instruction pattern
5852 @item @samp{remainder@var{m}3}
5853 Store the remainder of dividing operand 1 by operand 2 into
5854 operand 0, rounded to the nearest integer. All operands have
5855 mode @var{m}, which is a scalar or vector floating-point mode.
5857 This pattern is not allowed to @code{FAIL}.
5859 @cindex @code{scalb@var{m}3} instruction pattern
5860 @item @samp{scalb@var{m}3}
5861 Raise @code{FLT_RADIX} to the power of operand 2, multiply it by
5862 operand 1, and store the result in operand 0. All operands have
5863 mode @var{m}, which is a scalar or vector floating-point mode.
5865 This pattern is not allowed to @code{FAIL}.
5867 @cindex @code{ldexp@var{m}3} instruction pattern
5868 @item @samp{ldexp@var{m}3}
5869 Raise 2 to the power of operand 2, multiply it by operand 1, and store
5870 the result in operand 0. Operands 0 and 1 have mode @var{m}, which is
5871 a scalar or vector floating-point mode. Operand 2's mode has
5872 the same number of elements as @var{m} and each element is wide
5873 enough to store an @code{int}. The integers are signed.
5875 This pattern is not allowed to @code{FAIL}.
5877 @cindex @code{cos@var{m}2} instruction pattern
5878 @item @samp{cos@var{m}2}
5879 Store the cosine of operand 1 into operand 0. Both operands have
5880 mode @var{m}, which is a scalar or vector floating-point mode.
5882 This pattern is not allowed to @code{FAIL}.
5884 @cindex @code{sin@var{m}2} instruction pattern
5885 @item @samp{sin@var{m}2}
5886 Store the sine of operand 1 into operand 0. Both operands have
5887 mode @var{m}, which is a scalar or vector floating-point mode.
5889 This pattern is not allowed to @code{FAIL}.
5891 @cindex @code{sincos@var{m}3} instruction pattern
5892 @item @samp{sincos@var{m}3}
5893 Store the cosine of operand 2 into operand 0 and the sine of
5894 operand 2 into operand 1. All operands have mode @var{m},
5895 which is a scalar or vector floating-point mode.
5897 Targets that can calculate the sine and cosine simultaneously can
5898 implement this pattern as opposed to implementing individual
5899 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5900 and @code{cos} built-in functions will then be expanded to the
5901 @code{sincos@var{m}3} pattern, with one of the output values
5904 @cindex @code{tan@var{m}2} instruction pattern
5905 @item @samp{tan@var{m}2}
5906 Store the tangent of operand 1 into operand 0. Both operands have
5907 mode @var{m}, which is a scalar or vector floating-point mode.
5909 This pattern is not allowed to @code{FAIL}.
5911 @cindex @code{asin@var{m}2} instruction pattern
5912 @item @samp{asin@var{m}2}
5913 Store the arc sine of operand 1 into operand 0. Both operands have
5914 mode @var{m}, which is a scalar or vector floating-point mode.
5916 This pattern is not allowed to @code{FAIL}.
5918 @cindex @code{acos@var{m}2} instruction pattern
5919 @item @samp{acos@var{m}2}
5920 Store the arc cosine of operand 1 into operand 0. Both operands have
5921 mode @var{m}, which is a scalar or vector floating-point mode.
5923 This pattern is not allowed to @code{FAIL}.
5925 @cindex @code{atan@var{m}2} instruction pattern
5926 @item @samp{atan@var{m}2}
5927 Store the arc tangent of operand 1 into operand 0. Both operands have
5928 mode @var{m}, which is a scalar or vector floating-point mode.
5930 This pattern is not allowed to @code{FAIL}.
5932 @cindex @code{exp@var{m}2} instruction pattern
5933 @item @samp{exp@var{m}2}
5934 Raise e (the base of natural logarithms) to the power of operand 1
5935 and store the result in operand 0. Both operands have mode @var{m},
5936 which is a scalar or vector floating-point mode.
5938 This pattern is not allowed to @code{FAIL}.
5940 @cindex @code{expm1@var{m}2} instruction pattern
5941 @item @samp{expm1@var{m}2}
5942 Raise e (the base of natural logarithms) to the power of operand 1,
5943 subtract 1, and store the result in operand 0. Both operands have
5944 mode @var{m}, which is a scalar or vector floating-point mode.
5946 For inputs close to zero, the pattern is expected to be more
5947 accurate than a separate @code{exp@var{m}2} and @code{sub@var{m}3}
5950 This pattern is not allowed to @code{FAIL}.
5952 @cindex @code{exp10@var{m}2} instruction pattern
5953 @item @samp{exp10@var{m}2}
5954 Raise 10 to the power of operand 1 and store the result in operand 0.
5955 Both operands have mode @var{m}, which is a scalar or vector
5956 floating-point mode.
5958 This pattern is not allowed to @code{FAIL}.
5960 @cindex @code{exp2@var{m}2} instruction pattern
5961 @item @samp{exp2@var{m}2}
5962 Raise 2 to the power of operand 1 and store the result in operand 0.
5963 Both operands have mode @var{m}, which is a scalar or vector
5964 floating-point mode.
5966 This pattern is not allowed to @code{FAIL}.
5968 @cindex @code{log@var{m}2} instruction pattern
5969 @item @samp{log@var{m}2}
5970 Store the natural logarithm of operand 1 into operand 0. Both operands
5971 have mode @var{m}, which is a scalar or vector floating-point mode.
5973 This pattern is not allowed to @code{FAIL}.
5975 @cindex @code{log1p@var{m}2} instruction pattern
5976 @item @samp{log1p@var{m}2}
5977 Add 1 to operand 1, compute the natural logarithm, and store
5978 the result in operand 0. Both operands have mode @var{m}, which is
5979 a scalar or vector floating-point mode.
5981 For inputs close to zero, the pattern is expected to be more
5982 accurate than a separate @code{add@var{m}3} and @code{log@var{m}2}
5985 This pattern is not allowed to @code{FAIL}.
5987 @cindex @code{log10@var{m}2} instruction pattern
5988 @item @samp{log10@var{m}2}
5989 Store the base-10 logarithm of operand 1 into operand 0. Both operands
5990 have mode @var{m}, which is a scalar or vector floating-point mode.
5992 This pattern is not allowed to @code{FAIL}.
5994 @cindex @code{log2@var{m}2} instruction pattern
5995 @item @samp{log2@var{m}2}
5996 Store the base-2 logarithm of operand 1 into operand 0. Both operands
5997 have mode @var{m}, which is a scalar or vector floating-point mode.
5999 This pattern is not allowed to @code{FAIL}.
6001 @cindex @code{logb@var{m}2} instruction pattern
6002 @item @samp{logb@var{m}2}
6003 Store the base-@code{FLT_RADIX} logarithm of operand 1 into operand 0.
6004 Both operands have mode @var{m}, which is a scalar or vector
6005 floating-point mode.
6007 This pattern is not allowed to @code{FAIL}.
6009 @cindex @code{significand@var{m}2} instruction pattern
6010 @item @samp{significand@var{m}2}
6011 Store the significand of floating-point operand 1 in operand 0.
6012 Both operands have mode @var{m}, which is a scalar or vector
6013 floating-point mode.
6015 This pattern is not allowed to @code{FAIL}.
6017 @cindex @code{pow@var{m}3} instruction pattern
6018 @item @samp{pow@var{m}3}
6019 Store the value of operand 1 raised to the exponent operand 2
6020 into operand 0. All operands have mode @var{m}, which is a scalar
6021 or vector floating-point mode.
6023 This pattern is not allowed to @code{FAIL}.
6025 @cindex @code{atan2@var{m}3} instruction pattern
6026 @item @samp{atan2@var{m}3}
6027 Store the arc tangent (inverse tangent) of operand 1 divided by
6028 operand 2 into operand 0, using the signs of both arguments to
6029 determine the quadrant of the result. All operands have mode
6030 @var{m}, which is a scalar or vector floating-point mode.
6032 This pattern is not allowed to @code{FAIL}.
6034 @cindex @code{floor@var{m}2} instruction pattern
6035 @item @samp{floor@var{m}2}
6036 Store the largest integral value not greater than operand 1 in operand 0.
6037 Both operands have mode @var{m}, which is a scalar or vector
6038 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
6039 effect, the ``inexact'' exception may be raised for noninteger
6040 operands; otherwise, it may not.
6042 This pattern is not allowed to @code{FAIL}.
6044 @cindex @code{btrunc@var{m}2} instruction pattern
6045 @item @samp{btrunc@var{m}2}
6046 Round operand 1 to an integer, towards zero, and store the result in
6047 operand 0. Both operands have mode @var{m}, which is a scalar or
6048 vector floating-point mode. If @option{-ffp-int-builtin-inexact} is
6049 in effect, the ``inexact'' exception may be raised for noninteger
6050 operands; otherwise, it may not.
6052 This pattern is not allowed to @code{FAIL}.
6054 @cindex @code{round@var{m}2} instruction pattern
6055 @item @samp{round@var{m}2}
6056 Round operand 1 to the nearest integer, rounding away from zero in the
6057 event of a tie, and store the result in operand 0. Both operands have
6058 mode @var{m}, which is a scalar or vector floating-point mode. If
6059 @option{-ffp-int-builtin-inexact} is in effect, the ``inexact''
6060 exception may be raised for noninteger operands; otherwise, it may
6063 This pattern is not allowed to @code{FAIL}.
6065 @cindex @code{ceil@var{m}2} instruction pattern
6066 @item @samp{ceil@var{m}2}
6067 Store the smallest integral value not less than operand 1 in operand 0.
6068 Both operands have mode @var{m}, which is a scalar or vector
6069 floating-point mode. If @option{-ffp-int-builtin-inexact} is in
6070 effect, the ``inexact'' exception may be raised for noninteger
6071 operands; otherwise, it may not.
6073 This pattern is not allowed to @code{FAIL}.
6075 @cindex @code{nearbyint@var{m}2} instruction pattern
6076 @item @samp{nearbyint@var{m}2}
6077 Round operand 1 to an integer, using the current rounding mode, and
6078 store the result in operand 0. Do not raise an inexact condition when
6079 the result is different from the argument. Both operands have mode
6080 @var{m}, which is a scalar or vector floating-point mode.
6082 This pattern is not allowed to @code{FAIL}.
6084 @cindex @code{rint@var{m}2} instruction pattern
6085 @item @samp{rint@var{m}2}
6086 Round operand 1 to an integer, using the current rounding mode, and
6087 store the result in operand 0. Raise an inexact condition when
6088 the result is different from the argument. Both operands have mode
6089 @var{m}, which is a scalar or vector floating-point mode.
6091 This pattern is not allowed to @code{FAIL}.
6093 @cindex @code{lrint@var{m}@var{n}2}
6094 @item @samp{lrint@var{m}@var{n}2}
6095 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6096 point mode @var{n} as a signed number according to the current
6097 rounding mode and store in operand 0 (which has mode @var{n}).
6099 @cindex @code{lround@var{m}@var{n}2}
6100 @item @samp{lround@var{m}@var{n}2}
6101 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6102 point mode @var{n} as a signed number rounding to nearest and away
6103 from zero and store in operand 0 (which has mode @var{n}).
6105 @cindex @code{lfloor@var{m}@var{n}2}
6106 @item @samp{lfloor@var{m}@var{n}2}
6107 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6108 point mode @var{n} as a signed number rounding down and store in
6109 operand 0 (which has mode @var{n}).
6111 @cindex @code{lceil@var{m}@var{n}2}
6112 @item @samp{lceil@var{m}@var{n}2}
6113 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6114 point mode @var{n} as a signed number rounding up and store in
6115 operand 0 (which has mode @var{n}).
6117 @cindex @code{copysign@var{m}3} instruction pattern
6118 @item @samp{copysign@var{m}3}
6119 Store a value with the magnitude of operand 1 and the sign of operand
6120 2 into operand 0. All operands have mode @var{m}, which is a scalar or
6121 vector floating-point mode.
6123 This pattern is not allowed to @code{FAIL}.
6125 @cindex @code{xorsign@var{m}3} instruction pattern
6126 @item @samp{xorsign@var{m}3}
6127 Equivalent to @samp{op0 = op1 * copysign (1.0, op2)}: store a value with
6128 the magnitude of operand 1 and the sign of operand 2 into operand 0.
6129 All operands have mode @var{m}, which is a scalar or vector
6130 floating-point mode.
6132 This pattern is not allowed to @code{FAIL}.
6134 @cindex @code{ffs@var{m}2} instruction pattern
6135 @item @samp{ffs@var{m}2}
6136 Store into operand 0 one plus the index of the least significant 1-bit
6137 of operand 1. If operand 1 is zero, store zero.
6139 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6140 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6141 integer mode is suitable for the target. The compiler will insert
6142 conversion instructions as necessary (typically to convert the result
6143 to the same width as @code{int}). When @var{m} is a vector, both
6144 operands must have mode @var{m}.
6146 This pattern is not allowed to @code{FAIL}.
6148 @cindex @code{clrsb@var{m}2} instruction pattern
6149 @item @samp{clrsb@var{m}2}
6150 Count leading redundant sign bits.
6151 Store into operand 0 the number of redundant sign bits in operand 1, starting
6152 at the most significant bit position.
6153 A redundant sign bit is defined as any sign bit after the first. As such,
6154 this count will be one less than the count of leading sign bits.
6156 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6157 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6158 integer mode is suitable for the target. The compiler will insert
6159 conversion instructions as necessary (typically to convert the result
6160 to the same width as @code{int}). When @var{m} is a vector, both
6161 operands must have mode @var{m}.
6163 This pattern is not allowed to @code{FAIL}.
6165 @cindex @code{clz@var{m}2} instruction pattern
6166 @item @samp{clz@var{m}2}
6167 Store into operand 0 the number of leading 0-bits in operand 1, starting
6168 at the most significant bit position. If operand 1 is 0, the
6169 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
6170 the result is undefined or has a useful value.
6172 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6173 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6174 integer mode is suitable for the target. The compiler will insert
6175 conversion instructions as necessary (typically to convert the result
6176 to the same width as @code{int}). When @var{m} is a vector, both
6177 operands must have mode @var{m}.
6179 This pattern is not allowed to @code{FAIL}.
6181 @cindex @code{ctz@var{m}2} instruction pattern
6182 @item @samp{ctz@var{m}2}
6183 Store into operand 0 the number of trailing 0-bits in operand 1, starting
6184 at the least significant bit position. If operand 1 is 0, the
6185 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
6186 the result is undefined or has a useful value.
6188 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6189 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6190 integer mode is suitable for the target. The compiler will insert
6191 conversion instructions as necessary (typically to convert the result
6192 to the same width as @code{int}). When @var{m} is a vector, both
6193 operands must have mode @var{m}.
6195 This pattern is not allowed to @code{FAIL}.
6197 @cindex @code{popcount@var{m}2} instruction pattern
6198 @item @samp{popcount@var{m}2}
6199 Store into operand 0 the number of 1-bits in operand 1.
6201 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6202 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6203 integer mode is suitable for the target. The compiler will insert
6204 conversion instructions as necessary (typically to convert the result
6205 to the same width as @code{int}). When @var{m} is a vector, both
6206 operands must have mode @var{m}.
6208 This pattern is not allowed to @code{FAIL}.
6210 @cindex @code{parity@var{m}2} instruction pattern
6211 @item @samp{parity@var{m}2}
6212 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
6213 in operand 1 modulo 2.
6215 @var{m} is either a scalar or vector integer mode. When it is a scalar,
6216 operand 1 has mode @var{m} but operand 0 can have whatever scalar
6217 integer mode is suitable for the target. The compiler will insert
6218 conversion instructions as necessary (typically to convert the result
6219 to the same width as @code{int}). When @var{m} is a vector, both
6220 operands must have mode @var{m}.
6222 This pattern is not allowed to @code{FAIL}.
6224 @cindex @code{one_cmpl@var{m}2} instruction pattern
6225 @item @samp{one_cmpl@var{m}2}
6226 Store the bitwise-complement of operand 1 into operand 0.
6228 @cindex @code{movmem@var{m}} instruction pattern
6229 @item @samp{movmem@var{m}}
6230 Block move instruction. The destination and source blocks of memory
6231 are the first two operands, and both are @code{mem:BLK}s with an
6232 address in mode @code{Pmode}.
6234 The number of bytes to move is the third operand, in mode @var{m}.
6235 Usually, you specify @code{Pmode} for @var{m}. However, if you can
6236 generate better code knowing the range of valid lengths is smaller than
6237 those representable in a full Pmode pointer, you should provide
6239 mode corresponding to the range of values you can handle efficiently
6240 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
6241 that appear negative) and also a pattern with @code{Pmode}.
6243 The fourth operand is the known shared alignment of the source and
6244 destination, in the form of a @code{const_int} rtx. Thus, if the
6245 compiler knows that both source and destination are word-aligned,
6246 it may provide the value 4 for this operand.
6248 Optional operands 5 and 6 specify expected alignment and size of block
6249 respectively. The expected alignment differs from alignment in operand 4
6250 in a way that the blocks are not required to be aligned according to it in
6251 all cases. This expected alignment is also in bytes, just like operand 4.
6252 Expected size, when unknown, is set to @code{(const_int -1)}.
6254 Descriptions of multiple @code{movmem@var{m}} patterns can only be
6255 beneficial if the patterns for smaller modes have fewer restrictions
6256 on their first, second and fourth operands. Note that the mode @var{m}
6257 in @code{movmem@var{m}} does not impose any restriction on the mode of
6258 individually moved data units in the block.
6260 These patterns need not give special consideration to the possibility
6261 that the source and destination strings might overlap.
6263 @cindex @code{movstr} instruction pattern
6265 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
6266 an output operand in mode @code{Pmode}. The addresses of the
6267 destination and source strings are operands 1 and 2, and both are
6268 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
6269 the expansion of this pattern should store in operand 0 the address in
6270 which the @code{NUL} terminator was stored in the destination string.
6272 This patern has also several optional operands that are same as in
6275 @cindex @code{setmem@var{m}} instruction pattern
6276 @item @samp{setmem@var{m}}
6277 Block set instruction. The destination string is the first operand,
6278 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
6279 number of bytes to set is the second operand, in mode @var{m}. The value to
6280 initialize the memory with is the third operand. Targets that only support the
6281 clearing of memory should reject any value that is not the constant 0. See
6282 @samp{movmem@var{m}} for a discussion of the choice of mode.
6284 The fourth operand is the known alignment of the destination, in the form
6285 of a @code{const_int} rtx. Thus, if the compiler knows that the
6286 destination is word-aligned, it may provide the value 4 for this
6289 Optional operands 5 and 6 specify expected alignment and size of block
6290 respectively. The expected alignment differs from alignment in operand 4
6291 in a way that the blocks are not required to be aligned according to it in
6292 all cases. This expected alignment is also in bytes, just like operand 4.
6293 Expected size, when unknown, is set to @code{(const_int -1)}.
6294 Operand 7 is the minimal size of the block and operand 8 is the
6295 maximal size of the block (NULL if it cannot be represented as CONST_INT).
6296 Operand 9 is the probable maximal size (i.e.@: we cannot rely on it for
6297 correctness, but it can be used for choosing proper code sequence for a
6300 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
6302 @cindex @code{cmpstrn@var{m}} instruction pattern
6303 @item @samp{cmpstrn@var{m}}
6304 String compare instruction, with five operands. Operand 0 is the output;
6305 it has mode @var{m}. The remaining four operands are like the operands
6306 of @samp{movmem@var{m}}. The two memory blocks specified are compared
6307 byte by byte in lexicographic order starting at the beginning of each
6308 string. The instruction is not allowed to prefetch more than one byte
6309 at a time since either string may end in the first byte and reading past
6310 that may access an invalid page or segment and cause a fault. The
6311 comparison terminates early if the fetched bytes are different or if
6312 they are equal to zero. The effect of the instruction is to store a
6313 value in operand 0 whose sign indicates the result of the comparison.
6315 @cindex @code{cmpstr@var{m}} instruction pattern
6316 @item @samp{cmpstr@var{m}}
6317 String compare instruction, without known maximum length. Operand 0 is the
6318 output; it has mode @var{m}. The second and third operand are the blocks of
6319 memory to be compared; both are @code{mem:BLK} with an address in mode
6322 The fourth operand is the known shared alignment of the source and
6323 destination, in the form of a @code{const_int} rtx. Thus, if the
6324 compiler knows that both source and destination are word-aligned,
6325 it may provide the value 4 for this operand.
6327 The two memory blocks specified are compared byte by byte in lexicographic
6328 order starting at the beginning of each string. The instruction is not allowed
6329 to prefetch more than one byte at a time since either string may end in the
6330 first byte and reading past that may access an invalid page or segment and
6331 cause a fault. The comparison will terminate when the fetched bytes
6332 are different or if they are equal to zero. The effect of the
6333 instruction is to store a value in operand 0 whose sign indicates the
6334 result of the comparison.
6336 @cindex @code{cmpmem@var{m}} instruction pattern
6337 @item @samp{cmpmem@var{m}}
6338 Block compare instruction, with five operands like the operands
6339 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
6340 byte by byte in lexicographic order starting at the beginning of each
6341 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
6342 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
6343 the comparison will not stop if both bytes are zero. The effect of
6344 the instruction is to store a value in operand 0 whose sign indicates
6345 the result of the comparison.
6347 @cindex @code{strlen@var{m}} instruction pattern
6348 @item @samp{strlen@var{m}}
6349 Compute the length of a string, with three operands.
6350 Operand 0 is the result (of mode @var{m}), operand 1 is
6351 a @code{mem} referring to the first character of the string,
6352 operand 2 is the character to search for (normally zero),
6353 and operand 3 is a constant describing the known alignment
6354 of the beginning of the string.
6356 @cindex @code{float@var{m}@var{n}2} instruction pattern
6357 @item @samp{float@var{m}@var{n}2}
6358 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
6359 floating point mode @var{n} and store in operand 0 (which has mode
6362 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
6363 @item @samp{floatuns@var{m}@var{n}2}
6364 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
6365 to floating point mode @var{n} and store in operand 0 (which has mode
6368 @cindex @code{fix@var{m}@var{n}2} instruction pattern
6369 @item @samp{fix@var{m}@var{n}2}
6370 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6371 point mode @var{n} as a signed number and store in operand 0 (which
6372 has mode @var{n}). This instruction's result is defined only when
6373 the value of operand 1 is an integer.
6375 If the machine description defines this pattern, it also needs to
6376 define the @code{ftrunc} pattern.
6378 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
6379 @item @samp{fixuns@var{m}@var{n}2}
6380 Convert operand 1 (valid for floating point mode @var{m}) to fixed
6381 point mode @var{n} as an unsigned number and store in operand 0 (which
6382 has mode @var{n}). This instruction's result is defined only when the
6383 value of operand 1 is an integer.
6385 @cindex @code{ftrunc@var{m}2} instruction pattern
6386 @item @samp{ftrunc@var{m}2}
6387 Convert operand 1 (valid for floating point mode @var{m}) to an
6388 integer value, still represented in floating point mode @var{m}, and
6389 store it in operand 0 (valid for floating point mode @var{m}).
6391 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
6392 @item @samp{fix_trunc@var{m}@var{n}2}
6393 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
6394 of mode @var{m} by converting the value to an integer.
6396 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
6397 @item @samp{fixuns_trunc@var{m}@var{n}2}
6398 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
6399 value of mode @var{m} by converting the value to an integer.
6401 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
6402 @item @samp{trunc@var{m}@var{n}2}
6403 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
6404 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6405 point or both floating point.
6407 @cindex @code{extend@var{m}@var{n}2} instruction pattern
6408 @item @samp{extend@var{m}@var{n}2}
6409 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6410 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6411 point or both floating point.
6413 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
6414 @item @samp{zero_extend@var{m}@var{n}2}
6415 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
6416 store in operand 0 (which has mode @var{n}). Both modes must be fixed
6419 @cindex @code{fract@var{m}@var{n}2} instruction pattern
6420 @item @samp{fract@var{m}@var{n}2}
6421 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6422 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6423 could be fixed-point to fixed-point, signed integer to fixed-point,
6424 fixed-point to signed integer, floating-point to fixed-point,
6425 or fixed-point to floating-point.
6426 When overflows or underflows happen, the results are undefined.
6428 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
6429 @item @samp{satfract@var{m}@var{n}2}
6430 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6431 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6432 could be fixed-point to fixed-point, signed integer to fixed-point,
6433 or floating-point to fixed-point.
6434 When overflows or underflows happen, the instruction saturates the
6435 results to the maximum or the minimum.
6437 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
6438 @item @samp{fractuns@var{m}@var{n}2}
6439 Convert operand 1 of mode @var{m} to mode @var{n} and store in
6440 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
6441 could be unsigned integer to fixed-point, or
6442 fixed-point to unsigned integer.
6443 When overflows or underflows happen, the results are undefined.
6445 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
6446 @item @samp{satfractuns@var{m}@var{n}2}
6447 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
6448 @var{n} and store in operand 0 (which has mode @var{n}).
6449 When overflows or underflows happen, the instruction saturates the
6450 results to the maximum or the minimum.
6452 @cindex @code{extv@var{m}} instruction pattern
6453 @item @samp{extv@var{m}}
6454 Extract a bit-field from register operand 1, sign-extend it, and store
6455 it in operand 0. Operand 2 specifies the width of the field in bits
6456 and operand 3 the starting bit, which counts from the most significant
6457 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
6460 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
6461 target-specific mode.
6463 @cindex @code{extvmisalign@var{m}} instruction pattern
6464 @item @samp{extvmisalign@var{m}}
6465 Extract a bit-field from memory operand 1, sign extend it, and store
6466 it in operand 0. Operand 2 specifies the width in bits and operand 3
6467 the starting bit. The starting bit is always somewhere in the first byte of
6468 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6469 is true and from the least significant bit otherwise.
6471 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
6472 Operands 2 and 3 have a target-specific mode.
6474 The instruction must not read beyond the last byte of the bit-field.
6476 @cindex @code{extzv@var{m}} instruction pattern
6477 @item @samp{extzv@var{m}}
6478 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
6480 @cindex @code{extzvmisalign@var{m}} instruction pattern
6481 @item @samp{extzvmisalign@var{m}}
6482 Like @samp{extvmisalign@var{m}} except that the bit-field value is
6485 @cindex @code{insv@var{m}} instruction pattern
6486 @item @samp{insv@var{m}}
6487 Insert operand 3 into a bit-field of register operand 0. Operand 1
6488 specifies the width of the field in bits and operand 2 the starting bit,
6489 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6490 is true and from the least significant bit otherwise.
6492 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
6493 target-specific mode.
6495 @cindex @code{insvmisalign@var{m}} instruction pattern
6496 @item @samp{insvmisalign@var{m}}
6497 Insert operand 3 into a bit-field of memory operand 0. Operand 1
6498 specifies the width of the field in bits and operand 2 the starting bit.
6499 The starting bit is always somewhere in the first byte of operand 0;
6500 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
6501 is true and from the least significant bit otherwise.
6503 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
6504 Operands 1 and 2 have a target-specific mode.
6506 The instruction must not read or write beyond the last byte of the bit-field.
6508 @cindex @code{extv} instruction pattern
6510 Extract a bit-field from operand 1 (a register or memory operand), where
6511 operand 2 specifies the width in bits and operand 3 the starting bit,
6512 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
6513 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
6514 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
6515 be valid for @code{word_mode}.
6517 The RTL generation pass generates this instruction only with constants
6518 for operands 2 and 3 and the constant is never zero for operand 2.
6520 The bit-field value is sign-extended to a full word integer
6521 before it is stored in operand 0.
6523 This pattern is deprecated; please use @samp{extv@var{m}} and
6524 @code{extvmisalign@var{m}} instead.
6526 @cindex @code{extzv} instruction pattern
6528 Like @samp{extv} except that the bit-field value is zero-extended.
6530 This pattern is deprecated; please use @samp{extzv@var{m}} and
6531 @code{extzvmisalign@var{m}} instead.
6533 @cindex @code{insv} instruction pattern
6535 Store operand 3 (which must be valid for @code{word_mode}) into a
6536 bit-field in operand 0, where operand 1 specifies the width in bits and
6537 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
6538 @code{word_mode}; often @code{word_mode} is allowed only for registers.
6539 Operands 1 and 2 must be valid for @code{word_mode}.
6541 The RTL generation pass generates this instruction only with constants
6542 for operands 1 and 2 and the constant is never zero for operand 1.
6544 This pattern is deprecated; please use @samp{insv@var{m}} and
6545 @code{insvmisalign@var{m}} instead.
6547 @cindex @code{mov@var{mode}cc} instruction pattern
6548 @item @samp{mov@var{mode}cc}
6549 Conditionally move operand 2 or operand 3 into operand 0 according to the
6550 comparison in operand 1. If the comparison is true, operand 2 is moved
6551 into operand 0, otherwise operand 3 is moved.
6553 The mode of the operands being compared need not be the same as the operands
6554 being moved. Some machines, sparc64 for example, have instructions that
6555 conditionally move an integer value based on the floating point condition
6556 codes and vice versa.
6558 If the machine does not have conditional move instructions, do not
6559 define these patterns.
6561 @cindex @code{add@var{mode}cc} instruction pattern
6562 @item @samp{add@var{mode}cc}
6563 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
6564 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
6565 comparison in operand 1. If the comparison is false, operand 2 is moved into
6566 operand 0, otherwise (operand 2 + operand 3) is moved.
6568 @cindex @code{cond_add@var{mode}} instruction pattern
6569 @cindex @code{cond_sub@var{mode}} instruction pattern
6570 @cindex @code{cond_mul@var{mode}} instruction pattern
6571 @cindex @code{cond_div@var{mode}} instruction pattern
6572 @cindex @code{cond_udiv@var{mode}} instruction pattern
6573 @cindex @code{cond_mod@var{mode}} instruction pattern
6574 @cindex @code{cond_umod@var{mode}} instruction pattern
6575 @cindex @code{cond_and@var{mode}} instruction pattern
6576 @cindex @code{cond_ior@var{mode}} instruction pattern
6577 @cindex @code{cond_xor@var{mode}} instruction pattern
6578 @cindex @code{cond_smin@var{mode}} instruction pattern
6579 @cindex @code{cond_smax@var{mode}} instruction pattern
6580 @cindex @code{cond_umin@var{mode}} instruction pattern
6581 @cindex @code{cond_umax@var{mode}} instruction pattern
6582 @item @samp{cond_add@var{mode}}
6583 @itemx @samp{cond_sub@var{mode}}
6584 @itemx @samp{cond_mul@var{mode}}
6585 @itemx @samp{cond_div@var{mode}}
6586 @itemx @samp{cond_udiv@var{mode}}
6587 @itemx @samp{cond_mod@var{mode}}
6588 @itemx @samp{cond_umod@var{mode}}
6589 @itemx @samp{cond_and@var{mode}}
6590 @itemx @samp{cond_ior@var{mode}}
6591 @itemx @samp{cond_xor@var{mode}}
6592 @itemx @samp{cond_smin@var{mode}}
6593 @itemx @samp{cond_smax@var{mode}}
6594 @itemx @samp{cond_umin@var{mode}}
6595 @itemx @samp{cond_umax@var{mode}}
6596 When operand 1 is true, perform an operation on operands 2 and 3 and
6597 store the result in operand 0, otherwise store operand 4 in operand 0.
6598 The operation works elementwise if the operands are vectors.
6600 The scalar case is equivalent to:
6603 op0 = op1 ? op2 @var{op} op3 : op4;
6606 while the vector case is equivalent to:
6609 for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
6610 op0[i] = op1[i] ? op2[i] @var{op} op3[i] : op4[i];
6613 where, for example, @var{op} is @code{+} for @samp{cond_add@var{mode}}.
6615 When defined for floating-point modes, the contents of @samp{op3[i]}
6616 are not interpreted if @samp{op1[i]} is false, just like they would not
6617 be in a normal C @samp{?:} condition.
6619 Operands 0, 2, 3 and 4 all have mode @var{m}. Operand 1 is a scalar
6620 integer if @var{m} is scalar, otherwise it has the mode returned by
6621 @code{TARGET_VECTORIZE_GET_MASK_MODE}.
6623 @cindex @code{cond_fma@var{mode}} instruction pattern
6624 @cindex @code{cond_fms@var{mode}} instruction pattern
6625 @cindex @code{cond_fnma@var{mode}} instruction pattern
6626 @cindex @code{cond_fnms@var{mode}} instruction pattern
6627 @item @samp{cond_fma@var{mode}}
6628 @itemx @samp{cond_fms@var{mode}}
6629 @itemx @samp{cond_fnma@var{mode}}
6630 @itemx @samp{cond_fnms@var{mode}}
6631 Like @samp{cond_add@var{m}}, except that the conditional operation
6632 takes 3 operands rather than two. For example, the vector form of
6633 @samp{cond_fma@var{mode}} is equivalent to:
6636 for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
6637 op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i];
6640 @cindex @code{neg@var{mode}cc} instruction pattern
6641 @item @samp{neg@var{mode}cc}
6642 Similar to @samp{mov@var{mode}cc} but for conditional negation. Conditionally
6643 move the negation of operand 2 or the unchanged operand 3 into operand 0
6644 according to the comparison in operand 1. If the comparison is true, the negation
6645 of operand 2 is moved into operand 0, otherwise operand 3 is moved.
6647 @cindex @code{not@var{mode}cc} instruction pattern
6648 @item @samp{not@var{mode}cc}
6649 Similar to @samp{neg@var{mode}cc} but for conditional complement.
6650 Conditionally move the bitwise complement of operand 2 or the unchanged
6651 operand 3 into operand 0 according to the comparison in operand 1.
6652 If the comparison is true, the complement of operand 2 is moved into
6653 operand 0, otherwise operand 3 is moved.
6655 @cindex @code{cstore@var{mode}4} instruction pattern
6656 @item @samp{cstore@var{mode}4}
6657 Store zero or nonzero in operand 0 according to whether a comparison
6658 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
6659 are the first and second operand of the comparison, respectively.
6660 You specify the mode that operand 0 must have when you write the
6661 @code{match_operand} expression. The compiler automatically sees which
6662 mode you have used and supplies an operand of that mode.
6664 The value stored for a true condition must have 1 as its low bit, or
6665 else must be negative. Otherwise the instruction is not suitable and
6666 you should omit it from the machine description. You describe to the
6667 compiler exactly which value is stored by defining the macro
6668 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
6669 found that can be used for all the possible comparison operators, you
6670 should pick one and use a @code{define_expand} to map all results
6671 onto the one you chose.
6673 These operations may @code{FAIL}, but should do so only in relatively
6674 uncommon cases; if they would @code{FAIL} for common cases involving
6675 integer comparisons, it is best to restrict the predicates to not
6676 allow these operands. Likewise if a given comparison operator will
6677 always fail, independent of the operands (for floating-point modes, the
6678 @code{ordered_comparison_operator} predicate is often useful in this case).
6680 If this pattern is omitted, the compiler will generate a conditional
6681 branch---for example, it may copy a constant one to the target and branching
6682 around an assignment of zero to the target---or a libcall. If the predicate
6683 for operand 1 only rejects some operators, it will also try reordering the
6684 operands and/or inverting the result value (e.g.@: by an exclusive OR).
6685 These possibilities could be cheaper or equivalent to the instructions
6686 used for the @samp{cstore@var{mode}4} pattern followed by those required
6687 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
6688 case, you can and should make operand 1's predicate reject some operators
6689 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
6690 from the machine description.
6692 @cindex @code{cbranch@var{mode}4} instruction pattern
6693 @item @samp{cbranch@var{mode}4}
6694 Conditional branch instruction combined with a compare instruction.
6695 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
6696 first and second operands of the comparison, respectively. Operand 3
6697 is the @code{code_label} to jump to.
6699 @cindex @code{jump} instruction pattern
6701 A jump inside a function; an unconditional branch. Operand 0 is the
6702 @code{code_label} to jump to. This pattern name is mandatory on all
6705 @cindex @code{call} instruction pattern
6707 Subroutine call instruction returning no value. Operand 0 is the
6708 function to call; operand 1 is the number of bytes of arguments pushed
6709 as a @code{const_int}; operand 2 is the number of registers used as
6712 On most machines, operand 2 is not actually stored into the RTL
6713 pattern. It is supplied for the sake of some RISC machines which need
6714 to put this information into the assembler code; they can put it in
6715 the RTL instead of operand 1.
6717 Operand 0 should be a @code{mem} RTX whose address is the address of the
6718 function. Note, however, that this address can be a @code{symbol_ref}
6719 expression even if it would not be a legitimate memory address on the
6720 target machine. If it is also not a valid argument for a call
6721 instruction, the pattern for this operation should be a
6722 @code{define_expand} (@pxref{Expander Definitions}) that places the
6723 address into a register and uses that register in the call instruction.
6725 @cindex @code{call_value} instruction pattern
6726 @item @samp{call_value}
6727 Subroutine call instruction returning a value. Operand 0 is the hard
6728 register in which the value is returned. There are three more
6729 operands, the same as the three operands of the @samp{call}
6730 instruction (but with numbers increased by one).
6732 Subroutines that return @code{BLKmode} objects use the @samp{call}
6735 @cindex @code{call_pop} instruction pattern
6736 @cindex @code{call_value_pop} instruction pattern
6737 @item @samp{call_pop}, @samp{call_value_pop}
6738 Similar to @samp{call} and @samp{call_value}, except used if defined and
6739 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
6740 that contains both the function call and a @code{set} to indicate the
6741 adjustment made to the frame pointer.
6743 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
6744 patterns increases the number of functions for which the frame pointer
6745 can be eliminated, if desired.
6747 @cindex @code{untyped_call} instruction pattern
6748 @item @samp{untyped_call}
6749 Subroutine call instruction returning a value of any type. Operand 0 is
6750 the function to call; operand 1 is a memory location where the result of
6751 calling the function is to be stored; operand 2 is a @code{parallel}
6752 expression where each element is a @code{set} expression that indicates
6753 the saving of a function return value into the result block.
6755 This instruction pattern should be defined to support
6756 @code{__builtin_apply} on machines where special instructions are needed
6757 to call a subroutine with arbitrary arguments or to save the value
6758 returned. This instruction pattern is required on machines that have
6759 multiple registers that can hold a return value
6760 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
6762 @cindex @code{return} instruction pattern
6764 Subroutine return instruction. This instruction pattern name should be
6765 defined only if a single instruction can do all the work of returning
6768 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
6769 RTL generation phase. In this case it is to support machines where
6770 multiple instructions are usually needed to return from a function, but
6771 some class of functions only requires one instruction to implement a
6772 return. Normally, the applicable functions are those which do not need
6773 to save any registers or allocate stack space.
6775 It is valid for this pattern to expand to an instruction using
6776 @code{simple_return} if no epilogue is required.
6778 @cindex @code{simple_return} instruction pattern
6779 @item @samp{simple_return}
6780 Subroutine return instruction. This instruction pattern name should be
6781 defined only if a single instruction can do all the work of returning
6782 from a function on a path where no epilogue is required. This pattern
6783 is very similar to the @code{return} instruction pattern, but it is emitted
6784 only by the shrink-wrapping optimization on paths where the function
6785 prologue has not been executed, and a function return should occur without
6786 any of the effects of the epilogue. Additional uses may be introduced on
6787 paths where both the prologue and the epilogue have executed.
6789 @findex reload_completed
6790 @findex leaf_function_p
6791 For such machines, the condition specified in this pattern should only
6792 be true when @code{reload_completed} is nonzero and the function's
6793 epilogue would only be a single instruction. For machines with register
6794 windows, the routine @code{leaf_function_p} may be used to determine if
6795 a register window push is required.
6797 Machines that have conditional return instructions should define patterns
6803 (if_then_else (match_operator
6804 0 "comparison_operator"
6805 [(cc0) (const_int 0)])
6812 where @var{condition} would normally be the same condition specified on the
6813 named @samp{return} pattern.
6815 @cindex @code{untyped_return} instruction pattern
6816 @item @samp{untyped_return}
6817 Untyped subroutine return instruction. This instruction pattern should
6818 be defined to support @code{__builtin_return} on machines where special
6819 instructions are needed to return a value of any type.
6821 Operand 0 is a memory location where the result of calling a function
6822 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
6823 expression where each element is a @code{set} expression that indicates
6824 the restoring of a function return value from the result block.
6826 @cindex @code{nop} instruction pattern
6828 No-op instruction. This instruction pattern name should always be defined
6829 to output a no-op in assembler code. @code{(const_int 0)} will do as an
6832 @cindex @code{indirect_jump} instruction pattern
6833 @item @samp{indirect_jump}
6834 An instruction to jump to an address which is operand zero.
6835 This pattern name is mandatory on all machines.
6837 @cindex @code{casesi} instruction pattern
6839 Instruction to jump through a dispatch table, including bounds checking.
6840 This instruction takes five operands:
6844 The index to dispatch on, which has mode @code{SImode}.
6847 The lower bound for indices in the table, an integer constant.
6850 The total range of indices in the table---the largest index
6851 minus the smallest one (both inclusive).
6854 A label that precedes the table itself.
6857 A label to jump to if the index has a value outside the bounds.
6860 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
6861 @code{jump_table_data}. The number of elements in the table is one plus the
6862 difference between the upper bound and the lower bound.
6864 @cindex @code{tablejump} instruction pattern
6865 @item @samp{tablejump}
6866 Instruction to jump to a variable address. This is a low-level
6867 capability which can be used to implement a dispatch table when there
6868 is no @samp{casesi} pattern.
6870 This pattern requires two operands: the address or offset, and a label
6871 which should immediately precede the jump table. If the macro
6872 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
6873 operand is an offset which counts from the address of the table; otherwise,
6874 it is an absolute address to jump to. In either case, the first operand has
6877 The @samp{tablejump} insn is always the last insn before the jump
6878 table it uses. Its assembler code normally has no need to use the
6879 second operand, but you should incorporate it in the RTL pattern so
6880 that the jump optimizer will not delete the table as unreachable code.
6883 @cindex @code{doloop_end} instruction pattern
6884 @item @samp{doloop_end}
6885 Conditional branch instruction that decrements a register and
6886 jumps if the register is nonzero. Operand 0 is the register to
6887 decrement and test; operand 1 is the label to jump to if the
6888 register is nonzero.
6889 @xref{Looping Patterns}.
6891 This optional instruction pattern should be defined for machines with
6892 low-overhead looping instructions as the loop optimizer will try to
6893 modify suitable loops to utilize it. The target hook
6894 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
6895 low-overhead loops can be used.
6897 @cindex @code{doloop_begin} instruction pattern
6898 @item @samp{doloop_begin}
6899 Companion instruction to @code{doloop_end} required for machines that
6900 need to perform some initialization, such as loading a special counter
6901 register. Operand 1 is the associated @code{doloop_end} pattern and
6902 operand 0 is the register that it decrements.
6904 If initialization insns do not always need to be emitted, use a
6905 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
6907 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
6908 @item @samp{canonicalize_funcptr_for_compare}
6909 Canonicalize the function pointer in operand 1 and store the result
6912 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
6913 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
6914 and also has mode @code{Pmode}.
6916 Canonicalization of a function pointer usually involves computing
6917 the address of the function which would be called if the function
6918 pointer were used in an indirect call.
6920 Only define this pattern if function pointers on the target machine
6921 can have different values but still call the same function when
6922 used in an indirect call.
6924 @cindex @code{save_stack_block} instruction pattern
6925 @cindex @code{save_stack_function} instruction pattern
6926 @cindex @code{save_stack_nonlocal} instruction pattern
6927 @cindex @code{restore_stack_block} instruction pattern
6928 @cindex @code{restore_stack_function} instruction pattern
6929 @cindex @code{restore_stack_nonlocal} instruction pattern
6930 @item @samp{save_stack_block}
6931 @itemx @samp{save_stack_function}
6932 @itemx @samp{save_stack_nonlocal}
6933 @itemx @samp{restore_stack_block}
6934 @itemx @samp{restore_stack_function}
6935 @itemx @samp{restore_stack_nonlocal}
6936 Most machines save and restore the stack pointer by copying it to or
6937 from an object of mode @code{Pmode}. Do not define these patterns on
6940 Some machines require special handling for stack pointer saves and
6941 restores. On those machines, define the patterns corresponding to the
6942 non-standard cases by using a @code{define_expand} (@pxref{Expander
6943 Definitions}) that produces the required insns. The three types of
6944 saves and restores are:
6948 @samp{save_stack_block} saves the stack pointer at the start of a block
6949 that allocates a variable-sized object, and @samp{restore_stack_block}
6950 restores the stack pointer when the block is exited.
6953 @samp{save_stack_function} and @samp{restore_stack_function} do a
6954 similar job for the outermost block of a function and are used when the
6955 function allocates variable-sized objects or calls @code{alloca}. Only
6956 the epilogue uses the restored stack pointer, allowing a simpler save or
6957 restore sequence on some machines.
6960 @samp{save_stack_nonlocal} is used in functions that contain labels
6961 branched to by nested functions. It saves the stack pointer in such a
6962 way that the inner function can use @samp{restore_stack_nonlocal} to
6963 restore the stack pointer. The compiler generates code to restore the
6964 frame and argument pointer registers, but some machines require saving
6965 and restoring additional data such as register window information or
6966 stack backchains. Place insns in these patterns to save and restore any
6970 When saving the stack pointer, operand 0 is the save area and operand 1
6971 is the stack pointer. The mode used to allocate the save area defaults
6972 to @code{Pmode} but you can override that choice by defining the
6973 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
6974 specify an integral mode, or @code{VOIDmode} if no save area is needed
6975 for a particular type of save (either because no save is needed or
6976 because a machine-specific save area can be used). Operand 0 is the
6977 stack pointer and operand 1 is the save area for restore operations. If
6978 @samp{save_stack_block} is defined, operand 0 must not be
6979 @code{VOIDmode} since these saves can be arbitrarily nested.
6981 A save area is a @code{mem} that is at a constant offset from
6982 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
6983 nonlocal gotos and a @code{reg} in the other two cases.
6985 @cindex @code{allocate_stack} instruction pattern
6986 @item @samp{allocate_stack}
6987 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
6988 the stack pointer to create space for dynamically allocated data.
6990 Store the resultant pointer to this space into operand 0. If you
6991 are allocating space from the main stack, do this by emitting a
6992 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
6993 If you are allocating the space elsewhere, generate code to copy the
6994 location of the space to operand 0. In the latter case, you must
6995 ensure this space gets freed when the corresponding space on the main
6998 Do not define this pattern if all that must be done is the subtraction.
6999 Some machines require other operations such as stack probes or
7000 maintaining the back chain. Define this pattern to emit those
7001 operations in addition to updating the stack pointer.
7003 @cindex @code{check_stack} instruction pattern
7004 @item @samp{check_stack}
7005 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
7006 probing the stack, define this pattern to perform the needed check and signal
7007 an error if the stack has overflowed. The single operand is the address in
7008 the stack farthest from the current stack pointer that you need to validate.
7009 Normally, on platforms where this pattern is needed, you would obtain the
7010 stack limit from a global or thread-specific variable or register.
7012 @cindex @code{probe_stack_address} instruction pattern
7013 @item @samp{probe_stack_address}
7014 If stack checking (@pxref{Stack Checking}) can be done on your system by
7015 probing the stack but without the need to actually access it, define this
7016 pattern and signal an error if the stack has overflowed. The single operand
7017 is the memory address in the stack that needs to be probed.
7019 @cindex @code{probe_stack} instruction pattern
7020 @item @samp{probe_stack}
7021 If stack checking (@pxref{Stack Checking}) can be done on your system by
7022 probing the stack but doing it with a ``store zero'' instruction is not valid
7023 or optimal, define this pattern to do the probing differently and signal an
7024 error if the stack has overflowed. The single operand is the memory reference
7025 in the stack that needs to be probed.
7027 @cindex @code{nonlocal_goto} instruction pattern
7028 @item @samp{nonlocal_goto}
7029 Emit code to generate a non-local goto, e.g., a jump from one function
7030 to a label in an outer function. This pattern has four arguments,
7031 each representing a value to be used in the jump. The first
7032 argument is to be loaded into the frame pointer, the second is
7033 the address to branch to (code to dispatch to the actual label),
7034 the third is the address of a location where the stack is saved,
7035 and the last is the address of the label, to be placed in the
7036 location for the incoming static chain.
7038 On most machines you need not define this pattern, since GCC will
7039 already generate the correct code, which is to load the frame pointer
7040 and static chain, restore the stack (using the
7041 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
7042 to the dispatcher. You need only define this pattern if this code will
7043 not work on your machine.
7045 @cindex @code{nonlocal_goto_receiver} instruction pattern
7046 @item @samp{nonlocal_goto_receiver}
7047 This pattern, if defined, contains code needed at the target of a
7048 nonlocal goto after the code already generated by GCC@. You will not
7049 normally need to define this pattern. A typical reason why you might
7050 need this pattern is if some value, such as a pointer to a global table,
7051 must be restored when the frame pointer is restored. Note that a nonlocal
7052 goto only occurs within a unit-of-translation, so a global table pointer
7053 that is shared by all functions of a given module need not be restored.
7054 There are no arguments.
7056 @cindex @code{exception_receiver} instruction pattern
7057 @item @samp{exception_receiver}
7058 This pattern, if defined, contains code needed at the site of an
7059 exception handler that isn't needed at the site of a nonlocal goto. You
7060 will not normally need to define this pattern. A typical reason why you
7061 might need this pattern is if some value, such as a pointer to a global
7062 table, must be restored after control flow is branched to the handler of
7063 an exception. There are no arguments.
7065 @cindex @code{builtin_setjmp_setup} instruction pattern
7066 @item @samp{builtin_setjmp_setup}
7067 This pattern, if defined, contains additional code needed to initialize
7068 the @code{jmp_buf}. You will not normally need to define this pattern.
7069 A typical reason why you might need this pattern is if some value, such
7070 as a pointer to a global table, must be restored. Though it is
7071 preferred that the pointer value be recalculated if possible (given the
7072 address of a label for instance). The single argument is a pointer to
7073 the @code{jmp_buf}. Note that the buffer is five words long and that
7074 the first three are normally used by the generic mechanism.
7076 @cindex @code{builtin_setjmp_receiver} instruction pattern
7077 @item @samp{builtin_setjmp_receiver}
7078 This pattern, if defined, contains code needed at the site of a
7079 built-in setjmp that isn't needed at the site of a nonlocal goto. You
7080 will not normally need to define this pattern. A typical reason why you
7081 might need this pattern is if some value, such as a pointer to a global
7082 table, must be restored. It takes one argument, which is the label
7083 to which builtin_longjmp transferred control; this pattern may be emitted
7084 at a small offset from that label.
7086 @cindex @code{builtin_longjmp} instruction pattern
7087 @item @samp{builtin_longjmp}
7088 This pattern, if defined, performs the entire action of the longjmp.
7089 You will not normally need to define this pattern unless you also define
7090 @code{builtin_setjmp_setup}. The single argument is a pointer to the
7093 @cindex @code{eh_return} instruction pattern
7094 @item @samp{eh_return}
7095 This pattern, if defined, affects the way @code{__builtin_eh_return},
7096 and thence the call frame exception handling library routines, are
7097 built. It is intended to handle non-trivial actions needed along
7098 the abnormal return path.
7100 The address of the exception handler to which the function should return
7101 is passed as operand to this pattern. It will normally need to copied by
7102 the pattern to some special register or memory location.
7103 If the pattern needs to determine the location of the target call
7104 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
7105 if defined; it will have already been assigned.
7107 If this pattern is not defined, the default action will be to simply
7108 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
7109 that macro or this pattern needs to be defined if call frame exception
7110 handling is to be used.
7112 @cindex @code{prologue} instruction pattern
7113 @anchor{prologue instruction pattern}
7114 @item @samp{prologue}
7115 This pattern, if defined, emits RTL for entry to a function. The function
7116 entry is responsible for setting up the stack frame, initializing the frame
7117 pointer register, saving callee saved registers, etc.
7119 Using a prologue pattern is generally preferred over defining
7120 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
7122 The @code{prologue} pattern is particularly useful for targets which perform
7123 instruction scheduling.
7125 @cindex @code{window_save} instruction pattern
7126 @anchor{window_save instruction pattern}
7127 @item @samp{window_save}
7128 This pattern, if defined, emits RTL for a register window save. It should
7129 be defined if the target machine has register windows but the window events
7130 are decoupled from calls to subroutines. The canonical example is the SPARC
7133 @cindex @code{epilogue} instruction pattern
7134 @anchor{epilogue instruction pattern}
7135 @item @samp{epilogue}
7136 This pattern emits RTL for exit from a function. The function
7137 exit is responsible for deallocating the stack frame, restoring callee saved
7138 registers and emitting the return instruction.
7140 Using an epilogue pattern is generally preferred over defining
7141 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
7143 The @code{epilogue} pattern is particularly useful for targets which perform
7144 instruction scheduling or which have delay slots for their return instruction.
7146 @cindex @code{sibcall_epilogue} instruction pattern
7147 @item @samp{sibcall_epilogue}
7148 This pattern, if defined, emits RTL for exit from a function without the final
7149 branch back to the calling function. This pattern will be emitted before any
7150 sibling call (aka tail call) sites.
7152 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
7153 parameter passing or any stack slots for arguments passed to the current
7156 @cindex @code{trap} instruction pattern
7158 This pattern, if defined, signals an error, typically by causing some
7159 kind of signal to be raised.
7161 @cindex @code{ctrap@var{MM}4} instruction pattern
7162 @item @samp{ctrap@var{MM}4}
7163 Conditional trap instruction. Operand 0 is a piece of RTL which
7164 performs a comparison, and operands 1 and 2 are the arms of the
7165 comparison. Operand 3 is the trap code, an integer.
7167 A typical @code{ctrap} pattern looks like
7170 (define_insn "ctrapsi4"
7171 [(trap_if (match_operator 0 "trap_operator"
7172 [(match_operand 1 "register_operand")
7173 (match_operand 2 "immediate_operand")])
7174 (match_operand 3 "const_int_operand" "i"))]
7179 @cindex @code{prefetch} instruction pattern
7180 @item @samp{prefetch}
7181 This pattern, if defined, emits code for a non-faulting data prefetch
7182 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
7183 is a constant 1 if the prefetch is preparing for a write to the memory
7184 address, or a constant 0 otherwise. Operand 2 is the expected degree of
7185 temporal locality of the data and is a value between 0 and 3, inclusive; 0
7186 means that the data has no temporal locality, so it need not be left in the
7187 cache after the access; 3 means that the data has a high degree of temporal
7188 locality and should be left in all levels of cache possible; 1 and 2 mean,
7189 respectively, a low or moderate degree of temporal locality.
7191 Targets that do not support write prefetches or locality hints can ignore
7192 the values of operands 1 and 2.
7194 @cindex @code{blockage} instruction pattern
7195 @item @samp{blockage}
7196 This pattern defines a pseudo insn that prevents the instruction
7197 scheduler and other passes from moving instructions and using register
7198 equivalences across the boundary defined by the blockage insn.
7199 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
7201 @cindex @code{memory_blockage} instruction pattern
7202 @item @samp{memory_blockage}
7203 This pattern, if defined, represents a compiler memory barrier, and will be
7204 placed at points across which RTL passes may not propagate memory accesses.
7205 This instruction needs to read and write volatile BLKmode memory. It does
7206 not need to generate any machine instruction. If this pattern is not defined,
7207 the compiler falls back to emitting an instruction corresponding
7208 to @code{asm volatile ("" ::: "memory")}.
7210 @cindex @code{memory_barrier} instruction pattern
7211 @item @samp{memory_barrier}
7212 If the target memory model is not fully synchronous, then this pattern
7213 should be defined to an instruction that orders both loads and stores
7214 before the instruction with respect to loads and stores after the instruction.
7215 This pattern has no operands.
7217 @cindex @code{speculation_barrier} instruction pattern
7218 @item @samp{speculation_barrier}
7219 If the target can support speculative execution, then this pattern should
7220 be defined to an instruction that will block subsequent execution until
7221 any prior speculation conditions has been resolved. The pattern must also
7222 ensure that the compiler cannot move memory operations past the barrier,
7223 so it needs to be an UNSPEC_VOLATILE pattern. The pattern has no
7226 If this pattern is not defined then the default expansion of
7227 @code{__builtin_speculation_safe_value} will emit a warning. You can
7228 suppress this warning by defining this pattern with a final condition
7229 of @code{0} (zero), which tells the compiler that a speculation
7230 barrier is not needed for this target.
7232 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
7233 @item @samp{sync_compare_and_swap@var{mode}}
7234 This pattern, if defined, emits code for an atomic compare-and-swap
7235 operation. Operand 1 is the memory on which the atomic operation is
7236 performed. Operand 2 is the ``old'' value to be compared against the
7237 current contents of the memory location. Operand 3 is the ``new'' value
7238 to store in the memory if the compare succeeds. Operand 0 is the result
7239 of the operation; it should contain the contents of the memory
7240 before the operation. If the compare succeeds, this should obviously be
7241 a copy of operand 2.
7243 This pattern must show that both operand 0 and operand 1 are modified.
7245 This pattern must issue any memory barrier instructions such that all
7246 memory operations before the atomic operation occur before the atomic
7247 operation and all memory operations after the atomic operation occur
7248 after the atomic operation.
7250 For targets where the success or failure of the compare-and-swap
7251 operation is available via the status flags, it is possible to
7252 avoid a separate compare operation and issue the subsequent
7253 branch or store-flag operation immediately after the compare-and-swap.
7254 To this end, GCC will look for a @code{MODE_CC} set in the
7255 output of @code{sync_compare_and_swap@var{mode}}; if the machine
7256 description includes such a set, the target should also define special
7257 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
7258 be able to take the destination of the @code{MODE_CC} set and pass it
7259 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
7260 operand of the comparison (the second will be @code{(const_int 0)}).
7262 For targets where the operating system may provide support for this
7263 operation via library calls, the @code{sync_compare_and_swap_optab}
7264 may be initialized to a function with the same interface as the
7265 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
7266 set of @var{__sync} builtins are supported via library calls, the
7267 target can initialize all of the optabs at once with
7268 @code{init_sync_libfuncs}.
7269 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
7270 assumed that these library calls do @emph{not} use any kind of
7271 interruptable locking.
7273 @cindex @code{sync_add@var{mode}} instruction pattern
7274 @cindex @code{sync_sub@var{mode}} instruction pattern
7275 @cindex @code{sync_ior@var{mode}} instruction pattern
7276 @cindex @code{sync_and@var{mode}} instruction pattern
7277 @cindex @code{sync_xor@var{mode}} instruction pattern
7278 @cindex @code{sync_nand@var{mode}} instruction pattern
7279 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
7280 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
7281 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
7282 These patterns emit code for an atomic operation on memory.
7283 Operand 0 is the memory on which the atomic operation is performed.
7284 Operand 1 is the second operand to the binary operator.
7286 This pattern must issue any memory barrier instructions such that all
7287 memory operations before the atomic operation occur before the atomic
7288 operation and all memory operations after the atomic operation occur
7289 after the atomic operation.
7291 If these patterns are not defined, the operation will be constructed
7292 from a compare-and-swap operation, if defined.
7294 @cindex @code{sync_old_add@var{mode}} instruction pattern
7295 @cindex @code{sync_old_sub@var{mode}} instruction pattern
7296 @cindex @code{sync_old_ior@var{mode}} instruction pattern
7297 @cindex @code{sync_old_and@var{mode}} instruction pattern
7298 @cindex @code{sync_old_xor@var{mode}} instruction pattern
7299 @cindex @code{sync_old_nand@var{mode}} instruction pattern
7300 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
7301 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
7302 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
7303 These patterns emit code for an atomic operation on memory,
7304 and return the value that the memory contained before the operation.
7305 Operand 0 is the result value, operand 1 is the memory on which the
7306 atomic operation is performed, and operand 2 is the second operand
7307 to the binary operator.
7309 This pattern must issue any memory barrier instructions such that all
7310 memory operations before the atomic operation occur before the atomic
7311 operation and all memory operations after the atomic operation occur
7312 after the atomic operation.
7314 If these patterns are not defined, the operation will be constructed
7315 from a compare-and-swap operation, if defined.
7317 @cindex @code{sync_new_add@var{mode}} instruction pattern
7318 @cindex @code{sync_new_sub@var{mode}} instruction pattern
7319 @cindex @code{sync_new_ior@var{mode}} instruction pattern
7320 @cindex @code{sync_new_and@var{mode}} instruction pattern
7321 @cindex @code{sync_new_xor@var{mode}} instruction pattern
7322 @cindex @code{sync_new_nand@var{mode}} instruction pattern
7323 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
7324 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
7325 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
7326 These patterns are like their @code{sync_old_@var{op}} counterparts,
7327 except that they return the value that exists in the memory location
7328 after the operation, rather than before the operation.
7330 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
7331 @item @samp{sync_lock_test_and_set@var{mode}}
7332 This pattern takes two forms, based on the capabilities of the target.
7333 In either case, operand 0 is the result of the operand, operand 1 is
7334 the memory on which the atomic operation is performed, and operand 2
7335 is the value to set in the lock.
7337 In the ideal case, this operation is an atomic exchange operation, in
7338 which the previous value in memory operand is copied into the result
7339 operand, and the value operand is stored in the memory operand.
7341 For less capable targets, any value operand that is not the constant 1
7342 should be rejected with @code{FAIL}. In this case the target may use
7343 an atomic test-and-set bit operation. The result operand should contain
7344 1 if the bit was previously set and 0 if the bit was previously clear.
7345 The true contents of the memory operand are implementation defined.
7347 This pattern must issue any memory barrier instructions such that the
7348 pattern as a whole acts as an acquire barrier, that is all memory
7349 operations after the pattern do not occur until the lock is acquired.
7351 If this pattern is not defined, the operation will be constructed from
7352 a compare-and-swap operation, if defined.
7354 @cindex @code{sync_lock_release@var{mode}} instruction pattern
7355 @item @samp{sync_lock_release@var{mode}}
7356 This pattern, if defined, releases a lock set by
7357 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
7358 that contains the lock; operand 1 is the value to store in the lock.
7360 If the target doesn't implement full semantics for
7361 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
7362 the constant 0 should be rejected with @code{FAIL}, and the true contents
7363 of the memory operand are implementation defined.
7365 This pattern must issue any memory barrier instructions such that the
7366 pattern as a whole acts as a release barrier, that is the lock is
7367 released only after all previous memory operations have completed.
7369 If this pattern is not defined, then a @code{memory_barrier} pattern
7370 will be emitted, followed by a store of the value to the memory operand.
7372 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
7373 @item @samp{atomic_compare_and_swap@var{mode}}
7374 This pattern, if defined, emits code for an atomic compare-and-swap
7375 operation with memory model semantics. Operand 2 is the memory on which
7376 the atomic operation is performed. Operand 0 is an output operand which
7377 is set to true or false based on whether the operation succeeded. Operand
7378 1 is an output operand which is set to the contents of the memory before
7379 the operation was attempted. Operand 3 is the value that is expected to
7380 be in memory. Operand 4 is the value to put in memory if the expected
7381 value is found there. Operand 5 is set to 1 if this compare and swap is to
7382 be treated as a weak operation. Operand 6 is the memory model to be used
7383 if the operation is a success. Operand 7 is the memory model to be used
7384 if the operation fails.
7386 If memory referred to in operand 2 contains the value in operand 3, then
7387 operand 4 is stored in memory pointed to by operand 2 and fencing based on
7388 the memory model in operand 6 is issued.
7390 If memory referred to in operand 2 does not contain the value in operand 3,
7391 then fencing based on the memory model in operand 7 is issued.
7393 If a target does not support weak compare-and-swap operations, or the port
7394 elects not to implement weak operations, the argument in operand 5 can be
7395 ignored. Note a strong implementation must be provided.
7397 If this pattern is not provided, the @code{__atomic_compare_exchange}
7398 built-in functions will utilize the legacy @code{sync_compare_and_swap}
7399 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
7401 @cindex @code{atomic_load@var{mode}} instruction pattern
7402 @item @samp{atomic_load@var{mode}}
7403 This pattern implements an atomic load operation with memory model
7404 semantics. Operand 1 is the memory address being loaded from. Operand 0
7405 is the result of the load. Operand 2 is the memory model to be used for
7408 If not present, the @code{__atomic_load} built-in function will either
7409 resort to a normal load with memory barriers, or a compare-and-swap
7410 operation if a normal load would not be atomic.
7412 @cindex @code{atomic_store@var{mode}} instruction pattern
7413 @item @samp{atomic_store@var{mode}}
7414 This pattern implements an atomic store operation with memory model
7415 semantics. Operand 0 is the memory address being stored to. Operand 1
7416 is the value to be written. Operand 2 is the memory model to be used for
7419 If not present, the @code{__atomic_store} built-in function will attempt to
7420 perform a normal store and surround it with any required memory fences. If
7421 the store would not be atomic, then an @code{__atomic_exchange} is
7422 attempted with the result being ignored.
7424 @cindex @code{atomic_exchange@var{mode}} instruction pattern
7425 @item @samp{atomic_exchange@var{mode}}
7426 This pattern implements an atomic exchange operation with memory model
7427 semantics. Operand 1 is the memory location the operation is performed on.
7428 Operand 0 is an output operand which is set to the original value contained
7429 in the memory pointed to by operand 1. Operand 2 is the value to be
7430 stored. Operand 3 is the memory model to be used.
7432 If this pattern is not present, the built-in function
7433 @code{__atomic_exchange} will attempt to preform the operation with a
7434 compare and swap loop.
7436 @cindex @code{atomic_add@var{mode}} instruction pattern
7437 @cindex @code{atomic_sub@var{mode}} instruction pattern
7438 @cindex @code{atomic_or@var{mode}} instruction pattern
7439 @cindex @code{atomic_and@var{mode}} instruction pattern
7440 @cindex @code{atomic_xor@var{mode}} instruction pattern
7441 @cindex @code{atomic_nand@var{mode}} instruction pattern
7442 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
7443 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
7444 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
7445 These patterns emit code for an atomic operation on memory with memory
7446 model semantics. Operand 0 is the memory on which the atomic operation is
7447 performed. Operand 1 is the second operand to the binary operator.
7448 Operand 2 is the memory model to be used by the operation.
7450 If these patterns are not defined, attempts will be made to use legacy
7451 @code{sync} patterns, or equivalent patterns which return a result. If
7452 none of these are available a compare-and-swap loop will be used.
7454 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
7455 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
7456 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
7457 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
7458 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
7459 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
7460 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
7461 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
7462 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
7463 These patterns emit code for an atomic operation on memory with memory
7464 model semantics, and return the original value. Operand 0 is an output
7465 operand which contains the value of the memory location before the
7466 operation was performed. Operand 1 is the memory on which the atomic
7467 operation is performed. Operand 2 is the second operand to the binary
7468 operator. Operand 3 is the memory model to be used by the operation.
7470 If these patterns are not defined, attempts will be made to use legacy
7471 @code{sync} patterns. If none of these are available a compare-and-swap
7474 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
7475 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
7476 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
7477 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
7478 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
7479 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
7480 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
7481 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
7482 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
7483 These patterns emit code for an atomic operation on memory with memory
7484 model semantics and return the result after the operation is performed.
7485 Operand 0 is an output operand which contains the value after the
7486 operation. Operand 1 is the memory on which the atomic operation is
7487 performed. Operand 2 is the second operand to the binary operator.
7488 Operand 3 is the memory model to be used by the operation.
7490 If these patterns are not defined, attempts will be made to use legacy
7491 @code{sync} patterns, or equivalent patterns which return the result before
7492 the operation followed by the arithmetic operation required to produce the
7493 result. If none of these are available a compare-and-swap loop will be
7496 @cindex @code{atomic_test_and_set} instruction pattern
7497 @item @samp{atomic_test_and_set}
7498 This pattern emits code for @code{__builtin_atomic_test_and_set}.
7499 Operand 0 is an output operand which is set to true if the previous
7500 previous contents of the byte was "set", and false otherwise. Operand 1
7501 is the @code{QImode} memory to be modified. Operand 2 is the memory
7504 The specific value that defines "set" is implementation defined, and
7505 is normally based on what is performed by the native atomic test and set
7508 @cindex @code{atomic_bit_test_and_set@var{mode}} instruction pattern
7509 @cindex @code{atomic_bit_test_and_complement@var{mode}} instruction pattern
7510 @cindex @code{atomic_bit_test_and_reset@var{mode}} instruction pattern
7511 @item @samp{atomic_bit_test_and_set@var{mode}}
7512 @itemx @samp{atomic_bit_test_and_complement@var{mode}}
7513 @itemx @samp{atomic_bit_test_and_reset@var{mode}}
7514 These patterns emit code for an atomic bitwise operation on memory with memory
7515 model semantics, and return the original value of the specified bit.
7516 Operand 0 is an output operand which contains the value of the specified bit
7517 from the memory location before the operation was performed. Operand 1 is the
7518 memory on which the atomic operation is performed. Operand 2 is the bit within
7519 the operand, starting with least significant bit. Operand 3 is the memory model
7520 to be used by the operation. Operand 4 is a flag - it is @code{const1_rtx}
7521 if operand 0 should contain the original value of the specified bit in the
7522 least significant bit of the operand, and @code{const0_rtx} if the bit should
7523 be in its original position in the operand.
7524 @code{atomic_bit_test_and_set@var{mode}} atomically sets the specified bit after
7525 remembering its original value, @code{atomic_bit_test_and_complement@var{mode}}
7526 inverts the specified bit and @code{atomic_bit_test_and_reset@var{mode}} clears
7529 If these patterns are not defined, attempts will be made to use
7530 @code{atomic_fetch_or@var{mode}}, @code{atomic_fetch_xor@var{mode}} or
7531 @code{atomic_fetch_and@var{mode}} instruction patterns, or their @code{sync}
7532 counterparts. If none of these are available a compare-and-swap
7535 @cindex @code{mem_thread_fence} instruction pattern
7536 @item @samp{mem_thread_fence}
7537 This pattern emits code required to implement a thread fence with
7538 memory model semantics. Operand 0 is the memory model to be used.
7540 For the @code{__ATOMIC_RELAXED} model no instructions need to be issued
7541 and this expansion is not invoked.
7543 The compiler always emits a compiler memory barrier regardless of what
7544 expanding this pattern produced.
7546 If this pattern is not defined, the compiler falls back to expanding the
7547 @code{memory_barrier} pattern, then to emitting @code{__sync_synchronize}
7548 library call, and finally to just placing a compiler memory barrier.
7550 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
7551 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
7552 @item @samp{get_thread_pointer@var{mode}}
7553 @itemx @samp{set_thread_pointer@var{mode}}
7554 These patterns emit code that reads/sets the TLS thread pointer. Currently,
7555 these are only needed if the target needs to support the
7556 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
7559 The get/set patterns have a single output/input operand respectively,
7560 with @var{mode} intended to be @code{Pmode}.
7562 @cindex @code{stack_protect_combined_set} instruction pattern
7563 @item @samp{stack_protect_combined_set}
7564 This pattern, if defined, moves a @code{ptr_mode} value from an address
7565 whose declaration RTX is given in operand 1 to the memory in operand 0
7566 without leaving the value in a register afterward. If several
7567 instructions are needed by the target to perform the operation (eg. to
7568 load the address from a GOT entry then load the @code{ptr_mode} value
7569 and finally store it), it is the backend's responsibility to ensure no
7570 intermediate result gets spilled. This is to avoid leaking the value
7571 some place that an attacker might use to rewrite the stack guard slot
7572 after having clobbered it.
7574 If this pattern is not defined, then the address declaration is
7575 expanded first in the standard way and a @code{stack_protect_set}
7576 pattern is then generated to move the value from that address to the
7577 address in operand 0.
7579 @cindex @code{stack_protect_set} instruction pattern
7580 @item @samp{stack_protect_set}
7581 This pattern, if defined, moves a @code{ptr_mode} value from the valid
7582 memory location in operand 1 to the memory in operand 0 without leaving
7583 the value in a register afterward. This is to avoid leaking the value
7584 some place that an attacker might use to rewrite the stack guard slot
7585 after having clobbered it.
7587 Note: on targets where the addressing modes do not allow to load
7588 directly from stack guard address, the address is expanded in a standard
7589 way first which could cause some spills.
7591 If this pattern is not defined, then a plain move pattern is generated.
7593 @cindex @code{stack_protect_combined_test} instruction pattern
7594 @item @samp{stack_protect_combined_test}
7595 This pattern, if defined, compares a @code{ptr_mode} value from an
7596 address whose declaration RTX is given in operand 1 with the memory in
7597 operand 0 without leaving the value in a register afterward and
7598 branches to operand 2 if the values were equal. If several
7599 instructions are needed by the target to perform the operation (eg. to
7600 load the address from a GOT entry then load the @code{ptr_mode} value
7601 and finally store it), it is the backend's responsibility to ensure no
7602 intermediate result gets spilled. This is to avoid leaking the value
7603 some place that an attacker might use to rewrite the stack guard slot
7604 after having clobbered it.
7606 If this pattern is not defined, then the address declaration is
7607 expanded first in the standard way and a @code{stack_protect_test}
7608 pattern is then generated to compare the value from that address to the
7609 value at the memory in operand 0.
7611 @cindex @code{stack_protect_test} instruction pattern
7612 @item @samp{stack_protect_test}
7613 This pattern, if defined, compares a @code{ptr_mode} value from the
7614 valid memory location in operand 1 with the memory in operand 0 without
7615 leaving the value in a register afterward and branches to operand 2 if
7616 the values were equal.
7618 If this pattern is not defined, then a plain compare pattern and
7619 conditional branch pattern is used.
7621 @cindex @code{clear_cache} instruction pattern
7622 @item @samp{clear_cache}
7623 This pattern, if defined, flushes the instruction cache for a region of
7624 memory. The region is bounded to by the Pmode pointers in operand 0
7625 inclusive and operand 1 exclusive.
7627 If this pattern is not defined, a call to the library function
7628 @code{__clear_cache} is used.
7633 @c Each of the following nodes are wrapped in separate
7634 @c "@ifset INTERNALS" to work around memory limits for the default
7635 @c configuration in older tetex distributions. Known to not work:
7636 @c tetex-1.0.7, known to work: tetex-2.0.2.
7638 @node Pattern Ordering
7639 @section When the Order of Patterns Matters
7640 @cindex Pattern Ordering
7641 @cindex Ordering of Patterns
7643 Sometimes an insn can match more than one instruction pattern. Then the
7644 pattern that appears first in the machine description is the one used.
7645 Therefore, more specific patterns (patterns that will match fewer things)
7646 and faster instructions (those that will produce better code when they
7647 do match) should usually go first in the description.
7649 In some cases the effect of ordering the patterns can be used to hide
7650 a pattern when it is not valid. For example, the 68000 has an
7651 instruction for converting a fullword to floating point and another
7652 for converting a byte to floating point. An instruction converting
7653 an integer to floating point could match either one. We put the
7654 pattern to convert the fullword first to make sure that one will
7655 be used rather than the other. (Otherwise a large integer might
7656 be generated as a single-byte immediate quantity, which would not work.)
7657 Instead of using this pattern ordering it would be possible to make the
7658 pattern for convert-a-byte smart enough to deal properly with any
7663 @node Dependent Patterns
7664 @section Interdependence of Patterns
7665 @cindex Dependent Patterns
7666 @cindex Interdependence of Patterns
7668 In some cases machines support instructions identical except for the
7669 machine mode of one or more operands. For example, there may be
7670 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
7674 (set (match_operand:SI 0 @dots{})
7675 (extend:SI (match_operand:HI 1 @dots{})))
7677 (set (match_operand:SI 0 @dots{})
7678 (extend:SI (match_operand:QI 1 @dots{})))
7682 Constant integers do not specify a machine mode, so an instruction to
7683 extend a constant value could match either pattern. The pattern it
7684 actually will match is the one that appears first in the file. For correct
7685 results, this must be the one for the widest possible mode (@code{HImode},
7686 here). If the pattern matches the @code{QImode} instruction, the results
7687 will be incorrect if the constant value does not actually fit that mode.
7689 Such instructions to extend constants are rarely generated because they are
7690 optimized away, but they do occasionally happen in nonoptimized
7693 If a constraint in a pattern allows a constant, the reload pass may
7694 replace a register with a constant permitted by the constraint in some
7695 cases. Similarly for memory references. Because of this substitution,
7696 you should not provide separate patterns for increment and decrement
7697 instructions. Instead, they should be generated from the same pattern
7698 that supports register-register add insns by examining the operands and
7699 generating the appropriate machine instruction.
7704 @section Defining Jump Instruction Patterns
7705 @cindex jump instruction patterns
7706 @cindex defining jump instruction patterns
7708 GCC does not assume anything about how the machine realizes jumps.
7709 The machine description should define a single pattern, usually
7710 a @code{define_expand}, which expands to all the required insns.
7712 Usually, this would be a comparison insn to set the condition code
7713 and a separate branch insn testing the condition code and branching
7714 or not according to its value. For many machines, however,
7715 separating compares and branches is limiting, which is why the
7716 more flexible approach with one @code{define_expand} is used in GCC.
7717 The machine description becomes clearer for architectures that
7718 have compare-and-branch instructions but no condition code. It also
7719 works better when different sets of comparison operators are supported
7720 by different kinds of conditional branches (e.g.@: integer vs.@:
7721 floating-point), or by conditional branches with respect to conditional stores.
7723 Two separate insns are always used if the machine description represents
7724 a condition code register using the legacy RTL expression @code{(cc0)},
7725 and on most machines that use a separate condition code register
7726 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
7727 fact, the set and use of the condition code must be separate and
7728 adjacent@footnote{@code{note} insns can separate them, though.}, thus
7729 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
7730 so that the comparison and branch insns could be located from each other
7731 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
7733 Even in this case having a single entry point for conditional branches
7734 is advantageous, because it handles equally well the case where a single
7735 comparison instruction records the results of both signed and unsigned
7736 comparison of the given operands (with the branch insns coming in distinct
7737 signed and unsigned flavors) as in the x86 or SPARC, and the case where
7738 there are distinct signed and unsigned compare instructions and only
7739 one set of conditional branch instructions as in the PowerPC.
7743 @node Looping Patterns
7744 @section Defining Looping Instruction Patterns
7745 @cindex looping instruction patterns
7746 @cindex defining looping instruction patterns
7748 Some machines have special jump instructions that can be utilized to
7749 make loops more efficient. A common example is the 68000 @samp{dbra}
7750 instruction which performs a decrement of a register and a branch if the
7751 result was greater than zero. Other machines, in particular digital
7752 signal processors (DSPs), have special block repeat instructions to
7753 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
7754 DSPs have a block repeat instruction that loads special registers to
7755 mark the top and end of a loop and to count the number of loop
7756 iterations. This avoids the need for fetching and executing a
7757 @samp{dbra}-like instruction and avoids pipeline stalls associated with
7760 GCC has two special named patterns to support low overhead looping.
7761 They are @samp{doloop_begin} and @samp{doloop_end}. These are emitted
7762 by the loop optimizer for certain well-behaved loops with a finite
7763 number of loop iterations using information collected during strength
7766 The @samp{doloop_end} pattern describes the actual looping instruction
7767 (or the implicit looping operation) and the @samp{doloop_begin} pattern
7768 is an optional companion pattern that can be used for initialization
7769 needed for some low-overhead looping instructions.
7771 Note that some machines require the actual looping instruction to be
7772 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
7773 the true RTL for a looping instruction at the top of the loop can cause
7774 problems with flow analysis. So instead, a dummy @code{doloop} insn is
7775 emitted at the end of the loop. The machine dependent reorg pass checks
7776 for the presence of this @code{doloop} insn and then searches back to
7777 the top of the loop, where it inserts the true looping insn (provided
7778 there are no instructions in the loop which would cause problems). Any
7779 additional labels can be emitted at this point. In addition, if the
7780 desired special iteration counter register was not allocated, this
7781 machine dependent reorg pass could emit a traditional compare and jump
7784 For the @samp{doloop_end} pattern, the loop optimizer allocates an
7785 additional pseudo register as an iteration counter. This pseudo
7786 register cannot be used within the loop (i.e., general induction
7787 variables cannot be derived from it), however, in many cases the loop
7788 induction variable may become redundant and removed by the flow pass.
7790 The @samp{doloop_end} pattern must have a specific structure to be
7791 handled correctly by GCC. The example below is taken (slightly
7792 simplified) from the PDP-11 target:
7796 (define_expand "doloop_end"
7797 [(parallel [(set (pc)
7799 (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m")
7801 (label_ref (match_operand 1 "" ""))
7804 (plus:HI (match_dup 0)
7808 if (GET_MODE (operands[0]) != HImode)
7812 (define_insn "doloop_end_insn"
7815 (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m")
7817 (label_ref (match_operand 1 "" ""))
7820 (plus:HI (match_dup 0)
7825 if (which_alternative == 0)
7826 return "sob %0,%l1";
7829 output_asm_insn ("dec %0", operands);
7835 The first part of the pattern describes the branch condition. GCC
7836 supports three cases for the way the target machine handles the loop
7839 @item Loop terminates when the loop register decrements to zero. This
7840 is represented by a @code{ne} comparison of the register (its old value)
7841 with constant 1 (as in the example above).
7842 @item Loop terminates when the loop register decrements to @minus{}1.
7843 This is represented by a @code{ne} comparison of the register with
7845 @item Loop terminates when the loop register decrements to a negative
7846 value. This is represented by a @code{ge} comparison of the register
7847 with constant zero. For this case, GCC will attach a @code{REG_NONNEG}
7848 note to the @code{doloop_end} insn if it can determine that the register
7849 will be non-negative.
7852 Since the @code{doloop_end} insn is a jump insn that also has an output,
7853 the reload pass does not handle the output operand. Therefore, the
7854 constraint must allow for that operand to be in memory rather than a
7855 register. In the example shown above, that is handled (in the
7856 @code{doloop_end_insn} pattern) by using a loop instruction sequence
7857 that can handle memory operands when the memory alternative appears.
7859 GCC does not check the mode of the loop register operand when generating
7860 the @code{doloop_end} pattern. If the pattern is only valid for some
7861 modes but not others, the pattern should be a @code{define_expand}
7862 pattern that checks the operand mode in the preparation code, and issues
7863 @code{FAIL} if an unsupported mode is found. The example above does
7864 this, since the machine instruction to be used only exists for
7867 If the @code{doloop_end} pattern is a @code{define_expand}, there must
7868 also be a @code{define_insn} or @code{define_insn_and_split} matching
7869 the generated pattern. Otherwise, the compiler will fail during loop
7874 @node Insn Canonicalizations
7875 @section Canonicalization of Instructions
7876 @cindex canonicalization of instructions
7877 @cindex insn canonicalization
7879 There are often cases where multiple RTL expressions could represent an
7880 operation performed by a single machine instruction. This situation is
7881 most commonly encountered with logical, branch, and multiply-accumulate
7882 instructions. In such cases, the compiler attempts to convert these
7883 multiple RTL expressions into a single canonical form to reduce the
7884 number of insn patterns required.
7886 In addition to algebraic simplifications, following canonicalizations
7891 For commutative and comparison operators, a constant is always made the
7892 second operand. If a machine only supports a constant as the second
7893 operand, only patterns that match a constant in the second operand need
7897 For associative operators, a sequence of operators will always chain
7898 to the left; for instance, only the left operand of an integer @code{plus}
7899 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
7900 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
7901 @code{umax} are associative when applied to integers, and sometimes to
7905 @cindex @code{neg}, canonicalization of
7906 @cindex @code{not}, canonicalization of
7907 @cindex @code{mult}, canonicalization of
7908 @cindex @code{plus}, canonicalization of
7909 @cindex @code{minus}, canonicalization of
7910 For these operators, if only one operand is a @code{neg}, @code{not},
7911 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
7915 In combinations of @code{neg}, @code{mult}, @code{plus}, and
7916 @code{minus}, the @code{neg} operations (if any) will be moved inside
7917 the operations as far as possible. For instance,
7918 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
7919 @code{(plus (mult (neg B) C) A)} is canonicalized as
7920 @code{(minus A (mult B C))}.
7922 @cindex @code{compare}, canonicalization of
7924 For the @code{compare} operator, a constant is always the second operand
7925 if the first argument is a condition code register or @code{(cc0)}.
7928 For instructions that inherently set a condition code register, the
7929 @code{compare} operator is always written as the first RTL expression of
7930 the @code{parallel} instruction pattern. For example,
7934 [(set (reg:CCZ FLAGS_REG)
7937 (match_operand:SI 1 "register_operand" "%r")
7938 (match_operand:SI 2 "register_operand" "r"))
7940 (set (match_operand:SI 0 "register_operand" "=r")
7941 (plus:SI (match_dup 1) (match_dup 2)))]
7947 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
7948 @code{minus} is made the first operand under the same conditions as
7952 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
7953 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
7957 @code{(minus @var{x} (const_int @var{n}))} is converted to
7958 @code{(plus @var{x} (const_int @var{-n}))}.
7961 Within address computations (i.e., inside @code{mem}), a left shift is
7962 converted into the appropriate multiplication by a power of two.
7964 @cindex @code{ior}, canonicalization of
7965 @cindex @code{and}, canonicalization of
7966 @cindex De Morgan's law
7968 De Morgan's Law is used to move bitwise negation inside a bitwise
7969 logical-and or logical-or operation. If this results in only one
7970 operand being a @code{not} expression, it will be the first one.
7972 A machine that has an instruction that performs a bitwise logical-and of one
7973 operand with the bitwise negation of the other should specify the pattern
7974 for that instruction as
7978 [(set (match_operand:@var{m} 0 @dots{})
7979 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7980 (match_operand:@var{m} 2 @dots{})))]
7986 Similarly, a pattern for a ``NAND'' instruction should be written
7990 [(set (match_operand:@var{m} 0 @dots{})
7991 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7992 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
7997 In both cases, it is not necessary to include patterns for the many
7998 logically equivalent RTL expressions.
8000 @cindex @code{xor}, canonicalization of
8002 The only possible RTL expressions involving both bitwise exclusive-or
8003 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
8004 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
8007 The sum of three items, one of which is a constant, will only appear in
8011 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
8014 @cindex @code{zero_extract}, canonicalization of
8015 @cindex @code{sign_extract}, canonicalization of
8017 Equality comparisons of a group of bits (usually a single bit) with zero
8018 will be written using @code{zero_extract} rather than the equivalent
8019 @code{and} or @code{sign_extract} operations.
8021 @cindex @code{mult}, canonicalization of
8023 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
8024 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
8025 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
8026 for @code{zero_extend}.
8029 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
8030 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
8031 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
8032 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
8033 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
8034 operand of @code{mult} is also a shift, then that is extended also.
8035 This transformation is only applied when it can be proven that the
8036 original operation had sufficient precision to prevent overflow.
8040 Further canonicalization rules are defined in the function
8041 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
8045 @node Expander Definitions
8046 @section Defining RTL Sequences for Code Generation
8047 @cindex expander definitions
8048 @cindex code generation RTL sequences
8049 @cindex defining RTL sequences for code generation
8051 On some target machines, some standard pattern names for RTL generation
8052 cannot be handled with single insn, but a sequence of RTL insns can
8053 represent them. For these target machines, you can write a
8054 @code{define_expand} to specify how to generate the sequence of RTL@.
8056 @findex define_expand
8057 A @code{define_expand} is an RTL expression that looks almost like a
8058 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
8059 only for RTL generation and it can produce more than one RTL insn.
8061 A @code{define_expand} RTX has four operands:
8065 The name. Each @code{define_expand} must have a name, since the only
8066 use for it is to refer to it by name.
8069 The RTL template. This is a vector of RTL expressions representing
8070 a sequence of separate instructions. Unlike @code{define_insn}, there
8071 is no implicit surrounding @code{PARALLEL}.
8074 The condition, a string containing a C expression. This expression is
8075 used to express how the availability of this pattern depends on
8076 subclasses of target machine, selected by command-line options when GCC
8077 is run. This is just like the condition of a @code{define_insn} that
8078 has a standard name. Therefore, the condition (if present) may not
8079 depend on the data in the insn being matched, but only the
8080 target-machine-type flags. The compiler needs to test these conditions
8081 during initialization in order to learn exactly which named instructions
8082 are available in a particular run.
8085 The preparation statements, a string containing zero or more C
8086 statements which are to be executed before RTL code is generated from
8089 Usually these statements prepare temporary registers for use as
8090 internal operands in the RTL template, but they can also generate RTL
8091 insns directly by calling routines such as @code{emit_insn}, etc.
8092 Any such insns precede the ones that come from the RTL template.
8095 Optionally, a vector containing the values of attributes. @xref{Insn
8099 Every RTL insn emitted by a @code{define_expand} must match some
8100 @code{define_insn} in the machine description. Otherwise, the compiler
8101 will crash when trying to generate code for the insn or trying to optimize
8104 The RTL template, in addition to controlling generation of RTL insns,
8105 also describes the operands that need to be specified when this pattern
8106 is used. In particular, it gives a predicate for each operand.
8108 A true operand, which needs to be specified in order to generate RTL from
8109 the pattern, should be described with a @code{match_operand} in its first
8110 occurrence in the RTL template. This enters information on the operand's
8111 predicate into the tables that record such things. GCC uses the
8112 information to preload the operand into a register if that is required for
8113 valid RTL code. If the operand is referred to more than once, subsequent
8114 references should use @code{match_dup}.
8116 The RTL template may also refer to internal ``operands'' which are
8117 temporary registers or labels used only within the sequence made by the
8118 @code{define_expand}. Internal operands are substituted into the RTL
8119 template with @code{match_dup}, never with @code{match_operand}. The
8120 values of the internal operands are not passed in as arguments by the
8121 compiler when it requests use of this pattern. Instead, they are computed
8122 within the pattern, in the preparation statements. These statements
8123 compute the values and store them into the appropriate elements of
8124 @code{operands} so that @code{match_dup} can find them.
8126 There are two special macros defined for use in the preparation statements:
8127 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8134 Use the @code{DONE} macro to end RTL generation for the pattern. The
8135 only RTL insns resulting from the pattern on this occasion will be
8136 those already emitted by explicit calls to @code{emit_insn} within the
8137 preparation statements; the RTL template will not be generated.
8141 Make the pattern fail on this occasion. When a pattern fails, it means
8142 that the pattern was not truly available. The calling routines in the
8143 compiler will try other strategies for code generation using other patterns.
8145 Failure is currently supported only for binary (addition, multiplication,
8146 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
8150 If the preparation falls through (invokes neither @code{DONE} nor
8151 @code{FAIL}), then the @code{define_expand} acts like a
8152 @code{define_insn} in that the RTL template is used to generate the
8155 The RTL template is not used for matching, only for generating the
8156 initial insn list. If the preparation statement always invokes
8157 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
8158 list of operands, such as this example:
8162 (define_expand "addsi3"
8163 [(match_operand:SI 0 "register_operand" "")
8164 (match_operand:SI 1 "register_operand" "")
8165 (match_operand:SI 2 "register_operand" "")]
8171 handle_add (operands[0], operands[1], operands[2]);
8177 Here is an example, the definition of left-shift for the SPUR chip:
8181 (define_expand "ashlsi3"
8182 [(set (match_operand:SI 0 "register_operand" "")
8186 (match_operand:SI 1 "register_operand" "")
8187 (match_operand:SI 2 "nonmemory_operand" "")))]
8196 if (GET_CODE (operands[2]) != CONST_INT
8197 || (unsigned) INTVAL (operands[2]) > 3)
8204 This example uses @code{define_expand} so that it can generate an RTL insn
8205 for shifting when the shift-count is in the supported range of 0 to 3 but
8206 fail in other cases where machine insns aren't available. When it fails,
8207 the compiler tries another strategy using different patterns (such as, a
8210 If the compiler were able to handle nontrivial condition-strings in
8211 patterns with names, then it would be possible to use a
8212 @code{define_insn} in that case. Here is another case (zero-extension
8213 on the 68000) which makes more use of the power of @code{define_expand}:
8216 (define_expand "zero_extendhisi2"
8217 [(set (match_operand:SI 0 "general_operand" "")
8219 (set (strict_low_part
8223 (match_operand:HI 1 "general_operand" ""))]
8225 "operands[1] = make_safe_from (operands[1], operands[0]);")
8229 @findex make_safe_from
8230 Here two RTL insns are generated, one to clear the entire output operand
8231 and the other to copy the input operand into its low half. This sequence
8232 is incorrect if the input operand refers to [the old value of] the output
8233 operand, so the preparation statement makes sure this isn't so. The
8234 function @code{make_safe_from} copies the @code{operands[1]} into a
8235 temporary register if it refers to @code{operands[0]}. It does this
8236 by emitting another RTL insn.
8238 Finally, a third example shows the use of an internal operand.
8239 Zero-extension on the SPUR chip is done by @code{and}-ing the result
8240 against a halfword mask. But this mask cannot be represented by a
8241 @code{const_int} because the constant value is too large to be legitimate
8242 on this machine. So it must be copied into a register with
8243 @code{force_reg} and then the register used in the @code{and}.
8246 (define_expand "zero_extendhisi2"
8247 [(set (match_operand:SI 0 "register_operand" "")
8249 (match_operand:HI 1 "register_operand" "")
8254 = force_reg (SImode, GEN_INT (65535)); ")
8257 @emph{Note:} If the @code{define_expand} is used to serve a
8258 standard binary or unary arithmetic operation or a bit-field operation,
8259 then the last insn it generates must not be a @code{code_label},
8260 @code{barrier} or @code{note}. It must be an @code{insn},
8261 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
8262 at the end, emit an insn to copy the result of the operation into
8263 itself. Such an insn will generate no code, but it can avoid problems
8268 @node Insn Splitting
8269 @section Defining How to Split Instructions
8270 @cindex insn splitting
8271 @cindex instruction splitting
8272 @cindex splitting instructions
8274 There are two cases where you should specify how to split a pattern
8275 into multiple insns. On machines that have instructions requiring
8276 delay slots (@pxref{Delay Slots}) or that have instructions whose
8277 output is not available for multiple cycles (@pxref{Processor pipeline
8278 description}), the compiler phases that optimize these cases need to
8279 be able to move insns into one-instruction delay slots. However, some
8280 insns may generate more than one machine instruction. These insns
8281 cannot be placed into a delay slot.
8283 Often you can rewrite the single insn as a list of individual insns,
8284 each corresponding to one machine instruction. The disadvantage of
8285 doing so is that it will cause the compilation to be slower and require
8286 more space. If the resulting insns are too complex, it may also
8287 suppress some optimizations. The compiler splits the insn if there is a
8288 reason to believe that it might improve instruction or delay slot
8291 The insn combiner phase also splits putative insns. If three insns are
8292 merged into one insn with a complex expression that cannot be matched by
8293 some @code{define_insn} pattern, the combiner phase attempts to split
8294 the complex pattern into two insns that are recognized. Usually it can
8295 break the complex pattern into two patterns by splitting out some
8296 subexpression. However, in some other cases, such as performing an
8297 addition of a large constant in two insns on a RISC machine, the way to
8298 split the addition into two insns is machine-dependent.
8300 @findex define_split
8301 The @code{define_split} definition tells the compiler how to split a
8302 complex insn into several simpler insns. It looks like this:
8306 [@var{insn-pattern}]
8308 [@var{new-insn-pattern-1}
8309 @var{new-insn-pattern-2}
8311 "@var{preparation-statements}")
8314 @var{insn-pattern} is a pattern that needs to be split and
8315 @var{condition} is the final condition to be tested, as in a
8316 @code{define_insn}. When an insn matching @var{insn-pattern} and
8317 satisfying @var{condition} is found, it is replaced in the insn list
8318 with the insns given by @var{new-insn-pattern-1},
8319 @var{new-insn-pattern-2}, etc.
8321 The @var{preparation-statements} are similar to those statements that
8322 are specified for @code{define_expand} (@pxref{Expander Definitions})
8323 and are executed before the new RTL is generated to prepare for the
8324 generated code or emit some insns whose pattern is not fixed. Unlike
8325 those in @code{define_expand}, however, these statements must not
8326 generate any new pseudo-registers. Once reload has completed, they also
8327 must not allocate any space in the stack frame.
8329 There are two special macros defined for use in the preparation statements:
8330 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8337 Use the @code{DONE} macro to end RTL generation for the splitter. The
8338 only RTL insns generated as replacement for the matched input insn will
8339 be those already emitted by explicit calls to @code{emit_insn} within
8340 the preparation statements; the replacement pattern is not used.
8344 Make the @code{define_split} fail on this occasion. When a @code{define_split}
8345 fails, it means that the splitter was not truly available for the inputs
8346 it was given, and the input insn will not be split.
8349 If the preparation falls through (invokes neither @code{DONE} nor
8350 @code{FAIL}), then the @code{define_split} uses the replacement
8353 Patterns are matched against @var{insn-pattern} in two different
8354 circumstances. If an insn needs to be split for delay slot scheduling
8355 or insn scheduling, the insn is already known to be valid, which means
8356 that it must have been matched by some @code{define_insn} and, if
8357 @code{reload_completed} is nonzero, is known to satisfy the constraints
8358 of that @code{define_insn}. In that case, the new insn patterns must
8359 also be insns that are matched by some @code{define_insn} and, if
8360 @code{reload_completed} is nonzero, must also satisfy the constraints
8361 of those definitions.
8363 As an example of this usage of @code{define_split}, consider the following
8364 example from @file{a29k.md}, which splits a @code{sign_extend} from
8365 @code{HImode} to @code{SImode} into a pair of shift insns:
8369 [(set (match_operand:SI 0 "gen_reg_operand" "")
8370 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
8373 (ashift:SI (match_dup 1)
8376 (ashiftrt:SI (match_dup 0)
8379 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
8382 When the combiner phase tries to split an insn pattern, it is always the
8383 case that the pattern is @emph{not} matched by any @code{define_insn}.
8384 The combiner pass first tries to split a single @code{set} expression
8385 and then the same @code{set} expression inside a @code{parallel}, but
8386 followed by a @code{clobber} of a pseudo-reg to use as a scratch
8387 register. In these cases, the combiner expects exactly two new insn
8388 patterns to be generated. It will verify that these patterns match some
8389 @code{define_insn} definitions, so you need not do this test in the
8390 @code{define_split} (of course, there is no point in writing a
8391 @code{define_split} that will never produce insns that match).
8393 Here is an example of this use of @code{define_split}, taken from
8398 [(set (match_operand:SI 0 "gen_reg_operand" "")
8399 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
8400 (match_operand:SI 2 "non_add_cint_operand" "")))]
8402 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
8403 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
8406 int low = INTVAL (operands[2]) & 0xffff;
8407 int high = (unsigned) INTVAL (operands[2]) >> 16;
8410 high++, low |= 0xffff0000;
8412 operands[3] = GEN_INT (high << 16);
8413 operands[4] = GEN_INT (low);
8417 Here the predicate @code{non_add_cint_operand} matches any
8418 @code{const_int} that is @emph{not} a valid operand of a single add
8419 insn. The add with the smaller displacement is written so that it
8420 can be substituted into the address of a subsequent operation.
8422 An example that uses a scratch register, from the same file, generates
8423 an equality comparison of a register and a large constant:
8427 [(set (match_operand:CC 0 "cc_reg_operand" "")
8428 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
8429 (match_operand:SI 2 "non_short_cint_operand" "")))
8430 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
8431 "find_single_use (operands[0], insn, 0)
8432 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
8433 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
8434 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
8435 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
8438 /* @r{Get the constant we are comparing against, C, and see what it
8439 looks like sign-extended to 16 bits. Then see what constant
8440 could be XOR'ed with C to get the sign-extended value.} */
8442 int c = INTVAL (operands[2]);
8443 int sextc = (c << 16) >> 16;
8444 int xorv = c ^ sextc;
8446 operands[4] = GEN_INT (xorv);
8447 operands[5] = GEN_INT (sextc);
8451 To avoid confusion, don't write a single @code{define_split} that
8452 accepts some insns that match some @code{define_insn} as well as some
8453 insns that don't. Instead, write two separate @code{define_split}
8454 definitions, one for the insns that are valid and one for the insns that
8457 The splitter is allowed to split jump instructions into sequence of
8458 jumps or create new jumps in while splitting non-jump instructions. As
8459 the control flow graph and branch prediction information needs to be updated,
8460 several restriction apply.
8462 Splitting of jump instruction into sequence that over by another jump
8463 instruction is always valid, as compiler expect identical behavior of new
8464 jump. When new sequence contains multiple jump instructions or new labels,
8465 more assistance is needed. Splitter is required to create only unconditional
8466 jumps, or simple conditional jump instructions. Additionally it must attach a
8467 @code{REG_BR_PROB} note to each conditional jump. A global variable
8468 @code{split_branch_probability} holds the probability of the original branch in case
8469 it was a simple conditional jump, @minus{}1 otherwise. To simplify
8470 recomputing of edge frequencies, the new sequence is required to have only
8471 forward jumps to the newly created labels.
8473 @findex define_insn_and_split
8474 For the common case where the pattern of a define_split exactly matches the
8475 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
8479 (define_insn_and_split
8480 [@var{insn-pattern}]
8482 "@var{output-template}"
8483 "@var{split-condition}"
8484 [@var{new-insn-pattern-1}
8485 @var{new-insn-pattern-2}
8487 "@var{preparation-statements}"
8488 [@var{insn-attributes}])
8492 @var{insn-pattern}, @var{condition}, @var{output-template}, and
8493 @var{insn-attributes} are used as in @code{define_insn}. The
8494 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
8495 in a @code{define_split}. The @var{split-condition} is also used as in
8496 @code{define_split}, with the additional behavior that if the condition starts
8497 with @samp{&&}, the condition used for the split will be the constructed as a
8498 logical ``and'' of the split condition with the insn condition. For example,
8502 (define_insn_and_split "zero_extendhisi2_and"
8503 [(set (match_operand:SI 0 "register_operand" "=r")
8504 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
8505 (clobber (reg:CC 17))]
8506 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
8508 "&& reload_completed"
8509 [(parallel [(set (match_dup 0)
8510 (and:SI (match_dup 0) (const_int 65535)))
8511 (clobber (reg:CC 17))])]
8513 [(set_attr "type" "alu1")])
8517 In this case, the actual split condition will be
8518 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
8520 The @code{define_insn_and_split} construction provides exactly the same
8521 functionality as two separate @code{define_insn} and @code{define_split}
8522 patterns. It exists for compactness, and as a maintenance tool to prevent
8523 having to ensure the two patterns' templates match.
8527 @node Including Patterns
8528 @section Including Patterns in Machine Descriptions.
8529 @cindex insn includes
8532 The @code{include} pattern tells the compiler tools where to
8533 look for patterns that are in files other than in the file
8534 @file{.md}. This is used only at build time and there is no preprocessing allowed.
8548 (include "filestuff")
8552 Where @var{pathname} is a string that specifies the location of the file,
8553 specifies the include file to be in @file{gcc/config/target/filestuff}. The
8554 directory @file{gcc/config/target} is regarded as the default directory.
8557 Machine descriptions may be split up into smaller more manageable subsections
8558 and placed into subdirectories.
8564 (include "BOGUS/filestuff")
8568 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
8570 Specifying an absolute path for the include file such as;
8573 (include "/u2/BOGUS/filestuff")
8576 is permitted but is not encouraged.
8578 @subsection RTL Generation Tool Options for Directory Search
8579 @cindex directory options .md
8580 @cindex options, directory search
8581 @cindex search options
8583 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
8588 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
8593 Add the directory @var{dir} to the head of the list of directories to be
8594 searched for header files. This can be used to override a system machine definition
8595 file, substituting your own version, since these directories are
8596 searched before the default machine description file directories. If you use more than
8597 one @option{-I} option, the directories are scanned in left-to-right
8598 order; the standard default directory come after.
8603 @node Peephole Definitions
8604 @section Machine-Specific Peephole Optimizers
8605 @cindex peephole optimizer definitions
8606 @cindex defining peephole optimizers
8608 In addition to instruction patterns the @file{md} file may contain
8609 definitions of machine-specific peephole optimizations.
8611 The combiner does not notice certain peephole optimizations when the data
8612 flow in the program does not suggest that it should try them. For example,
8613 sometimes two consecutive insns related in purpose can be combined even
8614 though the second one does not appear to use a register computed in the
8615 first one. A machine-specific peephole optimizer can detect such
8618 There are two forms of peephole definitions that may be used. The
8619 original @code{define_peephole} is run at assembly output time to
8620 match insns and substitute assembly text. Use of @code{define_peephole}
8623 A newer @code{define_peephole2} matches insns and substitutes new
8624 insns. The @code{peephole2} pass is run after register allocation
8625 but before scheduling, which may result in much better code for
8626 targets that do scheduling.
8629 * define_peephole:: RTL to Text Peephole Optimizers
8630 * define_peephole2:: RTL to RTL Peephole Optimizers
8635 @node define_peephole
8636 @subsection RTL to Text Peephole Optimizers
8637 @findex define_peephole
8640 A definition looks like this:
8644 [@var{insn-pattern-1}
8645 @var{insn-pattern-2}
8649 "@var{optional-insn-attributes}")
8653 The last string operand may be omitted if you are not using any
8654 machine-specific information in this machine description. If present,
8655 it must obey the same rules as in a @code{define_insn}.
8657 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
8658 consecutive insns. The optimization applies to a sequence of insns when
8659 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
8660 the next, and so on.
8662 Each of the insns matched by a peephole must also match a
8663 @code{define_insn}. Peepholes are checked only at the last stage just
8664 before code generation, and only optionally. Therefore, any insn which
8665 would match a peephole but no @code{define_insn} will cause a crash in code
8666 generation in an unoptimized compilation, or at various optimization
8669 The operands of the insns are matched with @code{match_operands},
8670 @code{match_operator}, and @code{match_dup}, as usual. What is not
8671 usual is that the operand numbers apply to all the insn patterns in the
8672 definition. So, you can check for identical operands in two insns by
8673 using @code{match_operand} in one insn and @code{match_dup} in the
8676 The operand constraints used in @code{match_operand} patterns do not have
8677 any direct effect on the applicability of the peephole, but they will
8678 be validated afterward, so make sure your constraints are general enough
8679 to apply whenever the peephole matches. If the peephole matches
8680 but the constraints are not satisfied, the compiler will crash.
8682 It is safe to omit constraints in all the operands of the peephole; or
8683 you can write constraints which serve as a double-check on the criteria
8686 Once a sequence of insns matches the patterns, the @var{condition} is
8687 checked. This is a C expression which makes the final decision whether to
8688 perform the optimization (we do so if the expression is nonzero). If
8689 @var{condition} is omitted (in other words, the string is empty) then the
8690 optimization is applied to every sequence of insns that matches the
8693 The defined peephole optimizations are applied after register allocation
8694 is complete. Therefore, the peephole definition can check which
8695 operands have ended up in which kinds of registers, just by looking at
8698 @findex prev_active_insn
8699 The way to refer to the operands in @var{condition} is to write
8700 @code{operands[@var{i}]} for operand number @var{i} (as matched by
8701 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
8702 to refer to the last of the insns being matched; use
8703 @code{prev_active_insn} to find the preceding insns.
8705 @findex dead_or_set_p
8706 When optimizing computations with intermediate results, you can use
8707 @var{condition} to match only when the intermediate results are not used
8708 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
8709 @var{op})}, where @var{insn} is the insn in which you expect the value
8710 to be used for the last time (from the value of @code{insn}, together
8711 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
8712 value (from @code{operands[@var{i}]}).
8714 Applying the optimization means replacing the sequence of insns with one
8715 new insn. The @var{template} controls ultimate output of assembler code
8716 for this combined insn. It works exactly like the template of a
8717 @code{define_insn}. Operand numbers in this template are the same ones
8718 used in matching the original sequence of insns.
8720 The result of a defined peephole optimizer does not need to match any of
8721 the insn patterns in the machine description; it does not even have an
8722 opportunity to match them. The peephole optimizer definition itself serves
8723 as the insn pattern to control how the insn is output.
8725 Defined peephole optimizers are run as assembler code is being output,
8726 so the insns they produce are never combined or rearranged in any way.
8728 Here is an example, taken from the 68000 machine description:
8732 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
8733 (set (match_operand:DF 0 "register_operand" "=f")
8734 (match_operand:DF 1 "register_operand" "ad"))]
8735 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
8738 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8740 output_asm_insn ("move.l %1,(sp)", xoperands);
8741 output_asm_insn ("move.l %1,-(sp)", operands);
8742 return "fmove.d (sp)+,%0";
8744 output_asm_insn ("movel %1,sp@@", xoperands);
8745 output_asm_insn ("movel %1,sp@@-", operands);
8746 return "fmoved sp@@+,%0";
8752 The effect of this optimization is to change
8778 If a peephole matches a sequence including one or more jump insns, you must
8779 take account of the flags such as @code{CC_REVERSED} which specify that the
8780 condition codes are represented in an unusual manner. The compiler
8781 automatically alters any ordinary conditional jumps which occur in such
8782 situations, but the compiler cannot alter jumps which have been replaced by
8783 peephole optimizations. So it is up to you to alter the assembler code
8784 that the peephole produces. Supply C code to write the assembler output,
8785 and in this C code check the condition code status flags and change the
8786 assembler code as appropriate.
8789 @var{insn-pattern-1} and so on look @emph{almost} like the second
8790 operand of @code{define_insn}. There is one important difference: the
8791 second operand of @code{define_insn} consists of one or more RTX's
8792 enclosed in square brackets. Usually, there is only one: then the same
8793 action can be written as an element of a @code{define_peephole}. But
8794 when there are multiple actions in a @code{define_insn}, they are
8795 implicitly enclosed in a @code{parallel}. Then you must explicitly
8796 write the @code{parallel}, and the square brackets within it, in the
8797 @code{define_peephole}. Thus, if an insn pattern looks like this,
8800 (define_insn "divmodsi4"
8801 [(set (match_operand:SI 0 "general_operand" "=d")
8802 (div:SI (match_operand:SI 1 "general_operand" "0")
8803 (match_operand:SI 2 "general_operand" "dmsK")))
8804 (set (match_operand:SI 3 "general_operand" "=d")
8805 (mod:SI (match_dup 1) (match_dup 2)))]
8807 "divsl%.l %2,%3:%0")
8811 then the way to mention this insn in a peephole is as follows:
8817 [(set (match_operand:SI 0 "general_operand" "=d")
8818 (div:SI (match_operand:SI 1 "general_operand" "0")
8819 (match_operand:SI 2 "general_operand" "dmsK")))
8820 (set (match_operand:SI 3 "general_operand" "=d")
8821 (mod:SI (match_dup 1) (match_dup 2)))])
8828 @node define_peephole2
8829 @subsection RTL to RTL Peephole Optimizers
8830 @findex define_peephole2
8832 The @code{define_peephole2} definition tells the compiler how to
8833 substitute one sequence of instructions for another sequence,
8834 what additional scratch registers may be needed and what their
8839 [@var{insn-pattern-1}
8840 @var{insn-pattern-2}
8843 [@var{new-insn-pattern-1}
8844 @var{new-insn-pattern-2}
8846 "@var{preparation-statements}")
8849 The definition is almost identical to @code{define_split}
8850 (@pxref{Insn Splitting}) except that the pattern to match is not a
8851 single instruction, but a sequence of instructions.
8853 It is possible to request additional scratch registers for use in the
8854 output template. If appropriate registers are not free, the pattern
8855 will simply not match.
8857 @findex match_scratch
8859 Scratch registers are requested with a @code{match_scratch} pattern at
8860 the top level of the input pattern. The allocated register (initially) will
8861 be dead at the point requested within the original sequence. If the scratch
8862 is used at more than a single point, a @code{match_dup} pattern at the
8863 top level of the input pattern marks the last position in the input sequence
8864 at which the register must be available.
8866 Here is an example from the IA-32 machine description:
8870 [(match_scratch:SI 2 "r")
8871 (parallel [(set (match_operand:SI 0 "register_operand" "")
8872 (match_operator:SI 3 "arith_or_logical_operator"
8874 (match_operand:SI 1 "memory_operand" "")]))
8875 (clobber (reg:CC 17))])]
8876 "! optimize_size && ! TARGET_READ_MODIFY"
8877 [(set (match_dup 2) (match_dup 1))
8878 (parallel [(set (match_dup 0)
8879 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
8880 (clobber (reg:CC 17))])]
8885 This pattern tries to split a load from its use in the hopes that we'll be
8886 able to schedule around the memory load latency. It allocates a single
8887 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
8888 to be live only at the point just before the arithmetic.
8890 A real example requiring extended scratch lifetimes is harder to come by,
8891 so here's a silly made-up example:
8895 [(match_scratch:SI 4 "r")
8896 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
8897 (set (match_operand:SI 2 "" "") (match_dup 1))
8899 (set (match_operand:SI 3 "" "") (match_dup 1))]
8900 "/* @r{determine 1 does not overlap 0 and 2} */"
8901 [(set (match_dup 4) (match_dup 1))
8902 (set (match_dup 0) (match_dup 4))
8903 (set (match_dup 2) (match_dup 4))
8904 (set (match_dup 3) (match_dup 4))]
8908 There are two special macros defined for use in the preparation statements:
8909 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
8916 Use the @code{DONE} macro to end RTL generation for the peephole. The
8917 only RTL insns generated as replacement for the matched input insn will
8918 be those already emitted by explicit calls to @code{emit_insn} within
8919 the preparation statements; the replacement pattern is not used.
8923 Make the @code{define_peephole2} fail on this occasion. When a @code{define_peephole2}
8924 fails, it means that the replacement was not truly available for the
8925 particular inputs it was given. In that case, GCC may still apply a
8926 later @code{define_peephole2} that also matches the given insn pattern.
8927 (Note that this is different from @code{define_split}, where @code{FAIL}
8928 prevents the input insn from being split at all.)
8931 If the preparation falls through (invokes neither @code{DONE} nor
8932 @code{FAIL}), then the @code{define_peephole2} uses the replacement
8936 If we had not added the @code{(match_dup 4)} in the middle of the input
8937 sequence, it might have been the case that the register we chose at the
8938 beginning of the sequence is killed by the first or second @code{set}.
8942 @node Insn Attributes
8943 @section Instruction Attributes
8944 @cindex insn attributes
8945 @cindex instruction attributes
8947 In addition to describing the instruction supported by the target machine,
8948 the @file{md} file also defines a group of @dfn{attributes} and a set of
8949 values for each. Every generated insn is assigned a value for each attribute.
8950 One possible attribute would be the effect that the insn has on the machine's
8951 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
8952 to track the condition codes.
8955 * Defining Attributes:: Specifying attributes and their values.
8956 * Expressions:: Valid expressions for attribute values.
8957 * Tagging Insns:: Assigning attribute values to insns.
8958 * Attr Example:: An example of assigning attributes.
8959 * Insn Lengths:: Computing the length of insns.
8960 * Constant Attributes:: Defining attributes that are constant.
8961 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
8962 * Delay Slots:: Defining delay slots required for a machine.
8963 * Processor pipeline description:: Specifying information for insn scheduling.
8968 @node Defining Attributes
8969 @subsection Defining Attributes and their Values
8970 @cindex defining attributes and their values
8971 @cindex attributes, defining
8974 The @code{define_attr} expression is used to define each attribute required
8975 by the target machine. It looks like:
8978 (define_attr @var{name} @var{list-of-values} @var{default})
8981 @var{name} is a string specifying the name of the attribute being
8982 defined. Some attributes are used in a special way by the rest of the
8983 compiler. The @code{enabled} attribute can be used to conditionally
8984 enable or disable insn alternatives (@pxref{Disable Insn
8985 Alternatives}). The @code{predicable} attribute, together with a
8986 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
8987 be used to automatically generate conditional variants of instruction
8988 patterns. The @code{mnemonic} attribute can be used to check for the
8989 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
8990 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
8991 so they should not be used elsewhere as alternative names.
8993 @var{list-of-values} is either a string that specifies a comma-separated
8994 list of values that can be assigned to the attribute, or a null string to
8995 indicate that the attribute takes numeric values.
8997 @var{default} is an attribute expression that gives the value of this
8998 attribute for insns that match patterns whose definition does not include
8999 an explicit value for this attribute. @xref{Attr Example}, for more
9000 information on the handling of defaults. @xref{Constant Attributes},
9001 for information on attributes that do not depend on any particular insn.
9004 For each defined attribute, a number of definitions are written to the
9005 @file{insn-attr.h} file. For cases where an explicit set of values is
9006 specified for an attribute, the following are defined:
9010 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
9013 An enumerated class is defined for @samp{attr_@var{name}} with
9014 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
9015 the attribute name and value are first converted to uppercase.
9018 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
9019 returns the attribute value for that insn.
9022 For example, if the following is present in the @file{md} file:
9025 (define_attr "type" "branch,fp,load,store,arith" @dots{})
9029 the following lines will be written to the file @file{insn-attr.h}.
9032 #define HAVE_ATTR_type 1
9033 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
9034 TYPE_STORE, TYPE_ARITH@};
9035 extern enum attr_type get_attr_type ();
9038 If the attribute takes numeric values, no @code{enum} type will be
9039 defined and the function to obtain the attribute's value will return
9042 There are attributes which are tied to a specific meaning. These
9043 attributes are not free to use for other purposes:
9047 The @code{length} attribute is used to calculate the length of emitted
9048 code chunks. This is especially important when verifying branch
9049 distances. @xref{Insn Lengths}.
9052 The @code{enabled} attribute can be defined to prevent certain
9053 alternatives of an insn definition from being used during code
9054 generation. @xref{Disable Insn Alternatives}.
9057 The @code{mnemonic} attribute can be defined to implement instruction
9058 specific checks in e.g.@: the pipeline description.
9059 @xref{Mnemonic Attribute}.
9062 For each of these special attributes, the corresponding
9063 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
9064 attribute is not defined; in that case, it is defined as @samp{0}.
9066 @findex define_enum_attr
9067 @anchor{define_enum_attr}
9068 Another way of defining an attribute is to use:
9071 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
9074 This works in just the same way as @code{define_attr}, except that
9075 the list of values is taken from a separate enumeration called
9076 @var{enum} (@pxref{define_enum}). This form allows you to use
9077 the same list of values for several attributes without having to
9078 repeat the list each time. For example:
9081 (define_enum "processor" [
9086 (define_enum_attr "arch" "processor"
9087 (const (symbol_ref "target_arch")))
9088 (define_enum_attr "tune" "processor"
9089 (const (symbol_ref "target_tune")))
9092 defines the same attributes as:
9095 (define_attr "arch" "model_a,model_b,@dots{}"
9096 (const (symbol_ref "target_arch")))
9097 (define_attr "tune" "model_a,model_b,@dots{}"
9098 (const (symbol_ref "target_tune")))
9101 but without duplicating the processor list. The second example defines two
9102 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
9103 defines a single C enum (@code{processor}).
9107 @subsection Attribute Expressions
9108 @cindex attribute expressions
9110 RTL expressions used to define attributes use the codes described above
9111 plus a few specific to attribute definitions, to be discussed below.
9112 Attribute value expressions must have one of the following forms:
9115 @cindex @code{const_int} and attributes
9116 @item (const_int @var{i})
9117 The integer @var{i} specifies the value of a numeric attribute. @var{i}
9118 must be non-negative.
9120 The value of a numeric attribute can be specified either with a
9121 @code{const_int}, or as an integer represented as a string in
9122 @code{const_string}, @code{eq_attr} (see below), @code{attr},
9123 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
9124 overrides on specific instructions (@pxref{Tagging Insns}).
9126 @cindex @code{const_string} and attributes
9127 @item (const_string @var{value})
9128 The string @var{value} specifies a constant attribute value.
9129 If @var{value} is specified as @samp{"*"}, it means that the default value of
9130 the attribute is to be used for the insn containing this expression.
9131 @samp{"*"} obviously cannot be used in the @var{default} expression
9132 of a @code{define_attr}.
9134 If the attribute whose value is being specified is numeric, @var{value}
9135 must be a string containing a non-negative integer (normally
9136 @code{const_int} would be used in this case). Otherwise, it must
9137 contain one of the valid values for the attribute.
9139 @cindex @code{if_then_else} and attributes
9140 @item (if_then_else @var{test} @var{true-value} @var{false-value})
9141 @var{test} specifies an attribute test, whose format is defined below.
9142 The value of this expression is @var{true-value} if @var{test} is true,
9143 otherwise it is @var{false-value}.
9145 @cindex @code{cond} and attributes
9146 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
9147 The first operand of this expression is a vector containing an even
9148 number of expressions and consisting of pairs of @var{test} and @var{value}
9149 expressions. The value of the @code{cond} expression is that of the
9150 @var{value} corresponding to the first true @var{test} expression. If
9151 none of the @var{test} expressions are true, the value of the @code{cond}
9152 expression is that of the @var{default} expression.
9155 @var{test} expressions can have one of the following forms:
9158 @cindex @code{const_int} and attribute tests
9159 @item (const_int @var{i})
9160 This test is true if @var{i} is nonzero and false otherwise.
9162 @cindex @code{not} and attributes
9163 @cindex @code{ior} and attributes
9164 @cindex @code{and} and attributes
9165 @item (not @var{test})
9166 @itemx (ior @var{test1} @var{test2})
9167 @itemx (and @var{test1} @var{test2})
9168 These tests are true if the indicated logical function is true.
9170 @cindex @code{match_operand} and attributes
9171 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
9172 This test is true if operand @var{n} of the insn whose attribute value
9173 is being determined has mode @var{m} (this part of the test is ignored
9174 if @var{m} is @code{VOIDmode}) and the function specified by the string
9175 @var{pred} returns a nonzero value when passed operand @var{n} and mode
9176 @var{m} (this part of the test is ignored if @var{pred} is the null
9179 The @var{constraints} operand is ignored and should be the null string.
9181 @cindex @code{match_test} and attributes
9182 @item (match_test @var{c-expr})
9183 The test is true if C expression @var{c-expr} is true. In non-constant
9184 attributes, @var{c-expr} has access to the following variables:
9188 The rtl instruction under test.
9189 @item which_alternative
9190 The @code{define_insn} alternative that @var{insn} matches.
9191 @xref{Output Statement}.
9193 An array of @var{insn}'s rtl operands.
9196 @var{c-expr} behaves like the condition in a C @code{if} statement,
9197 so there is no need to explicitly convert the expression into a boolean
9198 0 or 1 value. For example, the following two tests are equivalent:
9201 (match_test "x & 2")
9202 (match_test "(x & 2) != 0")
9205 @cindex @code{le} and attributes
9206 @cindex @code{leu} and attributes
9207 @cindex @code{lt} and attributes
9208 @cindex @code{gt} and attributes
9209 @cindex @code{gtu} and attributes
9210 @cindex @code{ge} and attributes
9211 @cindex @code{geu} and attributes
9212 @cindex @code{ne} and attributes
9213 @cindex @code{eq} and attributes
9214 @cindex @code{plus} and attributes
9215 @cindex @code{minus} and attributes
9216 @cindex @code{mult} and attributes
9217 @cindex @code{div} and attributes
9218 @cindex @code{mod} and attributes
9219 @cindex @code{abs} and attributes
9220 @cindex @code{neg} and attributes
9221 @cindex @code{ashift} and attributes
9222 @cindex @code{lshiftrt} and attributes
9223 @cindex @code{ashiftrt} and attributes
9224 @item (le @var{arith1} @var{arith2})
9225 @itemx (leu @var{arith1} @var{arith2})
9226 @itemx (lt @var{arith1} @var{arith2})
9227 @itemx (ltu @var{arith1} @var{arith2})
9228 @itemx (gt @var{arith1} @var{arith2})
9229 @itemx (gtu @var{arith1} @var{arith2})
9230 @itemx (ge @var{arith1} @var{arith2})
9231 @itemx (geu @var{arith1} @var{arith2})
9232 @itemx (ne @var{arith1} @var{arith2})
9233 @itemx (eq @var{arith1} @var{arith2})
9234 These tests are true if the indicated comparison of the two arithmetic
9235 expressions is true. Arithmetic expressions are formed with
9236 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
9237 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
9238 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
9241 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
9242 Lengths},for additional forms). @code{symbol_ref} is a string
9243 denoting a C expression that yields an @code{int} when evaluated by the
9244 @samp{get_attr_@dots{}} routine. It should normally be a global
9248 @item (eq_attr @var{name} @var{value})
9249 @var{name} is a string specifying the name of an attribute.
9251 @var{value} is a string that is either a valid value for attribute
9252 @var{name}, a comma-separated list of values, or @samp{!} followed by a
9253 value or list. If @var{value} does not begin with a @samp{!}, this
9254 test is true if the value of the @var{name} attribute of the current
9255 insn is in the list specified by @var{value}. If @var{value} begins
9256 with a @samp{!}, this test is true if the attribute's value is
9257 @emph{not} in the specified list.
9262 (eq_attr "type" "load,store")
9269 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
9272 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
9273 value of the compiler variable @code{which_alternative}
9274 (@pxref{Output Statement}) and the values must be small integers. For
9278 (eq_attr "alternative" "2,3")
9285 (ior (eq (symbol_ref "which_alternative") (const_int 2))
9286 (eq (symbol_ref "which_alternative") (const_int 3)))
9289 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
9290 where the value of the attribute being tested is known for all insns matching
9291 a particular pattern. This is by far the most common case.
9294 @item (attr_flag @var{name})
9295 The value of an @code{attr_flag} expression is true if the flag
9296 specified by @var{name} is true for the @code{insn} currently being
9299 @var{name} is a string specifying one of a fixed set of flags to test.
9300 Test the flags @code{forward} and @code{backward} to determine the
9301 direction of a conditional branch.
9303 This example describes a conditional branch delay slot which
9304 can be nullified for forward branches that are taken (annul-true) or
9305 for backward branches which are not taken (annul-false).
9308 (define_delay (eq_attr "type" "cbranch")
9309 [(eq_attr "in_branch_delay" "true")
9310 (and (eq_attr "in_branch_delay" "true")
9311 (attr_flag "forward"))
9312 (and (eq_attr "in_branch_delay" "true")
9313 (attr_flag "backward"))])
9316 The @code{forward} and @code{backward} flags are false if the current
9317 @code{insn} being scheduled is not a conditional branch.
9319 @code{attr_flag} is only used during delay slot scheduling and has no
9320 meaning to other passes of the compiler.
9323 @item (attr @var{name})
9324 The value of another attribute is returned. This is most useful
9325 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
9326 produce more efficient code for non-numeric attributes.
9332 @subsection Assigning Attribute Values to Insns
9333 @cindex tagging insns
9334 @cindex assigning attribute values to insns
9336 The value assigned to an attribute of an insn is primarily determined by
9337 which pattern is matched by that insn (or which @code{define_peephole}
9338 generated it). Every @code{define_insn} and @code{define_peephole} can
9339 have an optional last argument to specify the values of attributes for
9340 matching insns. The value of any attribute not specified in a particular
9341 insn is set to the default value for that attribute, as specified in its
9342 @code{define_attr}. Extensive use of default values for attributes
9343 permits the specification of the values for only one or two attributes
9344 in the definition of most insn patterns, as seen in the example in the
9347 The optional last argument of @code{define_insn} and
9348 @code{define_peephole} is a vector of expressions, each of which defines
9349 the value for a single attribute. The most general way of assigning an
9350 attribute's value is to use a @code{set} expression whose first operand is an
9351 @code{attr} expression giving the name of the attribute being set. The
9352 second operand of the @code{set} is an attribute expression
9353 (@pxref{Expressions}) giving the value of the attribute.
9355 When the attribute value depends on the @samp{alternative} attribute
9356 (i.e., which is the applicable alternative in the constraint of the
9357 insn), the @code{set_attr_alternative} expression can be used. It
9358 allows the specification of a vector of attribute expressions, one for
9362 When the generality of arbitrary attribute expressions is not required,
9363 the simpler @code{set_attr} expression can be used, which allows
9364 specifying a string giving either a single attribute value or a list
9365 of attribute values, one for each alternative.
9367 The form of each of the above specifications is shown below. In each case,
9368 @var{name} is a string specifying the attribute to be set.
9371 @item (set_attr @var{name} @var{value-string})
9372 @var{value-string} is either a string giving the desired attribute value,
9373 or a string containing a comma-separated list giving the values for
9374 succeeding alternatives. The number of elements must match the number
9375 of alternatives in the constraint of the insn pattern.
9377 Note that it may be useful to specify @samp{*} for some alternative, in
9378 which case the attribute will assume its default value for insns matching
9381 @findex set_attr_alternative
9382 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
9383 Depending on the alternative of the insn, the value will be one of the
9384 specified values. This is a shorthand for using a @code{cond} with
9385 tests on the @samp{alternative} attribute.
9388 @item (set (attr @var{name}) @var{value})
9389 The first operand of this @code{set} must be the special RTL expression
9390 @code{attr}, whose sole operand is a string giving the name of the
9391 attribute being set. @var{value} is the value of the attribute.
9394 The following shows three different ways of representing the same
9395 attribute value specification:
9398 (set_attr "type" "load,store,arith")
9400 (set_attr_alternative "type"
9401 [(const_string "load") (const_string "store")
9402 (const_string "arith")])
9405 (cond [(eq_attr "alternative" "1") (const_string "load")
9406 (eq_attr "alternative" "2") (const_string "store")]
9407 (const_string "arith")))
9411 @findex define_asm_attributes
9412 The @code{define_asm_attributes} expression provides a mechanism to
9413 specify the attributes assigned to insns produced from an @code{asm}
9414 statement. It has the form:
9417 (define_asm_attributes [@var{attr-sets}])
9421 where @var{attr-sets} is specified the same as for both the
9422 @code{define_insn} and the @code{define_peephole} expressions.
9424 These values will typically be the ``worst case'' attribute values. For
9425 example, they might indicate that the condition code will be clobbered.
9427 A specification for a @code{length} attribute is handled specially. The
9428 way to compute the length of an @code{asm} insn is to multiply the
9429 length specified in the expression @code{define_asm_attributes} by the
9430 number of machine instructions specified in the @code{asm} statement,
9431 determined by counting the number of semicolons and newlines in the
9432 string. Therefore, the value of the @code{length} attribute specified
9433 in a @code{define_asm_attributes} should be the maximum possible length
9434 of a single machine instruction.
9439 @subsection Example of Attribute Specifications
9440 @cindex attribute specifications example
9441 @cindex attribute specifications
9443 The judicious use of defaulting is important in the efficient use of
9444 insn attributes. Typically, insns are divided into @dfn{types} and an
9445 attribute, customarily called @code{type}, is used to represent this
9446 value. This attribute is normally used only to define the default value
9447 for other attributes. An example will clarify this usage.
9449 Assume we have a RISC machine with a condition code and in which only
9450 full-word operations are performed in registers. Let us assume that we
9451 can divide all insns into loads, stores, (integer) arithmetic
9452 operations, floating point operations, and branches.
9454 Here we will concern ourselves with determining the effect of an insn on
9455 the condition code and will limit ourselves to the following possible
9456 effects: The condition code can be set unpredictably (clobbered), not
9457 be changed, be set to agree with the results of the operation, or only
9458 changed if the item previously set into the condition code has been
9461 Here is part of a sample @file{md} file for such a machine:
9464 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
9466 (define_attr "cc" "clobber,unchanged,set,change0"
9467 (cond [(eq_attr "type" "load")
9468 (const_string "change0")
9469 (eq_attr "type" "store,branch")
9470 (const_string "unchanged")
9471 (eq_attr "type" "arith")
9472 (if_then_else (match_operand:SI 0 "" "")
9473 (const_string "set")
9474 (const_string "clobber"))]
9475 (const_string "clobber")))
9478 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
9479 (match_operand:SI 1 "general_operand" "r,m,r"))]
9485 [(set_attr "type" "arith,load,store")])
9488 Note that we assume in the above example that arithmetic operations
9489 performed on quantities smaller than a machine word clobber the condition
9490 code since they will set the condition code to a value corresponding to the
9496 @subsection Computing the Length of an Insn
9497 @cindex insn lengths, computing
9498 @cindex computing the length of an insn
9500 For many machines, multiple types of branch instructions are provided, each
9501 for different length branch displacements. In most cases, the assembler
9502 will choose the correct instruction to use. However, when the assembler
9503 cannot do so, GCC can when a special attribute, the @code{length}
9504 attribute, is defined. This attribute must be defined to have numeric
9505 values by specifying a null string in its @code{define_attr}.
9507 In the case of the @code{length} attribute, two additional forms of
9508 arithmetic terms are allowed in test expressions:
9511 @cindex @code{match_dup} and attributes
9512 @item (match_dup @var{n})
9513 This refers to the address of operand @var{n} of the current insn, which
9514 must be a @code{label_ref}.
9516 @cindex @code{pc} and attributes
9518 For non-branch instructions and backward branch instructions, this refers
9519 to the address of the current insn. But for forward branch instructions,
9520 this refers to the address of the next insn, because the length of the
9521 current insn is to be computed.
9524 @cindex @code{addr_vec}, length of
9525 @cindex @code{addr_diff_vec}, length of
9526 For normal insns, the length will be determined by value of the
9527 @code{length} attribute. In the case of @code{addr_vec} and
9528 @code{addr_diff_vec} insn patterns, the length is computed as
9529 the number of vectors multiplied by the size of each vector.
9531 Lengths are measured in addressable storage units (bytes).
9533 Note that it is possible to call functions via the @code{symbol_ref}
9534 mechanism to compute the length of an insn. However, if you use this
9535 mechanism you must provide dummy clauses to express the maximum length
9536 without using the function call. You can an example of this in the
9537 @code{pa} machine description for the @code{call_symref} pattern.
9539 The following macros can be used to refine the length computation:
9542 @findex ADJUST_INSN_LENGTH
9543 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
9544 If defined, modifies the length assigned to instruction @var{insn} as a
9545 function of the context in which it is used. @var{length} is an lvalue
9546 that contains the initially computed length of the insn and should be
9547 updated with the correct length of the insn.
9549 This macro will normally not be required. A case in which it is
9550 required is the ROMP@. On this machine, the size of an @code{addr_vec}
9551 insn must be increased by two to compensate for the fact that alignment
9555 @findex get_attr_length
9556 The routine that returns @code{get_attr_length} (the value of the
9557 @code{length} attribute) can be used by the output routine to
9558 determine the form of the branch instruction to be written, as the
9559 example below illustrates.
9561 As an example of the specification of variable-length branches, consider
9562 the IBM 360. If we adopt the convention that a register will be set to
9563 the starting address of a function, we can jump to labels within 4k of
9564 the start using a four-byte instruction. Otherwise, we need a six-byte
9565 sequence to load the address from memory and then branch to it.
9567 On such a machine, a pattern for a branch instruction might be specified
9573 (label_ref (match_operand 0 "" "")))]
9576 return (get_attr_length (insn) == 4
9577 ? "b %l0" : "l r15,=a(%l0); br r15");
9579 [(set (attr "length")
9580 (if_then_else (lt (match_dup 0) (const_int 4096))
9587 @node Constant Attributes
9588 @subsection Constant Attributes
9589 @cindex constant attributes
9591 A special form of @code{define_attr}, where the expression for the
9592 default value is a @code{const} expression, indicates an attribute that
9593 is constant for a given run of the compiler. Constant attributes may be
9594 used to specify which variety of processor is used. For example,
9597 (define_attr "cpu" "m88100,m88110,m88000"
9599 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
9600 (symbol_ref "TARGET_88110") (const_string "m88110")]
9601 (const_string "m88000"))))
9603 (define_attr "memory" "fast,slow"
9605 (if_then_else (symbol_ref "TARGET_FAST_MEM")
9606 (const_string "fast")
9607 (const_string "slow"))))
9610 The routine generated for constant attributes has no parameters as it
9611 does not depend on any particular insn. RTL expressions used to define
9612 the value of a constant attribute may use the @code{symbol_ref} form,
9613 but may not use either the @code{match_operand} form or @code{eq_attr}
9614 forms involving insn attributes.
9618 @node Mnemonic Attribute
9619 @subsection Mnemonic Attribute
9620 @cindex mnemonic attribute
9622 The @code{mnemonic} attribute is a string type attribute holding the
9623 instruction mnemonic for an insn alternative. The attribute values
9624 will automatically be generated by the machine description parser if
9625 there is an attribute definition in the md file:
9628 (define_attr "mnemonic" "unknown" (const_string "unknown"))
9631 The default value can be freely chosen as long as it does not collide
9632 with any of the instruction mnemonics. This value will be used
9633 whenever the machine description parser is not able to determine the
9634 mnemonic string. This might be the case for output templates
9635 containing more than a single instruction as in
9636 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
9638 The @code{mnemonic} attribute set is not generated automatically if the
9639 instruction string is generated via C code.
9641 An existing @code{mnemonic} attribute set in an insn definition will not
9642 be overriden by the md file parser. That way it is possible to
9643 manually set the instruction mnemonics for the cases where the md file
9644 parser fails to determine it automatically.
9646 The @code{mnemonic} attribute is useful for dealing with instruction
9647 specific properties in the pipeline description without defining
9648 additional insn attributes.
9651 (define_attr "ooo_expanded" ""
9652 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
9660 @subsection Delay Slot Scheduling
9661 @cindex delay slots, defining
9663 The insn attribute mechanism can be used to specify the requirements for
9664 delay slots, if any, on a target machine. An instruction is said to
9665 require a @dfn{delay slot} if some instructions that are physically
9666 after the instruction are executed as if they were located before it.
9667 Classic examples are branch and call instructions, which often execute
9668 the following instruction before the branch or call is performed.
9670 On some machines, conditional branch instructions can optionally
9671 @dfn{annul} instructions in the delay slot. This means that the
9672 instruction will not be executed for certain branch outcomes. Both
9673 instructions that annul if the branch is true and instructions that
9674 annul if the branch is false are supported.
9676 Delay slot scheduling differs from instruction scheduling in that
9677 determining whether an instruction needs a delay slot is dependent only
9678 on the type of instruction being generated, not on data flow between the
9679 instructions. See the next section for a discussion of data-dependent
9680 instruction scheduling.
9682 @findex define_delay
9683 The requirement of an insn needing one or more delay slots is indicated
9684 via the @code{define_delay} expression. It has the following form:
9687 (define_delay @var{test}
9688 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
9689 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
9693 @var{test} is an attribute test that indicates whether this
9694 @code{define_delay} applies to a particular insn. If so, the number of
9695 required delay slots is determined by the length of the vector specified
9696 as the second argument. An insn placed in delay slot @var{n} must
9697 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
9698 attribute test that specifies which insns may be annulled if the branch
9699 is true. Similarly, @var{annul-false-n} specifies which insns in the
9700 delay slot may be annulled if the branch is false. If annulling is not
9701 supported for that delay slot, @code{(nil)} should be coded.
9703 For example, in the common case where branch and call insns require
9704 a single delay slot, which may contain any insn other than a branch or
9705 call, the following would be placed in the @file{md} file:
9708 (define_delay (eq_attr "type" "branch,call")
9709 [(eq_attr "type" "!branch,call") (nil) (nil)])
9712 Multiple @code{define_delay} expressions may be specified. In this
9713 case, each such expression specifies different delay slot requirements
9714 and there must be no insn for which tests in two @code{define_delay}
9715 expressions are both true.
9717 For example, if we have a machine that requires one delay slot for branches
9718 but two for calls, no delay slot can contain a branch or call insn,
9719 and any valid insn in the delay slot for the branch can be annulled if the
9720 branch is true, we might represent this as follows:
9723 (define_delay (eq_attr "type" "branch")
9724 [(eq_attr "type" "!branch,call")
9725 (eq_attr "type" "!branch,call")
9728 (define_delay (eq_attr "type" "call")
9729 [(eq_attr "type" "!branch,call") (nil) (nil)
9730 (eq_attr "type" "!branch,call") (nil) (nil)])
9732 @c the above is *still* too long. --mew 4feb93
9736 @node Processor pipeline description
9737 @subsection Specifying processor pipeline description
9738 @cindex processor pipeline description
9739 @cindex processor functional units
9740 @cindex instruction latency time
9741 @cindex interlock delays
9742 @cindex data dependence delays
9743 @cindex reservation delays
9744 @cindex pipeline hazard recognizer
9745 @cindex automaton based pipeline description
9746 @cindex regular expressions
9747 @cindex deterministic finite state automaton
9748 @cindex automaton based scheduler
9752 To achieve better performance, most modern processors
9753 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
9754 processors) have many @dfn{functional units} on which several
9755 instructions can be executed simultaneously. An instruction starts
9756 execution if its issue conditions are satisfied. If not, the
9757 instruction is stalled until its conditions are satisfied. Such
9758 @dfn{interlock (pipeline) delay} causes interruption of the fetching
9759 of successor instructions (or demands nop instructions, e.g.@: for some
9762 There are two major kinds of interlock delays in modern processors.
9763 The first one is a data dependence delay determining @dfn{instruction
9764 latency time}. The instruction execution is not started until all
9765 source data have been evaluated by prior instructions (there are more
9766 complex cases when the instruction execution starts even when the data
9767 are not available but will be ready in given time after the
9768 instruction execution start). Taking the data dependence delays into
9769 account is simple. The data dependence (true, output, and
9770 anti-dependence) delay between two instructions is given by a
9771 constant. In most cases this approach is adequate. The second kind
9772 of interlock delays is a reservation delay. The reservation delay
9773 means that two instructions under execution will be in need of shared
9774 processors resources, i.e.@: buses, internal registers, and/or
9775 functional units, which are reserved for some time. Taking this kind
9776 of delay into account is complex especially for modern @acronym{RISC}
9779 The task of exploiting more processor parallelism is solved by an
9780 instruction scheduler. For a better solution to this problem, the
9781 instruction scheduler has to have an adequate description of the
9782 processor parallelism (or @dfn{pipeline description}). GCC
9783 machine descriptions describe processor parallelism and functional
9784 unit reservations for groups of instructions with the aid of
9785 @dfn{regular expressions}.
9787 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
9788 figure out the possibility of the instruction issue by the processor
9789 on a given simulated processor cycle. The pipeline hazard recognizer is
9790 automatically generated from the processor pipeline description. The
9791 pipeline hazard recognizer generated from the machine description
9792 is based on a deterministic finite state automaton (@acronym{DFA}):
9793 the instruction issue is possible if there is a transition from one
9794 automaton state to another one. This algorithm is very fast, and
9795 furthermore, its speed is not dependent on processor
9796 complexity@footnote{However, the size of the automaton depends on
9797 processor complexity. To limit this effect, machine descriptions
9798 can split orthogonal parts of the machine description among several
9799 automata: but then, since each of these must be stepped independently,
9800 this does cause a small decrease in the algorithm's performance.}.
9802 @cindex automaton based pipeline description
9803 The rest of this section describes the directives that constitute
9804 an automaton-based processor pipeline description. The order of
9805 these constructions within the machine description file is not
9808 @findex define_automaton
9809 @cindex pipeline hazard recognizer
9810 The following optional construction describes names of automata
9811 generated and used for the pipeline hazards recognition. Sometimes
9812 the generated finite state automaton used by the pipeline hazard
9813 recognizer is large. If we use more than one automaton and bind functional
9814 units to the automata, the total size of the automata is usually
9815 less than the size of the single automaton. If there is no one such
9816 construction, only one finite state automaton is generated.
9819 (define_automaton @var{automata-names})
9822 @var{automata-names} is a string giving names of the automata. The
9823 names are separated by commas. All the automata should have unique names.
9824 The automaton name is used in the constructions @code{define_cpu_unit} and
9825 @code{define_query_cpu_unit}.
9827 @findex define_cpu_unit
9828 @cindex processor functional units
9829 Each processor functional unit used in the description of instruction
9830 reservations should be described by the following construction.
9833 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
9836 @var{unit-names} is a string giving the names of the functional units
9837 separated by commas. Don't use name @samp{nothing}, it is reserved
9840 @var{automaton-name} is a string giving the name of the automaton with
9841 which the unit is bound. The automaton should be described in
9842 construction @code{define_automaton}. You should give
9843 @dfn{automaton-name}, if there is a defined automaton.
9845 The assignment of units to automata are constrained by the uses of the
9846 units in insn reservations. The most important constraint is: if a
9847 unit reservation is present on a particular cycle of an alternative
9848 for an insn reservation, then some unit from the same automaton must
9849 be present on the same cycle for the other alternatives of the insn
9850 reservation. The rest of the constraints are mentioned in the
9851 description of the subsequent constructions.
9853 @findex define_query_cpu_unit
9854 @cindex querying function unit reservations
9855 The following construction describes CPU functional units analogously
9856 to @code{define_cpu_unit}. The reservation of such units can be
9857 queried for an automaton state. The instruction scheduler never
9858 queries reservation of functional units for given automaton state. So
9859 as a rule, you don't need this construction. This construction could
9860 be used for future code generation goals (e.g.@: to generate
9861 @acronym{VLIW} insn templates).
9864 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
9867 @var{unit-names} is a string giving names of the functional units
9868 separated by commas.
9870 @var{automaton-name} is a string giving the name of the automaton with
9871 which the unit is bound.
9873 @findex define_insn_reservation
9874 @cindex instruction latency time
9875 @cindex regular expressions
9877 The following construction is the major one to describe pipeline
9878 characteristics of an instruction.
9881 (define_insn_reservation @var{insn-name} @var{default_latency}
9882 @var{condition} @var{regexp})
9885 @var{default_latency} is a number giving latency time of the
9886 instruction. There is an important difference between the old
9887 description and the automaton based pipeline description. The latency
9888 time is used for all dependencies when we use the old description. In
9889 the automaton based pipeline description, the given latency time is only
9890 used for true dependencies. The cost of anti-dependencies is always
9891 zero and the cost of output dependencies is the difference between
9892 latency times of the producing and consuming insns (if the difference
9893 is negative, the cost is considered to be zero). You can always
9894 change the default costs for any description by using the target hook
9895 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
9897 @var{insn-name} is a string giving the internal name of the insn. The
9898 internal names are used in constructions @code{define_bypass} and in
9899 the automaton description file generated for debugging. The internal
9900 name has nothing in common with the names in @code{define_insn}. It is a
9901 good practice to use insn classes described in the processor manual.
9903 @var{condition} defines what RTL insns are described by this
9904 construction. You should remember that you will be in trouble if
9905 @var{condition} for two or more different
9906 @code{define_insn_reservation} constructions is TRUE for an insn. In
9907 this case what reservation will be used for the insn is not defined.
9908 Such cases are not checked during generation of the pipeline hazards
9909 recognizer because in general recognizing that two conditions may have
9910 the same value is quite difficult (especially if the conditions
9911 contain @code{symbol_ref}). It is also not checked during the
9912 pipeline hazard recognizer work because it would slow down the
9913 recognizer considerably.
9915 @var{regexp} is a string describing the reservation of the cpu's functional
9916 units by the instruction. The reservations are described by a regular
9917 expression according to the following syntax:
9920 regexp = regexp "," oneof
9923 oneof = oneof "|" allof
9926 allof = allof "+" repeat
9929 repeat = element "*" number
9932 element = cpu_function_unit_name
9941 @samp{,} is used for describing the start of the next cycle in
9945 @samp{|} is used for describing a reservation described by the first
9946 regular expression @strong{or} a reservation described by the second
9947 regular expression @strong{or} etc.
9950 @samp{+} is used for describing a reservation described by the first
9951 regular expression @strong{and} a reservation described by the
9952 second regular expression @strong{and} etc.
9955 @samp{*} is used for convenience and simply means a sequence in which
9956 the regular expression are repeated @var{number} times with cycle
9957 advancing (see @samp{,}).
9960 @samp{cpu_function_unit_name} denotes reservation of the named
9964 @samp{reservation_name} --- see description of construction
9965 @samp{define_reservation}.
9968 @samp{nothing} denotes no unit reservations.
9971 @findex define_reservation
9972 Sometimes unit reservations for different insns contain common parts.
9973 In such case, you can simplify the pipeline description by describing
9974 the common part by the following construction
9977 (define_reservation @var{reservation-name} @var{regexp})
9980 @var{reservation-name} is a string giving name of @var{regexp}.
9981 Functional unit names and reservation names are in the same name
9982 space. So the reservation names should be different from the
9983 functional unit names and cannot be the reserved name @samp{nothing}.
9985 @findex define_bypass
9986 @cindex instruction latency time
9988 The following construction is used to describe exceptions in the
9989 latency time for given instruction pair. This is so called bypasses.
9992 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
9996 @var{number} defines when the result generated by the instructions
9997 given in string @var{out_insn_names} will be ready for the
9998 instructions given in string @var{in_insn_names}. Each of these
9999 strings is a comma-separated list of filename-style globs and
10000 they refer to the names of @code{define_insn_reservation}s.
10003 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
10005 defines a bypass between instructions that start with
10006 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
10009 @var{guard} is an optional string giving the name of a C function which
10010 defines an additional guard for the bypass. The function will get the
10011 two insns as parameters. If the function returns zero the bypass will
10012 be ignored for this case. The additional guard is necessary to
10013 recognize complicated bypasses, e.g.@: when the consumer is only an address
10014 of insn @samp{store} (not a stored value).
10016 If there are more one bypass with the same output and input insns, the
10017 chosen bypass is the first bypass with a guard in description whose
10018 guard function returns nonzero. If there is no such bypass, then
10019 bypass without the guard function is chosen.
10021 @findex exclusion_set
10022 @findex presence_set
10023 @findex final_presence_set
10024 @findex absence_set
10025 @findex final_absence_set
10028 The following five constructions are usually used to describe
10029 @acronym{VLIW} processors, or more precisely, to describe a placement
10030 of small instructions into @acronym{VLIW} instruction slots. They
10031 can be used for @acronym{RISC} processors, too.
10034 (exclusion_set @var{unit-names} @var{unit-names})
10035 (presence_set @var{unit-names} @var{patterns})
10036 (final_presence_set @var{unit-names} @var{patterns})
10037 (absence_set @var{unit-names} @var{patterns})
10038 (final_absence_set @var{unit-names} @var{patterns})
10041 @var{unit-names} is a string giving names of functional units
10042 separated by commas.
10044 @var{patterns} is a string giving patterns of functional units
10045 separated by comma. Currently pattern is one unit or units
10046 separated by white-spaces.
10048 The first construction (@samp{exclusion_set}) means that each
10049 functional unit in the first string cannot be reserved simultaneously
10050 with a unit whose name is in the second string and vice versa. For
10051 example, the construction is useful for describing processors
10052 (e.g.@: some SPARC processors) with a fully pipelined floating point
10053 functional unit which can execute simultaneously only single floating
10054 point insns or only double floating point insns.
10056 The second construction (@samp{presence_set}) means that each
10057 functional unit in the first string cannot be reserved unless at
10058 least one of pattern of units whose names are in the second string is
10059 reserved. This is an asymmetric relation. For example, it is useful
10060 for description that @acronym{VLIW} @samp{slot1} is reserved after
10061 @samp{slot0} reservation. We could describe it by the following
10065 (presence_set "slot1" "slot0")
10068 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
10069 reservation. In this case we could write
10072 (presence_set "slot1" "slot0 b0")
10075 The third construction (@samp{final_presence_set}) is analogous to
10076 @samp{presence_set}. The difference between them is when checking is
10077 done. When an instruction is issued in given automaton state
10078 reflecting all current and planned unit reservations, the automaton
10079 state is changed. The first state is a source state, the second one
10080 is a result state. Checking for @samp{presence_set} is done on the
10081 source state reservation, checking for @samp{final_presence_set} is
10082 done on the result reservation. This construction is useful to
10083 describe a reservation which is actually two subsequent reservations.
10084 For example, if we use
10087 (presence_set "slot1" "slot0")
10090 the following insn will be never issued (because @samp{slot1} requires
10091 @samp{slot0} which is absent in the source state).
10094 (define_reservation "insn_and_nop" "slot0 + slot1")
10097 but it can be issued if we use analogous @samp{final_presence_set}.
10099 The forth construction (@samp{absence_set}) means that each functional
10100 unit in the first string can be reserved only if each pattern of units
10101 whose names are in the second string is not reserved. This is an
10102 asymmetric relation (actually @samp{exclusion_set} is analogous to
10103 this one but it is symmetric). For example it might be useful in a
10104 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
10105 after either @samp{slot1} or @samp{slot2} have been reserved. This
10106 can be described as:
10109 (absence_set "slot0" "slot1, slot2")
10112 Or @samp{slot2} cannot be reserved if @samp{slot0} and unit @samp{b0}
10113 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
10114 this case we could write
10117 (absence_set "slot2" "slot0 b0, slot1 b1")
10120 All functional units mentioned in a set should belong to the same
10123 The last construction (@samp{final_absence_set}) is analogous to
10124 @samp{absence_set} but checking is done on the result (state)
10125 reservation. See comments for @samp{final_presence_set}.
10127 @findex automata_option
10128 @cindex deterministic finite state automaton
10129 @cindex nondeterministic finite state automaton
10130 @cindex finite state automaton minimization
10131 You can control the generator of the pipeline hazard recognizer with
10132 the following construction.
10135 (automata_option @var{options})
10138 @var{options} is a string giving options which affect the generated
10139 code. Currently there are the following options:
10143 @dfn{no-minimization} makes no minimization of the automaton. This is
10144 only worth to do when we are debugging the description and need to
10145 look more accurately at reservations of states.
10148 @dfn{time} means printing time statistics about the generation of
10152 @dfn{stats} means printing statistics about the generated automata
10153 such as the number of DFA states, NDFA states and arcs.
10156 @dfn{v} means a generation of the file describing the result automata.
10157 The file has suffix @samp{.dfa} and can be used for the description
10158 verification and debugging.
10161 @dfn{w} means a generation of warning instead of error for
10162 non-critical errors.
10165 @dfn{no-comb-vect} prevents the automaton generator from generating
10166 two data structures and comparing them for space efficiency. Using
10167 a comb vector to represent transitions may be better, but it can be
10168 very expensive to construct. This option is useful if the build
10169 process spends an unacceptably long time in genautomata.
10172 @dfn{ndfa} makes nondeterministic finite state automata. This affects
10173 the treatment of operator @samp{|} in the regular expressions. The
10174 usual treatment of the operator is to try the first alternative and,
10175 if the reservation is not possible, the second alternative. The
10176 nondeterministic treatment means trying all alternatives, some of them
10177 may be rejected by reservations in the subsequent insns.
10180 @dfn{collapse-ndfa} modifies the behavior of the generator when
10181 producing an automaton. An additional state transition to collapse a
10182 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
10183 state is generated. It can be triggered by passing @code{const0_rtx} to
10184 state_transition. In such an automaton, cycle advance transitions are
10185 available only for these collapsed states. This option is useful for
10186 ports that want to use the @code{ndfa} option, but also want to use
10187 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
10190 @dfn{progress} means output of a progress bar showing how many states
10191 were generated so far for automaton being processed. This is useful
10192 during debugging a @acronym{DFA} description. If you see too many
10193 generated states, you could interrupt the generator of the pipeline
10194 hazard recognizer and try to figure out a reason for generation of the
10198 As an example, consider a superscalar @acronym{RISC} machine which can
10199 issue three insns (two integer insns and one floating point insn) on
10200 the cycle but can finish only two insns. To describe this, we define
10201 the following functional units.
10204 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
10205 (define_cpu_unit "port0, port1")
10208 All simple integer insns can be executed in any integer pipeline and
10209 their result is ready in two cycles. The simple integer insns are
10210 issued into the first pipeline unless it is reserved, otherwise they
10211 are issued into the second pipeline. Integer division and
10212 multiplication insns can be executed only in the second integer
10213 pipeline and their results are ready correspondingly in 9 and 4
10214 cycles. The integer division is not pipelined, i.e.@: the subsequent
10215 integer division insn cannot be issued until the current division
10216 insn finished. Floating point insns are fully pipelined and their
10217 results are ready in 3 cycles. Where the result of a floating point
10218 insn is used by an integer insn, an additional delay of one cycle is
10219 incurred. To describe all of this we could specify
10222 (define_cpu_unit "div")
10224 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
10225 "(i0_pipeline | i1_pipeline), (port0 | port1)")
10227 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
10228 "i1_pipeline, nothing*2, (port0 | port1)")
10230 (define_insn_reservation "div" 9 (eq_attr "type" "div")
10231 "i1_pipeline, div*7, div + (port0 | port1)")
10233 (define_insn_reservation "float" 3 (eq_attr "type" "float")
10234 "f_pipeline, nothing, (port0 | port1))
10236 (define_bypass 4 "float" "simple,mult,div")
10239 To simplify the description we could describe the following reservation
10242 (define_reservation "finish" "port0|port1")
10245 and use it in all @code{define_insn_reservation} as in the following
10249 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
10250 "(i0_pipeline | i1_pipeline), finish")
10256 @node Conditional Execution
10257 @section Conditional Execution
10258 @cindex conditional execution
10259 @cindex predication
10261 A number of architectures provide for some form of conditional
10262 execution, or predication. The hallmark of this feature is the
10263 ability to nullify most of the instructions in the instruction set.
10264 When the instruction set is large and not entirely symmetric, it
10265 can be quite tedious to describe these forms directly in the
10266 @file{.md} file. An alternative is the @code{define_cond_exec} template.
10268 @findex define_cond_exec
10271 [@var{predicate-pattern}]
10273 "@var{output-template}"
10274 "@var{optional-insn-attribues}")
10277 @var{predicate-pattern} is the condition that must be true for the
10278 insn to be executed at runtime and should match a relational operator.
10279 One can use @code{match_operator} to match several relational operators
10280 at once. Any @code{match_operand} operands must have no more than one
10283 @var{condition} is a C expression that must be true for the generated
10286 @findex current_insn_predicate
10287 @var{output-template} is a string similar to the @code{define_insn}
10288 output template (@pxref{Output Template}), except that the @samp{*}
10289 and @samp{@@} special cases do not apply. This is only useful if the
10290 assembly text for the predicate is a simple prefix to the main insn.
10291 In order to handle the general case, there is a global variable
10292 @code{current_insn_predicate} that will contain the entire predicate
10293 if the current insn is predicated, and will otherwise be @code{NULL}.
10295 @var{optional-insn-attributes} is an optional vector of attributes that gets
10296 appended to the insn attributes of the produced cond_exec rtx. It can
10297 be used to add some distinguishing attribute to cond_exec rtxs produced
10298 that way. An example usage would be to use this attribute in conjunction
10299 with attributes on the main pattern to disable particular alternatives under
10300 certain conditions.
10302 When @code{define_cond_exec} is used, an implicit reference to
10303 the @code{predicable} instruction attribute is made.
10304 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
10305 exactly two elements in its @var{list-of-values}), with the possible
10306 values being @code{no} and @code{yes}. The default and all uses in
10307 the insns must be a simple constant, not a complex expressions. It
10308 may, however, depend on the alternative, by using a comma-separated
10309 list of values. If that is the case, the port should also define an
10310 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
10311 should also allow only @code{no} and @code{yes} as its values.
10313 For each @code{define_insn} for which the @code{predicable}
10314 attribute is true, a new @code{define_insn} pattern will be
10315 generated that matches a predicated version of the instruction.
10319 (define_insn "addsi"
10320 [(set (match_operand:SI 0 "register_operand" "r")
10321 (plus:SI (match_operand:SI 1 "register_operand" "r")
10322 (match_operand:SI 2 "register_operand" "r")))]
10327 [(ne (match_operand:CC 0 "register_operand" "c")
10334 generates a new pattern
10339 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
10340 (set (match_operand:SI 0 "register_operand" "r")
10341 (plus:SI (match_operand:SI 1 "register_operand" "r")
10342 (match_operand:SI 2 "register_operand" "r"))))]
10343 "(@var{test2}) && (@var{test1})"
10344 "(%3) add %2,%1,%0")
10350 @section RTL Templates Transformations
10351 @cindex define_subst
10353 For some hardware architectures there are common cases when the RTL
10354 templates for the instructions can be derived from the other RTL
10355 templates using simple transformations. E.g., @file{i386.md} contains
10356 an RTL template for the ordinary @code{sub} instruction---
10357 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
10358 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
10359 implemented by a single meta-template capable of generating a modified
10360 case based on the initial one:
10362 @findex define_subst
10364 (define_subst "@var{name}"
10365 [@var{input-template}]
10367 [@var{output-template}])
10369 @var{input-template} is a pattern describing the source RTL template,
10370 which will be transformed.
10372 @var{condition} is a C expression that is conjunct with the condition
10373 from the input-template to generate a condition to be used in the
10376 @var{output-template} is a pattern that will be used in the resulting
10379 @code{define_subst} mechanism is tightly coupled with the notion of the
10380 subst attribute (@pxref{Subst Iterators}). The use of
10381 @code{define_subst} is triggered by a reference to a subst attribute in
10382 the transforming RTL template. This reference initiates duplication of
10383 the source RTL template and substitution of the attributes with their
10384 values. The source RTL template is left unchanged, while the copy is
10385 transformed by @code{define_subst}. This transformation can fail in the
10386 case when the source RTL template is not matched against the
10387 input-template of the @code{define_subst}. In such case the copy is
10390 @code{define_subst} can be used only in @code{define_insn} and
10391 @code{define_expand}, it cannot be used in other expressions (e.g.@: in
10392 @code{define_insn_and_split}).
10395 * Define Subst Example:: Example of @code{define_subst} work.
10396 * Define Subst Pattern Matching:: Process of template comparison.
10397 * Define Subst Output Template:: Generation of output template.
10400 @node Define Subst Example
10401 @subsection @code{define_subst} Example
10402 @cindex define_subst
10404 To illustrate how @code{define_subst} works, let us examine a simple
10405 template transformation.
10407 Suppose there are two kinds of instructions: one that touches flags and
10408 the other that does not. The instructions of the second type could be
10409 generated with the following @code{define_subst}:
10412 (define_subst "add_clobber_subst"
10413 [(set (match_operand:SI 0 "" "")
10414 (match_operand:SI 1 "" ""))]
10416 [(set (match_dup 0)
10418 (clobber (reg:CC FLAGS_REG))]
10421 This @code{define_subst} can be applied to any RTL pattern containing
10422 @code{set} of mode SI and generates a copy with clobber when it is
10425 Assume there is an RTL template for a @code{max} instruction to be used
10426 in @code{define_subst} mentioned above:
10429 (define_insn "maxsi"
10430 [(set (match_operand:SI 0 "register_operand" "=r")
10432 (match_operand:SI 1 "register_operand" "r")
10433 (match_operand:SI 2 "register_operand" "r")))]
10435 "max\t@{%2, %1, %0|%0, %1, %2@}"
10439 To mark the RTL template for @code{define_subst} application,
10440 subst-attributes are used. They should be declared in advance:
10443 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
10446 Here @samp{add_clobber_name} is the attribute name,
10447 @samp{add_clobber_subst} is the name of the corresponding
10448 @code{define_subst}, the third argument (@samp{_noclobber}) is the
10449 attribute value that would be substituted into the unchanged version of
10450 the source RTL template, and the last argument (@samp{_clobber}) is the
10451 value that would be substituted into the second, transformed,
10452 version of the RTL template.
10454 Once the subst-attribute has been defined, it should be used in RTL
10455 templates which need to be processed by the @code{define_subst}. So,
10456 the original RTL template should be changed:
10459 (define_insn "maxsi<add_clobber_name>"
10460 [(set (match_operand:SI 0 "register_operand" "=r")
10462 (match_operand:SI 1 "register_operand" "r")
10463 (match_operand:SI 2 "register_operand" "r")))]
10465 "max\t@{%2, %1, %0|%0, %1, %2@}"
10469 The result of the @code{define_subst} usage would look like the following:
10472 (define_insn "maxsi_noclobber"
10473 [(set (match_operand:SI 0 "register_operand" "=r")
10475 (match_operand:SI 1 "register_operand" "r")
10476 (match_operand:SI 2 "register_operand" "r")))]
10478 "max\t@{%2, %1, %0|%0, %1, %2@}"
10480 (define_insn "maxsi_clobber"
10481 [(set (match_operand:SI 0 "register_operand" "=r")
10483 (match_operand:SI 1 "register_operand" "r")
10484 (match_operand:SI 2 "register_operand" "r")))
10485 (clobber (reg:CC FLAGS_REG))]
10487 "max\t@{%2, %1, %0|%0, %1, %2@}"
10491 @node Define Subst Pattern Matching
10492 @subsection Pattern Matching in @code{define_subst}
10493 @cindex define_subst
10495 All expressions, allowed in @code{define_insn} or @code{define_expand},
10496 are allowed in the input-template of @code{define_subst}, except
10497 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
10498 meanings of expressions in the input-template were changed:
10500 @code{match_operand} matches any expression (possibly, a subtree in
10501 RTL-template), if modes of the @code{match_operand} and this expression
10502 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
10503 this expression is @code{match_dup}, @code{match_op_dup}. If the
10504 expression is @code{match_operand} too, and predicate of
10505 @code{match_operand} from the input pattern is not empty, then the
10506 predicates are compared. That can be used for more accurate filtering
10507 of accepted RTL-templates.
10509 @code{match_operator} matches common operators (like @code{plus},
10510 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
10511 @code{match_operator}s from the original pattern if the modes match and
10512 @code{match_operator} from the input pattern has the same number of
10513 operands as the operator from the original pattern.
10515 @node Define Subst Output Template
10516 @subsection Generation of output template in @code{define_subst}
10517 @cindex define_subst
10519 If all necessary checks for @code{define_subst} application pass, a new
10520 RTL-pattern, based on the output-template, is created to replace the old
10521 template. Like in input-patterns, meanings of some RTL expressions are
10522 changed when they are used in output-patterns of a @code{define_subst}.
10523 Thus, @code{match_dup} is used for copying the whole expression from the
10524 original pattern, which matched corresponding @code{match_operand} from
10527 @code{match_dup N} is used in the output template to be replaced with
10528 the expression from the original pattern, which matched
10529 @code{match_operand N} from the input pattern. As a consequence,
10530 @code{match_dup} cannot be used to point to @code{match_operand}s from
10531 the output pattern, it should always refer to a @code{match_operand}
10532 from the input pattern. If a @code{match_dup N} occurs more than once
10533 in the output template, its first occurrence is replaced with the
10534 expression from the original pattern, and the subsequent expressions
10535 are replaced with @code{match_dup N}, i.e., a reference to the first
10538 In the output template one can refer to the expressions from the
10539 original pattern and create new ones. For instance, some operands could
10540 be added by means of standard @code{match_operand}.
10542 After replacing @code{match_dup} with some RTL-subtree from the original
10543 pattern, it could happen that several @code{match_operand}s in the
10544 output pattern have the same indexes. It is unknown, how many and what
10545 indexes would be used in the expression which would replace
10546 @code{match_dup}, so such conflicts in indexes are inevitable. To
10547 overcome this issue, @code{match_operands} and @code{match_operators},
10548 which were introduced into the output pattern, are renumerated when all
10549 @code{match_dup}s are replaced.
10551 Number of alternatives in @code{match_operand}s introduced into the
10552 output template @code{M} could differ from the number of alternatives in
10553 the original pattern @code{N}, so in the resultant pattern there would
10554 be @code{N*M} alternatives. Thus, constraints from the original pattern
10555 would be duplicated @code{N} times, constraints from the output pattern
10556 would be duplicated @code{M} times, producing all possible combinations.
10560 @node Constant Definitions
10561 @section Constant Definitions
10562 @cindex constant definitions
10563 @findex define_constants
10565 Using literal constants inside instruction patterns reduces legibility and
10566 can be a maintenance problem.
10568 To overcome this problem, you may use the @code{define_constants}
10569 expression. It contains a vector of name-value pairs. From that
10570 point on, wherever any of the names appears in the MD file, it is as
10571 if the corresponding value had been written instead. You may use
10572 @code{define_constants} multiple times; each appearance adds more
10573 constants to the table. It is an error to redefine a constant with
10576 To come back to the a29k load multiple example, instead of
10580 [(match_parallel 0 "load_multiple_operation"
10581 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10582 (match_operand:SI 2 "memory_operand" "m"))
10584 (clobber (reg:SI 179))])]
10592 (define_constants [
10600 [(match_parallel 0 "load_multiple_operation"
10601 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
10602 (match_operand:SI 2 "memory_operand" "m"))
10603 (use (reg:SI R_CR))
10604 (clobber (reg:SI R_CR))])]
10609 The constants that are defined with a define_constant are also output
10610 in the insn-codes.h header file as #defines.
10612 @cindex enumerations
10613 @findex define_c_enum
10614 You can also use the machine description file to define enumerations.
10615 Like the constants defined by @code{define_constant}, these enumerations
10616 are visible to both the machine description file and the main C code.
10618 The syntax is as follows:
10621 (define_c_enum "@var{name}" [
10629 This definition causes the equivalent of the following C code to appear
10630 in @file{insn-constants.h}:
10637 @var{valuen} = @var{n}
10639 #define NUM_@var{cname}_VALUES (@var{n} + 1)
10642 where @var{cname} is the capitalized form of @var{name}.
10643 It also makes each @var{valuei} available in the machine description
10644 file, just as if it had been declared with:
10647 (define_constants [(@var{valuei} @var{i})])
10650 Each @var{valuei} is usually an upper-case identifier and usually
10651 begins with @var{cname}.
10653 You can split the enumeration definition into as many statements as
10654 you like. The above example is directly equivalent to:
10657 (define_c_enum "@var{name}" [@var{value0}])
10658 (define_c_enum "@var{name}" [@var{value1}])
10660 (define_c_enum "@var{name}" [@var{valuen}])
10663 Splitting the enumeration helps to improve the modularity of each
10664 individual @code{.md} file. For example, if a port defines its
10665 synchronization instructions in a separate @file{sync.md} file,
10666 it is convenient to define all synchronization-specific enumeration
10667 values in @file{sync.md} rather than in the main @file{.md} file.
10669 Some enumeration names have special significance to GCC:
10673 @findex unspec_volatile
10674 If an enumeration called @code{unspecv} is defined, GCC will use it
10675 when printing out @code{unspec_volatile} expressions. For example:
10678 (define_c_enum "unspecv" [
10683 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
10686 (unspec_volatile ... UNSPECV_BLOCKAGE)
10691 If an enumeration called @code{unspec} is defined, GCC will use
10692 it when printing out @code{unspec} expressions. GCC will also use
10693 it when printing out @code{unspec_volatile} expressions unless an
10694 @code{unspecv} enumeration is also defined. You can therefore
10695 decide whether to keep separate enumerations for volatile and
10696 non-volatile expressions or whether to use the same enumeration
10700 @findex define_enum
10701 @anchor{define_enum}
10702 Another way of defining an enumeration is to use @code{define_enum}:
10705 (define_enum "@var{name}" [
10713 This directive implies:
10716 (define_c_enum "@var{name}" [
10717 @var{cname}_@var{cvalue0}
10718 @var{cname}_@var{cvalue1}
10720 @var{cname}_@var{cvaluen}
10724 @findex define_enum_attr
10725 where @var{cvaluei} is the capitalized form of @var{valuei}.
10726 However, unlike @code{define_c_enum}, the enumerations defined
10727 by @code{define_enum} can be used in attribute specifications
10728 (@pxref{define_enum_attr}).
10733 @cindex iterators in @file{.md} files
10735 Ports often need to define similar patterns for more than one machine
10736 mode or for more than one rtx code. GCC provides some simple iterator
10737 facilities to make this process easier.
10740 * Mode Iterators:: Generating variations of patterns for different modes.
10741 * Code Iterators:: Doing the same for codes.
10742 * Int Iterators:: Doing the same for integers.
10743 * Subst Iterators:: Generating variations of patterns for define_subst.
10744 * Parameterized Names:: Specifying iterator values in C++ code.
10747 @node Mode Iterators
10748 @subsection Mode Iterators
10749 @cindex mode iterators in @file{.md} files
10751 Ports often need to define similar patterns for two or more different modes.
10756 If a processor has hardware support for both single and double
10757 floating-point arithmetic, the @code{SFmode} patterns tend to be
10758 very similar to the @code{DFmode} ones.
10761 If a port uses @code{SImode} pointers in one configuration and
10762 @code{DImode} pointers in another, it will usually have very similar
10763 @code{SImode} and @code{DImode} patterns for manipulating pointers.
10766 Mode iterators allow several patterns to be instantiated from one
10767 @file{.md} file template. They can be used with any type of
10768 rtx-based construct, such as a @code{define_insn},
10769 @code{define_split}, or @code{define_peephole2}.
10772 * Defining Mode Iterators:: Defining a new mode iterator.
10773 * Substitutions:: Combining mode iterators with substitutions
10774 * Examples:: Examples
10777 @node Defining Mode Iterators
10778 @subsubsection Defining Mode Iterators
10779 @findex define_mode_iterator
10781 The syntax for defining a mode iterator is:
10784 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
10787 This allows subsequent @file{.md} file constructs to use the mode suffix
10788 @code{:@var{name}}. Every construct that does so will be expanded
10789 @var{n} times, once with every use of @code{:@var{name}} replaced by
10790 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
10791 and so on. In the expansion for a particular @var{modei}, every
10792 C condition will also require that @var{condi} be true.
10797 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10800 defines a new mode suffix @code{:P}. Every construct that uses
10801 @code{:P} will be expanded twice, once with every @code{:P} replaced
10802 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
10803 The @code{:SI} version will only apply if @code{Pmode == SImode} and
10804 the @code{:DI} version will only apply if @code{Pmode == DImode}.
10806 As with other @file{.md} conditions, an empty string is treated
10807 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
10808 to @code{@var{mode}}. For example:
10811 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10814 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
10815 but that the @code{:SI} expansion has no such constraint.
10817 Iterators are applied in the order they are defined. This can be
10818 significant if two iterators are used in a construct that requires
10819 substitutions. @xref{Substitutions}.
10821 @node Substitutions
10822 @subsubsection Substitution in Mode Iterators
10823 @findex define_mode_attr
10825 If an @file{.md} file construct uses mode iterators, each version of the
10826 construct will often need slightly different strings or modes. For
10831 When a @code{define_expand} defines several @code{add@var{m}3} patterns
10832 (@pxref{Standard Names}), each expander will need to use the
10833 appropriate mode name for @var{m}.
10836 When a @code{define_insn} defines several instruction patterns,
10837 each instruction will often use a different assembler mnemonic.
10840 When a @code{define_insn} requires operands with different modes,
10841 using an iterator for one of the operand modes usually requires a specific
10842 mode for the other operand(s).
10845 GCC supports such variations through a system of ``mode attributes''.
10846 There are two standard attributes: @code{mode}, which is the name of
10847 the mode in lower case, and @code{MODE}, which is the same thing in
10848 upper case. You can define other attributes using:
10851 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
10854 where @var{name} is the name of the attribute and @var{valuei}
10855 is the value associated with @var{modei}.
10857 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
10858 each string and mode in the pattern for sequences of the form
10859 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
10860 mode attribute. If the attribute is defined for @var{mode}, the whole
10861 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
10864 For example, suppose an @file{.md} file has:
10867 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10868 (define_mode_attr load [(SI "lw") (DI "ld")])
10871 If one of the patterns that uses @code{:P} contains the string
10872 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
10873 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
10874 @code{"ld\t%0,%1"}.
10876 Here is an example of using an attribute for a mode:
10879 (define_mode_iterator LONG [SI DI])
10880 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
10881 (define_insn @dots{}
10882 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
10885 The @code{@var{iterator}:} prefix may be omitted, in which case the
10886 substitution will be attempted for every iterator expansion.
10889 @subsubsection Mode Iterator Examples
10891 Here is an example from the MIPS port. It defines the following
10892 modes and attributes (among others):
10895 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10896 (define_mode_attr d [(SI "") (DI "d")])
10899 and uses the following template to define both @code{subsi3}
10903 (define_insn "sub<mode>3"
10904 [(set (match_operand:GPR 0 "register_operand" "=d")
10905 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
10906 (match_operand:GPR 2 "register_operand" "d")))]
10908 "<d>subu\t%0,%1,%2"
10909 [(set_attr "type" "arith")
10910 (set_attr "mode" "<MODE>")])
10913 This is exactly equivalent to:
10916 (define_insn "subsi3"
10917 [(set (match_operand:SI 0 "register_operand" "=d")
10918 (minus:SI (match_operand:SI 1 "register_operand" "d")
10919 (match_operand:SI 2 "register_operand" "d")))]
10922 [(set_attr "type" "arith")
10923 (set_attr "mode" "SI")])
10925 (define_insn "subdi3"
10926 [(set (match_operand:DI 0 "register_operand" "=d")
10927 (minus:DI (match_operand:DI 1 "register_operand" "d")
10928 (match_operand:DI 2 "register_operand" "d")))]
10931 [(set_attr "type" "arith")
10932 (set_attr "mode" "DI")])
10935 @node Code Iterators
10936 @subsection Code Iterators
10937 @cindex code iterators in @file{.md} files
10938 @findex define_code_iterator
10939 @findex define_code_attr
10941 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
10946 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
10949 defines a pseudo rtx code @var{name} that can be instantiated as
10950 @var{codei} if condition @var{condi} is true. Each @var{codei}
10951 must have the same rtx format. @xref{RTL Classes}.
10953 As with mode iterators, each pattern that uses @var{name} will be
10954 expanded @var{n} times, once with all uses of @var{name} replaced by
10955 @var{code1}, once with all uses replaced by @var{code2}, and so on.
10956 @xref{Defining Mode Iterators}.
10958 It is possible to define attributes for codes as well as for modes.
10959 There are two standard code attributes: @code{code}, the name of the
10960 code in lower case, and @code{CODE}, the name of the code in upper case.
10961 Other attributes are defined using:
10964 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
10967 Instruction patterns can use code attributes as rtx codes, which can be
10968 useful if two sets of codes act in tandem. For example, the following
10969 @code{define_insn} defines two patterns, one calculating a signed absolute
10970 difference and another calculating an unsigned absolute difference:
10973 (define_code_iterator any_max [smax umax])
10974 (define_code_attr paired_min [(smax "smin") (umax "umin")])
10975 (define_insn @dots{}
10976 [(set (match_operand:SI 0 @dots{})
10977 (minus:SI (any_max:SI (match_operand:SI 1 @dots{})
10978 (match_operand:SI 2 @dots{}))
10979 (<paired_min>:SI (match_dup 1) (match_dup 2))))]
10983 The signed version of the instruction uses @code{smax} and @code{smin}
10984 while the unsigned version uses @code{umax} and @code{umin}. There
10985 are no versions that pair @code{smax} with @code{umin} or @code{umax}
10988 Here's an example of code iterators in action, taken from the MIPS port:
10991 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
10992 eq ne gt ge lt le gtu geu ltu leu])
10994 (define_expand "b<code>"
10996 (if_then_else (any_cond:CC (cc0)
10998 (label_ref (match_operand 0 ""))
11002 gen_conditional_branch (operands, <CODE>);
11007 This is equivalent to:
11010 (define_expand "bunordered"
11012 (if_then_else (unordered:CC (cc0)
11014 (label_ref (match_operand 0 ""))
11018 gen_conditional_branch (operands, UNORDERED);
11022 (define_expand "bordered"
11024 (if_then_else (ordered:CC (cc0)
11026 (label_ref (match_operand 0 ""))
11030 gen_conditional_branch (operands, ORDERED);
11037 @node Int Iterators
11038 @subsection Int Iterators
11039 @cindex int iterators in @file{.md} files
11040 @findex define_int_iterator
11041 @findex define_int_attr
11043 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
11048 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
11051 defines a pseudo integer constant @var{name} that can be instantiated as
11052 @var{inti} if condition @var{condi} is true. Each @var{int}
11053 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
11054 in only those rtx fields that have 'i' as the specifier. This means that
11055 each @var{int} has to be a constant defined using define_constant or
11058 As with mode and code iterators, each pattern that uses @var{name} will be
11059 expanded @var{n} times, once with all uses of @var{name} replaced by
11060 @var{int1}, once with all uses replaced by @var{int2}, and so on.
11061 @xref{Defining Mode Iterators}.
11063 It is possible to define attributes for ints as well as for codes and modes.
11064 Attributes are defined using:
11067 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
11070 Here's an example of int iterators in action, taken from the ARM port:
11073 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
11075 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
11077 (define_insn "neon_vq<absneg><mode>"
11078 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11079 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11080 (match_operand:SI 2 "immediate_operand" "i")]
11083 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
11084 [(set_attr "type" "neon_vqneg_vqabs")]
11089 This is equivalent to:
11092 (define_insn "neon_vqabs<mode>"
11093 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11094 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11095 (match_operand:SI 2 "immediate_operand" "i")]
11098 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
11099 [(set_attr "type" "neon_vqneg_vqabs")]
11102 (define_insn "neon_vqneg<mode>"
11103 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11104 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11105 (match_operand:SI 2 "immediate_operand" "i")]
11108 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
11109 [(set_attr "type" "neon_vqneg_vqabs")]
11114 @node Subst Iterators
11115 @subsection Subst Iterators
11116 @cindex subst iterators in @file{.md} files
11117 @findex define_subst
11118 @findex define_subst_attr
11120 Subst iterators are special type of iterators with the following
11121 restrictions: they could not be declared explicitly, they always have
11122 only two values, and they do not have explicit dedicated name.
11123 Subst-iterators are triggered only when corresponding subst-attribute is
11124 used in RTL-pattern.
11126 Subst iterators transform templates in the following way: the templates
11127 are duplicated, the subst-attributes in these templates are replaced
11128 with the corresponding values, and a new attribute is implicitly added
11129 to the given @code{define_insn}/@code{define_expand}. The name of the
11130 added attribute matches the name of @code{define_subst}. Such
11131 attributes are declared implicitly, and it is not allowed to have a
11132 @code{define_attr} named as a @code{define_subst}.
11134 Each subst iterator is linked to a @code{define_subst}. It is declared
11135 implicitly by the first appearance of the corresponding
11136 @code{define_subst_attr}, and it is not allowed to define it explicitly.
11138 Declarations of subst-attributes have the following syntax:
11140 @findex define_subst_attr
11142 (define_subst_attr "@var{name}"
11144 "@var{no-subst-value}"
11145 "@var{subst-applied-value}")
11148 @var{name} is a string with which the given subst-attribute could be
11151 @var{subst-name} shows which @code{define_subst} should be applied to an
11152 RTL-template if the given subst-attribute is present in the
11155 @var{no-subst-value} is a value with which subst-attribute would be
11156 replaced in the first copy of the original RTL-template.
11158 @var{subst-applied-value} is a value with which subst-attribute would be
11159 replaced in the second copy of the original RTL-template.
11161 @node Parameterized Names
11162 @subsection Parameterized Names
11163 @cindex @samp{@@} in instruction pattern names
11164 Ports sometimes need to apply iterators using C++ code, in order to
11165 get the code or RTL pattern for a specific instruction. For example,
11166 suppose we have the @samp{neon_vq<absneg><mode>} pattern given above:
11169 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
11171 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
11173 (define_insn "neon_vq<absneg><mode>"
11174 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11175 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11176 (match_operand:SI 2 "immediate_operand" "i")]
11182 A port might need to generate this pattern for a variable
11183 @samp{QABSNEG} value and a variable @samp{VDQIW} mode. There are two
11184 ways of doing this. The first is to build the rtx for the pattern
11185 directly from C++ code; this is a valid technique and avoids any risk
11186 of combinatorial explosion. The second is to prefix the instruction
11187 name with the special character @samp{@@}, which tells GCC to generate
11188 the four additional functions below. In each case, @var{name} is the
11189 name of the instruction without the leading @samp{@@} character,
11190 without the @samp{<@dots{}>} placeholders, and with any underscore
11191 before a @samp{<@dots{}>} placeholder removed if keeping it would
11192 lead to a double or trailing underscore.
11195 @item insn_code maybe_code_for_@var{name} (@var{i1}, @var{i2}, @dots{})
11196 See whether replacing the first @samp{<@dots{}>} placeholder with
11197 iterator value @var{i1}, the second with iterator value @var{i2}, and
11198 so on, gives a valid instruction. Return its code if so, otherwise
11199 return @code{CODE_FOR_nothing}.
11201 @item insn_code code_for_@var{name} (@var{i1}, @var{i2}, @dots{})
11202 Same, but abort the compiler if the requested instruction does not exist.
11204 @item rtx maybe_gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{})
11205 Check for a valid instruction in the same way as
11206 @code{maybe_code_for_@var{name}}. If the instruction exists,
11207 generate an instance of it using the operand values given by @var{op0},
11208 @var{op1}, and so on, otherwise return null.
11210 @item rtx gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{})
11211 Same, but abort the compiler if the requested instruction does not exist,
11212 or if the instruction generator invoked the @code{FAIL} macro.
11215 For example, changing the pattern above to:
11218 (define_insn "@@neon_vq<absneg><mode>"
11219 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
11220 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
11221 (match_operand:SI 2 "immediate_operand" "i")]
11227 would define the same patterns as before, but in addition would generate
11228 the four functions below:
11231 insn_code maybe_code_for_neon_vq (int, machine_mode);
11232 insn_code code_for_neon_vq (int, machine_mode);
11233 rtx maybe_gen_neon_vq (int, machine_mode, rtx, rtx, rtx);
11234 rtx gen_neon_vq (int, machine_mode, rtx, rtx, rtx);
11237 Calling @samp{code_for_neon_vq (UNSPEC_VQABS, V8QImode)}
11238 would then give @code{CODE_FOR_neon_vqabsv8qi}.
11240 It is possible to have multiple @samp{@@} patterns with the same
11241 name and same types of iterator. For example:
11244 (define_insn "@@some_arithmetic_op<mode>"
11245 [(set (match_operand:INTEGER_MODES 0 "register_operand") @dots{})]
11249 (define_insn "@@some_arithmetic_op<mode>"
11250 [(set (match_operand:FLOAT_MODES 0 "register_operand") @dots{})]
11255 would produce a single set of functions that handles both
11256 @code{INTEGER_MODES} and @code{FLOAT_MODES}.