19276e23a2073b47e779442e1dda381ff3da357f
[gcc.git] / gcc / dwarf2cfi.c
1 /* Dwarf2 Call Frame Information helper routines.
2 Copyright (C) 1992-2013 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
10
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "tm.h"
24 #include "version.h"
25 #include "flags.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "stor-layout.h"
29 #include "function.h"
30 #include "basic-block.h"
31 #include "dwarf2.h"
32 #include "dwarf2out.h"
33 #include "dwarf2asm.h"
34 #include "ggc.h"
35 #include "hash-table.h"
36 #include "tm_p.h"
37 #include "target.h"
38 #include "common/common-target.h"
39 #include "tree-pass.h"
40
41 #include "except.h" /* expand_builtin_dwarf_sp_column */
42 #include "expr.h" /* init_return_column_size */
43 #include "regs.h" /* expand_builtin_init_dwarf_reg_sizes */
44 #include "output.h" /* asm_out_file */
45 #include "debug.h" /* dwarf2out_do_frame, dwarf2out_do_cfi_asm */
46
47
48 /* ??? Poison these here until it can be done generically. They've been
49 totally replaced in this file; make sure it stays that way. */
50 #undef DWARF2_UNWIND_INFO
51 #undef DWARF2_FRAME_INFO
52 #if (GCC_VERSION >= 3000)
53 #pragma GCC poison DWARF2_UNWIND_INFO DWARF2_FRAME_INFO
54 #endif
55
56 #ifndef INCOMING_RETURN_ADDR_RTX
57 #define INCOMING_RETURN_ADDR_RTX (gcc_unreachable (), NULL_RTX)
58 #endif
59
60 /* Maximum size (in bytes) of an artificially generated label. */
61 #define MAX_ARTIFICIAL_LABEL_BYTES 30
62 \f
63 /* A collected description of an entire row of the abstract CFI table. */
64 typedef struct GTY(()) dw_cfi_row_struct
65 {
66 /* The expression that computes the CFA, expressed in two different ways.
67 The CFA member for the simple cases, and the full CFI expression for
68 the complex cases. The later will be a DW_CFA_cfa_expression. */
69 dw_cfa_location cfa;
70 dw_cfi_ref cfa_cfi;
71
72 /* The expressions for any register column that is saved. */
73 cfi_vec reg_save;
74 } dw_cfi_row;
75
76 /* The caller's ORIG_REG is saved in SAVED_IN_REG. */
77 typedef struct GTY(()) reg_saved_in_data_struct {
78 rtx orig_reg;
79 rtx saved_in_reg;
80 } reg_saved_in_data;
81
82
83 /* Since we no longer have a proper CFG, we're going to create a facsimile
84 of one on the fly while processing the frame-related insns.
85
86 We create dw_trace_info structures for each extended basic block beginning
87 and ending at a "save point". Save points are labels, barriers, certain
88 notes, and of course the beginning and end of the function.
89
90 As we encounter control transfer insns, we propagate the "current"
91 row state across the edges to the starts of traces. When checking is
92 enabled, we validate that we propagate the same data from all sources.
93
94 All traces are members of the TRACE_INFO array, in the order in which
95 they appear in the instruction stream.
96
97 All save points are present in the TRACE_INDEX hash, mapping the insn
98 starting a trace to the dw_trace_info describing the trace. */
99
100 typedef struct
101 {
102 /* The insn that begins the trace. */
103 rtx head;
104
105 /* The row state at the beginning and end of the trace. */
106 dw_cfi_row *beg_row, *end_row;
107
108 /* Tracking for DW_CFA_GNU_args_size. The "true" sizes are those we find
109 while scanning insns. However, the args_size value is irrelevant at
110 any point except can_throw_internal_p insns. Therefore the "delay"
111 sizes the values that must actually be emitted for this trace. */
112 HOST_WIDE_INT beg_true_args_size, end_true_args_size;
113 HOST_WIDE_INT beg_delay_args_size, end_delay_args_size;
114
115 /* The first EH insn in the trace, where beg_delay_args_size must be set. */
116 rtx eh_head;
117
118 /* The following variables contain data used in interpreting frame related
119 expressions. These are not part of the "real" row state as defined by
120 Dwarf, but it seems like they need to be propagated into a trace in case
121 frame related expressions have been sunk. */
122 /* ??? This seems fragile. These variables are fragments of a larger
123 expression. If we do not keep the entire expression together, we risk
124 not being able to put it together properly. Consider forcing targets
125 to generate self-contained expressions and dropping all of the magic
126 interpretation code in this file. Or at least refusing to shrink wrap
127 any frame related insn that doesn't contain a complete expression. */
128
129 /* The register used for saving registers to the stack, and its offset
130 from the CFA. */
131 dw_cfa_location cfa_store;
132
133 /* A temporary register holding an integral value used in adjusting SP
134 or setting up the store_reg. The "offset" field holds the integer
135 value, not an offset. */
136 dw_cfa_location cfa_temp;
137
138 /* A set of registers saved in other registers. This is the inverse of
139 the row->reg_save info, if the entry is a DW_CFA_register. This is
140 implemented as a flat array because it normally contains zero or 1
141 entry, depending on the target. IA-64 is the big spender here, using
142 a maximum of 5 entries. */
143 vec<reg_saved_in_data> regs_saved_in_regs;
144
145 /* An identifier for this trace. Used only for debugging dumps. */
146 unsigned id;
147
148 /* True if this trace immediately follows NOTE_INSN_SWITCH_TEXT_SECTIONS. */
149 bool switch_sections;
150
151 /* True if we've seen different values incoming to beg_true_args_size. */
152 bool args_size_undefined;
153 } dw_trace_info;
154
155
156 typedef dw_trace_info *dw_trace_info_ref;
157
158
159 /* Hashtable helpers. */
160
161 struct trace_info_hasher : typed_noop_remove <dw_trace_info>
162 {
163 typedef dw_trace_info value_type;
164 typedef dw_trace_info compare_type;
165 static inline hashval_t hash (const value_type *);
166 static inline bool equal (const value_type *, const compare_type *);
167 };
168
169 inline hashval_t
170 trace_info_hasher::hash (const value_type *ti)
171 {
172 return INSN_UID (ti->head);
173 }
174
175 inline bool
176 trace_info_hasher::equal (const value_type *a, const compare_type *b)
177 {
178 return a->head == b->head;
179 }
180
181
182 /* The variables making up the pseudo-cfg, as described above. */
183 static vec<dw_trace_info> trace_info;
184 static vec<dw_trace_info_ref> trace_work_list;
185 static hash_table <trace_info_hasher> trace_index;
186
187 /* A vector of call frame insns for the CIE. */
188 cfi_vec cie_cfi_vec;
189
190 /* The state of the first row of the FDE table, which includes the
191 state provided by the CIE. */
192 static GTY(()) dw_cfi_row *cie_cfi_row;
193
194 static GTY(()) reg_saved_in_data *cie_return_save;
195
196 static GTY(()) unsigned long dwarf2out_cfi_label_num;
197
198 /* The insn after which a new CFI note should be emitted. */
199 static rtx add_cfi_insn;
200
201 /* When non-null, add_cfi will add the CFI to this vector. */
202 static cfi_vec *add_cfi_vec;
203
204 /* The current instruction trace. */
205 static dw_trace_info *cur_trace;
206
207 /* The current, i.e. most recently generated, row of the CFI table. */
208 static dw_cfi_row *cur_row;
209
210 /* A copy of the current CFA, for use during the processing of a
211 single insn. */
212 static dw_cfa_location *cur_cfa;
213
214 /* We delay emitting a register save until either (a) we reach the end
215 of the prologue or (b) the register is clobbered. This clusters
216 register saves so that there are fewer pc advances. */
217
218 typedef struct {
219 rtx reg;
220 rtx saved_reg;
221 HOST_WIDE_INT cfa_offset;
222 } queued_reg_save;
223
224
225 static vec<queued_reg_save> queued_reg_saves;
226
227 /* True if any CFI directives were emitted at the current insn. */
228 static bool any_cfis_emitted;
229
230 /* Short-hand for commonly used register numbers. */
231 static unsigned dw_stack_pointer_regnum;
232 static unsigned dw_frame_pointer_regnum;
233 \f
234 /* Hook used by __throw. */
235
236 rtx
237 expand_builtin_dwarf_sp_column (void)
238 {
239 unsigned int dwarf_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM);
240 return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum, 1));
241 }
242
243 /* MEM is a memory reference for the register size table, each element of
244 which has mode MODE. Initialize column C as a return address column. */
245
246 static void
247 init_return_column_size (enum machine_mode mode, rtx mem, unsigned int c)
248 {
249 HOST_WIDE_INT offset = c * GET_MODE_SIZE (mode);
250 HOST_WIDE_INT size = GET_MODE_SIZE (Pmode);
251 emit_move_insn (adjust_address (mem, mode, offset),
252 gen_int_mode (size, mode));
253 }
254
255 /* Generate code to initialize the register size table. */
256
257 void
258 expand_builtin_init_dwarf_reg_sizes (tree address)
259 {
260 unsigned int i;
261 enum machine_mode mode = TYPE_MODE (char_type_node);
262 rtx addr = expand_normal (address);
263 rtx mem = gen_rtx_MEM (BLKmode, addr);
264 bool wrote_return_column = false;
265
266 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
267 {
268 unsigned int dnum = DWARF_FRAME_REGNUM (i);
269 unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1);
270
271 if (rnum < DWARF_FRAME_REGISTERS)
272 {
273 HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode);
274 enum machine_mode save_mode = reg_raw_mode[i];
275 HOST_WIDE_INT size;
276
277 if (HARD_REGNO_CALL_PART_CLOBBERED (i, save_mode))
278 save_mode = choose_hard_reg_mode (i, 1, true);
279 if (dnum == DWARF_FRAME_RETURN_COLUMN)
280 {
281 if (save_mode == VOIDmode)
282 continue;
283 wrote_return_column = true;
284 }
285 size = GET_MODE_SIZE (save_mode);
286 if (offset < 0)
287 continue;
288
289 emit_move_insn (adjust_address (mem, mode, offset),
290 gen_int_mode (size, mode));
291 }
292 }
293
294 if (!wrote_return_column)
295 init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN);
296
297 #ifdef DWARF_ALT_FRAME_RETURN_COLUMN
298 init_return_column_size (mode, mem, DWARF_ALT_FRAME_RETURN_COLUMN);
299 #endif
300
301 targetm.init_dwarf_reg_sizes_extra (address);
302 }
303
304 \f
305 static dw_trace_info *
306 get_trace_info (rtx insn)
307 {
308 dw_trace_info dummy;
309 dummy.head = insn;
310 return trace_index.find_with_hash (&dummy, INSN_UID (insn));
311 }
312
313 static bool
314 save_point_p (rtx insn)
315 {
316 /* Labels, except those that are really jump tables. */
317 if (LABEL_P (insn))
318 return inside_basic_block_p (insn);
319
320 /* We split traces at the prologue/epilogue notes because those
321 are points at which the unwind info is usually stable. This
322 makes it easier to find spots with identical unwind info so
323 that we can use remember/restore_state opcodes. */
324 if (NOTE_P (insn))
325 switch (NOTE_KIND (insn))
326 {
327 case NOTE_INSN_PROLOGUE_END:
328 case NOTE_INSN_EPILOGUE_BEG:
329 return true;
330 }
331
332 return false;
333 }
334
335 /* Divide OFF by DWARF_CIE_DATA_ALIGNMENT, asserting no remainder. */
336
337 static inline HOST_WIDE_INT
338 div_data_align (HOST_WIDE_INT off)
339 {
340 HOST_WIDE_INT r = off / DWARF_CIE_DATA_ALIGNMENT;
341 gcc_assert (r * DWARF_CIE_DATA_ALIGNMENT == off);
342 return r;
343 }
344
345 /* Return true if we need a signed version of a given opcode
346 (e.g. DW_CFA_offset_extended_sf vs DW_CFA_offset_extended). */
347
348 static inline bool
349 need_data_align_sf_opcode (HOST_WIDE_INT off)
350 {
351 return DWARF_CIE_DATA_ALIGNMENT < 0 ? off > 0 : off < 0;
352 }
353
354 /* Return a pointer to a newly allocated Call Frame Instruction. */
355
356 static inline dw_cfi_ref
357 new_cfi (void)
358 {
359 dw_cfi_ref cfi = ggc_alloc_dw_cfi_node ();
360
361 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = 0;
362 cfi->dw_cfi_oprnd2.dw_cfi_reg_num = 0;
363
364 return cfi;
365 }
366
367 /* Return a newly allocated CFI row, with no defined data. */
368
369 static dw_cfi_row *
370 new_cfi_row (void)
371 {
372 dw_cfi_row *row = ggc_alloc_cleared_dw_cfi_row ();
373
374 row->cfa.reg = INVALID_REGNUM;
375
376 return row;
377 }
378
379 /* Return a copy of an existing CFI row. */
380
381 static dw_cfi_row *
382 copy_cfi_row (dw_cfi_row *src)
383 {
384 dw_cfi_row *dst = ggc_alloc_dw_cfi_row ();
385
386 *dst = *src;
387 dst->reg_save = vec_safe_copy (src->reg_save);
388
389 return dst;
390 }
391
392 /* Generate a new label for the CFI info to refer to. */
393
394 static char *
395 dwarf2out_cfi_label (void)
396 {
397 int num = dwarf2out_cfi_label_num++;
398 char label[20];
399
400 ASM_GENERATE_INTERNAL_LABEL (label, "LCFI", num);
401
402 return xstrdup (label);
403 }
404
405 /* Add CFI either to the current insn stream or to a vector, or both. */
406
407 static void
408 add_cfi (dw_cfi_ref cfi)
409 {
410 any_cfis_emitted = true;
411
412 if (add_cfi_insn != NULL)
413 {
414 add_cfi_insn = emit_note_after (NOTE_INSN_CFI, add_cfi_insn);
415 NOTE_CFI (add_cfi_insn) = cfi;
416 }
417
418 if (add_cfi_vec != NULL)
419 vec_safe_push (*add_cfi_vec, cfi);
420 }
421
422 static void
423 add_cfi_args_size (HOST_WIDE_INT size)
424 {
425 dw_cfi_ref cfi = new_cfi ();
426
427 /* While we can occasionally have args_size < 0 internally, this state
428 should not persist at a point we actually need an opcode. */
429 gcc_assert (size >= 0);
430
431 cfi->dw_cfi_opc = DW_CFA_GNU_args_size;
432 cfi->dw_cfi_oprnd1.dw_cfi_offset = size;
433
434 add_cfi (cfi);
435 }
436
437 static void
438 add_cfi_restore (unsigned reg)
439 {
440 dw_cfi_ref cfi = new_cfi ();
441
442 cfi->dw_cfi_opc = (reg & ~0x3f ? DW_CFA_restore_extended : DW_CFA_restore);
443 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
444
445 add_cfi (cfi);
446 }
447
448 /* Perform ROW->REG_SAVE[COLUMN] = CFI. CFI may be null, indicating
449 that the register column is no longer saved. */
450
451 static void
452 update_row_reg_save (dw_cfi_row *row, unsigned column, dw_cfi_ref cfi)
453 {
454 if (vec_safe_length (row->reg_save) <= column)
455 vec_safe_grow_cleared (row->reg_save, column + 1);
456 (*row->reg_save)[column] = cfi;
457 }
458
459 /* This function fills in aa dw_cfa_location structure from a dwarf location
460 descriptor sequence. */
461
462 static void
463 get_cfa_from_loc_descr (dw_cfa_location *cfa, struct dw_loc_descr_struct *loc)
464 {
465 struct dw_loc_descr_struct *ptr;
466 cfa->offset = 0;
467 cfa->base_offset = 0;
468 cfa->indirect = 0;
469 cfa->reg = -1;
470
471 for (ptr = loc; ptr != NULL; ptr = ptr->dw_loc_next)
472 {
473 enum dwarf_location_atom op = ptr->dw_loc_opc;
474
475 switch (op)
476 {
477 case DW_OP_reg0:
478 case DW_OP_reg1:
479 case DW_OP_reg2:
480 case DW_OP_reg3:
481 case DW_OP_reg4:
482 case DW_OP_reg5:
483 case DW_OP_reg6:
484 case DW_OP_reg7:
485 case DW_OP_reg8:
486 case DW_OP_reg9:
487 case DW_OP_reg10:
488 case DW_OP_reg11:
489 case DW_OP_reg12:
490 case DW_OP_reg13:
491 case DW_OP_reg14:
492 case DW_OP_reg15:
493 case DW_OP_reg16:
494 case DW_OP_reg17:
495 case DW_OP_reg18:
496 case DW_OP_reg19:
497 case DW_OP_reg20:
498 case DW_OP_reg21:
499 case DW_OP_reg22:
500 case DW_OP_reg23:
501 case DW_OP_reg24:
502 case DW_OP_reg25:
503 case DW_OP_reg26:
504 case DW_OP_reg27:
505 case DW_OP_reg28:
506 case DW_OP_reg29:
507 case DW_OP_reg30:
508 case DW_OP_reg31:
509 cfa->reg = op - DW_OP_reg0;
510 break;
511 case DW_OP_regx:
512 cfa->reg = ptr->dw_loc_oprnd1.v.val_int;
513 break;
514 case DW_OP_breg0:
515 case DW_OP_breg1:
516 case DW_OP_breg2:
517 case DW_OP_breg3:
518 case DW_OP_breg4:
519 case DW_OP_breg5:
520 case DW_OP_breg6:
521 case DW_OP_breg7:
522 case DW_OP_breg8:
523 case DW_OP_breg9:
524 case DW_OP_breg10:
525 case DW_OP_breg11:
526 case DW_OP_breg12:
527 case DW_OP_breg13:
528 case DW_OP_breg14:
529 case DW_OP_breg15:
530 case DW_OP_breg16:
531 case DW_OP_breg17:
532 case DW_OP_breg18:
533 case DW_OP_breg19:
534 case DW_OP_breg20:
535 case DW_OP_breg21:
536 case DW_OP_breg22:
537 case DW_OP_breg23:
538 case DW_OP_breg24:
539 case DW_OP_breg25:
540 case DW_OP_breg26:
541 case DW_OP_breg27:
542 case DW_OP_breg28:
543 case DW_OP_breg29:
544 case DW_OP_breg30:
545 case DW_OP_breg31:
546 cfa->reg = op - DW_OP_breg0;
547 cfa->base_offset = ptr->dw_loc_oprnd1.v.val_int;
548 break;
549 case DW_OP_bregx:
550 cfa->reg = ptr->dw_loc_oprnd1.v.val_int;
551 cfa->base_offset = ptr->dw_loc_oprnd2.v.val_int;
552 break;
553 case DW_OP_deref:
554 cfa->indirect = 1;
555 break;
556 case DW_OP_plus_uconst:
557 cfa->offset = ptr->dw_loc_oprnd1.v.val_unsigned;
558 break;
559 default:
560 gcc_unreachable ();
561 }
562 }
563 }
564
565 /* Find the previous value for the CFA, iteratively. CFI is the opcode
566 to interpret, *LOC will be updated as necessary, *REMEMBER is used for
567 one level of remember/restore state processing. */
568
569 void
570 lookup_cfa_1 (dw_cfi_ref cfi, dw_cfa_location *loc, dw_cfa_location *remember)
571 {
572 switch (cfi->dw_cfi_opc)
573 {
574 case DW_CFA_def_cfa_offset:
575 case DW_CFA_def_cfa_offset_sf:
576 loc->offset = cfi->dw_cfi_oprnd1.dw_cfi_offset;
577 break;
578 case DW_CFA_def_cfa_register:
579 loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num;
580 break;
581 case DW_CFA_def_cfa:
582 case DW_CFA_def_cfa_sf:
583 loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num;
584 loc->offset = cfi->dw_cfi_oprnd2.dw_cfi_offset;
585 break;
586 case DW_CFA_def_cfa_expression:
587 get_cfa_from_loc_descr (loc, cfi->dw_cfi_oprnd1.dw_cfi_loc);
588 break;
589
590 case DW_CFA_remember_state:
591 gcc_assert (!remember->in_use);
592 *remember = *loc;
593 remember->in_use = 1;
594 break;
595 case DW_CFA_restore_state:
596 gcc_assert (remember->in_use);
597 *loc = *remember;
598 remember->in_use = 0;
599 break;
600
601 default:
602 break;
603 }
604 }
605
606 /* Determine if two dw_cfa_location structures define the same data. */
607
608 bool
609 cfa_equal_p (const dw_cfa_location *loc1, const dw_cfa_location *loc2)
610 {
611 return (loc1->reg == loc2->reg
612 && loc1->offset == loc2->offset
613 && loc1->indirect == loc2->indirect
614 && (loc1->indirect == 0
615 || loc1->base_offset == loc2->base_offset));
616 }
617
618 /* Determine if two CFI operands are identical. */
619
620 static bool
621 cfi_oprnd_equal_p (enum dw_cfi_oprnd_type t, dw_cfi_oprnd *a, dw_cfi_oprnd *b)
622 {
623 switch (t)
624 {
625 case dw_cfi_oprnd_unused:
626 return true;
627 case dw_cfi_oprnd_reg_num:
628 return a->dw_cfi_reg_num == b->dw_cfi_reg_num;
629 case dw_cfi_oprnd_offset:
630 return a->dw_cfi_offset == b->dw_cfi_offset;
631 case dw_cfi_oprnd_addr:
632 return (a->dw_cfi_addr == b->dw_cfi_addr
633 || strcmp (a->dw_cfi_addr, b->dw_cfi_addr) == 0);
634 case dw_cfi_oprnd_loc:
635 return loc_descr_equal_p (a->dw_cfi_loc, b->dw_cfi_loc);
636 }
637 gcc_unreachable ();
638 }
639
640 /* Determine if two CFI entries are identical. */
641
642 static bool
643 cfi_equal_p (dw_cfi_ref a, dw_cfi_ref b)
644 {
645 enum dwarf_call_frame_info opc;
646
647 /* Make things easier for our callers, including missing operands. */
648 if (a == b)
649 return true;
650 if (a == NULL || b == NULL)
651 return false;
652
653 /* Obviously, the opcodes must match. */
654 opc = a->dw_cfi_opc;
655 if (opc != b->dw_cfi_opc)
656 return false;
657
658 /* Compare the two operands, re-using the type of the operands as
659 already exposed elsewhere. */
660 return (cfi_oprnd_equal_p (dw_cfi_oprnd1_desc (opc),
661 &a->dw_cfi_oprnd1, &b->dw_cfi_oprnd1)
662 && cfi_oprnd_equal_p (dw_cfi_oprnd2_desc (opc),
663 &a->dw_cfi_oprnd2, &b->dw_cfi_oprnd2));
664 }
665
666 /* Determine if two CFI_ROW structures are identical. */
667
668 static bool
669 cfi_row_equal_p (dw_cfi_row *a, dw_cfi_row *b)
670 {
671 size_t i, n_a, n_b, n_max;
672
673 if (a->cfa_cfi)
674 {
675 if (!cfi_equal_p (a->cfa_cfi, b->cfa_cfi))
676 return false;
677 }
678 else if (!cfa_equal_p (&a->cfa, &b->cfa))
679 return false;
680
681 n_a = vec_safe_length (a->reg_save);
682 n_b = vec_safe_length (b->reg_save);
683 n_max = MAX (n_a, n_b);
684
685 for (i = 0; i < n_max; ++i)
686 {
687 dw_cfi_ref r_a = NULL, r_b = NULL;
688
689 if (i < n_a)
690 r_a = (*a->reg_save)[i];
691 if (i < n_b)
692 r_b = (*b->reg_save)[i];
693
694 if (!cfi_equal_p (r_a, r_b))
695 return false;
696 }
697
698 return true;
699 }
700
701 /* The CFA is now calculated from NEW_CFA. Consider OLD_CFA in determining
702 what opcode to emit. Returns the CFI opcode to effect the change, or
703 NULL if NEW_CFA == OLD_CFA. */
704
705 static dw_cfi_ref
706 def_cfa_0 (dw_cfa_location *old_cfa, dw_cfa_location *new_cfa)
707 {
708 dw_cfi_ref cfi;
709
710 /* If nothing changed, no need to issue any call frame instructions. */
711 if (cfa_equal_p (old_cfa, new_cfa))
712 return NULL;
713
714 cfi = new_cfi ();
715
716 if (new_cfa->reg == old_cfa->reg && !new_cfa->indirect && !old_cfa->indirect)
717 {
718 /* Construct a "DW_CFA_def_cfa_offset <offset>" instruction, indicating
719 the CFA register did not change but the offset did. The data
720 factoring for DW_CFA_def_cfa_offset_sf happens in output_cfi, or
721 in the assembler via the .cfi_def_cfa_offset directive. */
722 if (new_cfa->offset < 0)
723 cfi->dw_cfi_opc = DW_CFA_def_cfa_offset_sf;
724 else
725 cfi->dw_cfi_opc = DW_CFA_def_cfa_offset;
726 cfi->dw_cfi_oprnd1.dw_cfi_offset = new_cfa->offset;
727 }
728 else if (new_cfa->offset == old_cfa->offset
729 && old_cfa->reg != INVALID_REGNUM
730 && !new_cfa->indirect
731 && !old_cfa->indirect)
732 {
733 /* Construct a "DW_CFA_def_cfa_register <register>" instruction,
734 indicating the CFA register has changed to <register> but the
735 offset has not changed. */
736 cfi->dw_cfi_opc = DW_CFA_def_cfa_register;
737 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg;
738 }
739 else if (new_cfa->indirect == 0)
740 {
741 /* Construct a "DW_CFA_def_cfa <register> <offset>" instruction,
742 indicating the CFA register has changed to <register> with
743 the specified offset. The data factoring for DW_CFA_def_cfa_sf
744 happens in output_cfi, or in the assembler via the .cfi_def_cfa
745 directive. */
746 if (new_cfa->offset < 0)
747 cfi->dw_cfi_opc = DW_CFA_def_cfa_sf;
748 else
749 cfi->dw_cfi_opc = DW_CFA_def_cfa;
750 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg;
751 cfi->dw_cfi_oprnd2.dw_cfi_offset = new_cfa->offset;
752 }
753 else
754 {
755 /* Construct a DW_CFA_def_cfa_expression instruction to
756 calculate the CFA using a full location expression since no
757 register-offset pair is available. */
758 struct dw_loc_descr_struct *loc_list;
759
760 cfi->dw_cfi_opc = DW_CFA_def_cfa_expression;
761 loc_list = build_cfa_loc (new_cfa, 0);
762 cfi->dw_cfi_oprnd1.dw_cfi_loc = loc_list;
763 }
764
765 return cfi;
766 }
767
768 /* Similarly, but take OLD_CFA from CUR_ROW, and update it after the fact. */
769
770 static void
771 def_cfa_1 (dw_cfa_location *new_cfa)
772 {
773 dw_cfi_ref cfi;
774
775 if (cur_trace->cfa_store.reg == new_cfa->reg && new_cfa->indirect == 0)
776 cur_trace->cfa_store.offset = new_cfa->offset;
777
778 cfi = def_cfa_0 (&cur_row->cfa, new_cfa);
779 if (cfi)
780 {
781 cur_row->cfa = *new_cfa;
782 cur_row->cfa_cfi = (cfi->dw_cfi_opc == DW_CFA_def_cfa_expression
783 ? cfi : NULL);
784
785 add_cfi (cfi);
786 }
787 }
788
789 /* Add the CFI for saving a register. REG is the CFA column number.
790 If SREG is -1, the register is saved at OFFSET from the CFA;
791 otherwise it is saved in SREG. */
792
793 static void
794 reg_save (unsigned int reg, unsigned int sreg, HOST_WIDE_INT offset)
795 {
796 dw_fde_ref fde = cfun ? cfun->fde : NULL;
797 dw_cfi_ref cfi = new_cfi ();
798
799 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
800
801 /* When stack is aligned, store REG using DW_CFA_expression with FP. */
802 if (fde
803 && fde->stack_realign
804 && sreg == INVALID_REGNUM)
805 {
806 cfi->dw_cfi_opc = DW_CFA_expression;
807 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
808 cfi->dw_cfi_oprnd2.dw_cfi_loc
809 = build_cfa_aligned_loc (&cur_row->cfa, offset,
810 fde->stack_realignment);
811 }
812 else if (sreg == INVALID_REGNUM)
813 {
814 if (need_data_align_sf_opcode (offset))
815 cfi->dw_cfi_opc = DW_CFA_offset_extended_sf;
816 else if (reg & ~0x3f)
817 cfi->dw_cfi_opc = DW_CFA_offset_extended;
818 else
819 cfi->dw_cfi_opc = DW_CFA_offset;
820 cfi->dw_cfi_oprnd2.dw_cfi_offset = offset;
821 }
822 else if (sreg == reg)
823 {
824 /* While we could emit something like DW_CFA_same_value or
825 DW_CFA_restore, we never expect to see something like that
826 in a prologue. This is more likely to be a bug. A backend
827 can always bypass this by using REG_CFA_RESTORE directly. */
828 gcc_unreachable ();
829 }
830 else
831 {
832 cfi->dw_cfi_opc = DW_CFA_register;
833 cfi->dw_cfi_oprnd2.dw_cfi_reg_num = sreg;
834 }
835
836 add_cfi (cfi);
837 update_row_reg_save (cur_row, reg, cfi);
838 }
839
840 /* A subroutine of scan_trace. Check INSN for a REG_ARGS_SIZE note
841 and adjust data structures to match. */
842
843 static void
844 notice_args_size (rtx insn)
845 {
846 HOST_WIDE_INT args_size, delta;
847 rtx note;
848
849 note = find_reg_note (insn, REG_ARGS_SIZE, NULL);
850 if (note == NULL)
851 return;
852
853 args_size = INTVAL (XEXP (note, 0));
854 delta = args_size - cur_trace->end_true_args_size;
855 if (delta == 0)
856 return;
857
858 cur_trace->end_true_args_size = args_size;
859
860 /* If the CFA is computed off the stack pointer, then we must adjust
861 the computation of the CFA as well. */
862 if (cur_cfa->reg == dw_stack_pointer_regnum)
863 {
864 gcc_assert (!cur_cfa->indirect);
865
866 /* Convert a change in args_size (always a positive in the
867 direction of stack growth) to a change in stack pointer. */
868 #ifndef STACK_GROWS_DOWNWARD
869 delta = -delta;
870 #endif
871 cur_cfa->offset += delta;
872 }
873 }
874
875 /* A subroutine of scan_trace. INSN is can_throw_internal. Update the
876 data within the trace related to EH insns and args_size. */
877
878 static void
879 notice_eh_throw (rtx insn)
880 {
881 HOST_WIDE_INT args_size;
882
883 args_size = cur_trace->end_true_args_size;
884 if (cur_trace->eh_head == NULL)
885 {
886 cur_trace->eh_head = insn;
887 cur_trace->beg_delay_args_size = args_size;
888 cur_trace->end_delay_args_size = args_size;
889 }
890 else if (cur_trace->end_delay_args_size != args_size)
891 {
892 cur_trace->end_delay_args_size = args_size;
893
894 /* ??? If the CFA is the stack pointer, search backward for the last
895 CFI note and insert there. Given that the stack changed for the
896 args_size change, there *must* be such a note in between here and
897 the last eh insn. */
898 add_cfi_args_size (args_size);
899 }
900 }
901
902 /* Short-hand inline for the very common D_F_R (REGNO (x)) operation. */
903 /* ??? This ought to go into dwarf2out.h, except that dwarf2out.h is
904 used in places where rtl is prohibited. */
905
906 static inline unsigned
907 dwf_regno (const_rtx reg)
908 {
909 return DWARF_FRAME_REGNUM (REGNO (reg));
910 }
911
912 /* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */
913
914 static bool
915 compare_reg_or_pc (rtx x, rtx y)
916 {
917 if (REG_P (x) && REG_P (y))
918 return REGNO (x) == REGNO (y);
919 return x == y;
920 }
921
922 /* Record SRC as being saved in DEST. DEST may be null to delete an
923 existing entry. SRC may be a register or PC_RTX. */
924
925 static void
926 record_reg_saved_in_reg (rtx dest, rtx src)
927 {
928 reg_saved_in_data *elt;
929 size_t i;
930
931 FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, elt)
932 if (compare_reg_or_pc (elt->orig_reg, src))
933 {
934 if (dest == NULL)
935 cur_trace->regs_saved_in_regs.unordered_remove (i);
936 else
937 elt->saved_in_reg = dest;
938 return;
939 }
940
941 if (dest == NULL)
942 return;
943
944 reg_saved_in_data e = {src, dest};
945 cur_trace->regs_saved_in_regs.safe_push (e);
946 }
947
948 /* Add an entry to QUEUED_REG_SAVES saying that REG is now saved at
949 SREG, or if SREG is NULL then it is saved at OFFSET to the CFA. */
950
951 static void
952 queue_reg_save (rtx reg, rtx sreg, HOST_WIDE_INT offset)
953 {
954 queued_reg_save *q;
955 queued_reg_save e = {reg, sreg, offset};
956 size_t i;
957
958 /* Duplicates waste space, but it's also necessary to remove them
959 for correctness, since the queue gets output in reverse order. */
960 FOR_EACH_VEC_ELT (queued_reg_saves, i, q)
961 if (compare_reg_or_pc (q->reg, reg))
962 {
963 *q = e;
964 return;
965 }
966
967 queued_reg_saves.safe_push (e);
968 }
969
970 /* Output all the entries in QUEUED_REG_SAVES. */
971
972 static void
973 dwarf2out_flush_queued_reg_saves (void)
974 {
975 queued_reg_save *q;
976 size_t i;
977
978 FOR_EACH_VEC_ELT (queued_reg_saves, i, q)
979 {
980 unsigned int reg, sreg;
981
982 record_reg_saved_in_reg (q->saved_reg, q->reg);
983
984 if (q->reg == pc_rtx)
985 reg = DWARF_FRAME_RETURN_COLUMN;
986 else
987 reg = dwf_regno (q->reg);
988 if (q->saved_reg)
989 sreg = dwf_regno (q->saved_reg);
990 else
991 sreg = INVALID_REGNUM;
992 reg_save (reg, sreg, q->cfa_offset);
993 }
994
995 queued_reg_saves.truncate (0);
996 }
997
998 /* Does INSN clobber any register which QUEUED_REG_SAVES lists a saved
999 location for? Or, does it clobber a register which we've previously
1000 said that some other register is saved in, and for which we now
1001 have a new location for? */
1002
1003 static bool
1004 clobbers_queued_reg_save (const_rtx insn)
1005 {
1006 queued_reg_save *q;
1007 size_t iq;
1008
1009 FOR_EACH_VEC_ELT (queued_reg_saves, iq, q)
1010 {
1011 size_t ir;
1012 reg_saved_in_data *rir;
1013
1014 if (modified_in_p (q->reg, insn))
1015 return true;
1016
1017 FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, ir, rir)
1018 if (compare_reg_or_pc (q->reg, rir->orig_reg)
1019 && modified_in_p (rir->saved_in_reg, insn))
1020 return true;
1021 }
1022
1023 return false;
1024 }
1025
1026 /* What register, if any, is currently saved in REG? */
1027
1028 static rtx
1029 reg_saved_in (rtx reg)
1030 {
1031 unsigned int regn = REGNO (reg);
1032 queued_reg_save *q;
1033 reg_saved_in_data *rir;
1034 size_t i;
1035
1036 FOR_EACH_VEC_ELT (queued_reg_saves, i, q)
1037 if (q->saved_reg && regn == REGNO (q->saved_reg))
1038 return q->reg;
1039
1040 FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, rir)
1041 if (regn == REGNO (rir->saved_in_reg))
1042 return rir->orig_reg;
1043
1044 return NULL_RTX;
1045 }
1046
1047 /* A subroutine of dwarf2out_frame_debug, process a REG_DEF_CFA note. */
1048
1049 static void
1050 dwarf2out_frame_debug_def_cfa (rtx pat)
1051 {
1052 memset (cur_cfa, 0, sizeof (*cur_cfa));
1053
1054 if (GET_CODE (pat) == PLUS)
1055 {
1056 cur_cfa->offset = INTVAL (XEXP (pat, 1));
1057 pat = XEXP (pat, 0);
1058 }
1059 if (MEM_P (pat))
1060 {
1061 cur_cfa->indirect = 1;
1062 pat = XEXP (pat, 0);
1063 if (GET_CODE (pat) == PLUS)
1064 {
1065 cur_cfa->base_offset = INTVAL (XEXP (pat, 1));
1066 pat = XEXP (pat, 0);
1067 }
1068 }
1069 /* ??? If this fails, we could be calling into the _loc functions to
1070 define a full expression. So far no port does that. */
1071 gcc_assert (REG_P (pat));
1072 cur_cfa->reg = dwf_regno (pat);
1073 }
1074
1075 /* A subroutine of dwarf2out_frame_debug, process a REG_ADJUST_CFA note. */
1076
1077 static void
1078 dwarf2out_frame_debug_adjust_cfa (rtx pat)
1079 {
1080 rtx src, dest;
1081
1082 gcc_assert (GET_CODE (pat) == SET);
1083 dest = XEXP (pat, 0);
1084 src = XEXP (pat, 1);
1085
1086 switch (GET_CODE (src))
1087 {
1088 case PLUS:
1089 gcc_assert (dwf_regno (XEXP (src, 0)) == cur_cfa->reg);
1090 cur_cfa->offset -= INTVAL (XEXP (src, 1));
1091 break;
1092
1093 case REG:
1094 break;
1095
1096 default:
1097 gcc_unreachable ();
1098 }
1099
1100 cur_cfa->reg = dwf_regno (dest);
1101 gcc_assert (cur_cfa->indirect == 0);
1102 }
1103
1104 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_OFFSET note. */
1105
1106 static void
1107 dwarf2out_frame_debug_cfa_offset (rtx set)
1108 {
1109 HOST_WIDE_INT offset;
1110 rtx src, addr, span;
1111 unsigned int sregno;
1112
1113 src = XEXP (set, 1);
1114 addr = XEXP (set, 0);
1115 gcc_assert (MEM_P (addr));
1116 addr = XEXP (addr, 0);
1117
1118 /* As documented, only consider extremely simple addresses. */
1119 switch (GET_CODE (addr))
1120 {
1121 case REG:
1122 gcc_assert (dwf_regno (addr) == cur_cfa->reg);
1123 offset = -cur_cfa->offset;
1124 break;
1125 case PLUS:
1126 gcc_assert (dwf_regno (XEXP (addr, 0)) == cur_cfa->reg);
1127 offset = INTVAL (XEXP (addr, 1)) - cur_cfa->offset;
1128 break;
1129 default:
1130 gcc_unreachable ();
1131 }
1132
1133 if (src == pc_rtx)
1134 {
1135 span = NULL;
1136 sregno = DWARF_FRAME_RETURN_COLUMN;
1137 }
1138 else
1139 {
1140 span = targetm.dwarf_register_span (src);
1141 sregno = dwf_regno (src);
1142 }
1143
1144 /* ??? We'd like to use queue_reg_save, but we need to come up with
1145 a different flushing heuristic for epilogues. */
1146 if (!span)
1147 reg_save (sregno, INVALID_REGNUM, offset);
1148 else
1149 {
1150 /* We have a PARALLEL describing where the contents of SRC live.
1151 Queue register saves for each piece of the PARALLEL. */
1152 int par_index;
1153 int limit;
1154 HOST_WIDE_INT span_offset = offset;
1155
1156 gcc_assert (GET_CODE (span) == PARALLEL);
1157
1158 limit = XVECLEN (span, 0);
1159 for (par_index = 0; par_index < limit; par_index++)
1160 {
1161 rtx elem = XVECEXP (span, 0, par_index);
1162
1163 sregno = dwf_regno (src);
1164 reg_save (sregno, INVALID_REGNUM, span_offset);
1165 span_offset += GET_MODE_SIZE (GET_MODE (elem));
1166 }
1167 }
1168 }
1169
1170 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_REGISTER note. */
1171
1172 static void
1173 dwarf2out_frame_debug_cfa_register (rtx set)
1174 {
1175 rtx src, dest;
1176 unsigned sregno, dregno;
1177
1178 src = XEXP (set, 1);
1179 dest = XEXP (set, 0);
1180
1181 record_reg_saved_in_reg (dest, src);
1182 if (src == pc_rtx)
1183 sregno = DWARF_FRAME_RETURN_COLUMN;
1184 else
1185 sregno = dwf_regno (src);
1186
1187 dregno = dwf_regno (dest);
1188
1189 /* ??? We'd like to use queue_reg_save, but we need to come up with
1190 a different flushing heuristic for epilogues. */
1191 reg_save (sregno, dregno, 0);
1192 }
1193
1194 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */
1195
1196 static void
1197 dwarf2out_frame_debug_cfa_expression (rtx set)
1198 {
1199 rtx src, dest, span;
1200 dw_cfi_ref cfi = new_cfi ();
1201 unsigned regno;
1202
1203 dest = SET_DEST (set);
1204 src = SET_SRC (set);
1205
1206 gcc_assert (REG_P (src));
1207 gcc_assert (MEM_P (dest));
1208
1209 span = targetm.dwarf_register_span (src);
1210 gcc_assert (!span);
1211
1212 regno = dwf_regno (src);
1213
1214 cfi->dw_cfi_opc = DW_CFA_expression;
1215 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = regno;
1216 cfi->dw_cfi_oprnd2.dw_cfi_loc
1217 = mem_loc_descriptor (XEXP (dest, 0), get_address_mode (dest),
1218 GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED);
1219
1220 /* ??? We'd like to use queue_reg_save, were the interface different,
1221 and, as above, we could manage flushing for epilogues. */
1222 add_cfi (cfi);
1223 update_row_reg_save (cur_row, regno, cfi);
1224 }
1225
1226 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */
1227
1228 static void
1229 dwarf2out_frame_debug_cfa_restore (rtx reg)
1230 {
1231 unsigned int regno = dwf_regno (reg);
1232
1233 add_cfi_restore (regno);
1234 update_row_reg_save (cur_row, regno, NULL);
1235 }
1236
1237 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_WINDOW_SAVE.
1238 ??? Perhaps we should note in the CIE where windows are saved (instead of
1239 assuming 0(cfa)) and what registers are in the window. */
1240
1241 static void
1242 dwarf2out_frame_debug_cfa_window_save (void)
1243 {
1244 dw_cfi_ref cfi = new_cfi ();
1245
1246 cfi->dw_cfi_opc = DW_CFA_GNU_window_save;
1247 add_cfi (cfi);
1248 }
1249
1250 /* Record call frame debugging information for an expression EXPR,
1251 which either sets SP or FP (adjusting how we calculate the frame
1252 address) or saves a register to the stack or another register.
1253 LABEL indicates the address of EXPR.
1254
1255 This function encodes a state machine mapping rtxes to actions on
1256 cfa, cfa_store, and cfa_temp.reg. We describe these rules so
1257 users need not read the source code.
1258
1259 The High-Level Picture
1260
1261 Changes in the register we use to calculate the CFA: Currently we
1262 assume that if you copy the CFA register into another register, we
1263 should take the other one as the new CFA register; this seems to
1264 work pretty well. If it's wrong for some target, it's simple
1265 enough not to set RTX_FRAME_RELATED_P on the insn in question.
1266
1267 Changes in the register we use for saving registers to the stack:
1268 This is usually SP, but not always. Again, we deduce that if you
1269 copy SP into another register (and SP is not the CFA register),
1270 then the new register is the one we will be using for register
1271 saves. This also seems to work.
1272
1273 Register saves: There's not much guesswork about this one; if
1274 RTX_FRAME_RELATED_P is set on an insn which modifies memory, it's a
1275 register save, and the register used to calculate the destination
1276 had better be the one we think we're using for this purpose.
1277 It's also assumed that a copy from a call-saved register to another
1278 register is saving that register if RTX_FRAME_RELATED_P is set on
1279 that instruction. If the copy is from a call-saved register to
1280 the *same* register, that means that the register is now the same
1281 value as in the caller.
1282
1283 Except: If the register being saved is the CFA register, and the
1284 offset is nonzero, we are saving the CFA, so we assume we have to
1285 use DW_CFA_def_cfa_expression. If the offset is 0, we assume that
1286 the intent is to save the value of SP from the previous frame.
1287
1288 In addition, if a register has previously been saved to a different
1289 register,
1290
1291 Invariants / Summaries of Rules
1292
1293 cfa current rule for calculating the CFA. It usually
1294 consists of a register and an offset. This is
1295 actually stored in *cur_cfa, but abbreviated
1296 for the purposes of this documentation.
1297 cfa_store register used by prologue code to save things to the stack
1298 cfa_store.offset is the offset from the value of
1299 cfa_store.reg to the actual CFA
1300 cfa_temp register holding an integral value. cfa_temp.offset
1301 stores the value, which will be used to adjust the
1302 stack pointer. cfa_temp is also used like cfa_store,
1303 to track stores to the stack via fp or a temp reg.
1304
1305 Rules 1- 4: Setting a register's value to cfa.reg or an expression
1306 with cfa.reg as the first operand changes the cfa.reg and its
1307 cfa.offset. Rule 1 and 4 also set cfa_temp.reg and
1308 cfa_temp.offset.
1309
1310 Rules 6- 9: Set a non-cfa.reg register value to a constant or an
1311 expression yielding a constant. This sets cfa_temp.reg
1312 and cfa_temp.offset.
1313
1314 Rule 5: Create a new register cfa_store used to save items to the
1315 stack.
1316
1317 Rules 10-14: Save a register to the stack. Define offset as the
1318 difference of the original location and cfa_store's
1319 location (or cfa_temp's location if cfa_temp is used).
1320
1321 Rules 16-20: If AND operation happens on sp in prologue, we assume
1322 stack is realigned. We will use a group of DW_OP_XXX
1323 expressions to represent the location of the stored
1324 register instead of CFA+offset.
1325
1326 The Rules
1327
1328 "{a,b}" indicates a choice of a xor b.
1329 "<reg>:cfa.reg" indicates that <reg> must equal cfa.reg.
1330
1331 Rule 1:
1332 (set <reg1> <reg2>:cfa.reg)
1333 effects: cfa.reg = <reg1>
1334 cfa.offset unchanged
1335 cfa_temp.reg = <reg1>
1336 cfa_temp.offset = cfa.offset
1337
1338 Rule 2:
1339 (set sp ({minus,plus,losum} {sp,fp}:cfa.reg
1340 {<const_int>,<reg>:cfa_temp.reg}))
1341 effects: cfa.reg = sp if fp used
1342 cfa.offset += {+/- <const_int>, cfa_temp.offset} if cfa.reg==sp
1343 cfa_store.offset += {+/- <const_int>, cfa_temp.offset}
1344 if cfa_store.reg==sp
1345
1346 Rule 3:
1347 (set fp ({minus,plus,losum} <reg>:cfa.reg <const_int>))
1348 effects: cfa.reg = fp
1349 cfa_offset += +/- <const_int>
1350
1351 Rule 4:
1352 (set <reg1> ({plus,losum} <reg2>:cfa.reg <const_int>))
1353 constraints: <reg1> != fp
1354 <reg1> != sp
1355 effects: cfa.reg = <reg1>
1356 cfa_temp.reg = <reg1>
1357 cfa_temp.offset = cfa.offset
1358
1359 Rule 5:
1360 (set <reg1> (plus <reg2>:cfa_temp.reg sp:cfa.reg))
1361 constraints: <reg1> != fp
1362 <reg1> != sp
1363 effects: cfa_store.reg = <reg1>
1364 cfa_store.offset = cfa.offset - cfa_temp.offset
1365
1366 Rule 6:
1367 (set <reg> <const_int>)
1368 effects: cfa_temp.reg = <reg>
1369 cfa_temp.offset = <const_int>
1370
1371 Rule 7:
1372 (set <reg1>:cfa_temp.reg (ior <reg2>:cfa_temp.reg <const_int>))
1373 effects: cfa_temp.reg = <reg1>
1374 cfa_temp.offset |= <const_int>
1375
1376 Rule 8:
1377 (set <reg> (high <exp>))
1378 effects: none
1379
1380 Rule 9:
1381 (set <reg> (lo_sum <exp> <const_int>))
1382 effects: cfa_temp.reg = <reg>
1383 cfa_temp.offset = <const_int>
1384
1385 Rule 10:
1386 (set (mem ({pre,post}_modify sp:cfa_store (???? <reg1> <const_int>))) <reg2>)
1387 effects: cfa_store.offset -= <const_int>
1388 cfa.offset = cfa_store.offset if cfa.reg == sp
1389 cfa.reg = sp
1390 cfa.base_offset = -cfa_store.offset
1391
1392 Rule 11:
1393 (set (mem ({pre_inc,pre_dec,post_dec} sp:cfa_store.reg)) <reg>)
1394 effects: cfa_store.offset += -/+ mode_size(mem)
1395 cfa.offset = cfa_store.offset if cfa.reg == sp
1396 cfa.reg = sp
1397 cfa.base_offset = -cfa_store.offset
1398
1399 Rule 12:
1400 (set (mem ({minus,plus,losum} <reg1>:{cfa_store,cfa_temp} <const_int>))
1401
1402 <reg2>)
1403 effects: cfa.reg = <reg1>
1404 cfa.base_offset = -/+ <const_int> - {cfa_store,cfa_temp}.offset
1405
1406 Rule 13:
1407 (set (mem <reg1>:{cfa_store,cfa_temp}) <reg2>)
1408 effects: cfa.reg = <reg1>
1409 cfa.base_offset = -{cfa_store,cfa_temp}.offset
1410
1411 Rule 14:
1412 (set (mem (post_inc <reg1>:cfa_temp <const_int>)) <reg2>)
1413 effects: cfa.reg = <reg1>
1414 cfa.base_offset = -cfa_temp.offset
1415 cfa_temp.offset -= mode_size(mem)
1416
1417 Rule 15:
1418 (set <reg> {unspec, unspec_volatile})
1419 effects: target-dependent
1420
1421 Rule 16:
1422 (set sp (and: sp <const_int>))
1423 constraints: cfa_store.reg == sp
1424 effects: cfun->fde.stack_realign = 1
1425 cfa_store.offset = 0
1426 fde->drap_reg = cfa.reg if cfa.reg != sp and cfa.reg != fp
1427
1428 Rule 17:
1429 (set (mem ({pre_inc, pre_dec} sp)) (mem (plus (cfa.reg) (const_int))))
1430 effects: cfa_store.offset += -/+ mode_size(mem)
1431
1432 Rule 18:
1433 (set (mem ({pre_inc, pre_dec} sp)) fp)
1434 constraints: fde->stack_realign == 1
1435 effects: cfa_store.offset = 0
1436 cfa.reg != HARD_FRAME_POINTER_REGNUM
1437
1438 Rule 19:
1439 (set (mem ({pre_inc, pre_dec} sp)) cfa.reg)
1440 constraints: fde->stack_realign == 1
1441 && cfa.offset == 0
1442 && cfa.indirect == 0
1443 && cfa.reg != HARD_FRAME_POINTER_REGNUM
1444 effects: Use DW_CFA_def_cfa_expression to define cfa
1445 cfa.reg == fde->drap_reg */
1446
1447 static void
1448 dwarf2out_frame_debug_expr (rtx expr)
1449 {
1450 rtx src, dest, span;
1451 HOST_WIDE_INT offset;
1452 dw_fde_ref fde;
1453
1454 /* If RTX_FRAME_RELATED_P is set on a PARALLEL, process each member of
1455 the PARALLEL independently. The first element is always processed if
1456 it is a SET. This is for backward compatibility. Other elements
1457 are processed only if they are SETs and the RTX_FRAME_RELATED_P
1458 flag is set in them. */
1459 if (GET_CODE (expr) == PARALLEL || GET_CODE (expr) == SEQUENCE)
1460 {
1461 int par_index;
1462 int limit = XVECLEN (expr, 0);
1463 rtx elem;
1464
1465 /* PARALLELs have strict read-modify-write semantics, so we
1466 ought to evaluate every rvalue before changing any lvalue.
1467 It's cumbersome to do that in general, but there's an
1468 easy approximation that is enough for all current users:
1469 handle register saves before register assignments. */
1470 if (GET_CODE (expr) == PARALLEL)
1471 for (par_index = 0; par_index < limit; par_index++)
1472 {
1473 elem = XVECEXP (expr, 0, par_index);
1474 if (GET_CODE (elem) == SET
1475 && MEM_P (SET_DEST (elem))
1476 && (RTX_FRAME_RELATED_P (elem) || par_index == 0))
1477 dwarf2out_frame_debug_expr (elem);
1478 }
1479
1480 for (par_index = 0; par_index < limit; par_index++)
1481 {
1482 elem = XVECEXP (expr, 0, par_index);
1483 if (GET_CODE (elem) == SET
1484 && (!MEM_P (SET_DEST (elem)) || GET_CODE (expr) == SEQUENCE)
1485 && (RTX_FRAME_RELATED_P (elem) || par_index == 0))
1486 dwarf2out_frame_debug_expr (elem);
1487 }
1488 return;
1489 }
1490
1491 gcc_assert (GET_CODE (expr) == SET);
1492
1493 src = SET_SRC (expr);
1494 dest = SET_DEST (expr);
1495
1496 if (REG_P (src))
1497 {
1498 rtx rsi = reg_saved_in (src);
1499 if (rsi)
1500 src = rsi;
1501 }
1502
1503 fde = cfun->fde;
1504
1505 switch (GET_CODE (dest))
1506 {
1507 case REG:
1508 switch (GET_CODE (src))
1509 {
1510 /* Setting FP from SP. */
1511 case REG:
1512 if (cur_cfa->reg == dwf_regno (src))
1513 {
1514 /* Rule 1 */
1515 /* Update the CFA rule wrt SP or FP. Make sure src is
1516 relative to the current CFA register.
1517
1518 We used to require that dest be either SP or FP, but the
1519 ARM copies SP to a temporary register, and from there to
1520 FP. So we just rely on the backends to only set
1521 RTX_FRAME_RELATED_P on appropriate insns. */
1522 cur_cfa->reg = dwf_regno (dest);
1523 cur_trace->cfa_temp.reg = cur_cfa->reg;
1524 cur_trace->cfa_temp.offset = cur_cfa->offset;
1525 }
1526 else
1527 {
1528 /* Saving a register in a register. */
1529 gcc_assert (!fixed_regs [REGNO (dest)]
1530 /* For the SPARC and its register window. */
1531 || (dwf_regno (src) == DWARF_FRAME_RETURN_COLUMN));
1532
1533 /* After stack is aligned, we can only save SP in FP
1534 if drap register is used. In this case, we have
1535 to restore stack pointer with the CFA value and we
1536 don't generate this DWARF information. */
1537 if (fde
1538 && fde->stack_realign
1539 && REGNO (src) == STACK_POINTER_REGNUM)
1540 gcc_assert (REGNO (dest) == HARD_FRAME_POINTER_REGNUM
1541 && fde->drap_reg != INVALID_REGNUM
1542 && cur_cfa->reg != dwf_regno (src));
1543 else
1544 queue_reg_save (src, dest, 0);
1545 }
1546 break;
1547
1548 case PLUS:
1549 case MINUS:
1550 case LO_SUM:
1551 if (dest == stack_pointer_rtx)
1552 {
1553 /* Rule 2 */
1554 /* Adjusting SP. */
1555 switch (GET_CODE (XEXP (src, 1)))
1556 {
1557 case CONST_INT:
1558 offset = INTVAL (XEXP (src, 1));
1559 break;
1560 case REG:
1561 gcc_assert (dwf_regno (XEXP (src, 1))
1562 == cur_trace->cfa_temp.reg);
1563 offset = cur_trace->cfa_temp.offset;
1564 break;
1565 default:
1566 gcc_unreachable ();
1567 }
1568
1569 if (XEXP (src, 0) == hard_frame_pointer_rtx)
1570 {
1571 /* Restoring SP from FP in the epilogue. */
1572 gcc_assert (cur_cfa->reg == dw_frame_pointer_regnum);
1573 cur_cfa->reg = dw_stack_pointer_regnum;
1574 }
1575 else if (GET_CODE (src) == LO_SUM)
1576 /* Assume we've set the source reg of the LO_SUM from sp. */
1577 ;
1578 else
1579 gcc_assert (XEXP (src, 0) == stack_pointer_rtx);
1580
1581 if (GET_CODE (src) != MINUS)
1582 offset = -offset;
1583 if (cur_cfa->reg == dw_stack_pointer_regnum)
1584 cur_cfa->offset += offset;
1585 if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum)
1586 cur_trace->cfa_store.offset += offset;
1587 }
1588 else if (dest == hard_frame_pointer_rtx)
1589 {
1590 /* Rule 3 */
1591 /* Either setting the FP from an offset of the SP,
1592 or adjusting the FP */
1593 gcc_assert (frame_pointer_needed);
1594
1595 gcc_assert (REG_P (XEXP (src, 0))
1596 && dwf_regno (XEXP (src, 0)) == cur_cfa->reg
1597 && CONST_INT_P (XEXP (src, 1)));
1598 offset = INTVAL (XEXP (src, 1));
1599 if (GET_CODE (src) != MINUS)
1600 offset = -offset;
1601 cur_cfa->offset += offset;
1602 cur_cfa->reg = dw_frame_pointer_regnum;
1603 }
1604 else
1605 {
1606 gcc_assert (GET_CODE (src) != MINUS);
1607
1608 /* Rule 4 */
1609 if (REG_P (XEXP (src, 0))
1610 && dwf_regno (XEXP (src, 0)) == cur_cfa->reg
1611 && CONST_INT_P (XEXP (src, 1)))
1612 {
1613 /* Setting a temporary CFA register that will be copied
1614 into the FP later on. */
1615 offset = - INTVAL (XEXP (src, 1));
1616 cur_cfa->offset += offset;
1617 cur_cfa->reg = dwf_regno (dest);
1618 /* Or used to save regs to the stack. */
1619 cur_trace->cfa_temp.reg = cur_cfa->reg;
1620 cur_trace->cfa_temp.offset = cur_cfa->offset;
1621 }
1622
1623 /* Rule 5 */
1624 else if (REG_P (XEXP (src, 0))
1625 && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg
1626 && XEXP (src, 1) == stack_pointer_rtx)
1627 {
1628 /* Setting a scratch register that we will use instead
1629 of SP for saving registers to the stack. */
1630 gcc_assert (cur_cfa->reg == dw_stack_pointer_regnum);
1631 cur_trace->cfa_store.reg = dwf_regno (dest);
1632 cur_trace->cfa_store.offset
1633 = cur_cfa->offset - cur_trace->cfa_temp.offset;
1634 }
1635
1636 /* Rule 9 */
1637 else if (GET_CODE (src) == LO_SUM
1638 && CONST_INT_P (XEXP (src, 1)))
1639 {
1640 cur_trace->cfa_temp.reg = dwf_regno (dest);
1641 cur_trace->cfa_temp.offset = INTVAL (XEXP (src, 1));
1642 }
1643 else
1644 gcc_unreachable ();
1645 }
1646 break;
1647
1648 /* Rule 6 */
1649 case CONST_INT:
1650 cur_trace->cfa_temp.reg = dwf_regno (dest);
1651 cur_trace->cfa_temp.offset = INTVAL (src);
1652 break;
1653
1654 /* Rule 7 */
1655 case IOR:
1656 gcc_assert (REG_P (XEXP (src, 0))
1657 && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg
1658 && CONST_INT_P (XEXP (src, 1)));
1659
1660 cur_trace->cfa_temp.reg = dwf_regno (dest);
1661 cur_trace->cfa_temp.offset |= INTVAL (XEXP (src, 1));
1662 break;
1663
1664 /* Skip over HIGH, assuming it will be followed by a LO_SUM,
1665 which will fill in all of the bits. */
1666 /* Rule 8 */
1667 case HIGH:
1668 break;
1669
1670 /* Rule 15 */
1671 case UNSPEC:
1672 case UNSPEC_VOLATILE:
1673 /* All unspecs should be represented by REG_CFA_* notes. */
1674 gcc_unreachable ();
1675 return;
1676
1677 /* Rule 16 */
1678 case AND:
1679 /* If this AND operation happens on stack pointer in prologue,
1680 we assume the stack is realigned and we extract the
1681 alignment. */
1682 if (fde && XEXP (src, 0) == stack_pointer_rtx)
1683 {
1684 /* We interpret reg_save differently with stack_realign set.
1685 Thus we must flush whatever we have queued first. */
1686 dwarf2out_flush_queued_reg_saves ();
1687
1688 gcc_assert (cur_trace->cfa_store.reg
1689 == dwf_regno (XEXP (src, 0)));
1690 fde->stack_realign = 1;
1691 fde->stack_realignment = INTVAL (XEXP (src, 1));
1692 cur_trace->cfa_store.offset = 0;
1693
1694 if (cur_cfa->reg != dw_stack_pointer_regnum
1695 && cur_cfa->reg != dw_frame_pointer_regnum)
1696 fde->drap_reg = cur_cfa->reg;
1697 }
1698 return;
1699
1700 default:
1701 gcc_unreachable ();
1702 }
1703 break;
1704
1705 case MEM:
1706
1707 /* Saving a register to the stack. Make sure dest is relative to the
1708 CFA register. */
1709 switch (GET_CODE (XEXP (dest, 0)))
1710 {
1711 /* Rule 10 */
1712 /* With a push. */
1713 case PRE_MODIFY:
1714 case POST_MODIFY:
1715 /* We can't handle variable size modifications. */
1716 gcc_assert (GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1))
1717 == CONST_INT);
1718 offset = -INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1));
1719
1720 gcc_assert (REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
1721 && cur_trace->cfa_store.reg == dw_stack_pointer_regnum);
1722
1723 cur_trace->cfa_store.offset += offset;
1724 if (cur_cfa->reg == dw_stack_pointer_regnum)
1725 cur_cfa->offset = cur_trace->cfa_store.offset;
1726
1727 if (GET_CODE (XEXP (dest, 0)) == POST_MODIFY)
1728 offset -= cur_trace->cfa_store.offset;
1729 else
1730 offset = -cur_trace->cfa_store.offset;
1731 break;
1732
1733 /* Rule 11 */
1734 case PRE_INC:
1735 case PRE_DEC:
1736 case POST_DEC:
1737 offset = GET_MODE_SIZE (GET_MODE (dest));
1738 if (GET_CODE (XEXP (dest, 0)) == PRE_INC)
1739 offset = -offset;
1740
1741 gcc_assert ((REGNO (XEXP (XEXP (dest, 0), 0))
1742 == STACK_POINTER_REGNUM)
1743 && cur_trace->cfa_store.reg == dw_stack_pointer_regnum);
1744
1745 cur_trace->cfa_store.offset += offset;
1746
1747 /* Rule 18: If stack is aligned, we will use FP as a
1748 reference to represent the address of the stored
1749 regiser. */
1750 if (fde
1751 && fde->stack_realign
1752 && REG_P (src)
1753 && REGNO (src) == HARD_FRAME_POINTER_REGNUM)
1754 {
1755 gcc_assert (cur_cfa->reg != dw_frame_pointer_regnum);
1756 cur_trace->cfa_store.offset = 0;
1757 }
1758
1759 if (cur_cfa->reg == dw_stack_pointer_regnum)
1760 cur_cfa->offset = cur_trace->cfa_store.offset;
1761
1762 if (GET_CODE (XEXP (dest, 0)) == POST_DEC)
1763 offset += -cur_trace->cfa_store.offset;
1764 else
1765 offset = -cur_trace->cfa_store.offset;
1766 break;
1767
1768 /* Rule 12 */
1769 /* With an offset. */
1770 case PLUS:
1771 case MINUS:
1772 case LO_SUM:
1773 {
1774 unsigned int regno;
1775
1776 gcc_assert (CONST_INT_P (XEXP (XEXP (dest, 0), 1))
1777 && REG_P (XEXP (XEXP (dest, 0), 0)));
1778 offset = INTVAL (XEXP (XEXP (dest, 0), 1));
1779 if (GET_CODE (XEXP (dest, 0)) == MINUS)
1780 offset = -offset;
1781
1782 regno = dwf_regno (XEXP (XEXP (dest, 0), 0));
1783
1784 if (cur_cfa->reg == regno)
1785 offset -= cur_cfa->offset;
1786 else if (cur_trace->cfa_store.reg == regno)
1787 offset -= cur_trace->cfa_store.offset;
1788 else
1789 {
1790 gcc_assert (cur_trace->cfa_temp.reg == regno);
1791 offset -= cur_trace->cfa_temp.offset;
1792 }
1793 }
1794 break;
1795
1796 /* Rule 13 */
1797 /* Without an offset. */
1798 case REG:
1799 {
1800 unsigned int regno = dwf_regno (XEXP (dest, 0));
1801
1802 if (cur_cfa->reg == regno)
1803 offset = -cur_cfa->offset;
1804 else if (cur_trace->cfa_store.reg == regno)
1805 offset = -cur_trace->cfa_store.offset;
1806 else
1807 {
1808 gcc_assert (cur_trace->cfa_temp.reg == regno);
1809 offset = -cur_trace->cfa_temp.offset;
1810 }
1811 }
1812 break;
1813
1814 /* Rule 14 */
1815 case POST_INC:
1816 gcc_assert (cur_trace->cfa_temp.reg
1817 == dwf_regno (XEXP (XEXP (dest, 0), 0)));
1818 offset = -cur_trace->cfa_temp.offset;
1819 cur_trace->cfa_temp.offset -= GET_MODE_SIZE (GET_MODE (dest));
1820 break;
1821
1822 default:
1823 gcc_unreachable ();
1824 }
1825
1826 /* Rule 17 */
1827 /* If the source operand of this MEM operation is a memory,
1828 we only care how much stack grew. */
1829 if (MEM_P (src))
1830 break;
1831
1832 if (REG_P (src)
1833 && REGNO (src) != STACK_POINTER_REGNUM
1834 && REGNO (src) != HARD_FRAME_POINTER_REGNUM
1835 && dwf_regno (src) == cur_cfa->reg)
1836 {
1837 /* We're storing the current CFA reg into the stack. */
1838
1839 if (cur_cfa->offset == 0)
1840 {
1841 /* Rule 19 */
1842 /* If stack is aligned, putting CFA reg into stack means
1843 we can no longer use reg + offset to represent CFA.
1844 Here we use DW_CFA_def_cfa_expression instead. The
1845 result of this expression equals to the original CFA
1846 value. */
1847 if (fde
1848 && fde->stack_realign
1849 && cur_cfa->indirect == 0
1850 && cur_cfa->reg != dw_frame_pointer_regnum)
1851 {
1852 gcc_assert (fde->drap_reg == cur_cfa->reg);
1853
1854 cur_cfa->indirect = 1;
1855 cur_cfa->reg = dw_frame_pointer_regnum;
1856 cur_cfa->base_offset = offset;
1857 cur_cfa->offset = 0;
1858
1859 fde->drap_reg_saved = 1;
1860 break;
1861 }
1862
1863 /* If the source register is exactly the CFA, assume
1864 we're saving SP like any other register; this happens
1865 on the ARM. */
1866 queue_reg_save (stack_pointer_rtx, NULL_RTX, offset);
1867 break;
1868 }
1869 else
1870 {
1871 /* Otherwise, we'll need to look in the stack to
1872 calculate the CFA. */
1873 rtx x = XEXP (dest, 0);
1874
1875 if (!REG_P (x))
1876 x = XEXP (x, 0);
1877 gcc_assert (REG_P (x));
1878
1879 cur_cfa->reg = dwf_regno (x);
1880 cur_cfa->base_offset = offset;
1881 cur_cfa->indirect = 1;
1882 break;
1883 }
1884 }
1885
1886 span = NULL;
1887 if (REG_P (src))
1888 span = targetm.dwarf_register_span (src);
1889 if (!span)
1890 queue_reg_save (src, NULL_RTX, offset);
1891 else
1892 {
1893 /* We have a PARALLEL describing where the contents of SRC live.
1894 Queue register saves for each piece of the PARALLEL. */
1895 int par_index;
1896 int limit;
1897 HOST_WIDE_INT span_offset = offset;
1898
1899 gcc_assert (GET_CODE (span) == PARALLEL);
1900
1901 limit = XVECLEN (span, 0);
1902 for (par_index = 0; par_index < limit; par_index++)
1903 {
1904 rtx elem = XVECEXP (span, 0, par_index);
1905 queue_reg_save (elem, NULL_RTX, span_offset);
1906 span_offset += GET_MODE_SIZE (GET_MODE (elem));
1907 }
1908 }
1909 break;
1910
1911 default:
1912 gcc_unreachable ();
1913 }
1914 }
1915
1916 /* Record call frame debugging information for INSN, which either sets
1917 SP or FP (adjusting how we calculate the frame address) or saves a
1918 register to the stack. */
1919
1920 static void
1921 dwarf2out_frame_debug (rtx insn)
1922 {
1923 rtx note, n;
1924 bool handled_one = false;
1925
1926 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1927 switch (REG_NOTE_KIND (note))
1928 {
1929 case REG_FRAME_RELATED_EXPR:
1930 insn = XEXP (note, 0);
1931 goto do_frame_expr;
1932
1933 case REG_CFA_DEF_CFA:
1934 dwarf2out_frame_debug_def_cfa (XEXP (note, 0));
1935 handled_one = true;
1936 break;
1937
1938 case REG_CFA_ADJUST_CFA:
1939 n = XEXP (note, 0);
1940 if (n == NULL)
1941 {
1942 n = PATTERN (insn);
1943 if (GET_CODE (n) == PARALLEL)
1944 n = XVECEXP (n, 0, 0);
1945 }
1946 dwarf2out_frame_debug_adjust_cfa (n);
1947 handled_one = true;
1948 break;
1949
1950 case REG_CFA_OFFSET:
1951 n = XEXP (note, 0);
1952 if (n == NULL)
1953 n = single_set (insn);
1954 dwarf2out_frame_debug_cfa_offset (n);
1955 handled_one = true;
1956 break;
1957
1958 case REG_CFA_REGISTER:
1959 n = XEXP (note, 0);
1960 if (n == NULL)
1961 {
1962 n = PATTERN (insn);
1963 if (GET_CODE (n) == PARALLEL)
1964 n = XVECEXP (n, 0, 0);
1965 }
1966 dwarf2out_frame_debug_cfa_register (n);
1967 handled_one = true;
1968 break;
1969
1970 case REG_CFA_EXPRESSION:
1971 n = XEXP (note, 0);
1972 if (n == NULL)
1973 n = single_set (insn);
1974 dwarf2out_frame_debug_cfa_expression (n);
1975 handled_one = true;
1976 break;
1977
1978 case REG_CFA_RESTORE:
1979 n = XEXP (note, 0);
1980 if (n == NULL)
1981 {
1982 n = PATTERN (insn);
1983 if (GET_CODE (n) == PARALLEL)
1984 n = XVECEXP (n, 0, 0);
1985 n = XEXP (n, 0);
1986 }
1987 dwarf2out_frame_debug_cfa_restore (n);
1988 handled_one = true;
1989 break;
1990
1991 case REG_CFA_SET_VDRAP:
1992 n = XEXP (note, 0);
1993 if (REG_P (n))
1994 {
1995 dw_fde_ref fde = cfun->fde;
1996 if (fde)
1997 {
1998 gcc_assert (fde->vdrap_reg == INVALID_REGNUM);
1999 if (REG_P (n))
2000 fde->vdrap_reg = dwf_regno (n);
2001 }
2002 }
2003 handled_one = true;
2004 break;
2005
2006 case REG_CFA_WINDOW_SAVE:
2007 dwarf2out_frame_debug_cfa_window_save ();
2008 handled_one = true;
2009 break;
2010
2011 case REG_CFA_FLUSH_QUEUE:
2012 /* The actual flush happens elsewhere. */
2013 handled_one = true;
2014 break;
2015
2016 default:
2017 break;
2018 }
2019
2020 if (!handled_one)
2021 {
2022 insn = PATTERN (insn);
2023 do_frame_expr:
2024 dwarf2out_frame_debug_expr (insn);
2025
2026 /* Check again. A parallel can save and update the same register.
2027 We could probably check just once, here, but this is safer than
2028 removing the check at the start of the function. */
2029 if (clobbers_queued_reg_save (insn))
2030 dwarf2out_flush_queued_reg_saves ();
2031 }
2032 }
2033
2034 /* Emit CFI info to change the state from OLD_ROW to NEW_ROW. */
2035
2036 static void
2037 change_cfi_row (dw_cfi_row *old_row, dw_cfi_row *new_row)
2038 {
2039 size_t i, n_old, n_new, n_max;
2040 dw_cfi_ref cfi;
2041
2042 if (new_row->cfa_cfi && !cfi_equal_p (old_row->cfa_cfi, new_row->cfa_cfi))
2043 add_cfi (new_row->cfa_cfi);
2044 else
2045 {
2046 cfi = def_cfa_0 (&old_row->cfa, &new_row->cfa);
2047 if (cfi)
2048 add_cfi (cfi);
2049 }
2050
2051 n_old = vec_safe_length (old_row->reg_save);
2052 n_new = vec_safe_length (new_row->reg_save);
2053 n_max = MAX (n_old, n_new);
2054
2055 for (i = 0; i < n_max; ++i)
2056 {
2057 dw_cfi_ref r_old = NULL, r_new = NULL;
2058
2059 if (i < n_old)
2060 r_old = (*old_row->reg_save)[i];
2061 if (i < n_new)
2062 r_new = (*new_row->reg_save)[i];
2063
2064 if (r_old == r_new)
2065 ;
2066 else if (r_new == NULL)
2067 add_cfi_restore (i);
2068 else if (!cfi_equal_p (r_old, r_new))
2069 add_cfi (r_new);
2070 }
2071 }
2072
2073 /* Examine CFI and return true if a cfi label and set_loc is needed
2074 beforehand. Even when generating CFI assembler instructions, we
2075 still have to add the cfi to the list so that lookup_cfa_1 works
2076 later on. When -g2 and above we even need to force emitting of
2077 CFI labels and add to list a DW_CFA_set_loc for convert_cfa_to_fb_loc_list
2078 purposes. If we're generating DWARF3 output we use DW_OP_call_frame_cfa
2079 and so don't use convert_cfa_to_fb_loc_list. */
2080
2081 static bool
2082 cfi_label_required_p (dw_cfi_ref cfi)
2083 {
2084 if (!dwarf2out_do_cfi_asm ())
2085 return true;
2086
2087 if (dwarf_version == 2
2088 && debug_info_level > DINFO_LEVEL_TERSE
2089 && (write_symbols == DWARF2_DEBUG
2090 || write_symbols == VMS_AND_DWARF2_DEBUG))
2091 {
2092 switch (cfi->dw_cfi_opc)
2093 {
2094 case DW_CFA_def_cfa_offset:
2095 case DW_CFA_def_cfa_offset_sf:
2096 case DW_CFA_def_cfa_register:
2097 case DW_CFA_def_cfa:
2098 case DW_CFA_def_cfa_sf:
2099 case DW_CFA_def_cfa_expression:
2100 case DW_CFA_restore_state:
2101 return true;
2102 default:
2103 return false;
2104 }
2105 }
2106 return false;
2107 }
2108
2109 /* Walk the function, looking for NOTE_INSN_CFI notes. Add the CFIs to the
2110 function's FDE, adding CFI labels and set_loc/advance_loc opcodes as
2111 necessary. */
2112 static void
2113 add_cfis_to_fde (void)
2114 {
2115 dw_fde_ref fde = cfun->fde;
2116 rtx insn, next;
2117 /* We always start with a function_begin label. */
2118 bool first = false;
2119
2120 for (insn = get_insns (); insn; insn = next)
2121 {
2122 next = NEXT_INSN (insn);
2123
2124 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
2125 {
2126 fde->dw_fde_switch_cfi_index = vec_safe_length (fde->dw_fde_cfi);
2127 /* Don't attempt to advance_loc4 between labels
2128 in different sections. */
2129 first = true;
2130 }
2131
2132 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI)
2133 {
2134 bool required = cfi_label_required_p (NOTE_CFI (insn));
2135 while (next)
2136 if (NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_CFI)
2137 {
2138 required |= cfi_label_required_p (NOTE_CFI (next));
2139 next = NEXT_INSN (next);
2140 }
2141 else if (active_insn_p (next)
2142 || (NOTE_P (next) && (NOTE_KIND (next)
2143 == NOTE_INSN_SWITCH_TEXT_SECTIONS)))
2144 break;
2145 else
2146 next = NEXT_INSN (next);
2147 if (required)
2148 {
2149 int num = dwarf2out_cfi_label_num;
2150 const char *label = dwarf2out_cfi_label ();
2151 dw_cfi_ref xcfi;
2152 rtx tmp;
2153
2154 /* Set the location counter to the new label. */
2155 xcfi = new_cfi ();
2156 xcfi->dw_cfi_opc = (first ? DW_CFA_set_loc
2157 : DW_CFA_advance_loc4);
2158 xcfi->dw_cfi_oprnd1.dw_cfi_addr = label;
2159 vec_safe_push (fde->dw_fde_cfi, xcfi);
2160
2161 tmp = emit_note_before (NOTE_INSN_CFI_LABEL, insn);
2162 NOTE_LABEL_NUMBER (tmp) = num;
2163 }
2164
2165 do
2166 {
2167 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI)
2168 vec_safe_push (fde->dw_fde_cfi, NOTE_CFI (insn));
2169 insn = NEXT_INSN (insn);
2170 }
2171 while (insn != next);
2172 first = false;
2173 }
2174 }
2175 }
2176
2177 /* If LABEL is the start of a trace, then initialize the state of that
2178 trace from CUR_TRACE and CUR_ROW. */
2179
2180 static void
2181 maybe_record_trace_start (rtx start, rtx origin)
2182 {
2183 dw_trace_info *ti;
2184 HOST_WIDE_INT args_size;
2185
2186 ti = get_trace_info (start);
2187 gcc_assert (ti != NULL);
2188
2189 if (dump_file)
2190 {
2191 fprintf (dump_file, " saw edge from trace %u to %u (via %s %d)\n",
2192 cur_trace->id, ti->id,
2193 (origin ? rtx_name[(int) GET_CODE (origin)] : "fallthru"),
2194 (origin ? INSN_UID (origin) : 0));
2195 }
2196
2197 args_size = cur_trace->end_true_args_size;
2198 if (ti->beg_row == NULL)
2199 {
2200 /* This is the first time we've encountered this trace. Propagate
2201 state across the edge and push the trace onto the work list. */
2202 ti->beg_row = copy_cfi_row (cur_row);
2203 ti->beg_true_args_size = args_size;
2204
2205 ti->cfa_store = cur_trace->cfa_store;
2206 ti->cfa_temp = cur_trace->cfa_temp;
2207 ti->regs_saved_in_regs = cur_trace->regs_saved_in_regs.copy ();
2208
2209 trace_work_list.safe_push (ti);
2210
2211 if (dump_file)
2212 fprintf (dump_file, "\tpush trace %u to worklist\n", ti->id);
2213 }
2214 else
2215 {
2216
2217 /* We ought to have the same state incoming to a given trace no
2218 matter how we arrive at the trace. Anything else means we've
2219 got some kind of optimization error. */
2220 gcc_checking_assert (cfi_row_equal_p (cur_row, ti->beg_row));
2221
2222 /* The args_size is allowed to conflict if it isn't actually used. */
2223 if (ti->beg_true_args_size != args_size)
2224 ti->args_size_undefined = true;
2225 }
2226 }
2227
2228 /* Similarly, but handle the args_size and CFA reset across EH
2229 and non-local goto edges. */
2230
2231 static void
2232 maybe_record_trace_start_abnormal (rtx start, rtx origin)
2233 {
2234 HOST_WIDE_INT save_args_size, delta;
2235 dw_cfa_location save_cfa;
2236
2237 save_args_size = cur_trace->end_true_args_size;
2238 if (save_args_size == 0)
2239 {
2240 maybe_record_trace_start (start, origin);
2241 return;
2242 }
2243
2244 delta = -save_args_size;
2245 cur_trace->end_true_args_size = 0;
2246
2247 save_cfa = cur_row->cfa;
2248 if (cur_row->cfa.reg == dw_stack_pointer_regnum)
2249 {
2250 /* Convert a change in args_size (always a positive in the
2251 direction of stack growth) to a change in stack pointer. */
2252 #ifndef STACK_GROWS_DOWNWARD
2253 delta = -delta;
2254 #endif
2255 cur_row->cfa.offset += delta;
2256 }
2257
2258 maybe_record_trace_start (start, origin);
2259
2260 cur_trace->end_true_args_size = save_args_size;
2261 cur_row->cfa = save_cfa;
2262 }
2263
2264 /* Propagate CUR_TRACE state to the destinations implied by INSN. */
2265 /* ??? Sadly, this is in large part a duplicate of make_edges. */
2266
2267 static void
2268 create_trace_edges (rtx insn)
2269 {
2270 rtx tmp, lab;
2271 int i, n;
2272
2273 if (JUMP_P (insn))
2274 {
2275 if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
2276 return;
2277
2278 if (tablejump_p (insn, NULL, &tmp))
2279 {
2280 rtvec vec;
2281
2282 tmp = PATTERN (tmp);
2283 vec = XVEC (tmp, GET_CODE (tmp) == ADDR_DIFF_VEC);
2284
2285 n = GET_NUM_ELEM (vec);
2286 for (i = 0; i < n; ++i)
2287 {
2288 lab = XEXP (RTVEC_ELT (vec, i), 0);
2289 maybe_record_trace_start (lab, insn);
2290 }
2291 }
2292 else if (computed_jump_p (insn))
2293 {
2294 for (lab = forced_labels; lab; lab = XEXP (lab, 1))
2295 maybe_record_trace_start (XEXP (lab, 0), insn);
2296 }
2297 else if (returnjump_p (insn))
2298 ;
2299 else if ((tmp = extract_asm_operands (PATTERN (insn))) != NULL)
2300 {
2301 n = ASM_OPERANDS_LABEL_LENGTH (tmp);
2302 for (i = 0; i < n; ++i)
2303 {
2304 lab = XEXP (ASM_OPERANDS_LABEL (tmp, i), 0);
2305 maybe_record_trace_start (lab, insn);
2306 }
2307 }
2308 else
2309 {
2310 lab = JUMP_LABEL (insn);
2311 gcc_assert (lab != NULL);
2312 maybe_record_trace_start (lab, insn);
2313 }
2314 }
2315 else if (CALL_P (insn))
2316 {
2317 /* Sibling calls don't have edges inside this function. */
2318 if (SIBLING_CALL_P (insn))
2319 return;
2320
2321 /* Process non-local goto edges. */
2322 if (can_nonlocal_goto (insn))
2323 for (lab = nonlocal_goto_handler_labels; lab; lab = XEXP (lab, 1))
2324 maybe_record_trace_start_abnormal (XEXP (lab, 0), insn);
2325 }
2326 else if (GET_CODE (PATTERN (insn)) == SEQUENCE)
2327 {
2328 rtx seq = PATTERN (insn);
2329 int i, n = XVECLEN (seq, 0);
2330 for (i = 0; i < n; ++i)
2331 create_trace_edges (XVECEXP (seq, 0, i));
2332 return;
2333 }
2334
2335 /* Process EH edges. */
2336 if (CALL_P (insn) || cfun->can_throw_non_call_exceptions)
2337 {
2338 eh_landing_pad lp = get_eh_landing_pad_from_rtx (insn);
2339 if (lp)
2340 maybe_record_trace_start_abnormal (lp->landing_pad, insn);
2341 }
2342 }
2343
2344 /* A subroutine of scan_trace. Do what needs to be done "after" INSN. */
2345
2346 static void
2347 scan_insn_after (rtx insn)
2348 {
2349 if (RTX_FRAME_RELATED_P (insn))
2350 dwarf2out_frame_debug (insn);
2351 notice_args_size (insn);
2352 }
2353
2354 /* Scan the trace beginning at INSN and create the CFI notes for the
2355 instructions therein. */
2356
2357 static void
2358 scan_trace (dw_trace_info *trace)
2359 {
2360 rtx prev, insn = trace->head;
2361 dw_cfa_location this_cfa;
2362
2363 if (dump_file)
2364 fprintf (dump_file, "Processing trace %u : start at %s %d\n",
2365 trace->id, rtx_name[(int) GET_CODE (insn)],
2366 INSN_UID (insn));
2367
2368 trace->end_row = copy_cfi_row (trace->beg_row);
2369 trace->end_true_args_size = trace->beg_true_args_size;
2370
2371 cur_trace = trace;
2372 cur_row = trace->end_row;
2373
2374 this_cfa = cur_row->cfa;
2375 cur_cfa = &this_cfa;
2376
2377 for (prev = insn, insn = NEXT_INSN (insn);
2378 insn;
2379 prev = insn, insn = NEXT_INSN (insn))
2380 {
2381 rtx control;
2382
2383 /* Do everything that happens "before" the insn. */
2384 add_cfi_insn = prev;
2385
2386 /* Notice the end of a trace. */
2387 if (BARRIER_P (insn))
2388 {
2389 /* Don't bother saving the unneeded queued registers at all. */
2390 queued_reg_saves.truncate (0);
2391 break;
2392 }
2393 if (save_point_p (insn))
2394 {
2395 /* Propagate across fallthru edges. */
2396 dwarf2out_flush_queued_reg_saves ();
2397 maybe_record_trace_start (insn, NULL);
2398 break;
2399 }
2400
2401 if (DEBUG_INSN_P (insn) || !inside_basic_block_p (insn))
2402 continue;
2403
2404 /* Handle all changes to the row state. Sequences require special
2405 handling for the positioning of the notes. */
2406 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
2407 {
2408 rtx elt, pat = PATTERN (insn);
2409 int i, n = XVECLEN (pat, 0);
2410
2411 control = XVECEXP (pat, 0, 0);
2412 if (can_throw_internal (control))
2413 notice_eh_throw (control);
2414 dwarf2out_flush_queued_reg_saves ();
2415
2416 if (JUMP_P (control) && INSN_ANNULLED_BRANCH_P (control))
2417 {
2418 /* ??? Hopefully multiple delay slots are not annulled. */
2419 gcc_assert (n == 2);
2420 gcc_assert (!RTX_FRAME_RELATED_P (control));
2421 gcc_assert (!find_reg_note (control, REG_ARGS_SIZE, NULL));
2422
2423 elt = XVECEXP (pat, 0, 1);
2424
2425 if (INSN_FROM_TARGET_P (elt))
2426 {
2427 HOST_WIDE_INT restore_args_size;
2428 cfi_vec save_row_reg_save;
2429
2430 /* If ELT is an instruction from target of an annulled
2431 branch, the effects are for the target only and so
2432 the args_size and CFA along the current path
2433 shouldn't change. */
2434 add_cfi_insn = NULL;
2435 restore_args_size = cur_trace->end_true_args_size;
2436 cur_cfa = &cur_row->cfa;
2437 save_row_reg_save = vec_safe_copy (cur_row->reg_save);
2438
2439 scan_insn_after (elt);
2440
2441 /* ??? Should we instead save the entire row state? */
2442 gcc_assert (!queued_reg_saves.length ());
2443
2444 create_trace_edges (control);
2445
2446 cur_trace->end_true_args_size = restore_args_size;
2447 cur_row->cfa = this_cfa;
2448 cur_row->reg_save = save_row_reg_save;
2449 cur_cfa = &this_cfa;
2450 }
2451 else
2452 {
2453 /* If ELT is a annulled branch-taken instruction (i.e.
2454 executed only when branch is not taken), the args_size
2455 and CFA should not change through the jump. */
2456 create_trace_edges (control);
2457
2458 /* Update and continue with the trace. */
2459 add_cfi_insn = insn;
2460 scan_insn_after (elt);
2461 def_cfa_1 (&this_cfa);
2462 }
2463 continue;
2464 }
2465
2466 /* The insns in the delay slot should all be considered to happen
2467 "before" a call insn. Consider a call with a stack pointer
2468 adjustment in the delay slot. The backtrace from the callee
2469 should include the sp adjustment. Unfortunately, that leaves
2470 us with an unavoidable unwinding error exactly at the call insn
2471 itself. For jump insns we'd prefer to avoid this error by
2472 placing the notes after the sequence. */
2473 if (JUMP_P (control))
2474 add_cfi_insn = insn;
2475
2476 for (i = 1; i < n; ++i)
2477 {
2478 elt = XVECEXP (pat, 0, i);
2479 scan_insn_after (elt);
2480 }
2481
2482 /* Make sure any register saves are visible at the jump target. */
2483 dwarf2out_flush_queued_reg_saves ();
2484 any_cfis_emitted = false;
2485
2486 /* However, if there is some adjustment on the call itself, e.g.
2487 a call_pop, that action should be considered to happen after
2488 the call returns. */
2489 add_cfi_insn = insn;
2490 scan_insn_after (control);
2491 }
2492 else
2493 {
2494 /* Flush data before calls and jumps, and of course if necessary. */
2495 if (can_throw_internal (insn))
2496 {
2497 notice_eh_throw (insn);
2498 dwarf2out_flush_queued_reg_saves ();
2499 }
2500 else if (!NONJUMP_INSN_P (insn)
2501 || clobbers_queued_reg_save (insn)
2502 || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL))
2503 dwarf2out_flush_queued_reg_saves ();
2504 any_cfis_emitted = false;
2505
2506 add_cfi_insn = insn;
2507 scan_insn_after (insn);
2508 control = insn;
2509 }
2510
2511 /* Between frame-related-p and args_size we might have otherwise
2512 emitted two cfa adjustments. Do it now. */
2513 def_cfa_1 (&this_cfa);
2514
2515 /* Minimize the number of advances by emitting the entire queue
2516 once anything is emitted. */
2517 if (any_cfis_emitted
2518 || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL))
2519 dwarf2out_flush_queued_reg_saves ();
2520
2521 /* Note that a test for control_flow_insn_p does exactly the
2522 same tests as are done to actually create the edges. So
2523 always call the routine and let it not create edges for
2524 non-control-flow insns. */
2525 create_trace_edges (control);
2526 }
2527
2528 add_cfi_insn = NULL;
2529 cur_row = NULL;
2530 cur_trace = NULL;
2531 cur_cfa = NULL;
2532 }
2533
2534 /* Scan the function and create the initial set of CFI notes. */
2535
2536 static void
2537 create_cfi_notes (void)
2538 {
2539 dw_trace_info *ti;
2540
2541 gcc_checking_assert (!queued_reg_saves.exists ());
2542 gcc_checking_assert (!trace_work_list.exists ());
2543
2544 /* Always begin at the entry trace. */
2545 ti = &trace_info[0];
2546 scan_trace (ti);
2547
2548 while (!trace_work_list.is_empty ())
2549 {
2550 ti = trace_work_list.pop ();
2551 scan_trace (ti);
2552 }
2553
2554 queued_reg_saves.release ();
2555 trace_work_list.release ();
2556 }
2557
2558 /* Return the insn before the first NOTE_INSN_CFI after START. */
2559
2560 static rtx
2561 before_next_cfi_note (rtx start)
2562 {
2563 rtx prev = start;
2564 while (start)
2565 {
2566 if (NOTE_P (start) && NOTE_KIND (start) == NOTE_INSN_CFI)
2567 return prev;
2568 prev = start;
2569 start = NEXT_INSN (start);
2570 }
2571 gcc_unreachable ();
2572 }
2573
2574 /* Insert CFI notes between traces to properly change state between them. */
2575
2576 static void
2577 connect_traces (void)
2578 {
2579 unsigned i, n = trace_info.length ();
2580 dw_trace_info *prev_ti, *ti;
2581
2582 /* ??? Ideally, we should have both queued and processed every trace.
2583 However the current representation of constant pools on various targets
2584 is indistinguishable from unreachable code. Assume for the moment that
2585 we can simply skip over such traces. */
2586 /* ??? Consider creating a DATA_INSN rtx code to indicate that
2587 these are not "real" instructions, and should not be considered.
2588 This could be generically useful for tablejump data as well. */
2589 /* Remove all unprocessed traces from the list. */
2590 for (i = n - 1; i > 0; --i)
2591 {
2592 ti = &trace_info[i];
2593 if (ti->beg_row == NULL)
2594 {
2595 trace_info.ordered_remove (i);
2596 n -= 1;
2597 }
2598 else
2599 gcc_assert (ti->end_row != NULL);
2600 }
2601
2602 /* Work from the end back to the beginning. This lets us easily insert
2603 remember/restore_state notes in the correct order wrt other notes. */
2604 prev_ti = &trace_info[n - 1];
2605 for (i = n - 1; i > 0; --i)
2606 {
2607 dw_cfi_row *old_row;
2608
2609 ti = prev_ti;
2610 prev_ti = &trace_info[i - 1];
2611
2612 add_cfi_insn = ti->head;
2613
2614 /* In dwarf2out_switch_text_section, we'll begin a new FDE
2615 for the portion of the function in the alternate text
2616 section. The row state at the very beginning of that
2617 new FDE will be exactly the row state from the CIE. */
2618 if (ti->switch_sections)
2619 old_row = cie_cfi_row;
2620 else
2621 {
2622 old_row = prev_ti->end_row;
2623 /* If there's no change from the previous end state, fine. */
2624 if (cfi_row_equal_p (old_row, ti->beg_row))
2625 ;
2626 /* Otherwise check for the common case of sharing state with
2627 the beginning of an epilogue, but not the end. Insert
2628 remember/restore opcodes in that case. */
2629 else if (cfi_row_equal_p (prev_ti->beg_row, ti->beg_row))
2630 {
2631 dw_cfi_ref cfi;
2632
2633 /* Note that if we blindly insert the remember at the
2634 start of the trace, we can wind up increasing the
2635 size of the unwind info due to extra advance opcodes.
2636 Instead, put the remember immediately before the next
2637 state change. We know there must be one, because the
2638 state at the beginning and head of the trace differ. */
2639 add_cfi_insn = before_next_cfi_note (prev_ti->head);
2640 cfi = new_cfi ();
2641 cfi->dw_cfi_opc = DW_CFA_remember_state;
2642 add_cfi (cfi);
2643
2644 add_cfi_insn = ti->head;
2645 cfi = new_cfi ();
2646 cfi->dw_cfi_opc = DW_CFA_restore_state;
2647 add_cfi (cfi);
2648
2649 old_row = prev_ti->beg_row;
2650 }
2651 /* Otherwise, we'll simply change state from the previous end. */
2652 }
2653
2654 change_cfi_row (old_row, ti->beg_row);
2655
2656 if (dump_file && add_cfi_insn != ti->head)
2657 {
2658 rtx note;
2659
2660 fprintf (dump_file, "Fixup between trace %u and %u:\n",
2661 prev_ti->id, ti->id);
2662
2663 note = ti->head;
2664 do
2665 {
2666 note = NEXT_INSN (note);
2667 gcc_assert (NOTE_P (note) && NOTE_KIND (note) == NOTE_INSN_CFI);
2668 output_cfi_directive (dump_file, NOTE_CFI (note));
2669 }
2670 while (note != add_cfi_insn);
2671 }
2672 }
2673
2674 /* Connect args_size between traces that have can_throw_internal insns. */
2675 if (cfun->eh->lp_array)
2676 {
2677 HOST_WIDE_INT prev_args_size = 0;
2678
2679 for (i = 0; i < n; ++i)
2680 {
2681 ti = &trace_info[i];
2682
2683 if (ti->switch_sections)
2684 prev_args_size = 0;
2685 if (ti->eh_head == NULL)
2686 continue;
2687 gcc_assert (!ti->args_size_undefined);
2688
2689 if (ti->beg_delay_args_size != prev_args_size)
2690 {
2691 /* ??? Search back to previous CFI note. */
2692 add_cfi_insn = PREV_INSN (ti->eh_head);
2693 add_cfi_args_size (ti->beg_delay_args_size);
2694 }
2695
2696 prev_args_size = ti->end_delay_args_size;
2697 }
2698 }
2699 }
2700
2701 /* Set up the pseudo-cfg of instruction traces, as described at the
2702 block comment at the top of the file. */
2703
2704 static void
2705 create_pseudo_cfg (void)
2706 {
2707 bool saw_barrier, switch_sections;
2708 dw_trace_info ti;
2709 rtx insn;
2710 unsigned i;
2711
2712 /* The first trace begins at the start of the function,
2713 and begins with the CIE row state. */
2714 trace_info.create (16);
2715 memset (&ti, 0, sizeof (ti));
2716 ti.head = get_insns ();
2717 ti.beg_row = cie_cfi_row;
2718 ti.cfa_store = cie_cfi_row->cfa;
2719 ti.cfa_temp.reg = INVALID_REGNUM;
2720 trace_info.quick_push (ti);
2721
2722 if (cie_return_save)
2723 ti.regs_saved_in_regs.safe_push (*cie_return_save);
2724
2725 /* Walk all the insns, collecting start of trace locations. */
2726 saw_barrier = false;
2727 switch_sections = false;
2728 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2729 {
2730 if (BARRIER_P (insn))
2731 saw_barrier = true;
2732 else if (NOTE_P (insn)
2733 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
2734 {
2735 /* We should have just seen a barrier. */
2736 gcc_assert (saw_barrier);
2737 switch_sections = true;
2738 }
2739 /* Watch out for save_point notes between basic blocks.
2740 In particular, a note after a barrier. Do not record these,
2741 delaying trace creation until the label. */
2742 else if (save_point_p (insn)
2743 && (LABEL_P (insn) || !saw_barrier))
2744 {
2745 memset (&ti, 0, sizeof (ti));
2746 ti.head = insn;
2747 ti.switch_sections = switch_sections;
2748 ti.id = trace_info.length () - 1;
2749 trace_info.safe_push (ti);
2750
2751 saw_barrier = false;
2752 switch_sections = false;
2753 }
2754 }
2755
2756 /* Create the trace index after we've finished building trace_info,
2757 avoiding stale pointer problems due to reallocation. */
2758 trace_index.create (trace_info.length ());
2759 dw_trace_info *tp;
2760 FOR_EACH_VEC_ELT (trace_info, i, tp)
2761 {
2762 dw_trace_info **slot;
2763
2764 if (dump_file)
2765 fprintf (dump_file, "Creating trace %u : start at %s %d%s\n", i,
2766 rtx_name[(int) GET_CODE (tp->head)], INSN_UID (tp->head),
2767 tp->switch_sections ? " (section switch)" : "");
2768
2769 slot = trace_index.find_slot_with_hash (tp, INSN_UID (tp->head), INSERT);
2770 gcc_assert (*slot == NULL);
2771 *slot = tp;
2772 }
2773 }
2774
2775 /* Record the initial position of the return address. RTL is
2776 INCOMING_RETURN_ADDR_RTX. */
2777
2778 static void
2779 initial_return_save (rtx rtl)
2780 {
2781 unsigned int reg = INVALID_REGNUM;
2782 HOST_WIDE_INT offset = 0;
2783
2784 switch (GET_CODE (rtl))
2785 {
2786 case REG:
2787 /* RA is in a register. */
2788 reg = dwf_regno (rtl);
2789 break;
2790
2791 case MEM:
2792 /* RA is on the stack. */
2793 rtl = XEXP (rtl, 0);
2794 switch (GET_CODE (rtl))
2795 {
2796 case REG:
2797 gcc_assert (REGNO (rtl) == STACK_POINTER_REGNUM);
2798 offset = 0;
2799 break;
2800
2801 case PLUS:
2802 gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM);
2803 offset = INTVAL (XEXP (rtl, 1));
2804 break;
2805
2806 case MINUS:
2807 gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM);
2808 offset = -INTVAL (XEXP (rtl, 1));
2809 break;
2810
2811 default:
2812 gcc_unreachable ();
2813 }
2814
2815 break;
2816
2817 case PLUS:
2818 /* The return address is at some offset from any value we can
2819 actually load. For instance, on the SPARC it is in %i7+8. Just
2820 ignore the offset for now; it doesn't matter for unwinding frames. */
2821 gcc_assert (CONST_INT_P (XEXP (rtl, 1)));
2822 initial_return_save (XEXP (rtl, 0));
2823 return;
2824
2825 default:
2826 gcc_unreachable ();
2827 }
2828
2829 if (reg != DWARF_FRAME_RETURN_COLUMN)
2830 {
2831 if (reg != INVALID_REGNUM)
2832 record_reg_saved_in_reg (rtl, pc_rtx);
2833 reg_save (DWARF_FRAME_RETURN_COLUMN, reg, offset - cur_row->cfa.offset);
2834 }
2835 }
2836
2837 static void
2838 create_cie_data (void)
2839 {
2840 dw_cfa_location loc;
2841 dw_trace_info cie_trace;
2842
2843 dw_stack_pointer_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM);
2844 dw_frame_pointer_regnum = DWARF_FRAME_REGNUM (HARD_FRAME_POINTER_REGNUM);
2845
2846 memset (&cie_trace, 0, sizeof (cie_trace));
2847 cur_trace = &cie_trace;
2848
2849 add_cfi_vec = &cie_cfi_vec;
2850 cie_cfi_row = cur_row = new_cfi_row ();
2851
2852 /* On entry, the Canonical Frame Address is at SP. */
2853 memset (&loc, 0, sizeof (loc));
2854 loc.reg = dw_stack_pointer_regnum;
2855 loc.offset = INCOMING_FRAME_SP_OFFSET;
2856 def_cfa_1 (&loc);
2857
2858 if (targetm.debug_unwind_info () == UI_DWARF2
2859 || targetm_common.except_unwind_info (&global_options) == UI_DWARF2)
2860 {
2861 initial_return_save (INCOMING_RETURN_ADDR_RTX);
2862
2863 /* For a few targets, we have the return address incoming into a
2864 register, but choose a different return column. This will result
2865 in a DW_CFA_register for the return, and an entry in
2866 regs_saved_in_regs to match. If the target later stores that
2867 return address register to the stack, we want to be able to emit
2868 the DW_CFA_offset against the return column, not the intermediate
2869 save register. Save the contents of regs_saved_in_regs so that
2870 we can re-initialize it at the start of each function. */
2871 switch (cie_trace.regs_saved_in_regs.length ())
2872 {
2873 case 0:
2874 break;
2875 case 1:
2876 cie_return_save = ggc_alloc_reg_saved_in_data ();
2877 *cie_return_save = cie_trace.regs_saved_in_regs[0];
2878 cie_trace.regs_saved_in_regs.release ();
2879 break;
2880 default:
2881 gcc_unreachable ();
2882 }
2883 }
2884
2885 add_cfi_vec = NULL;
2886 cur_row = NULL;
2887 cur_trace = NULL;
2888 }
2889
2890 /* Annotate the function with NOTE_INSN_CFI notes to record the CFI
2891 state at each location within the function. These notes will be
2892 emitted during pass_final. */
2893
2894 static unsigned int
2895 execute_dwarf2_frame (void)
2896 {
2897 /* The first time we're called, compute the incoming frame state. */
2898 if (cie_cfi_vec == NULL)
2899 create_cie_data ();
2900
2901 dwarf2out_alloc_current_fde ();
2902
2903 create_pseudo_cfg ();
2904
2905 /* Do the work. */
2906 create_cfi_notes ();
2907 connect_traces ();
2908 add_cfis_to_fde ();
2909
2910 /* Free all the data we allocated. */
2911 {
2912 size_t i;
2913 dw_trace_info *ti;
2914
2915 FOR_EACH_VEC_ELT (trace_info, i, ti)
2916 ti->regs_saved_in_regs.release ();
2917 }
2918 trace_info.release ();
2919
2920 trace_index.dispose ();
2921
2922 return 0;
2923 }
2924 \f
2925 /* Convert a DWARF call frame info. operation to its string name */
2926
2927 static const char *
2928 dwarf_cfi_name (unsigned int cfi_opc)
2929 {
2930 const char *name = get_DW_CFA_name (cfi_opc);
2931
2932 if (name != NULL)
2933 return name;
2934
2935 return "DW_CFA_<unknown>";
2936 }
2937
2938 /* This routine will generate the correct assembly data for a location
2939 description based on a cfi entry with a complex address. */
2940
2941 static void
2942 output_cfa_loc (dw_cfi_ref cfi, int for_eh)
2943 {
2944 dw_loc_descr_ref loc;
2945 unsigned long size;
2946
2947 if (cfi->dw_cfi_opc == DW_CFA_expression)
2948 {
2949 unsigned r =
2950 DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
2951 dw2_asm_output_data (1, r, NULL);
2952 loc = cfi->dw_cfi_oprnd2.dw_cfi_loc;
2953 }
2954 else
2955 loc = cfi->dw_cfi_oprnd1.dw_cfi_loc;
2956
2957 /* Output the size of the block. */
2958 size = size_of_locs (loc);
2959 dw2_asm_output_data_uleb128 (size, NULL);
2960
2961 /* Now output the operations themselves. */
2962 output_loc_sequence (loc, for_eh);
2963 }
2964
2965 /* Similar, but used for .cfi_escape. */
2966
2967 static void
2968 output_cfa_loc_raw (dw_cfi_ref cfi)
2969 {
2970 dw_loc_descr_ref loc;
2971 unsigned long size;
2972
2973 if (cfi->dw_cfi_opc == DW_CFA_expression)
2974 {
2975 unsigned r =
2976 DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
2977 fprintf (asm_out_file, "%#x,", r);
2978 loc = cfi->dw_cfi_oprnd2.dw_cfi_loc;
2979 }
2980 else
2981 loc = cfi->dw_cfi_oprnd1.dw_cfi_loc;
2982
2983 /* Output the size of the block. */
2984 size = size_of_locs (loc);
2985 dw2_asm_output_data_uleb128_raw (size);
2986 fputc (',', asm_out_file);
2987
2988 /* Now output the operations themselves. */
2989 output_loc_sequence_raw (loc);
2990 }
2991
2992 /* Output a Call Frame Information opcode and its operand(s). */
2993
2994 void
2995 output_cfi (dw_cfi_ref cfi, dw_fde_ref fde, int for_eh)
2996 {
2997 unsigned long r;
2998 HOST_WIDE_INT off;
2999
3000 if (cfi->dw_cfi_opc == DW_CFA_advance_loc)
3001 dw2_asm_output_data (1, (cfi->dw_cfi_opc
3002 | (cfi->dw_cfi_oprnd1.dw_cfi_offset & 0x3f)),
3003 "DW_CFA_advance_loc " HOST_WIDE_INT_PRINT_HEX,
3004 ((unsigned HOST_WIDE_INT)
3005 cfi->dw_cfi_oprnd1.dw_cfi_offset));
3006 else if (cfi->dw_cfi_opc == DW_CFA_offset)
3007 {
3008 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3009 dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)),
3010 "DW_CFA_offset, column %#lx", r);
3011 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3012 dw2_asm_output_data_uleb128 (off, NULL);
3013 }
3014 else if (cfi->dw_cfi_opc == DW_CFA_restore)
3015 {
3016 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3017 dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)),
3018 "DW_CFA_restore, column %#lx", r);
3019 }
3020 else
3021 {
3022 dw2_asm_output_data (1, cfi->dw_cfi_opc,
3023 "%s", dwarf_cfi_name (cfi->dw_cfi_opc));
3024
3025 switch (cfi->dw_cfi_opc)
3026 {
3027 case DW_CFA_set_loc:
3028 if (for_eh)
3029 dw2_asm_output_encoded_addr_rtx (
3030 ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/1, /*global=*/0),
3031 gen_rtx_SYMBOL_REF (Pmode, cfi->dw_cfi_oprnd1.dw_cfi_addr),
3032 false, NULL);
3033 else
3034 dw2_asm_output_addr (DWARF2_ADDR_SIZE,
3035 cfi->dw_cfi_oprnd1.dw_cfi_addr, NULL);
3036 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3037 break;
3038
3039 case DW_CFA_advance_loc1:
3040 dw2_asm_output_delta (1, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3041 fde->dw_fde_current_label, NULL);
3042 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3043 break;
3044
3045 case DW_CFA_advance_loc2:
3046 dw2_asm_output_delta (2, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3047 fde->dw_fde_current_label, NULL);
3048 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3049 break;
3050
3051 case DW_CFA_advance_loc4:
3052 dw2_asm_output_delta (4, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3053 fde->dw_fde_current_label, NULL);
3054 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3055 break;
3056
3057 case DW_CFA_MIPS_advance_loc8:
3058 dw2_asm_output_delta (8, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3059 fde->dw_fde_current_label, NULL);
3060 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3061 break;
3062
3063 case DW_CFA_offset_extended:
3064 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3065 dw2_asm_output_data_uleb128 (r, NULL);
3066 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3067 dw2_asm_output_data_uleb128 (off, NULL);
3068 break;
3069
3070 case DW_CFA_def_cfa:
3071 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3072 dw2_asm_output_data_uleb128 (r, NULL);
3073 dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd2.dw_cfi_offset, NULL);
3074 break;
3075
3076 case DW_CFA_offset_extended_sf:
3077 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3078 dw2_asm_output_data_uleb128 (r, NULL);
3079 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3080 dw2_asm_output_data_sleb128 (off, NULL);
3081 break;
3082
3083 case DW_CFA_def_cfa_sf:
3084 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3085 dw2_asm_output_data_uleb128 (r, NULL);
3086 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3087 dw2_asm_output_data_sleb128 (off, NULL);
3088 break;
3089
3090 case DW_CFA_restore_extended:
3091 case DW_CFA_undefined:
3092 case DW_CFA_same_value:
3093 case DW_CFA_def_cfa_register:
3094 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3095 dw2_asm_output_data_uleb128 (r, NULL);
3096 break;
3097
3098 case DW_CFA_register:
3099 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3100 dw2_asm_output_data_uleb128 (r, NULL);
3101 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, for_eh);
3102 dw2_asm_output_data_uleb128 (r, NULL);
3103 break;
3104
3105 case DW_CFA_def_cfa_offset:
3106 case DW_CFA_GNU_args_size:
3107 dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd1.dw_cfi_offset, NULL);
3108 break;
3109
3110 case DW_CFA_def_cfa_offset_sf:
3111 off = div_data_align (cfi->dw_cfi_oprnd1.dw_cfi_offset);
3112 dw2_asm_output_data_sleb128 (off, NULL);
3113 break;
3114
3115 case DW_CFA_GNU_window_save:
3116 break;
3117
3118 case DW_CFA_def_cfa_expression:
3119 case DW_CFA_expression:
3120 output_cfa_loc (cfi, for_eh);
3121 break;
3122
3123 case DW_CFA_GNU_negative_offset_extended:
3124 /* Obsoleted by DW_CFA_offset_extended_sf. */
3125 gcc_unreachable ();
3126
3127 default:
3128 break;
3129 }
3130 }
3131 }
3132
3133 /* Similar, but do it via assembler directives instead. */
3134
3135 void
3136 output_cfi_directive (FILE *f, dw_cfi_ref cfi)
3137 {
3138 unsigned long r, r2;
3139
3140 switch (cfi->dw_cfi_opc)
3141 {
3142 case DW_CFA_advance_loc:
3143 case DW_CFA_advance_loc1:
3144 case DW_CFA_advance_loc2:
3145 case DW_CFA_advance_loc4:
3146 case DW_CFA_MIPS_advance_loc8:
3147 case DW_CFA_set_loc:
3148 /* Should only be created in a code path not followed when emitting
3149 via directives. The assembler is going to take care of this for
3150 us. But this routines is also used for debugging dumps, so
3151 print something. */
3152 gcc_assert (f != asm_out_file);
3153 fprintf (f, "\t.cfi_advance_loc\n");
3154 break;
3155
3156 case DW_CFA_offset:
3157 case DW_CFA_offset_extended:
3158 case DW_CFA_offset_extended_sf:
3159 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3160 fprintf (f, "\t.cfi_offset %lu, "HOST_WIDE_INT_PRINT_DEC"\n",
3161 r, cfi->dw_cfi_oprnd2.dw_cfi_offset);
3162 break;
3163
3164 case DW_CFA_restore:
3165 case DW_CFA_restore_extended:
3166 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3167 fprintf (f, "\t.cfi_restore %lu\n", r);
3168 break;
3169
3170 case DW_CFA_undefined:
3171 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3172 fprintf (f, "\t.cfi_undefined %lu\n", r);
3173 break;
3174
3175 case DW_CFA_same_value:
3176 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3177 fprintf (f, "\t.cfi_same_value %lu\n", r);
3178 break;
3179
3180 case DW_CFA_def_cfa:
3181 case DW_CFA_def_cfa_sf:
3182 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3183 fprintf (f, "\t.cfi_def_cfa %lu, "HOST_WIDE_INT_PRINT_DEC"\n",
3184 r, cfi->dw_cfi_oprnd2.dw_cfi_offset);
3185 break;
3186
3187 case DW_CFA_def_cfa_register:
3188 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3189 fprintf (f, "\t.cfi_def_cfa_register %lu\n", r);
3190 break;
3191
3192 case DW_CFA_register:
3193 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3194 r2 = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, 1);
3195 fprintf (f, "\t.cfi_register %lu, %lu\n", r, r2);
3196 break;
3197
3198 case DW_CFA_def_cfa_offset:
3199 case DW_CFA_def_cfa_offset_sf:
3200 fprintf (f, "\t.cfi_def_cfa_offset "
3201 HOST_WIDE_INT_PRINT_DEC"\n",
3202 cfi->dw_cfi_oprnd1.dw_cfi_offset);
3203 break;
3204
3205 case DW_CFA_remember_state:
3206 fprintf (f, "\t.cfi_remember_state\n");
3207 break;
3208 case DW_CFA_restore_state:
3209 fprintf (f, "\t.cfi_restore_state\n");
3210 break;
3211
3212 case DW_CFA_GNU_args_size:
3213 if (f == asm_out_file)
3214 {
3215 fprintf (f, "\t.cfi_escape %#x,", DW_CFA_GNU_args_size);
3216 dw2_asm_output_data_uleb128_raw (cfi->dw_cfi_oprnd1.dw_cfi_offset);
3217 if (flag_debug_asm)
3218 fprintf (f, "\t%s args_size "HOST_WIDE_INT_PRINT_DEC,
3219 ASM_COMMENT_START, cfi->dw_cfi_oprnd1.dw_cfi_offset);
3220 fputc ('\n', f);
3221 }
3222 else
3223 {
3224 fprintf (f, "\t.cfi_GNU_args_size "HOST_WIDE_INT_PRINT_DEC "\n",
3225 cfi->dw_cfi_oprnd1.dw_cfi_offset);
3226 }
3227 break;
3228
3229 case DW_CFA_GNU_window_save:
3230 fprintf (f, "\t.cfi_window_save\n");
3231 break;
3232
3233 case DW_CFA_def_cfa_expression:
3234 if (f != asm_out_file)
3235 {
3236 fprintf (f, "\t.cfi_def_cfa_expression ...\n");
3237 break;
3238 }
3239 /* FALLTHRU */
3240 case DW_CFA_expression:
3241 if (f != asm_out_file)
3242 {
3243 fprintf (f, "\t.cfi_cfa_expression ...\n");
3244 break;
3245 }
3246 fprintf (f, "\t.cfi_escape %#x,", cfi->dw_cfi_opc);
3247 output_cfa_loc_raw (cfi);
3248 fputc ('\n', f);
3249 break;
3250
3251 default:
3252 gcc_unreachable ();
3253 }
3254 }
3255
3256 void
3257 dwarf2out_emit_cfi (dw_cfi_ref cfi)
3258 {
3259 if (dwarf2out_do_cfi_asm ())
3260 output_cfi_directive (asm_out_file, cfi);
3261 }
3262
3263 static void
3264 dump_cfi_row (FILE *f, dw_cfi_row *row)
3265 {
3266 dw_cfi_ref cfi;
3267 unsigned i;
3268
3269 cfi = row->cfa_cfi;
3270 if (!cfi)
3271 {
3272 dw_cfa_location dummy;
3273 memset (&dummy, 0, sizeof (dummy));
3274 dummy.reg = INVALID_REGNUM;
3275 cfi = def_cfa_0 (&dummy, &row->cfa);
3276 }
3277 output_cfi_directive (f, cfi);
3278
3279 FOR_EACH_VEC_SAFE_ELT (row->reg_save, i, cfi)
3280 if (cfi)
3281 output_cfi_directive (f, cfi);
3282 }
3283
3284 void debug_cfi_row (dw_cfi_row *row);
3285
3286 void
3287 debug_cfi_row (dw_cfi_row *row)
3288 {
3289 dump_cfi_row (stderr, row);
3290 }
3291 \f
3292
3293 /* Save the result of dwarf2out_do_frame across PCH.
3294 This variable is tri-state, with 0 unset, >0 true, <0 false. */
3295 static GTY(()) signed char saved_do_cfi_asm = 0;
3296
3297 /* Decide whether we want to emit frame unwind information for the current
3298 translation unit. */
3299
3300 bool
3301 dwarf2out_do_frame (void)
3302 {
3303 /* We want to emit correct CFA location expressions or lists, so we
3304 have to return true if we're going to output debug info, even if
3305 we're not going to output frame or unwind info. */
3306 if (write_symbols == DWARF2_DEBUG || write_symbols == VMS_AND_DWARF2_DEBUG)
3307 return true;
3308
3309 if (saved_do_cfi_asm > 0)
3310 return true;
3311
3312 if (targetm.debug_unwind_info () == UI_DWARF2)
3313 return true;
3314
3315 if ((flag_unwind_tables || flag_exceptions)
3316 && targetm_common.except_unwind_info (&global_options) == UI_DWARF2)
3317 return true;
3318
3319 return false;
3320 }
3321
3322 /* Decide whether to emit frame unwind via assembler directives. */
3323
3324 bool
3325 dwarf2out_do_cfi_asm (void)
3326 {
3327 int enc;
3328
3329 if (saved_do_cfi_asm != 0)
3330 return saved_do_cfi_asm > 0;
3331
3332 /* Assume failure for a moment. */
3333 saved_do_cfi_asm = -1;
3334
3335 if (!flag_dwarf2_cfi_asm || !dwarf2out_do_frame ())
3336 return false;
3337 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
3338 return false;
3339
3340 /* Make sure the personality encoding is one the assembler can support.
3341 In particular, aligned addresses can't be handled. */
3342 enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/2,/*global=*/1);
3343 if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel)
3344 return false;
3345 enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0,/*global=*/0);
3346 if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel)
3347 return false;
3348
3349 /* If we can't get the assembler to emit only .debug_frame, and we don't need
3350 dwarf2 unwind info for exceptions, then emit .debug_frame by hand. */
3351 if (!HAVE_GAS_CFI_SECTIONS_DIRECTIVE
3352 && !flag_unwind_tables && !flag_exceptions
3353 && targetm_common.except_unwind_info (&global_options) != UI_DWARF2)
3354 return false;
3355
3356 /* Success! */
3357 saved_do_cfi_asm = 1;
3358 return true;
3359 }
3360
3361 static bool
3362 gate_dwarf2_frame (void)
3363 {
3364 #ifndef HAVE_prologue
3365 /* Targets which still implement the prologue in assembler text
3366 cannot use the generic dwarf2 unwinding. */
3367 return false;
3368 #endif
3369
3370 /* ??? What to do for UI_TARGET unwinding? They might be able to benefit
3371 from the optimized shrink-wrapping annotations that we will compute.
3372 For now, only produce the CFI notes for dwarf2. */
3373 return dwarf2out_do_frame ();
3374 }
3375
3376 namespace {
3377
3378 const pass_data pass_data_dwarf2_frame =
3379 {
3380 RTL_PASS, /* type */
3381 "dwarf2", /* name */
3382 OPTGROUP_NONE, /* optinfo_flags */
3383 true, /* has_gate */
3384 true, /* has_execute */
3385 TV_FINAL, /* tv_id */
3386 0, /* properties_required */
3387 0, /* properties_provided */
3388 0, /* properties_destroyed */
3389 0, /* todo_flags_start */
3390 0, /* todo_flags_finish */
3391 };
3392
3393 class pass_dwarf2_frame : public rtl_opt_pass
3394 {
3395 public:
3396 pass_dwarf2_frame (gcc::context *ctxt)
3397 : rtl_opt_pass (pass_data_dwarf2_frame, ctxt)
3398 {}
3399
3400 /* opt_pass methods: */
3401 bool gate () { return gate_dwarf2_frame (); }
3402 unsigned int execute () { return execute_dwarf2_frame (); }
3403
3404 }; // class pass_dwarf2_frame
3405
3406 } // anon namespace
3407
3408 rtl_opt_pass *
3409 make_pass_dwarf2_frame (gcc::context *ctxt)
3410 {
3411 return new pass_dwarf2_frame (ctxt);
3412 }
3413
3414 #include "gt-dwarf2cfi.h"