cgraph.h (cgraph_node_set_iterator, [...]): Remove typedef.
[gcc.git] / gcc / dwarf2cfi.c
1 /* Dwarf2 Call Frame Information helper routines.
2 Copyright (C) 1992-2013 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
10
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "tm.h"
24 #include "version.h"
25 #include "flags.h"
26 #include "rtl.h"
27 #include "tree.h"
28 #include "stor-layout.h"
29 #include "function.h"
30 #include "basic-block.h"
31 #include "dwarf2.h"
32 #include "dwarf2out.h"
33 #include "dwarf2asm.h"
34 #include "ggc.h"
35 #include "hash-table.h"
36 #include "tm_p.h"
37 #include "target.h"
38 #include "common/common-target.h"
39 #include "tree-pass.h"
40
41 #include "except.h" /* expand_builtin_dwarf_sp_column */
42 #include "expr.h" /* init_return_column_size */
43 #include "regs.h" /* expand_builtin_init_dwarf_reg_sizes */
44 #include "output.h" /* asm_out_file */
45 #include "debug.h" /* dwarf2out_do_frame, dwarf2out_do_cfi_asm */
46
47
48 /* ??? Poison these here until it can be done generically. They've been
49 totally replaced in this file; make sure it stays that way. */
50 #undef DWARF2_UNWIND_INFO
51 #undef DWARF2_FRAME_INFO
52 #if (GCC_VERSION >= 3000)
53 #pragma GCC poison DWARF2_UNWIND_INFO DWARF2_FRAME_INFO
54 #endif
55
56 #ifndef INCOMING_RETURN_ADDR_RTX
57 #define INCOMING_RETURN_ADDR_RTX (gcc_unreachable (), NULL_RTX)
58 #endif
59
60 /* Maximum size (in bytes) of an artificially generated label. */
61 #define MAX_ARTIFICIAL_LABEL_BYTES 30
62 \f
63 /* A collected description of an entire row of the abstract CFI table. */
64 typedef struct GTY(()) dw_cfi_row_struct
65 {
66 /* The expression that computes the CFA, expressed in two different ways.
67 The CFA member for the simple cases, and the full CFI expression for
68 the complex cases. The later will be a DW_CFA_cfa_expression. */
69 dw_cfa_location cfa;
70 dw_cfi_ref cfa_cfi;
71
72 /* The expressions for any register column that is saved. */
73 cfi_vec reg_save;
74 } dw_cfi_row;
75
76 /* The caller's ORIG_REG is saved in SAVED_IN_REG. */
77 typedef struct GTY(()) reg_saved_in_data_struct {
78 rtx orig_reg;
79 rtx saved_in_reg;
80 } reg_saved_in_data;
81
82
83 /* Since we no longer have a proper CFG, we're going to create a facsimile
84 of one on the fly while processing the frame-related insns.
85
86 We create dw_trace_info structures for each extended basic block beginning
87 and ending at a "save point". Save points are labels, barriers, certain
88 notes, and of course the beginning and end of the function.
89
90 As we encounter control transfer insns, we propagate the "current"
91 row state across the edges to the starts of traces. When checking is
92 enabled, we validate that we propagate the same data from all sources.
93
94 All traces are members of the TRACE_INFO array, in the order in which
95 they appear in the instruction stream.
96
97 All save points are present in the TRACE_INDEX hash, mapping the insn
98 starting a trace to the dw_trace_info describing the trace. */
99
100 typedef struct
101 {
102 /* The insn that begins the trace. */
103 rtx head;
104
105 /* The row state at the beginning and end of the trace. */
106 dw_cfi_row *beg_row, *end_row;
107
108 /* Tracking for DW_CFA_GNU_args_size. The "true" sizes are those we find
109 while scanning insns. However, the args_size value is irrelevant at
110 any point except can_throw_internal_p insns. Therefore the "delay"
111 sizes the values that must actually be emitted for this trace. */
112 HOST_WIDE_INT beg_true_args_size, end_true_args_size;
113 HOST_WIDE_INT beg_delay_args_size, end_delay_args_size;
114
115 /* The first EH insn in the trace, where beg_delay_args_size must be set. */
116 rtx eh_head;
117
118 /* The following variables contain data used in interpreting frame related
119 expressions. These are not part of the "real" row state as defined by
120 Dwarf, but it seems like they need to be propagated into a trace in case
121 frame related expressions have been sunk. */
122 /* ??? This seems fragile. These variables are fragments of a larger
123 expression. If we do not keep the entire expression together, we risk
124 not being able to put it together properly. Consider forcing targets
125 to generate self-contained expressions and dropping all of the magic
126 interpretation code in this file. Or at least refusing to shrink wrap
127 any frame related insn that doesn't contain a complete expression. */
128
129 /* The register used for saving registers to the stack, and its offset
130 from the CFA. */
131 dw_cfa_location cfa_store;
132
133 /* A temporary register holding an integral value used in adjusting SP
134 or setting up the store_reg. The "offset" field holds the integer
135 value, not an offset. */
136 dw_cfa_location cfa_temp;
137
138 /* A set of registers saved in other registers. This is the inverse of
139 the row->reg_save info, if the entry is a DW_CFA_register. This is
140 implemented as a flat array because it normally contains zero or 1
141 entry, depending on the target. IA-64 is the big spender here, using
142 a maximum of 5 entries. */
143 vec<reg_saved_in_data> regs_saved_in_regs;
144
145 /* An identifier for this trace. Used only for debugging dumps. */
146 unsigned id;
147
148 /* True if this trace immediately follows NOTE_INSN_SWITCH_TEXT_SECTIONS. */
149 bool switch_sections;
150
151 /* True if we've seen different values incoming to beg_true_args_size. */
152 bool args_size_undefined;
153 } dw_trace_info;
154
155
156 typedef dw_trace_info *dw_trace_info_ref;
157
158
159 /* Hashtable helpers. */
160
161 struct trace_info_hasher : typed_noop_remove <dw_trace_info>
162 {
163 typedef dw_trace_info value_type;
164 typedef dw_trace_info compare_type;
165 static inline hashval_t hash (const value_type *);
166 static inline bool equal (const value_type *, const compare_type *);
167 };
168
169 inline hashval_t
170 trace_info_hasher::hash (const value_type *ti)
171 {
172 return INSN_UID (ti->head);
173 }
174
175 inline bool
176 trace_info_hasher::equal (const value_type *a, const compare_type *b)
177 {
178 return a->head == b->head;
179 }
180
181
182 /* The variables making up the pseudo-cfg, as described above. */
183 static vec<dw_trace_info> trace_info;
184 static vec<dw_trace_info_ref> trace_work_list;
185 static hash_table <trace_info_hasher> trace_index;
186
187 /* A vector of call frame insns for the CIE. */
188 cfi_vec cie_cfi_vec;
189
190 /* The state of the first row of the FDE table, which includes the
191 state provided by the CIE. */
192 static GTY(()) dw_cfi_row *cie_cfi_row;
193
194 static GTY(()) reg_saved_in_data *cie_return_save;
195
196 static GTY(()) unsigned long dwarf2out_cfi_label_num;
197
198 /* The insn after which a new CFI note should be emitted. */
199 static rtx add_cfi_insn;
200
201 /* When non-null, add_cfi will add the CFI to this vector. */
202 static cfi_vec *add_cfi_vec;
203
204 /* The current instruction trace. */
205 static dw_trace_info *cur_trace;
206
207 /* The current, i.e. most recently generated, row of the CFI table. */
208 static dw_cfi_row *cur_row;
209
210 /* A copy of the current CFA, for use during the processing of a
211 single insn. */
212 static dw_cfa_location *cur_cfa;
213
214 /* We delay emitting a register save until either (a) we reach the end
215 of the prologue or (b) the register is clobbered. This clusters
216 register saves so that there are fewer pc advances. */
217
218 typedef struct {
219 rtx reg;
220 rtx saved_reg;
221 HOST_WIDE_INT cfa_offset;
222 } queued_reg_save;
223
224
225 static vec<queued_reg_save> queued_reg_saves;
226
227 /* True if any CFI directives were emitted at the current insn. */
228 static bool any_cfis_emitted;
229
230 /* Short-hand for commonly used register numbers. */
231 static unsigned dw_stack_pointer_regnum;
232 static unsigned dw_frame_pointer_regnum;
233 \f
234 /* Hook used by __throw. */
235
236 rtx
237 expand_builtin_dwarf_sp_column (void)
238 {
239 unsigned int dwarf_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM);
240 return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum, 1));
241 }
242
243 /* MEM is a memory reference for the register size table, each element of
244 which has mode MODE. Initialize column C as a return address column. */
245
246 static void
247 init_return_column_size (enum machine_mode mode, rtx mem, unsigned int c)
248 {
249 HOST_WIDE_INT offset = c * GET_MODE_SIZE (mode);
250 HOST_WIDE_INT size = GET_MODE_SIZE (Pmode);
251 emit_move_insn (adjust_address (mem, mode, offset),
252 gen_int_mode (size, mode));
253 }
254
255 /* Generate code to initialize the register size table. */
256
257 void
258 expand_builtin_init_dwarf_reg_sizes (tree address)
259 {
260 unsigned int i;
261 enum machine_mode mode = TYPE_MODE (char_type_node);
262 rtx addr = expand_normal (address);
263 rtx mem = gen_rtx_MEM (BLKmode, addr);
264 bool wrote_return_column = false;
265
266 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
267 {
268 unsigned int dnum = DWARF_FRAME_REGNUM (i);
269 unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1);
270
271 if (rnum < DWARF_FRAME_REGISTERS)
272 {
273 HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode);
274 enum machine_mode save_mode = reg_raw_mode[i];
275 HOST_WIDE_INT size;
276
277 if (HARD_REGNO_CALL_PART_CLOBBERED (i, save_mode))
278 save_mode = choose_hard_reg_mode (i, 1, true);
279 if (dnum == DWARF_FRAME_RETURN_COLUMN)
280 {
281 if (save_mode == VOIDmode)
282 continue;
283 wrote_return_column = true;
284 }
285 size = GET_MODE_SIZE (save_mode);
286 if (offset < 0)
287 continue;
288
289 emit_move_insn (adjust_address (mem, mode, offset),
290 gen_int_mode (size, mode));
291 }
292 }
293
294 if (!wrote_return_column)
295 init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN);
296
297 #ifdef DWARF_ALT_FRAME_RETURN_COLUMN
298 init_return_column_size (mode, mem, DWARF_ALT_FRAME_RETURN_COLUMN);
299 #endif
300
301 targetm.init_dwarf_reg_sizes_extra (address);
302 }
303
304 \f
305 static dw_trace_info *
306 get_trace_info (rtx insn)
307 {
308 dw_trace_info dummy;
309 dummy.head = insn;
310 return trace_index.find_with_hash (&dummy, INSN_UID (insn));
311 }
312
313 static bool
314 save_point_p (rtx insn)
315 {
316 /* Labels, except those that are really jump tables. */
317 if (LABEL_P (insn))
318 return inside_basic_block_p (insn);
319
320 /* We split traces at the prologue/epilogue notes because those
321 are points at which the unwind info is usually stable. This
322 makes it easier to find spots with identical unwind info so
323 that we can use remember/restore_state opcodes. */
324 if (NOTE_P (insn))
325 switch (NOTE_KIND (insn))
326 {
327 case NOTE_INSN_PROLOGUE_END:
328 case NOTE_INSN_EPILOGUE_BEG:
329 return true;
330 }
331
332 return false;
333 }
334
335 /* Divide OFF by DWARF_CIE_DATA_ALIGNMENT, asserting no remainder. */
336
337 static inline HOST_WIDE_INT
338 div_data_align (HOST_WIDE_INT off)
339 {
340 HOST_WIDE_INT r = off / DWARF_CIE_DATA_ALIGNMENT;
341 gcc_assert (r * DWARF_CIE_DATA_ALIGNMENT == off);
342 return r;
343 }
344
345 /* Return true if we need a signed version of a given opcode
346 (e.g. DW_CFA_offset_extended_sf vs DW_CFA_offset_extended). */
347
348 static inline bool
349 need_data_align_sf_opcode (HOST_WIDE_INT off)
350 {
351 return DWARF_CIE_DATA_ALIGNMENT < 0 ? off > 0 : off < 0;
352 }
353
354 /* Return a pointer to a newly allocated Call Frame Instruction. */
355
356 static inline dw_cfi_ref
357 new_cfi (void)
358 {
359 dw_cfi_ref cfi = ggc_alloc_dw_cfi_node ();
360
361 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = 0;
362 cfi->dw_cfi_oprnd2.dw_cfi_reg_num = 0;
363
364 return cfi;
365 }
366
367 /* Return a newly allocated CFI row, with no defined data. */
368
369 static dw_cfi_row *
370 new_cfi_row (void)
371 {
372 dw_cfi_row *row = ggc_alloc_cleared_dw_cfi_row ();
373
374 row->cfa.reg = INVALID_REGNUM;
375
376 return row;
377 }
378
379 /* Return a copy of an existing CFI row. */
380
381 static dw_cfi_row *
382 copy_cfi_row (dw_cfi_row *src)
383 {
384 dw_cfi_row *dst = ggc_alloc_dw_cfi_row ();
385
386 *dst = *src;
387 dst->reg_save = vec_safe_copy (src->reg_save);
388
389 return dst;
390 }
391
392 /* Generate a new label for the CFI info to refer to. */
393
394 static char *
395 dwarf2out_cfi_label (void)
396 {
397 int num = dwarf2out_cfi_label_num++;
398 char label[20];
399
400 ASM_GENERATE_INTERNAL_LABEL (label, "LCFI", num);
401
402 return xstrdup (label);
403 }
404
405 /* Add CFI either to the current insn stream or to a vector, or both. */
406
407 static void
408 add_cfi (dw_cfi_ref cfi)
409 {
410 any_cfis_emitted = true;
411
412 if (add_cfi_insn != NULL)
413 {
414 add_cfi_insn = emit_note_after (NOTE_INSN_CFI, add_cfi_insn);
415 NOTE_CFI (add_cfi_insn) = cfi;
416 }
417
418 if (add_cfi_vec != NULL)
419 vec_safe_push (*add_cfi_vec, cfi);
420 }
421
422 static void
423 add_cfi_args_size (HOST_WIDE_INT size)
424 {
425 dw_cfi_ref cfi = new_cfi ();
426
427 /* While we can occasionally have args_size < 0 internally, this state
428 should not persist at a point we actually need an opcode. */
429 gcc_assert (size >= 0);
430
431 cfi->dw_cfi_opc = DW_CFA_GNU_args_size;
432 cfi->dw_cfi_oprnd1.dw_cfi_offset = size;
433
434 add_cfi (cfi);
435 }
436
437 static void
438 add_cfi_restore (unsigned reg)
439 {
440 dw_cfi_ref cfi = new_cfi ();
441
442 cfi->dw_cfi_opc = (reg & ~0x3f ? DW_CFA_restore_extended : DW_CFA_restore);
443 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
444
445 add_cfi (cfi);
446 }
447
448 /* Perform ROW->REG_SAVE[COLUMN] = CFI. CFI may be null, indicating
449 that the register column is no longer saved. */
450
451 static void
452 update_row_reg_save (dw_cfi_row *row, unsigned column, dw_cfi_ref cfi)
453 {
454 if (vec_safe_length (row->reg_save) <= column)
455 vec_safe_grow_cleared (row->reg_save, column + 1);
456 (*row->reg_save)[column] = cfi;
457 }
458
459 /* This function fills in aa dw_cfa_location structure from a dwarf location
460 descriptor sequence. */
461
462 static void
463 get_cfa_from_loc_descr (dw_cfa_location *cfa, struct dw_loc_descr_node *loc)
464 {
465 struct dw_loc_descr_node *ptr;
466 cfa->offset = 0;
467 cfa->base_offset = 0;
468 cfa->indirect = 0;
469 cfa->reg = -1;
470
471 for (ptr = loc; ptr != NULL; ptr = ptr->dw_loc_next)
472 {
473 enum dwarf_location_atom op = ptr->dw_loc_opc;
474
475 switch (op)
476 {
477 case DW_OP_reg0:
478 case DW_OP_reg1:
479 case DW_OP_reg2:
480 case DW_OP_reg3:
481 case DW_OP_reg4:
482 case DW_OP_reg5:
483 case DW_OP_reg6:
484 case DW_OP_reg7:
485 case DW_OP_reg8:
486 case DW_OP_reg9:
487 case DW_OP_reg10:
488 case DW_OP_reg11:
489 case DW_OP_reg12:
490 case DW_OP_reg13:
491 case DW_OP_reg14:
492 case DW_OP_reg15:
493 case DW_OP_reg16:
494 case DW_OP_reg17:
495 case DW_OP_reg18:
496 case DW_OP_reg19:
497 case DW_OP_reg20:
498 case DW_OP_reg21:
499 case DW_OP_reg22:
500 case DW_OP_reg23:
501 case DW_OP_reg24:
502 case DW_OP_reg25:
503 case DW_OP_reg26:
504 case DW_OP_reg27:
505 case DW_OP_reg28:
506 case DW_OP_reg29:
507 case DW_OP_reg30:
508 case DW_OP_reg31:
509 cfa->reg = op - DW_OP_reg0;
510 break;
511 case DW_OP_regx:
512 cfa->reg = ptr->dw_loc_oprnd1.v.val_int;
513 break;
514 case DW_OP_breg0:
515 case DW_OP_breg1:
516 case DW_OP_breg2:
517 case DW_OP_breg3:
518 case DW_OP_breg4:
519 case DW_OP_breg5:
520 case DW_OP_breg6:
521 case DW_OP_breg7:
522 case DW_OP_breg8:
523 case DW_OP_breg9:
524 case DW_OP_breg10:
525 case DW_OP_breg11:
526 case DW_OP_breg12:
527 case DW_OP_breg13:
528 case DW_OP_breg14:
529 case DW_OP_breg15:
530 case DW_OP_breg16:
531 case DW_OP_breg17:
532 case DW_OP_breg18:
533 case DW_OP_breg19:
534 case DW_OP_breg20:
535 case DW_OP_breg21:
536 case DW_OP_breg22:
537 case DW_OP_breg23:
538 case DW_OP_breg24:
539 case DW_OP_breg25:
540 case DW_OP_breg26:
541 case DW_OP_breg27:
542 case DW_OP_breg28:
543 case DW_OP_breg29:
544 case DW_OP_breg30:
545 case DW_OP_breg31:
546 cfa->reg = op - DW_OP_breg0;
547 cfa->base_offset = ptr->dw_loc_oprnd1.v.val_int;
548 break;
549 case DW_OP_bregx:
550 cfa->reg = ptr->dw_loc_oprnd1.v.val_int;
551 cfa->base_offset = ptr->dw_loc_oprnd2.v.val_int;
552 break;
553 case DW_OP_deref:
554 cfa->indirect = 1;
555 break;
556 case DW_OP_plus_uconst:
557 cfa->offset = ptr->dw_loc_oprnd1.v.val_unsigned;
558 break;
559 default:
560 gcc_unreachable ();
561 }
562 }
563 }
564
565 /* Find the previous value for the CFA, iteratively. CFI is the opcode
566 to interpret, *LOC will be updated as necessary, *REMEMBER is used for
567 one level of remember/restore state processing. */
568
569 void
570 lookup_cfa_1 (dw_cfi_ref cfi, dw_cfa_location *loc, dw_cfa_location *remember)
571 {
572 switch (cfi->dw_cfi_opc)
573 {
574 case DW_CFA_def_cfa_offset:
575 case DW_CFA_def_cfa_offset_sf:
576 loc->offset = cfi->dw_cfi_oprnd1.dw_cfi_offset;
577 break;
578 case DW_CFA_def_cfa_register:
579 loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num;
580 break;
581 case DW_CFA_def_cfa:
582 case DW_CFA_def_cfa_sf:
583 loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num;
584 loc->offset = cfi->dw_cfi_oprnd2.dw_cfi_offset;
585 break;
586 case DW_CFA_def_cfa_expression:
587 get_cfa_from_loc_descr (loc, cfi->dw_cfi_oprnd1.dw_cfi_loc);
588 break;
589
590 case DW_CFA_remember_state:
591 gcc_assert (!remember->in_use);
592 *remember = *loc;
593 remember->in_use = 1;
594 break;
595 case DW_CFA_restore_state:
596 gcc_assert (remember->in_use);
597 *loc = *remember;
598 remember->in_use = 0;
599 break;
600
601 default:
602 break;
603 }
604 }
605
606 /* Determine if two dw_cfa_location structures define the same data. */
607
608 bool
609 cfa_equal_p (const dw_cfa_location *loc1, const dw_cfa_location *loc2)
610 {
611 return (loc1->reg == loc2->reg
612 && loc1->offset == loc2->offset
613 && loc1->indirect == loc2->indirect
614 && (loc1->indirect == 0
615 || loc1->base_offset == loc2->base_offset));
616 }
617
618 /* Determine if two CFI operands are identical. */
619
620 static bool
621 cfi_oprnd_equal_p (enum dw_cfi_oprnd_type t, dw_cfi_oprnd *a, dw_cfi_oprnd *b)
622 {
623 switch (t)
624 {
625 case dw_cfi_oprnd_unused:
626 return true;
627 case dw_cfi_oprnd_reg_num:
628 return a->dw_cfi_reg_num == b->dw_cfi_reg_num;
629 case dw_cfi_oprnd_offset:
630 return a->dw_cfi_offset == b->dw_cfi_offset;
631 case dw_cfi_oprnd_addr:
632 return (a->dw_cfi_addr == b->dw_cfi_addr
633 || strcmp (a->dw_cfi_addr, b->dw_cfi_addr) == 0);
634 case dw_cfi_oprnd_loc:
635 return loc_descr_equal_p (a->dw_cfi_loc, b->dw_cfi_loc);
636 }
637 gcc_unreachable ();
638 }
639
640 /* Determine if two CFI entries are identical. */
641
642 static bool
643 cfi_equal_p (dw_cfi_ref a, dw_cfi_ref b)
644 {
645 enum dwarf_call_frame_info opc;
646
647 /* Make things easier for our callers, including missing operands. */
648 if (a == b)
649 return true;
650 if (a == NULL || b == NULL)
651 return false;
652
653 /* Obviously, the opcodes must match. */
654 opc = a->dw_cfi_opc;
655 if (opc != b->dw_cfi_opc)
656 return false;
657
658 /* Compare the two operands, re-using the type of the operands as
659 already exposed elsewhere. */
660 return (cfi_oprnd_equal_p (dw_cfi_oprnd1_desc (opc),
661 &a->dw_cfi_oprnd1, &b->dw_cfi_oprnd1)
662 && cfi_oprnd_equal_p (dw_cfi_oprnd2_desc (opc),
663 &a->dw_cfi_oprnd2, &b->dw_cfi_oprnd2));
664 }
665
666 /* Determine if two CFI_ROW structures are identical. */
667
668 static bool
669 cfi_row_equal_p (dw_cfi_row *a, dw_cfi_row *b)
670 {
671 size_t i, n_a, n_b, n_max;
672
673 if (a->cfa_cfi)
674 {
675 if (!cfi_equal_p (a->cfa_cfi, b->cfa_cfi))
676 return false;
677 }
678 else if (!cfa_equal_p (&a->cfa, &b->cfa))
679 return false;
680
681 n_a = vec_safe_length (a->reg_save);
682 n_b = vec_safe_length (b->reg_save);
683 n_max = MAX (n_a, n_b);
684
685 for (i = 0; i < n_max; ++i)
686 {
687 dw_cfi_ref r_a = NULL, r_b = NULL;
688
689 if (i < n_a)
690 r_a = (*a->reg_save)[i];
691 if (i < n_b)
692 r_b = (*b->reg_save)[i];
693
694 if (!cfi_equal_p (r_a, r_b))
695 return false;
696 }
697
698 return true;
699 }
700
701 /* The CFA is now calculated from NEW_CFA. Consider OLD_CFA in determining
702 what opcode to emit. Returns the CFI opcode to effect the change, or
703 NULL if NEW_CFA == OLD_CFA. */
704
705 static dw_cfi_ref
706 def_cfa_0 (dw_cfa_location *old_cfa, dw_cfa_location *new_cfa)
707 {
708 dw_cfi_ref cfi;
709
710 /* If nothing changed, no need to issue any call frame instructions. */
711 if (cfa_equal_p (old_cfa, new_cfa))
712 return NULL;
713
714 cfi = new_cfi ();
715
716 if (new_cfa->reg == old_cfa->reg && !new_cfa->indirect && !old_cfa->indirect)
717 {
718 /* Construct a "DW_CFA_def_cfa_offset <offset>" instruction, indicating
719 the CFA register did not change but the offset did. The data
720 factoring for DW_CFA_def_cfa_offset_sf happens in output_cfi, or
721 in the assembler via the .cfi_def_cfa_offset directive. */
722 if (new_cfa->offset < 0)
723 cfi->dw_cfi_opc = DW_CFA_def_cfa_offset_sf;
724 else
725 cfi->dw_cfi_opc = DW_CFA_def_cfa_offset;
726 cfi->dw_cfi_oprnd1.dw_cfi_offset = new_cfa->offset;
727 }
728 else if (new_cfa->offset == old_cfa->offset
729 && old_cfa->reg != INVALID_REGNUM
730 && !new_cfa->indirect
731 && !old_cfa->indirect)
732 {
733 /* Construct a "DW_CFA_def_cfa_register <register>" instruction,
734 indicating the CFA register has changed to <register> but the
735 offset has not changed. */
736 cfi->dw_cfi_opc = DW_CFA_def_cfa_register;
737 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg;
738 }
739 else if (new_cfa->indirect == 0)
740 {
741 /* Construct a "DW_CFA_def_cfa <register> <offset>" instruction,
742 indicating the CFA register has changed to <register> with
743 the specified offset. The data factoring for DW_CFA_def_cfa_sf
744 happens in output_cfi, or in the assembler via the .cfi_def_cfa
745 directive. */
746 if (new_cfa->offset < 0)
747 cfi->dw_cfi_opc = DW_CFA_def_cfa_sf;
748 else
749 cfi->dw_cfi_opc = DW_CFA_def_cfa;
750 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg;
751 cfi->dw_cfi_oprnd2.dw_cfi_offset = new_cfa->offset;
752 }
753 else
754 {
755 /* Construct a DW_CFA_def_cfa_expression instruction to
756 calculate the CFA using a full location expression since no
757 register-offset pair is available. */
758 struct dw_loc_descr_node *loc_list;
759
760 cfi->dw_cfi_opc = DW_CFA_def_cfa_expression;
761 loc_list = build_cfa_loc (new_cfa, 0);
762 cfi->dw_cfi_oprnd1.dw_cfi_loc = loc_list;
763 }
764
765 return cfi;
766 }
767
768 /* Similarly, but take OLD_CFA from CUR_ROW, and update it after the fact. */
769
770 static void
771 def_cfa_1 (dw_cfa_location *new_cfa)
772 {
773 dw_cfi_ref cfi;
774
775 if (cur_trace->cfa_store.reg == new_cfa->reg && new_cfa->indirect == 0)
776 cur_trace->cfa_store.offset = new_cfa->offset;
777
778 cfi = def_cfa_0 (&cur_row->cfa, new_cfa);
779 if (cfi)
780 {
781 cur_row->cfa = *new_cfa;
782 cur_row->cfa_cfi = (cfi->dw_cfi_opc == DW_CFA_def_cfa_expression
783 ? cfi : NULL);
784
785 add_cfi (cfi);
786 }
787 }
788
789 /* Add the CFI for saving a register. REG is the CFA column number.
790 If SREG is -1, the register is saved at OFFSET from the CFA;
791 otherwise it is saved in SREG. */
792
793 static void
794 reg_save (unsigned int reg, unsigned int sreg, HOST_WIDE_INT offset)
795 {
796 dw_fde_ref fde = cfun ? cfun->fde : NULL;
797 dw_cfi_ref cfi = new_cfi ();
798
799 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
800
801 /* When stack is aligned, store REG using DW_CFA_expression with FP. */
802 if (fde
803 && fde->stack_realign
804 && sreg == INVALID_REGNUM)
805 {
806 cfi->dw_cfi_opc = DW_CFA_expression;
807 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
808 cfi->dw_cfi_oprnd2.dw_cfi_loc
809 = build_cfa_aligned_loc (&cur_row->cfa, offset,
810 fde->stack_realignment);
811 }
812 else if (sreg == INVALID_REGNUM)
813 {
814 if (need_data_align_sf_opcode (offset))
815 cfi->dw_cfi_opc = DW_CFA_offset_extended_sf;
816 else if (reg & ~0x3f)
817 cfi->dw_cfi_opc = DW_CFA_offset_extended;
818 else
819 cfi->dw_cfi_opc = DW_CFA_offset;
820 cfi->dw_cfi_oprnd2.dw_cfi_offset = offset;
821 }
822 else if (sreg == reg)
823 {
824 /* While we could emit something like DW_CFA_same_value or
825 DW_CFA_restore, we never expect to see something like that
826 in a prologue. This is more likely to be a bug. A backend
827 can always bypass this by using REG_CFA_RESTORE directly. */
828 gcc_unreachable ();
829 }
830 else
831 {
832 cfi->dw_cfi_opc = DW_CFA_register;
833 cfi->dw_cfi_oprnd2.dw_cfi_reg_num = sreg;
834 }
835
836 add_cfi (cfi);
837 update_row_reg_save (cur_row, reg, cfi);
838 }
839
840 /* A subroutine of scan_trace. Check INSN for a REG_ARGS_SIZE note
841 and adjust data structures to match. */
842
843 static void
844 notice_args_size (rtx insn)
845 {
846 HOST_WIDE_INT args_size, delta;
847 rtx note;
848
849 note = find_reg_note (insn, REG_ARGS_SIZE, NULL);
850 if (note == NULL)
851 return;
852
853 args_size = INTVAL (XEXP (note, 0));
854 delta = args_size - cur_trace->end_true_args_size;
855 if (delta == 0)
856 return;
857
858 cur_trace->end_true_args_size = args_size;
859
860 /* If the CFA is computed off the stack pointer, then we must adjust
861 the computation of the CFA as well. */
862 if (cur_cfa->reg == dw_stack_pointer_regnum)
863 {
864 gcc_assert (!cur_cfa->indirect);
865
866 /* Convert a change in args_size (always a positive in the
867 direction of stack growth) to a change in stack pointer. */
868 #ifndef STACK_GROWS_DOWNWARD
869 delta = -delta;
870 #endif
871 cur_cfa->offset += delta;
872 }
873 }
874
875 /* A subroutine of scan_trace. INSN is can_throw_internal. Update the
876 data within the trace related to EH insns and args_size. */
877
878 static void
879 notice_eh_throw (rtx insn)
880 {
881 HOST_WIDE_INT args_size;
882
883 args_size = cur_trace->end_true_args_size;
884 if (cur_trace->eh_head == NULL)
885 {
886 cur_trace->eh_head = insn;
887 cur_trace->beg_delay_args_size = args_size;
888 cur_trace->end_delay_args_size = args_size;
889 }
890 else if (cur_trace->end_delay_args_size != args_size)
891 {
892 cur_trace->end_delay_args_size = args_size;
893
894 /* ??? If the CFA is the stack pointer, search backward for the last
895 CFI note and insert there. Given that the stack changed for the
896 args_size change, there *must* be such a note in between here and
897 the last eh insn. */
898 add_cfi_args_size (args_size);
899 }
900 }
901
902 /* Short-hand inline for the very common D_F_R (REGNO (x)) operation. */
903 /* ??? This ought to go into dwarf2out.h, except that dwarf2out.h is
904 used in places where rtl is prohibited. */
905
906 static inline unsigned
907 dwf_regno (const_rtx reg)
908 {
909 gcc_assert (REGNO (reg) < FIRST_PSEUDO_REGISTER);
910 return DWARF_FRAME_REGNUM (REGNO (reg));
911 }
912
913 /* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */
914
915 static bool
916 compare_reg_or_pc (rtx x, rtx y)
917 {
918 if (REG_P (x) && REG_P (y))
919 return REGNO (x) == REGNO (y);
920 return x == y;
921 }
922
923 /* Record SRC as being saved in DEST. DEST may be null to delete an
924 existing entry. SRC may be a register or PC_RTX. */
925
926 static void
927 record_reg_saved_in_reg (rtx dest, rtx src)
928 {
929 reg_saved_in_data *elt;
930 size_t i;
931
932 FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, elt)
933 if (compare_reg_or_pc (elt->orig_reg, src))
934 {
935 if (dest == NULL)
936 cur_trace->regs_saved_in_regs.unordered_remove (i);
937 else
938 elt->saved_in_reg = dest;
939 return;
940 }
941
942 if (dest == NULL)
943 return;
944
945 reg_saved_in_data e = {src, dest};
946 cur_trace->regs_saved_in_regs.safe_push (e);
947 }
948
949 /* Add an entry to QUEUED_REG_SAVES saying that REG is now saved at
950 SREG, or if SREG is NULL then it is saved at OFFSET to the CFA. */
951
952 static void
953 queue_reg_save (rtx reg, rtx sreg, HOST_WIDE_INT offset)
954 {
955 queued_reg_save *q;
956 queued_reg_save e = {reg, sreg, offset};
957 size_t i;
958
959 /* Duplicates waste space, but it's also necessary to remove them
960 for correctness, since the queue gets output in reverse order. */
961 FOR_EACH_VEC_ELT (queued_reg_saves, i, q)
962 if (compare_reg_or_pc (q->reg, reg))
963 {
964 *q = e;
965 return;
966 }
967
968 queued_reg_saves.safe_push (e);
969 }
970
971 /* Output all the entries in QUEUED_REG_SAVES. */
972
973 static void
974 dwarf2out_flush_queued_reg_saves (void)
975 {
976 queued_reg_save *q;
977 size_t i;
978
979 FOR_EACH_VEC_ELT (queued_reg_saves, i, q)
980 {
981 unsigned int reg, sreg;
982
983 record_reg_saved_in_reg (q->saved_reg, q->reg);
984
985 if (q->reg == pc_rtx)
986 reg = DWARF_FRAME_RETURN_COLUMN;
987 else
988 reg = dwf_regno (q->reg);
989 if (q->saved_reg)
990 sreg = dwf_regno (q->saved_reg);
991 else
992 sreg = INVALID_REGNUM;
993 reg_save (reg, sreg, q->cfa_offset);
994 }
995
996 queued_reg_saves.truncate (0);
997 }
998
999 /* Does INSN clobber any register which QUEUED_REG_SAVES lists a saved
1000 location for? Or, does it clobber a register which we've previously
1001 said that some other register is saved in, and for which we now
1002 have a new location for? */
1003
1004 static bool
1005 clobbers_queued_reg_save (const_rtx insn)
1006 {
1007 queued_reg_save *q;
1008 size_t iq;
1009
1010 FOR_EACH_VEC_ELT (queued_reg_saves, iq, q)
1011 {
1012 size_t ir;
1013 reg_saved_in_data *rir;
1014
1015 if (modified_in_p (q->reg, insn))
1016 return true;
1017
1018 FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, ir, rir)
1019 if (compare_reg_or_pc (q->reg, rir->orig_reg)
1020 && modified_in_p (rir->saved_in_reg, insn))
1021 return true;
1022 }
1023
1024 return false;
1025 }
1026
1027 /* What register, if any, is currently saved in REG? */
1028
1029 static rtx
1030 reg_saved_in (rtx reg)
1031 {
1032 unsigned int regn = REGNO (reg);
1033 queued_reg_save *q;
1034 reg_saved_in_data *rir;
1035 size_t i;
1036
1037 FOR_EACH_VEC_ELT (queued_reg_saves, i, q)
1038 if (q->saved_reg && regn == REGNO (q->saved_reg))
1039 return q->reg;
1040
1041 FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, rir)
1042 if (regn == REGNO (rir->saved_in_reg))
1043 return rir->orig_reg;
1044
1045 return NULL_RTX;
1046 }
1047
1048 /* A subroutine of dwarf2out_frame_debug, process a REG_DEF_CFA note. */
1049
1050 static void
1051 dwarf2out_frame_debug_def_cfa (rtx pat)
1052 {
1053 memset (cur_cfa, 0, sizeof (*cur_cfa));
1054
1055 if (GET_CODE (pat) == PLUS)
1056 {
1057 cur_cfa->offset = INTVAL (XEXP (pat, 1));
1058 pat = XEXP (pat, 0);
1059 }
1060 if (MEM_P (pat))
1061 {
1062 cur_cfa->indirect = 1;
1063 pat = XEXP (pat, 0);
1064 if (GET_CODE (pat) == PLUS)
1065 {
1066 cur_cfa->base_offset = INTVAL (XEXP (pat, 1));
1067 pat = XEXP (pat, 0);
1068 }
1069 }
1070 /* ??? If this fails, we could be calling into the _loc functions to
1071 define a full expression. So far no port does that. */
1072 gcc_assert (REG_P (pat));
1073 cur_cfa->reg = dwf_regno (pat);
1074 }
1075
1076 /* A subroutine of dwarf2out_frame_debug, process a REG_ADJUST_CFA note. */
1077
1078 static void
1079 dwarf2out_frame_debug_adjust_cfa (rtx pat)
1080 {
1081 rtx src, dest;
1082
1083 gcc_assert (GET_CODE (pat) == SET);
1084 dest = XEXP (pat, 0);
1085 src = XEXP (pat, 1);
1086
1087 switch (GET_CODE (src))
1088 {
1089 case PLUS:
1090 gcc_assert (dwf_regno (XEXP (src, 0)) == cur_cfa->reg);
1091 cur_cfa->offset -= INTVAL (XEXP (src, 1));
1092 break;
1093
1094 case REG:
1095 break;
1096
1097 default:
1098 gcc_unreachable ();
1099 }
1100
1101 cur_cfa->reg = dwf_regno (dest);
1102 gcc_assert (cur_cfa->indirect == 0);
1103 }
1104
1105 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_OFFSET note. */
1106
1107 static void
1108 dwarf2out_frame_debug_cfa_offset (rtx set)
1109 {
1110 HOST_WIDE_INT offset;
1111 rtx src, addr, span;
1112 unsigned int sregno;
1113
1114 src = XEXP (set, 1);
1115 addr = XEXP (set, 0);
1116 gcc_assert (MEM_P (addr));
1117 addr = XEXP (addr, 0);
1118
1119 /* As documented, only consider extremely simple addresses. */
1120 switch (GET_CODE (addr))
1121 {
1122 case REG:
1123 gcc_assert (dwf_regno (addr) == cur_cfa->reg);
1124 offset = -cur_cfa->offset;
1125 break;
1126 case PLUS:
1127 gcc_assert (dwf_regno (XEXP (addr, 0)) == cur_cfa->reg);
1128 offset = INTVAL (XEXP (addr, 1)) - cur_cfa->offset;
1129 break;
1130 default:
1131 gcc_unreachable ();
1132 }
1133
1134 if (src == pc_rtx)
1135 {
1136 span = NULL;
1137 sregno = DWARF_FRAME_RETURN_COLUMN;
1138 }
1139 else
1140 {
1141 span = targetm.dwarf_register_span (src);
1142 sregno = dwf_regno (src);
1143 }
1144
1145 /* ??? We'd like to use queue_reg_save, but we need to come up with
1146 a different flushing heuristic for epilogues. */
1147 if (!span)
1148 reg_save (sregno, INVALID_REGNUM, offset);
1149 else
1150 {
1151 /* We have a PARALLEL describing where the contents of SRC live.
1152 Queue register saves for each piece of the PARALLEL. */
1153 int par_index;
1154 int limit;
1155 HOST_WIDE_INT span_offset = offset;
1156
1157 gcc_assert (GET_CODE (span) == PARALLEL);
1158
1159 limit = XVECLEN (span, 0);
1160 for (par_index = 0; par_index < limit; par_index++)
1161 {
1162 rtx elem = XVECEXP (span, 0, par_index);
1163
1164 sregno = dwf_regno (src);
1165 reg_save (sregno, INVALID_REGNUM, span_offset);
1166 span_offset += GET_MODE_SIZE (GET_MODE (elem));
1167 }
1168 }
1169 }
1170
1171 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_REGISTER note. */
1172
1173 static void
1174 dwarf2out_frame_debug_cfa_register (rtx set)
1175 {
1176 rtx src, dest;
1177 unsigned sregno, dregno;
1178
1179 src = XEXP (set, 1);
1180 dest = XEXP (set, 0);
1181
1182 record_reg_saved_in_reg (dest, src);
1183 if (src == pc_rtx)
1184 sregno = DWARF_FRAME_RETURN_COLUMN;
1185 else
1186 sregno = dwf_regno (src);
1187
1188 dregno = dwf_regno (dest);
1189
1190 /* ??? We'd like to use queue_reg_save, but we need to come up with
1191 a different flushing heuristic for epilogues. */
1192 reg_save (sregno, dregno, 0);
1193 }
1194
1195 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */
1196
1197 static void
1198 dwarf2out_frame_debug_cfa_expression (rtx set)
1199 {
1200 rtx src, dest, span;
1201 dw_cfi_ref cfi = new_cfi ();
1202 unsigned regno;
1203
1204 dest = SET_DEST (set);
1205 src = SET_SRC (set);
1206
1207 gcc_assert (REG_P (src));
1208 gcc_assert (MEM_P (dest));
1209
1210 span = targetm.dwarf_register_span (src);
1211 gcc_assert (!span);
1212
1213 regno = dwf_regno (src);
1214
1215 cfi->dw_cfi_opc = DW_CFA_expression;
1216 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = regno;
1217 cfi->dw_cfi_oprnd2.dw_cfi_loc
1218 = mem_loc_descriptor (XEXP (dest, 0), get_address_mode (dest),
1219 GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED);
1220
1221 /* ??? We'd like to use queue_reg_save, were the interface different,
1222 and, as above, we could manage flushing for epilogues. */
1223 add_cfi (cfi);
1224 update_row_reg_save (cur_row, regno, cfi);
1225 }
1226
1227 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */
1228
1229 static void
1230 dwarf2out_frame_debug_cfa_restore (rtx reg)
1231 {
1232 unsigned int regno = dwf_regno (reg);
1233
1234 add_cfi_restore (regno);
1235 update_row_reg_save (cur_row, regno, NULL);
1236 }
1237
1238 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_WINDOW_SAVE.
1239 ??? Perhaps we should note in the CIE where windows are saved (instead of
1240 assuming 0(cfa)) and what registers are in the window. */
1241
1242 static void
1243 dwarf2out_frame_debug_cfa_window_save (void)
1244 {
1245 dw_cfi_ref cfi = new_cfi ();
1246
1247 cfi->dw_cfi_opc = DW_CFA_GNU_window_save;
1248 add_cfi (cfi);
1249 }
1250
1251 /* Record call frame debugging information for an expression EXPR,
1252 which either sets SP or FP (adjusting how we calculate the frame
1253 address) or saves a register to the stack or another register.
1254 LABEL indicates the address of EXPR.
1255
1256 This function encodes a state machine mapping rtxes to actions on
1257 cfa, cfa_store, and cfa_temp.reg. We describe these rules so
1258 users need not read the source code.
1259
1260 The High-Level Picture
1261
1262 Changes in the register we use to calculate the CFA: Currently we
1263 assume that if you copy the CFA register into another register, we
1264 should take the other one as the new CFA register; this seems to
1265 work pretty well. If it's wrong for some target, it's simple
1266 enough not to set RTX_FRAME_RELATED_P on the insn in question.
1267
1268 Changes in the register we use for saving registers to the stack:
1269 This is usually SP, but not always. Again, we deduce that if you
1270 copy SP into another register (and SP is not the CFA register),
1271 then the new register is the one we will be using for register
1272 saves. This also seems to work.
1273
1274 Register saves: There's not much guesswork about this one; if
1275 RTX_FRAME_RELATED_P is set on an insn which modifies memory, it's a
1276 register save, and the register used to calculate the destination
1277 had better be the one we think we're using for this purpose.
1278 It's also assumed that a copy from a call-saved register to another
1279 register is saving that register if RTX_FRAME_RELATED_P is set on
1280 that instruction. If the copy is from a call-saved register to
1281 the *same* register, that means that the register is now the same
1282 value as in the caller.
1283
1284 Except: If the register being saved is the CFA register, and the
1285 offset is nonzero, we are saving the CFA, so we assume we have to
1286 use DW_CFA_def_cfa_expression. If the offset is 0, we assume that
1287 the intent is to save the value of SP from the previous frame.
1288
1289 In addition, if a register has previously been saved to a different
1290 register,
1291
1292 Invariants / Summaries of Rules
1293
1294 cfa current rule for calculating the CFA. It usually
1295 consists of a register and an offset. This is
1296 actually stored in *cur_cfa, but abbreviated
1297 for the purposes of this documentation.
1298 cfa_store register used by prologue code to save things to the stack
1299 cfa_store.offset is the offset from the value of
1300 cfa_store.reg to the actual CFA
1301 cfa_temp register holding an integral value. cfa_temp.offset
1302 stores the value, which will be used to adjust the
1303 stack pointer. cfa_temp is also used like cfa_store,
1304 to track stores to the stack via fp or a temp reg.
1305
1306 Rules 1- 4: Setting a register's value to cfa.reg or an expression
1307 with cfa.reg as the first operand changes the cfa.reg and its
1308 cfa.offset. Rule 1 and 4 also set cfa_temp.reg and
1309 cfa_temp.offset.
1310
1311 Rules 6- 9: Set a non-cfa.reg register value to a constant or an
1312 expression yielding a constant. This sets cfa_temp.reg
1313 and cfa_temp.offset.
1314
1315 Rule 5: Create a new register cfa_store used to save items to the
1316 stack.
1317
1318 Rules 10-14: Save a register to the stack. Define offset as the
1319 difference of the original location and cfa_store's
1320 location (or cfa_temp's location if cfa_temp is used).
1321
1322 Rules 16-20: If AND operation happens on sp in prologue, we assume
1323 stack is realigned. We will use a group of DW_OP_XXX
1324 expressions to represent the location of the stored
1325 register instead of CFA+offset.
1326
1327 The Rules
1328
1329 "{a,b}" indicates a choice of a xor b.
1330 "<reg>:cfa.reg" indicates that <reg> must equal cfa.reg.
1331
1332 Rule 1:
1333 (set <reg1> <reg2>:cfa.reg)
1334 effects: cfa.reg = <reg1>
1335 cfa.offset unchanged
1336 cfa_temp.reg = <reg1>
1337 cfa_temp.offset = cfa.offset
1338
1339 Rule 2:
1340 (set sp ({minus,plus,losum} {sp,fp}:cfa.reg
1341 {<const_int>,<reg>:cfa_temp.reg}))
1342 effects: cfa.reg = sp if fp used
1343 cfa.offset += {+/- <const_int>, cfa_temp.offset} if cfa.reg==sp
1344 cfa_store.offset += {+/- <const_int>, cfa_temp.offset}
1345 if cfa_store.reg==sp
1346
1347 Rule 3:
1348 (set fp ({minus,plus,losum} <reg>:cfa.reg <const_int>))
1349 effects: cfa.reg = fp
1350 cfa_offset += +/- <const_int>
1351
1352 Rule 4:
1353 (set <reg1> ({plus,losum} <reg2>:cfa.reg <const_int>))
1354 constraints: <reg1> != fp
1355 <reg1> != sp
1356 effects: cfa.reg = <reg1>
1357 cfa_temp.reg = <reg1>
1358 cfa_temp.offset = cfa.offset
1359
1360 Rule 5:
1361 (set <reg1> (plus <reg2>:cfa_temp.reg sp:cfa.reg))
1362 constraints: <reg1> != fp
1363 <reg1> != sp
1364 effects: cfa_store.reg = <reg1>
1365 cfa_store.offset = cfa.offset - cfa_temp.offset
1366
1367 Rule 6:
1368 (set <reg> <const_int>)
1369 effects: cfa_temp.reg = <reg>
1370 cfa_temp.offset = <const_int>
1371
1372 Rule 7:
1373 (set <reg1>:cfa_temp.reg (ior <reg2>:cfa_temp.reg <const_int>))
1374 effects: cfa_temp.reg = <reg1>
1375 cfa_temp.offset |= <const_int>
1376
1377 Rule 8:
1378 (set <reg> (high <exp>))
1379 effects: none
1380
1381 Rule 9:
1382 (set <reg> (lo_sum <exp> <const_int>))
1383 effects: cfa_temp.reg = <reg>
1384 cfa_temp.offset = <const_int>
1385
1386 Rule 10:
1387 (set (mem ({pre,post}_modify sp:cfa_store (???? <reg1> <const_int>))) <reg2>)
1388 effects: cfa_store.offset -= <const_int>
1389 cfa.offset = cfa_store.offset if cfa.reg == sp
1390 cfa.reg = sp
1391 cfa.base_offset = -cfa_store.offset
1392
1393 Rule 11:
1394 (set (mem ({pre_inc,pre_dec,post_dec} sp:cfa_store.reg)) <reg>)
1395 effects: cfa_store.offset += -/+ mode_size(mem)
1396 cfa.offset = cfa_store.offset if cfa.reg == sp
1397 cfa.reg = sp
1398 cfa.base_offset = -cfa_store.offset
1399
1400 Rule 12:
1401 (set (mem ({minus,plus,losum} <reg1>:{cfa_store,cfa_temp} <const_int>))
1402
1403 <reg2>)
1404 effects: cfa.reg = <reg1>
1405 cfa.base_offset = -/+ <const_int> - {cfa_store,cfa_temp}.offset
1406
1407 Rule 13:
1408 (set (mem <reg1>:{cfa_store,cfa_temp}) <reg2>)
1409 effects: cfa.reg = <reg1>
1410 cfa.base_offset = -{cfa_store,cfa_temp}.offset
1411
1412 Rule 14:
1413 (set (mem (post_inc <reg1>:cfa_temp <const_int>)) <reg2>)
1414 effects: cfa.reg = <reg1>
1415 cfa.base_offset = -cfa_temp.offset
1416 cfa_temp.offset -= mode_size(mem)
1417
1418 Rule 15:
1419 (set <reg> {unspec, unspec_volatile})
1420 effects: target-dependent
1421
1422 Rule 16:
1423 (set sp (and: sp <const_int>))
1424 constraints: cfa_store.reg == sp
1425 effects: cfun->fde.stack_realign = 1
1426 cfa_store.offset = 0
1427 fde->drap_reg = cfa.reg if cfa.reg != sp and cfa.reg != fp
1428
1429 Rule 17:
1430 (set (mem ({pre_inc, pre_dec} sp)) (mem (plus (cfa.reg) (const_int))))
1431 effects: cfa_store.offset += -/+ mode_size(mem)
1432
1433 Rule 18:
1434 (set (mem ({pre_inc, pre_dec} sp)) fp)
1435 constraints: fde->stack_realign == 1
1436 effects: cfa_store.offset = 0
1437 cfa.reg != HARD_FRAME_POINTER_REGNUM
1438
1439 Rule 19:
1440 (set (mem ({pre_inc, pre_dec} sp)) cfa.reg)
1441 constraints: fde->stack_realign == 1
1442 && cfa.offset == 0
1443 && cfa.indirect == 0
1444 && cfa.reg != HARD_FRAME_POINTER_REGNUM
1445 effects: Use DW_CFA_def_cfa_expression to define cfa
1446 cfa.reg == fde->drap_reg */
1447
1448 static void
1449 dwarf2out_frame_debug_expr (rtx expr)
1450 {
1451 rtx src, dest, span;
1452 HOST_WIDE_INT offset;
1453 dw_fde_ref fde;
1454
1455 /* If RTX_FRAME_RELATED_P is set on a PARALLEL, process each member of
1456 the PARALLEL independently. The first element is always processed if
1457 it is a SET. This is for backward compatibility. Other elements
1458 are processed only if they are SETs and the RTX_FRAME_RELATED_P
1459 flag is set in them. */
1460 if (GET_CODE (expr) == PARALLEL || GET_CODE (expr) == SEQUENCE)
1461 {
1462 int par_index;
1463 int limit = XVECLEN (expr, 0);
1464 rtx elem;
1465
1466 /* PARALLELs have strict read-modify-write semantics, so we
1467 ought to evaluate every rvalue before changing any lvalue.
1468 It's cumbersome to do that in general, but there's an
1469 easy approximation that is enough for all current users:
1470 handle register saves before register assignments. */
1471 if (GET_CODE (expr) == PARALLEL)
1472 for (par_index = 0; par_index < limit; par_index++)
1473 {
1474 elem = XVECEXP (expr, 0, par_index);
1475 if (GET_CODE (elem) == SET
1476 && MEM_P (SET_DEST (elem))
1477 && (RTX_FRAME_RELATED_P (elem) || par_index == 0))
1478 dwarf2out_frame_debug_expr (elem);
1479 }
1480
1481 for (par_index = 0; par_index < limit; par_index++)
1482 {
1483 elem = XVECEXP (expr, 0, par_index);
1484 if (GET_CODE (elem) == SET
1485 && (!MEM_P (SET_DEST (elem)) || GET_CODE (expr) == SEQUENCE)
1486 && (RTX_FRAME_RELATED_P (elem) || par_index == 0))
1487 dwarf2out_frame_debug_expr (elem);
1488 }
1489 return;
1490 }
1491
1492 gcc_assert (GET_CODE (expr) == SET);
1493
1494 src = SET_SRC (expr);
1495 dest = SET_DEST (expr);
1496
1497 if (REG_P (src))
1498 {
1499 rtx rsi = reg_saved_in (src);
1500 if (rsi)
1501 src = rsi;
1502 }
1503
1504 fde = cfun->fde;
1505
1506 switch (GET_CODE (dest))
1507 {
1508 case REG:
1509 switch (GET_CODE (src))
1510 {
1511 /* Setting FP from SP. */
1512 case REG:
1513 if (cur_cfa->reg == dwf_regno (src))
1514 {
1515 /* Rule 1 */
1516 /* Update the CFA rule wrt SP or FP. Make sure src is
1517 relative to the current CFA register.
1518
1519 We used to require that dest be either SP or FP, but the
1520 ARM copies SP to a temporary register, and from there to
1521 FP. So we just rely on the backends to only set
1522 RTX_FRAME_RELATED_P on appropriate insns. */
1523 cur_cfa->reg = dwf_regno (dest);
1524 cur_trace->cfa_temp.reg = cur_cfa->reg;
1525 cur_trace->cfa_temp.offset = cur_cfa->offset;
1526 }
1527 else
1528 {
1529 /* Saving a register in a register. */
1530 gcc_assert (!fixed_regs [REGNO (dest)]
1531 /* For the SPARC and its register window. */
1532 || (dwf_regno (src) == DWARF_FRAME_RETURN_COLUMN));
1533
1534 /* After stack is aligned, we can only save SP in FP
1535 if drap register is used. In this case, we have
1536 to restore stack pointer with the CFA value and we
1537 don't generate this DWARF information. */
1538 if (fde
1539 && fde->stack_realign
1540 && REGNO (src) == STACK_POINTER_REGNUM)
1541 gcc_assert (REGNO (dest) == HARD_FRAME_POINTER_REGNUM
1542 && fde->drap_reg != INVALID_REGNUM
1543 && cur_cfa->reg != dwf_regno (src));
1544 else
1545 queue_reg_save (src, dest, 0);
1546 }
1547 break;
1548
1549 case PLUS:
1550 case MINUS:
1551 case LO_SUM:
1552 if (dest == stack_pointer_rtx)
1553 {
1554 /* Rule 2 */
1555 /* Adjusting SP. */
1556 switch (GET_CODE (XEXP (src, 1)))
1557 {
1558 case CONST_INT:
1559 offset = INTVAL (XEXP (src, 1));
1560 break;
1561 case REG:
1562 gcc_assert (dwf_regno (XEXP (src, 1))
1563 == cur_trace->cfa_temp.reg);
1564 offset = cur_trace->cfa_temp.offset;
1565 break;
1566 default:
1567 gcc_unreachable ();
1568 }
1569
1570 if (XEXP (src, 0) == hard_frame_pointer_rtx)
1571 {
1572 /* Restoring SP from FP in the epilogue. */
1573 gcc_assert (cur_cfa->reg == dw_frame_pointer_regnum);
1574 cur_cfa->reg = dw_stack_pointer_regnum;
1575 }
1576 else if (GET_CODE (src) == LO_SUM)
1577 /* Assume we've set the source reg of the LO_SUM from sp. */
1578 ;
1579 else
1580 gcc_assert (XEXP (src, 0) == stack_pointer_rtx);
1581
1582 if (GET_CODE (src) != MINUS)
1583 offset = -offset;
1584 if (cur_cfa->reg == dw_stack_pointer_regnum)
1585 cur_cfa->offset += offset;
1586 if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum)
1587 cur_trace->cfa_store.offset += offset;
1588 }
1589 else if (dest == hard_frame_pointer_rtx)
1590 {
1591 /* Rule 3 */
1592 /* Either setting the FP from an offset of the SP,
1593 or adjusting the FP */
1594 gcc_assert (frame_pointer_needed);
1595
1596 gcc_assert (REG_P (XEXP (src, 0))
1597 && dwf_regno (XEXP (src, 0)) == cur_cfa->reg
1598 && CONST_INT_P (XEXP (src, 1)));
1599 offset = INTVAL (XEXP (src, 1));
1600 if (GET_CODE (src) != MINUS)
1601 offset = -offset;
1602 cur_cfa->offset += offset;
1603 cur_cfa->reg = dw_frame_pointer_regnum;
1604 }
1605 else
1606 {
1607 gcc_assert (GET_CODE (src) != MINUS);
1608
1609 /* Rule 4 */
1610 if (REG_P (XEXP (src, 0))
1611 && dwf_regno (XEXP (src, 0)) == cur_cfa->reg
1612 && CONST_INT_P (XEXP (src, 1)))
1613 {
1614 /* Setting a temporary CFA register that will be copied
1615 into the FP later on. */
1616 offset = - INTVAL (XEXP (src, 1));
1617 cur_cfa->offset += offset;
1618 cur_cfa->reg = dwf_regno (dest);
1619 /* Or used to save regs to the stack. */
1620 cur_trace->cfa_temp.reg = cur_cfa->reg;
1621 cur_trace->cfa_temp.offset = cur_cfa->offset;
1622 }
1623
1624 /* Rule 5 */
1625 else if (REG_P (XEXP (src, 0))
1626 && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg
1627 && XEXP (src, 1) == stack_pointer_rtx)
1628 {
1629 /* Setting a scratch register that we will use instead
1630 of SP for saving registers to the stack. */
1631 gcc_assert (cur_cfa->reg == dw_stack_pointer_regnum);
1632 cur_trace->cfa_store.reg = dwf_regno (dest);
1633 cur_trace->cfa_store.offset
1634 = cur_cfa->offset - cur_trace->cfa_temp.offset;
1635 }
1636
1637 /* Rule 9 */
1638 else if (GET_CODE (src) == LO_SUM
1639 && CONST_INT_P (XEXP (src, 1)))
1640 {
1641 cur_trace->cfa_temp.reg = dwf_regno (dest);
1642 cur_trace->cfa_temp.offset = INTVAL (XEXP (src, 1));
1643 }
1644 else
1645 gcc_unreachable ();
1646 }
1647 break;
1648
1649 /* Rule 6 */
1650 case CONST_INT:
1651 cur_trace->cfa_temp.reg = dwf_regno (dest);
1652 cur_trace->cfa_temp.offset = INTVAL (src);
1653 break;
1654
1655 /* Rule 7 */
1656 case IOR:
1657 gcc_assert (REG_P (XEXP (src, 0))
1658 && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg
1659 && CONST_INT_P (XEXP (src, 1)));
1660
1661 cur_trace->cfa_temp.reg = dwf_regno (dest);
1662 cur_trace->cfa_temp.offset |= INTVAL (XEXP (src, 1));
1663 break;
1664
1665 /* Skip over HIGH, assuming it will be followed by a LO_SUM,
1666 which will fill in all of the bits. */
1667 /* Rule 8 */
1668 case HIGH:
1669 break;
1670
1671 /* Rule 15 */
1672 case UNSPEC:
1673 case UNSPEC_VOLATILE:
1674 /* All unspecs should be represented by REG_CFA_* notes. */
1675 gcc_unreachable ();
1676 return;
1677
1678 /* Rule 16 */
1679 case AND:
1680 /* If this AND operation happens on stack pointer in prologue,
1681 we assume the stack is realigned and we extract the
1682 alignment. */
1683 if (fde && XEXP (src, 0) == stack_pointer_rtx)
1684 {
1685 /* We interpret reg_save differently with stack_realign set.
1686 Thus we must flush whatever we have queued first. */
1687 dwarf2out_flush_queued_reg_saves ();
1688
1689 gcc_assert (cur_trace->cfa_store.reg
1690 == dwf_regno (XEXP (src, 0)));
1691 fde->stack_realign = 1;
1692 fde->stack_realignment = INTVAL (XEXP (src, 1));
1693 cur_trace->cfa_store.offset = 0;
1694
1695 if (cur_cfa->reg != dw_stack_pointer_regnum
1696 && cur_cfa->reg != dw_frame_pointer_regnum)
1697 fde->drap_reg = cur_cfa->reg;
1698 }
1699 return;
1700
1701 default:
1702 gcc_unreachable ();
1703 }
1704 break;
1705
1706 case MEM:
1707
1708 /* Saving a register to the stack. Make sure dest is relative to the
1709 CFA register. */
1710 switch (GET_CODE (XEXP (dest, 0)))
1711 {
1712 /* Rule 10 */
1713 /* With a push. */
1714 case PRE_MODIFY:
1715 case POST_MODIFY:
1716 /* We can't handle variable size modifications. */
1717 gcc_assert (GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1))
1718 == CONST_INT);
1719 offset = -INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1));
1720
1721 gcc_assert (REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
1722 && cur_trace->cfa_store.reg == dw_stack_pointer_regnum);
1723
1724 cur_trace->cfa_store.offset += offset;
1725 if (cur_cfa->reg == dw_stack_pointer_regnum)
1726 cur_cfa->offset = cur_trace->cfa_store.offset;
1727
1728 if (GET_CODE (XEXP (dest, 0)) == POST_MODIFY)
1729 offset -= cur_trace->cfa_store.offset;
1730 else
1731 offset = -cur_trace->cfa_store.offset;
1732 break;
1733
1734 /* Rule 11 */
1735 case PRE_INC:
1736 case PRE_DEC:
1737 case POST_DEC:
1738 offset = GET_MODE_SIZE (GET_MODE (dest));
1739 if (GET_CODE (XEXP (dest, 0)) == PRE_INC)
1740 offset = -offset;
1741
1742 gcc_assert ((REGNO (XEXP (XEXP (dest, 0), 0))
1743 == STACK_POINTER_REGNUM)
1744 && cur_trace->cfa_store.reg == dw_stack_pointer_regnum);
1745
1746 cur_trace->cfa_store.offset += offset;
1747
1748 /* Rule 18: If stack is aligned, we will use FP as a
1749 reference to represent the address of the stored
1750 regiser. */
1751 if (fde
1752 && fde->stack_realign
1753 && REG_P (src)
1754 && REGNO (src) == HARD_FRAME_POINTER_REGNUM)
1755 {
1756 gcc_assert (cur_cfa->reg != dw_frame_pointer_regnum);
1757 cur_trace->cfa_store.offset = 0;
1758 }
1759
1760 if (cur_cfa->reg == dw_stack_pointer_regnum)
1761 cur_cfa->offset = cur_trace->cfa_store.offset;
1762
1763 if (GET_CODE (XEXP (dest, 0)) == POST_DEC)
1764 offset += -cur_trace->cfa_store.offset;
1765 else
1766 offset = -cur_trace->cfa_store.offset;
1767 break;
1768
1769 /* Rule 12 */
1770 /* With an offset. */
1771 case PLUS:
1772 case MINUS:
1773 case LO_SUM:
1774 {
1775 unsigned int regno;
1776
1777 gcc_assert (CONST_INT_P (XEXP (XEXP (dest, 0), 1))
1778 && REG_P (XEXP (XEXP (dest, 0), 0)));
1779 offset = INTVAL (XEXP (XEXP (dest, 0), 1));
1780 if (GET_CODE (XEXP (dest, 0)) == MINUS)
1781 offset = -offset;
1782
1783 regno = dwf_regno (XEXP (XEXP (dest, 0), 0));
1784
1785 if (cur_cfa->reg == regno)
1786 offset -= cur_cfa->offset;
1787 else if (cur_trace->cfa_store.reg == regno)
1788 offset -= cur_trace->cfa_store.offset;
1789 else
1790 {
1791 gcc_assert (cur_trace->cfa_temp.reg == regno);
1792 offset -= cur_trace->cfa_temp.offset;
1793 }
1794 }
1795 break;
1796
1797 /* Rule 13 */
1798 /* Without an offset. */
1799 case REG:
1800 {
1801 unsigned int regno = dwf_regno (XEXP (dest, 0));
1802
1803 if (cur_cfa->reg == regno)
1804 offset = -cur_cfa->offset;
1805 else if (cur_trace->cfa_store.reg == regno)
1806 offset = -cur_trace->cfa_store.offset;
1807 else
1808 {
1809 gcc_assert (cur_trace->cfa_temp.reg == regno);
1810 offset = -cur_trace->cfa_temp.offset;
1811 }
1812 }
1813 break;
1814
1815 /* Rule 14 */
1816 case POST_INC:
1817 gcc_assert (cur_trace->cfa_temp.reg
1818 == dwf_regno (XEXP (XEXP (dest, 0), 0)));
1819 offset = -cur_trace->cfa_temp.offset;
1820 cur_trace->cfa_temp.offset -= GET_MODE_SIZE (GET_MODE (dest));
1821 break;
1822
1823 default:
1824 gcc_unreachable ();
1825 }
1826
1827 /* Rule 17 */
1828 /* If the source operand of this MEM operation is a memory,
1829 we only care how much stack grew. */
1830 if (MEM_P (src))
1831 break;
1832
1833 if (REG_P (src)
1834 && REGNO (src) != STACK_POINTER_REGNUM
1835 && REGNO (src) != HARD_FRAME_POINTER_REGNUM
1836 && dwf_regno (src) == cur_cfa->reg)
1837 {
1838 /* We're storing the current CFA reg into the stack. */
1839
1840 if (cur_cfa->offset == 0)
1841 {
1842 /* Rule 19 */
1843 /* If stack is aligned, putting CFA reg into stack means
1844 we can no longer use reg + offset to represent CFA.
1845 Here we use DW_CFA_def_cfa_expression instead. The
1846 result of this expression equals to the original CFA
1847 value. */
1848 if (fde
1849 && fde->stack_realign
1850 && cur_cfa->indirect == 0
1851 && cur_cfa->reg != dw_frame_pointer_regnum)
1852 {
1853 gcc_assert (fde->drap_reg == cur_cfa->reg);
1854
1855 cur_cfa->indirect = 1;
1856 cur_cfa->reg = dw_frame_pointer_regnum;
1857 cur_cfa->base_offset = offset;
1858 cur_cfa->offset = 0;
1859
1860 fde->drap_reg_saved = 1;
1861 break;
1862 }
1863
1864 /* If the source register is exactly the CFA, assume
1865 we're saving SP like any other register; this happens
1866 on the ARM. */
1867 queue_reg_save (stack_pointer_rtx, NULL_RTX, offset);
1868 break;
1869 }
1870 else
1871 {
1872 /* Otherwise, we'll need to look in the stack to
1873 calculate the CFA. */
1874 rtx x = XEXP (dest, 0);
1875
1876 if (!REG_P (x))
1877 x = XEXP (x, 0);
1878 gcc_assert (REG_P (x));
1879
1880 cur_cfa->reg = dwf_regno (x);
1881 cur_cfa->base_offset = offset;
1882 cur_cfa->indirect = 1;
1883 break;
1884 }
1885 }
1886
1887 span = NULL;
1888 if (REG_P (src))
1889 span = targetm.dwarf_register_span (src);
1890 if (!span)
1891 queue_reg_save (src, NULL_RTX, offset);
1892 else
1893 {
1894 /* We have a PARALLEL describing where the contents of SRC live.
1895 Queue register saves for each piece of the PARALLEL. */
1896 int par_index;
1897 int limit;
1898 HOST_WIDE_INT span_offset = offset;
1899
1900 gcc_assert (GET_CODE (span) == PARALLEL);
1901
1902 limit = XVECLEN (span, 0);
1903 for (par_index = 0; par_index < limit; par_index++)
1904 {
1905 rtx elem = XVECEXP (span, 0, par_index);
1906 queue_reg_save (elem, NULL_RTX, span_offset);
1907 span_offset += GET_MODE_SIZE (GET_MODE (elem));
1908 }
1909 }
1910 break;
1911
1912 default:
1913 gcc_unreachable ();
1914 }
1915 }
1916
1917 /* Record call frame debugging information for INSN, which either sets
1918 SP or FP (adjusting how we calculate the frame address) or saves a
1919 register to the stack. */
1920
1921 static void
1922 dwarf2out_frame_debug (rtx insn)
1923 {
1924 rtx note, n;
1925 bool handled_one = false;
1926
1927 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
1928 switch (REG_NOTE_KIND (note))
1929 {
1930 case REG_FRAME_RELATED_EXPR:
1931 insn = XEXP (note, 0);
1932 goto do_frame_expr;
1933
1934 case REG_CFA_DEF_CFA:
1935 dwarf2out_frame_debug_def_cfa (XEXP (note, 0));
1936 handled_one = true;
1937 break;
1938
1939 case REG_CFA_ADJUST_CFA:
1940 n = XEXP (note, 0);
1941 if (n == NULL)
1942 {
1943 n = PATTERN (insn);
1944 if (GET_CODE (n) == PARALLEL)
1945 n = XVECEXP (n, 0, 0);
1946 }
1947 dwarf2out_frame_debug_adjust_cfa (n);
1948 handled_one = true;
1949 break;
1950
1951 case REG_CFA_OFFSET:
1952 n = XEXP (note, 0);
1953 if (n == NULL)
1954 n = single_set (insn);
1955 dwarf2out_frame_debug_cfa_offset (n);
1956 handled_one = true;
1957 break;
1958
1959 case REG_CFA_REGISTER:
1960 n = XEXP (note, 0);
1961 if (n == NULL)
1962 {
1963 n = PATTERN (insn);
1964 if (GET_CODE (n) == PARALLEL)
1965 n = XVECEXP (n, 0, 0);
1966 }
1967 dwarf2out_frame_debug_cfa_register (n);
1968 handled_one = true;
1969 break;
1970
1971 case REG_CFA_EXPRESSION:
1972 n = XEXP (note, 0);
1973 if (n == NULL)
1974 n = single_set (insn);
1975 dwarf2out_frame_debug_cfa_expression (n);
1976 handled_one = true;
1977 break;
1978
1979 case REG_CFA_RESTORE:
1980 n = XEXP (note, 0);
1981 if (n == NULL)
1982 {
1983 n = PATTERN (insn);
1984 if (GET_CODE (n) == PARALLEL)
1985 n = XVECEXP (n, 0, 0);
1986 n = XEXP (n, 0);
1987 }
1988 dwarf2out_frame_debug_cfa_restore (n);
1989 handled_one = true;
1990 break;
1991
1992 case REG_CFA_SET_VDRAP:
1993 n = XEXP (note, 0);
1994 if (REG_P (n))
1995 {
1996 dw_fde_ref fde = cfun->fde;
1997 if (fde)
1998 {
1999 gcc_assert (fde->vdrap_reg == INVALID_REGNUM);
2000 if (REG_P (n))
2001 fde->vdrap_reg = dwf_regno (n);
2002 }
2003 }
2004 handled_one = true;
2005 break;
2006
2007 case REG_CFA_WINDOW_SAVE:
2008 dwarf2out_frame_debug_cfa_window_save ();
2009 handled_one = true;
2010 break;
2011
2012 case REG_CFA_FLUSH_QUEUE:
2013 /* The actual flush happens elsewhere. */
2014 handled_one = true;
2015 break;
2016
2017 default:
2018 break;
2019 }
2020
2021 if (!handled_one)
2022 {
2023 insn = PATTERN (insn);
2024 do_frame_expr:
2025 dwarf2out_frame_debug_expr (insn);
2026
2027 /* Check again. A parallel can save and update the same register.
2028 We could probably check just once, here, but this is safer than
2029 removing the check at the start of the function. */
2030 if (clobbers_queued_reg_save (insn))
2031 dwarf2out_flush_queued_reg_saves ();
2032 }
2033 }
2034
2035 /* Emit CFI info to change the state from OLD_ROW to NEW_ROW. */
2036
2037 static void
2038 change_cfi_row (dw_cfi_row *old_row, dw_cfi_row *new_row)
2039 {
2040 size_t i, n_old, n_new, n_max;
2041 dw_cfi_ref cfi;
2042
2043 if (new_row->cfa_cfi && !cfi_equal_p (old_row->cfa_cfi, new_row->cfa_cfi))
2044 add_cfi (new_row->cfa_cfi);
2045 else
2046 {
2047 cfi = def_cfa_0 (&old_row->cfa, &new_row->cfa);
2048 if (cfi)
2049 add_cfi (cfi);
2050 }
2051
2052 n_old = vec_safe_length (old_row->reg_save);
2053 n_new = vec_safe_length (new_row->reg_save);
2054 n_max = MAX (n_old, n_new);
2055
2056 for (i = 0; i < n_max; ++i)
2057 {
2058 dw_cfi_ref r_old = NULL, r_new = NULL;
2059
2060 if (i < n_old)
2061 r_old = (*old_row->reg_save)[i];
2062 if (i < n_new)
2063 r_new = (*new_row->reg_save)[i];
2064
2065 if (r_old == r_new)
2066 ;
2067 else if (r_new == NULL)
2068 add_cfi_restore (i);
2069 else if (!cfi_equal_p (r_old, r_new))
2070 add_cfi (r_new);
2071 }
2072 }
2073
2074 /* Examine CFI and return true if a cfi label and set_loc is needed
2075 beforehand. Even when generating CFI assembler instructions, we
2076 still have to add the cfi to the list so that lookup_cfa_1 works
2077 later on. When -g2 and above we even need to force emitting of
2078 CFI labels and add to list a DW_CFA_set_loc for convert_cfa_to_fb_loc_list
2079 purposes. If we're generating DWARF3 output we use DW_OP_call_frame_cfa
2080 and so don't use convert_cfa_to_fb_loc_list. */
2081
2082 static bool
2083 cfi_label_required_p (dw_cfi_ref cfi)
2084 {
2085 if (!dwarf2out_do_cfi_asm ())
2086 return true;
2087
2088 if (dwarf_version == 2
2089 && debug_info_level > DINFO_LEVEL_TERSE
2090 && (write_symbols == DWARF2_DEBUG
2091 || write_symbols == VMS_AND_DWARF2_DEBUG))
2092 {
2093 switch (cfi->dw_cfi_opc)
2094 {
2095 case DW_CFA_def_cfa_offset:
2096 case DW_CFA_def_cfa_offset_sf:
2097 case DW_CFA_def_cfa_register:
2098 case DW_CFA_def_cfa:
2099 case DW_CFA_def_cfa_sf:
2100 case DW_CFA_def_cfa_expression:
2101 case DW_CFA_restore_state:
2102 return true;
2103 default:
2104 return false;
2105 }
2106 }
2107 return false;
2108 }
2109
2110 /* Walk the function, looking for NOTE_INSN_CFI notes. Add the CFIs to the
2111 function's FDE, adding CFI labels and set_loc/advance_loc opcodes as
2112 necessary. */
2113 static void
2114 add_cfis_to_fde (void)
2115 {
2116 dw_fde_ref fde = cfun->fde;
2117 rtx insn, next;
2118 /* We always start with a function_begin label. */
2119 bool first = false;
2120
2121 for (insn = get_insns (); insn; insn = next)
2122 {
2123 next = NEXT_INSN (insn);
2124
2125 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
2126 {
2127 fde->dw_fde_switch_cfi_index = vec_safe_length (fde->dw_fde_cfi);
2128 /* Don't attempt to advance_loc4 between labels
2129 in different sections. */
2130 first = true;
2131 }
2132
2133 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI)
2134 {
2135 bool required = cfi_label_required_p (NOTE_CFI (insn));
2136 while (next)
2137 if (NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_CFI)
2138 {
2139 required |= cfi_label_required_p (NOTE_CFI (next));
2140 next = NEXT_INSN (next);
2141 }
2142 else if (active_insn_p (next)
2143 || (NOTE_P (next) && (NOTE_KIND (next)
2144 == NOTE_INSN_SWITCH_TEXT_SECTIONS)))
2145 break;
2146 else
2147 next = NEXT_INSN (next);
2148 if (required)
2149 {
2150 int num = dwarf2out_cfi_label_num;
2151 const char *label = dwarf2out_cfi_label ();
2152 dw_cfi_ref xcfi;
2153 rtx tmp;
2154
2155 /* Set the location counter to the new label. */
2156 xcfi = new_cfi ();
2157 xcfi->dw_cfi_opc = (first ? DW_CFA_set_loc
2158 : DW_CFA_advance_loc4);
2159 xcfi->dw_cfi_oprnd1.dw_cfi_addr = label;
2160 vec_safe_push (fde->dw_fde_cfi, xcfi);
2161
2162 tmp = emit_note_before (NOTE_INSN_CFI_LABEL, insn);
2163 NOTE_LABEL_NUMBER (tmp) = num;
2164 }
2165
2166 do
2167 {
2168 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI)
2169 vec_safe_push (fde->dw_fde_cfi, NOTE_CFI (insn));
2170 insn = NEXT_INSN (insn);
2171 }
2172 while (insn != next);
2173 first = false;
2174 }
2175 }
2176 }
2177
2178 /* If LABEL is the start of a trace, then initialize the state of that
2179 trace from CUR_TRACE and CUR_ROW. */
2180
2181 static void
2182 maybe_record_trace_start (rtx start, rtx origin)
2183 {
2184 dw_trace_info *ti;
2185 HOST_WIDE_INT args_size;
2186
2187 ti = get_trace_info (start);
2188 gcc_assert (ti != NULL);
2189
2190 if (dump_file)
2191 {
2192 fprintf (dump_file, " saw edge from trace %u to %u (via %s %d)\n",
2193 cur_trace->id, ti->id,
2194 (origin ? rtx_name[(int) GET_CODE (origin)] : "fallthru"),
2195 (origin ? INSN_UID (origin) : 0));
2196 }
2197
2198 args_size = cur_trace->end_true_args_size;
2199 if (ti->beg_row == NULL)
2200 {
2201 /* This is the first time we've encountered this trace. Propagate
2202 state across the edge and push the trace onto the work list. */
2203 ti->beg_row = copy_cfi_row (cur_row);
2204 ti->beg_true_args_size = args_size;
2205
2206 ti->cfa_store = cur_trace->cfa_store;
2207 ti->cfa_temp = cur_trace->cfa_temp;
2208 ti->regs_saved_in_regs = cur_trace->regs_saved_in_regs.copy ();
2209
2210 trace_work_list.safe_push (ti);
2211
2212 if (dump_file)
2213 fprintf (dump_file, "\tpush trace %u to worklist\n", ti->id);
2214 }
2215 else
2216 {
2217
2218 /* We ought to have the same state incoming to a given trace no
2219 matter how we arrive at the trace. Anything else means we've
2220 got some kind of optimization error. */
2221 gcc_checking_assert (cfi_row_equal_p (cur_row, ti->beg_row));
2222
2223 /* The args_size is allowed to conflict if it isn't actually used. */
2224 if (ti->beg_true_args_size != args_size)
2225 ti->args_size_undefined = true;
2226 }
2227 }
2228
2229 /* Similarly, but handle the args_size and CFA reset across EH
2230 and non-local goto edges. */
2231
2232 static void
2233 maybe_record_trace_start_abnormal (rtx start, rtx origin)
2234 {
2235 HOST_WIDE_INT save_args_size, delta;
2236 dw_cfa_location save_cfa;
2237
2238 save_args_size = cur_trace->end_true_args_size;
2239 if (save_args_size == 0)
2240 {
2241 maybe_record_trace_start (start, origin);
2242 return;
2243 }
2244
2245 delta = -save_args_size;
2246 cur_trace->end_true_args_size = 0;
2247
2248 save_cfa = cur_row->cfa;
2249 if (cur_row->cfa.reg == dw_stack_pointer_regnum)
2250 {
2251 /* Convert a change in args_size (always a positive in the
2252 direction of stack growth) to a change in stack pointer. */
2253 #ifndef STACK_GROWS_DOWNWARD
2254 delta = -delta;
2255 #endif
2256 cur_row->cfa.offset += delta;
2257 }
2258
2259 maybe_record_trace_start (start, origin);
2260
2261 cur_trace->end_true_args_size = save_args_size;
2262 cur_row->cfa = save_cfa;
2263 }
2264
2265 /* Propagate CUR_TRACE state to the destinations implied by INSN. */
2266 /* ??? Sadly, this is in large part a duplicate of make_edges. */
2267
2268 static void
2269 create_trace_edges (rtx insn)
2270 {
2271 rtx tmp, lab;
2272 int i, n;
2273
2274 if (JUMP_P (insn))
2275 {
2276 if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
2277 return;
2278
2279 if (tablejump_p (insn, NULL, &tmp))
2280 {
2281 rtvec vec;
2282
2283 tmp = PATTERN (tmp);
2284 vec = XVEC (tmp, GET_CODE (tmp) == ADDR_DIFF_VEC);
2285
2286 n = GET_NUM_ELEM (vec);
2287 for (i = 0; i < n; ++i)
2288 {
2289 lab = XEXP (RTVEC_ELT (vec, i), 0);
2290 maybe_record_trace_start (lab, insn);
2291 }
2292 }
2293 else if (computed_jump_p (insn))
2294 {
2295 for (lab = forced_labels; lab; lab = XEXP (lab, 1))
2296 maybe_record_trace_start (XEXP (lab, 0), insn);
2297 }
2298 else if (returnjump_p (insn))
2299 ;
2300 else if ((tmp = extract_asm_operands (PATTERN (insn))) != NULL)
2301 {
2302 n = ASM_OPERANDS_LABEL_LENGTH (tmp);
2303 for (i = 0; i < n; ++i)
2304 {
2305 lab = XEXP (ASM_OPERANDS_LABEL (tmp, i), 0);
2306 maybe_record_trace_start (lab, insn);
2307 }
2308 }
2309 else
2310 {
2311 lab = JUMP_LABEL (insn);
2312 gcc_assert (lab != NULL);
2313 maybe_record_trace_start (lab, insn);
2314 }
2315 }
2316 else if (CALL_P (insn))
2317 {
2318 /* Sibling calls don't have edges inside this function. */
2319 if (SIBLING_CALL_P (insn))
2320 return;
2321
2322 /* Process non-local goto edges. */
2323 if (can_nonlocal_goto (insn))
2324 for (lab = nonlocal_goto_handler_labels; lab; lab = XEXP (lab, 1))
2325 maybe_record_trace_start_abnormal (XEXP (lab, 0), insn);
2326 }
2327 else if (GET_CODE (PATTERN (insn)) == SEQUENCE)
2328 {
2329 rtx seq = PATTERN (insn);
2330 int i, n = XVECLEN (seq, 0);
2331 for (i = 0; i < n; ++i)
2332 create_trace_edges (XVECEXP (seq, 0, i));
2333 return;
2334 }
2335
2336 /* Process EH edges. */
2337 if (CALL_P (insn) || cfun->can_throw_non_call_exceptions)
2338 {
2339 eh_landing_pad lp = get_eh_landing_pad_from_rtx (insn);
2340 if (lp)
2341 maybe_record_trace_start_abnormal (lp->landing_pad, insn);
2342 }
2343 }
2344
2345 /* A subroutine of scan_trace. Do what needs to be done "after" INSN. */
2346
2347 static void
2348 scan_insn_after (rtx insn)
2349 {
2350 if (RTX_FRAME_RELATED_P (insn))
2351 dwarf2out_frame_debug (insn);
2352 notice_args_size (insn);
2353 }
2354
2355 /* Scan the trace beginning at INSN and create the CFI notes for the
2356 instructions therein. */
2357
2358 static void
2359 scan_trace (dw_trace_info *trace)
2360 {
2361 rtx prev, insn = trace->head;
2362 dw_cfa_location this_cfa;
2363
2364 if (dump_file)
2365 fprintf (dump_file, "Processing trace %u : start at %s %d\n",
2366 trace->id, rtx_name[(int) GET_CODE (insn)],
2367 INSN_UID (insn));
2368
2369 trace->end_row = copy_cfi_row (trace->beg_row);
2370 trace->end_true_args_size = trace->beg_true_args_size;
2371
2372 cur_trace = trace;
2373 cur_row = trace->end_row;
2374
2375 this_cfa = cur_row->cfa;
2376 cur_cfa = &this_cfa;
2377
2378 for (prev = insn, insn = NEXT_INSN (insn);
2379 insn;
2380 prev = insn, insn = NEXT_INSN (insn))
2381 {
2382 rtx control;
2383
2384 /* Do everything that happens "before" the insn. */
2385 add_cfi_insn = prev;
2386
2387 /* Notice the end of a trace. */
2388 if (BARRIER_P (insn))
2389 {
2390 /* Don't bother saving the unneeded queued registers at all. */
2391 queued_reg_saves.truncate (0);
2392 break;
2393 }
2394 if (save_point_p (insn))
2395 {
2396 /* Propagate across fallthru edges. */
2397 dwarf2out_flush_queued_reg_saves ();
2398 maybe_record_trace_start (insn, NULL);
2399 break;
2400 }
2401
2402 if (DEBUG_INSN_P (insn) || !inside_basic_block_p (insn))
2403 continue;
2404
2405 /* Handle all changes to the row state. Sequences require special
2406 handling for the positioning of the notes. */
2407 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
2408 {
2409 rtx elt, pat = PATTERN (insn);
2410 int i, n = XVECLEN (pat, 0);
2411
2412 control = XVECEXP (pat, 0, 0);
2413 if (can_throw_internal (control))
2414 notice_eh_throw (control);
2415 dwarf2out_flush_queued_reg_saves ();
2416
2417 if (JUMP_P (control) && INSN_ANNULLED_BRANCH_P (control))
2418 {
2419 /* ??? Hopefully multiple delay slots are not annulled. */
2420 gcc_assert (n == 2);
2421 gcc_assert (!RTX_FRAME_RELATED_P (control));
2422 gcc_assert (!find_reg_note (control, REG_ARGS_SIZE, NULL));
2423
2424 elt = XVECEXP (pat, 0, 1);
2425
2426 if (INSN_FROM_TARGET_P (elt))
2427 {
2428 HOST_WIDE_INT restore_args_size;
2429 cfi_vec save_row_reg_save;
2430
2431 /* If ELT is an instruction from target of an annulled
2432 branch, the effects are for the target only and so
2433 the args_size and CFA along the current path
2434 shouldn't change. */
2435 add_cfi_insn = NULL;
2436 restore_args_size = cur_trace->end_true_args_size;
2437 cur_cfa = &cur_row->cfa;
2438 save_row_reg_save = vec_safe_copy (cur_row->reg_save);
2439
2440 scan_insn_after (elt);
2441
2442 /* ??? Should we instead save the entire row state? */
2443 gcc_assert (!queued_reg_saves.length ());
2444
2445 create_trace_edges (control);
2446
2447 cur_trace->end_true_args_size = restore_args_size;
2448 cur_row->cfa = this_cfa;
2449 cur_row->reg_save = save_row_reg_save;
2450 cur_cfa = &this_cfa;
2451 }
2452 else
2453 {
2454 /* If ELT is a annulled branch-taken instruction (i.e.
2455 executed only when branch is not taken), the args_size
2456 and CFA should not change through the jump. */
2457 create_trace_edges (control);
2458
2459 /* Update and continue with the trace. */
2460 add_cfi_insn = insn;
2461 scan_insn_after (elt);
2462 def_cfa_1 (&this_cfa);
2463 }
2464 continue;
2465 }
2466
2467 /* The insns in the delay slot should all be considered to happen
2468 "before" a call insn. Consider a call with a stack pointer
2469 adjustment in the delay slot. The backtrace from the callee
2470 should include the sp adjustment. Unfortunately, that leaves
2471 us with an unavoidable unwinding error exactly at the call insn
2472 itself. For jump insns we'd prefer to avoid this error by
2473 placing the notes after the sequence. */
2474 if (JUMP_P (control))
2475 add_cfi_insn = insn;
2476
2477 for (i = 1; i < n; ++i)
2478 {
2479 elt = XVECEXP (pat, 0, i);
2480 scan_insn_after (elt);
2481 }
2482
2483 /* Make sure any register saves are visible at the jump target. */
2484 dwarf2out_flush_queued_reg_saves ();
2485 any_cfis_emitted = false;
2486
2487 /* However, if there is some adjustment on the call itself, e.g.
2488 a call_pop, that action should be considered to happen after
2489 the call returns. */
2490 add_cfi_insn = insn;
2491 scan_insn_after (control);
2492 }
2493 else
2494 {
2495 /* Flush data before calls and jumps, and of course if necessary. */
2496 if (can_throw_internal (insn))
2497 {
2498 notice_eh_throw (insn);
2499 dwarf2out_flush_queued_reg_saves ();
2500 }
2501 else if (!NONJUMP_INSN_P (insn)
2502 || clobbers_queued_reg_save (insn)
2503 || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL))
2504 dwarf2out_flush_queued_reg_saves ();
2505 any_cfis_emitted = false;
2506
2507 add_cfi_insn = insn;
2508 scan_insn_after (insn);
2509 control = insn;
2510 }
2511
2512 /* Between frame-related-p and args_size we might have otherwise
2513 emitted two cfa adjustments. Do it now. */
2514 def_cfa_1 (&this_cfa);
2515
2516 /* Minimize the number of advances by emitting the entire queue
2517 once anything is emitted. */
2518 if (any_cfis_emitted
2519 || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL))
2520 dwarf2out_flush_queued_reg_saves ();
2521
2522 /* Note that a test for control_flow_insn_p does exactly the
2523 same tests as are done to actually create the edges. So
2524 always call the routine and let it not create edges for
2525 non-control-flow insns. */
2526 create_trace_edges (control);
2527 }
2528
2529 add_cfi_insn = NULL;
2530 cur_row = NULL;
2531 cur_trace = NULL;
2532 cur_cfa = NULL;
2533 }
2534
2535 /* Scan the function and create the initial set of CFI notes. */
2536
2537 static void
2538 create_cfi_notes (void)
2539 {
2540 dw_trace_info *ti;
2541
2542 gcc_checking_assert (!queued_reg_saves.exists ());
2543 gcc_checking_assert (!trace_work_list.exists ());
2544
2545 /* Always begin at the entry trace. */
2546 ti = &trace_info[0];
2547 scan_trace (ti);
2548
2549 while (!trace_work_list.is_empty ())
2550 {
2551 ti = trace_work_list.pop ();
2552 scan_trace (ti);
2553 }
2554
2555 queued_reg_saves.release ();
2556 trace_work_list.release ();
2557 }
2558
2559 /* Return the insn before the first NOTE_INSN_CFI after START. */
2560
2561 static rtx
2562 before_next_cfi_note (rtx start)
2563 {
2564 rtx prev = start;
2565 while (start)
2566 {
2567 if (NOTE_P (start) && NOTE_KIND (start) == NOTE_INSN_CFI)
2568 return prev;
2569 prev = start;
2570 start = NEXT_INSN (start);
2571 }
2572 gcc_unreachable ();
2573 }
2574
2575 /* Insert CFI notes between traces to properly change state between them. */
2576
2577 static void
2578 connect_traces (void)
2579 {
2580 unsigned i, n = trace_info.length ();
2581 dw_trace_info *prev_ti, *ti;
2582
2583 /* ??? Ideally, we should have both queued and processed every trace.
2584 However the current representation of constant pools on various targets
2585 is indistinguishable from unreachable code. Assume for the moment that
2586 we can simply skip over such traces. */
2587 /* ??? Consider creating a DATA_INSN rtx code to indicate that
2588 these are not "real" instructions, and should not be considered.
2589 This could be generically useful for tablejump data as well. */
2590 /* Remove all unprocessed traces from the list. */
2591 for (i = n - 1; i > 0; --i)
2592 {
2593 ti = &trace_info[i];
2594 if (ti->beg_row == NULL)
2595 {
2596 trace_info.ordered_remove (i);
2597 n -= 1;
2598 }
2599 else
2600 gcc_assert (ti->end_row != NULL);
2601 }
2602
2603 /* Work from the end back to the beginning. This lets us easily insert
2604 remember/restore_state notes in the correct order wrt other notes. */
2605 prev_ti = &trace_info[n - 1];
2606 for (i = n - 1; i > 0; --i)
2607 {
2608 dw_cfi_row *old_row;
2609
2610 ti = prev_ti;
2611 prev_ti = &trace_info[i - 1];
2612
2613 add_cfi_insn = ti->head;
2614
2615 /* In dwarf2out_switch_text_section, we'll begin a new FDE
2616 for the portion of the function in the alternate text
2617 section. The row state at the very beginning of that
2618 new FDE will be exactly the row state from the CIE. */
2619 if (ti->switch_sections)
2620 old_row = cie_cfi_row;
2621 else
2622 {
2623 old_row = prev_ti->end_row;
2624 /* If there's no change from the previous end state, fine. */
2625 if (cfi_row_equal_p (old_row, ti->beg_row))
2626 ;
2627 /* Otherwise check for the common case of sharing state with
2628 the beginning of an epilogue, but not the end. Insert
2629 remember/restore opcodes in that case. */
2630 else if (cfi_row_equal_p (prev_ti->beg_row, ti->beg_row))
2631 {
2632 dw_cfi_ref cfi;
2633
2634 /* Note that if we blindly insert the remember at the
2635 start of the trace, we can wind up increasing the
2636 size of the unwind info due to extra advance opcodes.
2637 Instead, put the remember immediately before the next
2638 state change. We know there must be one, because the
2639 state at the beginning and head of the trace differ. */
2640 add_cfi_insn = before_next_cfi_note (prev_ti->head);
2641 cfi = new_cfi ();
2642 cfi->dw_cfi_opc = DW_CFA_remember_state;
2643 add_cfi (cfi);
2644
2645 add_cfi_insn = ti->head;
2646 cfi = new_cfi ();
2647 cfi->dw_cfi_opc = DW_CFA_restore_state;
2648 add_cfi (cfi);
2649
2650 old_row = prev_ti->beg_row;
2651 }
2652 /* Otherwise, we'll simply change state from the previous end. */
2653 }
2654
2655 change_cfi_row (old_row, ti->beg_row);
2656
2657 if (dump_file && add_cfi_insn != ti->head)
2658 {
2659 rtx note;
2660
2661 fprintf (dump_file, "Fixup between trace %u and %u:\n",
2662 prev_ti->id, ti->id);
2663
2664 note = ti->head;
2665 do
2666 {
2667 note = NEXT_INSN (note);
2668 gcc_assert (NOTE_P (note) && NOTE_KIND (note) == NOTE_INSN_CFI);
2669 output_cfi_directive (dump_file, NOTE_CFI (note));
2670 }
2671 while (note != add_cfi_insn);
2672 }
2673 }
2674
2675 /* Connect args_size between traces that have can_throw_internal insns. */
2676 if (cfun->eh->lp_array)
2677 {
2678 HOST_WIDE_INT prev_args_size = 0;
2679
2680 for (i = 0; i < n; ++i)
2681 {
2682 ti = &trace_info[i];
2683
2684 if (ti->switch_sections)
2685 prev_args_size = 0;
2686 if (ti->eh_head == NULL)
2687 continue;
2688 gcc_assert (!ti->args_size_undefined);
2689
2690 if (ti->beg_delay_args_size != prev_args_size)
2691 {
2692 /* ??? Search back to previous CFI note. */
2693 add_cfi_insn = PREV_INSN (ti->eh_head);
2694 add_cfi_args_size (ti->beg_delay_args_size);
2695 }
2696
2697 prev_args_size = ti->end_delay_args_size;
2698 }
2699 }
2700 }
2701
2702 /* Set up the pseudo-cfg of instruction traces, as described at the
2703 block comment at the top of the file. */
2704
2705 static void
2706 create_pseudo_cfg (void)
2707 {
2708 bool saw_barrier, switch_sections;
2709 dw_trace_info ti;
2710 rtx insn;
2711 unsigned i;
2712
2713 /* The first trace begins at the start of the function,
2714 and begins with the CIE row state. */
2715 trace_info.create (16);
2716 memset (&ti, 0, sizeof (ti));
2717 ti.head = get_insns ();
2718 ti.beg_row = cie_cfi_row;
2719 ti.cfa_store = cie_cfi_row->cfa;
2720 ti.cfa_temp.reg = INVALID_REGNUM;
2721 trace_info.quick_push (ti);
2722
2723 if (cie_return_save)
2724 ti.regs_saved_in_regs.safe_push (*cie_return_save);
2725
2726 /* Walk all the insns, collecting start of trace locations. */
2727 saw_barrier = false;
2728 switch_sections = false;
2729 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2730 {
2731 if (BARRIER_P (insn))
2732 saw_barrier = true;
2733 else if (NOTE_P (insn)
2734 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
2735 {
2736 /* We should have just seen a barrier. */
2737 gcc_assert (saw_barrier);
2738 switch_sections = true;
2739 }
2740 /* Watch out for save_point notes between basic blocks.
2741 In particular, a note after a barrier. Do not record these,
2742 delaying trace creation until the label. */
2743 else if (save_point_p (insn)
2744 && (LABEL_P (insn) || !saw_barrier))
2745 {
2746 memset (&ti, 0, sizeof (ti));
2747 ti.head = insn;
2748 ti.switch_sections = switch_sections;
2749 ti.id = trace_info.length () - 1;
2750 trace_info.safe_push (ti);
2751
2752 saw_barrier = false;
2753 switch_sections = false;
2754 }
2755 }
2756
2757 /* Create the trace index after we've finished building trace_info,
2758 avoiding stale pointer problems due to reallocation. */
2759 trace_index.create (trace_info.length ());
2760 dw_trace_info *tp;
2761 FOR_EACH_VEC_ELT (trace_info, i, tp)
2762 {
2763 dw_trace_info **slot;
2764
2765 if (dump_file)
2766 fprintf (dump_file, "Creating trace %u : start at %s %d%s\n", i,
2767 rtx_name[(int) GET_CODE (tp->head)], INSN_UID (tp->head),
2768 tp->switch_sections ? " (section switch)" : "");
2769
2770 slot = trace_index.find_slot_with_hash (tp, INSN_UID (tp->head), INSERT);
2771 gcc_assert (*slot == NULL);
2772 *slot = tp;
2773 }
2774 }
2775
2776 /* Record the initial position of the return address. RTL is
2777 INCOMING_RETURN_ADDR_RTX. */
2778
2779 static void
2780 initial_return_save (rtx rtl)
2781 {
2782 unsigned int reg = INVALID_REGNUM;
2783 HOST_WIDE_INT offset = 0;
2784
2785 switch (GET_CODE (rtl))
2786 {
2787 case REG:
2788 /* RA is in a register. */
2789 reg = dwf_regno (rtl);
2790 break;
2791
2792 case MEM:
2793 /* RA is on the stack. */
2794 rtl = XEXP (rtl, 0);
2795 switch (GET_CODE (rtl))
2796 {
2797 case REG:
2798 gcc_assert (REGNO (rtl) == STACK_POINTER_REGNUM);
2799 offset = 0;
2800 break;
2801
2802 case PLUS:
2803 gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM);
2804 offset = INTVAL (XEXP (rtl, 1));
2805 break;
2806
2807 case MINUS:
2808 gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM);
2809 offset = -INTVAL (XEXP (rtl, 1));
2810 break;
2811
2812 default:
2813 gcc_unreachable ();
2814 }
2815
2816 break;
2817
2818 case PLUS:
2819 /* The return address is at some offset from any value we can
2820 actually load. For instance, on the SPARC it is in %i7+8. Just
2821 ignore the offset for now; it doesn't matter for unwinding frames. */
2822 gcc_assert (CONST_INT_P (XEXP (rtl, 1)));
2823 initial_return_save (XEXP (rtl, 0));
2824 return;
2825
2826 default:
2827 gcc_unreachable ();
2828 }
2829
2830 if (reg != DWARF_FRAME_RETURN_COLUMN)
2831 {
2832 if (reg != INVALID_REGNUM)
2833 record_reg_saved_in_reg (rtl, pc_rtx);
2834 reg_save (DWARF_FRAME_RETURN_COLUMN, reg, offset - cur_row->cfa.offset);
2835 }
2836 }
2837
2838 static void
2839 create_cie_data (void)
2840 {
2841 dw_cfa_location loc;
2842 dw_trace_info cie_trace;
2843
2844 dw_stack_pointer_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM);
2845 dw_frame_pointer_regnum = DWARF_FRAME_REGNUM (HARD_FRAME_POINTER_REGNUM);
2846
2847 memset (&cie_trace, 0, sizeof (cie_trace));
2848 cur_trace = &cie_trace;
2849
2850 add_cfi_vec = &cie_cfi_vec;
2851 cie_cfi_row = cur_row = new_cfi_row ();
2852
2853 /* On entry, the Canonical Frame Address is at SP. */
2854 memset (&loc, 0, sizeof (loc));
2855 loc.reg = dw_stack_pointer_regnum;
2856 loc.offset = INCOMING_FRAME_SP_OFFSET;
2857 def_cfa_1 (&loc);
2858
2859 if (targetm.debug_unwind_info () == UI_DWARF2
2860 || targetm_common.except_unwind_info (&global_options) == UI_DWARF2)
2861 {
2862 initial_return_save (INCOMING_RETURN_ADDR_RTX);
2863
2864 /* For a few targets, we have the return address incoming into a
2865 register, but choose a different return column. This will result
2866 in a DW_CFA_register for the return, and an entry in
2867 regs_saved_in_regs to match. If the target later stores that
2868 return address register to the stack, we want to be able to emit
2869 the DW_CFA_offset against the return column, not the intermediate
2870 save register. Save the contents of regs_saved_in_regs so that
2871 we can re-initialize it at the start of each function. */
2872 switch (cie_trace.regs_saved_in_regs.length ())
2873 {
2874 case 0:
2875 break;
2876 case 1:
2877 cie_return_save = ggc_alloc_reg_saved_in_data ();
2878 *cie_return_save = cie_trace.regs_saved_in_regs[0];
2879 cie_trace.regs_saved_in_regs.release ();
2880 break;
2881 default:
2882 gcc_unreachable ();
2883 }
2884 }
2885
2886 add_cfi_vec = NULL;
2887 cur_row = NULL;
2888 cur_trace = NULL;
2889 }
2890
2891 /* Annotate the function with NOTE_INSN_CFI notes to record the CFI
2892 state at each location within the function. These notes will be
2893 emitted during pass_final. */
2894
2895 static unsigned int
2896 execute_dwarf2_frame (void)
2897 {
2898 /* The first time we're called, compute the incoming frame state. */
2899 if (cie_cfi_vec == NULL)
2900 create_cie_data ();
2901
2902 dwarf2out_alloc_current_fde ();
2903
2904 create_pseudo_cfg ();
2905
2906 /* Do the work. */
2907 create_cfi_notes ();
2908 connect_traces ();
2909 add_cfis_to_fde ();
2910
2911 /* Free all the data we allocated. */
2912 {
2913 size_t i;
2914 dw_trace_info *ti;
2915
2916 FOR_EACH_VEC_ELT (trace_info, i, ti)
2917 ti->regs_saved_in_regs.release ();
2918 }
2919 trace_info.release ();
2920
2921 trace_index.dispose ();
2922
2923 return 0;
2924 }
2925 \f
2926 /* Convert a DWARF call frame info. operation to its string name */
2927
2928 static const char *
2929 dwarf_cfi_name (unsigned int cfi_opc)
2930 {
2931 const char *name = get_DW_CFA_name (cfi_opc);
2932
2933 if (name != NULL)
2934 return name;
2935
2936 return "DW_CFA_<unknown>";
2937 }
2938
2939 /* This routine will generate the correct assembly data for a location
2940 description based on a cfi entry with a complex address. */
2941
2942 static void
2943 output_cfa_loc (dw_cfi_ref cfi, int for_eh)
2944 {
2945 dw_loc_descr_ref loc;
2946 unsigned long size;
2947
2948 if (cfi->dw_cfi_opc == DW_CFA_expression)
2949 {
2950 unsigned r =
2951 DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
2952 dw2_asm_output_data (1, r, NULL);
2953 loc = cfi->dw_cfi_oprnd2.dw_cfi_loc;
2954 }
2955 else
2956 loc = cfi->dw_cfi_oprnd1.dw_cfi_loc;
2957
2958 /* Output the size of the block. */
2959 size = size_of_locs (loc);
2960 dw2_asm_output_data_uleb128 (size, NULL);
2961
2962 /* Now output the operations themselves. */
2963 output_loc_sequence (loc, for_eh);
2964 }
2965
2966 /* Similar, but used for .cfi_escape. */
2967
2968 static void
2969 output_cfa_loc_raw (dw_cfi_ref cfi)
2970 {
2971 dw_loc_descr_ref loc;
2972 unsigned long size;
2973
2974 if (cfi->dw_cfi_opc == DW_CFA_expression)
2975 {
2976 unsigned r =
2977 DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
2978 fprintf (asm_out_file, "%#x,", r);
2979 loc = cfi->dw_cfi_oprnd2.dw_cfi_loc;
2980 }
2981 else
2982 loc = cfi->dw_cfi_oprnd1.dw_cfi_loc;
2983
2984 /* Output the size of the block. */
2985 size = size_of_locs (loc);
2986 dw2_asm_output_data_uleb128_raw (size);
2987 fputc (',', asm_out_file);
2988
2989 /* Now output the operations themselves. */
2990 output_loc_sequence_raw (loc);
2991 }
2992
2993 /* Output a Call Frame Information opcode and its operand(s). */
2994
2995 void
2996 output_cfi (dw_cfi_ref cfi, dw_fde_ref fde, int for_eh)
2997 {
2998 unsigned long r;
2999 HOST_WIDE_INT off;
3000
3001 if (cfi->dw_cfi_opc == DW_CFA_advance_loc)
3002 dw2_asm_output_data (1, (cfi->dw_cfi_opc
3003 | (cfi->dw_cfi_oprnd1.dw_cfi_offset & 0x3f)),
3004 "DW_CFA_advance_loc " HOST_WIDE_INT_PRINT_HEX,
3005 ((unsigned HOST_WIDE_INT)
3006 cfi->dw_cfi_oprnd1.dw_cfi_offset));
3007 else if (cfi->dw_cfi_opc == DW_CFA_offset)
3008 {
3009 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3010 dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)),
3011 "DW_CFA_offset, column %#lx", r);
3012 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3013 dw2_asm_output_data_uleb128 (off, NULL);
3014 }
3015 else if (cfi->dw_cfi_opc == DW_CFA_restore)
3016 {
3017 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3018 dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)),
3019 "DW_CFA_restore, column %#lx", r);
3020 }
3021 else
3022 {
3023 dw2_asm_output_data (1, cfi->dw_cfi_opc,
3024 "%s", dwarf_cfi_name (cfi->dw_cfi_opc));
3025
3026 switch (cfi->dw_cfi_opc)
3027 {
3028 case DW_CFA_set_loc:
3029 if (for_eh)
3030 dw2_asm_output_encoded_addr_rtx (
3031 ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/1, /*global=*/0),
3032 gen_rtx_SYMBOL_REF (Pmode, cfi->dw_cfi_oprnd1.dw_cfi_addr),
3033 false, NULL);
3034 else
3035 dw2_asm_output_addr (DWARF2_ADDR_SIZE,
3036 cfi->dw_cfi_oprnd1.dw_cfi_addr, NULL);
3037 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3038 break;
3039
3040 case DW_CFA_advance_loc1:
3041 dw2_asm_output_delta (1, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3042 fde->dw_fde_current_label, NULL);
3043 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3044 break;
3045
3046 case DW_CFA_advance_loc2:
3047 dw2_asm_output_delta (2, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3048 fde->dw_fde_current_label, NULL);
3049 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3050 break;
3051
3052 case DW_CFA_advance_loc4:
3053 dw2_asm_output_delta (4, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3054 fde->dw_fde_current_label, NULL);
3055 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3056 break;
3057
3058 case DW_CFA_MIPS_advance_loc8:
3059 dw2_asm_output_delta (8, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3060 fde->dw_fde_current_label, NULL);
3061 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3062 break;
3063
3064 case DW_CFA_offset_extended:
3065 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3066 dw2_asm_output_data_uleb128 (r, NULL);
3067 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3068 dw2_asm_output_data_uleb128 (off, NULL);
3069 break;
3070
3071 case DW_CFA_def_cfa:
3072 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3073 dw2_asm_output_data_uleb128 (r, NULL);
3074 dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd2.dw_cfi_offset, NULL);
3075 break;
3076
3077 case DW_CFA_offset_extended_sf:
3078 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3079 dw2_asm_output_data_uleb128 (r, NULL);
3080 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3081 dw2_asm_output_data_sleb128 (off, NULL);
3082 break;
3083
3084 case DW_CFA_def_cfa_sf:
3085 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3086 dw2_asm_output_data_uleb128 (r, NULL);
3087 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3088 dw2_asm_output_data_sleb128 (off, NULL);
3089 break;
3090
3091 case DW_CFA_restore_extended:
3092 case DW_CFA_undefined:
3093 case DW_CFA_same_value:
3094 case DW_CFA_def_cfa_register:
3095 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3096 dw2_asm_output_data_uleb128 (r, NULL);
3097 break;
3098
3099 case DW_CFA_register:
3100 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3101 dw2_asm_output_data_uleb128 (r, NULL);
3102 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, for_eh);
3103 dw2_asm_output_data_uleb128 (r, NULL);
3104 break;
3105
3106 case DW_CFA_def_cfa_offset:
3107 case DW_CFA_GNU_args_size:
3108 dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd1.dw_cfi_offset, NULL);
3109 break;
3110
3111 case DW_CFA_def_cfa_offset_sf:
3112 off = div_data_align (cfi->dw_cfi_oprnd1.dw_cfi_offset);
3113 dw2_asm_output_data_sleb128 (off, NULL);
3114 break;
3115
3116 case DW_CFA_GNU_window_save:
3117 break;
3118
3119 case DW_CFA_def_cfa_expression:
3120 case DW_CFA_expression:
3121 output_cfa_loc (cfi, for_eh);
3122 break;
3123
3124 case DW_CFA_GNU_negative_offset_extended:
3125 /* Obsoleted by DW_CFA_offset_extended_sf. */
3126 gcc_unreachable ();
3127
3128 default:
3129 break;
3130 }
3131 }
3132 }
3133
3134 /* Similar, but do it via assembler directives instead. */
3135
3136 void
3137 output_cfi_directive (FILE *f, dw_cfi_ref cfi)
3138 {
3139 unsigned long r, r2;
3140
3141 switch (cfi->dw_cfi_opc)
3142 {
3143 case DW_CFA_advance_loc:
3144 case DW_CFA_advance_loc1:
3145 case DW_CFA_advance_loc2:
3146 case DW_CFA_advance_loc4:
3147 case DW_CFA_MIPS_advance_loc8:
3148 case DW_CFA_set_loc:
3149 /* Should only be created in a code path not followed when emitting
3150 via directives. The assembler is going to take care of this for
3151 us. But this routines is also used for debugging dumps, so
3152 print something. */
3153 gcc_assert (f != asm_out_file);
3154 fprintf (f, "\t.cfi_advance_loc\n");
3155 break;
3156
3157 case DW_CFA_offset:
3158 case DW_CFA_offset_extended:
3159 case DW_CFA_offset_extended_sf:
3160 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3161 fprintf (f, "\t.cfi_offset %lu, "HOST_WIDE_INT_PRINT_DEC"\n",
3162 r, cfi->dw_cfi_oprnd2.dw_cfi_offset);
3163 break;
3164
3165 case DW_CFA_restore:
3166 case DW_CFA_restore_extended:
3167 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3168 fprintf (f, "\t.cfi_restore %lu\n", r);
3169 break;
3170
3171 case DW_CFA_undefined:
3172 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3173 fprintf (f, "\t.cfi_undefined %lu\n", r);
3174 break;
3175
3176 case DW_CFA_same_value:
3177 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3178 fprintf (f, "\t.cfi_same_value %lu\n", r);
3179 break;
3180
3181 case DW_CFA_def_cfa:
3182 case DW_CFA_def_cfa_sf:
3183 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3184 fprintf (f, "\t.cfi_def_cfa %lu, "HOST_WIDE_INT_PRINT_DEC"\n",
3185 r, cfi->dw_cfi_oprnd2.dw_cfi_offset);
3186 break;
3187
3188 case DW_CFA_def_cfa_register:
3189 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3190 fprintf (f, "\t.cfi_def_cfa_register %lu\n", r);
3191 break;
3192
3193 case DW_CFA_register:
3194 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3195 r2 = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, 1);
3196 fprintf (f, "\t.cfi_register %lu, %lu\n", r, r2);
3197 break;
3198
3199 case DW_CFA_def_cfa_offset:
3200 case DW_CFA_def_cfa_offset_sf:
3201 fprintf (f, "\t.cfi_def_cfa_offset "
3202 HOST_WIDE_INT_PRINT_DEC"\n",
3203 cfi->dw_cfi_oprnd1.dw_cfi_offset);
3204 break;
3205
3206 case DW_CFA_remember_state:
3207 fprintf (f, "\t.cfi_remember_state\n");
3208 break;
3209 case DW_CFA_restore_state:
3210 fprintf (f, "\t.cfi_restore_state\n");
3211 break;
3212
3213 case DW_CFA_GNU_args_size:
3214 if (f == asm_out_file)
3215 {
3216 fprintf (f, "\t.cfi_escape %#x,", DW_CFA_GNU_args_size);
3217 dw2_asm_output_data_uleb128_raw (cfi->dw_cfi_oprnd1.dw_cfi_offset);
3218 if (flag_debug_asm)
3219 fprintf (f, "\t%s args_size "HOST_WIDE_INT_PRINT_DEC,
3220 ASM_COMMENT_START, cfi->dw_cfi_oprnd1.dw_cfi_offset);
3221 fputc ('\n', f);
3222 }
3223 else
3224 {
3225 fprintf (f, "\t.cfi_GNU_args_size "HOST_WIDE_INT_PRINT_DEC "\n",
3226 cfi->dw_cfi_oprnd1.dw_cfi_offset);
3227 }
3228 break;
3229
3230 case DW_CFA_GNU_window_save:
3231 fprintf (f, "\t.cfi_window_save\n");
3232 break;
3233
3234 case DW_CFA_def_cfa_expression:
3235 if (f != asm_out_file)
3236 {
3237 fprintf (f, "\t.cfi_def_cfa_expression ...\n");
3238 break;
3239 }
3240 /* FALLTHRU */
3241 case DW_CFA_expression:
3242 if (f != asm_out_file)
3243 {
3244 fprintf (f, "\t.cfi_cfa_expression ...\n");
3245 break;
3246 }
3247 fprintf (f, "\t.cfi_escape %#x,", cfi->dw_cfi_opc);
3248 output_cfa_loc_raw (cfi);
3249 fputc ('\n', f);
3250 break;
3251
3252 default:
3253 gcc_unreachable ();
3254 }
3255 }
3256
3257 void
3258 dwarf2out_emit_cfi (dw_cfi_ref cfi)
3259 {
3260 if (dwarf2out_do_cfi_asm ())
3261 output_cfi_directive (asm_out_file, cfi);
3262 }
3263
3264 static void
3265 dump_cfi_row (FILE *f, dw_cfi_row *row)
3266 {
3267 dw_cfi_ref cfi;
3268 unsigned i;
3269
3270 cfi = row->cfa_cfi;
3271 if (!cfi)
3272 {
3273 dw_cfa_location dummy;
3274 memset (&dummy, 0, sizeof (dummy));
3275 dummy.reg = INVALID_REGNUM;
3276 cfi = def_cfa_0 (&dummy, &row->cfa);
3277 }
3278 output_cfi_directive (f, cfi);
3279
3280 FOR_EACH_VEC_SAFE_ELT (row->reg_save, i, cfi)
3281 if (cfi)
3282 output_cfi_directive (f, cfi);
3283 }
3284
3285 void debug_cfi_row (dw_cfi_row *row);
3286
3287 void
3288 debug_cfi_row (dw_cfi_row *row)
3289 {
3290 dump_cfi_row (stderr, row);
3291 }
3292 \f
3293
3294 /* Save the result of dwarf2out_do_frame across PCH.
3295 This variable is tri-state, with 0 unset, >0 true, <0 false. */
3296 static GTY(()) signed char saved_do_cfi_asm = 0;
3297
3298 /* Decide whether we want to emit frame unwind information for the current
3299 translation unit. */
3300
3301 bool
3302 dwarf2out_do_frame (void)
3303 {
3304 /* We want to emit correct CFA location expressions or lists, so we
3305 have to return true if we're going to output debug info, even if
3306 we're not going to output frame or unwind info. */
3307 if (write_symbols == DWARF2_DEBUG || write_symbols == VMS_AND_DWARF2_DEBUG)
3308 return true;
3309
3310 if (saved_do_cfi_asm > 0)
3311 return true;
3312
3313 if (targetm.debug_unwind_info () == UI_DWARF2)
3314 return true;
3315
3316 if ((flag_unwind_tables || flag_exceptions)
3317 && targetm_common.except_unwind_info (&global_options) == UI_DWARF2)
3318 return true;
3319
3320 return false;
3321 }
3322
3323 /* Decide whether to emit frame unwind via assembler directives. */
3324
3325 bool
3326 dwarf2out_do_cfi_asm (void)
3327 {
3328 int enc;
3329
3330 if (saved_do_cfi_asm != 0)
3331 return saved_do_cfi_asm > 0;
3332
3333 /* Assume failure for a moment. */
3334 saved_do_cfi_asm = -1;
3335
3336 if (!flag_dwarf2_cfi_asm || !dwarf2out_do_frame ())
3337 return false;
3338 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
3339 return false;
3340
3341 /* Make sure the personality encoding is one the assembler can support.
3342 In particular, aligned addresses can't be handled. */
3343 enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/2,/*global=*/1);
3344 if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel)
3345 return false;
3346 enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0,/*global=*/0);
3347 if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel)
3348 return false;
3349
3350 /* If we can't get the assembler to emit only .debug_frame, and we don't need
3351 dwarf2 unwind info for exceptions, then emit .debug_frame by hand. */
3352 if (!HAVE_GAS_CFI_SECTIONS_DIRECTIVE
3353 && !flag_unwind_tables && !flag_exceptions
3354 && targetm_common.except_unwind_info (&global_options) != UI_DWARF2)
3355 return false;
3356
3357 /* Success! */
3358 saved_do_cfi_asm = 1;
3359 return true;
3360 }
3361
3362 static bool
3363 gate_dwarf2_frame (void)
3364 {
3365 #ifndef HAVE_prologue
3366 /* Targets which still implement the prologue in assembler text
3367 cannot use the generic dwarf2 unwinding. */
3368 return false;
3369 #endif
3370
3371 /* ??? What to do for UI_TARGET unwinding? They might be able to benefit
3372 from the optimized shrink-wrapping annotations that we will compute.
3373 For now, only produce the CFI notes for dwarf2. */
3374 return dwarf2out_do_frame ();
3375 }
3376
3377 namespace {
3378
3379 const pass_data pass_data_dwarf2_frame =
3380 {
3381 RTL_PASS, /* type */
3382 "dwarf2", /* name */
3383 OPTGROUP_NONE, /* optinfo_flags */
3384 true, /* has_gate */
3385 true, /* has_execute */
3386 TV_FINAL, /* tv_id */
3387 0, /* properties_required */
3388 0, /* properties_provided */
3389 0, /* properties_destroyed */
3390 0, /* todo_flags_start */
3391 0, /* todo_flags_finish */
3392 };
3393
3394 class pass_dwarf2_frame : public rtl_opt_pass
3395 {
3396 public:
3397 pass_dwarf2_frame (gcc::context *ctxt)
3398 : rtl_opt_pass (pass_data_dwarf2_frame, ctxt)
3399 {}
3400
3401 /* opt_pass methods: */
3402 bool gate () { return gate_dwarf2_frame (); }
3403 unsigned int execute () { return execute_dwarf2_frame (); }
3404
3405 }; // class pass_dwarf2_frame
3406
3407 } // anon namespace
3408
3409 rtl_opt_pass *
3410 make_pass_dwarf2_frame (gcc::context *ctxt)
3411 {
3412 return new pass_dwarf2_frame (ctxt);
3413 }
3414
3415 #include "gt-dwarf2cfi.h"