h8300: Generate correct unwind info around swap_into/out_of_er6.
[gcc.git] / gcc / dwarf2cfi.c
1 /* Dwarf2 Call Frame Information helper routines.
2 Copyright (C) 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "version.h"
27 #include "flags.h"
28 #include "rtl.h"
29 #include "function.h"
30 #include "basic-block.h"
31 #include "dwarf2.h"
32 #include "dwarf2out.h"
33 #include "dwarf2asm.h"
34 #include "ggc.h"
35 #include "tm_p.h"
36 #include "target.h"
37 #include "common/common-target.h"
38 #include "tree-pass.h"
39
40 #include "except.h" /* expand_builtin_dwarf_sp_column */
41 #include "expr.h" /* init_return_column_size */
42 #include "regs.h" /* expand_builtin_init_dwarf_reg_sizes */
43 #include "output.h" /* asm_out_file */
44 #include "debug.h" /* dwarf2out_do_frame, dwarf2out_do_cfi_asm */
45
46
47 /* ??? Poison these here until it can be done generically. They've been
48 totally replaced in this file; make sure it stays that way. */
49 #undef DWARF2_UNWIND_INFO
50 #undef DWARF2_FRAME_INFO
51 #if (GCC_VERSION >= 3000)
52 #pragma GCC poison DWARF2_UNWIND_INFO DWARF2_FRAME_INFO
53 #endif
54
55 #ifndef INCOMING_RETURN_ADDR_RTX
56 #define INCOMING_RETURN_ADDR_RTX (gcc_unreachable (), NULL_RTX)
57 #endif
58
59 /* Maximum size (in bytes) of an artificially generated label. */
60 #define MAX_ARTIFICIAL_LABEL_BYTES 30
61 \f
62 /* A collected description of an entire row of the abstract CFI table. */
63 typedef struct GTY(()) dw_cfi_row_struct
64 {
65 /* The expression that computes the CFA, expressed in two different ways.
66 The CFA member for the simple cases, and the full CFI expression for
67 the complex cases. The later will be a DW_CFA_cfa_expression. */
68 dw_cfa_location cfa;
69 dw_cfi_ref cfa_cfi;
70
71 /* The expressions for any register column that is saved. */
72 cfi_vec reg_save;
73
74 /* The value of any DW_CFA_GNU_args_size. */
75 HOST_WIDE_INT args_size;
76 } dw_cfi_row;
77
78 /* The caller's ORIG_REG is saved in SAVED_IN_REG. */
79 typedef struct GTY(()) reg_saved_in_data_struct {
80 rtx orig_reg;
81 rtx saved_in_reg;
82 } reg_saved_in_data;
83
84 DEF_VEC_O (reg_saved_in_data);
85 DEF_VEC_ALLOC_O (reg_saved_in_data, heap);
86
87 /* Since we no longer have a proper CFG, we're going to create a facsimile
88 of one on the fly while processing the frame-related insns.
89
90 We create dw_trace_info structures for each extended basic block beginning
91 and ending at a "save point". Save points are labels, barriers, certain
92 notes, and of course the beginning and end of the function.
93
94 As we encounter control transfer insns, we propagate the "current"
95 row state across the edges to the starts of traces. When checking is
96 enabled, we validate that we propagate the same data from all sources.
97
98 All traces are members of the TRACE_INFO array, in the order in which
99 they appear in the instruction stream.
100
101 All save points are present in the TRACE_INDEX hash, mapping the insn
102 starting a trace to the dw_trace_info describing the trace. */
103
104 typedef struct
105 {
106 /* The insn that begins the trace. */
107 rtx head;
108
109 /* The row state at the beginning and end of the trace. */
110 dw_cfi_row *beg_row, *end_row;
111
112 /* The following variables contain data used in interpreting frame related
113 expressions. These are not part of the "real" row state as defined by
114 Dwarf, but it seems like they need to be propagated into a trace in case
115 frame related expressions have been sunk. */
116 /* ??? This seems fragile. These variables are fragments of a larger
117 expression. If we do not keep the entire expression together, we risk
118 not being able to put it together properly. Consider forcing targets
119 to generate self-contained expressions and dropping all of the magic
120 interpretation code in this file. Or at least refusing to shrink wrap
121 any frame related insn that doesn't contain a complete expression. */
122
123 /* The register used for saving registers to the stack, and its offset
124 from the CFA. */
125 dw_cfa_location cfa_store;
126
127 /* A temporary register holding an integral value used in adjusting SP
128 or setting up the store_reg. The "offset" field holds the integer
129 value, not an offset. */
130 dw_cfa_location cfa_temp;
131
132 /* A set of registers saved in other registers. This is the inverse of
133 the row->reg_save info, if the entry is a DW_CFA_register. This is
134 implemented as a flat array because it normally contains zero or 1
135 entry, depending on the target. IA-64 is the big spender here, using
136 a maximum of 5 entries. */
137 VEC(reg_saved_in_data, heap) *regs_saved_in_regs;
138
139 /* An identifier for this trace. Used only for debugging dumps. */
140 unsigned id;
141
142 /* True if this trace immediately follows NOTE_INSN_SWITCH_TEXT_SECTIONS. */
143 bool switch_sections;
144 } dw_trace_info;
145
146 DEF_VEC_O (dw_trace_info);
147 DEF_VEC_ALLOC_O (dw_trace_info, heap);
148
149 typedef dw_trace_info *dw_trace_info_ref;
150
151 DEF_VEC_P (dw_trace_info_ref);
152 DEF_VEC_ALLOC_P (dw_trace_info_ref, heap);
153
154 /* The variables making up the pseudo-cfg, as described above. */
155 static VEC (dw_trace_info, heap) *trace_info;
156 static VEC (dw_trace_info_ref, heap) *trace_work_list;
157 static htab_t trace_index;
158
159 /* A vector of call frame insns for the CIE. */
160 cfi_vec cie_cfi_vec;
161
162 /* The state of the first row of the FDE table, which includes the
163 state provided by the CIE. */
164 static GTY(()) dw_cfi_row *cie_cfi_row;
165
166 static GTY(()) reg_saved_in_data *cie_return_save;
167
168 static GTY(()) unsigned long dwarf2out_cfi_label_num;
169
170 /* The insn after which a new CFI note should be emitted. */
171 static rtx add_cfi_insn;
172
173 /* When non-null, add_cfi will add the CFI to this vector. */
174 static cfi_vec *add_cfi_vec;
175
176 /* The current instruction trace. */
177 static dw_trace_info *cur_trace;
178
179 /* The current, i.e. most recently generated, row of the CFI table. */
180 static dw_cfi_row *cur_row;
181
182 /* We delay emitting a register save until either (a) we reach the end
183 of the prologue or (b) the register is clobbered. This clusters
184 register saves so that there are fewer pc advances. */
185
186 typedef struct {
187 rtx reg;
188 rtx saved_reg;
189 HOST_WIDE_INT cfa_offset;
190 } queued_reg_save;
191
192 DEF_VEC_O (queued_reg_save);
193 DEF_VEC_ALLOC_O (queued_reg_save, heap);
194
195 static VEC(queued_reg_save, heap) *queued_reg_saves;
196
197 /* The (really) current value for DW_CFA_GNU_args_size. We delay actually
198 emitting this data, i.e. updating CUR_ROW, without async unwind. */
199 static HOST_WIDE_INT queued_args_size;
200
201 /* True if any CFI directives were emitted at the current insn. */
202 static bool any_cfis_emitted;
203
204 /* Short-hand for commonly used register numbers. */
205 static unsigned dw_stack_pointer_regnum;
206 static unsigned dw_frame_pointer_regnum;
207 \f
208 /* Hook used by __throw. */
209
210 rtx
211 expand_builtin_dwarf_sp_column (void)
212 {
213 unsigned int dwarf_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM);
214 return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum, 1));
215 }
216
217 /* MEM is a memory reference for the register size table, each element of
218 which has mode MODE. Initialize column C as a return address column. */
219
220 static void
221 init_return_column_size (enum machine_mode mode, rtx mem, unsigned int c)
222 {
223 HOST_WIDE_INT offset = c * GET_MODE_SIZE (mode);
224 HOST_WIDE_INT size = GET_MODE_SIZE (Pmode);
225 emit_move_insn (adjust_address (mem, mode, offset), GEN_INT (size));
226 }
227
228 /* Generate code to initialize the register size table. */
229
230 void
231 expand_builtin_init_dwarf_reg_sizes (tree address)
232 {
233 unsigned int i;
234 enum machine_mode mode = TYPE_MODE (char_type_node);
235 rtx addr = expand_normal (address);
236 rtx mem = gen_rtx_MEM (BLKmode, addr);
237 bool wrote_return_column = false;
238
239 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
240 {
241 unsigned int dnum = DWARF_FRAME_REGNUM (i);
242 unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1);
243
244 if (rnum < DWARF_FRAME_REGISTERS)
245 {
246 HOST_WIDE_INT offset = rnum * GET_MODE_SIZE (mode);
247 enum machine_mode save_mode = reg_raw_mode[i];
248 HOST_WIDE_INT size;
249
250 if (HARD_REGNO_CALL_PART_CLOBBERED (i, save_mode))
251 save_mode = choose_hard_reg_mode (i, 1, true);
252 if (dnum == DWARF_FRAME_RETURN_COLUMN)
253 {
254 if (save_mode == VOIDmode)
255 continue;
256 wrote_return_column = true;
257 }
258 size = GET_MODE_SIZE (save_mode);
259 if (offset < 0)
260 continue;
261
262 emit_move_insn (adjust_address (mem, mode, offset),
263 gen_int_mode (size, mode));
264 }
265 }
266
267 if (!wrote_return_column)
268 init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN);
269
270 #ifdef DWARF_ALT_FRAME_RETURN_COLUMN
271 init_return_column_size (mode, mem, DWARF_ALT_FRAME_RETURN_COLUMN);
272 #endif
273
274 targetm.init_dwarf_reg_sizes_extra (address);
275 }
276
277 \f
278 static hashval_t
279 dw_trace_info_hash (const void *ptr)
280 {
281 const dw_trace_info *ti = (const dw_trace_info *) ptr;
282 return INSN_UID (ti->head);
283 }
284
285 static int
286 dw_trace_info_eq (const void *ptr_a, const void *ptr_b)
287 {
288 const dw_trace_info *a = (const dw_trace_info *) ptr_a;
289 const dw_trace_info *b = (const dw_trace_info *) ptr_b;
290 return a->head == b->head;
291 }
292
293 static dw_trace_info *
294 get_trace_info (rtx insn)
295 {
296 dw_trace_info dummy;
297 dummy.head = insn;
298 return (dw_trace_info *)
299 htab_find_with_hash (trace_index, &dummy, INSN_UID (insn));
300 }
301
302 static bool
303 save_point_p (rtx insn)
304 {
305 /* Labels, except those that are really jump tables. */
306 if (LABEL_P (insn))
307 return inside_basic_block_p (insn);
308
309 /* We split traces at the prologue/epilogue notes because those
310 are points at which the unwind info is usually stable. This
311 makes it easier to find spots with identical unwind info so
312 that we can use remember/restore_state opcodes. */
313 if (NOTE_P (insn))
314 switch (NOTE_KIND (insn))
315 {
316 case NOTE_INSN_PROLOGUE_END:
317 case NOTE_INSN_EPILOGUE_BEG:
318 return true;
319 }
320
321 return false;
322 }
323
324 /* Divide OFF by DWARF_CIE_DATA_ALIGNMENT, asserting no remainder. */
325
326 static inline HOST_WIDE_INT
327 div_data_align (HOST_WIDE_INT off)
328 {
329 HOST_WIDE_INT r = off / DWARF_CIE_DATA_ALIGNMENT;
330 gcc_assert (r * DWARF_CIE_DATA_ALIGNMENT == off);
331 return r;
332 }
333
334 /* Return true if we need a signed version of a given opcode
335 (e.g. DW_CFA_offset_extended_sf vs DW_CFA_offset_extended). */
336
337 static inline bool
338 need_data_align_sf_opcode (HOST_WIDE_INT off)
339 {
340 return DWARF_CIE_DATA_ALIGNMENT < 0 ? off > 0 : off < 0;
341 }
342
343 /* Return a pointer to a newly allocated Call Frame Instruction. */
344
345 static inline dw_cfi_ref
346 new_cfi (void)
347 {
348 dw_cfi_ref cfi = ggc_alloc_dw_cfi_node ();
349
350 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = 0;
351 cfi->dw_cfi_oprnd2.dw_cfi_reg_num = 0;
352
353 return cfi;
354 }
355
356 /* Return a newly allocated CFI row, with no defined data. */
357
358 static dw_cfi_row *
359 new_cfi_row (void)
360 {
361 dw_cfi_row *row = ggc_alloc_cleared_dw_cfi_row ();
362
363 row->cfa.reg = INVALID_REGNUM;
364
365 return row;
366 }
367
368 /* Return a copy of an existing CFI row. */
369
370 static dw_cfi_row *
371 copy_cfi_row (dw_cfi_row *src)
372 {
373 dw_cfi_row *dst = ggc_alloc_dw_cfi_row ();
374
375 *dst = *src;
376 dst->reg_save = VEC_copy (dw_cfi_ref, gc, src->reg_save);
377
378 return dst;
379 }
380
381 /* Generate a new label for the CFI info to refer to. */
382
383 static char *
384 dwarf2out_cfi_label (void)
385 {
386 int num = dwarf2out_cfi_label_num++;
387 char label[20];
388
389 ASM_GENERATE_INTERNAL_LABEL (label, "LCFI", num);
390
391 return xstrdup (label);
392 }
393
394 /* Add CFI either to the current insn stream or to a vector, or both. */
395
396 static void
397 add_cfi (dw_cfi_ref cfi)
398 {
399 any_cfis_emitted = true;
400
401 if (add_cfi_insn != NULL)
402 {
403 add_cfi_insn = emit_note_after (NOTE_INSN_CFI, add_cfi_insn);
404 NOTE_CFI (add_cfi_insn) = cfi;
405 }
406
407 if (add_cfi_vec != NULL)
408 VEC_safe_push (dw_cfi_ref, gc, *add_cfi_vec, cfi);
409 }
410
411 static void
412 add_cfi_args_size (HOST_WIDE_INT size)
413 {
414 dw_cfi_ref cfi = new_cfi ();
415
416 cfi->dw_cfi_opc = DW_CFA_GNU_args_size;
417 cfi->dw_cfi_oprnd1.dw_cfi_offset = size;
418
419 add_cfi (cfi);
420 }
421
422 static void
423 add_cfi_restore (unsigned reg)
424 {
425 dw_cfi_ref cfi = new_cfi ();
426
427 cfi->dw_cfi_opc = (reg & ~0x3f ? DW_CFA_restore_extended : DW_CFA_restore);
428 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
429
430 add_cfi (cfi);
431 }
432
433 /* Perform ROW->REG_SAVE[COLUMN] = CFI. CFI may be null, indicating
434 that the register column is no longer saved. */
435
436 static void
437 update_row_reg_save (dw_cfi_row *row, unsigned column, dw_cfi_ref cfi)
438 {
439 if (VEC_length (dw_cfi_ref, row->reg_save) <= column)
440 VEC_safe_grow_cleared (dw_cfi_ref, gc, row->reg_save, column + 1);
441 VEC_replace (dw_cfi_ref, row->reg_save, column, cfi);
442 }
443
444 /* This function fills in aa dw_cfa_location structure from a dwarf location
445 descriptor sequence. */
446
447 static void
448 get_cfa_from_loc_descr (dw_cfa_location *cfa, struct dw_loc_descr_struct *loc)
449 {
450 struct dw_loc_descr_struct *ptr;
451 cfa->offset = 0;
452 cfa->base_offset = 0;
453 cfa->indirect = 0;
454 cfa->reg = -1;
455
456 for (ptr = loc; ptr != NULL; ptr = ptr->dw_loc_next)
457 {
458 enum dwarf_location_atom op = ptr->dw_loc_opc;
459
460 switch (op)
461 {
462 case DW_OP_reg0:
463 case DW_OP_reg1:
464 case DW_OP_reg2:
465 case DW_OP_reg3:
466 case DW_OP_reg4:
467 case DW_OP_reg5:
468 case DW_OP_reg6:
469 case DW_OP_reg7:
470 case DW_OP_reg8:
471 case DW_OP_reg9:
472 case DW_OP_reg10:
473 case DW_OP_reg11:
474 case DW_OP_reg12:
475 case DW_OP_reg13:
476 case DW_OP_reg14:
477 case DW_OP_reg15:
478 case DW_OP_reg16:
479 case DW_OP_reg17:
480 case DW_OP_reg18:
481 case DW_OP_reg19:
482 case DW_OP_reg20:
483 case DW_OP_reg21:
484 case DW_OP_reg22:
485 case DW_OP_reg23:
486 case DW_OP_reg24:
487 case DW_OP_reg25:
488 case DW_OP_reg26:
489 case DW_OP_reg27:
490 case DW_OP_reg28:
491 case DW_OP_reg29:
492 case DW_OP_reg30:
493 case DW_OP_reg31:
494 cfa->reg = op - DW_OP_reg0;
495 break;
496 case DW_OP_regx:
497 cfa->reg = ptr->dw_loc_oprnd1.v.val_int;
498 break;
499 case DW_OP_breg0:
500 case DW_OP_breg1:
501 case DW_OP_breg2:
502 case DW_OP_breg3:
503 case DW_OP_breg4:
504 case DW_OP_breg5:
505 case DW_OP_breg6:
506 case DW_OP_breg7:
507 case DW_OP_breg8:
508 case DW_OP_breg9:
509 case DW_OP_breg10:
510 case DW_OP_breg11:
511 case DW_OP_breg12:
512 case DW_OP_breg13:
513 case DW_OP_breg14:
514 case DW_OP_breg15:
515 case DW_OP_breg16:
516 case DW_OP_breg17:
517 case DW_OP_breg18:
518 case DW_OP_breg19:
519 case DW_OP_breg20:
520 case DW_OP_breg21:
521 case DW_OP_breg22:
522 case DW_OP_breg23:
523 case DW_OP_breg24:
524 case DW_OP_breg25:
525 case DW_OP_breg26:
526 case DW_OP_breg27:
527 case DW_OP_breg28:
528 case DW_OP_breg29:
529 case DW_OP_breg30:
530 case DW_OP_breg31:
531 cfa->reg = op - DW_OP_breg0;
532 cfa->base_offset = ptr->dw_loc_oprnd1.v.val_int;
533 break;
534 case DW_OP_bregx:
535 cfa->reg = ptr->dw_loc_oprnd1.v.val_int;
536 cfa->base_offset = ptr->dw_loc_oprnd2.v.val_int;
537 break;
538 case DW_OP_deref:
539 cfa->indirect = 1;
540 break;
541 case DW_OP_plus_uconst:
542 cfa->offset = ptr->dw_loc_oprnd1.v.val_unsigned;
543 break;
544 default:
545 gcc_unreachable ();
546 }
547 }
548 }
549
550 /* Find the previous value for the CFA, iteratively. CFI is the opcode
551 to interpret, *LOC will be updated as necessary, *REMEMBER is used for
552 one level of remember/restore state processing. */
553
554 void
555 lookup_cfa_1 (dw_cfi_ref cfi, dw_cfa_location *loc, dw_cfa_location *remember)
556 {
557 switch (cfi->dw_cfi_opc)
558 {
559 case DW_CFA_def_cfa_offset:
560 case DW_CFA_def_cfa_offset_sf:
561 loc->offset = cfi->dw_cfi_oprnd1.dw_cfi_offset;
562 break;
563 case DW_CFA_def_cfa_register:
564 loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num;
565 break;
566 case DW_CFA_def_cfa:
567 case DW_CFA_def_cfa_sf:
568 loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num;
569 loc->offset = cfi->dw_cfi_oprnd2.dw_cfi_offset;
570 break;
571 case DW_CFA_def_cfa_expression:
572 get_cfa_from_loc_descr (loc, cfi->dw_cfi_oprnd1.dw_cfi_loc);
573 break;
574
575 case DW_CFA_remember_state:
576 gcc_assert (!remember->in_use);
577 *remember = *loc;
578 remember->in_use = 1;
579 break;
580 case DW_CFA_restore_state:
581 gcc_assert (remember->in_use);
582 *loc = *remember;
583 remember->in_use = 0;
584 break;
585
586 default:
587 break;
588 }
589 }
590
591 /* Determine if two dw_cfa_location structures define the same data. */
592
593 bool
594 cfa_equal_p (const dw_cfa_location *loc1, const dw_cfa_location *loc2)
595 {
596 return (loc1->reg == loc2->reg
597 && loc1->offset == loc2->offset
598 && loc1->indirect == loc2->indirect
599 && (loc1->indirect == 0
600 || loc1->base_offset == loc2->base_offset));
601 }
602
603 /* Determine if two CFI operands are identical. */
604
605 static bool
606 cfi_oprnd_equal_p (enum dw_cfi_oprnd_type t, dw_cfi_oprnd *a, dw_cfi_oprnd *b)
607 {
608 switch (t)
609 {
610 case dw_cfi_oprnd_unused:
611 return true;
612 case dw_cfi_oprnd_reg_num:
613 return a->dw_cfi_reg_num == b->dw_cfi_reg_num;
614 case dw_cfi_oprnd_offset:
615 return a->dw_cfi_offset == b->dw_cfi_offset;
616 case dw_cfi_oprnd_addr:
617 return (a->dw_cfi_addr == b->dw_cfi_addr
618 || strcmp (a->dw_cfi_addr, b->dw_cfi_addr) == 0);
619 case dw_cfi_oprnd_loc:
620 return loc_descr_equal_p (a->dw_cfi_loc, b->dw_cfi_loc);
621 }
622 gcc_unreachable ();
623 }
624
625 /* Determine if two CFI entries are identical. */
626
627 static bool
628 cfi_equal_p (dw_cfi_ref a, dw_cfi_ref b)
629 {
630 enum dwarf_call_frame_info opc;
631
632 /* Make things easier for our callers, including missing operands. */
633 if (a == b)
634 return true;
635 if (a == NULL || b == NULL)
636 return false;
637
638 /* Obviously, the opcodes must match. */
639 opc = a->dw_cfi_opc;
640 if (opc != b->dw_cfi_opc)
641 return false;
642
643 /* Compare the two operands, re-using the type of the operands as
644 already exposed elsewhere. */
645 return (cfi_oprnd_equal_p (dw_cfi_oprnd1_desc (opc),
646 &a->dw_cfi_oprnd1, &b->dw_cfi_oprnd1)
647 && cfi_oprnd_equal_p (dw_cfi_oprnd2_desc (opc),
648 &a->dw_cfi_oprnd2, &b->dw_cfi_oprnd2));
649 }
650
651 /* Determine if two CFI_ROW structures are identical. */
652
653 static bool
654 cfi_row_equal_p (dw_cfi_row *a, dw_cfi_row *b)
655 {
656 size_t i, n_a, n_b, n_max;
657
658 if (a->cfa_cfi)
659 {
660 if (!cfi_equal_p (a->cfa_cfi, b->cfa_cfi))
661 return false;
662 }
663 else if (!cfa_equal_p (&a->cfa, &b->cfa))
664 return false;
665
666 /* Logic suggests that we compare args_size here. However, if
667 EXIT_IGNORE_STACK we don't bother tracking the args_size after
668 the last time it really matters within the function. This does
669 in fact lead to paths with differing arg_size, but in cases for
670 which it doesn't matter. */
671 /* ??? If we really want to sanity check the output of the optimizers,
672 find a way to backtrack from epilogues to the last EH site. This
673 would allow us to distinguish regions with garbage args_size and
674 regions where paths ought to agree. */
675
676 n_a = VEC_length (dw_cfi_ref, a->reg_save);
677 n_b = VEC_length (dw_cfi_ref, b->reg_save);
678 n_max = MAX (n_a, n_b);
679
680 for (i = 0; i < n_max; ++i)
681 {
682 dw_cfi_ref r_a = NULL, r_b = NULL;
683
684 if (i < n_a)
685 r_a = VEC_index (dw_cfi_ref, a->reg_save, i);
686 if (i < n_b)
687 r_b = VEC_index (dw_cfi_ref, b->reg_save, i);
688
689 if (!cfi_equal_p (r_a, r_b))
690 return false;
691 }
692
693 return true;
694 }
695
696 /* The CFA is now calculated from NEW_CFA. Consider OLD_CFA in determining
697 what opcode to emit. Returns the CFI opcode to effect the change, or
698 NULL if NEW_CFA == OLD_CFA. */
699
700 static dw_cfi_ref
701 def_cfa_0 (dw_cfa_location *old_cfa, dw_cfa_location *new_cfa)
702 {
703 dw_cfi_ref cfi;
704
705 /* If nothing changed, no need to issue any call frame instructions. */
706 if (cfa_equal_p (old_cfa, new_cfa))
707 return NULL;
708
709 cfi = new_cfi ();
710
711 if (new_cfa->reg == old_cfa->reg && !new_cfa->indirect && !old_cfa->indirect)
712 {
713 /* Construct a "DW_CFA_def_cfa_offset <offset>" instruction, indicating
714 the CFA register did not change but the offset did. The data
715 factoring for DW_CFA_def_cfa_offset_sf happens in output_cfi, or
716 in the assembler via the .cfi_def_cfa_offset directive. */
717 if (new_cfa->offset < 0)
718 cfi->dw_cfi_opc = DW_CFA_def_cfa_offset_sf;
719 else
720 cfi->dw_cfi_opc = DW_CFA_def_cfa_offset;
721 cfi->dw_cfi_oprnd1.dw_cfi_offset = new_cfa->offset;
722 }
723
724 #ifndef MIPS_DEBUGGING_INFO /* SGI dbx thinks this means no offset. */
725 else if (new_cfa->offset == old_cfa->offset
726 && old_cfa->reg != INVALID_REGNUM
727 && !new_cfa->indirect
728 && !old_cfa->indirect)
729 {
730 /* Construct a "DW_CFA_def_cfa_register <register>" instruction,
731 indicating the CFA register has changed to <register> but the
732 offset has not changed. */
733 cfi->dw_cfi_opc = DW_CFA_def_cfa_register;
734 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg;
735 }
736 #endif
737
738 else if (new_cfa->indirect == 0)
739 {
740 /* Construct a "DW_CFA_def_cfa <register> <offset>" instruction,
741 indicating the CFA register has changed to <register> with
742 the specified offset. The data factoring for DW_CFA_def_cfa_sf
743 happens in output_cfi, or in the assembler via the .cfi_def_cfa
744 directive. */
745 if (new_cfa->offset < 0)
746 cfi->dw_cfi_opc = DW_CFA_def_cfa_sf;
747 else
748 cfi->dw_cfi_opc = DW_CFA_def_cfa;
749 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg;
750 cfi->dw_cfi_oprnd2.dw_cfi_offset = new_cfa->offset;
751 }
752 else
753 {
754 /* Construct a DW_CFA_def_cfa_expression instruction to
755 calculate the CFA using a full location expression since no
756 register-offset pair is available. */
757 struct dw_loc_descr_struct *loc_list;
758
759 cfi->dw_cfi_opc = DW_CFA_def_cfa_expression;
760 loc_list = build_cfa_loc (new_cfa, 0);
761 cfi->dw_cfi_oprnd1.dw_cfi_loc = loc_list;
762 }
763
764 return cfi;
765 }
766
767 /* Similarly, but take OLD_CFA from CUR_ROW, and update it after the fact. */
768
769 static void
770 def_cfa_1 (dw_cfa_location *new_cfa)
771 {
772 dw_cfi_ref cfi;
773
774 if (cur_trace->cfa_store.reg == new_cfa->reg && new_cfa->indirect == 0)
775 cur_trace->cfa_store.offset = new_cfa->offset;
776
777 cfi = def_cfa_0 (&cur_row->cfa, new_cfa);
778 if (cfi)
779 {
780 cur_row->cfa = *new_cfa;
781 cur_row->cfa_cfi = (cfi->dw_cfi_opc == DW_CFA_def_cfa_expression
782 ? cfi : NULL);
783
784 add_cfi (cfi);
785 }
786 }
787
788 /* Add the CFI for saving a register. REG is the CFA column number.
789 If SREG is -1, the register is saved at OFFSET from the CFA;
790 otherwise it is saved in SREG. */
791
792 static void
793 reg_save (unsigned int reg, unsigned int sreg, HOST_WIDE_INT offset)
794 {
795 dw_fde_ref fde = cfun ? cfun->fde : NULL;
796 dw_cfi_ref cfi = new_cfi ();
797
798 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
799
800 /* When stack is aligned, store REG using DW_CFA_expression with FP. */
801 if (fde
802 && fde->stack_realign
803 && sreg == INVALID_REGNUM)
804 {
805 cfi->dw_cfi_opc = DW_CFA_expression;
806 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg;
807 cfi->dw_cfi_oprnd2.dw_cfi_loc
808 = build_cfa_aligned_loc (&cur_row->cfa, offset,
809 fde->stack_realignment);
810 }
811 else if (sreg == INVALID_REGNUM)
812 {
813 if (need_data_align_sf_opcode (offset))
814 cfi->dw_cfi_opc = DW_CFA_offset_extended_sf;
815 else if (reg & ~0x3f)
816 cfi->dw_cfi_opc = DW_CFA_offset_extended;
817 else
818 cfi->dw_cfi_opc = DW_CFA_offset;
819 cfi->dw_cfi_oprnd2.dw_cfi_offset = offset;
820 }
821 else if (sreg == reg)
822 {
823 /* While we could emit something like DW_CFA_same_value or
824 DW_CFA_restore, we never expect to see something like that
825 in a prologue. This is more likely to be a bug. A backend
826 can always bypass this by using REG_CFA_RESTORE directly. */
827 gcc_unreachable ();
828 }
829 else
830 {
831 cfi->dw_cfi_opc = DW_CFA_register;
832 cfi->dw_cfi_oprnd2.dw_cfi_reg_num = sreg;
833 }
834
835 add_cfi (cfi);
836 update_row_reg_save (cur_row, reg, cfi);
837 }
838
839 /* Given a SET, calculate the amount of stack adjustment it
840 contains. */
841
842 static HOST_WIDE_INT
843 stack_adjust_offset (const_rtx pattern, HOST_WIDE_INT cur_args_size,
844 HOST_WIDE_INT cur_offset)
845 {
846 const_rtx src = SET_SRC (pattern);
847 const_rtx dest = SET_DEST (pattern);
848 HOST_WIDE_INT offset = 0;
849 enum rtx_code code;
850
851 if (dest == stack_pointer_rtx)
852 {
853 code = GET_CODE (src);
854
855 /* Assume (set (reg sp) (reg whatever)) sets args_size
856 level to 0. */
857 if (code == REG && src != stack_pointer_rtx)
858 {
859 offset = -cur_args_size;
860 #ifndef STACK_GROWS_DOWNWARD
861 offset = -offset;
862 #endif
863 return offset - cur_offset;
864 }
865
866 if (! (code == PLUS || code == MINUS)
867 || XEXP (src, 0) != stack_pointer_rtx
868 || !CONST_INT_P (XEXP (src, 1)))
869 return 0;
870
871 /* (set (reg sp) (plus (reg sp) (const_int))) */
872 offset = INTVAL (XEXP (src, 1));
873 if (code == PLUS)
874 offset = -offset;
875 return offset;
876 }
877
878 if (MEM_P (src) && !MEM_P (dest))
879 dest = src;
880 if (MEM_P (dest))
881 {
882 /* (set (mem (pre_dec (reg sp))) (foo)) */
883 src = XEXP (dest, 0);
884 code = GET_CODE (src);
885
886 switch (code)
887 {
888 case PRE_MODIFY:
889 case POST_MODIFY:
890 if (XEXP (src, 0) == stack_pointer_rtx)
891 {
892 rtx val = XEXP (XEXP (src, 1), 1);
893 /* We handle only adjustments by constant amount. */
894 gcc_assert (GET_CODE (XEXP (src, 1)) == PLUS
895 && CONST_INT_P (val));
896 offset = -INTVAL (val);
897 break;
898 }
899 return 0;
900
901 case PRE_DEC:
902 case POST_DEC:
903 if (XEXP (src, 0) == stack_pointer_rtx)
904 {
905 offset = GET_MODE_SIZE (GET_MODE (dest));
906 break;
907 }
908 return 0;
909
910 case PRE_INC:
911 case POST_INC:
912 if (XEXP (src, 0) == stack_pointer_rtx)
913 {
914 offset = -GET_MODE_SIZE (GET_MODE (dest));
915 break;
916 }
917 return 0;
918
919 default:
920 return 0;
921 }
922 }
923 else
924 return 0;
925
926 return offset;
927 }
928
929 /* Add a CFI to update the running total of the size of arguments
930 pushed onto the stack. */
931
932 static void
933 dwarf2out_args_size (HOST_WIDE_INT size)
934 {
935 if (size == cur_row->args_size)
936 return;
937
938 cur_row->args_size = size;
939 add_cfi_args_size (size);
940 }
941
942 /* Record a stack adjustment of OFFSET bytes. */
943
944 static void
945 dwarf2out_stack_adjust (HOST_WIDE_INT offset)
946 {
947 dw_cfa_location loc = cur_row->cfa;
948
949 if (loc.reg == dw_stack_pointer_regnum)
950 loc.offset += offset;
951
952 if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum)
953 cur_trace->cfa_store.offset += offset;
954
955 /* ??? The assumption seems to be that if A_O_A, the only CFA adjustments
956 involving the stack pointer are inside the prologue and marked as
957 RTX_FRAME_RELATED_P. That said, should we not verify this assumption
958 by *asserting* A_O_A at this point? Why else would we have a change
959 to the stack pointer? */
960 if (ACCUMULATE_OUTGOING_ARGS)
961 return;
962
963 #ifndef STACK_GROWS_DOWNWARD
964 offset = -offset;
965 #endif
966
967 queued_args_size += offset;
968 if (queued_args_size < 0)
969 queued_args_size = 0;
970
971 def_cfa_1 (&loc);
972 if (flag_asynchronous_unwind_tables)
973 dwarf2out_args_size (queued_args_size);
974 }
975
976 /* Check INSN to see if it looks like a push or a stack adjustment, and
977 make a note of it if it does. EH uses this information to find out
978 how much extra space it needs to pop off the stack. */
979
980 static void
981 dwarf2out_notice_stack_adjust (rtx insn, bool after_p)
982 {
983 HOST_WIDE_INT offset;
984 int i;
985
986 /* Don't handle epilogues at all. Certainly it would be wrong to do so
987 with this function. Proper support would require all frame-related
988 insns to be marked, and to be able to handle saving state around
989 epilogues textually in the middle of the function. */
990 if (prologue_epilogue_contains (insn))
991 return;
992
993 /* If INSN is an instruction from target of an annulled branch, the
994 effects are for the target only and so current argument size
995 shouldn't change at all. */
996 if (final_sequence
997 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
998 && INSN_FROM_TARGET_P (insn))
999 return;
1000
1001 /* If only calls can throw, and we have a frame pointer,
1002 save up adjustments until we see the CALL_INSN. */
1003 if (!flag_asynchronous_unwind_tables
1004 && cur_row->cfa.reg != dw_stack_pointer_regnum)
1005 {
1006 if (CALL_P (insn) && !after_p)
1007 {
1008 /* Extract the size of the args from the CALL rtx itself. */
1009 insn = PATTERN (insn);
1010 if (GET_CODE (insn) == PARALLEL)
1011 insn = XVECEXP (insn, 0, 0);
1012 if (GET_CODE (insn) == SET)
1013 insn = SET_SRC (insn);
1014 gcc_assert (GET_CODE (insn) == CALL);
1015 dwarf2out_args_size (INTVAL (XEXP (insn, 1)));
1016 }
1017 return;
1018 }
1019
1020 if (CALL_P (insn) && !after_p)
1021 {
1022 if (!flag_asynchronous_unwind_tables)
1023 dwarf2out_args_size (queued_args_size);
1024 return;
1025 }
1026 else if (BARRIER_P (insn))
1027 return;
1028 else if (GET_CODE (PATTERN (insn)) == SET)
1029 offset = stack_adjust_offset (PATTERN (insn), queued_args_size, 0);
1030 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1031 || GET_CODE (PATTERN (insn)) == SEQUENCE)
1032 {
1033 /* There may be stack adjustments inside compound insns. Search
1034 for them. */
1035 for (offset = 0, i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1036 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET)
1037 offset += stack_adjust_offset (XVECEXP (PATTERN (insn), 0, i),
1038 queued_args_size, offset);
1039 }
1040 else
1041 return;
1042
1043 if (offset == 0)
1044 return;
1045
1046 dwarf2out_stack_adjust (offset);
1047 }
1048
1049 /* Short-hand inline for the very common D_F_R (REGNO (x)) operation. */
1050 /* ??? This ought to go into dwarf2out.h, except that dwarf2out.h is
1051 used in places where rtl is prohibited. */
1052
1053 static inline unsigned
1054 dwf_regno (const_rtx reg)
1055 {
1056 return DWARF_FRAME_REGNUM (REGNO (reg));
1057 }
1058
1059 /* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */
1060
1061 static bool
1062 compare_reg_or_pc (rtx x, rtx y)
1063 {
1064 if (REG_P (x) && REG_P (y))
1065 return REGNO (x) == REGNO (y);
1066 return x == y;
1067 }
1068
1069 /* Record SRC as being saved in DEST. DEST may be null to delete an
1070 existing entry. SRC may be a register or PC_RTX. */
1071
1072 static void
1073 record_reg_saved_in_reg (rtx dest, rtx src)
1074 {
1075 reg_saved_in_data *elt;
1076 size_t i;
1077
1078 FOR_EACH_VEC_ELT (reg_saved_in_data, cur_trace->regs_saved_in_regs, i, elt)
1079 if (compare_reg_or_pc (elt->orig_reg, src))
1080 {
1081 if (dest == NULL)
1082 VEC_unordered_remove (reg_saved_in_data,
1083 cur_trace->regs_saved_in_regs, i);
1084 else
1085 elt->saved_in_reg = dest;
1086 return;
1087 }
1088
1089 if (dest == NULL)
1090 return;
1091
1092 elt = VEC_safe_push (reg_saved_in_data, heap,
1093 cur_trace->regs_saved_in_regs, NULL);
1094 elt->orig_reg = src;
1095 elt->saved_in_reg = dest;
1096 }
1097
1098 /* Add an entry to QUEUED_REG_SAVES saying that REG is now saved at
1099 SREG, or if SREG is NULL then it is saved at OFFSET to the CFA. */
1100
1101 static void
1102 queue_reg_save (rtx reg, rtx sreg, HOST_WIDE_INT offset)
1103 {
1104 queued_reg_save *q;
1105 size_t i;
1106
1107 /* Duplicates waste space, but it's also necessary to remove them
1108 for correctness, since the queue gets output in reverse order. */
1109 FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, i, q)
1110 if (compare_reg_or_pc (q->reg, reg))
1111 goto found;
1112
1113 q = VEC_safe_push (queued_reg_save, heap, queued_reg_saves, NULL);
1114
1115 found:
1116 q->reg = reg;
1117 q->saved_reg = sreg;
1118 q->cfa_offset = offset;
1119 }
1120
1121 /* Output all the entries in QUEUED_REG_SAVES. */
1122
1123 static void
1124 dwarf2out_flush_queued_reg_saves (void)
1125 {
1126 queued_reg_save *q;
1127 size_t i;
1128
1129 FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, i, q)
1130 {
1131 unsigned int reg, sreg;
1132
1133 record_reg_saved_in_reg (q->saved_reg, q->reg);
1134
1135 if (q->reg == pc_rtx)
1136 reg = DWARF_FRAME_RETURN_COLUMN;
1137 else
1138 reg = dwf_regno (q->reg);
1139 if (q->saved_reg)
1140 sreg = dwf_regno (q->saved_reg);
1141 else
1142 sreg = INVALID_REGNUM;
1143 reg_save (reg, sreg, q->cfa_offset);
1144 }
1145
1146 VEC_truncate (queued_reg_save, queued_reg_saves, 0);
1147 }
1148
1149 /* Does INSN clobber any register which QUEUED_REG_SAVES lists a saved
1150 location for? Or, does it clobber a register which we've previously
1151 said that some other register is saved in, and for which we now
1152 have a new location for? */
1153
1154 static bool
1155 clobbers_queued_reg_save (const_rtx insn)
1156 {
1157 queued_reg_save *q;
1158 size_t iq;
1159
1160 FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, iq, q)
1161 {
1162 size_t ir;
1163 reg_saved_in_data *rir;
1164
1165 if (modified_in_p (q->reg, insn))
1166 return true;
1167
1168 FOR_EACH_VEC_ELT (reg_saved_in_data,
1169 cur_trace->regs_saved_in_regs, ir, rir)
1170 if (compare_reg_or_pc (q->reg, rir->orig_reg)
1171 && modified_in_p (rir->saved_in_reg, insn))
1172 return true;
1173 }
1174
1175 return false;
1176 }
1177
1178 /* What register, if any, is currently saved in REG? */
1179
1180 static rtx
1181 reg_saved_in (rtx reg)
1182 {
1183 unsigned int regn = REGNO (reg);
1184 queued_reg_save *q;
1185 reg_saved_in_data *rir;
1186 size_t i;
1187
1188 FOR_EACH_VEC_ELT (queued_reg_save, queued_reg_saves, i, q)
1189 if (q->saved_reg && regn == REGNO (q->saved_reg))
1190 return q->reg;
1191
1192 FOR_EACH_VEC_ELT (reg_saved_in_data, cur_trace->regs_saved_in_regs, i, rir)
1193 if (regn == REGNO (rir->saved_in_reg))
1194 return rir->orig_reg;
1195
1196 return NULL_RTX;
1197 }
1198
1199 /* A subroutine of dwarf2out_frame_debug, process a REG_DEF_CFA note. */
1200
1201 static void
1202 dwarf2out_frame_debug_def_cfa (rtx pat)
1203 {
1204 dw_cfa_location loc;
1205
1206 memset (&loc, 0, sizeof (loc));
1207
1208 if (GET_CODE (pat) == PLUS)
1209 {
1210 loc.offset = INTVAL (XEXP (pat, 1));
1211 pat = XEXP (pat, 0);
1212 }
1213 if (MEM_P (pat))
1214 {
1215 loc.indirect = 1;
1216 pat = XEXP (pat, 0);
1217 if (GET_CODE (pat) == PLUS)
1218 {
1219 loc.base_offset = INTVAL (XEXP (pat, 1));
1220 pat = XEXP (pat, 0);
1221 }
1222 }
1223 /* ??? If this fails, we could be calling into the _loc functions to
1224 define a full expression. So far no port does that. */
1225 gcc_assert (REG_P (pat));
1226 loc.reg = dwf_regno (pat);
1227
1228 def_cfa_1 (&loc);
1229 }
1230
1231 /* A subroutine of dwarf2out_frame_debug, process a REG_ADJUST_CFA note. */
1232
1233 static void
1234 dwarf2out_frame_debug_adjust_cfa (rtx pat)
1235 {
1236 dw_cfa_location loc = cur_row->cfa;
1237 rtx src, dest;
1238
1239 gcc_assert (GET_CODE (pat) == SET);
1240 dest = XEXP (pat, 0);
1241 src = XEXP (pat, 1);
1242
1243 switch (GET_CODE (src))
1244 {
1245 case PLUS:
1246 gcc_assert (dwf_regno (XEXP (src, 0)) == loc.reg);
1247 loc.offset -= INTVAL (XEXP (src, 1));
1248 break;
1249
1250 case REG:
1251 break;
1252
1253 default:
1254 gcc_unreachable ();
1255 }
1256
1257 loc.reg = dwf_regno (dest);
1258 gcc_assert (loc.indirect == 0);
1259
1260 def_cfa_1 (&loc);
1261 }
1262
1263 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_OFFSET note. */
1264
1265 static void
1266 dwarf2out_frame_debug_cfa_offset (rtx set)
1267 {
1268 HOST_WIDE_INT offset;
1269 rtx src, addr, span;
1270 unsigned int sregno;
1271
1272 src = XEXP (set, 1);
1273 addr = XEXP (set, 0);
1274 gcc_assert (MEM_P (addr));
1275 addr = XEXP (addr, 0);
1276
1277 /* As documented, only consider extremely simple addresses. */
1278 switch (GET_CODE (addr))
1279 {
1280 case REG:
1281 gcc_assert (dwf_regno (addr) == cur_row->cfa.reg);
1282 offset = -cur_row->cfa.offset;
1283 break;
1284 case PLUS:
1285 gcc_assert (dwf_regno (XEXP (addr, 0)) == cur_row->cfa.reg);
1286 offset = INTVAL (XEXP (addr, 1)) - cur_row->cfa.offset;
1287 break;
1288 default:
1289 gcc_unreachable ();
1290 }
1291
1292 if (src == pc_rtx)
1293 {
1294 span = NULL;
1295 sregno = DWARF_FRAME_RETURN_COLUMN;
1296 }
1297 else
1298 {
1299 span = targetm.dwarf_register_span (src);
1300 sregno = dwf_regno (src);
1301 }
1302
1303 /* ??? We'd like to use queue_reg_save, but we need to come up with
1304 a different flushing heuristic for epilogues. */
1305 if (!span)
1306 reg_save (sregno, INVALID_REGNUM, offset);
1307 else
1308 {
1309 /* We have a PARALLEL describing where the contents of SRC live.
1310 Queue register saves for each piece of the PARALLEL. */
1311 int par_index;
1312 int limit;
1313 HOST_WIDE_INT span_offset = offset;
1314
1315 gcc_assert (GET_CODE (span) == PARALLEL);
1316
1317 limit = XVECLEN (span, 0);
1318 for (par_index = 0; par_index < limit; par_index++)
1319 {
1320 rtx elem = XVECEXP (span, 0, par_index);
1321
1322 sregno = dwf_regno (src);
1323 reg_save (sregno, INVALID_REGNUM, span_offset);
1324 span_offset += GET_MODE_SIZE (GET_MODE (elem));
1325 }
1326 }
1327 }
1328
1329 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_REGISTER note. */
1330
1331 static void
1332 dwarf2out_frame_debug_cfa_register (rtx set)
1333 {
1334 rtx src, dest;
1335 unsigned sregno, dregno;
1336
1337 src = XEXP (set, 1);
1338 dest = XEXP (set, 0);
1339
1340 record_reg_saved_in_reg (dest, src);
1341 if (src == pc_rtx)
1342 sregno = DWARF_FRAME_RETURN_COLUMN;
1343 else
1344 sregno = dwf_regno (src);
1345
1346 dregno = dwf_regno (dest);
1347
1348 /* ??? We'd like to use queue_reg_save, but we need to come up with
1349 a different flushing heuristic for epilogues. */
1350 reg_save (sregno, dregno, 0);
1351 }
1352
1353 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */
1354
1355 static void
1356 dwarf2out_frame_debug_cfa_expression (rtx set)
1357 {
1358 rtx src, dest, span;
1359 dw_cfi_ref cfi = new_cfi ();
1360 unsigned regno;
1361
1362 dest = SET_DEST (set);
1363 src = SET_SRC (set);
1364
1365 gcc_assert (REG_P (src));
1366 gcc_assert (MEM_P (dest));
1367
1368 span = targetm.dwarf_register_span (src);
1369 gcc_assert (!span);
1370
1371 regno = dwf_regno (src);
1372
1373 cfi->dw_cfi_opc = DW_CFA_expression;
1374 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = regno;
1375 cfi->dw_cfi_oprnd2.dw_cfi_loc
1376 = mem_loc_descriptor (XEXP (dest, 0), get_address_mode (dest),
1377 GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED);
1378
1379 /* ??? We'd like to use queue_reg_save, were the interface different,
1380 and, as above, we could manage flushing for epilogues. */
1381 add_cfi (cfi);
1382 update_row_reg_save (cur_row, regno, cfi);
1383 }
1384
1385 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */
1386
1387 static void
1388 dwarf2out_frame_debug_cfa_restore (rtx reg)
1389 {
1390 unsigned int regno = dwf_regno (reg);
1391
1392 add_cfi_restore (regno);
1393 update_row_reg_save (cur_row, regno, NULL);
1394 }
1395
1396 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_WINDOW_SAVE.
1397 ??? Perhaps we should note in the CIE where windows are saved (instead of
1398 assuming 0(cfa)) and what registers are in the window. */
1399
1400 static void
1401 dwarf2out_frame_debug_cfa_window_save (void)
1402 {
1403 dw_cfi_ref cfi = new_cfi ();
1404
1405 cfi->dw_cfi_opc = DW_CFA_GNU_window_save;
1406 add_cfi (cfi);
1407 }
1408
1409 /* Record call frame debugging information for an expression EXPR,
1410 which either sets SP or FP (adjusting how we calculate the frame
1411 address) or saves a register to the stack or another register.
1412 LABEL indicates the address of EXPR.
1413
1414 This function encodes a state machine mapping rtxes to actions on
1415 cfa, cfa_store, and cfa_temp.reg. We describe these rules so
1416 users need not read the source code.
1417
1418 The High-Level Picture
1419
1420 Changes in the register we use to calculate the CFA: Currently we
1421 assume that if you copy the CFA register into another register, we
1422 should take the other one as the new CFA register; this seems to
1423 work pretty well. If it's wrong for some target, it's simple
1424 enough not to set RTX_FRAME_RELATED_P on the insn in question.
1425
1426 Changes in the register we use for saving registers to the stack:
1427 This is usually SP, but not always. Again, we deduce that if you
1428 copy SP into another register (and SP is not the CFA register),
1429 then the new register is the one we will be using for register
1430 saves. This also seems to work.
1431
1432 Register saves: There's not much guesswork about this one; if
1433 RTX_FRAME_RELATED_P is set on an insn which modifies memory, it's a
1434 register save, and the register used to calculate the destination
1435 had better be the one we think we're using for this purpose.
1436 It's also assumed that a copy from a call-saved register to another
1437 register is saving that register if RTX_FRAME_RELATED_P is set on
1438 that instruction. If the copy is from a call-saved register to
1439 the *same* register, that means that the register is now the same
1440 value as in the caller.
1441
1442 Except: If the register being saved is the CFA register, and the
1443 offset is nonzero, we are saving the CFA, so we assume we have to
1444 use DW_CFA_def_cfa_expression. If the offset is 0, we assume that
1445 the intent is to save the value of SP from the previous frame.
1446
1447 In addition, if a register has previously been saved to a different
1448 register,
1449
1450 Invariants / Summaries of Rules
1451
1452 cfa current rule for calculating the CFA. It usually
1453 consists of a register and an offset. This is
1454 actually stored in cur_row->cfa, but abbreviated
1455 for the purposes of this documentation.
1456 cfa_store register used by prologue code to save things to the stack
1457 cfa_store.offset is the offset from the value of
1458 cfa_store.reg to the actual CFA
1459 cfa_temp register holding an integral value. cfa_temp.offset
1460 stores the value, which will be used to adjust the
1461 stack pointer. cfa_temp is also used like cfa_store,
1462 to track stores to the stack via fp or a temp reg.
1463
1464 Rules 1- 4: Setting a register's value to cfa.reg or an expression
1465 with cfa.reg as the first operand changes the cfa.reg and its
1466 cfa.offset. Rule 1 and 4 also set cfa_temp.reg and
1467 cfa_temp.offset.
1468
1469 Rules 6- 9: Set a non-cfa.reg register value to a constant or an
1470 expression yielding a constant. This sets cfa_temp.reg
1471 and cfa_temp.offset.
1472
1473 Rule 5: Create a new register cfa_store used to save items to the
1474 stack.
1475
1476 Rules 10-14: Save a register to the stack. Define offset as the
1477 difference of the original location and cfa_store's
1478 location (or cfa_temp's location if cfa_temp is used).
1479
1480 Rules 16-20: If AND operation happens on sp in prologue, we assume
1481 stack is realigned. We will use a group of DW_OP_XXX
1482 expressions to represent the location of the stored
1483 register instead of CFA+offset.
1484
1485 The Rules
1486
1487 "{a,b}" indicates a choice of a xor b.
1488 "<reg>:cfa.reg" indicates that <reg> must equal cfa.reg.
1489
1490 Rule 1:
1491 (set <reg1> <reg2>:cfa.reg)
1492 effects: cfa.reg = <reg1>
1493 cfa.offset unchanged
1494 cfa_temp.reg = <reg1>
1495 cfa_temp.offset = cfa.offset
1496
1497 Rule 2:
1498 (set sp ({minus,plus,losum} {sp,fp}:cfa.reg
1499 {<const_int>,<reg>:cfa_temp.reg}))
1500 effects: cfa.reg = sp if fp used
1501 cfa.offset += {+/- <const_int>, cfa_temp.offset} if cfa.reg==sp
1502 cfa_store.offset += {+/- <const_int>, cfa_temp.offset}
1503 if cfa_store.reg==sp
1504
1505 Rule 3:
1506 (set fp ({minus,plus,losum} <reg>:cfa.reg <const_int>))
1507 effects: cfa.reg = fp
1508 cfa_offset += +/- <const_int>
1509
1510 Rule 4:
1511 (set <reg1> ({plus,losum} <reg2>:cfa.reg <const_int>))
1512 constraints: <reg1> != fp
1513 <reg1> != sp
1514 effects: cfa.reg = <reg1>
1515 cfa_temp.reg = <reg1>
1516 cfa_temp.offset = cfa.offset
1517
1518 Rule 5:
1519 (set <reg1> (plus <reg2>:cfa_temp.reg sp:cfa.reg))
1520 constraints: <reg1> != fp
1521 <reg1> != sp
1522 effects: cfa_store.reg = <reg1>
1523 cfa_store.offset = cfa.offset - cfa_temp.offset
1524
1525 Rule 6:
1526 (set <reg> <const_int>)
1527 effects: cfa_temp.reg = <reg>
1528 cfa_temp.offset = <const_int>
1529
1530 Rule 7:
1531 (set <reg1>:cfa_temp.reg (ior <reg2>:cfa_temp.reg <const_int>))
1532 effects: cfa_temp.reg = <reg1>
1533 cfa_temp.offset |= <const_int>
1534
1535 Rule 8:
1536 (set <reg> (high <exp>))
1537 effects: none
1538
1539 Rule 9:
1540 (set <reg> (lo_sum <exp> <const_int>))
1541 effects: cfa_temp.reg = <reg>
1542 cfa_temp.offset = <const_int>
1543
1544 Rule 10:
1545 (set (mem ({pre,post}_modify sp:cfa_store (???? <reg1> <const_int>))) <reg2>)
1546 effects: cfa_store.offset -= <const_int>
1547 cfa.offset = cfa_store.offset if cfa.reg == sp
1548 cfa.reg = sp
1549 cfa.base_offset = -cfa_store.offset
1550
1551 Rule 11:
1552 (set (mem ({pre_inc,pre_dec,post_dec} sp:cfa_store.reg)) <reg>)
1553 effects: cfa_store.offset += -/+ mode_size(mem)
1554 cfa.offset = cfa_store.offset if cfa.reg == sp
1555 cfa.reg = sp
1556 cfa.base_offset = -cfa_store.offset
1557
1558 Rule 12:
1559 (set (mem ({minus,plus,losum} <reg1>:{cfa_store,cfa_temp} <const_int>))
1560
1561 <reg2>)
1562 effects: cfa.reg = <reg1>
1563 cfa.base_offset = -/+ <const_int> - {cfa_store,cfa_temp}.offset
1564
1565 Rule 13:
1566 (set (mem <reg1>:{cfa_store,cfa_temp}) <reg2>)
1567 effects: cfa.reg = <reg1>
1568 cfa.base_offset = -{cfa_store,cfa_temp}.offset
1569
1570 Rule 14:
1571 (set (mem (post_inc <reg1>:cfa_temp <const_int>)) <reg2>)
1572 effects: cfa.reg = <reg1>
1573 cfa.base_offset = -cfa_temp.offset
1574 cfa_temp.offset -= mode_size(mem)
1575
1576 Rule 15:
1577 (set <reg> {unspec, unspec_volatile})
1578 effects: target-dependent
1579
1580 Rule 16:
1581 (set sp (and: sp <const_int>))
1582 constraints: cfa_store.reg == sp
1583 effects: cfun->fde.stack_realign = 1
1584 cfa_store.offset = 0
1585 fde->drap_reg = cfa.reg if cfa.reg != sp and cfa.reg != fp
1586
1587 Rule 17:
1588 (set (mem ({pre_inc, pre_dec} sp)) (mem (plus (cfa.reg) (const_int))))
1589 effects: cfa_store.offset += -/+ mode_size(mem)
1590
1591 Rule 18:
1592 (set (mem ({pre_inc, pre_dec} sp)) fp)
1593 constraints: fde->stack_realign == 1
1594 effects: cfa_store.offset = 0
1595 cfa.reg != HARD_FRAME_POINTER_REGNUM
1596
1597 Rule 19:
1598 (set (mem ({pre_inc, pre_dec} sp)) cfa.reg)
1599 constraints: fde->stack_realign == 1
1600 && cfa.offset == 0
1601 && cfa.indirect == 0
1602 && cfa.reg != HARD_FRAME_POINTER_REGNUM
1603 effects: Use DW_CFA_def_cfa_expression to define cfa
1604 cfa.reg == fde->drap_reg */
1605
1606 static void
1607 dwarf2out_frame_debug_expr (rtx expr)
1608 {
1609 dw_cfa_location cfa = cur_row->cfa;
1610 rtx src, dest, span;
1611 HOST_WIDE_INT offset;
1612 dw_fde_ref fde;
1613
1614 /* If RTX_FRAME_RELATED_P is set on a PARALLEL, process each member of
1615 the PARALLEL independently. The first element is always processed if
1616 it is a SET. This is for backward compatibility. Other elements
1617 are processed only if they are SETs and the RTX_FRAME_RELATED_P
1618 flag is set in them. */
1619 if (GET_CODE (expr) == PARALLEL || GET_CODE (expr) == SEQUENCE)
1620 {
1621 int par_index;
1622 int limit = XVECLEN (expr, 0);
1623 rtx elem;
1624
1625 /* PARALLELs have strict read-modify-write semantics, so we
1626 ought to evaluate every rvalue before changing any lvalue.
1627 It's cumbersome to do that in general, but there's an
1628 easy approximation that is enough for all current users:
1629 handle register saves before register assignments. */
1630 if (GET_CODE (expr) == PARALLEL)
1631 for (par_index = 0; par_index < limit; par_index++)
1632 {
1633 elem = XVECEXP (expr, 0, par_index);
1634 if (GET_CODE (elem) == SET
1635 && MEM_P (SET_DEST (elem))
1636 && (RTX_FRAME_RELATED_P (elem) || par_index == 0))
1637 dwarf2out_frame_debug_expr (elem);
1638 }
1639
1640 for (par_index = 0; par_index < limit; par_index++)
1641 {
1642 elem = XVECEXP (expr, 0, par_index);
1643 if (GET_CODE (elem) == SET
1644 && (!MEM_P (SET_DEST (elem)) || GET_CODE (expr) == SEQUENCE)
1645 && (RTX_FRAME_RELATED_P (elem) || par_index == 0))
1646 dwarf2out_frame_debug_expr (elem);
1647 else if (GET_CODE (elem) == SET
1648 && par_index != 0
1649 && !RTX_FRAME_RELATED_P (elem))
1650 {
1651 /* Stack adjustment combining might combine some post-prologue
1652 stack adjustment into a prologue stack adjustment. */
1653 HOST_WIDE_INT offset
1654 = stack_adjust_offset (elem, queued_args_size, 0);
1655
1656 if (offset != 0)
1657 dwarf2out_stack_adjust (offset);
1658 }
1659 }
1660 return;
1661 }
1662
1663 gcc_assert (GET_CODE (expr) == SET);
1664
1665 src = SET_SRC (expr);
1666 dest = SET_DEST (expr);
1667
1668 if (REG_P (src))
1669 {
1670 rtx rsi = reg_saved_in (src);
1671 if (rsi)
1672 src = rsi;
1673 }
1674
1675 fde = cfun->fde;
1676
1677 switch (GET_CODE (dest))
1678 {
1679 case REG:
1680 switch (GET_CODE (src))
1681 {
1682 /* Setting FP from SP. */
1683 case REG:
1684 if (cfa.reg == dwf_regno (src))
1685 {
1686 /* Rule 1 */
1687 /* Update the CFA rule wrt SP or FP. Make sure src is
1688 relative to the current CFA register.
1689
1690 We used to require that dest be either SP or FP, but the
1691 ARM copies SP to a temporary register, and from there to
1692 FP. So we just rely on the backends to only set
1693 RTX_FRAME_RELATED_P on appropriate insns. */
1694 cfa.reg = dwf_regno (dest);
1695 cur_trace->cfa_temp.reg = cfa.reg;
1696 cur_trace->cfa_temp.offset = cfa.offset;
1697 }
1698 else
1699 {
1700 /* Saving a register in a register. */
1701 gcc_assert (!fixed_regs [REGNO (dest)]
1702 /* For the SPARC and its register window. */
1703 || (dwf_regno (src) == DWARF_FRAME_RETURN_COLUMN));
1704
1705 /* After stack is aligned, we can only save SP in FP
1706 if drap register is used. In this case, we have
1707 to restore stack pointer with the CFA value and we
1708 don't generate this DWARF information. */
1709 if (fde
1710 && fde->stack_realign
1711 && REGNO (src) == STACK_POINTER_REGNUM)
1712 gcc_assert (REGNO (dest) == HARD_FRAME_POINTER_REGNUM
1713 && fde->drap_reg != INVALID_REGNUM
1714 && cfa.reg != dwf_regno (src));
1715 else
1716 queue_reg_save (src, dest, 0);
1717 }
1718 break;
1719
1720 case PLUS:
1721 case MINUS:
1722 case LO_SUM:
1723 if (dest == stack_pointer_rtx)
1724 {
1725 /* Rule 2 */
1726 /* Adjusting SP. */
1727 switch (GET_CODE (XEXP (src, 1)))
1728 {
1729 case CONST_INT:
1730 offset = INTVAL (XEXP (src, 1));
1731 break;
1732 case REG:
1733 gcc_assert (dwf_regno (XEXP (src, 1))
1734 == cur_trace->cfa_temp.reg);
1735 offset = cur_trace->cfa_temp.offset;
1736 break;
1737 default:
1738 gcc_unreachable ();
1739 }
1740
1741 if (XEXP (src, 0) == hard_frame_pointer_rtx)
1742 {
1743 /* Restoring SP from FP in the epilogue. */
1744 gcc_assert (cfa.reg == dw_frame_pointer_regnum);
1745 cfa.reg = dw_stack_pointer_regnum;
1746 }
1747 else if (GET_CODE (src) == LO_SUM)
1748 /* Assume we've set the source reg of the LO_SUM from sp. */
1749 ;
1750 else
1751 gcc_assert (XEXP (src, 0) == stack_pointer_rtx);
1752
1753 if (GET_CODE (src) != MINUS)
1754 offset = -offset;
1755 if (cfa.reg == dw_stack_pointer_regnum)
1756 cfa.offset += offset;
1757 if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum)
1758 cur_trace->cfa_store.offset += offset;
1759 }
1760 else if (dest == hard_frame_pointer_rtx)
1761 {
1762 /* Rule 3 */
1763 /* Either setting the FP from an offset of the SP,
1764 or adjusting the FP */
1765 gcc_assert (frame_pointer_needed);
1766
1767 gcc_assert (REG_P (XEXP (src, 0))
1768 && dwf_regno (XEXP (src, 0)) == cfa.reg
1769 && CONST_INT_P (XEXP (src, 1)));
1770 offset = INTVAL (XEXP (src, 1));
1771 if (GET_CODE (src) != MINUS)
1772 offset = -offset;
1773 cfa.offset += offset;
1774 cfa.reg = dw_frame_pointer_regnum;
1775 }
1776 else
1777 {
1778 gcc_assert (GET_CODE (src) != MINUS);
1779
1780 /* Rule 4 */
1781 if (REG_P (XEXP (src, 0))
1782 && dwf_regno (XEXP (src, 0)) == cfa.reg
1783 && CONST_INT_P (XEXP (src, 1)))
1784 {
1785 /* Setting a temporary CFA register that will be copied
1786 into the FP later on. */
1787 offset = - INTVAL (XEXP (src, 1));
1788 cfa.offset += offset;
1789 cfa.reg = dwf_regno (dest);
1790 /* Or used to save regs to the stack. */
1791 cur_trace->cfa_temp.reg = cfa.reg;
1792 cur_trace->cfa_temp.offset = cfa.offset;
1793 }
1794
1795 /* Rule 5 */
1796 else if (REG_P (XEXP (src, 0))
1797 && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg
1798 && XEXP (src, 1) == stack_pointer_rtx)
1799 {
1800 /* Setting a scratch register that we will use instead
1801 of SP for saving registers to the stack. */
1802 gcc_assert (cfa.reg == dw_stack_pointer_regnum);
1803 cur_trace->cfa_store.reg = dwf_regno (dest);
1804 cur_trace->cfa_store.offset
1805 = cfa.offset - cur_trace->cfa_temp.offset;
1806 }
1807
1808 /* Rule 9 */
1809 else if (GET_CODE (src) == LO_SUM
1810 && CONST_INT_P (XEXP (src, 1)))
1811 {
1812 cur_trace->cfa_temp.reg = dwf_regno (dest);
1813 cur_trace->cfa_temp.offset = INTVAL (XEXP (src, 1));
1814 }
1815 else
1816 gcc_unreachable ();
1817 }
1818 break;
1819
1820 /* Rule 6 */
1821 case CONST_INT:
1822 cur_trace->cfa_temp.reg = dwf_regno (dest);
1823 cur_trace->cfa_temp.offset = INTVAL (src);
1824 break;
1825
1826 /* Rule 7 */
1827 case IOR:
1828 gcc_assert (REG_P (XEXP (src, 0))
1829 && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg
1830 && CONST_INT_P (XEXP (src, 1)));
1831
1832 cur_trace->cfa_temp.reg = dwf_regno (dest);
1833 cur_trace->cfa_temp.offset |= INTVAL (XEXP (src, 1));
1834 break;
1835
1836 /* Skip over HIGH, assuming it will be followed by a LO_SUM,
1837 which will fill in all of the bits. */
1838 /* Rule 8 */
1839 case HIGH:
1840 break;
1841
1842 /* Rule 15 */
1843 case UNSPEC:
1844 case UNSPEC_VOLATILE:
1845 /* All unspecs should be represented by REG_CFA_* notes. */
1846 gcc_unreachable ();
1847 return;
1848
1849 /* Rule 16 */
1850 case AND:
1851 /* If this AND operation happens on stack pointer in prologue,
1852 we assume the stack is realigned and we extract the
1853 alignment. */
1854 if (fde && XEXP (src, 0) == stack_pointer_rtx)
1855 {
1856 /* We interpret reg_save differently with stack_realign set.
1857 Thus we must flush whatever we have queued first. */
1858 dwarf2out_flush_queued_reg_saves ();
1859
1860 gcc_assert (cur_trace->cfa_store.reg
1861 == dwf_regno (XEXP (src, 0)));
1862 fde->stack_realign = 1;
1863 fde->stack_realignment = INTVAL (XEXP (src, 1));
1864 cur_trace->cfa_store.offset = 0;
1865
1866 if (cfa.reg != dw_stack_pointer_regnum
1867 && cfa.reg != dw_frame_pointer_regnum)
1868 fde->drap_reg = cfa.reg;
1869 }
1870 return;
1871
1872 default:
1873 gcc_unreachable ();
1874 }
1875
1876 def_cfa_1 (&cfa);
1877 break;
1878
1879 case MEM:
1880
1881 /* Saving a register to the stack. Make sure dest is relative to the
1882 CFA register. */
1883 switch (GET_CODE (XEXP (dest, 0)))
1884 {
1885 /* Rule 10 */
1886 /* With a push. */
1887 case PRE_MODIFY:
1888 case POST_MODIFY:
1889 /* We can't handle variable size modifications. */
1890 gcc_assert (GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1))
1891 == CONST_INT);
1892 offset = -INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1));
1893
1894 gcc_assert (REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
1895 && cur_trace->cfa_store.reg == dw_stack_pointer_regnum);
1896
1897 cur_trace->cfa_store.offset += offset;
1898 if (cfa.reg == dw_stack_pointer_regnum)
1899 cfa.offset = cur_trace->cfa_store.offset;
1900
1901 if (GET_CODE (XEXP (dest, 0)) == POST_MODIFY)
1902 offset -= cur_trace->cfa_store.offset;
1903 else
1904 offset = -cur_trace->cfa_store.offset;
1905 break;
1906
1907 /* Rule 11 */
1908 case PRE_INC:
1909 case PRE_DEC:
1910 case POST_DEC:
1911 offset = GET_MODE_SIZE (GET_MODE (dest));
1912 if (GET_CODE (XEXP (dest, 0)) == PRE_INC)
1913 offset = -offset;
1914
1915 gcc_assert ((REGNO (XEXP (XEXP (dest, 0), 0))
1916 == STACK_POINTER_REGNUM)
1917 && cur_trace->cfa_store.reg == dw_stack_pointer_regnum);
1918
1919 cur_trace->cfa_store.offset += offset;
1920
1921 /* Rule 18: If stack is aligned, we will use FP as a
1922 reference to represent the address of the stored
1923 regiser. */
1924 if (fde
1925 && fde->stack_realign
1926 && src == hard_frame_pointer_rtx)
1927 {
1928 gcc_assert (cfa.reg != dw_frame_pointer_regnum);
1929 cur_trace->cfa_store.offset = 0;
1930 }
1931
1932 if (cfa.reg == dw_stack_pointer_regnum)
1933 cfa.offset = cur_trace->cfa_store.offset;
1934
1935 if (GET_CODE (XEXP (dest, 0)) == POST_DEC)
1936 offset += -cur_trace->cfa_store.offset;
1937 else
1938 offset = -cur_trace->cfa_store.offset;
1939 break;
1940
1941 /* Rule 12 */
1942 /* With an offset. */
1943 case PLUS:
1944 case MINUS:
1945 case LO_SUM:
1946 {
1947 unsigned int regno;
1948
1949 gcc_assert (CONST_INT_P (XEXP (XEXP (dest, 0), 1))
1950 && REG_P (XEXP (XEXP (dest, 0), 0)));
1951 offset = INTVAL (XEXP (XEXP (dest, 0), 1));
1952 if (GET_CODE (XEXP (dest, 0)) == MINUS)
1953 offset = -offset;
1954
1955 regno = dwf_regno (XEXP (XEXP (dest, 0), 0));
1956
1957 if (cfa.reg == regno)
1958 offset -= cfa.offset;
1959 else if (cur_trace->cfa_store.reg == regno)
1960 offset -= cur_trace->cfa_store.offset;
1961 else
1962 {
1963 gcc_assert (cur_trace->cfa_temp.reg == regno);
1964 offset -= cur_trace->cfa_temp.offset;
1965 }
1966 }
1967 break;
1968
1969 /* Rule 13 */
1970 /* Without an offset. */
1971 case REG:
1972 {
1973 unsigned int regno = dwf_regno (XEXP (dest, 0));
1974
1975 if (cfa.reg == regno)
1976 offset = -cfa.offset;
1977 else if (cur_trace->cfa_store.reg == regno)
1978 offset = -cur_trace->cfa_store.offset;
1979 else
1980 {
1981 gcc_assert (cur_trace->cfa_temp.reg == regno);
1982 offset = -cur_trace->cfa_temp.offset;
1983 }
1984 }
1985 break;
1986
1987 /* Rule 14 */
1988 case POST_INC:
1989 gcc_assert (cur_trace->cfa_temp.reg
1990 == dwf_regno (XEXP (XEXP (dest, 0), 0)));
1991 offset = -cur_trace->cfa_temp.offset;
1992 cur_trace->cfa_temp.offset -= GET_MODE_SIZE (GET_MODE (dest));
1993 break;
1994
1995 default:
1996 gcc_unreachable ();
1997 }
1998
1999 /* Rule 17 */
2000 /* If the source operand of this MEM operation is a memory,
2001 we only care how much stack grew. */
2002 if (MEM_P (src))
2003 break;
2004
2005 if (REG_P (src)
2006 && REGNO (src) != STACK_POINTER_REGNUM
2007 && REGNO (src) != HARD_FRAME_POINTER_REGNUM
2008 && dwf_regno (src) == cfa.reg)
2009 {
2010 /* We're storing the current CFA reg into the stack. */
2011
2012 if (cfa.offset == 0)
2013 {
2014 /* Rule 19 */
2015 /* If stack is aligned, putting CFA reg into stack means
2016 we can no longer use reg + offset to represent CFA.
2017 Here we use DW_CFA_def_cfa_expression instead. The
2018 result of this expression equals to the original CFA
2019 value. */
2020 if (fde
2021 && fde->stack_realign
2022 && cfa.indirect == 0
2023 && cfa.reg != dw_frame_pointer_regnum)
2024 {
2025 dw_cfa_location cfa_exp;
2026
2027 gcc_assert (fde->drap_reg == cfa.reg);
2028
2029 cfa_exp.indirect = 1;
2030 cfa_exp.reg = dw_frame_pointer_regnum;
2031 cfa_exp.base_offset = offset;
2032 cfa_exp.offset = 0;
2033
2034 fde->drap_reg_saved = 1;
2035
2036 def_cfa_1 (&cfa_exp);
2037 break;
2038 }
2039
2040 /* If the source register is exactly the CFA, assume
2041 we're saving SP like any other register; this happens
2042 on the ARM. */
2043 def_cfa_1 (&cfa);
2044 queue_reg_save (stack_pointer_rtx, NULL_RTX, offset);
2045 break;
2046 }
2047 else
2048 {
2049 /* Otherwise, we'll need to look in the stack to
2050 calculate the CFA. */
2051 rtx x = XEXP (dest, 0);
2052
2053 if (!REG_P (x))
2054 x = XEXP (x, 0);
2055 gcc_assert (REG_P (x));
2056
2057 cfa.reg = dwf_regno (x);
2058 cfa.base_offset = offset;
2059 cfa.indirect = 1;
2060 def_cfa_1 (&cfa);
2061 break;
2062 }
2063 }
2064
2065 def_cfa_1 (&cfa);
2066
2067 span = NULL;
2068 if (REG_P (src))
2069 span = targetm.dwarf_register_span (src);
2070 if (!span)
2071 queue_reg_save (src, NULL_RTX, offset);
2072 else
2073 {
2074 /* We have a PARALLEL describing where the contents of SRC live.
2075 Queue register saves for each piece of the PARALLEL. */
2076 int par_index;
2077 int limit;
2078 HOST_WIDE_INT span_offset = offset;
2079
2080 gcc_assert (GET_CODE (span) == PARALLEL);
2081
2082 limit = XVECLEN (span, 0);
2083 for (par_index = 0; par_index < limit; par_index++)
2084 {
2085 rtx elem = XVECEXP (span, 0, par_index);
2086 queue_reg_save (elem, NULL_RTX, span_offset);
2087 span_offset += GET_MODE_SIZE (GET_MODE (elem));
2088 }
2089 }
2090 break;
2091
2092 default:
2093 gcc_unreachable ();
2094 }
2095 }
2096
2097 /* Record call frame debugging information for INSN, which either
2098 sets SP or FP (adjusting how we calculate the frame address) or saves a
2099 register to the stack. If INSN is NULL_RTX, initialize our state.
2100
2101 If AFTER_P is false, we're being called before the insn is emitted,
2102 otherwise after. Call instructions get invoked twice. */
2103
2104 static void
2105 dwarf2out_frame_debug (rtx insn, bool after_p)
2106 {
2107 rtx note, n;
2108 bool handled_one = false;
2109 bool need_flush = false;
2110
2111 if (!NONJUMP_INSN_P (insn) || clobbers_queued_reg_save (insn))
2112 dwarf2out_flush_queued_reg_saves ();
2113
2114 if (!RTX_FRAME_RELATED_P (insn))
2115 {
2116 /* ??? This should be done unconditionally since stack adjustments
2117 matter if the stack pointer is not the CFA register anymore but
2118 is still used to save registers. */
2119 if (!ACCUMULATE_OUTGOING_ARGS)
2120 dwarf2out_notice_stack_adjust (insn, after_p);
2121 return;
2122 }
2123
2124 any_cfis_emitted = false;
2125
2126 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
2127 switch (REG_NOTE_KIND (note))
2128 {
2129 case REG_FRAME_RELATED_EXPR:
2130 insn = XEXP (note, 0);
2131 goto do_frame_expr;
2132
2133 case REG_CFA_DEF_CFA:
2134 dwarf2out_frame_debug_def_cfa (XEXP (note, 0));
2135 handled_one = true;
2136 break;
2137
2138 case REG_CFA_ADJUST_CFA:
2139 n = XEXP (note, 0);
2140 if (n == NULL)
2141 {
2142 n = PATTERN (insn);
2143 if (GET_CODE (n) == PARALLEL)
2144 n = XVECEXP (n, 0, 0);
2145 }
2146 dwarf2out_frame_debug_adjust_cfa (n);
2147 handled_one = true;
2148 break;
2149
2150 case REG_CFA_OFFSET:
2151 n = XEXP (note, 0);
2152 if (n == NULL)
2153 n = single_set (insn);
2154 dwarf2out_frame_debug_cfa_offset (n);
2155 handled_one = true;
2156 break;
2157
2158 case REG_CFA_REGISTER:
2159 n = XEXP (note, 0);
2160 if (n == NULL)
2161 {
2162 n = PATTERN (insn);
2163 if (GET_CODE (n) == PARALLEL)
2164 n = XVECEXP (n, 0, 0);
2165 }
2166 dwarf2out_frame_debug_cfa_register (n);
2167 handled_one = true;
2168 break;
2169
2170 case REG_CFA_EXPRESSION:
2171 n = XEXP (note, 0);
2172 if (n == NULL)
2173 n = single_set (insn);
2174 dwarf2out_frame_debug_cfa_expression (n);
2175 handled_one = true;
2176 break;
2177
2178 case REG_CFA_RESTORE:
2179 n = XEXP (note, 0);
2180 if (n == NULL)
2181 {
2182 n = PATTERN (insn);
2183 if (GET_CODE (n) == PARALLEL)
2184 n = XVECEXP (n, 0, 0);
2185 n = XEXP (n, 0);
2186 }
2187 dwarf2out_frame_debug_cfa_restore (n);
2188 handled_one = true;
2189 break;
2190
2191 case REG_CFA_SET_VDRAP:
2192 n = XEXP (note, 0);
2193 if (REG_P (n))
2194 {
2195 dw_fde_ref fde = cfun->fde;
2196 if (fde)
2197 {
2198 gcc_assert (fde->vdrap_reg == INVALID_REGNUM);
2199 if (REG_P (n))
2200 fde->vdrap_reg = dwf_regno (n);
2201 }
2202 }
2203 handled_one = true;
2204 break;
2205
2206 case REG_CFA_WINDOW_SAVE:
2207 dwarf2out_frame_debug_cfa_window_save ();
2208 handled_one = true;
2209 break;
2210
2211 case REG_CFA_FLUSH_QUEUE:
2212 /* The actual flush happens below. */
2213 need_flush = true;
2214 handled_one = true;
2215 break;
2216
2217 default:
2218 break;
2219 }
2220
2221 if (handled_one)
2222 {
2223 /* Minimize the number of advances by emitting the entire queue
2224 once anything is emitted. */
2225 need_flush |= any_cfis_emitted;
2226 }
2227 else
2228 {
2229 insn = PATTERN (insn);
2230 do_frame_expr:
2231 dwarf2out_frame_debug_expr (insn);
2232
2233 /* Check again. A parallel can save and update the same register.
2234 We could probably check just once, here, but this is safer than
2235 removing the check at the start of the function. */
2236 if (any_cfis_emitted || clobbers_queued_reg_save (insn))
2237 need_flush = true;
2238 }
2239
2240 if (need_flush)
2241 dwarf2out_flush_queued_reg_saves ();
2242 }
2243
2244 /* Emit CFI info to change the state from OLD_ROW to NEW_ROW. */
2245
2246 static void
2247 change_cfi_row (dw_cfi_row *old_row, dw_cfi_row *new_row)
2248 {
2249 size_t i, n_old, n_new, n_max;
2250 dw_cfi_ref cfi;
2251
2252 if (new_row->cfa_cfi && !cfi_equal_p (old_row->cfa_cfi, new_row->cfa_cfi))
2253 add_cfi (new_row->cfa_cfi);
2254 else
2255 {
2256 cfi = def_cfa_0 (&old_row->cfa, &new_row->cfa);
2257 if (cfi)
2258 add_cfi (cfi);
2259 }
2260
2261 if (old_row->args_size != new_row->args_size)
2262 add_cfi_args_size (new_row->args_size);
2263
2264 n_old = VEC_length (dw_cfi_ref, old_row->reg_save);
2265 n_new = VEC_length (dw_cfi_ref, new_row->reg_save);
2266 n_max = MAX (n_old, n_new);
2267
2268 for (i = 0; i < n_max; ++i)
2269 {
2270 dw_cfi_ref r_old = NULL, r_new = NULL;
2271
2272 if (i < n_old)
2273 r_old = VEC_index (dw_cfi_ref, old_row->reg_save, i);
2274 if (i < n_new)
2275 r_new = VEC_index (dw_cfi_ref, new_row->reg_save, i);
2276
2277 if (r_old == r_new)
2278 ;
2279 else if (r_new == NULL)
2280 add_cfi_restore (i);
2281 else if (!cfi_equal_p (r_old, r_new))
2282 add_cfi (r_new);
2283 }
2284 }
2285
2286 /* Examine CFI and return true if a cfi label and set_loc is needed
2287 beforehand. Even when generating CFI assembler instructions, we
2288 still have to add the cfi to the list so that lookup_cfa_1 works
2289 later on. When -g2 and above we even need to force emitting of
2290 CFI labels and add to list a DW_CFA_set_loc for convert_cfa_to_fb_loc_list
2291 purposes. If we're generating DWARF3 output we use DW_OP_call_frame_cfa
2292 and so don't use convert_cfa_to_fb_loc_list. */
2293
2294 static bool
2295 cfi_label_required_p (dw_cfi_ref cfi)
2296 {
2297 if (!dwarf2out_do_cfi_asm ())
2298 return true;
2299
2300 if (dwarf_version == 2
2301 && debug_info_level > DINFO_LEVEL_TERSE
2302 && (write_symbols == DWARF2_DEBUG
2303 || write_symbols == VMS_AND_DWARF2_DEBUG))
2304 {
2305 switch (cfi->dw_cfi_opc)
2306 {
2307 case DW_CFA_def_cfa_offset:
2308 case DW_CFA_def_cfa_offset_sf:
2309 case DW_CFA_def_cfa_register:
2310 case DW_CFA_def_cfa:
2311 case DW_CFA_def_cfa_sf:
2312 case DW_CFA_def_cfa_expression:
2313 case DW_CFA_restore_state:
2314 return true;
2315 default:
2316 return false;
2317 }
2318 }
2319 return false;
2320 }
2321
2322 /* Walk the function, looking for NOTE_INSN_CFI notes. Add the CFIs to the
2323 function's FDE, adding CFI labels and set_loc/advance_loc opcodes as
2324 necessary. */
2325 static void
2326 add_cfis_to_fde (void)
2327 {
2328 dw_fde_ref fde = cfun->fde;
2329 rtx insn, next;
2330 /* We always start with a function_begin label. */
2331 bool first = false;
2332
2333 for (insn = get_insns (); insn; insn = next)
2334 {
2335 next = NEXT_INSN (insn);
2336
2337 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
2338 {
2339 fde->dw_fde_switch_cfi_index
2340 = VEC_length (dw_cfi_ref, fde->dw_fde_cfi);
2341 /* Don't attempt to advance_loc4 between labels
2342 in different sections. */
2343 first = true;
2344 }
2345
2346 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI)
2347 {
2348 bool required = cfi_label_required_p (NOTE_CFI (insn));
2349 while (next && NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_CFI)
2350 {
2351 required |= cfi_label_required_p (NOTE_CFI (next));
2352 next = NEXT_INSN (next);
2353 }
2354 if (required)
2355 {
2356 int num = dwarf2out_cfi_label_num;
2357 const char *label = dwarf2out_cfi_label ();
2358 dw_cfi_ref xcfi;
2359 rtx tmp;
2360
2361 /* Set the location counter to the new label. */
2362 xcfi = new_cfi ();
2363 xcfi->dw_cfi_opc = (first ? DW_CFA_set_loc
2364 : DW_CFA_advance_loc4);
2365 xcfi->dw_cfi_oprnd1.dw_cfi_addr = label;
2366 VEC_safe_push (dw_cfi_ref, gc, fde->dw_fde_cfi, xcfi);
2367
2368 tmp = emit_note_before (NOTE_INSN_CFI_LABEL, insn);
2369 NOTE_LABEL_NUMBER (tmp) = num;
2370 }
2371
2372 do
2373 {
2374 VEC_safe_push (dw_cfi_ref, gc, fde->dw_fde_cfi, NOTE_CFI (insn));
2375 insn = NEXT_INSN (insn);
2376 }
2377 while (insn != next);
2378 first = false;
2379 }
2380 }
2381 }
2382
2383 /* If LABEL is the start of a trace, then initialize the state of that
2384 trace from CUR_TRACE and CUR_ROW. */
2385
2386 static void
2387 maybe_record_trace_start (rtx start, rtx origin, bool abnormal)
2388 {
2389 dw_trace_info *ti;
2390
2391 /* Sync queued data before propagating to a destination,
2392 lest we propagate out-of-date data. */
2393 dwarf2out_flush_queued_reg_saves ();
2394 dwarf2out_args_size (queued_args_size);
2395
2396 ti = get_trace_info (start);
2397 gcc_assert (ti != NULL);
2398
2399 if (dump_file)
2400 {
2401 fprintf (dump_file, " saw edge from trace %u to %u (via %s %d)\n",
2402 cur_trace->id, ti->id,
2403 (origin ? rtx_name[(int) GET_CODE (origin)] : "fallthru"),
2404 (origin ? INSN_UID (origin) : 0));
2405 }
2406
2407 if (ti->beg_row == NULL)
2408 {
2409 /* This is the first time we've encountered this trace. Propagate
2410 state across the edge and push the trace onto the work list. */
2411 ti->beg_row = copy_cfi_row (cur_row);
2412 /* On all abnormal edges, especially EH and non-local-goto, we take
2413 care to free the pushed arguments. */
2414 if (abnormal)
2415 ti->beg_row->args_size = 0;
2416
2417 ti->cfa_store = cur_trace->cfa_store;
2418 ti->cfa_temp = cur_trace->cfa_temp;
2419 ti->regs_saved_in_regs = VEC_copy (reg_saved_in_data, heap,
2420 cur_trace->regs_saved_in_regs);
2421
2422 VEC_safe_push (dw_trace_info_ref, heap, trace_work_list, ti);
2423
2424 if (dump_file)
2425 fprintf (dump_file, "\tpush trace %u to worklist\n", ti->id);
2426 }
2427 else
2428 {
2429 /* We ought to have the same state incoming to a given trace no
2430 matter how we arrive at the trace. Anything else means we've
2431 got some kind of optimization error. */
2432 gcc_checking_assert (cfi_row_equal_p (cur_row, ti->beg_row));
2433 }
2434 }
2435
2436 /* Propagate CUR_TRACE state to the destinations implied by INSN. */
2437 /* ??? Sadly, this is in large part a duplicate of make_edges. */
2438
2439 static void
2440 create_trace_edges (rtx insn)
2441 {
2442 rtx tmp, lab;
2443 int i, n;
2444
2445 if (JUMP_P (insn))
2446 {
2447 if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
2448 ;
2449 else if (tablejump_p (insn, NULL, &tmp))
2450 {
2451 rtvec vec;
2452
2453 tmp = PATTERN (tmp);
2454 vec = XVEC (tmp, GET_CODE (tmp) == ADDR_DIFF_VEC);
2455
2456 n = GET_NUM_ELEM (vec);
2457 for (i = 0; i < n; ++i)
2458 {
2459 lab = XEXP (RTVEC_ELT (vec, i), 0);
2460 maybe_record_trace_start (lab, insn, false);
2461 }
2462 }
2463 else if (computed_jump_p (insn))
2464 {
2465 for (lab = forced_labels; lab; lab = XEXP (lab, 1))
2466 maybe_record_trace_start (XEXP (lab, 0), insn, true);
2467 }
2468 else if (returnjump_p (insn))
2469 ;
2470 else if ((tmp = extract_asm_operands (PATTERN (insn))) != NULL)
2471 {
2472 n = ASM_OPERANDS_LABEL_LENGTH (tmp);
2473 for (i = 0; i < n; ++i)
2474 {
2475 lab = XEXP (ASM_OPERANDS_LABEL (tmp, i), 0);
2476 maybe_record_trace_start (lab, insn, true);
2477 }
2478 }
2479 else
2480 {
2481 lab = JUMP_LABEL (insn);
2482 gcc_assert (lab != NULL);
2483 maybe_record_trace_start (lab, insn, false);
2484 }
2485 }
2486 else if (CALL_P (insn))
2487 {
2488 /* Sibling calls don't have edges inside this function. */
2489 if (SIBLING_CALL_P (insn))
2490 return;
2491
2492 /* Process non-local goto edges. */
2493 if (can_nonlocal_goto (insn))
2494 for (lab = nonlocal_goto_handler_labels; lab; lab = XEXP (lab, 1))
2495 maybe_record_trace_start (XEXP (lab, 0), insn, true);
2496 }
2497 else if (GET_CODE (PATTERN (insn)) == SEQUENCE)
2498 {
2499 rtx seq = PATTERN (insn);
2500 int i, n = XVECLEN (seq, 0);
2501 for (i = 0; i < n; ++i)
2502 create_trace_edges (XVECEXP (seq, 0, i));
2503 return;
2504 }
2505
2506 /* Process EH edges. */
2507 if (CALL_P (insn) || cfun->can_throw_non_call_exceptions)
2508 {
2509 eh_landing_pad lp = get_eh_landing_pad_from_rtx (insn);
2510 if (lp)
2511 maybe_record_trace_start (lp->landing_pad, insn, true);
2512 }
2513 }
2514
2515 /* Scan the trace beginning at INSN and create the CFI notes for the
2516 instructions therein. */
2517
2518 static void
2519 scan_trace (dw_trace_info *trace)
2520 {
2521 rtx insn = trace->head;
2522
2523 if (dump_file)
2524 fprintf (dump_file, "Processing trace %u : start at %s %d\n",
2525 trace->id, rtx_name[(int) GET_CODE (insn)],
2526 INSN_UID (insn));
2527
2528 trace->end_row = copy_cfi_row (trace->beg_row);
2529
2530 cur_trace = trace;
2531 cur_row = trace->end_row;
2532 queued_args_size = cur_row->args_size;
2533
2534 for (insn = NEXT_INSN (insn); insn ; insn = NEXT_INSN (insn))
2535 {
2536 rtx pat;
2537
2538 add_cfi_insn = PREV_INSN (insn);
2539
2540 /* Notice the end of a trace. */
2541 if (BARRIER_P (insn) || save_point_p (insn))
2542 {
2543 dwarf2out_flush_queued_reg_saves ();
2544 dwarf2out_args_size (queued_args_size);
2545
2546 /* Propagate across fallthru edges. */
2547 if (!BARRIER_P (insn))
2548 maybe_record_trace_start (insn, NULL, false);
2549 break;
2550 }
2551
2552 if (DEBUG_INSN_P (insn) || !inside_basic_block_p (insn))
2553 continue;
2554
2555 pat = PATTERN (insn);
2556 if (asm_noperands (pat) >= 0)
2557 {
2558 dwarf2out_frame_debug (insn, false);
2559 add_cfi_insn = insn;
2560 }
2561 else
2562 {
2563 if (GET_CODE (pat) == SEQUENCE)
2564 {
2565 int i, n = XVECLEN (pat, 0);
2566 for (i = 1; i < n; ++i)
2567 dwarf2out_frame_debug (XVECEXP (pat, 0, i), false);
2568 }
2569
2570 if (CALL_P (insn))
2571 dwarf2out_frame_debug (insn, false);
2572 else if (find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL)
2573 || (cfun->can_throw_non_call_exceptions
2574 && can_throw_internal (insn)))
2575 dwarf2out_flush_queued_reg_saves ();
2576
2577 /* Do not separate tablejump insns from their ADDR_DIFF_VEC.
2578 Putting the note after the VEC should be ok. */
2579 if (!tablejump_p (insn, NULL, &add_cfi_insn))
2580 add_cfi_insn = insn;
2581
2582 dwarf2out_frame_debug (insn, true);
2583 }
2584
2585 /* Note that a test for control_flow_insn_p does exactly the
2586 same tests as are done to actually create the edges. So
2587 always call the routine and let it not create edges for
2588 non-control-flow insns. */
2589 create_trace_edges (insn);
2590 }
2591
2592 add_cfi_insn = NULL;
2593 cur_row = NULL;
2594 cur_trace = NULL;
2595 }
2596
2597 /* Scan the function and create the initial set of CFI notes. */
2598
2599 static void
2600 create_cfi_notes (void)
2601 {
2602 dw_trace_info *ti;
2603
2604 gcc_checking_assert (queued_reg_saves == NULL);
2605 gcc_checking_assert (trace_work_list == NULL);
2606
2607 /* Always begin at the entry trace. */
2608 ti = VEC_index (dw_trace_info, trace_info, 0);
2609 scan_trace (ti);
2610
2611 while (!VEC_empty (dw_trace_info_ref, trace_work_list))
2612 {
2613 ti = VEC_pop (dw_trace_info_ref, trace_work_list);
2614 scan_trace (ti);
2615 }
2616
2617 VEC_free (queued_reg_save, heap, queued_reg_saves);
2618 VEC_free (dw_trace_info_ref, heap, trace_work_list);
2619 }
2620
2621 /* Return the insn before the first NOTE_INSN_CFI after START. */
2622
2623 static rtx
2624 before_next_cfi_note (rtx start)
2625 {
2626 rtx prev = start;
2627 while (start)
2628 {
2629 if (NOTE_P (start) && NOTE_KIND (start) == NOTE_INSN_CFI)
2630 return prev;
2631 prev = start;
2632 start = NEXT_INSN (start);
2633 }
2634 gcc_unreachable ();
2635 }
2636
2637 /* Insert CFI notes between traces to properly change state between them. */
2638
2639 static void
2640 connect_traces (void)
2641 {
2642 unsigned i, n = VEC_length (dw_trace_info, trace_info);
2643 dw_trace_info *prev_ti, *ti;
2644
2645 /* ??? Ideally, we should have both queued and processed every trace.
2646 However the current representation of constant pools on various targets
2647 is indistinguishable from unreachable code. Assume for the moment that
2648 we can simply skip over such traces. */
2649 /* ??? Consider creating a DATA_INSN rtx code to indicate that
2650 these are not "real" instructions, and should not be considered.
2651 This could be generically useful for tablejump data as well. */
2652 /* Remove all unprocessed traces from the list. */
2653 for (i = n - 1; i > 0; --i)
2654 {
2655 ti = VEC_index (dw_trace_info, trace_info, i);
2656 if (ti->beg_row == NULL)
2657 {
2658 VEC_ordered_remove (dw_trace_info, trace_info, i);
2659 n -= 1;
2660 }
2661 else
2662 gcc_assert (ti->end_row != NULL);
2663 }
2664
2665 /* Work from the end back to the beginning. This lets us easily insert
2666 remember/restore_state notes in the correct order wrt other notes. */
2667 prev_ti = VEC_index (dw_trace_info, trace_info, n - 1);
2668 for (i = n - 1; i > 0; --i)
2669 {
2670 dw_cfi_row *old_row;
2671
2672 ti = prev_ti;
2673 prev_ti = VEC_index (dw_trace_info, trace_info, i - 1);
2674
2675 add_cfi_insn = ti->head;
2676
2677 /* In dwarf2out_switch_text_section, we'll begin a new FDE
2678 for the portion of the function in the alternate text
2679 section. The row state at the very beginning of that
2680 new FDE will be exactly the row state from the CIE. */
2681 if (ti->switch_sections)
2682 old_row = cie_cfi_row;
2683 else
2684 {
2685 old_row = prev_ti->end_row;
2686 /* If there's no change from the previous end state, fine. */
2687 if (cfi_row_equal_p (old_row, ti->beg_row))
2688 ;
2689 /* Otherwise check for the common case of sharing state with
2690 the beginning of an epilogue, but not the end. Insert
2691 remember/restore opcodes in that case. */
2692 else if (cfi_row_equal_p (prev_ti->beg_row, ti->beg_row))
2693 {
2694 dw_cfi_ref cfi;
2695
2696 /* Note that if we blindly insert the remember at the
2697 start of the trace, we can wind up increasing the
2698 size of the unwind info due to extra advance opcodes.
2699 Instead, put the remember immediately before the next
2700 state change. We know there must be one, because the
2701 state at the beginning and head of the trace differ. */
2702 add_cfi_insn = before_next_cfi_note (prev_ti->head);
2703 cfi = new_cfi ();
2704 cfi->dw_cfi_opc = DW_CFA_remember_state;
2705 add_cfi (cfi);
2706
2707 add_cfi_insn = ti->head;
2708 cfi = new_cfi ();
2709 cfi->dw_cfi_opc = DW_CFA_restore_state;
2710 add_cfi (cfi);
2711
2712 old_row = prev_ti->beg_row;
2713 }
2714 /* Otherwise, we'll simply change state from the previous end. */
2715 }
2716
2717 change_cfi_row (old_row, ti->beg_row);
2718
2719 if (dump_file && add_cfi_insn != ti->head)
2720 {
2721 rtx note;
2722
2723 fprintf (dump_file, "Fixup between trace %u and %u:\n",
2724 prev_ti->id, ti->id);
2725
2726 note = ti->head;
2727 do
2728 {
2729 note = NEXT_INSN (note);
2730 gcc_assert (NOTE_P (note) && NOTE_KIND (note) == NOTE_INSN_CFI);
2731 output_cfi_directive (dump_file, NOTE_CFI (note));
2732 }
2733 while (note != add_cfi_insn);
2734 }
2735 }
2736 }
2737
2738 /* Set up the pseudo-cfg of instruction traces, as described at the
2739 block comment at the top of the file. */
2740
2741 static void
2742 create_pseudo_cfg (void)
2743 {
2744 bool saw_barrier, switch_sections;
2745 dw_trace_info *ti;
2746 rtx insn;
2747 unsigned i;
2748
2749 /* The first trace begins at the start of the function,
2750 and begins with the CIE row state. */
2751 trace_info = VEC_alloc (dw_trace_info, heap, 16);
2752 ti = VEC_quick_push (dw_trace_info, trace_info, NULL);
2753
2754 memset (ti, 0, sizeof (*ti));
2755 ti->head = get_insns ();
2756 ti->beg_row = cie_cfi_row;
2757 ti->cfa_store = cie_cfi_row->cfa;
2758 ti->cfa_temp.reg = INVALID_REGNUM;
2759 if (cie_return_save)
2760 VEC_safe_push (reg_saved_in_data, heap,
2761 ti->regs_saved_in_regs, cie_return_save);
2762
2763 /* Walk all the insns, collecting start of trace locations. */
2764 saw_barrier = false;
2765 switch_sections = false;
2766 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2767 {
2768 if (BARRIER_P (insn))
2769 saw_barrier = true;
2770 else if (NOTE_P (insn)
2771 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
2772 {
2773 /* We should have just seen a barrier. */
2774 gcc_assert (saw_barrier);
2775 switch_sections = true;
2776 }
2777 /* Watch out for save_point notes between basic blocks.
2778 In particular, a note after a barrier. Do not record these,
2779 delaying trace creation until the label. */
2780 else if (save_point_p (insn)
2781 && (LABEL_P (insn) || !saw_barrier))
2782 {
2783 ti = VEC_safe_push (dw_trace_info, heap, trace_info, NULL);
2784 memset (ti, 0, sizeof (*ti));
2785 ti->head = insn;
2786 ti->switch_sections = switch_sections;
2787 ti->id = VEC_length (dw_trace_info, trace_info) - 1;
2788
2789 saw_barrier = false;
2790 switch_sections = false;
2791 }
2792 }
2793
2794 /* Create the trace index after we've finished building trace_info,
2795 avoiding stale pointer problems due to reallocation. */
2796 trace_index = htab_create (VEC_length (dw_trace_info, trace_info),
2797 dw_trace_info_hash, dw_trace_info_eq, NULL);
2798 FOR_EACH_VEC_ELT (dw_trace_info, trace_info, i, ti)
2799 {
2800 void **slot;
2801
2802 if (dump_file)
2803 fprintf (dump_file, "Creating trace %u : start at %s %d%s\n", i,
2804 rtx_name[(int) GET_CODE (ti->head)], INSN_UID (ti->head),
2805 ti->switch_sections ? " (section switch)" : "");
2806
2807 slot = htab_find_slot_with_hash (trace_index, ti,
2808 INSN_UID (ti->head), INSERT);
2809 gcc_assert (*slot == NULL);
2810 *slot = (void *) ti;
2811 }
2812 }
2813
2814 /* Record the initial position of the return address. RTL is
2815 INCOMING_RETURN_ADDR_RTX. */
2816
2817 static void
2818 initial_return_save (rtx rtl)
2819 {
2820 unsigned int reg = INVALID_REGNUM;
2821 HOST_WIDE_INT offset = 0;
2822
2823 switch (GET_CODE (rtl))
2824 {
2825 case REG:
2826 /* RA is in a register. */
2827 reg = dwf_regno (rtl);
2828 break;
2829
2830 case MEM:
2831 /* RA is on the stack. */
2832 rtl = XEXP (rtl, 0);
2833 switch (GET_CODE (rtl))
2834 {
2835 case REG:
2836 gcc_assert (REGNO (rtl) == STACK_POINTER_REGNUM);
2837 offset = 0;
2838 break;
2839
2840 case PLUS:
2841 gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM);
2842 offset = INTVAL (XEXP (rtl, 1));
2843 break;
2844
2845 case MINUS:
2846 gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM);
2847 offset = -INTVAL (XEXP (rtl, 1));
2848 break;
2849
2850 default:
2851 gcc_unreachable ();
2852 }
2853
2854 break;
2855
2856 case PLUS:
2857 /* The return address is at some offset from any value we can
2858 actually load. For instance, on the SPARC it is in %i7+8. Just
2859 ignore the offset for now; it doesn't matter for unwinding frames. */
2860 gcc_assert (CONST_INT_P (XEXP (rtl, 1)));
2861 initial_return_save (XEXP (rtl, 0));
2862 return;
2863
2864 default:
2865 gcc_unreachable ();
2866 }
2867
2868 if (reg != DWARF_FRAME_RETURN_COLUMN)
2869 {
2870 if (reg != INVALID_REGNUM)
2871 record_reg_saved_in_reg (rtl, pc_rtx);
2872 reg_save (DWARF_FRAME_RETURN_COLUMN, reg, offset - cur_row->cfa.offset);
2873 }
2874 }
2875
2876 static void
2877 create_cie_data (void)
2878 {
2879 dw_cfa_location loc;
2880 dw_trace_info cie_trace;
2881
2882 dw_stack_pointer_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM);
2883 dw_frame_pointer_regnum = DWARF_FRAME_REGNUM (HARD_FRAME_POINTER_REGNUM);
2884
2885 memset (&cie_trace, 0, sizeof(cie_trace));
2886 cur_trace = &cie_trace;
2887
2888 add_cfi_vec = &cie_cfi_vec;
2889 cie_cfi_row = cur_row = new_cfi_row ();
2890
2891 /* On entry, the Canonical Frame Address is at SP. */
2892 memset(&loc, 0, sizeof (loc));
2893 loc.reg = dw_stack_pointer_regnum;
2894 loc.offset = INCOMING_FRAME_SP_OFFSET;
2895 def_cfa_1 (&loc);
2896
2897 if (targetm.debug_unwind_info () == UI_DWARF2
2898 || targetm_common.except_unwind_info (&global_options) == UI_DWARF2)
2899 {
2900 initial_return_save (INCOMING_RETURN_ADDR_RTX);
2901
2902 /* For a few targets, we have the return address incoming into a
2903 register, but choose a different return column. This will result
2904 in a DW_CFA_register for the return, and an entry in
2905 regs_saved_in_regs to match. If the target later stores that
2906 return address register to the stack, we want to be able to emit
2907 the DW_CFA_offset against the return column, not the intermediate
2908 save register. Save the contents of regs_saved_in_regs so that
2909 we can re-initialize it at the start of each function. */
2910 switch (VEC_length (reg_saved_in_data, cie_trace.regs_saved_in_regs))
2911 {
2912 case 0:
2913 break;
2914 case 1:
2915 cie_return_save = ggc_alloc_reg_saved_in_data ();
2916 *cie_return_save = *VEC_index (reg_saved_in_data,
2917 cie_trace.regs_saved_in_regs, 0);
2918 VEC_free (reg_saved_in_data, heap, cie_trace.regs_saved_in_regs);
2919 break;
2920 default:
2921 gcc_unreachable ();
2922 }
2923 }
2924
2925 add_cfi_vec = NULL;
2926 cur_row = NULL;
2927 cur_trace = NULL;
2928 }
2929
2930 /* Annotate the function with NOTE_INSN_CFI notes to record the CFI
2931 state at each location within the function. These notes will be
2932 emitted during pass_final. */
2933
2934 static unsigned int
2935 execute_dwarf2_frame (void)
2936 {
2937 /* The first time we're called, compute the incoming frame state. */
2938 if (cie_cfi_vec == NULL)
2939 create_cie_data ();
2940
2941 dwarf2out_alloc_current_fde ();
2942
2943 create_pseudo_cfg ();
2944
2945 /* Do the work. */
2946 create_cfi_notes ();
2947 connect_traces ();
2948 add_cfis_to_fde ();
2949
2950 /* Free all the data we allocated. */
2951 {
2952 size_t i;
2953 dw_trace_info *ti;
2954
2955 FOR_EACH_VEC_ELT (dw_trace_info, trace_info, i, ti)
2956 VEC_free (reg_saved_in_data, heap, ti->regs_saved_in_regs);
2957 }
2958 VEC_free (dw_trace_info, heap, trace_info);
2959
2960 htab_delete (trace_index);
2961 trace_index = NULL;
2962
2963 return 0;
2964 }
2965 \f
2966 /* Convert a DWARF call frame info. operation to its string name */
2967
2968 static const char *
2969 dwarf_cfi_name (unsigned int cfi_opc)
2970 {
2971 switch (cfi_opc)
2972 {
2973 case DW_CFA_advance_loc:
2974 return "DW_CFA_advance_loc";
2975 case DW_CFA_offset:
2976 return "DW_CFA_offset";
2977 case DW_CFA_restore:
2978 return "DW_CFA_restore";
2979 case DW_CFA_nop:
2980 return "DW_CFA_nop";
2981 case DW_CFA_set_loc:
2982 return "DW_CFA_set_loc";
2983 case DW_CFA_advance_loc1:
2984 return "DW_CFA_advance_loc1";
2985 case DW_CFA_advance_loc2:
2986 return "DW_CFA_advance_loc2";
2987 case DW_CFA_advance_loc4:
2988 return "DW_CFA_advance_loc4";
2989 case DW_CFA_offset_extended:
2990 return "DW_CFA_offset_extended";
2991 case DW_CFA_restore_extended:
2992 return "DW_CFA_restore_extended";
2993 case DW_CFA_undefined:
2994 return "DW_CFA_undefined";
2995 case DW_CFA_same_value:
2996 return "DW_CFA_same_value";
2997 case DW_CFA_register:
2998 return "DW_CFA_register";
2999 case DW_CFA_remember_state:
3000 return "DW_CFA_remember_state";
3001 case DW_CFA_restore_state:
3002 return "DW_CFA_restore_state";
3003 case DW_CFA_def_cfa:
3004 return "DW_CFA_def_cfa";
3005 case DW_CFA_def_cfa_register:
3006 return "DW_CFA_def_cfa_register";
3007 case DW_CFA_def_cfa_offset:
3008 return "DW_CFA_def_cfa_offset";
3009
3010 /* DWARF 3 */
3011 case DW_CFA_def_cfa_expression:
3012 return "DW_CFA_def_cfa_expression";
3013 case DW_CFA_expression:
3014 return "DW_CFA_expression";
3015 case DW_CFA_offset_extended_sf:
3016 return "DW_CFA_offset_extended_sf";
3017 case DW_CFA_def_cfa_sf:
3018 return "DW_CFA_def_cfa_sf";
3019 case DW_CFA_def_cfa_offset_sf:
3020 return "DW_CFA_def_cfa_offset_sf";
3021
3022 /* SGI/MIPS specific */
3023 case DW_CFA_MIPS_advance_loc8:
3024 return "DW_CFA_MIPS_advance_loc8";
3025
3026 /* GNU extensions */
3027 case DW_CFA_GNU_window_save:
3028 return "DW_CFA_GNU_window_save";
3029 case DW_CFA_GNU_args_size:
3030 return "DW_CFA_GNU_args_size";
3031 case DW_CFA_GNU_negative_offset_extended:
3032 return "DW_CFA_GNU_negative_offset_extended";
3033
3034 default:
3035 return "DW_CFA_<unknown>";
3036 }
3037 }
3038
3039 /* This routine will generate the correct assembly data for a location
3040 description based on a cfi entry with a complex address. */
3041
3042 static void
3043 output_cfa_loc (dw_cfi_ref cfi, int for_eh)
3044 {
3045 dw_loc_descr_ref loc;
3046 unsigned long size;
3047
3048 if (cfi->dw_cfi_opc == DW_CFA_expression)
3049 {
3050 unsigned r =
3051 DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3052 dw2_asm_output_data (1, r, NULL);
3053 loc = cfi->dw_cfi_oprnd2.dw_cfi_loc;
3054 }
3055 else
3056 loc = cfi->dw_cfi_oprnd1.dw_cfi_loc;
3057
3058 /* Output the size of the block. */
3059 size = size_of_locs (loc);
3060 dw2_asm_output_data_uleb128 (size, NULL);
3061
3062 /* Now output the operations themselves. */
3063 output_loc_sequence (loc, for_eh);
3064 }
3065
3066 /* Similar, but used for .cfi_escape. */
3067
3068 static void
3069 output_cfa_loc_raw (dw_cfi_ref cfi)
3070 {
3071 dw_loc_descr_ref loc;
3072 unsigned long size;
3073
3074 if (cfi->dw_cfi_opc == DW_CFA_expression)
3075 {
3076 unsigned r =
3077 DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3078 fprintf (asm_out_file, "%#x,", r);
3079 loc = cfi->dw_cfi_oprnd2.dw_cfi_loc;
3080 }
3081 else
3082 loc = cfi->dw_cfi_oprnd1.dw_cfi_loc;
3083
3084 /* Output the size of the block. */
3085 size = size_of_locs (loc);
3086 dw2_asm_output_data_uleb128_raw (size);
3087 fputc (',', asm_out_file);
3088
3089 /* Now output the operations themselves. */
3090 output_loc_sequence_raw (loc);
3091 }
3092
3093 /* Output a Call Frame Information opcode and its operand(s). */
3094
3095 void
3096 output_cfi (dw_cfi_ref cfi, dw_fde_ref fde, int for_eh)
3097 {
3098 unsigned long r;
3099 HOST_WIDE_INT off;
3100
3101 if (cfi->dw_cfi_opc == DW_CFA_advance_loc)
3102 dw2_asm_output_data (1, (cfi->dw_cfi_opc
3103 | (cfi->dw_cfi_oprnd1.dw_cfi_offset & 0x3f)),
3104 "DW_CFA_advance_loc " HOST_WIDE_INT_PRINT_HEX,
3105 ((unsigned HOST_WIDE_INT)
3106 cfi->dw_cfi_oprnd1.dw_cfi_offset));
3107 else if (cfi->dw_cfi_opc == DW_CFA_offset)
3108 {
3109 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3110 dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)),
3111 "DW_CFA_offset, column %#lx", r);
3112 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3113 dw2_asm_output_data_uleb128 (off, NULL);
3114 }
3115 else if (cfi->dw_cfi_opc == DW_CFA_restore)
3116 {
3117 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3118 dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)),
3119 "DW_CFA_restore, column %#lx", r);
3120 }
3121 else
3122 {
3123 dw2_asm_output_data (1, cfi->dw_cfi_opc,
3124 "%s", dwarf_cfi_name (cfi->dw_cfi_opc));
3125
3126 switch (cfi->dw_cfi_opc)
3127 {
3128 case DW_CFA_set_loc:
3129 if (for_eh)
3130 dw2_asm_output_encoded_addr_rtx (
3131 ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/1, /*global=*/0),
3132 gen_rtx_SYMBOL_REF (Pmode, cfi->dw_cfi_oprnd1.dw_cfi_addr),
3133 false, NULL);
3134 else
3135 dw2_asm_output_addr (DWARF2_ADDR_SIZE,
3136 cfi->dw_cfi_oprnd1.dw_cfi_addr, NULL);
3137 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3138 break;
3139
3140 case DW_CFA_advance_loc1:
3141 dw2_asm_output_delta (1, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3142 fde->dw_fde_current_label, NULL);
3143 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3144 break;
3145
3146 case DW_CFA_advance_loc2:
3147 dw2_asm_output_delta (2, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3148 fde->dw_fde_current_label, NULL);
3149 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3150 break;
3151
3152 case DW_CFA_advance_loc4:
3153 dw2_asm_output_delta (4, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3154 fde->dw_fde_current_label, NULL);
3155 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3156 break;
3157
3158 case DW_CFA_MIPS_advance_loc8:
3159 dw2_asm_output_delta (8, cfi->dw_cfi_oprnd1.dw_cfi_addr,
3160 fde->dw_fde_current_label, NULL);
3161 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr;
3162 break;
3163
3164 case DW_CFA_offset_extended:
3165 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3166 dw2_asm_output_data_uleb128 (r, NULL);
3167 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3168 dw2_asm_output_data_uleb128 (off, NULL);
3169 break;
3170
3171 case DW_CFA_def_cfa:
3172 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3173 dw2_asm_output_data_uleb128 (r, NULL);
3174 dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd2.dw_cfi_offset, NULL);
3175 break;
3176
3177 case DW_CFA_offset_extended_sf:
3178 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3179 dw2_asm_output_data_uleb128 (r, NULL);
3180 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3181 dw2_asm_output_data_sleb128 (off, NULL);
3182 break;
3183
3184 case DW_CFA_def_cfa_sf:
3185 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3186 dw2_asm_output_data_uleb128 (r, NULL);
3187 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset);
3188 dw2_asm_output_data_sleb128 (off, NULL);
3189 break;
3190
3191 case DW_CFA_restore_extended:
3192 case DW_CFA_undefined:
3193 case DW_CFA_same_value:
3194 case DW_CFA_def_cfa_register:
3195 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3196 dw2_asm_output_data_uleb128 (r, NULL);
3197 break;
3198
3199 case DW_CFA_register:
3200 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh);
3201 dw2_asm_output_data_uleb128 (r, NULL);
3202 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, for_eh);
3203 dw2_asm_output_data_uleb128 (r, NULL);
3204 break;
3205
3206 case DW_CFA_def_cfa_offset:
3207 case DW_CFA_GNU_args_size:
3208 dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd1.dw_cfi_offset, NULL);
3209 break;
3210
3211 case DW_CFA_def_cfa_offset_sf:
3212 off = div_data_align (cfi->dw_cfi_oprnd1.dw_cfi_offset);
3213 dw2_asm_output_data_sleb128 (off, NULL);
3214 break;
3215
3216 case DW_CFA_GNU_window_save:
3217 break;
3218
3219 case DW_CFA_def_cfa_expression:
3220 case DW_CFA_expression:
3221 output_cfa_loc (cfi, for_eh);
3222 break;
3223
3224 case DW_CFA_GNU_negative_offset_extended:
3225 /* Obsoleted by DW_CFA_offset_extended_sf. */
3226 gcc_unreachable ();
3227
3228 default:
3229 break;
3230 }
3231 }
3232 }
3233
3234 /* Similar, but do it via assembler directives instead. */
3235
3236 void
3237 output_cfi_directive (FILE *f, dw_cfi_ref cfi)
3238 {
3239 unsigned long r, r2;
3240
3241 switch (cfi->dw_cfi_opc)
3242 {
3243 case DW_CFA_advance_loc:
3244 case DW_CFA_advance_loc1:
3245 case DW_CFA_advance_loc2:
3246 case DW_CFA_advance_loc4:
3247 case DW_CFA_MIPS_advance_loc8:
3248 case DW_CFA_set_loc:
3249 /* Should only be created in a code path not followed when emitting
3250 via directives. The assembler is going to take care of this for
3251 us. But this routines is also used for debugging dumps, so
3252 print something. */
3253 gcc_assert (f != asm_out_file);
3254 fprintf (f, "\t.cfi_advance_loc\n");
3255 break;
3256
3257 case DW_CFA_offset:
3258 case DW_CFA_offset_extended:
3259 case DW_CFA_offset_extended_sf:
3260 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3261 fprintf (f, "\t.cfi_offset %lu, "HOST_WIDE_INT_PRINT_DEC"\n",
3262 r, cfi->dw_cfi_oprnd2.dw_cfi_offset);
3263 break;
3264
3265 case DW_CFA_restore:
3266 case DW_CFA_restore_extended:
3267 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3268 fprintf (f, "\t.cfi_restore %lu\n", r);
3269 break;
3270
3271 case DW_CFA_undefined:
3272 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3273 fprintf (f, "\t.cfi_undefined %lu\n", r);
3274 break;
3275
3276 case DW_CFA_same_value:
3277 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3278 fprintf (f, "\t.cfi_same_value %lu\n", r);
3279 break;
3280
3281 case DW_CFA_def_cfa:
3282 case DW_CFA_def_cfa_sf:
3283 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3284 fprintf (f, "\t.cfi_def_cfa %lu, "HOST_WIDE_INT_PRINT_DEC"\n",
3285 r, cfi->dw_cfi_oprnd2.dw_cfi_offset);
3286 break;
3287
3288 case DW_CFA_def_cfa_register:
3289 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3290 fprintf (f, "\t.cfi_def_cfa_register %lu\n", r);
3291 break;
3292
3293 case DW_CFA_register:
3294 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1);
3295 r2 = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, 1);
3296 fprintf (f, "\t.cfi_register %lu, %lu\n", r, r2);
3297 break;
3298
3299 case DW_CFA_def_cfa_offset:
3300 case DW_CFA_def_cfa_offset_sf:
3301 fprintf (f, "\t.cfi_def_cfa_offset "
3302 HOST_WIDE_INT_PRINT_DEC"\n",
3303 cfi->dw_cfi_oprnd1.dw_cfi_offset);
3304 break;
3305
3306 case DW_CFA_remember_state:
3307 fprintf (f, "\t.cfi_remember_state\n");
3308 break;
3309 case DW_CFA_restore_state:
3310 fprintf (f, "\t.cfi_restore_state\n");
3311 break;
3312
3313 case DW_CFA_GNU_args_size:
3314 if (f == asm_out_file)
3315 {
3316 fprintf (f, "\t.cfi_escape %#x,", DW_CFA_GNU_args_size);
3317 dw2_asm_output_data_uleb128_raw (cfi->dw_cfi_oprnd1.dw_cfi_offset);
3318 if (flag_debug_asm)
3319 fprintf (f, "\t%s args_size "HOST_WIDE_INT_PRINT_DEC,
3320 ASM_COMMENT_START, cfi->dw_cfi_oprnd1.dw_cfi_offset);
3321 fputc ('\n', f);
3322 }
3323 else
3324 {
3325 fprintf (f, "\t.cfi_GNU_args_size "HOST_WIDE_INT_PRINT_DEC "\n",
3326 cfi->dw_cfi_oprnd1.dw_cfi_offset);
3327 }
3328 break;
3329
3330 case DW_CFA_GNU_window_save:
3331 fprintf (f, "\t.cfi_window_save\n");
3332 break;
3333
3334 case DW_CFA_def_cfa_expression:
3335 if (f != asm_out_file)
3336 {
3337 fprintf (f, "\t.cfi_def_cfa_expression ...\n");
3338 break;
3339 }
3340 /* FALLTHRU */
3341 case DW_CFA_expression:
3342 if (f != asm_out_file)
3343 {
3344 fprintf (f, "\t.cfi_cfa_expression ...\n");
3345 break;
3346 }
3347 fprintf (f, "\t.cfi_escape %#x,", cfi->dw_cfi_opc);
3348 output_cfa_loc_raw (cfi);
3349 fputc ('\n', f);
3350 break;
3351
3352 default:
3353 gcc_unreachable ();
3354 }
3355 }
3356
3357 void
3358 dwarf2out_emit_cfi (dw_cfi_ref cfi)
3359 {
3360 if (dwarf2out_do_cfi_asm ())
3361 output_cfi_directive (asm_out_file, cfi);
3362 }
3363
3364 static void
3365 dump_cfi_row (FILE *f, dw_cfi_row *row)
3366 {
3367 dw_cfi_ref cfi;
3368 unsigned i;
3369
3370 cfi = row->cfa_cfi;
3371 if (!cfi)
3372 {
3373 dw_cfa_location dummy;
3374 memset(&dummy, 0, sizeof(dummy));
3375 dummy.reg = INVALID_REGNUM;
3376 cfi = def_cfa_0 (&dummy, &row->cfa);
3377 }
3378 output_cfi_directive (f, cfi);
3379
3380 FOR_EACH_VEC_ELT (dw_cfi_ref, row->reg_save, i, cfi)
3381 if (cfi)
3382 output_cfi_directive (f, cfi);
3383
3384 fprintf (f, "\t.cfi_GNU_args_size "HOST_WIDE_INT_PRINT_DEC "\n",
3385 row->args_size);
3386 }
3387
3388 void debug_cfi_row (dw_cfi_row *row);
3389
3390 void
3391 debug_cfi_row (dw_cfi_row *row)
3392 {
3393 dump_cfi_row (stderr, row);
3394 }
3395 \f
3396
3397 /* Save the result of dwarf2out_do_frame across PCH.
3398 This variable is tri-state, with 0 unset, >0 true, <0 false. */
3399 static GTY(()) signed char saved_do_cfi_asm = 0;
3400
3401 /* Decide whether we want to emit frame unwind information for the current
3402 translation unit. */
3403
3404 bool
3405 dwarf2out_do_frame (void)
3406 {
3407 /* We want to emit correct CFA location expressions or lists, so we
3408 have to return true if we're going to output debug info, even if
3409 we're not going to output frame or unwind info. */
3410 if (write_symbols == DWARF2_DEBUG || write_symbols == VMS_AND_DWARF2_DEBUG)
3411 return true;
3412
3413 if (saved_do_cfi_asm > 0)
3414 return true;
3415
3416 if (targetm.debug_unwind_info () == UI_DWARF2)
3417 return true;
3418
3419 if ((flag_unwind_tables || flag_exceptions)
3420 && targetm_common.except_unwind_info (&global_options) == UI_DWARF2)
3421 return true;
3422
3423 return false;
3424 }
3425
3426 /* Decide whether to emit frame unwind via assembler directives. */
3427
3428 bool
3429 dwarf2out_do_cfi_asm (void)
3430 {
3431 int enc;
3432
3433 #ifdef MIPS_DEBUGGING_INFO
3434 return false;
3435 #endif
3436
3437 if (saved_do_cfi_asm != 0)
3438 return saved_do_cfi_asm > 0;
3439
3440 /* Assume failure for a moment. */
3441 saved_do_cfi_asm = -1;
3442
3443 if (!flag_dwarf2_cfi_asm || !dwarf2out_do_frame ())
3444 return false;
3445 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
3446 return false;
3447
3448 /* Make sure the personality encoding is one the assembler can support.
3449 In particular, aligned addresses can't be handled. */
3450 enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/2,/*global=*/1);
3451 if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel)
3452 return false;
3453 enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0,/*global=*/0);
3454 if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel)
3455 return false;
3456
3457 /* If we can't get the assembler to emit only .debug_frame, and we don't need
3458 dwarf2 unwind info for exceptions, then emit .debug_frame by hand. */
3459 if (!HAVE_GAS_CFI_SECTIONS_DIRECTIVE
3460 && !flag_unwind_tables && !flag_exceptions
3461 && targetm_common.except_unwind_info (&global_options) != UI_DWARF2)
3462 return false;
3463
3464 /* Success! */
3465 saved_do_cfi_asm = 1;
3466 return true;
3467 }
3468
3469 static bool
3470 gate_dwarf2_frame (void)
3471 {
3472 #ifndef HAVE_prologue
3473 /* Targets which still implement the prologue in assembler text
3474 cannot use the generic dwarf2 unwinding. */
3475 return false;
3476 #endif
3477
3478 /* ??? What to do for UI_TARGET unwinding? They might be able to benefit
3479 from the optimized shrink-wrapping annotations that we will compute.
3480 For now, only produce the CFI notes for dwarf2. */
3481 return dwarf2out_do_frame ();
3482 }
3483
3484 struct rtl_opt_pass pass_dwarf2_frame =
3485 {
3486 {
3487 RTL_PASS,
3488 "dwarf2", /* name */
3489 gate_dwarf2_frame, /* gate */
3490 execute_dwarf2_frame, /* execute */
3491 NULL, /* sub */
3492 NULL, /* next */
3493 0, /* static_pass_number */
3494 TV_FINAL, /* tv_id */
3495 0, /* properties_required */
3496 0, /* properties_provided */
3497 0, /* properties_destroyed */
3498 0, /* todo_flags_start */
3499 0 /* todo_flags_finish */
3500 }
3501 };
3502
3503 #include "gt-dwarf2cfi.h"