1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 #include "coretypes.h"
33 #include "insn-config.h"
38 #include "langhooks.h"
40 static void store_fixed_bit_field (rtx
, unsigned HOST_WIDE_INT
,
41 unsigned HOST_WIDE_INT
,
42 unsigned HOST_WIDE_INT
, rtx
);
43 static void store_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
44 unsigned HOST_WIDE_INT
, rtx
);
45 static rtx
extract_fixed_bit_field (enum machine_mode
, rtx
,
46 unsigned HOST_WIDE_INT
,
47 unsigned HOST_WIDE_INT
,
48 unsigned HOST_WIDE_INT
, rtx
, int);
49 static rtx
mask_rtx (enum machine_mode
, int, int, int);
50 static rtx
lshift_value (enum machine_mode
, rtx
, int, int);
51 static rtx
extract_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
, int);
53 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, enum machine_mode
, rtx
);
54 static rtx
expand_smod_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
55 static rtx
expand_sdiv_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
57 /* Test whether a value is zero of a power of two. */
58 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
60 /* Nonzero means divides or modulus operations are relatively cheap for
61 powers of two, so don't use branches; emit the operation instead.
62 Usually, this will mean that the MD file will emit non-branch
65 static bool sdiv_pow2_cheap
[NUM_MACHINE_MODES
];
66 static bool smod_pow2_cheap
[NUM_MACHINE_MODES
];
68 #ifndef SLOW_UNALIGNED_ACCESS
69 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
72 /* For compilers that support multiple targets with different word sizes,
73 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
74 is the H8/300(H) compiler. */
76 #ifndef MAX_BITS_PER_WORD
77 #define MAX_BITS_PER_WORD BITS_PER_WORD
80 /* Reduce conditional compilation elsewhere. */
83 #define CODE_FOR_insv CODE_FOR_nothing
84 #define gen_insv(a,b,c,d) NULL_RTX
88 #define CODE_FOR_extv CODE_FOR_nothing
89 #define gen_extv(a,b,c,d) NULL_RTX
93 #define CODE_FOR_extzv CODE_FOR_nothing
94 #define gen_extzv(a,b,c,d) NULL_RTX
97 /* Cost of various pieces of RTL. Note that some of these are indexed by
98 shift count and some by mode. */
100 static int add_cost
[NUM_MACHINE_MODES
];
101 static int neg_cost
[NUM_MACHINE_MODES
];
102 static int shift_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
103 static int shiftadd_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
104 static int shiftsub_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
105 static int mul_cost
[NUM_MACHINE_MODES
];
106 static int div_cost
[NUM_MACHINE_MODES
];
107 static int mul_widen_cost
[NUM_MACHINE_MODES
];
108 static int mul_highpart_cost
[NUM_MACHINE_MODES
];
115 struct rtx_def reg
; rtunion reg_fld
[2];
116 struct rtx_def plus
; rtunion plus_fld1
;
118 struct rtx_def udiv
; rtunion udiv_fld1
;
119 struct rtx_def mult
; rtunion mult_fld1
;
120 struct rtx_def div
; rtunion div_fld1
;
121 struct rtx_def mod
; rtunion mod_fld1
;
123 struct rtx_def wide_mult
; rtunion wide_mult_fld1
;
124 struct rtx_def wide_lshr
; rtunion wide_lshr_fld1
;
125 struct rtx_def wide_trunc
;
126 struct rtx_def shift
; rtunion shift_fld1
;
127 struct rtx_def shift_mult
; rtunion shift_mult_fld1
;
128 struct rtx_def shift_add
; rtunion shift_add_fld1
;
129 struct rtx_def shift_sub
; rtunion shift_sub_fld1
;
132 rtx pow2
[MAX_BITS_PER_WORD
];
133 rtx cint
[MAX_BITS_PER_WORD
];
135 enum machine_mode mode
, wider_mode
;
137 zero_cost
= rtx_cost (const0_rtx
, 0);
139 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
141 pow2
[m
] = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
142 cint
[m
] = GEN_INT (m
);
145 memset (&all
, 0, sizeof all
);
147 PUT_CODE (&all
.reg
, REG
);
148 /* Avoid using hard regs in ways which may be unsupported. */
149 REGNO (&all
.reg
) = LAST_VIRTUAL_REGISTER
+ 1;
151 PUT_CODE (&all
.plus
, PLUS
);
152 XEXP (&all
.plus
, 0) = &all
.reg
;
153 XEXP (&all
.plus
, 1) = &all
.reg
;
155 PUT_CODE (&all
.neg
, NEG
);
156 XEXP (&all
.neg
, 0) = &all
.reg
;
158 PUT_CODE (&all
.udiv
, UDIV
);
159 XEXP (&all
.udiv
, 0) = &all
.reg
;
160 XEXP (&all
.udiv
, 1) = &all
.reg
;
162 PUT_CODE (&all
.mult
, MULT
);
163 XEXP (&all
.mult
, 0) = &all
.reg
;
164 XEXP (&all
.mult
, 1) = &all
.reg
;
166 PUT_CODE (&all
.div
, DIV
);
167 XEXP (&all
.div
, 0) = &all
.reg
;
168 XEXP (&all
.div
, 1) = 32 < MAX_BITS_PER_WORD
? cint
[32] : GEN_INT (32);
170 PUT_CODE (&all
.mod
, MOD
);
171 XEXP (&all
.mod
, 0) = &all
.reg
;
172 XEXP (&all
.mod
, 1) = XEXP (&all
.div
, 1);
174 PUT_CODE (&all
.zext
, ZERO_EXTEND
);
175 XEXP (&all
.zext
, 0) = &all
.reg
;
177 PUT_CODE (&all
.wide_mult
, MULT
);
178 XEXP (&all
.wide_mult
, 0) = &all
.zext
;
179 XEXP (&all
.wide_mult
, 1) = &all
.zext
;
181 PUT_CODE (&all
.wide_lshr
, LSHIFTRT
);
182 XEXP (&all
.wide_lshr
, 0) = &all
.wide_mult
;
184 PUT_CODE (&all
.wide_trunc
, TRUNCATE
);
185 XEXP (&all
.wide_trunc
, 0) = &all
.wide_lshr
;
187 PUT_CODE (&all
.shift
, ASHIFT
);
188 XEXP (&all
.shift
, 0) = &all
.reg
;
190 PUT_CODE (&all
.shift_mult
, MULT
);
191 XEXP (&all
.shift_mult
, 0) = &all
.reg
;
193 PUT_CODE (&all
.shift_add
, PLUS
);
194 XEXP (&all
.shift_add
, 0) = &all
.shift_mult
;
195 XEXP (&all
.shift_add
, 1) = &all
.reg
;
197 PUT_CODE (&all
.shift_sub
, MINUS
);
198 XEXP (&all
.shift_sub
, 0) = &all
.shift_mult
;
199 XEXP (&all
.shift_sub
, 1) = &all
.reg
;
201 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
203 mode
= GET_MODE_WIDER_MODE (mode
))
205 PUT_MODE (&all
.reg
, mode
);
206 PUT_MODE (&all
.plus
, mode
);
207 PUT_MODE (&all
.neg
, mode
);
208 PUT_MODE (&all
.udiv
, mode
);
209 PUT_MODE (&all
.mult
, mode
);
210 PUT_MODE (&all
.div
, mode
);
211 PUT_MODE (&all
.mod
, mode
);
212 PUT_MODE (&all
.wide_trunc
, mode
);
213 PUT_MODE (&all
.shift
, mode
);
214 PUT_MODE (&all
.shift_mult
, mode
);
215 PUT_MODE (&all
.shift_add
, mode
);
216 PUT_MODE (&all
.shift_sub
, mode
);
218 add_cost
[mode
] = rtx_cost (&all
.plus
, SET
);
219 neg_cost
[mode
] = rtx_cost (&all
.neg
, SET
);
220 div_cost
[mode
] = rtx_cost (&all
.udiv
, SET
);
221 mul_cost
[mode
] = rtx_cost (&all
.mult
, SET
);
223 sdiv_pow2_cheap
[mode
] = (rtx_cost (&all
.div
, SET
) <= 2 * add_cost
[mode
]);
224 smod_pow2_cheap
[mode
] = (rtx_cost (&all
.mod
, SET
) <= 4 * add_cost
[mode
]);
226 wider_mode
= GET_MODE_WIDER_MODE (mode
);
227 if (wider_mode
!= VOIDmode
)
229 PUT_MODE (&all
.zext
, wider_mode
);
230 PUT_MODE (&all
.wide_mult
, wider_mode
);
231 PUT_MODE (&all
.wide_lshr
, wider_mode
);
232 XEXP (&all
.wide_lshr
, 1) = GEN_INT (GET_MODE_BITSIZE (mode
));
234 mul_widen_cost
[wider_mode
] = rtx_cost (&all
.wide_mult
, SET
);
235 mul_highpart_cost
[mode
] = rtx_cost (&all
.wide_trunc
, SET
);
238 shift_cost
[mode
][0] = 0;
239 shiftadd_cost
[mode
][0] = shiftsub_cost
[mode
][0] = add_cost
[mode
];
241 n
= MIN (MAX_BITS_PER_WORD
, GET_MODE_BITSIZE (mode
));
242 for (m
= 1; m
< n
; m
++)
244 XEXP (&all
.shift
, 1) = cint
[m
];
245 XEXP (&all
.shift_mult
, 1) = pow2
[m
];
247 shift_cost
[mode
][m
] = rtx_cost (&all
.shift
, SET
);
248 shiftadd_cost
[mode
][m
] = rtx_cost (&all
.shift_add
, SET
);
249 shiftsub_cost
[mode
][m
] = rtx_cost (&all
.shift_sub
, SET
);
254 /* Return an rtx representing minus the value of X.
255 MODE is the intended mode of the result,
256 useful if X is a CONST_INT. */
259 negate_rtx (enum machine_mode mode
, rtx x
)
261 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
264 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
269 /* Report on the availability of insv/extv/extzv and the desired mode
270 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
271 is false; else the mode of the specified operand. If OPNO is -1,
272 all the caller cares about is whether the insn is available. */
274 mode_for_extraction (enum extraction_pattern pattern
, int opno
)
276 const struct insn_data
*data
;
283 data
= &insn_data
[CODE_FOR_insv
];
286 return MAX_MACHINE_MODE
;
291 data
= &insn_data
[CODE_FOR_extv
];
294 return MAX_MACHINE_MODE
;
299 data
= &insn_data
[CODE_FOR_extzv
];
302 return MAX_MACHINE_MODE
;
311 /* Everyone who uses this function used to follow it with
312 if (result == VOIDmode) result = word_mode; */
313 if (data
->operand
[opno
].mode
== VOIDmode
)
315 return data
->operand
[opno
].mode
;
319 /* Generate code to store value from rtx VALUE
320 into a bit-field within structure STR_RTX
321 containing BITSIZE bits starting at bit BITNUM.
322 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
323 ALIGN is the alignment that STR_RTX is known to have.
324 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
326 /* ??? Note that there are two different ideas here for how
327 to determine the size to count bits within, for a register.
328 One is BITS_PER_WORD, and the other is the size of operand 3
331 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
332 else, we use the mode of operand 3. */
335 store_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
336 unsigned HOST_WIDE_INT bitnum
, enum machine_mode fieldmode
,
340 = (MEM_P (str_rtx
)) ? BITS_PER_UNIT
: BITS_PER_WORD
;
341 unsigned HOST_WIDE_INT offset
, bitpos
;
346 enum machine_mode op_mode
= mode_for_extraction (EP_insv
, 3);
348 while (GET_CODE (op0
) == SUBREG
)
350 /* The following line once was done only if WORDS_BIG_ENDIAN,
351 but I think that is a mistake. WORDS_BIG_ENDIAN is
352 meaningful at a much higher level; when structures are copied
353 between memory and regs, the higher-numbered regs
354 always get higher addresses. */
355 bitnum
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
356 op0
= SUBREG_REG (op0
);
359 /* No action is needed if the target is a register and if the field
360 lies completely outside that register. This can occur if the source
361 code contains an out-of-bounds access to a small array. */
362 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
365 /* Use vec_set patterns for inserting parts of vectors whenever
367 if (VECTOR_MODE_P (GET_MODE (op0
))
369 && (vec_set_optab
->handlers
[GET_MODE (op0
)].insn_code
371 && fieldmode
== GET_MODE_INNER (GET_MODE (op0
))
372 && bitsize
== GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
373 && !(bitnum
% GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
375 enum machine_mode outermode
= GET_MODE (op0
);
376 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
377 int icode
= (int) vec_set_optab
->handlers
[outermode
].insn_code
;
378 int pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
379 rtx rtxpos
= GEN_INT (pos
);
383 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
384 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
385 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
389 if (! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
))
390 src
= copy_to_mode_reg (mode1
, src
);
392 if (! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
393 rtxpos
= copy_to_mode_reg (mode1
, rtxpos
);
395 /* We could handle this, but we should always be called with a pseudo
396 for our targets and all insns should take them as outputs. */
397 gcc_assert ((*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
)
398 && (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
)
399 && (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
));
400 pat
= GEN_FCN (icode
) (dest
, src
, rtxpos
);
411 /* If the target is a register, overwriting the entire object, or storing
412 a full-word or multi-word field can be done with just a SUBREG.
414 If the target is memory, storing any naturally aligned field can be
415 done with a simple store. For targets that support fast unaligned
416 memory, any naturally sized, unit aligned field can be done directly. */
418 offset
= bitnum
/ unit
;
419 bitpos
= bitnum
% unit
;
420 byte_offset
= (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
421 + (offset
* UNITS_PER_WORD
);
424 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
426 ? ((GET_MODE_SIZE (fieldmode
) >= UNITS_PER_WORD
427 || GET_MODE_SIZE (GET_MODE (op0
)) == GET_MODE_SIZE (fieldmode
))
428 && byte_offset
% GET_MODE_SIZE (fieldmode
) == 0)
429 : (! SLOW_UNALIGNED_ACCESS (fieldmode
, MEM_ALIGN (op0
))
430 || (offset
* BITS_PER_UNIT
% bitsize
== 0
431 && MEM_ALIGN (op0
) % GET_MODE_BITSIZE (fieldmode
) == 0))))
433 if (GET_MODE (op0
) != fieldmode
)
436 op0
= adjust_address (op0
, fieldmode
, offset
);
438 op0
= simplify_gen_subreg (fieldmode
, op0
, GET_MODE (op0
),
441 emit_move_insn (op0
, value
);
445 /* Make sure we are playing with integral modes. Pun with subregs
446 if we aren't. This must come after the entire register case above,
447 since that case is valid for any mode. The following cases are only
448 valid for integral modes. */
450 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
451 if (imode
!= GET_MODE (op0
))
454 op0
= adjust_address (op0
, imode
, 0);
457 gcc_assert (imode
!= BLKmode
);
458 op0
= gen_lowpart (imode
, op0
);
463 /* We may be accessing data outside the field, which means
464 we can alias adjacent data. */
467 op0
= shallow_copy_rtx (op0
);
468 set_mem_alias_set (op0
, 0);
469 set_mem_expr (op0
, 0);
472 /* If OP0 is a register, BITPOS must count within a word.
473 But as we have it, it counts within whatever size OP0 now has.
474 On a bigendian machine, these are not the same, so convert. */
477 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
478 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
480 /* Storing an lsb-aligned field in a register
481 can be done with a movestrict instruction. */
484 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0)
485 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
486 && (movstrict_optab
->handlers
[fieldmode
].insn_code
487 != CODE_FOR_nothing
))
489 int icode
= movstrict_optab
->handlers
[fieldmode
].insn_code
;
491 /* Get appropriate low part of the value being stored. */
492 if (GET_CODE (value
) == CONST_INT
|| REG_P (value
))
493 value
= gen_lowpart (fieldmode
, value
);
494 else if (!(GET_CODE (value
) == SYMBOL_REF
495 || GET_CODE (value
) == LABEL_REF
496 || GET_CODE (value
) == CONST
))
497 value
= convert_to_mode (fieldmode
, value
, 0);
499 if (! (*insn_data
[icode
].operand
[1].predicate
) (value
, fieldmode
))
500 value
= copy_to_mode_reg (fieldmode
, value
);
502 if (GET_CODE (op0
) == SUBREG
)
504 /* Else we've got some float mode source being extracted into
505 a different float mode destination -- this combination of
506 subregs results in Severe Tire Damage. */
507 gcc_assert (GET_MODE (SUBREG_REG (op0
)) == fieldmode
508 || GET_MODE_CLASS (fieldmode
) == MODE_INT
509 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
);
510 op0
= SUBREG_REG (op0
);
513 emit_insn (GEN_FCN (icode
)
514 (gen_rtx_SUBREG (fieldmode
, op0
,
515 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
516 + (offset
* UNITS_PER_WORD
)),
522 /* Handle fields bigger than a word. */
524 if (bitsize
> BITS_PER_WORD
)
526 /* Here we transfer the words of the field
527 in the order least significant first.
528 This is because the most significant word is the one which may
530 However, only do that if the value is not BLKmode. */
532 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
533 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
536 /* This is the mode we must force value to, so that there will be enough
537 subwords to extract. Note that fieldmode will often (always?) be
538 VOIDmode, because that is what store_field uses to indicate that this
539 is a bit field, but passing VOIDmode to operand_subword_force
541 fieldmode
= GET_MODE (value
);
542 if (fieldmode
== VOIDmode
)
543 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
545 for (i
= 0; i
< nwords
; i
++)
547 /* If I is 0, use the low-order word in both field and target;
548 if I is 1, use the next to lowest word; and so on. */
549 unsigned int wordnum
= (backwards
? nwords
- i
- 1 : i
);
550 unsigned int bit_offset
= (backwards
551 ? MAX ((int) bitsize
- ((int) i
+ 1)
554 : (int) i
* BITS_PER_WORD
);
556 store_bit_field (op0
, MIN (BITS_PER_WORD
,
557 bitsize
- i
* BITS_PER_WORD
),
558 bitnum
+ bit_offset
, word_mode
,
559 operand_subword_force (value
, wordnum
, fieldmode
));
564 /* From here on we can assume that the field to be stored in is
565 a full-word (whatever type that is), since it is shorter than a word. */
567 /* OFFSET is the number of words or bytes (UNIT says which)
568 from STR_RTX to the first word or byte containing part of the field. */
573 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
577 /* Since this is a destination (lvalue), we can't copy
578 it to a pseudo. We can remove a SUBREG that does not
579 change the size of the operand. Such a SUBREG may
580 have been added above. */
581 gcc_assert (GET_CODE (op0
) == SUBREG
582 && (GET_MODE_SIZE (GET_MODE (op0
))
583 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)))));
584 op0
= SUBREG_REG (op0
);
586 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
587 op0
, (offset
* UNITS_PER_WORD
));
592 /* If VALUE has a floating-point or complex mode, access it as an
593 integer of the corresponding size. This can occur on a machine
594 with 64 bit registers that uses SFmode for float. It can also
595 occur for unaligned float or complex fields. */
597 if (GET_MODE (value
) != VOIDmode
598 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_INT
599 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_PARTIAL_INT
)
601 value
= gen_reg_rtx (int_mode_for_mode (GET_MODE (value
)));
602 emit_move_insn (gen_lowpart (GET_MODE (orig_value
), value
), orig_value
);
605 /* Now OFFSET is nonzero only if OP0 is memory
606 and is therefore always measured in bytes. */
609 && GET_MODE (value
) != BLKmode
610 && !(bitsize
== 1 && GET_CODE (value
) == CONST_INT
)
612 && GET_MODE_BITSIZE (op_mode
) >= bitsize
613 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
614 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (op_mode
))))
616 int xbitpos
= bitpos
;
619 rtx last
= get_last_insn ();
621 enum machine_mode maxmode
= mode_for_extraction (EP_insv
, 3);
622 int save_volatile_ok
= volatile_ok
;
626 /* If this machine's insv can only insert into a register, copy OP0
627 into a register and save it back later. */
629 && ! ((*insn_data
[(int) CODE_FOR_insv
].operand
[0].predicate
)
633 enum machine_mode bestmode
;
635 /* Get the mode to use for inserting into this field. If OP0 is
636 BLKmode, get the smallest mode consistent with the alignment. If
637 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
638 mode. Otherwise, use the smallest mode containing the field. */
640 if (GET_MODE (op0
) == BLKmode
641 || GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (maxmode
))
643 = get_best_mode (bitsize
, bitnum
, MEM_ALIGN (op0
), maxmode
,
644 MEM_VOLATILE_P (op0
));
646 bestmode
= GET_MODE (op0
);
648 if (bestmode
== VOIDmode
649 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (op0
))
650 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (op0
)))
653 /* Adjust address to point to the containing unit of that mode.
654 Compute offset as multiple of this unit, counting in bytes. */
655 unit
= GET_MODE_BITSIZE (bestmode
);
656 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
657 bitpos
= bitnum
% unit
;
658 op0
= adjust_address (op0
, bestmode
, offset
);
660 /* Fetch that unit, store the bitfield in it, then store
662 tempreg
= copy_to_reg (op0
);
663 store_bit_field (tempreg
, bitsize
, bitpos
, fieldmode
, orig_value
);
664 emit_move_insn (op0
, tempreg
);
667 volatile_ok
= save_volatile_ok
;
669 /* Add OFFSET into OP0's address. */
671 xop0
= adjust_address (xop0
, byte_mode
, offset
);
673 /* If xop0 is a register, we need it in MAXMODE
674 to make it acceptable to the format of insv. */
675 if (GET_CODE (xop0
) == SUBREG
)
676 /* We can't just change the mode, because this might clobber op0,
677 and we will need the original value of op0 if insv fails. */
678 xop0
= gen_rtx_SUBREG (maxmode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
679 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
680 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
682 /* On big-endian machines, we count bits from the most significant.
683 If the bit field insn does not, we must invert. */
685 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
686 xbitpos
= unit
- bitsize
- xbitpos
;
688 /* We have been counting XBITPOS within UNIT.
689 Count instead within the size of the register. */
690 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
691 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
693 unit
= GET_MODE_BITSIZE (maxmode
);
695 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
697 if (GET_MODE (value
) != maxmode
)
699 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
701 /* Optimization: Don't bother really extending VALUE
702 if it has all the bits we will actually use. However,
703 if we must narrow it, be sure we do it correctly. */
705 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (maxmode
))
709 tmp
= simplify_subreg (maxmode
, value1
, GET_MODE (value
), 0);
711 tmp
= simplify_gen_subreg (maxmode
,
712 force_reg (GET_MODE (value
),
714 GET_MODE (value
), 0);
718 value1
= gen_lowpart (maxmode
, value1
);
720 else if (GET_CODE (value
) == CONST_INT
)
721 value1
= gen_int_mode (INTVAL (value
), maxmode
);
723 /* Parse phase is supposed to make VALUE's data type
724 match that of the component reference, which is a type
725 at least as wide as the field; so VALUE should have
726 a mode that corresponds to that type. */
727 gcc_assert (CONSTANT_P (value
));
730 /* If this machine's insv insists on a register,
731 get VALUE1 into a register. */
732 if (! ((*insn_data
[(int) CODE_FOR_insv
].operand
[3].predicate
)
734 value1
= force_reg (maxmode
, value1
);
736 pat
= gen_insv (xop0
, GEN_INT (bitsize
), GEN_INT (xbitpos
), value1
);
741 delete_insns_since (last
);
742 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
747 /* Insv is not available; store using shifts and boolean ops. */
748 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
752 /* Use shifts and boolean operations to store VALUE
753 into a bit field of width BITSIZE
754 in a memory location specified by OP0 except offset by OFFSET bytes.
755 (OFFSET must be 0 if OP0 is a register.)
756 The field starts at position BITPOS within the byte.
757 (If OP0 is a register, it may be a full word or a narrower mode,
758 but BITPOS still counts within a full word,
759 which is significant on bigendian machines.) */
762 store_fixed_bit_field (rtx op0
, unsigned HOST_WIDE_INT offset
,
763 unsigned HOST_WIDE_INT bitsize
,
764 unsigned HOST_WIDE_INT bitpos
, rtx value
)
766 enum machine_mode mode
;
767 unsigned int total_bits
= BITS_PER_WORD
;
772 /* There is a case not handled here:
773 a structure with a known alignment of just a halfword
774 and a field split across two aligned halfwords within the structure.
775 Or likewise a structure with a known alignment of just a byte
776 and a field split across two bytes.
777 Such cases are not supposed to be able to occur. */
779 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
781 gcc_assert (!offset
);
782 /* Special treatment for a bit field split across two registers. */
783 if (bitsize
+ bitpos
> BITS_PER_WORD
)
785 store_split_bit_field (op0
, bitsize
, bitpos
, value
);
791 /* Get the proper mode to use for this field. We want a mode that
792 includes the entire field. If such a mode would be larger than
793 a word, we won't be doing the extraction the normal way.
794 We don't want a mode bigger than the destination. */
796 mode
= GET_MODE (op0
);
797 if (GET_MODE_BITSIZE (mode
) == 0
798 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
800 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
801 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
803 if (mode
== VOIDmode
)
805 /* The only way this should occur is if the field spans word
807 store_split_bit_field (op0
, bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
812 total_bits
= GET_MODE_BITSIZE (mode
);
814 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
815 be in the range 0 to total_bits-1, and put any excess bytes in
817 if (bitpos
>= total_bits
)
819 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
820 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
824 /* Get ref to an aligned byte, halfword, or word containing the field.
825 Adjust BITPOS to be position within a word,
826 and OFFSET to be the offset of that word.
827 Then alter OP0 to refer to that word. */
828 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
829 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
830 op0
= adjust_address (op0
, mode
, offset
);
833 mode
= GET_MODE (op0
);
835 /* Now MODE is either some integral mode for a MEM as OP0,
836 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
837 The bit field is contained entirely within OP0.
838 BITPOS is the starting bit number within OP0.
839 (OP0's mode may actually be narrower than MODE.) */
841 if (BYTES_BIG_ENDIAN
)
842 /* BITPOS is the distance between our msb
843 and that of the containing datum.
844 Convert it to the distance from the lsb. */
845 bitpos
= total_bits
- bitsize
- bitpos
;
847 /* Now BITPOS is always the distance between our lsb
850 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
851 we must first convert its mode to MODE. */
853 if (GET_CODE (value
) == CONST_INT
)
855 HOST_WIDE_INT v
= INTVAL (value
);
857 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
858 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
862 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
863 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
864 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
867 value
= lshift_value (mode
, value
, bitpos
, bitsize
);
871 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
872 && bitpos
+ bitsize
!= GET_MODE_BITSIZE (mode
));
874 if (GET_MODE (value
) != mode
)
876 if ((REG_P (value
) || GET_CODE (value
) == SUBREG
)
877 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (value
)))
878 value
= gen_lowpart (mode
, value
);
880 value
= convert_to_mode (mode
, value
, 1);
884 value
= expand_binop (mode
, and_optab
, value
,
885 mask_rtx (mode
, 0, bitsize
, 0),
886 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
888 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
889 build_int_cst (NULL_TREE
, bitpos
), NULL_RTX
, 1);
892 /* Now clear the chosen bits in OP0,
893 except that if VALUE is -1 we need not bother. */
899 temp
= expand_binop (mode
, and_optab
, op0
,
900 mask_rtx (mode
, bitpos
, bitsize
, 1),
901 subtarget
, 1, OPTAB_LIB_WIDEN
);
907 /* Now logical-or VALUE into OP0, unless it is zero. */
910 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
911 subtarget
, 1, OPTAB_LIB_WIDEN
);
913 emit_move_insn (op0
, temp
);
916 /* Store a bit field that is split across multiple accessible memory objects.
918 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
919 BITSIZE is the field width; BITPOS the position of its first bit
921 VALUE is the value to store.
923 This does not yet handle fields wider than BITS_PER_WORD. */
926 store_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
927 unsigned HOST_WIDE_INT bitpos
, rtx value
)
930 unsigned int bitsdone
= 0;
932 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
934 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
935 unit
= BITS_PER_WORD
;
937 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
939 /* If VALUE is a constant other than a CONST_INT, get it into a register in
940 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
941 that VALUE might be a floating-point constant. */
942 if (CONSTANT_P (value
) && GET_CODE (value
) != CONST_INT
)
944 rtx word
= gen_lowpart_common (word_mode
, value
);
946 if (word
&& (value
!= word
))
949 value
= gen_lowpart_common (word_mode
,
950 force_reg (GET_MODE (value
) != VOIDmode
952 : word_mode
, value
));
955 while (bitsdone
< bitsize
)
957 unsigned HOST_WIDE_INT thissize
;
959 unsigned HOST_WIDE_INT thispos
;
960 unsigned HOST_WIDE_INT offset
;
962 offset
= (bitpos
+ bitsdone
) / unit
;
963 thispos
= (bitpos
+ bitsdone
) % unit
;
965 /* THISSIZE must not overrun a word boundary. Otherwise,
966 store_fixed_bit_field will call us again, and we will mutually
968 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
969 thissize
= MIN (thissize
, unit
- thispos
);
971 if (BYTES_BIG_ENDIAN
)
975 /* We must do an endian conversion exactly the same way as it is
976 done in extract_bit_field, so that the two calls to
977 extract_fixed_bit_field will have comparable arguments. */
978 if (!MEM_P (value
) || GET_MODE (value
) == BLKmode
)
979 total_bits
= BITS_PER_WORD
;
981 total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
983 /* Fetch successively less significant portions. */
984 if (GET_CODE (value
) == CONST_INT
)
985 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
986 >> (bitsize
- bitsdone
- thissize
))
987 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
989 /* The args are chosen so that the last part includes the
990 lsb. Give extract_bit_field the value it needs (with
991 endianness compensation) to fetch the piece we want. */
992 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
993 total_bits
- bitsize
+ bitsdone
,
998 /* Fetch successively more significant portions. */
999 if (GET_CODE (value
) == CONST_INT
)
1000 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1002 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1004 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
1005 bitsdone
, NULL_RTX
, 1);
1008 /* If OP0 is a register, then handle OFFSET here.
1010 When handling multiword bitfields, extract_bit_field may pass
1011 down a word_mode SUBREG of a larger REG for a bitfield that actually
1012 crosses a word boundary. Thus, for a SUBREG, we must find
1013 the current word starting from the base register. */
1014 if (GET_CODE (op0
) == SUBREG
)
1016 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1017 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1018 GET_MODE (SUBREG_REG (op0
)));
1021 else if (REG_P (op0
))
1023 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1029 /* OFFSET is in UNITs, and UNIT is in bits.
1030 store_fixed_bit_field wants offset in bytes. */
1031 store_fixed_bit_field (word
, offset
* unit
/ BITS_PER_UNIT
, thissize
,
1033 bitsdone
+= thissize
;
1037 /* Generate code to extract a byte-field from STR_RTX
1038 containing BITSIZE bits, starting at BITNUM,
1039 and put it in TARGET if possible (if TARGET is nonzero).
1040 Regardless of TARGET, we return the rtx for where the value is placed.
1042 STR_RTX is the structure containing the byte (a REG or MEM).
1043 UNSIGNEDP is nonzero if this is an unsigned bit field.
1044 MODE is the natural mode of the field value once extracted.
1045 TMODE is the mode the caller would like the value to have;
1046 but the value may be returned with type MODE instead.
1048 TOTAL_SIZE is the size in bytes of the containing structure,
1051 If a TARGET is specified and we can store in it at no extra cost,
1052 we do so, and return TARGET.
1053 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1054 if they are equally easy. */
1057 extract_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1058 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1059 enum machine_mode mode
, enum machine_mode tmode
)
1062 = (MEM_P (str_rtx
)) ? BITS_PER_UNIT
: BITS_PER_WORD
;
1063 unsigned HOST_WIDE_INT offset
, bitpos
;
1065 rtx spec_target
= target
;
1066 rtx spec_target_subreg
= 0;
1067 enum machine_mode int_mode
;
1068 enum machine_mode extv_mode
= mode_for_extraction (EP_extv
, 0);
1069 enum machine_mode extzv_mode
= mode_for_extraction (EP_extzv
, 0);
1070 enum machine_mode mode1
;
1073 if (tmode
== VOIDmode
)
1076 while (GET_CODE (op0
) == SUBREG
)
1078 bitnum
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1079 op0
= SUBREG_REG (op0
);
1082 /* If we have an out-of-bounds access to a register, just return an
1083 uninitialized register of the required mode. This can occur if the
1084 source code contains an out-of-bounds access to a small array. */
1085 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
1086 return gen_reg_rtx (tmode
);
1089 && mode
== GET_MODE (op0
)
1091 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1093 /* We're trying to extract a full register from itself. */
1097 /* Use vec_extract patterns for extracting parts of vectors whenever
1099 if (VECTOR_MODE_P (GET_MODE (op0
))
1101 && (vec_extract_optab
->handlers
[GET_MODE (op0
)].insn_code
1102 != CODE_FOR_nothing
)
1103 && ((bitnum
+ bitsize
- 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
1104 == bitnum
/ GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
1106 enum machine_mode outermode
= GET_MODE (op0
);
1107 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
1108 int icode
= (int) vec_extract_optab
->handlers
[outermode
].insn_code
;
1109 unsigned HOST_WIDE_INT pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
1110 rtx rtxpos
= GEN_INT (pos
);
1112 rtx dest
= NULL
, pat
, seq
;
1113 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
1114 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
1115 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
1117 if (innermode
== tmode
|| innermode
== mode
)
1121 dest
= gen_reg_rtx (innermode
);
1125 if (! (*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
))
1126 dest
= copy_to_mode_reg (mode0
, dest
);
1128 if (! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
))
1129 src
= copy_to_mode_reg (mode1
, src
);
1131 if (! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
1132 rtxpos
= copy_to_mode_reg (mode1
, rtxpos
);
1134 /* We could handle this, but we should always be called with a pseudo
1135 for our targets and all insns should take them as outputs. */
1136 gcc_assert ((*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
)
1137 && (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
)
1138 && (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
));
1140 pat
= GEN_FCN (icode
) (dest
, src
, rtxpos
);
1151 /* Make sure we are playing with integral modes. Pun with subregs
1154 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1155 if (imode
!= GET_MODE (op0
))
1158 op0
= adjust_address (op0
, imode
, 0);
1161 gcc_assert (imode
!= BLKmode
);
1162 op0
= gen_lowpart (imode
, op0
);
1164 /* If we got a SUBREG, force it into a register since we
1165 aren't going to be able to do another SUBREG on it. */
1166 if (GET_CODE (op0
) == SUBREG
)
1167 op0
= force_reg (imode
, op0
);
1172 /* We may be accessing data outside the field, which means
1173 we can alias adjacent data. */
1176 op0
= shallow_copy_rtx (op0
);
1177 set_mem_alias_set (op0
, 0);
1178 set_mem_expr (op0
, 0);
1181 /* Extraction of a full-word or multi-word value from a structure
1182 in a register or aligned memory can be done with just a SUBREG.
1183 A subword value in the least significant part of a register
1184 can also be extracted with a SUBREG. For this, we need the
1185 byte offset of the value in op0. */
1187 bitpos
= bitnum
% unit
;
1188 offset
= bitnum
/ unit
;
1189 byte_offset
= bitpos
/ BITS_PER_UNIT
+ offset
* UNITS_PER_WORD
;
1191 /* If OP0 is a register, BITPOS must count within a word.
1192 But as we have it, it counts within whatever size OP0 now has.
1193 On a bigendian machine, these are not the same, so convert. */
1194 if (BYTES_BIG_ENDIAN
1196 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
1197 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1199 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1200 If that's wrong, the solution is to test for it and set TARGET to 0
1203 /* Only scalar integer modes can be converted via subregs. There is an
1204 additional problem for FP modes here in that they can have a precision
1205 which is different from the size. mode_for_size uses precision, but
1206 we want a mode based on the size, so we must avoid calling it for FP
1208 mode1
= (SCALAR_INT_MODE_P (tmode
)
1209 ? mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0)
1212 if (((bitsize
>= BITS_PER_WORD
&& bitsize
== GET_MODE_BITSIZE (mode
)
1213 && bitpos
% BITS_PER_WORD
== 0)
1214 || (mode1
!= BLKmode
1215 /* ??? The big endian test here is wrong. This is correct
1216 if the value is in a register, and if mode_for_size is not
1217 the same mode as op0. This causes us to get unnecessarily
1218 inefficient code from the Thumb port when -mbig-endian. */
1219 && (BYTES_BIG_ENDIAN
1220 ? bitpos
+ bitsize
== BITS_PER_WORD
1223 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1224 GET_MODE_BITSIZE (GET_MODE (op0
)))
1225 && GET_MODE_SIZE (mode1
) != 0
1226 && byte_offset
% GET_MODE_SIZE (mode1
) == 0)
1228 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (op0
))
1229 || (offset
* BITS_PER_UNIT
% bitsize
== 0
1230 && MEM_ALIGN (op0
) % bitsize
== 0)))))
1232 if (mode1
!= GET_MODE (op0
))
1235 op0
= adjust_address (op0
, mode1
, offset
);
1238 rtx sub
= simplify_gen_subreg (mode1
, op0
, GET_MODE (op0
),
1241 goto no_subreg_mode_swap
;
1246 return convert_to_mode (tmode
, op0
, unsignedp
);
1249 no_subreg_mode_swap
:
1251 /* Handle fields bigger than a word. */
1253 if (bitsize
> BITS_PER_WORD
)
1255 /* Here we transfer the words of the field
1256 in the order least significant first.
1257 This is because the most significant word is the one which may
1258 be less than full. */
1260 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1263 if (target
== 0 || !REG_P (target
))
1264 target
= gen_reg_rtx (mode
);
1266 /* Indicate for flow that the entire target reg is being set. */
1267 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
1269 for (i
= 0; i
< nwords
; i
++)
1271 /* If I is 0, use the low-order word in both field and target;
1272 if I is 1, use the next to lowest word; and so on. */
1273 /* Word number in TARGET to use. */
1274 unsigned int wordnum
1276 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1278 /* Offset from start of field in OP0. */
1279 unsigned int bit_offset
= (WORDS_BIG_ENDIAN
1280 ? MAX (0, ((int) bitsize
- ((int) i
+ 1)
1281 * (int) BITS_PER_WORD
))
1282 : (int) i
* BITS_PER_WORD
);
1283 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1285 = extract_bit_field (op0
, MIN (BITS_PER_WORD
,
1286 bitsize
- i
* BITS_PER_WORD
),
1287 bitnum
+ bit_offset
, 1, target_part
, mode
,
1290 gcc_assert (target_part
);
1292 if (result_part
!= target_part
)
1293 emit_move_insn (target_part
, result_part
);
1298 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1299 need to be zero'd out. */
1300 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1302 unsigned int i
, total_words
;
1304 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1305 for (i
= nwords
; i
< total_words
; i
++)
1307 (operand_subword (target
,
1308 WORDS_BIG_ENDIAN
? total_words
- i
- 1 : i
,
1315 /* Signed bit field: sign-extend with two arithmetic shifts. */
1316 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1317 build_int_cst (NULL_TREE
,
1318 GET_MODE_BITSIZE (mode
) - bitsize
),
1320 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1321 build_int_cst (NULL_TREE
,
1322 GET_MODE_BITSIZE (mode
) - bitsize
),
1326 /* From here on we know the desired field is smaller than a word. */
1328 /* Check if there is a correspondingly-sized integer field, so we can
1329 safely extract it as one size of integer, if necessary; then
1330 truncate or extend to the size that is wanted; then use SUBREGs or
1331 convert_to_mode to get one of the modes we really wanted. */
1333 int_mode
= int_mode_for_mode (tmode
);
1334 if (int_mode
== BLKmode
)
1335 int_mode
= int_mode_for_mode (mode
);
1336 /* Should probably push op0 out to memory and then do a load. */
1337 gcc_assert (int_mode
!= BLKmode
);
1339 /* OFFSET is the number of words or bytes (UNIT says which)
1340 from STR_RTX to the first word or byte containing part of the field. */
1344 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1347 op0
= copy_to_reg (op0
);
1348 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
1349 op0
, (offset
* UNITS_PER_WORD
));
1354 /* Now OFFSET is nonzero only for memory operands. */
1360 && GET_MODE_BITSIZE (extzv_mode
) >= bitsize
1361 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1362 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extzv_mode
))))
1364 unsigned HOST_WIDE_INT xbitpos
= bitpos
, xoffset
= offset
;
1365 rtx bitsize_rtx
, bitpos_rtx
;
1366 rtx last
= get_last_insn ();
1368 rtx xtarget
= target
;
1369 rtx xspec_target
= spec_target
;
1370 rtx xspec_target_subreg
= spec_target_subreg
;
1372 enum machine_mode maxmode
= mode_for_extraction (EP_extzv
, 0);
1376 int save_volatile_ok
= volatile_ok
;
1379 /* Is the memory operand acceptable? */
1380 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[1].predicate
)
1381 (xop0
, GET_MODE (xop0
))))
1383 /* No, load into a reg and extract from there. */
1384 enum machine_mode bestmode
;
1386 /* Get the mode to use for inserting into this field. If
1387 OP0 is BLKmode, get the smallest mode consistent with the
1388 alignment. If OP0 is a non-BLKmode object that is no
1389 wider than MAXMODE, use its mode. Otherwise, use the
1390 smallest mode containing the field. */
1392 if (GET_MODE (xop0
) == BLKmode
1393 || (GET_MODE_SIZE (GET_MODE (op0
))
1394 > GET_MODE_SIZE (maxmode
)))
1395 bestmode
= get_best_mode (bitsize
, bitnum
,
1396 MEM_ALIGN (xop0
), maxmode
,
1397 MEM_VOLATILE_P (xop0
));
1399 bestmode
= GET_MODE (xop0
);
1401 if (bestmode
== VOIDmode
1402 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1403 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1406 /* Compute offset as multiple of this unit,
1407 counting in bytes. */
1408 unit
= GET_MODE_BITSIZE (bestmode
);
1409 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1410 xbitpos
= bitnum
% unit
;
1411 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1413 /* Fetch it to a register in that size. */
1414 xop0
= force_reg (bestmode
, xop0
);
1416 /* XBITPOS counts within UNIT, which is what is expected. */
1419 /* Get ref to first byte containing part of the field. */
1420 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1422 volatile_ok
= save_volatile_ok
;
1425 /* If op0 is a register, we need it in MAXMODE (which is usually
1426 SImode). to make it acceptable to the format of extzv. */
1427 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1429 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
1430 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1432 /* On big-endian machines, we count bits from the most significant.
1433 If the bit field insn does not, we must invert. */
1434 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1435 xbitpos
= unit
- bitsize
- xbitpos
;
1437 /* Now convert from counting within UNIT to counting in MAXMODE. */
1438 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
1439 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
1441 unit
= GET_MODE_BITSIZE (maxmode
);
1444 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1446 if (GET_MODE (xtarget
) != maxmode
)
1448 if (REG_P (xtarget
))
1450 int wider
= (GET_MODE_SIZE (maxmode
)
1451 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1452 xtarget
= gen_lowpart (maxmode
, xtarget
);
1454 xspec_target_subreg
= xtarget
;
1457 xtarget
= gen_reg_rtx (maxmode
);
1460 /* If this machine's extzv insists on a register target,
1461 make sure we have one. */
1462 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[0].predicate
)
1463 (xtarget
, maxmode
)))
1464 xtarget
= gen_reg_rtx (maxmode
);
1466 bitsize_rtx
= GEN_INT (bitsize
);
1467 bitpos_rtx
= GEN_INT (xbitpos
);
1469 pat
= gen_extzv (xtarget
, xop0
, bitsize_rtx
, bitpos_rtx
);
1474 spec_target
= xspec_target
;
1475 spec_target_subreg
= xspec_target_subreg
;
1479 delete_insns_since (last
);
1480 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1486 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1493 && GET_MODE_BITSIZE (extv_mode
) >= bitsize
1494 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1495 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extv_mode
))))
1497 int xbitpos
= bitpos
, xoffset
= offset
;
1498 rtx bitsize_rtx
, bitpos_rtx
;
1499 rtx last
= get_last_insn ();
1500 rtx xop0
= op0
, xtarget
= target
;
1501 rtx xspec_target
= spec_target
;
1502 rtx xspec_target_subreg
= spec_target_subreg
;
1504 enum machine_mode maxmode
= mode_for_extraction (EP_extv
, 0);
1508 /* Is the memory operand acceptable? */
1509 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[1].predicate
)
1510 (xop0
, GET_MODE (xop0
))))
1512 /* No, load into a reg and extract from there. */
1513 enum machine_mode bestmode
;
1515 /* Get the mode to use for inserting into this field. If
1516 OP0 is BLKmode, get the smallest mode consistent with the
1517 alignment. If OP0 is a non-BLKmode object that is no
1518 wider than MAXMODE, use its mode. Otherwise, use the
1519 smallest mode containing the field. */
1521 if (GET_MODE (xop0
) == BLKmode
1522 || (GET_MODE_SIZE (GET_MODE (op0
))
1523 > GET_MODE_SIZE (maxmode
)))
1524 bestmode
= get_best_mode (bitsize
, bitnum
,
1525 MEM_ALIGN (xop0
), maxmode
,
1526 MEM_VOLATILE_P (xop0
));
1528 bestmode
= GET_MODE (xop0
);
1530 if (bestmode
== VOIDmode
1531 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1532 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1535 /* Compute offset as multiple of this unit,
1536 counting in bytes. */
1537 unit
= GET_MODE_BITSIZE (bestmode
);
1538 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1539 xbitpos
= bitnum
% unit
;
1540 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1542 /* Fetch it to a register in that size. */
1543 xop0
= force_reg (bestmode
, xop0
);
1545 /* XBITPOS counts within UNIT, which is what is expected. */
1548 /* Get ref to first byte containing part of the field. */
1549 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1552 /* If op0 is a register, we need it in MAXMODE (which is usually
1553 SImode) to make it acceptable to the format of extv. */
1554 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1556 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
1557 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1559 /* On big-endian machines, we count bits from the most significant.
1560 If the bit field insn does not, we must invert. */
1561 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1562 xbitpos
= unit
- bitsize
- xbitpos
;
1564 /* XBITPOS counts within a size of UNIT.
1565 Adjust to count within a size of MAXMODE. */
1566 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
1567 xbitpos
+= (GET_MODE_BITSIZE (maxmode
) - unit
);
1569 unit
= GET_MODE_BITSIZE (maxmode
);
1572 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1574 if (GET_MODE (xtarget
) != maxmode
)
1576 if (REG_P (xtarget
))
1578 int wider
= (GET_MODE_SIZE (maxmode
)
1579 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1580 xtarget
= gen_lowpart (maxmode
, xtarget
);
1582 xspec_target_subreg
= xtarget
;
1585 xtarget
= gen_reg_rtx (maxmode
);
1588 /* If this machine's extv insists on a register target,
1589 make sure we have one. */
1590 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[0].predicate
)
1591 (xtarget
, maxmode
)))
1592 xtarget
= gen_reg_rtx (maxmode
);
1594 bitsize_rtx
= GEN_INT (bitsize
);
1595 bitpos_rtx
= GEN_INT (xbitpos
);
1597 pat
= gen_extv (xtarget
, xop0
, bitsize_rtx
, bitpos_rtx
);
1602 spec_target
= xspec_target
;
1603 spec_target_subreg
= xspec_target_subreg
;
1607 delete_insns_since (last
);
1608 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1614 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1617 if (target
== spec_target
)
1619 if (target
== spec_target_subreg
)
1621 if (GET_MODE (target
) != tmode
&& GET_MODE (target
) != mode
)
1623 /* If the target mode is not a scalar integral, first convert to the
1624 integer mode of that size and then access it as a floating-point
1625 value via a SUBREG. */
1626 if (!SCALAR_INT_MODE_P (tmode
))
1628 enum machine_mode smode
1629 = mode_for_size (GET_MODE_BITSIZE (tmode
), MODE_INT
, 0);
1630 target
= convert_to_mode (smode
, target
, unsignedp
);
1631 target
= force_reg (smode
, target
);
1632 return gen_lowpart (tmode
, target
);
1635 return convert_to_mode (tmode
, target
, unsignedp
);
1640 /* Extract a bit field using shifts and boolean operations
1641 Returns an rtx to represent the value.
1642 OP0 addresses a register (word) or memory (byte).
1643 BITPOS says which bit within the word or byte the bit field starts in.
1644 OFFSET says how many bytes farther the bit field starts;
1645 it is 0 if OP0 is a register.
1646 BITSIZE says how many bits long the bit field is.
1647 (If OP0 is a register, it may be narrower than a full word,
1648 but BITPOS still counts within a full word,
1649 which is significant on bigendian machines.)
1651 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1652 If TARGET is nonzero, attempts to store the value there
1653 and return TARGET, but this is not guaranteed.
1654 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1657 extract_fixed_bit_field (enum machine_mode tmode
, rtx op0
,
1658 unsigned HOST_WIDE_INT offset
,
1659 unsigned HOST_WIDE_INT bitsize
,
1660 unsigned HOST_WIDE_INT bitpos
, rtx target
,
1663 unsigned int total_bits
= BITS_PER_WORD
;
1664 enum machine_mode mode
;
1666 if (GET_CODE (op0
) == SUBREG
|| REG_P (op0
))
1668 /* Special treatment for a bit field split across two registers. */
1669 if (bitsize
+ bitpos
> BITS_PER_WORD
)
1670 return extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
);
1674 /* Get the proper mode to use for this field. We want a mode that
1675 includes the entire field. If such a mode would be larger than
1676 a word, we won't be doing the extraction the normal way. */
1678 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
1679 MEM_ALIGN (op0
), word_mode
, MEM_VOLATILE_P (op0
));
1681 if (mode
== VOIDmode
)
1682 /* The only way this should occur is if the field spans word
1684 return extract_split_bit_field (op0
, bitsize
,
1685 bitpos
+ offset
* BITS_PER_UNIT
,
1688 total_bits
= GET_MODE_BITSIZE (mode
);
1690 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1691 be in the range 0 to total_bits-1, and put any excess bytes in
1693 if (bitpos
>= total_bits
)
1695 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
1696 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
1700 /* Get ref to an aligned byte, halfword, or word containing the field.
1701 Adjust BITPOS to be position within a word,
1702 and OFFSET to be the offset of that word.
1703 Then alter OP0 to refer to that word. */
1704 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
1705 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
1706 op0
= adjust_address (op0
, mode
, offset
);
1709 mode
= GET_MODE (op0
);
1711 if (BYTES_BIG_ENDIAN
)
1712 /* BITPOS is the distance between our msb and that of OP0.
1713 Convert it to the distance from the lsb. */
1714 bitpos
= total_bits
- bitsize
- bitpos
;
1716 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1717 We have reduced the big-endian case to the little-endian case. */
1723 /* If the field does not already start at the lsb,
1724 shift it so it does. */
1725 tree amount
= build_int_cst (NULL_TREE
, bitpos
);
1726 /* Maybe propagate the target for the shift. */
1727 /* But not if we will return it--could confuse integrate.c. */
1728 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1729 if (tmode
!= mode
) subtarget
= 0;
1730 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1732 /* Convert the value to the desired mode. */
1734 op0
= convert_to_mode (tmode
, op0
, 1);
1736 /* Unless the msb of the field used to be the msb when we shifted,
1737 mask out the upper bits. */
1739 if (GET_MODE_BITSIZE (mode
) != bitpos
+ bitsize
)
1740 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1741 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1742 target
, 1, OPTAB_LIB_WIDEN
);
1746 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1747 then arithmetic-shift its lsb to the lsb of the word. */
1748 op0
= force_reg (mode
, op0
);
1752 /* Find the narrowest integer mode that contains the field. */
1754 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1755 mode
= GET_MODE_WIDER_MODE (mode
))
1756 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitpos
)
1758 op0
= convert_to_mode (mode
, op0
, 0);
1762 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitpos
))
1765 = build_int_cst (NULL_TREE
,
1766 GET_MODE_BITSIZE (mode
) - (bitsize
+ bitpos
));
1767 /* Maybe propagate the target for the shift. */
1768 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1769 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1772 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1773 build_int_cst (NULL_TREE
,
1774 GET_MODE_BITSIZE (mode
) - bitsize
),
1778 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1779 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1780 complement of that if COMPLEMENT. The mask is truncated if
1781 necessary to the width of mode MODE. The mask is zero-extended if
1782 BITSIZE+BITPOS is too small for MODE. */
1785 mask_rtx (enum machine_mode mode
, int bitpos
, int bitsize
, int complement
)
1787 HOST_WIDE_INT masklow
, maskhigh
;
1791 else if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1792 masklow
= (HOST_WIDE_INT
) -1 << bitpos
;
1796 if (bitpos
+ bitsize
< HOST_BITS_PER_WIDE_INT
)
1797 masklow
&= ((unsigned HOST_WIDE_INT
) -1
1798 >> (HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1800 if (bitpos
<= HOST_BITS_PER_WIDE_INT
)
1803 maskhigh
= (HOST_WIDE_INT
) -1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
1807 else if (bitpos
+ bitsize
> HOST_BITS_PER_WIDE_INT
)
1808 maskhigh
&= ((unsigned HOST_WIDE_INT
) -1
1809 >> (2 * HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1815 maskhigh
= ~maskhigh
;
1819 return immed_double_const (masklow
, maskhigh
, mode
);
1822 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1823 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1826 lshift_value (enum machine_mode mode
, rtx value
, int bitpos
, int bitsize
)
1828 unsigned HOST_WIDE_INT v
= INTVAL (value
);
1829 HOST_WIDE_INT low
, high
;
1831 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1832 v
&= ~((HOST_WIDE_INT
) -1 << bitsize
);
1834 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1837 high
= (bitpos
> 0 ? (v
>> (HOST_BITS_PER_WIDE_INT
- bitpos
)) : 0);
1842 high
= v
<< (bitpos
- HOST_BITS_PER_WIDE_INT
);
1845 return immed_double_const (low
, high
, mode
);
1848 /* Extract a bit field from a memory by forcing the alignment of the
1849 memory. This efficient only if the field spans at least 4 boundaries.
1852 BITSIZE is the field width; BITPOS is the position of the first bit.
1853 UNSIGNEDP is true if the result should be zero-extended. */
1856 extract_force_align_mem_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1857 unsigned HOST_WIDE_INT bitpos
,
1860 enum machine_mode mode
, dmode
;
1861 unsigned int m_bitsize
, m_size
;
1862 unsigned int sign_shift_up
, sign_shift_dn
;
1863 rtx base
, a1
, a2
, v1
, v2
, comb
, shift
, result
, start
;
1865 /* Choose a mode that will fit BITSIZE. */
1866 mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
1867 m_size
= GET_MODE_SIZE (mode
);
1868 m_bitsize
= GET_MODE_BITSIZE (mode
);
1870 /* Choose a mode twice as wide. Fail if no such mode exists. */
1871 dmode
= mode_for_size (m_bitsize
* 2, MODE_INT
, false);
1872 if (dmode
== BLKmode
)
1875 do_pending_stack_adjust ();
1876 start
= get_last_insn ();
1878 /* At the end, we'll need an additional shift to deal with sign/zero
1879 extension. By default this will be a left+right shift of the
1880 appropriate size. But we may be able to eliminate one of them. */
1881 sign_shift_up
= sign_shift_dn
= m_bitsize
- bitsize
;
1883 if (STRICT_ALIGNMENT
)
1885 base
= plus_constant (XEXP (op0
, 0), bitpos
/ BITS_PER_UNIT
);
1886 bitpos
%= BITS_PER_UNIT
;
1888 /* We load two values to be concatenate. There's an edge condition
1889 that bears notice -- an aligned value at the end of a page can
1890 only load one value lest we segfault. So the two values we load
1891 are at "base & -size" and "(base + size - 1) & -size". If base
1892 is unaligned, the addresses will be aligned and sequential; if
1893 base is aligned, the addresses will both be equal to base. */
1895 a1
= expand_simple_binop (Pmode
, AND
, force_operand (base
, NULL
),
1896 GEN_INT (-(HOST_WIDE_INT
)m_size
),
1897 NULL
, true, OPTAB_LIB_WIDEN
);
1898 mark_reg_pointer (a1
, m_bitsize
);
1899 v1
= gen_rtx_MEM (mode
, a1
);
1900 set_mem_align (v1
, m_bitsize
);
1901 v1
= force_reg (mode
, validize_mem (v1
));
1903 a2
= plus_constant (base
, GET_MODE_SIZE (mode
) - 1);
1904 a2
= expand_simple_binop (Pmode
, AND
, force_operand (a2
, NULL
),
1905 GEN_INT (-(HOST_WIDE_INT
)m_size
),
1906 NULL
, true, OPTAB_LIB_WIDEN
);
1907 v2
= gen_rtx_MEM (mode
, a2
);
1908 set_mem_align (v2
, m_bitsize
);
1909 v2
= force_reg (mode
, validize_mem (v2
));
1911 /* Combine these two values into a double-word value. */
1912 if (m_bitsize
== BITS_PER_WORD
)
1914 comb
= gen_reg_rtx (dmode
);
1915 emit_insn (gen_rtx_CLOBBER (VOIDmode
, comb
));
1916 emit_move_insn (gen_rtx_SUBREG (mode
, comb
, 0), v1
);
1917 emit_move_insn (gen_rtx_SUBREG (mode
, comb
, m_size
), v2
);
1921 if (BYTES_BIG_ENDIAN
)
1922 comb
= v1
, v1
= v2
, v2
= comb
;
1923 v1
= convert_modes (dmode
, mode
, v1
, true);
1926 v2
= convert_modes (dmode
, mode
, v2
, true);
1927 v2
= expand_simple_binop (dmode
, ASHIFT
, v2
, GEN_INT (m_bitsize
),
1928 NULL
, true, OPTAB_LIB_WIDEN
);
1931 comb
= expand_simple_binop (dmode
, IOR
, v1
, v2
, NULL
,
1932 true, OPTAB_LIB_WIDEN
);
1937 shift
= expand_simple_binop (Pmode
, AND
, base
, GEN_INT (m_size
- 1),
1938 NULL
, true, OPTAB_LIB_WIDEN
);
1939 shift
= expand_mult (Pmode
, shift
, GEN_INT (BITS_PER_UNIT
), NULL
, 1);
1943 if (sign_shift_up
<= bitpos
)
1944 bitpos
-= sign_shift_up
, sign_shift_up
= 0;
1945 shift
= expand_simple_binop (Pmode
, PLUS
, shift
, GEN_INT (bitpos
),
1946 NULL
, true, OPTAB_LIB_WIDEN
);
1951 unsigned HOST_WIDE_INT offset
= bitpos
/ BITS_PER_UNIT
;
1952 bitpos
%= BITS_PER_UNIT
;
1954 /* When strict alignment is not required, we can just load directly
1955 from memory without masking. If the remaining BITPOS offset is
1956 small enough, we may be able to do all operations in MODE as
1957 opposed to DMODE. */
1958 if (bitpos
+ bitsize
<= m_bitsize
)
1960 comb
= adjust_address (op0
, dmode
, offset
);
1962 if (sign_shift_up
<= bitpos
)
1963 bitpos
-= sign_shift_up
, sign_shift_up
= 0;
1964 shift
= GEN_INT (bitpos
);
1967 /* Shift down the double-word such that the requested value is at bit 0. */
1968 if (shift
!= const0_rtx
)
1969 comb
= expand_simple_binop (dmode
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
1970 comb
, shift
, NULL
, unsignedp
, OPTAB_LIB_WIDEN
);
1974 /* If the field exactly matches MODE, then all we need to do is return the
1975 lowpart. Otherwise, shift to get the sign bits set properly. */
1976 result
= force_reg (mode
, gen_lowpart (mode
, comb
));
1979 result
= expand_simple_binop (mode
, ASHIFT
, result
,
1980 GEN_INT (sign_shift_up
),
1981 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
1983 result
= expand_simple_binop (mode
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
1984 result
, GEN_INT (sign_shift_dn
),
1985 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
1990 delete_insns_since (start
);
1994 /* Extract a bit field that is split across two words
1995 and return an RTX for the result.
1997 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1998 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1999 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
2002 extract_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
2003 unsigned HOST_WIDE_INT bitpos
, int unsignedp
)
2006 unsigned int bitsdone
= 0;
2007 rtx result
= NULL_RTX
;
2010 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
2012 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
2013 unit
= BITS_PER_WORD
;
2016 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
2017 if (0 && bitsize
/ unit
> 2)
2019 rtx tmp
= extract_force_align_mem_bit_field (op0
, bitsize
, bitpos
,
2026 while (bitsdone
< bitsize
)
2028 unsigned HOST_WIDE_INT thissize
;
2030 unsigned HOST_WIDE_INT thispos
;
2031 unsigned HOST_WIDE_INT offset
;
2033 offset
= (bitpos
+ bitsdone
) / unit
;
2034 thispos
= (bitpos
+ bitsdone
) % unit
;
2036 /* THISSIZE must not overrun a word boundary. Otherwise,
2037 extract_fixed_bit_field will call us again, and we will mutually
2039 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
2040 thissize
= MIN (thissize
, unit
- thispos
);
2042 /* If OP0 is a register, then handle OFFSET here.
2044 When handling multiword bitfields, extract_bit_field may pass
2045 down a word_mode SUBREG of a larger REG for a bitfield that actually
2046 crosses a word boundary. Thus, for a SUBREG, we must find
2047 the current word starting from the base register. */
2048 if (GET_CODE (op0
) == SUBREG
)
2050 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
2051 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
2052 GET_MODE (SUBREG_REG (op0
)));
2055 else if (REG_P (op0
))
2057 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
2063 /* Extract the parts in bit-counting order,
2064 whose meaning is determined by BYTES_PER_UNIT.
2065 OFFSET is in UNITs, and UNIT is in bits.
2066 extract_fixed_bit_field wants offset in bytes. */
2067 part
= extract_fixed_bit_field (word_mode
, word
,
2068 offset
* unit
/ BITS_PER_UNIT
,
2069 thissize
, thispos
, 0, 1);
2070 bitsdone
+= thissize
;
2072 /* Shift this part into place for the result. */
2073 if (BYTES_BIG_ENDIAN
)
2075 if (bitsize
!= bitsdone
)
2076 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2077 build_int_cst (NULL_TREE
, bitsize
- bitsdone
),
2082 if (bitsdone
!= thissize
)
2083 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2084 build_int_cst (NULL_TREE
,
2085 bitsdone
- thissize
), 0, 1);
2091 /* Combine the parts with bitwise or. This works
2092 because we extracted each part as an unsigned bit field. */
2093 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
2099 /* Unsigned bit field: we are done. */
2102 /* Signed bit field: sign-extend with two arithmetic shifts. */
2103 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
2104 build_int_cst (NULL_TREE
, BITS_PER_WORD
- bitsize
),
2106 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
2107 build_int_cst (NULL_TREE
, BITS_PER_WORD
- bitsize
),
2111 /* Add INC into TARGET. */
2114 expand_inc (rtx target
, rtx inc
)
2116 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
2118 target
, 0, OPTAB_LIB_WIDEN
);
2119 if (value
!= target
)
2120 emit_move_insn (target
, value
);
2123 /* Subtract DEC from TARGET. */
2126 expand_dec (rtx target
, rtx dec
)
2128 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
2130 target
, 0, OPTAB_LIB_WIDEN
);
2131 if (value
!= target
)
2132 emit_move_insn (target
, value
);
2135 /* Output a shift instruction for expression code CODE,
2136 with SHIFTED being the rtx for the value to shift,
2137 and AMOUNT the tree for the amount to shift by.
2138 Store the result in the rtx TARGET, if that is convenient.
2139 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2140 Return the rtx for where the value is. */
2143 expand_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2144 tree amount
, rtx target
, int unsignedp
)
2147 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2148 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2151 /* Previously detected shift-counts computed by NEGATE_EXPR
2152 and shifted in the other direction; but that does not work
2155 op1
= expand_expr (amount
, NULL_RTX
, VOIDmode
, 0);
2157 if (SHIFT_COUNT_TRUNCATED
)
2159 if (GET_CODE (op1
) == CONST_INT
2160 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2161 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
2162 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
2163 % GET_MODE_BITSIZE (mode
));
2164 else if (GET_CODE (op1
) == SUBREG
2165 && subreg_lowpart_p (op1
))
2166 op1
= SUBREG_REG (op1
);
2169 if (op1
== const0_rtx
)
2172 /* Check whether its cheaper to implement a left shift by a constant
2173 bit count by a sequence of additions. */
2174 if (code
== LSHIFT_EXPR
2175 && GET_CODE (op1
) == CONST_INT
2177 && INTVAL (op1
) < GET_MODE_BITSIZE (mode
)
2178 && shift_cost
[mode
][INTVAL (op1
)] > INTVAL (op1
) * add_cost
[mode
])
2181 for (i
= 0; i
< INTVAL (op1
); i
++)
2183 temp
= force_reg (mode
, shifted
);
2184 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2185 unsignedp
, OPTAB_LIB_WIDEN
);
2190 for (try = 0; temp
== 0 && try < 3; try++)
2192 enum optab_methods methods
;
2195 methods
= OPTAB_DIRECT
;
2197 methods
= OPTAB_WIDEN
;
2199 methods
= OPTAB_LIB_WIDEN
;
2203 /* Widening does not work for rotation. */
2204 if (methods
== OPTAB_WIDEN
)
2206 else if (methods
== OPTAB_LIB_WIDEN
)
2208 /* If we have been unable to open-code this by a rotation,
2209 do it as the IOR of two shifts. I.e., to rotate A
2210 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2211 where C is the bitsize of A.
2213 It is theoretically possible that the target machine might
2214 not be able to perform either shift and hence we would
2215 be making two libcalls rather than just the one for the
2216 shift (similarly if IOR could not be done). We will allow
2217 this extremely unlikely lossage to avoid complicating the
2220 rtx subtarget
= target
== shifted
? 0 : target
;
2222 tree type
= TREE_TYPE (amount
);
2223 tree new_amount
= make_tree (type
, op1
);
2225 = fold_build2 (MINUS_EXPR
, type
,
2226 build_int_cst (type
, GET_MODE_BITSIZE (mode
)),
2229 shifted
= force_reg (mode
, shifted
);
2231 temp
= expand_shift (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2232 mode
, shifted
, new_amount
, 0, 1);
2233 temp1
= expand_shift (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2234 mode
, shifted
, other_amount
, subtarget
, 1);
2235 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2236 unsignedp
, methods
);
2239 temp
= expand_binop (mode
,
2240 left
? rotl_optab
: rotr_optab
,
2241 shifted
, op1
, target
, unsignedp
, methods
);
2244 temp
= expand_binop (mode
,
2245 left
? ashl_optab
: lshr_optab
,
2246 shifted
, op1
, target
, unsignedp
, methods
);
2248 /* Do arithmetic shifts.
2249 Also, if we are going to widen the operand, we can just as well
2250 use an arithmetic right-shift instead of a logical one. */
2251 if (temp
== 0 && ! rotate
2252 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2254 enum optab_methods methods1
= methods
;
2256 /* If trying to widen a log shift to an arithmetic shift,
2257 don't accept an arithmetic shift of the same size. */
2259 methods1
= OPTAB_MUST_WIDEN
;
2261 /* Arithmetic shift */
2263 temp
= expand_binop (mode
,
2264 left
? ashl_optab
: ashr_optab
,
2265 shifted
, op1
, target
, unsignedp
, methods1
);
2268 /* We used to try extzv here for logical right shifts, but that was
2269 only useful for one machine, the VAX, and caused poor code
2270 generation there for lshrdi3, so the code was deleted and a
2271 define_expand for lshrsi3 was added to vax.md. */
2291 /* This structure holds the "cost" of a multiply sequence. The
2292 "cost" field holds the total rtx_cost of every operator in the
2293 synthetic multiplication sequence, hence cost(a op b) is defined
2294 as rtx_cost(op) + cost(a) + cost(b), where cost(leaf) is zero.
2295 The "latency" field holds the minimum possible latency of the
2296 synthetic multiply, on a hypothetical infinitely parallel CPU.
2297 This is the critical path, or the maximum height, of the expression
2298 tree which is the sum of rtx_costs on the most expensive path from
2299 any leaf to the root. Hence latency(a op b) is defined as zero for
2300 leaves and rtx_cost(op) + max(latency(a), latency(b)) otherwise. */
2303 short cost
; /* Total rtx_cost of the multiplication sequence. */
2304 short latency
; /* The latency of the multiplication sequence. */
2307 /* This macro is used to compare a pointer to a mult_cost against an
2308 single integer "rtx_cost" value. This is equivalent to the macro
2309 CHEAPER_MULT_COST(X,Z) where Z = {Y,Y}. */
2310 #define MULT_COST_LESS(X,Y) ((X)->cost < (Y) \
2311 || ((X)->cost == (Y) && (X)->latency < (Y)))
2313 /* This macro is used to compare two pointers to mult_costs against
2314 each other. The macro returns true if X is cheaper than Y.
2315 Currently, the cheaper of two mult_costs is the one with the
2316 lower "cost". If "cost"s are tied, the lower latency is cheaper. */
2317 #define CHEAPER_MULT_COST(X,Y) ((X)->cost < (Y)->cost \
2318 || ((X)->cost == (Y)->cost \
2319 && (X)->latency < (Y)->latency))
2321 /* This structure records a sequence of operations.
2322 `ops' is the number of operations recorded.
2323 `cost' is their total cost.
2324 The operations are stored in `op' and the corresponding
2325 logarithms of the integer coefficients in `log'.
2327 These are the operations:
2328 alg_zero total := 0;
2329 alg_m total := multiplicand;
2330 alg_shift total := total * coeff
2331 alg_add_t_m2 total := total + multiplicand * coeff;
2332 alg_sub_t_m2 total := total - multiplicand * coeff;
2333 alg_add_factor total := total * coeff + total;
2334 alg_sub_factor total := total * coeff - total;
2335 alg_add_t2_m total := total * coeff + multiplicand;
2336 alg_sub_t2_m total := total * coeff - multiplicand;
2338 The first operand must be either alg_zero or alg_m. */
2342 struct mult_cost cost
;
2344 /* The size of the OP and LOG fields are not directly related to the
2345 word size, but the worst-case algorithms will be if we have few
2346 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2347 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2348 in total wordsize operations. */
2349 enum alg_code op
[MAX_BITS_PER_WORD
];
2350 char log
[MAX_BITS_PER_WORD
];
2353 /* The entry for our multiplication cache/hash table. */
2354 struct alg_hash_entry
{
2355 /* The number we are multiplying by. */
2358 /* The mode in which we are multiplying something by T. */
2359 enum machine_mode mode
;
2361 /* The best multiplication algorithm for t. */
2364 /* The cost of multiplication if ALG_CODE is not alg_impossible.
2365 Otherwise, the cost within which multiplication by T is
2367 struct mult_cost cost
;
2370 /* The number of cache/hash entries. */
2371 #define NUM_ALG_HASH_ENTRIES 307
2373 /* Each entry of ALG_HASH caches alg_code for some integer. This is
2374 actually a hash table. If we have a collision, that the older
2375 entry is kicked out. */
2376 static struct alg_hash_entry alg_hash
[NUM_ALG_HASH_ENTRIES
];
2378 /* Indicates the type of fixup needed after a constant multiplication.
2379 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2380 the result should be negated, and ADD_VARIANT means that the
2381 multiplicand should be added to the result. */
2382 enum mult_variant
{basic_variant
, negate_variant
, add_variant
};
2384 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2385 const struct mult_cost
*, enum machine_mode mode
);
2386 static bool choose_mult_variant (enum machine_mode
, HOST_WIDE_INT
,
2387 struct algorithm
*, enum mult_variant
*, int);
2388 static rtx
expand_mult_const (enum machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2389 const struct algorithm
*, enum mult_variant
);
2390 static unsigned HOST_WIDE_INT
choose_multiplier (unsigned HOST_WIDE_INT
, int,
2391 int, rtx
*, int *, int *);
2392 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2393 static rtx
extract_high_half (enum machine_mode
, rtx
);
2394 static rtx
expand_mult_highpart (enum machine_mode
, rtx
, rtx
, rtx
, int, int);
2395 static rtx
expand_mult_highpart_optab (enum machine_mode
, rtx
, rtx
, rtx
,
2397 /* Compute and return the best algorithm for multiplying by T.
2398 The algorithm must cost less than cost_limit
2399 If retval.cost >= COST_LIMIT, no algorithm was found and all
2400 other field of the returned struct are undefined.
2401 MODE is the machine mode of the multiplication. */
2404 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2405 const struct mult_cost
*cost_limit
, enum machine_mode mode
)
2408 struct algorithm
*alg_in
, *best_alg
;
2409 struct mult_cost best_cost
;
2410 struct mult_cost new_limit
;
2411 int op_cost
, op_latency
;
2412 unsigned HOST_WIDE_INT q
;
2413 int maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (mode
));
2415 bool cache_hit
= false;
2416 enum alg_code cache_alg
= alg_zero
;
2418 /* Indicate that no algorithm is yet found. If no algorithm
2419 is found, this value will be returned and indicate failure. */
2420 alg_out
->cost
.cost
= cost_limit
->cost
+ 1;
2421 alg_out
->cost
.latency
= cost_limit
->latency
+ 1;
2423 if (cost_limit
->cost
< 0
2424 || (cost_limit
->cost
== 0 && cost_limit
->latency
<= 0))
2427 /* Restrict the bits of "t" to the multiplication's mode. */
2428 t
&= GET_MODE_MASK (mode
);
2430 /* t == 1 can be done in zero cost. */
2434 alg_out
->cost
.cost
= 0;
2435 alg_out
->cost
.latency
= 0;
2436 alg_out
->op
[0] = alg_m
;
2440 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2444 if (MULT_COST_LESS (cost_limit
, zero_cost
))
2449 alg_out
->cost
.cost
= zero_cost
;
2450 alg_out
->cost
.latency
= zero_cost
;
2451 alg_out
->op
[0] = alg_zero
;
2456 /* We'll be needing a couple extra algorithm structures now. */
2458 alg_in
= alloca (sizeof (struct algorithm
));
2459 best_alg
= alloca (sizeof (struct algorithm
));
2460 best_cost
= *cost_limit
;
2462 /* Compute the hash index. */
2463 hash_index
= (t
^ (unsigned int) mode
) % NUM_ALG_HASH_ENTRIES
;
2465 /* See if we already know what to do for T. */
2466 if (alg_hash
[hash_index
].t
== t
2467 && alg_hash
[hash_index
].mode
== mode
2468 && alg_hash
[hash_index
].alg
!= alg_unknown
)
2470 cache_alg
= alg_hash
[hash_index
].alg
;
2472 if (cache_alg
== alg_impossible
)
2474 /* The cache tells us that it's impossible to synthesize
2475 multiplication by T within alg_hash[hash_index].cost. */
2476 if (!CHEAPER_MULT_COST (&alg_hash
[hash_index
].cost
, cost_limit
))
2477 /* COST_LIMIT is at least as restrictive as the one
2478 recorded in the hash table, in which case we have no
2479 hope of synthesizing a multiplication. Just
2483 /* If we get here, COST_LIMIT is less restrictive than the
2484 one recorded in the hash table, so we may be able to
2485 synthesize a multiplication. Proceed as if we didn't
2486 have the cache entry. */
2490 if (CHEAPER_MULT_COST (cost_limit
, &alg_hash
[hash_index
].cost
))
2491 /* The cached algorithm shows that this multiplication
2492 requires more cost than COST_LIMIT. Just return. This
2493 way, we don't clobber this cache entry with
2494 alg_impossible but retain useful information. */
2506 goto do_alg_addsub_t_m2
;
2508 case alg_add_factor
:
2509 case alg_sub_factor
:
2510 goto do_alg_addsub_factor
;
2513 goto do_alg_add_t2_m
;
2516 goto do_alg_sub_t2_m
;
2524 /* If we have a group of zero bits at the low-order part of T, try
2525 multiplying by the remaining bits and then doing a shift. */
2530 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2534 /* The function expand_shift will choose between a shift and
2535 a sequence of additions, so the observed cost is given as
2536 MIN (m * add_cost[mode], shift_cost[mode][m]). */
2537 op_cost
= m
* add_cost
[mode
];
2538 if (shift_cost
[mode
][m
] < op_cost
)
2539 op_cost
= shift_cost
[mode
][m
];
2540 new_limit
.cost
= best_cost
.cost
- op_cost
;
2541 new_limit
.latency
= best_cost
.latency
- op_cost
;
2542 synth_mult (alg_in
, q
, &new_limit
, mode
);
2544 alg_in
->cost
.cost
+= op_cost
;
2545 alg_in
->cost
.latency
+= op_cost
;
2546 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2548 struct algorithm
*x
;
2549 best_cost
= alg_in
->cost
;
2550 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2551 best_alg
->log
[best_alg
->ops
] = m
;
2552 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2559 /* If we have an odd number, add or subtract one. */
2562 unsigned HOST_WIDE_INT w
;
2565 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2567 /* If T was -1, then W will be zero after the loop. This is another
2568 case where T ends with ...111. Handling this with (T + 1) and
2569 subtract 1 produces slightly better code and results in algorithm
2570 selection much faster than treating it like the ...0111 case
2574 /* Reject the case where t is 3.
2575 Thus we prefer addition in that case. */
2578 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2580 op_cost
= add_cost
[mode
];
2581 new_limit
.cost
= best_cost
.cost
- op_cost
;
2582 new_limit
.latency
= best_cost
.latency
- op_cost
;
2583 synth_mult (alg_in
, t
+ 1, &new_limit
, mode
);
2585 alg_in
->cost
.cost
+= op_cost
;
2586 alg_in
->cost
.latency
+= op_cost
;
2587 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2589 struct algorithm
*x
;
2590 best_cost
= alg_in
->cost
;
2591 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2592 best_alg
->log
[best_alg
->ops
] = 0;
2593 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2598 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2600 op_cost
= add_cost
[mode
];
2601 new_limit
.cost
= best_cost
.cost
- op_cost
;
2602 new_limit
.latency
= best_cost
.latency
- op_cost
;
2603 synth_mult (alg_in
, t
- 1, &new_limit
, mode
);
2605 alg_in
->cost
.cost
+= op_cost
;
2606 alg_in
->cost
.latency
+= op_cost
;
2607 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2609 struct algorithm
*x
;
2610 best_cost
= alg_in
->cost
;
2611 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2612 best_alg
->log
[best_alg
->ops
] = 0;
2613 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2620 /* Look for factors of t of the form
2621 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2622 If we find such a factor, we can multiply by t using an algorithm that
2623 multiplies by q, shift the result by m and add/subtract it to itself.
2625 We search for large factors first and loop down, even if large factors
2626 are less probable than small; if we find a large factor we will find a
2627 good sequence quickly, and therefore be able to prune (by decreasing
2628 COST_LIMIT) the search. */
2630 do_alg_addsub_factor
:
2631 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2633 unsigned HOST_WIDE_INT d
;
2635 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2636 if (t
% d
== 0 && t
> d
&& m
< maxm
2637 && (!cache_hit
|| cache_alg
== alg_add_factor
))
2639 /* If the target has a cheap shift-and-add instruction use
2640 that in preference to a shift insn followed by an add insn.
2641 Assume that the shift-and-add is "atomic" with a latency
2642 equal to its cost, otherwise assume that on superscalar
2643 hardware the shift may be executed concurrently with the
2644 earlier steps in the algorithm. */
2645 op_cost
= add_cost
[mode
] + shift_cost
[mode
][m
];
2646 if (shiftadd_cost
[mode
][m
] < op_cost
)
2648 op_cost
= shiftadd_cost
[mode
][m
];
2649 op_latency
= op_cost
;
2652 op_latency
= add_cost
[mode
];
2654 new_limit
.cost
= best_cost
.cost
- op_cost
;
2655 new_limit
.latency
= best_cost
.latency
- op_latency
;
2656 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2658 alg_in
->cost
.cost
+= op_cost
;
2659 alg_in
->cost
.latency
+= op_latency
;
2660 if (alg_in
->cost
.latency
< op_cost
)
2661 alg_in
->cost
.latency
= op_cost
;
2662 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2664 struct algorithm
*x
;
2665 best_cost
= alg_in
->cost
;
2666 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2667 best_alg
->log
[best_alg
->ops
] = m
;
2668 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2670 /* Other factors will have been taken care of in the recursion. */
2674 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2675 if (t
% d
== 0 && t
> d
&& m
< maxm
2676 && (!cache_hit
|| cache_alg
== alg_sub_factor
))
2678 /* If the target has a cheap shift-and-subtract insn use
2679 that in preference to a shift insn followed by a sub insn.
2680 Assume that the shift-and-sub is "atomic" with a latency
2681 equal to it's cost, otherwise assume that on superscalar
2682 hardware the shift may be executed concurrently with the
2683 earlier steps in the algorithm. */
2684 op_cost
= add_cost
[mode
] + shift_cost
[mode
][m
];
2685 if (shiftsub_cost
[mode
][m
] < op_cost
)
2687 op_cost
= shiftsub_cost
[mode
][m
];
2688 op_latency
= op_cost
;
2691 op_latency
= add_cost
[mode
];
2693 new_limit
.cost
= best_cost
.cost
- op_cost
;
2694 new_limit
.latency
= best_cost
.latency
- op_latency
;
2695 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2697 alg_in
->cost
.cost
+= op_cost
;
2698 alg_in
->cost
.latency
+= op_latency
;
2699 if (alg_in
->cost
.latency
< op_cost
)
2700 alg_in
->cost
.latency
= op_cost
;
2701 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2703 struct algorithm
*x
;
2704 best_cost
= alg_in
->cost
;
2705 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2706 best_alg
->log
[best_alg
->ops
] = m
;
2707 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2715 /* Try shift-and-add (load effective address) instructions,
2716 i.e. do a*3, a*5, a*9. */
2723 if (m
>= 0 && m
< maxm
)
2725 op_cost
= shiftadd_cost
[mode
][m
];
2726 new_limit
.cost
= best_cost
.cost
- op_cost
;
2727 new_limit
.latency
= best_cost
.latency
- op_cost
;
2728 synth_mult (alg_in
, (t
- 1) >> m
, &new_limit
, mode
);
2730 alg_in
->cost
.cost
+= op_cost
;
2731 alg_in
->cost
.latency
+= op_cost
;
2732 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2734 struct algorithm
*x
;
2735 best_cost
= alg_in
->cost
;
2736 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2737 best_alg
->log
[best_alg
->ops
] = m
;
2738 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2748 if (m
>= 0 && m
< maxm
)
2750 op_cost
= shiftsub_cost
[mode
][m
];
2751 new_limit
.cost
= best_cost
.cost
- op_cost
;
2752 new_limit
.latency
= best_cost
.latency
- op_cost
;
2753 synth_mult (alg_in
, (t
+ 1) >> m
, &new_limit
, mode
);
2755 alg_in
->cost
.cost
+= op_cost
;
2756 alg_in
->cost
.latency
+= op_cost
;
2757 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2759 struct algorithm
*x
;
2760 best_cost
= alg_in
->cost
;
2761 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2762 best_alg
->log
[best_alg
->ops
] = m
;
2763 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2771 /* If best_cost has not decreased, we have not found any algorithm. */
2772 if (!CHEAPER_MULT_COST (&best_cost
, cost_limit
))
2774 /* We failed to find an algorithm. Record alg_impossible for
2775 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2776 we are asked to find an algorithm for T within the same or
2777 lower COST_LIMIT, we can immediately return to the
2779 alg_hash
[hash_index
].t
= t
;
2780 alg_hash
[hash_index
].mode
= mode
;
2781 alg_hash
[hash_index
].alg
= alg_impossible
;
2782 alg_hash
[hash_index
].cost
= *cost_limit
;
2786 /* Cache the result. */
2789 alg_hash
[hash_index
].t
= t
;
2790 alg_hash
[hash_index
].mode
= mode
;
2791 alg_hash
[hash_index
].alg
= best_alg
->op
[best_alg
->ops
];
2792 alg_hash
[hash_index
].cost
.cost
= best_cost
.cost
;
2793 alg_hash
[hash_index
].cost
.latency
= best_cost
.latency
;
2796 /* If we are getting a too long sequence for `struct algorithm'
2797 to record, make this search fail. */
2798 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2801 /* Copy the algorithm from temporary space to the space at alg_out.
2802 We avoid using structure assignment because the majority of
2803 best_alg is normally undefined, and this is a critical function. */
2804 alg_out
->ops
= best_alg
->ops
+ 1;
2805 alg_out
->cost
= best_cost
;
2806 memcpy (alg_out
->op
, best_alg
->op
,
2807 alg_out
->ops
* sizeof *alg_out
->op
);
2808 memcpy (alg_out
->log
, best_alg
->log
,
2809 alg_out
->ops
* sizeof *alg_out
->log
);
2812 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2813 Try three variations:
2815 - a shift/add sequence based on VAL itself
2816 - a shift/add sequence based on -VAL, followed by a negation
2817 - a shift/add sequence based on VAL - 1, followed by an addition.
2819 Return true if the cheapest of these cost less than MULT_COST,
2820 describing the algorithm in *ALG and final fixup in *VARIANT. */
2823 choose_mult_variant (enum machine_mode mode
, HOST_WIDE_INT val
,
2824 struct algorithm
*alg
, enum mult_variant
*variant
,
2827 struct algorithm alg2
;
2828 struct mult_cost limit
;
2831 *variant
= basic_variant
;
2832 limit
.cost
= mult_cost
;
2833 limit
.latency
= mult_cost
;
2834 synth_mult (alg
, val
, &limit
, mode
);
2836 /* This works only if the inverted value actually fits in an
2838 if (HOST_BITS_PER_INT
>= GET_MODE_BITSIZE (mode
))
2840 op_cost
= neg_cost
[mode
];
2841 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2843 limit
.cost
= alg
->cost
.cost
- op_cost
;
2844 limit
.latency
= alg
->cost
.latency
- op_cost
;
2848 limit
.cost
= mult_cost
- op_cost
;
2849 limit
.latency
= mult_cost
- op_cost
;
2852 synth_mult (&alg2
, -val
, &limit
, mode
);
2853 alg2
.cost
.cost
+= op_cost
;
2854 alg2
.cost
.latency
+= op_cost
;
2855 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2856 *alg
= alg2
, *variant
= negate_variant
;
2859 /* This proves very useful for division-by-constant. */
2860 op_cost
= add_cost
[mode
];
2861 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2863 limit
.cost
= alg
->cost
.cost
- op_cost
;
2864 limit
.latency
= alg
->cost
.latency
- op_cost
;
2868 limit
.cost
= mult_cost
- op_cost
;
2869 limit
.latency
= mult_cost
- op_cost
;
2872 synth_mult (&alg2
, val
- 1, &limit
, mode
);
2873 alg2
.cost
.cost
+= op_cost
;
2874 alg2
.cost
.latency
+= op_cost
;
2875 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2876 *alg
= alg2
, *variant
= add_variant
;
2878 return MULT_COST_LESS (&alg
->cost
, mult_cost
);
2881 /* A subroutine of expand_mult, used for constant multiplications.
2882 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2883 convenient. Use the shift/add sequence described by ALG and apply
2884 the final fixup specified by VARIANT. */
2887 expand_mult_const (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
2888 rtx target
, const struct algorithm
*alg
,
2889 enum mult_variant variant
)
2891 HOST_WIDE_INT val_so_far
;
2892 rtx insn
, accum
, tem
;
2894 enum machine_mode nmode
;
2896 /* Avoid referencing memory over and over.
2897 For speed, but also for correctness when mem is volatile. */
2899 op0
= force_reg (mode
, op0
);
2901 /* ACCUM starts out either as OP0 or as a zero, depending on
2902 the first operation. */
2904 if (alg
->op
[0] == alg_zero
)
2906 accum
= copy_to_mode_reg (mode
, const0_rtx
);
2909 else if (alg
->op
[0] == alg_m
)
2911 accum
= copy_to_mode_reg (mode
, op0
);
2917 for (opno
= 1; opno
< alg
->ops
; opno
++)
2919 int log
= alg
->log
[opno
];
2920 rtx shift_subtarget
= optimize
? 0 : accum
;
2922 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
2925 rtx accum_target
= optimize
? 0 : accum
;
2927 switch (alg
->op
[opno
])
2930 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2931 build_int_cst (NULL_TREE
, log
),
2937 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2938 build_int_cst (NULL_TREE
, log
),
2940 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2941 add_target
? add_target
: accum_target
);
2942 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2946 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2947 build_int_cst (NULL_TREE
, log
),
2949 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2950 add_target
? add_target
: accum_target
);
2951 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2955 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2956 build_int_cst (NULL_TREE
, log
),
2959 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2960 add_target
? add_target
: accum_target
);
2961 val_so_far
= (val_so_far
<< log
) + 1;
2965 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2966 build_int_cst (NULL_TREE
, log
),
2967 shift_subtarget
, 0);
2968 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2969 add_target
? add_target
: accum_target
);
2970 val_so_far
= (val_so_far
<< log
) - 1;
2973 case alg_add_factor
:
2974 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2975 build_int_cst (NULL_TREE
, log
),
2977 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2978 add_target
? add_target
: accum_target
);
2979 val_so_far
+= val_so_far
<< log
;
2982 case alg_sub_factor
:
2983 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2984 build_int_cst (NULL_TREE
, log
),
2986 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2988 ? add_target
: (optimize
? 0 : tem
)));
2989 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2996 /* Write a REG_EQUAL note on the last insn so that we can cse
2997 multiplication sequences. Note that if ACCUM is a SUBREG,
2998 we've set the inner register and must properly indicate
3001 tem
= op0
, nmode
= mode
;
3002 if (GET_CODE (accum
) == SUBREG
)
3004 nmode
= GET_MODE (SUBREG_REG (accum
));
3005 tem
= gen_lowpart (nmode
, op0
);
3008 insn
= get_last_insn ();
3009 set_unique_reg_note (insn
, REG_EQUAL
,
3010 gen_rtx_MULT (nmode
, tem
, GEN_INT (val_so_far
)));
3013 if (variant
== negate_variant
)
3015 val_so_far
= -val_so_far
;
3016 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
3018 else if (variant
== add_variant
)
3020 val_so_far
= val_so_far
+ 1;
3021 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
3024 /* Compare only the bits of val and val_so_far that are significant
3025 in the result mode, to avoid sign-/zero-extension confusion. */
3026 val
&= GET_MODE_MASK (mode
);
3027 val_so_far
&= GET_MODE_MASK (mode
);
3028 gcc_assert (val
== val_so_far
);
3033 /* Perform a multiplication and return an rtx for the result.
3034 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3035 TARGET is a suggestion for where to store the result (an rtx).
3037 We check specially for a constant integer as OP1.
3038 If you want this check for OP0 as well, then before calling
3039 you should swap the two operands if OP0 would be constant. */
3042 expand_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3045 enum mult_variant variant
;
3046 struct algorithm algorithm
;
3049 /* Handling const0_rtx here allows us to use zero as a rogue value for
3051 if (op1
== const0_rtx
)
3053 if (op1
== const1_rtx
)
3055 if (op1
== constm1_rtx
)
3056 return expand_unop (mode
,
3057 GET_MODE_CLASS (mode
) == MODE_INT
3058 && !unsignedp
&& flag_trapv
3059 ? negv_optab
: neg_optab
,
3062 /* These are the operations that are potentially turned into a sequence
3063 of shifts and additions. */
3064 if (SCALAR_INT_MODE_P (mode
)
3065 && (unsignedp
|| !flag_trapv
))
3067 HOST_WIDE_INT coeff
= 0;
3068 rtx fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3070 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3071 less than or equal in size to `unsigned int' this doesn't matter.
3072 If the mode is larger than `unsigned int', then synth_mult works
3073 only if the constant value exactly fits in an `unsigned int' without
3074 any truncation. This means that multiplying by negative values does
3075 not work; results are off by 2^32 on a 32 bit machine. */
3077 if (GET_CODE (op1
) == CONST_INT
)
3079 /* Attempt to handle multiplication of DImode values by negative
3080 coefficients, by performing the multiplication by a positive
3081 multiplier and then inverting the result. */
3082 if (INTVAL (op1
) < 0
3083 && GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
3085 /* Its safe to use -INTVAL (op1) even for INT_MIN, as the
3086 result is interpreted as an unsigned coefficient.
3087 Exclude cost of op0 from max_cost to match the cost
3088 calculation of the synth_mult. */
3089 max_cost
= rtx_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), SET
)
3092 && choose_mult_variant (mode
, -INTVAL (op1
), &algorithm
,
3093 &variant
, max_cost
))
3095 rtx temp
= expand_mult_const (mode
, op0
, -INTVAL (op1
),
3096 NULL_RTX
, &algorithm
,
3098 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3101 else coeff
= INTVAL (op1
);
3103 else if (GET_CODE (op1
) == CONST_DOUBLE
)
3105 /* If we are multiplying in DImode, it may still be a win
3106 to try to work with shifts and adds. */
3107 if (CONST_DOUBLE_HIGH (op1
) == 0)
3108 coeff
= CONST_DOUBLE_LOW (op1
);
3109 else if (CONST_DOUBLE_LOW (op1
) == 0
3110 && EXACT_POWER_OF_2_OR_ZERO_P (CONST_DOUBLE_HIGH (op1
)))
3112 int shift
= floor_log2 (CONST_DOUBLE_HIGH (op1
))
3113 + HOST_BITS_PER_WIDE_INT
;
3114 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3115 build_int_cst (NULL_TREE
, shift
),
3120 /* We used to test optimize here, on the grounds that it's better to
3121 produce a smaller program when -O is not used. But this causes
3122 such a terrible slowdown sometimes that it seems better to always
3126 /* Special case powers of two. */
3127 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3128 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3129 build_int_cst (NULL_TREE
, floor_log2 (coeff
)),
3132 /* Exclude cost of op0 from max_cost to match the cost
3133 calculation of the synth_mult. */
3134 max_cost
= rtx_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), SET
);
3135 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3137 return expand_mult_const (mode
, op0
, coeff
, target
,
3138 &algorithm
, variant
);
3142 if (GET_CODE (op0
) == CONST_DOUBLE
)
3149 /* Expand x*2.0 as x+x. */
3150 if (GET_CODE (op1
) == CONST_DOUBLE
3151 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3154 REAL_VALUE_FROM_CONST_DOUBLE (d
, op1
);
3156 if (REAL_VALUES_EQUAL (d
, dconst2
))
3158 op0
= force_reg (GET_MODE (op0
), op0
);
3159 return expand_binop (mode
, add_optab
, op0
, op0
,
3160 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3164 /* This used to use umul_optab if unsigned, but for non-widening multiply
3165 there is no difference between signed and unsigned. */
3166 op0
= expand_binop (mode
,
3168 && flag_trapv
&& (GET_MODE_CLASS(mode
) == MODE_INT
)
3169 ? smulv_optab
: smul_optab
,
3170 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
3175 /* Return the smallest n such that 2**n >= X. */
3178 ceil_log2 (unsigned HOST_WIDE_INT x
)
3180 return floor_log2 (x
- 1) + 1;
3183 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3184 replace division by D, and put the least significant N bits of the result
3185 in *MULTIPLIER_PTR and return the most significant bit.
3187 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3188 needed precision is in PRECISION (should be <= N).
3190 PRECISION should be as small as possible so this function can choose
3191 multiplier more freely.
3193 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3194 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3196 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3197 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3200 unsigned HOST_WIDE_INT
3201 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
3202 rtx
*multiplier_ptr
, int *post_shift_ptr
, int *lgup_ptr
)
3204 HOST_WIDE_INT mhigh_hi
, mlow_hi
;
3205 unsigned HOST_WIDE_INT mhigh_lo
, mlow_lo
;
3206 int lgup
, post_shift
;
3208 unsigned HOST_WIDE_INT nl
, dummy1
;
3209 HOST_WIDE_INT nh
, dummy2
;
3211 /* lgup = ceil(log2(divisor)); */
3212 lgup
= ceil_log2 (d
);
3214 gcc_assert (lgup
<= n
);
3217 pow2
= n
+ lgup
- precision
;
3219 /* We could handle this with some effort, but this case is much
3220 better handled directly with a scc insn, so rely on caller using
3222 gcc_assert (pow
!= 2 * HOST_BITS_PER_WIDE_INT
);
3224 /* mlow = 2^(N + lgup)/d */
3225 if (pow
>= HOST_BITS_PER_WIDE_INT
)
3227 nh
= (HOST_WIDE_INT
) 1 << (pow
- HOST_BITS_PER_WIDE_INT
);
3233 nl
= (unsigned HOST_WIDE_INT
) 1 << pow
;
3235 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
3236 &mlow_lo
, &mlow_hi
, &dummy1
, &dummy2
);
3238 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
3239 if (pow2
>= HOST_BITS_PER_WIDE_INT
)
3240 nh
|= (HOST_WIDE_INT
) 1 << (pow2
- HOST_BITS_PER_WIDE_INT
);
3242 nl
|= (unsigned HOST_WIDE_INT
) 1 << pow2
;
3243 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
3244 &mhigh_lo
, &mhigh_hi
, &dummy1
, &dummy2
);
3246 gcc_assert (!mhigh_hi
|| nh
- d
< d
);
3247 gcc_assert (mhigh_hi
<= 1 && mlow_hi
<= 1);
3248 /* Assert that mlow < mhigh. */
3249 gcc_assert (mlow_hi
< mhigh_hi
3250 || (mlow_hi
== mhigh_hi
&& mlow_lo
< mhigh_lo
));
3252 /* If precision == N, then mlow, mhigh exceed 2^N
3253 (but they do not exceed 2^(N+1)). */
3255 /* Reduce to lowest terms. */
3256 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
3258 unsigned HOST_WIDE_INT ml_lo
= (mlow_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mlow_lo
>> 1);
3259 unsigned HOST_WIDE_INT mh_lo
= (mhigh_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mhigh_lo
>> 1);
3269 *post_shift_ptr
= post_shift
;
3271 if (n
< HOST_BITS_PER_WIDE_INT
)
3273 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
3274 *multiplier_ptr
= GEN_INT (mhigh_lo
& mask
);
3275 return mhigh_lo
>= mask
;
3279 *multiplier_ptr
= GEN_INT (mhigh_lo
);
3284 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3285 congruent to 1 (mod 2**N). */
3287 static unsigned HOST_WIDE_INT
3288 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
3290 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3292 /* The algorithm notes that the choice y = x satisfies
3293 x*y == 1 mod 2^3, since x is assumed odd.
3294 Each iteration doubles the number of bits of significance in y. */
3296 unsigned HOST_WIDE_INT mask
;
3297 unsigned HOST_WIDE_INT y
= x
;
3300 mask
= (n
== HOST_BITS_PER_WIDE_INT
3301 ? ~(unsigned HOST_WIDE_INT
) 0
3302 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
3306 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
3312 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3313 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3314 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3315 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3318 The result is put in TARGET if that is convenient.
3320 MODE is the mode of operation. */
3323 expand_mult_highpart_adjust (enum machine_mode mode
, rtx adj_operand
, rtx op0
,
3324 rtx op1
, rtx target
, int unsignedp
)
3327 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
3329 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3330 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
) - 1),
3332 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
3334 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3337 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
3338 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
) - 1),
3340 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
3341 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3347 /* Subroutine of expand_mult_highpart. Return the MODE high part of OP. */
3350 extract_high_half (enum machine_mode mode
, rtx op
)
3352 enum machine_mode wider_mode
;
3354 if (mode
== word_mode
)
3355 return gen_highpart (mode
, op
);
3357 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3358 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
3359 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
)), 0, 1);
3360 return convert_modes (mode
, wider_mode
, op
, 0);
3363 /* Like expand_mult_highpart, but only consider using a multiplication
3364 optab. OP1 is an rtx for the constant operand. */
3367 expand_mult_highpart_optab (enum machine_mode mode
, rtx op0
, rtx op1
,
3368 rtx target
, int unsignedp
, int max_cost
)
3370 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
3371 enum machine_mode wider_mode
;
3376 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3377 size
= GET_MODE_BITSIZE (mode
);
3379 /* Firstly, try using a multiplication insn that only generates the needed
3380 high part of the product, and in the sign flavor of unsignedp. */
3381 if (mul_highpart_cost
[mode
] < max_cost
)
3383 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
3384 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3385 unsignedp
, OPTAB_DIRECT
);
3390 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3391 Need to adjust the result after the multiplication. */
3392 if (size
- 1 < BITS_PER_WORD
3393 && (mul_highpart_cost
[mode
] + 2 * shift_cost
[mode
][size
-1]
3394 + 4 * add_cost
[mode
] < max_cost
))
3396 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
3397 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3398 unsignedp
, OPTAB_DIRECT
);
3400 /* We used the wrong signedness. Adjust the result. */
3401 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3405 /* Try widening multiplication. */
3406 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
3407 if (moptab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3408 && mul_widen_cost
[wider_mode
] < max_cost
)
3410 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
3411 unsignedp
, OPTAB_WIDEN
);
3413 return extract_high_half (mode
, tem
);
3416 /* Try widening the mode and perform a non-widening multiplication. */
3417 if (smul_optab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3418 && size
- 1 < BITS_PER_WORD
3419 && mul_cost
[wider_mode
] + shift_cost
[mode
][size
-1] < max_cost
)
3421 rtx insns
, wop0
, wop1
;
3423 /* We need to widen the operands, for example to ensure the
3424 constant multiplier is correctly sign or zero extended.
3425 Use a sequence to clean-up any instructions emitted by
3426 the conversions if things don't work out. */
3428 wop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
3429 wop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
3430 tem
= expand_binop (wider_mode
, smul_optab
, wop0
, wop1
, 0,
3431 unsignedp
, OPTAB_WIDEN
);
3432 insns
= get_insns ();
3438 return extract_high_half (mode
, tem
);
3442 /* Try widening multiplication of opposite signedness, and adjust. */
3443 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3444 if (moptab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3445 && size
- 1 < BITS_PER_WORD
3446 && (mul_widen_cost
[wider_mode
] + 2 * shift_cost
[mode
][size
-1]
3447 + 4 * add_cost
[mode
] < max_cost
))
3449 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3450 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3453 tem
= extract_high_half (mode
, tem
);
3454 /* We used the wrong signedness. Adjust the result. */
3455 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3463 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3464 putting the high half of the result in TARGET if that is convenient,
3465 and return where the result is. If the operation can not be performed,
3468 MODE is the mode of operation and result.
3470 UNSIGNEDP nonzero means unsigned multiply.
3472 MAX_COST is the total allowed cost for the expanded RTL. */
3475 expand_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
3476 rtx target
, int unsignedp
, int max_cost
)
3478 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
3479 unsigned HOST_WIDE_INT cnst1
;
3481 bool sign_adjust
= false;
3482 enum mult_variant variant
;
3483 struct algorithm alg
;
3486 /* We can't support modes wider than HOST_BITS_PER_INT. */
3487 gcc_assert (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
);
3489 cnst1
= INTVAL (op1
) & GET_MODE_MASK (mode
);
3491 /* We can't optimize modes wider than BITS_PER_WORD.
3492 ??? We might be able to perform double-word arithmetic if
3493 mode == word_mode, however all the cost calculations in
3494 synth_mult etc. assume single-word operations. */
3495 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3496 return expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3497 unsignedp
, max_cost
);
3499 extra_cost
= shift_cost
[mode
][GET_MODE_BITSIZE (mode
) - 1];
3501 /* Check whether we try to multiply by a negative constant. */
3502 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3505 extra_cost
+= add_cost
[mode
];
3508 /* See whether shift/add multiplication is cheap enough. */
3509 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3510 max_cost
- extra_cost
))
3512 /* See whether the specialized multiplication optabs are
3513 cheaper than the shift/add version. */
3514 tem
= expand_mult_highpart_optab (mode
, op0
, op1
, target
, unsignedp
,
3515 alg
.cost
.cost
+ extra_cost
);
3519 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3520 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3521 tem
= extract_high_half (mode
, tem
);
3523 /* Adjust result for signedness. */
3525 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3529 return expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3530 unsignedp
, max_cost
);
3534 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3537 expand_smod_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3539 unsigned HOST_WIDE_INT masklow
, maskhigh
;
3540 rtx result
, temp
, shift
, label
;
3543 logd
= floor_log2 (d
);
3544 result
= gen_reg_rtx (mode
);
3546 /* Avoid conditional branches when they're expensive. */
3547 if (BRANCH_COST
>= 2
3550 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3554 signmask
= force_reg (mode
, signmask
);
3555 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3556 shift
= GEN_INT (GET_MODE_BITSIZE (mode
) - logd
);
3558 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3559 which instruction sequence to use. If logical right shifts
3560 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3561 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3563 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3564 if (lshr_optab
->handlers
[mode
].insn_code
== CODE_FOR_nothing
3565 || rtx_cost (temp
, SET
) > COSTS_N_INSNS (2))
3567 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3568 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3569 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3570 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3571 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (masklow
),
3572 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3573 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3574 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3575 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3576 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3580 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3581 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3582 signmask
= force_reg (mode
, signmask
);
3584 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3585 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3586 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (masklow
),
3587 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3588 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3589 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3595 /* Mask contains the mode's signbit and the significant bits of the
3596 modulus. By including the signbit in the operation, many targets
3597 can avoid an explicit compare operation in the following comparison
3600 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3601 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3603 masklow
|= (HOST_WIDE_INT
) -1 << (GET_MODE_BITSIZE (mode
) - 1);
3607 maskhigh
= (HOST_WIDE_INT
) -1
3608 << (GET_MODE_BITSIZE (mode
) - HOST_BITS_PER_WIDE_INT
- 1);
3610 temp
= expand_binop (mode
, and_optab
, op0
,
3611 immed_double_const (masklow
, maskhigh
, mode
),
3612 result
, 1, OPTAB_LIB_WIDEN
);
3614 emit_move_insn (result
, temp
);
3616 label
= gen_label_rtx ();
3617 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
3619 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
3620 0, OPTAB_LIB_WIDEN
);
3621 masklow
= (HOST_WIDE_INT
) -1 << logd
;
3623 temp
= expand_binop (mode
, ior_optab
, temp
,
3624 immed_double_const (masklow
, maskhigh
, mode
),
3625 result
, 1, OPTAB_LIB_WIDEN
);
3626 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
3627 0, OPTAB_LIB_WIDEN
);
3629 emit_move_insn (result
, temp
);
3634 /* Expand signed division of OP0 by a power of two D in mode MODE.
3635 This routine is only called for positive values of D. */
3638 expand_sdiv_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3644 logd
= floor_log2 (d
);
3645 shift
= build_int_cst (NULL_TREE
, logd
);
3647 if (d
== 2 && BRANCH_COST
>= 1)
3649 temp
= gen_reg_rtx (mode
);
3650 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
3651 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3652 0, OPTAB_LIB_WIDEN
);
3653 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3656 #ifdef HAVE_conditional_move
3657 if (BRANCH_COST
>= 2)
3661 /* ??? emit_conditional_move forces a stack adjustment via
3662 compare_from_rtx so, if the sequence is discarded, it will
3663 be lost. Do it now instead. */
3664 do_pending_stack_adjust ();
3667 temp2
= copy_to_mode_reg (mode
, op0
);
3668 temp
= expand_binop (mode
, add_optab
, temp2
, GEN_INT (d
-1),
3669 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3670 temp
= force_reg (mode
, temp
);
3672 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3673 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
3674 mode
, temp
, temp2
, mode
, 0);
3677 rtx seq
= get_insns ();
3680 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, shift
, NULL_RTX
, 0);
3686 if (BRANCH_COST
>= 2)
3688 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
3690 temp
= gen_reg_rtx (mode
);
3691 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
3692 if (shift_cost
[mode
][ushift
] > COSTS_N_INSNS (1))
3693 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (d
- 1),
3694 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3696 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
3697 build_int_cst (NULL_TREE
, ushift
),
3699 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3700 0, OPTAB_LIB_WIDEN
);
3701 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3704 label
= gen_label_rtx ();
3705 temp
= copy_to_mode_reg (mode
, op0
);
3706 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
3707 expand_inc (temp
, GEN_INT (d
- 1));
3709 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3712 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3713 if that is convenient, and returning where the result is.
3714 You may request either the quotient or the remainder as the result;
3715 specify REM_FLAG nonzero to get the remainder.
3717 CODE is the expression code for which kind of division this is;
3718 it controls how rounding is done. MODE is the machine mode to use.
3719 UNSIGNEDP nonzero means do unsigned division. */
3721 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3722 and then correct it by or'ing in missing high bits
3723 if result of ANDI is nonzero.
3724 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3725 This could optimize to a bfexts instruction.
3726 But C doesn't use these operations, so their optimizations are
3728 /* ??? For modulo, we don't actually need the highpart of the first product,
3729 the low part will do nicely. And for small divisors, the second multiply
3730 can also be a low-part only multiply or even be completely left out.
3731 E.g. to calculate the remainder of a division by 3 with a 32 bit
3732 multiply, multiply with 0x55555556 and extract the upper two bits;
3733 the result is exact for inputs up to 0x1fffffff.
3734 The input range can be reduced by using cross-sum rules.
3735 For odd divisors >= 3, the following table gives right shift counts
3736 so that if a number is shifted by an integer multiple of the given
3737 amount, the remainder stays the same:
3738 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3739 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3740 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3741 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3742 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3744 Cross-sum rules for even numbers can be derived by leaving as many bits
3745 to the right alone as the divisor has zeros to the right.
3746 E.g. if x is an unsigned 32 bit number:
3747 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3751 expand_divmod (int rem_flag
, enum tree_code code
, enum machine_mode mode
,
3752 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
3754 enum machine_mode compute_mode
;
3756 rtx quotient
= 0, remainder
= 0;
3760 optab optab1
, optab2
;
3761 int op1_is_constant
, op1_is_pow2
= 0;
3762 int max_cost
, extra_cost
;
3763 static HOST_WIDE_INT last_div_const
= 0;
3764 static HOST_WIDE_INT ext_op1
;
3766 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3767 if (op1_is_constant
)
3769 ext_op1
= INTVAL (op1
);
3771 ext_op1
&= GET_MODE_MASK (mode
);
3772 op1_is_pow2
= ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1
)
3773 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1
))));
3777 This is the structure of expand_divmod:
3779 First comes code to fix up the operands so we can perform the operations
3780 correctly and efficiently.
3782 Second comes a switch statement with code specific for each rounding mode.
3783 For some special operands this code emits all RTL for the desired
3784 operation, for other cases, it generates only a quotient and stores it in
3785 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3786 to indicate that it has not done anything.
3788 Last comes code that finishes the operation. If QUOTIENT is set and
3789 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3790 QUOTIENT is not set, it is computed using trunc rounding.
3792 We try to generate special code for division and remainder when OP1 is a
3793 constant. If |OP1| = 2**n we can use shifts and some other fast
3794 operations. For other values of OP1, we compute a carefully selected
3795 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3798 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3799 half of the product. Different strategies for generating the product are
3800 implemented in expand_mult_highpart.
3802 If what we actually want is the remainder, we generate that by another
3803 by-constant multiplication and a subtraction. */
3805 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3806 code below will malfunction if we are, so check here and handle
3807 the special case if so. */
3808 if (op1
== const1_rtx
)
3809 return rem_flag
? const0_rtx
: op0
;
3811 /* When dividing by -1, we could get an overflow.
3812 negv_optab can handle overflows. */
3813 if (! unsignedp
&& op1
== constm1_rtx
)
3817 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
3818 ? negv_optab
: neg_optab
, op0
, target
, 0);
3822 /* Don't use the function value register as a target
3823 since we have to read it as well as write it,
3824 and function-inlining gets confused by this. */
3825 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3826 /* Don't clobber an operand while doing a multi-step calculation. */
3827 || ((rem_flag
|| op1_is_constant
)
3828 && (reg_mentioned_p (target
, op0
)
3829 || (MEM_P (op0
) && MEM_P (target
))))
3830 || reg_mentioned_p (target
, op1
)
3831 || (MEM_P (op1
) && MEM_P (target
))))
3834 /* Get the mode in which to perform this computation. Normally it will
3835 be MODE, but sometimes we can't do the desired operation in MODE.
3836 If so, pick a wider mode in which we can do the operation. Convert
3837 to that mode at the start to avoid repeated conversions.
3839 First see what operations we need. These depend on the expression
3840 we are evaluating. (We assume that divxx3 insns exist under the
3841 same conditions that modxx3 insns and that these insns don't normally
3842 fail. If these assumptions are not correct, we may generate less
3843 efficient code in some cases.)
3845 Then see if we find a mode in which we can open-code that operation
3846 (either a division, modulus, or shift). Finally, check for the smallest
3847 mode for which we can do the operation with a library call. */
3849 /* We might want to refine this now that we have division-by-constant
3850 optimization. Since expand_mult_highpart tries so many variants, it is
3851 not straightforward to generalize this. Maybe we should make an array
3852 of possible modes in init_expmed? Save this for GCC 2.7. */
3854 optab1
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3855 ? (unsignedp
? lshr_optab
: ashr_optab
)
3856 : (unsignedp
? udiv_optab
: sdiv_optab
));
3857 optab2
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3859 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
3861 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3862 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3863 if (optab1
->handlers
[compute_mode
].insn_code
!= CODE_FOR_nothing
3864 || optab2
->handlers
[compute_mode
].insn_code
!= CODE_FOR_nothing
)
3867 if (compute_mode
== VOIDmode
)
3868 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3869 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3870 if (optab1
->handlers
[compute_mode
].libfunc
3871 || optab2
->handlers
[compute_mode
].libfunc
)
3874 /* If we still couldn't find a mode, use MODE, but expand_binop will
3876 if (compute_mode
== VOIDmode
)
3877 compute_mode
= mode
;
3879 if (target
&& GET_MODE (target
) == compute_mode
)
3882 tquotient
= gen_reg_rtx (compute_mode
);
3884 size
= GET_MODE_BITSIZE (compute_mode
);
3886 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3887 (mode), and thereby get better code when OP1 is a constant. Do that
3888 later. It will require going over all usages of SIZE below. */
3889 size
= GET_MODE_BITSIZE (mode
);
3892 /* Only deduct something for a REM if the last divide done was
3893 for a different constant. Then set the constant of the last
3895 max_cost
= div_cost
[compute_mode
]
3896 - (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3897 && INTVAL (op1
) == last_div_const
)
3898 ? mul_cost
[compute_mode
] + add_cost
[compute_mode
]
3901 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3903 /* Now convert to the best mode to use. */
3904 if (compute_mode
!= mode
)
3906 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3907 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3909 /* convert_modes may have placed op1 into a register, so we
3910 must recompute the following. */
3911 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3912 op1_is_pow2
= (op1_is_constant
3913 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3915 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
)))))) ;
3918 /* If one of the operands is a volatile MEM, copy it into a register. */
3920 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
3921 op0
= force_reg (compute_mode
, op0
);
3922 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
3923 op1
= force_reg (compute_mode
, op1
);
3925 /* If we need the remainder or if OP1 is constant, we need to
3926 put OP0 in a register in case it has any queued subexpressions. */
3927 if (rem_flag
|| op1_is_constant
)
3928 op0
= force_reg (compute_mode
, op0
);
3930 last
= get_last_insn ();
3932 /* Promote floor rounding to trunc rounding for unsigned operations. */
3935 if (code
== FLOOR_DIV_EXPR
)
3936 code
= TRUNC_DIV_EXPR
;
3937 if (code
== FLOOR_MOD_EXPR
)
3938 code
= TRUNC_MOD_EXPR
;
3939 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
3940 code
= TRUNC_DIV_EXPR
;
3943 if (op1
!= const0_rtx
)
3946 case TRUNC_MOD_EXPR
:
3947 case TRUNC_DIV_EXPR
:
3948 if (op1_is_constant
)
3952 unsigned HOST_WIDE_INT mh
;
3953 int pre_shift
, post_shift
;
3956 unsigned HOST_WIDE_INT d
= (INTVAL (op1
)
3957 & GET_MODE_MASK (compute_mode
));
3959 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3961 pre_shift
= floor_log2 (d
);
3965 = expand_binop (compute_mode
, and_optab
, op0
,
3966 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3970 return gen_lowpart (mode
, remainder
);
3972 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3973 build_int_cst (NULL_TREE
,
3977 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3979 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
3981 /* Most significant bit of divisor is set; emit an scc
3983 quotient
= emit_store_flag (tquotient
, GEU
, op0
, op1
,
3984 compute_mode
, 1, 1);
3990 /* Find a suitable multiplier and right shift count
3991 instead of multiplying with D. */
3993 mh
= choose_multiplier (d
, size
, size
,
3994 &ml
, &post_shift
, &dummy
);
3996 /* If the suggested multiplier is more than SIZE bits,
3997 we can do better for even divisors, using an
3998 initial right shift. */
3999 if (mh
!= 0 && (d
& 1) == 0)
4001 pre_shift
= floor_log2 (d
& -d
);
4002 mh
= choose_multiplier (d
>> pre_shift
, size
,
4004 &ml
, &post_shift
, &dummy
);
4014 if (post_shift
- 1 >= BITS_PER_WORD
)
4018 = (shift_cost
[compute_mode
][post_shift
- 1]
4019 + shift_cost
[compute_mode
][1]
4020 + 2 * add_cost
[compute_mode
]);
4021 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
4023 max_cost
- extra_cost
);
4026 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
4030 (RSHIFT_EXPR
, compute_mode
, t2
,
4031 build_int_cst (NULL_TREE
, 1),
4033 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
4036 quotient
= expand_shift
4037 (RSHIFT_EXPR
, compute_mode
, t4
,
4038 build_int_cst (NULL_TREE
, post_shift
- 1),
4045 if (pre_shift
>= BITS_PER_WORD
4046 || post_shift
>= BITS_PER_WORD
)
4050 (RSHIFT_EXPR
, compute_mode
, op0
,
4051 build_int_cst (NULL_TREE
, pre_shift
),
4054 = (shift_cost
[compute_mode
][pre_shift
]
4055 + shift_cost
[compute_mode
][post_shift
]);
4056 t2
= expand_mult_highpart (compute_mode
, t1
, ml
,
4058 max_cost
- extra_cost
);
4061 quotient
= expand_shift
4062 (RSHIFT_EXPR
, compute_mode
, t2
,
4063 build_int_cst (NULL_TREE
, post_shift
),
4068 else /* Too wide mode to use tricky code */
4071 insn
= get_last_insn ();
4073 && (set
= single_set (insn
)) != 0
4074 && SET_DEST (set
) == quotient
)
4075 set_unique_reg_note (insn
,
4077 gen_rtx_UDIV (compute_mode
, op0
, op1
));
4079 else /* TRUNC_DIV, signed */
4081 unsigned HOST_WIDE_INT ml
;
4082 int lgup
, post_shift
;
4084 HOST_WIDE_INT d
= INTVAL (op1
);
4085 unsigned HOST_WIDE_INT abs_d
= d
>= 0 ? d
: -d
;
4087 /* n rem d = n rem -d */
4088 if (rem_flag
&& d
< 0)
4091 op1
= gen_int_mode (abs_d
, compute_mode
);
4097 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
4099 else if (abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4101 /* This case is not handled correctly below. */
4102 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
4103 compute_mode
, 1, 1);
4107 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
4108 && (rem_flag
? smod_pow2_cheap
[compute_mode
]
4109 : sdiv_pow2_cheap
[compute_mode
])
4110 /* We assume that cheap metric is true if the
4111 optab has an expander for this mode. */
4112 && (((rem_flag
? smod_optab
: sdiv_optab
)
4113 ->handlers
[compute_mode
].insn_code
4114 != CODE_FOR_nothing
)
4115 || (sdivmod_optab
->handlers
[compute_mode
]
4116 .insn_code
!= CODE_FOR_nothing
)))
4118 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
4122 remainder
= expand_smod_pow2 (compute_mode
, op0
, d
);
4124 return gen_lowpart (mode
, remainder
);
4127 if (sdiv_pow2_cheap
[compute_mode
]
4128 && ((sdiv_optab
->handlers
[compute_mode
].insn_code
4129 != CODE_FOR_nothing
)
4130 || (sdivmod_optab
->handlers
[compute_mode
].insn_code
4131 != CODE_FOR_nothing
)))
4132 quotient
= expand_divmod (0, TRUNC_DIV_EXPR
,
4134 gen_int_mode (abs_d
,
4138 quotient
= expand_sdiv_pow2 (compute_mode
, op0
, abs_d
);
4140 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4141 negate the quotient. */
4144 insn
= get_last_insn ();
4146 && (set
= single_set (insn
)) != 0
4147 && SET_DEST (set
) == quotient
4148 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
4149 << (HOST_BITS_PER_WIDE_INT
- 1)))
4150 set_unique_reg_note (insn
,
4152 gen_rtx_DIV (compute_mode
,
4159 quotient
= expand_unop (compute_mode
, neg_optab
,
4160 quotient
, quotient
, 0);
4163 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4165 choose_multiplier (abs_d
, size
, size
- 1,
4166 &mlr
, &post_shift
, &lgup
);
4167 ml
= (unsigned HOST_WIDE_INT
) INTVAL (mlr
);
4168 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4172 if (post_shift
>= BITS_PER_WORD
4173 || size
- 1 >= BITS_PER_WORD
)
4176 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
4177 + shift_cost
[compute_mode
][size
- 1]
4178 + add_cost
[compute_mode
]);
4179 t1
= expand_mult_highpart (compute_mode
, op0
, mlr
,
4181 max_cost
- extra_cost
);
4185 (RSHIFT_EXPR
, compute_mode
, t1
,
4186 build_int_cst (NULL_TREE
, post_shift
),
4189 (RSHIFT_EXPR
, compute_mode
, op0
,
4190 build_int_cst (NULL_TREE
, size
- 1),
4194 = force_operand (gen_rtx_MINUS (compute_mode
,
4199 = force_operand (gen_rtx_MINUS (compute_mode
,
4207 if (post_shift
>= BITS_PER_WORD
4208 || size
- 1 >= BITS_PER_WORD
)
4211 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
4212 mlr
= gen_int_mode (ml
, compute_mode
);
4213 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
4214 + shift_cost
[compute_mode
][size
- 1]
4215 + 2 * add_cost
[compute_mode
]);
4216 t1
= expand_mult_highpart (compute_mode
, op0
, mlr
,
4218 max_cost
- extra_cost
);
4221 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
4225 (RSHIFT_EXPR
, compute_mode
, t2
,
4226 build_int_cst (NULL_TREE
, post_shift
),
4229 (RSHIFT_EXPR
, compute_mode
, op0
,
4230 build_int_cst (NULL_TREE
, size
- 1),
4234 = force_operand (gen_rtx_MINUS (compute_mode
,
4239 = force_operand (gen_rtx_MINUS (compute_mode
,
4244 else /* Too wide mode to use tricky code */
4247 insn
= get_last_insn ();
4249 && (set
= single_set (insn
)) != 0
4250 && SET_DEST (set
) == quotient
)
4251 set_unique_reg_note (insn
,
4253 gen_rtx_DIV (compute_mode
, op0
, op1
));
4258 delete_insns_since (last
);
4261 case FLOOR_DIV_EXPR
:
4262 case FLOOR_MOD_EXPR
:
4263 /* We will come here only for signed operations. */
4264 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4266 unsigned HOST_WIDE_INT mh
;
4267 int pre_shift
, lgup
, post_shift
;
4268 HOST_WIDE_INT d
= INTVAL (op1
);
4273 /* We could just as easily deal with negative constants here,
4274 but it does not seem worth the trouble for GCC 2.6. */
4275 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4277 pre_shift
= floor_log2 (d
);
4280 remainder
= expand_binop (compute_mode
, and_optab
, op0
,
4281 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
4282 remainder
, 0, OPTAB_LIB_WIDEN
);
4284 return gen_lowpart (mode
, remainder
);
4286 quotient
= expand_shift
4287 (RSHIFT_EXPR
, compute_mode
, op0
,
4288 build_int_cst (NULL_TREE
, pre_shift
),
4295 mh
= choose_multiplier (d
, size
, size
- 1,
4296 &ml
, &post_shift
, &lgup
);
4299 if (post_shift
< BITS_PER_WORD
4300 && size
- 1 < BITS_PER_WORD
)
4303 (RSHIFT_EXPR
, compute_mode
, op0
,
4304 build_int_cst (NULL_TREE
, size
- 1),
4306 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
4307 NULL_RTX
, 0, OPTAB_WIDEN
);
4308 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
4309 + shift_cost
[compute_mode
][size
- 1]
4310 + 2 * add_cost
[compute_mode
]);
4311 t3
= expand_mult_highpart (compute_mode
, t2
, ml
,
4313 max_cost
- extra_cost
);
4317 (RSHIFT_EXPR
, compute_mode
, t3
,
4318 build_int_cst (NULL_TREE
, post_shift
),
4320 quotient
= expand_binop (compute_mode
, xor_optab
,
4321 t4
, t1
, tquotient
, 0,
4329 rtx nsign
, t1
, t2
, t3
, t4
;
4330 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
4331 op0
, constm1_rtx
), NULL_RTX
);
4332 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
4334 nsign
= expand_shift
4335 (RSHIFT_EXPR
, compute_mode
, t2
,
4336 build_int_cst (NULL_TREE
, size
- 1),
4338 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
4340 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
4345 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
4347 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4356 delete_insns_since (last
);
4358 /* Try using an instruction that produces both the quotient and
4359 remainder, using truncation. We can easily compensate the quotient
4360 or remainder to get floor rounding, once we have the remainder.
4361 Notice that we compute also the final remainder value here,
4362 and return the result right away. */
4363 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4364 target
= gen_reg_rtx (compute_mode
);
4369 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4370 quotient
= gen_reg_rtx (compute_mode
);
4375 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4376 remainder
= gen_reg_rtx (compute_mode
);
4379 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
4380 quotient
, remainder
, 0))
4382 /* This could be computed with a branch-less sequence.
4383 Save that for later. */
4385 rtx label
= gen_label_rtx ();
4386 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
4387 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4388 NULL_RTX
, 0, OPTAB_WIDEN
);
4389 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
4390 expand_dec (quotient
, const1_rtx
);
4391 expand_inc (remainder
, op1
);
4393 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4396 /* No luck with division elimination or divmod. Have to do it
4397 by conditionally adjusting op0 *and* the result. */
4399 rtx label1
, label2
, label3
, label4
, label5
;
4403 quotient
= gen_reg_rtx (compute_mode
);
4404 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4405 label1
= gen_label_rtx ();
4406 label2
= gen_label_rtx ();
4407 label3
= gen_label_rtx ();
4408 label4
= gen_label_rtx ();
4409 label5
= gen_label_rtx ();
4410 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4411 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
4412 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4413 quotient
, 0, OPTAB_LIB_WIDEN
);
4414 if (tem
!= quotient
)
4415 emit_move_insn (quotient
, tem
);
4416 emit_jump_insn (gen_jump (label5
));
4418 emit_label (label1
);
4419 expand_inc (adjusted_op0
, const1_rtx
);
4420 emit_jump_insn (gen_jump (label4
));
4422 emit_label (label2
);
4423 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
4424 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4425 quotient
, 0, OPTAB_LIB_WIDEN
);
4426 if (tem
!= quotient
)
4427 emit_move_insn (quotient
, tem
);
4428 emit_jump_insn (gen_jump (label5
));
4430 emit_label (label3
);
4431 expand_dec (adjusted_op0
, const1_rtx
);
4432 emit_label (label4
);
4433 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4434 quotient
, 0, OPTAB_LIB_WIDEN
);
4435 if (tem
!= quotient
)
4436 emit_move_insn (quotient
, tem
);
4437 expand_dec (quotient
, const1_rtx
);
4438 emit_label (label5
);
4446 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
4449 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4450 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4451 build_int_cst (NULL_TREE
, floor_log2 (d
)),
4453 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4455 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4456 t3
= gen_reg_rtx (compute_mode
);
4457 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4458 compute_mode
, 1, 1);
4462 lab
= gen_label_rtx ();
4463 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4464 expand_inc (t1
, const1_rtx
);
4469 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4475 /* Try using an instruction that produces both the quotient and
4476 remainder, using truncation. We can easily compensate the
4477 quotient or remainder to get ceiling rounding, once we have the
4478 remainder. Notice that we compute also the final remainder
4479 value here, and return the result right away. */
4480 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4481 target
= gen_reg_rtx (compute_mode
);
4485 remainder
= (REG_P (target
)
4486 ? target
: gen_reg_rtx (compute_mode
));
4487 quotient
= gen_reg_rtx (compute_mode
);
4491 quotient
= (REG_P (target
)
4492 ? target
: gen_reg_rtx (compute_mode
));
4493 remainder
= gen_reg_rtx (compute_mode
);
4496 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4499 /* This could be computed with a branch-less sequence.
4500 Save that for later. */
4501 rtx label
= gen_label_rtx ();
4502 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4503 compute_mode
, label
);
4504 expand_inc (quotient
, const1_rtx
);
4505 expand_dec (remainder
, op1
);
4507 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4510 /* No luck with division elimination or divmod. Have to do it
4511 by conditionally adjusting op0 *and* the result. */
4514 rtx adjusted_op0
, tem
;
4516 quotient
= gen_reg_rtx (compute_mode
);
4517 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4518 label1
= gen_label_rtx ();
4519 label2
= gen_label_rtx ();
4520 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4521 compute_mode
, label1
);
4522 emit_move_insn (quotient
, const0_rtx
);
4523 emit_jump_insn (gen_jump (label2
));
4525 emit_label (label1
);
4526 expand_dec (adjusted_op0
, const1_rtx
);
4527 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4528 quotient
, 1, OPTAB_LIB_WIDEN
);
4529 if (tem
!= quotient
)
4530 emit_move_insn (quotient
, tem
);
4531 expand_inc (quotient
, const1_rtx
);
4532 emit_label (label2
);
4537 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4538 && INTVAL (op1
) >= 0)
4540 /* This is extremely similar to the code for the unsigned case
4541 above. For 2.7 we should merge these variants, but for
4542 2.6.1 I don't want to touch the code for unsigned since that
4543 get used in C. The signed case will only be used by other
4547 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4548 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4549 build_int_cst (NULL_TREE
, floor_log2 (d
)),
4551 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4553 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4554 t3
= gen_reg_rtx (compute_mode
);
4555 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4556 compute_mode
, 1, 1);
4560 lab
= gen_label_rtx ();
4561 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4562 expand_inc (t1
, const1_rtx
);
4567 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4573 /* Try using an instruction that produces both the quotient and
4574 remainder, using truncation. We can easily compensate the
4575 quotient or remainder to get ceiling rounding, once we have the
4576 remainder. Notice that we compute also the final remainder
4577 value here, and return the result right away. */
4578 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4579 target
= gen_reg_rtx (compute_mode
);
4582 remainder
= (REG_P (target
)
4583 ? target
: gen_reg_rtx (compute_mode
));
4584 quotient
= gen_reg_rtx (compute_mode
);
4588 quotient
= (REG_P (target
)
4589 ? target
: gen_reg_rtx (compute_mode
));
4590 remainder
= gen_reg_rtx (compute_mode
);
4593 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4596 /* This could be computed with a branch-less sequence.
4597 Save that for later. */
4599 rtx label
= gen_label_rtx ();
4600 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4601 compute_mode
, label
);
4602 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4603 NULL_RTX
, 0, OPTAB_WIDEN
);
4604 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4605 expand_inc (quotient
, const1_rtx
);
4606 expand_dec (remainder
, op1
);
4608 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4611 /* No luck with division elimination or divmod. Have to do it
4612 by conditionally adjusting op0 *and* the result. */
4614 rtx label1
, label2
, label3
, label4
, label5
;
4618 quotient
= gen_reg_rtx (compute_mode
);
4619 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4620 label1
= gen_label_rtx ();
4621 label2
= gen_label_rtx ();
4622 label3
= gen_label_rtx ();
4623 label4
= gen_label_rtx ();
4624 label5
= gen_label_rtx ();
4625 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4626 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
4627 compute_mode
, label1
);
4628 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4629 quotient
, 0, OPTAB_LIB_WIDEN
);
4630 if (tem
!= quotient
)
4631 emit_move_insn (quotient
, tem
);
4632 emit_jump_insn (gen_jump (label5
));
4634 emit_label (label1
);
4635 expand_dec (adjusted_op0
, const1_rtx
);
4636 emit_jump_insn (gen_jump (label4
));
4638 emit_label (label2
);
4639 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
4640 compute_mode
, label3
);
4641 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4642 quotient
, 0, OPTAB_LIB_WIDEN
);
4643 if (tem
!= quotient
)
4644 emit_move_insn (quotient
, tem
);
4645 emit_jump_insn (gen_jump (label5
));
4647 emit_label (label3
);
4648 expand_inc (adjusted_op0
, const1_rtx
);
4649 emit_label (label4
);
4650 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4651 quotient
, 0, OPTAB_LIB_WIDEN
);
4652 if (tem
!= quotient
)
4653 emit_move_insn (quotient
, tem
);
4654 expand_inc (quotient
, const1_rtx
);
4655 emit_label (label5
);
4660 case EXACT_DIV_EXPR
:
4661 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4663 HOST_WIDE_INT d
= INTVAL (op1
);
4664 unsigned HOST_WIDE_INT ml
;
4668 pre_shift
= floor_log2 (d
& -d
);
4669 ml
= invert_mod2n (d
>> pre_shift
, size
);
4670 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4671 build_int_cst (NULL_TREE
, pre_shift
),
4672 NULL_RTX
, unsignedp
);
4673 quotient
= expand_mult (compute_mode
, t1
,
4674 gen_int_mode (ml
, compute_mode
),
4677 insn
= get_last_insn ();
4678 set_unique_reg_note (insn
,
4680 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
4686 case ROUND_DIV_EXPR
:
4687 case ROUND_MOD_EXPR
:
4692 label
= gen_label_rtx ();
4693 quotient
= gen_reg_rtx (compute_mode
);
4694 remainder
= gen_reg_rtx (compute_mode
);
4695 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
4698 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
4699 quotient
, 1, OPTAB_LIB_WIDEN
);
4700 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
4701 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4702 remainder
, 1, OPTAB_LIB_WIDEN
);
4704 tem
= plus_constant (op1
, -1);
4705 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4706 build_int_cst (NULL_TREE
, 1),
4708 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
4709 expand_inc (quotient
, const1_rtx
);
4710 expand_dec (remainder
, op1
);
4715 rtx abs_rem
, abs_op1
, tem
, mask
;
4717 label
= gen_label_rtx ();
4718 quotient
= gen_reg_rtx (compute_mode
);
4719 remainder
= gen_reg_rtx (compute_mode
);
4720 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
4723 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
4724 quotient
, 0, OPTAB_LIB_WIDEN
);
4725 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
4726 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4727 remainder
, 0, OPTAB_LIB_WIDEN
);
4729 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
4730 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
4731 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
4732 build_int_cst (NULL_TREE
, 1),
4734 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
4735 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4736 NULL_RTX
, 0, OPTAB_WIDEN
);
4737 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4738 build_int_cst (NULL_TREE
, size
- 1),
4740 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
4741 NULL_RTX
, 0, OPTAB_WIDEN
);
4742 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4743 NULL_RTX
, 0, OPTAB_WIDEN
);
4744 expand_inc (quotient
, tem
);
4745 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
4746 NULL_RTX
, 0, OPTAB_WIDEN
);
4747 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4748 NULL_RTX
, 0, OPTAB_WIDEN
);
4749 expand_dec (remainder
, tem
);
4752 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4760 if (target
&& GET_MODE (target
) != compute_mode
)
4765 /* Try to produce the remainder without producing the quotient.
4766 If we seem to have a divmod pattern that does not require widening,
4767 don't try widening here. We should really have a WIDEN argument
4768 to expand_twoval_binop, since what we'd really like to do here is
4769 1) try a mod insn in compute_mode
4770 2) try a divmod insn in compute_mode
4771 3) try a div insn in compute_mode and multiply-subtract to get
4773 4) try the same things with widening allowed. */
4775 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4778 ((optab2
->handlers
[compute_mode
].insn_code
4779 != CODE_FOR_nothing
)
4780 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4783 /* No luck there. Can we do remainder and divide at once
4784 without a library call? */
4785 remainder
= gen_reg_rtx (compute_mode
);
4786 if (! expand_twoval_binop ((unsignedp
4790 NULL_RTX
, remainder
, unsignedp
))
4795 return gen_lowpart (mode
, remainder
);
4798 /* Produce the quotient. Try a quotient insn, but not a library call.
4799 If we have a divmod in this mode, use it in preference to widening
4800 the div (for this test we assume it will not fail). Note that optab2
4801 is set to the one of the two optabs that the call below will use. */
4803 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
4804 op0
, op1
, rem_flag
? NULL_RTX
: target
,
4806 ((optab2
->handlers
[compute_mode
].insn_code
4807 != CODE_FOR_nothing
)
4808 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4812 /* No luck there. Try a quotient-and-remainder insn,
4813 keeping the quotient alone. */
4814 quotient
= gen_reg_rtx (compute_mode
);
4815 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
4817 quotient
, NULL_RTX
, unsignedp
))
4821 /* Still no luck. If we are not computing the remainder,
4822 use a library call for the quotient. */
4823 quotient
= sign_expand_binop (compute_mode
,
4824 udiv_optab
, sdiv_optab
,
4826 unsignedp
, OPTAB_LIB_WIDEN
);
4833 if (target
&& GET_MODE (target
) != compute_mode
)
4838 /* No divide instruction either. Use library for remainder. */
4839 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4841 unsignedp
, OPTAB_LIB_WIDEN
);
4842 /* No remainder function. Try a quotient-and-remainder
4843 function, keeping the remainder. */
4846 remainder
= gen_reg_rtx (compute_mode
);
4847 if (!expand_twoval_binop_libfunc
4848 (unsignedp
? udivmod_optab
: sdivmod_optab
,
4850 NULL_RTX
, remainder
,
4851 unsignedp
? UMOD
: MOD
))
4852 remainder
= NULL_RTX
;
4857 /* We divided. Now finish doing X - Y * (X / Y). */
4858 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4859 NULL_RTX
, unsignedp
);
4860 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4861 remainder
, target
, unsignedp
,
4866 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4869 /* Return a tree node with data type TYPE, describing the value of X.
4870 Usually this is an VAR_DECL, if there is no obvious better choice.
4871 X may be an expression, however we only support those expressions
4872 generated by loop.c. */
4875 make_tree (tree type
, rtx x
)
4879 switch (GET_CODE (x
))
4883 HOST_WIDE_INT hi
= 0;
4886 && !(TYPE_UNSIGNED (type
)
4887 && (GET_MODE_BITSIZE (TYPE_MODE (type
))
4888 < HOST_BITS_PER_WIDE_INT
)))
4891 t
= build_int_cst_wide (type
, INTVAL (x
), hi
);
4897 if (GET_MODE (x
) == VOIDmode
)
4898 t
= build_int_cst_wide (type
,
4899 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4904 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4905 t
= build_real (type
, d
);
4916 units
= CONST_VECTOR_NUNITS (x
);
4918 /* Build a tree with vector elements. */
4919 for (i
= units
- 1; i
>= 0; --i
)
4921 elt
= CONST_VECTOR_ELT (x
, i
);
4922 t
= tree_cons (NULL_TREE
, make_tree (type
, elt
), t
);
4925 return build_vector (type
, t
);
4929 return fold_build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4930 make_tree (type
, XEXP (x
, 1)));
4933 return fold_build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4934 make_tree (type
, XEXP (x
, 1)));
4937 return fold_build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0)));
4940 return fold_build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4941 make_tree (type
, XEXP (x
, 1)));
4944 return fold_build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4945 make_tree (type
, XEXP (x
, 1)));
4948 t
= lang_hooks
.types
.unsigned_type (type
);
4949 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
4950 make_tree (t
, XEXP (x
, 0)),
4951 make_tree (type
, XEXP (x
, 1))));
4954 t
= lang_hooks
.types
.signed_type (type
);
4955 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
4956 make_tree (t
, XEXP (x
, 0)),
4957 make_tree (type
, XEXP (x
, 1))));
4960 if (TREE_CODE (type
) != REAL_TYPE
)
4961 t
= lang_hooks
.types
.signed_type (type
);
4965 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
4966 make_tree (t
, XEXP (x
, 0)),
4967 make_tree (t
, XEXP (x
, 1))));
4969 t
= lang_hooks
.types
.unsigned_type (type
);
4970 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
4971 make_tree (t
, XEXP (x
, 0)),
4972 make_tree (t
, XEXP (x
, 1))));
4976 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
4977 GET_CODE (x
) == ZERO_EXTEND
);
4978 return fold_convert (type
, make_tree (t
, XEXP (x
, 0)));
4981 t
= build_decl (VAR_DECL
, NULL_TREE
, type
);
4983 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4984 ptr_mode. So convert. */
4985 if (POINTER_TYPE_P (type
))
4986 x
= convert_memory_address (TYPE_MODE (type
), x
);
4988 /* Note that we do *not* use SET_DECL_RTL here, because we do not
4989 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
4990 t
->decl_with_rtl
.rtl
= x
;
4996 /* Check whether the multiplication X * MULT + ADD overflows.
4997 X, MULT and ADD must be CONST_*.
4998 MODE is the machine mode for the computation.
4999 X and MULT must have mode MODE. ADD may have a different mode.
5000 So can X (defaults to same as MODE).
5001 UNSIGNEDP is nonzero to do unsigned multiplication. */
5004 const_mult_add_overflow_p (rtx x
, rtx mult
, rtx add
,
5005 enum machine_mode mode
, int unsignedp
)
5007 tree type
, mult_type
, add_type
, result
;
5009 type
= lang_hooks
.types
.type_for_mode (mode
, unsignedp
);
5011 /* In order to get a proper overflow indication from an unsigned
5012 type, we have to pretend that it's a sizetype. */
5016 /* FIXME:It would be nice if we could step directly from this
5017 type to its sizetype equivalent. */
5018 mult_type
= build_distinct_type_copy (type
);
5019 TYPE_IS_SIZETYPE (mult_type
) = 1;
5022 add_type
= (GET_MODE (add
) == VOIDmode
? mult_type
5023 : lang_hooks
.types
.type_for_mode (GET_MODE (add
), unsignedp
));
5025 result
= fold_build2 (PLUS_EXPR
, mult_type
,
5026 fold_build2 (MULT_EXPR
, mult_type
,
5027 make_tree (mult_type
, x
),
5028 make_tree (mult_type
, mult
)),
5029 make_tree (add_type
, add
));
5031 return TREE_CONSTANT_OVERFLOW (result
);
5034 /* Return an rtx representing the value of X * MULT + ADD.
5035 TARGET is a suggestion for where to store the result (an rtx).
5036 MODE is the machine mode for the computation.
5037 X and MULT must have mode MODE. ADD may have a different mode.
5038 So can X (defaults to same as MODE).
5039 UNSIGNEDP is nonzero to do unsigned multiplication.
5040 This may emit insns. */
5043 expand_mult_add (rtx x
, rtx target
, rtx mult
, rtx add
, enum machine_mode mode
,
5046 tree type
= lang_hooks
.types
.type_for_mode (mode
, unsignedp
);
5047 tree add_type
= (GET_MODE (add
) == VOIDmode
5048 ? type
: lang_hooks
.types
.type_for_mode (GET_MODE (add
),
5050 tree result
= fold_build2 (PLUS_EXPR
, type
,
5051 fold_build2 (MULT_EXPR
, type
,
5052 make_tree (type
, x
),
5053 make_tree (type
, mult
)),
5054 make_tree (add_type
, add
));
5056 return expand_expr (result
, target
, VOIDmode
, 0);
5059 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5060 and returning TARGET.
5062 If TARGET is 0, a pseudo-register or constant is returned. */
5065 expand_and (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
5069 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
5070 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
5072 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
5076 else if (tem
!= target
)
5077 emit_move_insn (target
, tem
);
5081 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5082 and storing in TARGET. Normally return TARGET.
5083 Return 0 if that cannot be done.
5085 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5086 it is VOIDmode, they cannot both be CONST_INT.
5088 UNSIGNEDP is for the case where we have to widen the operands
5089 to perform the operation. It says to use zero-extension.
5091 NORMALIZEP is 1 if we should convert the result to be either zero
5092 or one. Normalize is -1 if we should convert the result to be
5093 either zero or -1. If NORMALIZEP is zero, the result will be left
5094 "raw" out of the scc insn. */
5097 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5098 enum machine_mode mode
, int unsignedp
, int normalizep
)
5101 enum insn_code icode
;
5102 enum machine_mode compare_mode
;
5103 enum machine_mode target_mode
= GET_MODE (target
);
5105 rtx last
= get_last_insn ();
5106 rtx pattern
, comparison
;
5109 code
= unsigned_condition (code
);
5111 /* If one operand is constant, make it the second one. Only do this
5112 if the other operand is not constant as well. */
5114 if (swap_commutative_operands_p (op0
, op1
))
5119 code
= swap_condition (code
);
5122 if (mode
== VOIDmode
)
5123 mode
= GET_MODE (op0
);
5125 /* For some comparisons with 1 and -1, we can convert this to
5126 comparisons with zero. This will often produce more opportunities for
5127 store-flag insns. */
5132 if (op1
== const1_rtx
)
5133 op1
= const0_rtx
, code
= LE
;
5136 if (op1
== constm1_rtx
)
5137 op1
= const0_rtx
, code
= LT
;
5140 if (op1
== const1_rtx
)
5141 op1
= const0_rtx
, code
= GT
;
5144 if (op1
== constm1_rtx
)
5145 op1
= const0_rtx
, code
= GE
;
5148 if (op1
== const1_rtx
)
5149 op1
= const0_rtx
, code
= NE
;
5152 if (op1
== const1_rtx
)
5153 op1
= const0_rtx
, code
= EQ
;
5159 /* If we are comparing a double-word integer with zero or -1, we can
5160 convert the comparison into one involving a single word. */
5161 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
5162 && GET_MODE_CLASS (mode
) == MODE_INT
5163 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
5165 if ((code
== EQ
|| code
== NE
)
5166 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
5168 rtx op00
, op01
, op0both
;
5170 /* Do a logical OR or AND of the two words and compare the result. */
5171 op00
= simplify_gen_subreg (word_mode
, op0
, mode
, 0);
5172 op01
= simplify_gen_subreg (word_mode
, op0
, mode
, UNITS_PER_WORD
);
5173 op0both
= expand_binop (word_mode
,
5174 op1
== const0_rtx
? ior_optab
: and_optab
,
5175 op00
, op01
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
5178 return emit_store_flag (target
, code
, op0both
, op1
, word_mode
,
5179 unsignedp
, normalizep
);
5181 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
5185 /* If testing the sign bit, can just test on high word. */
5186 op0h
= simplify_gen_subreg (word_mode
, op0
, mode
,
5187 subreg_highpart_offset (word_mode
, mode
));
5188 return emit_store_flag (target
, code
, op0h
, op1
, word_mode
,
5189 unsignedp
, normalizep
);
5193 /* From now on, we won't change CODE, so set ICODE now. */
5194 icode
= setcc_gen_code
[(int) code
];
5196 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5197 complement of A (for GE) and shifting the sign bit to the low bit. */
5198 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
5199 && GET_MODE_CLASS (mode
) == MODE_INT
5200 && (normalizep
|| STORE_FLAG_VALUE
== 1
5201 || (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5202 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5203 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))))
5207 /* If the result is to be wider than OP0, it is best to convert it
5208 first. If it is to be narrower, it is *incorrect* to convert it
5210 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
5212 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5216 if (target_mode
!= mode
)
5220 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
5221 ((STORE_FLAG_VALUE
== 1 || normalizep
)
5222 ? 0 : subtarget
), 0);
5224 if (STORE_FLAG_VALUE
== 1 || normalizep
)
5225 /* If we are supposed to produce a 0/1 value, we want to do
5226 a logical shift from the sign bit to the low-order bit; for
5227 a -1/0 value, we do an arithmetic shift. */
5228 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5229 size_int (GET_MODE_BITSIZE (mode
) - 1),
5230 subtarget
, normalizep
!= -1);
5232 if (mode
!= target_mode
)
5233 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5238 if (icode
!= CODE_FOR_nothing
)
5240 insn_operand_predicate_fn pred
;
5242 /* We think we may be able to do this with a scc insn. Emit the
5243 comparison and then the scc insn. */
5245 do_pending_stack_adjust ();
5246 last
= get_last_insn ();
5249 = compare_from_rtx (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
);
5250 if (CONSTANT_P (comparison
))
5252 switch (GET_CODE (comparison
))
5255 if (comparison
== const0_rtx
)
5259 #ifdef FLOAT_STORE_FLAG_VALUE
5261 if (comparison
== CONST0_RTX (GET_MODE (comparison
)))
5269 if (normalizep
== 1)
5271 if (normalizep
== -1)
5273 return const_true_rtx
;
5276 /* The code of COMPARISON may not match CODE if compare_from_rtx
5277 decided to swap its operands and reverse the original code.
5279 We know that compare_from_rtx returns either a CONST_INT or
5280 a new comparison code, so it is safe to just extract the
5281 code from COMPARISON. */
5282 code
= GET_CODE (comparison
);
5284 /* Get a reference to the target in the proper mode for this insn. */
5285 compare_mode
= insn_data
[(int) icode
].operand
[0].mode
;
5287 pred
= insn_data
[(int) icode
].operand
[0].predicate
;
5288 if (optimize
|| ! (*pred
) (subtarget
, compare_mode
))
5289 subtarget
= gen_reg_rtx (compare_mode
);
5291 pattern
= GEN_FCN (icode
) (subtarget
);
5294 emit_insn (pattern
);
5296 /* If we are converting to a wider mode, first convert to
5297 TARGET_MODE, then normalize. This produces better combining
5298 opportunities on machines that have a SIGN_EXTRACT when we are
5299 testing a single bit. This mostly benefits the 68k.
5301 If STORE_FLAG_VALUE does not have the sign bit set when
5302 interpreted in COMPARE_MODE, we can do this conversion as
5303 unsigned, which is usually more efficient. */
5304 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (compare_mode
))
5306 convert_move (target
, subtarget
,
5307 (GET_MODE_BITSIZE (compare_mode
)
5308 <= HOST_BITS_PER_WIDE_INT
)
5309 && 0 == (STORE_FLAG_VALUE
5310 & ((HOST_WIDE_INT
) 1
5311 << (GET_MODE_BITSIZE (compare_mode
) -1))));
5313 compare_mode
= target_mode
;
5318 /* If we want to keep subexpressions around, don't reuse our
5324 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
5325 we don't have to do anything. */
5326 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
5328 /* STORE_FLAG_VALUE might be the most negative number, so write
5329 the comparison this way to avoid a compiler-time warning. */
5330 else if (- normalizep
== STORE_FLAG_VALUE
)
5331 op0
= expand_unop (compare_mode
, neg_optab
, op0
, subtarget
, 0);
5333 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
5334 makes it hard to use a value of just the sign bit due to
5335 ANSI integer constant typing rules. */
5336 else if (GET_MODE_BITSIZE (compare_mode
) <= HOST_BITS_PER_WIDE_INT
5337 && (STORE_FLAG_VALUE
5338 & ((HOST_WIDE_INT
) 1
5339 << (GET_MODE_BITSIZE (compare_mode
) - 1))))
5340 op0
= expand_shift (RSHIFT_EXPR
, compare_mode
, op0
,
5341 size_int (GET_MODE_BITSIZE (compare_mode
) - 1),
5342 subtarget
, normalizep
== 1);
5345 gcc_assert (STORE_FLAG_VALUE
& 1);
5347 op0
= expand_and (compare_mode
, op0
, const1_rtx
, subtarget
);
5348 if (normalizep
== -1)
5349 op0
= expand_unop (compare_mode
, neg_optab
, op0
, op0
, 0);
5352 /* If we were converting to a smaller mode, do the
5354 if (target_mode
!= compare_mode
)
5356 convert_move (target
, op0
, 0);
5364 delete_insns_since (last
);
5366 /* If optimizing, use different pseudo registers for each insn, instead
5367 of reusing the same pseudo. This leads to better CSE, but slows
5368 down the compiler, since there are more pseudos */
5369 subtarget
= (!optimize
5370 && (target_mode
== mode
)) ? target
: NULL_RTX
;
5372 /* If we reached here, we can't do this with a scc insn. However, there
5373 are some comparisons that can be done directly. For example, if
5374 this is an equality comparison of integers, we can try to exclusive-or
5375 (or subtract) the two operands and use a recursive call to try the
5376 comparison with zero. Don't do any of these cases if branches are
5380 && GET_MODE_CLASS (mode
) == MODE_INT
&& (code
== EQ
|| code
== NE
)
5381 && op1
!= const0_rtx
)
5383 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
5387 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
5390 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
5391 mode
, unsignedp
, normalizep
);
5393 delete_insns_since (last
);
5397 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5398 the constant zero. Reject all other comparisons at this point. Only
5399 do LE and GT if branches are expensive since they are expensive on
5400 2-operand machines. */
5402 if (BRANCH_COST
== 0
5403 || GET_MODE_CLASS (mode
) != MODE_INT
|| op1
!= const0_rtx
5404 || (code
!= EQ
&& code
!= NE
5405 && (BRANCH_COST
<= 1 || (code
!= LE
&& code
!= GT
))))
5408 /* See what we need to return. We can only return a 1, -1, or the
5411 if (normalizep
== 0)
5413 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5414 normalizep
= STORE_FLAG_VALUE
;
5416 else if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5417 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5418 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
5424 /* Try to put the result of the comparison in the sign bit. Assume we can't
5425 do the necessary operation below. */
5429 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5430 the sign bit set. */
5434 /* This is destructive, so SUBTARGET can't be OP0. */
5435 if (rtx_equal_p (subtarget
, op0
))
5438 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
5441 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
5445 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5446 number of bits in the mode of OP0, minus one. */
5450 if (rtx_equal_p (subtarget
, op0
))
5453 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5454 size_int (GET_MODE_BITSIZE (mode
) - 1),
5456 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5460 if (code
== EQ
|| code
== NE
)
5462 /* For EQ or NE, one way to do the comparison is to apply an operation
5463 that converts the operand into a positive number if it is nonzero
5464 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5465 for NE we negate. This puts the result in the sign bit. Then we
5466 normalize with a shift, if needed.
5468 Two operations that can do the above actions are ABS and FFS, so try
5469 them. If that doesn't work, and MODE is smaller than a full word,
5470 we can use zero-extension to the wider mode (an unsigned conversion)
5471 as the operation. */
5473 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5474 that is compensated by the subsequent overflow when subtracting
5477 if (abs_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
)
5478 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5479 else if (ffs_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
)
5480 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5481 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5483 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5490 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5493 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5496 /* If we couldn't do it that way, for NE we can "or" the two's complement
5497 of the value with itself. For EQ, we take the one's complement of
5498 that "or", which is an extra insn, so we only handle EQ if branches
5501 if (tem
== 0 && (code
== NE
|| BRANCH_COST
> 1))
5503 if (rtx_equal_p (subtarget
, op0
))
5506 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5507 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5510 if (tem
&& code
== EQ
)
5511 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5515 if (tem
&& normalizep
)
5516 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
5517 size_int (GET_MODE_BITSIZE (mode
) - 1),
5518 subtarget
, normalizep
== 1);
5522 if (GET_MODE (tem
) != target_mode
)
5524 convert_move (target
, tem
, 0);
5527 else if (!subtarget
)
5529 emit_move_insn (target
, tem
);
5534 delete_insns_since (last
);
5539 /* Like emit_store_flag, but always succeeds. */
5542 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5543 enum machine_mode mode
, int unsignedp
, int normalizep
)
5547 /* First see if emit_store_flag can do the job. */
5548 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
5552 if (normalizep
== 0)
5555 /* If this failed, we have to do this with set/compare/jump/set code. */
5558 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
5559 target
= gen_reg_rtx (GET_MODE (target
));
5561 emit_move_insn (target
, const1_rtx
);
5562 label
= gen_label_rtx ();
5563 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
5566 emit_move_insn (target
, const0_rtx
);
5572 /* Perform possibly multi-word comparison and conditional jump to LABEL
5573 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
5575 The algorithm is based on the code in expr.c:do_jump.
5577 Note that this does not perform a general comparison. Only
5578 variants generated within expmed.c are correctly handled, others
5579 could be handled if needed. */
5582 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, enum machine_mode mode
,
5585 /* If this mode is an integer too wide to compare properly,
5586 compare word by word. Rely on cse to optimize constant cases. */
5588 if (GET_MODE_CLASS (mode
) == MODE_INT
5589 && ! can_compare_p (op
, mode
, ccp_jump
))
5591 rtx label2
= gen_label_rtx ();
5596 do_jump_by_parts_greater_rtx (mode
, 1, arg2
, arg1
, label2
, label
);
5600 do_jump_by_parts_greater_rtx (mode
, 1, arg1
, arg2
, label
, label2
);
5604 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label2
, label
);
5608 do_jump_by_parts_greater_rtx (mode
, 0, arg1
, arg2
, label2
, label
);
5612 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label
, label2
);
5615 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
5616 that's the only equality operations we do */
5618 gcc_assert (arg2
== const0_rtx
&& mode
== GET_MODE(arg1
));
5619 do_jump_by_parts_equality_rtx (arg1
, label2
, label
);
5623 gcc_assert (arg2
== const0_rtx
&& mode
== GET_MODE(arg1
));
5624 do_jump_by_parts_equality_rtx (arg1
, label
, label2
);
5631 emit_label (label2
);
5634 emit_cmp_and_jump_insns (arg1
, arg2
, op
, NULL_RTX
, mode
, 0, label
);