1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "coretypes.h"
33 #include "insn-config.h"
38 #include "langhooks.h"
40 static void store_fixed_bit_field (rtx
, unsigned HOST_WIDE_INT
,
41 unsigned HOST_WIDE_INT
,
42 unsigned HOST_WIDE_INT
, rtx
);
43 static void store_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
44 unsigned HOST_WIDE_INT
, rtx
);
45 static rtx
extract_fixed_bit_field (enum machine_mode
, rtx
,
46 unsigned HOST_WIDE_INT
,
47 unsigned HOST_WIDE_INT
,
48 unsigned HOST_WIDE_INT
, rtx
, int);
49 static rtx
mask_rtx (enum machine_mode
, int, int, int);
50 static rtx
lshift_value (enum machine_mode
, rtx
, int, int);
51 static rtx
extract_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
, int);
53 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, enum machine_mode
, rtx
);
54 static rtx
expand_smod_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
55 static rtx
expand_sdiv_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
57 /* Test whether a value is zero of a power of two. */
58 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
60 /* Nonzero means divides or modulus operations are relatively cheap for
61 powers of two, so don't use branches; emit the operation instead.
62 Usually, this will mean that the MD file will emit non-branch
65 static bool sdiv_pow2_cheap
[NUM_MACHINE_MODES
];
66 static bool smod_pow2_cheap
[NUM_MACHINE_MODES
];
68 #ifndef SLOW_UNALIGNED_ACCESS
69 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
72 /* For compilers that support multiple targets with different word sizes,
73 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
74 is the H8/300(H) compiler. */
76 #ifndef MAX_BITS_PER_WORD
77 #define MAX_BITS_PER_WORD BITS_PER_WORD
80 /* Reduce conditional compilation elsewhere. */
83 #define CODE_FOR_insv CODE_FOR_nothing
84 #define gen_insv(a,b,c,d) NULL_RTX
88 #define CODE_FOR_extv CODE_FOR_nothing
89 #define gen_extv(a,b,c,d) NULL_RTX
93 #define CODE_FOR_extzv CODE_FOR_nothing
94 #define gen_extzv(a,b,c,d) NULL_RTX
97 /* Cost of various pieces of RTL. Note that some of these are indexed by
98 shift count and some by mode. */
100 static int add_cost
[NUM_MACHINE_MODES
];
101 static int neg_cost
[NUM_MACHINE_MODES
];
102 static int shift_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
103 static int shiftadd_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
104 static int shiftsub_cost
[NUM_MACHINE_MODES
][MAX_BITS_PER_WORD
];
105 static int mul_cost
[NUM_MACHINE_MODES
];
106 static int div_cost
[NUM_MACHINE_MODES
];
107 static int mul_widen_cost
[NUM_MACHINE_MODES
];
108 static int mul_highpart_cost
[NUM_MACHINE_MODES
];
115 struct rtx_def reg
; rtunion reg_fld
[2];
116 struct rtx_def plus
; rtunion plus_fld1
;
118 struct rtx_def udiv
; rtunion udiv_fld1
;
119 struct rtx_def mult
; rtunion mult_fld1
;
120 struct rtx_def div
; rtunion div_fld1
;
121 struct rtx_def mod
; rtunion mod_fld1
;
123 struct rtx_def wide_mult
; rtunion wide_mult_fld1
;
124 struct rtx_def wide_lshr
; rtunion wide_lshr_fld1
;
125 struct rtx_def wide_trunc
;
126 struct rtx_def shift
; rtunion shift_fld1
;
127 struct rtx_def shift_mult
; rtunion shift_mult_fld1
;
128 struct rtx_def shift_add
; rtunion shift_add_fld1
;
129 struct rtx_def shift_sub
; rtunion shift_sub_fld1
;
132 rtx pow2
[MAX_BITS_PER_WORD
];
133 rtx cint
[MAX_BITS_PER_WORD
];
135 enum machine_mode mode
, wider_mode
;
137 zero_cost
= rtx_cost (const0_rtx
, 0);
139 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
141 pow2
[m
] = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
142 cint
[m
] = GEN_INT (m
);
145 memset (&all
, 0, sizeof all
);
147 PUT_CODE (&all
.reg
, REG
);
148 REGNO (&all
.reg
) = 10000;
150 PUT_CODE (&all
.plus
, PLUS
);
151 XEXP (&all
.plus
, 0) = &all
.reg
;
152 XEXP (&all
.plus
, 1) = &all
.reg
;
154 PUT_CODE (&all
.neg
, NEG
);
155 XEXP (&all
.neg
, 0) = &all
.reg
;
157 PUT_CODE (&all
.udiv
, UDIV
);
158 XEXP (&all
.udiv
, 0) = &all
.reg
;
159 XEXP (&all
.udiv
, 1) = &all
.reg
;
161 PUT_CODE (&all
.mult
, MULT
);
162 XEXP (&all
.mult
, 0) = &all
.reg
;
163 XEXP (&all
.mult
, 1) = &all
.reg
;
165 PUT_CODE (&all
.div
, DIV
);
166 XEXP (&all
.div
, 0) = &all
.reg
;
167 XEXP (&all
.div
, 1) = 32 < MAX_BITS_PER_WORD
? cint
[32] : GEN_INT (32);
169 PUT_CODE (&all
.mod
, MOD
);
170 XEXP (&all
.mod
, 0) = &all
.reg
;
171 XEXP (&all
.mod
, 1) = XEXP (&all
.div
, 1);
173 PUT_CODE (&all
.zext
, ZERO_EXTEND
);
174 XEXP (&all
.zext
, 0) = &all
.reg
;
176 PUT_CODE (&all
.wide_mult
, MULT
);
177 XEXP (&all
.wide_mult
, 0) = &all
.zext
;
178 XEXP (&all
.wide_mult
, 1) = &all
.zext
;
180 PUT_CODE (&all
.wide_lshr
, LSHIFTRT
);
181 XEXP (&all
.wide_lshr
, 0) = &all
.wide_mult
;
183 PUT_CODE (&all
.wide_trunc
, TRUNCATE
);
184 XEXP (&all
.wide_trunc
, 0) = &all
.wide_lshr
;
186 PUT_CODE (&all
.shift
, ASHIFT
);
187 XEXP (&all
.shift
, 0) = &all
.reg
;
189 PUT_CODE (&all
.shift_mult
, MULT
);
190 XEXP (&all
.shift_mult
, 0) = &all
.reg
;
192 PUT_CODE (&all
.shift_add
, PLUS
);
193 XEXP (&all
.shift_add
, 0) = &all
.shift_mult
;
194 XEXP (&all
.shift_add
, 1) = &all
.reg
;
196 PUT_CODE (&all
.shift_sub
, MINUS
);
197 XEXP (&all
.shift_sub
, 0) = &all
.shift_mult
;
198 XEXP (&all
.shift_sub
, 1) = &all
.reg
;
200 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
202 mode
= GET_MODE_WIDER_MODE (mode
))
204 PUT_MODE (&all
.reg
, mode
);
205 PUT_MODE (&all
.plus
, mode
);
206 PUT_MODE (&all
.neg
, mode
);
207 PUT_MODE (&all
.udiv
, mode
);
208 PUT_MODE (&all
.mult
, mode
);
209 PUT_MODE (&all
.div
, mode
);
210 PUT_MODE (&all
.mod
, mode
);
211 PUT_MODE (&all
.wide_trunc
, mode
);
212 PUT_MODE (&all
.shift
, mode
);
213 PUT_MODE (&all
.shift_mult
, mode
);
214 PUT_MODE (&all
.shift_add
, mode
);
215 PUT_MODE (&all
.shift_sub
, mode
);
217 add_cost
[mode
] = rtx_cost (&all
.plus
, SET
);
218 neg_cost
[mode
] = rtx_cost (&all
.neg
, SET
);
219 div_cost
[mode
] = rtx_cost (&all
.udiv
, SET
);
220 mul_cost
[mode
] = rtx_cost (&all
.mult
, SET
);
222 sdiv_pow2_cheap
[mode
] = (rtx_cost (&all
.div
, SET
) <= 2 * add_cost
[mode
]);
223 smod_pow2_cheap
[mode
] = (rtx_cost (&all
.mod
, SET
) <= 4 * add_cost
[mode
]);
225 wider_mode
= GET_MODE_WIDER_MODE (mode
);
226 if (wider_mode
!= VOIDmode
)
228 PUT_MODE (&all
.zext
, wider_mode
);
229 PUT_MODE (&all
.wide_mult
, wider_mode
);
230 PUT_MODE (&all
.wide_lshr
, wider_mode
);
231 XEXP (&all
.wide_lshr
, 1) = GEN_INT (GET_MODE_BITSIZE (mode
));
233 mul_widen_cost
[wider_mode
] = rtx_cost (&all
.wide_mult
, SET
);
234 mul_highpart_cost
[mode
] = rtx_cost (&all
.wide_trunc
, SET
);
237 shift_cost
[mode
][0] = 0;
238 shiftadd_cost
[mode
][0] = shiftsub_cost
[mode
][0] = add_cost
[mode
];
240 n
= MIN (MAX_BITS_PER_WORD
, GET_MODE_BITSIZE (mode
));
241 for (m
= 1; m
< n
; m
++)
243 XEXP (&all
.shift
, 1) = cint
[m
];
244 XEXP (&all
.shift_mult
, 1) = pow2
[m
];
246 shift_cost
[mode
][m
] = rtx_cost (&all
.shift
, SET
);
247 shiftadd_cost
[mode
][m
] = rtx_cost (&all
.shift_add
, SET
);
248 shiftsub_cost
[mode
][m
] = rtx_cost (&all
.shift_sub
, SET
);
253 /* Return an rtx representing minus the value of X.
254 MODE is the intended mode of the result,
255 useful if X is a CONST_INT. */
258 negate_rtx (enum machine_mode mode
, rtx x
)
260 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
263 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
268 /* Report on the availability of insv/extv/extzv and the desired mode
269 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
270 is false; else the mode of the specified operand. If OPNO is -1,
271 all the caller cares about is whether the insn is available. */
273 mode_for_extraction (enum extraction_pattern pattern
, int opno
)
275 const struct insn_data
*data
;
282 data
= &insn_data
[CODE_FOR_insv
];
285 return MAX_MACHINE_MODE
;
290 data
= &insn_data
[CODE_FOR_extv
];
293 return MAX_MACHINE_MODE
;
298 data
= &insn_data
[CODE_FOR_extzv
];
301 return MAX_MACHINE_MODE
;
310 /* Everyone who uses this function used to follow it with
311 if (result == VOIDmode) result = word_mode; */
312 if (data
->operand
[opno
].mode
== VOIDmode
)
314 return data
->operand
[opno
].mode
;
318 /* Generate code to store value from rtx VALUE
319 into a bit-field within structure STR_RTX
320 containing BITSIZE bits starting at bit BITNUM.
321 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
322 ALIGN is the alignment that STR_RTX is known to have.
323 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
325 /* ??? Note that there are two different ideas here for how
326 to determine the size to count bits within, for a register.
327 One is BITS_PER_WORD, and the other is the size of operand 3
330 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
331 else, we use the mode of operand 3. */
334 store_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
335 unsigned HOST_WIDE_INT bitnum
, enum machine_mode fieldmode
,
339 = (MEM_P (str_rtx
)) ? BITS_PER_UNIT
: BITS_PER_WORD
;
340 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
341 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
346 enum machine_mode op_mode
= mode_for_extraction (EP_insv
, 3);
348 while (GET_CODE (op0
) == SUBREG
)
350 /* The following line once was done only if WORDS_BIG_ENDIAN,
351 but I think that is a mistake. WORDS_BIG_ENDIAN is
352 meaningful at a much higher level; when structures are copied
353 between memory and regs, the higher-numbered regs
354 always get higher addresses. */
355 offset
+= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
);
356 /* We used to adjust BITPOS here, but now we do the whole adjustment
357 right after the loop. */
358 op0
= SUBREG_REG (op0
);
361 /* Use vec_set patterns for inserting parts of vectors whenever
363 if (VECTOR_MODE_P (GET_MODE (op0
))
365 && (vec_set_optab
->handlers
[GET_MODE (op0
)].insn_code
367 && fieldmode
== GET_MODE_INNER (GET_MODE (op0
))
368 && bitsize
== GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
369 && !(bitnum
% GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
371 enum machine_mode outermode
= GET_MODE (op0
);
372 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
373 int icode
= (int) vec_set_optab
->handlers
[outermode
].insn_code
;
374 int pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
375 rtx rtxpos
= GEN_INT (pos
);
379 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
380 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
381 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
385 if (! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
))
386 src
= copy_to_mode_reg (mode1
, src
);
388 if (! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
389 rtxpos
= copy_to_mode_reg (mode1
, rtxpos
);
391 /* We could handle this, but we should always be called with a pseudo
392 for our targets and all insns should take them as outputs. */
393 gcc_assert ((*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
)
394 && (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
)
395 && (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
));
396 pat
= GEN_FCN (icode
) (dest
, src
, rtxpos
);
409 int old_generating_concat_p
= generating_concat_p
;
410 generating_concat_p
= 0;
411 value
= force_not_mem (value
);
412 generating_concat_p
= old_generating_concat_p
;
415 /* If the target is a register, overwriting the entire object, or storing
416 a full-word or multi-word field can be done with just a SUBREG.
418 If the target is memory, storing any naturally aligned field can be
419 done with a simple store. For targets that support fast unaligned
420 memory, any naturally sized, unit aligned field can be done directly. */
422 byte_offset
= (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
423 + (offset
* UNITS_PER_WORD
);
426 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
428 ? ((GET_MODE_SIZE (fieldmode
) >= UNITS_PER_WORD
429 || GET_MODE_SIZE (GET_MODE (op0
)) == GET_MODE_SIZE (fieldmode
))
430 && byte_offset
% GET_MODE_SIZE (fieldmode
) == 0)
431 : (! SLOW_UNALIGNED_ACCESS (fieldmode
, MEM_ALIGN (op0
))
432 || (offset
* BITS_PER_UNIT
% bitsize
== 0
433 && MEM_ALIGN (op0
) % GET_MODE_BITSIZE (fieldmode
) == 0))))
435 if (GET_MODE (op0
) != fieldmode
)
438 op0
= adjust_address (op0
, fieldmode
, offset
);
440 op0
= simplify_gen_subreg (fieldmode
, op0
, GET_MODE (op0
),
443 emit_move_insn (op0
, value
);
447 /* Make sure we are playing with integral modes. Pun with subregs
448 if we aren't. This must come after the entire register case above,
449 since that case is valid for any mode. The following cases are only
450 valid for integral modes. */
452 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
453 if (imode
!= GET_MODE (op0
))
456 op0
= adjust_address (op0
, imode
, 0);
459 gcc_assert (imode
!= BLKmode
);
460 op0
= gen_lowpart (imode
, op0
);
465 /* We may be accessing data outside the field, which means
466 we can alias adjacent data. */
469 op0
= shallow_copy_rtx (op0
);
470 set_mem_alias_set (op0
, 0);
471 set_mem_expr (op0
, 0);
474 /* If OP0 is a register, BITPOS must count within a word.
475 But as we have it, it counts within whatever size OP0 now has.
476 On a bigendian machine, these are not the same, so convert. */
479 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
480 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
482 /* Storing an lsb-aligned field in a register
483 can be done with a movestrict instruction. */
486 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0)
487 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
488 && (movstrict_optab
->handlers
[fieldmode
].insn_code
489 != CODE_FOR_nothing
))
491 int icode
= movstrict_optab
->handlers
[fieldmode
].insn_code
;
493 /* Get appropriate low part of the value being stored. */
494 if (GET_CODE (value
) == CONST_INT
|| REG_P (value
))
495 value
= gen_lowpart (fieldmode
, value
);
496 else if (!(GET_CODE (value
) == SYMBOL_REF
497 || GET_CODE (value
) == LABEL_REF
498 || GET_CODE (value
) == CONST
))
499 value
= convert_to_mode (fieldmode
, value
, 0);
501 if (! (*insn_data
[icode
].operand
[1].predicate
) (value
, fieldmode
))
502 value
= copy_to_mode_reg (fieldmode
, value
);
504 if (GET_CODE (op0
) == SUBREG
)
506 /* Else we've got some float mode source being extracted into
507 a different float mode destination -- this combination of
508 subregs results in Severe Tire Damage. */
509 gcc_assert (GET_MODE (SUBREG_REG (op0
)) == fieldmode
510 || GET_MODE_CLASS (fieldmode
) == MODE_INT
511 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
);
512 op0
= SUBREG_REG (op0
);
515 emit_insn (GEN_FCN (icode
)
516 (gen_rtx_SUBREG (fieldmode
, op0
,
517 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
518 + (offset
* UNITS_PER_WORD
)),
524 /* Handle fields bigger than a word. */
526 if (bitsize
> BITS_PER_WORD
)
528 /* Here we transfer the words of the field
529 in the order least significant first.
530 This is because the most significant word is the one which may
532 However, only do that if the value is not BLKmode. */
534 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
535 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
538 /* This is the mode we must force value to, so that there will be enough
539 subwords to extract. Note that fieldmode will often (always?) be
540 VOIDmode, because that is what store_field uses to indicate that this
541 is a bit field, but passing VOIDmode to operand_subword_force will
542 result in an abort. */
543 fieldmode
= GET_MODE (value
);
544 if (fieldmode
== VOIDmode
)
545 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
547 for (i
= 0; i
< nwords
; i
++)
549 /* If I is 0, use the low-order word in both field and target;
550 if I is 1, use the next to lowest word; and so on. */
551 unsigned int wordnum
= (backwards
? nwords
- i
- 1 : i
);
552 unsigned int bit_offset
= (backwards
553 ? MAX ((int) bitsize
- ((int) i
+ 1)
556 : (int) i
* BITS_PER_WORD
);
558 store_bit_field (op0
, MIN (BITS_PER_WORD
,
559 bitsize
- i
* BITS_PER_WORD
),
560 bitnum
+ bit_offset
, word_mode
,
561 operand_subword_force (value
, wordnum
, fieldmode
));
566 /* From here on we can assume that the field to be stored in is
567 a full-word (whatever type that is), since it is shorter than a word. */
569 /* OFFSET is the number of words or bytes (UNIT says which)
570 from STR_RTX to the first word or byte containing part of the field. */
575 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
579 /* Since this is a destination (lvalue), we can't copy it to a
580 pseudo. We can trivially remove a SUBREG that does not
581 change the size of the operand. Such a SUBREG may have been
582 added above. Otherwise, abort. */
583 gcc_assert (GET_CODE (op0
) == SUBREG
584 && (GET_MODE_SIZE (GET_MODE (op0
))
585 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)))));
586 op0
= SUBREG_REG (op0
);
588 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
589 op0
, (offset
* UNITS_PER_WORD
));
594 /* If VALUE has a floating-point or complex mode, access it as an
595 integer of the corresponding size. This can occur on a machine
596 with 64 bit registers that uses SFmode for float. It can also
597 occur for unaligned float or complex fields. */
599 if (GET_MODE (value
) != VOIDmode
600 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_INT
601 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_PARTIAL_INT
)
603 value
= gen_reg_rtx (int_mode_for_mode (GET_MODE (value
)));
604 emit_move_insn (gen_lowpart (GET_MODE (orig_value
), value
), orig_value
);
607 /* Now OFFSET is nonzero only if OP0 is memory
608 and is therefore always measured in bytes. */
611 && GET_MODE (value
) != BLKmode
612 && !(bitsize
== 1 && GET_CODE (value
) == CONST_INT
)
613 /* Ensure insv's size is wide enough for this field. */
614 && (GET_MODE_BITSIZE (op_mode
) >= bitsize
)
615 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
616 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (op_mode
))))
618 int xbitpos
= bitpos
;
621 rtx last
= get_last_insn ();
623 enum machine_mode maxmode
= mode_for_extraction (EP_insv
, 3);
624 int save_volatile_ok
= volatile_ok
;
628 /* If this machine's insv can only insert into a register, copy OP0
629 into a register and save it back later. */
630 /* This used to check flag_force_mem, but that was a serious
631 de-optimization now that flag_force_mem is enabled by -O2. */
633 && ! ((*insn_data
[(int) CODE_FOR_insv
].operand
[0].predicate
)
637 enum machine_mode bestmode
;
639 /* Get the mode to use for inserting into this field. If OP0 is
640 BLKmode, get the smallest mode consistent with the alignment. If
641 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
642 mode. Otherwise, use the smallest mode containing the field. */
644 if (GET_MODE (op0
) == BLKmode
645 || GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (maxmode
))
647 = get_best_mode (bitsize
, bitnum
, MEM_ALIGN (op0
), maxmode
,
648 MEM_VOLATILE_P (op0
));
650 bestmode
= GET_MODE (op0
);
652 if (bestmode
== VOIDmode
653 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (op0
))
654 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (op0
)))
657 /* Adjust address to point to the containing unit of that mode.
658 Compute offset as multiple of this unit, counting in bytes. */
659 unit
= GET_MODE_BITSIZE (bestmode
);
660 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
661 bitpos
= bitnum
% unit
;
662 op0
= adjust_address (op0
, bestmode
, offset
);
664 /* Fetch that unit, store the bitfield in it, then store
666 tempreg
= copy_to_reg (op0
);
667 store_bit_field (tempreg
, bitsize
, bitpos
, fieldmode
, orig_value
);
668 emit_move_insn (op0
, tempreg
);
671 volatile_ok
= save_volatile_ok
;
673 /* Add OFFSET into OP0's address. */
675 xop0
= adjust_address (xop0
, byte_mode
, offset
);
677 /* If xop0 is a register, we need it in MAXMODE
678 to make it acceptable to the format of insv. */
679 if (GET_CODE (xop0
) == SUBREG
)
680 /* We can't just change the mode, because this might clobber op0,
681 and we will need the original value of op0 if insv fails. */
682 xop0
= gen_rtx_SUBREG (maxmode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
683 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
684 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
686 /* On big-endian machines, we count bits from the most significant.
687 If the bit field insn does not, we must invert. */
689 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
690 xbitpos
= unit
- bitsize
- xbitpos
;
692 /* We have been counting XBITPOS within UNIT.
693 Count instead within the size of the register. */
694 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
695 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
697 unit
= GET_MODE_BITSIZE (maxmode
);
699 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
701 if (GET_MODE (value
) != maxmode
)
703 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
705 /* Optimization: Don't bother really extending VALUE
706 if it has all the bits we will actually use. However,
707 if we must narrow it, be sure we do it correctly. */
709 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (maxmode
))
713 tmp
= simplify_subreg (maxmode
, value1
, GET_MODE (value
), 0);
715 tmp
= simplify_gen_subreg (maxmode
,
716 force_reg (GET_MODE (value
),
718 GET_MODE (value
), 0);
722 value1
= gen_lowpart (maxmode
, value1
);
724 else if (GET_CODE (value
) == CONST_INT
)
725 value1
= gen_int_mode (INTVAL (value
), maxmode
);
727 /* Parse phase is supposed to make VALUE's data type
728 match that of the component reference, which is a type
729 at least as wide as the field; so VALUE should have
730 a mode that corresponds to that type. */
731 gcc_assert (CONSTANT_P (value
));
734 /* If this machine's insv insists on a register,
735 get VALUE1 into a register. */
736 if (! ((*insn_data
[(int) CODE_FOR_insv
].operand
[3].predicate
)
738 value1
= force_reg (maxmode
, value1
);
740 pat
= gen_insv (xop0
, GEN_INT (bitsize
), GEN_INT (xbitpos
), value1
);
745 delete_insns_since (last
);
746 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
751 /* Insv is not available; store using shifts and boolean ops. */
752 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
756 /* Use shifts and boolean operations to store VALUE
757 into a bit field of width BITSIZE
758 in a memory location specified by OP0 except offset by OFFSET bytes.
759 (OFFSET must be 0 if OP0 is a register.)
760 The field starts at position BITPOS within the byte.
761 (If OP0 is a register, it may be a full word or a narrower mode,
762 but BITPOS still counts within a full word,
763 which is significant on bigendian machines.) */
766 store_fixed_bit_field (rtx op0
, unsigned HOST_WIDE_INT offset
,
767 unsigned HOST_WIDE_INT bitsize
,
768 unsigned HOST_WIDE_INT bitpos
, rtx value
)
770 enum machine_mode mode
;
771 unsigned int total_bits
= BITS_PER_WORD
;
776 /* There is a case not handled here:
777 a structure with a known alignment of just a halfword
778 and a field split across two aligned halfwords within the structure.
779 Or likewise a structure with a known alignment of just a byte
780 and a field split across two bytes.
781 Such cases are not supposed to be able to occur. */
783 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
785 gcc_assert (!offset
);
786 /* Special treatment for a bit field split across two registers. */
787 if (bitsize
+ bitpos
> BITS_PER_WORD
)
789 store_split_bit_field (op0
, bitsize
, bitpos
, value
);
795 /* Get the proper mode to use for this field. We want a mode that
796 includes the entire field. If such a mode would be larger than
797 a word, we won't be doing the extraction the normal way.
798 We don't want a mode bigger than the destination. */
800 mode
= GET_MODE (op0
);
801 if (GET_MODE_BITSIZE (mode
) == 0
802 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
804 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
805 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
807 if (mode
== VOIDmode
)
809 /* The only way this should occur is if the field spans word
811 store_split_bit_field (op0
, bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
816 total_bits
= GET_MODE_BITSIZE (mode
);
818 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
819 be in the range 0 to total_bits-1, and put any excess bytes in
821 if (bitpos
>= total_bits
)
823 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
824 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
828 /* Get ref to an aligned byte, halfword, or word containing the field.
829 Adjust BITPOS to be position within a word,
830 and OFFSET to be the offset of that word.
831 Then alter OP0 to refer to that word. */
832 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
833 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
834 op0
= adjust_address (op0
, mode
, offset
);
837 mode
= GET_MODE (op0
);
839 /* Now MODE is either some integral mode for a MEM as OP0,
840 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
841 The bit field is contained entirely within OP0.
842 BITPOS is the starting bit number within OP0.
843 (OP0's mode may actually be narrower than MODE.) */
845 if (BYTES_BIG_ENDIAN
)
846 /* BITPOS is the distance between our msb
847 and that of the containing datum.
848 Convert it to the distance from the lsb. */
849 bitpos
= total_bits
- bitsize
- bitpos
;
851 /* Now BITPOS is always the distance between our lsb
854 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
855 we must first convert its mode to MODE. */
857 if (GET_CODE (value
) == CONST_INT
)
859 HOST_WIDE_INT v
= INTVAL (value
);
861 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
862 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
866 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
867 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
868 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
871 value
= lshift_value (mode
, value
, bitpos
, bitsize
);
875 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
876 && bitpos
+ bitsize
!= GET_MODE_BITSIZE (mode
));
878 if (GET_MODE (value
) != mode
)
880 if ((REG_P (value
) || GET_CODE (value
) == SUBREG
)
881 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (value
)))
882 value
= gen_lowpart (mode
, value
);
884 value
= convert_to_mode (mode
, value
, 1);
888 value
= expand_binop (mode
, and_optab
, value
,
889 mask_rtx (mode
, 0, bitsize
, 0),
890 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
892 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
893 build_int_cst (NULL_TREE
, bitpos
), NULL_RTX
, 1);
896 /* Now clear the chosen bits in OP0,
897 except that if VALUE is -1 we need not bother. */
899 subtarget
= (REG_P (op0
) || ! flag_force_mem
) ? op0
: 0;
903 temp
= expand_binop (mode
, and_optab
, op0
,
904 mask_rtx (mode
, bitpos
, bitsize
, 1),
905 subtarget
, 1, OPTAB_LIB_WIDEN
);
911 /* Now logical-or VALUE into OP0, unless it is zero. */
914 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
915 subtarget
, 1, OPTAB_LIB_WIDEN
);
917 emit_move_insn (op0
, temp
);
920 /* Store a bit field that is split across multiple accessible memory objects.
922 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
923 BITSIZE is the field width; BITPOS the position of its first bit
925 VALUE is the value to store.
927 This does not yet handle fields wider than BITS_PER_WORD. */
930 store_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
931 unsigned HOST_WIDE_INT bitpos
, rtx value
)
934 unsigned int bitsdone
= 0;
936 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
938 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
939 unit
= BITS_PER_WORD
;
941 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
943 /* If VALUE is a constant other than a CONST_INT, get it into a register in
944 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
945 that VALUE might be a floating-point constant. */
946 if (CONSTANT_P (value
) && GET_CODE (value
) != CONST_INT
)
948 rtx word
= gen_lowpart_common (word_mode
, value
);
950 if (word
&& (value
!= word
))
953 value
= gen_lowpart_common (word_mode
,
954 force_reg (GET_MODE (value
) != VOIDmode
956 : word_mode
, value
));
959 while (bitsdone
< bitsize
)
961 unsigned HOST_WIDE_INT thissize
;
963 unsigned HOST_WIDE_INT thispos
;
964 unsigned HOST_WIDE_INT offset
;
966 offset
= (bitpos
+ bitsdone
) / unit
;
967 thispos
= (bitpos
+ bitsdone
) % unit
;
969 /* THISSIZE must not overrun a word boundary. Otherwise,
970 store_fixed_bit_field will call us again, and we will mutually
972 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
973 thissize
= MIN (thissize
, unit
- thispos
);
975 if (BYTES_BIG_ENDIAN
)
979 /* We must do an endian conversion exactly the same way as it is
980 done in extract_bit_field, so that the two calls to
981 extract_fixed_bit_field will have comparable arguments. */
982 if (!MEM_P (value
) || GET_MODE (value
) == BLKmode
)
983 total_bits
= BITS_PER_WORD
;
985 total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
987 /* Fetch successively less significant portions. */
988 if (GET_CODE (value
) == CONST_INT
)
989 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
990 >> (bitsize
- bitsdone
- thissize
))
991 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
993 /* The args are chosen so that the last part includes the
994 lsb. Give extract_bit_field the value it needs (with
995 endianness compensation) to fetch the piece we want. */
996 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
997 total_bits
- bitsize
+ bitsdone
,
1002 /* Fetch successively more significant portions. */
1003 if (GET_CODE (value
) == CONST_INT
)
1004 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1006 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1008 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
1009 bitsdone
, NULL_RTX
, 1);
1012 /* If OP0 is a register, then handle OFFSET here.
1014 When handling multiword bitfields, extract_bit_field may pass
1015 down a word_mode SUBREG of a larger REG for a bitfield that actually
1016 crosses a word boundary. Thus, for a SUBREG, we must find
1017 the current word starting from the base register. */
1018 if (GET_CODE (op0
) == SUBREG
)
1020 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1021 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1022 GET_MODE (SUBREG_REG (op0
)));
1025 else if (REG_P (op0
))
1027 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1033 /* OFFSET is in UNITs, and UNIT is in bits.
1034 store_fixed_bit_field wants offset in bytes. */
1035 store_fixed_bit_field (word
, offset
* unit
/ BITS_PER_UNIT
, thissize
,
1037 bitsdone
+= thissize
;
1041 /* Generate code to extract a byte-field from STR_RTX
1042 containing BITSIZE bits, starting at BITNUM,
1043 and put it in TARGET if possible (if TARGET is nonzero).
1044 Regardless of TARGET, we return the rtx for where the value is placed.
1046 STR_RTX is the structure containing the byte (a REG or MEM).
1047 UNSIGNEDP is nonzero if this is an unsigned bit field.
1048 MODE is the natural mode of the field value once extracted.
1049 TMODE is the mode the caller would like the value to have;
1050 but the value may be returned with type MODE instead.
1052 TOTAL_SIZE is the size in bytes of the containing structure,
1055 If a TARGET is specified and we can store in it at no extra cost,
1056 we do so, and return TARGET.
1057 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1058 if they are equally easy. */
1061 extract_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1062 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1063 enum machine_mode mode
, enum machine_mode tmode
)
1066 = (MEM_P (str_rtx
)) ? BITS_PER_UNIT
: BITS_PER_WORD
;
1067 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
1068 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
1070 rtx spec_target
= target
;
1071 rtx spec_target_subreg
= 0;
1072 enum machine_mode int_mode
;
1073 enum machine_mode extv_mode
= mode_for_extraction (EP_extv
, 0);
1074 enum machine_mode extzv_mode
= mode_for_extraction (EP_extzv
, 0);
1075 enum machine_mode mode1
;
1078 if (tmode
== VOIDmode
)
1081 while (GET_CODE (op0
) == SUBREG
)
1083 bitpos
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1086 offset
+= (bitpos
/ unit
);
1089 op0
= SUBREG_REG (op0
);
1093 && mode
== GET_MODE (op0
)
1095 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1097 /* We're trying to extract a full register from itself. */
1101 /* Use vec_extract patterns for extracting parts of vectors whenever
1103 if (VECTOR_MODE_P (GET_MODE (op0
))
1105 && (vec_extract_optab
->handlers
[GET_MODE (op0
)].insn_code
1106 != CODE_FOR_nothing
)
1107 && ((bitnum
+ bitsize
- 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
1108 == bitnum
/ GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
1110 enum machine_mode outermode
= GET_MODE (op0
);
1111 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
1112 int icode
= (int) vec_extract_optab
->handlers
[outermode
].insn_code
;
1113 unsigned HOST_WIDE_INT pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
1114 rtx rtxpos
= GEN_INT (pos
);
1116 rtx dest
= NULL
, pat
, seq
;
1117 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
1118 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
1119 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
1121 if (innermode
== tmode
|| innermode
== mode
)
1125 dest
= gen_reg_rtx (innermode
);
1129 if (! (*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
))
1130 dest
= copy_to_mode_reg (mode0
, dest
);
1132 if (! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
))
1133 src
= copy_to_mode_reg (mode1
, src
);
1135 if (! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
1136 rtxpos
= copy_to_mode_reg (mode1
, rtxpos
);
1138 /* We could handle this, but we should always be called with a pseudo
1139 for our targets and all insns should take them as outputs. */
1140 gcc_assert ((*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
)
1141 && (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
)
1142 && (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
));
1144 pat
= GEN_FCN (icode
) (dest
, src
, rtxpos
);
1155 /* Make sure we are playing with integral modes. Pun with subregs
1158 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1159 if (imode
!= GET_MODE (op0
))
1162 op0
= adjust_address (op0
, imode
, 0);
1165 gcc_assert (imode
!= BLKmode
);
1166 op0
= gen_lowpart (imode
, op0
);
1168 /* If we got a SUBREG, force it into a register since we
1169 aren't going to be able to do another SUBREG on it. */
1170 if (GET_CODE (op0
) == SUBREG
)
1171 op0
= force_reg (imode
, op0
);
1176 /* We may be accessing data outside the field, which means
1177 we can alias adjacent data. */
1180 op0
= shallow_copy_rtx (op0
);
1181 set_mem_alias_set (op0
, 0);
1182 set_mem_expr (op0
, 0);
1185 /* Extraction of a full-word or multi-word value from a structure
1186 in a register or aligned memory can be done with just a SUBREG.
1187 A subword value in the least significant part of a register
1188 can also be extracted with a SUBREG. For this, we need the
1189 byte offset of the value in op0. */
1191 byte_offset
= bitpos
/ BITS_PER_UNIT
+ offset
* UNITS_PER_WORD
;
1193 /* If OP0 is a register, BITPOS must count within a word.
1194 But as we have it, it counts within whatever size OP0 now has.
1195 On a bigendian machine, these are not the same, so convert. */
1196 if (BYTES_BIG_ENDIAN
1198 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
1199 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1201 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1202 If that's wrong, the solution is to test for it and set TARGET to 0
1205 /* Only scalar integer modes can be converted via subregs. There is an
1206 additional problem for FP modes here in that they can have a precision
1207 which is different from the size. mode_for_size uses precision, but
1208 we want a mode based on the size, so we must avoid calling it for FP
1210 mode1
= (SCALAR_INT_MODE_P (tmode
)
1211 ? mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0)
1214 if (((bitsize
>= BITS_PER_WORD
&& bitsize
== GET_MODE_BITSIZE (mode
)
1215 && bitpos
% BITS_PER_WORD
== 0)
1216 || (mode1
!= BLKmode
1217 /* ??? The big endian test here is wrong. This is correct
1218 if the value is in a register, and if mode_for_size is not
1219 the same mode as op0. This causes us to get unnecessarily
1220 inefficient code from the Thumb port when -mbig-endian. */
1221 && (BYTES_BIG_ENDIAN
1222 ? bitpos
+ bitsize
== BITS_PER_WORD
1225 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1226 GET_MODE_BITSIZE (GET_MODE (op0
)))
1227 && GET_MODE_SIZE (mode1
) != 0
1228 && byte_offset
% GET_MODE_SIZE (mode1
) == 0)
1230 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (op0
))
1231 || (offset
* BITS_PER_UNIT
% bitsize
== 0
1232 && MEM_ALIGN (op0
) % bitsize
== 0)))))
1234 if (mode1
!= GET_MODE (op0
))
1237 op0
= adjust_address (op0
, mode1
, offset
);
1240 rtx sub
= simplify_gen_subreg (mode1
, op0
, GET_MODE (op0
),
1243 goto no_subreg_mode_swap
;
1248 return convert_to_mode (tmode
, op0
, unsignedp
);
1251 no_subreg_mode_swap
:
1253 /* Handle fields bigger than a word. */
1255 if (bitsize
> BITS_PER_WORD
)
1257 /* Here we transfer the words of the field
1258 in the order least significant first.
1259 This is because the most significant word is the one which may
1260 be less than full. */
1262 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1265 if (target
== 0 || !REG_P (target
))
1266 target
= gen_reg_rtx (mode
);
1268 /* Indicate for flow that the entire target reg is being set. */
1269 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
1271 for (i
= 0; i
< nwords
; i
++)
1273 /* If I is 0, use the low-order word in both field and target;
1274 if I is 1, use the next to lowest word; and so on. */
1275 /* Word number in TARGET to use. */
1276 unsigned int wordnum
1278 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1280 /* Offset from start of field in OP0. */
1281 unsigned int bit_offset
= (WORDS_BIG_ENDIAN
1282 ? MAX (0, ((int) bitsize
- ((int) i
+ 1)
1283 * (int) BITS_PER_WORD
))
1284 : (int) i
* BITS_PER_WORD
);
1285 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1287 = extract_bit_field (op0
, MIN (BITS_PER_WORD
,
1288 bitsize
- i
* BITS_PER_WORD
),
1289 bitnum
+ bit_offset
, 1, target_part
, mode
,
1292 gcc_assert (target_part
);
1294 if (result_part
!= target_part
)
1295 emit_move_insn (target_part
, result_part
);
1300 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1301 need to be zero'd out. */
1302 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1304 unsigned int i
, total_words
;
1306 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1307 for (i
= nwords
; i
< total_words
; i
++)
1309 (operand_subword (target
,
1310 WORDS_BIG_ENDIAN
? total_words
- i
- 1 : i
,
1317 /* Signed bit field: sign-extend with two arithmetic shifts. */
1318 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1319 build_int_cst (NULL_TREE
,
1320 GET_MODE_BITSIZE (mode
) - bitsize
),
1322 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1323 build_int_cst (NULL_TREE
,
1324 GET_MODE_BITSIZE (mode
) - bitsize
),
1328 /* From here on we know the desired field is smaller than a word. */
1330 /* Check if there is a correspondingly-sized integer field, so we can
1331 safely extract it as one size of integer, if necessary; then
1332 truncate or extend to the size that is wanted; then use SUBREGs or
1333 convert_to_mode to get one of the modes we really wanted. */
1335 int_mode
= int_mode_for_mode (tmode
);
1336 if (int_mode
== BLKmode
)
1337 int_mode
= int_mode_for_mode (mode
);
1338 /* Should probably push op0 out to memory and then do a load. */
1339 gcc_assert (int_mode
!= BLKmode
);
1341 /* OFFSET is the number of words or bytes (UNIT says which)
1342 from STR_RTX to the first word or byte containing part of the field. */
1346 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1349 op0
= copy_to_reg (op0
);
1350 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
1351 op0
, (offset
* UNITS_PER_WORD
));
1356 /* Now OFFSET is nonzero only for memory operands. */
1361 && (GET_MODE_BITSIZE (extzv_mode
) >= bitsize
)
1362 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1363 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extzv_mode
))))
1365 unsigned HOST_WIDE_INT xbitpos
= bitpos
, xoffset
= offset
;
1366 rtx bitsize_rtx
, bitpos_rtx
;
1367 rtx last
= get_last_insn ();
1369 rtx xtarget
= target
;
1370 rtx xspec_target
= spec_target
;
1371 rtx xspec_target_subreg
= spec_target_subreg
;
1373 enum machine_mode maxmode
= mode_for_extraction (EP_extzv
, 0);
1377 int save_volatile_ok
= volatile_ok
;
1380 /* Is the memory operand acceptable? */
1381 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[1].predicate
)
1382 (xop0
, GET_MODE (xop0
))))
1384 /* No, load into a reg and extract from there. */
1385 enum machine_mode bestmode
;
1387 /* Get the mode to use for inserting into this field. If
1388 OP0 is BLKmode, get the smallest mode consistent with the
1389 alignment. If OP0 is a non-BLKmode object that is no
1390 wider than MAXMODE, use its mode. Otherwise, use the
1391 smallest mode containing the field. */
1393 if (GET_MODE (xop0
) == BLKmode
1394 || (GET_MODE_SIZE (GET_MODE (op0
))
1395 > GET_MODE_SIZE (maxmode
)))
1396 bestmode
= get_best_mode (bitsize
, bitnum
,
1397 MEM_ALIGN (xop0
), maxmode
,
1398 MEM_VOLATILE_P (xop0
));
1400 bestmode
= GET_MODE (xop0
);
1402 if (bestmode
== VOIDmode
1403 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1404 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1407 /* Compute offset as multiple of this unit,
1408 counting in bytes. */
1409 unit
= GET_MODE_BITSIZE (bestmode
);
1410 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1411 xbitpos
= bitnum
% unit
;
1412 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1414 /* Fetch it to a register in that size. */
1415 xop0
= force_reg (bestmode
, xop0
);
1417 /* XBITPOS counts within UNIT, which is what is expected. */
1420 /* Get ref to first byte containing part of the field. */
1421 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1423 volatile_ok
= save_volatile_ok
;
1426 /* If op0 is a register, we need it in MAXMODE (which is usually
1427 SImode). to make it acceptable to the format of extzv. */
1428 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1430 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
1431 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1433 /* On big-endian machines, we count bits from the most significant.
1434 If the bit field insn does not, we must invert. */
1435 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1436 xbitpos
= unit
- bitsize
- xbitpos
;
1438 /* Now convert from counting within UNIT to counting in MAXMODE. */
1439 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
1440 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
1442 unit
= GET_MODE_BITSIZE (maxmode
);
1445 || (flag_force_mem
&& MEM_P (xtarget
)))
1446 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1448 if (GET_MODE (xtarget
) != maxmode
)
1450 if (REG_P (xtarget
))
1452 int wider
= (GET_MODE_SIZE (maxmode
)
1453 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1454 xtarget
= gen_lowpart (maxmode
, xtarget
);
1456 xspec_target_subreg
= xtarget
;
1459 xtarget
= gen_reg_rtx (maxmode
);
1462 /* If this machine's extzv insists on a register target,
1463 make sure we have one. */
1464 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[0].predicate
)
1465 (xtarget
, maxmode
)))
1466 xtarget
= gen_reg_rtx (maxmode
);
1468 bitsize_rtx
= GEN_INT (bitsize
);
1469 bitpos_rtx
= GEN_INT (xbitpos
);
1471 pat
= gen_extzv (xtarget
, xop0
, bitsize_rtx
, bitpos_rtx
);
1476 spec_target
= xspec_target
;
1477 spec_target_subreg
= xspec_target_subreg
;
1481 delete_insns_since (last
);
1482 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1488 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1494 && (GET_MODE_BITSIZE (extv_mode
) >= bitsize
)
1495 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1496 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extv_mode
))))
1498 int xbitpos
= bitpos
, xoffset
= offset
;
1499 rtx bitsize_rtx
, bitpos_rtx
;
1500 rtx last
= get_last_insn ();
1501 rtx xop0
= op0
, xtarget
= target
;
1502 rtx xspec_target
= spec_target
;
1503 rtx xspec_target_subreg
= spec_target_subreg
;
1505 enum machine_mode maxmode
= mode_for_extraction (EP_extv
, 0);
1509 /* Is the memory operand acceptable? */
1510 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[1].predicate
)
1511 (xop0
, GET_MODE (xop0
))))
1513 /* No, load into a reg and extract from there. */
1514 enum machine_mode bestmode
;
1516 /* Get the mode to use for inserting into this field. If
1517 OP0 is BLKmode, get the smallest mode consistent with the
1518 alignment. If OP0 is a non-BLKmode object that is no
1519 wider than MAXMODE, use its mode. Otherwise, use the
1520 smallest mode containing the field. */
1522 if (GET_MODE (xop0
) == BLKmode
1523 || (GET_MODE_SIZE (GET_MODE (op0
))
1524 > GET_MODE_SIZE (maxmode
)))
1525 bestmode
= get_best_mode (bitsize
, bitnum
,
1526 MEM_ALIGN (xop0
), maxmode
,
1527 MEM_VOLATILE_P (xop0
));
1529 bestmode
= GET_MODE (xop0
);
1531 if (bestmode
== VOIDmode
1532 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1533 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1536 /* Compute offset as multiple of this unit,
1537 counting in bytes. */
1538 unit
= GET_MODE_BITSIZE (bestmode
);
1539 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1540 xbitpos
= bitnum
% unit
;
1541 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1543 /* Fetch it to a register in that size. */
1544 xop0
= force_reg (bestmode
, xop0
);
1546 /* XBITPOS counts within UNIT, which is what is expected. */
1549 /* Get ref to first byte containing part of the field. */
1550 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1553 /* If op0 is a register, we need it in MAXMODE (which is usually
1554 SImode) to make it acceptable to the format of extv. */
1555 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1557 if (REG_P (xop0
) && GET_MODE (xop0
) != maxmode
)
1558 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1560 /* On big-endian machines, we count bits from the most significant.
1561 If the bit field insn does not, we must invert. */
1562 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1563 xbitpos
= unit
- bitsize
- xbitpos
;
1565 /* XBITPOS counts within a size of UNIT.
1566 Adjust to count within a size of MAXMODE. */
1567 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
1568 xbitpos
+= (GET_MODE_BITSIZE (maxmode
) - unit
);
1570 unit
= GET_MODE_BITSIZE (maxmode
);
1573 || (flag_force_mem
&& MEM_P (xtarget
)))
1574 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1576 if (GET_MODE (xtarget
) != maxmode
)
1578 if (REG_P (xtarget
))
1580 int wider
= (GET_MODE_SIZE (maxmode
)
1581 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1582 xtarget
= gen_lowpart (maxmode
, xtarget
);
1584 xspec_target_subreg
= xtarget
;
1587 xtarget
= gen_reg_rtx (maxmode
);
1590 /* If this machine's extv insists on a register target,
1591 make sure we have one. */
1592 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[0].predicate
)
1593 (xtarget
, maxmode
)))
1594 xtarget
= gen_reg_rtx (maxmode
);
1596 bitsize_rtx
= GEN_INT (bitsize
);
1597 bitpos_rtx
= GEN_INT (xbitpos
);
1599 pat
= gen_extv (xtarget
, xop0
, bitsize_rtx
, bitpos_rtx
);
1604 spec_target
= xspec_target
;
1605 spec_target_subreg
= xspec_target_subreg
;
1609 delete_insns_since (last
);
1610 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1616 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1619 if (target
== spec_target
)
1621 if (target
== spec_target_subreg
)
1623 if (GET_MODE (target
) != tmode
&& GET_MODE (target
) != mode
)
1625 /* If the target mode is not a scalar integral, first convert to the
1626 integer mode of that size and then access it as a floating-point
1627 value via a SUBREG. */
1628 if (!SCALAR_INT_MODE_P (tmode
))
1630 enum machine_mode smode
1631 = mode_for_size (GET_MODE_BITSIZE (tmode
), MODE_INT
, 0);
1632 target
= convert_to_mode (smode
, target
, unsignedp
);
1633 target
= force_reg (smode
, target
);
1634 return gen_lowpart (tmode
, target
);
1637 return convert_to_mode (tmode
, target
, unsignedp
);
1642 /* Extract a bit field using shifts and boolean operations
1643 Returns an rtx to represent the value.
1644 OP0 addresses a register (word) or memory (byte).
1645 BITPOS says which bit within the word or byte the bit field starts in.
1646 OFFSET says how many bytes farther the bit field starts;
1647 it is 0 if OP0 is a register.
1648 BITSIZE says how many bits long the bit field is.
1649 (If OP0 is a register, it may be narrower than a full word,
1650 but BITPOS still counts within a full word,
1651 which is significant on bigendian machines.)
1653 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1654 If TARGET is nonzero, attempts to store the value there
1655 and return TARGET, but this is not guaranteed.
1656 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1659 extract_fixed_bit_field (enum machine_mode tmode
, rtx op0
,
1660 unsigned HOST_WIDE_INT offset
,
1661 unsigned HOST_WIDE_INT bitsize
,
1662 unsigned HOST_WIDE_INT bitpos
, rtx target
,
1665 unsigned int total_bits
= BITS_PER_WORD
;
1666 enum machine_mode mode
;
1668 if (GET_CODE (op0
) == SUBREG
|| REG_P (op0
))
1670 /* Special treatment for a bit field split across two registers. */
1671 if (bitsize
+ bitpos
> BITS_PER_WORD
)
1672 return extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
);
1676 /* Get the proper mode to use for this field. We want a mode that
1677 includes the entire field. If such a mode would be larger than
1678 a word, we won't be doing the extraction the normal way. */
1680 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
1681 MEM_ALIGN (op0
), word_mode
, MEM_VOLATILE_P (op0
));
1683 if (mode
== VOIDmode
)
1684 /* The only way this should occur is if the field spans word
1686 return extract_split_bit_field (op0
, bitsize
,
1687 bitpos
+ offset
* BITS_PER_UNIT
,
1690 total_bits
= GET_MODE_BITSIZE (mode
);
1692 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1693 be in the range 0 to total_bits-1, and put any excess bytes in
1695 if (bitpos
>= total_bits
)
1697 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
1698 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
1702 /* Get ref to an aligned byte, halfword, or word containing the field.
1703 Adjust BITPOS to be position within a word,
1704 and OFFSET to be the offset of that word.
1705 Then alter OP0 to refer to that word. */
1706 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
1707 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
1708 op0
= adjust_address (op0
, mode
, offset
);
1711 mode
= GET_MODE (op0
);
1713 if (BYTES_BIG_ENDIAN
)
1714 /* BITPOS is the distance between our msb and that of OP0.
1715 Convert it to the distance from the lsb. */
1716 bitpos
= total_bits
- bitsize
- bitpos
;
1718 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1719 We have reduced the big-endian case to the little-endian case. */
1725 /* If the field does not already start at the lsb,
1726 shift it so it does. */
1727 tree amount
= build_int_cst (NULL_TREE
, bitpos
);
1728 /* Maybe propagate the target for the shift. */
1729 /* But not if we will return it--could confuse integrate.c. */
1730 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1731 if (tmode
!= mode
) subtarget
= 0;
1732 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1734 /* Convert the value to the desired mode. */
1736 op0
= convert_to_mode (tmode
, op0
, 1);
1738 /* Unless the msb of the field used to be the msb when we shifted,
1739 mask out the upper bits. */
1741 if (GET_MODE_BITSIZE (mode
) != bitpos
+ bitsize
)
1742 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1743 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1744 target
, 1, OPTAB_LIB_WIDEN
);
1748 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1749 then arithmetic-shift its lsb to the lsb of the word. */
1750 op0
= force_reg (mode
, op0
);
1754 /* Find the narrowest integer mode that contains the field. */
1756 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1757 mode
= GET_MODE_WIDER_MODE (mode
))
1758 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitpos
)
1760 op0
= convert_to_mode (mode
, op0
, 0);
1764 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitpos
))
1767 = build_int_cst (NULL_TREE
,
1768 GET_MODE_BITSIZE (mode
) - (bitsize
+ bitpos
));
1769 /* Maybe propagate the target for the shift. */
1770 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1771 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1774 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1775 build_int_cst (NULL_TREE
,
1776 GET_MODE_BITSIZE (mode
) - bitsize
),
1780 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1781 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1782 complement of that if COMPLEMENT. The mask is truncated if
1783 necessary to the width of mode MODE. The mask is zero-extended if
1784 BITSIZE+BITPOS is too small for MODE. */
1787 mask_rtx (enum machine_mode mode
, int bitpos
, int bitsize
, int complement
)
1789 HOST_WIDE_INT masklow
, maskhigh
;
1793 else if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1794 masklow
= (HOST_WIDE_INT
) -1 << bitpos
;
1798 if (bitpos
+ bitsize
< HOST_BITS_PER_WIDE_INT
)
1799 masklow
&= ((unsigned HOST_WIDE_INT
) -1
1800 >> (HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1802 if (bitpos
<= HOST_BITS_PER_WIDE_INT
)
1805 maskhigh
= (HOST_WIDE_INT
) -1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
1809 else if (bitpos
+ bitsize
> HOST_BITS_PER_WIDE_INT
)
1810 maskhigh
&= ((unsigned HOST_WIDE_INT
) -1
1811 >> (2 * HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1817 maskhigh
= ~maskhigh
;
1821 return immed_double_const (masklow
, maskhigh
, mode
);
1824 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1825 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1828 lshift_value (enum machine_mode mode
, rtx value
, int bitpos
, int bitsize
)
1830 unsigned HOST_WIDE_INT v
= INTVAL (value
);
1831 HOST_WIDE_INT low
, high
;
1833 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1834 v
&= ~((HOST_WIDE_INT
) -1 << bitsize
);
1836 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1839 high
= (bitpos
> 0 ? (v
>> (HOST_BITS_PER_WIDE_INT
- bitpos
)) : 0);
1844 high
= v
<< (bitpos
- HOST_BITS_PER_WIDE_INT
);
1847 return immed_double_const (low
, high
, mode
);
1850 /* Extract a bit field from a memory by forcing the alignment of the
1851 memory. This efficient only if the field spans at least 4 boundaries.
1854 BITSIZE is the field width; BITPOS is the position of the first bit.
1855 UNSIGNEDP is true if the result should be zero-extended. */
1858 extract_force_align_mem_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1859 unsigned HOST_WIDE_INT bitpos
,
1862 enum machine_mode mode
, dmode
;
1863 unsigned int m_bitsize
, m_size
;
1864 unsigned int sign_shift_up
, sign_shift_dn
;
1865 rtx base
, a1
, a2
, v1
, v2
, comb
, shift
, result
, start
;
1867 /* Choose a mode that will fit BITSIZE. */
1868 mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
1869 m_size
= GET_MODE_SIZE (mode
);
1870 m_bitsize
= GET_MODE_BITSIZE (mode
);
1872 /* Choose a mode twice as wide. Fail if no such mode exists. */
1873 dmode
= mode_for_size (m_bitsize
* 2, MODE_INT
, false);
1874 if (dmode
== BLKmode
)
1877 do_pending_stack_adjust ();
1878 start
= get_last_insn ();
1880 /* At the end, we'll need an additional shift to deal with sign/zero
1881 extension. By default this will be a left+right shift of the
1882 appropriate size. But we may be able to eliminate one of them. */
1883 sign_shift_up
= sign_shift_dn
= m_bitsize
- bitsize
;
1885 if (STRICT_ALIGNMENT
)
1887 base
= plus_constant (XEXP (op0
, 0), bitpos
/ BITS_PER_UNIT
);
1888 bitpos
%= BITS_PER_UNIT
;
1890 /* We load two values to be concatenate. There's an edge condition
1891 that bears notice -- an aligned value at the end of a page can
1892 only load one value lest we segfault. So the two values we load
1893 are at "base & -size" and "(base + size - 1) & -size". If base
1894 is unaligned, the addresses will be aligned and sequential; if
1895 base is aligned, the addresses will both be equal to base. */
1897 a1
= expand_simple_binop (Pmode
, AND
, force_operand (base
, NULL
),
1898 GEN_INT (-(HOST_WIDE_INT
)m_size
),
1899 NULL
, true, OPTAB_LIB_WIDEN
);
1900 mark_reg_pointer (a1
, m_bitsize
);
1901 v1
= gen_rtx_MEM (mode
, a1
);
1902 set_mem_align (v1
, m_bitsize
);
1903 v1
= force_reg (mode
, validize_mem (v1
));
1905 a2
= plus_constant (base
, GET_MODE_SIZE (mode
) - 1);
1906 a2
= expand_simple_binop (Pmode
, AND
, force_operand (a2
, NULL
),
1907 GEN_INT (-(HOST_WIDE_INT
)m_size
),
1908 NULL
, true, OPTAB_LIB_WIDEN
);
1909 v2
= gen_rtx_MEM (mode
, a2
);
1910 set_mem_align (v2
, m_bitsize
);
1911 v2
= force_reg (mode
, validize_mem (v2
));
1913 /* Combine these two values into a double-word value. */
1914 if (m_bitsize
== BITS_PER_WORD
)
1916 comb
= gen_reg_rtx (dmode
);
1917 emit_insn (gen_rtx_CLOBBER (VOIDmode
, comb
));
1918 emit_move_insn (gen_rtx_SUBREG (mode
, comb
, 0), v1
);
1919 emit_move_insn (gen_rtx_SUBREG (mode
, comb
, m_size
), v2
);
1923 if (BYTES_BIG_ENDIAN
)
1924 comb
= v1
, v1
= v2
, v2
= comb
;
1925 v1
= convert_modes (dmode
, mode
, v1
, true);
1928 v2
= convert_modes (dmode
, mode
, v2
, true);
1929 v2
= expand_simple_binop (dmode
, ASHIFT
, v2
, GEN_INT (m_bitsize
),
1930 NULL
, true, OPTAB_LIB_WIDEN
);
1933 comb
= expand_simple_binop (dmode
, IOR
, v1
, v2
, NULL
,
1934 true, OPTAB_LIB_WIDEN
);
1939 shift
= expand_simple_binop (Pmode
, AND
, base
, GEN_INT (m_size
- 1),
1940 NULL
, true, OPTAB_LIB_WIDEN
);
1941 shift
= expand_mult (Pmode
, shift
, GEN_INT (BITS_PER_UNIT
), NULL
, 1);
1945 if (sign_shift_up
<= bitpos
)
1946 bitpos
-= sign_shift_up
, sign_shift_up
= 0;
1947 shift
= expand_simple_binop (Pmode
, PLUS
, shift
, GEN_INT (bitpos
),
1948 NULL
, true, OPTAB_LIB_WIDEN
);
1953 unsigned HOST_WIDE_INT offset
= bitpos
/ BITS_PER_UNIT
;
1954 bitpos
%= BITS_PER_UNIT
;
1956 /* When strict alignment is not required, we can just load directly
1957 from memory without masking. If the remaining BITPOS offset is
1958 small enough, we may be able to do all operations in MODE as
1959 opposed to DMODE. */
1960 if (bitpos
+ bitsize
<= m_bitsize
)
1962 comb
= adjust_address (op0
, dmode
, offset
);
1964 if (sign_shift_up
<= bitpos
)
1965 bitpos
-= sign_shift_up
, sign_shift_up
= 0;
1966 shift
= GEN_INT (bitpos
);
1969 /* Shift down the double-word such that the requested value is at bit 0. */
1970 if (shift
!= const0_rtx
)
1971 comb
= expand_simple_binop (dmode
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
1972 comb
, shift
, NULL
, unsignedp
, OPTAB_LIB_WIDEN
);
1976 /* If the field exactly matches MODE, then all we need to do is return the
1977 lowpart. Otherwise, shift to get the sign bits set properly. */
1978 result
= force_reg (mode
, gen_lowpart (mode
, comb
));
1981 result
= expand_simple_binop (mode
, ASHIFT
, result
,
1982 GEN_INT (sign_shift_up
),
1983 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
1985 result
= expand_simple_binop (mode
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
1986 result
, GEN_INT (sign_shift_dn
),
1987 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
1992 delete_insns_since (start
);
1996 /* Extract a bit field that is split across two words
1997 and return an RTX for the result.
1999 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
2000 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
2001 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
2004 extract_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
2005 unsigned HOST_WIDE_INT bitpos
, int unsignedp
)
2008 unsigned int bitsdone
= 0;
2009 rtx result
= NULL_RTX
;
2012 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
2014 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
2015 unit
= BITS_PER_WORD
;
2018 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
2019 if (0 && bitsize
/ unit
> 2)
2021 rtx tmp
= extract_force_align_mem_bit_field (op0
, bitsize
, bitpos
,
2028 while (bitsdone
< bitsize
)
2030 unsigned HOST_WIDE_INT thissize
;
2032 unsigned HOST_WIDE_INT thispos
;
2033 unsigned HOST_WIDE_INT offset
;
2035 offset
= (bitpos
+ bitsdone
) / unit
;
2036 thispos
= (bitpos
+ bitsdone
) % unit
;
2038 /* THISSIZE must not overrun a word boundary. Otherwise,
2039 extract_fixed_bit_field will call us again, and we will mutually
2041 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
2042 thissize
= MIN (thissize
, unit
- thispos
);
2044 /* If OP0 is a register, then handle OFFSET here.
2046 When handling multiword bitfields, extract_bit_field may pass
2047 down a word_mode SUBREG of a larger REG for a bitfield that actually
2048 crosses a word boundary. Thus, for a SUBREG, we must find
2049 the current word starting from the base register. */
2050 if (GET_CODE (op0
) == SUBREG
)
2052 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
2053 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
2054 GET_MODE (SUBREG_REG (op0
)));
2057 else if (REG_P (op0
))
2059 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
2065 /* Extract the parts in bit-counting order,
2066 whose meaning is determined by BYTES_PER_UNIT.
2067 OFFSET is in UNITs, and UNIT is in bits.
2068 extract_fixed_bit_field wants offset in bytes. */
2069 part
= extract_fixed_bit_field (word_mode
, word
,
2070 offset
* unit
/ BITS_PER_UNIT
,
2071 thissize
, thispos
, 0, 1);
2072 bitsdone
+= thissize
;
2074 /* Shift this part into place for the result. */
2075 if (BYTES_BIG_ENDIAN
)
2077 if (bitsize
!= bitsdone
)
2078 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2079 build_int_cst (NULL_TREE
, bitsize
- bitsdone
),
2084 if (bitsdone
!= thissize
)
2085 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2086 build_int_cst (NULL_TREE
,
2087 bitsdone
- thissize
), 0, 1);
2093 /* Combine the parts with bitwise or. This works
2094 because we extracted each part as an unsigned bit field. */
2095 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
2101 /* Unsigned bit field: we are done. */
2104 /* Signed bit field: sign-extend with two arithmetic shifts. */
2105 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
2106 build_int_cst (NULL_TREE
, BITS_PER_WORD
- bitsize
),
2108 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
2109 build_int_cst (NULL_TREE
, BITS_PER_WORD
- bitsize
),
2113 /* Add INC into TARGET. */
2116 expand_inc (rtx target
, rtx inc
)
2118 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
2120 target
, 0, OPTAB_LIB_WIDEN
);
2121 if (value
!= target
)
2122 emit_move_insn (target
, value
);
2125 /* Subtract DEC from TARGET. */
2128 expand_dec (rtx target
, rtx dec
)
2130 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
2132 target
, 0, OPTAB_LIB_WIDEN
);
2133 if (value
!= target
)
2134 emit_move_insn (target
, value
);
2137 /* Output a shift instruction for expression code CODE,
2138 with SHIFTED being the rtx for the value to shift,
2139 and AMOUNT the tree for the amount to shift by.
2140 Store the result in the rtx TARGET, if that is convenient.
2141 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2142 Return the rtx for where the value is. */
2145 expand_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2146 tree amount
, rtx target
, int unsignedp
)
2149 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2150 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2153 /* Previously detected shift-counts computed by NEGATE_EXPR
2154 and shifted in the other direction; but that does not work
2157 op1
= expand_expr (amount
, NULL_RTX
, VOIDmode
, 0);
2159 if (SHIFT_COUNT_TRUNCATED
)
2161 if (GET_CODE (op1
) == CONST_INT
2162 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2163 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
2164 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
2165 % GET_MODE_BITSIZE (mode
));
2166 else if (GET_CODE (op1
) == SUBREG
2167 && subreg_lowpart_p (op1
))
2168 op1
= SUBREG_REG (op1
);
2171 if (op1
== const0_rtx
)
2174 /* Check whether its cheaper to implement a left shift by a constant
2175 bit count by a sequence of additions. */
2176 if (code
== LSHIFT_EXPR
2177 && GET_CODE (op1
) == CONST_INT
2179 && INTVAL (op1
) < GET_MODE_BITSIZE (mode
)
2180 && shift_cost
[mode
][INTVAL (op1
)] > INTVAL (op1
) * add_cost
[mode
])
2183 for (i
= 0; i
< INTVAL (op1
); i
++)
2185 temp
= force_reg (mode
, shifted
);
2186 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2187 unsignedp
, OPTAB_LIB_WIDEN
);
2192 for (try = 0; temp
== 0 && try < 3; try++)
2194 enum optab_methods methods
;
2197 methods
= OPTAB_DIRECT
;
2199 methods
= OPTAB_WIDEN
;
2201 methods
= OPTAB_LIB_WIDEN
;
2205 /* Widening does not work for rotation. */
2206 if (methods
== OPTAB_WIDEN
)
2208 else if (methods
== OPTAB_LIB_WIDEN
)
2210 /* If we have been unable to open-code this by a rotation,
2211 do it as the IOR of two shifts. I.e., to rotate A
2212 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2213 where C is the bitsize of A.
2215 It is theoretically possible that the target machine might
2216 not be able to perform either shift and hence we would
2217 be making two libcalls rather than just the one for the
2218 shift (similarly if IOR could not be done). We will allow
2219 this extremely unlikely lossage to avoid complicating the
2222 rtx subtarget
= target
== shifted
? 0 : target
;
2224 tree type
= TREE_TYPE (amount
);
2225 tree new_amount
= make_tree (type
, op1
);
2227 = fold (build2 (MINUS_EXPR
, type
, convert
2228 (type
, build_int_cst
2229 (NULL_TREE
, GET_MODE_BITSIZE (mode
))),
2232 shifted
= force_reg (mode
, shifted
);
2234 temp
= expand_shift (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2235 mode
, shifted
, new_amount
, subtarget
, 1);
2236 temp1
= expand_shift (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2237 mode
, shifted
, other_amount
, 0, 1);
2238 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2239 unsignedp
, methods
);
2242 temp
= expand_binop (mode
,
2243 left
? rotl_optab
: rotr_optab
,
2244 shifted
, op1
, target
, unsignedp
, methods
);
2246 /* If we don't have the rotate, but we are rotating by a constant
2247 that is in range, try a rotate in the opposite direction. */
2249 if (temp
== 0 && GET_CODE (op1
) == CONST_INT
2251 && (unsigned int) INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
2252 temp
= expand_binop (mode
,
2253 left
? rotr_optab
: rotl_optab
,
2255 GEN_INT (GET_MODE_BITSIZE (mode
)
2257 target
, unsignedp
, methods
);
2260 temp
= expand_binop (mode
,
2261 left
? ashl_optab
: lshr_optab
,
2262 shifted
, op1
, target
, unsignedp
, methods
);
2264 /* Do arithmetic shifts.
2265 Also, if we are going to widen the operand, we can just as well
2266 use an arithmetic right-shift instead of a logical one. */
2267 if (temp
== 0 && ! rotate
2268 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2270 enum optab_methods methods1
= methods
;
2272 /* If trying to widen a log shift to an arithmetic shift,
2273 don't accept an arithmetic shift of the same size. */
2275 methods1
= OPTAB_MUST_WIDEN
;
2277 /* Arithmetic shift */
2279 temp
= expand_binop (mode
,
2280 left
? ashl_optab
: ashr_optab
,
2281 shifted
, op1
, target
, unsignedp
, methods1
);
2284 /* We used to try extzv here for logical right shifts, but that was
2285 only useful for one machine, the VAX, and caused poor code
2286 generation there for lshrdi3, so the code was deleted and a
2287 define_expand for lshrsi3 was added to vax.md. */
2294 enum alg_code
{ alg_unknown
, alg_zero
, alg_m
, alg_shift
,
2295 alg_add_t_m2
, alg_sub_t_m2
,
2296 alg_add_factor
, alg_sub_factor
,
2297 alg_add_t2_m
, alg_sub_t2_m
};
2299 /* This structure holds the "cost" of a multiply sequence. The
2300 "cost" field holds the total rtx_cost of every operator in the
2301 synthetic multiplication sequence, hence cost(a op b) is defined
2302 as rtx_cost(op) + cost(a) + cost(b), where cost(leaf) is zero.
2303 The "latency" field holds the minimum possible latency of the
2304 synthetic multiply, on a hypothetical infinitely parallel CPU.
2305 This is the critical path, or the maximum height, of the expression
2306 tree which is the sum of rtx_costs on the most expensive path from
2307 any leaf to the root. Hence latency(a op b) is defined as zero for
2308 leaves and rtx_cost(op) + max(latency(a), latency(b)) otherwise. */
2311 short cost
; /* Total rtx_cost of the multiplication sequence. */
2312 short latency
; /* The latency of the multiplication sequence. */
2315 /* This macro is used to compare a pointer to a mult_cost against an
2316 single integer "rtx_cost" value. This is equivalent to the macro
2317 CHEAPER_MULT_COST(X,Z) where Z = {Y,Y}. */
2318 #define MULT_COST_LESS(X,Y) ((X)->cost < (Y) \
2319 || ((X)->cost == (Y) && (X)->latency < (Y)))
2321 /* This macro is used to compare two pointers to mult_costs against
2322 each other. The macro returns true if X is cheaper than Y.
2323 Currently, the cheaper of two mult_costs is the one with the
2324 lower "cost". If "cost"s are tied, the lower latency is cheaper. */
2325 #define CHEAPER_MULT_COST(X,Y) ((X)->cost < (Y)->cost \
2326 || ((X)->cost == (Y)->cost \
2327 && (X)->latency < (Y)->latency))
2329 /* This structure records a sequence of operations.
2330 `ops' is the number of operations recorded.
2331 `cost' is their total cost.
2332 The operations are stored in `op' and the corresponding
2333 logarithms of the integer coefficients in `log'.
2335 These are the operations:
2336 alg_zero total := 0;
2337 alg_m total := multiplicand;
2338 alg_shift total := total * coeff
2339 alg_add_t_m2 total := total + multiplicand * coeff;
2340 alg_sub_t_m2 total := total - multiplicand * coeff;
2341 alg_add_factor total := total * coeff + total;
2342 alg_sub_factor total := total * coeff - total;
2343 alg_add_t2_m total := total * coeff + multiplicand;
2344 alg_sub_t2_m total := total * coeff - multiplicand;
2346 The first operand must be either alg_zero or alg_m. */
2350 struct mult_cost cost
;
2352 /* The size of the OP and LOG fields are not directly related to the
2353 word size, but the worst-case algorithms will be if we have few
2354 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2355 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2356 in total wordsize operations. */
2357 enum alg_code op
[MAX_BITS_PER_WORD
];
2358 char log
[MAX_BITS_PER_WORD
];
2361 /* The entry for our multiplication cache/hash table. */
2362 struct alg_hash_entry
{
2363 /* The number we are multiplying by. */
2366 /* The mode in which we are multiplying something by T. */
2367 enum machine_mode mode
;
2369 /* The best multiplication algorithm for t. */
2373 /* The number of cache/hash entries. */
2374 #define NUM_ALG_HASH_ENTRIES 307
2376 /* Each entry of ALG_HASH caches alg_code for some integer. This is
2377 actually a hash table. If we have a collision, that the older
2378 entry is kicked out. */
2379 static struct alg_hash_entry alg_hash
[NUM_ALG_HASH_ENTRIES
];
2381 /* Indicates the type of fixup needed after a constant multiplication.
2382 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2383 the result should be negated, and ADD_VARIANT means that the
2384 multiplicand should be added to the result. */
2385 enum mult_variant
{basic_variant
, negate_variant
, add_variant
};
2387 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2388 const struct mult_cost
*, enum machine_mode mode
);
2389 static bool choose_mult_variant (enum machine_mode
, HOST_WIDE_INT
,
2390 struct algorithm
*, enum mult_variant
*, int);
2391 static rtx
expand_mult_const (enum machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2392 const struct algorithm
*, enum mult_variant
);
2393 static unsigned HOST_WIDE_INT
choose_multiplier (unsigned HOST_WIDE_INT
, int,
2394 int, rtx
*, int *, int *);
2395 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2396 static rtx
extract_high_half (enum machine_mode
, rtx
);
2397 static rtx
expand_mult_highpart (enum machine_mode
, rtx
, rtx
, rtx
, int, int);
2398 static rtx
expand_mult_highpart_optab (enum machine_mode
, rtx
, rtx
, rtx
,
2400 /* Compute and return the best algorithm for multiplying by T.
2401 The algorithm must cost less than cost_limit
2402 If retval.cost >= COST_LIMIT, no algorithm was found and all
2403 other field of the returned struct are undefined.
2404 MODE is the machine mode of the multiplication. */
2407 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2408 const struct mult_cost
*cost_limit
, enum machine_mode mode
)
2411 struct algorithm
*alg_in
, *best_alg
;
2412 struct mult_cost best_cost
;
2413 struct mult_cost new_limit
;
2414 int op_cost
, op_latency
;
2415 unsigned HOST_WIDE_INT q
;
2416 int maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (mode
));
2418 bool cache_hit
= false;
2419 enum alg_code cache_alg
= alg_zero
;
2421 /* Indicate that no algorithm is yet found. If no algorithm
2422 is found, this value will be returned and indicate failure. */
2423 alg_out
->cost
.cost
= cost_limit
->cost
+ 1;
2424 alg_out
->cost
.latency
= cost_limit
->latency
+ 1;
2426 if (cost_limit
->cost
< 0
2427 || (cost_limit
->cost
== 0 && cost_limit
->latency
<= 0))
2430 /* Restrict the bits of "t" to the multiplication's mode. */
2431 t
&= GET_MODE_MASK (mode
);
2433 /* t == 1 can be done in zero cost. */
2437 alg_out
->cost
.cost
= 0;
2438 alg_out
->cost
.latency
= 0;
2439 alg_out
->op
[0] = alg_m
;
2443 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2447 if (MULT_COST_LESS (cost_limit
, zero_cost
))
2452 alg_out
->cost
.cost
= zero_cost
;
2453 alg_out
->cost
.latency
= zero_cost
;
2454 alg_out
->op
[0] = alg_zero
;
2459 /* We'll be needing a couple extra algorithm structures now. */
2461 alg_in
= alloca (sizeof (struct algorithm
));
2462 best_alg
= alloca (sizeof (struct algorithm
));
2463 best_cost
= *cost_limit
;
2465 /* Compute the hash index. */
2466 hash_index
= (t
^ (unsigned int) mode
) % NUM_ALG_HASH_ENTRIES
;
2468 /* See if we already know what to do for T. */
2469 if (alg_hash
[hash_index
].t
== t
2470 && alg_hash
[hash_index
].mode
== mode
2471 && alg_hash
[hash_index
].alg
!= alg_unknown
)
2474 cache_alg
= alg_hash
[hash_index
].alg
;
2482 goto do_alg_addsub_t_m2
;
2484 case alg_add_factor
:
2485 case alg_sub_factor
:
2486 goto do_alg_addsub_factor
;
2489 goto do_alg_add_t2_m
;
2492 goto do_alg_sub_t2_m
;
2499 /* If we have a group of zero bits at the low-order part of T, try
2500 multiplying by the remaining bits and then doing a shift. */
2505 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2509 /* The function expand_shift will choose between a shift and
2510 a sequence of additions, so the observed cost is given as
2511 MIN (m * add_cost[mode], shift_cost[mode][m]). */
2512 op_cost
= m
* add_cost
[mode
];
2513 if (shift_cost
[mode
][m
] < op_cost
)
2514 op_cost
= shift_cost
[mode
][m
];
2515 new_limit
.cost
= best_cost
.cost
- op_cost
;
2516 new_limit
.latency
= best_cost
.latency
- op_cost
;
2517 synth_mult (alg_in
, q
, &new_limit
, mode
);
2519 alg_in
->cost
.cost
+= op_cost
;
2520 alg_in
->cost
.latency
+= op_cost
;
2521 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2523 struct algorithm
*x
;
2524 best_cost
= alg_in
->cost
;
2525 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2526 best_alg
->log
[best_alg
->ops
] = m
;
2527 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2534 /* If we have an odd number, add or subtract one. */
2537 unsigned HOST_WIDE_INT w
;
2540 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2542 /* If T was -1, then W will be zero after the loop. This is another
2543 case where T ends with ...111. Handling this with (T + 1) and
2544 subtract 1 produces slightly better code and results in algorithm
2545 selection much faster than treating it like the ...0111 case
2549 /* Reject the case where t is 3.
2550 Thus we prefer addition in that case. */
2553 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2555 op_cost
= add_cost
[mode
];
2556 new_limit
.cost
= best_cost
.cost
- op_cost
;
2557 new_limit
.latency
= best_cost
.latency
- op_cost
;
2558 synth_mult (alg_in
, t
+ 1, &new_limit
, mode
);
2560 alg_in
->cost
.cost
+= op_cost
;
2561 alg_in
->cost
.latency
+= op_cost
;
2562 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2564 struct algorithm
*x
;
2565 best_cost
= alg_in
->cost
;
2566 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2567 best_alg
->log
[best_alg
->ops
] = 0;
2568 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2573 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2575 op_cost
= add_cost
[mode
];
2576 new_limit
.cost
= best_cost
.cost
- op_cost
;
2577 new_limit
.latency
= best_cost
.latency
- op_cost
;
2578 synth_mult (alg_in
, t
- 1, &new_limit
, mode
);
2580 alg_in
->cost
.cost
+= op_cost
;
2581 alg_in
->cost
.latency
+= op_cost
;
2582 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2584 struct algorithm
*x
;
2585 best_cost
= alg_in
->cost
;
2586 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2587 best_alg
->log
[best_alg
->ops
] = 0;
2588 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2595 /* Look for factors of t of the form
2596 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2597 If we find such a factor, we can multiply by t using an algorithm that
2598 multiplies by q, shift the result by m and add/subtract it to itself.
2600 We search for large factors first and loop down, even if large factors
2601 are less probable than small; if we find a large factor we will find a
2602 good sequence quickly, and therefore be able to prune (by decreasing
2603 COST_LIMIT) the search. */
2605 do_alg_addsub_factor
:
2606 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2608 unsigned HOST_WIDE_INT d
;
2610 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2611 if (t
% d
== 0 && t
> d
&& m
< maxm
2612 && (!cache_hit
|| cache_alg
== alg_add_factor
))
2614 /* If the target has a cheap shift-and-add instruction use
2615 that in preference to a shift insn followed by an add insn.
2616 Assume that the shift-and-add is "atomic" with a latency
2617 equal to its cost, otherwise assume that on superscalar
2618 hardware the shift may be executed concurrently with the
2619 earlier steps in the algorithm. */
2620 op_cost
= add_cost
[mode
] + shift_cost
[mode
][m
];
2621 if (shiftadd_cost
[mode
][m
] < op_cost
)
2623 op_cost
= shiftadd_cost
[mode
][m
];
2624 op_latency
= op_cost
;
2627 op_latency
= add_cost
[mode
];
2629 new_limit
.cost
= best_cost
.cost
- op_cost
;
2630 new_limit
.latency
= best_cost
.latency
- op_latency
;
2631 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2633 alg_in
->cost
.cost
+= op_cost
;
2634 alg_in
->cost
.latency
+= op_latency
;
2635 if (alg_in
->cost
.latency
< op_cost
)
2636 alg_in
->cost
.latency
= op_cost
;
2637 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2639 struct algorithm
*x
;
2640 best_cost
= alg_in
->cost
;
2641 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2642 best_alg
->log
[best_alg
->ops
] = m
;
2643 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2645 /* Other factors will have been taken care of in the recursion. */
2649 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2650 if (t
% d
== 0 && t
> d
&& m
< maxm
2651 && (!cache_hit
|| cache_alg
== alg_sub_factor
))
2653 /* If the target has a cheap shift-and-subtract insn use
2654 that in preference to a shift insn followed by a sub insn.
2655 Assume that the shift-and-sub is "atomic" with a latency
2656 equal to it's cost, otherwise assume that on superscalar
2657 hardware the shift may be executed concurrently with the
2658 earlier steps in the algorithm. */
2659 op_cost
= add_cost
[mode
] + shift_cost
[mode
][m
];
2660 if (shiftsub_cost
[mode
][m
] < op_cost
)
2662 op_cost
= shiftsub_cost
[mode
][m
];
2663 op_latency
= op_cost
;
2666 op_latency
= add_cost
[mode
];
2668 new_limit
.cost
= best_cost
.cost
- op_cost
;
2669 new_limit
.latency
= best_cost
.latency
- op_latency
;
2670 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2672 alg_in
->cost
.cost
+= op_cost
;
2673 alg_in
->cost
.latency
+= op_latency
;
2674 if (alg_in
->cost
.latency
< op_cost
)
2675 alg_in
->cost
.latency
= op_cost
;
2676 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2678 struct algorithm
*x
;
2679 best_cost
= alg_in
->cost
;
2680 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2681 best_alg
->log
[best_alg
->ops
] = m
;
2682 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2690 /* Try shift-and-add (load effective address) instructions,
2691 i.e. do a*3, a*5, a*9. */
2698 if (m
>= 0 && m
< maxm
)
2700 op_cost
= shiftadd_cost
[mode
][m
];
2701 new_limit
.cost
= best_cost
.cost
- op_cost
;
2702 new_limit
.latency
= best_cost
.latency
- op_cost
;
2703 synth_mult (alg_in
, (t
- 1) >> m
, &new_limit
, mode
);
2705 alg_in
->cost
.cost
+= op_cost
;
2706 alg_in
->cost
.latency
+= op_cost
;
2707 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2709 struct algorithm
*x
;
2710 best_cost
= alg_in
->cost
;
2711 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2712 best_alg
->log
[best_alg
->ops
] = m
;
2713 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2723 if (m
>= 0 && m
< maxm
)
2725 op_cost
= shiftsub_cost
[mode
][m
];
2726 new_limit
.cost
= best_cost
.cost
- op_cost
;
2727 new_limit
.latency
= best_cost
.latency
- op_cost
;
2728 synth_mult (alg_in
, (t
+ 1) >> m
, &new_limit
, mode
);
2730 alg_in
->cost
.cost
+= op_cost
;
2731 alg_in
->cost
.latency
+= op_cost
;
2732 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2734 struct algorithm
*x
;
2735 best_cost
= alg_in
->cost
;
2736 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2737 best_alg
->log
[best_alg
->ops
] = m
;
2738 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2746 /* If best_cost has not decreased, we have not found any algorithm. */
2747 if (!CHEAPER_MULT_COST (&best_cost
, cost_limit
))
2750 /* Cache the result. */
2753 alg_hash
[hash_index
].t
= t
;
2754 alg_hash
[hash_index
].mode
= mode
;
2755 alg_hash
[hash_index
].alg
= best_alg
->op
[best_alg
->ops
];
2758 /* If we are getting a too long sequence for `struct algorithm'
2759 to record, make this search fail. */
2760 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2763 /* Copy the algorithm from temporary space to the space at alg_out.
2764 We avoid using structure assignment because the majority of
2765 best_alg is normally undefined, and this is a critical function. */
2766 alg_out
->ops
= best_alg
->ops
+ 1;
2767 alg_out
->cost
= best_cost
;
2768 memcpy (alg_out
->op
, best_alg
->op
,
2769 alg_out
->ops
* sizeof *alg_out
->op
);
2770 memcpy (alg_out
->log
, best_alg
->log
,
2771 alg_out
->ops
* sizeof *alg_out
->log
);
2774 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2775 Try three variations:
2777 - a shift/add sequence based on VAL itself
2778 - a shift/add sequence based on -VAL, followed by a negation
2779 - a shift/add sequence based on VAL - 1, followed by an addition.
2781 Return true if the cheapest of these cost less than MULT_COST,
2782 describing the algorithm in *ALG and final fixup in *VARIANT. */
2785 choose_mult_variant (enum machine_mode mode
, HOST_WIDE_INT val
,
2786 struct algorithm
*alg
, enum mult_variant
*variant
,
2789 struct algorithm alg2
;
2790 struct mult_cost limit
;
2793 *variant
= basic_variant
;
2794 limit
.cost
= mult_cost
;
2795 limit
.latency
= mult_cost
;
2796 synth_mult (alg
, val
, &limit
, mode
);
2798 /* This works only if the inverted value actually fits in an
2800 if (HOST_BITS_PER_INT
>= GET_MODE_BITSIZE (mode
))
2802 op_cost
= neg_cost
[mode
];
2803 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2805 limit
.cost
= alg
->cost
.cost
- op_cost
;
2806 limit
.latency
= alg
->cost
.latency
- op_cost
;
2810 limit
.cost
= mult_cost
- op_cost
;
2811 limit
.latency
= mult_cost
- op_cost
;
2814 synth_mult (&alg2
, -val
, &limit
, mode
);
2815 alg2
.cost
.cost
+= op_cost
;
2816 alg2
.cost
.latency
+= op_cost
;
2817 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2818 *alg
= alg2
, *variant
= negate_variant
;
2821 /* This proves very useful for division-by-constant. */
2822 op_cost
= add_cost
[mode
];
2823 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2825 limit
.cost
= alg
->cost
.cost
- op_cost
;
2826 limit
.latency
= alg
->cost
.latency
- op_cost
;
2830 limit
.cost
= mult_cost
- op_cost
;
2831 limit
.latency
= mult_cost
- op_cost
;
2834 synth_mult (&alg2
, val
- 1, &limit
, mode
);
2835 alg2
.cost
.cost
+= op_cost
;
2836 alg2
.cost
.latency
+= op_cost
;
2837 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2838 *alg
= alg2
, *variant
= add_variant
;
2840 return MULT_COST_LESS (&alg
->cost
, mult_cost
);
2843 /* A subroutine of expand_mult, used for constant multiplications.
2844 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2845 convenient. Use the shift/add sequence described by ALG and apply
2846 the final fixup specified by VARIANT. */
2849 expand_mult_const (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
2850 rtx target
, const struct algorithm
*alg
,
2851 enum mult_variant variant
)
2853 HOST_WIDE_INT val_so_far
;
2854 rtx insn
, accum
, tem
;
2856 enum machine_mode nmode
;
2858 /* Avoid referencing memory over and over.
2859 For speed, but also for correctness when mem is volatile. */
2861 op0
= force_reg (mode
, op0
);
2863 /* ACCUM starts out either as OP0 or as a zero, depending on
2864 the first operation. */
2866 if (alg
->op
[0] == alg_zero
)
2868 accum
= copy_to_mode_reg (mode
, const0_rtx
);
2871 else if (alg
->op
[0] == alg_m
)
2873 accum
= copy_to_mode_reg (mode
, op0
);
2879 for (opno
= 1; opno
< alg
->ops
; opno
++)
2881 int log
= alg
->log
[opno
];
2882 rtx shift_subtarget
= optimize
? 0 : accum
;
2884 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
2887 rtx accum_target
= optimize
? 0 : accum
;
2889 switch (alg
->op
[opno
])
2892 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2893 build_int_cst (NULL_TREE
, log
),
2899 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2900 build_int_cst (NULL_TREE
, log
),
2902 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2903 add_target
? add_target
: accum_target
);
2904 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2908 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2909 build_int_cst (NULL_TREE
, log
),
2911 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2912 add_target
? add_target
: accum_target
);
2913 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2917 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2918 build_int_cst (NULL_TREE
, log
),
2921 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2922 add_target
? add_target
: accum_target
);
2923 val_so_far
= (val_so_far
<< log
) + 1;
2927 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2928 build_int_cst (NULL_TREE
, log
),
2929 shift_subtarget
, 0);
2930 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2931 add_target
? add_target
: accum_target
);
2932 val_so_far
= (val_so_far
<< log
) - 1;
2935 case alg_add_factor
:
2936 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2937 build_int_cst (NULL_TREE
, log
),
2939 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2940 add_target
? add_target
: accum_target
);
2941 val_so_far
+= val_so_far
<< log
;
2944 case alg_sub_factor
:
2945 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2946 build_int_cst (NULL_TREE
, log
),
2948 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2950 ? add_target
: (optimize
? 0 : tem
)));
2951 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2958 /* Write a REG_EQUAL note on the last insn so that we can cse
2959 multiplication sequences. Note that if ACCUM is a SUBREG,
2960 we've set the inner register and must properly indicate
2963 tem
= op0
, nmode
= mode
;
2964 if (GET_CODE (accum
) == SUBREG
)
2966 nmode
= GET_MODE (SUBREG_REG (accum
));
2967 tem
= gen_lowpart (nmode
, op0
);
2970 insn
= get_last_insn ();
2971 set_unique_reg_note (insn
, REG_EQUAL
,
2972 gen_rtx_MULT (nmode
, tem
, GEN_INT (val_so_far
)));
2975 if (variant
== negate_variant
)
2977 val_so_far
= -val_so_far
;
2978 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
2980 else if (variant
== add_variant
)
2982 val_so_far
= val_so_far
+ 1;
2983 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
2986 /* Compare only the bits of val and val_so_far that are significant
2987 in the result mode, to avoid sign-/zero-extension confusion. */
2988 val
&= GET_MODE_MASK (mode
);
2989 val_so_far
&= GET_MODE_MASK (mode
);
2990 gcc_assert (val
== val_so_far
);
2995 /* Perform a multiplication and return an rtx for the result.
2996 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2997 TARGET is a suggestion for where to store the result (an rtx).
2999 We check specially for a constant integer as OP1.
3000 If you want this check for OP0 as well, then before calling
3001 you should swap the two operands if OP0 would be constant. */
3004 expand_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3007 rtx const_op1
= op1
;
3008 enum mult_variant variant
;
3009 struct algorithm algorithm
;
3011 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3012 less than or equal in size to `unsigned int' this doesn't matter.
3013 If the mode is larger than `unsigned int', then synth_mult works only
3014 if the constant value exactly fits in an `unsigned int' without any
3015 truncation. This means that multiplying by negative values does
3016 not work; results are off by 2^32 on a 32 bit machine. */
3018 /* If we are multiplying in DImode, it may still be a win
3019 to try to work with shifts and adds. */
3020 if (GET_CODE (op1
) == CONST_DOUBLE
3021 && GET_MODE_CLASS (GET_MODE (op1
)) == MODE_INT
3022 && HOST_BITS_PER_INT
>= BITS_PER_WORD
3023 && CONST_DOUBLE_HIGH (op1
) == 0)
3024 const_op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
3025 else if (HOST_BITS_PER_INT
< GET_MODE_BITSIZE (mode
)
3026 && GET_CODE (op1
) == CONST_INT
3027 && INTVAL (op1
) < 0)
3030 /* We used to test optimize here, on the grounds that it's better to
3031 produce a smaller program when -O is not used.
3032 But this causes such a terrible slowdown sometimes
3033 that it seems better to use synth_mult always. */
3035 if (const_op1
&& GET_CODE (const_op1
) == CONST_INT
3036 && (unsignedp
|| !flag_trapv
))
3038 HOST_WIDE_INT coeff
= INTVAL (const_op1
);
3041 /* Special case powers of two. */
3042 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3048 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3049 build_int_cst (NULL_TREE
, floor_log2 (coeff
)),
3053 mult_cost
= rtx_cost (gen_rtx_MULT (mode
, op0
, op1
), SET
);
3054 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3056 return expand_mult_const (mode
, op0
, coeff
, target
,
3057 &algorithm
, variant
);
3060 if (GET_CODE (op0
) == CONST_DOUBLE
)
3067 /* Expand x*2.0 as x+x. */
3068 if (GET_CODE (op1
) == CONST_DOUBLE
3069 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3072 REAL_VALUE_FROM_CONST_DOUBLE (d
, op1
);
3074 if (REAL_VALUES_EQUAL (d
, dconst2
))
3076 op0
= force_reg (GET_MODE (op0
), op0
);
3077 return expand_binop (mode
, add_optab
, op0
, op0
,
3078 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3082 /* This used to use umul_optab if unsigned, but for non-widening multiply
3083 there is no difference between signed and unsigned. */
3084 op0
= expand_binop (mode
,
3086 && flag_trapv
&& (GET_MODE_CLASS(mode
) == MODE_INT
)
3087 ? smulv_optab
: smul_optab
,
3088 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
3093 /* Return the smallest n such that 2**n >= X. */
3096 ceil_log2 (unsigned HOST_WIDE_INT x
)
3098 return floor_log2 (x
- 1) + 1;
3101 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3102 replace division by D, and put the least significant N bits of the result
3103 in *MULTIPLIER_PTR and return the most significant bit.
3105 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3106 needed precision is in PRECISION (should be <= N).
3108 PRECISION should be as small as possible so this function can choose
3109 multiplier more freely.
3111 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3112 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3114 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3115 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3118 unsigned HOST_WIDE_INT
3119 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
3120 rtx
*multiplier_ptr
, int *post_shift_ptr
, int *lgup_ptr
)
3122 HOST_WIDE_INT mhigh_hi
, mlow_hi
;
3123 unsigned HOST_WIDE_INT mhigh_lo
, mlow_lo
;
3124 int lgup
, post_shift
;
3126 unsigned HOST_WIDE_INT nl
, dummy1
;
3127 HOST_WIDE_INT nh
, dummy2
;
3129 /* lgup = ceil(log2(divisor)); */
3130 lgup
= ceil_log2 (d
);
3132 gcc_assert (lgup
<= n
);
3135 pow2
= n
+ lgup
- precision
;
3137 /* We could handle this with some effort, but this case is much
3138 better handled directly with a scc insn, so rely on caller using
3140 gcc_assert (pow
!= 2 * HOST_BITS_PER_WIDE_INT
);
3142 /* mlow = 2^(N + lgup)/d */
3143 if (pow
>= HOST_BITS_PER_WIDE_INT
)
3145 nh
= (HOST_WIDE_INT
) 1 << (pow
- HOST_BITS_PER_WIDE_INT
);
3151 nl
= (unsigned HOST_WIDE_INT
) 1 << pow
;
3153 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
3154 &mlow_lo
, &mlow_hi
, &dummy1
, &dummy2
);
3156 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
3157 if (pow2
>= HOST_BITS_PER_WIDE_INT
)
3158 nh
|= (HOST_WIDE_INT
) 1 << (pow2
- HOST_BITS_PER_WIDE_INT
);
3160 nl
|= (unsigned HOST_WIDE_INT
) 1 << pow2
;
3161 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
3162 &mhigh_lo
, &mhigh_hi
, &dummy1
, &dummy2
);
3164 gcc_assert (!mhigh_hi
|| nh
- d
< d
);
3165 gcc_assert (mhigh_hi
<= 1 && mlow_hi
<= 1);
3166 /* Assert that mlow < mhigh. */
3167 gcc_assert (mlow_hi
< mhigh_hi
3168 || (mlow_hi
== mhigh_hi
&& mlow_lo
< mhigh_lo
));
3170 /* If precision == N, then mlow, mhigh exceed 2^N
3171 (but they do not exceed 2^(N+1)). */
3173 /* Reduce to lowest terms. */
3174 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
3176 unsigned HOST_WIDE_INT ml_lo
= (mlow_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mlow_lo
>> 1);
3177 unsigned HOST_WIDE_INT mh_lo
= (mhigh_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mhigh_lo
>> 1);
3187 *post_shift_ptr
= post_shift
;
3189 if (n
< HOST_BITS_PER_WIDE_INT
)
3191 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
3192 *multiplier_ptr
= GEN_INT (mhigh_lo
& mask
);
3193 return mhigh_lo
>= mask
;
3197 *multiplier_ptr
= GEN_INT (mhigh_lo
);
3202 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3203 congruent to 1 (mod 2**N). */
3205 static unsigned HOST_WIDE_INT
3206 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
3208 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3210 /* The algorithm notes that the choice y = x satisfies
3211 x*y == 1 mod 2^3, since x is assumed odd.
3212 Each iteration doubles the number of bits of significance in y. */
3214 unsigned HOST_WIDE_INT mask
;
3215 unsigned HOST_WIDE_INT y
= x
;
3218 mask
= (n
== HOST_BITS_PER_WIDE_INT
3219 ? ~(unsigned HOST_WIDE_INT
) 0
3220 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
3224 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
3230 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3231 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3232 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3233 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3236 The result is put in TARGET if that is convenient.
3238 MODE is the mode of operation. */
3241 expand_mult_highpart_adjust (enum machine_mode mode
, rtx adj_operand
, rtx op0
,
3242 rtx op1
, rtx target
, int unsignedp
)
3245 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
3247 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3248 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
) - 1),
3250 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
3252 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3255 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
3256 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
) - 1),
3258 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
3259 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3265 /* Subroutine of expand_mult_highpart. Return the MODE high part of OP. */
3268 extract_high_half (enum machine_mode mode
, rtx op
)
3270 enum machine_mode wider_mode
;
3272 if (mode
== word_mode
)
3273 return gen_highpart (mode
, op
);
3275 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3276 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
3277 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
)), 0, 1);
3278 return convert_modes (mode
, wider_mode
, op
, 0);
3281 /* Like expand_mult_highpart, but only consider using a multiplication
3282 optab. OP1 is an rtx for the constant operand. */
3285 expand_mult_highpart_optab (enum machine_mode mode
, rtx op0
, rtx op1
,
3286 rtx target
, int unsignedp
, int max_cost
)
3288 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
3289 enum machine_mode wider_mode
;
3294 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3295 size
= GET_MODE_BITSIZE (mode
);
3297 /* Firstly, try using a multiplication insn that only generates the needed
3298 high part of the product, and in the sign flavor of unsignedp. */
3299 if (mul_highpart_cost
[mode
] < max_cost
)
3301 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
3302 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3303 unsignedp
, OPTAB_DIRECT
);
3308 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3309 Need to adjust the result after the multiplication. */
3310 if (size
- 1 < BITS_PER_WORD
3311 && (mul_highpart_cost
[mode
] + 2 * shift_cost
[mode
][size
-1]
3312 + 4 * add_cost
[mode
] < max_cost
))
3314 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
3315 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3316 unsignedp
, OPTAB_DIRECT
);
3318 /* We used the wrong signedness. Adjust the result. */
3319 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3323 /* Try widening multiplication. */
3324 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
3325 if (moptab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3326 && mul_widen_cost
[wider_mode
] < max_cost
)
3328 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
3329 unsignedp
, OPTAB_WIDEN
);
3331 return extract_high_half (mode
, tem
);
3334 /* Try widening the mode and perform a non-widening multiplication. */
3335 if (smul_optab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3336 && size
- 1 < BITS_PER_WORD
3337 && mul_cost
[wider_mode
] + shift_cost
[mode
][size
-1] < max_cost
)
3339 rtx insns
, wop0
, wop1
;
3341 /* We need to widen the operands, for example to ensure the
3342 constant multiplier is correctly sign or zero extended.
3343 Use a sequence to clean-up any instructions emitted by
3344 the conversions if things don't work out. */
3346 wop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
3347 wop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
3348 tem
= expand_binop (wider_mode
, smul_optab
, wop0
, wop1
, 0,
3349 unsignedp
, OPTAB_WIDEN
);
3350 insns
= get_insns ();
3356 return extract_high_half (mode
, tem
);
3360 /* Try widening multiplication of opposite signedness, and adjust. */
3361 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3362 if (moptab
->handlers
[wider_mode
].insn_code
!= CODE_FOR_nothing
3363 && size
- 1 < BITS_PER_WORD
3364 && (mul_widen_cost
[wider_mode
] + 2 * shift_cost
[mode
][size
-1]
3365 + 4 * add_cost
[mode
] < max_cost
))
3367 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3368 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3371 tem
= extract_high_half (mode
, tem
);
3372 /* We used the wrong signedness. Adjust the result. */
3373 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3381 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3382 putting the high half of the result in TARGET if that is convenient,
3383 and return where the result is. If the operation can not be performed,
3386 MODE is the mode of operation and result.
3388 UNSIGNEDP nonzero means unsigned multiply.
3390 MAX_COST is the total allowed cost for the expanded RTL. */
3393 expand_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
3394 rtx target
, int unsignedp
, int max_cost
)
3396 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
3397 unsigned HOST_WIDE_INT cnst1
;
3399 bool sign_adjust
= false;
3400 enum mult_variant variant
;
3401 struct algorithm alg
;
3404 /* We can't support modes wider than HOST_BITS_PER_INT. */
3405 gcc_assert (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
);
3407 cnst1
= INTVAL (op1
) & GET_MODE_MASK (mode
);
3409 /* We can't optimize modes wider than BITS_PER_WORD.
3410 ??? We might be able to perform double-word arithmetic if
3411 mode == word_mode, however all the cost calculations in
3412 synth_mult etc. assume single-word operations. */
3413 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3414 return expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3415 unsignedp
, max_cost
);
3417 extra_cost
= shift_cost
[mode
][GET_MODE_BITSIZE (mode
) - 1];
3419 /* Check whether we try to multiply by a negative constant. */
3420 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3423 extra_cost
+= add_cost
[mode
];
3426 /* See whether shift/add multiplication is cheap enough. */
3427 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3428 max_cost
- extra_cost
))
3430 /* See whether the specialized multiplication optabs are
3431 cheaper than the shift/add version. */
3432 tem
= expand_mult_highpart_optab (mode
, op0
, op1
, target
, unsignedp
,
3433 alg
.cost
.cost
+ extra_cost
);
3437 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3438 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3439 tem
= extract_high_half (mode
, tem
);
3441 /* Adjust result for signedness. */
3443 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3447 return expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3448 unsignedp
, max_cost
);
3452 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3455 expand_smod_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3457 unsigned HOST_WIDE_INT masklow
, maskhigh
;
3458 rtx result
, temp
, shift
, label
;
3461 logd
= floor_log2 (d
);
3462 result
= gen_reg_rtx (mode
);
3464 /* Avoid conditional branches when they're expensive. */
3465 if (BRANCH_COST
>= 2
3468 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3472 signmask
= force_reg (mode
, signmask
);
3473 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3474 shift
= GEN_INT (GET_MODE_BITSIZE (mode
) - logd
);
3476 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3477 which instruction sequence to use. If logical right shifts
3478 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3479 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3481 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3482 if (lshr_optab
->handlers
[mode
].insn_code
== CODE_FOR_nothing
3483 || rtx_cost (temp
, SET
) > COSTS_N_INSNS (2))
3485 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3486 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3487 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3488 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3489 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (masklow
),
3490 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3491 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3492 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3493 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3494 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3498 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3499 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3500 signmask
= force_reg (mode
, signmask
);
3502 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3503 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3504 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (masklow
),
3505 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3506 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3507 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3513 /* Mask contains the mode's signbit and the significant bits of the
3514 modulus. By including the signbit in the operation, many targets
3515 can avoid an explicit compare operation in the following comparison
3518 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3519 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3521 masklow
|= (HOST_WIDE_INT
) -1 << (GET_MODE_BITSIZE (mode
) - 1);
3525 maskhigh
= (HOST_WIDE_INT
) -1
3526 << (GET_MODE_BITSIZE (mode
) - HOST_BITS_PER_WIDE_INT
- 1);
3528 temp
= expand_binop (mode
, and_optab
, op0
,
3529 immed_double_const (masklow
, maskhigh
, mode
),
3530 result
, 1, OPTAB_LIB_WIDEN
);
3532 emit_move_insn (result
, temp
);
3534 label
= gen_label_rtx ();
3535 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
3537 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
3538 0, OPTAB_LIB_WIDEN
);
3539 masklow
= (HOST_WIDE_INT
) -1 << logd
;
3541 temp
= expand_binop (mode
, ior_optab
, temp
,
3542 immed_double_const (masklow
, maskhigh
, mode
),
3543 result
, 1, OPTAB_LIB_WIDEN
);
3544 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
3545 0, OPTAB_LIB_WIDEN
);
3547 emit_move_insn (result
, temp
);
3552 /* Expand signed division of OP0 by a power of two D in mode MODE.
3553 This routine is only called for positive values of D. */
3556 expand_sdiv_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3562 logd
= floor_log2 (d
);
3563 shift
= build_int_cst (NULL_TREE
, logd
);
3565 if (d
== 2 && BRANCH_COST
>= 1)
3567 temp
= gen_reg_rtx (mode
);
3568 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
3569 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3570 0, OPTAB_LIB_WIDEN
);
3571 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3574 #ifdef HAVE_conditional_move
3575 if (BRANCH_COST
>= 2)
3579 /* ??? emit_conditional_move forces a stack adjustment via
3580 compare_from_rtx so, if the sequence is discarded, it will
3581 be lost. Do it now instead. */
3582 do_pending_stack_adjust ();
3585 temp2
= copy_to_mode_reg (mode
, op0
);
3586 temp
= expand_binop (mode
, add_optab
, temp2
, GEN_INT (d
-1),
3587 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3588 temp
= force_reg (mode
, temp
);
3590 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3591 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
3592 mode
, temp
, temp2
, mode
, 0);
3595 rtx seq
= get_insns ();
3598 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, shift
, NULL_RTX
, 0);
3604 if (BRANCH_COST
>= 2)
3606 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
3608 temp
= gen_reg_rtx (mode
);
3609 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
3610 if (shift_cost
[mode
][ushift
] > COSTS_N_INSNS (1))
3611 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (d
- 1),
3612 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3614 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
3615 build_int_cst (NULL_TREE
, ushift
),
3617 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3618 0, OPTAB_LIB_WIDEN
);
3619 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3622 label
= gen_label_rtx ();
3623 temp
= copy_to_mode_reg (mode
, op0
);
3624 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
3625 expand_inc (temp
, GEN_INT (d
- 1));
3627 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3630 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3631 if that is convenient, and returning where the result is.
3632 You may request either the quotient or the remainder as the result;
3633 specify REM_FLAG nonzero to get the remainder.
3635 CODE is the expression code for which kind of division this is;
3636 it controls how rounding is done. MODE is the machine mode to use.
3637 UNSIGNEDP nonzero means do unsigned division. */
3639 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3640 and then correct it by or'ing in missing high bits
3641 if result of ANDI is nonzero.
3642 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3643 This could optimize to a bfexts instruction.
3644 But C doesn't use these operations, so their optimizations are
3646 /* ??? For modulo, we don't actually need the highpart of the first product,
3647 the low part will do nicely. And for small divisors, the second multiply
3648 can also be a low-part only multiply or even be completely left out.
3649 E.g. to calculate the remainder of a division by 3 with a 32 bit
3650 multiply, multiply with 0x55555556 and extract the upper two bits;
3651 the result is exact for inputs up to 0x1fffffff.
3652 The input range can be reduced by using cross-sum rules.
3653 For odd divisors >= 3, the following table gives right shift counts
3654 so that if a number is shifted by an integer multiple of the given
3655 amount, the remainder stays the same:
3656 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3657 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3658 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3659 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3660 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3662 Cross-sum rules for even numbers can be derived by leaving as many bits
3663 to the right alone as the divisor has zeros to the right.
3664 E.g. if x is an unsigned 32 bit number:
3665 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3669 expand_divmod (int rem_flag
, enum tree_code code
, enum machine_mode mode
,
3670 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
3672 enum machine_mode compute_mode
;
3674 rtx quotient
= 0, remainder
= 0;
3678 optab optab1
, optab2
;
3679 int op1_is_constant
, op1_is_pow2
= 0;
3680 int max_cost
, extra_cost
;
3681 static HOST_WIDE_INT last_div_const
= 0;
3682 static HOST_WIDE_INT ext_op1
;
3684 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3685 if (op1_is_constant
)
3687 ext_op1
= INTVAL (op1
);
3689 ext_op1
&= GET_MODE_MASK (mode
);
3690 op1_is_pow2
= ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1
)
3691 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1
))));
3695 This is the structure of expand_divmod:
3697 First comes code to fix up the operands so we can perform the operations
3698 correctly and efficiently.
3700 Second comes a switch statement with code specific for each rounding mode.
3701 For some special operands this code emits all RTL for the desired
3702 operation, for other cases, it generates only a quotient and stores it in
3703 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3704 to indicate that it has not done anything.
3706 Last comes code that finishes the operation. If QUOTIENT is set and
3707 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3708 QUOTIENT is not set, it is computed using trunc rounding.
3710 We try to generate special code for division and remainder when OP1 is a
3711 constant. If |OP1| = 2**n we can use shifts and some other fast
3712 operations. For other values of OP1, we compute a carefully selected
3713 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3716 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3717 half of the product. Different strategies for generating the product are
3718 implemented in expand_mult_highpart.
3720 If what we actually want is the remainder, we generate that by another
3721 by-constant multiplication and a subtraction. */
3723 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3724 code below will malfunction if we are, so check here and handle
3725 the special case if so. */
3726 if (op1
== const1_rtx
)
3727 return rem_flag
? const0_rtx
: op0
;
3729 /* When dividing by -1, we could get an overflow.
3730 negv_optab can handle overflows. */
3731 if (! unsignedp
&& op1
== constm1_rtx
)
3735 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
3736 ? negv_optab
: neg_optab
, op0
, target
, 0);
3740 /* Don't use the function value register as a target
3741 since we have to read it as well as write it,
3742 and function-inlining gets confused by this. */
3743 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3744 /* Don't clobber an operand while doing a multi-step calculation. */
3745 || ((rem_flag
|| op1_is_constant
)
3746 && (reg_mentioned_p (target
, op0
)
3747 || (MEM_P (op0
) && MEM_P (target
))))
3748 || reg_mentioned_p (target
, op1
)
3749 || (MEM_P (op1
) && MEM_P (target
))))
3752 /* Get the mode in which to perform this computation. Normally it will
3753 be MODE, but sometimes we can't do the desired operation in MODE.
3754 If so, pick a wider mode in which we can do the operation. Convert
3755 to that mode at the start to avoid repeated conversions.
3757 First see what operations we need. These depend on the expression
3758 we are evaluating. (We assume that divxx3 insns exist under the
3759 same conditions that modxx3 insns and that these insns don't normally
3760 fail. If these assumptions are not correct, we may generate less
3761 efficient code in some cases.)
3763 Then see if we find a mode in which we can open-code that operation
3764 (either a division, modulus, or shift). Finally, check for the smallest
3765 mode for which we can do the operation with a library call. */
3767 /* We might want to refine this now that we have division-by-constant
3768 optimization. Since expand_mult_highpart tries so many variants, it is
3769 not straightforward to generalize this. Maybe we should make an array
3770 of possible modes in init_expmed? Save this for GCC 2.7. */
3772 optab1
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3773 ? (unsignedp
? lshr_optab
: ashr_optab
)
3774 : (unsignedp
? udiv_optab
: sdiv_optab
));
3775 optab2
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3777 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
3779 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3780 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3781 if (optab1
->handlers
[compute_mode
].insn_code
!= CODE_FOR_nothing
3782 || optab2
->handlers
[compute_mode
].insn_code
!= CODE_FOR_nothing
)
3785 if (compute_mode
== VOIDmode
)
3786 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3787 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3788 if (optab1
->handlers
[compute_mode
].libfunc
3789 || optab2
->handlers
[compute_mode
].libfunc
)
3792 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3794 if (compute_mode
== VOIDmode
)
3795 compute_mode
= mode
;
3797 if (target
&& GET_MODE (target
) == compute_mode
)
3800 tquotient
= gen_reg_rtx (compute_mode
);
3802 size
= GET_MODE_BITSIZE (compute_mode
);
3804 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3805 (mode), and thereby get better code when OP1 is a constant. Do that
3806 later. It will require going over all usages of SIZE below. */
3807 size
= GET_MODE_BITSIZE (mode
);
3810 /* Only deduct something for a REM if the last divide done was
3811 for a different constant. Then set the constant of the last
3813 max_cost
= div_cost
[compute_mode
]
3814 - (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3815 && INTVAL (op1
) == last_div_const
)
3816 ? mul_cost
[compute_mode
] + add_cost
[compute_mode
]
3819 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3821 /* Now convert to the best mode to use. */
3822 if (compute_mode
!= mode
)
3824 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3825 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3827 /* convert_modes may have placed op1 into a register, so we
3828 must recompute the following. */
3829 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3830 op1_is_pow2
= (op1_is_constant
3831 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3833 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
)))))) ;
3836 /* If one of the operands is a volatile MEM, copy it into a register. */
3838 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
3839 op0
= force_reg (compute_mode
, op0
);
3840 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
3841 op1
= force_reg (compute_mode
, op1
);
3843 /* If we need the remainder or if OP1 is constant, we need to
3844 put OP0 in a register in case it has any queued subexpressions. */
3845 if (rem_flag
|| op1_is_constant
)
3846 op0
= force_reg (compute_mode
, op0
);
3848 last
= get_last_insn ();
3850 /* Promote floor rounding to trunc rounding for unsigned operations. */
3853 if (code
== FLOOR_DIV_EXPR
)
3854 code
= TRUNC_DIV_EXPR
;
3855 if (code
== FLOOR_MOD_EXPR
)
3856 code
= TRUNC_MOD_EXPR
;
3857 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
3858 code
= TRUNC_DIV_EXPR
;
3861 if (op1
!= const0_rtx
)
3864 case TRUNC_MOD_EXPR
:
3865 case TRUNC_DIV_EXPR
:
3866 if (op1_is_constant
)
3870 unsigned HOST_WIDE_INT mh
;
3871 int pre_shift
, post_shift
;
3874 unsigned HOST_WIDE_INT d
= (INTVAL (op1
)
3875 & GET_MODE_MASK (compute_mode
));
3877 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3879 pre_shift
= floor_log2 (d
);
3883 = expand_binop (compute_mode
, and_optab
, op0
,
3884 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3888 return gen_lowpart (mode
, remainder
);
3890 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3891 build_int_cst (NULL_TREE
,
3895 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3897 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
3899 /* Most significant bit of divisor is set; emit an scc
3901 quotient
= emit_store_flag (tquotient
, GEU
, op0
, op1
,
3902 compute_mode
, 1, 1);
3908 /* Find a suitable multiplier and right shift count
3909 instead of multiplying with D. */
3911 mh
= choose_multiplier (d
, size
, size
,
3912 &ml
, &post_shift
, &dummy
);
3914 /* If the suggested multiplier is more than SIZE bits,
3915 we can do better for even divisors, using an
3916 initial right shift. */
3917 if (mh
!= 0 && (d
& 1) == 0)
3919 pre_shift
= floor_log2 (d
& -d
);
3920 mh
= choose_multiplier (d
>> pre_shift
, size
,
3922 &ml
, &post_shift
, &dummy
);
3932 if (post_shift
- 1 >= BITS_PER_WORD
)
3936 = (shift_cost
[compute_mode
][post_shift
- 1]
3937 + shift_cost
[compute_mode
][1]
3938 + 2 * add_cost
[compute_mode
]);
3939 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3941 max_cost
- extra_cost
);
3944 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
3948 (RSHIFT_EXPR
, compute_mode
, t2
,
3949 build_int_cst (NULL_TREE
, 1),
3951 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
3954 quotient
= expand_shift
3955 (RSHIFT_EXPR
, compute_mode
, t4
,
3956 build_int_cst (NULL_TREE
, post_shift
- 1),
3963 if (pre_shift
>= BITS_PER_WORD
3964 || post_shift
>= BITS_PER_WORD
)
3968 (RSHIFT_EXPR
, compute_mode
, op0
,
3969 build_int_cst (NULL_TREE
, pre_shift
),
3972 = (shift_cost
[compute_mode
][pre_shift
]
3973 + shift_cost
[compute_mode
][post_shift
]);
3974 t2
= expand_mult_highpart (compute_mode
, t1
, ml
,
3976 max_cost
- extra_cost
);
3979 quotient
= expand_shift
3980 (RSHIFT_EXPR
, compute_mode
, t2
,
3981 build_int_cst (NULL_TREE
, post_shift
),
3986 else /* Too wide mode to use tricky code */
3989 insn
= get_last_insn ();
3991 && (set
= single_set (insn
)) != 0
3992 && SET_DEST (set
) == quotient
)
3993 set_unique_reg_note (insn
,
3995 gen_rtx_UDIV (compute_mode
, op0
, op1
));
3997 else /* TRUNC_DIV, signed */
3999 unsigned HOST_WIDE_INT ml
;
4000 int lgup
, post_shift
;
4002 HOST_WIDE_INT d
= INTVAL (op1
);
4003 unsigned HOST_WIDE_INT abs_d
= d
>= 0 ? d
: -d
;
4005 /* n rem d = n rem -d */
4006 if (rem_flag
&& d
< 0)
4009 op1
= gen_int_mode (abs_d
, compute_mode
);
4015 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
4017 else if (abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4019 /* This case is not handled correctly below. */
4020 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
4021 compute_mode
, 1, 1);
4025 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
4026 && (rem_flag
? smod_pow2_cheap
[compute_mode
]
4027 : sdiv_pow2_cheap
[compute_mode
])
4028 /* We assume that cheap metric is true if the
4029 optab has an expander for this mode. */
4030 && (((rem_flag
? smod_optab
: sdiv_optab
)
4031 ->handlers
[compute_mode
].insn_code
4032 != CODE_FOR_nothing
)
4033 || (sdivmod_optab
->handlers
[compute_mode
]
4034 .insn_code
!= CODE_FOR_nothing
)))
4036 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
4040 remainder
= expand_smod_pow2 (compute_mode
, op0
, d
);
4042 return gen_lowpart (mode
, remainder
);
4045 if (sdiv_pow2_cheap
[compute_mode
]
4046 && ((sdiv_optab
->handlers
[compute_mode
].insn_code
4047 != CODE_FOR_nothing
)
4048 || (sdivmod_optab
->handlers
[compute_mode
].insn_code
4049 != CODE_FOR_nothing
)))
4050 quotient
= expand_divmod (0, TRUNC_DIV_EXPR
,
4052 gen_int_mode (abs_d
,
4056 quotient
= expand_sdiv_pow2 (compute_mode
, op0
, abs_d
);
4058 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4059 negate the quotient. */
4062 insn
= get_last_insn ();
4064 && (set
= single_set (insn
)) != 0
4065 && SET_DEST (set
) == quotient
4066 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
4067 << (HOST_BITS_PER_WIDE_INT
- 1)))
4068 set_unique_reg_note (insn
,
4070 gen_rtx_DIV (compute_mode
,
4077 quotient
= expand_unop (compute_mode
, neg_optab
,
4078 quotient
, quotient
, 0);
4081 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4083 choose_multiplier (abs_d
, size
, size
- 1,
4084 &mlr
, &post_shift
, &lgup
);
4085 ml
= (unsigned HOST_WIDE_INT
) INTVAL (mlr
);
4086 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4090 if (post_shift
>= BITS_PER_WORD
4091 || size
- 1 >= BITS_PER_WORD
)
4094 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
4095 + shift_cost
[compute_mode
][size
- 1]
4096 + add_cost
[compute_mode
]);
4097 t1
= expand_mult_highpart (compute_mode
, op0
, mlr
,
4099 max_cost
- extra_cost
);
4103 (RSHIFT_EXPR
, compute_mode
, t1
,
4104 build_int_cst (NULL_TREE
, post_shift
),
4107 (RSHIFT_EXPR
, compute_mode
, op0
,
4108 build_int_cst (NULL_TREE
, size
- 1),
4112 = force_operand (gen_rtx_MINUS (compute_mode
,
4117 = force_operand (gen_rtx_MINUS (compute_mode
,
4125 if (post_shift
>= BITS_PER_WORD
4126 || size
- 1 >= BITS_PER_WORD
)
4129 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
4130 mlr
= gen_int_mode (ml
, compute_mode
);
4131 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
4132 + shift_cost
[compute_mode
][size
- 1]
4133 + 2 * add_cost
[compute_mode
]);
4134 t1
= expand_mult_highpart (compute_mode
, op0
, mlr
,
4136 max_cost
- extra_cost
);
4139 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
4143 (RSHIFT_EXPR
, compute_mode
, t2
,
4144 build_int_cst (NULL_TREE
, post_shift
),
4147 (RSHIFT_EXPR
, compute_mode
, op0
,
4148 build_int_cst (NULL_TREE
, size
- 1),
4152 = force_operand (gen_rtx_MINUS (compute_mode
,
4157 = force_operand (gen_rtx_MINUS (compute_mode
,
4162 else /* Too wide mode to use tricky code */
4165 insn
= get_last_insn ();
4167 && (set
= single_set (insn
)) != 0
4168 && SET_DEST (set
) == quotient
)
4169 set_unique_reg_note (insn
,
4171 gen_rtx_DIV (compute_mode
, op0
, op1
));
4176 delete_insns_since (last
);
4179 case FLOOR_DIV_EXPR
:
4180 case FLOOR_MOD_EXPR
:
4181 /* We will come here only for signed operations. */
4182 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4184 unsigned HOST_WIDE_INT mh
;
4185 int pre_shift
, lgup
, post_shift
;
4186 HOST_WIDE_INT d
= INTVAL (op1
);
4191 /* We could just as easily deal with negative constants here,
4192 but it does not seem worth the trouble for GCC 2.6. */
4193 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4195 pre_shift
= floor_log2 (d
);
4198 remainder
= expand_binop (compute_mode
, and_optab
, op0
,
4199 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
4200 remainder
, 0, OPTAB_LIB_WIDEN
);
4202 return gen_lowpart (mode
, remainder
);
4204 quotient
= expand_shift
4205 (RSHIFT_EXPR
, compute_mode
, op0
,
4206 build_int_cst (NULL_TREE
, pre_shift
),
4213 mh
= choose_multiplier (d
, size
, size
- 1,
4214 &ml
, &post_shift
, &lgup
);
4217 if (post_shift
< BITS_PER_WORD
4218 && size
- 1 < BITS_PER_WORD
)
4221 (RSHIFT_EXPR
, compute_mode
, op0
,
4222 build_int_cst (NULL_TREE
, size
- 1),
4224 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
4225 NULL_RTX
, 0, OPTAB_WIDEN
);
4226 extra_cost
= (shift_cost
[compute_mode
][post_shift
]
4227 + shift_cost
[compute_mode
][size
- 1]
4228 + 2 * add_cost
[compute_mode
]);
4229 t3
= expand_mult_highpart (compute_mode
, t2
, ml
,
4231 max_cost
- extra_cost
);
4235 (RSHIFT_EXPR
, compute_mode
, t3
,
4236 build_int_cst (NULL_TREE
, post_shift
),
4238 quotient
= expand_binop (compute_mode
, xor_optab
,
4239 t4
, t1
, tquotient
, 0,
4247 rtx nsign
, t1
, t2
, t3
, t4
;
4248 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
4249 op0
, constm1_rtx
), NULL_RTX
);
4250 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
4252 nsign
= expand_shift
4253 (RSHIFT_EXPR
, compute_mode
, t2
,
4254 build_int_cst (NULL_TREE
, size
- 1),
4256 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
4258 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
4263 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
4265 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4274 delete_insns_since (last
);
4276 /* Try using an instruction that produces both the quotient and
4277 remainder, using truncation. We can easily compensate the quotient
4278 or remainder to get floor rounding, once we have the remainder.
4279 Notice that we compute also the final remainder value here,
4280 and return the result right away. */
4281 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4282 target
= gen_reg_rtx (compute_mode
);
4287 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4288 quotient
= gen_reg_rtx (compute_mode
);
4293 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4294 remainder
= gen_reg_rtx (compute_mode
);
4297 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
4298 quotient
, remainder
, 0))
4300 /* This could be computed with a branch-less sequence.
4301 Save that for later. */
4303 rtx label
= gen_label_rtx ();
4304 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
4305 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4306 NULL_RTX
, 0, OPTAB_WIDEN
);
4307 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
4308 expand_dec (quotient
, const1_rtx
);
4309 expand_inc (remainder
, op1
);
4311 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4314 /* No luck with division elimination or divmod. Have to do it
4315 by conditionally adjusting op0 *and* the result. */
4317 rtx label1
, label2
, label3
, label4
, label5
;
4321 quotient
= gen_reg_rtx (compute_mode
);
4322 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4323 label1
= gen_label_rtx ();
4324 label2
= gen_label_rtx ();
4325 label3
= gen_label_rtx ();
4326 label4
= gen_label_rtx ();
4327 label5
= gen_label_rtx ();
4328 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4329 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
4330 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4331 quotient
, 0, OPTAB_LIB_WIDEN
);
4332 if (tem
!= quotient
)
4333 emit_move_insn (quotient
, tem
);
4334 emit_jump_insn (gen_jump (label5
));
4336 emit_label (label1
);
4337 expand_inc (adjusted_op0
, const1_rtx
);
4338 emit_jump_insn (gen_jump (label4
));
4340 emit_label (label2
);
4341 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
4342 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4343 quotient
, 0, OPTAB_LIB_WIDEN
);
4344 if (tem
!= quotient
)
4345 emit_move_insn (quotient
, tem
);
4346 emit_jump_insn (gen_jump (label5
));
4348 emit_label (label3
);
4349 expand_dec (adjusted_op0
, const1_rtx
);
4350 emit_label (label4
);
4351 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4352 quotient
, 0, OPTAB_LIB_WIDEN
);
4353 if (tem
!= quotient
)
4354 emit_move_insn (quotient
, tem
);
4355 expand_dec (quotient
, const1_rtx
);
4356 emit_label (label5
);
4364 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
4367 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4368 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4369 build_int_cst (NULL_TREE
, floor_log2 (d
)),
4371 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4373 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4374 t3
= gen_reg_rtx (compute_mode
);
4375 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4376 compute_mode
, 1, 1);
4380 lab
= gen_label_rtx ();
4381 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4382 expand_inc (t1
, const1_rtx
);
4387 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4393 /* Try using an instruction that produces both the quotient and
4394 remainder, using truncation. We can easily compensate the
4395 quotient or remainder to get ceiling rounding, once we have the
4396 remainder. Notice that we compute also the final remainder
4397 value here, and return the result right away. */
4398 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4399 target
= gen_reg_rtx (compute_mode
);
4403 remainder
= (REG_P (target
)
4404 ? target
: gen_reg_rtx (compute_mode
));
4405 quotient
= gen_reg_rtx (compute_mode
);
4409 quotient
= (REG_P (target
)
4410 ? target
: gen_reg_rtx (compute_mode
));
4411 remainder
= gen_reg_rtx (compute_mode
);
4414 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4417 /* This could be computed with a branch-less sequence.
4418 Save that for later. */
4419 rtx label
= gen_label_rtx ();
4420 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4421 compute_mode
, label
);
4422 expand_inc (quotient
, const1_rtx
);
4423 expand_dec (remainder
, op1
);
4425 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4428 /* No luck with division elimination or divmod. Have to do it
4429 by conditionally adjusting op0 *and* the result. */
4432 rtx adjusted_op0
, tem
;
4434 quotient
= gen_reg_rtx (compute_mode
);
4435 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4436 label1
= gen_label_rtx ();
4437 label2
= gen_label_rtx ();
4438 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4439 compute_mode
, label1
);
4440 emit_move_insn (quotient
, const0_rtx
);
4441 emit_jump_insn (gen_jump (label2
));
4443 emit_label (label1
);
4444 expand_dec (adjusted_op0
, const1_rtx
);
4445 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4446 quotient
, 1, OPTAB_LIB_WIDEN
);
4447 if (tem
!= quotient
)
4448 emit_move_insn (quotient
, tem
);
4449 expand_inc (quotient
, const1_rtx
);
4450 emit_label (label2
);
4455 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4456 && INTVAL (op1
) >= 0)
4458 /* This is extremely similar to the code for the unsigned case
4459 above. For 2.7 we should merge these variants, but for
4460 2.6.1 I don't want to touch the code for unsigned since that
4461 get used in C. The signed case will only be used by other
4465 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4466 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4467 build_int_cst (NULL_TREE
, floor_log2 (d
)),
4469 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4471 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4472 t3
= gen_reg_rtx (compute_mode
);
4473 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4474 compute_mode
, 1, 1);
4478 lab
= gen_label_rtx ();
4479 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4480 expand_inc (t1
, const1_rtx
);
4485 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4491 /* Try using an instruction that produces both the quotient and
4492 remainder, using truncation. We can easily compensate the
4493 quotient or remainder to get ceiling rounding, once we have the
4494 remainder. Notice that we compute also the final remainder
4495 value here, and return the result right away. */
4496 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4497 target
= gen_reg_rtx (compute_mode
);
4500 remainder
= (REG_P (target
)
4501 ? target
: gen_reg_rtx (compute_mode
));
4502 quotient
= gen_reg_rtx (compute_mode
);
4506 quotient
= (REG_P (target
)
4507 ? target
: gen_reg_rtx (compute_mode
));
4508 remainder
= gen_reg_rtx (compute_mode
);
4511 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4514 /* This could be computed with a branch-less sequence.
4515 Save that for later. */
4517 rtx label
= gen_label_rtx ();
4518 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4519 compute_mode
, label
);
4520 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4521 NULL_RTX
, 0, OPTAB_WIDEN
);
4522 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4523 expand_inc (quotient
, const1_rtx
);
4524 expand_dec (remainder
, op1
);
4526 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4529 /* No luck with division elimination or divmod. Have to do it
4530 by conditionally adjusting op0 *and* the result. */
4532 rtx label1
, label2
, label3
, label4
, label5
;
4536 quotient
= gen_reg_rtx (compute_mode
);
4537 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4538 label1
= gen_label_rtx ();
4539 label2
= gen_label_rtx ();
4540 label3
= gen_label_rtx ();
4541 label4
= gen_label_rtx ();
4542 label5
= gen_label_rtx ();
4543 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4544 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
4545 compute_mode
, label1
);
4546 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4547 quotient
, 0, OPTAB_LIB_WIDEN
);
4548 if (tem
!= quotient
)
4549 emit_move_insn (quotient
, tem
);
4550 emit_jump_insn (gen_jump (label5
));
4552 emit_label (label1
);
4553 expand_dec (adjusted_op0
, const1_rtx
);
4554 emit_jump_insn (gen_jump (label4
));
4556 emit_label (label2
);
4557 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
4558 compute_mode
, label3
);
4559 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4560 quotient
, 0, OPTAB_LIB_WIDEN
);
4561 if (tem
!= quotient
)
4562 emit_move_insn (quotient
, tem
);
4563 emit_jump_insn (gen_jump (label5
));
4565 emit_label (label3
);
4566 expand_inc (adjusted_op0
, const1_rtx
);
4567 emit_label (label4
);
4568 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4569 quotient
, 0, OPTAB_LIB_WIDEN
);
4570 if (tem
!= quotient
)
4571 emit_move_insn (quotient
, tem
);
4572 expand_inc (quotient
, const1_rtx
);
4573 emit_label (label5
);
4578 case EXACT_DIV_EXPR
:
4579 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4581 HOST_WIDE_INT d
= INTVAL (op1
);
4582 unsigned HOST_WIDE_INT ml
;
4586 pre_shift
= floor_log2 (d
& -d
);
4587 ml
= invert_mod2n (d
>> pre_shift
, size
);
4588 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4589 build_int_cst (NULL_TREE
, pre_shift
),
4590 NULL_RTX
, unsignedp
);
4591 quotient
= expand_mult (compute_mode
, t1
,
4592 gen_int_mode (ml
, compute_mode
),
4595 insn
= get_last_insn ();
4596 set_unique_reg_note (insn
,
4598 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
4604 case ROUND_DIV_EXPR
:
4605 case ROUND_MOD_EXPR
:
4610 label
= gen_label_rtx ();
4611 quotient
= gen_reg_rtx (compute_mode
);
4612 remainder
= gen_reg_rtx (compute_mode
);
4613 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
4616 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
4617 quotient
, 1, OPTAB_LIB_WIDEN
);
4618 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
4619 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4620 remainder
, 1, OPTAB_LIB_WIDEN
);
4622 tem
= plus_constant (op1
, -1);
4623 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4624 build_int_cst (NULL_TREE
, 1),
4626 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
4627 expand_inc (quotient
, const1_rtx
);
4628 expand_dec (remainder
, op1
);
4633 rtx abs_rem
, abs_op1
, tem
, mask
;
4635 label
= gen_label_rtx ();
4636 quotient
= gen_reg_rtx (compute_mode
);
4637 remainder
= gen_reg_rtx (compute_mode
);
4638 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
4641 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
4642 quotient
, 0, OPTAB_LIB_WIDEN
);
4643 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
4644 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4645 remainder
, 0, OPTAB_LIB_WIDEN
);
4647 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
4648 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
4649 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
4650 build_int_cst (NULL_TREE
, 1),
4652 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
4653 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4654 NULL_RTX
, 0, OPTAB_WIDEN
);
4655 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4656 build_int_cst (NULL_TREE
, size
- 1),
4658 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
4659 NULL_RTX
, 0, OPTAB_WIDEN
);
4660 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4661 NULL_RTX
, 0, OPTAB_WIDEN
);
4662 expand_inc (quotient
, tem
);
4663 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
4664 NULL_RTX
, 0, OPTAB_WIDEN
);
4665 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4666 NULL_RTX
, 0, OPTAB_WIDEN
);
4667 expand_dec (remainder
, tem
);
4670 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4678 if (target
&& GET_MODE (target
) != compute_mode
)
4683 /* Try to produce the remainder without producing the quotient.
4684 If we seem to have a divmod pattern that does not require widening,
4685 don't try widening here. We should really have a WIDEN argument
4686 to expand_twoval_binop, since what we'd really like to do here is
4687 1) try a mod insn in compute_mode
4688 2) try a divmod insn in compute_mode
4689 3) try a div insn in compute_mode and multiply-subtract to get
4691 4) try the same things with widening allowed. */
4693 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4696 ((optab2
->handlers
[compute_mode
].insn_code
4697 != CODE_FOR_nothing
)
4698 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4701 /* No luck there. Can we do remainder and divide at once
4702 without a library call? */
4703 remainder
= gen_reg_rtx (compute_mode
);
4704 if (! expand_twoval_binop ((unsignedp
4708 NULL_RTX
, remainder
, unsignedp
))
4713 return gen_lowpart (mode
, remainder
);
4716 /* Produce the quotient. Try a quotient insn, but not a library call.
4717 If we have a divmod in this mode, use it in preference to widening
4718 the div (for this test we assume it will not fail). Note that optab2
4719 is set to the one of the two optabs that the call below will use. */
4721 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
4722 op0
, op1
, rem_flag
? NULL_RTX
: target
,
4724 ((optab2
->handlers
[compute_mode
].insn_code
4725 != CODE_FOR_nothing
)
4726 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4730 /* No luck there. Try a quotient-and-remainder insn,
4731 keeping the quotient alone. */
4732 quotient
= gen_reg_rtx (compute_mode
);
4733 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
4735 quotient
, NULL_RTX
, unsignedp
))
4739 /* Still no luck. If we are not computing the remainder,
4740 use a library call for the quotient. */
4741 quotient
= sign_expand_binop (compute_mode
,
4742 udiv_optab
, sdiv_optab
,
4744 unsignedp
, OPTAB_LIB_WIDEN
);
4751 if (target
&& GET_MODE (target
) != compute_mode
)
4756 /* No divide instruction either. Use library for remainder. */
4757 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4759 unsignedp
, OPTAB_LIB_WIDEN
);
4760 /* No remainder function. Try a quotient-and-remainder
4761 function, keeping the remainder. */
4764 remainder
= gen_reg_rtx (compute_mode
);
4765 if (!expand_twoval_binop_libfunc
4766 (unsignedp
? udivmod_optab
: sdivmod_optab
,
4768 NULL_RTX
, remainder
,
4769 unsignedp
? UMOD
: MOD
))
4770 remainder
= NULL_RTX
;
4775 /* We divided. Now finish doing X - Y * (X / Y). */
4776 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4777 NULL_RTX
, unsignedp
);
4778 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4779 remainder
, target
, unsignedp
,
4784 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4787 /* Return a tree node with data type TYPE, describing the value of X.
4788 Usually this is an VAR_DECL, if there is no obvious better choice.
4789 X may be an expression, however we only support those expressions
4790 generated by loop.c. */
4793 make_tree (tree type
, rtx x
)
4797 switch (GET_CODE (x
))
4801 HOST_WIDE_INT hi
= 0;
4804 && !(TYPE_UNSIGNED (type
)
4805 && (GET_MODE_BITSIZE (TYPE_MODE (type
))
4806 < HOST_BITS_PER_WIDE_INT
)))
4809 t
= build_int_cst_wide (type
, INTVAL (x
), hi
);
4815 if (GET_MODE (x
) == VOIDmode
)
4816 t
= build_int_cst_wide (type
,
4817 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4822 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4823 t
= build_real (type
, d
);
4834 units
= CONST_VECTOR_NUNITS (x
);
4836 /* Build a tree with vector elements. */
4837 for (i
= units
- 1; i
>= 0; --i
)
4839 elt
= CONST_VECTOR_ELT (x
, i
);
4840 t
= tree_cons (NULL_TREE
, make_tree (type
, elt
), t
);
4843 return build_vector (type
, t
);
4847 return fold (build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4848 make_tree (type
, XEXP (x
, 1))));
4851 return fold (build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4852 make_tree (type
, XEXP (x
, 1))));
4855 return fold (build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0))));
4858 return fold (build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4859 make_tree (type
, XEXP (x
, 1))));
4862 return fold (build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4863 make_tree (type
, XEXP (x
, 1))));
4866 t
= lang_hooks
.types
.unsigned_type (type
);
4867 return fold (convert (type
,
4868 build2 (RSHIFT_EXPR
, t
,
4869 make_tree (t
, XEXP (x
, 0)),
4870 make_tree (type
, XEXP (x
, 1)))));
4873 t
= lang_hooks
.types
.signed_type (type
);
4874 return fold (convert (type
,
4875 build2 (RSHIFT_EXPR
, t
,
4876 make_tree (t
, XEXP (x
, 0)),
4877 make_tree (type
, XEXP (x
, 1)))));
4880 if (TREE_CODE (type
) != REAL_TYPE
)
4881 t
= lang_hooks
.types
.signed_type (type
);
4885 return fold (convert (type
,
4886 build2 (TRUNC_DIV_EXPR
, t
,
4887 make_tree (t
, XEXP (x
, 0)),
4888 make_tree (t
, XEXP (x
, 1)))));
4890 t
= lang_hooks
.types
.unsigned_type (type
);
4891 return fold (convert (type
,
4892 build2 (TRUNC_DIV_EXPR
, t
,
4893 make_tree (t
, XEXP (x
, 0)),
4894 make_tree (t
, XEXP (x
, 1)))));
4898 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
4899 GET_CODE (x
) == ZERO_EXTEND
);
4900 return fold (convert (type
, make_tree (t
, XEXP (x
, 0))));
4903 t
= build_decl (VAR_DECL
, NULL_TREE
, type
);
4905 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4906 ptr_mode. So convert. */
4907 if (POINTER_TYPE_P (type
))
4908 x
= convert_memory_address (TYPE_MODE (type
), x
);
4910 /* Note that we do *not* use SET_DECL_RTL here, because we do not
4911 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
4918 /* Check whether the multiplication X * MULT + ADD overflows.
4919 X, MULT and ADD must be CONST_*.
4920 MODE is the machine mode for the computation.
4921 X and MULT must have mode MODE. ADD may have a different mode.
4922 So can X (defaults to same as MODE).
4923 UNSIGNEDP is nonzero to do unsigned multiplication. */
4926 const_mult_add_overflow_p (rtx x
, rtx mult
, rtx add
,
4927 enum machine_mode mode
, int unsignedp
)
4929 tree type
, mult_type
, add_type
, result
;
4931 type
= lang_hooks
.types
.type_for_mode (mode
, unsignedp
);
4933 /* In order to get a proper overflow indication from an unsigned
4934 type, we have to pretend that it's a sizetype. */
4938 /* FIXME:It would be nice if we could step directly from this
4939 type to its sizetype equivalent. */
4940 mult_type
= build_distinct_type_copy (type
);
4941 TYPE_IS_SIZETYPE (mult_type
) = 1;
4944 add_type
= (GET_MODE (add
) == VOIDmode
? mult_type
4945 : lang_hooks
.types
.type_for_mode (GET_MODE (add
), unsignedp
));
4947 result
= fold (build2 (PLUS_EXPR
, mult_type
,
4948 fold (build2 (MULT_EXPR
, mult_type
,
4949 make_tree (mult_type
, x
),
4950 make_tree (mult_type
, mult
))),
4951 make_tree (add_type
, add
)));
4953 return TREE_CONSTANT_OVERFLOW (result
);
4956 /* Return an rtx representing the value of X * MULT + ADD.
4957 TARGET is a suggestion for where to store the result (an rtx).
4958 MODE is the machine mode for the computation.
4959 X and MULT must have mode MODE. ADD may have a different mode.
4960 So can X (defaults to same as MODE).
4961 UNSIGNEDP is nonzero to do unsigned multiplication.
4962 This may emit insns. */
4965 expand_mult_add (rtx x
, rtx target
, rtx mult
, rtx add
, enum machine_mode mode
,
4968 tree type
= lang_hooks
.types
.type_for_mode (mode
, unsignedp
);
4969 tree add_type
= (GET_MODE (add
) == VOIDmode
4970 ? type
: lang_hooks
.types
.type_for_mode (GET_MODE (add
),
4972 tree result
= fold (build2 (PLUS_EXPR
, type
,
4973 fold (build2 (MULT_EXPR
, type
,
4974 make_tree (type
, x
),
4975 make_tree (type
, mult
))),
4976 make_tree (add_type
, add
)));
4978 return expand_expr (result
, target
, VOIDmode
, 0);
4981 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4982 and returning TARGET.
4984 If TARGET is 0, a pseudo-register or constant is returned. */
4987 expand_and (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
4991 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
4992 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
4994 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
4998 else if (tem
!= target
)
4999 emit_move_insn (target
, tem
);
5003 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5004 and storing in TARGET. Normally return TARGET.
5005 Return 0 if that cannot be done.
5007 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5008 it is VOIDmode, they cannot both be CONST_INT.
5010 UNSIGNEDP is for the case where we have to widen the operands
5011 to perform the operation. It says to use zero-extension.
5013 NORMALIZEP is 1 if we should convert the result to be either zero
5014 or one. Normalize is -1 if we should convert the result to be
5015 either zero or -1. If NORMALIZEP is zero, the result will be left
5016 "raw" out of the scc insn. */
5019 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5020 enum machine_mode mode
, int unsignedp
, int normalizep
)
5023 enum insn_code icode
;
5024 enum machine_mode compare_mode
;
5025 enum machine_mode target_mode
= GET_MODE (target
);
5027 rtx last
= get_last_insn ();
5028 rtx pattern
, comparison
;
5031 code
= unsigned_condition (code
);
5033 /* If one operand is constant, make it the second one. Only do this
5034 if the other operand is not constant as well. */
5036 if (swap_commutative_operands_p (op0
, op1
))
5041 code
= swap_condition (code
);
5044 if (mode
== VOIDmode
)
5045 mode
= GET_MODE (op0
);
5047 /* For some comparisons with 1 and -1, we can convert this to
5048 comparisons with zero. This will often produce more opportunities for
5049 store-flag insns. */
5054 if (op1
== const1_rtx
)
5055 op1
= const0_rtx
, code
= LE
;
5058 if (op1
== constm1_rtx
)
5059 op1
= const0_rtx
, code
= LT
;
5062 if (op1
== const1_rtx
)
5063 op1
= const0_rtx
, code
= GT
;
5066 if (op1
== constm1_rtx
)
5067 op1
= const0_rtx
, code
= GE
;
5070 if (op1
== const1_rtx
)
5071 op1
= const0_rtx
, code
= NE
;
5074 if (op1
== const1_rtx
)
5075 op1
= const0_rtx
, code
= EQ
;
5081 /* If we are comparing a double-word integer with zero or -1, we can
5082 convert the comparison into one involving a single word. */
5083 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
5084 && GET_MODE_CLASS (mode
) == MODE_INT
5085 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
5087 if ((code
== EQ
|| code
== NE
)
5088 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
5090 rtx op00
, op01
, op0both
;
5092 /* Do a logical OR or AND of the two words and compare the result. */
5093 op00
= simplify_gen_subreg (word_mode
, op0
, mode
, 0);
5094 op01
= simplify_gen_subreg (word_mode
, op0
, mode
, UNITS_PER_WORD
);
5095 op0both
= expand_binop (word_mode
,
5096 op1
== const0_rtx
? ior_optab
: and_optab
,
5097 op00
, op01
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
5100 return emit_store_flag (target
, code
, op0both
, op1
, word_mode
,
5101 unsignedp
, normalizep
);
5103 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
5107 /* If testing the sign bit, can just test on high word. */
5108 op0h
= simplify_gen_subreg (word_mode
, op0
, mode
,
5109 subreg_highpart_offset (word_mode
, mode
));
5110 return emit_store_flag (target
, code
, op0h
, op1
, word_mode
,
5111 unsignedp
, normalizep
);
5115 /* From now on, we won't change CODE, so set ICODE now. */
5116 icode
= setcc_gen_code
[(int) code
];
5118 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5119 complement of A (for GE) and shifting the sign bit to the low bit. */
5120 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
5121 && GET_MODE_CLASS (mode
) == MODE_INT
5122 && (normalizep
|| STORE_FLAG_VALUE
== 1
5123 || (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5124 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5125 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))))
5129 /* If the result is to be wider than OP0, it is best to convert it
5130 first. If it is to be narrower, it is *incorrect* to convert it
5132 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
5134 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5138 if (target_mode
!= mode
)
5142 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
5143 ((STORE_FLAG_VALUE
== 1 || normalizep
)
5144 ? 0 : subtarget
), 0);
5146 if (STORE_FLAG_VALUE
== 1 || normalizep
)
5147 /* If we are supposed to produce a 0/1 value, we want to do
5148 a logical shift from the sign bit to the low-order bit; for
5149 a -1/0 value, we do an arithmetic shift. */
5150 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5151 size_int (GET_MODE_BITSIZE (mode
) - 1),
5152 subtarget
, normalizep
!= -1);
5154 if (mode
!= target_mode
)
5155 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5160 if (icode
!= CODE_FOR_nothing
)
5162 insn_operand_predicate_fn pred
;
5164 /* We think we may be able to do this with a scc insn. Emit the
5165 comparison and then the scc insn. */
5167 do_pending_stack_adjust ();
5168 last
= get_last_insn ();
5171 = compare_from_rtx (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
);
5172 if (CONSTANT_P (comparison
))
5174 switch (GET_CODE (comparison
))
5177 if (comparison
== const0_rtx
)
5181 #ifdef FLOAT_STORE_FLAG_VALUE
5183 if (comparison
== CONST0_RTX (GET_MODE (comparison
)))
5191 if (normalizep
== 1)
5193 if (normalizep
== -1)
5195 return const_true_rtx
;
5198 /* The code of COMPARISON may not match CODE if compare_from_rtx
5199 decided to swap its operands and reverse the original code.
5201 We know that compare_from_rtx returns either a CONST_INT or
5202 a new comparison code, so it is safe to just extract the
5203 code from COMPARISON. */
5204 code
= GET_CODE (comparison
);
5206 /* Get a reference to the target in the proper mode for this insn. */
5207 compare_mode
= insn_data
[(int) icode
].operand
[0].mode
;
5209 pred
= insn_data
[(int) icode
].operand
[0].predicate
;
5210 if (optimize
|| ! (*pred
) (subtarget
, compare_mode
))
5211 subtarget
= gen_reg_rtx (compare_mode
);
5213 pattern
= GEN_FCN (icode
) (subtarget
);
5216 emit_insn (pattern
);
5218 /* If we are converting to a wider mode, first convert to
5219 TARGET_MODE, then normalize. This produces better combining
5220 opportunities on machines that have a SIGN_EXTRACT when we are
5221 testing a single bit. This mostly benefits the 68k.
5223 If STORE_FLAG_VALUE does not have the sign bit set when
5224 interpreted in COMPARE_MODE, we can do this conversion as
5225 unsigned, which is usually more efficient. */
5226 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (compare_mode
))
5228 convert_move (target
, subtarget
,
5229 (GET_MODE_BITSIZE (compare_mode
)
5230 <= HOST_BITS_PER_WIDE_INT
)
5231 && 0 == (STORE_FLAG_VALUE
5232 & ((HOST_WIDE_INT
) 1
5233 << (GET_MODE_BITSIZE (compare_mode
) -1))));
5235 compare_mode
= target_mode
;
5240 /* If we want to keep subexpressions around, don't reuse our
5246 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
5247 we don't have to do anything. */
5248 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
5250 /* STORE_FLAG_VALUE might be the most negative number, so write
5251 the comparison this way to avoid a compiler-time warning. */
5252 else if (- normalizep
== STORE_FLAG_VALUE
)
5253 op0
= expand_unop (compare_mode
, neg_optab
, op0
, subtarget
, 0);
5255 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
5256 makes it hard to use a value of just the sign bit due to
5257 ANSI integer constant typing rules. */
5258 else if (GET_MODE_BITSIZE (compare_mode
) <= HOST_BITS_PER_WIDE_INT
5259 && (STORE_FLAG_VALUE
5260 & ((HOST_WIDE_INT
) 1
5261 << (GET_MODE_BITSIZE (compare_mode
) - 1))))
5262 op0
= expand_shift (RSHIFT_EXPR
, compare_mode
, op0
,
5263 size_int (GET_MODE_BITSIZE (compare_mode
) - 1),
5264 subtarget
, normalizep
== 1);
5267 gcc_assert (STORE_FLAG_VALUE
& 1);
5269 op0
= expand_and (compare_mode
, op0
, const1_rtx
, subtarget
);
5270 if (normalizep
== -1)
5271 op0
= expand_unop (compare_mode
, neg_optab
, op0
, op0
, 0);
5274 /* If we were converting to a smaller mode, do the
5276 if (target_mode
!= compare_mode
)
5278 convert_move (target
, op0
, 0);
5286 delete_insns_since (last
);
5288 /* If optimizing, use different pseudo registers for each insn, instead
5289 of reusing the same pseudo. This leads to better CSE, but slows
5290 down the compiler, since there are more pseudos */
5291 subtarget
= (!optimize
5292 && (target_mode
== mode
)) ? target
: NULL_RTX
;
5294 /* If we reached here, we can't do this with a scc insn. However, there
5295 are some comparisons that can be done directly. For example, if
5296 this is an equality comparison of integers, we can try to exclusive-or
5297 (or subtract) the two operands and use a recursive call to try the
5298 comparison with zero. Don't do any of these cases if branches are
5302 && GET_MODE_CLASS (mode
) == MODE_INT
&& (code
== EQ
|| code
== NE
)
5303 && op1
!= const0_rtx
)
5305 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
5309 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
5312 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
5313 mode
, unsignedp
, normalizep
);
5315 delete_insns_since (last
);
5319 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5320 the constant zero. Reject all other comparisons at this point. Only
5321 do LE and GT if branches are expensive since they are expensive on
5322 2-operand machines. */
5324 if (BRANCH_COST
== 0
5325 || GET_MODE_CLASS (mode
) != MODE_INT
|| op1
!= const0_rtx
5326 || (code
!= EQ
&& code
!= NE
5327 && (BRANCH_COST
<= 1 || (code
!= LE
&& code
!= GT
))))
5330 /* See what we need to return. We can only return a 1, -1, or the
5333 if (normalizep
== 0)
5335 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5336 normalizep
= STORE_FLAG_VALUE
;
5338 else if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5339 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5340 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
5346 /* Try to put the result of the comparison in the sign bit. Assume we can't
5347 do the necessary operation below. */
5351 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5352 the sign bit set. */
5356 /* This is destructive, so SUBTARGET can't be OP0. */
5357 if (rtx_equal_p (subtarget
, op0
))
5360 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
5363 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
5367 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5368 number of bits in the mode of OP0, minus one. */
5372 if (rtx_equal_p (subtarget
, op0
))
5375 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5376 size_int (GET_MODE_BITSIZE (mode
) - 1),
5378 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5382 if (code
== EQ
|| code
== NE
)
5384 /* For EQ or NE, one way to do the comparison is to apply an operation
5385 that converts the operand into a positive number if it is nonzero
5386 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5387 for NE we negate. This puts the result in the sign bit. Then we
5388 normalize with a shift, if needed.
5390 Two operations that can do the above actions are ABS and FFS, so try
5391 them. If that doesn't work, and MODE is smaller than a full word,
5392 we can use zero-extension to the wider mode (an unsigned conversion)
5393 as the operation. */
5395 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5396 that is compensated by the subsequent overflow when subtracting
5399 if (abs_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
)
5400 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5401 else if (ffs_optab
->handlers
[mode
].insn_code
!= CODE_FOR_nothing
)
5402 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5403 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5405 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5412 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5415 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5418 /* If we couldn't do it that way, for NE we can "or" the two's complement
5419 of the value with itself. For EQ, we take the one's complement of
5420 that "or", which is an extra insn, so we only handle EQ if branches
5423 if (tem
== 0 && (code
== NE
|| BRANCH_COST
> 1))
5425 if (rtx_equal_p (subtarget
, op0
))
5428 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5429 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5432 if (tem
&& code
== EQ
)
5433 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5437 if (tem
&& normalizep
)
5438 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
5439 size_int (GET_MODE_BITSIZE (mode
) - 1),
5440 subtarget
, normalizep
== 1);
5444 if (GET_MODE (tem
) != target_mode
)
5446 convert_move (target
, tem
, 0);
5449 else if (!subtarget
)
5451 emit_move_insn (target
, tem
);
5456 delete_insns_since (last
);
5461 /* Like emit_store_flag, but always succeeds. */
5464 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5465 enum machine_mode mode
, int unsignedp
, int normalizep
)
5469 /* First see if emit_store_flag can do the job. */
5470 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
5474 if (normalizep
== 0)
5477 /* If this failed, we have to do this with set/compare/jump/set code. */
5480 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
5481 target
= gen_reg_rtx (GET_MODE (target
));
5483 emit_move_insn (target
, const1_rtx
);
5484 label
= gen_label_rtx ();
5485 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
5488 emit_move_insn (target
, const0_rtx
);
5494 /* Perform possibly multi-word comparison and conditional jump to LABEL
5495 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
5497 The algorithm is based on the code in expr.c:do_jump.
5499 Note that this does not perform a general comparison. Only variants
5500 generated within expmed.c are correctly handled, others abort (but could
5501 be handled if needed). */
5504 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, enum machine_mode mode
,
5507 /* If this mode is an integer too wide to compare properly,
5508 compare word by word. Rely on cse to optimize constant cases. */
5510 if (GET_MODE_CLASS (mode
) == MODE_INT
5511 && ! can_compare_p (op
, mode
, ccp_jump
))
5513 rtx label2
= gen_label_rtx ();
5518 do_jump_by_parts_greater_rtx (mode
, 1, arg2
, arg1
, label2
, label
);
5522 do_jump_by_parts_greater_rtx (mode
, 1, arg1
, arg2
, label
, label2
);
5526 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label2
, label
);
5530 do_jump_by_parts_greater_rtx (mode
, 0, arg1
, arg2
, label2
, label
);
5534 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label
, label2
);
5537 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
5538 that's the only equality operations we do */
5540 gcc_assert (arg2
== const0_rtx
&& mode
== GET_MODE(arg1
));
5541 do_jump_by_parts_equality_rtx (arg1
, label2
, label
);
5545 gcc_assert (arg2
== const0_rtx
&& mode
== GET_MODE(arg1
));
5546 do_jump_by_parts_equality_rtx (arg1
, label
, label2
);
5553 emit_label (label2
);
5556 emit_cmp_and_jump_insns (arg1
, arg2
, op
, NULL_RTX
, mode
, 0, label
);