1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987-2018 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
36 #include "diagnostic-core.h"
37 #include "fold-const.h"
38 #include "stor-layout.h"
42 #include "langhooks.h"
43 #include "tree-vector-builder.h"
45 struct target_expmed default_target_expmed
;
47 struct target_expmed
*this_target_expmed
= &default_target_expmed
;
50 static bool store_integral_bit_field (rtx
, opt_scalar_int_mode
,
51 unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
,
53 poly_uint64
, poly_uint64
,
54 machine_mode
, rtx
, bool, bool);
55 static void store_fixed_bit_field (rtx
, opt_scalar_int_mode
,
56 unsigned HOST_WIDE_INT
,
57 unsigned HOST_WIDE_INT
,
58 poly_uint64
, poly_uint64
,
59 rtx
, scalar_int_mode
, bool);
60 static void store_fixed_bit_field_1 (rtx
, scalar_int_mode
,
61 unsigned HOST_WIDE_INT
,
62 unsigned HOST_WIDE_INT
,
63 rtx
, scalar_int_mode
, bool);
64 static void store_split_bit_field (rtx
, opt_scalar_int_mode
,
65 unsigned HOST_WIDE_INT
,
66 unsigned HOST_WIDE_INT
,
67 poly_uint64
, poly_uint64
,
68 rtx
, scalar_int_mode
, bool);
69 static rtx
extract_integral_bit_field (rtx
, opt_scalar_int_mode
,
70 unsigned HOST_WIDE_INT
,
71 unsigned HOST_WIDE_INT
, int, rtx
,
72 machine_mode
, machine_mode
, bool, bool);
73 static rtx
extract_fixed_bit_field (machine_mode
, rtx
, opt_scalar_int_mode
,
74 unsigned HOST_WIDE_INT
,
75 unsigned HOST_WIDE_INT
, rtx
, int, bool);
76 static rtx
extract_fixed_bit_field_1 (machine_mode
, rtx
, scalar_int_mode
,
77 unsigned HOST_WIDE_INT
,
78 unsigned HOST_WIDE_INT
, rtx
, int, bool);
79 static rtx
lshift_value (machine_mode
, unsigned HOST_WIDE_INT
, int);
80 static rtx
extract_split_bit_field (rtx
, opt_scalar_int_mode
,
81 unsigned HOST_WIDE_INT
,
82 unsigned HOST_WIDE_INT
, int, bool);
83 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, machine_mode
, rtx_code_label
*);
84 static rtx
expand_smod_pow2 (scalar_int_mode
, rtx
, HOST_WIDE_INT
);
85 static rtx
expand_sdiv_pow2 (scalar_int_mode
, rtx
, HOST_WIDE_INT
);
87 /* Return a constant integer mask value of mode MODE with BITSIZE ones
88 followed by BITPOS zeros, or the complement of that if COMPLEMENT.
89 The mask is truncated if necessary to the width of mode MODE. The
90 mask is zero-extended if BITSIZE+BITPOS is too small for MODE. */
93 mask_rtx (scalar_int_mode mode
, int bitpos
, int bitsize
, bool complement
)
95 return immed_wide_int_const
96 (wi::shifted_mask (bitpos
, bitsize
, complement
,
97 GET_MODE_PRECISION (mode
)), mode
);
100 /* Test whether a value is zero of a power of two. */
101 #define EXACT_POWER_OF_2_OR_ZERO_P(x) \
102 (((x) & ((x) - HOST_WIDE_INT_1U)) == 0)
104 struct init_expmed_rtl
125 rtx pow2
[MAX_BITS_PER_WORD
];
126 rtx cint
[MAX_BITS_PER_WORD
];
130 init_expmed_one_conv (struct init_expmed_rtl
*all
, scalar_int_mode to_mode
,
131 scalar_int_mode from_mode
, bool speed
)
133 int to_size
, from_size
;
136 to_size
= GET_MODE_PRECISION (to_mode
);
137 from_size
= GET_MODE_PRECISION (from_mode
);
139 /* Most partial integers have a precision less than the "full"
140 integer it requires for storage. In case one doesn't, for
141 comparison purposes here, reduce the bit size by one in that
143 if (GET_MODE_CLASS (to_mode
) == MODE_PARTIAL_INT
144 && pow2p_hwi (to_size
))
146 if (GET_MODE_CLASS (from_mode
) == MODE_PARTIAL_INT
147 && pow2p_hwi (from_size
))
150 /* Assume cost of zero-extend and sign-extend is the same. */
151 which
= (to_size
< from_size
? all
->trunc
: all
->zext
);
153 PUT_MODE (all
->reg
, from_mode
);
154 set_convert_cost (to_mode
, from_mode
, speed
,
155 set_src_cost (which
, to_mode
, speed
));
159 init_expmed_one_mode (struct init_expmed_rtl
*all
,
160 machine_mode mode
, int speed
)
162 int m
, n
, mode_bitsize
;
163 machine_mode mode_from
;
165 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
167 PUT_MODE (all
->reg
, mode
);
168 PUT_MODE (all
->plus
, mode
);
169 PUT_MODE (all
->neg
, mode
);
170 PUT_MODE (all
->mult
, mode
);
171 PUT_MODE (all
->sdiv
, mode
);
172 PUT_MODE (all
->udiv
, mode
);
173 PUT_MODE (all
->sdiv_32
, mode
);
174 PUT_MODE (all
->smod_32
, mode
);
175 PUT_MODE (all
->wide_trunc
, mode
);
176 PUT_MODE (all
->shift
, mode
);
177 PUT_MODE (all
->shift_mult
, mode
);
178 PUT_MODE (all
->shift_add
, mode
);
179 PUT_MODE (all
->shift_sub0
, mode
);
180 PUT_MODE (all
->shift_sub1
, mode
);
181 PUT_MODE (all
->zext
, mode
);
182 PUT_MODE (all
->trunc
, mode
);
184 set_add_cost (speed
, mode
, set_src_cost (all
->plus
, mode
, speed
));
185 set_neg_cost (speed
, mode
, set_src_cost (all
->neg
, mode
, speed
));
186 set_mul_cost (speed
, mode
, set_src_cost (all
->mult
, mode
, speed
));
187 set_sdiv_cost (speed
, mode
, set_src_cost (all
->sdiv
, mode
, speed
));
188 set_udiv_cost (speed
, mode
, set_src_cost (all
->udiv
, mode
, speed
));
190 set_sdiv_pow2_cheap (speed
, mode
, (set_src_cost (all
->sdiv_32
, mode
, speed
)
191 <= 2 * add_cost (speed
, mode
)));
192 set_smod_pow2_cheap (speed
, mode
, (set_src_cost (all
->smod_32
, mode
, speed
)
193 <= 4 * add_cost (speed
, mode
)));
195 set_shift_cost (speed
, mode
, 0, 0);
197 int cost
= add_cost (speed
, mode
);
198 set_shiftadd_cost (speed
, mode
, 0, cost
);
199 set_shiftsub0_cost (speed
, mode
, 0, cost
);
200 set_shiftsub1_cost (speed
, mode
, 0, cost
);
203 n
= MIN (MAX_BITS_PER_WORD
, mode_bitsize
);
204 for (m
= 1; m
< n
; m
++)
206 XEXP (all
->shift
, 1) = all
->cint
[m
];
207 XEXP (all
->shift_mult
, 1) = all
->pow2
[m
];
209 set_shift_cost (speed
, mode
, m
, set_src_cost (all
->shift
, mode
, speed
));
210 set_shiftadd_cost (speed
, mode
, m
, set_src_cost (all
->shift_add
, mode
,
212 set_shiftsub0_cost (speed
, mode
, m
, set_src_cost (all
->shift_sub0
, mode
,
214 set_shiftsub1_cost (speed
, mode
, m
, set_src_cost (all
->shift_sub1
, mode
,
218 scalar_int_mode int_mode_to
;
219 if (is_a
<scalar_int_mode
> (mode
, &int_mode_to
))
221 for (mode_from
= MIN_MODE_INT
; mode_from
<= MAX_MODE_INT
;
222 mode_from
= (machine_mode
)(mode_from
+ 1))
223 init_expmed_one_conv (all
, int_mode_to
,
224 as_a
<scalar_int_mode
> (mode_from
), speed
);
226 scalar_int_mode wider_mode
;
227 if (GET_MODE_CLASS (int_mode_to
) == MODE_INT
228 && GET_MODE_WIDER_MODE (int_mode_to
).exists (&wider_mode
))
230 PUT_MODE (all
->zext
, wider_mode
);
231 PUT_MODE (all
->wide_mult
, wider_mode
);
232 PUT_MODE (all
->wide_lshr
, wider_mode
);
233 XEXP (all
->wide_lshr
, 1)
234 = gen_int_shift_amount (wider_mode
, mode_bitsize
);
236 set_mul_widen_cost (speed
, wider_mode
,
237 set_src_cost (all
->wide_mult
, wider_mode
, speed
));
238 set_mul_highpart_cost (speed
, int_mode_to
,
239 set_src_cost (all
->wide_trunc
,
240 int_mode_to
, speed
));
248 struct init_expmed_rtl all
;
249 machine_mode mode
= QImode
;
252 memset (&all
, 0, sizeof all
);
253 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
255 all
.pow2
[m
] = GEN_INT (HOST_WIDE_INT_1
<< m
);
256 all
.cint
[m
] = GEN_INT (m
);
259 /* Avoid using hard regs in ways which may be unsupported. */
260 all
.reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
261 all
.plus
= gen_rtx_PLUS (mode
, all
.reg
, all
.reg
);
262 all
.neg
= gen_rtx_NEG (mode
, all
.reg
);
263 all
.mult
= gen_rtx_MULT (mode
, all
.reg
, all
.reg
);
264 all
.sdiv
= gen_rtx_DIV (mode
, all
.reg
, all
.reg
);
265 all
.udiv
= gen_rtx_UDIV (mode
, all
.reg
, all
.reg
);
266 all
.sdiv_32
= gen_rtx_DIV (mode
, all
.reg
, all
.pow2
[5]);
267 all
.smod_32
= gen_rtx_MOD (mode
, all
.reg
, all
.pow2
[5]);
268 all
.zext
= gen_rtx_ZERO_EXTEND (mode
, all
.reg
);
269 all
.wide_mult
= gen_rtx_MULT (mode
, all
.zext
, all
.zext
);
270 all
.wide_lshr
= gen_rtx_LSHIFTRT (mode
, all
.wide_mult
, all
.reg
);
271 all
.wide_trunc
= gen_rtx_TRUNCATE (mode
, all
.wide_lshr
);
272 all
.shift
= gen_rtx_ASHIFT (mode
, all
.reg
, all
.reg
);
273 all
.shift_mult
= gen_rtx_MULT (mode
, all
.reg
, all
.reg
);
274 all
.shift_add
= gen_rtx_PLUS (mode
, all
.shift_mult
, all
.reg
);
275 all
.shift_sub0
= gen_rtx_MINUS (mode
, all
.shift_mult
, all
.reg
);
276 all
.shift_sub1
= gen_rtx_MINUS (mode
, all
.reg
, all
.shift_mult
);
277 all
.trunc
= gen_rtx_TRUNCATE (mode
, all
.reg
);
279 for (speed
= 0; speed
< 2; speed
++)
281 crtl
->maybe_hot_insn_p
= speed
;
282 set_zero_cost (speed
, set_src_cost (const0_rtx
, mode
, speed
));
284 for (mode
= MIN_MODE_INT
; mode
<= MAX_MODE_INT
;
285 mode
= (machine_mode
)(mode
+ 1))
286 init_expmed_one_mode (&all
, mode
, speed
);
288 if (MIN_MODE_PARTIAL_INT
!= VOIDmode
)
289 for (mode
= MIN_MODE_PARTIAL_INT
; mode
<= MAX_MODE_PARTIAL_INT
;
290 mode
= (machine_mode
)(mode
+ 1))
291 init_expmed_one_mode (&all
, mode
, speed
);
293 if (MIN_MODE_VECTOR_INT
!= VOIDmode
)
294 for (mode
= MIN_MODE_VECTOR_INT
; mode
<= MAX_MODE_VECTOR_INT
;
295 mode
= (machine_mode
)(mode
+ 1))
296 init_expmed_one_mode (&all
, mode
, speed
);
299 if (alg_hash_used_p ())
301 struct alg_hash_entry
*p
= alg_hash_entry_ptr (0);
302 memset (p
, 0, sizeof (*p
) * NUM_ALG_HASH_ENTRIES
);
305 set_alg_hash_used_p (true);
306 default_rtl_profile ();
308 ggc_free (all
.trunc
);
309 ggc_free (all
.shift_sub1
);
310 ggc_free (all
.shift_sub0
);
311 ggc_free (all
.shift_add
);
312 ggc_free (all
.shift_mult
);
313 ggc_free (all
.shift
);
314 ggc_free (all
.wide_trunc
);
315 ggc_free (all
.wide_lshr
);
316 ggc_free (all
.wide_mult
);
318 ggc_free (all
.smod_32
);
319 ggc_free (all
.sdiv_32
);
328 /* Return an rtx representing minus the value of X.
329 MODE is the intended mode of the result,
330 useful if X is a CONST_INT. */
333 negate_rtx (machine_mode mode
, rtx x
)
335 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
338 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
343 /* Whether reverse storage order is supported on the target. */
344 static int reverse_storage_order_supported
= -1;
346 /* Check whether reverse storage order is supported on the target. */
349 check_reverse_storage_order_support (void)
351 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
353 reverse_storage_order_supported
= 0;
354 sorry ("reverse scalar storage order");
357 reverse_storage_order_supported
= 1;
360 /* Whether reverse FP storage order is supported on the target. */
361 static int reverse_float_storage_order_supported
= -1;
363 /* Check whether reverse FP storage order is supported on the target. */
366 check_reverse_float_storage_order_support (void)
368 if (FLOAT_WORDS_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
370 reverse_float_storage_order_supported
= 0;
371 sorry ("reverse floating-point scalar storage order");
374 reverse_float_storage_order_supported
= 1;
377 /* Return an rtx representing value of X with reverse storage order.
378 MODE is the intended mode of the result,
379 useful if X is a CONST_INT. */
382 flip_storage_order (machine_mode mode
, rtx x
)
384 scalar_int_mode int_mode
;
390 if (COMPLEX_MODE_P (mode
))
392 rtx real
= read_complex_part (x
, false);
393 rtx imag
= read_complex_part (x
, true);
395 real
= flip_storage_order (GET_MODE_INNER (mode
), real
);
396 imag
= flip_storage_order (GET_MODE_INNER (mode
), imag
);
398 return gen_rtx_CONCAT (mode
, real
, imag
);
401 if (__builtin_expect (reverse_storage_order_supported
< 0, 0))
402 check_reverse_storage_order_support ();
404 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
406 if (FLOAT_MODE_P (mode
)
407 && __builtin_expect (reverse_float_storage_order_supported
< 0, 0))
408 check_reverse_float_storage_order_support ();
410 if (!int_mode_for_size (GET_MODE_PRECISION (mode
), 0).exists (&int_mode
))
412 sorry ("reverse storage order for %smode", GET_MODE_NAME (mode
));
415 x
= gen_lowpart (int_mode
, x
);
418 result
= simplify_unary_operation (BSWAP
, int_mode
, x
, int_mode
);
420 result
= expand_unop (int_mode
, bswap_optab
, x
, NULL_RTX
, 1);
422 if (int_mode
!= mode
)
423 result
= gen_lowpart (mode
, result
);
428 /* If MODE is set, adjust bitfield memory MEM so that it points to the
429 first unit of mode MODE that contains a bitfield of size BITSIZE at
430 bit position BITNUM. If MODE is not set, return a BLKmode reference
431 to every byte in the bitfield. Set *NEW_BITNUM to the bit position
432 of the field within the new memory. */
435 narrow_bit_field_mem (rtx mem
, opt_scalar_int_mode mode
,
436 unsigned HOST_WIDE_INT bitsize
,
437 unsigned HOST_WIDE_INT bitnum
,
438 unsigned HOST_WIDE_INT
*new_bitnum
)
440 scalar_int_mode imode
;
441 if (mode
.exists (&imode
))
443 unsigned int unit
= GET_MODE_BITSIZE (imode
);
444 *new_bitnum
= bitnum
% unit
;
445 HOST_WIDE_INT offset
= (bitnum
- *new_bitnum
) / BITS_PER_UNIT
;
446 return adjust_bitfield_address (mem
, imode
, offset
);
450 *new_bitnum
= bitnum
% BITS_PER_UNIT
;
451 HOST_WIDE_INT offset
= bitnum
/ BITS_PER_UNIT
;
452 HOST_WIDE_INT size
= ((*new_bitnum
+ bitsize
+ BITS_PER_UNIT
- 1)
454 return adjust_bitfield_address_size (mem
, BLKmode
, offset
, size
);
458 /* The caller wants to perform insertion or extraction PATTERN on a
459 bitfield of size BITSIZE at BITNUM bits into memory operand OP0.
460 BITREGION_START and BITREGION_END are as for store_bit_field
461 and FIELDMODE is the natural mode of the field.
463 Search for a mode that is compatible with the memory access
464 restrictions and (where applicable) with a register insertion or
465 extraction. Return the new memory on success, storing the adjusted
466 bit position in *NEW_BITNUM. Return null otherwise. */
469 adjust_bit_field_mem_for_reg (enum extraction_pattern pattern
,
470 rtx op0
, HOST_WIDE_INT bitsize
,
471 HOST_WIDE_INT bitnum
,
472 poly_uint64 bitregion_start
,
473 poly_uint64 bitregion_end
,
474 machine_mode fieldmode
,
475 unsigned HOST_WIDE_INT
*new_bitnum
)
477 bit_field_mode_iterator
iter (bitsize
, bitnum
, bitregion_start
,
478 bitregion_end
, MEM_ALIGN (op0
),
479 MEM_VOLATILE_P (op0
));
480 scalar_int_mode best_mode
;
481 if (iter
.next_mode (&best_mode
))
483 /* We can use a memory in BEST_MODE. See whether this is true for
484 any wider modes. All other things being equal, we prefer to
485 use the widest mode possible because it tends to expose more
486 CSE opportunities. */
487 if (!iter
.prefer_smaller_modes ())
489 /* Limit the search to the mode required by the corresponding
490 register insertion or extraction instruction, if any. */
491 scalar_int_mode limit_mode
= word_mode
;
492 extraction_insn insn
;
493 if (get_best_reg_extraction_insn (&insn
, pattern
,
494 GET_MODE_BITSIZE (best_mode
),
496 limit_mode
= insn
.field_mode
;
498 scalar_int_mode wider_mode
;
499 while (iter
.next_mode (&wider_mode
)
500 && GET_MODE_SIZE (wider_mode
) <= GET_MODE_SIZE (limit_mode
))
501 best_mode
= wider_mode
;
503 return narrow_bit_field_mem (op0
, best_mode
, bitsize
, bitnum
,
509 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
510 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
511 offset is then BITNUM / BITS_PER_UNIT. */
514 lowpart_bit_field_p (poly_uint64 bitnum
, poly_uint64 bitsize
,
515 machine_mode struct_mode
)
517 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (struct_mode
);
518 if (BYTES_BIG_ENDIAN
)
519 return (multiple_p (bitnum
, BITS_PER_UNIT
)
520 && (known_eq (bitnum
+ bitsize
, GET_MODE_BITSIZE (struct_mode
))
521 || multiple_p (bitnum
+ bitsize
,
522 regsize
* BITS_PER_UNIT
)));
524 return multiple_p (bitnum
, regsize
* BITS_PER_UNIT
);
527 /* Return true if -fstrict-volatile-bitfields applies to an access of OP0
528 containing BITSIZE bits starting at BITNUM, with field mode FIELDMODE.
529 Return false if the access would touch memory outside the range
530 BITREGION_START to BITREGION_END for conformance to the C++ memory
534 strict_volatile_bitfield_p (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
535 unsigned HOST_WIDE_INT bitnum
,
536 scalar_int_mode fieldmode
,
537 poly_uint64 bitregion_start
,
538 poly_uint64 bitregion_end
)
540 unsigned HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (fieldmode
);
542 /* -fstrict-volatile-bitfields must be enabled and we must have a
545 || !MEM_VOLATILE_P (op0
)
546 || flag_strict_volatile_bitfields
<= 0)
549 /* The bit size must not be larger than the field mode, and
550 the field mode must not be larger than a word. */
551 if (bitsize
> modesize
|| modesize
> BITS_PER_WORD
)
554 /* Check for cases of unaligned fields that must be split. */
555 if (bitnum
% modesize
+ bitsize
> modesize
)
558 /* The memory must be sufficiently aligned for a MODESIZE access.
559 This condition guarantees, that the memory access will not
560 touch anything after the end of the structure. */
561 if (MEM_ALIGN (op0
) < modesize
)
564 /* Check for cases where the C++ memory model applies. */
565 if (maybe_ne (bitregion_end
, 0U)
566 && (maybe_lt (bitnum
- bitnum
% modesize
, bitregion_start
)
567 || maybe_gt (bitnum
- bitnum
% modesize
+ modesize
- 1,
574 /* Return true if OP is a memory and if a bitfield of size BITSIZE at
575 bit number BITNUM can be treated as a simple value of mode MODE.
576 Store the byte offset in *BYTENUM if so. */
579 simple_mem_bitfield_p (rtx op0
, poly_uint64 bitsize
, poly_uint64 bitnum
,
580 machine_mode mode
, poly_uint64
*bytenum
)
583 && multiple_p (bitnum
, BITS_PER_UNIT
, bytenum
)
584 && known_eq (bitsize
, GET_MODE_BITSIZE (mode
))
585 && (!targetm
.slow_unaligned_access (mode
, MEM_ALIGN (op0
))
586 || (multiple_p (bitnum
, GET_MODE_ALIGNMENT (mode
))
587 && MEM_ALIGN (op0
) >= GET_MODE_ALIGNMENT (mode
))));
590 /* Try to use instruction INSV to store VALUE into a field of OP0.
591 If OP0_MODE is defined, it is the mode of OP0, otherwise OP0 is a
592 BLKmode MEM. VALUE_MODE is the mode of VALUE. BITSIZE and BITNUM
593 are as for store_bit_field. */
596 store_bit_field_using_insv (const extraction_insn
*insv
, rtx op0
,
597 opt_scalar_int_mode op0_mode
,
598 unsigned HOST_WIDE_INT bitsize
,
599 unsigned HOST_WIDE_INT bitnum
,
600 rtx value
, scalar_int_mode value_mode
)
602 struct expand_operand ops
[4];
605 rtx_insn
*last
= get_last_insn ();
606 bool copy_back
= false;
608 scalar_int_mode op_mode
= insv
->field_mode
;
609 unsigned int unit
= GET_MODE_BITSIZE (op_mode
);
610 if (bitsize
== 0 || bitsize
> unit
)
614 /* Get a reference to the first byte of the field. */
615 xop0
= narrow_bit_field_mem (xop0
, insv
->struct_mode
, bitsize
, bitnum
,
619 /* Convert from counting within OP0 to counting in OP_MODE. */
620 if (BYTES_BIG_ENDIAN
)
621 bitnum
+= unit
- GET_MODE_BITSIZE (op0_mode
.require ());
623 /* If xop0 is a register, we need it in OP_MODE
624 to make it acceptable to the format of insv. */
625 if (GET_CODE (xop0
) == SUBREG
)
626 /* We can't just change the mode, because this might clobber op0,
627 and we will need the original value of op0 if insv fails. */
628 xop0
= gen_rtx_SUBREG (op_mode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
629 if (REG_P (xop0
) && GET_MODE (xop0
) != op_mode
)
630 xop0
= gen_lowpart_SUBREG (op_mode
, xop0
);
633 /* If the destination is a paradoxical subreg such that we need a
634 truncate to the inner mode, perform the insertion on a temporary and
635 truncate the result to the original destination. Note that we can't
636 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
637 X) 0)) is (reg:N X). */
638 if (GET_CODE (xop0
) == SUBREG
639 && REG_P (SUBREG_REG (xop0
))
640 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0
)),
643 rtx tem
= gen_reg_rtx (op_mode
);
644 emit_move_insn (tem
, xop0
);
649 /* There are similar overflow check at the start of store_bit_field_1,
650 but that only check the situation where the field lies completely
651 outside the register, while there do have situation where the field
652 lies partialy in the register, we need to adjust bitsize for this
653 partial overflow situation. Without this fix, pr48335-2.c on big-endian
654 will broken on those arch support bit insert instruction, like arm, aarch64
656 if (bitsize
+ bitnum
> unit
&& bitnum
< unit
)
658 warning (OPT_Wextra
, "write of %wu-bit data outside the bound of "
659 "destination object, data truncated into %wu-bit",
660 bitsize
, unit
- bitnum
);
661 bitsize
= unit
- bitnum
;
664 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
665 "backwards" from the size of the unit we are inserting into.
666 Otherwise, we count bits from the most significant on a
667 BYTES/BITS_BIG_ENDIAN machine. */
669 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
670 bitnum
= unit
- bitsize
- bitnum
;
672 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
674 if (value_mode
!= op_mode
)
676 if (GET_MODE_BITSIZE (value_mode
) >= bitsize
)
679 /* Optimization: Don't bother really extending VALUE
680 if it has all the bits we will actually use. However,
681 if we must narrow it, be sure we do it correctly. */
683 if (GET_MODE_SIZE (value_mode
) < GET_MODE_SIZE (op_mode
))
685 tmp
= simplify_subreg (op_mode
, value1
, value_mode
, 0);
687 tmp
= simplify_gen_subreg (op_mode
,
688 force_reg (value_mode
, value1
),
693 tmp
= gen_lowpart_if_possible (op_mode
, value1
);
695 tmp
= gen_lowpart (op_mode
, force_reg (value_mode
, value1
));
699 else if (CONST_INT_P (value
))
700 value1
= gen_int_mode (INTVAL (value
), op_mode
);
702 /* Parse phase is supposed to make VALUE's data type
703 match that of the component reference, which is a type
704 at least as wide as the field; so VALUE should have
705 a mode that corresponds to that type. */
706 gcc_assert (CONSTANT_P (value
));
709 create_fixed_operand (&ops
[0], xop0
);
710 create_integer_operand (&ops
[1], bitsize
);
711 create_integer_operand (&ops
[2], bitnum
);
712 create_input_operand (&ops
[3], value1
, op_mode
);
713 if (maybe_expand_insn (insv
->icode
, 4, ops
))
716 convert_move (op0
, xop0
, true);
719 delete_insns_since (last
);
723 /* A subroutine of store_bit_field, with the same arguments. Return true
724 if the operation could be implemented.
726 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
727 no other way of implementing the operation. If FALLBACK_P is false,
728 return false instead. */
731 store_bit_field_1 (rtx str_rtx
, poly_uint64 bitsize
, poly_uint64 bitnum
,
732 poly_uint64 bitregion_start
, poly_uint64 bitregion_end
,
733 machine_mode fieldmode
,
734 rtx value
, bool reverse
, bool fallback_p
)
738 while (GET_CODE (op0
) == SUBREG
)
740 bitnum
+= subreg_memory_offset (op0
) * BITS_PER_UNIT
;
741 op0
= SUBREG_REG (op0
);
744 /* No action is needed if the target is a register and if the field
745 lies completely outside that register. This can occur if the source
746 code contains an out-of-bounds access to a small array. */
747 if (REG_P (op0
) && known_ge (bitnum
, GET_MODE_BITSIZE (GET_MODE (op0
))))
750 /* Use vec_set patterns for inserting parts of vectors whenever
752 machine_mode outermode
= GET_MODE (op0
);
753 scalar_mode innermode
= GET_MODE_INNER (outermode
);
755 if (VECTOR_MODE_P (outermode
)
757 && optab_handler (vec_set_optab
, outermode
) != CODE_FOR_nothing
758 && fieldmode
== innermode
759 && known_eq (bitsize
, GET_MODE_BITSIZE (innermode
))
760 && multiple_p (bitnum
, GET_MODE_BITSIZE (innermode
), &pos
))
762 struct expand_operand ops
[3];
763 enum insn_code icode
= optab_handler (vec_set_optab
, outermode
);
765 create_fixed_operand (&ops
[0], op0
);
766 create_input_operand (&ops
[1], value
, innermode
);
767 create_integer_operand (&ops
[2], pos
);
768 if (maybe_expand_insn (icode
, 3, ops
))
772 /* If the target is a register, overwriting the entire object, or storing
773 a full-word or multi-word field can be done with just a SUBREG. */
775 && known_eq (bitsize
, GET_MODE_BITSIZE (fieldmode
)))
777 /* Use the subreg machinery either to narrow OP0 to the required
778 words or to cope with mode punning between equal-sized modes.
779 In the latter case, use subreg on the rhs side, not lhs. */
781 HOST_WIDE_INT regnum
;
782 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (GET_MODE (op0
));
783 if (known_eq (bitnum
, 0U)
784 && known_eq (bitsize
, GET_MODE_BITSIZE (GET_MODE (op0
))))
786 sub
= simplify_gen_subreg (GET_MODE (op0
), value
, fieldmode
, 0);
790 sub
= flip_storage_order (GET_MODE (op0
), sub
);
791 emit_move_insn (op0
, sub
);
795 else if (constant_multiple_p (bitnum
, regsize
* BITS_PER_UNIT
, ®num
)
796 && multiple_p (bitsize
, regsize
* BITS_PER_UNIT
))
798 sub
= simplify_gen_subreg (fieldmode
, op0
, GET_MODE (op0
),
803 value
= flip_storage_order (fieldmode
, value
);
804 emit_move_insn (sub
, value
);
810 /* If the target is memory, storing any naturally aligned field can be
811 done with a simple store. For targets that support fast unaligned
812 memory, any naturally sized, unit aligned field can be done directly. */
814 if (simple_mem_bitfield_p (op0
, bitsize
, bitnum
, fieldmode
, &bytenum
))
816 op0
= adjust_bitfield_address (op0
, fieldmode
, bytenum
);
818 value
= flip_storage_order (fieldmode
, value
);
819 emit_move_insn (op0
, value
);
823 /* It's possible we'll need to handle other cases here for
824 polynomial bitnum and bitsize. */
826 /* From here on we need to be looking at a fixed-size insertion. */
827 unsigned HOST_WIDE_INT ibitsize
= bitsize
.to_constant ();
828 unsigned HOST_WIDE_INT ibitnum
= bitnum
.to_constant ();
830 /* Make sure we are playing with integral modes. Pun with subregs
831 if we aren't. This must come after the entire register case above,
832 since that case is valid for any mode. The following cases are only
833 valid for integral modes. */
834 opt_scalar_int_mode op0_mode
= int_mode_for_mode (GET_MODE (op0
));
835 scalar_int_mode imode
;
836 if (!op0_mode
.exists (&imode
) || imode
!= GET_MODE (op0
))
839 op0
= adjust_bitfield_address_size (op0
, op0_mode
.else_blk (),
842 op0
= gen_lowpart (op0_mode
.require (), op0
);
845 return store_integral_bit_field (op0
, op0_mode
, ibitsize
, ibitnum
,
846 bitregion_start
, bitregion_end
,
847 fieldmode
, value
, reverse
, fallback_p
);
850 /* Subroutine of store_bit_field_1, with the same arguments, except
851 that BITSIZE and BITNUM are constant. Handle cases specific to
852 integral modes. If OP0_MODE is defined, it is the mode of OP0,
853 otherwise OP0 is a BLKmode MEM. */
856 store_integral_bit_field (rtx op0
, opt_scalar_int_mode op0_mode
,
857 unsigned HOST_WIDE_INT bitsize
,
858 unsigned HOST_WIDE_INT bitnum
,
859 poly_uint64 bitregion_start
,
860 poly_uint64 bitregion_end
,
861 machine_mode fieldmode
,
862 rtx value
, bool reverse
, bool fallback_p
)
864 /* Storing an lsb-aligned field in a register
865 can be done with a movstrict instruction. */
869 && lowpart_bit_field_p (bitnum
, bitsize
, op0_mode
.require ())
870 && known_eq (bitsize
, GET_MODE_BITSIZE (fieldmode
))
871 && optab_handler (movstrict_optab
, fieldmode
) != CODE_FOR_nothing
)
873 struct expand_operand ops
[2];
874 enum insn_code icode
= optab_handler (movstrict_optab
, fieldmode
);
876 unsigned HOST_WIDE_INT subreg_off
;
878 if (GET_CODE (arg0
) == SUBREG
)
880 /* Else we've got some float mode source being extracted into
881 a different float mode destination -- this combination of
882 subregs results in Severe Tire Damage. */
883 gcc_assert (GET_MODE (SUBREG_REG (arg0
)) == fieldmode
884 || GET_MODE_CLASS (fieldmode
) == MODE_INT
885 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
);
886 arg0
= SUBREG_REG (arg0
);
889 subreg_off
= bitnum
/ BITS_PER_UNIT
;
890 if (validate_subreg (fieldmode
, GET_MODE (arg0
), arg0
, subreg_off
))
892 arg0
= gen_rtx_SUBREG (fieldmode
, arg0
, subreg_off
);
894 create_fixed_operand (&ops
[0], arg0
);
895 /* Shrink the source operand to FIELDMODE. */
896 create_convert_operand_to (&ops
[1], value
, fieldmode
, false);
897 if (maybe_expand_insn (icode
, 2, ops
))
902 /* Handle fields bigger than a word. */
904 if (bitsize
> BITS_PER_WORD
)
906 /* Here we transfer the words of the field
907 in the order least significant first.
908 This is because the most significant word is the one which may
910 However, only do that if the value is not BLKmode. */
912 const bool backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
913 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
917 /* This is the mode we must force value to, so that there will be enough
918 subwords to extract. Note that fieldmode will often (always?) be
919 VOIDmode, because that is what store_field uses to indicate that this
920 is a bit field, but passing VOIDmode to operand_subword_force
923 The mode must be fixed-size, since insertions into variable-sized
924 objects are meant to be handled before calling this function. */
925 fixed_size_mode value_mode
= as_a
<fixed_size_mode
> (GET_MODE (value
));
926 if (value_mode
== VOIDmode
)
927 value_mode
= smallest_int_mode_for_size (nwords
* BITS_PER_WORD
);
929 last
= get_last_insn ();
930 for (i
= 0; i
< nwords
; i
++)
932 /* If I is 0, use the low-order word in both field and target;
933 if I is 1, use the next to lowest word; and so on. */
934 unsigned int wordnum
= (backwards
935 ? GET_MODE_SIZE (value_mode
) / UNITS_PER_WORD
938 unsigned int bit_offset
= (backwards
^ reverse
939 ? MAX ((int) bitsize
- ((int) i
+ 1)
942 : (int) i
* BITS_PER_WORD
);
943 rtx value_word
= operand_subword_force (value
, wordnum
, value_mode
);
944 unsigned HOST_WIDE_INT new_bitsize
=
945 MIN (BITS_PER_WORD
, bitsize
- i
* BITS_PER_WORD
);
947 /* If the remaining chunk doesn't have full wordsize we have
948 to make sure that for big-endian machines the higher order
950 if (new_bitsize
< BITS_PER_WORD
&& BYTES_BIG_ENDIAN
&& !backwards
)
952 int shift
= BITS_PER_WORD
- new_bitsize
;
953 rtx shift_rtx
= gen_int_shift_amount (word_mode
, shift
);
954 value_word
= simplify_expand_binop (word_mode
, lshr_optab
,
955 value_word
, shift_rtx
,
960 if (!store_bit_field_1 (op0
, new_bitsize
,
962 bitregion_start
, bitregion_end
,
964 value_word
, reverse
, fallback_p
))
966 delete_insns_since (last
);
973 /* If VALUE has a floating-point or complex mode, access it as an
974 integer of the corresponding size. This can occur on a machine
975 with 64 bit registers that uses SFmode for float. It can also
976 occur for unaligned float or complex fields. */
977 rtx orig_value
= value
;
978 scalar_int_mode value_mode
;
979 if (GET_MODE (value
) == VOIDmode
)
980 /* By this point we've dealt with values that are bigger than a word,
981 so word_mode is a conservatively correct choice. */
982 value_mode
= word_mode
;
983 else if (!is_a
<scalar_int_mode
> (GET_MODE (value
), &value_mode
))
985 value_mode
= int_mode_for_mode (GET_MODE (value
)).require ();
986 value
= gen_reg_rtx (value_mode
);
987 emit_move_insn (gen_lowpart (GET_MODE (orig_value
), value
), orig_value
);
990 /* If OP0 is a multi-word register, narrow it to the affected word.
991 If the region spans two words, defer to store_split_bit_field.
992 Don't do this if op0 is a single hard register wider than word
993 such as a float or vector register. */
995 && GET_MODE_SIZE (op0_mode
.require ()) > UNITS_PER_WORD
997 || !HARD_REGISTER_P (op0
)
998 || hard_regno_nregs (REGNO (op0
), op0_mode
.require ()) != 1))
1000 if (bitnum
% BITS_PER_WORD
+ bitsize
> BITS_PER_WORD
)
1005 store_split_bit_field (op0
, op0_mode
, bitsize
, bitnum
,
1006 bitregion_start
, bitregion_end
,
1007 value
, value_mode
, reverse
);
1010 op0
= simplify_gen_subreg (word_mode
, op0
, op0_mode
.require (),
1011 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
1013 op0_mode
= word_mode
;
1014 bitnum
%= BITS_PER_WORD
;
1017 /* From here on we can assume that the field to be stored in fits
1018 within a word. If the destination is a register, it too fits
1021 extraction_insn insv
;
1024 && get_best_reg_extraction_insn (&insv
, EP_insv
,
1025 GET_MODE_BITSIZE (op0_mode
.require ()),
1027 && store_bit_field_using_insv (&insv
, op0
, op0_mode
,
1028 bitsize
, bitnum
, value
, value_mode
))
1031 /* If OP0 is a memory, try copying it to a register and seeing if a
1032 cheap register alternative is available. */
1033 if (MEM_P (op0
) && !reverse
)
1035 if (get_best_mem_extraction_insn (&insv
, EP_insv
, bitsize
, bitnum
,
1037 && store_bit_field_using_insv (&insv
, op0
, op0_mode
,
1038 bitsize
, bitnum
, value
, value_mode
))
1041 rtx_insn
*last
= get_last_insn ();
1043 /* Try loading part of OP0 into a register, inserting the bitfield
1044 into that, and then copying the result back to OP0. */
1045 unsigned HOST_WIDE_INT bitpos
;
1046 rtx xop0
= adjust_bit_field_mem_for_reg (EP_insv
, op0
, bitsize
, bitnum
,
1047 bitregion_start
, bitregion_end
,
1048 fieldmode
, &bitpos
);
1051 rtx tempreg
= copy_to_reg (xop0
);
1052 if (store_bit_field_1 (tempreg
, bitsize
, bitpos
,
1053 bitregion_start
, bitregion_end
,
1054 fieldmode
, orig_value
, reverse
, false))
1056 emit_move_insn (xop0
, tempreg
);
1059 delete_insns_since (last
);
1066 store_fixed_bit_field (op0
, op0_mode
, bitsize
, bitnum
, bitregion_start
,
1067 bitregion_end
, value
, value_mode
, reverse
);
1071 /* Generate code to store value from rtx VALUE
1072 into a bit-field within structure STR_RTX
1073 containing BITSIZE bits starting at bit BITNUM.
1075 BITREGION_START is bitpos of the first bitfield in this region.
1076 BITREGION_END is the bitpos of the ending bitfield in this region.
1077 These two fields are 0, if the C++ memory model does not apply,
1078 or we are not interested in keeping track of bitfield regions.
1080 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
1082 If REVERSE is true, the store is to be done in reverse order. */
1085 store_bit_field (rtx str_rtx
, poly_uint64 bitsize
, poly_uint64 bitnum
,
1086 poly_uint64 bitregion_start
, poly_uint64 bitregion_end
,
1087 machine_mode fieldmode
,
1088 rtx value
, bool reverse
)
1090 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
1091 unsigned HOST_WIDE_INT ibitsize
= 0, ibitnum
= 0;
1092 scalar_int_mode int_mode
;
1093 if (bitsize
.is_constant (&ibitsize
)
1094 && bitnum
.is_constant (&ibitnum
)
1095 && is_a
<scalar_int_mode
> (fieldmode
, &int_mode
)
1096 && strict_volatile_bitfield_p (str_rtx
, ibitsize
, ibitnum
, int_mode
,
1097 bitregion_start
, bitregion_end
))
1099 /* Storing of a full word can be done with a simple store.
1100 We know here that the field can be accessed with one single
1101 instruction. For targets that support unaligned memory,
1102 an unaligned access may be necessary. */
1103 if (ibitsize
== GET_MODE_BITSIZE (int_mode
))
1105 str_rtx
= adjust_bitfield_address (str_rtx
, int_mode
,
1106 ibitnum
/ BITS_PER_UNIT
);
1108 value
= flip_storage_order (int_mode
, value
);
1109 gcc_assert (ibitnum
% BITS_PER_UNIT
== 0);
1110 emit_move_insn (str_rtx
, value
);
1116 str_rtx
= narrow_bit_field_mem (str_rtx
, int_mode
, ibitsize
,
1118 gcc_assert (ibitnum
+ ibitsize
<= GET_MODE_BITSIZE (int_mode
));
1119 temp
= copy_to_reg (str_rtx
);
1120 if (!store_bit_field_1 (temp
, ibitsize
, ibitnum
, 0, 0,
1121 int_mode
, value
, reverse
, true))
1124 emit_move_insn (str_rtx
, temp
);
1130 /* Under the C++0x memory model, we must not touch bits outside the
1131 bit region. Adjust the address to start at the beginning of the
1133 if (MEM_P (str_rtx
) && maybe_ne (bitregion_start
, 0U))
1135 scalar_int_mode best_mode
;
1136 machine_mode addr_mode
= VOIDmode
;
1138 poly_uint64 offset
= exact_div (bitregion_start
, BITS_PER_UNIT
);
1139 bitnum
-= bitregion_start
;
1140 poly_int64 size
= bits_to_bytes_round_up (bitnum
+ bitsize
);
1141 bitregion_end
-= bitregion_start
;
1142 bitregion_start
= 0;
1143 if (bitsize
.is_constant (&ibitsize
)
1144 && bitnum
.is_constant (&ibitnum
)
1145 && get_best_mode (ibitsize
, ibitnum
,
1146 bitregion_start
, bitregion_end
,
1147 MEM_ALIGN (str_rtx
), INT_MAX
,
1148 MEM_VOLATILE_P (str_rtx
), &best_mode
))
1149 addr_mode
= best_mode
;
1150 str_rtx
= adjust_bitfield_address_size (str_rtx
, addr_mode
,
1154 if (!store_bit_field_1 (str_rtx
, bitsize
, bitnum
,
1155 bitregion_start
, bitregion_end
,
1156 fieldmode
, value
, reverse
, true))
1160 /* Use shifts and boolean operations to store VALUE into a bit field of
1161 width BITSIZE in OP0, starting at bit BITNUM. If OP0_MODE is defined,
1162 it is the mode of OP0, otherwise OP0 is a BLKmode MEM. VALUE_MODE is
1165 If REVERSE is true, the store is to be done in reverse order. */
1168 store_fixed_bit_field (rtx op0
, opt_scalar_int_mode op0_mode
,
1169 unsigned HOST_WIDE_INT bitsize
,
1170 unsigned HOST_WIDE_INT bitnum
,
1171 poly_uint64 bitregion_start
, poly_uint64 bitregion_end
,
1172 rtx value
, scalar_int_mode value_mode
, bool reverse
)
1174 /* There is a case not handled here:
1175 a structure with a known alignment of just a halfword
1176 and a field split across two aligned halfwords within the structure.
1177 Or likewise a structure with a known alignment of just a byte
1178 and a field split across two bytes.
1179 Such cases are not supposed to be able to occur. */
1181 scalar_int_mode best_mode
;
1184 unsigned int max_bitsize
= BITS_PER_WORD
;
1185 scalar_int_mode imode
;
1186 if (op0_mode
.exists (&imode
) && GET_MODE_BITSIZE (imode
) < max_bitsize
)
1187 max_bitsize
= GET_MODE_BITSIZE (imode
);
1189 if (!get_best_mode (bitsize
, bitnum
, bitregion_start
, bitregion_end
,
1190 MEM_ALIGN (op0
), max_bitsize
, MEM_VOLATILE_P (op0
),
1193 /* The only way this should occur is if the field spans word
1195 store_split_bit_field (op0
, op0_mode
, bitsize
, bitnum
,
1196 bitregion_start
, bitregion_end
,
1197 value
, value_mode
, reverse
);
1201 op0
= narrow_bit_field_mem (op0
, best_mode
, bitsize
, bitnum
, &bitnum
);
1204 best_mode
= op0_mode
.require ();
1206 store_fixed_bit_field_1 (op0
, best_mode
, bitsize
, bitnum
,
1207 value
, value_mode
, reverse
);
1210 /* Helper function for store_fixed_bit_field, stores
1211 the bit field always using MODE, which is the mode of OP0. The other
1212 arguments are as for store_fixed_bit_field. */
1215 store_fixed_bit_field_1 (rtx op0
, scalar_int_mode mode
,
1216 unsigned HOST_WIDE_INT bitsize
,
1217 unsigned HOST_WIDE_INT bitnum
,
1218 rtx value
, scalar_int_mode value_mode
, bool reverse
)
1224 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1225 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
1227 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
1228 /* BITNUM is the distance between our msb
1229 and that of the containing datum.
1230 Convert it to the distance from the lsb. */
1231 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
1233 /* Now BITNUM is always the distance between our lsb
1236 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
1237 we must first convert its mode to MODE. */
1239 if (CONST_INT_P (value
))
1241 unsigned HOST_WIDE_INT v
= UINTVAL (value
);
1243 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1244 v
&= (HOST_WIDE_INT_1U
<< bitsize
) - 1;
1248 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
1249 && v
== (HOST_WIDE_INT_1U
<< bitsize
) - 1)
1250 || (bitsize
== HOST_BITS_PER_WIDE_INT
1251 && v
== HOST_WIDE_INT_M1U
))
1254 value
= lshift_value (mode
, v
, bitnum
);
1258 int must_and
= (GET_MODE_BITSIZE (value_mode
) != bitsize
1259 && bitnum
+ bitsize
!= GET_MODE_BITSIZE (mode
));
1261 if (value_mode
!= mode
)
1262 value
= convert_to_mode (mode
, value
, 1);
1265 value
= expand_binop (mode
, and_optab
, value
,
1266 mask_rtx (mode
, 0, bitsize
, 0),
1267 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1269 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
1270 bitnum
, NULL_RTX
, 1);
1274 value
= flip_storage_order (mode
, value
);
1276 /* Now clear the chosen bits in OP0,
1277 except that if VALUE is -1 we need not bother. */
1278 /* We keep the intermediates in registers to allow CSE to combine
1279 consecutive bitfield assignments. */
1281 temp
= force_reg (mode
, op0
);
1285 rtx mask
= mask_rtx (mode
, bitnum
, bitsize
, 1);
1287 mask
= flip_storage_order (mode
, mask
);
1288 temp
= expand_binop (mode
, and_optab
, temp
, mask
,
1289 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1290 temp
= force_reg (mode
, temp
);
1293 /* Now logical-or VALUE into OP0, unless it is zero. */
1297 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
1298 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1299 temp
= force_reg (mode
, temp
);
1304 op0
= copy_rtx (op0
);
1305 emit_move_insn (op0
, temp
);
1309 /* Store a bit field that is split across multiple accessible memory objects.
1311 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1312 BITSIZE is the field width; BITPOS the position of its first bit
1314 VALUE is the value to store, which has mode VALUE_MODE.
1315 If OP0_MODE is defined, it is the mode of OP0, otherwise OP0 is
1318 If REVERSE is true, the store is to be done in reverse order.
1320 This does not yet handle fields wider than BITS_PER_WORD. */
1323 store_split_bit_field (rtx op0
, opt_scalar_int_mode op0_mode
,
1324 unsigned HOST_WIDE_INT bitsize
,
1325 unsigned HOST_WIDE_INT bitpos
,
1326 poly_uint64 bitregion_start
, poly_uint64 bitregion_end
,
1327 rtx value
, scalar_int_mode value_mode
, bool reverse
)
1329 unsigned int unit
, total_bits
, bitsdone
= 0;
1331 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1333 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1334 unit
= BITS_PER_WORD
;
1336 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1338 /* If OP0 is a memory with a mode, then UNIT must not be larger than
1339 OP0's mode as well. Otherwise, store_fixed_bit_field will call us
1340 again, and we will mutually recurse forever. */
1341 if (MEM_P (op0
) && op0_mode
.exists ())
1342 unit
= MIN (unit
, GET_MODE_BITSIZE (op0_mode
.require ()));
1344 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1345 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1346 that VALUE might be a floating-point constant. */
1347 if (CONSTANT_P (value
) && !CONST_INT_P (value
))
1349 rtx word
= gen_lowpart_common (word_mode
, value
);
1351 if (word
&& (value
!= word
))
1354 value
= gen_lowpart_common (word_mode
, force_reg (value_mode
, value
));
1355 value_mode
= word_mode
;
1358 total_bits
= GET_MODE_BITSIZE (value_mode
);
1360 while (bitsdone
< bitsize
)
1362 unsigned HOST_WIDE_INT thissize
;
1363 unsigned HOST_WIDE_INT thispos
;
1364 unsigned HOST_WIDE_INT offset
;
1367 offset
= (bitpos
+ bitsdone
) / unit
;
1368 thispos
= (bitpos
+ bitsdone
) % unit
;
1370 /* When region of bytes we can touch is restricted, decrease
1371 UNIT close to the end of the region as needed. If op0 is a REG
1372 or SUBREG of REG, don't do this, as there can't be data races
1373 on a register and we can expand shorter code in some cases. */
1374 if (maybe_ne (bitregion_end
, 0U)
1375 && unit
> BITS_PER_UNIT
1376 && maybe_gt (bitpos
+ bitsdone
- thispos
+ unit
, bitregion_end
+ 1)
1378 && (GET_CODE (op0
) != SUBREG
|| !REG_P (SUBREG_REG (op0
))))
1384 /* THISSIZE must not overrun a word boundary. Otherwise,
1385 store_fixed_bit_field will call us again, and we will mutually
1387 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1388 thissize
= MIN (thissize
, unit
- thispos
);
1390 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
1392 /* Fetch successively less significant portions. */
1393 if (CONST_INT_P (value
))
1394 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1395 >> (bitsize
- bitsdone
- thissize
))
1396 & ((HOST_WIDE_INT_1
<< thissize
) - 1));
1397 /* Likewise, but the source is little-endian. */
1399 part
= extract_fixed_bit_field (word_mode
, value
, value_mode
,
1401 bitsize
- bitsdone
- thissize
,
1402 NULL_RTX
, 1, false);
1404 /* The args are chosen so that the last part includes the
1405 lsb. Give extract_bit_field the value it needs (with
1406 endianness compensation) to fetch the piece we want. */
1407 part
= extract_fixed_bit_field (word_mode
, value
, value_mode
,
1409 total_bits
- bitsize
+ bitsdone
,
1410 NULL_RTX
, 1, false);
1414 /* Fetch successively more significant portions. */
1415 if (CONST_INT_P (value
))
1416 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1418 & ((HOST_WIDE_INT_1
<< thissize
) - 1));
1419 /* Likewise, but the source is big-endian. */
1421 part
= extract_fixed_bit_field (word_mode
, value
, value_mode
,
1423 total_bits
- bitsdone
- thissize
,
1424 NULL_RTX
, 1, false);
1426 part
= extract_fixed_bit_field (word_mode
, value
, value_mode
,
1427 thissize
, bitsdone
, NULL_RTX
,
1431 /* If OP0 is a register, then handle OFFSET here. */
1432 rtx op0_piece
= op0
;
1433 opt_scalar_int_mode op0_piece_mode
= op0_mode
;
1434 if (SUBREG_P (op0
) || REG_P (op0
))
1436 scalar_int_mode imode
;
1437 if (op0_mode
.exists (&imode
)
1438 && GET_MODE_SIZE (imode
) < UNITS_PER_WORD
)
1441 op0_piece
= const0_rtx
;
1445 op0_piece
= operand_subword_force (op0
,
1446 offset
* unit
/ BITS_PER_WORD
,
1448 op0_piece_mode
= word_mode
;
1450 offset
&= BITS_PER_WORD
/ unit
- 1;
1453 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1454 it is just an out-of-bounds access. Ignore it. */
1455 if (op0_piece
!= const0_rtx
)
1456 store_fixed_bit_field (op0_piece
, op0_piece_mode
, thissize
,
1457 offset
* unit
+ thispos
, bitregion_start
,
1458 bitregion_end
, part
, word_mode
, reverse
);
1459 bitsdone
+= thissize
;
1463 /* A subroutine of extract_bit_field_1 that converts return value X
1464 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1465 to extract_bit_field. */
1468 convert_extracted_bit_field (rtx x
, machine_mode mode
,
1469 machine_mode tmode
, bool unsignedp
)
1471 if (GET_MODE (x
) == tmode
|| GET_MODE (x
) == mode
)
1474 /* If the x mode is not a scalar integral, first convert to the
1475 integer mode of that size and then access it as a floating-point
1476 value via a SUBREG. */
1477 if (!SCALAR_INT_MODE_P (tmode
))
1479 scalar_int_mode int_mode
= int_mode_for_mode (tmode
).require ();
1480 x
= convert_to_mode (int_mode
, x
, unsignedp
);
1481 x
= force_reg (int_mode
, x
);
1482 return gen_lowpart (tmode
, x
);
1485 return convert_to_mode (tmode
, x
, unsignedp
);
1488 /* Try to use an ext(z)v pattern to extract a field from OP0.
1489 Return the extracted value on success, otherwise return null.
1490 EXTV describes the extraction instruction to use. If OP0_MODE
1491 is defined, it is the mode of OP0, otherwise OP0 is a BLKmode MEM.
1492 The other arguments are as for extract_bit_field. */
1495 extract_bit_field_using_extv (const extraction_insn
*extv
, rtx op0
,
1496 opt_scalar_int_mode op0_mode
,
1497 unsigned HOST_WIDE_INT bitsize
,
1498 unsigned HOST_WIDE_INT bitnum
,
1499 int unsignedp
, rtx target
,
1500 machine_mode mode
, machine_mode tmode
)
1502 struct expand_operand ops
[4];
1503 rtx spec_target
= target
;
1504 rtx spec_target_subreg
= 0;
1505 scalar_int_mode ext_mode
= extv
->field_mode
;
1506 unsigned unit
= GET_MODE_BITSIZE (ext_mode
);
1508 if (bitsize
== 0 || unit
< bitsize
)
1512 /* Get a reference to the first byte of the field. */
1513 op0
= narrow_bit_field_mem (op0
, extv
->struct_mode
, bitsize
, bitnum
,
1517 /* Convert from counting within OP0 to counting in EXT_MODE. */
1518 if (BYTES_BIG_ENDIAN
)
1519 bitnum
+= unit
- GET_MODE_BITSIZE (op0_mode
.require ());
1521 /* If op0 is a register, we need it in EXT_MODE to make it
1522 acceptable to the format of ext(z)v. */
1523 if (GET_CODE (op0
) == SUBREG
&& op0_mode
.require () != ext_mode
)
1525 if (REG_P (op0
) && op0_mode
.require () != ext_mode
)
1526 op0
= gen_lowpart_SUBREG (ext_mode
, op0
);
1529 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1530 "backwards" from the size of the unit we are extracting from.
1531 Otherwise, we count bits from the most significant on a
1532 BYTES/BITS_BIG_ENDIAN machine. */
1534 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1535 bitnum
= unit
- bitsize
- bitnum
;
1538 target
= spec_target
= gen_reg_rtx (tmode
);
1540 if (GET_MODE (target
) != ext_mode
)
1542 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1543 between the mode of the extraction (word_mode) and the target
1544 mode. Instead, create a temporary and use convert_move to set
1547 && TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (target
), ext_mode
))
1549 target
= gen_lowpart (ext_mode
, target
);
1550 if (partial_subreg_p (GET_MODE (spec_target
), ext_mode
))
1551 spec_target_subreg
= target
;
1554 target
= gen_reg_rtx (ext_mode
);
1557 create_output_operand (&ops
[0], target
, ext_mode
);
1558 create_fixed_operand (&ops
[1], op0
);
1559 create_integer_operand (&ops
[2], bitsize
);
1560 create_integer_operand (&ops
[3], bitnum
);
1561 if (maybe_expand_insn (extv
->icode
, 4, ops
))
1563 target
= ops
[0].value
;
1564 if (target
== spec_target
)
1566 if (target
== spec_target_subreg
)
1568 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1573 /* See whether it would be valid to extract the part of OP0 described
1574 by BITNUM and BITSIZE into a value of mode MODE using a subreg
1575 operation. Return the subreg if so, otherwise return null. */
1578 extract_bit_field_as_subreg (machine_mode mode
, rtx op0
,
1579 poly_uint64 bitsize
, poly_uint64 bitnum
)
1581 poly_uint64 bytenum
;
1582 if (multiple_p (bitnum
, BITS_PER_UNIT
, &bytenum
)
1583 && known_eq (bitsize
, GET_MODE_BITSIZE (mode
))
1584 && lowpart_bit_field_p (bitnum
, bitsize
, GET_MODE (op0
))
1585 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op0
)))
1586 return simplify_gen_subreg (mode
, op0
, GET_MODE (op0
), bytenum
);
1590 /* A subroutine of extract_bit_field, with the same arguments.
1591 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1592 if we can find no other means of implementing the operation.
1593 if FALLBACK_P is false, return NULL instead. */
1596 extract_bit_field_1 (rtx str_rtx
, poly_uint64 bitsize
, poly_uint64 bitnum
,
1597 int unsignedp
, rtx target
, machine_mode mode
,
1598 machine_mode tmode
, bool reverse
, bool fallback_p
,
1604 if (tmode
== VOIDmode
)
1607 while (GET_CODE (op0
) == SUBREG
)
1609 bitnum
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1610 op0
= SUBREG_REG (op0
);
1613 /* If we have an out-of-bounds access to a register, just return an
1614 uninitialized register of the required mode. This can occur if the
1615 source code contains an out-of-bounds access to a small array. */
1616 if (REG_P (op0
) && known_ge (bitnum
, GET_MODE_BITSIZE (GET_MODE (op0
))))
1617 return gen_reg_rtx (tmode
);
1620 && mode
== GET_MODE (op0
)
1621 && known_eq (bitnum
, 0U)
1622 && known_eq (bitsize
, GET_MODE_BITSIZE (GET_MODE (op0
))))
1625 op0
= flip_storage_order (mode
, op0
);
1626 /* We're trying to extract a full register from itself. */
1630 /* First try to check for vector from vector extractions. */
1631 if (VECTOR_MODE_P (GET_MODE (op0
))
1633 && VECTOR_MODE_P (tmode
)
1634 && known_eq (bitsize
, GET_MODE_BITSIZE (tmode
))
1635 && maybe_gt (GET_MODE_SIZE (GET_MODE (op0
)), GET_MODE_SIZE (tmode
)))
1637 machine_mode new_mode
= GET_MODE (op0
);
1638 if (GET_MODE_INNER (new_mode
) != GET_MODE_INNER (tmode
))
1640 scalar_mode inner_mode
= GET_MODE_INNER (tmode
);
1642 if (!multiple_p (GET_MODE_BITSIZE (GET_MODE (op0
)),
1643 GET_MODE_UNIT_BITSIZE (tmode
), &nunits
)
1644 || !mode_for_vector (inner_mode
, nunits
).exists (&new_mode
)
1645 || !VECTOR_MODE_P (new_mode
)
1646 || maybe_ne (GET_MODE_SIZE (new_mode
),
1647 GET_MODE_SIZE (GET_MODE (op0
)))
1648 || GET_MODE_INNER (new_mode
) != GET_MODE_INNER (tmode
)
1649 || !targetm
.vector_mode_supported_p (new_mode
))
1650 new_mode
= VOIDmode
;
1653 if (new_mode
!= VOIDmode
1654 && (convert_optab_handler (vec_extract_optab
, new_mode
, tmode
)
1655 != CODE_FOR_nothing
)
1656 && multiple_p (bitnum
, GET_MODE_BITSIZE (tmode
), &pos
))
1658 struct expand_operand ops
[3];
1659 machine_mode outermode
= new_mode
;
1660 machine_mode innermode
= tmode
;
1661 enum insn_code icode
1662 = convert_optab_handler (vec_extract_optab
, outermode
, innermode
);
1664 if (new_mode
!= GET_MODE (op0
))
1665 op0
= gen_lowpart (new_mode
, op0
);
1666 create_output_operand (&ops
[0], target
, innermode
);
1668 create_input_operand (&ops
[1], op0
, outermode
);
1669 create_integer_operand (&ops
[2], pos
);
1670 if (maybe_expand_insn (icode
, 3, ops
))
1672 if (alt_rtl
&& ops
[0].target
)
1674 target
= ops
[0].value
;
1675 if (GET_MODE (target
) != mode
)
1676 return gen_lowpart (tmode
, target
);
1682 /* See if we can get a better vector mode before extracting. */
1683 if (VECTOR_MODE_P (GET_MODE (op0
))
1685 && GET_MODE_INNER (GET_MODE (op0
)) != tmode
)
1687 machine_mode new_mode
;
1689 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1690 new_mode
= MIN_MODE_VECTOR_FLOAT
;
1691 else if (GET_MODE_CLASS (tmode
) == MODE_FRACT
)
1692 new_mode
= MIN_MODE_VECTOR_FRACT
;
1693 else if (GET_MODE_CLASS (tmode
) == MODE_UFRACT
)
1694 new_mode
= MIN_MODE_VECTOR_UFRACT
;
1695 else if (GET_MODE_CLASS (tmode
) == MODE_ACCUM
)
1696 new_mode
= MIN_MODE_VECTOR_ACCUM
;
1697 else if (GET_MODE_CLASS (tmode
) == MODE_UACCUM
)
1698 new_mode
= MIN_MODE_VECTOR_UACCUM
;
1700 new_mode
= MIN_MODE_VECTOR_INT
;
1702 FOR_EACH_MODE_FROM (new_mode
, new_mode
)
1703 if (known_eq (GET_MODE_SIZE (new_mode
), GET_MODE_SIZE (GET_MODE (op0
)))
1704 && known_eq (GET_MODE_UNIT_SIZE (new_mode
), GET_MODE_SIZE (tmode
))
1705 && targetm
.vector_mode_supported_p (new_mode
))
1707 if (new_mode
!= VOIDmode
)
1708 op0
= gen_lowpart (new_mode
, op0
);
1711 /* Use vec_extract patterns for extracting parts of vectors whenever
1712 available. If that fails, see whether the current modes and bitregion
1713 give a natural subreg. */
1714 machine_mode outermode
= GET_MODE (op0
);
1715 if (VECTOR_MODE_P (outermode
) && !MEM_P (op0
))
1717 scalar_mode innermode
= GET_MODE_INNER (outermode
);
1718 enum insn_code icode
1719 = convert_optab_handler (vec_extract_optab
, outermode
, innermode
);
1721 if (icode
!= CODE_FOR_nothing
1722 && known_eq (bitsize
, GET_MODE_BITSIZE (innermode
))
1723 && multiple_p (bitnum
, GET_MODE_BITSIZE (innermode
), &pos
))
1725 struct expand_operand ops
[3];
1727 create_output_operand (&ops
[0], target
, innermode
);
1729 create_input_operand (&ops
[1], op0
, outermode
);
1730 create_integer_operand (&ops
[2], pos
);
1731 if (maybe_expand_insn (icode
, 3, ops
))
1733 if (alt_rtl
&& ops
[0].target
)
1735 target
= ops
[0].value
;
1736 if (GET_MODE (target
) != mode
)
1737 return gen_lowpart (tmode
, target
);
1741 /* Using subregs is useful if we're extracting one register vector
1742 from a multi-register vector. extract_bit_field_as_subreg checks
1743 for valid bitsize and bitnum, so we don't need to do that here. */
1744 if (VECTOR_MODE_P (mode
))
1746 rtx sub
= extract_bit_field_as_subreg (mode
, op0
, bitsize
, bitnum
);
1752 /* Make sure we are playing with integral modes. Pun with subregs
1754 opt_scalar_int_mode op0_mode
= int_mode_for_mode (GET_MODE (op0
));
1755 scalar_int_mode imode
;
1756 if (!op0_mode
.exists (&imode
) || imode
!= GET_MODE (op0
))
1759 op0
= adjust_bitfield_address_size (op0
, op0_mode
.else_blk (),
1761 else if (op0_mode
.exists (&imode
))
1763 op0
= gen_lowpart (imode
, op0
);
1765 /* If we got a SUBREG, force it into a register since we
1766 aren't going to be able to do another SUBREG on it. */
1767 if (GET_CODE (op0
) == SUBREG
)
1768 op0
= force_reg (imode
, op0
);
1772 poly_int64 size
= GET_MODE_SIZE (GET_MODE (op0
));
1773 rtx mem
= assign_stack_temp (GET_MODE (op0
), size
);
1774 emit_move_insn (mem
, op0
);
1775 op0
= adjust_bitfield_address_size (mem
, BLKmode
, 0, size
);
1779 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1780 If that's wrong, the solution is to test for it and set TARGET to 0
1783 /* Get the mode of the field to use for atomic access or subreg
1785 if (!SCALAR_INT_MODE_P (tmode
)
1786 || !mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0).exists (&mode1
))
1788 gcc_assert (mode1
!= BLKmode
);
1790 /* Extraction of a full MODE1 value can be done with a subreg as long
1791 as the least significant bit of the value is the least significant
1792 bit of either OP0 or a word of OP0. */
1793 if (!MEM_P (op0
) && !reverse
)
1795 rtx sub
= extract_bit_field_as_subreg (mode1
, op0
, bitsize
, bitnum
);
1797 return convert_extracted_bit_field (sub
, mode
, tmode
, unsignedp
);
1800 /* Extraction of a full MODE1 value can be done with a load as long as
1801 the field is on a byte boundary and is sufficiently aligned. */
1802 poly_uint64 bytenum
;
1803 if (simple_mem_bitfield_p (op0
, bitsize
, bitnum
, mode1
, &bytenum
))
1805 op0
= adjust_bitfield_address (op0
, mode1
, bytenum
);
1807 op0
= flip_storage_order (mode1
, op0
);
1808 return convert_extracted_bit_field (op0
, mode
, tmode
, unsignedp
);
1811 /* If we have a memory source and a non-constant bit offset, restrict
1812 the memory to the referenced bytes. This is a worst-case fallback
1813 but is useful for things like vector booleans. */
1814 if (MEM_P (op0
) && !bitnum
.is_constant ())
1816 bytenum
= bits_to_bytes_round_down (bitnum
);
1817 bitnum
= num_trailing_bits (bitnum
);
1818 poly_uint64 bytesize
= bits_to_bytes_round_up (bitnum
+ bitsize
);
1819 op0
= adjust_bitfield_address_size (op0
, BLKmode
, bytenum
, bytesize
);
1820 op0_mode
= opt_scalar_int_mode ();
1823 /* It's possible we'll need to handle other cases here for
1824 polynomial bitnum and bitsize. */
1826 /* From here on we need to be looking at a fixed-size insertion. */
1827 return extract_integral_bit_field (op0
, op0_mode
, bitsize
.to_constant (),
1828 bitnum
.to_constant (), unsignedp
,
1829 target
, mode
, tmode
, reverse
, fallback_p
);
1832 /* Subroutine of extract_bit_field_1, with the same arguments, except
1833 that BITSIZE and BITNUM are constant. Handle cases specific to
1834 integral modes. If OP0_MODE is defined, it is the mode of OP0,
1835 otherwise OP0 is a BLKmode MEM. */
1838 extract_integral_bit_field (rtx op0
, opt_scalar_int_mode op0_mode
,
1839 unsigned HOST_WIDE_INT bitsize
,
1840 unsigned HOST_WIDE_INT bitnum
, int unsignedp
,
1841 rtx target
, machine_mode mode
, machine_mode tmode
,
1842 bool reverse
, bool fallback_p
)
1844 /* Handle fields bigger than a word. */
1846 if (bitsize
> BITS_PER_WORD
)
1848 /* Here we transfer the words of the field
1849 in the order least significant first.
1850 This is because the most significant word is the one which may
1851 be less than full. */
1853 const bool backwards
= WORDS_BIG_ENDIAN
;
1854 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1858 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1859 target
= gen_reg_rtx (mode
);
1861 /* In case we're about to clobber a base register or something
1862 (see gcc.c-torture/execute/20040625-1.c). */
1863 if (reg_mentioned_p (target
, op0
))
1864 target
= gen_reg_rtx (mode
);
1866 /* Indicate for flow that the entire target reg is being set. */
1867 emit_clobber (target
);
1869 /* The mode must be fixed-size, since extract_bit_field_1 handles
1870 extractions from variable-sized objects before calling this
1872 unsigned int target_size
1873 = GET_MODE_SIZE (GET_MODE (target
)).to_constant ();
1874 last
= get_last_insn ();
1875 for (i
= 0; i
< nwords
; i
++)
1877 /* If I is 0, use the low-order word in both field and target;
1878 if I is 1, use the next to lowest word; and so on. */
1879 /* Word number in TARGET to use. */
1880 unsigned int wordnum
1881 = (backwards
? target_size
/ UNITS_PER_WORD
- i
- 1 : i
);
1882 /* Offset from start of field in OP0. */
1883 unsigned int bit_offset
= (backwards
^ reverse
1884 ? MAX ((int) bitsize
- ((int) i
+ 1)
1887 : (int) i
* BITS_PER_WORD
);
1888 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1890 = extract_bit_field_1 (op0
, MIN (BITS_PER_WORD
,
1891 bitsize
- i
* BITS_PER_WORD
),
1892 bitnum
+ bit_offset
, 1, target_part
,
1893 mode
, word_mode
, reverse
, fallback_p
, NULL
);
1895 gcc_assert (target_part
);
1898 delete_insns_since (last
);
1902 if (result_part
!= target_part
)
1903 emit_move_insn (target_part
, result_part
);
1908 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1909 need to be zero'd out. */
1910 if (target_size
> nwords
* UNITS_PER_WORD
)
1912 unsigned int i
, total_words
;
1914 total_words
= target_size
/ UNITS_PER_WORD
;
1915 for (i
= nwords
; i
< total_words
; i
++)
1917 (operand_subword (target
,
1918 backwards
? total_words
- i
- 1 : i
,
1925 /* Signed bit field: sign-extend with two arithmetic shifts. */
1926 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1927 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1928 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1929 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1932 /* If OP0 is a multi-word register, narrow it to the affected word.
1933 If the region spans two words, defer to extract_split_bit_field. */
1934 if (!MEM_P (op0
) && GET_MODE_SIZE (op0_mode
.require ()) > UNITS_PER_WORD
)
1936 if (bitnum
% BITS_PER_WORD
+ bitsize
> BITS_PER_WORD
)
1940 target
= extract_split_bit_field (op0
, op0_mode
, bitsize
, bitnum
,
1941 unsignedp
, reverse
);
1942 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1944 op0
= simplify_gen_subreg (word_mode
, op0
, op0_mode
.require (),
1945 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
1946 op0_mode
= word_mode
;
1947 bitnum
%= BITS_PER_WORD
;
1950 /* From here on we know the desired field is smaller than a word.
1951 If OP0 is a register, it too fits within a word. */
1952 enum extraction_pattern pattern
= unsignedp
? EP_extzv
: EP_extv
;
1953 extraction_insn extv
;
1956 /* ??? We could limit the structure size to the part of OP0 that
1957 contains the field, with appropriate checks for endianness
1958 and TARGET_TRULY_NOOP_TRUNCATION. */
1959 && get_best_reg_extraction_insn (&extv
, pattern
,
1960 GET_MODE_BITSIZE (op0_mode
.require ()),
1963 rtx result
= extract_bit_field_using_extv (&extv
, op0
, op0_mode
,
1965 unsignedp
, target
, mode
,
1971 /* If OP0 is a memory, try copying it to a register and seeing if a
1972 cheap register alternative is available. */
1973 if (MEM_P (op0
) & !reverse
)
1975 if (get_best_mem_extraction_insn (&extv
, pattern
, bitsize
, bitnum
,
1978 rtx result
= extract_bit_field_using_extv (&extv
, op0
, op0_mode
,
1980 unsignedp
, target
, mode
,
1986 rtx_insn
*last
= get_last_insn ();
1988 /* Try loading part of OP0 into a register and extracting the
1989 bitfield from that. */
1990 unsigned HOST_WIDE_INT bitpos
;
1991 rtx xop0
= adjust_bit_field_mem_for_reg (pattern
, op0
, bitsize
, bitnum
,
1992 0, 0, tmode
, &bitpos
);
1995 xop0
= copy_to_reg (xop0
);
1996 rtx result
= extract_bit_field_1 (xop0
, bitsize
, bitpos
,
1998 mode
, tmode
, reverse
, false, NULL
);
2001 delete_insns_since (last
);
2008 /* Find a correspondingly-sized integer field, so we can apply
2009 shifts and masks to it. */
2010 scalar_int_mode int_mode
;
2011 if (!int_mode_for_mode (tmode
).exists (&int_mode
))
2012 /* If this fails, we should probably push op0 out to memory and then
2014 int_mode
= int_mode_for_mode (mode
).require ();
2016 target
= extract_fixed_bit_field (int_mode
, op0
, op0_mode
, bitsize
,
2017 bitnum
, target
, unsignedp
, reverse
);
2019 /* Complex values must be reversed piecewise, so we need to undo the global
2020 reversal, convert to the complex mode and reverse again. */
2021 if (reverse
&& COMPLEX_MODE_P (tmode
))
2023 target
= flip_storage_order (int_mode
, target
);
2024 target
= convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
2025 target
= flip_storage_order (tmode
, target
);
2028 target
= convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
2033 /* Generate code to extract a byte-field from STR_RTX
2034 containing BITSIZE bits, starting at BITNUM,
2035 and put it in TARGET if possible (if TARGET is nonzero).
2036 Regardless of TARGET, we return the rtx for where the value is placed.
2038 STR_RTX is the structure containing the byte (a REG or MEM).
2039 UNSIGNEDP is nonzero if this is an unsigned bit field.
2040 MODE is the natural mode of the field value once extracted.
2041 TMODE is the mode the caller would like the value to have;
2042 but the value may be returned with type MODE instead.
2044 If REVERSE is true, the extraction is to be done in reverse order.
2046 If a TARGET is specified and we can store in it at no extra cost,
2047 we do so, and return TARGET.
2048 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
2049 if they are equally easy. */
2052 extract_bit_field (rtx str_rtx
, poly_uint64 bitsize
, poly_uint64 bitnum
,
2053 int unsignedp
, rtx target
, machine_mode mode
,
2054 machine_mode tmode
, bool reverse
, rtx
*alt_rtl
)
2058 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
2059 if (maybe_ne (GET_MODE_BITSIZE (GET_MODE (str_rtx
)), 0))
2060 mode1
= GET_MODE (str_rtx
);
2061 else if (target
&& maybe_ne (GET_MODE_BITSIZE (GET_MODE (target
)), 0))
2062 mode1
= GET_MODE (target
);
2066 unsigned HOST_WIDE_INT ibitsize
, ibitnum
;
2067 scalar_int_mode int_mode
;
2068 if (bitsize
.is_constant (&ibitsize
)
2069 && bitnum
.is_constant (&ibitnum
)
2070 && is_a
<scalar_int_mode
> (mode1
, &int_mode
)
2071 && strict_volatile_bitfield_p (str_rtx
, ibitsize
, ibitnum
,
2074 /* Extraction of a full INT_MODE value can be done with a simple load.
2075 We know here that the field can be accessed with one single
2076 instruction. For targets that support unaligned memory,
2077 an unaligned access may be necessary. */
2078 if (ibitsize
== GET_MODE_BITSIZE (int_mode
))
2080 rtx result
= adjust_bitfield_address (str_rtx
, int_mode
,
2081 ibitnum
/ BITS_PER_UNIT
);
2083 result
= flip_storage_order (int_mode
, result
);
2084 gcc_assert (ibitnum
% BITS_PER_UNIT
== 0);
2085 return convert_extracted_bit_field (result
, mode
, tmode
, unsignedp
);
2088 str_rtx
= narrow_bit_field_mem (str_rtx
, int_mode
, ibitsize
, ibitnum
,
2090 gcc_assert (ibitnum
+ ibitsize
<= GET_MODE_BITSIZE (int_mode
));
2091 str_rtx
= copy_to_reg (str_rtx
);
2092 return extract_bit_field_1 (str_rtx
, ibitsize
, ibitnum
, unsignedp
,
2093 target
, mode
, tmode
, reverse
, true, alt_rtl
);
2096 return extract_bit_field_1 (str_rtx
, bitsize
, bitnum
, unsignedp
,
2097 target
, mode
, tmode
, reverse
, true, alt_rtl
);
2100 /* Use shifts and boolean operations to extract a field of BITSIZE bits
2101 from bit BITNUM of OP0. If OP0_MODE is defined, it is the mode of OP0,
2102 otherwise OP0 is a BLKmode MEM.
2104 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
2105 If REVERSE is true, the extraction is to be done in reverse order.
2107 If TARGET is nonzero, attempts to store the value there
2108 and return TARGET, but this is not guaranteed.
2109 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
2112 extract_fixed_bit_field (machine_mode tmode
, rtx op0
,
2113 opt_scalar_int_mode op0_mode
,
2114 unsigned HOST_WIDE_INT bitsize
,
2115 unsigned HOST_WIDE_INT bitnum
, rtx target
,
2116 int unsignedp
, bool reverse
)
2118 scalar_int_mode mode
;
2121 if (!get_best_mode (bitsize
, bitnum
, 0, 0, MEM_ALIGN (op0
),
2122 BITS_PER_WORD
, MEM_VOLATILE_P (op0
), &mode
))
2123 /* The only way this should occur is if the field spans word
2125 return extract_split_bit_field (op0
, op0_mode
, bitsize
, bitnum
,
2126 unsignedp
, reverse
);
2128 op0
= narrow_bit_field_mem (op0
, mode
, bitsize
, bitnum
, &bitnum
);
2131 mode
= op0_mode
.require ();
2133 return extract_fixed_bit_field_1 (tmode
, op0
, mode
, bitsize
, bitnum
,
2134 target
, unsignedp
, reverse
);
2137 /* Helper function for extract_fixed_bit_field, extracts
2138 the bit field always using MODE, which is the mode of OP0.
2139 The other arguments are as for extract_fixed_bit_field. */
2142 extract_fixed_bit_field_1 (machine_mode tmode
, rtx op0
, scalar_int_mode mode
,
2143 unsigned HOST_WIDE_INT bitsize
,
2144 unsigned HOST_WIDE_INT bitnum
, rtx target
,
2145 int unsignedp
, bool reverse
)
2147 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
2148 for invalid input, such as extract equivalent of f5 from
2149 gcc.dg/pr48335-2.c. */
2151 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
2152 /* BITNUM is the distance between our msb and that of OP0.
2153 Convert it to the distance from the lsb. */
2154 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
2156 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
2157 We have reduced the big-endian case to the little-endian case. */
2159 op0
= flip_storage_order (mode
, op0
);
2165 /* If the field does not already start at the lsb,
2166 shift it so it does. */
2167 /* Maybe propagate the target for the shift. */
2168 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
2171 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, bitnum
, subtarget
, 1);
2173 /* Convert the value to the desired mode. TMODE must also be a
2174 scalar integer for this conversion to make sense, since we
2175 shouldn't reinterpret the bits. */
2176 scalar_int_mode new_mode
= as_a
<scalar_int_mode
> (tmode
);
2177 if (mode
!= new_mode
)
2178 op0
= convert_to_mode (new_mode
, op0
, 1);
2180 /* Unless the msb of the field used to be the msb when we shifted,
2181 mask out the upper bits. */
2183 if (GET_MODE_BITSIZE (mode
) != bitnum
+ bitsize
)
2184 return expand_binop (new_mode
, and_optab
, op0
,
2185 mask_rtx (new_mode
, 0, bitsize
, 0),
2186 target
, 1, OPTAB_LIB_WIDEN
);
2190 /* To extract a signed bit-field, first shift its msb to the msb of the word,
2191 then arithmetic-shift its lsb to the lsb of the word. */
2192 op0
= force_reg (mode
, op0
);
2194 /* Find the narrowest integer mode that contains the field. */
2196 opt_scalar_int_mode mode_iter
;
2197 FOR_EACH_MODE_IN_CLASS (mode_iter
, MODE_INT
)
2198 if (GET_MODE_BITSIZE (mode_iter
.require ()) >= bitsize
+ bitnum
)
2201 mode
= mode_iter
.require ();
2202 op0
= convert_to_mode (mode
, op0
, 0);
2207 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitnum
))
2209 int amount
= GET_MODE_BITSIZE (mode
) - (bitsize
+ bitnum
);
2210 /* Maybe propagate the target for the shift. */
2211 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
2212 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
2215 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
2216 GET_MODE_BITSIZE (mode
) - bitsize
, target
, 0);
2219 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
2223 lshift_value (machine_mode mode
, unsigned HOST_WIDE_INT value
,
2226 return immed_wide_int_const (wi::lshift (value
, bitpos
), mode
);
2229 /* Extract a bit field that is split across two words
2230 and return an RTX for the result.
2232 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
2233 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
2234 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
2235 If OP0_MODE is defined, it is the mode of OP0, otherwise OP0 is
2238 If REVERSE is true, the extraction is to be done in reverse order. */
2241 extract_split_bit_field (rtx op0
, opt_scalar_int_mode op0_mode
,
2242 unsigned HOST_WIDE_INT bitsize
,
2243 unsigned HOST_WIDE_INT bitpos
, int unsignedp
,
2247 unsigned int bitsdone
= 0;
2248 rtx result
= NULL_RTX
;
2251 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
2253 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
2254 unit
= BITS_PER_WORD
;
2256 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
2258 while (bitsdone
< bitsize
)
2260 unsigned HOST_WIDE_INT thissize
;
2262 unsigned HOST_WIDE_INT thispos
;
2263 unsigned HOST_WIDE_INT offset
;
2265 offset
= (bitpos
+ bitsdone
) / unit
;
2266 thispos
= (bitpos
+ bitsdone
) % unit
;
2268 /* THISSIZE must not overrun a word boundary. Otherwise,
2269 extract_fixed_bit_field will call us again, and we will mutually
2271 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
2272 thissize
= MIN (thissize
, unit
- thispos
);
2274 /* If OP0 is a register, then handle OFFSET here. */
2275 rtx op0_piece
= op0
;
2276 opt_scalar_int_mode op0_piece_mode
= op0_mode
;
2277 if (SUBREG_P (op0
) || REG_P (op0
))
2279 op0_piece
= operand_subword_force (op0
, offset
, op0_mode
.require ());
2280 op0_piece_mode
= word_mode
;
2284 /* Extract the parts in bit-counting order,
2285 whose meaning is determined by BYTES_PER_UNIT.
2286 OFFSET is in UNITs, and UNIT is in bits. */
2287 part
= extract_fixed_bit_field (word_mode
, op0_piece
, op0_piece_mode
,
2288 thissize
, offset
* unit
+ thispos
,
2290 bitsdone
+= thissize
;
2292 /* Shift this part into place for the result. */
2293 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
2295 if (bitsize
!= bitsdone
)
2296 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2297 bitsize
- bitsdone
, 0, 1);
2301 if (bitsdone
!= thissize
)
2302 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2303 bitsdone
- thissize
, 0, 1);
2309 /* Combine the parts with bitwise or. This works
2310 because we extracted each part as an unsigned bit field. */
2311 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
2317 /* Unsigned bit field: we are done. */
2320 /* Signed bit field: sign-extend with two arithmetic shifts. */
2321 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
2322 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
2323 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
2324 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
2327 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
2328 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
2329 MODE, fill the upper bits with zeros. Fail if the layout of either
2330 mode is unknown (as for CC modes) or if the extraction would involve
2331 unprofitable mode punning. Return the value on success, otherwise
2334 This is different from gen_lowpart* in these respects:
2336 - the returned value must always be considered an rvalue
2338 - when MODE is wider than SRC_MODE, the extraction involves
2341 - when MODE is smaller than SRC_MODE, the extraction involves
2342 a truncation (and is thus subject to TARGET_TRULY_NOOP_TRUNCATION).
2344 In other words, this routine performs a computation, whereas the
2345 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2349 extract_low_bits (machine_mode mode
, machine_mode src_mode
, rtx src
)
2351 scalar_int_mode int_mode
, src_int_mode
;
2353 if (mode
== src_mode
)
2356 if (CONSTANT_P (src
))
2358 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2359 fails, it will happily create (subreg (symbol_ref)) or similar
2361 poly_uint64 byte
= subreg_lowpart_offset (mode
, src_mode
);
2362 rtx ret
= simplify_subreg (mode
, src
, src_mode
, byte
);
2366 if (GET_MODE (src
) == VOIDmode
2367 || !validate_subreg (mode
, src_mode
, src
, byte
))
2370 src
= force_reg (GET_MODE (src
), src
);
2371 return gen_rtx_SUBREG (mode
, src
, byte
);
2374 if (GET_MODE_CLASS (mode
) == MODE_CC
|| GET_MODE_CLASS (src_mode
) == MODE_CC
)
2377 if (known_eq (GET_MODE_BITSIZE (mode
), GET_MODE_BITSIZE (src_mode
))
2378 && targetm
.modes_tieable_p (mode
, src_mode
))
2380 rtx x
= gen_lowpart_common (mode
, src
);
2385 if (!int_mode_for_mode (src_mode
).exists (&src_int_mode
)
2386 || !int_mode_for_mode (mode
).exists (&int_mode
))
2389 if (!targetm
.modes_tieable_p (src_int_mode
, src_mode
))
2391 if (!targetm
.modes_tieable_p (int_mode
, mode
))
2394 src
= gen_lowpart (src_int_mode
, src
);
2395 src
= convert_modes (int_mode
, src_int_mode
, src
, true);
2396 src
= gen_lowpart (mode
, src
);
2400 /* Add INC into TARGET. */
2403 expand_inc (rtx target
, rtx inc
)
2405 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
2407 target
, 0, OPTAB_LIB_WIDEN
);
2408 if (value
!= target
)
2409 emit_move_insn (target
, value
);
2412 /* Subtract DEC from TARGET. */
2415 expand_dec (rtx target
, rtx dec
)
2417 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
2419 target
, 0, OPTAB_LIB_WIDEN
);
2420 if (value
!= target
)
2421 emit_move_insn (target
, value
);
2424 /* Output a shift instruction for expression code CODE,
2425 with SHIFTED being the rtx for the value to shift,
2426 and AMOUNT the rtx for the amount to shift by.
2427 Store the result in the rtx TARGET, if that is convenient.
2428 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2429 Return the rtx for where the value is.
2430 If that cannot be done, abort the compilation unless MAY_FAIL is true,
2431 in which case 0 is returned. */
2434 expand_shift_1 (enum tree_code code
, machine_mode mode
, rtx shifted
,
2435 rtx amount
, rtx target
, int unsignedp
, bool may_fail
= false)
2438 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2439 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2440 optab lshift_optab
= ashl_optab
;
2441 optab rshift_arith_optab
= ashr_optab
;
2442 optab rshift_uns_optab
= lshr_optab
;
2443 optab lrotate_optab
= rotl_optab
;
2444 optab rrotate_optab
= rotr_optab
;
2445 machine_mode op1_mode
;
2446 scalar_mode scalar_mode
= GET_MODE_INNER (mode
);
2448 bool speed
= optimize_insn_for_speed_p ();
2451 op1_mode
= GET_MODE (op1
);
2453 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2454 shift amount is a vector, use the vector/vector shift patterns. */
2455 if (VECTOR_MODE_P (mode
) && VECTOR_MODE_P (op1_mode
))
2457 lshift_optab
= vashl_optab
;
2458 rshift_arith_optab
= vashr_optab
;
2459 rshift_uns_optab
= vlshr_optab
;
2460 lrotate_optab
= vrotl_optab
;
2461 rrotate_optab
= vrotr_optab
;
2464 /* Previously detected shift-counts computed by NEGATE_EXPR
2465 and shifted in the other direction; but that does not work
2468 if (SHIFT_COUNT_TRUNCATED
)
2470 if (CONST_INT_P (op1
)
2471 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2472 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (scalar_mode
)))
2473 op1
= gen_int_shift_amount (mode
,
2474 (unsigned HOST_WIDE_INT
) INTVAL (op1
)
2475 % GET_MODE_BITSIZE (scalar_mode
));
2476 else if (GET_CODE (op1
) == SUBREG
2477 && subreg_lowpart_p (op1
)
2478 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1
)))
2479 && SCALAR_INT_MODE_P (GET_MODE (op1
)))
2480 op1
= SUBREG_REG (op1
);
2483 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
2484 prefer left rotation, if op1 is from bitsize / 2 + 1 to
2485 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
2488 && CONST_INT_P (op1
)
2489 && IN_RANGE (INTVAL (op1
), GET_MODE_BITSIZE (scalar_mode
) / 2 + left
,
2490 GET_MODE_BITSIZE (scalar_mode
) - 1))
2492 op1
= gen_int_shift_amount (mode
, (GET_MODE_BITSIZE (scalar_mode
)
2495 code
= left
? LROTATE_EXPR
: RROTATE_EXPR
;
2498 /* Rotation of 16bit values by 8 bits is effectively equivalent to a bswaphi.
2499 Note that this is not the case for bigger values. For instance a rotation
2500 of 0x01020304 by 16 bits gives 0x03040102 which is different from
2501 0x04030201 (bswapsi). */
2503 && CONST_INT_P (op1
)
2504 && INTVAL (op1
) == BITS_PER_UNIT
2505 && GET_MODE_SIZE (scalar_mode
) == 2
2506 && optab_handler (bswap_optab
, mode
) != CODE_FOR_nothing
)
2507 return expand_unop (mode
, bswap_optab
, shifted
, NULL_RTX
, unsignedp
);
2509 if (op1
== const0_rtx
)
2512 /* Check whether its cheaper to implement a left shift by a constant
2513 bit count by a sequence of additions. */
2514 if (code
== LSHIFT_EXPR
2515 && CONST_INT_P (op1
)
2517 && INTVAL (op1
) < GET_MODE_PRECISION (scalar_mode
)
2518 && INTVAL (op1
) < MAX_BITS_PER_WORD
2519 && (shift_cost (speed
, mode
, INTVAL (op1
))
2520 > INTVAL (op1
) * add_cost (speed
, mode
))
2521 && shift_cost (speed
, mode
, INTVAL (op1
)) != MAX_COST
)
2524 for (i
= 0; i
< INTVAL (op1
); i
++)
2526 temp
= force_reg (mode
, shifted
);
2527 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2528 unsignedp
, OPTAB_LIB_WIDEN
);
2533 for (attempt
= 0; temp
== 0 && attempt
< 3; attempt
++)
2535 enum optab_methods methods
;
2538 methods
= OPTAB_DIRECT
;
2539 else if (attempt
== 1)
2540 methods
= OPTAB_WIDEN
;
2542 methods
= OPTAB_LIB_WIDEN
;
2546 /* Widening does not work for rotation. */
2547 if (methods
== OPTAB_WIDEN
)
2549 else if (methods
== OPTAB_LIB_WIDEN
)
2551 /* If we have been unable to open-code this by a rotation,
2552 do it as the IOR of two shifts. I.e., to rotate A
2554 (A << N) | ((unsigned) A >> ((-N) & (C - 1)))
2555 where C is the bitsize of A.
2557 It is theoretically possible that the target machine might
2558 not be able to perform either shift and hence we would
2559 be making two libcalls rather than just the one for the
2560 shift (similarly if IOR could not be done). We will allow
2561 this extremely unlikely lossage to avoid complicating the
2564 rtx subtarget
= target
== shifted
? 0 : target
;
2565 rtx new_amount
, other_amount
;
2569 if (op1
== const0_rtx
)
2571 else if (CONST_INT_P (op1
))
2572 other_amount
= gen_int_shift_amount
2573 (mode
, GET_MODE_BITSIZE (scalar_mode
) - INTVAL (op1
));
2577 = simplify_gen_unary (NEG
, GET_MODE (op1
),
2578 op1
, GET_MODE (op1
));
2579 HOST_WIDE_INT mask
= GET_MODE_PRECISION (scalar_mode
) - 1;
2581 = simplify_gen_binary (AND
, GET_MODE (op1
), other_amount
,
2582 gen_int_mode (mask
, GET_MODE (op1
)));
2585 shifted
= force_reg (mode
, shifted
);
2587 temp
= expand_shift_1 (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2588 mode
, shifted
, new_amount
, 0, 1);
2589 temp1
= expand_shift_1 (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2590 mode
, shifted
, other_amount
,
2592 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2593 unsignedp
, methods
);
2596 temp
= expand_binop (mode
,
2597 left
? lrotate_optab
: rrotate_optab
,
2598 shifted
, op1
, target
, unsignedp
, methods
);
2601 temp
= expand_binop (mode
,
2602 left
? lshift_optab
: rshift_uns_optab
,
2603 shifted
, op1
, target
, unsignedp
, methods
);
2605 /* Do arithmetic shifts.
2606 Also, if we are going to widen the operand, we can just as well
2607 use an arithmetic right-shift instead of a logical one. */
2608 if (temp
== 0 && ! rotate
2609 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2611 enum optab_methods methods1
= methods
;
2613 /* If trying to widen a log shift to an arithmetic shift,
2614 don't accept an arithmetic shift of the same size. */
2616 methods1
= OPTAB_MUST_WIDEN
;
2618 /* Arithmetic shift */
2620 temp
= expand_binop (mode
,
2621 left
? lshift_optab
: rshift_arith_optab
,
2622 shifted
, op1
, target
, unsignedp
, methods1
);
2625 /* We used to try extzv here for logical right shifts, but that was
2626 only useful for one machine, the VAX, and caused poor code
2627 generation there for lshrdi3, so the code was deleted and a
2628 define_expand for lshrsi3 was added to vax.md. */
2631 gcc_assert (temp
!= NULL_RTX
|| may_fail
);
2635 /* Output a shift instruction for expression code CODE,
2636 with SHIFTED being the rtx for the value to shift,
2637 and AMOUNT the amount to shift by.
2638 Store the result in the rtx TARGET, if that is convenient.
2639 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2640 Return the rtx for where the value is. */
2643 expand_shift (enum tree_code code
, machine_mode mode
, rtx shifted
,
2644 poly_int64 amount
, rtx target
, int unsignedp
)
2646 return expand_shift_1 (code
, mode
, shifted
,
2647 gen_int_shift_amount (mode
, amount
),
2651 /* Likewise, but return 0 if that cannot be done. */
2654 maybe_expand_shift (enum tree_code code
, machine_mode mode
, rtx shifted
,
2655 int amount
, rtx target
, int unsignedp
)
2657 return expand_shift_1 (code
, mode
,
2658 shifted
, GEN_INT (amount
), target
, unsignedp
, true);
2661 /* Output a shift instruction for expression code CODE,
2662 with SHIFTED being the rtx for the value to shift,
2663 and AMOUNT the tree for the amount to shift by.
2664 Store the result in the rtx TARGET, if that is convenient.
2665 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2666 Return the rtx for where the value is. */
2669 expand_variable_shift (enum tree_code code
, machine_mode mode
, rtx shifted
,
2670 tree amount
, rtx target
, int unsignedp
)
2672 return expand_shift_1 (code
, mode
,
2673 shifted
, expand_normal (amount
), target
, unsignedp
);
2677 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2678 const struct mult_cost
*, machine_mode mode
);
2679 static rtx
expand_mult_const (machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2680 const struct algorithm
*, enum mult_variant
);
2681 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2682 static rtx
extract_high_half (scalar_int_mode
, rtx
);
2683 static rtx
expmed_mult_highpart (scalar_int_mode
, rtx
, rtx
, rtx
, int, int);
2684 static rtx
expmed_mult_highpart_optab (scalar_int_mode
, rtx
, rtx
, rtx
,
2686 /* Compute and return the best algorithm for multiplying by T.
2687 The algorithm must cost less than cost_limit
2688 If retval.cost >= COST_LIMIT, no algorithm was found and all
2689 other field of the returned struct are undefined.
2690 MODE is the machine mode of the multiplication. */
2693 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2694 const struct mult_cost
*cost_limit
, machine_mode mode
)
2697 struct algorithm
*alg_in
, *best_alg
;
2698 struct mult_cost best_cost
;
2699 struct mult_cost new_limit
;
2700 int op_cost
, op_latency
;
2701 unsigned HOST_WIDE_INT orig_t
= t
;
2702 unsigned HOST_WIDE_INT q
;
2703 int maxm
, hash_index
;
2704 bool cache_hit
= false;
2705 enum alg_code cache_alg
= alg_zero
;
2706 bool speed
= optimize_insn_for_speed_p ();
2707 scalar_int_mode imode
;
2708 struct alg_hash_entry
*entry_ptr
;
2710 /* Indicate that no algorithm is yet found. If no algorithm
2711 is found, this value will be returned and indicate failure. */
2712 alg_out
->cost
.cost
= cost_limit
->cost
+ 1;
2713 alg_out
->cost
.latency
= cost_limit
->latency
+ 1;
2715 if (cost_limit
->cost
< 0
2716 || (cost_limit
->cost
== 0 && cost_limit
->latency
<= 0))
2719 /* Be prepared for vector modes. */
2720 imode
= as_a
<scalar_int_mode
> (GET_MODE_INNER (mode
));
2722 maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (imode
));
2724 /* Restrict the bits of "t" to the multiplication's mode. */
2725 t
&= GET_MODE_MASK (imode
);
2727 /* t == 1 can be done in zero cost. */
2731 alg_out
->cost
.cost
= 0;
2732 alg_out
->cost
.latency
= 0;
2733 alg_out
->op
[0] = alg_m
;
2737 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2741 if (MULT_COST_LESS (cost_limit
, zero_cost (speed
)))
2746 alg_out
->cost
.cost
= zero_cost (speed
);
2747 alg_out
->cost
.latency
= zero_cost (speed
);
2748 alg_out
->op
[0] = alg_zero
;
2753 /* We'll be needing a couple extra algorithm structures now. */
2755 alg_in
= XALLOCA (struct algorithm
);
2756 best_alg
= XALLOCA (struct algorithm
);
2757 best_cost
= *cost_limit
;
2759 /* Compute the hash index. */
2760 hash_index
= (t
^ (unsigned int) mode
^ (speed
* 256)) % NUM_ALG_HASH_ENTRIES
;
2762 /* See if we already know what to do for T. */
2763 entry_ptr
= alg_hash_entry_ptr (hash_index
);
2764 if (entry_ptr
->t
== t
2765 && entry_ptr
->mode
== mode
2766 && entry_ptr
->speed
== speed
2767 && entry_ptr
->alg
!= alg_unknown
)
2769 cache_alg
= entry_ptr
->alg
;
2771 if (cache_alg
== alg_impossible
)
2773 /* The cache tells us that it's impossible to synthesize
2774 multiplication by T within entry_ptr->cost. */
2775 if (!CHEAPER_MULT_COST (&entry_ptr
->cost
, cost_limit
))
2776 /* COST_LIMIT is at least as restrictive as the one
2777 recorded in the hash table, in which case we have no
2778 hope of synthesizing a multiplication. Just
2782 /* If we get here, COST_LIMIT is less restrictive than the
2783 one recorded in the hash table, so we may be able to
2784 synthesize a multiplication. Proceed as if we didn't
2785 have the cache entry. */
2789 if (CHEAPER_MULT_COST (cost_limit
, &entry_ptr
->cost
))
2790 /* The cached algorithm shows that this multiplication
2791 requires more cost than COST_LIMIT. Just return. This
2792 way, we don't clobber this cache entry with
2793 alg_impossible but retain useful information. */
2805 goto do_alg_addsub_t_m2
;
2807 case alg_add_factor
:
2808 case alg_sub_factor
:
2809 goto do_alg_addsub_factor
;
2812 goto do_alg_add_t2_m
;
2815 goto do_alg_sub_t2_m
;
2823 /* If we have a group of zero bits at the low-order part of T, try
2824 multiplying by the remaining bits and then doing a shift. */
2829 m
= ctz_or_zero (t
); /* m = number of low zero bits */
2833 /* The function expand_shift will choose between a shift and
2834 a sequence of additions, so the observed cost is given as
2835 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2836 op_cost
= m
* add_cost (speed
, mode
);
2837 if (shift_cost (speed
, mode
, m
) < op_cost
)
2838 op_cost
= shift_cost (speed
, mode
, m
);
2839 new_limit
.cost
= best_cost
.cost
- op_cost
;
2840 new_limit
.latency
= best_cost
.latency
- op_cost
;
2841 synth_mult (alg_in
, q
, &new_limit
, mode
);
2843 alg_in
->cost
.cost
+= op_cost
;
2844 alg_in
->cost
.latency
+= op_cost
;
2845 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2847 best_cost
= alg_in
->cost
;
2848 std::swap (alg_in
, best_alg
);
2849 best_alg
->log
[best_alg
->ops
] = m
;
2850 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2853 /* See if treating ORIG_T as a signed number yields a better
2854 sequence. Try this sequence only for a negative ORIG_T
2855 as it would be useless for a non-negative ORIG_T. */
2856 if ((HOST_WIDE_INT
) orig_t
< 0)
2858 /* Shift ORIG_T as follows because a right shift of a
2859 negative-valued signed type is implementation
2861 q
= ~(~orig_t
>> m
);
2862 /* The function expand_shift will choose between a shift
2863 and a sequence of additions, so the observed cost is
2864 given as MIN (m * add_cost(speed, mode),
2865 shift_cost(speed, mode, m)). */
2866 op_cost
= m
* add_cost (speed
, mode
);
2867 if (shift_cost (speed
, mode
, m
) < op_cost
)
2868 op_cost
= shift_cost (speed
, mode
, m
);
2869 new_limit
.cost
= best_cost
.cost
- op_cost
;
2870 new_limit
.latency
= best_cost
.latency
- op_cost
;
2871 synth_mult (alg_in
, q
, &new_limit
, mode
);
2873 alg_in
->cost
.cost
+= op_cost
;
2874 alg_in
->cost
.latency
+= op_cost
;
2875 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2877 best_cost
= alg_in
->cost
;
2878 std::swap (alg_in
, best_alg
);
2879 best_alg
->log
[best_alg
->ops
] = m
;
2880 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2888 /* If we have an odd number, add or subtract one. */
2891 unsigned HOST_WIDE_INT w
;
2894 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2896 /* If T was -1, then W will be zero after the loop. This is another
2897 case where T ends with ...111. Handling this with (T + 1) and
2898 subtract 1 produces slightly better code and results in algorithm
2899 selection much faster than treating it like the ...0111 case
2903 /* Reject the case where t is 3.
2904 Thus we prefer addition in that case. */
2907 /* T ends with ...111. Multiply by (T + 1) and subtract T. */
2909 op_cost
= add_cost (speed
, mode
);
2910 new_limit
.cost
= best_cost
.cost
- op_cost
;
2911 new_limit
.latency
= best_cost
.latency
- op_cost
;
2912 synth_mult (alg_in
, t
+ 1, &new_limit
, mode
);
2914 alg_in
->cost
.cost
+= op_cost
;
2915 alg_in
->cost
.latency
+= op_cost
;
2916 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2918 best_cost
= alg_in
->cost
;
2919 std::swap (alg_in
, best_alg
);
2920 best_alg
->log
[best_alg
->ops
] = 0;
2921 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2926 /* T ends with ...01 or ...011. Multiply by (T - 1) and add T. */
2928 op_cost
= add_cost (speed
, mode
);
2929 new_limit
.cost
= best_cost
.cost
- op_cost
;
2930 new_limit
.latency
= best_cost
.latency
- op_cost
;
2931 synth_mult (alg_in
, t
- 1, &new_limit
, mode
);
2933 alg_in
->cost
.cost
+= op_cost
;
2934 alg_in
->cost
.latency
+= op_cost
;
2935 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2937 best_cost
= alg_in
->cost
;
2938 std::swap (alg_in
, best_alg
);
2939 best_alg
->log
[best_alg
->ops
] = 0;
2940 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2944 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2945 quickly with a - a * n for some appropriate constant n. */
2946 m
= exact_log2 (-orig_t
+ 1);
2947 if (m
>= 0 && m
< maxm
)
2949 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2950 /* If the target has a cheap shift-and-subtract insn use
2951 that in preference to a shift insn followed by a sub insn.
2952 Assume that the shift-and-sub is "atomic" with a latency
2953 equal to it's cost, otherwise assume that on superscalar
2954 hardware the shift may be executed concurrently with the
2955 earlier steps in the algorithm. */
2956 if (shiftsub1_cost (speed
, mode
, m
) <= op_cost
)
2958 op_cost
= shiftsub1_cost (speed
, mode
, m
);
2959 op_latency
= op_cost
;
2962 op_latency
= add_cost (speed
, mode
);
2964 new_limit
.cost
= best_cost
.cost
- op_cost
;
2965 new_limit
.latency
= best_cost
.latency
- op_latency
;
2966 synth_mult (alg_in
, (unsigned HOST_WIDE_INT
) (-orig_t
+ 1) >> m
,
2969 alg_in
->cost
.cost
+= op_cost
;
2970 alg_in
->cost
.latency
+= op_latency
;
2971 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2973 best_cost
= alg_in
->cost
;
2974 std::swap (alg_in
, best_alg
);
2975 best_alg
->log
[best_alg
->ops
] = m
;
2976 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2984 /* Look for factors of t of the form
2985 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2986 If we find such a factor, we can multiply by t using an algorithm that
2987 multiplies by q, shift the result by m and add/subtract it to itself.
2989 We search for large factors first and loop down, even if large factors
2990 are less probable than small; if we find a large factor we will find a
2991 good sequence quickly, and therefore be able to prune (by decreasing
2992 COST_LIMIT) the search. */
2994 do_alg_addsub_factor
:
2995 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2997 unsigned HOST_WIDE_INT d
;
2999 d
= (HOST_WIDE_INT_1U
<< m
) + 1;
3000 if (t
% d
== 0 && t
> d
&& m
< maxm
3001 && (!cache_hit
|| cache_alg
== alg_add_factor
))
3003 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
3004 if (shiftadd_cost (speed
, mode
, m
) <= op_cost
)
3005 op_cost
= shiftadd_cost (speed
, mode
, m
);
3007 op_latency
= op_cost
;
3010 new_limit
.cost
= best_cost
.cost
- op_cost
;
3011 new_limit
.latency
= best_cost
.latency
- op_latency
;
3012 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
3014 alg_in
->cost
.cost
+= op_cost
;
3015 alg_in
->cost
.latency
+= op_latency
;
3016 if (alg_in
->cost
.latency
< op_cost
)
3017 alg_in
->cost
.latency
= op_cost
;
3018 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
3020 best_cost
= alg_in
->cost
;
3021 std::swap (alg_in
, best_alg
);
3022 best_alg
->log
[best_alg
->ops
] = m
;
3023 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
3025 /* Other factors will have been taken care of in the recursion. */
3029 d
= (HOST_WIDE_INT_1U
<< m
) - 1;
3030 if (t
% d
== 0 && t
> d
&& m
< maxm
3031 && (!cache_hit
|| cache_alg
== alg_sub_factor
))
3033 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
3034 if (shiftsub0_cost (speed
, mode
, m
) <= op_cost
)
3035 op_cost
= shiftsub0_cost (speed
, mode
, m
);
3037 op_latency
= op_cost
;
3039 new_limit
.cost
= best_cost
.cost
- op_cost
;
3040 new_limit
.latency
= best_cost
.latency
- op_latency
;
3041 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
3043 alg_in
->cost
.cost
+= op_cost
;
3044 alg_in
->cost
.latency
+= op_latency
;
3045 if (alg_in
->cost
.latency
< op_cost
)
3046 alg_in
->cost
.latency
= op_cost
;
3047 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
3049 best_cost
= alg_in
->cost
;
3050 std::swap (alg_in
, best_alg
);
3051 best_alg
->log
[best_alg
->ops
] = m
;
3052 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
3060 /* Try shift-and-add (load effective address) instructions,
3061 i.e. do a*3, a*5, a*9. */
3069 op_cost
= shiftadd_cost (speed
, mode
, m
);
3070 new_limit
.cost
= best_cost
.cost
- op_cost
;
3071 new_limit
.latency
= best_cost
.latency
- op_cost
;
3072 synth_mult (alg_in
, (t
- 1) >> m
, &new_limit
, mode
);
3074 alg_in
->cost
.cost
+= op_cost
;
3075 alg_in
->cost
.latency
+= op_cost
;
3076 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
3078 best_cost
= alg_in
->cost
;
3079 std::swap (alg_in
, best_alg
);
3080 best_alg
->log
[best_alg
->ops
] = m
;
3081 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
3092 op_cost
= shiftsub0_cost (speed
, mode
, m
);
3093 new_limit
.cost
= best_cost
.cost
- op_cost
;
3094 new_limit
.latency
= best_cost
.latency
- op_cost
;
3095 synth_mult (alg_in
, (t
+ 1) >> m
, &new_limit
, mode
);
3097 alg_in
->cost
.cost
+= op_cost
;
3098 alg_in
->cost
.latency
+= op_cost
;
3099 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
3101 best_cost
= alg_in
->cost
;
3102 std::swap (alg_in
, best_alg
);
3103 best_alg
->log
[best_alg
->ops
] = m
;
3104 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
3112 /* If best_cost has not decreased, we have not found any algorithm. */
3113 if (!CHEAPER_MULT_COST (&best_cost
, cost_limit
))
3115 /* We failed to find an algorithm. Record alg_impossible for
3116 this case (that is, <T, MODE, COST_LIMIT>) so that next time
3117 we are asked to find an algorithm for T within the same or
3118 lower COST_LIMIT, we can immediately return to the
3121 entry_ptr
->mode
= mode
;
3122 entry_ptr
->speed
= speed
;
3123 entry_ptr
->alg
= alg_impossible
;
3124 entry_ptr
->cost
= *cost_limit
;
3128 /* Cache the result. */
3132 entry_ptr
->mode
= mode
;
3133 entry_ptr
->speed
= speed
;
3134 entry_ptr
->alg
= best_alg
->op
[best_alg
->ops
];
3135 entry_ptr
->cost
.cost
= best_cost
.cost
;
3136 entry_ptr
->cost
.latency
= best_cost
.latency
;
3139 /* If we are getting a too long sequence for `struct algorithm'
3140 to record, make this search fail. */
3141 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
3144 /* Copy the algorithm from temporary space to the space at alg_out.
3145 We avoid using structure assignment because the majority of
3146 best_alg is normally undefined, and this is a critical function. */
3147 alg_out
->ops
= best_alg
->ops
+ 1;
3148 alg_out
->cost
= best_cost
;
3149 memcpy (alg_out
->op
, best_alg
->op
,
3150 alg_out
->ops
* sizeof *alg_out
->op
);
3151 memcpy (alg_out
->log
, best_alg
->log
,
3152 alg_out
->ops
* sizeof *alg_out
->log
);
3155 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
3156 Try three variations:
3158 - a shift/add sequence based on VAL itself
3159 - a shift/add sequence based on -VAL, followed by a negation
3160 - a shift/add sequence based on VAL - 1, followed by an addition.
3162 Return true if the cheapest of these cost less than MULT_COST,
3163 describing the algorithm in *ALG and final fixup in *VARIANT. */
3166 choose_mult_variant (machine_mode mode
, HOST_WIDE_INT val
,
3167 struct algorithm
*alg
, enum mult_variant
*variant
,
3170 struct algorithm alg2
;
3171 struct mult_cost limit
;
3173 bool speed
= optimize_insn_for_speed_p ();
3175 /* Fail quickly for impossible bounds. */
3179 /* Ensure that mult_cost provides a reasonable upper bound.
3180 Any constant multiplication can be performed with less
3181 than 2 * bits additions. */
3182 op_cost
= 2 * GET_MODE_UNIT_BITSIZE (mode
) * add_cost (speed
, mode
);
3183 if (mult_cost
> op_cost
)
3184 mult_cost
= op_cost
;
3186 *variant
= basic_variant
;
3187 limit
.cost
= mult_cost
;
3188 limit
.latency
= mult_cost
;
3189 synth_mult (alg
, val
, &limit
, mode
);
3191 /* This works only if the inverted value actually fits in an
3193 if (HOST_BITS_PER_INT
>= GET_MODE_UNIT_BITSIZE (mode
))
3195 op_cost
= neg_cost (speed
, mode
);
3196 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
3198 limit
.cost
= alg
->cost
.cost
- op_cost
;
3199 limit
.latency
= alg
->cost
.latency
- op_cost
;
3203 limit
.cost
= mult_cost
- op_cost
;
3204 limit
.latency
= mult_cost
- op_cost
;
3207 synth_mult (&alg2
, -val
, &limit
, mode
);
3208 alg2
.cost
.cost
+= op_cost
;
3209 alg2
.cost
.latency
+= op_cost
;
3210 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
3211 *alg
= alg2
, *variant
= negate_variant
;
3214 /* This proves very useful for division-by-constant. */
3215 op_cost
= add_cost (speed
, mode
);
3216 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
3218 limit
.cost
= alg
->cost
.cost
- op_cost
;
3219 limit
.latency
= alg
->cost
.latency
- op_cost
;
3223 limit
.cost
= mult_cost
- op_cost
;
3224 limit
.latency
= mult_cost
- op_cost
;
3227 synth_mult (&alg2
, val
- 1, &limit
, mode
);
3228 alg2
.cost
.cost
+= op_cost
;
3229 alg2
.cost
.latency
+= op_cost
;
3230 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
3231 *alg
= alg2
, *variant
= add_variant
;
3233 return MULT_COST_LESS (&alg
->cost
, mult_cost
);
3236 /* A subroutine of expand_mult, used for constant multiplications.
3237 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
3238 convenient. Use the shift/add sequence described by ALG and apply
3239 the final fixup specified by VARIANT. */
3242 expand_mult_const (machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
3243 rtx target
, const struct algorithm
*alg
,
3244 enum mult_variant variant
)
3246 unsigned HOST_WIDE_INT val_so_far
;
3252 /* Avoid referencing memory over and over and invalid sharing
3254 op0
= force_reg (mode
, op0
);
3256 /* ACCUM starts out either as OP0 or as a zero, depending on
3257 the first operation. */
3259 if (alg
->op
[0] == alg_zero
)
3261 accum
= copy_to_mode_reg (mode
, CONST0_RTX (mode
));
3264 else if (alg
->op
[0] == alg_m
)
3266 accum
= copy_to_mode_reg (mode
, op0
);
3272 for (opno
= 1; opno
< alg
->ops
; opno
++)
3274 int log
= alg
->log
[opno
];
3275 rtx shift_subtarget
= optimize
? 0 : accum
;
3277 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
3280 rtx accum_target
= optimize
? 0 : accum
;
3283 switch (alg
->op
[opno
])
3286 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
3287 /* REG_EQUAL note will be attached to the following insn. */
3288 emit_move_insn (accum
, tem
);
3293 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
3294 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
3295 add_target
? add_target
: accum_target
);
3296 val_so_far
+= HOST_WIDE_INT_1U
<< log
;
3300 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
3301 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
3302 add_target
? add_target
: accum_target
);
3303 val_so_far
-= HOST_WIDE_INT_1U
<< log
;
3307 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
3308 log
, shift_subtarget
, 0);
3309 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
3310 add_target
? add_target
: accum_target
);
3311 val_so_far
= (val_so_far
<< log
) + 1;
3315 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
3316 log
, shift_subtarget
, 0);
3317 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
3318 add_target
? add_target
: accum_target
);
3319 val_so_far
= (val_so_far
<< log
) - 1;
3322 case alg_add_factor
:
3323 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
3324 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
3325 add_target
? add_target
: accum_target
);
3326 val_so_far
+= val_so_far
<< log
;
3329 case alg_sub_factor
:
3330 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
3331 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
3333 ? add_target
: (optimize
? 0 : tem
)));
3334 val_so_far
= (val_so_far
<< log
) - val_so_far
;
3341 if (SCALAR_INT_MODE_P (mode
))
3343 /* Write a REG_EQUAL note on the last insn so that we can cse
3344 multiplication sequences. Note that if ACCUM is a SUBREG,
3345 we've set the inner register and must properly indicate that. */
3346 tem
= op0
, nmode
= mode
;
3347 accum_inner
= accum
;
3348 if (GET_CODE (accum
) == SUBREG
)
3350 accum_inner
= SUBREG_REG (accum
);
3351 nmode
= GET_MODE (accum_inner
);
3352 tem
= gen_lowpart (nmode
, op0
);
3355 insn
= get_last_insn ();
3356 set_dst_reg_note (insn
, REG_EQUAL
,
3357 gen_rtx_MULT (nmode
, tem
,
3358 gen_int_mode (val_so_far
, nmode
)),
3363 if (variant
== negate_variant
)
3365 val_so_far
= -val_so_far
;
3366 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
3368 else if (variant
== add_variant
)
3370 val_so_far
= val_so_far
+ 1;
3371 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
3374 /* Compare only the bits of val and val_so_far that are significant
3375 in the result mode, to avoid sign-/zero-extension confusion. */
3376 nmode
= GET_MODE_INNER (mode
);
3377 val
&= GET_MODE_MASK (nmode
);
3378 val_so_far
&= GET_MODE_MASK (nmode
);
3379 gcc_assert (val
== (HOST_WIDE_INT
) val_so_far
);
3384 /* Perform a multiplication and return an rtx for the result.
3385 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3386 TARGET is a suggestion for where to store the result (an rtx).
3388 We check specially for a constant integer as OP1.
3389 If you want this check for OP0 as well, then before calling
3390 you should swap the two operands if OP0 would be constant. */
3393 expand_mult (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3394 int unsignedp
, bool no_libcall
)
3396 enum mult_variant variant
;
3397 struct algorithm algorithm
;
3400 bool speed
= optimize_insn_for_speed_p ();
3401 bool do_trapv
= flag_trapv
&& SCALAR_INT_MODE_P (mode
) && !unsignedp
;
3403 if (CONSTANT_P (op0
))
3404 std::swap (op0
, op1
);
3406 /* For vectors, there are several simplifications that can be made if
3407 all elements of the vector constant are identical. */
3408 scalar_op1
= unwrap_const_vec_duplicate (op1
);
3410 if (INTEGRAL_MODE_P (mode
))
3413 HOST_WIDE_INT coeff
;
3417 if (op1
== CONST0_RTX (mode
))
3419 if (op1
== CONST1_RTX (mode
))
3421 if (op1
== CONSTM1_RTX (mode
))
3422 return expand_unop (mode
, do_trapv
? negv_optab
: neg_optab
,
3428 /* If mode is integer vector mode, check if the backend supports
3429 vector lshift (by scalar or vector) at all. If not, we can't use
3430 synthetized multiply. */
3431 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
3432 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
3433 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
)
3436 /* These are the operations that are potentially turned into
3437 a sequence of shifts and additions. */
3438 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
3440 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3441 less than or equal in size to `unsigned int' this doesn't matter.
3442 If the mode is larger than `unsigned int', then synth_mult works
3443 only if the constant value exactly fits in an `unsigned int' without
3444 any truncation. This means that multiplying by negative values does
3445 not work; results are off by 2^32 on a 32 bit machine. */
3446 if (CONST_INT_P (scalar_op1
))
3448 coeff
= INTVAL (scalar_op1
);
3451 #if TARGET_SUPPORTS_WIDE_INT
3452 else if (CONST_WIDE_INT_P (scalar_op1
))
3454 else if (CONST_DOUBLE_AS_INT_P (scalar_op1
))
3457 int shift
= wi::exact_log2 (rtx_mode_t (scalar_op1
, mode
));
3458 /* Perfect power of 2 (other than 1, which is handled above). */
3460 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3461 shift
, target
, unsignedp
);
3468 /* We used to test optimize here, on the grounds that it's better to
3469 produce a smaller program when -O is not used. But this causes
3470 such a terrible slowdown sometimes that it seems better to always
3473 /* Special case powers of two. */
3474 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
)
3475 && !(is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
))
3476 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3477 floor_log2 (coeff
), target
, unsignedp
);
3479 fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3481 /* Attempt to handle multiplication of DImode values by negative
3482 coefficients, by performing the multiplication by a positive
3483 multiplier and then inverting the result. */
3484 if (is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
)
3486 /* Its safe to use -coeff even for INT_MIN, as the
3487 result is interpreted as an unsigned coefficient.
3488 Exclude cost of op0 from max_cost to match the cost
3489 calculation of the synth_mult. */
3490 coeff
= -(unsigned HOST_WIDE_INT
) coeff
;
3491 max_cost
= (set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
),
3493 - neg_cost (speed
, mode
));
3497 /* Special case powers of two. */
3498 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3500 rtx temp
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
3501 floor_log2 (coeff
), target
, unsignedp
);
3502 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3505 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3508 rtx temp
= expand_mult_const (mode
, op0
, coeff
, NULL_RTX
,
3509 &algorithm
, variant
);
3510 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3515 /* Exclude cost of op0 from max_cost to match the cost
3516 calculation of the synth_mult. */
3517 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), mode
, speed
);
3518 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3519 return expand_mult_const (mode
, op0
, coeff
, target
,
3520 &algorithm
, variant
);
3524 /* Expand x*2.0 as x+x. */
3525 if (CONST_DOUBLE_AS_FLOAT_P (scalar_op1
)
3526 && real_equal (CONST_DOUBLE_REAL_VALUE (scalar_op1
), &dconst2
))
3528 op0
= force_reg (GET_MODE (op0
), op0
);
3529 return expand_binop (mode
, add_optab
, op0
, op0
,
3531 no_libcall
? OPTAB_WIDEN
: OPTAB_LIB_WIDEN
);
3534 /* This used to use umul_optab if unsigned, but for non-widening multiply
3535 there is no difference between signed and unsigned. */
3536 op0
= expand_binop (mode
, do_trapv
? smulv_optab
: smul_optab
,
3537 op0
, op1
, target
, unsignedp
,
3538 no_libcall
? OPTAB_WIDEN
: OPTAB_LIB_WIDEN
);
3539 gcc_assert (op0
|| no_libcall
);
3543 /* Return a cost estimate for multiplying a register by the given
3544 COEFFicient in the given MODE and SPEED. */
3547 mult_by_coeff_cost (HOST_WIDE_INT coeff
, machine_mode mode
, bool speed
)
3550 struct algorithm algorithm
;
3551 enum mult_variant variant
;
3553 rtx fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3554 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, fake_reg
),
3556 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3557 return algorithm
.cost
.cost
;
3562 /* Perform a widening multiplication and return an rtx for the result.
3563 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3564 TARGET is a suggestion for where to store the result (an rtx).
3565 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3566 or smul_widen_optab.
3568 We check specially for a constant integer as OP1, comparing the
3569 cost of a widening multiply against the cost of a sequence of shifts
3573 expand_widening_mult (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3574 int unsignedp
, optab this_optab
)
3576 bool speed
= optimize_insn_for_speed_p ();
3579 if (CONST_INT_P (op1
)
3580 && GET_MODE (op0
) != VOIDmode
3581 && (cop1
= convert_modes (mode
, GET_MODE (op0
), op1
,
3582 this_optab
== umul_widen_optab
))
3583 && CONST_INT_P (cop1
)
3584 && (INTVAL (cop1
) >= 0
3585 || HWI_COMPUTABLE_MODE_P (mode
)))
3587 HOST_WIDE_INT coeff
= INTVAL (cop1
);
3589 enum mult_variant variant
;
3590 struct algorithm algorithm
;
3593 return CONST0_RTX (mode
);
3595 /* Special case powers of two. */
3596 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3598 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3599 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3600 floor_log2 (coeff
), target
, unsignedp
);
3603 /* Exclude cost of op0 from max_cost to match the cost
3604 calculation of the synth_mult. */
3605 max_cost
= mul_widen_cost (speed
, mode
);
3606 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3609 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3610 return expand_mult_const (mode
, op0
, coeff
, target
,
3611 &algorithm
, variant
);
3614 return expand_binop (mode
, this_optab
, op0
, op1
, target
,
3615 unsignedp
, OPTAB_LIB_WIDEN
);
3618 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3619 replace division by D, and put the least significant N bits of the result
3620 in *MULTIPLIER_PTR and return the most significant bit.
3622 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3623 needed precision is in PRECISION (should be <= N).
3625 PRECISION should be as small as possible so this function can choose
3626 multiplier more freely.
3628 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3629 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3631 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3632 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3634 unsigned HOST_WIDE_INT
3635 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
3636 unsigned HOST_WIDE_INT
*multiplier_ptr
,
3637 int *post_shift_ptr
, int *lgup_ptr
)
3639 int lgup
, post_shift
;
3642 /* lgup = ceil(log2(divisor)); */
3643 lgup
= ceil_log2 (d
);
3645 gcc_assert (lgup
<= n
);
3648 pow2
= n
+ lgup
- precision
;
3650 /* mlow = 2^(N + lgup)/d */
3651 wide_int val
= wi::set_bit_in_zero (pow
, HOST_BITS_PER_DOUBLE_INT
);
3652 wide_int mlow
= wi::udiv_trunc (val
, d
);
3654 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3655 val
|= wi::set_bit_in_zero (pow2
, HOST_BITS_PER_DOUBLE_INT
);
3656 wide_int mhigh
= wi::udiv_trunc (val
, d
);
3658 /* If precision == N, then mlow, mhigh exceed 2^N
3659 (but they do not exceed 2^(N+1)). */
3661 /* Reduce to lowest terms. */
3662 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
3664 unsigned HOST_WIDE_INT ml_lo
= wi::extract_uhwi (mlow
, 1,
3665 HOST_BITS_PER_WIDE_INT
);
3666 unsigned HOST_WIDE_INT mh_lo
= wi::extract_uhwi (mhigh
, 1,
3667 HOST_BITS_PER_WIDE_INT
);
3671 mlow
= wi::uhwi (ml_lo
, HOST_BITS_PER_DOUBLE_INT
);
3672 mhigh
= wi::uhwi (mh_lo
, HOST_BITS_PER_DOUBLE_INT
);
3675 *post_shift_ptr
= post_shift
;
3677 if (n
< HOST_BITS_PER_WIDE_INT
)
3679 unsigned HOST_WIDE_INT mask
= (HOST_WIDE_INT_1U
<< n
) - 1;
3680 *multiplier_ptr
= mhigh
.to_uhwi () & mask
;
3681 return mhigh
.to_uhwi () > mask
;
3685 *multiplier_ptr
= mhigh
.to_uhwi ();
3686 return wi::extract_uhwi (mhigh
, HOST_BITS_PER_WIDE_INT
, 1);
3690 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3691 congruent to 1 (mod 2**N). */
3693 static unsigned HOST_WIDE_INT
3694 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
3696 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3698 /* The algorithm notes that the choice y = x satisfies
3699 x*y == 1 mod 2^3, since x is assumed odd.
3700 Each iteration doubles the number of bits of significance in y. */
3702 unsigned HOST_WIDE_INT mask
;
3703 unsigned HOST_WIDE_INT y
= x
;
3706 mask
= (n
== HOST_BITS_PER_WIDE_INT
3708 : (HOST_WIDE_INT_1U
<< n
) - 1);
3712 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
3718 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3719 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3720 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3721 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3724 The result is put in TARGET if that is convenient.
3726 MODE is the mode of operation. */
3729 expand_mult_highpart_adjust (scalar_int_mode mode
, rtx adj_operand
, rtx op0
,
3730 rtx op1
, rtx target
, int unsignedp
)
3733 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
3735 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3736 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3737 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
3739 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3742 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
3743 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3744 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
3745 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3751 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3754 extract_high_half (scalar_int_mode mode
, rtx op
)
3756 if (mode
== word_mode
)
3757 return gen_highpart (mode
, op
);
3759 scalar_int_mode wider_mode
= GET_MODE_WIDER_MODE (mode
).require ();
3761 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
3762 GET_MODE_BITSIZE (mode
), 0, 1);
3763 return convert_modes (mode
, wider_mode
, op
, 0);
3766 /* Like expmed_mult_highpart, but only consider using a multiplication
3767 optab. OP1 is an rtx for the constant operand. */
3770 expmed_mult_highpart_optab (scalar_int_mode mode
, rtx op0
, rtx op1
,
3771 rtx target
, int unsignedp
, int max_cost
)
3773 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
3777 bool speed
= optimize_insn_for_speed_p ();
3779 scalar_int_mode wider_mode
= GET_MODE_WIDER_MODE (mode
).require ();
3781 size
= GET_MODE_BITSIZE (mode
);
3783 /* Firstly, try using a multiplication insn that only generates the needed
3784 high part of the product, and in the sign flavor of unsignedp. */
3785 if (mul_highpart_cost (speed
, mode
) < max_cost
)
3787 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
3788 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3789 unsignedp
, OPTAB_DIRECT
);
3794 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3795 Need to adjust the result after the multiplication. */
3796 if (size
- 1 < BITS_PER_WORD
3797 && (mul_highpart_cost (speed
, mode
)
3798 + 2 * shift_cost (speed
, mode
, size
-1)
3799 + 4 * add_cost (speed
, mode
) < max_cost
))
3801 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
3802 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3803 unsignedp
, OPTAB_DIRECT
);
3805 /* We used the wrong signedness. Adjust the result. */
3806 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3810 /* Try widening multiplication. */
3811 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
3812 if (convert_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3813 && mul_widen_cost (speed
, wider_mode
) < max_cost
)
3815 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
3816 unsignedp
, OPTAB_WIDEN
);
3818 return extract_high_half (mode
, tem
);
3821 /* Try widening the mode and perform a non-widening multiplication. */
3822 if (optab_handler (smul_optab
, wider_mode
) != CODE_FOR_nothing
3823 && size
- 1 < BITS_PER_WORD
3824 && (mul_cost (speed
, wider_mode
) + shift_cost (speed
, mode
, size
-1)
3830 /* We need to widen the operands, for example to ensure the
3831 constant multiplier is correctly sign or zero extended.
3832 Use a sequence to clean-up any instructions emitted by
3833 the conversions if things don't work out. */
3835 wop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
3836 wop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
3837 tem
= expand_binop (wider_mode
, smul_optab
, wop0
, wop1
, 0,
3838 unsignedp
, OPTAB_WIDEN
);
3839 insns
= get_insns ();
3845 return extract_high_half (mode
, tem
);
3849 /* Try widening multiplication of opposite signedness, and adjust. */
3850 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3851 if (convert_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3852 && size
- 1 < BITS_PER_WORD
3853 && (mul_widen_cost (speed
, wider_mode
)
3854 + 2 * shift_cost (speed
, mode
, size
-1)
3855 + 4 * add_cost (speed
, mode
) < max_cost
))
3857 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3858 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3861 tem
= extract_high_half (mode
, tem
);
3862 /* We used the wrong signedness. Adjust the result. */
3863 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3871 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3872 putting the high half of the result in TARGET if that is convenient,
3873 and return where the result is. If the operation can not be performed,
3876 MODE is the mode of operation and result.
3878 UNSIGNEDP nonzero means unsigned multiply.
3880 MAX_COST is the total allowed cost for the expanded RTL. */
3883 expmed_mult_highpart (scalar_int_mode mode
, rtx op0
, rtx op1
,
3884 rtx target
, int unsignedp
, int max_cost
)
3886 unsigned HOST_WIDE_INT cnst1
;
3888 bool sign_adjust
= false;
3889 enum mult_variant variant
;
3890 struct algorithm alg
;
3892 bool speed
= optimize_insn_for_speed_p ();
3894 /* We can't support modes wider than HOST_BITS_PER_INT. */
3895 gcc_assert (HWI_COMPUTABLE_MODE_P (mode
));
3897 cnst1
= INTVAL (op1
) & GET_MODE_MASK (mode
);
3899 /* We can't optimize modes wider than BITS_PER_WORD.
3900 ??? We might be able to perform double-word arithmetic if
3901 mode == word_mode, however all the cost calculations in
3902 synth_mult etc. assume single-word operations. */
3903 scalar_int_mode wider_mode
= GET_MODE_WIDER_MODE (mode
).require ();
3904 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3905 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3906 unsignedp
, max_cost
);
3908 extra_cost
= shift_cost (speed
, mode
, GET_MODE_BITSIZE (mode
) - 1);
3910 /* Check whether we try to multiply by a negative constant. */
3911 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3914 extra_cost
+= add_cost (speed
, mode
);
3917 /* See whether shift/add multiplication is cheap enough. */
3918 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3919 max_cost
- extra_cost
))
3921 /* See whether the specialized multiplication optabs are
3922 cheaper than the shift/add version. */
3923 tem
= expmed_mult_highpart_optab (mode
, op0
, op1
, target
, unsignedp
,
3924 alg
.cost
.cost
+ extra_cost
);
3928 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3929 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3930 tem
= extract_high_half (mode
, tem
);
3932 /* Adjust result for signedness. */
3934 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3938 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3939 unsignedp
, max_cost
);
3943 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3946 expand_smod_pow2 (scalar_int_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3948 rtx result
, temp
, shift
;
3949 rtx_code_label
*label
;
3951 int prec
= GET_MODE_PRECISION (mode
);
3953 logd
= floor_log2 (d
);
3954 result
= gen_reg_rtx (mode
);
3956 /* Avoid conditional branches when they're expensive. */
3957 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3958 && optimize_insn_for_speed_p ())
3960 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3964 HOST_WIDE_INT masklow
= (HOST_WIDE_INT_1
<< logd
) - 1;
3965 signmask
= force_reg (mode
, signmask
);
3966 shift
= gen_int_shift_amount (mode
, GET_MODE_BITSIZE (mode
) - logd
);
3968 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3969 which instruction sequence to use. If logical right shifts
3970 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3971 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3973 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3974 if (optab_handler (lshr_optab
, mode
) == CODE_FOR_nothing
3975 || (set_src_cost (temp
, mode
, optimize_insn_for_speed_p ())
3976 > COSTS_N_INSNS (2)))
3978 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3979 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3980 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3981 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3982 temp
= expand_binop (mode
, and_optab
, temp
,
3983 gen_int_mode (masklow
, mode
),
3984 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3985 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3986 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3987 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3988 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3992 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3993 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3994 signmask
= force_reg (mode
, signmask
);
3996 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3997 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3998 temp
= expand_binop (mode
, and_optab
, temp
,
3999 gen_int_mode (masklow
, mode
),
4000 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4001 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
4002 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4008 /* Mask contains the mode's signbit and the significant bits of the
4009 modulus. By including the signbit in the operation, many targets
4010 can avoid an explicit compare operation in the following comparison
4012 wide_int mask
= wi::mask (logd
, false, prec
);
4013 mask
= wi::set_bit (mask
, prec
- 1);
4015 temp
= expand_binop (mode
, and_optab
, op0
,
4016 immed_wide_int_const (mask
, mode
),
4017 result
, 1, OPTAB_LIB_WIDEN
);
4019 emit_move_insn (result
, temp
);
4021 label
= gen_label_rtx ();
4022 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
4024 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
4025 0, OPTAB_LIB_WIDEN
);
4027 mask
= wi::mask (logd
, true, prec
);
4028 temp
= expand_binop (mode
, ior_optab
, temp
,
4029 immed_wide_int_const (mask
, mode
),
4030 result
, 1, OPTAB_LIB_WIDEN
);
4031 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
4032 0, OPTAB_LIB_WIDEN
);
4034 emit_move_insn (result
, temp
);
4039 /* Expand signed division of OP0 by a power of two D in mode MODE.
4040 This routine is only called for positive values of D. */
4043 expand_sdiv_pow2 (scalar_int_mode mode
, rtx op0
, HOST_WIDE_INT d
)
4046 rtx_code_label
*label
;
4049 logd
= floor_log2 (d
);
4052 && BRANCH_COST (optimize_insn_for_speed_p (),
4055 temp
= gen_reg_rtx (mode
);
4056 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
4057 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
4058 0, OPTAB_LIB_WIDEN
);
4059 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
4062 if (HAVE_conditional_move
4063 && BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2)
4068 temp2
= copy_to_mode_reg (mode
, op0
);
4069 temp
= expand_binop (mode
, add_optab
, temp2
, gen_int_mode (d
- 1, mode
),
4070 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
4071 temp
= force_reg (mode
, temp
);
4073 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
4074 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
4075 mode
, temp
, temp2
, mode
, 0);
4078 rtx_insn
*seq
= get_insns ();
4081 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, logd
, NULL_RTX
, 0);
4086 if (BRANCH_COST (optimize_insn_for_speed_p (),
4089 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
4091 temp
= gen_reg_rtx (mode
);
4092 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
4093 if (GET_MODE_BITSIZE (mode
) >= BITS_PER_WORD
4094 || shift_cost (optimize_insn_for_speed_p (), mode
, ushift
)
4095 > COSTS_N_INSNS (1))
4096 temp
= expand_binop (mode
, and_optab
, temp
, gen_int_mode (d
- 1, mode
),
4097 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
4099 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
4100 ushift
, NULL_RTX
, 1);
4101 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
4102 0, OPTAB_LIB_WIDEN
);
4103 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
4106 label
= gen_label_rtx ();
4107 temp
= copy_to_mode_reg (mode
, op0
);
4108 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
4109 expand_inc (temp
, gen_int_mode (d
- 1, mode
));
4111 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
4114 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
4115 if that is convenient, and returning where the result is.
4116 You may request either the quotient or the remainder as the result;
4117 specify REM_FLAG nonzero to get the remainder.
4119 CODE is the expression code for which kind of division this is;
4120 it controls how rounding is done. MODE is the machine mode to use.
4121 UNSIGNEDP nonzero means do unsigned division. */
4123 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
4124 and then correct it by or'ing in missing high bits
4125 if result of ANDI is nonzero.
4126 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
4127 This could optimize to a bfexts instruction.
4128 But C doesn't use these operations, so their optimizations are
4130 /* ??? For modulo, we don't actually need the highpart of the first product,
4131 the low part will do nicely. And for small divisors, the second multiply
4132 can also be a low-part only multiply or even be completely left out.
4133 E.g. to calculate the remainder of a division by 3 with a 32 bit
4134 multiply, multiply with 0x55555556 and extract the upper two bits;
4135 the result is exact for inputs up to 0x1fffffff.
4136 The input range can be reduced by using cross-sum rules.
4137 For odd divisors >= 3, the following table gives right shift counts
4138 so that if a number is shifted by an integer multiple of the given
4139 amount, the remainder stays the same:
4140 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
4141 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
4142 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
4143 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
4144 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
4146 Cross-sum rules for even numbers can be derived by leaving as many bits
4147 to the right alone as the divisor has zeros to the right.
4148 E.g. if x is an unsigned 32 bit number:
4149 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
4153 expand_divmod (int rem_flag
, enum tree_code code
, machine_mode mode
,
4154 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
4156 machine_mode compute_mode
;
4158 rtx quotient
= 0, remainder
= 0;
4161 optab optab1
, optab2
;
4162 int op1_is_constant
, op1_is_pow2
= 0;
4163 int max_cost
, extra_cost
;
4164 static HOST_WIDE_INT last_div_const
= 0;
4165 bool speed
= optimize_insn_for_speed_p ();
4167 op1_is_constant
= CONST_INT_P (op1
);
4168 if (op1_is_constant
)
4170 wide_int ext_op1
= rtx_mode_t (op1
, mode
);
4171 op1_is_pow2
= (wi::popcount (ext_op1
) == 1
4173 && wi::popcount (wi::neg (ext_op1
)) == 1));
4177 This is the structure of expand_divmod:
4179 First comes code to fix up the operands so we can perform the operations
4180 correctly and efficiently.
4182 Second comes a switch statement with code specific for each rounding mode.
4183 For some special operands this code emits all RTL for the desired
4184 operation, for other cases, it generates only a quotient and stores it in
4185 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
4186 to indicate that it has not done anything.
4188 Last comes code that finishes the operation. If QUOTIENT is set and
4189 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
4190 QUOTIENT is not set, it is computed using trunc rounding.
4192 We try to generate special code for division and remainder when OP1 is a
4193 constant. If |OP1| = 2**n we can use shifts and some other fast
4194 operations. For other values of OP1, we compute a carefully selected
4195 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
4198 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
4199 half of the product. Different strategies for generating the product are
4200 implemented in expmed_mult_highpart.
4202 If what we actually want is the remainder, we generate that by another
4203 by-constant multiplication and a subtraction. */
4205 /* We shouldn't be called with OP1 == const1_rtx, but some of the
4206 code below will malfunction if we are, so check here and handle
4207 the special case if so. */
4208 if (op1
== const1_rtx
)
4209 return rem_flag
? const0_rtx
: op0
;
4211 /* When dividing by -1, we could get an overflow.
4212 negv_optab can handle overflows. */
4213 if (! unsignedp
&& op1
== constm1_rtx
)
4217 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS (mode
) == MODE_INT
4218 ? negv_optab
: neg_optab
, op0
, target
, 0);
4222 /* Don't use the function value register as a target
4223 since we have to read it as well as write it,
4224 and function-inlining gets confused by this. */
4225 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
4226 /* Don't clobber an operand while doing a multi-step calculation. */
4227 || ((rem_flag
|| op1_is_constant
)
4228 && (reg_mentioned_p (target
, op0
)
4229 || (MEM_P (op0
) && MEM_P (target
))))
4230 || reg_mentioned_p (target
, op1
)
4231 || (MEM_P (op1
) && MEM_P (target
))))
4234 /* Get the mode in which to perform this computation. Normally it will
4235 be MODE, but sometimes we can't do the desired operation in MODE.
4236 If so, pick a wider mode in which we can do the operation. Convert
4237 to that mode at the start to avoid repeated conversions.
4239 First see what operations we need. These depend on the expression
4240 we are evaluating. (We assume that divxx3 insns exist under the
4241 same conditions that modxx3 insns and that these insns don't normally
4242 fail. If these assumptions are not correct, we may generate less
4243 efficient code in some cases.)
4245 Then see if we find a mode in which we can open-code that operation
4246 (either a division, modulus, or shift). Finally, check for the smallest
4247 mode for which we can do the operation with a library call. */
4249 /* We might want to refine this now that we have division-by-constant
4250 optimization. Since expmed_mult_highpart tries so many variants, it is
4251 not straightforward to generalize this. Maybe we should make an array
4252 of possible modes in init_expmed? Save this for GCC 2.7. */
4254 optab1
= (op1_is_pow2
4255 ? (unsignedp
? lshr_optab
: ashr_optab
)
4256 : (unsignedp
? udiv_optab
: sdiv_optab
));
4257 optab2
= (op1_is_pow2
? optab1
4258 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
4260 FOR_EACH_MODE_FROM (compute_mode
, mode
)
4261 if (optab_handler (optab1
, compute_mode
) != CODE_FOR_nothing
4262 || optab_handler (optab2
, compute_mode
) != CODE_FOR_nothing
)
4265 if (compute_mode
== VOIDmode
)
4266 FOR_EACH_MODE_FROM (compute_mode
, mode
)
4267 if (optab_libfunc (optab1
, compute_mode
)
4268 || optab_libfunc (optab2
, compute_mode
))
4271 /* If we still couldn't find a mode, use MODE, but expand_binop will
4273 if (compute_mode
== VOIDmode
)
4274 compute_mode
= mode
;
4276 if (target
&& GET_MODE (target
) == compute_mode
)
4279 tquotient
= gen_reg_rtx (compute_mode
);
4282 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
4283 (mode), and thereby get better code when OP1 is a constant. Do that
4284 later. It will require going over all usages of SIZE below. */
4285 size
= GET_MODE_BITSIZE (mode
);
4288 /* Only deduct something for a REM if the last divide done was
4289 for a different constant. Then set the constant of the last
4291 max_cost
= (unsignedp
4292 ? udiv_cost (speed
, compute_mode
)
4293 : sdiv_cost (speed
, compute_mode
));
4294 if (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
4295 && INTVAL (op1
) == last_div_const
))
4296 max_cost
-= (mul_cost (speed
, compute_mode
)
4297 + add_cost (speed
, compute_mode
));
4299 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
4301 /* Now convert to the best mode to use. */
4302 if (compute_mode
!= mode
)
4304 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
4305 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
4307 /* convert_modes may have placed op1 into a register, so we
4308 must recompute the following. */
4309 op1_is_constant
= CONST_INT_P (op1
);
4310 if (op1_is_constant
)
4312 wide_int ext_op1
= rtx_mode_t (op1
, compute_mode
);
4313 op1_is_pow2
= (wi::popcount (ext_op1
) == 1
4315 && wi::popcount (wi::neg (ext_op1
)) == 1));
4321 /* If one of the operands is a volatile MEM, copy it into a register. */
4323 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
4324 op0
= force_reg (compute_mode
, op0
);
4325 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
4326 op1
= force_reg (compute_mode
, op1
);
4328 /* If we need the remainder or if OP1 is constant, we need to
4329 put OP0 in a register in case it has any queued subexpressions. */
4330 if (rem_flag
|| op1_is_constant
)
4331 op0
= force_reg (compute_mode
, op0
);
4333 last
= get_last_insn ();
4335 /* Promote floor rounding to trunc rounding for unsigned operations. */
4338 if (code
== FLOOR_DIV_EXPR
)
4339 code
= TRUNC_DIV_EXPR
;
4340 if (code
== FLOOR_MOD_EXPR
)
4341 code
= TRUNC_MOD_EXPR
;
4342 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
4343 code
= TRUNC_DIV_EXPR
;
4346 if (op1
!= const0_rtx
)
4349 case TRUNC_MOD_EXPR
:
4350 case TRUNC_DIV_EXPR
:
4351 if (op1_is_constant
)
4353 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (compute_mode
);
4354 int size
= GET_MODE_BITSIZE (int_mode
);
4357 unsigned HOST_WIDE_INT mh
, ml
;
4358 int pre_shift
, post_shift
;
4360 wide_int wd
= rtx_mode_t (op1
, int_mode
);
4361 unsigned HOST_WIDE_INT d
= wd
.to_uhwi ();
4363 if (wi::popcount (wd
) == 1)
4365 pre_shift
= floor_log2 (d
);
4368 unsigned HOST_WIDE_INT mask
4369 = (HOST_WIDE_INT_1U
<< pre_shift
) - 1;
4371 = expand_binop (int_mode
, and_optab
, op0
,
4372 gen_int_mode (mask
, int_mode
),
4376 return gen_lowpart (mode
, remainder
);
4378 quotient
= expand_shift (RSHIFT_EXPR
, int_mode
, op0
,
4379 pre_shift
, tquotient
, 1);
4381 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4383 if (d
>= (HOST_WIDE_INT_1U
<< (size
- 1)))
4385 /* Most significant bit of divisor is set; emit an scc
4387 quotient
= emit_store_flag_force (tquotient
, GEU
, op0
, op1
,
4392 /* Find a suitable multiplier and right shift count
4393 instead of multiplying with D. */
4395 mh
= choose_multiplier (d
, size
, size
,
4396 &ml
, &post_shift
, &dummy
);
4398 /* If the suggested multiplier is more than SIZE bits,
4399 we can do better for even divisors, using an
4400 initial right shift. */
4401 if (mh
!= 0 && (d
& 1) == 0)
4403 pre_shift
= ctz_or_zero (d
);
4404 mh
= choose_multiplier (d
>> pre_shift
, size
,
4406 &ml
, &post_shift
, &dummy
);
4416 if (post_shift
- 1 >= BITS_PER_WORD
)
4420 = (shift_cost (speed
, int_mode
, post_shift
- 1)
4421 + shift_cost (speed
, int_mode
, 1)
4422 + 2 * add_cost (speed
, int_mode
));
4423 t1
= expmed_mult_highpart
4424 (int_mode
, op0
, gen_int_mode (ml
, int_mode
),
4425 NULL_RTX
, 1, max_cost
- extra_cost
);
4428 t2
= force_operand (gen_rtx_MINUS (int_mode
,
4431 t3
= expand_shift (RSHIFT_EXPR
, int_mode
,
4432 t2
, 1, NULL_RTX
, 1);
4433 t4
= force_operand (gen_rtx_PLUS (int_mode
,
4436 quotient
= expand_shift
4437 (RSHIFT_EXPR
, int_mode
, t4
,
4438 post_shift
- 1, tquotient
, 1);
4444 if (pre_shift
>= BITS_PER_WORD
4445 || post_shift
>= BITS_PER_WORD
)
4449 (RSHIFT_EXPR
, int_mode
, op0
,
4450 pre_shift
, NULL_RTX
, 1);
4452 = (shift_cost (speed
, int_mode
, pre_shift
)
4453 + shift_cost (speed
, int_mode
, post_shift
));
4454 t2
= expmed_mult_highpart
4456 gen_int_mode (ml
, int_mode
),
4457 NULL_RTX
, 1, max_cost
- extra_cost
);
4460 quotient
= expand_shift
4461 (RSHIFT_EXPR
, int_mode
, t2
,
4462 post_shift
, tquotient
, 1);
4466 else /* Too wide mode to use tricky code */
4469 insn
= get_last_insn ();
4471 set_dst_reg_note (insn
, REG_EQUAL
,
4472 gen_rtx_UDIV (int_mode
, op0
, op1
),
4475 else /* TRUNC_DIV, signed */
4477 unsigned HOST_WIDE_INT ml
;
4478 int lgup
, post_shift
;
4480 HOST_WIDE_INT d
= INTVAL (op1
);
4481 unsigned HOST_WIDE_INT abs_d
;
4483 /* Since d might be INT_MIN, we have to cast to
4484 unsigned HOST_WIDE_INT before negating to avoid
4485 undefined signed overflow. */
4487 ? (unsigned HOST_WIDE_INT
) d
4488 : - (unsigned HOST_WIDE_INT
) d
);
4490 /* n rem d = n rem -d */
4491 if (rem_flag
&& d
< 0)
4494 op1
= gen_int_mode (abs_d
, int_mode
);
4500 quotient
= expand_unop (int_mode
, neg_optab
, op0
,
4502 else if (size
<= HOST_BITS_PER_WIDE_INT
4503 && abs_d
== HOST_WIDE_INT_1U
<< (size
- 1))
4505 /* This case is not handled correctly below. */
4506 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
4511 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
4512 && (size
<= HOST_BITS_PER_WIDE_INT
|| d
>= 0)
4514 ? smod_pow2_cheap (speed
, int_mode
)
4515 : sdiv_pow2_cheap (speed
, int_mode
))
4516 /* We assume that cheap metric is true if the
4517 optab has an expander for this mode. */
4518 && ((optab_handler ((rem_flag
? smod_optab
4521 != CODE_FOR_nothing
)
4522 || (optab_handler (sdivmod_optab
, int_mode
)
4523 != CODE_FOR_nothing
)))
4525 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
)
4526 && (size
<= HOST_BITS_PER_WIDE_INT
4527 || abs_d
!= (unsigned HOST_WIDE_INT
) d
))
4531 remainder
= expand_smod_pow2 (int_mode
, op0
, d
);
4533 return gen_lowpart (mode
, remainder
);
4536 if (sdiv_pow2_cheap (speed
, int_mode
)
4537 && ((optab_handler (sdiv_optab
, int_mode
)
4538 != CODE_FOR_nothing
)
4539 || (optab_handler (sdivmod_optab
, int_mode
)
4540 != CODE_FOR_nothing
)))
4541 quotient
= expand_divmod (0, TRUNC_DIV_EXPR
,
4543 gen_int_mode (abs_d
,
4547 quotient
= expand_sdiv_pow2 (int_mode
, op0
, abs_d
);
4549 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4550 negate the quotient. */
4553 insn
= get_last_insn ();
4555 && abs_d
< (HOST_WIDE_INT_1U
4556 << (HOST_BITS_PER_WIDE_INT
- 1)))
4557 set_dst_reg_note (insn
, REG_EQUAL
,
4558 gen_rtx_DIV (int_mode
, op0
,
4564 quotient
= expand_unop (int_mode
, neg_optab
,
4565 quotient
, quotient
, 0);
4568 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4570 choose_multiplier (abs_d
, size
, size
- 1,
4571 &ml
, &post_shift
, &lgup
);
4572 if (ml
< HOST_WIDE_INT_1U
<< (size
- 1))
4576 if (post_shift
>= BITS_PER_WORD
4577 || size
- 1 >= BITS_PER_WORD
)
4580 extra_cost
= (shift_cost (speed
, int_mode
, post_shift
)
4581 + shift_cost (speed
, int_mode
, size
- 1)
4582 + add_cost (speed
, int_mode
));
4583 t1
= expmed_mult_highpart
4584 (int_mode
, op0
, gen_int_mode (ml
, int_mode
),
4585 NULL_RTX
, 0, max_cost
- extra_cost
);
4589 (RSHIFT_EXPR
, int_mode
, t1
,
4590 post_shift
, NULL_RTX
, 0);
4592 (RSHIFT_EXPR
, int_mode
, op0
,
4593 size
- 1, NULL_RTX
, 0);
4596 = force_operand (gen_rtx_MINUS (int_mode
, t3
, t2
),
4600 = force_operand (gen_rtx_MINUS (int_mode
, t2
, t3
),
4607 if (post_shift
>= BITS_PER_WORD
4608 || size
- 1 >= BITS_PER_WORD
)
4611 ml
|= HOST_WIDE_INT_M1U
<< (size
- 1);
4612 mlr
= gen_int_mode (ml
, int_mode
);
4613 extra_cost
= (shift_cost (speed
, int_mode
, post_shift
)
4614 + shift_cost (speed
, int_mode
, size
- 1)
4615 + 2 * add_cost (speed
, int_mode
));
4616 t1
= expmed_mult_highpart (int_mode
, op0
, mlr
,
4618 max_cost
- extra_cost
);
4621 t2
= force_operand (gen_rtx_PLUS (int_mode
, t1
, op0
),
4624 (RSHIFT_EXPR
, int_mode
, t2
,
4625 post_shift
, NULL_RTX
, 0);
4627 (RSHIFT_EXPR
, int_mode
, op0
,
4628 size
- 1, NULL_RTX
, 0);
4631 = force_operand (gen_rtx_MINUS (int_mode
, t4
, t3
),
4635 = force_operand (gen_rtx_MINUS (int_mode
, t3
, t4
),
4639 else /* Too wide mode to use tricky code */
4642 insn
= get_last_insn ();
4644 set_dst_reg_note (insn
, REG_EQUAL
,
4645 gen_rtx_DIV (int_mode
, op0
, op1
),
4651 delete_insns_since (last
);
4654 case FLOOR_DIV_EXPR
:
4655 case FLOOR_MOD_EXPR
:
4656 /* We will come here only for signed operations. */
4657 if (op1_is_constant
&& HWI_COMPUTABLE_MODE_P (compute_mode
))
4659 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (compute_mode
);
4660 int size
= GET_MODE_BITSIZE (int_mode
);
4661 unsigned HOST_WIDE_INT mh
, ml
;
4662 int pre_shift
, lgup
, post_shift
;
4663 HOST_WIDE_INT d
= INTVAL (op1
);
4667 /* We could just as easily deal with negative constants here,
4668 but it does not seem worth the trouble for GCC 2.6. */
4669 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4671 pre_shift
= floor_log2 (d
);
4674 unsigned HOST_WIDE_INT mask
4675 = (HOST_WIDE_INT_1U
<< pre_shift
) - 1;
4676 remainder
= expand_binop
4677 (int_mode
, and_optab
, op0
,
4678 gen_int_mode (mask
, int_mode
),
4679 remainder
, 0, OPTAB_LIB_WIDEN
);
4681 return gen_lowpart (mode
, remainder
);
4683 quotient
= expand_shift
4684 (RSHIFT_EXPR
, int_mode
, op0
,
4685 pre_shift
, tquotient
, 0);
4691 mh
= choose_multiplier (d
, size
, size
- 1,
4692 &ml
, &post_shift
, &lgup
);
4695 if (post_shift
< BITS_PER_WORD
4696 && size
- 1 < BITS_PER_WORD
)
4699 (RSHIFT_EXPR
, int_mode
, op0
,
4700 size
- 1, NULL_RTX
, 0);
4701 t2
= expand_binop (int_mode
, xor_optab
, op0
, t1
,
4702 NULL_RTX
, 0, OPTAB_WIDEN
);
4703 extra_cost
= (shift_cost (speed
, int_mode
, post_shift
)
4704 + shift_cost (speed
, int_mode
, size
- 1)
4705 + 2 * add_cost (speed
, int_mode
));
4706 t3
= expmed_mult_highpart
4707 (int_mode
, t2
, gen_int_mode (ml
, int_mode
),
4708 NULL_RTX
, 1, max_cost
- extra_cost
);
4712 (RSHIFT_EXPR
, int_mode
, t3
,
4713 post_shift
, NULL_RTX
, 1);
4714 quotient
= expand_binop (int_mode
, xor_optab
,
4715 t4
, t1
, tquotient
, 0,
4723 rtx nsign
, t1
, t2
, t3
, t4
;
4724 t1
= force_operand (gen_rtx_PLUS (int_mode
,
4725 op0
, constm1_rtx
), NULL_RTX
);
4726 t2
= expand_binop (int_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
4728 nsign
= expand_shift (RSHIFT_EXPR
, int_mode
, t2
,
4729 size
- 1, NULL_RTX
, 0);
4730 t3
= force_operand (gen_rtx_MINUS (int_mode
, t1
, nsign
),
4732 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, int_mode
, t3
, op1
,
4737 t5
= expand_unop (int_mode
, one_cmpl_optab
, nsign
,
4739 quotient
= force_operand (gen_rtx_PLUS (int_mode
, t4
, t5
),
4747 delete_insns_since (last
);
4749 /* Try using an instruction that produces both the quotient and
4750 remainder, using truncation. We can easily compensate the quotient
4751 or remainder to get floor rounding, once we have the remainder.
4752 Notice that we compute also the final remainder value here,
4753 and return the result right away. */
4754 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4755 target
= gen_reg_rtx (compute_mode
);
4760 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4761 quotient
= gen_reg_rtx (compute_mode
);
4766 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4767 remainder
= gen_reg_rtx (compute_mode
);
4770 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
4771 quotient
, remainder
, 0))
4773 /* This could be computed with a branch-less sequence.
4774 Save that for later. */
4776 rtx_code_label
*label
= gen_label_rtx ();
4777 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
4778 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4779 NULL_RTX
, 0, OPTAB_WIDEN
);
4780 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
4781 expand_dec (quotient
, const1_rtx
);
4782 expand_inc (remainder
, op1
);
4784 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4787 /* No luck with division elimination or divmod. Have to do it
4788 by conditionally adjusting op0 *and* the result. */
4790 rtx_code_label
*label1
, *label2
, *label3
, *label4
, *label5
;
4794 quotient
= gen_reg_rtx (compute_mode
);
4795 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4796 label1
= gen_label_rtx ();
4797 label2
= gen_label_rtx ();
4798 label3
= gen_label_rtx ();
4799 label4
= gen_label_rtx ();
4800 label5
= gen_label_rtx ();
4801 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4802 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
4803 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4804 quotient
, 0, OPTAB_LIB_WIDEN
);
4805 if (tem
!= quotient
)
4806 emit_move_insn (quotient
, tem
);
4807 emit_jump_insn (targetm
.gen_jump (label5
));
4809 emit_label (label1
);
4810 expand_inc (adjusted_op0
, const1_rtx
);
4811 emit_jump_insn (targetm
.gen_jump (label4
));
4813 emit_label (label2
);
4814 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
4815 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4816 quotient
, 0, OPTAB_LIB_WIDEN
);
4817 if (tem
!= quotient
)
4818 emit_move_insn (quotient
, tem
);
4819 emit_jump_insn (targetm
.gen_jump (label5
));
4821 emit_label (label3
);
4822 expand_dec (adjusted_op0
, const1_rtx
);
4823 emit_label (label4
);
4824 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4825 quotient
, 0, OPTAB_LIB_WIDEN
);
4826 if (tem
!= quotient
)
4827 emit_move_insn (quotient
, tem
);
4828 expand_dec (quotient
, const1_rtx
);
4829 emit_label (label5
);
4838 && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4839 && (HWI_COMPUTABLE_MODE_P (compute_mode
)
4840 || INTVAL (op1
) >= 0))
4842 scalar_int_mode int_mode
4843 = as_a
<scalar_int_mode
> (compute_mode
);
4845 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4846 t1
= expand_shift (RSHIFT_EXPR
, int_mode
, op0
,
4847 floor_log2 (d
), tquotient
, 1);
4848 t2
= expand_binop (int_mode
, and_optab
, op0
,
4849 gen_int_mode (d
- 1, int_mode
),
4850 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4851 t3
= gen_reg_rtx (int_mode
);
4852 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
, int_mode
, 1, 1);
4855 rtx_code_label
*lab
;
4856 lab
= gen_label_rtx ();
4857 do_cmp_and_jump (t2
, const0_rtx
, EQ
, int_mode
, lab
);
4858 expand_inc (t1
, const1_rtx
);
4863 quotient
= force_operand (gen_rtx_PLUS (int_mode
, t1
, t3
),
4868 /* Try using an instruction that produces both the quotient and
4869 remainder, using truncation. We can easily compensate the
4870 quotient or remainder to get ceiling rounding, once we have the
4871 remainder. Notice that we compute also the final remainder
4872 value here, and return the result right away. */
4873 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4874 target
= gen_reg_rtx (compute_mode
);
4878 remainder
= (REG_P (target
)
4879 ? target
: gen_reg_rtx (compute_mode
));
4880 quotient
= gen_reg_rtx (compute_mode
);
4884 quotient
= (REG_P (target
)
4885 ? target
: gen_reg_rtx (compute_mode
));
4886 remainder
= gen_reg_rtx (compute_mode
);
4889 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4892 /* This could be computed with a branch-less sequence.
4893 Save that for later. */
4894 rtx_code_label
*label
= gen_label_rtx ();
4895 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4896 compute_mode
, label
);
4897 expand_inc (quotient
, const1_rtx
);
4898 expand_dec (remainder
, op1
);
4900 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4903 /* No luck with division elimination or divmod. Have to do it
4904 by conditionally adjusting op0 *and* the result. */
4906 rtx_code_label
*label1
, *label2
;
4907 rtx adjusted_op0
, tem
;
4909 quotient
= gen_reg_rtx (compute_mode
);
4910 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4911 label1
= gen_label_rtx ();
4912 label2
= gen_label_rtx ();
4913 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4914 compute_mode
, label1
);
4915 emit_move_insn (quotient
, const0_rtx
);
4916 emit_jump_insn (targetm
.gen_jump (label2
));
4918 emit_label (label1
);
4919 expand_dec (adjusted_op0
, const1_rtx
);
4920 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4921 quotient
, 1, OPTAB_LIB_WIDEN
);
4922 if (tem
!= quotient
)
4923 emit_move_insn (quotient
, tem
);
4924 expand_inc (quotient
, const1_rtx
);
4925 emit_label (label2
);
4930 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4931 && INTVAL (op1
) >= 0)
4933 /* This is extremely similar to the code for the unsigned case
4934 above. For 2.7 we should merge these variants, but for
4935 2.6.1 I don't want to touch the code for unsigned since that
4936 get used in C. The signed case will only be used by other
4940 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4941 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4942 floor_log2 (d
), tquotient
, 0);
4943 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4944 gen_int_mode (d
- 1, compute_mode
),
4945 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4946 t3
= gen_reg_rtx (compute_mode
);
4947 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4948 compute_mode
, 1, 1);
4951 rtx_code_label
*lab
;
4952 lab
= gen_label_rtx ();
4953 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4954 expand_inc (t1
, const1_rtx
);
4959 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4965 /* Try using an instruction that produces both the quotient and
4966 remainder, using truncation. We can easily compensate the
4967 quotient or remainder to get ceiling rounding, once we have the
4968 remainder. Notice that we compute also the final remainder
4969 value here, and return the result right away. */
4970 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4971 target
= gen_reg_rtx (compute_mode
);
4974 remainder
= (REG_P (target
)
4975 ? target
: gen_reg_rtx (compute_mode
));
4976 quotient
= gen_reg_rtx (compute_mode
);
4980 quotient
= (REG_P (target
)
4981 ? target
: gen_reg_rtx (compute_mode
));
4982 remainder
= gen_reg_rtx (compute_mode
);
4985 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4988 /* This could be computed with a branch-less sequence.
4989 Save that for later. */
4991 rtx_code_label
*label
= gen_label_rtx ();
4992 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4993 compute_mode
, label
);
4994 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4995 NULL_RTX
, 0, OPTAB_WIDEN
);
4996 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4997 expand_inc (quotient
, const1_rtx
);
4998 expand_dec (remainder
, op1
);
5000 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
5003 /* No luck with division elimination or divmod. Have to do it
5004 by conditionally adjusting op0 *and* the result. */
5006 rtx_code_label
*label1
, *label2
, *label3
, *label4
, *label5
;
5010 quotient
= gen_reg_rtx (compute_mode
);
5011 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
5012 label1
= gen_label_rtx ();
5013 label2
= gen_label_rtx ();
5014 label3
= gen_label_rtx ();
5015 label4
= gen_label_rtx ();
5016 label5
= gen_label_rtx ();
5017 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
5018 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
5019 compute_mode
, label1
);
5020 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
5021 quotient
, 0, OPTAB_LIB_WIDEN
);
5022 if (tem
!= quotient
)
5023 emit_move_insn (quotient
, tem
);
5024 emit_jump_insn (targetm
.gen_jump (label5
));
5026 emit_label (label1
);
5027 expand_dec (adjusted_op0
, const1_rtx
);
5028 emit_jump_insn (targetm
.gen_jump (label4
));
5030 emit_label (label2
);
5031 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
5032 compute_mode
, label3
);
5033 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
5034 quotient
, 0, OPTAB_LIB_WIDEN
);
5035 if (tem
!= quotient
)
5036 emit_move_insn (quotient
, tem
);
5037 emit_jump_insn (targetm
.gen_jump (label5
));
5039 emit_label (label3
);
5040 expand_inc (adjusted_op0
, const1_rtx
);
5041 emit_label (label4
);
5042 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
5043 quotient
, 0, OPTAB_LIB_WIDEN
);
5044 if (tem
!= quotient
)
5045 emit_move_insn (quotient
, tem
);
5046 expand_inc (quotient
, const1_rtx
);
5047 emit_label (label5
);
5052 case EXACT_DIV_EXPR
:
5053 if (op1_is_constant
&& HWI_COMPUTABLE_MODE_P (compute_mode
))
5055 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (compute_mode
);
5056 int size
= GET_MODE_BITSIZE (int_mode
);
5057 HOST_WIDE_INT d
= INTVAL (op1
);
5058 unsigned HOST_WIDE_INT ml
;
5062 pre_shift
= ctz_or_zero (d
);
5063 ml
= invert_mod2n (d
>> pre_shift
, size
);
5064 t1
= expand_shift (RSHIFT_EXPR
, int_mode
, op0
,
5065 pre_shift
, NULL_RTX
, unsignedp
);
5066 quotient
= expand_mult (int_mode
, t1
, gen_int_mode (ml
, int_mode
),
5069 insn
= get_last_insn ();
5070 set_dst_reg_note (insn
, REG_EQUAL
,
5071 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
5072 int_mode
, op0
, op1
),
5077 case ROUND_DIV_EXPR
:
5078 case ROUND_MOD_EXPR
:
5081 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (compute_mode
);
5083 rtx_code_label
*label
;
5084 label
= gen_label_rtx ();
5085 quotient
= gen_reg_rtx (int_mode
);
5086 remainder
= gen_reg_rtx (int_mode
);
5087 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
5090 quotient
= expand_binop (int_mode
, udiv_optab
, op0
, op1
,
5091 quotient
, 1, OPTAB_LIB_WIDEN
);
5092 tem
= expand_mult (int_mode
, quotient
, op1
, NULL_RTX
, 1);
5093 remainder
= expand_binop (int_mode
, sub_optab
, op0
, tem
,
5094 remainder
, 1, OPTAB_LIB_WIDEN
);
5096 tem
= plus_constant (int_mode
, op1
, -1);
5097 tem
= expand_shift (RSHIFT_EXPR
, int_mode
, tem
, 1, NULL_RTX
, 1);
5098 do_cmp_and_jump (remainder
, tem
, LEU
, int_mode
, label
);
5099 expand_inc (quotient
, const1_rtx
);
5100 expand_dec (remainder
, op1
);
5105 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (compute_mode
);
5106 int size
= GET_MODE_BITSIZE (int_mode
);
5107 rtx abs_rem
, abs_op1
, tem
, mask
;
5108 rtx_code_label
*label
;
5109 label
= gen_label_rtx ();
5110 quotient
= gen_reg_rtx (int_mode
);
5111 remainder
= gen_reg_rtx (int_mode
);
5112 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
5115 quotient
= expand_binop (int_mode
, sdiv_optab
, op0
, op1
,
5116 quotient
, 0, OPTAB_LIB_WIDEN
);
5117 tem
= expand_mult (int_mode
, quotient
, op1
, NULL_RTX
, 0);
5118 remainder
= expand_binop (int_mode
, sub_optab
, op0
, tem
,
5119 remainder
, 0, OPTAB_LIB_WIDEN
);
5121 abs_rem
= expand_abs (int_mode
, remainder
, NULL_RTX
, 1, 0);
5122 abs_op1
= expand_abs (int_mode
, op1
, NULL_RTX
, 1, 0);
5123 tem
= expand_shift (LSHIFT_EXPR
, int_mode
, abs_rem
,
5125 do_cmp_and_jump (tem
, abs_op1
, LTU
, int_mode
, label
);
5126 tem
= expand_binop (int_mode
, xor_optab
, op0
, op1
,
5127 NULL_RTX
, 0, OPTAB_WIDEN
);
5128 mask
= expand_shift (RSHIFT_EXPR
, int_mode
, tem
,
5129 size
- 1, NULL_RTX
, 0);
5130 tem
= expand_binop (int_mode
, xor_optab
, mask
, const1_rtx
,
5131 NULL_RTX
, 0, OPTAB_WIDEN
);
5132 tem
= expand_binop (int_mode
, sub_optab
, tem
, mask
,
5133 NULL_RTX
, 0, OPTAB_WIDEN
);
5134 expand_inc (quotient
, tem
);
5135 tem
= expand_binop (int_mode
, xor_optab
, mask
, op1
,
5136 NULL_RTX
, 0, OPTAB_WIDEN
);
5137 tem
= expand_binop (int_mode
, sub_optab
, tem
, mask
,
5138 NULL_RTX
, 0, OPTAB_WIDEN
);
5139 expand_dec (remainder
, tem
);
5142 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
5150 if (target
&& GET_MODE (target
) != compute_mode
)
5155 /* Try to produce the remainder without producing the quotient.
5156 If we seem to have a divmod pattern that does not require widening,
5157 don't try widening here. We should really have a WIDEN argument
5158 to expand_twoval_binop, since what we'd really like to do here is
5159 1) try a mod insn in compute_mode
5160 2) try a divmod insn in compute_mode
5161 3) try a div insn in compute_mode and multiply-subtract to get
5163 4) try the same things with widening allowed. */
5165 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
5168 ((optab_handler (optab2
, compute_mode
)
5169 != CODE_FOR_nothing
)
5170 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
5173 /* No luck there. Can we do remainder and divide at once
5174 without a library call? */
5175 remainder
= gen_reg_rtx (compute_mode
);
5176 if (! expand_twoval_binop ((unsignedp
5180 NULL_RTX
, remainder
, unsignedp
))
5185 return gen_lowpart (mode
, remainder
);
5188 /* Produce the quotient. Try a quotient insn, but not a library call.
5189 If we have a divmod in this mode, use it in preference to widening
5190 the div (for this test we assume it will not fail). Note that optab2
5191 is set to the one of the two optabs that the call below will use. */
5193 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
5194 op0
, op1
, rem_flag
? NULL_RTX
: target
,
5196 ((optab_handler (optab2
, compute_mode
)
5197 != CODE_FOR_nothing
)
5198 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
5202 /* No luck there. Try a quotient-and-remainder insn,
5203 keeping the quotient alone. */
5204 quotient
= gen_reg_rtx (compute_mode
);
5205 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
5207 quotient
, NULL_RTX
, unsignedp
))
5211 /* Still no luck. If we are not computing the remainder,
5212 use a library call for the quotient. */
5213 quotient
= sign_expand_binop (compute_mode
,
5214 udiv_optab
, sdiv_optab
,
5216 unsignedp
, OPTAB_LIB_WIDEN
);
5223 if (target
&& GET_MODE (target
) != compute_mode
)
5228 /* No divide instruction either. Use library for remainder. */
5229 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
5231 unsignedp
, OPTAB_LIB_WIDEN
);
5232 /* No remainder function. Try a quotient-and-remainder
5233 function, keeping the remainder. */
5236 remainder
= gen_reg_rtx (compute_mode
);
5237 if (!expand_twoval_binop_libfunc
5238 (unsignedp
? udivmod_optab
: sdivmod_optab
,
5240 NULL_RTX
, remainder
,
5241 unsignedp
? UMOD
: MOD
))
5242 remainder
= NULL_RTX
;
5247 /* We divided. Now finish doing X - Y * (X / Y). */
5248 remainder
= expand_mult (compute_mode
, quotient
, op1
,
5249 NULL_RTX
, unsignedp
);
5250 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
5251 remainder
, target
, unsignedp
,
5256 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
5259 /* Return a tree node with data type TYPE, describing the value of X.
5260 Usually this is an VAR_DECL, if there is no obvious better choice.
5261 X may be an expression, however we only support those expressions
5262 generated by loop.c. */
5265 make_tree (tree type
, rtx x
)
5269 switch (GET_CODE (x
))
5272 case CONST_WIDE_INT
:
5273 t
= wide_int_to_tree (type
, rtx_mode_t (x
, TYPE_MODE (type
)));
5277 STATIC_ASSERT (HOST_BITS_PER_WIDE_INT
* 2 <= MAX_BITSIZE_MODE_ANY_INT
);
5278 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (x
) == VOIDmode
)
5279 t
= wide_int_to_tree (type
,
5280 wide_int::from_array (&CONST_DOUBLE_LOW (x
), 2,
5281 HOST_BITS_PER_WIDE_INT
* 2));
5283 t
= build_real (type
, *CONST_DOUBLE_REAL_VALUE (x
));
5289 unsigned int npatterns
= CONST_VECTOR_NPATTERNS (x
);
5290 unsigned int nelts_per_pattern
= CONST_VECTOR_NELTS_PER_PATTERN (x
);
5291 tree itype
= TREE_TYPE (type
);
5293 /* Build a tree with vector elements. */
5294 tree_vector_builder
elts (type
, npatterns
, nelts_per_pattern
);
5295 unsigned int count
= elts
.encoded_nelts ();
5296 for (unsigned int i
= 0; i
< count
; ++i
)
5298 rtx elt
= CONST_VECTOR_ELT (x
, i
);
5299 elts
.quick_push (make_tree (itype
, elt
));
5302 return elts
.build ();
5306 return fold_build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5307 make_tree (type
, XEXP (x
, 1)));
5310 return fold_build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5311 make_tree (type
, XEXP (x
, 1)));
5314 return fold_build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0)));
5317 return fold_build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5318 make_tree (type
, XEXP (x
, 1)));
5321 return fold_build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5322 make_tree (type
, XEXP (x
, 1)));
5325 t
= unsigned_type_for (type
);
5326 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5327 make_tree (t
, XEXP (x
, 0)),
5328 make_tree (type
, XEXP (x
, 1))));
5331 t
= signed_type_for (type
);
5332 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5333 make_tree (t
, XEXP (x
, 0)),
5334 make_tree (type
, XEXP (x
, 1))));
5337 if (TREE_CODE (type
) != REAL_TYPE
)
5338 t
= signed_type_for (type
);
5342 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5343 make_tree (t
, XEXP (x
, 0)),
5344 make_tree (t
, XEXP (x
, 1))));
5346 t
= unsigned_type_for (type
);
5347 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5348 make_tree (t
, XEXP (x
, 0)),
5349 make_tree (t
, XEXP (x
, 1))));
5353 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
5354 GET_CODE (x
) == ZERO_EXTEND
);
5355 return fold_convert (type
, make_tree (t
, XEXP (x
, 0)));
5358 return make_tree (type
, XEXP (x
, 0));
5361 t
= SYMBOL_REF_DECL (x
);
5363 return fold_convert (type
, build_fold_addr_expr (t
));
5367 if (CONST_POLY_INT_P (x
))
5368 return wide_int_to_tree (t
, const_poly_int_value (x
));
5370 t
= build_decl (RTL_LOCATION (x
), VAR_DECL
, NULL_TREE
, type
);
5372 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5373 address mode to pointer mode. */
5374 if (POINTER_TYPE_P (type
))
5375 x
= convert_memory_address_addr_space
5376 (SCALAR_INT_TYPE_MODE (type
), x
, TYPE_ADDR_SPACE (TREE_TYPE (type
)));
5378 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5379 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5380 t
->decl_with_rtl
.rtl
= x
;
5386 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5387 and returning TARGET.
5389 If TARGET is 0, a pseudo-register or constant is returned. */
5392 expand_and (machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
5396 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
5397 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
5399 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
5403 else if (tem
!= target
)
5404 emit_move_insn (target
, tem
);
5408 /* Helper function for emit_store_flag. */
5410 emit_cstore (rtx target
, enum insn_code icode
, enum rtx_code code
,
5411 machine_mode mode
, machine_mode compare_mode
,
5412 int unsignedp
, rtx x
, rtx y
, int normalizep
,
5413 machine_mode target_mode
)
5415 struct expand_operand ops
[4];
5416 rtx op0
, comparison
, subtarget
;
5418 scalar_int_mode result_mode
= targetm
.cstore_mode (icode
);
5419 scalar_int_mode int_target_mode
;
5421 last
= get_last_insn ();
5422 x
= prepare_operand (icode
, x
, 2, mode
, compare_mode
, unsignedp
);
5423 y
= prepare_operand (icode
, y
, 3, mode
, compare_mode
, unsignedp
);
5426 delete_insns_since (last
);
5430 if (target_mode
== VOIDmode
)
5431 int_target_mode
= result_mode
;
5433 int_target_mode
= as_a
<scalar_int_mode
> (target_mode
);
5435 target
= gen_reg_rtx (int_target_mode
);
5437 comparison
= gen_rtx_fmt_ee (code
, result_mode
, x
, y
);
5439 create_output_operand (&ops
[0], optimize
? NULL_RTX
: target
, result_mode
);
5440 create_fixed_operand (&ops
[1], comparison
);
5441 create_fixed_operand (&ops
[2], x
);
5442 create_fixed_operand (&ops
[3], y
);
5443 if (!maybe_expand_insn (icode
, 4, ops
))
5445 delete_insns_since (last
);
5448 subtarget
= ops
[0].value
;
5450 /* If we are converting to a wider mode, first convert to
5451 INT_TARGET_MODE, then normalize. This produces better combining
5452 opportunities on machines that have a SIGN_EXTRACT when we are
5453 testing a single bit. This mostly benefits the 68k.
5455 If STORE_FLAG_VALUE does not have the sign bit set when
5456 interpreted in MODE, we can do this conversion as unsigned, which
5457 is usually more efficient. */
5458 if (GET_MODE_SIZE (int_target_mode
) > GET_MODE_SIZE (result_mode
))
5460 convert_move (target
, subtarget
,
5461 val_signbit_known_clear_p (result_mode
,
5464 result_mode
= int_target_mode
;
5469 /* If we want to keep subexpressions around, don't reuse our last
5474 /* Now normalize to the proper value in MODE. Sometimes we don't
5475 have to do anything. */
5476 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
5478 /* STORE_FLAG_VALUE might be the most negative number, so write
5479 the comparison this way to avoid a compiler-time warning. */
5480 else if (- normalizep
== STORE_FLAG_VALUE
)
5481 op0
= expand_unop (result_mode
, neg_optab
, op0
, subtarget
, 0);
5483 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5484 it hard to use a value of just the sign bit due to ANSI integer
5485 constant typing rules. */
5486 else if (val_signbit_known_set_p (result_mode
, STORE_FLAG_VALUE
))
5487 op0
= expand_shift (RSHIFT_EXPR
, result_mode
, op0
,
5488 GET_MODE_BITSIZE (result_mode
) - 1, subtarget
,
5492 gcc_assert (STORE_FLAG_VALUE
& 1);
5494 op0
= expand_and (result_mode
, op0
, const1_rtx
, subtarget
);
5495 if (normalizep
== -1)
5496 op0
= expand_unop (result_mode
, neg_optab
, op0
, op0
, 0);
5499 /* If we were converting to a smaller mode, do the conversion now. */
5500 if (int_target_mode
!= result_mode
)
5502 convert_move (target
, op0
, 0);
5510 /* A subroutine of emit_store_flag only including "tricks" that do not
5511 need a recursive call. These are kept separate to avoid infinite
5515 emit_store_flag_1 (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5516 machine_mode mode
, int unsignedp
, int normalizep
,
5517 machine_mode target_mode
)
5520 enum insn_code icode
;
5521 machine_mode compare_mode
;
5522 enum mode_class mclass
;
5523 enum rtx_code scode
;
5526 code
= unsigned_condition (code
);
5527 scode
= swap_condition (code
);
5529 /* If one operand is constant, make it the second one. Only do this
5530 if the other operand is not constant as well. */
5532 if (swap_commutative_operands_p (op0
, op1
))
5534 std::swap (op0
, op1
);
5535 code
= swap_condition (code
);
5538 if (mode
== VOIDmode
)
5539 mode
= GET_MODE (op0
);
5541 /* For some comparisons with 1 and -1, we can convert this to
5542 comparisons with zero. This will often produce more opportunities for
5543 store-flag insns. */
5548 if (op1
== const1_rtx
)
5549 op1
= const0_rtx
, code
= LE
;
5552 if (op1
== constm1_rtx
)
5553 op1
= const0_rtx
, code
= LT
;
5556 if (op1
== const1_rtx
)
5557 op1
= const0_rtx
, code
= GT
;
5560 if (op1
== constm1_rtx
)
5561 op1
= const0_rtx
, code
= GE
;
5564 if (op1
== const1_rtx
)
5565 op1
= const0_rtx
, code
= NE
;
5568 if (op1
== const1_rtx
)
5569 op1
= const0_rtx
, code
= EQ
;
5575 /* If we are comparing a double-word integer with zero or -1, we can
5576 convert the comparison into one involving a single word. */
5577 scalar_int_mode int_mode
;
5578 if (is_int_mode (mode
, &int_mode
)
5579 && GET_MODE_BITSIZE (int_mode
) == BITS_PER_WORD
* 2
5580 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
5583 if ((code
== EQ
|| code
== NE
)
5584 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
5588 /* Do a logical OR or AND of the two words and compare the
5590 op00
= simplify_gen_subreg (word_mode
, op0
, int_mode
, 0);
5591 op01
= simplify_gen_subreg (word_mode
, op0
, int_mode
, UNITS_PER_WORD
);
5592 tem
= expand_binop (word_mode
,
5593 op1
== const0_rtx
? ior_optab
: and_optab
,
5594 op00
, op01
, NULL_RTX
, unsignedp
,
5598 tem
= emit_store_flag (NULL_RTX
, code
, tem
, op1
, word_mode
,
5599 unsignedp
, normalizep
);
5601 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
5605 /* If testing the sign bit, can just test on high word. */
5606 op0h
= simplify_gen_subreg (word_mode
, op0
, int_mode
,
5607 subreg_highpart_offset (word_mode
,
5609 tem
= emit_store_flag (NULL_RTX
, code
, op0h
, op1
, word_mode
,
5610 unsignedp
, normalizep
);
5617 if (target_mode
== VOIDmode
|| GET_MODE (tem
) == target_mode
)
5620 target
= gen_reg_rtx (target_mode
);
5622 convert_move (target
, tem
,
5623 !val_signbit_known_set_p (word_mode
,
5624 (normalizep
? normalizep
5625 : STORE_FLAG_VALUE
)));
5630 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5631 complement of A (for GE) and shifting the sign bit to the low bit. */
5632 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
5633 && is_int_mode (mode
, &int_mode
)
5634 && (normalizep
|| STORE_FLAG_VALUE
== 1
5635 || val_signbit_p (int_mode
, STORE_FLAG_VALUE
)))
5637 scalar_int_mode int_target_mode
;
5641 int_target_mode
= int_mode
;
5644 /* If the result is to be wider than OP0, it is best to convert it
5645 first. If it is to be narrower, it is *incorrect* to convert it
5647 int_target_mode
= as_a
<scalar_int_mode
> (target_mode
);
5648 if (GET_MODE_SIZE (int_target_mode
) > GET_MODE_SIZE (int_mode
))
5650 op0
= convert_modes (int_target_mode
, int_mode
, op0
, 0);
5651 int_mode
= int_target_mode
;
5655 if (int_target_mode
!= int_mode
)
5659 op0
= expand_unop (int_mode
, one_cmpl_optab
, op0
,
5660 ((STORE_FLAG_VALUE
== 1 || normalizep
)
5661 ? 0 : subtarget
), 0);
5663 if (STORE_FLAG_VALUE
== 1 || normalizep
)
5664 /* If we are supposed to produce a 0/1 value, we want to do
5665 a logical shift from the sign bit to the low-order bit; for
5666 a -1/0 value, we do an arithmetic shift. */
5667 op0
= expand_shift (RSHIFT_EXPR
, int_mode
, op0
,
5668 GET_MODE_BITSIZE (int_mode
) - 1,
5669 subtarget
, normalizep
!= -1);
5671 if (int_mode
!= int_target_mode
)
5672 op0
= convert_modes (int_target_mode
, int_mode
, op0
, 0);
5677 mclass
= GET_MODE_CLASS (mode
);
5678 FOR_EACH_MODE_FROM (compare_mode
, mode
)
5680 machine_mode optab_mode
= mclass
== MODE_CC
? CCmode
: compare_mode
;
5681 icode
= optab_handler (cstore_optab
, optab_mode
);
5682 if (icode
!= CODE_FOR_nothing
)
5684 do_pending_stack_adjust ();
5685 rtx tem
= emit_cstore (target
, icode
, code
, mode
, compare_mode
,
5686 unsignedp
, op0
, op1
, normalizep
, target_mode
);
5690 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5692 tem
= emit_cstore (target
, icode
, scode
, mode
, compare_mode
,
5693 unsignedp
, op1
, op0
, normalizep
, target_mode
);
5704 /* Subroutine of emit_store_flag that handles cases in which the operands
5705 are scalar integers. SUBTARGET is the target to use for temporary
5706 operations and TRUEVAL is the value to store when the condition is
5707 true. All other arguments are as for emit_store_flag. */
5710 emit_store_flag_int (rtx target
, rtx subtarget
, enum rtx_code code
, rtx op0
,
5711 rtx op1
, scalar_int_mode mode
, int unsignedp
,
5712 int normalizep
, rtx trueval
)
5714 machine_mode target_mode
= target
? GET_MODE (target
) : VOIDmode
;
5715 rtx_insn
*last
= get_last_insn ();
5717 /* If this is an equality comparison of integers, we can try to exclusive-or
5718 (or subtract) the two operands and use a recursive call to try the
5719 comparison with zero. Don't do any of these cases if branches are
5722 if ((code
== EQ
|| code
== NE
) && op1
!= const0_rtx
)
5724 rtx tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
5728 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
5731 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
5732 mode
, unsignedp
, normalizep
);
5736 delete_insns_since (last
);
5739 /* For integer comparisons, try the reverse comparison. However, for
5740 small X and if we'd have anyway to extend, implementing "X != 0"
5741 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5742 rtx_code rcode
= reverse_condition (code
);
5743 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5744 && ! (optab_handler (cstore_optab
, mode
) == CODE_FOR_nothing
5746 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5747 && op1
== const0_rtx
))
5749 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5750 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5752 /* Again, for the reverse comparison, use either an addition or a XOR. */
5754 && rtx_cost (GEN_INT (normalizep
), mode
, PLUS
, 1,
5755 optimize_insn_for_speed_p ()) == 0)
5757 rtx tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5758 STORE_FLAG_VALUE
, target_mode
);
5760 tem
= expand_binop (target_mode
, add_optab
, tem
,
5761 gen_int_mode (normalizep
, target_mode
),
5762 target
, 0, OPTAB_WIDEN
);
5767 && rtx_cost (trueval
, mode
, XOR
, 1,
5768 optimize_insn_for_speed_p ()) == 0)
5770 rtx tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5771 normalizep
, target_mode
);
5773 tem
= expand_binop (target_mode
, xor_optab
, tem
, trueval
, target
,
5774 INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5779 delete_insns_since (last
);
5782 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5783 the constant zero. Reject all other comparisons at this point. Only
5784 do LE and GT if branches are expensive since they are expensive on
5785 2-operand machines. */
5787 if (op1
!= const0_rtx
5788 || (code
!= EQ
&& code
!= NE
5789 && (BRANCH_COST (optimize_insn_for_speed_p (),
5790 false) <= 1 || (code
!= LE
&& code
!= GT
))))
5793 /* Try to put the result of the comparison in the sign bit. Assume we can't
5794 do the necessary operation below. */
5798 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5799 the sign bit set. */
5803 /* This is destructive, so SUBTARGET can't be OP0. */
5804 if (rtx_equal_p (subtarget
, op0
))
5807 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
5810 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
5814 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5815 number of bits in the mode of OP0, minus one. */
5819 if (rtx_equal_p (subtarget
, op0
))
5822 tem
= maybe_expand_shift (RSHIFT_EXPR
, mode
, op0
,
5823 GET_MODE_BITSIZE (mode
) - 1,
5826 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5830 if (code
== EQ
|| code
== NE
)
5832 /* For EQ or NE, one way to do the comparison is to apply an operation
5833 that converts the operand into a positive number if it is nonzero
5834 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5835 for NE we negate. This puts the result in the sign bit. Then we
5836 normalize with a shift, if needed.
5838 Two operations that can do the above actions are ABS and FFS, so try
5839 them. If that doesn't work, and MODE is smaller than a full word,
5840 we can use zero-extension to the wider mode (an unsigned conversion)
5841 as the operation. */
5843 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5844 that is compensated by the subsequent overflow when subtracting
5847 if (optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)
5848 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5849 else if (optab_handler (ffs_optab
, mode
) != CODE_FOR_nothing
)
5850 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5851 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5853 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5860 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5863 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5866 /* If we couldn't do it that way, for NE we can "or" the two's complement
5867 of the value with itself. For EQ, we take the one's complement of
5868 that "or", which is an extra insn, so we only handle EQ if branches
5873 || BRANCH_COST (optimize_insn_for_speed_p (),
5876 if (rtx_equal_p (subtarget
, op0
))
5879 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5880 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5883 if (tem
&& code
== EQ
)
5884 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5888 if (tem
&& normalizep
)
5889 tem
= maybe_expand_shift (RSHIFT_EXPR
, mode
, tem
,
5890 GET_MODE_BITSIZE (mode
) - 1,
5891 subtarget
, normalizep
== 1);
5897 else if (GET_MODE (tem
) != target_mode
)
5899 convert_move (target
, tem
, 0);
5902 else if (!subtarget
)
5904 emit_move_insn (target
, tem
);
5909 delete_insns_since (last
);
5914 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5915 and storing in TARGET. Normally return TARGET.
5916 Return 0 if that cannot be done.
5918 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5919 it is VOIDmode, they cannot both be CONST_INT.
5921 UNSIGNEDP is for the case where we have to widen the operands
5922 to perform the operation. It says to use zero-extension.
5924 NORMALIZEP is 1 if we should convert the result to be either zero
5925 or one. Normalize is -1 if we should convert the result to be
5926 either zero or -1. If NORMALIZEP is zero, the result will be left
5927 "raw" out of the scc insn. */
5930 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5931 machine_mode mode
, int unsignedp
, int normalizep
)
5933 machine_mode target_mode
= target
? GET_MODE (target
) : VOIDmode
;
5934 enum rtx_code rcode
;
5939 /* If we compare constants, we shouldn't use a store-flag operation,
5940 but a constant load. We can get there via the vanilla route that
5941 usually generates a compare-branch sequence, but will in this case
5942 fold the comparison to a constant, and thus elide the branch. */
5943 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
5946 tem
= emit_store_flag_1 (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
,
5951 /* If we reached here, we can't do this with a scc insn, however there
5952 are some comparisons that can be done in other ways. Don't do any
5953 of these cases if branches are very cheap. */
5954 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5957 /* See what we need to return. We can only return a 1, -1, or the
5960 if (normalizep
== 0)
5962 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5963 normalizep
= STORE_FLAG_VALUE
;
5965 else if (val_signbit_p (mode
, STORE_FLAG_VALUE
))
5971 last
= get_last_insn ();
5973 /* If optimizing, use different pseudo registers for each insn, instead
5974 of reusing the same pseudo. This leads to better CSE, but slows
5975 down the compiler, since there are more pseudos. */
5976 subtarget
= (!optimize
5977 && (target_mode
== mode
)) ? target
: NULL_RTX
;
5978 trueval
= GEN_INT (normalizep
? normalizep
: STORE_FLAG_VALUE
);
5980 /* For floating-point comparisons, try the reverse comparison or try
5981 changing the "orderedness" of the comparison. */
5982 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5984 enum rtx_code first_code
;
5987 rcode
= reverse_condition_maybe_unordered (code
);
5988 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5989 && (code
== ORDERED
|| code
== UNORDERED
5990 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5991 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5993 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5994 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5996 /* For the reverse comparison, use either an addition or a XOR. */
5998 && rtx_cost (GEN_INT (normalizep
), mode
, PLUS
, 1,
5999 optimize_insn_for_speed_p ()) == 0)
6001 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
6002 STORE_FLAG_VALUE
, target_mode
);
6004 return expand_binop (target_mode
, add_optab
, tem
,
6005 gen_int_mode (normalizep
, target_mode
),
6006 target
, 0, OPTAB_WIDEN
);
6009 && rtx_cost (trueval
, mode
, XOR
, 1,
6010 optimize_insn_for_speed_p ()) == 0)
6012 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
6013 normalizep
, target_mode
);
6015 return expand_binop (target_mode
, xor_optab
, tem
, trueval
,
6016 target
, INTVAL (trueval
) >= 0,
6021 delete_insns_since (last
);
6023 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
6024 if (code
== ORDERED
|| code
== UNORDERED
)
6027 and_them
= split_comparison (code
, mode
, &first_code
, &code
);
6029 /* If there are no NaNs, the first comparison should always fall through.
6030 Effectively change the comparison to the other one. */
6031 if (!HONOR_NANS (mode
))
6033 gcc_assert (first_code
== (and_them
? ORDERED
: UNORDERED
));
6034 return emit_store_flag_1 (target
, code
, op0
, op1
, mode
, 0, normalizep
,
6038 if (!HAVE_conditional_move
)
6041 /* Do not turn a trapping comparison into a non-trapping one. */
6042 if ((code
!= EQ
&& code
!= NE
&& code
!= UNEQ
&& code
!= LTGT
)
6043 && flag_trapping_math
)
6046 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
6047 conditional move. */
6048 tem
= emit_store_flag_1 (subtarget
, first_code
, op0
, op1
, mode
, 0,
6049 normalizep
, target_mode
);
6054 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
6055 tem
, const0_rtx
, GET_MODE (tem
), 0);
6057 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
6058 trueval
, tem
, GET_MODE (tem
), 0);
6061 delete_insns_since (last
);
6065 /* The remaining tricks only apply to integer comparisons. */
6067 scalar_int_mode int_mode
;
6068 if (is_int_mode (mode
, &int_mode
))
6069 return emit_store_flag_int (target
, subtarget
, code
, op0
, op1
, int_mode
,
6070 unsignedp
, normalizep
, trueval
);
6075 /* Like emit_store_flag, but always succeeds. */
6078 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
6079 machine_mode mode
, int unsignedp
, int normalizep
)
6082 rtx_code_label
*label
;
6083 rtx trueval
, falseval
;
6085 /* First see if emit_store_flag can do the job. */
6086 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
6090 /* If one operand is constant, make it the second one. Only do this
6091 if the other operand is not constant as well. */
6092 if (swap_commutative_operands_p (op0
, op1
))
6094 std::swap (op0
, op1
);
6095 code
= swap_condition (code
);
6098 if (mode
== VOIDmode
)
6099 mode
= GET_MODE (op0
);
6102 target
= gen_reg_rtx (word_mode
);
6104 /* If this failed, we have to do this with set/compare/jump/set code.
6105 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
6106 trueval
= normalizep
? GEN_INT (normalizep
) : const1_rtx
;
6108 && GET_MODE_CLASS (mode
) == MODE_INT
6111 && op1
== const0_rtx
)
6113 label
= gen_label_rtx ();
6114 do_compare_rtx_and_jump (target
, const0_rtx
, EQ
, unsignedp
, mode
,
6115 NULL_RTX
, NULL
, label
,
6116 profile_probability::uninitialized ());
6117 emit_move_insn (target
, trueval
);
6123 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
6124 target
= gen_reg_rtx (GET_MODE (target
));
6126 /* Jump in the right direction if the target cannot implement CODE
6127 but can jump on its reverse condition. */
6128 falseval
= const0_rtx
;
6129 if (! can_compare_p (code
, mode
, ccp_jump
)
6130 && (! FLOAT_MODE_P (mode
)
6131 || code
== ORDERED
|| code
== UNORDERED
6132 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
6133 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
6135 enum rtx_code rcode
;
6136 if (FLOAT_MODE_P (mode
))
6137 rcode
= reverse_condition_maybe_unordered (code
);
6139 rcode
= reverse_condition (code
);
6141 /* Canonicalize to UNORDERED for the libcall. */
6142 if (can_compare_p (rcode
, mode
, ccp_jump
)
6143 || (code
== ORDERED
&& ! can_compare_p (ORDERED
, mode
, ccp_jump
)))
6146 trueval
= const0_rtx
;
6151 emit_move_insn (target
, trueval
);
6152 label
= gen_label_rtx ();
6153 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
, NULL
,
6154 label
, profile_probability::uninitialized ());
6156 emit_move_insn (target
, falseval
);
6162 /* Perform possibly multi-word comparison and conditional jump to LABEL
6163 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
6164 now a thin wrapper around do_compare_rtx_and_jump. */
6167 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, machine_mode mode
,
6168 rtx_code_label
*label
)
6170 int unsignedp
= (op
== LTU
|| op
== LEU
|| op
== GTU
|| op
== GEU
);
6171 do_compare_rtx_and_jump (arg1
, arg2
, op
, unsignedp
, mode
, NULL_RTX
,
6172 NULL
, label
, profile_probability::uninitialized ());