1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
27 #include "coretypes.h"
29 #include "diagnostic-core.h"
34 #include "insn-config.h"
38 #include "langhooks.h"
43 struct target_expmed default_target_expmed
;
45 struct target_expmed
*this_target_expmed
= &default_target_expmed
;
48 static void store_fixed_bit_field (rtx
, unsigned HOST_WIDE_INT
,
49 unsigned HOST_WIDE_INT
,
50 unsigned HOST_WIDE_INT
,
51 unsigned HOST_WIDE_INT
,
53 static void store_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
54 unsigned HOST_WIDE_INT
,
55 unsigned HOST_WIDE_INT
,
56 unsigned HOST_WIDE_INT
,
58 static rtx
extract_fixed_bit_field (enum machine_mode
, rtx
,
59 unsigned HOST_WIDE_INT
,
60 unsigned HOST_WIDE_INT
, rtx
, int, bool);
61 static rtx
mask_rtx (enum machine_mode
, int, int, int);
62 static rtx
lshift_value (enum machine_mode
, rtx
, int, int);
63 static rtx
extract_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
64 unsigned HOST_WIDE_INT
, int);
65 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, enum machine_mode
, rtx
);
66 static rtx
expand_smod_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
67 static rtx
expand_sdiv_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
69 /* Test whether a value is zero of a power of two. */
70 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
72 /* Reduce conditional compilation elsewhere. */
75 #define CODE_FOR_insv CODE_FOR_nothing
76 #define gen_insv(a,b,c,d) NULL_RTX
80 #define CODE_FOR_extv CODE_FOR_nothing
81 #define gen_extv(a,b,c,d) NULL_RTX
85 #define CODE_FOR_extzv CODE_FOR_nothing
86 #define gen_extzv(a,b,c,d) NULL_RTX
89 struct init_expmed_rtl
91 struct rtx_def reg
; rtunion reg_fld
[2];
92 struct rtx_def plus
; rtunion plus_fld1
;
94 struct rtx_def mult
; rtunion mult_fld1
;
95 struct rtx_def sdiv
; rtunion sdiv_fld1
;
96 struct rtx_def udiv
; rtunion udiv_fld1
;
97 struct rtx_def sdiv_32
; rtunion sdiv_32_fld1
;
98 struct rtx_def smod_32
; rtunion smod_32_fld1
;
99 struct rtx_def wide_mult
; rtunion wide_mult_fld1
;
100 struct rtx_def wide_lshr
; rtunion wide_lshr_fld1
;
101 struct rtx_def wide_trunc
;
102 struct rtx_def shift
; rtunion shift_fld1
;
103 struct rtx_def shift_mult
; rtunion shift_mult_fld1
;
104 struct rtx_def shift_add
; rtunion shift_add_fld1
;
105 struct rtx_def shift_sub0
; rtunion shift_sub0_fld1
;
106 struct rtx_def shift_sub1
; rtunion shift_sub1_fld1
;
108 struct rtx_def trunc
;
110 rtx pow2
[MAX_BITS_PER_WORD
];
111 rtx cint
[MAX_BITS_PER_WORD
];
115 init_expmed_one_conv (struct init_expmed_rtl
*all
, enum machine_mode to_mode
,
116 enum machine_mode from_mode
, bool speed
)
118 int to_size
, from_size
;
121 /* We're given no information about the true size of a partial integer,
122 only the size of the "full" integer it requires for storage. For
123 comparison purposes here, reduce the bit size by one in that case. */
124 to_size
= (GET_MODE_BITSIZE (to_mode
)
125 - (GET_MODE_CLASS (to_mode
) == MODE_PARTIAL_INT
));
126 from_size
= (GET_MODE_BITSIZE (from_mode
)
127 - (GET_MODE_CLASS (from_mode
) == MODE_PARTIAL_INT
));
129 /* Assume cost of zero-extend and sign-extend is the same. */
130 which
= (to_size
< from_size
? &all
->trunc
: &all
->zext
);
132 PUT_MODE (&all
->reg
, from_mode
);
133 set_convert_cost (to_mode
, from_mode
, speed
, set_src_cost (which
, speed
));
137 init_expmed_one_mode (struct init_expmed_rtl
*all
,
138 enum machine_mode mode
, int speed
)
140 int m
, n
, mode_bitsize
;
141 enum machine_mode mode_from
;
143 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
145 PUT_MODE (&all
->reg
, mode
);
146 PUT_MODE (&all
->plus
, mode
);
147 PUT_MODE (&all
->neg
, mode
);
148 PUT_MODE (&all
->mult
, mode
);
149 PUT_MODE (&all
->sdiv
, mode
);
150 PUT_MODE (&all
->udiv
, mode
);
151 PUT_MODE (&all
->sdiv_32
, mode
);
152 PUT_MODE (&all
->smod_32
, mode
);
153 PUT_MODE (&all
->wide_trunc
, mode
);
154 PUT_MODE (&all
->shift
, mode
);
155 PUT_MODE (&all
->shift_mult
, mode
);
156 PUT_MODE (&all
->shift_add
, mode
);
157 PUT_MODE (&all
->shift_sub0
, mode
);
158 PUT_MODE (&all
->shift_sub1
, mode
);
159 PUT_MODE (&all
->zext
, mode
);
160 PUT_MODE (&all
->trunc
, mode
);
162 set_add_cost (speed
, mode
, set_src_cost (&all
->plus
, speed
));
163 set_neg_cost (speed
, mode
, set_src_cost (&all
->neg
, speed
));
164 set_mul_cost (speed
, mode
, set_src_cost (&all
->mult
, speed
));
165 set_sdiv_cost (speed
, mode
, set_src_cost (&all
->sdiv
, speed
));
166 set_udiv_cost (speed
, mode
, set_src_cost (&all
->udiv
, speed
));
168 set_sdiv_pow2_cheap (speed
, mode
, (set_src_cost (&all
->sdiv_32
, speed
)
169 <= 2 * add_cost (speed
, mode
)));
170 set_smod_pow2_cheap (speed
, mode
, (set_src_cost (&all
->smod_32
, speed
)
171 <= 4 * add_cost (speed
, mode
)));
173 set_shift_cost (speed
, mode
, 0, 0);
175 int cost
= add_cost (speed
, mode
);
176 set_shiftadd_cost (speed
, mode
, 0, cost
);
177 set_shiftsub0_cost (speed
, mode
, 0, cost
);
178 set_shiftsub1_cost (speed
, mode
, 0, cost
);
181 n
= MIN (MAX_BITS_PER_WORD
, mode_bitsize
);
182 for (m
= 1; m
< n
; m
++)
184 XEXP (&all
->shift
, 1) = all
->cint
[m
];
185 XEXP (&all
->shift_mult
, 1) = all
->pow2
[m
];
187 set_shift_cost (speed
, mode
, m
, set_src_cost (&all
->shift
, speed
));
188 set_shiftadd_cost (speed
, mode
, m
, set_src_cost (&all
->shift_add
, speed
));
189 set_shiftsub0_cost (speed
, mode
, m
, set_src_cost (&all
->shift_sub0
, speed
));
190 set_shiftsub1_cost (speed
, mode
, m
, set_src_cost (&all
->shift_sub1
, speed
));
193 if (SCALAR_INT_MODE_P (mode
))
195 for (mode_from
= MIN_MODE_INT
; mode_from
<= MAX_MODE_INT
;
196 mode_from
= (enum machine_mode
)(mode_from
+ 1))
197 init_expmed_one_conv (all
, mode
, mode_from
, speed
);
199 if (GET_MODE_CLASS (mode
) == MODE_INT
)
201 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
202 if (wider_mode
!= VOIDmode
)
204 PUT_MODE (&all
->zext
, wider_mode
);
205 PUT_MODE (&all
->wide_mult
, wider_mode
);
206 PUT_MODE (&all
->wide_lshr
, wider_mode
);
207 XEXP (&all
->wide_lshr
, 1) = GEN_INT (mode_bitsize
);
209 set_mul_widen_cost (speed
, wider_mode
,
210 set_src_cost (&all
->wide_mult
, speed
));
211 set_mul_highpart_cost (speed
, mode
,
212 set_src_cost (&all
->wide_trunc
, speed
));
220 struct init_expmed_rtl all
;
221 enum machine_mode mode
;
224 memset (&all
, 0, sizeof all
);
225 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
227 all
.pow2
[m
] = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
228 all
.cint
[m
] = GEN_INT (m
);
231 PUT_CODE (&all
.reg
, REG
);
232 /* Avoid using hard regs in ways which may be unsupported. */
233 SET_REGNO (&all
.reg
, LAST_VIRTUAL_REGISTER
+ 1);
235 PUT_CODE (&all
.plus
, PLUS
);
236 XEXP (&all
.plus
, 0) = &all
.reg
;
237 XEXP (&all
.plus
, 1) = &all
.reg
;
239 PUT_CODE (&all
.neg
, NEG
);
240 XEXP (&all
.neg
, 0) = &all
.reg
;
242 PUT_CODE (&all
.mult
, MULT
);
243 XEXP (&all
.mult
, 0) = &all
.reg
;
244 XEXP (&all
.mult
, 1) = &all
.reg
;
246 PUT_CODE (&all
.sdiv
, DIV
);
247 XEXP (&all
.sdiv
, 0) = &all
.reg
;
248 XEXP (&all
.sdiv
, 1) = &all
.reg
;
250 PUT_CODE (&all
.udiv
, UDIV
);
251 XEXP (&all
.udiv
, 0) = &all
.reg
;
252 XEXP (&all
.udiv
, 1) = &all
.reg
;
254 PUT_CODE (&all
.sdiv_32
, DIV
);
255 XEXP (&all
.sdiv_32
, 0) = &all
.reg
;
256 XEXP (&all
.sdiv_32
, 1) = 32 < MAX_BITS_PER_WORD
? all
.cint
[32] : GEN_INT (32);
258 PUT_CODE (&all
.smod_32
, MOD
);
259 XEXP (&all
.smod_32
, 0) = &all
.reg
;
260 XEXP (&all
.smod_32
, 1) = XEXP (&all
.sdiv_32
, 1);
262 PUT_CODE (&all
.zext
, ZERO_EXTEND
);
263 XEXP (&all
.zext
, 0) = &all
.reg
;
265 PUT_CODE (&all
.wide_mult
, MULT
);
266 XEXP (&all
.wide_mult
, 0) = &all
.zext
;
267 XEXP (&all
.wide_mult
, 1) = &all
.zext
;
269 PUT_CODE (&all
.wide_lshr
, LSHIFTRT
);
270 XEXP (&all
.wide_lshr
, 0) = &all
.wide_mult
;
272 PUT_CODE (&all
.wide_trunc
, TRUNCATE
);
273 XEXP (&all
.wide_trunc
, 0) = &all
.wide_lshr
;
275 PUT_CODE (&all
.shift
, ASHIFT
);
276 XEXP (&all
.shift
, 0) = &all
.reg
;
278 PUT_CODE (&all
.shift_mult
, MULT
);
279 XEXP (&all
.shift_mult
, 0) = &all
.reg
;
281 PUT_CODE (&all
.shift_add
, PLUS
);
282 XEXP (&all
.shift_add
, 0) = &all
.shift_mult
;
283 XEXP (&all
.shift_add
, 1) = &all
.reg
;
285 PUT_CODE (&all
.shift_sub0
, MINUS
);
286 XEXP (&all
.shift_sub0
, 0) = &all
.shift_mult
;
287 XEXP (&all
.shift_sub0
, 1) = &all
.reg
;
289 PUT_CODE (&all
.shift_sub1
, MINUS
);
290 XEXP (&all
.shift_sub1
, 0) = &all
.reg
;
291 XEXP (&all
.shift_sub1
, 1) = &all
.shift_mult
;
293 PUT_CODE (&all
.trunc
, TRUNCATE
);
294 XEXP (&all
.trunc
, 0) = &all
.reg
;
296 for (speed
= 0; speed
< 2; speed
++)
298 crtl
->maybe_hot_insn_p
= speed
;
299 set_zero_cost (speed
, set_src_cost (const0_rtx
, speed
));
301 for (mode
= MIN_MODE_INT
; mode
<= MAX_MODE_INT
;
302 mode
= (enum machine_mode
)(mode
+ 1))
303 init_expmed_one_mode (&all
, mode
, speed
);
305 if (MIN_MODE_PARTIAL_INT
!= VOIDmode
)
306 for (mode
= MIN_MODE_PARTIAL_INT
; mode
<= MAX_MODE_PARTIAL_INT
;
307 mode
= (enum machine_mode
)(mode
+ 1))
308 init_expmed_one_mode (&all
, mode
, speed
);
310 if (MIN_MODE_VECTOR_INT
!= VOIDmode
)
311 for (mode
= MIN_MODE_VECTOR_INT
; mode
<= MAX_MODE_VECTOR_INT
;
312 mode
= (enum machine_mode
)(mode
+ 1))
313 init_expmed_one_mode (&all
, mode
, speed
);
316 if (alg_hash_used_p ())
318 struct alg_hash_entry
*p
= alg_hash_entry_ptr (0);
319 memset (p
, 0, sizeof (*p
) * NUM_ALG_HASH_ENTRIES
);
322 set_alg_hash_used_p (true);
323 default_rtl_profile ();
326 /* Return an rtx representing minus the value of X.
327 MODE is the intended mode of the result,
328 useful if X is a CONST_INT. */
331 negate_rtx (enum machine_mode mode
, rtx x
)
333 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
336 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
341 /* Report on the availability of insv/extv/extzv and the desired mode
342 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
343 is false; else the mode of the specified operand. If OPNO is -1,
344 all the caller cares about is whether the insn is available. */
346 mode_for_extraction (enum extraction_pattern pattern
, int opno
)
348 const struct insn_data_d
*data
;
355 data
= &insn_data
[CODE_FOR_insv
];
358 return MAX_MACHINE_MODE
;
363 data
= &insn_data
[CODE_FOR_extv
];
366 return MAX_MACHINE_MODE
;
371 data
= &insn_data
[CODE_FOR_extzv
];
374 return MAX_MACHINE_MODE
;
383 /* Everyone who uses this function used to follow it with
384 if (result == VOIDmode) result = word_mode; */
385 if (data
->operand
[opno
].mode
== VOIDmode
)
387 return data
->operand
[opno
].mode
;
390 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
391 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
392 offset is then BITNUM / BITS_PER_UNIT. */
395 lowpart_bit_field_p (unsigned HOST_WIDE_INT bitnum
,
396 unsigned HOST_WIDE_INT bitsize
,
397 enum machine_mode struct_mode
)
399 if (BYTES_BIG_ENDIAN
)
400 return (bitnum
% BITS_PER_UNIT
== 0
401 && (bitnum
+ bitsize
== GET_MODE_BITSIZE (struct_mode
)
402 || (bitnum
+ bitsize
) % BITS_PER_WORD
== 0));
404 return bitnum
% BITS_PER_WORD
== 0;
407 /* A subroutine of store_bit_field, with the same arguments. Return true
408 if the operation could be implemented.
410 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
411 no other way of implementing the operation. If FALLBACK_P is false,
412 return false instead. */
415 store_bit_field_1 (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
416 unsigned HOST_WIDE_INT bitnum
,
417 unsigned HOST_WIDE_INT bitregion_start
,
418 unsigned HOST_WIDE_INT bitregion_end
,
419 enum machine_mode fieldmode
,
420 rtx value
, bool fallback_p
)
425 while (GET_CODE (op0
) == SUBREG
)
427 /* The following line once was done only if WORDS_BIG_ENDIAN,
428 but I think that is a mistake. WORDS_BIG_ENDIAN is
429 meaningful at a much higher level; when structures are copied
430 between memory and regs, the higher-numbered regs
431 always get higher addresses. */
432 int inner_mode_size
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)));
433 int outer_mode_size
= GET_MODE_SIZE (GET_MODE (op0
));
436 /* Paradoxical subregs need special handling on big endian machines. */
437 if (SUBREG_BYTE (op0
) == 0 && inner_mode_size
< outer_mode_size
)
439 int difference
= inner_mode_size
- outer_mode_size
;
441 if (WORDS_BIG_ENDIAN
)
442 byte_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
443 if (BYTES_BIG_ENDIAN
)
444 byte_offset
+= difference
% UNITS_PER_WORD
;
447 byte_offset
= SUBREG_BYTE (op0
);
449 bitnum
+= byte_offset
* BITS_PER_UNIT
;
450 op0
= SUBREG_REG (op0
);
453 /* No action is needed if the target is a register and if the field
454 lies completely outside that register. This can occur if the source
455 code contains an out-of-bounds access to a small array. */
456 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
459 /* Use vec_set patterns for inserting parts of vectors whenever
461 if (VECTOR_MODE_P (GET_MODE (op0
))
463 && optab_handler (vec_set_optab
, GET_MODE (op0
)) != CODE_FOR_nothing
464 && fieldmode
== GET_MODE_INNER (GET_MODE (op0
))
465 && bitsize
== GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
466 && !(bitnum
% GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
468 struct expand_operand ops
[3];
469 enum machine_mode outermode
= GET_MODE (op0
);
470 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
471 enum insn_code icode
= optab_handler (vec_set_optab
, outermode
);
472 int pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
474 create_fixed_operand (&ops
[0], op0
);
475 create_input_operand (&ops
[1], value
, innermode
);
476 create_integer_operand (&ops
[2], pos
);
477 if (maybe_expand_insn (icode
, 3, ops
))
481 /* If the target is a register, overwriting the entire object, or storing
482 a full-word or multi-word field can be done with just a SUBREG. */
484 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
485 && ((bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)) && bitnum
== 0)
486 || (bitsize
% BITS_PER_WORD
== 0 && bitnum
% BITS_PER_WORD
== 0)))
488 /* Use the subreg machinery either to narrow OP0 to the required
489 words or to cope with mode punning between equal-sized modes. */
490 rtx sub
= simplify_gen_subreg (fieldmode
, op0
, GET_MODE (op0
),
491 bitnum
/ BITS_PER_UNIT
);
494 emit_move_insn (sub
, value
);
499 /* If the target is memory, storing any naturally aligned field can be
500 done with a simple store. For targets that support fast unaligned
501 memory, any naturally sized, unit aligned field can be done directly. */
503 && bitnum
% BITS_PER_UNIT
== 0
504 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
505 && (!SLOW_UNALIGNED_ACCESS (fieldmode
, MEM_ALIGN (op0
))
506 || (bitnum
% bitsize
== 0
507 && MEM_ALIGN (op0
) % bitsize
== 0)))
509 op0
= adjust_bitfield_address (op0
, fieldmode
, bitnum
/ BITS_PER_UNIT
);
510 emit_move_insn (op0
, value
);
514 /* Make sure we are playing with integral modes. Pun with subregs
515 if we aren't. This must come after the entire register case above,
516 since that case is valid for any mode. The following cases are only
517 valid for integral modes. */
519 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
520 if (imode
!= GET_MODE (op0
))
523 op0
= adjust_bitfield_address (op0
, imode
, 0);
526 gcc_assert (imode
!= BLKmode
);
527 op0
= gen_lowpart (imode
, op0
);
532 /* Storing an lsb-aligned field in a register
533 can be done with a movstrict instruction. */
536 && lowpart_bit_field_p (bitnum
, bitsize
, GET_MODE (op0
))
537 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
538 && optab_handler (movstrict_optab
, fieldmode
) != CODE_FOR_nothing
)
540 struct expand_operand ops
[2];
541 enum insn_code icode
= optab_handler (movstrict_optab
, fieldmode
);
543 unsigned HOST_WIDE_INT subreg_off
;
545 if (GET_CODE (arg0
) == SUBREG
)
547 /* Else we've got some float mode source being extracted into
548 a different float mode destination -- this combination of
549 subregs results in Severe Tire Damage. */
550 gcc_assert (GET_MODE (SUBREG_REG (arg0
)) == fieldmode
551 || GET_MODE_CLASS (fieldmode
) == MODE_INT
552 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
);
553 arg0
= SUBREG_REG (arg0
);
556 subreg_off
= bitnum
/ BITS_PER_UNIT
;
557 if (validate_subreg (fieldmode
, GET_MODE (arg0
), arg0
, subreg_off
))
559 arg0
= gen_rtx_SUBREG (fieldmode
, arg0
, subreg_off
);
561 create_fixed_operand (&ops
[0], arg0
);
562 /* Shrink the source operand to FIELDMODE. */
563 create_convert_operand_to (&ops
[1], value
, fieldmode
, false);
564 if (maybe_expand_insn (icode
, 2, ops
))
569 /* Handle fields bigger than a word. */
571 if (bitsize
> BITS_PER_WORD
)
573 /* Here we transfer the words of the field
574 in the order least significant first.
575 This is because the most significant word is the one which may
577 However, only do that if the value is not BLKmode. */
579 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
580 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
584 /* This is the mode we must force value to, so that there will be enough
585 subwords to extract. Note that fieldmode will often (always?) be
586 VOIDmode, because that is what store_field uses to indicate that this
587 is a bit field, but passing VOIDmode to operand_subword_force
589 fieldmode
= GET_MODE (value
);
590 if (fieldmode
== VOIDmode
)
591 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
593 last
= get_last_insn ();
594 for (i
= 0; i
< nwords
; i
++)
596 /* If I is 0, use the low-order word in both field and target;
597 if I is 1, use the next to lowest word; and so on. */
598 unsigned int wordnum
= (backwards
599 ? GET_MODE_SIZE (fieldmode
) / UNITS_PER_WORD
602 unsigned int bit_offset
= (backwards
603 ? MAX ((int) bitsize
- ((int) i
+ 1)
606 : (int) i
* BITS_PER_WORD
);
607 rtx value_word
= operand_subword_force (value
, wordnum
, fieldmode
);
608 unsigned HOST_WIDE_INT new_bitsize
=
609 MIN (BITS_PER_WORD
, bitsize
- i
* BITS_PER_WORD
);
611 /* If the remaining chunk doesn't have full wordsize we have
612 to make sure that for big endian machines the higher order
614 if (new_bitsize
< BITS_PER_WORD
&& BYTES_BIG_ENDIAN
&& !backwards
)
615 value_word
= simplify_expand_binop (word_mode
, lshr_optab
,
617 GEN_INT (BITS_PER_WORD
622 if (!store_bit_field_1 (op0
, new_bitsize
,
624 bitregion_start
, bitregion_end
,
626 value_word
, fallback_p
))
628 delete_insns_since (last
);
635 /* If VALUE has a floating-point or complex mode, access it as an
636 integer of the corresponding size. This can occur on a machine
637 with 64 bit registers that uses SFmode for float. It can also
638 occur for unaligned float or complex fields. */
640 if (GET_MODE (value
) != VOIDmode
641 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_INT
642 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_PARTIAL_INT
)
644 value
= gen_reg_rtx (int_mode_for_mode (GET_MODE (value
)));
645 emit_move_insn (gen_lowpart (GET_MODE (orig_value
), value
), orig_value
);
648 /* If OP0 is a multi-word register, narrow it to the affected word.
649 If the region spans two words, defer to store_split_bit_field. */
650 if (!MEM_P (op0
) && GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
652 op0
= simplify_gen_subreg (word_mode
, op0
, GET_MODE (op0
),
653 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
655 bitnum
%= BITS_PER_WORD
;
656 if (bitnum
+ bitsize
> BITS_PER_WORD
)
661 store_split_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
662 bitregion_end
, value
);
667 /* From here on we can assume that the field to be stored in fits
668 within a word. If the destination is a register, it too fits
671 enum machine_mode op_mode
= mode_for_extraction (EP_insv
, 3);
673 && GET_MODE (value
) != BLKmode
675 && GET_MODE_BITSIZE (op_mode
) >= bitsize
676 /* Do not use insv for volatile bitfields when
677 -fstrict-volatile-bitfields is in effect. */
678 && !(MEM_P (op0
) && MEM_VOLATILE_P (op0
)
679 && flag_strict_volatile_bitfields
> 0)
680 /* Do not use insv if the bit region is restricted and
681 op_mode integer at offset doesn't fit into the
682 restricted region. */
683 && !(MEM_P (op0
) && bitregion_end
684 && bitnum
- (bitnum
% BITS_PER_UNIT
) + GET_MODE_BITSIZE (op_mode
)
685 > bitregion_end
+ 1))
687 struct expand_operand ops
[4];
688 unsigned HOST_WIDE_INT bitpos
= bitnum
;
691 rtx last
= get_last_insn ();
692 bool copy_back
= false;
694 unsigned int unit
= GET_MODE_BITSIZE (op_mode
);
697 /* Get a reference to the first byte of the field. */
698 xop0
= adjust_bitfield_address (xop0
, byte_mode
,
699 bitpos
/ BITS_PER_UNIT
);
700 bitpos
%= BITS_PER_UNIT
;
704 /* Convert from counting within OP0 to counting in OP_MODE. */
705 if (BYTES_BIG_ENDIAN
)
706 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
709 /* If xop0 is a register, we need it in OP_MODE
710 to make it acceptable to the format of insv. */
711 if (GET_CODE (xop0
) == SUBREG
)
712 /* We can't just change the mode, because this might clobber op0,
713 and we will need the original value of op0 if insv fails. */
714 xop0
= gen_rtx_SUBREG (op_mode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
715 if (REG_P (xop0
) && GET_MODE (xop0
) != op_mode
)
716 xop0
= gen_lowpart_SUBREG (op_mode
, xop0
);
718 /* If the destination is a paradoxical subreg such that we need a
719 truncate to the inner mode, perform the insertion on a temporary and
720 truncate the result to the original destination. Note that we can't
721 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
722 X) 0)) is (reg:N X). */
723 if (GET_CODE (xop0
) == SUBREG
724 && REG_P (SUBREG_REG (xop0
))
725 && (!TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0
)),
728 rtx tem
= gen_reg_rtx (op_mode
);
729 emit_move_insn (tem
, xop0
);
734 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
735 "backwards" from the size of the unit we are inserting into.
736 Otherwise, we count bits from the most significant on a
737 BYTES/BITS_BIG_ENDIAN machine. */
739 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
740 bitpos
= unit
- bitsize
- bitpos
;
742 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
744 if (GET_MODE (value
) != op_mode
)
746 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
748 /* Optimization: Don't bother really extending VALUE
749 if it has all the bits we will actually use. However,
750 if we must narrow it, be sure we do it correctly. */
752 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (op_mode
))
756 tmp
= simplify_subreg (op_mode
, value1
, GET_MODE (value
), 0);
758 tmp
= simplify_gen_subreg (op_mode
,
759 force_reg (GET_MODE (value
),
761 GET_MODE (value
), 0);
765 value1
= gen_lowpart (op_mode
, value1
);
767 else if (CONST_INT_P (value
))
768 value1
= gen_int_mode (INTVAL (value
), op_mode
);
770 /* Parse phase is supposed to make VALUE's data type
771 match that of the component reference, which is a type
772 at least as wide as the field; so VALUE should have
773 a mode that corresponds to that type. */
774 gcc_assert (CONSTANT_P (value
));
777 create_fixed_operand (&ops
[0], xop0
);
778 create_integer_operand (&ops
[1], bitsize
);
779 create_integer_operand (&ops
[2], bitpos
);
780 create_input_operand (&ops
[3], value1
, op_mode
);
781 if (maybe_expand_insn (CODE_FOR_insv
, 4, ops
))
784 convert_move (op0
, xop0
, true);
787 delete_insns_since (last
);
790 /* If OP0 is a memory, try copying it to a register and seeing if a
791 cheap register alternative is available. */
792 if (HAVE_insv
&& MEM_P (op0
))
794 enum machine_mode bestmode
;
795 unsigned HOST_WIDE_INT maxbits
= MAX_FIXED_MODE_SIZE
;
798 maxbits
= bitregion_end
- bitregion_start
+ 1;
800 /* Get the mode to use for inserting into this field. If OP0 is
801 BLKmode, get the smallest mode consistent with the alignment. If
802 OP0 is a non-BLKmode object that is no wider than OP_MODE, use its
803 mode. Otherwise, use the smallest mode containing the field. */
805 if (GET_MODE (op0
) == BLKmode
806 || GET_MODE_BITSIZE (GET_MODE (op0
)) > maxbits
807 || (op_mode
!= MAX_MACHINE_MODE
808 && GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (op_mode
)))
809 bestmode
= get_best_mode (bitsize
, bitnum
,
810 bitregion_start
, bitregion_end
,
812 (op_mode
== MAX_MACHINE_MODE
813 ? VOIDmode
: op_mode
),
814 MEM_VOLATILE_P (op0
));
816 bestmode
= GET_MODE (op0
);
818 if (bestmode
!= VOIDmode
819 && GET_MODE_SIZE (bestmode
) >= GET_MODE_SIZE (fieldmode
)
820 && !(SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (op0
))
821 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (op0
)))
823 rtx last
, tempreg
, xop0
;
825 unsigned HOST_WIDE_INT offset
, bitpos
;
827 last
= get_last_insn ();
829 /* Adjust address to point to the containing unit of
830 that mode. Compute the offset as a multiple of this unit,
831 counting in bytes. */
832 unit
= GET_MODE_BITSIZE (bestmode
);
833 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
834 bitpos
= bitnum
% unit
;
835 xop0
= adjust_bitfield_address (op0
, bestmode
, offset
);
837 /* Fetch that unit, store the bitfield in it, then store
839 tempreg
= copy_to_reg (xop0
);
840 if (store_bit_field_1 (tempreg
, bitsize
, bitpos
,
841 bitregion_start
, bitregion_end
,
842 fieldmode
, orig_value
, false))
844 emit_move_insn (xop0
, tempreg
);
847 delete_insns_since (last
);
854 store_fixed_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
855 bitregion_end
, value
);
859 /* Generate code to store value from rtx VALUE
860 into a bit-field within structure STR_RTX
861 containing BITSIZE bits starting at bit BITNUM.
863 BITREGION_START is bitpos of the first bitfield in this region.
864 BITREGION_END is the bitpos of the ending bitfield in this region.
865 These two fields are 0, if the C++ memory model does not apply,
866 or we are not interested in keeping track of bitfield regions.
868 FIELDMODE is the machine-mode of the FIELD_DECL node for this field. */
871 store_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
872 unsigned HOST_WIDE_INT bitnum
,
873 unsigned HOST_WIDE_INT bitregion_start
,
874 unsigned HOST_WIDE_INT bitregion_end
,
875 enum machine_mode fieldmode
,
878 /* Under the C++0x memory model, we must not touch bits outside the
879 bit region. Adjust the address to start at the beginning of the
881 if (MEM_P (str_rtx
) && bitregion_start
> 0)
883 enum machine_mode bestmode
;
884 enum machine_mode op_mode
;
885 unsigned HOST_WIDE_INT offset
;
887 op_mode
= mode_for_extraction (EP_insv
, 3);
888 if (op_mode
== MAX_MACHINE_MODE
)
891 gcc_assert ((bitregion_start
% BITS_PER_UNIT
) == 0);
893 offset
= bitregion_start
/ BITS_PER_UNIT
;
894 bitnum
-= bitregion_start
;
895 bitregion_end
-= bitregion_start
;
897 bestmode
= get_best_mode (bitsize
, bitnum
,
898 bitregion_start
, bitregion_end
,
901 MEM_VOLATILE_P (str_rtx
));
902 str_rtx
= adjust_address (str_rtx
, bestmode
, offset
);
905 if (!store_bit_field_1 (str_rtx
, bitsize
, bitnum
,
906 bitregion_start
, bitregion_end
,
907 fieldmode
, value
, true))
911 /* Use shifts and boolean operations to store VALUE into a bit field of
912 width BITSIZE in OP0, starting at bit BITNUM. */
915 store_fixed_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
916 unsigned HOST_WIDE_INT bitnum
,
917 unsigned HOST_WIDE_INT bitregion_start
,
918 unsigned HOST_WIDE_INT bitregion_end
,
921 enum machine_mode mode
;
926 /* There is a case not handled here:
927 a structure with a known alignment of just a halfword
928 and a field split across two aligned halfwords within the structure.
929 Or likewise a structure with a known alignment of just a byte
930 and a field split across two bytes.
931 Such cases are not supposed to be able to occur. */
935 unsigned HOST_WIDE_INT maxbits
= MAX_FIXED_MODE_SIZE
;
938 maxbits
= bitregion_end
- bitregion_start
+ 1;
940 /* Get the proper mode to use for this field. We want a mode that
941 includes the entire field. If such a mode would be larger than
942 a word, we won't be doing the extraction the normal way.
943 We don't want a mode bigger than the destination. */
945 mode
= GET_MODE (op0
);
946 if (GET_MODE_BITSIZE (mode
) == 0
947 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
950 if (MEM_VOLATILE_P (op0
)
951 && GET_MODE_BITSIZE (GET_MODE (op0
)) > 0
952 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= maxbits
953 && flag_strict_volatile_bitfields
> 0)
954 mode
= GET_MODE (op0
);
956 mode
= get_best_mode (bitsize
, bitnum
, bitregion_start
, bitregion_end
,
957 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
959 if (mode
== VOIDmode
)
961 /* The only way this should occur is if the field spans word
963 store_split_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
964 bitregion_end
, value
);
968 HOST_WIDE_INT bit_offset
= bitnum
- bitnum
% GET_MODE_BITSIZE (mode
);
969 op0
= adjust_bitfield_address (op0
, mode
, bit_offset
/ BITS_PER_UNIT
);
970 bitnum
-= bit_offset
;
973 mode
= GET_MODE (op0
);
974 gcc_assert (SCALAR_INT_MODE_P (mode
));
976 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
977 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
979 if (BYTES_BIG_ENDIAN
)
980 /* BITNUM is the distance between our msb
981 and that of the containing datum.
982 Convert it to the distance from the lsb. */
983 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
985 /* Now BITNUM is always the distance between our lsb
988 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
989 we must first convert its mode to MODE. */
991 if (CONST_INT_P (value
))
993 HOST_WIDE_INT v
= INTVAL (value
);
995 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
996 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
1000 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
1001 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
1002 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
1005 value
= lshift_value (mode
, value
, bitnum
, bitsize
);
1009 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
1010 && bitnum
+ bitsize
!= GET_MODE_BITSIZE (mode
));
1012 if (GET_MODE (value
) != mode
)
1013 value
= convert_to_mode (mode
, value
, 1);
1016 value
= expand_binop (mode
, and_optab
, value
,
1017 mask_rtx (mode
, 0, bitsize
, 0),
1018 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1020 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
1021 bitnum
, NULL_RTX
, 1);
1024 /* Now clear the chosen bits in OP0,
1025 except that if VALUE is -1 we need not bother. */
1026 /* We keep the intermediates in registers to allow CSE to combine
1027 consecutive bitfield assignments. */
1029 temp
= force_reg (mode
, op0
);
1033 temp
= expand_binop (mode
, and_optab
, temp
,
1034 mask_rtx (mode
, bitnum
, bitsize
, 1),
1035 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1036 temp
= force_reg (mode
, temp
);
1039 /* Now logical-or VALUE into OP0, unless it is zero. */
1043 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
1044 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1045 temp
= force_reg (mode
, temp
);
1050 op0
= copy_rtx (op0
);
1051 emit_move_insn (op0
, temp
);
1055 /* Store a bit field that is split across multiple accessible memory objects.
1057 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1058 BITSIZE is the field width; BITPOS the position of its first bit
1060 VALUE is the value to store.
1062 This does not yet handle fields wider than BITS_PER_WORD. */
1065 store_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1066 unsigned HOST_WIDE_INT bitpos
,
1067 unsigned HOST_WIDE_INT bitregion_start
,
1068 unsigned HOST_WIDE_INT bitregion_end
,
1072 unsigned int bitsdone
= 0;
1074 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1076 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1077 unit
= BITS_PER_WORD
;
1079 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1081 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1082 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1083 that VALUE might be a floating-point constant. */
1084 if (CONSTANT_P (value
) && !CONST_INT_P (value
))
1086 rtx word
= gen_lowpart_common (word_mode
, value
);
1088 if (word
&& (value
!= word
))
1091 value
= gen_lowpart_common (word_mode
,
1092 force_reg (GET_MODE (value
) != VOIDmode
1094 : word_mode
, value
));
1097 while (bitsdone
< bitsize
)
1099 unsigned HOST_WIDE_INT thissize
;
1101 unsigned HOST_WIDE_INT thispos
;
1102 unsigned HOST_WIDE_INT offset
;
1104 offset
= (bitpos
+ bitsdone
) / unit
;
1105 thispos
= (bitpos
+ bitsdone
) % unit
;
1107 /* When region of bytes we can touch is restricted, decrease
1108 UNIT close to the end of the region as needed. */
1110 && unit
> BITS_PER_UNIT
1111 && bitpos
+ bitsdone
- thispos
+ unit
> bitregion_end
+ 1)
1117 /* THISSIZE must not overrun a word boundary. Otherwise,
1118 store_fixed_bit_field will call us again, and we will mutually
1120 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1121 thissize
= MIN (thissize
, unit
- thispos
);
1123 if (BYTES_BIG_ENDIAN
)
1125 /* Fetch successively less significant portions. */
1126 if (CONST_INT_P (value
))
1127 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1128 >> (bitsize
- bitsdone
- thissize
))
1129 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1132 int total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
1133 /* The args are chosen so that the last part includes the
1134 lsb. Give extract_bit_field the value it needs (with
1135 endianness compensation) to fetch the piece we want. */
1136 part
= extract_fixed_bit_field (word_mode
, value
, thissize
,
1137 total_bits
- bitsize
+ bitsdone
,
1138 NULL_RTX
, 1, false);
1143 /* Fetch successively more significant portions. */
1144 if (CONST_INT_P (value
))
1145 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1147 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1149 part
= extract_fixed_bit_field (word_mode
, value
, thissize
,
1150 bitsdone
, NULL_RTX
, 1, false);
1153 /* If OP0 is a register, then handle OFFSET here.
1155 When handling multiword bitfields, extract_bit_field may pass
1156 down a word_mode SUBREG of a larger REG for a bitfield that actually
1157 crosses a word boundary. Thus, for a SUBREG, we must find
1158 the current word starting from the base register. */
1159 if (GET_CODE (op0
) == SUBREG
)
1161 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1162 enum machine_mode sub_mode
= GET_MODE (SUBREG_REG (op0
));
1163 if (sub_mode
!= BLKmode
&& GET_MODE_SIZE (sub_mode
) < UNITS_PER_WORD
)
1164 word
= word_offset
? const0_rtx
: op0
;
1166 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1167 GET_MODE (SUBREG_REG (op0
)));
1170 else if (REG_P (op0
))
1172 enum machine_mode op0_mode
= GET_MODE (op0
);
1173 if (op0_mode
!= BLKmode
&& GET_MODE_SIZE (op0_mode
) < UNITS_PER_WORD
)
1174 word
= offset
? const0_rtx
: op0
;
1176 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1182 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1183 it is just an out-of-bounds access. Ignore it. */
1184 if (word
!= const0_rtx
)
1185 store_fixed_bit_field (word
, thissize
, offset
* unit
+ thispos
,
1186 bitregion_start
, bitregion_end
, part
);
1187 bitsdone
+= thissize
;
1191 /* A subroutine of extract_bit_field_1 that converts return value X
1192 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1193 to extract_bit_field. */
1196 convert_extracted_bit_field (rtx x
, enum machine_mode mode
,
1197 enum machine_mode tmode
, bool unsignedp
)
1199 if (GET_MODE (x
) == tmode
|| GET_MODE (x
) == mode
)
1202 /* If the x mode is not a scalar integral, first convert to the
1203 integer mode of that size and then access it as a floating-point
1204 value via a SUBREG. */
1205 if (!SCALAR_INT_MODE_P (tmode
))
1207 enum machine_mode smode
;
1209 smode
= mode_for_size (GET_MODE_BITSIZE (tmode
), MODE_INT
, 0);
1210 x
= convert_to_mode (smode
, x
, unsignedp
);
1211 x
= force_reg (smode
, x
);
1212 return gen_lowpart (tmode
, x
);
1215 return convert_to_mode (tmode
, x
, unsignedp
);
1218 /* A subroutine of extract_bit_field, with the same arguments.
1219 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1220 if we can find no other means of implementing the operation.
1221 if FALLBACK_P is false, return NULL instead. */
1224 extract_bit_field_1 (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1225 unsigned HOST_WIDE_INT bitnum
,
1226 int unsignedp
, bool packedp
, rtx target
,
1227 enum machine_mode mode
, enum machine_mode tmode
,
1231 enum machine_mode int_mode
;
1232 enum machine_mode ext_mode
;
1233 enum machine_mode mode1
;
1235 if (tmode
== VOIDmode
)
1238 while (GET_CODE (op0
) == SUBREG
)
1240 bitnum
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1241 op0
= SUBREG_REG (op0
);
1244 /* If we have an out-of-bounds access to a register, just return an
1245 uninitialized register of the required mode. This can occur if the
1246 source code contains an out-of-bounds access to a small array. */
1247 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
1248 return gen_reg_rtx (tmode
);
1251 && mode
== GET_MODE (op0
)
1253 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1255 /* We're trying to extract a full register from itself. */
1259 /* See if we can get a better vector mode before extracting. */
1260 if (VECTOR_MODE_P (GET_MODE (op0
))
1262 && GET_MODE_INNER (GET_MODE (op0
)) != tmode
)
1264 enum machine_mode new_mode
;
1266 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1267 new_mode
= MIN_MODE_VECTOR_FLOAT
;
1268 else if (GET_MODE_CLASS (tmode
) == MODE_FRACT
)
1269 new_mode
= MIN_MODE_VECTOR_FRACT
;
1270 else if (GET_MODE_CLASS (tmode
) == MODE_UFRACT
)
1271 new_mode
= MIN_MODE_VECTOR_UFRACT
;
1272 else if (GET_MODE_CLASS (tmode
) == MODE_ACCUM
)
1273 new_mode
= MIN_MODE_VECTOR_ACCUM
;
1274 else if (GET_MODE_CLASS (tmode
) == MODE_UACCUM
)
1275 new_mode
= MIN_MODE_VECTOR_UACCUM
;
1277 new_mode
= MIN_MODE_VECTOR_INT
;
1279 for (; new_mode
!= VOIDmode
; new_mode
= GET_MODE_WIDER_MODE (new_mode
))
1280 if (GET_MODE_SIZE (new_mode
) == GET_MODE_SIZE (GET_MODE (op0
))
1281 && targetm
.vector_mode_supported_p (new_mode
))
1283 if (new_mode
!= VOIDmode
)
1284 op0
= gen_lowpart (new_mode
, op0
);
1287 /* Use vec_extract patterns for extracting parts of vectors whenever
1289 if (VECTOR_MODE_P (GET_MODE (op0
))
1291 && optab_handler (vec_extract_optab
, GET_MODE (op0
)) != CODE_FOR_nothing
1292 && ((bitnum
+ bitsize
- 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
1293 == bitnum
/ GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
1295 struct expand_operand ops
[3];
1296 enum machine_mode outermode
= GET_MODE (op0
);
1297 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
1298 enum insn_code icode
= optab_handler (vec_extract_optab
, outermode
);
1299 unsigned HOST_WIDE_INT pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
1301 create_output_operand (&ops
[0], target
, innermode
);
1302 create_input_operand (&ops
[1], op0
, outermode
);
1303 create_integer_operand (&ops
[2], pos
);
1304 if (maybe_expand_insn (icode
, 3, ops
))
1306 target
= ops
[0].value
;
1307 if (GET_MODE (target
) != mode
)
1308 return gen_lowpart (tmode
, target
);
1313 /* Make sure we are playing with integral modes. Pun with subregs
1316 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1317 if (imode
!= GET_MODE (op0
))
1320 op0
= adjust_bitfield_address (op0
, imode
, 0);
1321 else if (imode
!= BLKmode
)
1323 op0
= gen_lowpart (imode
, op0
);
1325 /* If we got a SUBREG, force it into a register since we
1326 aren't going to be able to do another SUBREG on it. */
1327 if (GET_CODE (op0
) == SUBREG
)
1328 op0
= force_reg (imode
, op0
);
1330 else if (REG_P (op0
))
1333 imode
= smallest_mode_for_size (GET_MODE_BITSIZE (GET_MODE (op0
)),
1335 reg
= gen_reg_rtx (imode
);
1336 subreg
= gen_lowpart_SUBREG (GET_MODE (op0
), reg
);
1337 emit_move_insn (subreg
, op0
);
1339 bitnum
+= SUBREG_BYTE (subreg
) * BITS_PER_UNIT
;
1343 rtx mem
= assign_stack_temp (GET_MODE (op0
),
1344 GET_MODE_SIZE (GET_MODE (op0
)));
1345 emit_move_insn (mem
, op0
);
1346 op0
= adjust_bitfield_address (mem
, BLKmode
, 0);
1351 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1352 If that's wrong, the solution is to test for it and set TARGET to 0
1355 /* If the bitfield is volatile, we need to make sure the access
1356 remains on a type-aligned boundary. */
1357 if (GET_CODE (op0
) == MEM
1358 && MEM_VOLATILE_P (op0
)
1359 && GET_MODE_BITSIZE (GET_MODE (op0
)) > 0
1360 && flag_strict_volatile_bitfields
> 0)
1361 goto no_subreg_mode_swap
;
1363 /* Only scalar integer modes can be converted via subregs. There is an
1364 additional problem for FP modes here in that they can have a precision
1365 which is different from the size. mode_for_size uses precision, but
1366 we want a mode based on the size, so we must avoid calling it for FP
1369 if (SCALAR_INT_MODE_P (tmode
))
1371 enum machine_mode try_mode
= mode_for_size (bitsize
,
1372 GET_MODE_CLASS (tmode
), 0);
1373 if (try_mode
!= BLKmode
)
1376 gcc_assert (mode1
!= BLKmode
);
1378 /* Extraction of a full MODE1 value can be done with a subreg as long
1379 as the least significant bit of the value is the least significant
1380 bit of either OP0 or a word of OP0. */
1382 && lowpart_bit_field_p (bitnum
, bitsize
, GET_MODE (op0
))
1383 && bitsize
== GET_MODE_BITSIZE (mode1
)
1384 && TRULY_NOOP_TRUNCATION_MODES_P (mode1
, GET_MODE (op0
)))
1386 rtx sub
= simplify_gen_subreg (mode1
, op0
, GET_MODE (op0
),
1387 bitnum
/ BITS_PER_UNIT
);
1389 return convert_extracted_bit_field (sub
, mode
, tmode
, unsignedp
);
1392 /* Extraction of a full MODE1 value can be done with a load as long as
1393 the field is on a byte boundary and is sufficiently aligned. */
1395 && bitnum
% BITS_PER_UNIT
== 0
1396 && bitsize
== GET_MODE_BITSIZE (mode1
)
1397 && (!SLOW_UNALIGNED_ACCESS (mode1
, MEM_ALIGN (op0
))
1398 || (bitnum
% bitsize
== 0
1399 && MEM_ALIGN (op0
) % bitsize
== 0)))
1401 op0
= adjust_bitfield_address (op0
, mode1
, bitnum
/ BITS_PER_UNIT
);
1402 return convert_extracted_bit_field (op0
, mode
, tmode
, unsignedp
);
1405 no_subreg_mode_swap
:
1407 /* Handle fields bigger than a word. */
1409 if (bitsize
> BITS_PER_WORD
)
1411 /* Here we transfer the words of the field
1412 in the order least significant first.
1413 This is because the most significant word is the one which may
1414 be less than full. */
1416 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1420 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1421 target
= gen_reg_rtx (mode
);
1423 /* Indicate for flow that the entire target reg is being set. */
1424 emit_clobber (target
);
1426 last
= get_last_insn ();
1427 for (i
= 0; i
< nwords
; i
++)
1429 /* If I is 0, use the low-order word in both field and target;
1430 if I is 1, use the next to lowest word; and so on. */
1431 /* Word number in TARGET to use. */
1432 unsigned int wordnum
1434 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1436 /* Offset from start of field in OP0. */
1437 unsigned int bit_offset
= (WORDS_BIG_ENDIAN
1438 ? MAX (0, ((int) bitsize
- ((int) i
+ 1)
1439 * (int) BITS_PER_WORD
))
1440 : (int) i
* BITS_PER_WORD
);
1441 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1443 = extract_bit_field_1 (op0
, MIN (BITS_PER_WORD
,
1444 bitsize
- i
* BITS_PER_WORD
),
1445 bitnum
+ bit_offset
, 1, false, target_part
,
1446 mode
, word_mode
, fallback_p
);
1448 gcc_assert (target_part
);
1451 delete_insns_since (last
);
1455 if (result_part
!= target_part
)
1456 emit_move_insn (target_part
, result_part
);
1461 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1462 need to be zero'd out. */
1463 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1465 unsigned int i
, total_words
;
1467 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1468 for (i
= nwords
; i
< total_words
; i
++)
1470 (operand_subword (target
,
1471 WORDS_BIG_ENDIAN
? total_words
- i
- 1 : i
,
1478 /* Signed bit field: sign-extend with two arithmetic shifts. */
1479 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1480 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1481 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1482 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1485 /* If OP0 is a multi-word register, narrow it to the affected word.
1486 If the region spans two words, defer to extract_split_bit_field. */
1487 if (!MEM_P (op0
) && GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1489 op0
= simplify_gen_subreg (word_mode
, op0
, GET_MODE (op0
),
1490 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
1491 bitnum
%= BITS_PER_WORD
;
1492 if (bitnum
+ bitsize
> BITS_PER_WORD
)
1496 target
= extract_split_bit_field (op0
, bitsize
, bitnum
, unsignedp
);
1497 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1501 /* From here on we know the desired field is smaller than a word.
1502 If OP0 is a register, it too fits within a word. */
1504 ext_mode
= mode_for_extraction (unsignedp
? EP_extzv
: EP_extv
, 0);
1505 if (ext_mode
!= MAX_MACHINE_MODE
1507 && GET_MODE_BITSIZE (ext_mode
) >= bitsize
1508 /* Do not use extv/extzv for volatile bitfields when
1509 -fstrict-volatile-bitfields is in effect. */
1510 && !(MEM_P (op0
) && MEM_VOLATILE_P (op0
)
1511 && flag_strict_volatile_bitfields
> 0)
1512 /* If op0 is a register, we need it in EXT_MODE to make it
1513 acceptable to the format of ext(z)v. */
1514 && !(GET_CODE (op0
) == SUBREG
&& GET_MODE (op0
) != ext_mode
))
1516 struct expand_operand ops
[4];
1517 unsigned HOST_WIDE_INT bitpos
= bitnum
;
1519 rtx xtarget
= target
;
1520 rtx xspec_target
= target
;
1521 rtx xspec_target_subreg
= 0;
1522 unsigned unit
= GET_MODE_BITSIZE (ext_mode
);
1524 /* If op0 is a register, we need it in EXT_MODE to make it
1525 acceptable to the format of ext(z)v. */
1526 if (REG_P (xop0
) && GET_MODE (xop0
) != ext_mode
)
1527 xop0
= gen_lowpart_SUBREG (ext_mode
, xop0
);
1531 /* Get a reference to the first byte of the field. */
1532 xop0
= adjust_bitfield_address (xop0
, byte_mode
,
1533 bitpos
/ BITS_PER_UNIT
);
1534 bitpos
%= BITS_PER_UNIT
;
1538 /* Convert from counting within OP0 to counting in EXT_MODE. */
1539 if (BYTES_BIG_ENDIAN
)
1540 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1543 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1544 "backwards" from the size of the unit we are extracting from.
1545 Otherwise, we count bits from the most significant on a
1546 BYTES/BITS_BIG_ENDIAN machine. */
1548 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1549 bitpos
= unit
- bitsize
- bitpos
;
1552 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1554 if (GET_MODE (xtarget
) != ext_mode
)
1556 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1557 between the mode of the extraction (word_mode) and the target
1558 mode. Instead, create a temporary and use convert_move to set
1561 && TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (xtarget
), ext_mode
))
1563 xtarget
= gen_lowpart (ext_mode
, xtarget
);
1564 if (GET_MODE_PRECISION (ext_mode
)
1565 > GET_MODE_PRECISION (GET_MODE (xspec_target
)))
1566 xspec_target_subreg
= xtarget
;
1569 xtarget
= gen_reg_rtx (ext_mode
);
1572 create_output_operand (&ops
[0], xtarget
, ext_mode
);
1573 create_fixed_operand (&ops
[1], xop0
);
1574 create_integer_operand (&ops
[2], bitsize
);
1575 create_integer_operand (&ops
[3], bitpos
);
1576 if (maybe_expand_insn (unsignedp
? CODE_FOR_extzv
: CODE_FOR_extv
,
1579 xtarget
= ops
[0].value
;
1580 if (xtarget
== xspec_target
)
1582 if (xtarget
== xspec_target_subreg
)
1583 return xspec_target
;
1584 return convert_extracted_bit_field (xtarget
, mode
, tmode
, unsignedp
);
1588 /* If OP0 is a memory, try copying it to a register and seeing if a
1589 cheap register alternative is available. */
1590 if (ext_mode
!= MAX_MACHINE_MODE
&& MEM_P (op0
))
1592 enum machine_mode bestmode
;
1594 /* Get the mode to use for inserting into this field. If
1595 OP0 is BLKmode, get the smallest mode consistent with the
1596 alignment. If OP0 is a non-BLKmode object that is no
1597 wider than EXT_MODE, use its mode. Otherwise, use the
1598 smallest mode containing the field. */
1600 if (GET_MODE (op0
) == BLKmode
1601 || (ext_mode
!= MAX_MACHINE_MODE
1602 && GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (ext_mode
)))
1603 bestmode
= get_best_mode (bitsize
, bitnum
, 0, 0, MEM_ALIGN (op0
),
1604 (ext_mode
== MAX_MACHINE_MODE
1605 ? VOIDmode
: ext_mode
),
1606 MEM_VOLATILE_P (op0
));
1608 bestmode
= GET_MODE (op0
);
1610 if (bestmode
!= VOIDmode
1611 && !(SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (op0
))
1612 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (op0
)))
1614 unsigned HOST_WIDE_INT offset
, bitpos
;
1616 /* Compute the offset as a multiple of this unit,
1617 counting in bytes. */
1618 unsigned int unit
= GET_MODE_BITSIZE (bestmode
);
1619 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1620 bitpos
= bitnum
% unit
;
1622 /* Make sure the register is big enough for the whole field. */
1623 if (bitpos
+ bitsize
<= unit
)
1625 rtx last
, result
, xop0
;
1627 last
= get_last_insn ();
1629 /* Fetch it to a register in that size. */
1630 xop0
= adjust_bitfield_address (op0
, bestmode
, offset
);
1631 xop0
= force_reg (bestmode
, xop0
);
1632 result
= extract_bit_field_1 (xop0
, bitsize
, bitpos
,
1633 unsignedp
, packedp
, target
,
1634 mode
, tmode
, false);
1638 delete_insns_since (last
);
1646 /* Find a correspondingly-sized integer field, so we can apply
1647 shifts and masks to it. */
1648 int_mode
= int_mode_for_mode (tmode
);
1649 if (int_mode
== BLKmode
)
1650 int_mode
= int_mode_for_mode (mode
);
1651 /* Should probably push op0 out to memory and then do a load. */
1652 gcc_assert (int_mode
!= BLKmode
);
1654 target
= extract_fixed_bit_field (int_mode
, op0
, bitsize
, bitnum
,
1655 target
, unsignedp
, packedp
);
1656 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1659 /* Generate code to extract a byte-field from STR_RTX
1660 containing BITSIZE bits, starting at BITNUM,
1661 and put it in TARGET if possible (if TARGET is nonzero).
1662 Regardless of TARGET, we return the rtx for where the value is placed.
1664 STR_RTX is the structure containing the byte (a REG or MEM).
1665 UNSIGNEDP is nonzero if this is an unsigned bit field.
1666 PACKEDP is nonzero if the field has the packed attribute.
1667 MODE is the natural mode of the field value once extracted.
1668 TMODE is the mode the caller would like the value to have;
1669 but the value may be returned with type MODE instead.
1671 If a TARGET is specified and we can store in it at no extra cost,
1672 we do so, and return TARGET.
1673 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1674 if they are equally easy. */
1677 extract_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1678 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, bool packedp
,
1679 rtx target
, enum machine_mode mode
, enum machine_mode tmode
)
1681 return extract_bit_field_1 (str_rtx
, bitsize
, bitnum
, unsignedp
, packedp
,
1682 target
, mode
, tmode
, true);
1685 /* Use shifts and boolean operations to extract a field of BITSIZE bits
1686 from bit BITNUM of OP0.
1688 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1689 PACKEDP is true if the field has the packed attribute.
1691 If TARGET is nonzero, attempts to store the value there
1692 and return TARGET, but this is not guaranteed.
1693 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1696 extract_fixed_bit_field (enum machine_mode tmode
, rtx op0
,
1697 unsigned HOST_WIDE_INT bitsize
,
1698 unsigned HOST_WIDE_INT bitnum
, rtx target
,
1699 int unsignedp
, bool packedp
)
1701 enum machine_mode mode
;
1705 /* Get the proper mode to use for this field. We want a mode that
1706 includes the entire field. If such a mode would be larger than
1707 a word, we won't be doing the extraction the normal way. */
1709 if (MEM_VOLATILE_P (op0
)
1710 && flag_strict_volatile_bitfields
> 0)
1712 if (GET_MODE_BITSIZE (GET_MODE (op0
)) > 0)
1713 mode
= GET_MODE (op0
);
1714 else if (target
&& GET_MODE_BITSIZE (GET_MODE (target
)) > 0)
1715 mode
= GET_MODE (target
);
1720 mode
= get_best_mode (bitsize
, bitnum
, 0, 0,
1721 MEM_ALIGN (op0
), word_mode
, MEM_VOLATILE_P (op0
));
1723 if (mode
== VOIDmode
)
1724 /* The only way this should occur is if the field spans word
1726 return extract_split_bit_field (op0
, bitsize
, bitnum
, unsignedp
);
1728 unsigned int total_bits
= GET_MODE_BITSIZE (mode
);
1729 HOST_WIDE_INT bit_offset
= bitnum
- bitnum
% total_bits
;
1731 /* If we're accessing a volatile MEM, we can't apply BIT_OFFSET
1732 if it results in a multi-word access where we otherwise wouldn't
1733 have one. So, check for that case here. */
1735 && MEM_VOLATILE_P (op0
)
1736 && flag_strict_volatile_bitfields
> 0
1737 && bitnum
% BITS_PER_UNIT
+ bitsize
<= total_bits
1738 && bitnum
% GET_MODE_BITSIZE (mode
) + bitsize
> total_bits
)
1740 if (STRICT_ALIGNMENT
)
1742 static bool informed_about_misalignment
= false;
1746 if (bitsize
== total_bits
)
1747 warning_at (input_location
, OPT_fstrict_volatile_bitfields
,
1748 "multiple accesses to volatile structure"
1749 " member because of packed attribute");
1751 warning_at (input_location
, OPT_fstrict_volatile_bitfields
,
1752 "multiple accesses to volatile structure"
1753 " bitfield because of packed attribute");
1755 return extract_split_bit_field (op0
, bitsize
, bitnum
,
1759 if (bitsize
== total_bits
)
1760 warning_at (input_location
, OPT_fstrict_volatile_bitfields
,
1761 "mis-aligned access used for structure member");
1763 warning_at (input_location
, OPT_fstrict_volatile_bitfields
,
1764 "mis-aligned access used for structure bitfield");
1766 if (! informed_about_misalignment
)
1768 informed_about_misalignment
= true;
1769 inform (input_location
,
1770 "when a volatile object spans multiple type-sized"
1771 " locations, the compiler must choose between using"
1772 " a single mis-aligned access to preserve the"
1773 " volatility, or using multiple aligned accesses"
1774 " to avoid runtime faults; this code may fail at"
1775 " runtime if the hardware does not allow this"
1779 bit_offset
= bitnum
- bitnum
% BITS_PER_UNIT
;
1781 op0
= adjust_bitfield_address (op0
, mode
, bit_offset
/ BITS_PER_UNIT
);
1782 bitnum
-= bit_offset
;
1785 mode
= GET_MODE (op0
);
1786 gcc_assert (SCALAR_INT_MODE_P (mode
));
1788 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1789 for invalid input, such as extract equivalent of f5 from
1790 gcc.dg/pr48335-2.c. */
1792 if (BYTES_BIG_ENDIAN
)
1793 /* BITNUM is the distance between our msb and that of OP0.
1794 Convert it to the distance from the lsb. */
1795 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
1797 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
1798 We have reduced the big-endian case to the little-endian case. */
1804 /* If the field does not already start at the lsb,
1805 shift it so it does. */
1806 /* Maybe propagate the target for the shift. */
1807 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1810 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, bitnum
, subtarget
, 1);
1812 /* Convert the value to the desired mode. */
1814 op0
= convert_to_mode (tmode
, op0
, 1);
1816 /* Unless the msb of the field used to be the msb when we shifted,
1817 mask out the upper bits. */
1819 if (GET_MODE_BITSIZE (mode
) != bitnum
+ bitsize
)
1820 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1821 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1822 target
, 1, OPTAB_LIB_WIDEN
);
1826 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1827 then arithmetic-shift its lsb to the lsb of the word. */
1828 op0
= force_reg (mode
, op0
);
1830 /* Find the narrowest integer mode that contains the field. */
1832 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1833 mode
= GET_MODE_WIDER_MODE (mode
))
1834 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitnum
)
1836 op0
= convert_to_mode (mode
, op0
, 0);
1843 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitnum
))
1845 int amount
= GET_MODE_BITSIZE (mode
) - (bitsize
+ bitnum
);
1846 /* Maybe propagate the target for the shift. */
1847 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1848 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1851 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1852 GET_MODE_BITSIZE (mode
) - bitsize
, target
, 0);
1855 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1856 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1857 complement of that if COMPLEMENT. The mask is truncated if
1858 necessary to the width of mode MODE. The mask is zero-extended if
1859 BITSIZE+BITPOS is too small for MODE. */
1862 mask_rtx (enum machine_mode mode
, int bitpos
, int bitsize
, int complement
)
1866 mask
= double_int::mask (bitsize
);
1867 mask
= mask
.llshift (bitpos
, HOST_BITS_PER_DOUBLE_INT
);
1872 return immed_double_int_const (mask
, mode
);
1875 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1876 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1879 lshift_value (enum machine_mode mode
, rtx value
, int bitpos
, int bitsize
)
1883 val
= double_int::from_uhwi (INTVAL (value
)).zext (bitsize
);
1884 val
= val
.llshift (bitpos
, HOST_BITS_PER_DOUBLE_INT
);
1886 return immed_double_int_const (val
, mode
);
1889 /* Extract a bit field that is split across two words
1890 and return an RTX for the result.
1892 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1893 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1894 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1897 extract_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1898 unsigned HOST_WIDE_INT bitpos
, int unsignedp
)
1901 unsigned int bitsdone
= 0;
1902 rtx result
= NULL_RTX
;
1905 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1907 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1908 unit
= BITS_PER_WORD
;
1910 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1912 while (bitsdone
< bitsize
)
1914 unsigned HOST_WIDE_INT thissize
;
1916 unsigned HOST_WIDE_INT thispos
;
1917 unsigned HOST_WIDE_INT offset
;
1919 offset
= (bitpos
+ bitsdone
) / unit
;
1920 thispos
= (bitpos
+ bitsdone
) % unit
;
1922 /* THISSIZE must not overrun a word boundary. Otherwise,
1923 extract_fixed_bit_field will call us again, and we will mutually
1925 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1926 thissize
= MIN (thissize
, unit
- thispos
);
1928 /* If OP0 is a register, then handle OFFSET here.
1930 When handling multiword bitfields, extract_bit_field may pass
1931 down a word_mode SUBREG of a larger REG for a bitfield that actually
1932 crosses a word boundary. Thus, for a SUBREG, we must find
1933 the current word starting from the base register. */
1934 if (GET_CODE (op0
) == SUBREG
)
1936 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1937 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1938 GET_MODE (SUBREG_REG (op0
)));
1941 else if (REG_P (op0
))
1943 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1949 /* Extract the parts in bit-counting order,
1950 whose meaning is determined by BYTES_PER_UNIT.
1951 OFFSET is in UNITs, and UNIT is in bits. */
1952 part
= extract_fixed_bit_field (word_mode
, word
, thissize
,
1953 offset
* unit
+ thispos
, 0, 1, false);
1954 bitsdone
+= thissize
;
1956 /* Shift this part into place for the result. */
1957 if (BYTES_BIG_ENDIAN
)
1959 if (bitsize
!= bitsdone
)
1960 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1961 bitsize
- bitsdone
, 0, 1);
1965 if (bitsdone
!= thissize
)
1966 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1967 bitsdone
- thissize
, 0, 1);
1973 /* Combine the parts with bitwise or. This works
1974 because we extracted each part as an unsigned bit field. */
1975 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
1981 /* Unsigned bit field: we are done. */
1984 /* Signed bit field: sign-extend with two arithmetic shifts. */
1985 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
1986 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
1987 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
1988 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
1991 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
1992 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
1993 MODE, fill the upper bits with zeros. Fail if the layout of either
1994 mode is unknown (as for CC modes) or if the extraction would involve
1995 unprofitable mode punning. Return the value on success, otherwise
1998 This is different from gen_lowpart* in these respects:
2000 - the returned value must always be considered an rvalue
2002 - when MODE is wider than SRC_MODE, the extraction involves
2005 - when MODE is smaller than SRC_MODE, the extraction involves
2006 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
2008 In other words, this routine performs a computation, whereas the
2009 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2013 extract_low_bits (enum machine_mode mode
, enum machine_mode src_mode
, rtx src
)
2015 enum machine_mode int_mode
, src_int_mode
;
2017 if (mode
== src_mode
)
2020 if (CONSTANT_P (src
))
2022 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2023 fails, it will happily create (subreg (symbol_ref)) or similar
2025 unsigned int byte
= subreg_lowpart_offset (mode
, src_mode
);
2026 rtx ret
= simplify_subreg (mode
, src
, src_mode
, byte
);
2030 if (GET_MODE (src
) == VOIDmode
2031 || !validate_subreg (mode
, src_mode
, src
, byte
))
2034 src
= force_reg (GET_MODE (src
), src
);
2035 return gen_rtx_SUBREG (mode
, src
, byte
);
2038 if (GET_MODE_CLASS (mode
) == MODE_CC
|| GET_MODE_CLASS (src_mode
) == MODE_CC
)
2041 if (GET_MODE_BITSIZE (mode
) == GET_MODE_BITSIZE (src_mode
)
2042 && MODES_TIEABLE_P (mode
, src_mode
))
2044 rtx x
= gen_lowpart_common (mode
, src
);
2049 src_int_mode
= int_mode_for_mode (src_mode
);
2050 int_mode
= int_mode_for_mode (mode
);
2051 if (src_int_mode
== BLKmode
|| int_mode
== BLKmode
)
2054 if (!MODES_TIEABLE_P (src_int_mode
, src_mode
))
2056 if (!MODES_TIEABLE_P (int_mode
, mode
))
2059 src
= gen_lowpart (src_int_mode
, src
);
2060 src
= convert_modes (int_mode
, src_int_mode
, src
, true);
2061 src
= gen_lowpart (mode
, src
);
2065 /* Add INC into TARGET. */
2068 expand_inc (rtx target
, rtx inc
)
2070 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
2072 target
, 0, OPTAB_LIB_WIDEN
);
2073 if (value
!= target
)
2074 emit_move_insn (target
, value
);
2077 /* Subtract DEC from TARGET. */
2080 expand_dec (rtx target
, rtx dec
)
2082 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
2084 target
, 0, OPTAB_LIB_WIDEN
);
2085 if (value
!= target
)
2086 emit_move_insn (target
, value
);
2089 /* Output a shift instruction for expression code CODE,
2090 with SHIFTED being the rtx for the value to shift,
2091 and AMOUNT the rtx for the amount to shift by.
2092 Store the result in the rtx TARGET, if that is convenient.
2093 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2094 Return the rtx for where the value is. */
2097 expand_shift_1 (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2098 rtx amount
, rtx target
, int unsignedp
)
2101 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2102 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2103 optab lshift_optab
= ashl_optab
;
2104 optab rshift_arith_optab
= ashr_optab
;
2105 optab rshift_uns_optab
= lshr_optab
;
2106 optab lrotate_optab
= rotl_optab
;
2107 optab rrotate_optab
= rotr_optab
;
2108 enum machine_mode op1_mode
;
2110 bool speed
= optimize_insn_for_speed_p ();
2113 op1_mode
= GET_MODE (op1
);
2115 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2116 shift amount is a vector, use the vector/vector shift patterns. */
2117 if (VECTOR_MODE_P (mode
) && VECTOR_MODE_P (op1_mode
))
2119 lshift_optab
= vashl_optab
;
2120 rshift_arith_optab
= vashr_optab
;
2121 rshift_uns_optab
= vlshr_optab
;
2122 lrotate_optab
= vrotl_optab
;
2123 rrotate_optab
= vrotr_optab
;
2126 /* Previously detected shift-counts computed by NEGATE_EXPR
2127 and shifted in the other direction; but that does not work
2130 if (SHIFT_COUNT_TRUNCATED
)
2132 if (CONST_INT_P (op1
)
2133 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2134 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
2135 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
2136 % GET_MODE_BITSIZE (mode
));
2137 else if (GET_CODE (op1
) == SUBREG
2138 && subreg_lowpart_p (op1
)
2139 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (op1
))))
2140 op1
= SUBREG_REG (op1
);
2143 if (op1
== const0_rtx
)
2146 /* Check whether its cheaper to implement a left shift by a constant
2147 bit count by a sequence of additions. */
2148 if (code
== LSHIFT_EXPR
2149 && CONST_INT_P (op1
)
2151 && INTVAL (op1
) < GET_MODE_PRECISION (mode
)
2152 && INTVAL (op1
) < MAX_BITS_PER_WORD
2153 && (shift_cost (speed
, mode
, INTVAL (op1
))
2154 > INTVAL (op1
) * add_cost (speed
, mode
))
2155 && shift_cost (speed
, mode
, INTVAL (op1
)) != MAX_COST
)
2158 for (i
= 0; i
< INTVAL (op1
); i
++)
2160 temp
= force_reg (mode
, shifted
);
2161 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2162 unsignedp
, OPTAB_LIB_WIDEN
);
2167 for (attempt
= 0; temp
== 0 && attempt
< 3; attempt
++)
2169 enum optab_methods methods
;
2172 methods
= OPTAB_DIRECT
;
2173 else if (attempt
== 1)
2174 methods
= OPTAB_WIDEN
;
2176 methods
= OPTAB_LIB_WIDEN
;
2180 /* Widening does not work for rotation. */
2181 if (methods
== OPTAB_WIDEN
)
2183 else if (methods
== OPTAB_LIB_WIDEN
)
2185 /* If we have been unable to open-code this by a rotation,
2186 do it as the IOR of two shifts. I.e., to rotate A
2187 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2188 where C is the bitsize of A.
2190 It is theoretically possible that the target machine might
2191 not be able to perform either shift and hence we would
2192 be making two libcalls rather than just the one for the
2193 shift (similarly if IOR could not be done). We will allow
2194 this extremely unlikely lossage to avoid complicating the
2197 rtx subtarget
= target
== shifted
? 0 : target
;
2198 rtx new_amount
, other_amount
;
2202 if (CONST_INT_P (op1
))
2203 other_amount
= GEN_INT (GET_MODE_BITSIZE (mode
)
2207 = simplify_gen_binary (MINUS
, GET_MODE (op1
),
2208 GEN_INT (GET_MODE_PRECISION (mode
)),
2211 shifted
= force_reg (mode
, shifted
);
2213 temp
= expand_shift_1 (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2214 mode
, shifted
, new_amount
, 0, 1);
2215 temp1
= expand_shift_1 (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2216 mode
, shifted
, other_amount
,
2218 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2219 unsignedp
, methods
);
2222 temp
= expand_binop (mode
,
2223 left
? lrotate_optab
: rrotate_optab
,
2224 shifted
, op1
, target
, unsignedp
, methods
);
2227 temp
= expand_binop (mode
,
2228 left
? lshift_optab
: rshift_uns_optab
,
2229 shifted
, op1
, target
, unsignedp
, methods
);
2231 /* Do arithmetic shifts.
2232 Also, if we are going to widen the operand, we can just as well
2233 use an arithmetic right-shift instead of a logical one. */
2234 if (temp
== 0 && ! rotate
2235 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2237 enum optab_methods methods1
= methods
;
2239 /* If trying to widen a log shift to an arithmetic shift,
2240 don't accept an arithmetic shift of the same size. */
2242 methods1
= OPTAB_MUST_WIDEN
;
2244 /* Arithmetic shift */
2246 temp
= expand_binop (mode
,
2247 left
? lshift_optab
: rshift_arith_optab
,
2248 shifted
, op1
, target
, unsignedp
, methods1
);
2251 /* We used to try extzv here for logical right shifts, but that was
2252 only useful for one machine, the VAX, and caused poor code
2253 generation there for lshrdi3, so the code was deleted and a
2254 define_expand for lshrsi3 was added to vax.md. */
2261 /* Output a shift instruction for expression code CODE,
2262 with SHIFTED being the rtx for the value to shift,
2263 and AMOUNT the amount to shift by.
2264 Store the result in the rtx TARGET, if that is convenient.
2265 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2266 Return the rtx for where the value is. */
2269 expand_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2270 int amount
, rtx target
, int unsignedp
)
2272 return expand_shift_1 (code
, mode
,
2273 shifted
, GEN_INT (amount
), target
, unsignedp
);
2276 /* Output a shift instruction for expression code CODE,
2277 with SHIFTED being the rtx for the value to shift,
2278 and AMOUNT the tree for the amount to shift by.
2279 Store the result in the rtx TARGET, if that is convenient.
2280 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2281 Return the rtx for where the value is. */
2284 expand_variable_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2285 tree amount
, rtx target
, int unsignedp
)
2287 return expand_shift_1 (code
, mode
,
2288 shifted
, expand_normal (amount
), target
, unsignedp
);
2292 /* Indicates the type of fixup needed after a constant multiplication.
2293 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2294 the result should be negated, and ADD_VARIANT means that the
2295 multiplicand should be added to the result. */
2296 enum mult_variant
{basic_variant
, negate_variant
, add_variant
};
2298 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2299 const struct mult_cost
*, enum machine_mode mode
);
2300 static bool choose_mult_variant (enum machine_mode
, HOST_WIDE_INT
,
2301 struct algorithm
*, enum mult_variant
*, int);
2302 static rtx
expand_mult_const (enum machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2303 const struct algorithm
*, enum mult_variant
);
2304 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2305 static rtx
extract_high_half (enum machine_mode
, rtx
);
2306 static rtx
expmed_mult_highpart (enum machine_mode
, rtx
, rtx
, rtx
, int, int);
2307 static rtx
expmed_mult_highpart_optab (enum machine_mode
, rtx
, rtx
, rtx
,
2309 /* Compute and return the best algorithm for multiplying by T.
2310 The algorithm must cost less than cost_limit
2311 If retval.cost >= COST_LIMIT, no algorithm was found and all
2312 other field of the returned struct are undefined.
2313 MODE is the machine mode of the multiplication. */
2316 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2317 const struct mult_cost
*cost_limit
, enum machine_mode mode
)
2320 struct algorithm
*alg_in
, *best_alg
;
2321 struct mult_cost best_cost
;
2322 struct mult_cost new_limit
;
2323 int op_cost
, op_latency
;
2324 unsigned HOST_WIDE_INT orig_t
= t
;
2325 unsigned HOST_WIDE_INT q
;
2326 int maxm
, hash_index
;
2327 bool cache_hit
= false;
2328 enum alg_code cache_alg
= alg_zero
;
2329 bool speed
= optimize_insn_for_speed_p ();
2330 enum machine_mode imode
;
2331 struct alg_hash_entry
*entry_ptr
;
2333 /* Indicate that no algorithm is yet found. If no algorithm
2334 is found, this value will be returned and indicate failure. */
2335 alg_out
->cost
.cost
= cost_limit
->cost
+ 1;
2336 alg_out
->cost
.latency
= cost_limit
->latency
+ 1;
2338 if (cost_limit
->cost
< 0
2339 || (cost_limit
->cost
== 0 && cost_limit
->latency
<= 0))
2342 /* Be prepared for vector modes. */
2343 imode
= GET_MODE_INNER (mode
);
2344 if (imode
== VOIDmode
)
2347 maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (imode
));
2349 /* Restrict the bits of "t" to the multiplication's mode. */
2350 t
&= GET_MODE_MASK (imode
);
2352 /* t == 1 can be done in zero cost. */
2356 alg_out
->cost
.cost
= 0;
2357 alg_out
->cost
.latency
= 0;
2358 alg_out
->op
[0] = alg_m
;
2362 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2366 if (MULT_COST_LESS (cost_limit
, zero_cost (speed
)))
2371 alg_out
->cost
.cost
= zero_cost (speed
);
2372 alg_out
->cost
.latency
= zero_cost (speed
);
2373 alg_out
->op
[0] = alg_zero
;
2378 /* We'll be needing a couple extra algorithm structures now. */
2380 alg_in
= XALLOCA (struct algorithm
);
2381 best_alg
= XALLOCA (struct algorithm
);
2382 best_cost
= *cost_limit
;
2384 /* Compute the hash index. */
2385 hash_index
= (t
^ (unsigned int) mode
^ (speed
* 256)) % NUM_ALG_HASH_ENTRIES
;
2387 /* See if we already know what to do for T. */
2388 entry_ptr
= alg_hash_entry_ptr (hash_index
);
2389 if (entry_ptr
->t
== t
2390 && entry_ptr
->mode
== mode
2391 && entry_ptr
->mode
== mode
2392 && entry_ptr
->speed
== speed
2393 && entry_ptr
->alg
!= alg_unknown
)
2395 cache_alg
= entry_ptr
->alg
;
2397 if (cache_alg
== alg_impossible
)
2399 /* The cache tells us that it's impossible to synthesize
2400 multiplication by T within entry_ptr->cost. */
2401 if (!CHEAPER_MULT_COST (&entry_ptr
->cost
, cost_limit
))
2402 /* COST_LIMIT is at least as restrictive as the one
2403 recorded in the hash table, in which case we have no
2404 hope of synthesizing a multiplication. Just
2408 /* If we get here, COST_LIMIT is less restrictive than the
2409 one recorded in the hash table, so we may be able to
2410 synthesize a multiplication. Proceed as if we didn't
2411 have the cache entry. */
2415 if (CHEAPER_MULT_COST (cost_limit
, &entry_ptr
->cost
))
2416 /* The cached algorithm shows that this multiplication
2417 requires more cost than COST_LIMIT. Just return. This
2418 way, we don't clobber this cache entry with
2419 alg_impossible but retain useful information. */
2431 goto do_alg_addsub_t_m2
;
2433 case alg_add_factor
:
2434 case alg_sub_factor
:
2435 goto do_alg_addsub_factor
;
2438 goto do_alg_add_t2_m
;
2441 goto do_alg_sub_t2_m
;
2449 /* If we have a group of zero bits at the low-order part of T, try
2450 multiplying by the remaining bits and then doing a shift. */
2455 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2459 /* The function expand_shift will choose between a shift and
2460 a sequence of additions, so the observed cost is given as
2461 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2462 op_cost
= m
* add_cost (speed
, mode
);
2463 if (shift_cost (speed
, mode
, m
) < op_cost
)
2464 op_cost
= shift_cost (speed
, mode
, m
);
2465 new_limit
.cost
= best_cost
.cost
- op_cost
;
2466 new_limit
.latency
= best_cost
.latency
- op_cost
;
2467 synth_mult (alg_in
, q
, &new_limit
, mode
);
2469 alg_in
->cost
.cost
+= op_cost
;
2470 alg_in
->cost
.latency
+= op_cost
;
2471 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2473 struct algorithm
*x
;
2474 best_cost
= alg_in
->cost
;
2475 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2476 best_alg
->log
[best_alg
->ops
] = m
;
2477 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2480 /* See if treating ORIG_T as a signed number yields a better
2481 sequence. Try this sequence only for a negative ORIG_T
2482 as it would be useless for a non-negative ORIG_T. */
2483 if ((HOST_WIDE_INT
) orig_t
< 0)
2485 /* Shift ORIG_T as follows because a right shift of a
2486 negative-valued signed type is implementation
2488 q
= ~(~orig_t
>> m
);
2489 /* The function expand_shift will choose between a shift
2490 and a sequence of additions, so the observed cost is
2491 given as MIN (m * add_cost(speed, mode),
2492 shift_cost(speed, mode, m)). */
2493 op_cost
= m
* add_cost (speed
, mode
);
2494 if (shift_cost (speed
, mode
, m
) < op_cost
)
2495 op_cost
= shift_cost (speed
, mode
, m
);
2496 new_limit
.cost
= best_cost
.cost
- op_cost
;
2497 new_limit
.latency
= best_cost
.latency
- op_cost
;
2498 synth_mult (alg_in
, q
, &new_limit
, mode
);
2500 alg_in
->cost
.cost
+= op_cost
;
2501 alg_in
->cost
.latency
+= op_cost
;
2502 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2504 struct algorithm
*x
;
2505 best_cost
= alg_in
->cost
;
2506 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2507 best_alg
->log
[best_alg
->ops
] = m
;
2508 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2516 /* If we have an odd number, add or subtract one. */
2519 unsigned HOST_WIDE_INT w
;
2522 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2524 /* If T was -1, then W will be zero after the loop. This is another
2525 case where T ends with ...111. Handling this with (T + 1) and
2526 subtract 1 produces slightly better code and results in algorithm
2527 selection much faster than treating it like the ...0111 case
2531 /* Reject the case where t is 3.
2532 Thus we prefer addition in that case. */
2535 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2537 op_cost
= add_cost (speed
, mode
);
2538 new_limit
.cost
= best_cost
.cost
- op_cost
;
2539 new_limit
.latency
= best_cost
.latency
- op_cost
;
2540 synth_mult (alg_in
, t
+ 1, &new_limit
, mode
);
2542 alg_in
->cost
.cost
+= op_cost
;
2543 alg_in
->cost
.latency
+= op_cost
;
2544 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2546 struct algorithm
*x
;
2547 best_cost
= alg_in
->cost
;
2548 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2549 best_alg
->log
[best_alg
->ops
] = 0;
2550 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2555 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2557 op_cost
= add_cost (speed
, mode
);
2558 new_limit
.cost
= best_cost
.cost
- op_cost
;
2559 new_limit
.latency
= best_cost
.latency
- op_cost
;
2560 synth_mult (alg_in
, t
- 1, &new_limit
, mode
);
2562 alg_in
->cost
.cost
+= op_cost
;
2563 alg_in
->cost
.latency
+= op_cost
;
2564 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2566 struct algorithm
*x
;
2567 best_cost
= alg_in
->cost
;
2568 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2569 best_alg
->log
[best_alg
->ops
] = 0;
2570 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2574 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2575 quickly with a - a * n for some appropriate constant n. */
2576 m
= exact_log2 (-orig_t
+ 1);
2577 if (m
>= 0 && m
< maxm
)
2579 op_cost
= shiftsub1_cost (speed
, mode
, m
);
2580 new_limit
.cost
= best_cost
.cost
- op_cost
;
2581 new_limit
.latency
= best_cost
.latency
- op_cost
;
2582 synth_mult (alg_in
, (unsigned HOST_WIDE_INT
) (-orig_t
+ 1) >> m
,
2585 alg_in
->cost
.cost
+= op_cost
;
2586 alg_in
->cost
.latency
+= op_cost
;
2587 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2589 struct algorithm
*x
;
2590 best_cost
= alg_in
->cost
;
2591 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2592 best_alg
->log
[best_alg
->ops
] = m
;
2593 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2601 /* Look for factors of t of the form
2602 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2603 If we find such a factor, we can multiply by t using an algorithm that
2604 multiplies by q, shift the result by m and add/subtract it to itself.
2606 We search for large factors first and loop down, even if large factors
2607 are less probable than small; if we find a large factor we will find a
2608 good sequence quickly, and therefore be able to prune (by decreasing
2609 COST_LIMIT) the search. */
2611 do_alg_addsub_factor
:
2612 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2614 unsigned HOST_WIDE_INT d
;
2616 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2617 if (t
% d
== 0 && t
> d
&& m
< maxm
2618 && (!cache_hit
|| cache_alg
== alg_add_factor
))
2620 /* If the target has a cheap shift-and-add instruction use
2621 that in preference to a shift insn followed by an add insn.
2622 Assume that the shift-and-add is "atomic" with a latency
2623 equal to its cost, otherwise assume that on superscalar
2624 hardware the shift may be executed concurrently with the
2625 earlier steps in the algorithm. */
2626 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2627 if (shiftadd_cost (speed
, mode
, m
) < op_cost
)
2629 op_cost
= shiftadd_cost (speed
, mode
, m
);
2630 op_latency
= op_cost
;
2633 op_latency
= add_cost (speed
, mode
);
2635 new_limit
.cost
= best_cost
.cost
- op_cost
;
2636 new_limit
.latency
= best_cost
.latency
- op_latency
;
2637 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2639 alg_in
->cost
.cost
+= op_cost
;
2640 alg_in
->cost
.latency
+= op_latency
;
2641 if (alg_in
->cost
.latency
< op_cost
)
2642 alg_in
->cost
.latency
= op_cost
;
2643 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2645 struct algorithm
*x
;
2646 best_cost
= alg_in
->cost
;
2647 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2648 best_alg
->log
[best_alg
->ops
] = m
;
2649 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2651 /* Other factors will have been taken care of in the recursion. */
2655 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2656 if (t
% d
== 0 && t
> d
&& m
< maxm
2657 && (!cache_hit
|| cache_alg
== alg_sub_factor
))
2659 /* If the target has a cheap shift-and-subtract insn use
2660 that in preference to a shift insn followed by a sub insn.
2661 Assume that the shift-and-sub is "atomic" with a latency
2662 equal to it's cost, otherwise assume that on superscalar
2663 hardware the shift may be executed concurrently with the
2664 earlier steps in the algorithm. */
2665 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2666 if (shiftsub0_cost (speed
, mode
, m
) < op_cost
)
2668 op_cost
= shiftsub0_cost (speed
, mode
, m
);
2669 op_latency
= op_cost
;
2672 op_latency
= add_cost (speed
, mode
);
2674 new_limit
.cost
= best_cost
.cost
- op_cost
;
2675 new_limit
.latency
= best_cost
.latency
- op_latency
;
2676 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2678 alg_in
->cost
.cost
+= op_cost
;
2679 alg_in
->cost
.latency
+= op_latency
;
2680 if (alg_in
->cost
.latency
< op_cost
)
2681 alg_in
->cost
.latency
= op_cost
;
2682 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2684 struct algorithm
*x
;
2685 best_cost
= alg_in
->cost
;
2686 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2687 best_alg
->log
[best_alg
->ops
] = m
;
2688 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2696 /* Try shift-and-add (load effective address) instructions,
2697 i.e. do a*3, a*5, a*9. */
2704 if (m
>= 0 && m
< maxm
)
2706 op_cost
= shiftadd_cost (speed
, mode
, m
);
2707 new_limit
.cost
= best_cost
.cost
- op_cost
;
2708 new_limit
.latency
= best_cost
.latency
- op_cost
;
2709 synth_mult (alg_in
, (t
- 1) >> m
, &new_limit
, mode
);
2711 alg_in
->cost
.cost
+= op_cost
;
2712 alg_in
->cost
.latency
+= op_cost
;
2713 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2715 struct algorithm
*x
;
2716 best_cost
= alg_in
->cost
;
2717 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2718 best_alg
->log
[best_alg
->ops
] = m
;
2719 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2729 if (m
>= 0 && m
< maxm
)
2731 op_cost
= shiftsub0_cost (speed
, mode
, m
);
2732 new_limit
.cost
= best_cost
.cost
- op_cost
;
2733 new_limit
.latency
= best_cost
.latency
- op_cost
;
2734 synth_mult (alg_in
, (t
+ 1) >> m
, &new_limit
, mode
);
2736 alg_in
->cost
.cost
+= op_cost
;
2737 alg_in
->cost
.latency
+= op_cost
;
2738 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2740 struct algorithm
*x
;
2741 best_cost
= alg_in
->cost
;
2742 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2743 best_alg
->log
[best_alg
->ops
] = m
;
2744 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2752 /* If best_cost has not decreased, we have not found any algorithm. */
2753 if (!CHEAPER_MULT_COST (&best_cost
, cost_limit
))
2755 /* We failed to find an algorithm. Record alg_impossible for
2756 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2757 we are asked to find an algorithm for T within the same or
2758 lower COST_LIMIT, we can immediately return to the
2761 entry_ptr
->mode
= mode
;
2762 entry_ptr
->speed
= speed
;
2763 entry_ptr
->alg
= alg_impossible
;
2764 entry_ptr
->cost
= *cost_limit
;
2768 /* Cache the result. */
2772 entry_ptr
->mode
= mode
;
2773 entry_ptr
->speed
= speed
;
2774 entry_ptr
->alg
= best_alg
->op
[best_alg
->ops
];
2775 entry_ptr
->cost
.cost
= best_cost
.cost
;
2776 entry_ptr
->cost
.latency
= best_cost
.latency
;
2779 /* If we are getting a too long sequence for `struct algorithm'
2780 to record, make this search fail. */
2781 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2784 /* Copy the algorithm from temporary space to the space at alg_out.
2785 We avoid using structure assignment because the majority of
2786 best_alg is normally undefined, and this is a critical function. */
2787 alg_out
->ops
= best_alg
->ops
+ 1;
2788 alg_out
->cost
= best_cost
;
2789 memcpy (alg_out
->op
, best_alg
->op
,
2790 alg_out
->ops
* sizeof *alg_out
->op
);
2791 memcpy (alg_out
->log
, best_alg
->log
,
2792 alg_out
->ops
* sizeof *alg_out
->log
);
2795 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2796 Try three variations:
2798 - a shift/add sequence based on VAL itself
2799 - a shift/add sequence based on -VAL, followed by a negation
2800 - a shift/add sequence based on VAL - 1, followed by an addition.
2802 Return true if the cheapest of these cost less than MULT_COST,
2803 describing the algorithm in *ALG and final fixup in *VARIANT. */
2806 choose_mult_variant (enum machine_mode mode
, HOST_WIDE_INT val
,
2807 struct algorithm
*alg
, enum mult_variant
*variant
,
2810 struct algorithm alg2
;
2811 struct mult_cost limit
;
2813 bool speed
= optimize_insn_for_speed_p ();
2815 /* Fail quickly for impossible bounds. */
2819 /* Ensure that mult_cost provides a reasonable upper bound.
2820 Any constant multiplication can be performed with less
2821 than 2 * bits additions. */
2822 op_cost
= 2 * GET_MODE_UNIT_BITSIZE (mode
) * add_cost (speed
, mode
);
2823 if (mult_cost
> op_cost
)
2824 mult_cost
= op_cost
;
2826 *variant
= basic_variant
;
2827 limit
.cost
= mult_cost
;
2828 limit
.latency
= mult_cost
;
2829 synth_mult (alg
, val
, &limit
, mode
);
2831 /* This works only if the inverted value actually fits in an
2833 if (HOST_BITS_PER_INT
>= GET_MODE_UNIT_BITSIZE (mode
))
2835 op_cost
= neg_cost(speed
, mode
);
2836 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2838 limit
.cost
= alg
->cost
.cost
- op_cost
;
2839 limit
.latency
= alg
->cost
.latency
- op_cost
;
2843 limit
.cost
= mult_cost
- op_cost
;
2844 limit
.latency
= mult_cost
- op_cost
;
2847 synth_mult (&alg2
, -val
, &limit
, mode
);
2848 alg2
.cost
.cost
+= op_cost
;
2849 alg2
.cost
.latency
+= op_cost
;
2850 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2851 *alg
= alg2
, *variant
= negate_variant
;
2854 /* This proves very useful for division-by-constant. */
2855 op_cost
= add_cost (speed
, mode
);
2856 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2858 limit
.cost
= alg
->cost
.cost
- op_cost
;
2859 limit
.latency
= alg
->cost
.latency
- op_cost
;
2863 limit
.cost
= mult_cost
- op_cost
;
2864 limit
.latency
= mult_cost
- op_cost
;
2867 synth_mult (&alg2
, val
- 1, &limit
, mode
);
2868 alg2
.cost
.cost
+= op_cost
;
2869 alg2
.cost
.latency
+= op_cost
;
2870 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2871 *alg
= alg2
, *variant
= add_variant
;
2873 return MULT_COST_LESS (&alg
->cost
, mult_cost
);
2876 /* A subroutine of expand_mult, used for constant multiplications.
2877 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2878 convenient. Use the shift/add sequence described by ALG and apply
2879 the final fixup specified by VARIANT. */
2882 expand_mult_const (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
2883 rtx target
, const struct algorithm
*alg
,
2884 enum mult_variant variant
)
2886 HOST_WIDE_INT val_so_far
;
2887 rtx insn
, accum
, tem
;
2889 enum machine_mode nmode
;
2891 /* Avoid referencing memory over and over and invalid sharing
2893 op0
= force_reg (mode
, op0
);
2895 /* ACCUM starts out either as OP0 or as a zero, depending on
2896 the first operation. */
2898 if (alg
->op
[0] == alg_zero
)
2900 accum
= copy_to_mode_reg (mode
, CONST0_RTX (mode
));
2903 else if (alg
->op
[0] == alg_m
)
2905 accum
= copy_to_mode_reg (mode
, op0
);
2911 for (opno
= 1; opno
< alg
->ops
; opno
++)
2913 int log
= alg
->log
[opno
];
2914 rtx shift_subtarget
= optimize
? 0 : accum
;
2916 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
2919 rtx accum_target
= optimize
? 0 : accum
;
2922 switch (alg
->op
[opno
])
2925 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
2926 /* REG_EQUAL note will be attached to the following insn. */
2927 emit_move_insn (accum
, tem
);
2932 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
2933 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2934 add_target
? add_target
: accum_target
);
2935 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2939 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
2940 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2941 add_target
? add_target
: accum_target
);
2942 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2946 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2947 log
, shift_subtarget
, 0);
2948 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2949 add_target
? add_target
: accum_target
);
2950 val_so_far
= (val_so_far
<< log
) + 1;
2954 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2955 log
, shift_subtarget
, 0);
2956 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2957 add_target
? add_target
: accum_target
);
2958 val_so_far
= (val_so_far
<< log
) - 1;
2961 case alg_add_factor
:
2962 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
2963 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2964 add_target
? add_target
: accum_target
);
2965 val_so_far
+= val_so_far
<< log
;
2968 case alg_sub_factor
:
2969 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
2970 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2972 ? add_target
: (optimize
? 0 : tem
)));
2973 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2980 if (SCALAR_INT_MODE_P (mode
))
2982 /* Write a REG_EQUAL note on the last insn so that we can cse
2983 multiplication sequences. Note that if ACCUM is a SUBREG,
2984 we've set the inner register and must properly indicate that. */
2985 tem
= op0
, nmode
= mode
;
2986 accum_inner
= accum
;
2987 if (GET_CODE (accum
) == SUBREG
)
2989 accum_inner
= SUBREG_REG (accum
);
2990 nmode
= GET_MODE (accum_inner
);
2991 tem
= gen_lowpart (nmode
, op0
);
2994 insn
= get_last_insn ();
2995 set_dst_reg_note (insn
, REG_EQUAL
,
2996 gen_rtx_MULT (nmode
, tem
, GEN_INT (val_so_far
)),
3001 if (variant
== negate_variant
)
3003 val_so_far
= -val_so_far
;
3004 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
3006 else if (variant
== add_variant
)
3008 val_so_far
= val_so_far
+ 1;
3009 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
3012 /* Compare only the bits of val and val_so_far that are significant
3013 in the result mode, to avoid sign-/zero-extension confusion. */
3014 nmode
= GET_MODE_INNER (mode
);
3015 if (nmode
== VOIDmode
)
3017 val
&= GET_MODE_MASK (nmode
);
3018 val_so_far
&= GET_MODE_MASK (nmode
);
3019 gcc_assert (val
== val_so_far
);
3024 /* Perform a multiplication and return an rtx for the result.
3025 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3026 TARGET is a suggestion for where to store the result (an rtx).
3028 We check specially for a constant integer as OP1.
3029 If you want this check for OP0 as well, then before calling
3030 you should swap the two operands if OP0 would be constant. */
3033 expand_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3036 enum mult_variant variant
;
3037 struct algorithm algorithm
;
3040 bool speed
= optimize_insn_for_speed_p ();
3041 bool do_trapv
= flag_trapv
&& SCALAR_INT_MODE_P (mode
) && !unsignedp
;
3043 if (CONSTANT_P (op0
))
3050 /* For vectors, there are several simplifications that can be made if
3051 all elements of the vector constant are identical. */
3053 if (GET_CODE (op1
) == CONST_VECTOR
)
3055 int i
, n
= CONST_VECTOR_NUNITS (op1
);
3056 scalar_op1
= CONST_VECTOR_ELT (op1
, 0);
3057 for (i
= 1; i
< n
; ++i
)
3058 if (!rtx_equal_p (scalar_op1
, CONST_VECTOR_ELT (op1
, i
)))
3062 if (INTEGRAL_MODE_P (mode
))
3065 HOST_WIDE_INT coeff
;
3069 if (op1
== CONST0_RTX (mode
))
3071 if (op1
== CONST1_RTX (mode
))
3073 if (op1
== CONSTM1_RTX (mode
))
3074 return expand_unop (mode
, do_trapv
? negv_optab
: neg_optab
,
3080 /* These are the operations that are potentially turned into
3081 a sequence of shifts and additions. */
3082 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
3084 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3085 less than or equal in size to `unsigned int' this doesn't matter.
3086 If the mode is larger than `unsigned int', then synth_mult works
3087 only if the constant value exactly fits in an `unsigned int' without
3088 any truncation. This means that multiplying by negative values does
3089 not work; results are off by 2^32 on a 32 bit machine. */
3091 if (CONST_INT_P (scalar_op1
))
3093 coeff
= INTVAL (scalar_op1
);
3096 else if (CONST_DOUBLE_AS_INT_P (scalar_op1
))
3098 /* If we are multiplying in DImode, it may still be a win
3099 to try to work with shifts and adds. */
3100 if (CONST_DOUBLE_HIGH (scalar_op1
) == 0
3101 && CONST_DOUBLE_LOW (scalar_op1
) > 0)
3103 coeff
= CONST_DOUBLE_LOW (scalar_op1
);
3106 else if (CONST_DOUBLE_LOW (scalar_op1
) == 0)
3108 coeff
= CONST_DOUBLE_HIGH (scalar_op1
);
3109 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3111 int shift
= floor_log2 (coeff
) + HOST_BITS_PER_WIDE_INT
;
3112 if (shift
< HOST_BITS_PER_DOUBLE_INT
- 1
3113 || mode_bitsize
<= HOST_BITS_PER_DOUBLE_INT
)
3114 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3115 shift
, target
, unsignedp
);
3125 /* We used to test optimize here, on the grounds that it's better to
3126 produce a smaller program when -O is not used. But this causes
3127 such a terrible slowdown sometimes that it seems better to always
3130 /* Special case powers of two. */
3131 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3132 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3133 floor_log2 (coeff
), target
, unsignedp
);
3135 fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3137 /* Attempt to handle multiplication of DImode values by negative
3138 coefficients, by performing the multiplication by a positive
3139 multiplier and then inverting the result. */
3140 if (is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
)
3142 /* Its safe to use -coeff even for INT_MIN, as the
3143 result is interpreted as an unsigned coefficient.
3144 Exclude cost of op0 from max_cost to match the cost
3145 calculation of the synth_mult. */
3146 max_cost
= (set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), speed
)
3147 - neg_cost(speed
, mode
));
3149 && choose_mult_variant (mode
, -coeff
, &algorithm
,
3150 &variant
, max_cost
))
3152 rtx temp
= expand_mult_const (mode
, op0
, -coeff
, NULL_RTX
,
3153 &algorithm
, variant
);
3154 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3159 /* Exclude cost of op0 from max_cost to match the cost
3160 calculation of the synth_mult. */
3161 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), speed
);
3162 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3163 return expand_mult_const (mode
, op0
, coeff
, target
,
3164 &algorithm
, variant
);
3168 /* Expand x*2.0 as x+x. */
3169 if (CONST_DOUBLE_AS_FLOAT_P (scalar_op1
))
3172 REAL_VALUE_FROM_CONST_DOUBLE (d
, scalar_op1
);
3174 if (REAL_VALUES_EQUAL (d
, dconst2
))
3176 op0
= force_reg (GET_MODE (op0
), op0
);
3177 return expand_binop (mode
, add_optab
, op0
, op0
,
3178 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3183 /* This used to use umul_optab if unsigned, but for non-widening multiply
3184 there is no difference between signed and unsigned. */
3185 op0
= expand_binop (mode
, do_trapv
? smulv_optab
: smul_optab
,
3186 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
3191 /* Return a cost estimate for multiplying a register by the given
3192 COEFFicient in the given MODE and SPEED. */
3195 mult_by_coeff_cost (HOST_WIDE_INT coeff
, enum machine_mode mode
, bool speed
)
3198 struct algorithm algorithm
;
3199 enum mult_variant variant
;
3201 rtx fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3202 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, fake_reg
), speed
);
3203 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3204 return algorithm
.cost
.cost
;
3209 /* Perform a widening multiplication and return an rtx for the result.
3210 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3211 TARGET is a suggestion for where to store the result (an rtx).
3212 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3213 or smul_widen_optab.
3215 We check specially for a constant integer as OP1, comparing the
3216 cost of a widening multiply against the cost of a sequence of shifts
3220 expand_widening_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3221 int unsignedp
, optab this_optab
)
3223 bool speed
= optimize_insn_for_speed_p ();
3226 if (CONST_INT_P (op1
)
3227 && GET_MODE (op0
) != VOIDmode
3228 && (cop1
= convert_modes (mode
, GET_MODE (op0
), op1
,
3229 this_optab
== umul_widen_optab
))
3230 && CONST_INT_P (cop1
)
3231 && (INTVAL (cop1
) >= 0
3232 || HWI_COMPUTABLE_MODE_P (mode
)))
3234 HOST_WIDE_INT coeff
= INTVAL (cop1
);
3236 enum mult_variant variant
;
3237 struct algorithm algorithm
;
3239 /* Special case powers of two. */
3240 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3242 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3243 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3244 floor_log2 (coeff
), target
, unsignedp
);
3247 /* Exclude cost of op0 from max_cost to match the cost
3248 calculation of the synth_mult. */
3249 max_cost
= mul_widen_cost (speed
, mode
);
3250 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3253 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3254 return expand_mult_const (mode
, op0
, coeff
, target
,
3255 &algorithm
, variant
);
3258 return expand_binop (mode
, this_optab
, op0
, op1
, target
,
3259 unsignedp
, OPTAB_LIB_WIDEN
);
3262 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3263 replace division by D, and put the least significant N bits of the result
3264 in *MULTIPLIER_PTR and return the most significant bit.
3266 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3267 needed precision is in PRECISION (should be <= N).
3269 PRECISION should be as small as possible so this function can choose
3270 multiplier more freely.
3272 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3273 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3275 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3276 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3278 unsigned HOST_WIDE_INT
3279 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
3280 unsigned HOST_WIDE_INT
*multiplier_ptr
,
3281 int *post_shift_ptr
, int *lgup_ptr
)
3283 double_int mhigh
, mlow
;
3284 int lgup
, post_shift
;
3287 /* lgup = ceil(log2(divisor)); */
3288 lgup
= ceil_log2 (d
);
3290 gcc_assert (lgup
<= n
);
3293 pow2
= n
+ lgup
- precision
;
3295 /* We could handle this with some effort, but this case is much
3296 better handled directly with a scc insn, so rely on caller using
3298 gcc_assert (pow
!= HOST_BITS_PER_DOUBLE_INT
);
3300 /* mlow = 2^(N + lgup)/d */
3301 double_int val
= double_int_zero
.set_bit (pow
);
3302 mlow
= val
.div (double_int::from_uhwi (d
), true, TRUNC_DIV_EXPR
);
3304 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3305 val
|= double_int_zero
.set_bit (pow2
);
3306 mhigh
= val
.div (double_int::from_uhwi (d
), true, TRUNC_DIV_EXPR
);
3308 gcc_assert (!mhigh
.high
|| val
.high
- d
< d
);
3309 gcc_assert (mhigh
.high
<= 1 && mlow
.high
<= 1);
3310 /* Assert that mlow < mhigh. */
3311 gcc_assert (mlow
.ult (mhigh
));
3313 /* If precision == N, then mlow, mhigh exceed 2^N
3314 (but they do not exceed 2^(N+1)). */
3316 /* Reduce to lowest terms. */
3317 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
3319 int shft
= HOST_BITS_PER_WIDE_INT
- 1;
3320 unsigned HOST_WIDE_INT ml_lo
= (mlow
.high
<< shft
) | (mlow
.low
>> 1);
3321 unsigned HOST_WIDE_INT mh_lo
= (mhigh
.high
<< shft
) | (mhigh
.low
>> 1);
3325 mlow
= double_int::from_uhwi (ml_lo
);
3326 mhigh
= double_int::from_uhwi (mh_lo
);
3329 *post_shift_ptr
= post_shift
;
3331 if (n
< HOST_BITS_PER_WIDE_INT
)
3333 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
3334 *multiplier_ptr
= mhigh
.low
& mask
;
3335 return mhigh
.low
>= mask
;
3339 *multiplier_ptr
= mhigh
.low
;
3344 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3345 congruent to 1 (mod 2**N). */
3347 static unsigned HOST_WIDE_INT
3348 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
3350 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3352 /* The algorithm notes that the choice y = x satisfies
3353 x*y == 1 mod 2^3, since x is assumed odd.
3354 Each iteration doubles the number of bits of significance in y. */
3356 unsigned HOST_WIDE_INT mask
;
3357 unsigned HOST_WIDE_INT y
= x
;
3360 mask
= (n
== HOST_BITS_PER_WIDE_INT
3361 ? ~(unsigned HOST_WIDE_INT
) 0
3362 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
3366 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
3372 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3373 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3374 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3375 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3378 The result is put in TARGET if that is convenient.
3380 MODE is the mode of operation. */
3383 expand_mult_highpart_adjust (enum machine_mode mode
, rtx adj_operand
, rtx op0
,
3384 rtx op1
, rtx target
, int unsignedp
)
3387 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
3389 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3390 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3391 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
3393 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3396 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
3397 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3398 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
3399 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3405 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3408 extract_high_half (enum machine_mode mode
, rtx op
)
3410 enum machine_mode wider_mode
;
3412 if (mode
== word_mode
)
3413 return gen_highpart (mode
, op
);
3415 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3417 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3418 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
3419 GET_MODE_BITSIZE (mode
), 0, 1);
3420 return convert_modes (mode
, wider_mode
, op
, 0);
3423 /* Like expmed_mult_highpart, but only consider using a multiplication
3424 optab. OP1 is an rtx for the constant operand. */
3427 expmed_mult_highpart_optab (enum machine_mode mode
, rtx op0
, rtx op1
,
3428 rtx target
, int unsignedp
, int max_cost
)
3430 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
3431 enum machine_mode wider_mode
;
3435 bool speed
= optimize_insn_for_speed_p ();
3437 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3439 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3440 size
= GET_MODE_BITSIZE (mode
);
3442 /* Firstly, try using a multiplication insn that only generates the needed
3443 high part of the product, and in the sign flavor of unsignedp. */
3444 if (mul_highpart_cost (speed
, mode
) < max_cost
)
3446 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
3447 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3448 unsignedp
, OPTAB_DIRECT
);
3453 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3454 Need to adjust the result after the multiplication. */
3455 if (size
- 1 < BITS_PER_WORD
3456 && (mul_highpart_cost (speed
, mode
)
3457 + 2 * shift_cost (speed
, mode
, size
-1)
3458 + 4 * add_cost (speed
, mode
) < max_cost
))
3460 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
3461 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3462 unsignedp
, OPTAB_DIRECT
);
3464 /* We used the wrong signedness. Adjust the result. */
3465 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3469 /* Try widening multiplication. */
3470 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
3471 if (widening_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3472 && mul_widen_cost (speed
, wider_mode
) < max_cost
)
3474 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
3475 unsignedp
, OPTAB_WIDEN
);
3477 return extract_high_half (mode
, tem
);
3480 /* Try widening the mode and perform a non-widening multiplication. */
3481 if (optab_handler (smul_optab
, wider_mode
) != CODE_FOR_nothing
3482 && size
- 1 < BITS_PER_WORD
3483 && (mul_cost (speed
, wider_mode
) + shift_cost (speed
, mode
, size
-1)
3486 rtx insns
, wop0
, wop1
;
3488 /* We need to widen the operands, for example to ensure the
3489 constant multiplier is correctly sign or zero extended.
3490 Use a sequence to clean-up any instructions emitted by
3491 the conversions if things don't work out. */
3493 wop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
3494 wop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
3495 tem
= expand_binop (wider_mode
, smul_optab
, wop0
, wop1
, 0,
3496 unsignedp
, OPTAB_WIDEN
);
3497 insns
= get_insns ();
3503 return extract_high_half (mode
, tem
);
3507 /* Try widening multiplication of opposite signedness, and adjust. */
3508 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3509 if (widening_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3510 && size
- 1 < BITS_PER_WORD
3511 && (mul_widen_cost (speed
, wider_mode
)
3512 + 2 * shift_cost (speed
, mode
, size
-1)
3513 + 4 * add_cost (speed
, mode
) < max_cost
))
3515 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3516 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3519 tem
= extract_high_half (mode
, tem
);
3520 /* We used the wrong signedness. Adjust the result. */
3521 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3529 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3530 putting the high half of the result in TARGET if that is convenient,
3531 and return where the result is. If the operation can not be performed,
3534 MODE is the mode of operation and result.
3536 UNSIGNEDP nonzero means unsigned multiply.
3538 MAX_COST is the total allowed cost for the expanded RTL. */
3541 expmed_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
3542 rtx target
, int unsignedp
, int max_cost
)
3544 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
3545 unsigned HOST_WIDE_INT cnst1
;
3547 bool sign_adjust
= false;
3548 enum mult_variant variant
;
3549 struct algorithm alg
;
3551 bool speed
= optimize_insn_for_speed_p ();
3553 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3554 /* We can't support modes wider than HOST_BITS_PER_INT. */
3555 gcc_assert (HWI_COMPUTABLE_MODE_P (mode
));
3557 cnst1
= INTVAL (op1
) & GET_MODE_MASK (mode
);
3559 /* We can't optimize modes wider than BITS_PER_WORD.
3560 ??? We might be able to perform double-word arithmetic if
3561 mode == word_mode, however all the cost calculations in
3562 synth_mult etc. assume single-word operations. */
3563 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3564 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3565 unsignedp
, max_cost
);
3567 extra_cost
= shift_cost (speed
, mode
, GET_MODE_BITSIZE (mode
) - 1);
3569 /* Check whether we try to multiply by a negative constant. */
3570 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3573 extra_cost
+= add_cost (speed
, mode
);
3576 /* See whether shift/add multiplication is cheap enough. */
3577 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3578 max_cost
- extra_cost
))
3580 /* See whether the specialized multiplication optabs are
3581 cheaper than the shift/add version. */
3582 tem
= expmed_mult_highpart_optab (mode
, op0
, op1
, target
, unsignedp
,
3583 alg
.cost
.cost
+ extra_cost
);
3587 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3588 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3589 tem
= extract_high_half (mode
, tem
);
3591 /* Adjust result for signedness. */
3593 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3597 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3598 unsignedp
, max_cost
);
3602 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3605 expand_smod_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3607 unsigned HOST_WIDE_INT masklow
, maskhigh
;
3608 rtx result
, temp
, shift
, label
;
3611 logd
= floor_log2 (d
);
3612 result
= gen_reg_rtx (mode
);
3614 /* Avoid conditional branches when they're expensive. */
3615 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3616 && optimize_insn_for_speed_p ())
3618 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3622 signmask
= force_reg (mode
, signmask
);
3623 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3624 shift
= GEN_INT (GET_MODE_BITSIZE (mode
) - logd
);
3626 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3627 which instruction sequence to use. If logical right shifts
3628 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3629 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3631 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3632 if (optab_handler (lshr_optab
, mode
) == CODE_FOR_nothing
3633 || (set_src_cost (temp
, optimize_insn_for_speed_p ())
3634 > COSTS_N_INSNS (2)))
3636 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3637 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3638 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3639 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3640 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (masklow
),
3641 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3642 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3643 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3644 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3645 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3649 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3650 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3651 signmask
= force_reg (mode
, signmask
);
3653 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3654 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3655 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (masklow
),
3656 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3657 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3658 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3664 /* Mask contains the mode's signbit and the significant bits of the
3665 modulus. By including the signbit in the operation, many targets
3666 can avoid an explicit compare operation in the following comparison
3669 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3670 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3672 masklow
|= (HOST_WIDE_INT
) -1 << (GET_MODE_BITSIZE (mode
) - 1);
3676 maskhigh
= (HOST_WIDE_INT
) -1
3677 << (GET_MODE_BITSIZE (mode
) - HOST_BITS_PER_WIDE_INT
- 1);
3679 temp
= expand_binop (mode
, and_optab
, op0
,
3680 immed_double_const (masklow
, maskhigh
, mode
),
3681 result
, 1, OPTAB_LIB_WIDEN
);
3683 emit_move_insn (result
, temp
);
3685 label
= gen_label_rtx ();
3686 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
3688 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
3689 0, OPTAB_LIB_WIDEN
);
3690 masklow
= (HOST_WIDE_INT
) -1 << logd
;
3692 temp
= expand_binop (mode
, ior_optab
, temp
,
3693 immed_double_const (masklow
, maskhigh
, mode
),
3694 result
, 1, OPTAB_LIB_WIDEN
);
3695 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
3696 0, OPTAB_LIB_WIDEN
);
3698 emit_move_insn (result
, temp
);
3703 /* Expand signed division of OP0 by a power of two D in mode MODE.
3704 This routine is only called for positive values of D. */
3707 expand_sdiv_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3712 logd
= floor_log2 (d
);
3715 && BRANCH_COST (optimize_insn_for_speed_p (),
3718 temp
= gen_reg_rtx (mode
);
3719 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
3720 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3721 0, OPTAB_LIB_WIDEN
);
3722 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3725 #ifdef HAVE_conditional_move
3726 if (BRANCH_COST (optimize_insn_for_speed_p (), false)
3731 /* ??? emit_conditional_move forces a stack adjustment via
3732 compare_from_rtx so, if the sequence is discarded, it will
3733 be lost. Do it now instead. */
3734 do_pending_stack_adjust ();
3737 temp2
= copy_to_mode_reg (mode
, op0
);
3738 temp
= expand_binop (mode
, add_optab
, temp2
, GEN_INT (d
-1),
3739 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3740 temp
= force_reg (mode
, temp
);
3742 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3743 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
3744 mode
, temp
, temp2
, mode
, 0);
3747 rtx seq
= get_insns ();
3750 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, logd
, NULL_RTX
, 0);
3756 if (BRANCH_COST (optimize_insn_for_speed_p (),
3759 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
3761 temp
= gen_reg_rtx (mode
);
3762 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
3763 if (shift_cost (optimize_insn_for_speed_p (), mode
, ushift
)
3764 > COSTS_N_INSNS (1))
3765 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (d
- 1),
3766 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3768 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
3769 ushift
, NULL_RTX
, 1);
3770 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3771 0, OPTAB_LIB_WIDEN
);
3772 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3775 label
= gen_label_rtx ();
3776 temp
= copy_to_mode_reg (mode
, op0
);
3777 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
3778 expand_inc (temp
, GEN_INT (d
- 1));
3780 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3783 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3784 if that is convenient, and returning where the result is.
3785 You may request either the quotient or the remainder as the result;
3786 specify REM_FLAG nonzero to get the remainder.
3788 CODE is the expression code for which kind of division this is;
3789 it controls how rounding is done. MODE is the machine mode to use.
3790 UNSIGNEDP nonzero means do unsigned division. */
3792 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3793 and then correct it by or'ing in missing high bits
3794 if result of ANDI is nonzero.
3795 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3796 This could optimize to a bfexts instruction.
3797 But C doesn't use these operations, so their optimizations are
3799 /* ??? For modulo, we don't actually need the highpart of the first product,
3800 the low part will do nicely. And for small divisors, the second multiply
3801 can also be a low-part only multiply or even be completely left out.
3802 E.g. to calculate the remainder of a division by 3 with a 32 bit
3803 multiply, multiply with 0x55555556 and extract the upper two bits;
3804 the result is exact for inputs up to 0x1fffffff.
3805 The input range can be reduced by using cross-sum rules.
3806 For odd divisors >= 3, the following table gives right shift counts
3807 so that if a number is shifted by an integer multiple of the given
3808 amount, the remainder stays the same:
3809 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3810 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3811 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3812 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3813 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3815 Cross-sum rules for even numbers can be derived by leaving as many bits
3816 to the right alone as the divisor has zeros to the right.
3817 E.g. if x is an unsigned 32 bit number:
3818 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3822 expand_divmod (int rem_flag
, enum tree_code code
, enum machine_mode mode
,
3823 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
3825 enum machine_mode compute_mode
;
3827 rtx quotient
= 0, remainder
= 0;
3831 optab optab1
, optab2
;
3832 int op1_is_constant
, op1_is_pow2
= 0;
3833 int max_cost
, extra_cost
;
3834 static HOST_WIDE_INT last_div_const
= 0;
3835 static HOST_WIDE_INT ext_op1
;
3836 bool speed
= optimize_insn_for_speed_p ();
3838 op1_is_constant
= CONST_INT_P (op1
);
3839 if (op1_is_constant
)
3841 ext_op1
= INTVAL (op1
);
3843 ext_op1
&= GET_MODE_MASK (mode
);
3844 op1_is_pow2
= ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1
)
3845 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1
))));
3849 This is the structure of expand_divmod:
3851 First comes code to fix up the operands so we can perform the operations
3852 correctly and efficiently.
3854 Second comes a switch statement with code specific for each rounding mode.
3855 For some special operands this code emits all RTL for the desired
3856 operation, for other cases, it generates only a quotient and stores it in
3857 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3858 to indicate that it has not done anything.
3860 Last comes code that finishes the operation. If QUOTIENT is set and
3861 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3862 QUOTIENT is not set, it is computed using trunc rounding.
3864 We try to generate special code for division and remainder when OP1 is a
3865 constant. If |OP1| = 2**n we can use shifts and some other fast
3866 operations. For other values of OP1, we compute a carefully selected
3867 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3870 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3871 half of the product. Different strategies for generating the product are
3872 implemented in expmed_mult_highpart.
3874 If what we actually want is the remainder, we generate that by another
3875 by-constant multiplication and a subtraction. */
3877 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3878 code below will malfunction if we are, so check here and handle
3879 the special case if so. */
3880 if (op1
== const1_rtx
)
3881 return rem_flag
? const0_rtx
: op0
;
3883 /* When dividing by -1, we could get an overflow.
3884 negv_optab can handle overflows. */
3885 if (! unsignedp
&& op1
== constm1_rtx
)
3889 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
3890 ? negv_optab
: neg_optab
, op0
, target
, 0);
3894 /* Don't use the function value register as a target
3895 since we have to read it as well as write it,
3896 and function-inlining gets confused by this. */
3897 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3898 /* Don't clobber an operand while doing a multi-step calculation. */
3899 || ((rem_flag
|| op1_is_constant
)
3900 && (reg_mentioned_p (target
, op0
)
3901 || (MEM_P (op0
) && MEM_P (target
))))
3902 || reg_mentioned_p (target
, op1
)
3903 || (MEM_P (op1
) && MEM_P (target
))))
3906 /* Get the mode in which to perform this computation. Normally it will
3907 be MODE, but sometimes we can't do the desired operation in MODE.
3908 If so, pick a wider mode in which we can do the operation. Convert
3909 to that mode at the start to avoid repeated conversions.
3911 First see what operations we need. These depend on the expression
3912 we are evaluating. (We assume that divxx3 insns exist under the
3913 same conditions that modxx3 insns and that these insns don't normally
3914 fail. If these assumptions are not correct, we may generate less
3915 efficient code in some cases.)
3917 Then see if we find a mode in which we can open-code that operation
3918 (either a division, modulus, or shift). Finally, check for the smallest
3919 mode for which we can do the operation with a library call. */
3921 /* We might want to refine this now that we have division-by-constant
3922 optimization. Since expmed_mult_highpart tries so many variants, it is
3923 not straightforward to generalize this. Maybe we should make an array
3924 of possible modes in init_expmed? Save this for GCC 2.7. */
3926 optab1
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3927 ? (unsignedp
? lshr_optab
: ashr_optab
)
3928 : (unsignedp
? udiv_optab
: sdiv_optab
));
3929 optab2
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3931 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
3933 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3934 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3935 if (optab_handler (optab1
, compute_mode
) != CODE_FOR_nothing
3936 || optab_handler (optab2
, compute_mode
) != CODE_FOR_nothing
)
3939 if (compute_mode
== VOIDmode
)
3940 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3941 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3942 if (optab_libfunc (optab1
, compute_mode
)
3943 || optab_libfunc (optab2
, compute_mode
))
3946 /* If we still couldn't find a mode, use MODE, but expand_binop will
3948 if (compute_mode
== VOIDmode
)
3949 compute_mode
= mode
;
3951 if (target
&& GET_MODE (target
) == compute_mode
)
3954 tquotient
= gen_reg_rtx (compute_mode
);
3956 size
= GET_MODE_BITSIZE (compute_mode
);
3958 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3959 (mode), and thereby get better code when OP1 is a constant. Do that
3960 later. It will require going over all usages of SIZE below. */
3961 size
= GET_MODE_BITSIZE (mode
);
3964 /* Only deduct something for a REM if the last divide done was
3965 for a different constant. Then set the constant of the last
3967 max_cost
= (unsignedp
3968 ? udiv_cost (speed
, compute_mode
)
3969 : sdiv_cost (speed
, compute_mode
));
3970 if (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3971 && INTVAL (op1
) == last_div_const
))
3972 max_cost
-= (mul_cost (speed
, compute_mode
)
3973 + add_cost (speed
, compute_mode
));
3975 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3977 /* Now convert to the best mode to use. */
3978 if (compute_mode
!= mode
)
3980 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3981 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3983 /* convert_modes may have placed op1 into a register, so we
3984 must recompute the following. */
3985 op1_is_constant
= CONST_INT_P (op1
);
3986 op1_is_pow2
= (op1_is_constant
3987 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3989 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
)))))) ;
3992 /* If one of the operands is a volatile MEM, copy it into a register. */
3994 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
3995 op0
= force_reg (compute_mode
, op0
);
3996 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
3997 op1
= force_reg (compute_mode
, op1
);
3999 /* If we need the remainder or if OP1 is constant, we need to
4000 put OP0 in a register in case it has any queued subexpressions. */
4001 if (rem_flag
|| op1_is_constant
)
4002 op0
= force_reg (compute_mode
, op0
);
4004 last
= get_last_insn ();
4006 /* Promote floor rounding to trunc rounding for unsigned operations. */
4009 if (code
== FLOOR_DIV_EXPR
)
4010 code
= TRUNC_DIV_EXPR
;
4011 if (code
== FLOOR_MOD_EXPR
)
4012 code
= TRUNC_MOD_EXPR
;
4013 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
4014 code
= TRUNC_DIV_EXPR
;
4017 if (op1
!= const0_rtx
)
4020 case TRUNC_MOD_EXPR
:
4021 case TRUNC_DIV_EXPR
:
4022 if (op1_is_constant
)
4026 unsigned HOST_WIDE_INT mh
, ml
;
4027 int pre_shift
, post_shift
;
4029 unsigned HOST_WIDE_INT d
= (INTVAL (op1
)
4030 & GET_MODE_MASK (compute_mode
));
4032 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4034 pre_shift
= floor_log2 (d
);
4038 = expand_binop (compute_mode
, and_optab
, op0
,
4039 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
4043 return gen_lowpart (mode
, remainder
);
4045 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4046 pre_shift
, tquotient
, 1);
4048 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4050 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
4052 /* Most significant bit of divisor is set; emit an scc
4054 quotient
= emit_store_flag_force (tquotient
, GEU
, op0
, op1
,
4055 compute_mode
, 1, 1);
4059 /* Find a suitable multiplier and right shift count
4060 instead of multiplying with D. */
4062 mh
= choose_multiplier (d
, size
, size
,
4063 &ml
, &post_shift
, &dummy
);
4065 /* If the suggested multiplier is more than SIZE bits,
4066 we can do better for even divisors, using an
4067 initial right shift. */
4068 if (mh
!= 0 && (d
& 1) == 0)
4070 pre_shift
= floor_log2 (d
& -d
);
4071 mh
= choose_multiplier (d
>> pre_shift
, size
,
4073 &ml
, &post_shift
, &dummy
);
4083 if (post_shift
- 1 >= BITS_PER_WORD
)
4087 = (shift_cost (speed
, compute_mode
, post_shift
- 1)
4088 + shift_cost (speed
, compute_mode
, 1)
4089 + 2 * add_cost (speed
, compute_mode
));
4090 t1
= expmed_mult_highpart (compute_mode
, op0
,
4093 max_cost
- extra_cost
);
4096 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
4099 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
,
4100 t2
, 1, NULL_RTX
, 1);
4101 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
4104 quotient
= expand_shift
4105 (RSHIFT_EXPR
, compute_mode
, t4
,
4106 post_shift
- 1, tquotient
, 1);
4112 if (pre_shift
>= BITS_PER_WORD
4113 || post_shift
>= BITS_PER_WORD
)
4117 (RSHIFT_EXPR
, compute_mode
, op0
,
4118 pre_shift
, NULL_RTX
, 1);
4120 = (shift_cost (speed
, compute_mode
, pre_shift
)
4121 + shift_cost (speed
, compute_mode
, post_shift
));
4122 t2
= expmed_mult_highpart (compute_mode
, t1
,
4125 max_cost
- extra_cost
);
4128 quotient
= expand_shift
4129 (RSHIFT_EXPR
, compute_mode
, t2
,
4130 post_shift
, tquotient
, 1);
4134 else /* Too wide mode to use tricky code */
4137 insn
= get_last_insn ();
4139 set_dst_reg_note (insn
, REG_EQUAL
,
4140 gen_rtx_UDIV (compute_mode
, op0
, op1
),
4143 else /* TRUNC_DIV, signed */
4145 unsigned HOST_WIDE_INT ml
;
4146 int lgup
, post_shift
;
4148 HOST_WIDE_INT d
= INTVAL (op1
);
4149 unsigned HOST_WIDE_INT abs_d
;
4151 /* Since d might be INT_MIN, we have to cast to
4152 unsigned HOST_WIDE_INT before negating to avoid
4153 undefined signed overflow. */
4155 ? (unsigned HOST_WIDE_INT
) d
4156 : - (unsigned HOST_WIDE_INT
) d
);
4158 /* n rem d = n rem -d */
4159 if (rem_flag
&& d
< 0)
4162 op1
= gen_int_mode (abs_d
, compute_mode
);
4168 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
4170 else if (HOST_BITS_PER_WIDE_INT
>= size
4171 && abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4173 /* This case is not handled correctly below. */
4174 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
4175 compute_mode
, 1, 1);
4179 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
4181 ? smod_pow2_cheap (speed
, compute_mode
)
4182 : sdiv_pow2_cheap (speed
, compute_mode
))
4183 /* We assume that cheap metric is true if the
4184 optab has an expander for this mode. */
4185 && ((optab_handler ((rem_flag
? smod_optab
4188 != CODE_FOR_nothing
)
4189 || (optab_handler (sdivmod_optab
,
4191 != CODE_FOR_nothing
)))
4193 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
4197 remainder
= expand_smod_pow2 (compute_mode
, op0
, d
);
4199 return gen_lowpart (mode
, remainder
);
4202 if (sdiv_pow2_cheap (speed
, compute_mode
)
4203 && ((optab_handler (sdiv_optab
, compute_mode
)
4204 != CODE_FOR_nothing
)
4205 || (optab_handler (sdivmod_optab
, compute_mode
)
4206 != CODE_FOR_nothing
)))
4207 quotient
= expand_divmod (0, TRUNC_DIV_EXPR
,
4209 gen_int_mode (abs_d
,
4213 quotient
= expand_sdiv_pow2 (compute_mode
, op0
, abs_d
);
4215 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4216 negate the quotient. */
4219 insn
= get_last_insn ();
4221 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
4222 << (HOST_BITS_PER_WIDE_INT
- 1)))
4223 set_dst_reg_note (insn
, REG_EQUAL
,
4224 gen_rtx_DIV (compute_mode
, op0
,
4230 quotient
= expand_unop (compute_mode
, neg_optab
,
4231 quotient
, quotient
, 0);
4234 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4236 choose_multiplier (abs_d
, size
, size
- 1,
4237 &ml
, &post_shift
, &lgup
);
4238 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4242 if (post_shift
>= BITS_PER_WORD
4243 || size
- 1 >= BITS_PER_WORD
)
4246 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4247 + shift_cost (speed
, compute_mode
, size
- 1)
4248 + add_cost (speed
, compute_mode
));
4249 t1
= expmed_mult_highpart (compute_mode
, op0
,
4250 GEN_INT (ml
), NULL_RTX
, 0,
4251 max_cost
- extra_cost
);
4255 (RSHIFT_EXPR
, compute_mode
, t1
,
4256 post_shift
, NULL_RTX
, 0);
4258 (RSHIFT_EXPR
, compute_mode
, op0
,
4259 size
- 1, NULL_RTX
, 0);
4262 = force_operand (gen_rtx_MINUS (compute_mode
,
4267 = force_operand (gen_rtx_MINUS (compute_mode
,
4275 if (post_shift
>= BITS_PER_WORD
4276 || size
- 1 >= BITS_PER_WORD
)
4279 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
4280 mlr
= gen_int_mode (ml
, compute_mode
);
4281 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4282 + shift_cost (speed
, compute_mode
, size
- 1)
4283 + 2 * add_cost (speed
, compute_mode
));
4284 t1
= expmed_mult_highpart (compute_mode
, op0
, mlr
,
4286 max_cost
- extra_cost
);
4289 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
4293 (RSHIFT_EXPR
, compute_mode
, t2
,
4294 post_shift
, NULL_RTX
, 0);
4296 (RSHIFT_EXPR
, compute_mode
, op0
,
4297 size
- 1, NULL_RTX
, 0);
4300 = force_operand (gen_rtx_MINUS (compute_mode
,
4305 = force_operand (gen_rtx_MINUS (compute_mode
,
4310 else /* Too wide mode to use tricky code */
4313 insn
= get_last_insn ();
4315 set_dst_reg_note (insn
, REG_EQUAL
,
4316 gen_rtx_DIV (compute_mode
, op0
, op1
),
4322 delete_insns_since (last
);
4325 case FLOOR_DIV_EXPR
:
4326 case FLOOR_MOD_EXPR
:
4327 /* We will come here only for signed operations. */
4328 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4330 unsigned HOST_WIDE_INT mh
, ml
;
4331 int pre_shift
, lgup
, post_shift
;
4332 HOST_WIDE_INT d
= INTVAL (op1
);
4336 /* We could just as easily deal with negative constants here,
4337 but it does not seem worth the trouble for GCC 2.6. */
4338 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4340 pre_shift
= floor_log2 (d
);
4343 remainder
= expand_binop (compute_mode
, and_optab
, op0
,
4344 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
4345 remainder
, 0, OPTAB_LIB_WIDEN
);
4347 return gen_lowpart (mode
, remainder
);
4349 quotient
= expand_shift
4350 (RSHIFT_EXPR
, compute_mode
, op0
,
4351 pre_shift
, tquotient
, 0);
4357 mh
= choose_multiplier (d
, size
, size
- 1,
4358 &ml
, &post_shift
, &lgup
);
4361 if (post_shift
< BITS_PER_WORD
4362 && size
- 1 < BITS_PER_WORD
)
4365 (RSHIFT_EXPR
, compute_mode
, op0
,
4366 size
- 1, NULL_RTX
, 0);
4367 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
4368 NULL_RTX
, 0, OPTAB_WIDEN
);
4369 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4370 + shift_cost (speed
, compute_mode
, size
- 1)
4371 + 2 * add_cost (speed
, compute_mode
));
4372 t3
= expmed_mult_highpart (compute_mode
, t2
,
4373 GEN_INT (ml
), NULL_RTX
, 1,
4374 max_cost
- extra_cost
);
4378 (RSHIFT_EXPR
, compute_mode
, t3
,
4379 post_shift
, NULL_RTX
, 1);
4380 quotient
= expand_binop (compute_mode
, xor_optab
,
4381 t4
, t1
, tquotient
, 0,
4389 rtx nsign
, t1
, t2
, t3
, t4
;
4390 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
4391 op0
, constm1_rtx
), NULL_RTX
);
4392 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
4394 nsign
= expand_shift
4395 (RSHIFT_EXPR
, compute_mode
, t2
,
4396 size
- 1, NULL_RTX
, 0);
4397 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
4399 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
4404 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
4406 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4415 delete_insns_since (last
);
4417 /* Try using an instruction that produces both the quotient and
4418 remainder, using truncation. We can easily compensate the quotient
4419 or remainder to get floor rounding, once we have the remainder.
4420 Notice that we compute also the final remainder value here,
4421 and return the result right away. */
4422 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4423 target
= gen_reg_rtx (compute_mode
);
4428 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4429 quotient
= gen_reg_rtx (compute_mode
);
4434 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4435 remainder
= gen_reg_rtx (compute_mode
);
4438 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
4439 quotient
, remainder
, 0))
4441 /* This could be computed with a branch-less sequence.
4442 Save that for later. */
4444 rtx label
= gen_label_rtx ();
4445 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
4446 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4447 NULL_RTX
, 0, OPTAB_WIDEN
);
4448 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
4449 expand_dec (quotient
, const1_rtx
);
4450 expand_inc (remainder
, op1
);
4452 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4455 /* No luck with division elimination or divmod. Have to do it
4456 by conditionally adjusting op0 *and* the result. */
4458 rtx label1
, label2
, label3
, label4
, label5
;
4462 quotient
= gen_reg_rtx (compute_mode
);
4463 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4464 label1
= gen_label_rtx ();
4465 label2
= gen_label_rtx ();
4466 label3
= gen_label_rtx ();
4467 label4
= gen_label_rtx ();
4468 label5
= gen_label_rtx ();
4469 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4470 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
4471 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4472 quotient
, 0, OPTAB_LIB_WIDEN
);
4473 if (tem
!= quotient
)
4474 emit_move_insn (quotient
, tem
);
4475 emit_jump_insn (gen_jump (label5
));
4477 emit_label (label1
);
4478 expand_inc (adjusted_op0
, const1_rtx
);
4479 emit_jump_insn (gen_jump (label4
));
4481 emit_label (label2
);
4482 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
4483 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4484 quotient
, 0, OPTAB_LIB_WIDEN
);
4485 if (tem
!= quotient
)
4486 emit_move_insn (quotient
, tem
);
4487 emit_jump_insn (gen_jump (label5
));
4489 emit_label (label3
);
4490 expand_dec (adjusted_op0
, const1_rtx
);
4491 emit_label (label4
);
4492 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4493 quotient
, 0, OPTAB_LIB_WIDEN
);
4494 if (tem
!= quotient
)
4495 emit_move_insn (quotient
, tem
);
4496 expand_dec (quotient
, const1_rtx
);
4497 emit_label (label5
);
4505 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
4508 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4509 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4510 floor_log2 (d
), tquotient
, 1);
4511 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4513 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4514 t3
= gen_reg_rtx (compute_mode
);
4515 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4516 compute_mode
, 1, 1);
4520 lab
= gen_label_rtx ();
4521 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4522 expand_inc (t1
, const1_rtx
);
4527 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4533 /* Try using an instruction that produces both the quotient and
4534 remainder, using truncation. We can easily compensate the
4535 quotient or remainder to get ceiling rounding, once we have the
4536 remainder. Notice that we compute also the final remainder
4537 value here, and return the result right away. */
4538 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4539 target
= gen_reg_rtx (compute_mode
);
4543 remainder
= (REG_P (target
)
4544 ? target
: gen_reg_rtx (compute_mode
));
4545 quotient
= gen_reg_rtx (compute_mode
);
4549 quotient
= (REG_P (target
)
4550 ? target
: gen_reg_rtx (compute_mode
));
4551 remainder
= gen_reg_rtx (compute_mode
);
4554 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4557 /* This could be computed with a branch-less sequence.
4558 Save that for later. */
4559 rtx label
= gen_label_rtx ();
4560 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4561 compute_mode
, label
);
4562 expand_inc (quotient
, const1_rtx
);
4563 expand_dec (remainder
, op1
);
4565 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4568 /* No luck with division elimination or divmod. Have to do it
4569 by conditionally adjusting op0 *and* the result. */
4572 rtx adjusted_op0
, tem
;
4574 quotient
= gen_reg_rtx (compute_mode
);
4575 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4576 label1
= gen_label_rtx ();
4577 label2
= gen_label_rtx ();
4578 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4579 compute_mode
, label1
);
4580 emit_move_insn (quotient
, const0_rtx
);
4581 emit_jump_insn (gen_jump (label2
));
4583 emit_label (label1
);
4584 expand_dec (adjusted_op0
, const1_rtx
);
4585 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4586 quotient
, 1, OPTAB_LIB_WIDEN
);
4587 if (tem
!= quotient
)
4588 emit_move_insn (quotient
, tem
);
4589 expand_inc (quotient
, const1_rtx
);
4590 emit_label (label2
);
4595 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4596 && INTVAL (op1
) >= 0)
4598 /* This is extremely similar to the code for the unsigned case
4599 above. For 2.7 we should merge these variants, but for
4600 2.6.1 I don't want to touch the code for unsigned since that
4601 get used in C. The signed case will only be used by other
4605 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4606 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4607 floor_log2 (d
), tquotient
, 0);
4608 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4610 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4611 t3
= gen_reg_rtx (compute_mode
);
4612 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4613 compute_mode
, 1, 1);
4617 lab
= gen_label_rtx ();
4618 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4619 expand_inc (t1
, const1_rtx
);
4624 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4630 /* Try using an instruction that produces both the quotient and
4631 remainder, using truncation. We can easily compensate the
4632 quotient or remainder to get ceiling rounding, once we have the
4633 remainder. Notice that we compute also the final remainder
4634 value here, and return the result right away. */
4635 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4636 target
= gen_reg_rtx (compute_mode
);
4639 remainder
= (REG_P (target
)
4640 ? target
: gen_reg_rtx (compute_mode
));
4641 quotient
= gen_reg_rtx (compute_mode
);
4645 quotient
= (REG_P (target
)
4646 ? target
: gen_reg_rtx (compute_mode
));
4647 remainder
= gen_reg_rtx (compute_mode
);
4650 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4653 /* This could be computed with a branch-less sequence.
4654 Save that for later. */
4656 rtx label
= gen_label_rtx ();
4657 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4658 compute_mode
, label
);
4659 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4660 NULL_RTX
, 0, OPTAB_WIDEN
);
4661 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4662 expand_inc (quotient
, const1_rtx
);
4663 expand_dec (remainder
, op1
);
4665 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4668 /* No luck with division elimination or divmod. Have to do it
4669 by conditionally adjusting op0 *and* the result. */
4671 rtx label1
, label2
, label3
, label4
, label5
;
4675 quotient
= gen_reg_rtx (compute_mode
);
4676 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4677 label1
= gen_label_rtx ();
4678 label2
= gen_label_rtx ();
4679 label3
= gen_label_rtx ();
4680 label4
= gen_label_rtx ();
4681 label5
= gen_label_rtx ();
4682 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4683 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
4684 compute_mode
, label1
);
4685 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4686 quotient
, 0, OPTAB_LIB_WIDEN
);
4687 if (tem
!= quotient
)
4688 emit_move_insn (quotient
, tem
);
4689 emit_jump_insn (gen_jump (label5
));
4691 emit_label (label1
);
4692 expand_dec (adjusted_op0
, const1_rtx
);
4693 emit_jump_insn (gen_jump (label4
));
4695 emit_label (label2
);
4696 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
4697 compute_mode
, label3
);
4698 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4699 quotient
, 0, OPTAB_LIB_WIDEN
);
4700 if (tem
!= quotient
)
4701 emit_move_insn (quotient
, tem
);
4702 emit_jump_insn (gen_jump (label5
));
4704 emit_label (label3
);
4705 expand_inc (adjusted_op0
, const1_rtx
);
4706 emit_label (label4
);
4707 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4708 quotient
, 0, OPTAB_LIB_WIDEN
);
4709 if (tem
!= quotient
)
4710 emit_move_insn (quotient
, tem
);
4711 expand_inc (quotient
, const1_rtx
);
4712 emit_label (label5
);
4717 case EXACT_DIV_EXPR
:
4718 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4720 HOST_WIDE_INT d
= INTVAL (op1
);
4721 unsigned HOST_WIDE_INT ml
;
4725 pre_shift
= floor_log2 (d
& -d
);
4726 ml
= invert_mod2n (d
>> pre_shift
, size
);
4727 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4728 pre_shift
, NULL_RTX
, unsignedp
);
4729 quotient
= expand_mult (compute_mode
, t1
,
4730 gen_int_mode (ml
, compute_mode
),
4733 insn
= get_last_insn ();
4734 set_dst_reg_note (insn
, REG_EQUAL
,
4735 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
4736 compute_mode
, op0
, op1
),
4741 case ROUND_DIV_EXPR
:
4742 case ROUND_MOD_EXPR
:
4747 label
= gen_label_rtx ();
4748 quotient
= gen_reg_rtx (compute_mode
);
4749 remainder
= gen_reg_rtx (compute_mode
);
4750 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
4753 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
4754 quotient
, 1, OPTAB_LIB_WIDEN
);
4755 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
4756 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4757 remainder
, 1, OPTAB_LIB_WIDEN
);
4759 tem
= plus_constant (compute_mode
, op1
, -1);
4760 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
, 1, NULL_RTX
, 1);
4761 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
4762 expand_inc (quotient
, const1_rtx
);
4763 expand_dec (remainder
, op1
);
4768 rtx abs_rem
, abs_op1
, tem
, mask
;
4770 label
= gen_label_rtx ();
4771 quotient
= gen_reg_rtx (compute_mode
);
4772 remainder
= gen_reg_rtx (compute_mode
);
4773 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
4776 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
4777 quotient
, 0, OPTAB_LIB_WIDEN
);
4778 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
4779 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4780 remainder
, 0, OPTAB_LIB_WIDEN
);
4782 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
4783 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
4784 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
4786 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
4787 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4788 NULL_RTX
, 0, OPTAB_WIDEN
);
4789 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4790 size
- 1, NULL_RTX
, 0);
4791 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
4792 NULL_RTX
, 0, OPTAB_WIDEN
);
4793 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4794 NULL_RTX
, 0, OPTAB_WIDEN
);
4795 expand_inc (quotient
, tem
);
4796 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
4797 NULL_RTX
, 0, OPTAB_WIDEN
);
4798 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4799 NULL_RTX
, 0, OPTAB_WIDEN
);
4800 expand_dec (remainder
, tem
);
4803 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4811 if (target
&& GET_MODE (target
) != compute_mode
)
4816 /* Try to produce the remainder without producing the quotient.
4817 If we seem to have a divmod pattern that does not require widening,
4818 don't try widening here. We should really have a WIDEN argument
4819 to expand_twoval_binop, since what we'd really like to do here is
4820 1) try a mod insn in compute_mode
4821 2) try a divmod insn in compute_mode
4822 3) try a div insn in compute_mode and multiply-subtract to get
4824 4) try the same things with widening allowed. */
4826 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4829 ((optab_handler (optab2
, compute_mode
)
4830 != CODE_FOR_nothing
)
4831 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4834 /* No luck there. Can we do remainder and divide at once
4835 without a library call? */
4836 remainder
= gen_reg_rtx (compute_mode
);
4837 if (! expand_twoval_binop ((unsignedp
4841 NULL_RTX
, remainder
, unsignedp
))
4846 return gen_lowpart (mode
, remainder
);
4849 /* Produce the quotient. Try a quotient insn, but not a library call.
4850 If we have a divmod in this mode, use it in preference to widening
4851 the div (for this test we assume it will not fail). Note that optab2
4852 is set to the one of the two optabs that the call below will use. */
4854 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
4855 op0
, op1
, rem_flag
? NULL_RTX
: target
,
4857 ((optab_handler (optab2
, compute_mode
)
4858 != CODE_FOR_nothing
)
4859 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4863 /* No luck there. Try a quotient-and-remainder insn,
4864 keeping the quotient alone. */
4865 quotient
= gen_reg_rtx (compute_mode
);
4866 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
4868 quotient
, NULL_RTX
, unsignedp
))
4872 /* Still no luck. If we are not computing the remainder,
4873 use a library call for the quotient. */
4874 quotient
= sign_expand_binop (compute_mode
,
4875 udiv_optab
, sdiv_optab
,
4877 unsignedp
, OPTAB_LIB_WIDEN
);
4884 if (target
&& GET_MODE (target
) != compute_mode
)
4889 /* No divide instruction either. Use library for remainder. */
4890 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4892 unsignedp
, OPTAB_LIB_WIDEN
);
4893 /* No remainder function. Try a quotient-and-remainder
4894 function, keeping the remainder. */
4897 remainder
= gen_reg_rtx (compute_mode
);
4898 if (!expand_twoval_binop_libfunc
4899 (unsignedp
? udivmod_optab
: sdivmod_optab
,
4901 NULL_RTX
, remainder
,
4902 unsignedp
? UMOD
: MOD
))
4903 remainder
= NULL_RTX
;
4908 /* We divided. Now finish doing X - Y * (X / Y). */
4909 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4910 NULL_RTX
, unsignedp
);
4911 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4912 remainder
, target
, unsignedp
,
4917 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4920 /* Return a tree node with data type TYPE, describing the value of X.
4921 Usually this is an VAR_DECL, if there is no obvious better choice.
4922 X may be an expression, however we only support those expressions
4923 generated by loop.c. */
4926 make_tree (tree type
, rtx x
)
4930 switch (GET_CODE (x
))
4934 HOST_WIDE_INT hi
= 0;
4937 && !(TYPE_UNSIGNED (type
)
4938 && (GET_MODE_BITSIZE (TYPE_MODE (type
))
4939 < HOST_BITS_PER_WIDE_INT
)))
4942 t
= build_int_cst_wide (type
, INTVAL (x
), hi
);
4948 if (GET_MODE (x
) == VOIDmode
)
4949 t
= build_int_cst_wide (type
,
4950 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4955 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4956 t
= build_real (type
, d
);
4963 int units
= CONST_VECTOR_NUNITS (x
);
4964 tree itype
= TREE_TYPE (type
);
4968 /* Build a tree with vector elements. */
4969 elts
= XALLOCAVEC (tree
, units
);
4970 for (i
= units
- 1; i
>= 0; --i
)
4972 rtx elt
= CONST_VECTOR_ELT (x
, i
);
4973 elts
[i
] = make_tree (itype
, elt
);
4976 return build_vector (type
, elts
);
4980 return fold_build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4981 make_tree (type
, XEXP (x
, 1)));
4984 return fold_build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4985 make_tree (type
, XEXP (x
, 1)));
4988 return fold_build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0)));
4991 return fold_build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4992 make_tree (type
, XEXP (x
, 1)));
4995 return fold_build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4996 make_tree (type
, XEXP (x
, 1)));
4999 t
= unsigned_type_for (type
);
5000 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5001 make_tree (t
, XEXP (x
, 0)),
5002 make_tree (type
, XEXP (x
, 1))));
5005 t
= signed_type_for (type
);
5006 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5007 make_tree (t
, XEXP (x
, 0)),
5008 make_tree (type
, XEXP (x
, 1))));
5011 if (TREE_CODE (type
) != REAL_TYPE
)
5012 t
= signed_type_for (type
);
5016 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5017 make_tree (t
, XEXP (x
, 0)),
5018 make_tree (t
, XEXP (x
, 1))));
5020 t
= unsigned_type_for (type
);
5021 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5022 make_tree (t
, XEXP (x
, 0)),
5023 make_tree (t
, XEXP (x
, 1))));
5027 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
5028 GET_CODE (x
) == ZERO_EXTEND
);
5029 return fold_convert (type
, make_tree (t
, XEXP (x
, 0)));
5032 return make_tree (type
, XEXP (x
, 0));
5035 t
= SYMBOL_REF_DECL (x
);
5037 return fold_convert (type
, build_fold_addr_expr (t
));
5038 /* else fall through. */
5041 t
= build_decl (RTL_LOCATION (x
), VAR_DECL
, NULL_TREE
, type
);
5043 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5044 address mode to pointer mode. */
5045 if (POINTER_TYPE_P (type
))
5046 x
= convert_memory_address_addr_space
5047 (TYPE_MODE (type
), x
, TYPE_ADDR_SPACE (TREE_TYPE (type
)));
5049 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5050 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5051 t
->decl_with_rtl
.rtl
= x
;
5057 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5058 and returning TARGET.
5060 If TARGET is 0, a pseudo-register or constant is returned. */
5063 expand_and (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
5067 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
5068 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
5070 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
5074 else if (tem
!= target
)
5075 emit_move_insn (target
, tem
);
5079 /* Helper function for emit_store_flag. */
5081 emit_cstore (rtx target
, enum insn_code icode
, enum rtx_code code
,
5082 enum machine_mode mode
, enum machine_mode compare_mode
,
5083 int unsignedp
, rtx x
, rtx y
, int normalizep
,
5084 enum machine_mode target_mode
)
5086 struct expand_operand ops
[4];
5087 rtx op0
, last
, comparison
, subtarget
;
5088 enum machine_mode result_mode
= insn_data
[(int) icode
].operand
[0].mode
;
5090 last
= get_last_insn ();
5091 x
= prepare_operand (icode
, x
, 2, mode
, compare_mode
, unsignedp
);
5092 y
= prepare_operand (icode
, y
, 3, mode
, compare_mode
, unsignedp
);
5095 delete_insns_since (last
);
5099 if (target_mode
== VOIDmode
)
5100 target_mode
= result_mode
;
5102 target
= gen_reg_rtx (target_mode
);
5104 comparison
= gen_rtx_fmt_ee (code
, result_mode
, x
, y
);
5106 create_output_operand (&ops
[0], optimize
? NULL_RTX
: target
, result_mode
);
5107 create_fixed_operand (&ops
[1], comparison
);
5108 create_fixed_operand (&ops
[2], x
);
5109 create_fixed_operand (&ops
[3], y
);
5110 if (!maybe_expand_insn (icode
, 4, ops
))
5112 delete_insns_since (last
);
5115 subtarget
= ops
[0].value
;
5117 /* If we are converting to a wider mode, first convert to
5118 TARGET_MODE, then normalize. This produces better combining
5119 opportunities on machines that have a SIGN_EXTRACT when we are
5120 testing a single bit. This mostly benefits the 68k.
5122 If STORE_FLAG_VALUE does not have the sign bit set when
5123 interpreted in MODE, we can do this conversion as unsigned, which
5124 is usually more efficient. */
5125 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (result_mode
))
5127 convert_move (target
, subtarget
,
5128 val_signbit_known_clear_p (result_mode
,
5131 result_mode
= target_mode
;
5136 /* If we want to keep subexpressions around, don't reuse our last
5141 /* Now normalize to the proper value in MODE. Sometimes we don't
5142 have to do anything. */
5143 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
5145 /* STORE_FLAG_VALUE might be the most negative number, so write
5146 the comparison this way to avoid a compiler-time warning. */
5147 else if (- normalizep
== STORE_FLAG_VALUE
)
5148 op0
= expand_unop (result_mode
, neg_optab
, op0
, subtarget
, 0);
5150 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5151 it hard to use a value of just the sign bit due to ANSI integer
5152 constant typing rules. */
5153 else if (val_signbit_known_set_p (result_mode
, STORE_FLAG_VALUE
))
5154 op0
= expand_shift (RSHIFT_EXPR
, result_mode
, op0
,
5155 GET_MODE_BITSIZE (result_mode
) - 1, subtarget
,
5159 gcc_assert (STORE_FLAG_VALUE
& 1);
5161 op0
= expand_and (result_mode
, op0
, const1_rtx
, subtarget
);
5162 if (normalizep
== -1)
5163 op0
= expand_unop (result_mode
, neg_optab
, op0
, op0
, 0);
5166 /* If we were converting to a smaller mode, do the conversion now. */
5167 if (target_mode
!= result_mode
)
5169 convert_move (target
, op0
, 0);
5177 /* A subroutine of emit_store_flag only including "tricks" that do not
5178 need a recursive call. These are kept separate to avoid infinite
5182 emit_store_flag_1 (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5183 enum machine_mode mode
, int unsignedp
, int normalizep
,
5184 enum machine_mode target_mode
)
5187 enum insn_code icode
;
5188 enum machine_mode compare_mode
;
5189 enum mode_class mclass
;
5190 enum rtx_code scode
;
5194 code
= unsigned_condition (code
);
5195 scode
= swap_condition (code
);
5197 /* If one operand is constant, make it the second one. Only do this
5198 if the other operand is not constant as well. */
5200 if (swap_commutative_operands_p (op0
, op1
))
5205 code
= swap_condition (code
);
5208 if (mode
== VOIDmode
)
5209 mode
= GET_MODE (op0
);
5211 /* For some comparisons with 1 and -1, we can convert this to
5212 comparisons with zero. This will often produce more opportunities for
5213 store-flag insns. */
5218 if (op1
== const1_rtx
)
5219 op1
= const0_rtx
, code
= LE
;
5222 if (op1
== constm1_rtx
)
5223 op1
= const0_rtx
, code
= LT
;
5226 if (op1
== const1_rtx
)
5227 op1
= const0_rtx
, code
= GT
;
5230 if (op1
== constm1_rtx
)
5231 op1
= const0_rtx
, code
= GE
;
5234 if (op1
== const1_rtx
)
5235 op1
= const0_rtx
, code
= NE
;
5238 if (op1
== const1_rtx
)
5239 op1
= const0_rtx
, code
= EQ
;
5245 /* If we are comparing a double-word integer with zero or -1, we can
5246 convert the comparison into one involving a single word. */
5247 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
5248 && GET_MODE_CLASS (mode
) == MODE_INT
5249 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
5251 if ((code
== EQ
|| code
== NE
)
5252 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
5256 /* Do a logical OR or AND of the two words and compare the
5258 op00
= simplify_gen_subreg (word_mode
, op0
, mode
, 0);
5259 op01
= simplify_gen_subreg (word_mode
, op0
, mode
, UNITS_PER_WORD
);
5260 tem
= expand_binop (word_mode
,
5261 op1
== const0_rtx
? ior_optab
: and_optab
,
5262 op00
, op01
, NULL_RTX
, unsignedp
,
5266 tem
= emit_store_flag (NULL_RTX
, code
, tem
, op1
, word_mode
,
5267 unsignedp
, normalizep
);
5269 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
5273 /* If testing the sign bit, can just test on high word. */
5274 op0h
= simplify_gen_subreg (word_mode
, op0
, mode
,
5275 subreg_highpart_offset (word_mode
,
5277 tem
= emit_store_flag (NULL_RTX
, code
, op0h
, op1
, word_mode
,
5278 unsignedp
, normalizep
);
5285 if (target_mode
== VOIDmode
|| GET_MODE (tem
) == target_mode
)
5288 target
= gen_reg_rtx (target_mode
);
5290 convert_move (target
, tem
,
5291 !val_signbit_known_set_p (word_mode
,
5292 (normalizep
? normalizep
5293 : STORE_FLAG_VALUE
)));
5298 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5299 complement of A (for GE) and shifting the sign bit to the low bit. */
5300 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
5301 && GET_MODE_CLASS (mode
) == MODE_INT
5302 && (normalizep
|| STORE_FLAG_VALUE
== 1
5303 || val_signbit_p (mode
, STORE_FLAG_VALUE
)))
5310 /* If the result is to be wider than OP0, it is best to convert it
5311 first. If it is to be narrower, it is *incorrect* to convert it
5313 else if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
5315 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5319 if (target_mode
!= mode
)
5323 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
5324 ((STORE_FLAG_VALUE
== 1 || normalizep
)
5325 ? 0 : subtarget
), 0);
5327 if (STORE_FLAG_VALUE
== 1 || normalizep
)
5328 /* If we are supposed to produce a 0/1 value, we want to do
5329 a logical shift from the sign bit to the low-order bit; for
5330 a -1/0 value, we do an arithmetic shift. */
5331 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5332 GET_MODE_BITSIZE (mode
) - 1,
5333 subtarget
, normalizep
!= -1);
5335 if (mode
!= target_mode
)
5336 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5341 mclass
= GET_MODE_CLASS (mode
);
5342 for (compare_mode
= mode
; compare_mode
!= VOIDmode
;
5343 compare_mode
= GET_MODE_WIDER_MODE (compare_mode
))
5345 enum machine_mode optab_mode
= mclass
== MODE_CC
? CCmode
: compare_mode
;
5346 icode
= optab_handler (cstore_optab
, optab_mode
);
5347 if (icode
!= CODE_FOR_nothing
)
5349 do_pending_stack_adjust ();
5350 tem
= emit_cstore (target
, icode
, code
, mode
, compare_mode
,
5351 unsignedp
, op0
, op1
, normalizep
, target_mode
);
5355 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5357 tem
= emit_cstore (target
, icode
, scode
, mode
, compare_mode
,
5358 unsignedp
, op1
, op0
, normalizep
, target_mode
);
5369 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5370 and storing in TARGET. Normally return TARGET.
5371 Return 0 if that cannot be done.
5373 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5374 it is VOIDmode, they cannot both be CONST_INT.
5376 UNSIGNEDP is for the case where we have to widen the operands
5377 to perform the operation. It says to use zero-extension.
5379 NORMALIZEP is 1 if we should convert the result to be either zero
5380 or one. Normalize is -1 if we should convert the result to be
5381 either zero or -1. If NORMALIZEP is zero, the result will be left
5382 "raw" out of the scc insn. */
5385 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5386 enum machine_mode mode
, int unsignedp
, int normalizep
)
5388 enum machine_mode target_mode
= target
? GET_MODE (target
) : VOIDmode
;
5389 enum rtx_code rcode
;
5391 rtx tem
, last
, trueval
;
5393 tem
= emit_store_flag_1 (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
,
5398 /* If we reached here, we can't do this with a scc insn, however there
5399 are some comparisons that can be done in other ways. Don't do any
5400 of these cases if branches are very cheap. */
5401 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5404 /* See what we need to return. We can only return a 1, -1, or the
5407 if (normalizep
== 0)
5409 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5410 normalizep
= STORE_FLAG_VALUE
;
5412 else if (val_signbit_p (mode
, STORE_FLAG_VALUE
))
5418 last
= get_last_insn ();
5420 /* If optimizing, use different pseudo registers for each insn, instead
5421 of reusing the same pseudo. This leads to better CSE, but slows
5422 down the compiler, since there are more pseudos */
5423 subtarget
= (!optimize
5424 && (target_mode
== mode
)) ? target
: NULL_RTX
;
5425 trueval
= GEN_INT (normalizep
? normalizep
: STORE_FLAG_VALUE
);
5427 /* For floating-point comparisons, try the reverse comparison or try
5428 changing the "orderedness" of the comparison. */
5429 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5431 enum rtx_code first_code
;
5434 rcode
= reverse_condition_maybe_unordered (code
);
5435 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5436 && (code
== ORDERED
|| code
== UNORDERED
5437 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5438 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5440 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5441 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5443 /* For the reverse comparison, use either an addition or a XOR. */
5445 && rtx_cost (GEN_INT (normalizep
), PLUS
, 1,
5446 optimize_insn_for_speed_p ()) == 0)
5448 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5449 STORE_FLAG_VALUE
, target_mode
);
5451 return expand_binop (target_mode
, add_optab
, tem
,
5452 GEN_INT (normalizep
),
5453 target
, 0, OPTAB_WIDEN
);
5456 && rtx_cost (trueval
, XOR
, 1,
5457 optimize_insn_for_speed_p ()) == 0)
5459 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5460 normalizep
, target_mode
);
5462 return expand_binop (target_mode
, xor_optab
, tem
, trueval
,
5463 target
, INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5467 delete_insns_since (last
);
5469 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5470 if (code
== ORDERED
|| code
== UNORDERED
)
5473 and_them
= split_comparison (code
, mode
, &first_code
, &code
);
5475 /* If there are no NaNs, the first comparison should always fall through.
5476 Effectively change the comparison to the other one. */
5477 if (!HONOR_NANS (mode
))
5479 gcc_assert (first_code
== (and_them
? ORDERED
: UNORDERED
));
5480 return emit_store_flag_1 (target
, code
, op0
, op1
, mode
, 0, normalizep
,
5484 #ifdef HAVE_conditional_move
5485 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5486 conditional move. */
5487 tem
= emit_store_flag_1 (subtarget
, first_code
, op0
, op1
, mode
, 0,
5488 normalizep
, target_mode
);
5493 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
5494 tem
, const0_rtx
, GET_MODE (tem
), 0);
5496 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
5497 trueval
, tem
, GET_MODE (tem
), 0);
5500 delete_insns_since (last
);
5507 /* The remaining tricks only apply to integer comparisons. */
5509 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5512 /* If this is an equality comparison of integers, we can try to exclusive-or
5513 (or subtract) the two operands and use a recursive call to try the
5514 comparison with zero. Don't do any of these cases if branches are
5517 if ((code
== EQ
|| code
== NE
) && op1
!= const0_rtx
)
5519 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
5523 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
5526 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
5527 mode
, unsignedp
, normalizep
);
5531 delete_insns_since (last
);
5534 /* For integer comparisons, try the reverse comparison. However, for
5535 small X and if we'd have anyway to extend, implementing "X != 0"
5536 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5537 rcode
= reverse_condition (code
);
5538 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5539 && ! (optab_handler (cstore_optab
, mode
) == CODE_FOR_nothing
5541 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5542 && op1
== const0_rtx
))
5544 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5545 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5547 /* Again, for the reverse comparison, use either an addition or a XOR. */
5549 && rtx_cost (GEN_INT (normalizep
), PLUS
, 1,
5550 optimize_insn_for_speed_p ()) == 0)
5552 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5553 STORE_FLAG_VALUE
, target_mode
);
5555 tem
= expand_binop (target_mode
, add_optab
, tem
,
5556 GEN_INT (normalizep
), target
, 0, OPTAB_WIDEN
);
5559 && rtx_cost (trueval
, XOR
, 1,
5560 optimize_insn_for_speed_p ()) == 0)
5562 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5563 normalizep
, target_mode
);
5565 tem
= expand_binop (target_mode
, xor_optab
, tem
, trueval
, target
,
5566 INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5571 delete_insns_since (last
);
5574 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5575 the constant zero. Reject all other comparisons at this point. Only
5576 do LE and GT if branches are expensive since they are expensive on
5577 2-operand machines. */
5579 if (op1
!= const0_rtx
5580 || (code
!= EQ
&& code
!= NE
5581 && (BRANCH_COST (optimize_insn_for_speed_p (),
5582 false) <= 1 || (code
!= LE
&& code
!= GT
))))
5585 /* Try to put the result of the comparison in the sign bit. Assume we can't
5586 do the necessary operation below. */
5590 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5591 the sign bit set. */
5595 /* This is destructive, so SUBTARGET can't be OP0. */
5596 if (rtx_equal_p (subtarget
, op0
))
5599 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
5602 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
5606 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5607 number of bits in the mode of OP0, minus one. */
5611 if (rtx_equal_p (subtarget
, op0
))
5614 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5615 GET_MODE_BITSIZE (mode
) - 1,
5617 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5621 if (code
== EQ
|| code
== NE
)
5623 /* For EQ or NE, one way to do the comparison is to apply an operation
5624 that converts the operand into a positive number if it is nonzero
5625 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5626 for NE we negate. This puts the result in the sign bit. Then we
5627 normalize with a shift, if needed.
5629 Two operations that can do the above actions are ABS and FFS, so try
5630 them. If that doesn't work, and MODE is smaller than a full word,
5631 we can use zero-extension to the wider mode (an unsigned conversion)
5632 as the operation. */
5634 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5635 that is compensated by the subsequent overflow when subtracting
5638 if (optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)
5639 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5640 else if (optab_handler (ffs_optab
, mode
) != CODE_FOR_nothing
)
5641 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5642 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5644 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5651 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5654 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5657 /* If we couldn't do it that way, for NE we can "or" the two's complement
5658 of the value with itself. For EQ, we take the one's complement of
5659 that "or", which is an extra insn, so we only handle EQ if branches
5664 || BRANCH_COST (optimize_insn_for_speed_p (),
5667 if (rtx_equal_p (subtarget
, op0
))
5670 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5671 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5674 if (tem
&& code
== EQ
)
5675 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5679 if (tem
&& normalizep
)
5680 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
5681 GET_MODE_BITSIZE (mode
) - 1,
5682 subtarget
, normalizep
== 1);
5688 else if (GET_MODE (tem
) != target_mode
)
5690 convert_move (target
, tem
, 0);
5693 else if (!subtarget
)
5695 emit_move_insn (target
, tem
);
5700 delete_insns_since (last
);
5705 /* Like emit_store_flag, but always succeeds. */
5708 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5709 enum machine_mode mode
, int unsignedp
, int normalizep
)
5712 rtx trueval
, falseval
;
5714 /* First see if emit_store_flag can do the job. */
5715 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
5720 target
= gen_reg_rtx (word_mode
);
5722 /* If this failed, we have to do this with set/compare/jump/set code.
5723 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5724 trueval
= normalizep
? GEN_INT (normalizep
) : const1_rtx
;
5726 && GET_MODE_CLASS (mode
) == MODE_INT
5729 && op1
== const0_rtx
)
5731 label
= gen_label_rtx ();
5732 do_compare_rtx_and_jump (target
, const0_rtx
, EQ
, unsignedp
,
5733 mode
, NULL_RTX
, NULL_RTX
, label
, -1);
5734 emit_move_insn (target
, trueval
);
5740 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
5741 target
= gen_reg_rtx (GET_MODE (target
));
5743 /* Jump in the right direction if the target cannot implement CODE
5744 but can jump on its reverse condition. */
5745 falseval
= const0_rtx
;
5746 if (! can_compare_p (code
, mode
, ccp_jump
)
5747 && (! FLOAT_MODE_P (mode
)
5748 || code
== ORDERED
|| code
== UNORDERED
5749 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5750 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5752 enum rtx_code rcode
;
5753 if (FLOAT_MODE_P (mode
))
5754 rcode
= reverse_condition_maybe_unordered (code
);
5756 rcode
= reverse_condition (code
);
5758 /* Canonicalize to UNORDERED for the libcall. */
5759 if (can_compare_p (rcode
, mode
, ccp_jump
)
5760 || (code
== ORDERED
&& ! can_compare_p (ORDERED
, mode
, ccp_jump
)))
5763 trueval
= const0_rtx
;
5768 emit_move_insn (target
, trueval
);
5769 label
= gen_label_rtx ();
5770 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
5771 NULL_RTX
, label
, -1);
5773 emit_move_insn (target
, falseval
);
5779 /* Perform possibly multi-word comparison and conditional jump to LABEL
5780 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5781 now a thin wrapper around do_compare_rtx_and_jump. */
5784 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, enum machine_mode mode
,
5787 int unsignedp
= (op
== LTU
|| op
== LEU
|| op
== GTU
|| op
== GEU
);
5788 do_compare_rtx_and_jump (arg1
, arg2
, op
, unsignedp
, mode
,
5789 NULL_RTX
, NULL_RTX
, label
, -1);