1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987-2014 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
26 #include "diagnostic-core.h"
29 #include "stor-layout.h"
32 #include "insn-config.h"
36 #include "langhooks.h"
41 struct target_expmed default_target_expmed
;
43 struct target_expmed
*this_target_expmed
= &default_target_expmed
;
46 static void store_fixed_bit_field (rtx
, unsigned HOST_WIDE_INT
,
47 unsigned HOST_WIDE_INT
,
48 unsigned HOST_WIDE_INT
,
49 unsigned HOST_WIDE_INT
,
51 static void store_fixed_bit_field_1 (rtx
, unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
,
54 static void store_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
55 unsigned HOST_WIDE_INT
,
56 unsigned HOST_WIDE_INT
,
57 unsigned HOST_WIDE_INT
,
59 static rtx
extract_fixed_bit_field (enum machine_mode
, rtx
,
60 unsigned HOST_WIDE_INT
,
61 unsigned HOST_WIDE_INT
, rtx
, int);
62 static rtx
extract_fixed_bit_field_1 (enum machine_mode
, rtx
,
63 unsigned HOST_WIDE_INT
,
64 unsigned HOST_WIDE_INT
, rtx
, int);
65 static rtx
lshift_value (enum machine_mode
, unsigned HOST_WIDE_INT
, int);
66 static rtx
extract_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
67 unsigned HOST_WIDE_INT
, int);
68 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, enum machine_mode
, rtx_code_label
*);
69 static rtx
expand_smod_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
70 static rtx
expand_sdiv_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
72 /* Return a constant integer mask value of mode MODE with BITSIZE ones
73 followed by BITPOS zeros, or the complement of that if COMPLEMENT.
74 The mask is truncated if necessary to the width of mode MODE. The
75 mask is zero-extended if BITSIZE+BITPOS is too small for MODE. */
78 mask_rtx (enum machine_mode mode
, int bitpos
, int bitsize
, bool complement
)
80 return immed_wide_int_const
81 (wi::shifted_mask (bitpos
, bitsize
, complement
,
82 GET_MODE_PRECISION (mode
)), mode
);
85 /* Test whether a value is zero of a power of two. */
86 #define EXACT_POWER_OF_2_OR_ZERO_P(x) \
87 (((x) & ((x) - (unsigned HOST_WIDE_INT) 1)) == 0)
89 struct init_expmed_rtl
110 rtx pow2
[MAX_BITS_PER_WORD
];
111 rtx cint
[MAX_BITS_PER_WORD
];
115 init_expmed_one_conv (struct init_expmed_rtl
*all
, enum machine_mode to_mode
,
116 enum machine_mode from_mode
, bool speed
)
118 int to_size
, from_size
;
121 to_size
= GET_MODE_PRECISION (to_mode
);
122 from_size
= GET_MODE_PRECISION (from_mode
);
124 /* Most partial integers have a precision less than the "full"
125 integer it requires for storage. In case one doesn't, for
126 comparison purposes here, reduce the bit size by one in that
128 if (GET_MODE_CLASS (to_mode
) == MODE_PARTIAL_INT
129 && exact_log2 (to_size
) != -1)
131 if (GET_MODE_CLASS (from_mode
) == MODE_PARTIAL_INT
132 && exact_log2 (from_size
) != -1)
135 /* Assume cost of zero-extend and sign-extend is the same. */
136 which
= (to_size
< from_size
? all
->trunc
: all
->zext
);
138 PUT_MODE (all
->reg
, from_mode
);
139 set_convert_cost (to_mode
, from_mode
, speed
, set_src_cost (which
, speed
));
143 init_expmed_one_mode (struct init_expmed_rtl
*all
,
144 enum machine_mode mode
, int speed
)
146 int m
, n
, mode_bitsize
;
147 enum machine_mode mode_from
;
149 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
151 PUT_MODE (all
->reg
, mode
);
152 PUT_MODE (all
->plus
, mode
);
153 PUT_MODE (all
->neg
, mode
);
154 PUT_MODE (all
->mult
, mode
);
155 PUT_MODE (all
->sdiv
, mode
);
156 PUT_MODE (all
->udiv
, mode
);
157 PUT_MODE (all
->sdiv_32
, mode
);
158 PUT_MODE (all
->smod_32
, mode
);
159 PUT_MODE (all
->wide_trunc
, mode
);
160 PUT_MODE (all
->shift
, mode
);
161 PUT_MODE (all
->shift_mult
, mode
);
162 PUT_MODE (all
->shift_add
, mode
);
163 PUT_MODE (all
->shift_sub0
, mode
);
164 PUT_MODE (all
->shift_sub1
, mode
);
165 PUT_MODE (all
->zext
, mode
);
166 PUT_MODE (all
->trunc
, mode
);
168 set_add_cost (speed
, mode
, set_src_cost (all
->plus
, speed
));
169 set_neg_cost (speed
, mode
, set_src_cost (all
->neg
, speed
));
170 set_mul_cost (speed
, mode
, set_src_cost (all
->mult
, speed
));
171 set_sdiv_cost (speed
, mode
, set_src_cost (all
->sdiv
, speed
));
172 set_udiv_cost (speed
, mode
, set_src_cost (all
->udiv
, speed
));
174 set_sdiv_pow2_cheap (speed
, mode
, (set_src_cost (all
->sdiv_32
, speed
)
175 <= 2 * add_cost (speed
, mode
)));
176 set_smod_pow2_cheap (speed
, mode
, (set_src_cost (all
->smod_32
, speed
)
177 <= 4 * add_cost (speed
, mode
)));
179 set_shift_cost (speed
, mode
, 0, 0);
181 int cost
= add_cost (speed
, mode
);
182 set_shiftadd_cost (speed
, mode
, 0, cost
);
183 set_shiftsub0_cost (speed
, mode
, 0, cost
);
184 set_shiftsub1_cost (speed
, mode
, 0, cost
);
187 n
= MIN (MAX_BITS_PER_WORD
, mode_bitsize
);
188 for (m
= 1; m
< n
; m
++)
190 XEXP (all
->shift
, 1) = all
->cint
[m
];
191 XEXP (all
->shift_mult
, 1) = all
->pow2
[m
];
193 set_shift_cost (speed
, mode
, m
, set_src_cost (all
->shift
, speed
));
194 set_shiftadd_cost (speed
, mode
, m
, set_src_cost (all
->shift_add
, speed
));
195 set_shiftsub0_cost (speed
, mode
, m
, set_src_cost (all
->shift_sub0
, speed
));
196 set_shiftsub1_cost (speed
, mode
, m
, set_src_cost (all
->shift_sub1
, speed
));
199 if (SCALAR_INT_MODE_P (mode
))
201 for (mode_from
= MIN_MODE_INT
; mode_from
<= MAX_MODE_INT
;
202 mode_from
= (enum machine_mode
)(mode_from
+ 1))
203 init_expmed_one_conv (all
, mode
, mode_from
, speed
);
205 if (GET_MODE_CLASS (mode
) == MODE_INT
)
207 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
208 if (wider_mode
!= VOIDmode
)
210 PUT_MODE (all
->zext
, wider_mode
);
211 PUT_MODE (all
->wide_mult
, wider_mode
);
212 PUT_MODE (all
->wide_lshr
, wider_mode
);
213 XEXP (all
->wide_lshr
, 1) = GEN_INT (mode_bitsize
);
215 set_mul_widen_cost (speed
, wider_mode
,
216 set_src_cost (all
->wide_mult
, speed
));
217 set_mul_highpart_cost (speed
, mode
,
218 set_src_cost (all
->wide_trunc
, speed
));
226 struct init_expmed_rtl all
;
227 enum machine_mode mode
= QImode
;
230 memset (&all
, 0, sizeof all
);
231 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
233 all
.pow2
[m
] = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
234 all
.cint
[m
] = GEN_INT (m
);
237 /* Avoid using hard regs in ways which may be unsupported. */
238 all
.reg
= gen_rtx_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
239 all
.plus
= gen_rtx_PLUS (mode
, all
.reg
, all
.reg
);
240 all
.neg
= gen_rtx_NEG (mode
, all
.reg
);
241 all
.mult
= gen_rtx_MULT (mode
, all
.reg
, all
.reg
);
242 all
.sdiv
= gen_rtx_DIV (mode
, all
.reg
, all
.reg
);
243 all
.udiv
= gen_rtx_UDIV (mode
, all
.reg
, all
.reg
);
244 all
.sdiv_32
= gen_rtx_DIV (mode
, all
.reg
, all
.pow2
[5]);
245 all
.smod_32
= gen_rtx_MOD (mode
, all
.reg
, all
.pow2
[5]);
246 all
.zext
= gen_rtx_ZERO_EXTEND (mode
, all
.reg
);
247 all
.wide_mult
= gen_rtx_MULT (mode
, all
.zext
, all
.zext
);
248 all
.wide_lshr
= gen_rtx_LSHIFTRT (mode
, all
.wide_mult
, all
.reg
);
249 all
.wide_trunc
= gen_rtx_TRUNCATE (mode
, all
.wide_lshr
);
250 all
.shift
= gen_rtx_ASHIFT (mode
, all
.reg
, all
.reg
);
251 all
.shift_mult
= gen_rtx_MULT (mode
, all
.reg
, all
.reg
);
252 all
.shift_add
= gen_rtx_PLUS (mode
, all
.shift_mult
, all
.reg
);
253 all
.shift_sub0
= gen_rtx_MINUS (mode
, all
.shift_mult
, all
.reg
);
254 all
.shift_sub1
= gen_rtx_MINUS (mode
, all
.reg
, all
.shift_mult
);
255 all
.trunc
= gen_rtx_TRUNCATE (mode
, all
.reg
);
257 for (speed
= 0; speed
< 2; speed
++)
259 crtl
->maybe_hot_insn_p
= speed
;
260 set_zero_cost (speed
, set_src_cost (const0_rtx
, speed
));
262 for (mode
= MIN_MODE_INT
; mode
<= MAX_MODE_INT
;
263 mode
= (enum machine_mode
)(mode
+ 1))
264 init_expmed_one_mode (&all
, mode
, speed
);
266 if (MIN_MODE_PARTIAL_INT
!= VOIDmode
)
267 for (mode
= MIN_MODE_PARTIAL_INT
; mode
<= MAX_MODE_PARTIAL_INT
;
268 mode
= (enum machine_mode
)(mode
+ 1))
269 init_expmed_one_mode (&all
, mode
, speed
);
271 if (MIN_MODE_VECTOR_INT
!= VOIDmode
)
272 for (mode
= MIN_MODE_VECTOR_INT
; mode
<= MAX_MODE_VECTOR_INT
;
273 mode
= (enum machine_mode
)(mode
+ 1))
274 init_expmed_one_mode (&all
, mode
, speed
);
277 if (alg_hash_used_p ())
279 struct alg_hash_entry
*p
= alg_hash_entry_ptr (0);
280 memset (p
, 0, sizeof (*p
) * NUM_ALG_HASH_ENTRIES
);
283 set_alg_hash_used_p (true);
284 default_rtl_profile ();
286 ggc_free (all
.trunc
);
287 ggc_free (all
.shift_sub1
);
288 ggc_free (all
.shift_sub0
);
289 ggc_free (all
.shift_add
);
290 ggc_free (all
.shift_mult
);
291 ggc_free (all
.shift
);
292 ggc_free (all
.wide_trunc
);
293 ggc_free (all
.wide_lshr
);
294 ggc_free (all
.wide_mult
);
296 ggc_free (all
.smod_32
);
297 ggc_free (all
.sdiv_32
);
306 /* Return an rtx representing minus the value of X.
307 MODE is the intended mode of the result,
308 useful if X is a CONST_INT. */
311 negate_rtx (enum machine_mode mode
, rtx x
)
313 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
316 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
321 /* Adjust bitfield memory MEM so that it points to the first unit of mode
322 MODE that contains a bitfield of size BITSIZE at bit position BITNUM.
323 If MODE is BLKmode, return a reference to every byte in the bitfield.
324 Set *NEW_BITNUM to the bit position of the field within the new memory. */
327 narrow_bit_field_mem (rtx mem
, enum machine_mode mode
,
328 unsigned HOST_WIDE_INT bitsize
,
329 unsigned HOST_WIDE_INT bitnum
,
330 unsigned HOST_WIDE_INT
*new_bitnum
)
334 *new_bitnum
= bitnum
% BITS_PER_UNIT
;
335 HOST_WIDE_INT offset
= bitnum
/ BITS_PER_UNIT
;
336 HOST_WIDE_INT size
= ((*new_bitnum
+ bitsize
+ BITS_PER_UNIT
- 1)
338 return adjust_bitfield_address_size (mem
, mode
, offset
, size
);
342 unsigned int unit
= GET_MODE_BITSIZE (mode
);
343 *new_bitnum
= bitnum
% unit
;
344 HOST_WIDE_INT offset
= (bitnum
- *new_bitnum
) / BITS_PER_UNIT
;
345 return adjust_bitfield_address (mem
, mode
, offset
);
349 /* The caller wants to perform insertion or extraction PATTERN on a
350 bitfield of size BITSIZE at BITNUM bits into memory operand OP0.
351 BITREGION_START and BITREGION_END are as for store_bit_field
352 and FIELDMODE is the natural mode of the field.
354 Search for a mode that is compatible with the memory access
355 restrictions and (where applicable) with a register insertion or
356 extraction. Return the new memory on success, storing the adjusted
357 bit position in *NEW_BITNUM. Return null otherwise. */
360 adjust_bit_field_mem_for_reg (enum extraction_pattern pattern
,
361 rtx op0
, HOST_WIDE_INT bitsize
,
362 HOST_WIDE_INT bitnum
,
363 unsigned HOST_WIDE_INT bitregion_start
,
364 unsigned HOST_WIDE_INT bitregion_end
,
365 enum machine_mode fieldmode
,
366 unsigned HOST_WIDE_INT
*new_bitnum
)
368 bit_field_mode_iterator
iter (bitsize
, bitnum
, bitregion_start
,
369 bitregion_end
, MEM_ALIGN (op0
),
370 MEM_VOLATILE_P (op0
));
371 enum machine_mode best_mode
;
372 if (iter
.next_mode (&best_mode
))
374 /* We can use a memory in BEST_MODE. See whether this is true for
375 any wider modes. All other things being equal, we prefer to
376 use the widest mode possible because it tends to expose more
377 CSE opportunities. */
378 if (!iter
.prefer_smaller_modes ())
380 /* Limit the search to the mode required by the corresponding
381 register insertion or extraction instruction, if any. */
382 enum machine_mode limit_mode
= word_mode
;
383 extraction_insn insn
;
384 if (get_best_reg_extraction_insn (&insn
, pattern
,
385 GET_MODE_BITSIZE (best_mode
),
387 limit_mode
= insn
.field_mode
;
389 enum machine_mode wider_mode
;
390 while (iter
.next_mode (&wider_mode
)
391 && GET_MODE_SIZE (wider_mode
) <= GET_MODE_SIZE (limit_mode
))
392 best_mode
= wider_mode
;
394 return narrow_bit_field_mem (op0
, best_mode
, bitsize
, bitnum
,
400 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
401 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
402 offset is then BITNUM / BITS_PER_UNIT. */
405 lowpart_bit_field_p (unsigned HOST_WIDE_INT bitnum
,
406 unsigned HOST_WIDE_INT bitsize
,
407 enum machine_mode struct_mode
)
409 if (BYTES_BIG_ENDIAN
)
410 return (bitnum
% BITS_PER_UNIT
== 0
411 && (bitnum
+ bitsize
== GET_MODE_BITSIZE (struct_mode
)
412 || (bitnum
+ bitsize
) % BITS_PER_WORD
== 0));
414 return bitnum
% BITS_PER_WORD
== 0;
417 /* Return true if -fstrict-volatile-bitfields applies to an access of OP0
418 containing BITSIZE bits starting at BITNUM, with field mode FIELDMODE.
419 Return false if the access would touch memory outside the range
420 BITREGION_START to BITREGION_END for conformance to the C++ memory
424 strict_volatile_bitfield_p (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
425 unsigned HOST_WIDE_INT bitnum
,
426 enum machine_mode fieldmode
,
427 unsigned HOST_WIDE_INT bitregion_start
,
428 unsigned HOST_WIDE_INT bitregion_end
)
430 unsigned HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (fieldmode
);
432 /* -fstrict-volatile-bitfields must be enabled and we must have a
435 || !MEM_VOLATILE_P (op0
)
436 || flag_strict_volatile_bitfields
<= 0)
439 /* Non-integral modes likely only happen with packed structures.
441 if (!SCALAR_INT_MODE_P (fieldmode
))
444 /* The bit size must not be larger than the field mode, and
445 the field mode must not be larger than a word. */
446 if (bitsize
> modesize
|| modesize
> BITS_PER_WORD
)
449 /* Check for cases of unaligned fields that must be split. */
450 if (bitnum
% BITS_PER_UNIT
+ bitsize
> modesize
452 && bitnum
% GET_MODE_ALIGNMENT (fieldmode
) + bitsize
> modesize
))
455 /* Check for cases where the C++ memory model applies. */
456 if (bitregion_end
!= 0
457 && (bitnum
- bitnum
% modesize
< bitregion_start
458 || bitnum
- bitnum
% modesize
+ modesize
> bitregion_end
))
464 /* Return true if OP is a memory and if a bitfield of size BITSIZE at
465 bit number BITNUM can be treated as a simple value of mode MODE. */
468 simple_mem_bitfield_p (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
469 unsigned HOST_WIDE_INT bitnum
, enum machine_mode mode
)
472 && bitnum
% BITS_PER_UNIT
== 0
473 && bitsize
== GET_MODE_BITSIZE (mode
)
474 && (!SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (op0
))
475 || (bitnum
% GET_MODE_ALIGNMENT (mode
) == 0
476 && MEM_ALIGN (op0
) >= GET_MODE_ALIGNMENT (mode
))));
479 /* Try to use instruction INSV to store VALUE into a field of OP0.
480 BITSIZE and BITNUM are as for store_bit_field. */
483 store_bit_field_using_insv (const extraction_insn
*insv
, rtx op0
,
484 unsigned HOST_WIDE_INT bitsize
,
485 unsigned HOST_WIDE_INT bitnum
,
488 struct expand_operand ops
[4];
491 rtx_insn
*last
= get_last_insn ();
492 bool copy_back
= false;
494 enum machine_mode op_mode
= insv
->field_mode
;
495 unsigned int unit
= GET_MODE_BITSIZE (op_mode
);
496 if (bitsize
== 0 || bitsize
> unit
)
500 /* Get a reference to the first byte of the field. */
501 xop0
= narrow_bit_field_mem (xop0
, insv
->struct_mode
, bitsize
, bitnum
,
505 /* Convert from counting within OP0 to counting in OP_MODE. */
506 if (BYTES_BIG_ENDIAN
)
507 bitnum
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
509 /* If xop0 is a register, we need it in OP_MODE
510 to make it acceptable to the format of insv. */
511 if (GET_CODE (xop0
) == SUBREG
)
512 /* We can't just change the mode, because this might clobber op0,
513 and we will need the original value of op0 if insv fails. */
514 xop0
= gen_rtx_SUBREG (op_mode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
515 if (REG_P (xop0
) && GET_MODE (xop0
) != op_mode
)
516 xop0
= gen_lowpart_SUBREG (op_mode
, xop0
);
519 /* If the destination is a paradoxical subreg such that we need a
520 truncate to the inner mode, perform the insertion on a temporary and
521 truncate the result to the original destination. Note that we can't
522 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
523 X) 0)) is (reg:N X). */
524 if (GET_CODE (xop0
) == SUBREG
525 && REG_P (SUBREG_REG (xop0
))
526 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0
)),
529 rtx tem
= gen_reg_rtx (op_mode
);
530 emit_move_insn (tem
, xop0
);
535 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
536 "backwards" from the size of the unit we are inserting into.
537 Otherwise, we count bits from the most significant on a
538 BYTES/BITS_BIG_ENDIAN machine. */
540 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
541 bitnum
= unit
- bitsize
- bitnum
;
543 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
545 if (GET_MODE (value
) != op_mode
)
547 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
549 /* Optimization: Don't bother really extending VALUE
550 if it has all the bits we will actually use. However,
551 if we must narrow it, be sure we do it correctly. */
553 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (op_mode
))
557 tmp
= simplify_subreg (op_mode
, value1
, GET_MODE (value
), 0);
559 tmp
= simplify_gen_subreg (op_mode
,
560 force_reg (GET_MODE (value
),
562 GET_MODE (value
), 0);
566 value1
= gen_lowpart (op_mode
, value1
);
568 else if (CONST_INT_P (value
))
569 value1
= gen_int_mode (INTVAL (value
), op_mode
);
571 /* Parse phase is supposed to make VALUE's data type
572 match that of the component reference, which is a type
573 at least as wide as the field; so VALUE should have
574 a mode that corresponds to that type. */
575 gcc_assert (CONSTANT_P (value
));
578 create_fixed_operand (&ops
[0], xop0
);
579 create_integer_operand (&ops
[1], bitsize
);
580 create_integer_operand (&ops
[2], bitnum
);
581 create_input_operand (&ops
[3], value1
, op_mode
);
582 if (maybe_expand_insn (insv
->icode
, 4, ops
))
585 convert_move (op0
, xop0
, true);
588 delete_insns_since (last
);
592 /* A subroutine of store_bit_field, with the same arguments. Return true
593 if the operation could be implemented.
595 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
596 no other way of implementing the operation. If FALLBACK_P is false,
597 return false instead. */
600 store_bit_field_1 (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
601 unsigned HOST_WIDE_INT bitnum
,
602 unsigned HOST_WIDE_INT bitregion_start
,
603 unsigned HOST_WIDE_INT bitregion_end
,
604 enum machine_mode fieldmode
,
605 rtx value
, bool fallback_p
)
610 while (GET_CODE (op0
) == SUBREG
)
612 /* The following line once was done only if WORDS_BIG_ENDIAN,
613 but I think that is a mistake. WORDS_BIG_ENDIAN is
614 meaningful at a much higher level; when structures are copied
615 between memory and regs, the higher-numbered regs
616 always get higher addresses. */
617 int inner_mode_size
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)));
618 int outer_mode_size
= GET_MODE_SIZE (GET_MODE (op0
));
621 /* Paradoxical subregs need special handling on big endian machines. */
622 if (SUBREG_BYTE (op0
) == 0 && inner_mode_size
< outer_mode_size
)
624 int difference
= inner_mode_size
- outer_mode_size
;
626 if (WORDS_BIG_ENDIAN
)
627 byte_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
628 if (BYTES_BIG_ENDIAN
)
629 byte_offset
+= difference
% UNITS_PER_WORD
;
632 byte_offset
= SUBREG_BYTE (op0
);
634 bitnum
+= byte_offset
* BITS_PER_UNIT
;
635 op0
= SUBREG_REG (op0
);
638 /* No action is needed if the target is a register and if the field
639 lies completely outside that register. This can occur if the source
640 code contains an out-of-bounds access to a small array. */
641 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
644 /* Use vec_set patterns for inserting parts of vectors whenever
646 if (VECTOR_MODE_P (GET_MODE (op0
))
648 && optab_handler (vec_set_optab
, GET_MODE (op0
)) != CODE_FOR_nothing
649 && fieldmode
== GET_MODE_INNER (GET_MODE (op0
))
650 && bitsize
== GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
651 && !(bitnum
% GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
653 struct expand_operand ops
[3];
654 enum machine_mode outermode
= GET_MODE (op0
);
655 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
656 enum insn_code icode
= optab_handler (vec_set_optab
, outermode
);
657 int pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
659 create_fixed_operand (&ops
[0], op0
);
660 create_input_operand (&ops
[1], value
, innermode
);
661 create_integer_operand (&ops
[2], pos
);
662 if (maybe_expand_insn (icode
, 3, ops
))
666 /* If the target is a register, overwriting the entire object, or storing
667 a full-word or multi-word field can be done with just a SUBREG. */
669 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
670 && ((bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)) && bitnum
== 0)
671 || (bitsize
% BITS_PER_WORD
== 0 && bitnum
% BITS_PER_WORD
== 0)))
673 /* Use the subreg machinery either to narrow OP0 to the required
674 words or to cope with mode punning between equal-sized modes.
675 In the latter case, use subreg on the rhs side, not lhs. */
678 if (bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
680 sub
= simplify_gen_subreg (GET_MODE (op0
), value
, fieldmode
, 0);
683 emit_move_insn (op0
, sub
);
689 sub
= simplify_gen_subreg (fieldmode
, op0
, GET_MODE (op0
),
690 bitnum
/ BITS_PER_UNIT
);
693 emit_move_insn (sub
, value
);
699 /* If the target is memory, storing any naturally aligned field can be
700 done with a simple store. For targets that support fast unaligned
701 memory, any naturally sized, unit aligned field can be done directly. */
702 if (simple_mem_bitfield_p (op0
, bitsize
, bitnum
, fieldmode
))
704 op0
= adjust_bitfield_address (op0
, fieldmode
, bitnum
/ BITS_PER_UNIT
);
705 emit_move_insn (op0
, value
);
709 /* Make sure we are playing with integral modes. Pun with subregs
710 if we aren't. This must come after the entire register case above,
711 since that case is valid for any mode. The following cases are only
712 valid for integral modes. */
714 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
715 if (imode
!= GET_MODE (op0
))
718 op0
= adjust_bitfield_address_size (op0
, imode
, 0, MEM_SIZE (op0
));
721 gcc_assert (imode
!= BLKmode
);
722 op0
= gen_lowpart (imode
, op0
);
727 /* Storing an lsb-aligned field in a register
728 can be done with a movstrict instruction. */
731 && lowpart_bit_field_p (bitnum
, bitsize
, GET_MODE (op0
))
732 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
733 && optab_handler (movstrict_optab
, fieldmode
) != CODE_FOR_nothing
)
735 struct expand_operand ops
[2];
736 enum insn_code icode
= optab_handler (movstrict_optab
, fieldmode
);
738 unsigned HOST_WIDE_INT subreg_off
;
740 if (GET_CODE (arg0
) == SUBREG
)
742 /* Else we've got some float mode source being extracted into
743 a different float mode destination -- this combination of
744 subregs results in Severe Tire Damage. */
745 gcc_assert (GET_MODE (SUBREG_REG (arg0
)) == fieldmode
746 || GET_MODE_CLASS (fieldmode
) == MODE_INT
747 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
);
748 arg0
= SUBREG_REG (arg0
);
751 subreg_off
= bitnum
/ BITS_PER_UNIT
;
752 if (validate_subreg (fieldmode
, GET_MODE (arg0
), arg0
, subreg_off
))
754 arg0
= gen_rtx_SUBREG (fieldmode
, arg0
, subreg_off
);
756 create_fixed_operand (&ops
[0], arg0
);
757 /* Shrink the source operand to FIELDMODE. */
758 create_convert_operand_to (&ops
[1], value
, fieldmode
, false);
759 if (maybe_expand_insn (icode
, 2, ops
))
764 /* Handle fields bigger than a word. */
766 if (bitsize
> BITS_PER_WORD
)
768 /* Here we transfer the words of the field
769 in the order least significant first.
770 This is because the most significant word is the one which may
772 However, only do that if the value is not BLKmode. */
774 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
775 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
779 /* This is the mode we must force value to, so that there will be enough
780 subwords to extract. Note that fieldmode will often (always?) be
781 VOIDmode, because that is what store_field uses to indicate that this
782 is a bit field, but passing VOIDmode to operand_subword_force
784 fieldmode
= GET_MODE (value
);
785 if (fieldmode
== VOIDmode
)
786 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
788 last
= get_last_insn ();
789 for (i
= 0; i
< nwords
; i
++)
791 /* If I is 0, use the low-order word in both field and target;
792 if I is 1, use the next to lowest word; and so on. */
793 unsigned int wordnum
= (backwards
794 ? GET_MODE_SIZE (fieldmode
) / UNITS_PER_WORD
797 unsigned int bit_offset
= (backwards
798 ? MAX ((int) bitsize
- ((int) i
+ 1)
801 : (int) i
* BITS_PER_WORD
);
802 rtx value_word
= operand_subword_force (value
, wordnum
, fieldmode
);
803 unsigned HOST_WIDE_INT new_bitsize
=
804 MIN (BITS_PER_WORD
, bitsize
- i
* BITS_PER_WORD
);
806 /* If the remaining chunk doesn't have full wordsize we have
807 to make sure that for big endian machines the higher order
809 if (new_bitsize
< BITS_PER_WORD
&& BYTES_BIG_ENDIAN
&& !backwards
)
810 value_word
= simplify_expand_binop (word_mode
, lshr_optab
,
812 GEN_INT (BITS_PER_WORD
817 if (!store_bit_field_1 (op0
, new_bitsize
,
819 bitregion_start
, bitregion_end
,
821 value_word
, fallback_p
))
823 delete_insns_since (last
);
830 /* If VALUE has a floating-point or complex mode, access it as an
831 integer of the corresponding size. This can occur on a machine
832 with 64 bit registers that uses SFmode for float. It can also
833 occur for unaligned float or complex fields. */
835 if (GET_MODE (value
) != VOIDmode
836 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_INT
837 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_PARTIAL_INT
)
839 value
= gen_reg_rtx (int_mode_for_mode (GET_MODE (value
)));
840 emit_move_insn (gen_lowpart (GET_MODE (orig_value
), value
), orig_value
);
843 /* If OP0 is a multi-word register, narrow it to the affected word.
844 If the region spans two words, defer to store_split_bit_field. */
845 if (!MEM_P (op0
) && GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
847 op0
= simplify_gen_subreg (word_mode
, op0
, GET_MODE (op0
),
848 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
850 bitnum
%= BITS_PER_WORD
;
851 if (bitnum
+ bitsize
> BITS_PER_WORD
)
856 store_split_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
857 bitregion_end
, value
);
862 /* From here on we can assume that the field to be stored in fits
863 within a word. If the destination is a register, it too fits
866 extraction_insn insv
;
868 && get_best_reg_extraction_insn (&insv
, EP_insv
,
869 GET_MODE_BITSIZE (GET_MODE (op0
)),
871 && store_bit_field_using_insv (&insv
, op0
, bitsize
, bitnum
, value
))
874 /* If OP0 is a memory, try copying it to a register and seeing if a
875 cheap register alternative is available. */
878 if (get_best_mem_extraction_insn (&insv
, EP_insv
, bitsize
, bitnum
,
880 && store_bit_field_using_insv (&insv
, op0
, bitsize
, bitnum
, value
))
883 rtx_insn
*last
= get_last_insn ();
885 /* Try loading part of OP0 into a register, inserting the bitfield
886 into that, and then copying the result back to OP0. */
887 unsigned HOST_WIDE_INT bitpos
;
888 rtx xop0
= adjust_bit_field_mem_for_reg (EP_insv
, op0
, bitsize
, bitnum
,
889 bitregion_start
, bitregion_end
,
893 rtx tempreg
= copy_to_reg (xop0
);
894 if (store_bit_field_1 (tempreg
, bitsize
, bitpos
,
895 bitregion_start
, bitregion_end
,
896 fieldmode
, orig_value
, false))
898 emit_move_insn (xop0
, tempreg
);
901 delete_insns_since (last
);
908 store_fixed_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
909 bitregion_end
, value
);
913 /* Generate code to store value from rtx VALUE
914 into a bit-field within structure STR_RTX
915 containing BITSIZE bits starting at bit BITNUM.
917 BITREGION_START is bitpos of the first bitfield in this region.
918 BITREGION_END is the bitpos of the ending bitfield in this region.
919 These two fields are 0, if the C++ memory model does not apply,
920 or we are not interested in keeping track of bitfield regions.
922 FIELDMODE is the machine-mode of the FIELD_DECL node for this field. */
925 store_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
926 unsigned HOST_WIDE_INT bitnum
,
927 unsigned HOST_WIDE_INT bitregion_start
,
928 unsigned HOST_WIDE_INT bitregion_end
,
929 enum machine_mode fieldmode
,
932 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
933 if (strict_volatile_bitfield_p (str_rtx
, bitsize
, bitnum
, fieldmode
,
934 bitregion_start
, bitregion_end
))
936 /* Storing any naturally aligned field can be done with a simple
937 store. For targets that support fast unaligned memory, any
938 naturally sized, unit aligned field can be done directly. */
939 if (simple_mem_bitfield_p (str_rtx
, bitsize
, bitnum
, fieldmode
))
941 str_rtx
= adjust_bitfield_address (str_rtx
, fieldmode
,
942 bitnum
/ BITS_PER_UNIT
);
943 emit_move_insn (str_rtx
, value
);
947 str_rtx
= narrow_bit_field_mem (str_rtx
, fieldmode
, bitsize
, bitnum
,
949 /* Explicitly override the C/C++ memory model; ignore the
950 bit range so that we can do the access in the mode mandated
951 by -fstrict-volatile-bitfields instead. */
952 store_fixed_bit_field_1 (str_rtx
, bitsize
, bitnum
, value
);
958 /* Under the C++0x memory model, we must not touch bits outside the
959 bit region. Adjust the address to start at the beginning of the
961 if (MEM_P (str_rtx
) && bitregion_start
> 0)
963 enum machine_mode bestmode
;
964 HOST_WIDE_INT offset
, size
;
966 gcc_assert ((bitregion_start
% BITS_PER_UNIT
) == 0);
968 offset
= bitregion_start
/ BITS_PER_UNIT
;
969 bitnum
-= bitregion_start
;
970 size
= (bitnum
+ bitsize
+ BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
971 bitregion_end
-= bitregion_start
;
973 bestmode
= get_best_mode (bitsize
, bitnum
,
974 bitregion_start
, bitregion_end
,
975 MEM_ALIGN (str_rtx
), VOIDmode
,
976 MEM_VOLATILE_P (str_rtx
));
977 str_rtx
= adjust_bitfield_address_size (str_rtx
, bestmode
, offset
, size
);
980 if (!store_bit_field_1 (str_rtx
, bitsize
, bitnum
,
981 bitregion_start
, bitregion_end
,
982 fieldmode
, value
, true))
986 /* Use shifts and boolean operations to store VALUE into a bit field of
987 width BITSIZE in OP0, starting at bit BITNUM. */
990 store_fixed_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
991 unsigned HOST_WIDE_INT bitnum
,
992 unsigned HOST_WIDE_INT bitregion_start
,
993 unsigned HOST_WIDE_INT bitregion_end
,
996 /* There is a case not handled here:
997 a structure with a known alignment of just a halfword
998 and a field split across two aligned halfwords within the structure.
999 Or likewise a structure with a known alignment of just a byte
1000 and a field split across two bytes.
1001 Such cases are not supposed to be able to occur. */
1005 enum machine_mode mode
= GET_MODE (op0
);
1006 if (GET_MODE_BITSIZE (mode
) == 0
1007 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
1009 mode
= get_best_mode (bitsize
, bitnum
, bitregion_start
, bitregion_end
,
1010 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
1012 if (mode
== VOIDmode
)
1014 /* The only way this should occur is if the field spans word
1016 store_split_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
1017 bitregion_end
, value
);
1021 op0
= narrow_bit_field_mem (op0
, mode
, bitsize
, bitnum
, &bitnum
);
1024 store_fixed_bit_field_1 (op0
, bitsize
, bitnum
, value
);
1027 /* Helper function for store_fixed_bit_field, stores
1028 the bit field always using the MODE of OP0. */
1031 store_fixed_bit_field_1 (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1032 unsigned HOST_WIDE_INT bitnum
,
1035 enum machine_mode mode
;
1040 mode
= GET_MODE (op0
);
1041 gcc_assert (SCALAR_INT_MODE_P (mode
));
1043 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1044 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
1046 if (BYTES_BIG_ENDIAN
)
1047 /* BITNUM is the distance between our msb
1048 and that of the containing datum.
1049 Convert it to the distance from the lsb. */
1050 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
1052 /* Now BITNUM is always the distance between our lsb
1055 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
1056 we must first convert its mode to MODE. */
1058 if (CONST_INT_P (value
))
1060 HOST_WIDE_INT v
= INTVAL (value
);
1062 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1063 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
1067 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
1068 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
1069 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
1072 value
= lshift_value (mode
, v
, bitnum
);
1076 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
1077 && bitnum
+ bitsize
!= GET_MODE_BITSIZE (mode
));
1079 if (GET_MODE (value
) != mode
)
1080 value
= convert_to_mode (mode
, value
, 1);
1083 value
= expand_binop (mode
, and_optab
, value
,
1084 mask_rtx (mode
, 0, bitsize
, 0),
1085 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1087 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
1088 bitnum
, NULL_RTX
, 1);
1091 /* Now clear the chosen bits in OP0,
1092 except that if VALUE is -1 we need not bother. */
1093 /* We keep the intermediates in registers to allow CSE to combine
1094 consecutive bitfield assignments. */
1096 temp
= force_reg (mode
, op0
);
1100 temp
= expand_binop (mode
, and_optab
, temp
,
1101 mask_rtx (mode
, bitnum
, bitsize
, 1),
1102 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1103 temp
= force_reg (mode
, temp
);
1106 /* Now logical-or VALUE into OP0, unless it is zero. */
1110 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
1111 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1112 temp
= force_reg (mode
, temp
);
1117 op0
= copy_rtx (op0
);
1118 emit_move_insn (op0
, temp
);
1122 /* Store a bit field that is split across multiple accessible memory objects.
1124 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1125 BITSIZE is the field width; BITPOS the position of its first bit
1127 VALUE is the value to store.
1129 This does not yet handle fields wider than BITS_PER_WORD. */
1132 store_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1133 unsigned HOST_WIDE_INT bitpos
,
1134 unsigned HOST_WIDE_INT bitregion_start
,
1135 unsigned HOST_WIDE_INT bitregion_end
,
1139 unsigned int bitsdone
= 0;
1141 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1143 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1144 unit
= BITS_PER_WORD
;
1146 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1148 /* If OP0 is a memory with a mode, then UNIT must not be larger than
1149 OP0's mode as well. Otherwise, store_fixed_bit_field will call us
1150 again, and we will mutually recurse forever. */
1151 if (MEM_P (op0
) && GET_MODE_BITSIZE (GET_MODE (op0
)) > 0)
1152 unit
= MIN (unit
, GET_MODE_BITSIZE (GET_MODE (op0
)));
1154 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1155 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1156 that VALUE might be a floating-point constant. */
1157 if (CONSTANT_P (value
) && !CONST_INT_P (value
))
1159 rtx word
= gen_lowpart_common (word_mode
, value
);
1161 if (word
&& (value
!= word
))
1164 value
= gen_lowpart_common (word_mode
,
1165 force_reg (GET_MODE (value
) != VOIDmode
1167 : word_mode
, value
));
1170 while (bitsdone
< bitsize
)
1172 unsigned HOST_WIDE_INT thissize
;
1174 unsigned HOST_WIDE_INT thispos
;
1175 unsigned HOST_WIDE_INT offset
;
1177 offset
= (bitpos
+ bitsdone
) / unit
;
1178 thispos
= (bitpos
+ bitsdone
) % unit
;
1180 /* When region of bytes we can touch is restricted, decrease
1181 UNIT close to the end of the region as needed. If op0 is a REG
1182 or SUBREG of REG, don't do this, as there can't be data races
1183 on a register and we can expand shorter code in some cases. */
1185 && unit
> BITS_PER_UNIT
1186 && bitpos
+ bitsdone
- thispos
+ unit
> bitregion_end
+ 1
1188 && (GET_CODE (op0
) != SUBREG
|| !REG_P (SUBREG_REG (op0
))))
1194 /* THISSIZE must not overrun a word boundary. Otherwise,
1195 store_fixed_bit_field will call us again, and we will mutually
1197 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1198 thissize
= MIN (thissize
, unit
- thispos
);
1200 if (BYTES_BIG_ENDIAN
)
1202 /* Fetch successively less significant portions. */
1203 if (CONST_INT_P (value
))
1204 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1205 >> (bitsize
- bitsdone
- thissize
))
1206 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1209 int total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
1210 /* The args are chosen so that the last part includes the
1211 lsb. Give extract_bit_field the value it needs (with
1212 endianness compensation) to fetch the piece we want. */
1213 part
= extract_fixed_bit_field (word_mode
, value
, thissize
,
1214 total_bits
- bitsize
+ bitsdone
,
1220 /* Fetch successively more significant portions. */
1221 if (CONST_INT_P (value
))
1222 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1224 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1226 part
= extract_fixed_bit_field (word_mode
, value
, thissize
,
1227 bitsdone
, NULL_RTX
, 1);
1230 /* If OP0 is a register, then handle OFFSET here.
1232 When handling multiword bitfields, extract_bit_field may pass
1233 down a word_mode SUBREG of a larger REG for a bitfield that actually
1234 crosses a word boundary. Thus, for a SUBREG, we must find
1235 the current word starting from the base register. */
1236 if (GET_CODE (op0
) == SUBREG
)
1238 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
)
1239 + (offset
* unit
/ BITS_PER_WORD
);
1240 enum machine_mode sub_mode
= GET_MODE (SUBREG_REG (op0
));
1241 if (sub_mode
!= BLKmode
&& GET_MODE_SIZE (sub_mode
) < UNITS_PER_WORD
)
1242 word
= word_offset
? const0_rtx
: op0
;
1244 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1245 GET_MODE (SUBREG_REG (op0
)));
1246 offset
&= BITS_PER_WORD
/ unit
- 1;
1248 else if (REG_P (op0
))
1250 enum machine_mode op0_mode
= GET_MODE (op0
);
1251 if (op0_mode
!= BLKmode
&& GET_MODE_SIZE (op0_mode
) < UNITS_PER_WORD
)
1252 word
= offset
? const0_rtx
: op0
;
1254 word
= operand_subword_force (op0
, offset
* unit
/ BITS_PER_WORD
,
1256 offset
&= BITS_PER_WORD
/ unit
- 1;
1261 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1262 it is just an out-of-bounds access. Ignore it. */
1263 if (word
!= const0_rtx
)
1264 store_fixed_bit_field (word
, thissize
, offset
* unit
+ thispos
,
1265 bitregion_start
, bitregion_end
, part
);
1266 bitsdone
+= thissize
;
1270 /* A subroutine of extract_bit_field_1 that converts return value X
1271 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1272 to extract_bit_field. */
1275 convert_extracted_bit_field (rtx x
, enum machine_mode mode
,
1276 enum machine_mode tmode
, bool unsignedp
)
1278 if (GET_MODE (x
) == tmode
|| GET_MODE (x
) == mode
)
1281 /* If the x mode is not a scalar integral, first convert to the
1282 integer mode of that size and then access it as a floating-point
1283 value via a SUBREG. */
1284 if (!SCALAR_INT_MODE_P (tmode
))
1286 enum machine_mode smode
;
1288 smode
= mode_for_size (GET_MODE_BITSIZE (tmode
), MODE_INT
, 0);
1289 x
= convert_to_mode (smode
, x
, unsignedp
);
1290 x
= force_reg (smode
, x
);
1291 return gen_lowpart (tmode
, x
);
1294 return convert_to_mode (tmode
, x
, unsignedp
);
1297 /* Try to use an ext(z)v pattern to extract a field from OP0.
1298 Return the extracted value on success, otherwise return null.
1299 EXT_MODE is the mode of the extraction and the other arguments
1300 are as for extract_bit_field. */
1303 extract_bit_field_using_extv (const extraction_insn
*extv
, rtx op0
,
1304 unsigned HOST_WIDE_INT bitsize
,
1305 unsigned HOST_WIDE_INT bitnum
,
1306 int unsignedp
, rtx target
,
1307 enum machine_mode mode
, enum machine_mode tmode
)
1309 struct expand_operand ops
[4];
1310 rtx spec_target
= target
;
1311 rtx spec_target_subreg
= 0;
1312 enum machine_mode ext_mode
= extv
->field_mode
;
1313 unsigned unit
= GET_MODE_BITSIZE (ext_mode
);
1315 if (bitsize
== 0 || unit
< bitsize
)
1319 /* Get a reference to the first byte of the field. */
1320 op0
= narrow_bit_field_mem (op0
, extv
->struct_mode
, bitsize
, bitnum
,
1324 /* Convert from counting within OP0 to counting in EXT_MODE. */
1325 if (BYTES_BIG_ENDIAN
)
1326 bitnum
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1328 /* If op0 is a register, we need it in EXT_MODE to make it
1329 acceptable to the format of ext(z)v. */
1330 if (GET_CODE (op0
) == SUBREG
&& GET_MODE (op0
) != ext_mode
)
1332 if (REG_P (op0
) && GET_MODE (op0
) != ext_mode
)
1333 op0
= gen_lowpart_SUBREG (ext_mode
, op0
);
1336 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1337 "backwards" from the size of the unit we are extracting from.
1338 Otherwise, we count bits from the most significant on a
1339 BYTES/BITS_BIG_ENDIAN machine. */
1341 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1342 bitnum
= unit
- bitsize
- bitnum
;
1345 target
= spec_target
= gen_reg_rtx (tmode
);
1347 if (GET_MODE (target
) != ext_mode
)
1349 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1350 between the mode of the extraction (word_mode) and the target
1351 mode. Instead, create a temporary and use convert_move to set
1354 && TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (target
), ext_mode
))
1356 target
= gen_lowpart (ext_mode
, target
);
1357 if (GET_MODE_PRECISION (ext_mode
)
1358 > GET_MODE_PRECISION (GET_MODE (spec_target
)))
1359 spec_target_subreg
= target
;
1362 target
= gen_reg_rtx (ext_mode
);
1365 create_output_operand (&ops
[0], target
, ext_mode
);
1366 create_fixed_operand (&ops
[1], op0
);
1367 create_integer_operand (&ops
[2], bitsize
);
1368 create_integer_operand (&ops
[3], bitnum
);
1369 if (maybe_expand_insn (extv
->icode
, 4, ops
))
1371 target
= ops
[0].value
;
1372 if (target
== spec_target
)
1374 if (target
== spec_target_subreg
)
1376 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1381 /* A subroutine of extract_bit_field, with the same arguments.
1382 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1383 if we can find no other means of implementing the operation.
1384 if FALLBACK_P is false, return NULL instead. */
1387 extract_bit_field_1 (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1388 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1389 enum machine_mode mode
, enum machine_mode tmode
,
1393 enum machine_mode int_mode
;
1394 enum machine_mode mode1
;
1396 if (tmode
== VOIDmode
)
1399 while (GET_CODE (op0
) == SUBREG
)
1401 bitnum
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1402 op0
= SUBREG_REG (op0
);
1405 /* If we have an out-of-bounds access to a register, just return an
1406 uninitialized register of the required mode. This can occur if the
1407 source code contains an out-of-bounds access to a small array. */
1408 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
1409 return gen_reg_rtx (tmode
);
1412 && mode
== GET_MODE (op0
)
1414 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1416 /* We're trying to extract a full register from itself. */
1420 /* See if we can get a better vector mode before extracting. */
1421 if (VECTOR_MODE_P (GET_MODE (op0
))
1423 && GET_MODE_INNER (GET_MODE (op0
)) != tmode
)
1425 enum machine_mode new_mode
;
1427 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1428 new_mode
= MIN_MODE_VECTOR_FLOAT
;
1429 else if (GET_MODE_CLASS (tmode
) == MODE_FRACT
)
1430 new_mode
= MIN_MODE_VECTOR_FRACT
;
1431 else if (GET_MODE_CLASS (tmode
) == MODE_UFRACT
)
1432 new_mode
= MIN_MODE_VECTOR_UFRACT
;
1433 else if (GET_MODE_CLASS (tmode
) == MODE_ACCUM
)
1434 new_mode
= MIN_MODE_VECTOR_ACCUM
;
1435 else if (GET_MODE_CLASS (tmode
) == MODE_UACCUM
)
1436 new_mode
= MIN_MODE_VECTOR_UACCUM
;
1438 new_mode
= MIN_MODE_VECTOR_INT
;
1440 for (; new_mode
!= VOIDmode
; new_mode
= GET_MODE_WIDER_MODE (new_mode
))
1441 if (GET_MODE_SIZE (new_mode
) == GET_MODE_SIZE (GET_MODE (op0
))
1442 && targetm
.vector_mode_supported_p (new_mode
))
1444 if (new_mode
!= VOIDmode
)
1445 op0
= gen_lowpart (new_mode
, op0
);
1448 /* Use vec_extract patterns for extracting parts of vectors whenever
1450 if (VECTOR_MODE_P (GET_MODE (op0
))
1452 && optab_handler (vec_extract_optab
, GET_MODE (op0
)) != CODE_FOR_nothing
1453 && ((bitnum
+ bitsize
- 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
1454 == bitnum
/ GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
1456 struct expand_operand ops
[3];
1457 enum machine_mode outermode
= GET_MODE (op0
);
1458 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
1459 enum insn_code icode
= optab_handler (vec_extract_optab
, outermode
);
1460 unsigned HOST_WIDE_INT pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
1462 create_output_operand (&ops
[0], target
, innermode
);
1463 create_input_operand (&ops
[1], op0
, outermode
);
1464 create_integer_operand (&ops
[2], pos
);
1465 if (maybe_expand_insn (icode
, 3, ops
))
1467 target
= ops
[0].value
;
1468 if (GET_MODE (target
) != mode
)
1469 return gen_lowpart (tmode
, target
);
1474 /* Make sure we are playing with integral modes. Pun with subregs
1477 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1478 if (imode
!= GET_MODE (op0
))
1481 op0
= adjust_bitfield_address_size (op0
, imode
, 0, MEM_SIZE (op0
));
1482 else if (imode
!= BLKmode
)
1484 op0
= gen_lowpart (imode
, op0
);
1486 /* If we got a SUBREG, force it into a register since we
1487 aren't going to be able to do another SUBREG on it. */
1488 if (GET_CODE (op0
) == SUBREG
)
1489 op0
= force_reg (imode
, op0
);
1491 else if (REG_P (op0
))
1494 imode
= smallest_mode_for_size (GET_MODE_BITSIZE (GET_MODE (op0
)),
1496 reg
= gen_reg_rtx (imode
);
1497 subreg
= gen_lowpart_SUBREG (GET_MODE (op0
), reg
);
1498 emit_move_insn (subreg
, op0
);
1500 bitnum
+= SUBREG_BYTE (subreg
) * BITS_PER_UNIT
;
1504 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (op0
));
1505 rtx mem
= assign_stack_temp (GET_MODE (op0
), size
);
1506 emit_move_insn (mem
, op0
);
1507 op0
= adjust_bitfield_address_size (mem
, BLKmode
, 0, size
);
1512 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1513 If that's wrong, the solution is to test for it and set TARGET to 0
1516 /* Get the mode of the field to use for atomic access or subreg
1519 if (SCALAR_INT_MODE_P (tmode
))
1521 enum machine_mode try_mode
= mode_for_size (bitsize
,
1522 GET_MODE_CLASS (tmode
), 0);
1523 if (try_mode
!= BLKmode
)
1526 gcc_assert (mode1
!= BLKmode
);
1528 /* Extraction of a full MODE1 value can be done with a subreg as long
1529 as the least significant bit of the value is the least significant
1530 bit of either OP0 or a word of OP0. */
1532 && lowpart_bit_field_p (bitnum
, bitsize
, GET_MODE (op0
))
1533 && bitsize
== GET_MODE_BITSIZE (mode1
)
1534 && TRULY_NOOP_TRUNCATION_MODES_P (mode1
, GET_MODE (op0
)))
1536 rtx sub
= simplify_gen_subreg (mode1
, op0
, GET_MODE (op0
),
1537 bitnum
/ BITS_PER_UNIT
);
1539 return convert_extracted_bit_field (sub
, mode
, tmode
, unsignedp
);
1542 /* Extraction of a full MODE1 value can be done with a load as long as
1543 the field is on a byte boundary and is sufficiently aligned. */
1544 if (simple_mem_bitfield_p (op0
, bitsize
, bitnum
, mode1
))
1546 op0
= adjust_bitfield_address (op0
, mode1
, bitnum
/ BITS_PER_UNIT
);
1547 return convert_extracted_bit_field (op0
, mode
, tmode
, unsignedp
);
1550 /* Handle fields bigger than a word. */
1552 if (bitsize
> BITS_PER_WORD
)
1554 /* Here we transfer the words of the field
1555 in the order least significant first.
1556 This is because the most significant word is the one which may
1557 be less than full. */
1559 unsigned int backwards
= WORDS_BIG_ENDIAN
;
1560 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1564 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1565 target
= gen_reg_rtx (mode
);
1567 /* Indicate for flow that the entire target reg is being set. */
1568 emit_clobber (target
);
1570 last
= get_last_insn ();
1571 for (i
= 0; i
< nwords
; i
++)
1573 /* If I is 0, use the low-order word in both field and target;
1574 if I is 1, use the next to lowest word; and so on. */
1575 /* Word number in TARGET to use. */
1576 unsigned int wordnum
1578 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1580 /* Offset from start of field in OP0. */
1581 unsigned int bit_offset
= (backwards
1582 ? MAX ((int) bitsize
- ((int) i
+ 1)
1585 : (int) i
* BITS_PER_WORD
);
1586 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1588 = extract_bit_field_1 (op0
, MIN (BITS_PER_WORD
,
1589 bitsize
- i
* BITS_PER_WORD
),
1590 bitnum
+ bit_offset
, 1, target_part
,
1591 mode
, word_mode
, fallback_p
);
1593 gcc_assert (target_part
);
1596 delete_insns_since (last
);
1600 if (result_part
!= target_part
)
1601 emit_move_insn (target_part
, result_part
);
1606 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1607 need to be zero'd out. */
1608 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1610 unsigned int i
, total_words
;
1612 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1613 for (i
= nwords
; i
< total_words
; i
++)
1615 (operand_subword (target
,
1616 backwards
? total_words
- i
- 1 : i
,
1623 /* Signed bit field: sign-extend with two arithmetic shifts. */
1624 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1625 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1626 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1627 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1630 /* If OP0 is a multi-word register, narrow it to the affected word.
1631 If the region spans two words, defer to extract_split_bit_field. */
1632 if (!MEM_P (op0
) && GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1634 op0
= simplify_gen_subreg (word_mode
, op0
, GET_MODE (op0
),
1635 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
1636 bitnum
%= BITS_PER_WORD
;
1637 if (bitnum
+ bitsize
> BITS_PER_WORD
)
1641 target
= extract_split_bit_field (op0
, bitsize
, bitnum
, unsignedp
);
1642 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1646 /* From here on we know the desired field is smaller than a word.
1647 If OP0 is a register, it too fits within a word. */
1648 enum extraction_pattern pattern
= unsignedp
? EP_extzv
: EP_extv
;
1649 extraction_insn extv
;
1651 /* ??? We could limit the structure size to the part of OP0 that
1652 contains the field, with appropriate checks for endianness
1653 and TRULY_NOOP_TRUNCATION. */
1654 && get_best_reg_extraction_insn (&extv
, pattern
,
1655 GET_MODE_BITSIZE (GET_MODE (op0
)),
1658 rtx result
= extract_bit_field_using_extv (&extv
, op0
, bitsize
, bitnum
,
1659 unsignedp
, target
, mode
,
1665 /* If OP0 is a memory, try copying it to a register and seeing if a
1666 cheap register alternative is available. */
1669 if (get_best_mem_extraction_insn (&extv
, pattern
, bitsize
, bitnum
,
1672 rtx result
= extract_bit_field_using_extv (&extv
, op0
, bitsize
,
1680 rtx_insn
*last
= get_last_insn ();
1682 /* Try loading part of OP0 into a register and extracting the
1683 bitfield from that. */
1684 unsigned HOST_WIDE_INT bitpos
;
1685 rtx xop0
= adjust_bit_field_mem_for_reg (pattern
, op0
, bitsize
, bitnum
,
1686 0, 0, tmode
, &bitpos
);
1689 xop0
= copy_to_reg (xop0
);
1690 rtx result
= extract_bit_field_1 (xop0
, bitsize
, bitpos
,
1692 mode
, tmode
, false);
1695 delete_insns_since (last
);
1702 /* Find a correspondingly-sized integer field, so we can apply
1703 shifts and masks to it. */
1704 int_mode
= int_mode_for_mode (tmode
);
1705 if (int_mode
== BLKmode
)
1706 int_mode
= int_mode_for_mode (mode
);
1707 /* Should probably push op0 out to memory and then do a load. */
1708 gcc_assert (int_mode
!= BLKmode
);
1710 target
= extract_fixed_bit_field (int_mode
, op0
, bitsize
, bitnum
,
1712 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1715 /* Generate code to extract a byte-field from STR_RTX
1716 containing BITSIZE bits, starting at BITNUM,
1717 and put it in TARGET if possible (if TARGET is nonzero).
1718 Regardless of TARGET, we return the rtx for where the value is placed.
1720 STR_RTX is the structure containing the byte (a REG or MEM).
1721 UNSIGNEDP is nonzero if this is an unsigned bit field.
1722 MODE is the natural mode of the field value once extracted.
1723 TMODE is the mode the caller would like the value to have;
1724 but the value may be returned with type MODE instead.
1726 If a TARGET is specified and we can store in it at no extra cost,
1727 we do so, and return TARGET.
1728 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1729 if they are equally easy. */
1732 extract_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1733 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1734 enum machine_mode mode
, enum machine_mode tmode
)
1736 enum machine_mode mode1
;
1738 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
1739 if (GET_MODE_BITSIZE (GET_MODE (str_rtx
)) > 0)
1740 mode1
= GET_MODE (str_rtx
);
1741 else if (target
&& GET_MODE_BITSIZE (GET_MODE (target
)) > 0)
1742 mode1
= GET_MODE (target
);
1746 if (strict_volatile_bitfield_p (str_rtx
, bitsize
, bitnum
, mode1
, 0, 0))
1750 /* Extraction of a full MODE1 value can be done with a load as long as
1751 the field is on a byte boundary and is sufficiently aligned. */
1752 if (simple_mem_bitfield_p (str_rtx
, bitsize
, bitnum
, mode1
))
1753 result
= adjust_bitfield_address (str_rtx
, mode1
,
1754 bitnum
/ BITS_PER_UNIT
);
1757 str_rtx
= narrow_bit_field_mem (str_rtx
, mode1
, bitsize
, bitnum
,
1759 result
= extract_fixed_bit_field_1 (mode
, str_rtx
, bitsize
, bitnum
,
1763 return convert_extracted_bit_field (result
, mode
, tmode
, unsignedp
);
1766 return extract_bit_field_1 (str_rtx
, bitsize
, bitnum
, unsignedp
,
1767 target
, mode
, tmode
, true);
1770 /* Use shifts and boolean operations to extract a field of BITSIZE bits
1771 from bit BITNUM of OP0.
1773 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1774 If TARGET is nonzero, attempts to store the value there
1775 and return TARGET, but this is not guaranteed.
1776 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1779 extract_fixed_bit_field (enum machine_mode tmode
, rtx op0
,
1780 unsigned HOST_WIDE_INT bitsize
,
1781 unsigned HOST_WIDE_INT bitnum
, rtx target
,
1786 enum machine_mode mode
1787 = get_best_mode (bitsize
, bitnum
, 0, 0, MEM_ALIGN (op0
), word_mode
,
1788 MEM_VOLATILE_P (op0
));
1790 if (mode
== VOIDmode
)
1791 /* The only way this should occur is if the field spans word
1793 return extract_split_bit_field (op0
, bitsize
, bitnum
, unsignedp
);
1795 op0
= narrow_bit_field_mem (op0
, mode
, bitsize
, bitnum
, &bitnum
);
1798 return extract_fixed_bit_field_1 (tmode
, op0
, bitsize
, bitnum
,
1802 /* Helper function for extract_fixed_bit_field, extracts
1803 the bit field always using the MODE of OP0. */
1806 extract_fixed_bit_field_1 (enum machine_mode tmode
, rtx op0
,
1807 unsigned HOST_WIDE_INT bitsize
,
1808 unsigned HOST_WIDE_INT bitnum
, rtx target
,
1811 enum machine_mode mode
= GET_MODE (op0
);
1812 gcc_assert (SCALAR_INT_MODE_P (mode
));
1814 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1815 for invalid input, such as extract equivalent of f5 from
1816 gcc.dg/pr48335-2.c. */
1818 if (BYTES_BIG_ENDIAN
)
1819 /* BITNUM is the distance between our msb and that of OP0.
1820 Convert it to the distance from the lsb. */
1821 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
1823 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
1824 We have reduced the big-endian case to the little-endian case. */
1830 /* If the field does not already start at the lsb,
1831 shift it so it does. */
1832 /* Maybe propagate the target for the shift. */
1833 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1836 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, bitnum
, subtarget
, 1);
1838 /* Convert the value to the desired mode. */
1840 op0
= convert_to_mode (tmode
, op0
, 1);
1842 /* Unless the msb of the field used to be the msb when we shifted,
1843 mask out the upper bits. */
1845 if (GET_MODE_BITSIZE (mode
) != bitnum
+ bitsize
)
1846 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1847 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1848 target
, 1, OPTAB_LIB_WIDEN
);
1852 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1853 then arithmetic-shift its lsb to the lsb of the word. */
1854 op0
= force_reg (mode
, op0
);
1856 /* Find the narrowest integer mode that contains the field. */
1858 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1859 mode
= GET_MODE_WIDER_MODE (mode
))
1860 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitnum
)
1862 op0
= convert_to_mode (mode
, op0
, 0);
1869 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitnum
))
1871 int amount
= GET_MODE_BITSIZE (mode
) - (bitsize
+ bitnum
);
1872 /* Maybe propagate the target for the shift. */
1873 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1874 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1877 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1878 GET_MODE_BITSIZE (mode
) - bitsize
, target
, 0);
1881 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1885 lshift_value (enum machine_mode mode
, unsigned HOST_WIDE_INT value
,
1888 return immed_wide_int_const (wi::lshift (value
, bitpos
), mode
);
1891 /* Extract a bit field that is split across two words
1892 and return an RTX for the result.
1894 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1895 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1896 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1899 extract_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1900 unsigned HOST_WIDE_INT bitpos
, int unsignedp
)
1903 unsigned int bitsdone
= 0;
1904 rtx result
= NULL_RTX
;
1907 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1909 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1910 unit
= BITS_PER_WORD
;
1912 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1914 while (bitsdone
< bitsize
)
1916 unsigned HOST_WIDE_INT thissize
;
1918 unsigned HOST_WIDE_INT thispos
;
1919 unsigned HOST_WIDE_INT offset
;
1921 offset
= (bitpos
+ bitsdone
) / unit
;
1922 thispos
= (bitpos
+ bitsdone
) % unit
;
1924 /* THISSIZE must not overrun a word boundary. Otherwise,
1925 extract_fixed_bit_field will call us again, and we will mutually
1927 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1928 thissize
= MIN (thissize
, unit
- thispos
);
1930 /* If OP0 is a register, then handle OFFSET here.
1932 When handling multiword bitfields, extract_bit_field may pass
1933 down a word_mode SUBREG of a larger REG for a bitfield that actually
1934 crosses a word boundary. Thus, for a SUBREG, we must find
1935 the current word starting from the base register. */
1936 if (GET_CODE (op0
) == SUBREG
)
1938 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1939 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1940 GET_MODE (SUBREG_REG (op0
)));
1943 else if (REG_P (op0
))
1945 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1951 /* Extract the parts in bit-counting order,
1952 whose meaning is determined by BYTES_PER_UNIT.
1953 OFFSET is in UNITs, and UNIT is in bits. */
1954 part
= extract_fixed_bit_field (word_mode
, word
, thissize
,
1955 offset
* unit
+ thispos
, 0, 1);
1956 bitsdone
+= thissize
;
1958 /* Shift this part into place for the result. */
1959 if (BYTES_BIG_ENDIAN
)
1961 if (bitsize
!= bitsdone
)
1962 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1963 bitsize
- bitsdone
, 0, 1);
1967 if (bitsdone
!= thissize
)
1968 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1969 bitsdone
- thissize
, 0, 1);
1975 /* Combine the parts with bitwise or. This works
1976 because we extracted each part as an unsigned bit field. */
1977 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
1983 /* Unsigned bit field: we are done. */
1986 /* Signed bit field: sign-extend with two arithmetic shifts. */
1987 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
1988 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
1989 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
1990 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
1993 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
1994 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
1995 MODE, fill the upper bits with zeros. Fail if the layout of either
1996 mode is unknown (as for CC modes) or if the extraction would involve
1997 unprofitable mode punning. Return the value on success, otherwise
2000 This is different from gen_lowpart* in these respects:
2002 - the returned value must always be considered an rvalue
2004 - when MODE is wider than SRC_MODE, the extraction involves
2007 - when MODE is smaller than SRC_MODE, the extraction involves
2008 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
2010 In other words, this routine performs a computation, whereas the
2011 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2015 extract_low_bits (enum machine_mode mode
, enum machine_mode src_mode
, rtx src
)
2017 enum machine_mode int_mode
, src_int_mode
;
2019 if (mode
== src_mode
)
2022 if (CONSTANT_P (src
))
2024 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2025 fails, it will happily create (subreg (symbol_ref)) or similar
2027 unsigned int byte
= subreg_lowpart_offset (mode
, src_mode
);
2028 rtx ret
= simplify_subreg (mode
, src
, src_mode
, byte
);
2032 if (GET_MODE (src
) == VOIDmode
2033 || !validate_subreg (mode
, src_mode
, src
, byte
))
2036 src
= force_reg (GET_MODE (src
), src
);
2037 return gen_rtx_SUBREG (mode
, src
, byte
);
2040 if (GET_MODE_CLASS (mode
) == MODE_CC
|| GET_MODE_CLASS (src_mode
) == MODE_CC
)
2043 if (GET_MODE_BITSIZE (mode
) == GET_MODE_BITSIZE (src_mode
)
2044 && MODES_TIEABLE_P (mode
, src_mode
))
2046 rtx x
= gen_lowpart_common (mode
, src
);
2051 src_int_mode
= int_mode_for_mode (src_mode
);
2052 int_mode
= int_mode_for_mode (mode
);
2053 if (src_int_mode
== BLKmode
|| int_mode
== BLKmode
)
2056 if (!MODES_TIEABLE_P (src_int_mode
, src_mode
))
2058 if (!MODES_TIEABLE_P (int_mode
, mode
))
2061 src
= gen_lowpart (src_int_mode
, src
);
2062 src
= convert_modes (int_mode
, src_int_mode
, src
, true);
2063 src
= gen_lowpart (mode
, src
);
2067 /* Add INC into TARGET. */
2070 expand_inc (rtx target
, rtx inc
)
2072 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
2074 target
, 0, OPTAB_LIB_WIDEN
);
2075 if (value
!= target
)
2076 emit_move_insn (target
, value
);
2079 /* Subtract DEC from TARGET. */
2082 expand_dec (rtx target
, rtx dec
)
2084 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
2086 target
, 0, OPTAB_LIB_WIDEN
);
2087 if (value
!= target
)
2088 emit_move_insn (target
, value
);
2091 /* Output a shift instruction for expression code CODE,
2092 with SHIFTED being the rtx for the value to shift,
2093 and AMOUNT the rtx for the amount to shift by.
2094 Store the result in the rtx TARGET, if that is convenient.
2095 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2096 Return the rtx for where the value is. */
2099 expand_shift_1 (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2100 rtx amount
, rtx target
, int unsignedp
)
2103 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2104 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2105 optab lshift_optab
= ashl_optab
;
2106 optab rshift_arith_optab
= ashr_optab
;
2107 optab rshift_uns_optab
= lshr_optab
;
2108 optab lrotate_optab
= rotl_optab
;
2109 optab rrotate_optab
= rotr_optab
;
2110 enum machine_mode op1_mode
;
2111 enum machine_mode scalar_mode
= mode
;
2113 bool speed
= optimize_insn_for_speed_p ();
2115 if (VECTOR_MODE_P (mode
))
2116 scalar_mode
= GET_MODE_INNER (mode
);
2118 op1_mode
= GET_MODE (op1
);
2120 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2121 shift amount is a vector, use the vector/vector shift patterns. */
2122 if (VECTOR_MODE_P (mode
) && VECTOR_MODE_P (op1_mode
))
2124 lshift_optab
= vashl_optab
;
2125 rshift_arith_optab
= vashr_optab
;
2126 rshift_uns_optab
= vlshr_optab
;
2127 lrotate_optab
= vrotl_optab
;
2128 rrotate_optab
= vrotr_optab
;
2131 /* Previously detected shift-counts computed by NEGATE_EXPR
2132 and shifted in the other direction; but that does not work
2135 if (SHIFT_COUNT_TRUNCATED
)
2137 if (CONST_INT_P (op1
)
2138 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2139 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (scalar_mode
)))
2140 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
2141 % GET_MODE_BITSIZE (scalar_mode
));
2142 else if (GET_CODE (op1
) == SUBREG
2143 && subreg_lowpart_p (op1
)
2144 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1
)))
2145 && SCALAR_INT_MODE_P (GET_MODE (op1
)))
2146 op1
= SUBREG_REG (op1
);
2149 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
2150 prefer left rotation, if op1 is from bitsize / 2 + 1 to
2151 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
2154 && CONST_INT_P (op1
)
2155 && IN_RANGE (INTVAL (op1
), GET_MODE_BITSIZE (scalar_mode
) / 2 + left
,
2156 GET_MODE_BITSIZE (scalar_mode
) - 1))
2158 op1
= GEN_INT (GET_MODE_BITSIZE (scalar_mode
) - INTVAL (op1
));
2160 code
= left
? LROTATE_EXPR
: RROTATE_EXPR
;
2163 if (op1
== const0_rtx
)
2166 /* Check whether its cheaper to implement a left shift by a constant
2167 bit count by a sequence of additions. */
2168 if (code
== LSHIFT_EXPR
2169 && CONST_INT_P (op1
)
2171 && INTVAL (op1
) < GET_MODE_PRECISION (scalar_mode
)
2172 && INTVAL (op1
) < MAX_BITS_PER_WORD
2173 && (shift_cost (speed
, mode
, INTVAL (op1
))
2174 > INTVAL (op1
) * add_cost (speed
, mode
))
2175 && shift_cost (speed
, mode
, INTVAL (op1
)) != MAX_COST
)
2178 for (i
= 0; i
< INTVAL (op1
); i
++)
2180 temp
= force_reg (mode
, shifted
);
2181 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2182 unsignedp
, OPTAB_LIB_WIDEN
);
2187 for (attempt
= 0; temp
== 0 && attempt
< 3; attempt
++)
2189 enum optab_methods methods
;
2192 methods
= OPTAB_DIRECT
;
2193 else if (attempt
== 1)
2194 methods
= OPTAB_WIDEN
;
2196 methods
= OPTAB_LIB_WIDEN
;
2200 /* Widening does not work for rotation. */
2201 if (methods
== OPTAB_WIDEN
)
2203 else if (methods
== OPTAB_LIB_WIDEN
)
2205 /* If we have been unable to open-code this by a rotation,
2206 do it as the IOR of two shifts. I.e., to rotate A
2208 (A << N) | ((unsigned) A >> ((-N) & (C - 1)))
2209 where C is the bitsize of A.
2211 It is theoretically possible that the target machine might
2212 not be able to perform either shift and hence we would
2213 be making two libcalls rather than just the one for the
2214 shift (similarly if IOR could not be done). We will allow
2215 this extremely unlikely lossage to avoid complicating the
2218 rtx subtarget
= target
== shifted
? 0 : target
;
2219 rtx new_amount
, other_amount
;
2223 if (op1
== const0_rtx
)
2225 else if (CONST_INT_P (op1
))
2226 other_amount
= GEN_INT (GET_MODE_BITSIZE (scalar_mode
)
2231 = simplify_gen_unary (NEG
, GET_MODE (op1
),
2232 op1
, GET_MODE (op1
));
2233 HOST_WIDE_INT mask
= GET_MODE_PRECISION (scalar_mode
) - 1;
2235 = simplify_gen_binary (AND
, GET_MODE (op1
), other_amount
,
2236 gen_int_mode (mask
, GET_MODE (op1
)));
2239 shifted
= force_reg (mode
, shifted
);
2241 temp
= expand_shift_1 (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2242 mode
, shifted
, new_amount
, 0, 1);
2243 temp1
= expand_shift_1 (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2244 mode
, shifted
, other_amount
,
2246 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2247 unsignedp
, methods
);
2250 temp
= expand_binop (mode
,
2251 left
? lrotate_optab
: rrotate_optab
,
2252 shifted
, op1
, target
, unsignedp
, methods
);
2255 temp
= expand_binop (mode
,
2256 left
? lshift_optab
: rshift_uns_optab
,
2257 shifted
, op1
, target
, unsignedp
, methods
);
2259 /* Do arithmetic shifts.
2260 Also, if we are going to widen the operand, we can just as well
2261 use an arithmetic right-shift instead of a logical one. */
2262 if (temp
== 0 && ! rotate
2263 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2265 enum optab_methods methods1
= methods
;
2267 /* If trying to widen a log shift to an arithmetic shift,
2268 don't accept an arithmetic shift of the same size. */
2270 methods1
= OPTAB_MUST_WIDEN
;
2272 /* Arithmetic shift */
2274 temp
= expand_binop (mode
,
2275 left
? lshift_optab
: rshift_arith_optab
,
2276 shifted
, op1
, target
, unsignedp
, methods1
);
2279 /* We used to try extzv here for logical right shifts, but that was
2280 only useful for one machine, the VAX, and caused poor code
2281 generation there for lshrdi3, so the code was deleted and a
2282 define_expand for lshrsi3 was added to vax.md. */
2289 /* Output a shift instruction for expression code CODE,
2290 with SHIFTED being the rtx for the value to shift,
2291 and AMOUNT the amount to shift by.
2292 Store the result in the rtx TARGET, if that is convenient.
2293 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2294 Return the rtx for where the value is. */
2297 expand_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2298 int amount
, rtx target
, int unsignedp
)
2300 return expand_shift_1 (code
, mode
,
2301 shifted
, GEN_INT (amount
), target
, unsignedp
);
2304 /* Output a shift instruction for expression code CODE,
2305 with SHIFTED being the rtx for the value to shift,
2306 and AMOUNT the tree for the amount to shift by.
2307 Store the result in the rtx TARGET, if that is convenient.
2308 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2309 Return the rtx for where the value is. */
2312 expand_variable_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2313 tree amount
, rtx target
, int unsignedp
)
2315 return expand_shift_1 (code
, mode
,
2316 shifted
, expand_normal (amount
), target
, unsignedp
);
2320 /* Indicates the type of fixup needed after a constant multiplication.
2321 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2322 the result should be negated, and ADD_VARIANT means that the
2323 multiplicand should be added to the result. */
2324 enum mult_variant
{basic_variant
, negate_variant
, add_variant
};
2326 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2327 const struct mult_cost
*, enum machine_mode mode
);
2328 static bool choose_mult_variant (enum machine_mode
, HOST_WIDE_INT
,
2329 struct algorithm
*, enum mult_variant
*, int);
2330 static rtx
expand_mult_const (enum machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2331 const struct algorithm
*, enum mult_variant
);
2332 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2333 static rtx
extract_high_half (enum machine_mode
, rtx
);
2334 static rtx
expmed_mult_highpart (enum machine_mode
, rtx
, rtx
, rtx
, int, int);
2335 static rtx
expmed_mult_highpart_optab (enum machine_mode
, rtx
, rtx
, rtx
,
2337 /* Compute and return the best algorithm for multiplying by T.
2338 The algorithm must cost less than cost_limit
2339 If retval.cost >= COST_LIMIT, no algorithm was found and all
2340 other field of the returned struct are undefined.
2341 MODE is the machine mode of the multiplication. */
2344 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2345 const struct mult_cost
*cost_limit
, enum machine_mode mode
)
2348 struct algorithm
*alg_in
, *best_alg
;
2349 struct mult_cost best_cost
;
2350 struct mult_cost new_limit
;
2351 int op_cost
, op_latency
;
2352 unsigned HOST_WIDE_INT orig_t
= t
;
2353 unsigned HOST_WIDE_INT q
;
2354 int maxm
, hash_index
;
2355 bool cache_hit
= false;
2356 enum alg_code cache_alg
= alg_zero
;
2357 bool speed
= optimize_insn_for_speed_p ();
2358 enum machine_mode imode
;
2359 struct alg_hash_entry
*entry_ptr
;
2361 /* Indicate that no algorithm is yet found. If no algorithm
2362 is found, this value will be returned and indicate failure. */
2363 alg_out
->cost
.cost
= cost_limit
->cost
+ 1;
2364 alg_out
->cost
.latency
= cost_limit
->latency
+ 1;
2366 if (cost_limit
->cost
< 0
2367 || (cost_limit
->cost
== 0 && cost_limit
->latency
<= 0))
2370 /* Be prepared for vector modes. */
2371 imode
= GET_MODE_INNER (mode
);
2372 if (imode
== VOIDmode
)
2375 maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (imode
));
2377 /* Restrict the bits of "t" to the multiplication's mode. */
2378 t
&= GET_MODE_MASK (imode
);
2380 /* t == 1 can be done in zero cost. */
2384 alg_out
->cost
.cost
= 0;
2385 alg_out
->cost
.latency
= 0;
2386 alg_out
->op
[0] = alg_m
;
2390 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2394 if (MULT_COST_LESS (cost_limit
, zero_cost (speed
)))
2399 alg_out
->cost
.cost
= zero_cost (speed
);
2400 alg_out
->cost
.latency
= zero_cost (speed
);
2401 alg_out
->op
[0] = alg_zero
;
2406 /* We'll be needing a couple extra algorithm structures now. */
2408 alg_in
= XALLOCA (struct algorithm
);
2409 best_alg
= XALLOCA (struct algorithm
);
2410 best_cost
= *cost_limit
;
2412 /* Compute the hash index. */
2413 hash_index
= (t
^ (unsigned int) mode
^ (speed
* 256)) % NUM_ALG_HASH_ENTRIES
;
2415 /* See if we already know what to do for T. */
2416 entry_ptr
= alg_hash_entry_ptr (hash_index
);
2417 if (entry_ptr
->t
== t
2418 && entry_ptr
->mode
== mode
2419 && entry_ptr
->mode
== mode
2420 && entry_ptr
->speed
== speed
2421 && entry_ptr
->alg
!= alg_unknown
)
2423 cache_alg
= entry_ptr
->alg
;
2425 if (cache_alg
== alg_impossible
)
2427 /* The cache tells us that it's impossible to synthesize
2428 multiplication by T within entry_ptr->cost. */
2429 if (!CHEAPER_MULT_COST (&entry_ptr
->cost
, cost_limit
))
2430 /* COST_LIMIT is at least as restrictive as the one
2431 recorded in the hash table, in which case we have no
2432 hope of synthesizing a multiplication. Just
2436 /* If we get here, COST_LIMIT is less restrictive than the
2437 one recorded in the hash table, so we may be able to
2438 synthesize a multiplication. Proceed as if we didn't
2439 have the cache entry. */
2443 if (CHEAPER_MULT_COST (cost_limit
, &entry_ptr
->cost
))
2444 /* The cached algorithm shows that this multiplication
2445 requires more cost than COST_LIMIT. Just return. This
2446 way, we don't clobber this cache entry with
2447 alg_impossible but retain useful information. */
2459 goto do_alg_addsub_t_m2
;
2461 case alg_add_factor
:
2462 case alg_sub_factor
:
2463 goto do_alg_addsub_factor
;
2466 goto do_alg_add_t2_m
;
2469 goto do_alg_sub_t2_m
;
2477 /* If we have a group of zero bits at the low-order part of T, try
2478 multiplying by the remaining bits and then doing a shift. */
2483 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2487 /* The function expand_shift will choose between a shift and
2488 a sequence of additions, so the observed cost is given as
2489 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2490 op_cost
= m
* add_cost (speed
, mode
);
2491 if (shift_cost (speed
, mode
, m
) < op_cost
)
2492 op_cost
= shift_cost (speed
, mode
, m
);
2493 new_limit
.cost
= best_cost
.cost
- op_cost
;
2494 new_limit
.latency
= best_cost
.latency
- op_cost
;
2495 synth_mult (alg_in
, q
, &new_limit
, mode
);
2497 alg_in
->cost
.cost
+= op_cost
;
2498 alg_in
->cost
.latency
+= op_cost
;
2499 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2501 struct algorithm
*x
;
2502 best_cost
= alg_in
->cost
;
2503 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2504 best_alg
->log
[best_alg
->ops
] = m
;
2505 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2508 /* See if treating ORIG_T as a signed number yields a better
2509 sequence. Try this sequence only for a negative ORIG_T
2510 as it would be useless for a non-negative ORIG_T. */
2511 if ((HOST_WIDE_INT
) orig_t
< 0)
2513 /* Shift ORIG_T as follows because a right shift of a
2514 negative-valued signed type is implementation
2516 q
= ~(~orig_t
>> m
);
2517 /* The function expand_shift will choose between a shift
2518 and a sequence of additions, so the observed cost is
2519 given as MIN (m * add_cost(speed, mode),
2520 shift_cost(speed, mode, m)). */
2521 op_cost
= m
* add_cost (speed
, mode
);
2522 if (shift_cost (speed
, mode
, m
) < op_cost
)
2523 op_cost
= shift_cost (speed
, mode
, m
);
2524 new_limit
.cost
= best_cost
.cost
- op_cost
;
2525 new_limit
.latency
= best_cost
.latency
- op_cost
;
2526 synth_mult (alg_in
, q
, &new_limit
, mode
);
2528 alg_in
->cost
.cost
+= op_cost
;
2529 alg_in
->cost
.latency
+= op_cost
;
2530 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2532 struct algorithm
*x
;
2533 best_cost
= alg_in
->cost
;
2534 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2535 best_alg
->log
[best_alg
->ops
] = m
;
2536 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2544 /* If we have an odd number, add or subtract one. */
2547 unsigned HOST_WIDE_INT w
;
2550 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2552 /* If T was -1, then W will be zero after the loop. This is another
2553 case where T ends with ...111. Handling this with (T + 1) and
2554 subtract 1 produces slightly better code and results in algorithm
2555 selection much faster than treating it like the ...0111 case
2559 /* Reject the case where t is 3.
2560 Thus we prefer addition in that case. */
2563 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2565 op_cost
= add_cost (speed
, mode
);
2566 new_limit
.cost
= best_cost
.cost
- op_cost
;
2567 new_limit
.latency
= best_cost
.latency
- op_cost
;
2568 synth_mult (alg_in
, t
+ 1, &new_limit
, mode
);
2570 alg_in
->cost
.cost
+= op_cost
;
2571 alg_in
->cost
.latency
+= op_cost
;
2572 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2574 struct algorithm
*x
;
2575 best_cost
= alg_in
->cost
;
2576 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2577 best_alg
->log
[best_alg
->ops
] = 0;
2578 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2583 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2585 op_cost
= add_cost (speed
, mode
);
2586 new_limit
.cost
= best_cost
.cost
- op_cost
;
2587 new_limit
.latency
= best_cost
.latency
- op_cost
;
2588 synth_mult (alg_in
, t
- 1, &new_limit
, mode
);
2590 alg_in
->cost
.cost
+= op_cost
;
2591 alg_in
->cost
.latency
+= op_cost
;
2592 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2594 struct algorithm
*x
;
2595 best_cost
= alg_in
->cost
;
2596 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2597 best_alg
->log
[best_alg
->ops
] = 0;
2598 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2602 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2603 quickly with a - a * n for some appropriate constant n. */
2604 m
= exact_log2 (-orig_t
+ 1);
2605 if (m
>= 0 && m
< maxm
)
2607 op_cost
= shiftsub1_cost (speed
, mode
, m
);
2608 new_limit
.cost
= best_cost
.cost
- op_cost
;
2609 new_limit
.latency
= best_cost
.latency
- op_cost
;
2610 synth_mult (alg_in
, (unsigned HOST_WIDE_INT
) (-orig_t
+ 1) >> m
,
2613 alg_in
->cost
.cost
+= op_cost
;
2614 alg_in
->cost
.latency
+= op_cost
;
2615 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2617 struct algorithm
*x
;
2618 best_cost
= alg_in
->cost
;
2619 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2620 best_alg
->log
[best_alg
->ops
] = m
;
2621 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2629 /* Look for factors of t of the form
2630 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2631 If we find such a factor, we can multiply by t using an algorithm that
2632 multiplies by q, shift the result by m and add/subtract it to itself.
2634 We search for large factors first and loop down, even if large factors
2635 are less probable than small; if we find a large factor we will find a
2636 good sequence quickly, and therefore be able to prune (by decreasing
2637 COST_LIMIT) the search. */
2639 do_alg_addsub_factor
:
2640 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2642 unsigned HOST_WIDE_INT d
;
2644 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2645 if (t
% d
== 0 && t
> d
&& m
< maxm
2646 && (!cache_hit
|| cache_alg
== alg_add_factor
))
2648 /* If the target has a cheap shift-and-add instruction use
2649 that in preference to a shift insn followed by an add insn.
2650 Assume that the shift-and-add is "atomic" with a latency
2651 equal to its cost, otherwise assume that on superscalar
2652 hardware the shift may be executed concurrently with the
2653 earlier steps in the algorithm. */
2654 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2655 if (shiftadd_cost (speed
, mode
, m
) < op_cost
)
2657 op_cost
= shiftadd_cost (speed
, mode
, m
);
2658 op_latency
= op_cost
;
2661 op_latency
= add_cost (speed
, mode
);
2663 new_limit
.cost
= best_cost
.cost
- op_cost
;
2664 new_limit
.latency
= best_cost
.latency
- op_latency
;
2665 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2667 alg_in
->cost
.cost
+= op_cost
;
2668 alg_in
->cost
.latency
+= op_latency
;
2669 if (alg_in
->cost
.latency
< op_cost
)
2670 alg_in
->cost
.latency
= op_cost
;
2671 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2673 struct algorithm
*x
;
2674 best_cost
= alg_in
->cost
;
2675 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2676 best_alg
->log
[best_alg
->ops
] = m
;
2677 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2679 /* Other factors will have been taken care of in the recursion. */
2683 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2684 if (t
% d
== 0 && t
> d
&& m
< maxm
2685 && (!cache_hit
|| cache_alg
== alg_sub_factor
))
2687 /* If the target has a cheap shift-and-subtract insn use
2688 that in preference to a shift insn followed by a sub insn.
2689 Assume that the shift-and-sub is "atomic" with a latency
2690 equal to it's cost, otherwise assume that on superscalar
2691 hardware the shift may be executed concurrently with the
2692 earlier steps in the algorithm. */
2693 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2694 if (shiftsub0_cost (speed
, mode
, m
) < op_cost
)
2696 op_cost
= shiftsub0_cost (speed
, mode
, m
);
2697 op_latency
= op_cost
;
2700 op_latency
= add_cost (speed
, mode
);
2702 new_limit
.cost
= best_cost
.cost
- op_cost
;
2703 new_limit
.latency
= best_cost
.latency
- op_latency
;
2704 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2706 alg_in
->cost
.cost
+= op_cost
;
2707 alg_in
->cost
.latency
+= op_latency
;
2708 if (alg_in
->cost
.latency
< op_cost
)
2709 alg_in
->cost
.latency
= op_cost
;
2710 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2712 struct algorithm
*x
;
2713 best_cost
= alg_in
->cost
;
2714 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2715 best_alg
->log
[best_alg
->ops
] = m
;
2716 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2724 /* Try shift-and-add (load effective address) instructions,
2725 i.e. do a*3, a*5, a*9. */
2732 if (m
>= 0 && m
< maxm
)
2734 op_cost
= shiftadd_cost (speed
, mode
, m
);
2735 new_limit
.cost
= best_cost
.cost
- op_cost
;
2736 new_limit
.latency
= best_cost
.latency
- op_cost
;
2737 synth_mult (alg_in
, (t
- 1) >> m
, &new_limit
, mode
);
2739 alg_in
->cost
.cost
+= op_cost
;
2740 alg_in
->cost
.latency
+= op_cost
;
2741 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2743 struct algorithm
*x
;
2744 best_cost
= alg_in
->cost
;
2745 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2746 best_alg
->log
[best_alg
->ops
] = m
;
2747 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2757 if (m
>= 0 && m
< maxm
)
2759 op_cost
= shiftsub0_cost (speed
, mode
, m
);
2760 new_limit
.cost
= best_cost
.cost
- op_cost
;
2761 new_limit
.latency
= best_cost
.latency
- op_cost
;
2762 synth_mult (alg_in
, (t
+ 1) >> m
, &new_limit
, mode
);
2764 alg_in
->cost
.cost
+= op_cost
;
2765 alg_in
->cost
.latency
+= op_cost
;
2766 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2768 struct algorithm
*x
;
2769 best_cost
= alg_in
->cost
;
2770 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2771 best_alg
->log
[best_alg
->ops
] = m
;
2772 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2780 /* If best_cost has not decreased, we have not found any algorithm. */
2781 if (!CHEAPER_MULT_COST (&best_cost
, cost_limit
))
2783 /* We failed to find an algorithm. Record alg_impossible for
2784 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2785 we are asked to find an algorithm for T within the same or
2786 lower COST_LIMIT, we can immediately return to the
2789 entry_ptr
->mode
= mode
;
2790 entry_ptr
->speed
= speed
;
2791 entry_ptr
->alg
= alg_impossible
;
2792 entry_ptr
->cost
= *cost_limit
;
2796 /* Cache the result. */
2800 entry_ptr
->mode
= mode
;
2801 entry_ptr
->speed
= speed
;
2802 entry_ptr
->alg
= best_alg
->op
[best_alg
->ops
];
2803 entry_ptr
->cost
.cost
= best_cost
.cost
;
2804 entry_ptr
->cost
.latency
= best_cost
.latency
;
2807 /* If we are getting a too long sequence for `struct algorithm'
2808 to record, make this search fail. */
2809 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2812 /* Copy the algorithm from temporary space to the space at alg_out.
2813 We avoid using structure assignment because the majority of
2814 best_alg is normally undefined, and this is a critical function. */
2815 alg_out
->ops
= best_alg
->ops
+ 1;
2816 alg_out
->cost
= best_cost
;
2817 memcpy (alg_out
->op
, best_alg
->op
,
2818 alg_out
->ops
* sizeof *alg_out
->op
);
2819 memcpy (alg_out
->log
, best_alg
->log
,
2820 alg_out
->ops
* sizeof *alg_out
->log
);
2823 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2824 Try three variations:
2826 - a shift/add sequence based on VAL itself
2827 - a shift/add sequence based on -VAL, followed by a negation
2828 - a shift/add sequence based on VAL - 1, followed by an addition.
2830 Return true if the cheapest of these cost less than MULT_COST,
2831 describing the algorithm in *ALG and final fixup in *VARIANT. */
2834 choose_mult_variant (enum machine_mode mode
, HOST_WIDE_INT val
,
2835 struct algorithm
*alg
, enum mult_variant
*variant
,
2838 struct algorithm alg2
;
2839 struct mult_cost limit
;
2841 bool speed
= optimize_insn_for_speed_p ();
2843 /* Fail quickly for impossible bounds. */
2847 /* Ensure that mult_cost provides a reasonable upper bound.
2848 Any constant multiplication can be performed with less
2849 than 2 * bits additions. */
2850 op_cost
= 2 * GET_MODE_UNIT_BITSIZE (mode
) * add_cost (speed
, mode
);
2851 if (mult_cost
> op_cost
)
2852 mult_cost
= op_cost
;
2854 *variant
= basic_variant
;
2855 limit
.cost
= mult_cost
;
2856 limit
.latency
= mult_cost
;
2857 synth_mult (alg
, val
, &limit
, mode
);
2859 /* This works only if the inverted value actually fits in an
2861 if (HOST_BITS_PER_INT
>= GET_MODE_UNIT_BITSIZE (mode
))
2863 op_cost
= neg_cost (speed
, mode
);
2864 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2866 limit
.cost
= alg
->cost
.cost
- op_cost
;
2867 limit
.latency
= alg
->cost
.latency
- op_cost
;
2871 limit
.cost
= mult_cost
- op_cost
;
2872 limit
.latency
= mult_cost
- op_cost
;
2875 synth_mult (&alg2
, -val
, &limit
, mode
);
2876 alg2
.cost
.cost
+= op_cost
;
2877 alg2
.cost
.latency
+= op_cost
;
2878 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2879 *alg
= alg2
, *variant
= negate_variant
;
2882 /* This proves very useful for division-by-constant. */
2883 op_cost
= add_cost (speed
, mode
);
2884 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2886 limit
.cost
= alg
->cost
.cost
- op_cost
;
2887 limit
.latency
= alg
->cost
.latency
- op_cost
;
2891 limit
.cost
= mult_cost
- op_cost
;
2892 limit
.latency
= mult_cost
- op_cost
;
2895 synth_mult (&alg2
, val
- 1, &limit
, mode
);
2896 alg2
.cost
.cost
+= op_cost
;
2897 alg2
.cost
.latency
+= op_cost
;
2898 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2899 *alg
= alg2
, *variant
= add_variant
;
2901 return MULT_COST_LESS (&alg
->cost
, mult_cost
);
2904 /* A subroutine of expand_mult, used for constant multiplications.
2905 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2906 convenient. Use the shift/add sequence described by ALG and apply
2907 the final fixup specified by VARIANT. */
2910 expand_mult_const (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
2911 rtx target
, const struct algorithm
*alg
,
2912 enum mult_variant variant
)
2914 HOST_WIDE_INT val_so_far
;
2918 enum machine_mode nmode
;
2920 /* Avoid referencing memory over and over and invalid sharing
2922 op0
= force_reg (mode
, op0
);
2924 /* ACCUM starts out either as OP0 or as a zero, depending on
2925 the first operation. */
2927 if (alg
->op
[0] == alg_zero
)
2929 accum
= copy_to_mode_reg (mode
, CONST0_RTX (mode
));
2932 else if (alg
->op
[0] == alg_m
)
2934 accum
= copy_to_mode_reg (mode
, op0
);
2940 for (opno
= 1; opno
< alg
->ops
; opno
++)
2942 int log
= alg
->log
[opno
];
2943 rtx shift_subtarget
= optimize
? 0 : accum
;
2945 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
2948 rtx accum_target
= optimize
? 0 : accum
;
2951 switch (alg
->op
[opno
])
2954 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
2955 /* REG_EQUAL note will be attached to the following insn. */
2956 emit_move_insn (accum
, tem
);
2961 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
2962 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2963 add_target
? add_target
: accum_target
);
2964 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2968 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
2969 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2970 add_target
? add_target
: accum_target
);
2971 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2975 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2976 log
, shift_subtarget
, 0);
2977 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2978 add_target
? add_target
: accum_target
);
2979 val_so_far
= (val_so_far
<< log
) + 1;
2983 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2984 log
, shift_subtarget
, 0);
2985 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2986 add_target
? add_target
: accum_target
);
2987 val_so_far
= (val_so_far
<< log
) - 1;
2990 case alg_add_factor
:
2991 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
2992 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2993 add_target
? add_target
: accum_target
);
2994 val_so_far
+= val_so_far
<< log
;
2997 case alg_sub_factor
:
2998 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
2999 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
3001 ? add_target
: (optimize
? 0 : tem
)));
3002 val_so_far
= (val_so_far
<< log
) - val_so_far
;
3009 if (SCALAR_INT_MODE_P (mode
))
3011 /* Write a REG_EQUAL note on the last insn so that we can cse
3012 multiplication sequences. Note that if ACCUM is a SUBREG,
3013 we've set the inner register and must properly indicate that. */
3014 tem
= op0
, nmode
= mode
;
3015 accum_inner
= accum
;
3016 if (GET_CODE (accum
) == SUBREG
)
3018 accum_inner
= SUBREG_REG (accum
);
3019 nmode
= GET_MODE (accum_inner
);
3020 tem
= gen_lowpart (nmode
, op0
);
3023 insn
= get_last_insn ();
3024 set_dst_reg_note (insn
, REG_EQUAL
,
3025 gen_rtx_MULT (nmode
, tem
,
3026 gen_int_mode (val_so_far
, nmode
)),
3031 if (variant
== negate_variant
)
3033 val_so_far
= -val_so_far
;
3034 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
3036 else if (variant
== add_variant
)
3038 val_so_far
= val_so_far
+ 1;
3039 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
3042 /* Compare only the bits of val and val_so_far that are significant
3043 in the result mode, to avoid sign-/zero-extension confusion. */
3044 nmode
= GET_MODE_INNER (mode
);
3045 if (nmode
== VOIDmode
)
3047 val
&= GET_MODE_MASK (nmode
);
3048 val_so_far
&= GET_MODE_MASK (nmode
);
3049 gcc_assert (val
== val_so_far
);
3054 /* Perform a multiplication and return an rtx for the result.
3055 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3056 TARGET is a suggestion for where to store the result (an rtx).
3058 We check specially for a constant integer as OP1.
3059 If you want this check for OP0 as well, then before calling
3060 you should swap the two operands if OP0 would be constant. */
3063 expand_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3066 enum mult_variant variant
;
3067 struct algorithm algorithm
;
3070 bool speed
= optimize_insn_for_speed_p ();
3071 bool do_trapv
= flag_trapv
&& SCALAR_INT_MODE_P (mode
) && !unsignedp
;
3073 if (CONSTANT_P (op0
))
3080 /* For vectors, there are several simplifications that can be made if
3081 all elements of the vector constant are identical. */
3083 if (GET_CODE (op1
) == CONST_VECTOR
)
3085 int i
, n
= CONST_VECTOR_NUNITS (op1
);
3086 scalar_op1
= CONST_VECTOR_ELT (op1
, 0);
3087 for (i
= 1; i
< n
; ++i
)
3088 if (!rtx_equal_p (scalar_op1
, CONST_VECTOR_ELT (op1
, i
)))
3092 if (INTEGRAL_MODE_P (mode
))
3095 HOST_WIDE_INT coeff
;
3099 if (op1
== CONST0_RTX (mode
))
3101 if (op1
== CONST1_RTX (mode
))
3103 if (op1
== CONSTM1_RTX (mode
))
3104 return expand_unop (mode
, do_trapv
? negv_optab
: neg_optab
,
3110 /* If mode is integer vector mode, check if the backend supports
3111 vector lshift (by scalar or vector) at all. If not, we can't use
3112 synthetized multiply. */
3113 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
3114 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
3115 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
)
3118 /* These are the operations that are potentially turned into
3119 a sequence of shifts and additions. */
3120 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
3122 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3123 less than or equal in size to `unsigned int' this doesn't matter.
3124 If the mode is larger than `unsigned int', then synth_mult works
3125 only if the constant value exactly fits in an `unsigned int' without
3126 any truncation. This means that multiplying by negative values does
3127 not work; results are off by 2^32 on a 32 bit machine. */
3128 if (CONST_INT_P (scalar_op1
))
3130 coeff
= INTVAL (scalar_op1
);
3133 #if TARGET_SUPPORTS_WIDE_INT
3134 else if (CONST_WIDE_INT_P (scalar_op1
))
3136 else if (CONST_DOUBLE_AS_INT_P (scalar_op1
))
3139 int shift
= wi::exact_log2 (std::make_pair (scalar_op1
, mode
));
3140 /* Perfect power of 2 (other than 1, which is handled above). */
3142 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3143 shift
, target
, unsignedp
);
3150 /* We used to test optimize here, on the grounds that it's better to
3151 produce a smaller program when -O is not used. But this causes
3152 such a terrible slowdown sometimes that it seems better to always
3155 /* Special case powers of two. */
3156 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
)
3157 && !(is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
))
3158 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3159 floor_log2 (coeff
), target
, unsignedp
);
3161 fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3163 /* Attempt to handle multiplication of DImode values by negative
3164 coefficients, by performing the multiplication by a positive
3165 multiplier and then inverting the result. */
3166 if (is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
)
3168 /* Its safe to use -coeff even for INT_MIN, as the
3169 result is interpreted as an unsigned coefficient.
3170 Exclude cost of op0 from max_cost to match the cost
3171 calculation of the synth_mult. */
3172 coeff
= -(unsigned HOST_WIDE_INT
) coeff
;
3173 max_cost
= (set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), speed
)
3174 - neg_cost (speed
, mode
));
3178 /* Special case powers of two. */
3179 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3181 rtx temp
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
3182 floor_log2 (coeff
), target
, unsignedp
);
3183 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3186 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3189 rtx temp
= expand_mult_const (mode
, op0
, coeff
, NULL_RTX
,
3190 &algorithm
, variant
);
3191 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3196 /* Exclude cost of op0 from max_cost to match the cost
3197 calculation of the synth_mult. */
3198 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), speed
);
3199 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3200 return expand_mult_const (mode
, op0
, coeff
, target
,
3201 &algorithm
, variant
);
3205 /* Expand x*2.0 as x+x. */
3206 if (CONST_DOUBLE_AS_FLOAT_P (scalar_op1
))
3209 REAL_VALUE_FROM_CONST_DOUBLE (d
, scalar_op1
);
3211 if (REAL_VALUES_EQUAL (d
, dconst2
))
3213 op0
= force_reg (GET_MODE (op0
), op0
);
3214 return expand_binop (mode
, add_optab
, op0
, op0
,
3215 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3220 /* This used to use umul_optab if unsigned, but for non-widening multiply
3221 there is no difference between signed and unsigned. */
3222 op0
= expand_binop (mode
, do_trapv
? smulv_optab
: smul_optab
,
3223 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
3228 /* Return a cost estimate for multiplying a register by the given
3229 COEFFicient in the given MODE and SPEED. */
3232 mult_by_coeff_cost (HOST_WIDE_INT coeff
, enum machine_mode mode
, bool speed
)
3235 struct algorithm algorithm
;
3236 enum mult_variant variant
;
3238 rtx fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3239 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, fake_reg
), speed
);
3240 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3241 return algorithm
.cost
.cost
;
3246 /* Perform a widening multiplication and return an rtx for the result.
3247 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3248 TARGET is a suggestion for where to store the result (an rtx).
3249 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3250 or smul_widen_optab.
3252 We check specially for a constant integer as OP1, comparing the
3253 cost of a widening multiply against the cost of a sequence of shifts
3257 expand_widening_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3258 int unsignedp
, optab this_optab
)
3260 bool speed
= optimize_insn_for_speed_p ();
3263 if (CONST_INT_P (op1
)
3264 && GET_MODE (op0
) != VOIDmode
3265 && (cop1
= convert_modes (mode
, GET_MODE (op0
), op1
,
3266 this_optab
== umul_widen_optab
))
3267 && CONST_INT_P (cop1
)
3268 && (INTVAL (cop1
) >= 0
3269 || HWI_COMPUTABLE_MODE_P (mode
)))
3271 HOST_WIDE_INT coeff
= INTVAL (cop1
);
3273 enum mult_variant variant
;
3274 struct algorithm algorithm
;
3276 /* Special case powers of two. */
3277 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3279 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3280 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3281 floor_log2 (coeff
), target
, unsignedp
);
3284 /* Exclude cost of op0 from max_cost to match the cost
3285 calculation of the synth_mult. */
3286 max_cost
= mul_widen_cost (speed
, mode
);
3287 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3290 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3291 return expand_mult_const (mode
, op0
, coeff
, target
,
3292 &algorithm
, variant
);
3295 return expand_binop (mode
, this_optab
, op0
, op1
, target
,
3296 unsignedp
, OPTAB_LIB_WIDEN
);
3299 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3300 replace division by D, and put the least significant N bits of the result
3301 in *MULTIPLIER_PTR and return the most significant bit.
3303 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3304 needed precision is in PRECISION (should be <= N).
3306 PRECISION should be as small as possible so this function can choose
3307 multiplier more freely.
3309 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3310 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3312 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3313 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3315 unsigned HOST_WIDE_INT
3316 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
3317 unsigned HOST_WIDE_INT
*multiplier_ptr
,
3318 int *post_shift_ptr
, int *lgup_ptr
)
3320 int lgup
, post_shift
;
3323 /* lgup = ceil(log2(divisor)); */
3324 lgup
= ceil_log2 (d
);
3326 gcc_assert (lgup
<= n
);
3329 pow2
= n
+ lgup
- precision
;
3331 /* mlow = 2^(N + lgup)/d */
3332 wide_int val
= wi::set_bit_in_zero (pow
, HOST_BITS_PER_DOUBLE_INT
);
3333 wide_int mlow
= wi::udiv_trunc (val
, d
);
3335 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3336 val
|= wi::set_bit_in_zero (pow2
, HOST_BITS_PER_DOUBLE_INT
);
3337 wide_int mhigh
= wi::udiv_trunc (val
, d
);
3339 /* If precision == N, then mlow, mhigh exceed 2^N
3340 (but they do not exceed 2^(N+1)). */
3342 /* Reduce to lowest terms. */
3343 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
3345 unsigned HOST_WIDE_INT ml_lo
= wi::extract_uhwi (mlow
, 1,
3346 HOST_BITS_PER_WIDE_INT
);
3347 unsigned HOST_WIDE_INT mh_lo
= wi::extract_uhwi (mhigh
, 1,
3348 HOST_BITS_PER_WIDE_INT
);
3352 mlow
= wi::uhwi (ml_lo
, HOST_BITS_PER_DOUBLE_INT
);
3353 mhigh
= wi::uhwi (mh_lo
, HOST_BITS_PER_DOUBLE_INT
);
3356 *post_shift_ptr
= post_shift
;
3358 if (n
< HOST_BITS_PER_WIDE_INT
)
3360 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
3361 *multiplier_ptr
= mhigh
.to_uhwi () & mask
;
3362 return mhigh
.to_uhwi () >= mask
;
3366 *multiplier_ptr
= mhigh
.to_uhwi ();
3367 return wi::extract_uhwi (mhigh
, HOST_BITS_PER_WIDE_INT
, 1);
3371 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3372 congruent to 1 (mod 2**N). */
3374 static unsigned HOST_WIDE_INT
3375 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
3377 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3379 /* The algorithm notes that the choice y = x satisfies
3380 x*y == 1 mod 2^3, since x is assumed odd.
3381 Each iteration doubles the number of bits of significance in y. */
3383 unsigned HOST_WIDE_INT mask
;
3384 unsigned HOST_WIDE_INT y
= x
;
3387 mask
= (n
== HOST_BITS_PER_WIDE_INT
3388 ? ~(unsigned HOST_WIDE_INT
) 0
3389 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
3393 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
3399 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3400 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3401 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3402 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3405 The result is put in TARGET if that is convenient.
3407 MODE is the mode of operation. */
3410 expand_mult_highpart_adjust (enum machine_mode mode
, rtx adj_operand
, rtx op0
,
3411 rtx op1
, rtx target
, int unsignedp
)
3414 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
3416 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3417 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3418 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
3420 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3423 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
3424 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3425 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
3426 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3432 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3435 extract_high_half (enum machine_mode mode
, rtx op
)
3437 enum machine_mode wider_mode
;
3439 if (mode
== word_mode
)
3440 return gen_highpart (mode
, op
);
3442 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3444 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3445 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
3446 GET_MODE_BITSIZE (mode
), 0, 1);
3447 return convert_modes (mode
, wider_mode
, op
, 0);
3450 /* Like expmed_mult_highpart, but only consider using a multiplication
3451 optab. OP1 is an rtx for the constant operand. */
3454 expmed_mult_highpart_optab (enum machine_mode mode
, rtx op0
, rtx op1
,
3455 rtx target
, int unsignedp
, int max_cost
)
3457 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
3458 enum machine_mode wider_mode
;
3462 bool speed
= optimize_insn_for_speed_p ();
3464 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3466 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3467 size
= GET_MODE_BITSIZE (mode
);
3469 /* Firstly, try using a multiplication insn that only generates the needed
3470 high part of the product, and in the sign flavor of unsignedp. */
3471 if (mul_highpart_cost (speed
, mode
) < max_cost
)
3473 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
3474 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3475 unsignedp
, OPTAB_DIRECT
);
3480 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3481 Need to adjust the result after the multiplication. */
3482 if (size
- 1 < BITS_PER_WORD
3483 && (mul_highpart_cost (speed
, mode
)
3484 + 2 * shift_cost (speed
, mode
, size
-1)
3485 + 4 * add_cost (speed
, mode
) < max_cost
))
3487 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
3488 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3489 unsignedp
, OPTAB_DIRECT
);
3491 /* We used the wrong signedness. Adjust the result. */
3492 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3496 /* Try widening multiplication. */
3497 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
3498 if (widening_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3499 && mul_widen_cost (speed
, wider_mode
) < max_cost
)
3501 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
3502 unsignedp
, OPTAB_WIDEN
);
3504 return extract_high_half (mode
, tem
);
3507 /* Try widening the mode and perform a non-widening multiplication. */
3508 if (optab_handler (smul_optab
, wider_mode
) != CODE_FOR_nothing
3509 && size
- 1 < BITS_PER_WORD
3510 && (mul_cost (speed
, wider_mode
) + shift_cost (speed
, mode
, size
-1)
3516 /* We need to widen the operands, for example to ensure the
3517 constant multiplier is correctly sign or zero extended.
3518 Use a sequence to clean-up any instructions emitted by
3519 the conversions if things don't work out. */
3521 wop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
3522 wop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
3523 tem
= expand_binop (wider_mode
, smul_optab
, wop0
, wop1
, 0,
3524 unsignedp
, OPTAB_WIDEN
);
3525 insns
= get_insns ();
3531 return extract_high_half (mode
, tem
);
3535 /* Try widening multiplication of opposite signedness, and adjust. */
3536 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3537 if (widening_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3538 && size
- 1 < BITS_PER_WORD
3539 && (mul_widen_cost (speed
, wider_mode
)
3540 + 2 * shift_cost (speed
, mode
, size
-1)
3541 + 4 * add_cost (speed
, mode
) < max_cost
))
3543 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3544 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3547 tem
= extract_high_half (mode
, tem
);
3548 /* We used the wrong signedness. Adjust the result. */
3549 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3557 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3558 putting the high half of the result in TARGET if that is convenient,
3559 and return where the result is. If the operation can not be performed,
3562 MODE is the mode of operation and result.
3564 UNSIGNEDP nonzero means unsigned multiply.
3566 MAX_COST is the total allowed cost for the expanded RTL. */
3569 expmed_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
3570 rtx target
, int unsignedp
, int max_cost
)
3572 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
3573 unsigned HOST_WIDE_INT cnst1
;
3575 bool sign_adjust
= false;
3576 enum mult_variant variant
;
3577 struct algorithm alg
;
3579 bool speed
= optimize_insn_for_speed_p ();
3581 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3582 /* We can't support modes wider than HOST_BITS_PER_INT. */
3583 gcc_assert (HWI_COMPUTABLE_MODE_P (mode
));
3585 cnst1
= INTVAL (op1
) & GET_MODE_MASK (mode
);
3587 /* We can't optimize modes wider than BITS_PER_WORD.
3588 ??? We might be able to perform double-word arithmetic if
3589 mode == word_mode, however all the cost calculations in
3590 synth_mult etc. assume single-word operations. */
3591 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3592 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3593 unsignedp
, max_cost
);
3595 extra_cost
= shift_cost (speed
, mode
, GET_MODE_BITSIZE (mode
) - 1);
3597 /* Check whether we try to multiply by a negative constant. */
3598 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3601 extra_cost
+= add_cost (speed
, mode
);
3604 /* See whether shift/add multiplication is cheap enough. */
3605 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3606 max_cost
- extra_cost
))
3608 /* See whether the specialized multiplication optabs are
3609 cheaper than the shift/add version. */
3610 tem
= expmed_mult_highpart_optab (mode
, op0
, op1
, target
, unsignedp
,
3611 alg
.cost
.cost
+ extra_cost
);
3615 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3616 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3617 tem
= extract_high_half (mode
, tem
);
3619 /* Adjust result for signedness. */
3621 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3625 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3626 unsignedp
, max_cost
);
3630 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3633 expand_smod_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3635 rtx result
, temp
, shift
;
3636 rtx_code_label
*label
;
3638 int prec
= GET_MODE_PRECISION (mode
);
3640 logd
= floor_log2 (d
);
3641 result
= gen_reg_rtx (mode
);
3643 /* Avoid conditional branches when they're expensive. */
3644 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3645 && optimize_insn_for_speed_p ())
3647 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3651 HOST_WIDE_INT masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3652 signmask
= force_reg (mode
, signmask
);
3653 shift
= GEN_INT (GET_MODE_BITSIZE (mode
) - logd
);
3655 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3656 which instruction sequence to use. If logical right shifts
3657 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3658 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3660 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3661 if (optab_handler (lshr_optab
, mode
) == CODE_FOR_nothing
3662 || (set_src_cost (temp
, optimize_insn_for_speed_p ())
3663 > COSTS_N_INSNS (2)))
3665 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3666 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3667 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3668 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3669 temp
= expand_binop (mode
, and_optab
, temp
,
3670 gen_int_mode (masklow
, mode
),
3671 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3672 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3673 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3674 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3675 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3679 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3680 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3681 signmask
= force_reg (mode
, signmask
);
3683 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3684 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3685 temp
= expand_binop (mode
, and_optab
, temp
,
3686 gen_int_mode (masklow
, mode
),
3687 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3688 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3689 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3695 /* Mask contains the mode's signbit and the significant bits of the
3696 modulus. By including the signbit in the operation, many targets
3697 can avoid an explicit compare operation in the following comparison
3699 wide_int mask
= wi::mask (logd
, false, prec
);
3700 mask
= wi::set_bit (mask
, prec
- 1);
3702 temp
= expand_binop (mode
, and_optab
, op0
,
3703 immed_wide_int_const (mask
, mode
),
3704 result
, 1, OPTAB_LIB_WIDEN
);
3706 emit_move_insn (result
, temp
);
3708 label
= gen_label_rtx ();
3709 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
3711 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
3712 0, OPTAB_LIB_WIDEN
);
3714 mask
= wi::mask (logd
, true, prec
);
3715 temp
= expand_binop (mode
, ior_optab
, temp
,
3716 immed_wide_int_const (mask
, mode
),
3717 result
, 1, OPTAB_LIB_WIDEN
);
3718 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
3719 0, OPTAB_LIB_WIDEN
);
3721 emit_move_insn (result
, temp
);
3726 /* Expand signed division of OP0 by a power of two D in mode MODE.
3727 This routine is only called for positive values of D. */
3730 expand_sdiv_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3733 rtx_code_label
*label
;
3736 logd
= floor_log2 (d
);
3739 && BRANCH_COST (optimize_insn_for_speed_p (),
3742 temp
= gen_reg_rtx (mode
);
3743 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
3744 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3745 0, OPTAB_LIB_WIDEN
);
3746 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3749 #ifdef HAVE_conditional_move
3750 if (BRANCH_COST (optimize_insn_for_speed_p (), false)
3756 temp2
= copy_to_mode_reg (mode
, op0
);
3757 temp
= expand_binop (mode
, add_optab
, temp2
, gen_int_mode (d
- 1, mode
),
3758 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3759 temp
= force_reg (mode
, temp
);
3761 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3762 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
3763 mode
, temp
, temp2
, mode
, 0);
3766 rtx_insn
*seq
= get_insns ();
3769 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, logd
, NULL_RTX
, 0);
3775 if (BRANCH_COST (optimize_insn_for_speed_p (),
3778 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
3780 temp
= gen_reg_rtx (mode
);
3781 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
3782 if (GET_MODE_BITSIZE (mode
) >= BITS_PER_WORD
3783 || shift_cost (optimize_insn_for_speed_p (), mode
, ushift
)
3784 > COSTS_N_INSNS (1))
3785 temp
= expand_binop (mode
, and_optab
, temp
, gen_int_mode (d
- 1, mode
),
3786 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3788 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
3789 ushift
, NULL_RTX
, 1);
3790 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3791 0, OPTAB_LIB_WIDEN
);
3792 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3795 label
= gen_label_rtx ();
3796 temp
= copy_to_mode_reg (mode
, op0
);
3797 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
3798 expand_inc (temp
, gen_int_mode (d
- 1, mode
));
3800 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3803 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3804 if that is convenient, and returning where the result is.
3805 You may request either the quotient or the remainder as the result;
3806 specify REM_FLAG nonzero to get the remainder.
3808 CODE is the expression code for which kind of division this is;
3809 it controls how rounding is done. MODE is the machine mode to use.
3810 UNSIGNEDP nonzero means do unsigned division. */
3812 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3813 and then correct it by or'ing in missing high bits
3814 if result of ANDI is nonzero.
3815 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3816 This could optimize to a bfexts instruction.
3817 But C doesn't use these operations, so their optimizations are
3819 /* ??? For modulo, we don't actually need the highpart of the first product,
3820 the low part will do nicely. And for small divisors, the second multiply
3821 can also be a low-part only multiply or even be completely left out.
3822 E.g. to calculate the remainder of a division by 3 with a 32 bit
3823 multiply, multiply with 0x55555556 and extract the upper two bits;
3824 the result is exact for inputs up to 0x1fffffff.
3825 The input range can be reduced by using cross-sum rules.
3826 For odd divisors >= 3, the following table gives right shift counts
3827 so that if a number is shifted by an integer multiple of the given
3828 amount, the remainder stays the same:
3829 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3830 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3831 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3832 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3833 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3835 Cross-sum rules for even numbers can be derived by leaving as many bits
3836 to the right alone as the divisor has zeros to the right.
3837 E.g. if x is an unsigned 32 bit number:
3838 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3842 expand_divmod (int rem_flag
, enum tree_code code
, enum machine_mode mode
,
3843 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
3845 enum machine_mode compute_mode
;
3847 rtx quotient
= 0, remainder
= 0;
3851 optab optab1
, optab2
;
3852 int op1_is_constant
, op1_is_pow2
= 0;
3853 int max_cost
, extra_cost
;
3854 static HOST_WIDE_INT last_div_const
= 0;
3855 bool speed
= optimize_insn_for_speed_p ();
3857 op1_is_constant
= CONST_INT_P (op1
);
3858 if (op1_is_constant
)
3860 unsigned HOST_WIDE_INT ext_op1
= UINTVAL (op1
);
3862 ext_op1
&= GET_MODE_MASK (mode
);
3863 op1_is_pow2
= ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1
)
3864 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1
))));
3868 This is the structure of expand_divmod:
3870 First comes code to fix up the operands so we can perform the operations
3871 correctly and efficiently.
3873 Second comes a switch statement with code specific for each rounding mode.
3874 For some special operands this code emits all RTL for the desired
3875 operation, for other cases, it generates only a quotient and stores it in
3876 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3877 to indicate that it has not done anything.
3879 Last comes code that finishes the operation. If QUOTIENT is set and
3880 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3881 QUOTIENT is not set, it is computed using trunc rounding.
3883 We try to generate special code for division and remainder when OP1 is a
3884 constant. If |OP1| = 2**n we can use shifts and some other fast
3885 operations. For other values of OP1, we compute a carefully selected
3886 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3889 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3890 half of the product. Different strategies for generating the product are
3891 implemented in expmed_mult_highpart.
3893 If what we actually want is the remainder, we generate that by another
3894 by-constant multiplication and a subtraction. */
3896 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3897 code below will malfunction if we are, so check here and handle
3898 the special case if so. */
3899 if (op1
== const1_rtx
)
3900 return rem_flag
? const0_rtx
: op0
;
3902 /* When dividing by -1, we could get an overflow.
3903 negv_optab can handle overflows. */
3904 if (! unsignedp
&& op1
== constm1_rtx
)
3908 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS (mode
) == MODE_INT
3909 ? negv_optab
: neg_optab
, op0
, target
, 0);
3913 /* Don't use the function value register as a target
3914 since we have to read it as well as write it,
3915 and function-inlining gets confused by this. */
3916 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3917 /* Don't clobber an operand while doing a multi-step calculation. */
3918 || ((rem_flag
|| op1_is_constant
)
3919 && (reg_mentioned_p (target
, op0
)
3920 || (MEM_P (op0
) && MEM_P (target
))))
3921 || reg_mentioned_p (target
, op1
)
3922 || (MEM_P (op1
) && MEM_P (target
))))
3925 /* Get the mode in which to perform this computation. Normally it will
3926 be MODE, but sometimes we can't do the desired operation in MODE.
3927 If so, pick a wider mode in which we can do the operation. Convert
3928 to that mode at the start to avoid repeated conversions.
3930 First see what operations we need. These depend on the expression
3931 we are evaluating. (We assume that divxx3 insns exist under the
3932 same conditions that modxx3 insns and that these insns don't normally
3933 fail. If these assumptions are not correct, we may generate less
3934 efficient code in some cases.)
3936 Then see if we find a mode in which we can open-code that operation
3937 (either a division, modulus, or shift). Finally, check for the smallest
3938 mode for which we can do the operation with a library call. */
3940 /* We might want to refine this now that we have division-by-constant
3941 optimization. Since expmed_mult_highpart tries so many variants, it is
3942 not straightforward to generalize this. Maybe we should make an array
3943 of possible modes in init_expmed? Save this for GCC 2.7. */
3945 optab1
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3946 ? (unsignedp
? lshr_optab
: ashr_optab
)
3947 : (unsignedp
? udiv_optab
: sdiv_optab
));
3948 optab2
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3950 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
3952 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3953 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3954 if (optab_handler (optab1
, compute_mode
) != CODE_FOR_nothing
3955 || optab_handler (optab2
, compute_mode
) != CODE_FOR_nothing
)
3958 if (compute_mode
== VOIDmode
)
3959 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3960 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3961 if (optab_libfunc (optab1
, compute_mode
)
3962 || optab_libfunc (optab2
, compute_mode
))
3965 /* If we still couldn't find a mode, use MODE, but expand_binop will
3967 if (compute_mode
== VOIDmode
)
3968 compute_mode
= mode
;
3970 if (target
&& GET_MODE (target
) == compute_mode
)
3973 tquotient
= gen_reg_rtx (compute_mode
);
3975 size
= GET_MODE_BITSIZE (compute_mode
);
3977 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3978 (mode), and thereby get better code when OP1 is a constant. Do that
3979 later. It will require going over all usages of SIZE below. */
3980 size
= GET_MODE_BITSIZE (mode
);
3983 /* Only deduct something for a REM if the last divide done was
3984 for a different constant. Then set the constant of the last
3986 max_cost
= (unsignedp
3987 ? udiv_cost (speed
, compute_mode
)
3988 : sdiv_cost (speed
, compute_mode
));
3989 if (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3990 && INTVAL (op1
) == last_div_const
))
3991 max_cost
-= (mul_cost (speed
, compute_mode
)
3992 + add_cost (speed
, compute_mode
));
3994 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3996 /* Now convert to the best mode to use. */
3997 if (compute_mode
!= mode
)
3999 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
4000 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
4002 /* convert_modes may have placed op1 into a register, so we
4003 must recompute the following. */
4004 op1_is_constant
= CONST_INT_P (op1
);
4005 op1_is_pow2
= (op1_is_constant
4006 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4008 && EXACT_POWER_OF_2_OR_ZERO_P (-UINTVAL (op1
))))));
4011 /* If one of the operands is a volatile MEM, copy it into a register. */
4013 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
4014 op0
= force_reg (compute_mode
, op0
);
4015 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
4016 op1
= force_reg (compute_mode
, op1
);
4018 /* If we need the remainder or if OP1 is constant, we need to
4019 put OP0 in a register in case it has any queued subexpressions. */
4020 if (rem_flag
|| op1_is_constant
)
4021 op0
= force_reg (compute_mode
, op0
);
4023 last
= get_last_insn ();
4025 /* Promote floor rounding to trunc rounding for unsigned operations. */
4028 if (code
== FLOOR_DIV_EXPR
)
4029 code
= TRUNC_DIV_EXPR
;
4030 if (code
== FLOOR_MOD_EXPR
)
4031 code
= TRUNC_MOD_EXPR
;
4032 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
4033 code
= TRUNC_DIV_EXPR
;
4036 if (op1
!= const0_rtx
)
4039 case TRUNC_MOD_EXPR
:
4040 case TRUNC_DIV_EXPR
:
4041 if (op1_is_constant
)
4045 unsigned HOST_WIDE_INT mh
, ml
;
4046 int pre_shift
, post_shift
;
4048 unsigned HOST_WIDE_INT d
= (INTVAL (op1
)
4049 & GET_MODE_MASK (compute_mode
));
4051 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4053 pre_shift
= floor_log2 (d
);
4056 unsigned HOST_WIDE_INT mask
4057 = ((unsigned HOST_WIDE_INT
) 1 << pre_shift
) - 1;
4059 = expand_binop (compute_mode
, and_optab
, op0
,
4060 gen_int_mode (mask
, compute_mode
),
4064 return gen_lowpart (mode
, remainder
);
4066 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4067 pre_shift
, tquotient
, 1);
4069 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4071 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
4073 /* Most significant bit of divisor is set; emit an scc
4075 quotient
= emit_store_flag_force (tquotient
, GEU
, op0
, op1
,
4076 compute_mode
, 1, 1);
4080 /* Find a suitable multiplier and right shift count
4081 instead of multiplying with D. */
4083 mh
= choose_multiplier (d
, size
, size
,
4084 &ml
, &post_shift
, &dummy
);
4086 /* If the suggested multiplier is more than SIZE bits,
4087 we can do better for even divisors, using an
4088 initial right shift. */
4089 if (mh
!= 0 && (d
& 1) == 0)
4091 pre_shift
= floor_log2 (d
& -d
);
4092 mh
= choose_multiplier (d
>> pre_shift
, size
,
4094 &ml
, &post_shift
, &dummy
);
4104 if (post_shift
- 1 >= BITS_PER_WORD
)
4108 = (shift_cost (speed
, compute_mode
, post_shift
- 1)
4109 + shift_cost (speed
, compute_mode
, 1)
4110 + 2 * add_cost (speed
, compute_mode
));
4111 t1
= expmed_mult_highpart
4113 gen_int_mode (ml
, compute_mode
),
4114 NULL_RTX
, 1, max_cost
- extra_cost
);
4117 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
4120 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
,
4121 t2
, 1, NULL_RTX
, 1);
4122 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
4125 quotient
= expand_shift
4126 (RSHIFT_EXPR
, compute_mode
, t4
,
4127 post_shift
- 1, tquotient
, 1);
4133 if (pre_shift
>= BITS_PER_WORD
4134 || post_shift
>= BITS_PER_WORD
)
4138 (RSHIFT_EXPR
, compute_mode
, op0
,
4139 pre_shift
, NULL_RTX
, 1);
4141 = (shift_cost (speed
, compute_mode
, pre_shift
)
4142 + shift_cost (speed
, compute_mode
, post_shift
));
4143 t2
= expmed_mult_highpart
4145 gen_int_mode (ml
, compute_mode
),
4146 NULL_RTX
, 1, max_cost
- extra_cost
);
4149 quotient
= expand_shift
4150 (RSHIFT_EXPR
, compute_mode
, t2
,
4151 post_shift
, tquotient
, 1);
4155 else /* Too wide mode to use tricky code */
4158 insn
= get_last_insn ();
4160 set_dst_reg_note (insn
, REG_EQUAL
,
4161 gen_rtx_UDIV (compute_mode
, op0
, op1
),
4164 else /* TRUNC_DIV, signed */
4166 unsigned HOST_WIDE_INT ml
;
4167 int lgup
, post_shift
;
4169 HOST_WIDE_INT d
= INTVAL (op1
);
4170 unsigned HOST_WIDE_INT abs_d
;
4172 /* Since d might be INT_MIN, we have to cast to
4173 unsigned HOST_WIDE_INT before negating to avoid
4174 undefined signed overflow. */
4176 ? (unsigned HOST_WIDE_INT
) d
4177 : - (unsigned HOST_WIDE_INT
) d
);
4179 /* n rem d = n rem -d */
4180 if (rem_flag
&& d
< 0)
4183 op1
= gen_int_mode (abs_d
, compute_mode
);
4189 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
4191 else if (HOST_BITS_PER_WIDE_INT
>= size
4192 && abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4194 /* This case is not handled correctly below. */
4195 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
4196 compute_mode
, 1, 1);
4200 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
4202 ? smod_pow2_cheap (speed
, compute_mode
)
4203 : sdiv_pow2_cheap (speed
, compute_mode
))
4204 /* We assume that cheap metric is true if the
4205 optab has an expander for this mode. */
4206 && ((optab_handler ((rem_flag
? smod_optab
4209 != CODE_FOR_nothing
)
4210 || (optab_handler (sdivmod_optab
,
4212 != CODE_FOR_nothing
)))
4214 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
4218 remainder
= expand_smod_pow2 (compute_mode
, op0
, d
);
4220 return gen_lowpart (mode
, remainder
);
4223 if (sdiv_pow2_cheap (speed
, compute_mode
)
4224 && ((optab_handler (sdiv_optab
, compute_mode
)
4225 != CODE_FOR_nothing
)
4226 || (optab_handler (sdivmod_optab
, compute_mode
)
4227 != CODE_FOR_nothing
)))
4228 quotient
= expand_divmod (0, TRUNC_DIV_EXPR
,
4230 gen_int_mode (abs_d
,
4234 quotient
= expand_sdiv_pow2 (compute_mode
, op0
, abs_d
);
4236 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4237 negate the quotient. */
4240 insn
= get_last_insn ();
4242 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
4243 << (HOST_BITS_PER_WIDE_INT
- 1)))
4244 set_dst_reg_note (insn
, REG_EQUAL
,
4245 gen_rtx_DIV (compute_mode
, op0
,
4251 quotient
= expand_unop (compute_mode
, neg_optab
,
4252 quotient
, quotient
, 0);
4255 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4257 choose_multiplier (abs_d
, size
, size
- 1,
4258 &ml
, &post_shift
, &lgup
);
4259 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4263 if (post_shift
>= BITS_PER_WORD
4264 || size
- 1 >= BITS_PER_WORD
)
4267 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4268 + shift_cost (speed
, compute_mode
, size
- 1)
4269 + add_cost (speed
, compute_mode
));
4270 t1
= expmed_mult_highpart
4271 (compute_mode
, op0
, gen_int_mode (ml
, compute_mode
),
4272 NULL_RTX
, 0, max_cost
- extra_cost
);
4276 (RSHIFT_EXPR
, compute_mode
, t1
,
4277 post_shift
, NULL_RTX
, 0);
4279 (RSHIFT_EXPR
, compute_mode
, op0
,
4280 size
- 1, NULL_RTX
, 0);
4283 = force_operand (gen_rtx_MINUS (compute_mode
,
4288 = force_operand (gen_rtx_MINUS (compute_mode
,
4296 if (post_shift
>= BITS_PER_WORD
4297 || size
- 1 >= BITS_PER_WORD
)
4300 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
4301 mlr
= gen_int_mode (ml
, compute_mode
);
4302 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4303 + shift_cost (speed
, compute_mode
, size
- 1)
4304 + 2 * add_cost (speed
, compute_mode
));
4305 t1
= expmed_mult_highpart (compute_mode
, op0
, mlr
,
4307 max_cost
- extra_cost
);
4310 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
4314 (RSHIFT_EXPR
, compute_mode
, t2
,
4315 post_shift
, NULL_RTX
, 0);
4317 (RSHIFT_EXPR
, compute_mode
, op0
,
4318 size
- 1, NULL_RTX
, 0);
4321 = force_operand (gen_rtx_MINUS (compute_mode
,
4326 = force_operand (gen_rtx_MINUS (compute_mode
,
4331 else /* Too wide mode to use tricky code */
4334 insn
= get_last_insn ();
4336 set_dst_reg_note (insn
, REG_EQUAL
,
4337 gen_rtx_DIV (compute_mode
, op0
, op1
),
4343 delete_insns_since (last
);
4346 case FLOOR_DIV_EXPR
:
4347 case FLOOR_MOD_EXPR
:
4348 /* We will come here only for signed operations. */
4349 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4351 unsigned HOST_WIDE_INT mh
, ml
;
4352 int pre_shift
, lgup
, post_shift
;
4353 HOST_WIDE_INT d
= INTVAL (op1
);
4357 /* We could just as easily deal with negative constants here,
4358 but it does not seem worth the trouble for GCC 2.6. */
4359 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4361 pre_shift
= floor_log2 (d
);
4364 unsigned HOST_WIDE_INT mask
4365 = ((unsigned HOST_WIDE_INT
) 1 << pre_shift
) - 1;
4366 remainder
= expand_binop
4367 (compute_mode
, and_optab
, op0
,
4368 gen_int_mode (mask
, compute_mode
),
4369 remainder
, 0, OPTAB_LIB_WIDEN
);
4371 return gen_lowpart (mode
, remainder
);
4373 quotient
= expand_shift
4374 (RSHIFT_EXPR
, compute_mode
, op0
,
4375 pre_shift
, tquotient
, 0);
4381 mh
= choose_multiplier (d
, size
, size
- 1,
4382 &ml
, &post_shift
, &lgup
);
4385 if (post_shift
< BITS_PER_WORD
4386 && size
- 1 < BITS_PER_WORD
)
4389 (RSHIFT_EXPR
, compute_mode
, op0
,
4390 size
- 1, NULL_RTX
, 0);
4391 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
4392 NULL_RTX
, 0, OPTAB_WIDEN
);
4393 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4394 + shift_cost (speed
, compute_mode
, size
- 1)
4395 + 2 * add_cost (speed
, compute_mode
));
4396 t3
= expmed_mult_highpart
4397 (compute_mode
, t2
, gen_int_mode (ml
, compute_mode
),
4398 NULL_RTX
, 1, max_cost
- extra_cost
);
4402 (RSHIFT_EXPR
, compute_mode
, t3
,
4403 post_shift
, NULL_RTX
, 1);
4404 quotient
= expand_binop (compute_mode
, xor_optab
,
4405 t4
, t1
, tquotient
, 0,
4413 rtx nsign
, t1
, t2
, t3
, t4
;
4414 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
4415 op0
, constm1_rtx
), NULL_RTX
);
4416 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
4418 nsign
= expand_shift
4419 (RSHIFT_EXPR
, compute_mode
, t2
,
4420 size
- 1, NULL_RTX
, 0);
4421 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
4423 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
4428 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
4430 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4439 delete_insns_since (last
);
4441 /* Try using an instruction that produces both the quotient and
4442 remainder, using truncation. We can easily compensate the quotient
4443 or remainder to get floor rounding, once we have the remainder.
4444 Notice that we compute also the final remainder value here,
4445 and return the result right away. */
4446 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4447 target
= gen_reg_rtx (compute_mode
);
4452 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4453 quotient
= gen_reg_rtx (compute_mode
);
4458 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4459 remainder
= gen_reg_rtx (compute_mode
);
4462 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
4463 quotient
, remainder
, 0))
4465 /* This could be computed with a branch-less sequence.
4466 Save that for later. */
4468 rtx_code_label
*label
= gen_label_rtx ();
4469 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
4470 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4471 NULL_RTX
, 0, OPTAB_WIDEN
);
4472 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
4473 expand_dec (quotient
, const1_rtx
);
4474 expand_inc (remainder
, op1
);
4476 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4479 /* No luck with division elimination or divmod. Have to do it
4480 by conditionally adjusting op0 *and* the result. */
4482 rtx_code_label
*label1
, *label2
, *label3
, *label4
, *label5
;
4486 quotient
= gen_reg_rtx (compute_mode
);
4487 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4488 label1
= gen_label_rtx ();
4489 label2
= gen_label_rtx ();
4490 label3
= gen_label_rtx ();
4491 label4
= gen_label_rtx ();
4492 label5
= gen_label_rtx ();
4493 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4494 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
4495 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4496 quotient
, 0, OPTAB_LIB_WIDEN
);
4497 if (tem
!= quotient
)
4498 emit_move_insn (quotient
, tem
);
4499 emit_jump_insn (gen_jump (label5
));
4501 emit_label (label1
);
4502 expand_inc (adjusted_op0
, const1_rtx
);
4503 emit_jump_insn (gen_jump (label4
));
4505 emit_label (label2
);
4506 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
4507 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4508 quotient
, 0, OPTAB_LIB_WIDEN
);
4509 if (tem
!= quotient
)
4510 emit_move_insn (quotient
, tem
);
4511 emit_jump_insn (gen_jump (label5
));
4513 emit_label (label3
);
4514 expand_dec (adjusted_op0
, const1_rtx
);
4515 emit_label (label4
);
4516 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4517 quotient
, 0, OPTAB_LIB_WIDEN
);
4518 if (tem
!= quotient
)
4519 emit_move_insn (quotient
, tem
);
4520 expand_dec (quotient
, const1_rtx
);
4521 emit_label (label5
);
4529 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
4532 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4533 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4534 floor_log2 (d
), tquotient
, 1);
4535 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4536 gen_int_mode (d
- 1, compute_mode
),
4537 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4538 t3
= gen_reg_rtx (compute_mode
);
4539 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4540 compute_mode
, 1, 1);
4543 rtx_code_label
*lab
;
4544 lab
= gen_label_rtx ();
4545 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4546 expand_inc (t1
, const1_rtx
);
4551 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4557 /* Try using an instruction that produces both the quotient and
4558 remainder, using truncation. We can easily compensate the
4559 quotient or remainder to get ceiling rounding, once we have the
4560 remainder. Notice that we compute also the final remainder
4561 value here, and return the result right away. */
4562 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4563 target
= gen_reg_rtx (compute_mode
);
4567 remainder
= (REG_P (target
)
4568 ? target
: gen_reg_rtx (compute_mode
));
4569 quotient
= gen_reg_rtx (compute_mode
);
4573 quotient
= (REG_P (target
)
4574 ? target
: gen_reg_rtx (compute_mode
));
4575 remainder
= gen_reg_rtx (compute_mode
);
4578 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4581 /* This could be computed with a branch-less sequence.
4582 Save that for later. */
4583 rtx_code_label
*label
= gen_label_rtx ();
4584 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4585 compute_mode
, label
);
4586 expand_inc (quotient
, const1_rtx
);
4587 expand_dec (remainder
, op1
);
4589 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4592 /* No luck with division elimination or divmod. Have to do it
4593 by conditionally adjusting op0 *and* the result. */
4595 rtx_code_label
*label1
, *label2
;
4596 rtx adjusted_op0
, tem
;
4598 quotient
= gen_reg_rtx (compute_mode
);
4599 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4600 label1
= gen_label_rtx ();
4601 label2
= gen_label_rtx ();
4602 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4603 compute_mode
, label1
);
4604 emit_move_insn (quotient
, const0_rtx
);
4605 emit_jump_insn (gen_jump (label2
));
4607 emit_label (label1
);
4608 expand_dec (adjusted_op0
, const1_rtx
);
4609 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4610 quotient
, 1, OPTAB_LIB_WIDEN
);
4611 if (tem
!= quotient
)
4612 emit_move_insn (quotient
, tem
);
4613 expand_inc (quotient
, const1_rtx
);
4614 emit_label (label2
);
4619 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4620 && INTVAL (op1
) >= 0)
4622 /* This is extremely similar to the code for the unsigned case
4623 above. For 2.7 we should merge these variants, but for
4624 2.6.1 I don't want to touch the code for unsigned since that
4625 get used in C. The signed case will only be used by other
4629 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4630 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4631 floor_log2 (d
), tquotient
, 0);
4632 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4633 gen_int_mode (d
- 1, compute_mode
),
4634 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4635 t3
= gen_reg_rtx (compute_mode
);
4636 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4637 compute_mode
, 1, 1);
4640 rtx_code_label
*lab
;
4641 lab
= gen_label_rtx ();
4642 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4643 expand_inc (t1
, const1_rtx
);
4648 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4654 /* Try using an instruction that produces both the quotient and
4655 remainder, using truncation. We can easily compensate the
4656 quotient or remainder to get ceiling rounding, once we have the
4657 remainder. Notice that we compute also the final remainder
4658 value here, and return the result right away. */
4659 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4660 target
= gen_reg_rtx (compute_mode
);
4663 remainder
= (REG_P (target
)
4664 ? target
: gen_reg_rtx (compute_mode
));
4665 quotient
= gen_reg_rtx (compute_mode
);
4669 quotient
= (REG_P (target
)
4670 ? target
: gen_reg_rtx (compute_mode
));
4671 remainder
= gen_reg_rtx (compute_mode
);
4674 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4677 /* This could be computed with a branch-less sequence.
4678 Save that for later. */
4680 rtx_code_label
*label
= gen_label_rtx ();
4681 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4682 compute_mode
, label
);
4683 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4684 NULL_RTX
, 0, OPTAB_WIDEN
);
4685 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4686 expand_inc (quotient
, const1_rtx
);
4687 expand_dec (remainder
, op1
);
4689 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4692 /* No luck with division elimination or divmod. Have to do it
4693 by conditionally adjusting op0 *and* the result. */
4695 rtx_code_label
*label1
, *label2
, *label3
, *label4
, *label5
;
4699 quotient
= gen_reg_rtx (compute_mode
);
4700 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4701 label1
= gen_label_rtx ();
4702 label2
= gen_label_rtx ();
4703 label3
= gen_label_rtx ();
4704 label4
= gen_label_rtx ();
4705 label5
= gen_label_rtx ();
4706 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4707 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
4708 compute_mode
, label1
);
4709 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4710 quotient
, 0, OPTAB_LIB_WIDEN
);
4711 if (tem
!= quotient
)
4712 emit_move_insn (quotient
, tem
);
4713 emit_jump_insn (gen_jump (label5
));
4715 emit_label (label1
);
4716 expand_dec (adjusted_op0
, const1_rtx
);
4717 emit_jump_insn (gen_jump (label4
));
4719 emit_label (label2
);
4720 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
4721 compute_mode
, label3
);
4722 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4723 quotient
, 0, OPTAB_LIB_WIDEN
);
4724 if (tem
!= quotient
)
4725 emit_move_insn (quotient
, tem
);
4726 emit_jump_insn (gen_jump (label5
));
4728 emit_label (label3
);
4729 expand_inc (adjusted_op0
, const1_rtx
);
4730 emit_label (label4
);
4731 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4732 quotient
, 0, OPTAB_LIB_WIDEN
);
4733 if (tem
!= quotient
)
4734 emit_move_insn (quotient
, tem
);
4735 expand_inc (quotient
, const1_rtx
);
4736 emit_label (label5
);
4741 case EXACT_DIV_EXPR
:
4742 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4744 HOST_WIDE_INT d
= INTVAL (op1
);
4745 unsigned HOST_WIDE_INT ml
;
4749 pre_shift
= floor_log2 (d
& -d
);
4750 ml
= invert_mod2n (d
>> pre_shift
, size
);
4751 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4752 pre_shift
, NULL_RTX
, unsignedp
);
4753 quotient
= expand_mult (compute_mode
, t1
,
4754 gen_int_mode (ml
, compute_mode
),
4757 insn
= get_last_insn ();
4758 set_dst_reg_note (insn
, REG_EQUAL
,
4759 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
4760 compute_mode
, op0
, op1
),
4765 case ROUND_DIV_EXPR
:
4766 case ROUND_MOD_EXPR
:
4770 rtx_code_label
*label
;
4771 label
= gen_label_rtx ();
4772 quotient
= gen_reg_rtx (compute_mode
);
4773 remainder
= gen_reg_rtx (compute_mode
);
4774 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
4777 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
4778 quotient
, 1, OPTAB_LIB_WIDEN
);
4779 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
4780 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4781 remainder
, 1, OPTAB_LIB_WIDEN
);
4783 tem
= plus_constant (compute_mode
, op1
, -1);
4784 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
, 1, NULL_RTX
, 1);
4785 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
4786 expand_inc (quotient
, const1_rtx
);
4787 expand_dec (remainder
, op1
);
4792 rtx abs_rem
, abs_op1
, tem
, mask
;
4793 rtx_code_label
*label
;
4794 label
= gen_label_rtx ();
4795 quotient
= gen_reg_rtx (compute_mode
);
4796 remainder
= gen_reg_rtx (compute_mode
);
4797 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
4800 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
4801 quotient
, 0, OPTAB_LIB_WIDEN
);
4802 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
4803 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4804 remainder
, 0, OPTAB_LIB_WIDEN
);
4806 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
4807 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
4808 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
4810 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
4811 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4812 NULL_RTX
, 0, OPTAB_WIDEN
);
4813 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4814 size
- 1, NULL_RTX
, 0);
4815 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
4816 NULL_RTX
, 0, OPTAB_WIDEN
);
4817 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4818 NULL_RTX
, 0, OPTAB_WIDEN
);
4819 expand_inc (quotient
, tem
);
4820 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
4821 NULL_RTX
, 0, OPTAB_WIDEN
);
4822 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4823 NULL_RTX
, 0, OPTAB_WIDEN
);
4824 expand_dec (remainder
, tem
);
4827 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4835 if (target
&& GET_MODE (target
) != compute_mode
)
4840 /* Try to produce the remainder without producing the quotient.
4841 If we seem to have a divmod pattern that does not require widening,
4842 don't try widening here. We should really have a WIDEN argument
4843 to expand_twoval_binop, since what we'd really like to do here is
4844 1) try a mod insn in compute_mode
4845 2) try a divmod insn in compute_mode
4846 3) try a div insn in compute_mode and multiply-subtract to get
4848 4) try the same things with widening allowed. */
4850 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4853 ((optab_handler (optab2
, compute_mode
)
4854 != CODE_FOR_nothing
)
4855 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4858 /* No luck there. Can we do remainder and divide at once
4859 without a library call? */
4860 remainder
= gen_reg_rtx (compute_mode
);
4861 if (! expand_twoval_binop ((unsignedp
4865 NULL_RTX
, remainder
, unsignedp
))
4870 return gen_lowpart (mode
, remainder
);
4873 /* Produce the quotient. Try a quotient insn, but not a library call.
4874 If we have a divmod in this mode, use it in preference to widening
4875 the div (for this test we assume it will not fail). Note that optab2
4876 is set to the one of the two optabs that the call below will use. */
4878 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
4879 op0
, op1
, rem_flag
? NULL_RTX
: target
,
4881 ((optab_handler (optab2
, compute_mode
)
4882 != CODE_FOR_nothing
)
4883 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4887 /* No luck there. Try a quotient-and-remainder insn,
4888 keeping the quotient alone. */
4889 quotient
= gen_reg_rtx (compute_mode
);
4890 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
4892 quotient
, NULL_RTX
, unsignedp
))
4896 /* Still no luck. If we are not computing the remainder,
4897 use a library call for the quotient. */
4898 quotient
= sign_expand_binop (compute_mode
,
4899 udiv_optab
, sdiv_optab
,
4901 unsignedp
, OPTAB_LIB_WIDEN
);
4908 if (target
&& GET_MODE (target
) != compute_mode
)
4913 /* No divide instruction either. Use library for remainder. */
4914 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4916 unsignedp
, OPTAB_LIB_WIDEN
);
4917 /* No remainder function. Try a quotient-and-remainder
4918 function, keeping the remainder. */
4921 remainder
= gen_reg_rtx (compute_mode
);
4922 if (!expand_twoval_binop_libfunc
4923 (unsignedp
? udivmod_optab
: sdivmod_optab
,
4925 NULL_RTX
, remainder
,
4926 unsignedp
? UMOD
: MOD
))
4927 remainder
= NULL_RTX
;
4932 /* We divided. Now finish doing X - Y * (X / Y). */
4933 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4934 NULL_RTX
, unsignedp
);
4935 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4936 remainder
, target
, unsignedp
,
4941 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4944 /* Return a tree node with data type TYPE, describing the value of X.
4945 Usually this is an VAR_DECL, if there is no obvious better choice.
4946 X may be an expression, however we only support those expressions
4947 generated by loop.c. */
4950 make_tree (tree type
, rtx x
)
4954 switch (GET_CODE (x
))
4957 case CONST_WIDE_INT
:
4958 t
= wide_int_to_tree (type
, std::make_pair (x
, TYPE_MODE (type
)));
4962 STATIC_ASSERT (HOST_BITS_PER_WIDE_INT
* 2 <= MAX_BITSIZE_MODE_ANY_INT
);
4963 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (x
) == VOIDmode
)
4964 t
= wide_int_to_tree (type
,
4965 wide_int::from_array (&CONST_DOUBLE_LOW (x
), 2,
4966 HOST_BITS_PER_WIDE_INT
* 2));
4971 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4972 t
= build_real (type
, d
);
4979 int units
= CONST_VECTOR_NUNITS (x
);
4980 tree itype
= TREE_TYPE (type
);
4984 /* Build a tree with vector elements. */
4985 elts
= XALLOCAVEC (tree
, units
);
4986 for (i
= units
- 1; i
>= 0; --i
)
4988 rtx elt
= CONST_VECTOR_ELT (x
, i
);
4989 elts
[i
] = make_tree (itype
, elt
);
4992 return build_vector (type
, elts
);
4996 return fold_build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4997 make_tree (type
, XEXP (x
, 1)));
5000 return fold_build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5001 make_tree (type
, XEXP (x
, 1)));
5004 return fold_build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0)));
5007 return fold_build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5008 make_tree (type
, XEXP (x
, 1)));
5011 return fold_build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5012 make_tree (type
, XEXP (x
, 1)));
5015 t
= unsigned_type_for (type
);
5016 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5017 make_tree (t
, XEXP (x
, 0)),
5018 make_tree (type
, XEXP (x
, 1))));
5021 t
= signed_type_for (type
);
5022 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5023 make_tree (t
, XEXP (x
, 0)),
5024 make_tree (type
, XEXP (x
, 1))));
5027 if (TREE_CODE (type
) != REAL_TYPE
)
5028 t
= signed_type_for (type
);
5032 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5033 make_tree (t
, XEXP (x
, 0)),
5034 make_tree (t
, XEXP (x
, 1))));
5036 t
= unsigned_type_for (type
);
5037 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5038 make_tree (t
, XEXP (x
, 0)),
5039 make_tree (t
, XEXP (x
, 1))));
5043 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
5044 GET_CODE (x
) == ZERO_EXTEND
);
5045 return fold_convert (type
, make_tree (t
, XEXP (x
, 0)));
5048 return make_tree (type
, XEXP (x
, 0));
5051 t
= SYMBOL_REF_DECL (x
);
5053 return fold_convert (type
, build_fold_addr_expr (t
));
5054 /* else fall through. */
5057 t
= build_decl (RTL_LOCATION (x
), VAR_DECL
, NULL_TREE
, type
);
5059 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5060 address mode to pointer mode. */
5061 if (POINTER_TYPE_P (type
))
5062 x
= convert_memory_address_addr_space
5063 (TYPE_MODE (type
), x
, TYPE_ADDR_SPACE (TREE_TYPE (type
)));
5065 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5066 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5067 t
->decl_with_rtl
.rtl
= x
;
5073 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5074 and returning TARGET.
5076 If TARGET is 0, a pseudo-register or constant is returned. */
5079 expand_and (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
5083 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
5084 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
5086 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
5090 else if (tem
!= target
)
5091 emit_move_insn (target
, tem
);
5095 /* Helper function for emit_store_flag. */
5097 emit_cstore (rtx target
, enum insn_code icode
, enum rtx_code code
,
5098 enum machine_mode mode
, enum machine_mode compare_mode
,
5099 int unsignedp
, rtx x
, rtx y
, int normalizep
,
5100 enum machine_mode target_mode
)
5102 struct expand_operand ops
[4];
5103 rtx op0
, comparison
, subtarget
;
5105 enum machine_mode result_mode
= targetm
.cstore_mode (icode
);
5107 last
= get_last_insn ();
5108 x
= prepare_operand (icode
, x
, 2, mode
, compare_mode
, unsignedp
);
5109 y
= prepare_operand (icode
, y
, 3, mode
, compare_mode
, unsignedp
);
5112 delete_insns_since (last
);
5116 if (target_mode
== VOIDmode
)
5117 target_mode
= result_mode
;
5119 target
= gen_reg_rtx (target_mode
);
5121 comparison
= gen_rtx_fmt_ee (code
, result_mode
, x
, y
);
5123 create_output_operand (&ops
[0], optimize
? NULL_RTX
: target
, result_mode
);
5124 create_fixed_operand (&ops
[1], comparison
);
5125 create_fixed_operand (&ops
[2], x
);
5126 create_fixed_operand (&ops
[3], y
);
5127 if (!maybe_expand_insn (icode
, 4, ops
))
5129 delete_insns_since (last
);
5132 subtarget
= ops
[0].value
;
5134 /* If we are converting to a wider mode, first convert to
5135 TARGET_MODE, then normalize. This produces better combining
5136 opportunities on machines that have a SIGN_EXTRACT when we are
5137 testing a single bit. This mostly benefits the 68k.
5139 If STORE_FLAG_VALUE does not have the sign bit set when
5140 interpreted in MODE, we can do this conversion as unsigned, which
5141 is usually more efficient. */
5142 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (result_mode
))
5144 convert_move (target
, subtarget
,
5145 val_signbit_known_clear_p (result_mode
,
5148 result_mode
= target_mode
;
5153 /* If we want to keep subexpressions around, don't reuse our last
5158 /* Now normalize to the proper value in MODE. Sometimes we don't
5159 have to do anything. */
5160 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
5162 /* STORE_FLAG_VALUE might be the most negative number, so write
5163 the comparison this way to avoid a compiler-time warning. */
5164 else if (- normalizep
== STORE_FLAG_VALUE
)
5165 op0
= expand_unop (result_mode
, neg_optab
, op0
, subtarget
, 0);
5167 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5168 it hard to use a value of just the sign bit due to ANSI integer
5169 constant typing rules. */
5170 else if (val_signbit_known_set_p (result_mode
, STORE_FLAG_VALUE
))
5171 op0
= expand_shift (RSHIFT_EXPR
, result_mode
, op0
,
5172 GET_MODE_BITSIZE (result_mode
) - 1, subtarget
,
5176 gcc_assert (STORE_FLAG_VALUE
& 1);
5178 op0
= expand_and (result_mode
, op0
, const1_rtx
, subtarget
);
5179 if (normalizep
== -1)
5180 op0
= expand_unop (result_mode
, neg_optab
, op0
, op0
, 0);
5183 /* If we were converting to a smaller mode, do the conversion now. */
5184 if (target_mode
!= result_mode
)
5186 convert_move (target
, op0
, 0);
5194 /* A subroutine of emit_store_flag only including "tricks" that do not
5195 need a recursive call. These are kept separate to avoid infinite
5199 emit_store_flag_1 (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5200 enum machine_mode mode
, int unsignedp
, int normalizep
,
5201 enum machine_mode target_mode
)
5204 enum insn_code icode
;
5205 enum machine_mode compare_mode
;
5206 enum mode_class mclass
;
5207 enum rtx_code scode
;
5211 code
= unsigned_condition (code
);
5212 scode
= swap_condition (code
);
5214 /* If one operand is constant, make it the second one. Only do this
5215 if the other operand is not constant as well. */
5217 if (swap_commutative_operands_p (op0
, op1
))
5222 code
= swap_condition (code
);
5225 if (mode
== VOIDmode
)
5226 mode
= GET_MODE (op0
);
5228 /* For some comparisons with 1 and -1, we can convert this to
5229 comparisons with zero. This will often produce more opportunities for
5230 store-flag insns. */
5235 if (op1
== const1_rtx
)
5236 op1
= const0_rtx
, code
= LE
;
5239 if (op1
== constm1_rtx
)
5240 op1
= const0_rtx
, code
= LT
;
5243 if (op1
== const1_rtx
)
5244 op1
= const0_rtx
, code
= GT
;
5247 if (op1
== constm1_rtx
)
5248 op1
= const0_rtx
, code
= GE
;
5251 if (op1
== const1_rtx
)
5252 op1
= const0_rtx
, code
= NE
;
5255 if (op1
== const1_rtx
)
5256 op1
= const0_rtx
, code
= EQ
;
5262 /* If we are comparing a double-word integer with zero or -1, we can
5263 convert the comparison into one involving a single word. */
5264 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
5265 && GET_MODE_CLASS (mode
) == MODE_INT
5266 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
5268 if ((code
== EQ
|| code
== NE
)
5269 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
5273 /* Do a logical OR or AND of the two words and compare the
5275 op00
= simplify_gen_subreg (word_mode
, op0
, mode
, 0);
5276 op01
= simplify_gen_subreg (word_mode
, op0
, mode
, UNITS_PER_WORD
);
5277 tem
= expand_binop (word_mode
,
5278 op1
== const0_rtx
? ior_optab
: and_optab
,
5279 op00
, op01
, NULL_RTX
, unsignedp
,
5283 tem
= emit_store_flag (NULL_RTX
, code
, tem
, op1
, word_mode
,
5284 unsignedp
, normalizep
);
5286 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
5290 /* If testing the sign bit, can just test on high word. */
5291 op0h
= simplify_gen_subreg (word_mode
, op0
, mode
,
5292 subreg_highpart_offset (word_mode
,
5294 tem
= emit_store_flag (NULL_RTX
, code
, op0h
, op1
, word_mode
,
5295 unsignedp
, normalizep
);
5302 if (target_mode
== VOIDmode
|| GET_MODE (tem
) == target_mode
)
5305 target
= gen_reg_rtx (target_mode
);
5307 convert_move (target
, tem
,
5308 !val_signbit_known_set_p (word_mode
,
5309 (normalizep
? normalizep
5310 : STORE_FLAG_VALUE
)));
5315 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5316 complement of A (for GE) and shifting the sign bit to the low bit. */
5317 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
5318 && GET_MODE_CLASS (mode
) == MODE_INT
5319 && (normalizep
|| STORE_FLAG_VALUE
== 1
5320 || val_signbit_p (mode
, STORE_FLAG_VALUE
)))
5327 /* If the result is to be wider than OP0, it is best to convert it
5328 first. If it is to be narrower, it is *incorrect* to convert it
5330 else if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
5332 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5336 if (target_mode
!= mode
)
5340 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
5341 ((STORE_FLAG_VALUE
== 1 || normalizep
)
5342 ? 0 : subtarget
), 0);
5344 if (STORE_FLAG_VALUE
== 1 || normalizep
)
5345 /* If we are supposed to produce a 0/1 value, we want to do
5346 a logical shift from the sign bit to the low-order bit; for
5347 a -1/0 value, we do an arithmetic shift. */
5348 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5349 GET_MODE_BITSIZE (mode
) - 1,
5350 subtarget
, normalizep
!= -1);
5352 if (mode
!= target_mode
)
5353 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5358 mclass
= GET_MODE_CLASS (mode
);
5359 for (compare_mode
= mode
; compare_mode
!= VOIDmode
;
5360 compare_mode
= GET_MODE_WIDER_MODE (compare_mode
))
5362 enum machine_mode optab_mode
= mclass
== MODE_CC
? CCmode
: compare_mode
;
5363 icode
= optab_handler (cstore_optab
, optab_mode
);
5364 if (icode
!= CODE_FOR_nothing
)
5366 do_pending_stack_adjust ();
5367 tem
= emit_cstore (target
, icode
, code
, mode
, compare_mode
,
5368 unsignedp
, op0
, op1
, normalizep
, target_mode
);
5372 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5374 tem
= emit_cstore (target
, icode
, scode
, mode
, compare_mode
,
5375 unsignedp
, op1
, op0
, normalizep
, target_mode
);
5386 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5387 and storing in TARGET. Normally return TARGET.
5388 Return 0 if that cannot be done.
5390 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5391 it is VOIDmode, they cannot both be CONST_INT.
5393 UNSIGNEDP is for the case where we have to widen the operands
5394 to perform the operation. It says to use zero-extension.
5396 NORMALIZEP is 1 if we should convert the result to be either zero
5397 or one. Normalize is -1 if we should convert the result to be
5398 either zero or -1. If NORMALIZEP is zero, the result will be left
5399 "raw" out of the scc insn. */
5402 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5403 enum machine_mode mode
, int unsignedp
, int normalizep
)
5405 enum machine_mode target_mode
= target
? GET_MODE (target
) : VOIDmode
;
5406 enum rtx_code rcode
;
5411 /* If we compare constants, we shouldn't use a store-flag operation,
5412 but a constant load. We can get there via the vanilla route that
5413 usually generates a compare-branch sequence, but will in this case
5414 fold the comparison to a constant, and thus elide the branch. */
5415 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
5418 tem
= emit_store_flag_1 (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
,
5423 /* If we reached here, we can't do this with a scc insn, however there
5424 are some comparisons that can be done in other ways. Don't do any
5425 of these cases if branches are very cheap. */
5426 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5429 /* See what we need to return. We can only return a 1, -1, or the
5432 if (normalizep
== 0)
5434 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5435 normalizep
= STORE_FLAG_VALUE
;
5437 else if (val_signbit_p (mode
, STORE_FLAG_VALUE
))
5443 last
= get_last_insn ();
5445 /* If optimizing, use different pseudo registers for each insn, instead
5446 of reusing the same pseudo. This leads to better CSE, but slows
5447 down the compiler, since there are more pseudos */
5448 subtarget
= (!optimize
5449 && (target_mode
== mode
)) ? target
: NULL_RTX
;
5450 trueval
= GEN_INT (normalizep
? normalizep
: STORE_FLAG_VALUE
);
5452 /* For floating-point comparisons, try the reverse comparison or try
5453 changing the "orderedness" of the comparison. */
5454 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5456 enum rtx_code first_code
;
5459 rcode
= reverse_condition_maybe_unordered (code
);
5460 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5461 && (code
== ORDERED
|| code
== UNORDERED
5462 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5463 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5465 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5466 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5468 /* For the reverse comparison, use either an addition or a XOR. */
5470 && rtx_cost (GEN_INT (normalizep
), PLUS
, 1,
5471 optimize_insn_for_speed_p ()) == 0)
5473 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5474 STORE_FLAG_VALUE
, target_mode
);
5476 return expand_binop (target_mode
, add_optab
, tem
,
5477 gen_int_mode (normalizep
, target_mode
),
5478 target
, 0, OPTAB_WIDEN
);
5481 && rtx_cost (trueval
, XOR
, 1,
5482 optimize_insn_for_speed_p ()) == 0)
5484 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5485 normalizep
, target_mode
);
5487 return expand_binop (target_mode
, xor_optab
, tem
, trueval
,
5488 target
, INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5492 delete_insns_since (last
);
5494 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5495 if (code
== ORDERED
|| code
== UNORDERED
)
5498 and_them
= split_comparison (code
, mode
, &first_code
, &code
);
5500 /* If there are no NaNs, the first comparison should always fall through.
5501 Effectively change the comparison to the other one. */
5502 if (!HONOR_NANS (mode
))
5504 gcc_assert (first_code
== (and_them
? ORDERED
: UNORDERED
));
5505 return emit_store_flag_1 (target
, code
, op0
, op1
, mode
, 0, normalizep
,
5509 #ifdef HAVE_conditional_move
5510 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5511 conditional move. */
5512 tem
= emit_store_flag_1 (subtarget
, first_code
, op0
, op1
, mode
, 0,
5513 normalizep
, target_mode
);
5518 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
5519 tem
, const0_rtx
, GET_MODE (tem
), 0);
5521 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
5522 trueval
, tem
, GET_MODE (tem
), 0);
5525 delete_insns_since (last
);
5532 /* The remaining tricks only apply to integer comparisons. */
5534 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5537 /* If this is an equality comparison of integers, we can try to exclusive-or
5538 (or subtract) the two operands and use a recursive call to try the
5539 comparison with zero. Don't do any of these cases if branches are
5542 if ((code
== EQ
|| code
== NE
) && op1
!= const0_rtx
)
5544 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
5548 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
5551 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
5552 mode
, unsignedp
, normalizep
);
5556 delete_insns_since (last
);
5559 /* For integer comparisons, try the reverse comparison. However, for
5560 small X and if we'd have anyway to extend, implementing "X != 0"
5561 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5562 rcode
= reverse_condition (code
);
5563 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5564 && ! (optab_handler (cstore_optab
, mode
) == CODE_FOR_nothing
5566 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5567 && op1
== const0_rtx
))
5569 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5570 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5572 /* Again, for the reverse comparison, use either an addition or a XOR. */
5574 && rtx_cost (GEN_INT (normalizep
), PLUS
, 1,
5575 optimize_insn_for_speed_p ()) == 0)
5577 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5578 STORE_FLAG_VALUE
, target_mode
);
5580 tem
= expand_binop (target_mode
, add_optab
, tem
,
5581 gen_int_mode (normalizep
, target_mode
),
5582 target
, 0, OPTAB_WIDEN
);
5585 && rtx_cost (trueval
, XOR
, 1,
5586 optimize_insn_for_speed_p ()) == 0)
5588 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5589 normalizep
, target_mode
);
5591 tem
= expand_binop (target_mode
, xor_optab
, tem
, trueval
, target
,
5592 INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5597 delete_insns_since (last
);
5600 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5601 the constant zero. Reject all other comparisons at this point. Only
5602 do LE and GT if branches are expensive since they are expensive on
5603 2-operand machines. */
5605 if (op1
!= const0_rtx
5606 || (code
!= EQ
&& code
!= NE
5607 && (BRANCH_COST (optimize_insn_for_speed_p (),
5608 false) <= 1 || (code
!= LE
&& code
!= GT
))))
5611 /* Try to put the result of the comparison in the sign bit. Assume we can't
5612 do the necessary operation below. */
5616 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5617 the sign bit set. */
5621 /* This is destructive, so SUBTARGET can't be OP0. */
5622 if (rtx_equal_p (subtarget
, op0
))
5625 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
5628 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
5632 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5633 number of bits in the mode of OP0, minus one. */
5637 if (rtx_equal_p (subtarget
, op0
))
5640 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5641 GET_MODE_BITSIZE (mode
) - 1,
5643 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5647 if (code
== EQ
|| code
== NE
)
5649 /* For EQ or NE, one way to do the comparison is to apply an operation
5650 that converts the operand into a positive number if it is nonzero
5651 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5652 for NE we negate. This puts the result in the sign bit. Then we
5653 normalize with a shift, if needed.
5655 Two operations that can do the above actions are ABS and FFS, so try
5656 them. If that doesn't work, and MODE is smaller than a full word,
5657 we can use zero-extension to the wider mode (an unsigned conversion)
5658 as the operation. */
5660 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5661 that is compensated by the subsequent overflow when subtracting
5664 if (optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)
5665 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5666 else if (optab_handler (ffs_optab
, mode
) != CODE_FOR_nothing
)
5667 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5668 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5670 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5677 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5680 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5683 /* If we couldn't do it that way, for NE we can "or" the two's complement
5684 of the value with itself. For EQ, we take the one's complement of
5685 that "or", which is an extra insn, so we only handle EQ if branches
5690 || BRANCH_COST (optimize_insn_for_speed_p (),
5693 if (rtx_equal_p (subtarget
, op0
))
5696 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5697 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5700 if (tem
&& code
== EQ
)
5701 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5705 if (tem
&& normalizep
)
5706 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
5707 GET_MODE_BITSIZE (mode
) - 1,
5708 subtarget
, normalizep
== 1);
5714 else if (GET_MODE (tem
) != target_mode
)
5716 convert_move (target
, tem
, 0);
5719 else if (!subtarget
)
5721 emit_move_insn (target
, tem
);
5726 delete_insns_since (last
);
5731 /* Like emit_store_flag, but always succeeds. */
5734 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5735 enum machine_mode mode
, int unsignedp
, int normalizep
)
5738 rtx_code_label
*label
;
5739 rtx trueval
, falseval
;
5741 /* First see if emit_store_flag can do the job. */
5742 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
5747 target
= gen_reg_rtx (word_mode
);
5749 /* If this failed, we have to do this with set/compare/jump/set code.
5750 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5751 trueval
= normalizep
? GEN_INT (normalizep
) : const1_rtx
;
5753 && GET_MODE_CLASS (mode
) == MODE_INT
5756 && op1
== const0_rtx
)
5758 label
= gen_label_rtx ();
5759 do_compare_rtx_and_jump (target
, const0_rtx
, EQ
, unsignedp
,
5760 mode
, NULL_RTX
, NULL_RTX
, label
, -1);
5761 emit_move_insn (target
, trueval
);
5767 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
5768 target
= gen_reg_rtx (GET_MODE (target
));
5770 /* Jump in the right direction if the target cannot implement CODE
5771 but can jump on its reverse condition. */
5772 falseval
= const0_rtx
;
5773 if (! can_compare_p (code
, mode
, ccp_jump
)
5774 && (! FLOAT_MODE_P (mode
)
5775 || code
== ORDERED
|| code
== UNORDERED
5776 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5777 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5779 enum rtx_code rcode
;
5780 if (FLOAT_MODE_P (mode
))
5781 rcode
= reverse_condition_maybe_unordered (code
);
5783 rcode
= reverse_condition (code
);
5785 /* Canonicalize to UNORDERED for the libcall. */
5786 if (can_compare_p (rcode
, mode
, ccp_jump
)
5787 || (code
== ORDERED
&& ! can_compare_p (ORDERED
, mode
, ccp_jump
)))
5790 trueval
= const0_rtx
;
5795 emit_move_insn (target
, trueval
);
5796 label
= gen_label_rtx ();
5797 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
5798 NULL_RTX
, label
, -1);
5800 emit_move_insn (target
, falseval
);
5806 /* Perform possibly multi-word comparison and conditional jump to LABEL
5807 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5808 now a thin wrapper around do_compare_rtx_and_jump. */
5811 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, enum machine_mode mode
,
5812 rtx_code_label
*label
)
5814 int unsignedp
= (op
== LTU
|| op
== LEU
|| op
== GTU
|| op
== GEU
);
5815 do_compare_rtx_and_jump (arg1
, arg2
, op
, unsignedp
, mode
,
5816 NULL_RTX
, NULL_RTX
, label
, -1);