1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
28 #include "diagnostic-core.h"
34 #include "insn-config.h"
38 #include "langhooks.h"
43 struct target_expmed default_target_expmed
;
45 struct target_expmed
*this_target_expmed
= &default_target_expmed
;
48 static void store_fixed_bit_field (rtx
, unsigned HOST_WIDE_INT
,
49 unsigned HOST_WIDE_INT
,
50 unsigned HOST_WIDE_INT
, rtx
);
51 static void store_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
, rtx
);
53 static rtx
extract_fixed_bit_field (enum machine_mode
, rtx
,
54 unsigned HOST_WIDE_INT
,
55 unsigned HOST_WIDE_INT
,
56 unsigned HOST_WIDE_INT
, rtx
, int);
57 static rtx
mask_rtx (enum machine_mode
, int, int, int);
58 static rtx
lshift_value (enum machine_mode
, rtx
, int, int);
59 static rtx
extract_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
60 unsigned HOST_WIDE_INT
, int);
61 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, enum machine_mode
, rtx
);
62 static rtx
expand_smod_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
63 static rtx
expand_sdiv_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
65 /* Test whether a value is zero of a power of two. */
66 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
68 #ifndef SLOW_UNALIGNED_ACCESS
69 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
73 /* Reduce conditional compilation elsewhere. */
76 #define CODE_FOR_insv CODE_FOR_nothing
77 #define gen_insv(a,b,c,d) NULL_RTX
81 #define CODE_FOR_extv CODE_FOR_nothing
82 #define gen_extv(a,b,c,d) NULL_RTX
86 #define CODE_FOR_extzv CODE_FOR_nothing
87 #define gen_extzv(a,b,c,d) NULL_RTX
95 struct rtx_def reg
; rtunion reg_fld
[2];
96 struct rtx_def plus
; rtunion plus_fld1
;
98 struct rtx_def mult
; rtunion mult_fld1
;
99 struct rtx_def sdiv
; rtunion sdiv_fld1
;
100 struct rtx_def udiv
; rtunion udiv_fld1
;
102 struct rtx_def sdiv_32
; rtunion sdiv_32_fld1
;
103 struct rtx_def smod_32
; rtunion smod_32_fld1
;
104 struct rtx_def wide_mult
; rtunion wide_mult_fld1
;
105 struct rtx_def wide_lshr
; rtunion wide_lshr_fld1
;
106 struct rtx_def wide_trunc
;
107 struct rtx_def shift
; rtunion shift_fld1
;
108 struct rtx_def shift_mult
; rtunion shift_mult_fld1
;
109 struct rtx_def shift_add
; rtunion shift_add_fld1
;
110 struct rtx_def shift_sub0
; rtunion shift_sub0_fld1
;
111 struct rtx_def shift_sub1
; rtunion shift_sub1_fld1
;
114 rtx pow2
[MAX_BITS_PER_WORD
];
115 rtx cint
[MAX_BITS_PER_WORD
];
117 enum machine_mode mode
, wider_mode
;
121 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
123 pow2
[m
] = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
124 cint
[m
] = GEN_INT (m
);
126 memset (&all
, 0, sizeof all
);
128 PUT_CODE (&all
.reg
, REG
);
129 /* Avoid using hard regs in ways which may be unsupported. */
130 SET_REGNO (&all
.reg
, LAST_VIRTUAL_REGISTER
+ 1);
132 PUT_CODE (&all
.plus
, PLUS
);
133 XEXP (&all
.plus
, 0) = &all
.reg
;
134 XEXP (&all
.plus
, 1) = &all
.reg
;
136 PUT_CODE (&all
.neg
, NEG
);
137 XEXP (&all
.neg
, 0) = &all
.reg
;
139 PUT_CODE (&all
.mult
, MULT
);
140 XEXP (&all
.mult
, 0) = &all
.reg
;
141 XEXP (&all
.mult
, 1) = &all
.reg
;
143 PUT_CODE (&all
.sdiv
, DIV
);
144 XEXP (&all
.sdiv
, 0) = &all
.reg
;
145 XEXP (&all
.sdiv
, 1) = &all
.reg
;
147 PUT_CODE (&all
.udiv
, UDIV
);
148 XEXP (&all
.udiv
, 0) = &all
.reg
;
149 XEXP (&all
.udiv
, 1) = &all
.reg
;
151 PUT_CODE (&all
.sdiv_32
, DIV
);
152 XEXP (&all
.sdiv_32
, 0) = &all
.reg
;
153 XEXP (&all
.sdiv_32
, 1) = 32 < MAX_BITS_PER_WORD
? cint
[32] : GEN_INT (32);
155 PUT_CODE (&all
.smod_32
, MOD
);
156 XEXP (&all
.smod_32
, 0) = &all
.reg
;
157 XEXP (&all
.smod_32
, 1) = XEXP (&all
.sdiv_32
, 1);
159 PUT_CODE (&all
.zext
, ZERO_EXTEND
);
160 XEXP (&all
.zext
, 0) = &all
.reg
;
162 PUT_CODE (&all
.wide_mult
, MULT
);
163 XEXP (&all
.wide_mult
, 0) = &all
.zext
;
164 XEXP (&all
.wide_mult
, 1) = &all
.zext
;
166 PUT_CODE (&all
.wide_lshr
, LSHIFTRT
);
167 XEXP (&all
.wide_lshr
, 0) = &all
.wide_mult
;
169 PUT_CODE (&all
.wide_trunc
, TRUNCATE
);
170 XEXP (&all
.wide_trunc
, 0) = &all
.wide_lshr
;
172 PUT_CODE (&all
.shift
, ASHIFT
);
173 XEXP (&all
.shift
, 0) = &all
.reg
;
175 PUT_CODE (&all
.shift_mult
, MULT
);
176 XEXP (&all
.shift_mult
, 0) = &all
.reg
;
178 PUT_CODE (&all
.shift_add
, PLUS
);
179 XEXP (&all
.shift_add
, 0) = &all
.shift_mult
;
180 XEXP (&all
.shift_add
, 1) = &all
.reg
;
182 PUT_CODE (&all
.shift_sub0
, MINUS
);
183 XEXP (&all
.shift_sub0
, 0) = &all
.shift_mult
;
184 XEXP (&all
.shift_sub0
, 1) = &all
.reg
;
186 PUT_CODE (&all
.shift_sub1
, MINUS
);
187 XEXP (&all
.shift_sub1
, 0) = &all
.reg
;
188 XEXP (&all
.shift_sub1
, 1) = &all
.shift_mult
;
190 for (speed
= 0; speed
< 2; speed
++)
192 crtl
->maybe_hot_insn_p
= speed
;
193 zero_cost
[speed
] = rtx_cost (const0_rtx
, SET
, speed
);
195 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
197 mode
= GET_MODE_WIDER_MODE (mode
))
199 PUT_MODE (&all
.reg
, mode
);
200 PUT_MODE (&all
.plus
, mode
);
201 PUT_MODE (&all
.neg
, mode
);
202 PUT_MODE (&all
.mult
, mode
);
203 PUT_MODE (&all
.sdiv
, mode
);
204 PUT_MODE (&all
.udiv
, mode
);
205 PUT_MODE (&all
.sdiv_32
, mode
);
206 PUT_MODE (&all
.smod_32
, mode
);
207 PUT_MODE (&all
.wide_trunc
, mode
);
208 PUT_MODE (&all
.shift
, mode
);
209 PUT_MODE (&all
.shift_mult
, mode
);
210 PUT_MODE (&all
.shift_add
, mode
);
211 PUT_MODE (&all
.shift_sub0
, mode
);
212 PUT_MODE (&all
.shift_sub1
, mode
);
214 add_cost
[speed
][mode
] = rtx_cost (&all
.plus
, SET
, speed
);
215 neg_cost
[speed
][mode
] = rtx_cost (&all
.neg
, SET
, speed
);
216 mul_cost
[speed
][mode
] = rtx_cost (&all
.mult
, SET
, speed
);
217 sdiv_cost
[speed
][mode
] = rtx_cost (&all
.sdiv
, SET
, speed
);
218 udiv_cost
[speed
][mode
] = rtx_cost (&all
.udiv
, SET
, speed
);
220 sdiv_pow2_cheap
[speed
][mode
] = (rtx_cost (&all
.sdiv_32
, SET
, speed
)
221 <= 2 * add_cost
[speed
][mode
]);
222 smod_pow2_cheap
[speed
][mode
] = (rtx_cost (&all
.smod_32
, SET
, speed
)
223 <= 4 * add_cost
[speed
][mode
]);
225 wider_mode
= GET_MODE_WIDER_MODE (mode
);
226 if (wider_mode
!= VOIDmode
)
228 PUT_MODE (&all
.zext
, wider_mode
);
229 PUT_MODE (&all
.wide_mult
, wider_mode
);
230 PUT_MODE (&all
.wide_lshr
, wider_mode
);
231 XEXP (&all
.wide_lshr
, 1) = GEN_INT (GET_MODE_BITSIZE (mode
));
233 mul_widen_cost
[speed
][wider_mode
]
234 = rtx_cost (&all
.wide_mult
, SET
, speed
);
235 mul_highpart_cost
[speed
][mode
]
236 = rtx_cost (&all
.wide_trunc
, SET
, speed
);
239 shift_cost
[speed
][mode
][0] = 0;
240 shiftadd_cost
[speed
][mode
][0] = shiftsub0_cost
[speed
][mode
][0]
241 = shiftsub1_cost
[speed
][mode
][0] = add_cost
[speed
][mode
];
243 n
= MIN (MAX_BITS_PER_WORD
, GET_MODE_BITSIZE (mode
));
244 for (m
= 1; m
< n
; m
++)
246 XEXP (&all
.shift
, 1) = cint
[m
];
247 XEXP (&all
.shift_mult
, 1) = pow2
[m
];
249 shift_cost
[speed
][mode
][m
] = rtx_cost (&all
.shift
, SET
, speed
);
250 shiftadd_cost
[speed
][mode
][m
] = rtx_cost (&all
.shift_add
, SET
, speed
);
251 shiftsub0_cost
[speed
][mode
][m
] = rtx_cost (&all
.shift_sub0
, SET
, speed
);
252 shiftsub1_cost
[speed
][mode
][m
] = rtx_cost (&all
.shift_sub1
, SET
, speed
);
257 memset (alg_hash
, 0, sizeof (alg_hash
));
259 alg_hash_used_p
= true;
260 default_rtl_profile ();
263 /* Return an rtx representing minus the value of X.
264 MODE is the intended mode of the result,
265 useful if X is a CONST_INT. */
268 negate_rtx (enum machine_mode mode
, rtx x
)
270 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
273 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
278 /* Report on the availability of insv/extv/extzv and the desired mode
279 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
280 is false; else the mode of the specified operand. If OPNO is -1,
281 all the caller cares about is whether the insn is available. */
283 mode_for_extraction (enum extraction_pattern pattern
, int opno
)
285 const struct insn_data_d
*data
;
292 data
= &insn_data
[CODE_FOR_insv
];
295 return MAX_MACHINE_MODE
;
300 data
= &insn_data
[CODE_FOR_extv
];
303 return MAX_MACHINE_MODE
;
308 data
= &insn_data
[CODE_FOR_extzv
];
311 return MAX_MACHINE_MODE
;
320 /* Everyone who uses this function used to follow it with
321 if (result == VOIDmode) result = word_mode; */
322 if (data
->operand
[opno
].mode
== VOIDmode
)
324 return data
->operand
[opno
].mode
;
327 /* Return true if X, of mode MODE, matches the predicate for operand
328 OPNO of instruction ICODE. Allow volatile memories, regardless of
329 the ambient volatile_ok setting. */
332 check_predicate_volatile_ok (enum insn_code icode
, int opno
,
333 rtx x
, enum machine_mode mode
)
335 bool save_volatile_ok
, result
;
337 save_volatile_ok
= volatile_ok
;
338 result
= insn_data
[(int) icode
].operand
[opno
].predicate (x
, mode
);
339 volatile_ok
= save_volatile_ok
;
343 /* A subroutine of store_bit_field, with the same arguments. Return true
344 if the operation could be implemented.
346 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
347 no other way of implementing the operation. If FALLBACK_P is false,
348 return false instead. */
351 store_bit_field_1 (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
352 unsigned HOST_WIDE_INT bitnum
, enum machine_mode fieldmode
,
353 rtx value
, bool fallback_p
)
356 = (MEM_P (str_rtx
)) ? BITS_PER_UNIT
: BITS_PER_WORD
;
357 unsigned HOST_WIDE_INT offset
, bitpos
;
362 enum machine_mode op_mode
= mode_for_extraction (EP_insv
, 3);
364 while (GET_CODE (op0
) == SUBREG
)
366 /* The following line once was done only if WORDS_BIG_ENDIAN,
367 but I think that is a mistake. WORDS_BIG_ENDIAN is
368 meaningful at a much higher level; when structures are copied
369 between memory and regs, the higher-numbered regs
370 always get higher addresses. */
371 int inner_mode_size
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)));
372 int outer_mode_size
= GET_MODE_SIZE (GET_MODE (op0
));
376 /* Paradoxical subregs need special handling on big endian machines. */
377 if (SUBREG_BYTE (op0
) == 0 && inner_mode_size
< outer_mode_size
)
379 int difference
= inner_mode_size
- outer_mode_size
;
381 if (WORDS_BIG_ENDIAN
)
382 byte_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
383 if (BYTES_BIG_ENDIAN
)
384 byte_offset
+= difference
% UNITS_PER_WORD
;
387 byte_offset
= SUBREG_BYTE (op0
);
389 bitnum
+= byte_offset
* BITS_PER_UNIT
;
390 op0
= SUBREG_REG (op0
);
393 /* No action is needed if the target is a register and if the field
394 lies completely outside that register. This can occur if the source
395 code contains an out-of-bounds access to a small array. */
396 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
399 /* Use vec_set patterns for inserting parts of vectors whenever
401 if (VECTOR_MODE_P (GET_MODE (op0
))
403 && optab_handler (vec_set_optab
, GET_MODE (op0
)) != CODE_FOR_nothing
404 && fieldmode
== GET_MODE_INNER (GET_MODE (op0
))
405 && bitsize
== GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
406 && !(bitnum
% GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
408 enum machine_mode outermode
= GET_MODE (op0
);
409 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
410 int icode
= (int) optab_handler (vec_set_optab
, outermode
);
411 int pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
412 rtx rtxpos
= GEN_INT (pos
);
416 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
417 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
418 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
422 if (! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
))
423 src
= copy_to_mode_reg (mode1
, src
);
425 if (! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
426 rtxpos
= copy_to_mode_reg (mode1
, rtxpos
);
428 /* We could handle this, but we should always be called with a pseudo
429 for our targets and all insns should take them as outputs. */
430 gcc_assert ((*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
)
431 && (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
)
432 && (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
));
433 pat
= GEN_FCN (icode
) (dest
, src
, rtxpos
);
444 /* If the target is a register, overwriting the entire object, or storing
445 a full-word or multi-word field can be done with just a SUBREG.
447 If the target is memory, storing any naturally aligned field can be
448 done with a simple store. For targets that support fast unaligned
449 memory, any naturally sized, unit aligned field can be done directly. */
451 offset
= bitnum
/ unit
;
452 bitpos
= bitnum
% unit
;
453 byte_offset
= (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
454 + (offset
* UNITS_PER_WORD
);
457 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
459 ? ((GET_MODE_SIZE (fieldmode
) >= UNITS_PER_WORD
460 || GET_MODE_SIZE (GET_MODE (op0
)) == GET_MODE_SIZE (fieldmode
))
461 && byte_offset
% GET_MODE_SIZE (fieldmode
) == 0)
462 : (! SLOW_UNALIGNED_ACCESS (fieldmode
, MEM_ALIGN (op0
))
463 || (offset
* BITS_PER_UNIT
% bitsize
== 0
464 && MEM_ALIGN (op0
) % GET_MODE_BITSIZE (fieldmode
) == 0))))
467 op0
= adjust_address (op0
, fieldmode
, offset
);
468 else if (GET_MODE (op0
) != fieldmode
)
469 op0
= simplify_gen_subreg (fieldmode
, op0
, GET_MODE (op0
),
471 emit_move_insn (op0
, value
);
475 /* Make sure we are playing with integral modes. Pun with subregs
476 if we aren't. This must come after the entire register case above,
477 since that case is valid for any mode. The following cases are only
478 valid for integral modes. */
480 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
481 if (imode
!= GET_MODE (op0
))
484 op0
= adjust_address (op0
, imode
, 0);
487 gcc_assert (imode
!= BLKmode
);
488 op0
= gen_lowpart (imode
, op0
);
493 /* We may be accessing data outside the field, which means
494 we can alias adjacent data. */
497 op0
= shallow_copy_rtx (op0
);
498 set_mem_alias_set (op0
, 0);
499 set_mem_expr (op0
, 0);
502 /* If OP0 is a register, BITPOS must count within a word.
503 But as we have it, it counts within whatever size OP0 now has.
504 On a bigendian machine, these are not the same, so convert. */
507 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
508 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
510 /* Storing an lsb-aligned field in a register
511 can be done with a movestrict instruction. */
514 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0)
515 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
516 && optab_handler (movstrict_optab
, fieldmode
) != CODE_FOR_nothing
)
518 int icode
= optab_handler (movstrict_optab
, fieldmode
);
520 rtx start
= get_last_insn ();
523 /* Get appropriate low part of the value being stored. */
524 if (CONST_INT_P (value
) || REG_P (value
))
525 value
= gen_lowpart (fieldmode
, value
);
526 else if (!(GET_CODE (value
) == SYMBOL_REF
527 || GET_CODE (value
) == LABEL_REF
528 || GET_CODE (value
) == CONST
))
529 value
= convert_to_mode (fieldmode
, value
, 0);
531 if (! (*insn_data
[icode
].operand
[1].predicate
) (value
, fieldmode
))
532 value
= copy_to_mode_reg (fieldmode
, value
);
534 if (GET_CODE (op0
) == SUBREG
)
536 /* Else we've got some float mode source being extracted into
537 a different float mode destination -- this combination of
538 subregs results in Severe Tire Damage. */
539 gcc_assert (GET_MODE (SUBREG_REG (op0
)) == fieldmode
540 || GET_MODE_CLASS (fieldmode
) == MODE_INT
541 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
);
542 arg0
= SUBREG_REG (op0
);
545 insn
= (GEN_FCN (icode
)
546 (gen_rtx_SUBREG (fieldmode
, arg0
,
547 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
548 + (offset
* UNITS_PER_WORD
)),
555 delete_insns_since (start
);
558 /* Handle fields bigger than a word. */
560 if (bitsize
> BITS_PER_WORD
)
562 /* Here we transfer the words of the field
563 in the order least significant first.
564 This is because the most significant word is the one which may
566 However, only do that if the value is not BLKmode. */
568 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
569 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
573 /* This is the mode we must force value to, so that there will be enough
574 subwords to extract. Note that fieldmode will often (always?) be
575 VOIDmode, because that is what store_field uses to indicate that this
576 is a bit field, but passing VOIDmode to operand_subword_force
578 fieldmode
= GET_MODE (value
);
579 if (fieldmode
== VOIDmode
)
580 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
582 last
= get_last_insn ();
583 for (i
= 0; i
< nwords
; i
++)
585 /* If I is 0, use the low-order word in both field and target;
586 if I is 1, use the next to lowest word; and so on. */
587 unsigned int wordnum
= (backwards
? nwords
- i
- 1 : i
);
588 unsigned int bit_offset
= (backwards
589 ? MAX ((int) bitsize
- ((int) i
+ 1)
592 : (int) i
* BITS_PER_WORD
);
593 rtx value_word
= operand_subword_force (value
, wordnum
, fieldmode
);
595 if (!store_bit_field_1 (op0
, MIN (BITS_PER_WORD
,
596 bitsize
- i
* BITS_PER_WORD
),
597 bitnum
+ bit_offset
, word_mode
,
598 value_word
, fallback_p
))
600 delete_insns_since (last
);
607 /* From here on we can assume that the field to be stored in is
608 a full-word (whatever type that is), since it is shorter than a word. */
610 /* OFFSET is the number of words or bytes (UNIT says which)
611 from STR_RTX to the first word or byte containing part of the field. */
616 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
620 /* Since this is a destination (lvalue), we can't copy
621 it to a pseudo. We can remove a SUBREG that does not
622 change the size of the operand. Such a SUBREG may
623 have been added above. */
624 gcc_assert (GET_CODE (op0
) == SUBREG
625 && (GET_MODE_SIZE (GET_MODE (op0
))
626 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)))));
627 op0
= SUBREG_REG (op0
);
629 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
630 op0
, (offset
* UNITS_PER_WORD
));
635 /* If VALUE has a floating-point or complex mode, access it as an
636 integer of the corresponding size. This can occur on a machine
637 with 64 bit registers that uses SFmode for float. It can also
638 occur for unaligned float or complex fields. */
640 if (GET_MODE (value
) != VOIDmode
641 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_INT
642 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_PARTIAL_INT
)
644 value
= gen_reg_rtx (int_mode_for_mode (GET_MODE (value
)));
645 emit_move_insn (gen_lowpart (GET_MODE (orig_value
), value
), orig_value
);
648 /* Now OFFSET is nonzero only if OP0 is memory
649 and is therefore always measured in bytes. */
652 && GET_MODE (value
) != BLKmode
654 && GET_MODE_BITSIZE (op_mode
) >= bitsize
655 && ! ((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
656 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (op_mode
)))
657 && insn_data
[CODE_FOR_insv
].operand
[1].predicate (GEN_INT (bitsize
),
659 && check_predicate_volatile_ok (CODE_FOR_insv
, 0, op0
, VOIDmode
))
661 int xbitpos
= bitpos
;
664 rtx last
= get_last_insn ();
666 bool copy_back
= false;
668 /* Add OFFSET into OP0's address. */
670 xop0
= adjust_address (xop0
, byte_mode
, offset
);
672 /* If xop0 is a register, we need it in OP_MODE
673 to make it acceptable to the format of insv. */
674 if (GET_CODE (xop0
) == SUBREG
)
675 /* We can't just change the mode, because this might clobber op0,
676 and we will need the original value of op0 if insv fails. */
677 xop0
= gen_rtx_SUBREG (op_mode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
678 if (REG_P (xop0
) && GET_MODE (xop0
) != op_mode
)
679 xop0
= gen_lowpart_SUBREG (op_mode
, xop0
);
681 /* If the destination is a paradoxical subreg such that we need a
682 truncate to the inner mode, perform the insertion on a temporary and
683 truncate the result to the original destination. Note that we can't
684 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
685 X) 0)) is (reg:N X). */
686 if (GET_CODE (xop0
) == SUBREG
687 && REG_P (SUBREG_REG (xop0
))
688 && (!TRULY_NOOP_TRUNCATION
689 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (xop0
))),
690 GET_MODE_BITSIZE (op_mode
))))
692 rtx tem
= gen_reg_rtx (op_mode
);
693 emit_move_insn (tem
, xop0
);
698 /* On big-endian machines, we count bits from the most significant.
699 If the bit field insn does not, we must invert. */
701 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
702 xbitpos
= unit
- bitsize
- xbitpos
;
704 /* We have been counting XBITPOS within UNIT.
705 Count instead within the size of the register. */
706 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
707 xbitpos
+= GET_MODE_BITSIZE (op_mode
) - unit
;
709 unit
= GET_MODE_BITSIZE (op_mode
);
711 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
713 if (GET_MODE (value
) != op_mode
)
715 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
717 /* Optimization: Don't bother really extending VALUE
718 if it has all the bits we will actually use. However,
719 if we must narrow it, be sure we do it correctly. */
721 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (op_mode
))
725 tmp
= simplify_subreg (op_mode
, value1
, GET_MODE (value
), 0);
727 tmp
= simplify_gen_subreg (op_mode
,
728 force_reg (GET_MODE (value
),
730 GET_MODE (value
), 0);
734 value1
= gen_lowpart (op_mode
, value1
);
736 else if (CONST_INT_P (value
))
737 value1
= gen_int_mode (INTVAL (value
), op_mode
);
739 /* Parse phase is supposed to make VALUE's data type
740 match that of the component reference, which is a type
741 at least as wide as the field; so VALUE should have
742 a mode that corresponds to that type. */
743 gcc_assert (CONSTANT_P (value
));
746 /* If this machine's insv insists on a register,
747 get VALUE1 into a register. */
748 if (! ((*insn_data
[(int) CODE_FOR_insv
].operand
[3].predicate
)
750 value1
= force_reg (op_mode
, value1
);
752 pat
= gen_insv (xop0
, GEN_INT (bitsize
), GEN_INT (xbitpos
), value1
);
758 convert_move (op0
, xop0
, true);
761 delete_insns_since (last
);
764 /* If OP0 is a memory, try copying it to a register and seeing if a
765 cheap register alternative is available. */
766 if (HAVE_insv
&& MEM_P (op0
))
768 enum machine_mode bestmode
;
770 /* Get the mode to use for inserting into this field. If OP0 is
771 BLKmode, get the smallest mode consistent with the alignment. If
772 OP0 is a non-BLKmode object that is no wider than OP_MODE, use its
773 mode. Otherwise, use the smallest mode containing the field. */
775 if (GET_MODE (op0
) == BLKmode
776 || (op_mode
!= MAX_MACHINE_MODE
777 && GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (op_mode
)))
778 bestmode
= get_best_mode (bitsize
, bitnum
, MEM_ALIGN (op0
),
779 (op_mode
== MAX_MACHINE_MODE
780 ? VOIDmode
: op_mode
),
781 MEM_VOLATILE_P (op0
));
783 bestmode
= GET_MODE (op0
);
785 if (bestmode
!= VOIDmode
786 && GET_MODE_SIZE (bestmode
) >= GET_MODE_SIZE (fieldmode
)
787 && !(SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (op0
))
788 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (op0
)))
790 rtx last
, tempreg
, xop0
;
791 unsigned HOST_WIDE_INT xoffset
, xbitpos
;
793 last
= get_last_insn ();
795 /* Adjust address to point to the containing unit of
796 that mode. Compute the offset as a multiple of this unit,
797 counting in bytes. */
798 unit
= GET_MODE_BITSIZE (bestmode
);
799 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
800 xbitpos
= bitnum
% unit
;
801 xop0
= adjust_address (op0
, bestmode
, xoffset
);
803 /* Fetch that unit, store the bitfield in it, then store
805 tempreg
= copy_to_reg (xop0
);
806 if (store_bit_field_1 (tempreg
, bitsize
, xbitpos
,
807 fieldmode
, orig_value
, false))
809 emit_move_insn (xop0
, tempreg
);
812 delete_insns_since (last
);
819 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
823 /* Generate code to store value from rtx VALUE
824 into a bit-field within structure STR_RTX
825 containing BITSIZE bits starting at bit BITNUM.
826 FIELDMODE is the machine-mode of the FIELD_DECL node for this field. */
829 store_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
830 unsigned HOST_WIDE_INT bitnum
, enum machine_mode fieldmode
,
833 if (!store_bit_field_1 (str_rtx
, bitsize
, bitnum
, fieldmode
, value
, true))
837 /* Use shifts and boolean operations to store VALUE
838 into a bit field of width BITSIZE
839 in a memory location specified by OP0 except offset by OFFSET bytes.
840 (OFFSET must be 0 if OP0 is a register.)
841 The field starts at position BITPOS within the byte.
842 (If OP0 is a register, it may be a full word or a narrower mode,
843 but BITPOS still counts within a full word,
844 which is significant on bigendian machines.) */
847 store_fixed_bit_field (rtx op0
, unsigned HOST_WIDE_INT offset
,
848 unsigned HOST_WIDE_INT bitsize
,
849 unsigned HOST_WIDE_INT bitpos
, rtx value
)
851 enum machine_mode mode
;
852 unsigned int total_bits
= BITS_PER_WORD
;
857 /* There is a case not handled here:
858 a structure with a known alignment of just a halfword
859 and a field split across two aligned halfwords within the structure.
860 Or likewise a structure with a known alignment of just a byte
861 and a field split across two bytes.
862 Such cases are not supposed to be able to occur. */
864 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
866 gcc_assert (!offset
);
867 /* Special treatment for a bit field split across two registers. */
868 if (bitsize
+ bitpos
> BITS_PER_WORD
)
870 store_split_bit_field (op0
, bitsize
, bitpos
, value
);
876 /* Get the proper mode to use for this field. We want a mode that
877 includes the entire field. If such a mode would be larger than
878 a word, we won't be doing the extraction the normal way.
879 We don't want a mode bigger than the destination. */
881 mode
= GET_MODE (op0
);
882 if (GET_MODE_BITSIZE (mode
) == 0
883 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
886 if (MEM_VOLATILE_P (op0
)
887 && GET_MODE_BITSIZE (GET_MODE (op0
)) > 0
888 && flag_strict_volatile_bitfields
> 0)
889 mode
= GET_MODE (op0
);
891 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
892 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
894 if (mode
== VOIDmode
)
896 /* The only way this should occur is if the field spans word
898 store_split_bit_field (op0
, bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
903 total_bits
= GET_MODE_BITSIZE (mode
);
905 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
906 be in the range 0 to total_bits-1, and put any excess bytes in
908 if (bitpos
>= total_bits
)
910 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
911 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
915 /* Get ref to an aligned byte, halfword, or word containing the field.
916 Adjust BITPOS to be position within a word,
917 and OFFSET to be the offset of that word.
918 Then alter OP0 to refer to that word. */
919 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
920 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
921 op0
= adjust_address (op0
, mode
, offset
);
924 mode
= GET_MODE (op0
);
926 /* Now MODE is either some integral mode for a MEM as OP0,
927 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
928 The bit field is contained entirely within OP0.
929 BITPOS is the starting bit number within OP0.
930 (OP0's mode may actually be narrower than MODE.) */
932 if (BYTES_BIG_ENDIAN
)
933 /* BITPOS is the distance between our msb
934 and that of the containing datum.
935 Convert it to the distance from the lsb. */
936 bitpos
= total_bits
- bitsize
- bitpos
;
938 /* Now BITPOS is always the distance between our lsb
941 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
942 we must first convert its mode to MODE. */
944 if (CONST_INT_P (value
))
946 HOST_WIDE_INT v
= INTVAL (value
);
948 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
949 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
953 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
954 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
955 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
958 value
= lshift_value (mode
, value
, bitpos
, bitsize
);
962 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
963 && bitpos
+ bitsize
!= GET_MODE_BITSIZE (mode
));
965 if (GET_MODE (value
) != mode
)
966 value
= convert_to_mode (mode
, value
, 1);
969 value
= expand_binop (mode
, and_optab
, value
,
970 mask_rtx (mode
, 0, bitsize
, 0),
971 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
973 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
974 build_int_cst (NULL_TREE
, bitpos
), NULL_RTX
, 1);
977 /* Now clear the chosen bits in OP0,
978 except that if VALUE is -1 we need not bother. */
979 /* We keep the intermediates in registers to allow CSE to combine
980 consecutive bitfield assignments. */
982 temp
= force_reg (mode
, op0
);
986 temp
= expand_binop (mode
, and_optab
, temp
,
987 mask_rtx (mode
, bitpos
, bitsize
, 1),
988 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
989 temp
= force_reg (mode
, temp
);
992 /* Now logical-or VALUE into OP0, unless it is zero. */
996 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
997 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
998 temp
= force_reg (mode
, temp
);
1003 op0
= copy_rtx (op0
);
1004 emit_move_insn (op0
, temp
);
1008 /* Store a bit field that is split across multiple accessible memory objects.
1010 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1011 BITSIZE is the field width; BITPOS the position of its first bit
1013 VALUE is the value to store.
1015 This does not yet handle fields wider than BITS_PER_WORD. */
1018 store_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1019 unsigned HOST_WIDE_INT bitpos
, rtx value
)
1022 unsigned int bitsdone
= 0;
1024 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1026 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1027 unit
= BITS_PER_WORD
;
1029 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1031 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1032 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1033 that VALUE might be a floating-point constant. */
1034 if (CONSTANT_P (value
) && !CONST_INT_P (value
))
1036 rtx word
= gen_lowpart_common (word_mode
, value
);
1038 if (word
&& (value
!= word
))
1041 value
= gen_lowpart_common (word_mode
,
1042 force_reg (GET_MODE (value
) != VOIDmode
1044 : word_mode
, value
));
1047 while (bitsdone
< bitsize
)
1049 unsigned HOST_WIDE_INT thissize
;
1051 unsigned HOST_WIDE_INT thispos
;
1052 unsigned HOST_WIDE_INT offset
;
1054 offset
= (bitpos
+ bitsdone
) / unit
;
1055 thispos
= (bitpos
+ bitsdone
) % unit
;
1057 /* THISSIZE must not overrun a word boundary. Otherwise,
1058 store_fixed_bit_field will call us again, and we will mutually
1060 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1061 thissize
= MIN (thissize
, unit
- thispos
);
1063 if (BYTES_BIG_ENDIAN
)
1067 /* We must do an endian conversion exactly the same way as it is
1068 done in extract_bit_field, so that the two calls to
1069 extract_fixed_bit_field will have comparable arguments. */
1070 if (!MEM_P (value
) || GET_MODE (value
) == BLKmode
)
1071 total_bits
= BITS_PER_WORD
;
1073 total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
1075 /* Fetch successively less significant portions. */
1076 if (CONST_INT_P (value
))
1077 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1078 >> (bitsize
- bitsdone
- thissize
))
1079 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1081 /* The args are chosen so that the last part includes the
1082 lsb. Give extract_bit_field the value it needs (with
1083 endianness compensation) to fetch the piece we want. */
1084 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
1085 total_bits
- bitsize
+ bitsdone
,
1090 /* Fetch successively more significant portions. */
1091 if (CONST_INT_P (value
))
1092 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1094 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1096 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
1097 bitsdone
, NULL_RTX
, 1);
1100 /* If OP0 is a register, then handle OFFSET here.
1102 When handling multiword bitfields, extract_bit_field may pass
1103 down a word_mode SUBREG of a larger REG for a bitfield that actually
1104 crosses a word boundary. Thus, for a SUBREG, we must find
1105 the current word starting from the base register. */
1106 if (GET_CODE (op0
) == SUBREG
)
1108 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1109 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1110 GET_MODE (SUBREG_REG (op0
)));
1113 else if (REG_P (op0
))
1115 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1121 /* OFFSET is in UNITs, and UNIT is in bits.
1122 store_fixed_bit_field wants offset in bytes. */
1123 store_fixed_bit_field (word
, offset
* unit
/ BITS_PER_UNIT
, thissize
,
1125 bitsdone
+= thissize
;
1129 /* A subroutine of extract_bit_field_1 that converts return value X
1130 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1131 to extract_bit_field. */
1134 convert_extracted_bit_field (rtx x
, enum machine_mode mode
,
1135 enum machine_mode tmode
, bool unsignedp
)
1137 if (GET_MODE (x
) == tmode
|| GET_MODE (x
) == mode
)
1140 /* If the x mode is not a scalar integral, first convert to the
1141 integer mode of that size and then access it as a floating-point
1142 value via a SUBREG. */
1143 if (!SCALAR_INT_MODE_P (tmode
))
1145 enum machine_mode smode
;
1147 smode
= mode_for_size (GET_MODE_BITSIZE (tmode
), MODE_INT
, 0);
1148 x
= convert_to_mode (smode
, x
, unsignedp
);
1149 x
= force_reg (smode
, x
);
1150 return gen_lowpart (tmode
, x
);
1153 return convert_to_mode (tmode
, x
, unsignedp
);
1156 /* A subroutine of extract_bit_field, with the same arguments.
1157 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1158 if we can find no other means of implementing the operation.
1159 if FALLBACK_P is false, return NULL instead. */
1162 extract_bit_field_1 (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1163 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1164 enum machine_mode mode
, enum machine_mode tmode
,
1168 = (MEM_P (str_rtx
)) ? BITS_PER_UNIT
: BITS_PER_WORD
;
1169 unsigned HOST_WIDE_INT offset
, bitpos
;
1171 enum machine_mode int_mode
;
1172 enum machine_mode ext_mode
;
1173 enum machine_mode mode1
;
1174 enum insn_code icode
;
1177 if (tmode
== VOIDmode
)
1180 while (GET_CODE (op0
) == SUBREG
)
1182 bitnum
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1183 op0
= SUBREG_REG (op0
);
1186 /* If we have an out-of-bounds access to a register, just return an
1187 uninitialized register of the required mode. This can occur if the
1188 source code contains an out-of-bounds access to a small array. */
1189 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
1190 return gen_reg_rtx (tmode
);
1193 && mode
== GET_MODE (op0
)
1195 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1197 /* We're trying to extract a full register from itself. */
1201 /* See if we can get a better vector mode before extracting. */
1202 if (VECTOR_MODE_P (GET_MODE (op0
))
1204 && GET_MODE_INNER (GET_MODE (op0
)) != tmode
)
1206 enum machine_mode new_mode
;
1207 int nunits
= GET_MODE_NUNITS (GET_MODE (op0
));
1209 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1210 new_mode
= MIN_MODE_VECTOR_FLOAT
;
1211 else if (GET_MODE_CLASS (tmode
) == MODE_FRACT
)
1212 new_mode
= MIN_MODE_VECTOR_FRACT
;
1213 else if (GET_MODE_CLASS (tmode
) == MODE_UFRACT
)
1214 new_mode
= MIN_MODE_VECTOR_UFRACT
;
1215 else if (GET_MODE_CLASS (tmode
) == MODE_ACCUM
)
1216 new_mode
= MIN_MODE_VECTOR_ACCUM
;
1217 else if (GET_MODE_CLASS (tmode
) == MODE_UACCUM
)
1218 new_mode
= MIN_MODE_VECTOR_UACCUM
;
1220 new_mode
= MIN_MODE_VECTOR_INT
;
1222 for (; new_mode
!= VOIDmode
; new_mode
= GET_MODE_WIDER_MODE (new_mode
))
1223 if (GET_MODE_NUNITS (new_mode
) == nunits
1224 && GET_MODE_SIZE (new_mode
) == GET_MODE_SIZE (GET_MODE (op0
))
1225 && targetm
.vector_mode_supported_p (new_mode
))
1227 if (new_mode
!= VOIDmode
)
1228 op0
= gen_lowpart (new_mode
, op0
);
1231 /* Use vec_extract patterns for extracting parts of vectors whenever
1233 if (VECTOR_MODE_P (GET_MODE (op0
))
1235 && optab_handler (vec_extract_optab
, GET_MODE (op0
)) != CODE_FOR_nothing
1236 && ((bitnum
+ bitsize
- 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
1237 == bitnum
/ GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
1239 enum machine_mode outermode
= GET_MODE (op0
);
1240 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
1241 int icode
= (int) optab_handler (vec_extract_optab
, outermode
);
1242 unsigned HOST_WIDE_INT pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
1243 rtx rtxpos
= GEN_INT (pos
);
1245 rtx dest
= NULL
, pat
, seq
;
1246 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
1247 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
1248 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
1250 if (innermode
== tmode
|| innermode
== mode
)
1254 dest
= gen_reg_rtx (innermode
);
1258 if (! (*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
))
1259 dest
= copy_to_mode_reg (mode0
, dest
);
1261 if (! (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
))
1262 src
= copy_to_mode_reg (mode1
, src
);
1264 if (! (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
))
1265 rtxpos
= copy_to_mode_reg (mode1
, rtxpos
);
1267 /* We could handle this, but we should always be called with a pseudo
1268 for our targets and all insns should take them as outputs. */
1269 gcc_assert ((*insn_data
[icode
].operand
[0].predicate
) (dest
, mode0
)
1270 && (*insn_data
[icode
].operand
[1].predicate
) (src
, mode1
)
1271 && (*insn_data
[icode
].operand
[2].predicate
) (rtxpos
, mode2
));
1273 pat
= GEN_FCN (icode
) (dest
, src
, rtxpos
);
1281 return gen_lowpart (tmode
, dest
);
1286 /* Make sure we are playing with integral modes. Pun with subregs
1289 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1290 if (imode
!= GET_MODE (op0
))
1293 op0
= adjust_address (op0
, imode
, 0);
1294 else if (imode
!= BLKmode
)
1296 op0
= gen_lowpart (imode
, op0
);
1298 /* If we got a SUBREG, force it into a register since we
1299 aren't going to be able to do another SUBREG on it. */
1300 if (GET_CODE (op0
) == SUBREG
)
1301 op0
= force_reg (imode
, op0
);
1303 else if (REG_P (op0
))
1306 imode
= smallest_mode_for_size (GET_MODE_BITSIZE (GET_MODE (op0
)),
1308 reg
= gen_reg_rtx (imode
);
1309 subreg
= gen_lowpart_SUBREG (GET_MODE (op0
), reg
);
1310 emit_move_insn (subreg
, op0
);
1312 bitnum
+= SUBREG_BYTE (subreg
) * BITS_PER_UNIT
;
1316 rtx mem
= assign_stack_temp (GET_MODE (op0
),
1317 GET_MODE_SIZE (GET_MODE (op0
)), 0);
1318 emit_move_insn (mem
, op0
);
1319 op0
= adjust_address (mem
, BLKmode
, 0);
1324 /* We may be accessing data outside the field, which means
1325 we can alias adjacent data. */
1328 op0
= shallow_copy_rtx (op0
);
1329 set_mem_alias_set (op0
, 0);
1330 set_mem_expr (op0
, 0);
1333 /* Extraction of a full-word or multi-word value from a structure
1334 in a register or aligned memory can be done with just a SUBREG.
1335 A subword value in the least significant part of a register
1336 can also be extracted with a SUBREG. For this, we need the
1337 byte offset of the value in op0. */
1339 bitpos
= bitnum
% unit
;
1340 offset
= bitnum
/ unit
;
1341 byte_offset
= bitpos
/ BITS_PER_UNIT
+ offset
* UNITS_PER_WORD
;
1343 /* If OP0 is a register, BITPOS must count within a word.
1344 But as we have it, it counts within whatever size OP0 now has.
1345 On a bigendian machine, these are not the same, so convert. */
1346 if (BYTES_BIG_ENDIAN
1348 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
1349 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1351 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1352 If that's wrong, the solution is to test for it and set TARGET to 0
1355 /* Only scalar integer modes can be converted via subregs. There is an
1356 additional problem for FP modes here in that they can have a precision
1357 which is different from the size. mode_for_size uses precision, but
1358 we want a mode based on the size, so we must avoid calling it for FP
1360 mode1
= (SCALAR_INT_MODE_P (tmode
)
1361 ? mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0)
1364 /* If the bitfield is volatile, we need to make sure the access
1365 remains on a type-aligned boundary. */
1366 if (GET_CODE (op0
) == MEM
1367 && MEM_VOLATILE_P (op0
)
1368 && GET_MODE_BITSIZE (GET_MODE (op0
)) > 0
1369 && flag_strict_volatile_bitfields
> 0)
1370 goto no_subreg_mode_swap
;
1372 if (((bitsize
>= BITS_PER_WORD
&& bitsize
== GET_MODE_BITSIZE (mode
)
1373 && bitpos
% BITS_PER_WORD
== 0)
1374 || (mode1
!= BLKmode
1375 /* ??? The big endian test here is wrong. This is correct
1376 if the value is in a register, and if mode_for_size is not
1377 the same mode as op0. This causes us to get unnecessarily
1378 inefficient code from the Thumb port when -mbig-endian. */
1379 && (BYTES_BIG_ENDIAN
1380 ? bitpos
+ bitsize
== BITS_PER_WORD
1383 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode1
),
1384 GET_MODE_BITSIZE (GET_MODE (op0
)))
1385 && GET_MODE_SIZE (mode1
) != 0
1386 && byte_offset
% GET_MODE_SIZE (mode1
) == 0)
1388 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (op0
))
1389 || (offset
* BITS_PER_UNIT
% bitsize
== 0
1390 && MEM_ALIGN (op0
) % bitsize
== 0)))))
1393 op0
= adjust_address (op0
, mode1
, offset
);
1394 else if (mode1
!= GET_MODE (op0
))
1396 rtx sub
= simplify_gen_subreg (mode1
, op0
, GET_MODE (op0
),
1399 goto no_subreg_mode_swap
;
1403 return convert_to_mode (tmode
, op0
, unsignedp
);
1406 no_subreg_mode_swap
:
1408 /* Handle fields bigger than a word. */
1410 if (bitsize
> BITS_PER_WORD
)
1412 /* Here we transfer the words of the field
1413 in the order least significant first.
1414 This is because the most significant word is the one which may
1415 be less than full. */
1417 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1420 if (target
== 0 || !REG_P (target
))
1421 target
= gen_reg_rtx (mode
);
1423 /* Indicate for flow that the entire target reg is being set. */
1424 emit_clobber (target
);
1426 for (i
= 0; i
< nwords
; i
++)
1428 /* If I is 0, use the low-order word in both field and target;
1429 if I is 1, use the next to lowest word; and so on. */
1430 /* Word number in TARGET to use. */
1431 unsigned int wordnum
1433 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1435 /* Offset from start of field in OP0. */
1436 unsigned int bit_offset
= (WORDS_BIG_ENDIAN
1437 ? MAX (0, ((int) bitsize
- ((int) i
+ 1)
1438 * (int) BITS_PER_WORD
))
1439 : (int) i
* BITS_PER_WORD
);
1440 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1442 = extract_bit_field (op0
, MIN (BITS_PER_WORD
,
1443 bitsize
- i
* BITS_PER_WORD
),
1444 bitnum
+ bit_offset
, 1, target_part
, mode
,
1447 gcc_assert (target_part
);
1449 if (result_part
!= target_part
)
1450 emit_move_insn (target_part
, result_part
);
1455 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1456 need to be zero'd out. */
1457 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1459 unsigned int i
, total_words
;
1461 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1462 for (i
= nwords
; i
< total_words
; i
++)
1464 (operand_subword (target
,
1465 WORDS_BIG_ENDIAN
? total_words
- i
- 1 : i
,
1472 /* Signed bit field: sign-extend with two arithmetic shifts. */
1473 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1474 build_int_cst (NULL_TREE
,
1475 GET_MODE_BITSIZE (mode
) - bitsize
),
1477 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1478 build_int_cst (NULL_TREE
,
1479 GET_MODE_BITSIZE (mode
) - bitsize
),
1483 /* From here on we know the desired field is smaller than a word. */
1485 /* Check if there is a correspondingly-sized integer field, so we can
1486 safely extract it as one size of integer, if necessary; then
1487 truncate or extend to the size that is wanted; then use SUBREGs or
1488 convert_to_mode to get one of the modes we really wanted. */
1490 int_mode
= int_mode_for_mode (tmode
);
1491 if (int_mode
== BLKmode
)
1492 int_mode
= int_mode_for_mode (mode
);
1493 /* Should probably push op0 out to memory and then do a load. */
1494 gcc_assert (int_mode
!= BLKmode
);
1496 /* OFFSET is the number of words or bytes (UNIT says which)
1497 from STR_RTX to the first word or byte containing part of the field. */
1501 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1504 op0
= copy_to_reg (op0
);
1505 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
1506 op0
, (offset
* UNITS_PER_WORD
));
1511 /* Now OFFSET is nonzero only for memory operands. */
1512 ext_mode
= mode_for_extraction (unsignedp
? EP_extzv
: EP_extv
, 0);
1513 icode
= unsignedp
? CODE_FOR_extzv
: CODE_FOR_extv
;
1514 if (ext_mode
!= MAX_MACHINE_MODE
1516 && GET_MODE_BITSIZE (ext_mode
) >= bitsize
1517 /* If op0 is a register, we need it in EXT_MODE to make it
1518 acceptable to the format of ext(z)v. */
1519 && !(GET_CODE (op0
) == SUBREG
&& GET_MODE (op0
) != ext_mode
)
1520 && !((REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1521 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (ext_mode
)))
1522 && check_predicate_volatile_ok (icode
, 1, op0
, GET_MODE (op0
)))
1524 unsigned HOST_WIDE_INT xbitpos
= bitpos
, xoffset
= offset
;
1525 rtx bitsize_rtx
, bitpos_rtx
;
1526 rtx last
= get_last_insn ();
1528 rtx xtarget
= target
;
1529 rtx xspec_target
= target
;
1530 rtx xspec_target_subreg
= 0;
1533 /* If op0 is a register, we need it in EXT_MODE to make it
1534 acceptable to the format of ext(z)v. */
1535 if (REG_P (xop0
) && GET_MODE (xop0
) != ext_mode
)
1536 xop0
= gen_lowpart_SUBREG (ext_mode
, xop0
);
1538 /* Get ref to first byte containing part of the field. */
1539 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1541 /* On big-endian machines, we count bits from the most significant.
1542 If the bit field insn does not, we must invert. */
1543 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1544 xbitpos
= unit
- bitsize
- xbitpos
;
1546 /* Now convert from counting within UNIT to counting in EXT_MODE. */
1547 if (BITS_BIG_ENDIAN
&& !MEM_P (xop0
))
1548 xbitpos
+= GET_MODE_BITSIZE (ext_mode
) - unit
;
1550 unit
= GET_MODE_BITSIZE (ext_mode
);
1553 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1555 if (GET_MODE (xtarget
) != ext_mode
)
1557 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1558 between the mode of the extraction (word_mode) and the target
1559 mode. Instead, create a temporary and use convert_move to set
1562 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (xtarget
)),
1563 GET_MODE_BITSIZE (ext_mode
)))
1565 xtarget
= gen_lowpart (ext_mode
, xtarget
);
1566 if (GET_MODE_SIZE (ext_mode
)
1567 > GET_MODE_SIZE (GET_MODE (xspec_target
)))
1568 xspec_target_subreg
= xtarget
;
1571 xtarget
= gen_reg_rtx (ext_mode
);
1574 /* If this machine's ext(z)v insists on a register target,
1575 make sure we have one. */
1576 if (!insn_data
[(int) icode
].operand
[0].predicate (xtarget
, ext_mode
))
1577 xtarget
= gen_reg_rtx (ext_mode
);
1579 bitsize_rtx
= GEN_INT (bitsize
);
1580 bitpos_rtx
= GEN_INT (xbitpos
);
1583 ? gen_extzv (xtarget
, xop0
, bitsize_rtx
, bitpos_rtx
)
1584 : gen_extv (xtarget
, xop0
, bitsize_rtx
, bitpos_rtx
));
1588 if (xtarget
== xspec_target
)
1590 if (xtarget
== xspec_target_subreg
)
1591 return xspec_target
;
1592 return convert_extracted_bit_field (xtarget
, mode
, tmode
, unsignedp
);
1594 delete_insns_since (last
);
1597 /* If OP0 is a memory, try copying it to a register and seeing if a
1598 cheap register alternative is available. */
1599 if (ext_mode
!= MAX_MACHINE_MODE
&& MEM_P (op0
))
1601 enum machine_mode bestmode
;
1603 /* Get the mode to use for inserting into this field. If
1604 OP0 is BLKmode, get the smallest mode consistent with the
1605 alignment. If OP0 is a non-BLKmode object that is no
1606 wider than EXT_MODE, use its mode. Otherwise, use the
1607 smallest mode containing the field. */
1609 if (GET_MODE (op0
) == BLKmode
1610 || (ext_mode
!= MAX_MACHINE_MODE
1611 && GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (ext_mode
)))
1612 bestmode
= get_best_mode (bitsize
, bitnum
, MEM_ALIGN (op0
),
1613 (ext_mode
== MAX_MACHINE_MODE
1614 ? VOIDmode
: ext_mode
),
1615 MEM_VOLATILE_P (op0
));
1617 bestmode
= GET_MODE (op0
);
1619 if (bestmode
!= VOIDmode
1620 && !(SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (op0
))
1621 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (op0
)))
1623 unsigned HOST_WIDE_INT xoffset
, xbitpos
;
1625 /* Compute the offset as a multiple of this unit,
1626 counting in bytes. */
1627 unit
= GET_MODE_BITSIZE (bestmode
);
1628 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1629 xbitpos
= bitnum
% unit
;
1631 /* Make sure the register is big enough for the whole field. */
1632 if (xoffset
* BITS_PER_UNIT
+ unit
1633 >= offset
* BITS_PER_UNIT
+ bitsize
)
1635 rtx last
, result
, xop0
;
1637 last
= get_last_insn ();
1639 /* Fetch it to a register in that size. */
1640 xop0
= adjust_address (op0
, bestmode
, xoffset
);
1641 xop0
= force_reg (bestmode
, xop0
);
1642 result
= extract_bit_field_1 (xop0
, bitsize
, xbitpos
,
1644 mode
, tmode
, false);
1648 delete_insns_since (last
);
1656 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1657 bitpos
, target
, unsignedp
);
1658 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1661 /* Generate code to extract a byte-field from STR_RTX
1662 containing BITSIZE bits, starting at BITNUM,
1663 and put it in TARGET if possible (if TARGET is nonzero).
1664 Regardless of TARGET, we return the rtx for where the value is placed.
1666 STR_RTX is the structure containing the byte (a REG or MEM).
1667 UNSIGNEDP is nonzero if this is an unsigned bit field.
1668 MODE is the natural mode of the field value once extracted.
1669 TMODE is the mode the caller would like the value to have;
1670 but the value may be returned with type MODE instead.
1672 If a TARGET is specified and we can store in it at no extra cost,
1673 we do so, and return TARGET.
1674 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1675 if they are equally easy. */
1678 extract_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1679 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1680 enum machine_mode mode
, enum machine_mode tmode
)
1682 return extract_bit_field_1 (str_rtx
, bitsize
, bitnum
, unsignedp
,
1683 target
, mode
, tmode
, true);
1686 /* Extract a bit field using shifts and boolean operations
1687 Returns an rtx to represent the value.
1688 OP0 addresses a register (word) or memory (byte).
1689 BITPOS says which bit within the word or byte the bit field starts in.
1690 OFFSET says how many bytes farther the bit field starts;
1691 it is 0 if OP0 is a register.
1692 BITSIZE says how many bits long the bit field is.
1693 (If OP0 is a register, it may be narrower than a full word,
1694 but BITPOS still counts within a full word,
1695 which is significant on bigendian machines.)
1697 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1698 If TARGET is nonzero, attempts to store the value there
1699 and return TARGET, but this is not guaranteed.
1700 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1703 extract_fixed_bit_field (enum machine_mode tmode
, rtx op0
,
1704 unsigned HOST_WIDE_INT offset
,
1705 unsigned HOST_WIDE_INT bitsize
,
1706 unsigned HOST_WIDE_INT bitpos
, rtx target
,
1709 unsigned int total_bits
= BITS_PER_WORD
;
1710 enum machine_mode mode
;
1712 if (GET_CODE (op0
) == SUBREG
|| REG_P (op0
))
1714 /* Special treatment for a bit field split across two registers. */
1715 if (bitsize
+ bitpos
> BITS_PER_WORD
)
1716 return extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
);
1720 /* Get the proper mode to use for this field. We want a mode that
1721 includes the entire field. If such a mode would be larger than
1722 a word, we won't be doing the extraction the normal way. */
1724 if (MEM_VOLATILE_P (op0
)
1725 && flag_strict_volatile_bitfields
> 0)
1727 if (GET_MODE_BITSIZE (GET_MODE (op0
)) > 0)
1728 mode
= GET_MODE (op0
);
1729 else if (target
&& GET_MODE_BITSIZE (GET_MODE (target
)) > 0)
1730 mode
= GET_MODE (target
);
1735 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
1736 MEM_ALIGN (op0
), word_mode
, MEM_VOLATILE_P (op0
));
1738 if (mode
== VOIDmode
)
1739 /* The only way this should occur is if the field spans word
1741 return extract_split_bit_field (op0
, bitsize
,
1742 bitpos
+ offset
* BITS_PER_UNIT
,
1745 total_bits
= GET_MODE_BITSIZE (mode
);
1747 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1748 be in the range 0 to total_bits-1, and put any excess bytes in
1750 if (bitpos
>= total_bits
)
1752 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
1753 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
1757 /* If we're accessing a volatile MEM, we can't do the next
1758 alignment step if it results in a multi-word access where we
1759 otherwise wouldn't have one. So, check for that case
1762 && MEM_VOLATILE_P (op0
)
1763 && flag_strict_volatile_bitfields
> 0
1764 && bitpos
+ bitsize
<= total_bits
1765 && bitpos
+ bitsize
+ (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
> total_bits
)
1767 if (STRICT_ALIGNMENT
)
1769 static bool informed_about_misalignment
= false;
1772 if (bitsize
== total_bits
)
1773 warned
= warning_at (input_location
, OPT_fstrict_volatile_bitfields
,
1774 "mis-aligned access used for structure member");
1776 warned
= warning_at (input_location
, OPT_fstrict_volatile_bitfields
,
1777 "mis-aligned access used for structure bitfield");
1779 if (! informed_about_misalignment
&& warned
)
1781 informed_about_misalignment
= true;
1782 inform (input_location
,
1783 "When a volatile object spans multiple type-sized locations,"
1784 " the compiler must choose between using a single mis-aligned access to"
1785 " preserve the volatility, or using multiple aligned accesses to avoid"
1786 " runtime faults. This code may fail at runtime if the hardware does"
1787 " not allow this access.");
1794 /* Get ref to an aligned byte, halfword, or word containing the field.
1795 Adjust BITPOS to be position within a word,
1796 and OFFSET to be the offset of that word.
1797 Then alter OP0 to refer to that word. */
1798 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
1799 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
1802 op0
= adjust_address (op0
, mode
, offset
);
1805 mode
= GET_MODE (op0
);
1807 if (BYTES_BIG_ENDIAN
)
1808 /* BITPOS is the distance between our msb and that of OP0.
1809 Convert it to the distance from the lsb. */
1810 bitpos
= total_bits
- bitsize
- bitpos
;
1812 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1813 We have reduced the big-endian case to the little-endian case. */
1819 /* If the field does not already start at the lsb,
1820 shift it so it does. */
1821 tree amount
= build_int_cst (NULL_TREE
, bitpos
);
1822 /* Maybe propagate the target for the shift. */
1823 /* But not if we will return it--could confuse integrate.c. */
1824 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1825 if (tmode
!= mode
) subtarget
= 0;
1826 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1828 /* Convert the value to the desired mode. */
1830 op0
= convert_to_mode (tmode
, op0
, 1);
1832 /* Unless the msb of the field used to be the msb when we shifted,
1833 mask out the upper bits. */
1835 if (GET_MODE_BITSIZE (mode
) != bitpos
+ bitsize
)
1836 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1837 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1838 target
, 1, OPTAB_LIB_WIDEN
);
1842 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1843 then arithmetic-shift its lsb to the lsb of the word. */
1844 op0
= force_reg (mode
, op0
);
1848 /* Find the narrowest integer mode that contains the field. */
1850 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1851 mode
= GET_MODE_WIDER_MODE (mode
))
1852 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitpos
)
1854 op0
= convert_to_mode (mode
, op0
, 0);
1858 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitpos
))
1861 = build_int_cst (NULL_TREE
,
1862 GET_MODE_BITSIZE (mode
) - (bitsize
+ bitpos
));
1863 /* Maybe propagate the target for the shift. */
1864 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1865 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1868 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1869 build_int_cst (NULL_TREE
,
1870 GET_MODE_BITSIZE (mode
) - bitsize
),
1874 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1875 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1876 complement of that if COMPLEMENT. The mask is truncated if
1877 necessary to the width of mode MODE. The mask is zero-extended if
1878 BITSIZE+BITPOS is too small for MODE. */
1881 mask_rtx (enum machine_mode mode
, int bitpos
, int bitsize
, int complement
)
1885 mask
= double_int_mask (bitsize
);
1886 mask
= double_int_lshift (mask
, bitpos
, HOST_BITS_PER_DOUBLE_INT
, false);
1889 mask
= double_int_not (mask
);
1891 return immed_double_int_const (mask
, mode
);
1894 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1895 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1898 lshift_value (enum machine_mode mode
, rtx value
, int bitpos
, int bitsize
)
1902 val
= double_int_zext (uhwi_to_double_int (INTVAL (value
)), bitsize
);
1903 val
= double_int_lshift (val
, bitpos
, HOST_BITS_PER_DOUBLE_INT
, false);
1905 return immed_double_int_const (val
, mode
);
1908 /* Extract a bit field that is split across two words
1909 and return an RTX for the result.
1911 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1912 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1913 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1916 extract_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1917 unsigned HOST_WIDE_INT bitpos
, int unsignedp
)
1920 unsigned int bitsdone
= 0;
1921 rtx result
= NULL_RTX
;
1924 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1926 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1927 unit
= BITS_PER_WORD
;
1929 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1931 while (bitsdone
< bitsize
)
1933 unsigned HOST_WIDE_INT thissize
;
1935 unsigned HOST_WIDE_INT thispos
;
1936 unsigned HOST_WIDE_INT offset
;
1938 offset
= (bitpos
+ bitsdone
) / unit
;
1939 thispos
= (bitpos
+ bitsdone
) % unit
;
1941 /* THISSIZE must not overrun a word boundary. Otherwise,
1942 extract_fixed_bit_field will call us again, and we will mutually
1944 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1945 thissize
= MIN (thissize
, unit
- thispos
);
1947 /* If OP0 is a register, then handle OFFSET here.
1949 When handling multiword bitfields, extract_bit_field may pass
1950 down a word_mode SUBREG of a larger REG for a bitfield that actually
1951 crosses a word boundary. Thus, for a SUBREG, we must find
1952 the current word starting from the base register. */
1953 if (GET_CODE (op0
) == SUBREG
)
1955 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1956 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1957 GET_MODE (SUBREG_REG (op0
)));
1960 else if (REG_P (op0
))
1962 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1968 /* Extract the parts in bit-counting order,
1969 whose meaning is determined by BYTES_PER_UNIT.
1970 OFFSET is in UNITs, and UNIT is in bits.
1971 extract_fixed_bit_field wants offset in bytes. */
1972 part
= extract_fixed_bit_field (word_mode
, word
,
1973 offset
* unit
/ BITS_PER_UNIT
,
1974 thissize
, thispos
, 0, 1);
1975 bitsdone
+= thissize
;
1977 /* Shift this part into place for the result. */
1978 if (BYTES_BIG_ENDIAN
)
1980 if (bitsize
!= bitsdone
)
1981 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1982 build_int_cst (NULL_TREE
, bitsize
- bitsdone
),
1987 if (bitsdone
!= thissize
)
1988 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1989 build_int_cst (NULL_TREE
,
1990 bitsdone
- thissize
), 0, 1);
1996 /* Combine the parts with bitwise or. This works
1997 because we extracted each part as an unsigned bit field. */
1998 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
2004 /* Unsigned bit field: we are done. */
2007 /* Signed bit field: sign-extend with two arithmetic shifts. */
2008 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
2009 build_int_cst (NULL_TREE
, BITS_PER_WORD
- bitsize
),
2011 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
2012 build_int_cst (NULL_TREE
, BITS_PER_WORD
- bitsize
),
2016 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
2017 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
2018 MODE, fill the upper bits with zeros. Fail if the layout of either
2019 mode is unknown (as for CC modes) or if the extraction would involve
2020 unprofitable mode punning. Return the value on success, otherwise
2023 This is different from gen_lowpart* in these respects:
2025 - the returned value must always be considered an rvalue
2027 - when MODE is wider than SRC_MODE, the extraction involves
2030 - when MODE is smaller than SRC_MODE, the extraction involves
2031 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
2033 In other words, this routine performs a computation, whereas the
2034 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2038 extract_low_bits (enum machine_mode mode
, enum machine_mode src_mode
, rtx src
)
2040 enum machine_mode int_mode
, src_int_mode
;
2042 if (mode
== src_mode
)
2045 if (CONSTANT_P (src
))
2047 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2048 fails, it will happily create (subreg (symbol_ref)) or similar
2050 unsigned int byte
= subreg_lowpart_offset (mode
, src_mode
);
2051 rtx ret
= simplify_subreg (mode
, src
, src_mode
, byte
);
2055 if (GET_MODE (src
) == VOIDmode
2056 || !validate_subreg (mode
, src_mode
, src
, byte
))
2059 src
= force_reg (GET_MODE (src
), src
);
2060 return gen_rtx_SUBREG (mode
, src
, byte
);
2063 if (GET_MODE_CLASS (mode
) == MODE_CC
|| GET_MODE_CLASS (src_mode
) == MODE_CC
)
2066 if (GET_MODE_BITSIZE (mode
) == GET_MODE_BITSIZE (src_mode
)
2067 && MODES_TIEABLE_P (mode
, src_mode
))
2069 rtx x
= gen_lowpart_common (mode
, src
);
2074 src_int_mode
= int_mode_for_mode (src_mode
);
2075 int_mode
= int_mode_for_mode (mode
);
2076 if (src_int_mode
== BLKmode
|| int_mode
== BLKmode
)
2079 if (!MODES_TIEABLE_P (src_int_mode
, src_mode
))
2081 if (!MODES_TIEABLE_P (int_mode
, mode
))
2084 src
= gen_lowpart (src_int_mode
, src
);
2085 src
= convert_modes (int_mode
, src_int_mode
, src
, true);
2086 src
= gen_lowpart (mode
, src
);
2090 /* Add INC into TARGET. */
2093 expand_inc (rtx target
, rtx inc
)
2095 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
2097 target
, 0, OPTAB_LIB_WIDEN
);
2098 if (value
!= target
)
2099 emit_move_insn (target
, value
);
2102 /* Subtract DEC from TARGET. */
2105 expand_dec (rtx target
, rtx dec
)
2107 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
2109 target
, 0, OPTAB_LIB_WIDEN
);
2110 if (value
!= target
)
2111 emit_move_insn (target
, value
);
2114 /* Output a shift instruction for expression code CODE,
2115 with SHIFTED being the rtx for the value to shift,
2116 and AMOUNT the tree for the amount to shift by.
2117 Store the result in the rtx TARGET, if that is convenient.
2118 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2119 Return the rtx for where the value is. */
2122 expand_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2123 tree amount
, rtx target
, int unsignedp
)
2126 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2127 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2128 optab lshift_optab
= ashl_optab
;
2129 optab rshift_arith_optab
= ashr_optab
;
2130 optab rshift_uns_optab
= lshr_optab
;
2131 optab lrotate_optab
= rotl_optab
;
2132 optab rrotate_optab
= rotr_optab
;
2133 enum machine_mode op1_mode
;
2135 bool speed
= optimize_insn_for_speed_p ();
2137 op1
= expand_normal (amount
);
2138 op1_mode
= GET_MODE (op1
);
2140 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2141 shift amount is a vector, use the vector/vector shift patterns. */
2142 if (VECTOR_MODE_P (mode
) && VECTOR_MODE_P (op1_mode
))
2144 lshift_optab
= vashl_optab
;
2145 rshift_arith_optab
= vashr_optab
;
2146 rshift_uns_optab
= vlshr_optab
;
2147 lrotate_optab
= vrotl_optab
;
2148 rrotate_optab
= vrotr_optab
;
2151 /* Previously detected shift-counts computed by NEGATE_EXPR
2152 and shifted in the other direction; but that does not work
2155 if (SHIFT_COUNT_TRUNCATED
)
2157 if (CONST_INT_P (op1
)
2158 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2159 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
2160 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
2161 % GET_MODE_BITSIZE (mode
));
2162 else if (GET_CODE (op1
) == SUBREG
2163 && subreg_lowpart_p (op1
)
2164 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (op1
))))
2165 op1
= SUBREG_REG (op1
);
2168 if (op1
== const0_rtx
)
2171 /* Check whether its cheaper to implement a left shift by a constant
2172 bit count by a sequence of additions. */
2173 if (code
== LSHIFT_EXPR
2174 && CONST_INT_P (op1
)
2176 && INTVAL (op1
) < GET_MODE_BITSIZE (mode
)
2177 && INTVAL (op1
) < MAX_BITS_PER_WORD
2178 && shift_cost
[speed
][mode
][INTVAL (op1
)] > INTVAL (op1
) * add_cost
[speed
][mode
]
2179 && shift_cost
[speed
][mode
][INTVAL (op1
)] != MAX_COST
)
2182 for (i
= 0; i
< INTVAL (op1
); i
++)
2184 temp
= force_reg (mode
, shifted
);
2185 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2186 unsignedp
, OPTAB_LIB_WIDEN
);
2191 for (attempt
= 0; temp
== 0 && attempt
< 3; attempt
++)
2193 enum optab_methods methods
;
2196 methods
= OPTAB_DIRECT
;
2197 else if (attempt
== 1)
2198 methods
= OPTAB_WIDEN
;
2200 methods
= OPTAB_LIB_WIDEN
;
2204 /* Widening does not work for rotation. */
2205 if (methods
== OPTAB_WIDEN
)
2207 else if (methods
== OPTAB_LIB_WIDEN
)
2209 /* If we have been unable to open-code this by a rotation,
2210 do it as the IOR of two shifts. I.e., to rotate A
2211 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
2212 where C is the bitsize of A.
2214 It is theoretically possible that the target machine might
2215 not be able to perform either shift and hence we would
2216 be making two libcalls rather than just the one for the
2217 shift (similarly if IOR could not be done). We will allow
2218 this extremely unlikely lossage to avoid complicating the
2221 rtx subtarget
= target
== shifted
? 0 : target
;
2222 tree new_amount
, other_amount
;
2224 tree type
= TREE_TYPE (amount
);
2225 if (GET_MODE (op1
) != TYPE_MODE (type
)
2226 && GET_MODE (op1
) != VOIDmode
)
2227 op1
= convert_to_mode (TYPE_MODE (type
), op1
, 1);
2228 new_amount
= make_tree (type
, op1
);
2230 = fold_build2 (MINUS_EXPR
, type
,
2231 build_int_cst (type
, GET_MODE_BITSIZE (mode
)),
2234 shifted
= force_reg (mode
, shifted
);
2236 temp
= expand_shift (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2237 mode
, shifted
, new_amount
, 0, 1);
2238 temp1
= expand_shift (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2239 mode
, shifted
, other_amount
, subtarget
, 1);
2240 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2241 unsignedp
, methods
);
2244 temp
= expand_binop (mode
,
2245 left
? lrotate_optab
: rrotate_optab
,
2246 shifted
, op1
, target
, unsignedp
, methods
);
2249 temp
= expand_binop (mode
,
2250 left
? lshift_optab
: rshift_uns_optab
,
2251 shifted
, op1
, target
, unsignedp
, methods
);
2253 /* Do arithmetic shifts.
2254 Also, if we are going to widen the operand, we can just as well
2255 use an arithmetic right-shift instead of a logical one. */
2256 if (temp
== 0 && ! rotate
2257 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2259 enum optab_methods methods1
= methods
;
2261 /* If trying to widen a log shift to an arithmetic shift,
2262 don't accept an arithmetic shift of the same size. */
2264 methods1
= OPTAB_MUST_WIDEN
;
2266 /* Arithmetic shift */
2268 temp
= expand_binop (mode
,
2269 left
? lshift_optab
: rshift_arith_optab
,
2270 shifted
, op1
, target
, unsignedp
, methods1
);
2273 /* We used to try extzv here for logical right shifts, but that was
2274 only useful for one machine, the VAX, and caused poor code
2275 generation there for lshrdi3, so the code was deleted and a
2276 define_expand for lshrsi3 was added to vax.md. */
2283 /* Indicates the type of fixup needed after a constant multiplication.
2284 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2285 the result should be negated, and ADD_VARIANT means that the
2286 multiplicand should be added to the result. */
2287 enum mult_variant
{basic_variant
, negate_variant
, add_variant
};
2289 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2290 const struct mult_cost
*, enum machine_mode mode
);
2291 static bool choose_mult_variant (enum machine_mode
, HOST_WIDE_INT
,
2292 struct algorithm
*, enum mult_variant
*, int);
2293 static rtx
expand_mult_const (enum machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2294 const struct algorithm
*, enum mult_variant
);
2295 static unsigned HOST_WIDE_INT
choose_multiplier (unsigned HOST_WIDE_INT
, int,
2296 int, rtx
*, int *, int *);
2297 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2298 static rtx
extract_high_half (enum machine_mode
, rtx
);
2299 static rtx
expand_mult_highpart (enum machine_mode
, rtx
, rtx
, rtx
, int, int);
2300 static rtx
expand_mult_highpart_optab (enum machine_mode
, rtx
, rtx
, rtx
,
2302 /* Compute and return the best algorithm for multiplying by T.
2303 The algorithm must cost less than cost_limit
2304 If retval.cost >= COST_LIMIT, no algorithm was found and all
2305 other field of the returned struct are undefined.
2306 MODE is the machine mode of the multiplication. */
2309 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2310 const struct mult_cost
*cost_limit
, enum machine_mode mode
)
2313 struct algorithm
*alg_in
, *best_alg
;
2314 struct mult_cost best_cost
;
2315 struct mult_cost new_limit
;
2316 int op_cost
, op_latency
;
2317 unsigned HOST_WIDE_INT orig_t
= t
;
2318 unsigned HOST_WIDE_INT q
;
2319 int maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (mode
));
2321 bool cache_hit
= false;
2322 enum alg_code cache_alg
= alg_zero
;
2323 bool speed
= optimize_insn_for_speed_p ();
2325 /* Indicate that no algorithm is yet found. If no algorithm
2326 is found, this value will be returned and indicate failure. */
2327 alg_out
->cost
.cost
= cost_limit
->cost
+ 1;
2328 alg_out
->cost
.latency
= cost_limit
->latency
+ 1;
2330 if (cost_limit
->cost
< 0
2331 || (cost_limit
->cost
== 0 && cost_limit
->latency
<= 0))
2334 /* Restrict the bits of "t" to the multiplication's mode. */
2335 t
&= GET_MODE_MASK (mode
);
2337 /* t == 1 can be done in zero cost. */
2341 alg_out
->cost
.cost
= 0;
2342 alg_out
->cost
.latency
= 0;
2343 alg_out
->op
[0] = alg_m
;
2347 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2351 if (MULT_COST_LESS (cost_limit
, zero_cost
[speed
]))
2356 alg_out
->cost
.cost
= zero_cost
[speed
];
2357 alg_out
->cost
.latency
= zero_cost
[speed
];
2358 alg_out
->op
[0] = alg_zero
;
2363 /* We'll be needing a couple extra algorithm structures now. */
2365 alg_in
= XALLOCA (struct algorithm
);
2366 best_alg
= XALLOCA (struct algorithm
);
2367 best_cost
= *cost_limit
;
2369 /* Compute the hash index. */
2370 hash_index
= (t
^ (unsigned int) mode
^ (speed
* 256)) % NUM_ALG_HASH_ENTRIES
;
2372 /* See if we already know what to do for T. */
2373 if (alg_hash
[hash_index
].t
== t
2374 && alg_hash
[hash_index
].mode
== mode
2375 && alg_hash
[hash_index
].mode
== mode
2376 && alg_hash
[hash_index
].speed
== speed
2377 && alg_hash
[hash_index
].alg
!= alg_unknown
)
2379 cache_alg
= alg_hash
[hash_index
].alg
;
2381 if (cache_alg
== alg_impossible
)
2383 /* The cache tells us that it's impossible to synthesize
2384 multiplication by T within alg_hash[hash_index].cost. */
2385 if (!CHEAPER_MULT_COST (&alg_hash
[hash_index
].cost
, cost_limit
))
2386 /* COST_LIMIT is at least as restrictive as the one
2387 recorded in the hash table, in which case we have no
2388 hope of synthesizing a multiplication. Just
2392 /* If we get here, COST_LIMIT is less restrictive than the
2393 one recorded in the hash table, so we may be able to
2394 synthesize a multiplication. Proceed as if we didn't
2395 have the cache entry. */
2399 if (CHEAPER_MULT_COST (cost_limit
, &alg_hash
[hash_index
].cost
))
2400 /* The cached algorithm shows that this multiplication
2401 requires more cost than COST_LIMIT. Just return. This
2402 way, we don't clobber this cache entry with
2403 alg_impossible but retain useful information. */
2415 goto do_alg_addsub_t_m2
;
2417 case alg_add_factor
:
2418 case alg_sub_factor
:
2419 goto do_alg_addsub_factor
;
2422 goto do_alg_add_t2_m
;
2425 goto do_alg_sub_t2_m
;
2433 /* If we have a group of zero bits at the low-order part of T, try
2434 multiplying by the remaining bits and then doing a shift. */
2439 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2443 /* The function expand_shift will choose between a shift and
2444 a sequence of additions, so the observed cost is given as
2445 MIN (m * add_cost[speed][mode], shift_cost[speed][mode][m]). */
2446 op_cost
= m
* add_cost
[speed
][mode
];
2447 if (shift_cost
[speed
][mode
][m
] < op_cost
)
2448 op_cost
= shift_cost
[speed
][mode
][m
];
2449 new_limit
.cost
= best_cost
.cost
- op_cost
;
2450 new_limit
.latency
= best_cost
.latency
- op_cost
;
2451 synth_mult (alg_in
, q
, &new_limit
, mode
);
2453 alg_in
->cost
.cost
+= op_cost
;
2454 alg_in
->cost
.latency
+= op_cost
;
2455 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2457 struct algorithm
*x
;
2458 best_cost
= alg_in
->cost
;
2459 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2460 best_alg
->log
[best_alg
->ops
] = m
;
2461 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2464 /* See if treating ORIG_T as a signed number yields a better
2465 sequence. Try this sequence only for a negative ORIG_T
2466 as it would be useless for a non-negative ORIG_T. */
2467 if ((HOST_WIDE_INT
) orig_t
< 0)
2469 /* Shift ORIG_T as follows because a right shift of a
2470 negative-valued signed type is implementation
2472 q
= ~(~orig_t
>> m
);
2473 /* The function expand_shift will choose between a shift
2474 and a sequence of additions, so the observed cost is
2475 given as MIN (m * add_cost[speed][mode],
2476 shift_cost[speed][mode][m]). */
2477 op_cost
= m
* add_cost
[speed
][mode
];
2478 if (shift_cost
[speed
][mode
][m
] < op_cost
)
2479 op_cost
= shift_cost
[speed
][mode
][m
];
2480 new_limit
.cost
= best_cost
.cost
- op_cost
;
2481 new_limit
.latency
= best_cost
.latency
- op_cost
;
2482 synth_mult (alg_in
, q
, &new_limit
, mode
);
2484 alg_in
->cost
.cost
+= op_cost
;
2485 alg_in
->cost
.latency
+= op_cost
;
2486 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2488 struct algorithm
*x
;
2489 best_cost
= alg_in
->cost
;
2490 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2491 best_alg
->log
[best_alg
->ops
] = m
;
2492 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2500 /* If we have an odd number, add or subtract one. */
2503 unsigned HOST_WIDE_INT w
;
2506 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2508 /* If T was -1, then W will be zero after the loop. This is another
2509 case where T ends with ...111. Handling this with (T + 1) and
2510 subtract 1 produces slightly better code and results in algorithm
2511 selection much faster than treating it like the ...0111 case
2515 /* Reject the case where t is 3.
2516 Thus we prefer addition in that case. */
2519 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2521 op_cost
= add_cost
[speed
][mode
];
2522 new_limit
.cost
= best_cost
.cost
- op_cost
;
2523 new_limit
.latency
= best_cost
.latency
- op_cost
;
2524 synth_mult (alg_in
, t
+ 1, &new_limit
, mode
);
2526 alg_in
->cost
.cost
+= op_cost
;
2527 alg_in
->cost
.latency
+= op_cost
;
2528 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2530 struct algorithm
*x
;
2531 best_cost
= alg_in
->cost
;
2532 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2533 best_alg
->log
[best_alg
->ops
] = 0;
2534 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2539 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2541 op_cost
= add_cost
[speed
][mode
];
2542 new_limit
.cost
= best_cost
.cost
- op_cost
;
2543 new_limit
.latency
= best_cost
.latency
- op_cost
;
2544 synth_mult (alg_in
, t
- 1, &new_limit
, mode
);
2546 alg_in
->cost
.cost
+= op_cost
;
2547 alg_in
->cost
.latency
+= op_cost
;
2548 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2550 struct algorithm
*x
;
2551 best_cost
= alg_in
->cost
;
2552 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2553 best_alg
->log
[best_alg
->ops
] = 0;
2554 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2558 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2559 quickly with a - a * n for some appropriate constant n. */
2560 m
= exact_log2 (-orig_t
+ 1);
2561 if (m
>= 0 && m
< maxm
)
2563 op_cost
= shiftsub1_cost
[speed
][mode
][m
];
2564 new_limit
.cost
= best_cost
.cost
- op_cost
;
2565 new_limit
.latency
= best_cost
.latency
- op_cost
;
2566 synth_mult (alg_in
, (unsigned HOST_WIDE_INT
) (-orig_t
+ 1) >> m
, &new_limit
, mode
);
2568 alg_in
->cost
.cost
+= op_cost
;
2569 alg_in
->cost
.latency
+= op_cost
;
2570 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2572 struct algorithm
*x
;
2573 best_cost
= alg_in
->cost
;
2574 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2575 best_alg
->log
[best_alg
->ops
] = m
;
2576 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2584 /* Look for factors of t of the form
2585 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2586 If we find such a factor, we can multiply by t using an algorithm that
2587 multiplies by q, shift the result by m and add/subtract it to itself.
2589 We search for large factors first and loop down, even if large factors
2590 are less probable than small; if we find a large factor we will find a
2591 good sequence quickly, and therefore be able to prune (by decreasing
2592 COST_LIMIT) the search. */
2594 do_alg_addsub_factor
:
2595 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2597 unsigned HOST_WIDE_INT d
;
2599 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2600 if (t
% d
== 0 && t
> d
&& m
< maxm
2601 && (!cache_hit
|| cache_alg
== alg_add_factor
))
2603 /* If the target has a cheap shift-and-add instruction use
2604 that in preference to a shift insn followed by an add insn.
2605 Assume that the shift-and-add is "atomic" with a latency
2606 equal to its cost, otherwise assume that on superscalar
2607 hardware the shift may be executed concurrently with the
2608 earlier steps in the algorithm. */
2609 op_cost
= add_cost
[speed
][mode
] + shift_cost
[speed
][mode
][m
];
2610 if (shiftadd_cost
[speed
][mode
][m
] < op_cost
)
2612 op_cost
= shiftadd_cost
[speed
][mode
][m
];
2613 op_latency
= op_cost
;
2616 op_latency
= add_cost
[speed
][mode
];
2618 new_limit
.cost
= best_cost
.cost
- op_cost
;
2619 new_limit
.latency
= best_cost
.latency
- op_latency
;
2620 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2622 alg_in
->cost
.cost
+= op_cost
;
2623 alg_in
->cost
.latency
+= op_latency
;
2624 if (alg_in
->cost
.latency
< op_cost
)
2625 alg_in
->cost
.latency
= op_cost
;
2626 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2628 struct algorithm
*x
;
2629 best_cost
= alg_in
->cost
;
2630 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2631 best_alg
->log
[best_alg
->ops
] = m
;
2632 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2634 /* Other factors will have been taken care of in the recursion. */
2638 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2639 if (t
% d
== 0 && t
> d
&& m
< maxm
2640 && (!cache_hit
|| cache_alg
== alg_sub_factor
))
2642 /* If the target has a cheap shift-and-subtract insn use
2643 that in preference to a shift insn followed by a sub insn.
2644 Assume that the shift-and-sub is "atomic" with a latency
2645 equal to it's cost, otherwise assume that on superscalar
2646 hardware the shift may be executed concurrently with the
2647 earlier steps in the algorithm. */
2648 op_cost
= add_cost
[speed
][mode
] + shift_cost
[speed
][mode
][m
];
2649 if (shiftsub0_cost
[speed
][mode
][m
] < op_cost
)
2651 op_cost
= shiftsub0_cost
[speed
][mode
][m
];
2652 op_latency
= op_cost
;
2655 op_latency
= add_cost
[speed
][mode
];
2657 new_limit
.cost
= best_cost
.cost
- op_cost
;
2658 new_limit
.latency
= best_cost
.latency
- op_latency
;
2659 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2661 alg_in
->cost
.cost
+= op_cost
;
2662 alg_in
->cost
.latency
+= op_latency
;
2663 if (alg_in
->cost
.latency
< op_cost
)
2664 alg_in
->cost
.latency
= op_cost
;
2665 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2667 struct algorithm
*x
;
2668 best_cost
= alg_in
->cost
;
2669 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2670 best_alg
->log
[best_alg
->ops
] = m
;
2671 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2679 /* Try shift-and-add (load effective address) instructions,
2680 i.e. do a*3, a*5, a*9. */
2687 if (m
>= 0 && m
< maxm
)
2689 op_cost
= shiftadd_cost
[speed
][mode
][m
];
2690 new_limit
.cost
= best_cost
.cost
- op_cost
;
2691 new_limit
.latency
= best_cost
.latency
- op_cost
;
2692 synth_mult (alg_in
, (t
- 1) >> m
, &new_limit
, mode
);
2694 alg_in
->cost
.cost
+= op_cost
;
2695 alg_in
->cost
.latency
+= op_cost
;
2696 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2698 struct algorithm
*x
;
2699 best_cost
= alg_in
->cost
;
2700 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2701 best_alg
->log
[best_alg
->ops
] = m
;
2702 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2712 if (m
>= 0 && m
< maxm
)
2714 op_cost
= shiftsub0_cost
[speed
][mode
][m
];
2715 new_limit
.cost
= best_cost
.cost
- op_cost
;
2716 new_limit
.latency
= best_cost
.latency
- op_cost
;
2717 synth_mult (alg_in
, (t
+ 1) >> m
, &new_limit
, mode
);
2719 alg_in
->cost
.cost
+= op_cost
;
2720 alg_in
->cost
.latency
+= op_cost
;
2721 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2723 struct algorithm
*x
;
2724 best_cost
= alg_in
->cost
;
2725 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2726 best_alg
->log
[best_alg
->ops
] = m
;
2727 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2735 /* If best_cost has not decreased, we have not found any algorithm. */
2736 if (!CHEAPER_MULT_COST (&best_cost
, cost_limit
))
2738 /* We failed to find an algorithm. Record alg_impossible for
2739 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2740 we are asked to find an algorithm for T within the same or
2741 lower COST_LIMIT, we can immediately return to the
2743 alg_hash
[hash_index
].t
= t
;
2744 alg_hash
[hash_index
].mode
= mode
;
2745 alg_hash
[hash_index
].speed
= speed
;
2746 alg_hash
[hash_index
].alg
= alg_impossible
;
2747 alg_hash
[hash_index
].cost
= *cost_limit
;
2751 /* Cache the result. */
2754 alg_hash
[hash_index
].t
= t
;
2755 alg_hash
[hash_index
].mode
= mode
;
2756 alg_hash
[hash_index
].speed
= speed
;
2757 alg_hash
[hash_index
].alg
= best_alg
->op
[best_alg
->ops
];
2758 alg_hash
[hash_index
].cost
.cost
= best_cost
.cost
;
2759 alg_hash
[hash_index
].cost
.latency
= best_cost
.latency
;
2762 /* If we are getting a too long sequence for `struct algorithm'
2763 to record, make this search fail. */
2764 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2767 /* Copy the algorithm from temporary space to the space at alg_out.
2768 We avoid using structure assignment because the majority of
2769 best_alg is normally undefined, and this is a critical function. */
2770 alg_out
->ops
= best_alg
->ops
+ 1;
2771 alg_out
->cost
= best_cost
;
2772 memcpy (alg_out
->op
, best_alg
->op
,
2773 alg_out
->ops
* sizeof *alg_out
->op
);
2774 memcpy (alg_out
->log
, best_alg
->log
,
2775 alg_out
->ops
* sizeof *alg_out
->log
);
2778 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2779 Try three variations:
2781 - a shift/add sequence based on VAL itself
2782 - a shift/add sequence based on -VAL, followed by a negation
2783 - a shift/add sequence based on VAL - 1, followed by an addition.
2785 Return true if the cheapest of these cost less than MULT_COST,
2786 describing the algorithm in *ALG and final fixup in *VARIANT. */
2789 choose_mult_variant (enum machine_mode mode
, HOST_WIDE_INT val
,
2790 struct algorithm
*alg
, enum mult_variant
*variant
,
2793 struct algorithm alg2
;
2794 struct mult_cost limit
;
2796 bool speed
= optimize_insn_for_speed_p ();
2798 /* Fail quickly for impossible bounds. */
2802 /* Ensure that mult_cost provides a reasonable upper bound.
2803 Any constant multiplication can be performed with less
2804 than 2 * bits additions. */
2805 op_cost
= 2 * GET_MODE_BITSIZE (mode
) * add_cost
[speed
][mode
];
2806 if (mult_cost
> op_cost
)
2807 mult_cost
= op_cost
;
2809 *variant
= basic_variant
;
2810 limit
.cost
= mult_cost
;
2811 limit
.latency
= mult_cost
;
2812 synth_mult (alg
, val
, &limit
, mode
);
2814 /* This works only if the inverted value actually fits in an
2816 if (HOST_BITS_PER_INT
>= GET_MODE_BITSIZE (mode
))
2818 op_cost
= neg_cost
[speed
][mode
];
2819 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2821 limit
.cost
= alg
->cost
.cost
- op_cost
;
2822 limit
.latency
= alg
->cost
.latency
- op_cost
;
2826 limit
.cost
= mult_cost
- op_cost
;
2827 limit
.latency
= mult_cost
- op_cost
;
2830 synth_mult (&alg2
, -val
, &limit
, mode
);
2831 alg2
.cost
.cost
+= op_cost
;
2832 alg2
.cost
.latency
+= op_cost
;
2833 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2834 *alg
= alg2
, *variant
= negate_variant
;
2837 /* This proves very useful for division-by-constant. */
2838 op_cost
= add_cost
[speed
][mode
];
2839 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2841 limit
.cost
= alg
->cost
.cost
- op_cost
;
2842 limit
.latency
= alg
->cost
.latency
- op_cost
;
2846 limit
.cost
= mult_cost
- op_cost
;
2847 limit
.latency
= mult_cost
- op_cost
;
2850 synth_mult (&alg2
, val
- 1, &limit
, mode
);
2851 alg2
.cost
.cost
+= op_cost
;
2852 alg2
.cost
.latency
+= op_cost
;
2853 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2854 *alg
= alg2
, *variant
= add_variant
;
2856 return MULT_COST_LESS (&alg
->cost
, mult_cost
);
2859 /* A subroutine of expand_mult, used for constant multiplications.
2860 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2861 convenient. Use the shift/add sequence described by ALG and apply
2862 the final fixup specified by VARIANT. */
2865 expand_mult_const (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
2866 rtx target
, const struct algorithm
*alg
,
2867 enum mult_variant variant
)
2869 HOST_WIDE_INT val_so_far
;
2870 rtx insn
, accum
, tem
;
2872 enum machine_mode nmode
;
2874 /* Avoid referencing memory over and over and invalid sharing
2876 op0
= force_reg (mode
, op0
);
2878 /* ACCUM starts out either as OP0 or as a zero, depending on
2879 the first operation. */
2881 if (alg
->op
[0] == alg_zero
)
2883 accum
= copy_to_mode_reg (mode
, const0_rtx
);
2886 else if (alg
->op
[0] == alg_m
)
2888 accum
= copy_to_mode_reg (mode
, op0
);
2894 for (opno
= 1; opno
< alg
->ops
; opno
++)
2896 int log
= alg
->log
[opno
];
2897 rtx shift_subtarget
= optimize
? 0 : accum
;
2899 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
2902 rtx accum_target
= optimize
? 0 : accum
;
2904 switch (alg
->op
[opno
])
2907 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2908 build_int_cst (NULL_TREE
, log
),
2914 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2915 build_int_cst (NULL_TREE
, log
),
2917 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2918 add_target
? add_target
: accum_target
);
2919 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2923 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2924 build_int_cst (NULL_TREE
, log
),
2926 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2927 add_target
? add_target
: accum_target
);
2928 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2932 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2933 build_int_cst (NULL_TREE
, log
),
2936 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2937 add_target
? add_target
: accum_target
);
2938 val_so_far
= (val_so_far
<< log
) + 1;
2942 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2943 build_int_cst (NULL_TREE
, log
),
2944 shift_subtarget
, 0);
2945 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2946 add_target
? add_target
: accum_target
);
2947 val_so_far
= (val_so_far
<< log
) - 1;
2950 case alg_add_factor
:
2951 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2952 build_int_cst (NULL_TREE
, log
),
2954 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2955 add_target
? add_target
: accum_target
);
2956 val_so_far
+= val_so_far
<< log
;
2959 case alg_sub_factor
:
2960 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2961 build_int_cst (NULL_TREE
, log
),
2963 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2965 ? add_target
: (optimize
? 0 : tem
)));
2966 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2973 /* Write a REG_EQUAL note on the last insn so that we can cse
2974 multiplication sequences. Note that if ACCUM is a SUBREG,
2975 we've set the inner register and must properly indicate
2978 tem
= op0
, nmode
= mode
;
2979 if (GET_CODE (accum
) == SUBREG
)
2981 nmode
= GET_MODE (SUBREG_REG (accum
));
2982 tem
= gen_lowpart (nmode
, op0
);
2985 insn
= get_last_insn ();
2986 set_unique_reg_note (insn
, REG_EQUAL
,
2987 gen_rtx_MULT (nmode
, tem
,
2988 GEN_INT (val_so_far
)));
2991 if (variant
== negate_variant
)
2993 val_so_far
= -val_so_far
;
2994 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
2996 else if (variant
== add_variant
)
2998 val_so_far
= val_so_far
+ 1;
2999 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
3002 /* Compare only the bits of val and val_so_far that are significant
3003 in the result mode, to avoid sign-/zero-extension confusion. */
3004 val
&= GET_MODE_MASK (mode
);
3005 val_so_far
&= GET_MODE_MASK (mode
);
3006 gcc_assert (val
== val_so_far
);
3011 /* Perform a multiplication and return an rtx for the result.
3012 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3013 TARGET is a suggestion for where to store the result (an rtx).
3015 We check specially for a constant integer as OP1.
3016 If you want this check for OP0 as well, then before calling
3017 you should swap the two operands if OP0 would be constant. */
3020 expand_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3023 enum mult_variant variant
;
3024 struct algorithm algorithm
;
3026 bool speed
= optimize_insn_for_speed_p ();
3028 /* Handling const0_rtx here allows us to use zero as a rogue value for
3030 if (op1
== const0_rtx
)
3032 if (op1
== const1_rtx
)
3034 if (op1
== constm1_rtx
)
3035 return expand_unop (mode
,
3036 GET_MODE_CLASS (mode
) == MODE_INT
3037 && !unsignedp
&& flag_trapv
3038 ? negv_optab
: neg_optab
,
3041 /* These are the operations that are potentially turned into a sequence
3042 of shifts and additions. */
3043 if (SCALAR_INT_MODE_P (mode
)
3044 && (unsignedp
|| !flag_trapv
))
3046 HOST_WIDE_INT coeff
= 0;
3047 rtx fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3049 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3050 less than or equal in size to `unsigned int' this doesn't matter.
3051 If the mode is larger than `unsigned int', then synth_mult works
3052 only if the constant value exactly fits in an `unsigned int' without
3053 any truncation. This means that multiplying by negative values does
3054 not work; results are off by 2^32 on a 32 bit machine. */
3056 if (CONST_INT_P (op1
))
3058 /* Attempt to handle multiplication of DImode values by negative
3059 coefficients, by performing the multiplication by a positive
3060 multiplier and then inverting the result. */
3061 if (INTVAL (op1
) < 0
3062 && GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
3064 /* Its safe to use -INTVAL (op1) even for INT_MIN, as the
3065 result is interpreted as an unsigned coefficient.
3066 Exclude cost of op0 from max_cost to match the cost
3067 calculation of the synth_mult. */
3068 max_cost
= rtx_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), SET
, speed
)
3069 - neg_cost
[speed
][mode
];
3071 && choose_mult_variant (mode
, -INTVAL (op1
), &algorithm
,
3072 &variant
, max_cost
))
3074 rtx temp
= expand_mult_const (mode
, op0
, -INTVAL (op1
),
3075 NULL_RTX
, &algorithm
,
3077 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3080 else coeff
= INTVAL (op1
);
3082 else if (GET_CODE (op1
) == CONST_DOUBLE
)
3084 /* If we are multiplying in DImode, it may still be a win
3085 to try to work with shifts and adds. */
3086 if (CONST_DOUBLE_HIGH (op1
) == 0
3087 && CONST_DOUBLE_LOW (op1
) > 0)
3088 coeff
= CONST_DOUBLE_LOW (op1
);
3089 else if (CONST_DOUBLE_LOW (op1
) == 0
3090 && EXACT_POWER_OF_2_OR_ZERO_P (CONST_DOUBLE_HIGH (op1
)))
3092 int shift
= floor_log2 (CONST_DOUBLE_HIGH (op1
))
3093 + HOST_BITS_PER_WIDE_INT
;
3094 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3095 build_int_cst (NULL_TREE
, shift
),
3100 /* We used to test optimize here, on the grounds that it's better to
3101 produce a smaller program when -O is not used. But this causes
3102 such a terrible slowdown sometimes that it seems better to always
3106 /* Special case powers of two. */
3107 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3108 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3109 build_int_cst (NULL_TREE
, floor_log2 (coeff
)),
3112 /* Exclude cost of op0 from max_cost to match the cost
3113 calculation of the synth_mult. */
3114 max_cost
= rtx_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), SET
, speed
);
3115 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3117 return expand_mult_const (mode
, op0
, coeff
, target
,
3118 &algorithm
, variant
);
3122 if (GET_CODE (op0
) == CONST_DOUBLE
)
3129 /* Expand x*2.0 as x+x. */
3130 if (GET_CODE (op1
) == CONST_DOUBLE
3131 && SCALAR_FLOAT_MODE_P (mode
))
3134 REAL_VALUE_FROM_CONST_DOUBLE (d
, op1
);
3136 if (REAL_VALUES_EQUAL (d
, dconst2
))
3138 op0
= force_reg (GET_MODE (op0
), op0
);
3139 return expand_binop (mode
, add_optab
, op0
, op0
,
3140 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3144 /* This used to use umul_optab if unsigned, but for non-widening multiply
3145 there is no difference between signed and unsigned. */
3146 op0
= expand_binop (mode
,
3148 && flag_trapv
&& (GET_MODE_CLASS(mode
) == MODE_INT
)
3149 ? smulv_optab
: smul_optab
,
3150 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
3155 /* Perform a widening multiplication and return an rtx for the result.
3156 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3157 TARGET is a suggestion for where to store the result (an rtx).
3158 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3159 or smul_widen_optab.
3161 We check specially for a constant integer as OP1, comparing the
3162 cost of a widening multiply against the cost of a sequence of shifts
3166 expand_widening_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3167 int unsignedp
, optab this_optab
)
3169 bool speed
= optimize_insn_for_speed_p ();
3171 if (CONST_INT_P (op1
)
3172 && (INTVAL (op1
) >= 0
3173 || GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
))
3175 HOST_WIDE_INT coeff
= INTVAL (op1
);
3177 enum mult_variant variant
;
3178 struct algorithm algorithm
;
3180 /* Special case powers of two. */
3181 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3183 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3184 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3185 build_int_cst (NULL_TREE
, floor_log2 (coeff
)),
3189 /* Exclude cost of op0 from max_cost to match the cost
3190 calculation of the synth_mult. */
3191 max_cost
= mul_widen_cost
[speed
][mode
];
3192 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3195 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3196 return expand_mult_const (mode
, op0
, coeff
, target
,
3197 &algorithm
, variant
);
3200 return expand_binop (mode
, this_optab
, op0
, op1
, target
,
3201 unsignedp
, OPTAB_LIB_WIDEN
);
3204 /* Return the smallest n such that 2**n >= X. */
3207 ceil_log2 (unsigned HOST_WIDE_INT x
)
3209 return floor_log2 (x
- 1) + 1;
3212 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3213 replace division by D, and put the least significant N bits of the result
3214 in *MULTIPLIER_PTR and return the most significant bit.
3216 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3217 needed precision is in PRECISION (should be <= N).
3219 PRECISION should be as small as possible so this function can choose
3220 multiplier more freely.
3222 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3223 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3225 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3226 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3229 unsigned HOST_WIDE_INT
3230 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
3231 rtx
*multiplier_ptr
, int *post_shift_ptr
, int *lgup_ptr
)
3233 HOST_WIDE_INT mhigh_hi
, mlow_hi
;
3234 unsigned HOST_WIDE_INT mhigh_lo
, mlow_lo
;
3235 int lgup
, post_shift
;
3237 unsigned HOST_WIDE_INT nl
, dummy1
;
3238 HOST_WIDE_INT nh
, dummy2
;
3240 /* lgup = ceil(log2(divisor)); */
3241 lgup
= ceil_log2 (d
);
3243 gcc_assert (lgup
<= n
);
3246 pow2
= n
+ lgup
- precision
;
3248 /* We could handle this with some effort, but this case is much
3249 better handled directly with a scc insn, so rely on caller using
3251 gcc_assert (pow
!= 2 * HOST_BITS_PER_WIDE_INT
);
3253 /* mlow = 2^(N + lgup)/d */
3254 if (pow
>= HOST_BITS_PER_WIDE_INT
)
3256 nh
= (HOST_WIDE_INT
) 1 << (pow
- HOST_BITS_PER_WIDE_INT
);
3262 nl
= (unsigned HOST_WIDE_INT
) 1 << pow
;
3264 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
3265 &mlow_lo
, &mlow_hi
, &dummy1
, &dummy2
);
3267 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
3268 if (pow2
>= HOST_BITS_PER_WIDE_INT
)
3269 nh
|= (HOST_WIDE_INT
) 1 << (pow2
- HOST_BITS_PER_WIDE_INT
);
3271 nl
|= (unsigned HOST_WIDE_INT
) 1 << pow2
;
3272 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
3273 &mhigh_lo
, &mhigh_hi
, &dummy1
, &dummy2
);
3275 gcc_assert (!mhigh_hi
|| nh
- d
< d
);
3276 gcc_assert (mhigh_hi
<= 1 && mlow_hi
<= 1);
3277 /* Assert that mlow < mhigh. */
3278 gcc_assert (mlow_hi
< mhigh_hi
3279 || (mlow_hi
== mhigh_hi
&& mlow_lo
< mhigh_lo
));
3281 /* If precision == N, then mlow, mhigh exceed 2^N
3282 (but they do not exceed 2^(N+1)). */
3284 /* Reduce to lowest terms. */
3285 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
3287 unsigned HOST_WIDE_INT ml_lo
= (mlow_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mlow_lo
>> 1);
3288 unsigned HOST_WIDE_INT mh_lo
= (mhigh_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mhigh_lo
>> 1);
3298 *post_shift_ptr
= post_shift
;
3300 if (n
< HOST_BITS_PER_WIDE_INT
)
3302 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
3303 *multiplier_ptr
= GEN_INT (mhigh_lo
& mask
);
3304 return mhigh_lo
>= mask
;
3308 *multiplier_ptr
= GEN_INT (mhigh_lo
);
3313 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3314 congruent to 1 (mod 2**N). */
3316 static unsigned HOST_WIDE_INT
3317 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
3319 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3321 /* The algorithm notes that the choice y = x satisfies
3322 x*y == 1 mod 2^3, since x is assumed odd.
3323 Each iteration doubles the number of bits of significance in y. */
3325 unsigned HOST_WIDE_INT mask
;
3326 unsigned HOST_WIDE_INT y
= x
;
3329 mask
= (n
== HOST_BITS_PER_WIDE_INT
3330 ? ~(unsigned HOST_WIDE_INT
) 0
3331 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
3335 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
3341 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3342 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3343 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3344 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3347 The result is put in TARGET if that is convenient.
3349 MODE is the mode of operation. */
3352 expand_mult_highpart_adjust (enum machine_mode mode
, rtx adj_operand
, rtx op0
,
3353 rtx op1
, rtx target
, int unsignedp
)
3356 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
3358 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3359 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
) - 1),
3361 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
3363 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3366 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
3367 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
) - 1),
3369 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
3370 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3376 /* Subroutine of expand_mult_highpart. Return the MODE high part of OP. */
3379 extract_high_half (enum machine_mode mode
, rtx op
)
3381 enum machine_mode wider_mode
;
3383 if (mode
== word_mode
)
3384 return gen_highpart (mode
, op
);
3386 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3388 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3389 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
3390 build_int_cst (NULL_TREE
, GET_MODE_BITSIZE (mode
)), 0, 1);
3391 return convert_modes (mode
, wider_mode
, op
, 0);
3394 /* Like expand_mult_highpart, but only consider using a multiplication
3395 optab. OP1 is an rtx for the constant operand. */
3398 expand_mult_highpart_optab (enum machine_mode mode
, rtx op0
, rtx op1
,
3399 rtx target
, int unsignedp
, int max_cost
)
3401 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
3402 enum machine_mode wider_mode
;
3406 bool speed
= optimize_insn_for_speed_p ();
3408 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3410 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3411 size
= GET_MODE_BITSIZE (mode
);
3413 /* Firstly, try using a multiplication insn that only generates the needed
3414 high part of the product, and in the sign flavor of unsignedp. */
3415 if (mul_highpart_cost
[speed
][mode
] < max_cost
)
3417 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
3418 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3419 unsignedp
, OPTAB_DIRECT
);
3424 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3425 Need to adjust the result after the multiplication. */
3426 if (size
- 1 < BITS_PER_WORD
3427 && (mul_highpart_cost
[speed
][mode
] + 2 * shift_cost
[speed
][mode
][size
-1]
3428 + 4 * add_cost
[speed
][mode
] < max_cost
))
3430 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
3431 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3432 unsignedp
, OPTAB_DIRECT
);
3434 /* We used the wrong signedness. Adjust the result. */
3435 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3439 /* Try widening multiplication. */
3440 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
3441 if (optab_handler (moptab
, wider_mode
) != CODE_FOR_nothing
3442 && mul_widen_cost
[speed
][wider_mode
] < max_cost
)
3444 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
3445 unsignedp
, OPTAB_WIDEN
);
3447 return extract_high_half (mode
, tem
);
3450 /* Try widening the mode and perform a non-widening multiplication. */
3451 if (optab_handler (smul_optab
, wider_mode
) != CODE_FOR_nothing
3452 && size
- 1 < BITS_PER_WORD
3453 && mul_cost
[speed
][wider_mode
] + shift_cost
[speed
][mode
][size
-1] < max_cost
)
3455 rtx insns
, wop0
, wop1
;
3457 /* We need to widen the operands, for example to ensure the
3458 constant multiplier is correctly sign or zero extended.
3459 Use a sequence to clean-up any instructions emitted by
3460 the conversions if things don't work out. */
3462 wop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
3463 wop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
3464 tem
= expand_binop (wider_mode
, smul_optab
, wop0
, wop1
, 0,
3465 unsignedp
, OPTAB_WIDEN
);
3466 insns
= get_insns ();
3472 return extract_high_half (mode
, tem
);
3476 /* Try widening multiplication of opposite signedness, and adjust. */
3477 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3478 if (optab_handler (moptab
, wider_mode
) != CODE_FOR_nothing
3479 && size
- 1 < BITS_PER_WORD
3480 && (mul_widen_cost
[speed
][wider_mode
] + 2 * shift_cost
[speed
][mode
][size
-1]
3481 + 4 * add_cost
[speed
][mode
] < max_cost
))
3483 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3484 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3487 tem
= extract_high_half (mode
, tem
);
3488 /* We used the wrong signedness. Adjust the result. */
3489 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3497 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3498 putting the high half of the result in TARGET if that is convenient,
3499 and return where the result is. If the operation can not be performed,
3502 MODE is the mode of operation and result.
3504 UNSIGNEDP nonzero means unsigned multiply.
3506 MAX_COST is the total allowed cost for the expanded RTL. */
3509 expand_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
3510 rtx target
, int unsignedp
, int max_cost
)
3512 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
3513 unsigned HOST_WIDE_INT cnst1
;
3515 bool sign_adjust
= false;
3516 enum mult_variant variant
;
3517 struct algorithm alg
;
3519 bool speed
= optimize_insn_for_speed_p ();
3521 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3522 /* We can't support modes wider than HOST_BITS_PER_INT. */
3523 gcc_assert (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
);
3525 cnst1
= INTVAL (op1
) & GET_MODE_MASK (mode
);
3527 /* We can't optimize modes wider than BITS_PER_WORD.
3528 ??? We might be able to perform double-word arithmetic if
3529 mode == word_mode, however all the cost calculations in
3530 synth_mult etc. assume single-word operations. */
3531 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3532 return expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3533 unsignedp
, max_cost
);
3535 extra_cost
= shift_cost
[speed
][mode
][GET_MODE_BITSIZE (mode
) - 1];
3537 /* Check whether we try to multiply by a negative constant. */
3538 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3541 extra_cost
+= add_cost
[speed
][mode
];
3544 /* See whether shift/add multiplication is cheap enough. */
3545 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3546 max_cost
- extra_cost
))
3548 /* See whether the specialized multiplication optabs are
3549 cheaper than the shift/add version. */
3550 tem
= expand_mult_highpart_optab (mode
, op0
, op1
, target
, unsignedp
,
3551 alg
.cost
.cost
+ extra_cost
);
3555 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3556 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3557 tem
= extract_high_half (mode
, tem
);
3559 /* Adjust result for signedness. */
3561 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3565 return expand_mult_highpart_optab (mode
, op0
, op1
, target
,
3566 unsignedp
, max_cost
);
3570 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3573 expand_smod_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3575 unsigned HOST_WIDE_INT masklow
, maskhigh
;
3576 rtx result
, temp
, shift
, label
;
3579 logd
= floor_log2 (d
);
3580 result
= gen_reg_rtx (mode
);
3582 /* Avoid conditional branches when they're expensive. */
3583 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3584 && optimize_insn_for_speed_p ())
3586 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3590 signmask
= force_reg (mode
, signmask
);
3591 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3592 shift
= GEN_INT (GET_MODE_BITSIZE (mode
) - logd
);
3594 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3595 which instruction sequence to use. If logical right shifts
3596 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3597 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3599 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3600 if (optab_handler (lshr_optab
, mode
) == CODE_FOR_nothing
3601 || rtx_cost (temp
, SET
, optimize_insn_for_speed_p ()) > COSTS_N_INSNS (2))
3603 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3604 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3605 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3606 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3607 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (masklow
),
3608 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3609 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3610 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3611 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3612 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3616 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3617 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3618 signmask
= force_reg (mode
, signmask
);
3620 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3621 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3622 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (masklow
),
3623 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3624 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3625 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3631 /* Mask contains the mode's signbit and the significant bits of the
3632 modulus. By including the signbit in the operation, many targets
3633 can avoid an explicit compare operation in the following comparison
3636 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3637 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3639 masklow
|= (HOST_WIDE_INT
) -1 << (GET_MODE_BITSIZE (mode
) - 1);
3643 maskhigh
= (HOST_WIDE_INT
) -1
3644 << (GET_MODE_BITSIZE (mode
) - HOST_BITS_PER_WIDE_INT
- 1);
3646 temp
= expand_binop (mode
, and_optab
, op0
,
3647 immed_double_const (masklow
, maskhigh
, mode
),
3648 result
, 1, OPTAB_LIB_WIDEN
);
3650 emit_move_insn (result
, temp
);
3652 label
= gen_label_rtx ();
3653 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
3655 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
3656 0, OPTAB_LIB_WIDEN
);
3657 masklow
= (HOST_WIDE_INT
) -1 << logd
;
3659 temp
= expand_binop (mode
, ior_optab
, temp
,
3660 immed_double_const (masklow
, maskhigh
, mode
),
3661 result
, 1, OPTAB_LIB_WIDEN
);
3662 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
3663 0, OPTAB_LIB_WIDEN
);
3665 emit_move_insn (result
, temp
);
3670 /* Expand signed division of OP0 by a power of two D in mode MODE.
3671 This routine is only called for positive values of D. */
3674 expand_sdiv_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3680 logd
= floor_log2 (d
);
3681 shift
= build_int_cst (NULL_TREE
, logd
);
3684 && BRANCH_COST (optimize_insn_for_speed_p (),
3687 temp
= gen_reg_rtx (mode
);
3688 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
3689 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3690 0, OPTAB_LIB_WIDEN
);
3691 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3694 #ifdef HAVE_conditional_move
3695 if (BRANCH_COST (optimize_insn_for_speed_p (), false)
3700 /* ??? emit_conditional_move forces a stack adjustment via
3701 compare_from_rtx so, if the sequence is discarded, it will
3702 be lost. Do it now instead. */
3703 do_pending_stack_adjust ();
3706 temp2
= copy_to_mode_reg (mode
, op0
);
3707 temp
= expand_binop (mode
, add_optab
, temp2
, GEN_INT (d
-1),
3708 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3709 temp
= force_reg (mode
, temp
);
3711 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3712 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
3713 mode
, temp
, temp2
, mode
, 0);
3716 rtx seq
= get_insns ();
3719 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, shift
, NULL_RTX
, 0);
3725 if (BRANCH_COST (optimize_insn_for_speed_p (),
3728 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
3730 temp
= gen_reg_rtx (mode
);
3731 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
3732 if (shift_cost
[optimize_insn_for_speed_p ()][mode
][ushift
] > COSTS_N_INSNS (1))
3733 temp
= expand_binop (mode
, and_optab
, temp
, GEN_INT (d
- 1),
3734 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3736 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
3737 build_int_cst (NULL_TREE
, ushift
),
3739 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3740 0, OPTAB_LIB_WIDEN
);
3741 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3744 label
= gen_label_rtx ();
3745 temp
= copy_to_mode_reg (mode
, op0
);
3746 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
3747 expand_inc (temp
, GEN_INT (d
- 1));
3749 return expand_shift (RSHIFT_EXPR
, mode
, temp
, shift
, NULL_RTX
, 0);
3752 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3753 if that is convenient, and returning where the result is.
3754 You may request either the quotient or the remainder as the result;
3755 specify REM_FLAG nonzero to get the remainder.
3757 CODE is the expression code for which kind of division this is;
3758 it controls how rounding is done. MODE is the machine mode to use.
3759 UNSIGNEDP nonzero means do unsigned division. */
3761 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3762 and then correct it by or'ing in missing high bits
3763 if result of ANDI is nonzero.
3764 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3765 This could optimize to a bfexts instruction.
3766 But C doesn't use these operations, so their optimizations are
3768 /* ??? For modulo, we don't actually need the highpart of the first product,
3769 the low part will do nicely. And for small divisors, the second multiply
3770 can also be a low-part only multiply or even be completely left out.
3771 E.g. to calculate the remainder of a division by 3 with a 32 bit
3772 multiply, multiply with 0x55555556 and extract the upper two bits;
3773 the result is exact for inputs up to 0x1fffffff.
3774 The input range can be reduced by using cross-sum rules.
3775 For odd divisors >= 3, the following table gives right shift counts
3776 so that if a number is shifted by an integer multiple of the given
3777 amount, the remainder stays the same:
3778 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3779 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3780 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3781 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3782 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3784 Cross-sum rules for even numbers can be derived by leaving as many bits
3785 to the right alone as the divisor has zeros to the right.
3786 E.g. if x is an unsigned 32 bit number:
3787 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3791 expand_divmod (int rem_flag
, enum tree_code code
, enum machine_mode mode
,
3792 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
3794 enum machine_mode compute_mode
;
3796 rtx quotient
= 0, remainder
= 0;
3800 optab optab1
, optab2
;
3801 int op1_is_constant
, op1_is_pow2
= 0;
3802 int max_cost
, extra_cost
;
3803 static HOST_WIDE_INT last_div_const
= 0;
3804 static HOST_WIDE_INT ext_op1
;
3805 bool speed
= optimize_insn_for_speed_p ();
3807 op1_is_constant
= CONST_INT_P (op1
);
3808 if (op1_is_constant
)
3810 ext_op1
= INTVAL (op1
);
3812 ext_op1
&= GET_MODE_MASK (mode
);
3813 op1_is_pow2
= ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1
)
3814 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1
))));
3818 This is the structure of expand_divmod:
3820 First comes code to fix up the operands so we can perform the operations
3821 correctly and efficiently.
3823 Second comes a switch statement with code specific for each rounding mode.
3824 For some special operands this code emits all RTL for the desired
3825 operation, for other cases, it generates only a quotient and stores it in
3826 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3827 to indicate that it has not done anything.
3829 Last comes code that finishes the operation. If QUOTIENT is set and
3830 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3831 QUOTIENT is not set, it is computed using trunc rounding.
3833 We try to generate special code for division and remainder when OP1 is a
3834 constant. If |OP1| = 2**n we can use shifts and some other fast
3835 operations. For other values of OP1, we compute a carefully selected
3836 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3839 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3840 half of the product. Different strategies for generating the product are
3841 implemented in expand_mult_highpart.
3843 If what we actually want is the remainder, we generate that by another
3844 by-constant multiplication and a subtraction. */
3846 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3847 code below will malfunction if we are, so check here and handle
3848 the special case if so. */
3849 if (op1
== const1_rtx
)
3850 return rem_flag
? const0_rtx
: op0
;
3852 /* When dividing by -1, we could get an overflow.
3853 negv_optab can handle overflows. */
3854 if (! unsignedp
&& op1
== constm1_rtx
)
3858 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
3859 ? negv_optab
: neg_optab
, op0
, target
, 0);
3863 /* Don't use the function value register as a target
3864 since we have to read it as well as write it,
3865 and function-inlining gets confused by this. */
3866 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3867 /* Don't clobber an operand while doing a multi-step calculation. */
3868 || ((rem_flag
|| op1_is_constant
)
3869 && (reg_mentioned_p (target
, op0
)
3870 || (MEM_P (op0
) && MEM_P (target
))))
3871 || reg_mentioned_p (target
, op1
)
3872 || (MEM_P (op1
) && MEM_P (target
))))
3875 /* Get the mode in which to perform this computation. Normally it will
3876 be MODE, but sometimes we can't do the desired operation in MODE.
3877 If so, pick a wider mode in which we can do the operation. Convert
3878 to that mode at the start to avoid repeated conversions.
3880 First see what operations we need. These depend on the expression
3881 we are evaluating. (We assume that divxx3 insns exist under the
3882 same conditions that modxx3 insns and that these insns don't normally
3883 fail. If these assumptions are not correct, we may generate less
3884 efficient code in some cases.)
3886 Then see if we find a mode in which we can open-code that operation
3887 (either a division, modulus, or shift). Finally, check for the smallest
3888 mode for which we can do the operation with a library call. */
3890 /* We might want to refine this now that we have division-by-constant
3891 optimization. Since expand_mult_highpart tries so many variants, it is
3892 not straightforward to generalize this. Maybe we should make an array
3893 of possible modes in init_expmed? Save this for GCC 2.7. */
3895 optab1
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3896 ? (unsignedp
? lshr_optab
: ashr_optab
)
3897 : (unsignedp
? udiv_optab
: sdiv_optab
));
3898 optab2
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3900 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
3902 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3903 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3904 if (optab_handler (optab1
, compute_mode
) != CODE_FOR_nothing
3905 || optab_handler (optab2
, compute_mode
) != CODE_FOR_nothing
)
3908 if (compute_mode
== VOIDmode
)
3909 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3910 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3911 if (optab_libfunc (optab1
, compute_mode
)
3912 || optab_libfunc (optab2
, compute_mode
))
3915 /* If we still couldn't find a mode, use MODE, but expand_binop will
3917 if (compute_mode
== VOIDmode
)
3918 compute_mode
= mode
;
3920 if (target
&& GET_MODE (target
) == compute_mode
)
3923 tquotient
= gen_reg_rtx (compute_mode
);
3925 size
= GET_MODE_BITSIZE (compute_mode
);
3927 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3928 (mode), and thereby get better code when OP1 is a constant. Do that
3929 later. It will require going over all usages of SIZE below. */
3930 size
= GET_MODE_BITSIZE (mode
);
3933 /* Only deduct something for a REM if the last divide done was
3934 for a different constant. Then set the constant of the last
3936 max_cost
= unsignedp
? udiv_cost
[speed
][compute_mode
] : sdiv_cost
[speed
][compute_mode
];
3937 if (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3938 && INTVAL (op1
) == last_div_const
))
3939 max_cost
-= mul_cost
[speed
][compute_mode
] + add_cost
[speed
][compute_mode
];
3941 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3943 /* Now convert to the best mode to use. */
3944 if (compute_mode
!= mode
)
3946 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3947 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3949 /* convert_modes may have placed op1 into a register, so we
3950 must recompute the following. */
3951 op1_is_constant
= CONST_INT_P (op1
);
3952 op1_is_pow2
= (op1_is_constant
3953 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3955 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
)))))) ;
3958 /* If one of the operands is a volatile MEM, copy it into a register. */
3960 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
3961 op0
= force_reg (compute_mode
, op0
);
3962 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
3963 op1
= force_reg (compute_mode
, op1
);
3965 /* If we need the remainder or if OP1 is constant, we need to
3966 put OP0 in a register in case it has any queued subexpressions. */
3967 if (rem_flag
|| op1_is_constant
)
3968 op0
= force_reg (compute_mode
, op0
);
3970 last
= get_last_insn ();
3972 /* Promote floor rounding to trunc rounding for unsigned operations. */
3975 if (code
== FLOOR_DIV_EXPR
)
3976 code
= TRUNC_DIV_EXPR
;
3977 if (code
== FLOOR_MOD_EXPR
)
3978 code
= TRUNC_MOD_EXPR
;
3979 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
3980 code
= TRUNC_DIV_EXPR
;
3983 if (op1
!= const0_rtx
)
3986 case TRUNC_MOD_EXPR
:
3987 case TRUNC_DIV_EXPR
:
3988 if (op1_is_constant
)
3992 unsigned HOST_WIDE_INT mh
;
3993 int pre_shift
, post_shift
;
3996 unsigned HOST_WIDE_INT d
= (INTVAL (op1
)
3997 & GET_MODE_MASK (compute_mode
));
3999 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4001 pre_shift
= floor_log2 (d
);
4005 = expand_binop (compute_mode
, and_optab
, op0
,
4006 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
4010 return gen_lowpart (mode
, remainder
);
4012 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4013 build_int_cst (NULL_TREE
,
4017 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4019 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
4021 /* Most significant bit of divisor is set; emit an scc
4023 quotient
= emit_store_flag_force (tquotient
, GEU
, op0
, op1
,
4024 compute_mode
, 1, 1);
4028 /* Find a suitable multiplier and right shift count
4029 instead of multiplying with D. */
4031 mh
= choose_multiplier (d
, size
, size
,
4032 &ml
, &post_shift
, &dummy
);
4034 /* If the suggested multiplier is more than SIZE bits,
4035 we can do better for even divisors, using an
4036 initial right shift. */
4037 if (mh
!= 0 && (d
& 1) == 0)
4039 pre_shift
= floor_log2 (d
& -d
);
4040 mh
= choose_multiplier (d
>> pre_shift
, size
,
4042 &ml
, &post_shift
, &dummy
);
4052 if (post_shift
- 1 >= BITS_PER_WORD
)
4056 = (shift_cost
[speed
][compute_mode
][post_shift
- 1]
4057 + shift_cost
[speed
][compute_mode
][1]
4058 + 2 * add_cost
[speed
][compute_mode
]);
4059 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
4061 max_cost
- extra_cost
);
4064 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
4067 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
4068 integer_one_node
, NULL_RTX
, 1);
4069 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
4072 quotient
= expand_shift
4073 (RSHIFT_EXPR
, compute_mode
, t4
,
4074 build_int_cst (NULL_TREE
, post_shift
- 1),
4081 if (pre_shift
>= BITS_PER_WORD
4082 || post_shift
>= BITS_PER_WORD
)
4086 (RSHIFT_EXPR
, compute_mode
, op0
,
4087 build_int_cst (NULL_TREE
, pre_shift
),
4090 = (shift_cost
[speed
][compute_mode
][pre_shift
]
4091 + shift_cost
[speed
][compute_mode
][post_shift
]);
4092 t2
= expand_mult_highpart (compute_mode
, t1
, ml
,
4094 max_cost
- extra_cost
);
4097 quotient
= expand_shift
4098 (RSHIFT_EXPR
, compute_mode
, t2
,
4099 build_int_cst (NULL_TREE
, post_shift
),
4104 else /* Too wide mode to use tricky code */
4107 insn
= get_last_insn ();
4109 && (set
= single_set (insn
)) != 0
4110 && SET_DEST (set
) == quotient
)
4111 set_unique_reg_note (insn
,
4113 gen_rtx_UDIV (compute_mode
, op0
, op1
));
4115 else /* TRUNC_DIV, signed */
4117 unsigned HOST_WIDE_INT ml
;
4118 int lgup
, post_shift
;
4120 HOST_WIDE_INT d
= INTVAL (op1
);
4121 unsigned HOST_WIDE_INT abs_d
;
4123 /* Since d might be INT_MIN, we have to cast to
4124 unsigned HOST_WIDE_INT before negating to avoid
4125 undefined signed overflow. */
4127 ? (unsigned HOST_WIDE_INT
) d
4128 : - (unsigned HOST_WIDE_INT
) d
);
4130 /* n rem d = n rem -d */
4131 if (rem_flag
&& d
< 0)
4134 op1
= gen_int_mode (abs_d
, compute_mode
);
4140 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
4142 else if (HOST_BITS_PER_WIDE_INT
>= size
4143 && abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4145 /* This case is not handled correctly below. */
4146 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
4147 compute_mode
, 1, 1);
4151 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
4152 && (rem_flag
? smod_pow2_cheap
[speed
][compute_mode
]
4153 : sdiv_pow2_cheap
[speed
][compute_mode
])
4154 /* We assume that cheap metric is true if the
4155 optab has an expander for this mode. */
4156 && ((optab_handler ((rem_flag
? smod_optab
4159 != CODE_FOR_nothing
)
4160 || (optab_handler (sdivmod_optab
,
4162 != CODE_FOR_nothing
)))
4164 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
4168 remainder
= expand_smod_pow2 (compute_mode
, op0
, d
);
4170 return gen_lowpart (mode
, remainder
);
4173 if (sdiv_pow2_cheap
[speed
][compute_mode
]
4174 && ((optab_handler (sdiv_optab
, compute_mode
)
4175 != CODE_FOR_nothing
)
4176 || (optab_handler (sdivmod_optab
, compute_mode
)
4177 != CODE_FOR_nothing
)))
4178 quotient
= expand_divmod (0, TRUNC_DIV_EXPR
,
4180 gen_int_mode (abs_d
,
4184 quotient
= expand_sdiv_pow2 (compute_mode
, op0
, abs_d
);
4186 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4187 negate the quotient. */
4190 insn
= get_last_insn ();
4192 && (set
= single_set (insn
)) != 0
4193 && SET_DEST (set
) == quotient
4194 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
4195 << (HOST_BITS_PER_WIDE_INT
- 1)))
4196 set_unique_reg_note (insn
,
4198 gen_rtx_DIV (compute_mode
,
4205 quotient
= expand_unop (compute_mode
, neg_optab
,
4206 quotient
, quotient
, 0);
4209 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4211 choose_multiplier (abs_d
, size
, size
- 1,
4212 &mlr
, &post_shift
, &lgup
);
4213 ml
= (unsigned HOST_WIDE_INT
) INTVAL (mlr
);
4214 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4218 if (post_shift
>= BITS_PER_WORD
4219 || size
- 1 >= BITS_PER_WORD
)
4222 extra_cost
= (shift_cost
[speed
][compute_mode
][post_shift
]
4223 + shift_cost
[speed
][compute_mode
][size
- 1]
4224 + add_cost
[speed
][compute_mode
]);
4225 t1
= expand_mult_highpart (compute_mode
, op0
, mlr
,
4227 max_cost
- extra_cost
);
4231 (RSHIFT_EXPR
, compute_mode
, t1
,
4232 build_int_cst (NULL_TREE
, post_shift
),
4235 (RSHIFT_EXPR
, compute_mode
, op0
,
4236 build_int_cst (NULL_TREE
, size
- 1),
4240 = force_operand (gen_rtx_MINUS (compute_mode
,
4245 = force_operand (gen_rtx_MINUS (compute_mode
,
4253 if (post_shift
>= BITS_PER_WORD
4254 || size
- 1 >= BITS_PER_WORD
)
4257 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
4258 mlr
= gen_int_mode (ml
, compute_mode
);
4259 extra_cost
= (shift_cost
[speed
][compute_mode
][post_shift
]
4260 + shift_cost
[speed
][compute_mode
][size
- 1]
4261 + 2 * add_cost
[speed
][compute_mode
]);
4262 t1
= expand_mult_highpart (compute_mode
, op0
, mlr
,
4264 max_cost
- extra_cost
);
4267 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
4271 (RSHIFT_EXPR
, compute_mode
, t2
,
4272 build_int_cst (NULL_TREE
, post_shift
),
4275 (RSHIFT_EXPR
, compute_mode
, op0
,
4276 build_int_cst (NULL_TREE
, size
- 1),
4280 = force_operand (gen_rtx_MINUS (compute_mode
,
4285 = force_operand (gen_rtx_MINUS (compute_mode
,
4290 else /* Too wide mode to use tricky code */
4293 insn
= get_last_insn ();
4295 && (set
= single_set (insn
)) != 0
4296 && SET_DEST (set
) == quotient
)
4297 set_unique_reg_note (insn
,
4299 gen_rtx_DIV (compute_mode
, op0
, op1
));
4304 delete_insns_since (last
);
4307 case FLOOR_DIV_EXPR
:
4308 case FLOOR_MOD_EXPR
:
4309 /* We will come here only for signed operations. */
4310 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4312 unsigned HOST_WIDE_INT mh
;
4313 int pre_shift
, lgup
, post_shift
;
4314 HOST_WIDE_INT d
= INTVAL (op1
);
4319 /* We could just as easily deal with negative constants here,
4320 but it does not seem worth the trouble for GCC 2.6. */
4321 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4323 pre_shift
= floor_log2 (d
);
4326 remainder
= expand_binop (compute_mode
, and_optab
, op0
,
4327 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
4328 remainder
, 0, OPTAB_LIB_WIDEN
);
4330 return gen_lowpart (mode
, remainder
);
4332 quotient
= expand_shift
4333 (RSHIFT_EXPR
, compute_mode
, op0
,
4334 build_int_cst (NULL_TREE
, pre_shift
),
4341 mh
= choose_multiplier (d
, size
, size
- 1,
4342 &ml
, &post_shift
, &lgup
);
4345 if (post_shift
< BITS_PER_WORD
4346 && size
- 1 < BITS_PER_WORD
)
4349 (RSHIFT_EXPR
, compute_mode
, op0
,
4350 build_int_cst (NULL_TREE
, size
- 1),
4352 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
4353 NULL_RTX
, 0, OPTAB_WIDEN
);
4354 extra_cost
= (shift_cost
[speed
][compute_mode
][post_shift
]
4355 + shift_cost
[speed
][compute_mode
][size
- 1]
4356 + 2 * add_cost
[speed
][compute_mode
]);
4357 t3
= expand_mult_highpart (compute_mode
, t2
, ml
,
4359 max_cost
- extra_cost
);
4363 (RSHIFT_EXPR
, compute_mode
, t3
,
4364 build_int_cst (NULL_TREE
, post_shift
),
4366 quotient
= expand_binop (compute_mode
, xor_optab
,
4367 t4
, t1
, tquotient
, 0,
4375 rtx nsign
, t1
, t2
, t3
, t4
;
4376 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
4377 op0
, constm1_rtx
), NULL_RTX
);
4378 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
4380 nsign
= expand_shift
4381 (RSHIFT_EXPR
, compute_mode
, t2
,
4382 build_int_cst (NULL_TREE
, size
- 1),
4384 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
4386 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
4391 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
4393 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4402 delete_insns_since (last
);
4404 /* Try using an instruction that produces both the quotient and
4405 remainder, using truncation. We can easily compensate the quotient
4406 or remainder to get floor rounding, once we have the remainder.
4407 Notice that we compute also the final remainder value here,
4408 and return the result right away. */
4409 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4410 target
= gen_reg_rtx (compute_mode
);
4415 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4416 quotient
= gen_reg_rtx (compute_mode
);
4421 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4422 remainder
= gen_reg_rtx (compute_mode
);
4425 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
4426 quotient
, remainder
, 0))
4428 /* This could be computed with a branch-less sequence.
4429 Save that for later. */
4431 rtx label
= gen_label_rtx ();
4432 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
4433 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4434 NULL_RTX
, 0, OPTAB_WIDEN
);
4435 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
4436 expand_dec (quotient
, const1_rtx
);
4437 expand_inc (remainder
, op1
);
4439 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4442 /* No luck with division elimination or divmod. Have to do it
4443 by conditionally adjusting op0 *and* the result. */
4445 rtx label1
, label2
, label3
, label4
, label5
;
4449 quotient
= gen_reg_rtx (compute_mode
);
4450 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4451 label1
= gen_label_rtx ();
4452 label2
= gen_label_rtx ();
4453 label3
= gen_label_rtx ();
4454 label4
= gen_label_rtx ();
4455 label5
= gen_label_rtx ();
4456 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4457 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
4458 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4459 quotient
, 0, OPTAB_LIB_WIDEN
);
4460 if (tem
!= quotient
)
4461 emit_move_insn (quotient
, tem
);
4462 emit_jump_insn (gen_jump (label5
));
4464 emit_label (label1
);
4465 expand_inc (adjusted_op0
, const1_rtx
);
4466 emit_jump_insn (gen_jump (label4
));
4468 emit_label (label2
);
4469 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
4470 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4471 quotient
, 0, OPTAB_LIB_WIDEN
);
4472 if (tem
!= quotient
)
4473 emit_move_insn (quotient
, tem
);
4474 emit_jump_insn (gen_jump (label5
));
4476 emit_label (label3
);
4477 expand_dec (adjusted_op0
, const1_rtx
);
4478 emit_label (label4
);
4479 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4480 quotient
, 0, OPTAB_LIB_WIDEN
);
4481 if (tem
!= quotient
)
4482 emit_move_insn (quotient
, tem
);
4483 expand_dec (quotient
, const1_rtx
);
4484 emit_label (label5
);
4492 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
4495 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4496 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4497 build_int_cst (NULL_TREE
, floor_log2 (d
)),
4499 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4501 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4502 t3
= gen_reg_rtx (compute_mode
);
4503 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4504 compute_mode
, 1, 1);
4508 lab
= gen_label_rtx ();
4509 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4510 expand_inc (t1
, const1_rtx
);
4515 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4521 /* Try using an instruction that produces both the quotient and
4522 remainder, using truncation. We can easily compensate the
4523 quotient or remainder to get ceiling rounding, once we have the
4524 remainder. Notice that we compute also the final remainder
4525 value here, and return the result right away. */
4526 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4527 target
= gen_reg_rtx (compute_mode
);
4531 remainder
= (REG_P (target
)
4532 ? target
: gen_reg_rtx (compute_mode
));
4533 quotient
= gen_reg_rtx (compute_mode
);
4537 quotient
= (REG_P (target
)
4538 ? target
: gen_reg_rtx (compute_mode
));
4539 remainder
= gen_reg_rtx (compute_mode
);
4542 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4545 /* This could be computed with a branch-less sequence.
4546 Save that for later. */
4547 rtx label
= gen_label_rtx ();
4548 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4549 compute_mode
, label
);
4550 expand_inc (quotient
, const1_rtx
);
4551 expand_dec (remainder
, op1
);
4553 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4556 /* No luck with division elimination or divmod. Have to do it
4557 by conditionally adjusting op0 *and* the result. */
4560 rtx adjusted_op0
, tem
;
4562 quotient
= gen_reg_rtx (compute_mode
);
4563 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4564 label1
= gen_label_rtx ();
4565 label2
= gen_label_rtx ();
4566 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4567 compute_mode
, label1
);
4568 emit_move_insn (quotient
, const0_rtx
);
4569 emit_jump_insn (gen_jump (label2
));
4571 emit_label (label1
);
4572 expand_dec (adjusted_op0
, const1_rtx
);
4573 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4574 quotient
, 1, OPTAB_LIB_WIDEN
);
4575 if (tem
!= quotient
)
4576 emit_move_insn (quotient
, tem
);
4577 expand_inc (quotient
, const1_rtx
);
4578 emit_label (label2
);
4583 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4584 && INTVAL (op1
) >= 0)
4586 /* This is extremely similar to the code for the unsigned case
4587 above. For 2.7 we should merge these variants, but for
4588 2.6.1 I don't want to touch the code for unsigned since that
4589 get used in C. The signed case will only be used by other
4593 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4594 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4595 build_int_cst (NULL_TREE
, floor_log2 (d
)),
4597 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4599 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4600 t3
= gen_reg_rtx (compute_mode
);
4601 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4602 compute_mode
, 1, 1);
4606 lab
= gen_label_rtx ();
4607 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4608 expand_inc (t1
, const1_rtx
);
4613 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4619 /* Try using an instruction that produces both the quotient and
4620 remainder, using truncation. We can easily compensate the
4621 quotient or remainder to get ceiling rounding, once we have the
4622 remainder. Notice that we compute also the final remainder
4623 value here, and return the result right away. */
4624 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4625 target
= gen_reg_rtx (compute_mode
);
4628 remainder
= (REG_P (target
)
4629 ? target
: gen_reg_rtx (compute_mode
));
4630 quotient
= gen_reg_rtx (compute_mode
);
4634 quotient
= (REG_P (target
)
4635 ? target
: gen_reg_rtx (compute_mode
));
4636 remainder
= gen_reg_rtx (compute_mode
);
4639 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4642 /* This could be computed with a branch-less sequence.
4643 Save that for later. */
4645 rtx label
= gen_label_rtx ();
4646 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4647 compute_mode
, label
);
4648 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4649 NULL_RTX
, 0, OPTAB_WIDEN
);
4650 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4651 expand_inc (quotient
, const1_rtx
);
4652 expand_dec (remainder
, op1
);
4654 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4657 /* No luck with division elimination or divmod. Have to do it
4658 by conditionally adjusting op0 *and* the result. */
4660 rtx label1
, label2
, label3
, label4
, label5
;
4664 quotient
= gen_reg_rtx (compute_mode
);
4665 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4666 label1
= gen_label_rtx ();
4667 label2
= gen_label_rtx ();
4668 label3
= gen_label_rtx ();
4669 label4
= gen_label_rtx ();
4670 label5
= gen_label_rtx ();
4671 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4672 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
4673 compute_mode
, label1
);
4674 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4675 quotient
, 0, OPTAB_LIB_WIDEN
);
4676 if (tem
!= quotient
)
4677 emit_move_insn (quotient
, tem
);
4678 emit_jump_insn (gen_jump (label5
));
4680 emit_label (label1
);
4681 expand_dec (adjusted_op0
, const1_rtx
);
4682 emit_jump_insn (gen_jump (label4
));
4684 emit_label (label2
);
4685 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
4686 compute_mode
, label3
);
4687 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4688 quotient
, 0, OPTAB_LIB_WIDEN
);
4689 if (tem
!= quotient
)
4690 emit_move_insn (quotient
, tem
);
4691 emit_jump_insn (gen_jump (label5
));
4693 emit_label (label3
);
4694 expand_inc (adjusted_op0
, const1_rtx
);
4695 emit_label (label4
);
4696 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4697 quotient
, 0, OPTAB_LIB_WIDEN
);
4698 if (tem
!= quotient
)
4699 emit_move_insn (quotient
, tem
);
4700 expand_inc (quotient
, const1_rtx
);
4701 emit_label (label5
);
4706 case EXACT_DIV_EXPR
:
4707 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4709 HOST_WIDE_INT d
= INTVAL (op1
);
4710 unsigned HOST_WIDE_INT ml
;
4714 pre_shift
= floor_log2 (d
& -d
);
4715 ml
= invert_mod2n (d
>> pre_shift
, size
);
4716 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4717 build_int_cst (NULL_TREE
, pre_shift
),
4718 NULL_RTX
, unsignedp
);
4719 quotient
= expand_mult (compute_mode
, t1
,
4720 gen_int_mode (ml
, compute_mode
),
4723 insn
= get_last_insn ();
4724 set_unique_reg_note (insn
,
4726 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
4732 case ROUND_DIV_EXPR
:
4733 case ROUND_MOD_EXPR
:
4738 label
= gen_label_rtx ();
4739 quotient
= gen_reg_rtx (compute_mode
);
4740 remainder
= gen_reg_rtx (compute_mode
);
4741 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
4744 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
4745 quotient
, 1, OPTAB_LIB_WIDEN
);
4746 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
4747 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4748 remainder
, 1, OPTAB_LIB_WIDEN
);
4750 tem
= plus_constant (op1
, -1);
4751 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4752 integer_one_node
, NULL_RTX
, 1);
4753 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
4754 expand_inc (quotient
, const1_rtx
);
4755 expand_dec (remainder
, op1
);
4760 rtx abs_rem
, abs_op1
, tem
, mask
;
4762 label
= gen_label_rtx ();
4763 quotient
= gen_reg_rtx (compute_mode
);
4764 remainder
= gen_reg_rtx (compute_mode
);
4765 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
4768 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
4769 quotient
, 0, OPTAB_LIB_WIDEN
);
4770 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
4771 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4772 remainder
, 0, OPTAB_LIB_WIDEN
);
4774 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
4775 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
4776 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
4777 integer_one_node
, NULL_RTX
, 1);
4778 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
4779 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4780 NULL_RTX
, 0, OPTAB_WIDEN
);
4781 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4782 build_int_cst (NULL_TREE
, size
- 1),
4784 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
4785 NULL_RTX
, 0, OPTAB_WIDEN
);
4786 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4787 NULL_RTX
, 0, OPTAB_WIDEN
);
4788 expand_inc (quotient
, tem
);
4789 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
4790 NULL_RTX
, 0, OPTAB_WIDEN
);
4791 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4792 NULL_RTX
, 0, OPTAB_WIDEN
);
4793 expand_dec (remainder
, tem
);
4796 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4804 if (target
&& GET_MODE (target
) != compute_mode
)
4809 /* Try to produce the remainder without producing the quotient.
4810 If we seem to have a divmod pattern that does not require widening,
4811 don't try widening here. We should really have a WIDEN argument
4812 to expand_twoval_binop, since what we'd really like to do here is
4813 1) try a mod insn in compute_mode
4814 2) try a divmod insn in compute_mode
4815 3) try a div insn in compute_mode and multiply-subtract to get
4817 4) try the same things with widening allowed. */
4819 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4822 ((optab_handler (optab2
, compute_mode
)
4823 != CODE_FOR_nothing
)
4824 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4827 /* No luck there. Can we do remainder and divide at once
4828 without a library call? */
4829 remainder
= gen_reg_rtx (compute_mode
);
4830 if (! expand_twoval_binop ((unsignedp
4834 NULL_RTX
, remainder
, unsignedp
))
4839 return gen_lowpart (mode
, remainder
);
4842 /* Produce the quotient. Try a quotient insn, but not a library call.
4843 If we have a divmod in this mode, use it in preference to widening
4844 the div (for this test we assume it will not fail). Note that optab2
4845 is set to the one of the two optabs that the call below will use. */
4847 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
4848 op0
, op1
, rem_flag
? NULL_RTX
: target
,
4850 ((optab_handler (optab2
, compute_mode
)
4851 != CODE_FOR_nothing
)
4852 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4856 /* No luck there. Try a quotient-and-remainder insn,
4857 keeping the quotient alone. */
4858 quotient
= gen_reg_rtx (compute_mode
);
4859 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
4861 quotient
, NULL_RTX
, unsignedp
))
4865 /* Still no luck. If we are not computing the remainder,
4866 use a library call for the quotient. */
4867 quotient
= sign_expand_binop (compute_mode
,
4868 udiv_optab
, sdiv_optab
,
4870 unsignedp
, OPTAB_LIB_WIDEN
);
4877 if (target
&& GET_MODE (target
) != compute_mode
)
4882 /* No divide instruction either. Use library for remainder. */
4883 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4885 unsignedp
, OPTAB_LIB_WIDEN
);
4886 /* No remainder function. Try a quotient-and-remainder
4887 function, keeping the remainder. */
4890 remainder
= gen_reg_rtx (compute_mode
);
4891 if (!expand_twoval_binop_libfunc
4892 (unsignedp
? udivmod_optab
: sdivmod_optab
,
4894 NULL_RTX
, remainder
,
4895 unsignedp
? UMOD
: MOD
))
4896 remainder
= NULL_RTX
;
4901 /* We divided. Now finish doing X - Y * (X / Y). */
4902 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4903 NULL_RTX
, unsignedp
);
4904 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4905 remainder
, target
, unsignedp
,
4910 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4913 /* Return a tree node with data type TYPE, describing the value of X.
4914 Usually this is an VAR_DECL, if there is no obvious better choice.
4915 X may be an expression, however we only support those expressions
4916 generated by loop.c. */
4919 make_tree (tree type
, rtx x
)
4923 switch (GET_CODE (x
))
4927 HOST_WIDE_INT hi
= 0;
4930 && !(TYPE_UNSIGNED (type
)
4931 && (GET_MODE_BITSIZE (TYPE_MODE (type
))
4932 < HOST_BITS_PER_WIDE_INT
)))
4935 t
= build_int_cst_wide (type
, INTVAL (x
), hi
);
4941 if (GET_MODE (x
) == VOIDmode
)
4942 t
= build_int_cst_wide (type
,
4943 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4948 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4949 t
= build_real (type
, d
);
4956 int units
= CONST_VECTOR_NUNITS (x
);
4957 tree itype
= TREE_TYPE (type
);
4962 /* Build a tree with vector elements. */
4963 for (i
= units
- 1; i
>= 0; --i
)
4965 rtx elt
= CONST_VECTOR_ELT (x
, i
);
4966 t
= tree_cons (NULL_TREE
, make_tree (itype
, elt
), t
);
4969 return build_vector (type
, t
);
4973 return fold_build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4974 make_tree (type
, XEXP (x
, 1)));
4977 return fold_build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4978 make_tree (type
, XEXP (x
, 1)));
4981 return fold_build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0)));
4984 return fold_build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4985 make_tree (type
, XEXP (x
, 1)));
4988 return fold_build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4989 make_tree (type
, XEXP (x
, 1)));
4992 t
= unsigned_type_for (type
);
4993 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
4994 make_tree (t
, XEXP (x
, 0)),
4995 make_tree (type
, XEXP (x
, 1))));
4998 t
= signed_type_for (type
);
4999 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5000 make_tree (t
, XEXP (x
, 0)),
5001 make_tree (type
, XEXP (x
, 1))));
5004 if (TREE_CODE (type
) != REAL_TYPE
)
5005 t
= signed_type_for (type
);
5009 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5010 make_tree (t
, XEXP (x
, 0)),
5011 make_tree (t
, XEXP (x
, 1))));
5013 t
= unsigned_type_for (type
);
5014 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5015 make_tree (t
, XEXP (x
, 0)),
5016 make_tree (t
, XEXP (x
, 1))));
5020 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
5021 GET_CODE (x
) == ZERO_EXTEND
);
5022 return fold_convert (type
, make_tree (t
, XEXP (x
, 0)));
5025 return make_tree (type
, XEXP (x
, 0));
5028 t
= SYMBOL_REF_DECL (x
);
5030 return fold_convert (type
, build_fold_addr_expr (t
));
5031 /* else fall through. */
5034 t
= build_decl (RTL_LOCATION (x
), VAR_DECL
, NULL_TREE
, type
);
5036 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5037 address mode to pointer mode. */
5038 if (POINTER_TYPE_P (type
))
5039 x
= convert_memory_address_addr_space
5040 (TYPE_MODE (type
), x
, TYPE_ADDR_SPACE (TREE_TYPE (type
)));
5042 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5043 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5044 t
->decl_with_rtl
.rtl
= x
;
5050 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5051 and returning TARGET.
5053 If TARGET is 0, a pseudo-register or constant is returned. */
5056 expand_and (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
5060 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
5061 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
5063 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
5067 else if (tem
!= target
)
5068 emit_move_insn (target
, tem
);
5072 /* Helper function for emit_store_flag. */
5074 emit_cstore (rtx target
, enum insn_code icode
, enum rtx_code code
,
5075 enum machine_mode mode
, enum machine_mode compare_mode
,
5076 int unsignedp
, rtx x
, rtx y
, int normalizep
,
5077 enum machine_mode target_mode
)
5079 rtx op0
, last
, comparison
, subtarget
, pattern
;
5080 enum machine_mode result_mode
= insn_data
[(int) icode
].operand
[0].mode
;
5082 last
= get_last_insn ();
5083 x
= prepare_operand (icode
, x
, 2, mode
, compare_mode
, unsignedp
);
5084 y
= prepare_operand (icode
, y
, 3, mode
, compare_mode
, unsignedp
);
5085 comparison
= gen_rtx_fmt_ee (code
, result_mode
, x
, y
);
5087 || !insn_data
[icode
].operand
[2].predicate
5088 (x
, insn_data
[icode
].operand
[2].mode
)
5089 || !insn_data
[icode
].operand
[3].predicate
5090 (y
, insn_data
[icode
].operand
[3].mode
)
5091 || !insn_data
[icode
].operand
[1].predicate (comparison
, VOIDmode
))
5093 delete_insns_since (last
);
5097 if (target_mode
== VOIDmode
)
5098 target_mode
= result_mode
;
5100 target
= gen_reg_rtx (target_mode
);
5103 || !(insn_data
[(int) icode
].operand
[0].predicate (target
, result_mode
)))
5104 subtarget
= gen_reg_rtx (result_mode
);
5108 pattern
= GEN_FCN (icode
) (subtarget
, comparison
, x
, y
);
5111 emit_insn (pattern
);
5113 /* If we are converting to a wider mode, first convert to
5114 TARGET_MODE, then normalize. This produces better combining
5115 opportunities on machines that have a SIGN_EXTRACT when we are
5116 testing a single bit. This mostly benefits the 68k.
5118 If STORE_FLAG_VALUE does not have the sign bit set when
5119 interpreted in MODE, we can do this conversion as unsigned, which
5120 is usually more efficient. */
5121 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (result_mode
))
5123 convert_move (target
, subtarget
,
5124 (GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
)
5125 && 0 == (STORE_FLAG_VALUE
5126 & ((HOST_WIDE_INT
) 1
5127 << (GET_MODE_BITSIZE (result_mode
) -1))));
5129 result_mode
= target_mode
;
5134 /* If we want to keep subexpressions around, don't reuse our last
5139 /* Now normalize to the proper value in MODE. Sometimes we don't
5140 have to do anything. */
5141 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
5143 /* STORE_FLAG_VALUE might be the most negative number, so write
5144 the comparison this way to avoid a compiler-time warning. */
5145 else if (- normalizep
== STORE_FLAG_VALUE
)
5146 op0
= expand_unop (result_mode
, neg_optab
, op0
, subtarget
, 0);
5148 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5149 it hard to use a value of just the sign bit due to ANSI integer
5150 constant typing rules. */
5151 else if (GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
5152 && (STORE_FLAG_VALUE
5153 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (result_mode
) - 1))))
5154 op0
= expand_shift (RSHIFT_EXPR
, result_mode
, op0
,
5155 size_int (GET_MODE_BITSIZE (result_mode
) - 1), subtarget
,
5159 gcc_assert (STORE_FLAG_VALUE
& 1);
5161 op0
= expand_and (result_mode
, op0
, const1_rtx
, subtarget
);
5162 if (normalizep
== -1)
5163 op0
= expand_unop (result_mode
, neg_optab
, op0
, op0
, 0);
5166 /* If we were converting to a smaller mode, do the conversion now. */
5167 if (target_mode
!= result_mode
)
5169 convert_move (target
, op0
, 0);
5177 /* A subroutine of emit_store_flag only including "tricks" that do not
5178 need a recursive call. These are kept separate to avoid infinite
5182 emit_store_flag_1 (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5183 enum machine_mode mode
, int unsignedp
, int normalizep
,
5184 enum machine_mode target_mode
)
5187 enum insn_code icode
;
5188 enum machine_mode compare_mode
;
5189 enum mode_class mclass
;
5190 enum rtx_code scode
;
5194 code
= unsigned_condition (code
);
5195 scode
= swap_condition (code
);
5197 /* If one operand is constant, make it the second one. Only do this
5198 if the other operand is not constant as well. */
5200 if (swap_commutative_operands_p (op0
, op1
))
5205 code
= swap_condition (code
);
5208 if (mode
== VOIDmode
)
5209 mode
= GET_MODE (op0
);
5211 /* For some comparisons with 1 and -1, we can convert this to
5212 comparisons with zero. This will often produce more opportunities for
5213 store-flag insns. */
5218 if (op1
== const1_rtx
)
5219 op1
= const0_rtx
, code
= LE
;
5222 if (op1
== constm1_rtx
)
5223 op1
= const0_rtx
, code
= LT
;
5226 if (op1
== const1_rtx
)
5227 op1
= const0_rtx
, code
= GT
;
5230 if (op1
== constm1_rtx
)
5231 op1
= const0_rtx
, code
= GE
;
5234 if (op1
== const1_rtx
)
5235 op1
= const0_rtx
, code
= NE
;
5238 if (op1
== const1_rtx
)
5239 op1
= const0_rtx
, code
= EQ
;
5245 /* If we are comparing a double-word integer with zero or -1, we can
5246 convert the comparison into one involving a single word. */
5247 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
5248 && GET_MODE_CLASS (mode
) == MODE_INT
5249 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
5251 if ((code
== EQ
|| code
== NE
)
5252 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
5256 /* Do a logical OR or AND of the two words and compare the
5258 op00
= simplify_gen_subreg (word_mode
, op0
, mode
, 0);
5259 op01
= simplify_gen_subreg (word_mode
, op0
, mode
, UNITS_PER_WORD
);
5260 tem
= expand_binop (word_mode
,
5261 op1
== const0_rtx
? ior_optab
: and_optab
,
5262 op00
, op01
, NULL_RTX
, unsignedp
,
5266 tem
= emit_store_flag (NULL_RTX
, code
, tem
, op1
, word_mode
,
5267 unsignedp
, normalizep
);
5269 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
5273 /* If testing the sign bit, can just test on high word. */
5274 op0h
= simplify_gen_subreg (word_mode
, op0
, mode
,
5275 subreg_highpart_offset (word_mode
,
5277 tem
= emit_store_flag (NULL_RTX
, code
, op0h
, op1
, word_mode
,
5278 unsignedp
, normalizep
);
5285 if (target_mode
== VOIDmode
|| GET_MODE (tem
) == target_mode
)
5288 target
= gen_reg_rtx (target_mode
);
5290 convert_move (target
, tem
,
5291 0 == ((normalizep
? normalizep
: STORE_FLAG_VALUE
)
5292 & ((HOST_WIDE_INT
) 1
5293 << (GET_MODE_BITSIZE (word_mode
) -1))));
5298 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5299 complement of A (for GE) and shifting the sign bit to the low bit. */
5300 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
5301 && GET_MODE_CLASS (mode
) == MODE_INT
5302 && (normalizep
|| STORE_FLAG_VALUE
== 1
5303 || (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5304 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5305 == ((unsigned HOST_WIDE_INT
) 1
5306 << (GET_MODE_BITSIZE (mode
) - 1))))))
5313 /* If the result is to be wider than OP0, it is best to convert it
5314 first. If it is to be narrower, it is *incorrect* to convert it
5316 else if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
5318 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5322 if (target_mode
!= mode
)
5326 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
5327 ((STORE_FLAG_VALUE
== 1 || normalizep
)
5328 ? 0 : subtarget
), 0);
5330 if (STORE_FLAG_VALUE
== 1 || normalizep
)
5331 /* If we are supposed to produce a 0/1 value, we want to do
5332 a logical shift from the sign bit to the low-order bit; for
5333 a -1/0 value, we do an arithmetic shift. */
5334 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5335 size_int (GET_MODE_BITSIZE (mode
) - 1),
5336 subtarget
, normalizep
!= -1);
5338 if (mode
!= target_mode
)
5339 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5344 mclass
= GET_MODE_CLASS (mode
);
5345 for (compare_mode
= mode
; compare_mode
!= VOIDmode
;
5346 compare_mode
= GET_MODE_WIDER_MODE (compare_mode
))
5348 enum machine_mode optab_mode
= mclass
== MODE_CC
? CCmode
: compare_mode
;
5349 icode
= optab_handler (cstore_optab
, optab_mode
);
5350 if (icode
!= CODE_FOR_nothing
)
5352 do_pending_stack_adjust ();
5353 tem
= emit_cstore (target
, icode
, code
, mode
, compare_mode
,
5354 unsignedp
, op0
, op1
, normalizep
, target_mode
);
5358 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5360 tem
= emit_cstore (target
, icode
, scode
, mode
, compare_mode
,
5361 unsignedp
, op1
, op0
, normalizep
, target_mode
);
5372 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5373 and storing in TARGET. Normally return TARGET.
5374 Return 0 if that cannot be done.
5376 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5377 it is VOIDmode, they cannot both be CONST_INT.
5379 UNSIGNEDP is for the case where we have to widen the operands
5380 to perform the operation. It says to use zero-extension.
5382 NORMALIZEP is 1 if we should convert the result to be either zero
5383 or one. Normalize is -1 if we should convert the result to be
5384 either zero or -1. If NORMALIZEP is zero, the result will be left
5385 "raw" out of the scc insn. */
5388 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5389 enum machine_mode mode
, int unsignedp
, int normalizep
)
5391 enum machine_mode target_mode
= target
? GET_MODE (target
) : VOIDmode
;
5392 enum rtx_code rcode
;
5394 rtx tem
, last
, trueval
;
5396 tem
= emit_store_flag_1 (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
,
5401 /* If we reached here, we can't do this with a scc insn, however there
5402 are some comparisons that can be done in other ways. Don't do any
5403 of these cases if branches are very cheap. */
5404 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5407 /* See what we need to return. We can only return a 1, -1, or the
5410 if (normalizep
== 0)
5412 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5413 normalizep
= STORE_FLAG_VALUE
;
5415 else if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5416 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5417 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
5423 last
= get_last_insn ();
5425 /* If optimizing, use different pseudo registers for each insn, instead
5426 of reusing the same pseudo. This leads to better CSE, but slows
5427 down the compiler, since there are more pseudos */
5428 subtarget
= (!optimize
5429 && (target_mode
== mode
)) ? target
: NULL_RTX
;
5430 trueval
= GEN_INT (normalizep
? normalizep
: STORE_FLAG_VALUE
);
5432 /* For floating-point comparisons, try the reverse comparison or try
5433 changing the "orderedness" of the comparison. */
5434 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5436 enum rtx_code first_code
;
5439 rcode
= reverse_condition_maybe_unordered (code
);
5440 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5441 && (code
== ORDERED
|| code
== UNORDERED
5442 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5443 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5445 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5446 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5448 /* For the reverse comparison, use either an addition or a XOR. */
5450 && rtx_cost (GEN_INT (normalizep
), PLUS
,
5451 optimize_insn_for_speed_p ()) == 0)
5453 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5454 STORE_FLAG_VALUE
, target_mode
);
5456 return expand_binop (target_mode
, add_optab
, tem
,
5457 GEN_INT (normalizep
),
5458 target
, 0, OPTAB_WIDEN
);
5461 && rtx_cost (trueval
, XOR
,
5462 optimize_insn_for_speed_p ()) == 0)
5464 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5465 normalizep
, target_mode
);
5467 return expand_binop (target_mode
, xor_optab
, tem
, trueval
,
5468 target
, INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5472 delete_insns_since (last
);
5474 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5475 if (code
== ORDERED
|| code
== UNORDERED
)
5478 and_them
= split_comparison (code
, mode
, &first_code
, &code
);
5480 /* If there are no NaNs, the first comparison should always fall through.
5481 Effectively change the comparison to the other one. */
5482 if (!HONOR_NANS (mode
))
5484 gcc_assert (first_code
== (and_them
? ORDERED
: UNORDERED
));
5485 return emit_store_flag_1 (target
, code
, op0
, op1
, mode
, 0, normalizep
,
5489 #ifdef HAVE_conditional_move
5490 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5491 conditional move. */
5492 tem
= emit_store_flag_1 (subtarget
, first_code
, op0
, op1
, mode
, 0,
5493 normalizep
, target_mode
);
5498 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
5499 tem
, const0_rtx
, GET_MODE (tem
), 0);
5501 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
5502 trueval
, tem
, GET_MODE (tem
), 0);
5505 delete_insns_since (last
);
5512 /* The remaining tricks only apply to integer comparisons. */
5514 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5517 /* If this is an equality comparison of integers, we can try to exclusive-or
5518 (or subtract) the two operands and use a recursive call to try the
5519 comparison with zero. Don't do any of these cases if branches are
5522 if ((code
== EQ
|| code
== NE
) && op1
!= const0_rtx
)
5524 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
5528 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
5531 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
5532 mode
, unsignedp
, normalizep
);
5536 delete_insns_since (last
);
5539 /* For integer comparisons, try the reverse comparison. However, for
5540 small X and if we'd have anyway to extend, implementing "X != 0"
5541 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5542 rcode
= reverse_condition (code
);
5543 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5544 && ! (optab_handler (cstore_optab
, mode
) == CODE_FOR_nothing
5546 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5547 && op1
== const0_rtx
))
5549 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5550 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5552 /* Again, for the reverse comparison, use either an addition or a XOR. */
5554 && rtx_cost (GEN_INT (normalizep
), PLUS
,
5555 optimize_insn_for_speed_p ()) == 0)
5557 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5558 STORE_FLAG_VALUE
, target_mode
);
5560 tem
= expand_binop (target_mode
, add_optab
, tem
,
5561 GEN_INT (normalizep
), target
, 0, OPTAB_WIDEN
);
5564 && rtx_cost (trueval
, XOR
,
5565 optimize_insn_for_speed_p ()) == 0)
5567 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5568 normalizep
, target_mode
);
5570 tem
= expand_binop (target_mode
, xor_optab
, tem
, trueval
, target
,
5571 INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5576 delete_insns_since (last
);
5579 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5580 the constant zero. Reject all other comparisons at this point. Only
5581 do LE and GT if branches are expensive since they are expensive on
5582 2-operand machines. */
5584 if (op1
!= const0_rtx
5585 || (code
!= EQ
&& code
!= NE
5586 && (BRANCH_COST (optimize_insn_for_speed_p (),
5587 false) <= 1 || (code
!= LE
&& code
!= GT
))))
5590 /* Try to put the result of the comparison in the sign bit. Assume we can't
5591 do the necessary operation below. */
5595 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5596 the sign bit set. */
5600 /* This is destructive, so SUBTARGET can't be OP0. */
5601 if (rtx_equal_p (subtarget
, op0
))
5604 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
5607 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
5611 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5612 number of bits in the mode of OP0, minus one. */
5616 if (rtx_equal_p (subtarget
, op0
))
5619 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5620 size_int (GET_MODE_BITSIZE (mode
) - 1),
5622 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5626 if (code
== EQ
|| code
== NE
)
5628 /* For EQ or NE, one way to do the comparison is to apply an operation
5629 that converts the operand into a positive number if it is nonzero
5630 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5631 for NE we negate. This puts the result in the sign bit. Then we
5632 normalize with a shift, if needed.
5634 Two operations that can do the above actions are ABS and FFS, so try
5635 them. If that doesn't work, and MODE is smaller than a full word,
5636 we can use zero-extension to the wider mode (an unsigned conversion)
5637 as the operation. */
5639 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5640 that is compensated by the subsequent overflow when subtracting
5643 if (optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)
5644 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5645 else if (optab_handler (ffs_optab
, mode
) != CODE_FOR_nothing
)
5646 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5647 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5649 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5656 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5659 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5662 /* If we couldn't do it that way, for NE we can "or" the two's complement
5663 of the value with itself. For EQ, we take the one's complement of
5664 that "or", which is an extra insn, so we only handle EQ if branches
5669 || BRANCH_COST (optimize_insn_for_speed_p (),
5672 if (rtx_equal_p (subtarget
, op0
))
5675 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5676 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5679 if (tem
&& code
== EQ
)
5680 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5684 if (tem
&& normalizep
)
5685 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
5686 size_int (GET_MODE_BITSIZE (mode
) - 1),
5687 subtarget
, normalizep
== 1);
5693 else if (GET_MODE (tem
) != target_mode
)
5695 convert_move (target
, tem
, 0);
5698 else if (!subtarget
)
5700 emit_move_insn (target
, tem
);
5705 delete_insns_since (last
);
5710 /* Like emit_store_flag, but always succeeds. */
5713 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5714 enum machine_mode mode
, int unsignedp
, int normalizep
)
5717 rtx trueval
, falseval
;
5719 /* First see if emit_store_flag can do the job. */
5720 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
5725 target
= gen_reg_rtx (word_mode
);
5727 /* If this failed, we have to do this with set/compare/jump/set code.
5728 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5729 trueval
= normalizep
? GEN_INT (normalizep
) : const1_rtx
;
5731 && GET_MODE_CLASS (mode
) == MODE_INT
5734 && op1
== const0_rtx
)
5736 label
= gen_label_rtx ();
5737 do_compare_rtx_and_jump (target
, const0_rtx
, EQ
, unsignedp
,
5738 mode
, NULL_RTX
, NULL_RTX
, label
, -1);
5739 emit_move_insn (target
, trueval
);
5745 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
5746 target
= gen_reg_rtx (GET_MODE (target
));
5748 /* Jump in the right direction if the target cannot implement CODE
5749 but can jump on its reverse condition. */
5750 falseval
= const0_rtx
;
5751 if (! can_compare_p (code
, mode
, ccp_jump
)
5752 && (! FLOAT_MODE_P (mode
)
5753 || code
== ORDERED
|| code
== UNORDERED
5754 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5755 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5757 enum rtx_code rcode
;
5758 if (FLOAT_MODE_P (mode
))
5759 rcode
= reverse_condition_maybe_unordered (code
);
5761 rcode
= reverse_condition (code
);
5763 /* Canonicalize to UNORDERED for the libcall. */
5764 if (can_compare_p (rcode
, mode
, ccp_jump
)
5765 || (code
== ORDERED
&& ! can_compare_p (ORDERED
, mode
, ccp_jump
)))
5768 trueval
= const0_rtx
;
5773 emit_move_insn (target
, trueval
);
5774 label
= gen_label_rtx ();
5775 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
5776 NULL_RTX
, label
, -1);
5778 emit_move_insn (target
, falseval
);
5784 /* Perform possibly multi-word comparison and conditional jump to LABEL
5785 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5786 now a thin wrapper around do_compare_rtx_and_jump. */
5789 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, enum machine_mode mode
,
5792 int unsignedp
= (op
== LTU
|| op
== LEU
|| op
== GTU
|| op
== GEU
);
5793 do_compare_rtx_and_jump (arg1
, arg2
, op
, unsignedp
, mode
,
5794 NULL_RTX
, NULL_RTX
, label
, -1);