1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987-2013 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
26 #include "diagnostic-core.h"
31 #include "insn-config.h"
35 #include "langhooks.h"
40 struct target_expmed default_target_expmed
;
42 struct target_expmed
*this_target_expmed
= &default_target_expmed
;
45 static void store_fixed_bit_field (rtx
, unsigned HOST_WIDE_INT
,
46 unsigned HOST_WIDE_INT
,
47 unsigned HOST_WIDE_INT
,
48 unsigned HOST_WIDE_INT
,
50 static void store_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
51 unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
,
53 unsigned HOST_WIDE_INT
,
55 static rtx
extract_fixed_bit_field (enum machine_mode
, rtx
,
56 unsigned HOST_WIDE_INT
,
57 unsigned HOST_WIDE_INT
, rtx
, int);
58 static rtx
mask_rtx (enum machine_mode
, int, int, int);
59 static rtx
lshift_value (enum machine_mode
, unsigned HOST_WIDE_INT
, int);
60 static rtx
extract_split_bit_field (rtx
, unsigned HOST_WIDE_INT
,
61 unsigned HOST_WIDE_INT
, int);
62 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, enum machine_mode
, rtx
);
63 static rtx
expand_smod_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
64 static rtx
expand_sdiv_pow2 (enum machine_mode
, rtx
, HOST_WIDE_INT
);
66 /* Test whether a value is zero of a power of two. */
67 #define EXACT_POWER_OF_2_OR_ZERO_P(x) \
68 (((x) & ((x) - (unsigned HOST_WIDE_INT) 1)) == 0)
70 struct init_expmed_rtl
78 struct rtx_def sdiv_32
;
79 struct rtx_def smod_32
;
80 struct rtx_def wide_mult
;
81 struct rtx_def wide_lshr
;
82 struct rtx_def wide_trunc
;
84 struct rtx_def shift_mult
;
85 struct rtx_def shift_add
;
86 struct rtx_def shift_sub0
;
87 struct rtx_def shift_sub1
;
91 rtx pow2
[MAX_BITS_PER_WORD
];
92 rtx cint
[MAX_BITS_PER_WORD
];
96 init_expmed_one_conv (struct init_expmed_rtl
*all
, enum machine_mode to_mode
,
97 enum machine_mode from_mode
, bool speed
)
99 int to_size
, from_size
;
102 /* We're given no information about the true size of a partial integer,
103 only the size of the "full" integer it requires for storage. For
104 comparison purposes here, reduce the bit size by one in that case. */
105 to_size
= (GET_MODE_BITSIZE (to_mode
)
106 - (GET_MODE_CLASS (to_mode
) == MODE_PARTIAL_INT
));
107 from_size
= (GET_MODE_BITSIZE (from_mode
)
108 - (GET_MODE_CLASS (from_mode
) == MODE_PARTIAL_INT
));
110 /* Assume cost of zero-extend and sign-extend is the same. */
111 which
= (to_size
< from_size
? &all
->trunc
: &all
->zext
);
113 PUT_MODE (&all
->reg
, from_mode
);
114 set_convert_cost (to_mode
, from_mode
, speed
, set_src_cost (which
, speed
));
118 init_expmed_one_mode (struct init_expmed_rtl
*all
,
119 enum machine_mode mode
, int speed
)
121 int m
, n
, mode_bitsize
;
122 enum machine_mode mode_from
;
124 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
126 PUT_MODE (&all
->reg
, mode
);
127 PUT_MODE (&all
->plus
, mode
);
128 PUT_MODE (&all
->neg
, mode
);
129 PUT_MODE (&all
->mult
, mode
);
130 PUT_MODE (&all
->sdiv
, mode
);
131 PUT_MODE (&all
->udiv
, mode
);
132 PUT_MODE (&all
->sdiv_32
, mode
);
133 PUT_MODE (&all
->smod_32
, mode
);
134 PUT_MODE (&all
->wide_trunc
, mode
);
135 PUT_MODE (&all
->shift
, mode
);
136 PUT_MODE (&all
->shift_mult
, mode
);
137 PUT_MODE (&all
->shift_add
, mode
);
138 PUT_MODE (&all
->shift_sub0
, mode
);
139 PUT_MODE (&all
->shift_sub1
, mode
);
140 PUT_MODE (&all
->zext
, mode
);
141 PUT_MODE (&all
->trunc
, mode
);
143 set_add_cost (speed
, mode
, set_src_cost (&all
->plus
, speed
));
144 set_neg_cost (speed
, mode
, set_src_cost (&all
->neg
, speed
));
145 set_mul_cost (speed
, mode
, set_src_cost (&all
->mult
, speed
));
146 set_sdiv_cost (speed
, mode
, set_src_cost (&all
->sdiv
, speed
));
147 set_udiv_cost (speed
, mode
, set_src_cost (&all
->udiv
, speed
));
149 set_sdiv_pow2_cheap (speed
, mode
, (set_src_cost (&all
->sdiv_32
, speed
)
150 <= 2 * add_cost (speed
, mode
)));
151 set_smod_pow2_cheap (speed
, mode
, (set_src_cost (&all
->smod_32
, speed
)
152 <= 4 * add_cost (speed
, mode
)));
154 set_shift_cost (speed
, mode
, 0, 0);
156 int cost
= add_cost (speed
, mode
);
157 set_shiftadd_cost (speed
, mode
, 0, cost
);
158 set_shiftsub0_cost (speed
, mode
, 0, cost
);
159 set_shiftsub1_cost (speed
, mode
, 0, cost
);
162 n
= MIN (MAX_BITS_PER_WORD
, mode_bitsize
);
163 for (m
= 1; m
< n
; m
++)
165 XEXP (&all
->shift
, 1) = all
->cint
[m
];
166 XEXP (&all
->shift_mult
, 1) = all
->pow2
[m
];
168 set_shift_cost (speed
, mode
, m
, set_src_cost (&all
->shift
, speed
));
169 set_shiftadd_cost (speed
, mode
, m
, set_src_cost (&all
->shift_add
, speed
));
170 set_shiftsub0_cost (speed
, mode
, m
, set_src_cost (&all
->shift_sub0
, speed
));
171 set_shiftsub1_cost (speed
, mode
, m
, set_src_cost (&all
->shift_sub1
, speed
));
174 if (SCALAR_INT_MODE_P (mode
))
176 for (mode_from
= MIN_MODE_INT
; mode_from
<= MAX_MODE_INT
;
177 mode_from
= (enum machine_mode
)(mode_from
+ 1))
178 init_expmed_one_conv (all
, mode
, mode_from
, speed
);
180 if (GET_MODE_CLASS (mode
) == MODE_INT
)
182 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
183 if (wider_mode
!= VOIDmode
)
185 PUT_MODE (&all
->zext
, wider_mode
);
186 PUT_MODE (&all
->wide_mult
, wider_mode
);
187 PUT_MODE (&all
->wide_lshr
, wider_mode
);
188 XEXP (&all
->wide_lshr
, 1) = GEN_INT (mode_bitsize
);
190 set_mul_widen_cost (speed
, wider_mode
,
191 set_src_cost (&all
->wide_mult
, speed
));
192 set_mul_highpart_cost (speed
, mode
,
193 set_src_cost (&all
->wide_trunc
, speed
));
201 struct init_expmed_rtl all
;
202 enum machine_mode mode
;
205 memset (&all
, 0, sizeof all
);
206 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
208 all
.pow2
[m
] = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
209 all
.cint
[m
] = GEN_INT (m
);
212 PUT_CODE (&all
.reg
, REG
);
213 /* Avoid using hard regs in ways which may be unsupported. */
214 SET_REGNO (&all
.reg
, LAST_VIRTUAL_REGISTER
+ 1);
216 PUT_CODE (&all
.plus
, PLUS
);
217 XEXP (&all
.plus
, 0) = &all
.reg
;
218 XEXP (&all
.plus
, 1) = &all
.reg
;
220 PUT_CODE (&all
.neg
, NEG
);
221 XEXP (&all
.neg
, 0) = &all
.reg
;
223 PUT_CODE (&all
.mult
, MULT
);
224 XEXP (&all
.mult
, 0) = &all
.reg
;
225 XEXP (&all
.mult
, 1) = &all
.reg
;
227 PUT_CODE (&all
.sdiv
, DIV
);
228 XEXP (&all
.sdiv
, 0) = &all
.reg
;
229 XEXP (&all
.sdiv
, 1) = &all
.reg
;
231 PUT_CODE (&all
.udiv
, UDIV
);
232 XEXP (&all
.udiv
, 0) = &all
.reg
;
233 XEXP (&all
.udiv
, 1) = &all
.reg
;
235 PUT_CODE (&all
.sdiv_32
, DIV
);
236 XEXP (&all
.sdiv_32
, 0) = &all
.reg
;
237 XEXP (&all
.sdiv_32
, 1) = 32 < MAX_BITS_PER_WORD
? all
.cint
[32] : GEN_INT (32);
239 PUT_CODE (&all
.smod_32
, MOD
);
240 XEXP (&all
.smod_32
, 0) = &all
.reg
;
241 XEXP (&all
.smod_32
, 1) = XEXP (&all
.sdiv_32
, 1);
243 PUT_CODE (&all
.zext
, ZERO_EXTEND
);
244 XEXP (&all
.zext
, 0) = &all
.reg
;
246 PUT_CODE (&all
.wide_mult
, MULT
);
247 XEXP (&all
.wide_mult
, 0) = &all
.zext
;
248 XEXP (&all
.wide_mult
, 1) = &all
.zext
;
250 PUT_CODE (&all
.wide_lshr
, LSHIFTRT
);
251 XEXP (&all
.wide_lshr
, 0) = &all
.wide_mult
;
253 PUT_CODE (&all
.wide_trunc
, TRUNCATE
);
254 XEXP (&all
.wide_trunc
, 0) = &all
.wide_lshr
;
256 PUT_CODE (&all
.shift
, ASHIFT
);
257 XEXP (&all
.shift
, 0) = &all
.reg
;
259 PUT_CODE (&all
.shift_mult
, MULT
);
260 XEXP (&all
.shift_mult
, 0) = &all
.reg
;
262 PUT_CODE (&all
.shift_add
, PLUS
);
263 XEXP (&all
.shift_add
, 0) = &all
.shift_mult
;
264 XEXP (&all
.shift_add
, 1) = &all
.reg
;
266 PUT_CODE (&all
.shift_sub0
, MINUS
);
267 XEXP (&all
.shift_sub0
, 0) = &all
.shift_mult
;
268 XEXP (&all
.shift_sub0
, 1) = &all
.reg
;
270 PUT_CODE (&all
.shift_sub1
, MINUS
);
271 XEXP (&all
.shift_sub1
, 0) = &all
.reg
;
272 XEXP (&all
.shift_sub1
, 1) = &all
.shift_mult
;
274 PUT_CODE (&all
.trunc
, TRUNCATE
);
275 XEXP (&all
.trunc
, 0) = &all
.reg
;
277 for (speed
= 0; speed
< 2; speed
++)
279 crtl
->maybe_hot_insn_p
= speed
;
280 set_zero_cost (speed
, set_src_cost (const0_rtx
, speed
));
282 for (mode
= MIN_MODE_INT
; mode
<= MAX_MODE_INT
;
283 mode
= (enum machine_mode
)(mode
+ 1))
284 init_expmed_one_mode (&all
, mode
, speed
);
286 if (MIN_MODE_PARTIAL_INT
!= VOIDmode
)
287 for (mode
= MIN_MODE_PARTIAL_INT
; mode
<= MAX_MODE_PARTIAL_INT
;
288 mode
= (enum machine_mode
)(mode
+ 1))
289 init_expmed_one_mode (&all
, mode
, speed
);
291 if (MIN_MODE_VECTOR_INT
!= VOIDmode
)
292 for (mode
= MIN_MODE_VECTOR_INT
; mode
<= MAX_MODE_VECTOR_INT
;
293 mode
= (enum machine_mode
)(mode
+ 1))
294 init_expmed_one_mode (&all
, mode
, speed
);
297 if (alg_hash_used_p ())
299 struct alg_hash_entry
*p
= alg_hash_entry_ptr (0);
300 memset (p
, 0, sizeof (*p
) * NUM_ALG_HASH_ENTRIES
);
303 set_alg_hash_used_p (true);
304 default_rtl_profile ();
307 /* Return an rtx representing minus the value of X.
308 MODE is the intended mode of the result,
309 useful if X is a CONST_INT. */
312 negate_rtx (enum machine_mode mode
, rtx x
)
314 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
317 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
322 /* Adjust bitfield memory MEM so that it points to the first unit of mode
323 MODE that contains a bitfield of size BITSIZE at bit position BITNUM.
324 If MODE is BLKmode, return a reference to every byte in the bitfield.
325 Set *NEW_BITNUM to the bit position of the field within the new memory. */
328 narrow_bit_field_mem (rtx mem
, enum machine_mode mode
,
329 unsigned HOST_WIDE_INT bitsize
,
330 unsigned HOST_WIDE_INT bitnum
,
331 unsigned HOST_WIDE_INT
*new_bitnum
)
335 *new_bitnum
= bitnum
% BITS_PER_UNIT
;
336 HOST_WIDE_INT offset
= bitnum
/ BITS_PER_UNIT
;
337 HOST_WIDE_INT size
= ((*new_bitnum
+ bitsize
+ BITS_PER_UNIT
- 1)
339 return adjust_bitfield_address_size (mem
, mode
, offset
, size
);
343 unsigned int unit
= GET_MODE_BITSIZE (mode
);
344 *new_bitnum
= bitnum
% unit
;
345 HOST_WIDE_INT offset
= (bitnum
- *new_bitnum
) / BITS_PER_UNIT
;
346 return adjust_bitfield_address (mem
, mode
, offset
);
350 /* The caller wants to perform insertion or extraction PATTERN on a
351 bitfield of size BITSIZE at BITNUM bits into memory operand OP0.
352 BITREGION_START and BITREGION_END are as for store_bit_field
353 and FIELDMODE is the natural mode of the field.
355 Search for a mode that is compatible with the memory access
356 restrictions and (where applicable) with a register insertion or
357 extraction. Return the new memory on success, storing the adjusted
358 bit position in *NEW_BITNUM. Return null otherwise. */
361 adjust_bit_field_mem_for_reg (enum extraction_pattern pattern
,
362 rtx op0
, HOST_WIDE_INT bitsize
,
363 HOST_WIDE_INT bitnum
,
364 unsigned HOST_WIDE_INT bitregion_start
,
365 unsigned HOST_WIDE_INT bitregion_end
,
366 enum machine_mode fieldmode
,
367 unsigned HOST_WIDE_INT
*new_bitnum
)
369 bit_field_mode_iterator
iter (bitsize
, bitnum
, bitregion_start
,
370 bitregion_end
, MEM_ALIGN (op0
),
371 MEM_VOLATILE_P (op0
));
372 enum machine_mode best_mode
;
373 if (iter
.next_mode (&best_mode
))
375 /* We can use a memory in BEST_MODE. See whether this is true for
376 any wider modes. All other things being equal, we prefer to
377 use the widest mode possible because it tends to expose more
378 CSE opportunities. */
379 if (!iter
.prefer_smaller_modes ())
381 /* Limit the search to the mode required by the corresponding
382 register insertion or extraction instruction, if any. */
383 enum machine_mode limit_mode
= word_mode
;
384 extraction_insn insn
;
385 if (get_best_reg_extraction_insn (&insn
, pattern
,
386 GET_MODE_BITSIZE (best_mode
),
388 limit_mode
= insn
.field_mode
;
390 enum machine_mode wider_mode
;
391 while (iter
.next_mode (&wider_mode
)
392 && GET_MODE_SIZE (wider_mode
) <= GET_MODE_SIZE (limit_mode
))
393 best_mode
= wider_mode
;
395 return narrow_bit_field_mem (op0
, best_mode
, bitsize
, bitnum
,
401 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
402 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
403 offset is then BITNUM / BITS_PER_UNIT. */
406 lowpart_bit_field_p (unsigned HOST_WIDE_INT bitnum
,
407 unsigned HOST_WIDE_INT bitsize
,
408 enum machine_mode struct_mode
)
410 if (BYTES_BIG_ENDIAN
)
411 return (bitnum
% BITS_PER_UNIT
== 0
412 && (bitnum
+ bitsize
== GET_MODE_BITSIZE (struct_mode
)
413 || (bitnum
+ bitsize
) % BITS_PER_WORD
== 0));
415 return bitnum
% BITS_PER_WORD
== 0;
418 /* Return true if OP is a memory and if a bitfield of size BITSIZE at
419 bit number BITNUM can be treated as a simple value of mode MODE. */
422 simple_mem_bitfield_p (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
423 unsigned HOST_WIDE_INT bitnum
, enum machine_mode mode
)
426 && bitnum
% BITS_PER_UNIT
== 0
427 && bitsize
== GET_MODE_BITSIZE (mode
)
428 && (!SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (op0
))
429 || (bitnum
% GET_MODE_ALIGNMENT (mode
) == 0
430 && MEM_ALIGN (op0
) >= GET_MODE_ALIGNMENT (mode
))));
433 /* Try to use instruction INSV to store VALUE into a field of OP0.
434 BITSIZE and BITNUM are as for store_bit_field. */
437 store_bit_field_using_insv (const extraction_insn
*insv
, rtx op0
,
438 unsigned HOST_WIDE_INT bitsize
,
439 unsigned HOST_WIDE_INT bitnum
, rtx value
)
441 struct expand_operand ops
[4];
444 rtx last
= get_last_insn ();
445 bool copy_back
= false;
447 enum machine_mode op_mode
= insv
->field_mode
;
448 unsigned int unit
= GET_MODE_BITSIZE (op_mode
);
449 if (bitsize
== 0 || bitsize
> unit
)
453 /* Get a reference to the first byte of the field. */
454 xop0
= narrow_bit_field_mem (xop0
, insv
->struct_mode
, bitsize
, bitnum
,
458 /* Convert from counting within OP0 to counting in OP_MODE. */
459 if (BYTES_BIG_ENDIAN
)
460 bitnum
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
462 /* If xop0 is a register, we need it in OP_MODE
463 to make it acceptable to the format of insv. */
464 if (GET_CODE (xop0
) == SUBREG
)
465 /* We can't just change the mode, because this might clobber op0,
466 and we will need the original value of op0 if insv fails. */
467 xop0
= gen_rtx_SUBREG (op_mode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
468 if (REG_P (xop0
) && GET_MODE (xop0
) != op_mode
)
469 xop0
= gen_lowpart_SUBREG (op_mode
, xop0
);
472 /* If the destination is a paradoxical subreg such that we need a
473 truncate to the inner mode, perform the insertion on a temporary and
474 truncate the result to the original destination. Note that we can't
475 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
476 X) 0)) is (reg:N X). */
477 if (GET_CODE (xop0
) == SUBREG
478 && REG_P (SUBREG_REG (xop0
))
479 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0
)),
482 rtx tem
= gen_reg_rtx (op_mode
);
483 emit_move_insn (tem
, xop0
);
488 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
489 "backwards" from the size of the unit we are inserting into.
490 Otherwise, we count bits from the most significant on a
491 BYTES/BITS_BIG_ENDIAN machine. */
493 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
494 bitnum
= unit
- bitsize
- bitnum
;
496 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
498 if (GET_MODE (value
) != op_mode
)
500 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
502 /* Optimization: Don't bother really extending VALUE
503 if it has all the bits we will actually use. However,
504 if we must narrow it, be sure we do it correctly. */
506 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (op_mode
))
510 tmp
= simplify_subreg (op_mode
, value1
, GET_MODE (value
), 0);
512 tmp
= simplify_gen_subreg (op_mode
,
513 force_reg (GET_MODE (value
),
515 GET_MODE (value
), 0);
519 value1
= gen_lowpart (op_mode
, value1
);
521 else if (CONST_INT_P (value
))
522 value1
= gen_int_mode (INTVAL (value
), op_mode
);
524 /* Parse phase is supposed to make VALUE's data type
525 match that of the component reference, which is a type
526 at least as wide as the field; so VALUE should have
527 a mode that corresponds to that type. */
528 gcc_assert (CONSTANT_P (value
));
531 create_fixed_operand (&ops
[0], xop0
);
532 create_integer_operand (&ops
[1], bitsize
);
533 create_integer_operand (&ops
[2], bitnum
);
534 create_input_operand (&ops
[3], value1
, op_mode
);
535 if (maybe_expand_insn (insv
->icode
, 4, ops
))
538 convert_move (op0
, xop0
, true);
541 delete_insns_since (last
);
545 /* A subroutine of store_bit_field, with the same arguments. Return true
546 if the operation could be implemented.
548 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
549 no other way of implementing the operation. If FALLBACK_P is false,
550 return false instead. */
553 store_bit_field_1 (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
554 unsigned HOST_WIDE_INT bitnum
,
555 unsigned HOST_WIDE_INT bitregion_start
,
556 unsigned HOST_WIDE_INT bitregion_end
,
557 enum machine_mode fieldmode
,
558 rtx value
, bool fallback_p
)
563 while (GET_CODE (op0
) == SUBREG
)
565 /* The following line once was done only if WORDS_BIG_ENDIAN,
566 but I think that is a mistake. WORDS_BIG_ENDIAN is
567 meaningful at a much higher level; when structures are copied
568 between memory and regs, the higher-numbered regs
569 always get higher addresses. */
570 int inner_mode_size
= GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)));
571 int outer_mode_size
= GET_MODE_SIZE (GET_MODE (op0
));
574 /* Paradoxical subregs need special handling on big endian machines. */
575 if (SUBREG_BYTE (op0
) == 0 && inner_mode_size
< outer_mode_size
)
577 int difference
= inner_mode_size
- outer_mode_size
;
579 if (WORDS_BIG_ENDIAN
)
580 byte_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
581 if (BYTES_BIG_ENDIAN
)
582 byte_offset
+= difference
% UNITS_PER_WORD
;
585 byte_offset
= SUBREG_BYTE (op0
);
587 bitnum
+= byte_offset
* BITS_PER_UNIT
;
588 op0
= SUBREG_REG (op0
);
591 /* No action is needed if the target is a register and if the field
592 lies completely outside that register. This can occur if the source
593 code contains an out-of-bounds access to a small array. */
594 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
597 /* Use vec_set patterns for inserting parts of vectors whenever
599 if (VECTOR_MODE_P (GET_MODE (op0
))
601 && optab_handler (vec_set_optab
, GET_MODE (op0
)) != CODE_FOR_nothing
602 && fieldmode
== GET_MODE_INNER (GET_MODE (op0
))
603 && bitsize
== GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
604 && !(bitnum
% GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
606 struct expand_operand ops
[3];
607 enum machine_mode outermode
= GET_MODE (op0
);
608 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
609 enum insn_code icode
= optab_handler (vec_set_optab
, outermode
);
610 int pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
612 create_fixed_operand (&ops
[0], op0
);
613 create_input_operand (&ops
[1], value
, innermode
);
614 create_integer_operand (&ops
[2], pos
);
615 if (maybe_expand_insn (icode
, 3, ops
))
619 /* If the target is a register, overwriting the entire object, or storing
620 a full-word or multi-word field can be done with just a SUBREG. */
622 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
623 && ((bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)) && bitnum
== 0)
624 || (bitsize
% BITS_PER_WORD
== 0 && bitnum
% BITS_PER_WORD
== 0)))
626 /* Use the subreg machinery either to narrow OP0 to the required
627 words or to cope with mode punning between equal-sized modes. */
628 rtx sub
= simplify_gen_subreg (fieldmode
, op0
, GET_MODE (op0
),
629 bitnum
/ BITS_PER_UNIT
);
632 emit_move_insn (sub
, value
);
637 /* If the target is memory, storing any naturally aligned field can be
638 done with a simple store. For targets that support fast unaligned
639 memory, any naturally sized, unit aligned field can be done directly. */
640 if (simple_mem_bitfield_p (op0
, bitsize
, bitnum
, fieldmode
))
642 op0
= adjust_bitfield_address (op0
, fieldmode
, bitnum
/ BITS_PER_UNIT
);
643 emit_move_insn (op0
, value
);
647 /* Make sure we are playing with integral modes. Pun with subregs
648 if we aren't. This must come after the entire register case above,
649 since that case is valid for any mode. The following cases are only
650 valid for integral modes. */
652 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
653 if (imode
!= GET_MODE (op0
))
656 op0
= adjust_bitfield_address_size (op0
, imode
, 0, MEM_SIZE (op0
));
659 gcc_assert (imode
!= BLKmode
);
660 op0
= gen_lowpart (imode
, op0
);
665 /* Storing an lsb-aligned field in a register
666 can be done with a movstrict instruction. */
669 && lowpart_bit_field_p (bitnum
, bitsize
, GET_MODE (op0
))
670 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
671 && optab_handler (movstrict_optab
, fieldmode
) != CODE_FOR_nothing
)
673 struct expand_operand ops
[2];
674 enum insn_code icode
= optab_handler (movstrict_optab
, fieldmode
);
676 unsigned HOST_WIDE_INT subreg_off
;
678 if (GET_CODE (arg0
) == SUBREG
)
680 /* Else we've got some float mode source being extracted into
681 a different float mode destination -- this combination of
682 subregs results in Severe Tire Damage. */
683 gcc_assert (GET_MODE (SUBREG_REG (arg0
)) == fieldmode
684 || GET_MODE_CLASS (fieldmode
) == MODE_INT
685 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
);
686 arg0
= SUBREG_REG (arg0
);
689 subreg_off
= bitnum
/ BITS_PER_UNIT
;
690 if (validate_subreg (fieldmode
, GET_MODE (arg0
), arg0
, subreg_off
))
692 arg0
= gen_rtx_SUBREG (fieldmode
, arg0
, subreg_off
);
694 create_fixed_operand (&ops
[0], arg0
);
695 /* Shrink the source operand to FIELDMODE. */
696 create_convert_operand_to (&ops
[1], value
, fieldmode
, false);
697 if (maybe_expand_insn (icode
, 2, ops
))
702 /* Handle fields bigger than a word. */
704 if (bitsize
> BITS_PER_WORD
)
706 /* Here we transfer the words of the field
707 in the order least significant first.
708 This is because the most significant word is the one which may
710 However, only do that if the value is not BLKmode. */
712 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
713 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
717 /* This is the mode we must force value to, so that there will be enough
718 subwords to extract. Note that fieldmode will often (always?) be
719 VOIDmode, because that is what store_field uses to indicate that this
720 is a bit field, but passing VOIDmode to operand_subword_force
722 fieldmode
= GET_MODE (value
);
723 if (fieldmode
== VOIDmode
)
724 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
726 last
= get_last_insn ();
727 for (i
= 0; i
< nwords
; i
++)
729 /* If I is 0, use the low-order word in both field and target;
730 if I is 1, use the next to lowest word; and so on. */
731 unsigned int wordnum
= (backwards
732 ? GET_MODE_SIZE (fieldmode
) / UNITS_PER_WORD
735 unsigned int bit_offset
= (backwards
736 ? MAX ((int) bitsize
- ((int) i
+ 1)
739 : (int) i
* BITS_PER_WORD
);
740 rtx value_word
= operand_subword_force (value
, wordnum
, fieldmode
);
741 unsigned HOST_WIDE_INT new_bitsize
=
742 MIN (BITS_PER_WORD
, bitsize
- i
* BITS_PER_WORD
);
744 /* If the remaining chunk doesn't have full wordsize we have
745 to make sure that for big endian machines the higher order
747 if (new_bitsize
< BITS_PER_WORD
&& BYTES_BIG_ENDIAN
&& !backwards
)
748 value_word
= simplify_expand_binop (word_mode
, lshr_optab
,
750 GEN_INT (BITS_PER_WORD
755 if (!store_bit_field_1 (op0
, new_bitsize
,
757 bitregion_start
, bitregion_end
,
759 value_word
, fallback_p
))
761 delete_insns_since (last
);
768 /* If VALUE has a floating-point or complex mode, access it as an
769 integer of the corresponding size. This can occur on a machine
770 with 64 bit registers that uses SFmode for float. It can also
771 occur for unaligned float or complex fields. */
773 if (GET_MODE (value
) != VOIDmode
774 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_INT
775 && GET_MODE_CLASS (GET_MODE (value
)) != MODE_PARTIAL_INT
)
777 value
= gen_reg_rtx (int_mode_for_mode (GET_MODE (value
)));
778 emit_move_insn (gen_lowpart (GET_MODE (orig_value
), value
), orig_value
);
781 /* If OP0 is a multi-word register, narrow it to the affected word.
782 If the region spans two words, defer to store_split_bit_field. */
783 if (!MEM_P (op0
) && GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
785 op0
= simplify_gen_subreg (word_mode
, op0
, GET_MODE (op0
),
786 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
788 bitnum
%= BITS_PER_WORD
;
789 if (bitnum
+ bitsize
> BITS_PER_WORD
)
794 store_split_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
795 bitregion_end
, value
);
800 /* From here on we can assume that the field to be stored in fits
801 within a word. If the destination is a register, it too fits
804 extraction_insn insv
;
806 && get_best_reg_extraction_insn (&insv
, EP_insv
,
807 GET_MODE_BITSIZE (GET_MODE (op0
)),
809 && store_bit_field_using_insv (&insv
, op0
, bitsize
, bitnum
, value
))
812 /* If OP0 is a memory, try copying it to a register and seeing if a
813 cheap register alternative is available. */
816 /* Do not use unaligned memory insvs for volatile bitfields when
817 -fstrict-volatile-bitfields is in effect. */
818 if (!(MEM_VOLATILE_P (op0
)
819 && flag_strict_volatile_bitfields
> 0)
820 && get_best_mem_extraction_insn (&insv
, EP_insv
, bitsize
, bitnum
,
822 && store_bit_field_using_insv (&insv
, op0
, bitsize
, bitnum
, value
))
825 rtx last
= get_last_insn ();
827 /* Try loading part of OP0 into a register, inserting the bitfield
828 into that, and then copying the result back to OP0. */
829 unsigned HOST_WIDE_INT bitpos
;
830 rtx xop0
= adjust_bit_field_mem_for_reg (EP_insv
, op0
, bitsize
, bitnum
,
831 bitregion_start
, bitregion_end
,
835 rtx tempreg
= copy_to_reg (xop0
);
836 if (store_bit_field_1 (tempreg
, bitsize
, bitpos
,
837 bitregion_start
, bitregion_end
,
838 fieldmode
, orig_value
, false))
840 emit_move_insn (xop0
, tempreg
);
843 delete_insns_since (last
);
850 store_fixed_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
851 bitregion_end
, value
);
855 /* Generate code to store value from rtx VALUE
856 into a bit-field within structure STR_RTX
857 containing BITSIZE bits starting at bit BITNUM.
859 BITREGION_START is bitpos of the first bitfield in this region.
860 BITREGION_END is the bitpos of the ending bitfield in this region.
861 These two fields are 0, if the C++ memory model does not apply,
862 or we are not interested in keeping track of bitfield regions.
864 FIELDMODE is the machine-mode of the FIELD_DECL node for this field. */
867 store_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
868 unsigned HOST_WIDE_INT bitnum
,
869 unsigned HOST_WIDE_INT bitregion_start
,
870 unsigned HOST_WIDE_INT bitregion_end
,
871 enum machine_mode fieldmode
,
874 /* Under the C++0x memory model, we must not touch bits outside the
875 bit region. Adjust the address to start at the beginning of the
877 if (MEM_P (str_rtx
) && bitregion_start
> 0)
879 enum machine_mode bestmode
;
880 HOST_WIDE_INT offset
, size
;
882 gcc_assert ((bitregion_start
% BITS_PER_UNIT
) == 0);
884 offset
= bitregion_start
/ BITS_PER_UNIT
;
885 bitnum
-= bitregion_start
;
886 size
= (bitnum
+ bitsize
+ BITS_PER_UNIT
- 1) / BITS_PER_UNIT
;
887 bitregion_end
-= bitregion_start
;
889 bestmode
= get_best_mode (bitsize
, bitnum
,
890 bitregion_start
, bitregion_end
,
891 MEM_ALIGN (str_rtx
), VOIDmode
,
892 MEM_VOLATILE_P (str_rtx
));
893 str_rtx
= adjust_bitfield_address_size (str_rtx
, bestmode
, offset
, size
);
896 if (!store_bit_field_1 (str_rtx
, bitsize
, bitnum
,
897 bitregion_start
, bitregion_end
,
898 fieldmode
, value
, true))
902 /* Use shifts and boolean operations to store VALUE into a bit field of
903 width BITSIZE in OP0, starting at bit BITNUM. */
906 store_fixed_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
907 unsigned HOST_WIDE_INT bitnum
,
908 unsigned HOST_WIDE_INT bitregion_start
,
909 unsigned HOST_WIDE_INT bitregion_end
,
912 enum machine_mode mode
;
917 /* There is a case not handled here:
918 a structure with a known alignment of just a halfword
919 and a field split across two aligned halfwords within the structure.
920 Or likewise a structure with a known alignment of just a byte
921 and a field split across two bytes.
922 Such cases are not supposed to be able to occur. */
926 unsigned HOST_WIDE_INT maxbits
= MAX_FIXED_MODE_SIZE
;
929 maxbits
= bitregion_end
- bitregion_start
+ 1;
931 /* Get the proper mode to use for this field. We want a mode that
932 includes the entire field. If such a mode would be larger than
933 a word, we won't be doing the extraction the normal way.
934 We don't want a mode bigger than the destination. */
936 mode
= GET_MODE (op0
);
937 if (GET_MODE_BITSIZE (mode
) == 0
938 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
941 if (MEM_VOLATILE_P (op0
)
942 && GET_MODE_BITSIZE (GET_MODE (op0
)) > 0
943 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= maxbits
944 && flag_strict_volatile_bitfields
> 0)
945 mode
= GET_MODE (op0
);
947 mode
= get_best_mode (bitsize
, bitnum
, bitregion_start
, bitregion_end
,
948 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
950 if (mode
== VOIDmode
)
952 /* The only way this should occur is if the field spans word
954 store_split_bit_field (op0
, bitsize
, bitnum
, bitregion_start
,
955 bitregion_end
, value
);
959 op0
= narrow_bit_field_mem (op0
, mode
, bitsize
, bitnum
, &bitnum
);
962 mode
= GET_MODE (op0
);
963 gcc_assert (SCALAR_INT_MODE_P (mode
));
965 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
966 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
968 if (BYTES_BIG_ENDIAN
)
969 /* BITNUM is the distance between our msb
970 and that of the containing datum.
971 Convert it to the distance from the lsb. */
972 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
974 /* Now BITNUM is always the distance between our lsb
977 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
978 we must first convert its mode to MODE. */
980 if (CONST_INT_P (value
))
982 HOST_WIDE_INT v
= INTVAL (value
);
984 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
985 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
989 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
990 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
991 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
994 value
= lshift_value (mode
, v
, bitnum
);
998 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
999 && bitnum
+ bitsize
!= GET_MODE_BITSIZE (mode
));
1001 if (GET_MODE (value
) != mode
)
1002 value
= convert_to_mode (mode
, value
, 1);
1005 value
= expand_binop (mode
, and_optab
, value
,
1006 mask_rtx (mode
, 0, bitsize
, 0),
1007 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1009 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
1010 bitnum
, NULL_RTX
, 1);
1013 /* Now clear the chosen bits in OP0,
1014 except that if VALUE is -1 we need not bother. */
1015 /* We keep the intermediates in registers to allow CSE to combine
1016 consecutive bitfield assignments. */
1018 temp
= force_reg (mode
, op0
);
1022 temp
= expand_binop (mode
, and_optab
, temp
,
1023 mask_rtx (mode
, bitnum
, bitsize
, 1),
1024 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1025 temp
= force_reg (mode
, temp
);
1028 /* Now logical-or VALUE into OP0, unless it is zero. */
1032 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
1033 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1034 temp
= force_reg (mode
, temp
);
1039 op0
= copy_rtx (op0
);
1040 emit_move_insn (op0
, temp
);
1044 /* Store a bit field that is split across multiple accessible memory objects.
1046 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1047 BITSIZE is the field width; BITPOS the position of its first bit
1049 VALUE is the value to store.
1051 This does not yet handle fields wider than BITS_PER_WORD. */
1054 store_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1055 unsigned HOST_WIDE_INT bitpos
,
1056 unsigned HOST_WIDE_INT bitregion_start
,
1057 unsigned HOST_WIDE_INT bitregion_end
,
1061 unsigned int bitsdone
= 0;
1063 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1065 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1066 unit
= BITS_PER_WORD
;
1068 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1070 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1071 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1072 that VALUE might be a floating-point constant. */
1073 if (CONSTANT_P (value
) && !CONST_INT_P (value
))
1075 rtx word
= gen_lowpart_common (word_mode
, value
);
1077 if (word
&& (value
!= word
))
1080 value
= gen_lowpart_common (word_mode
,
1081 force_reg (GET_MODE (value
) != VOIDmode
1083 : word_mode
, value
));
1086 while (bitsdone
< bitsize
)
1088 unsigned HOST_WIDE_INT thissize
;
1090 unsigned HOST_WIDE_INT thispos
;
1091 unsigned HOST_WIDE_INT offset
;
1093 offset
= (bitpos
+ bitsdone
) / unit
;
1094 thispos
= (bitpos
+ bitsdone
) % unit
;
1096 /* When region of bytes we can touch is restricted, decrease
1097 UNIT close to the end of the region as needed. If op0 is a REG
1098 or SUBREG of REG, don't do this, as there can't be data races
1099 on a register and we can expand shorter code in some cases. */
1101 && unit
> BITS_PER_UNIT
1102 && bitpos
+ bitsdone
- thispos
+ unit
> bitregion_end
+ 1
1104 && (GET_CODE (op0
) != SUBREG
|| !REG_P (SUBREG_REG (op0
))))
1110 /* THISSIZE must not overrun a word boundary. Otherwise,
1111 store_fixed_bit_field will call us again, and we will mutually
1113 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1114 thissize
= MIN (thissize
, unit
- thispos
);
1116 if (BYTES_BIG_ENDIAN
)
1118 /* Fetch successively less significant portions. */
1119 if (CONST_INT_P (value
))
1120 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1121 >> (bitsize
- bitsdone
- thissize
))
1122 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1125 int total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
1126 /* The args are chosen so that the last part includes the
1127 lsb. Give extract_bit_field the value it needs (with
1128 endianness compensation) to fetch the piece we want. */
1129 part
= extract_fixed_bit_field (word_mode
, value
, thissize
,
1130 total_bits
- bitsize
+ bitsdone
,
1136 /* Fetch successively more significant portions. */
1137 if (CONST_INT_P (value
))
1138 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1140 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
1142 part
= extract_fixed_bit_field (word_mode
, value
, thissize
,
1143 bitsdone
, NULL_RTX
, 1);
1146 /* If OP0 is a register, then handle OFFSET here.
1148 When handling multiword bitfields, extract_bit_field may pass
1149 down a word_mode SUBREG of a larger REG for a bitfield that actually
1150 crosses a word boundary. Thus, for a SUBREG, we must find
1151 the current word starting from the base register. */
1152 if (GET_CODE (op0
) == SUBREG
)
1154 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
)
1155 + (offset
* unit
/ BITS_PER_WORD
);
1156 enum machine_mode sub_mode
= GET_MODE (SUBREG_REG (op0
));
1157 if (sub_mode
!= BLKmode
&& GET_MODE_SIZE (sub_mode
) < UNITS_PER_WORD
)
1158 word
= word_offset
? const0_rtx
: op0
;
1160 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1161 GET_MODE (SUBREG_REG (op0
)));
1162 offset
&= BITS_PER_WORD
/ unit
- 1;
1164 else if (REG_P (op0
))
1166 enum machine_mode op0_mode
= GET_MODE (op0
);
1167 if (op0_mode
!= BLKmode
&& GET_MODE_SIZE (op0_mode
) < UNITS_PER_WORD
)
1168 word
= offset
? const0_rtx
: op0
;
1170 word
= operand_subword_force (op0
, offset
* unit
/ BITS_PER_WORD
,
1172 offset
&= BITS_PER_WORD
/ unit
- 1;
1177 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1178 it is just an out-of-bounds access. Ignore it. */
1179 if (word
!= const0_rtx
)
1180 store_fixed_bit_field (word
, thissize
, offset
* unit
+ thispos
,
1181 bitregion_start
, bitregion_end
, part
);
1182 bitsdone
+= thissize
;
1186 /* A subroutine of extract_bit_field_1 that converts return value X
1187 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1188 to extract_bit_field. */
1191 convert_extracted_bit_field (rtx x
, enum machine_mode mode
,
1192 enum machine_mode tmode
, bool unsignedp
)
1194 if (GET_MODE (x
) == tmode
|| GET_MODE (x
) == mode
)
1197 /* If the x mode is not a scalar integral, first convert to the
1198 integer mode of that size and then access it as a floating-point
1199 value via a SUBREG. */
1200 if (!SCALAR_INT_MODE_P (tmode
))
1202 enum machine_mode smode
;
1204 smode
= mode_for_size (GET_MODE_BITSIZE (tmode
), MODE_INT
, 0);
1205 x
= convert_to_mode (smode
, x
, unsignedp
);
1206 x
= force_reg (smode
, x
);
1207 return gen_lowpart (tmode
, x
);
1210 return convert_to_mode (tmode
, x
, unsignedp
);
1213 /* Try to use an ext(z)v pattern to extract a field from OP0.
1214 Return the extracted value on success, otherwise return null.
1215 EXT_MODE is the mode of the extraction and the other arguments
1216 are as for extract_bit_field. */
1219 extract_bit_field_using_extv (const extraction_insn
*extv
, rtx op0
,
1220 unsigned HOST_WIDE_INT bitsize
,
1221 unsigned HOST_WIDE_INT bitnum
,
1222 int unsignedp
, rtx target
,
1223 enum machine_mode mode
, enum machine_mode tmode
)
1225 struct expand_operand ops
[4];
1226 rtx spec_target
= target
;
1227 rtx spec_target_subreg
= 0;
1228 enum machine_mode ext_mode
= extv
->field_mode
;
1229 unsigned unit
= GET_MODE_BITSIZE (ext_mode
);
1231 if (bitsize
== 0 || unit
< bitsize
)
1235 /* Get a reference to the first byte of the field. */
1236 op0
= narrow_bit_field_mem (op0
, extv
->struct_mode
, bitsize
, bitnum
,
1240 /* Convert from counting within OP0 to counting in EXT_MODE. */
1241 if (BYTES_BIG_ENDIAN
)
1242 bitnum
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1244 /* If op0 is a register, we need it in EXT_MODE to make it
1245 acceptable to the format of ext(z)v. */
1246 if (GET_CODE (op0
) == SUBREG
&& GET_MODE (op0
) != ext_mode
)
1248 if (REG_P (op0
) && GET_MODE (op0
) != ext_mode
)
1249 op0
= gen_lowpart_SUBREG (ext_mode
, op0
);
1252 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1253 "backwards" from the size of the unit we are extracting from.
1254 Otherwise, we count bits from the most significant on a
1255 BYTES/BITS_BIG_ENDIAN machine. */
1257 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1258 bitnum
= unit
- bitsize
- bitnum
;
1261 target
= spec_target
= gen_reg_rtx (tmode
);
1263 if (GET_MODE (target
) != ext_mode
)
1265 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1266 between the mode of the extraction (word_mode) and the target
1267 mode. Instead, create a temporary and use convert_move to set
1270 && TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (target
), ext_mode
))
1272 target
= gen_lowpart (ext_mode
, target
);
1273 if (GET_MODE_PRECISION (ext_mode
)
1274 > GET_MODE_PRECISION (GET_MODE (spec_target
)))
1275 spec_target_subreg
= target
;
1278 target
= gen_reg_rtx (ext_mode
);
1281 create_output_operand (&ops
[0], target
, ext_mode
);
1282 create_fixed_operand (&ops
[1], op0
);
1283 create_integer_operand (&ops
[2], bitsize
);
1284 create_integer_operand (&ops
[3], bitnum
);
1285 if (maybe_expand_insn (extv
->icode
, 4, ops
))
1287 target
= ops
[0].value
;
1288 if (target
== spec_target
)
1290 if (target
== spec_target_subreg
)
1292 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1297 /* A subroutine of extract_bit_field, with the same arguments.
1298 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1299 if we can find no other means of implementing the operation.
1300 if FALLBACK_P is false, return NULL instead. */
1303 extract_bit_field_1 (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1304 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1305 enum machine_mode mode
, enum machine_mode tmode
,
1309 enum machine_mode int_mode
;
1310 enum machine_mode mode1
;
1312 if (tmode
== VOIDmode
)
1315 while (GET_CODE (op0
) == SUBREG
)
1317 bitnum
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1318 op0
= SUBREG_REG (op0
);
1321 /* If we have an out-of-bounds access to a register, just return an
1322 uninitialized register of the required mode. This can occur if the
1323 source code contains an out-of-bounds access to a small array. */
1324 if (REG_P (op0
) && bitnum
>= GET_MODE_BITSIZE (GET_MODE (op0
)))
1325 return gen_reg_rtx (tmode
);
1328 && mode
== GET_MODE (op0
)
1330 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1332 /* We're trying to extract a full register from itself. */
1336 /* See if we can get a better vector mode before extracting. */
1337 if (VECTOR_MODE_P (GET_MODE (op0
))
1339 && GET_MODE_INNER (GET_MODE (op0
)) != tmode
)
1341 enum machine_mode new_mode
;
1343 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1344 new_mode
= MIN_MODE_VECTOR_FLOAT
;
1345 else if (GET_MODE_CLASS (tmode
) == MODE_FRACT
)
1346 new_mode
= MIN_MODE_VECTOR_FRACT
;
1347 else if (GET_MODE_CLASS (tmode
) == MODE_UFRACT
)
1348 new_mode
= MIN_MODE_VECTOR_UFRACT
;
1349 else if (GET_MODE_CLASS (tmode
) == MODE_ACCUM
)
1350 new_mode
= MIN_MODE_VECTOR_ACCUM
;
1351 else if (GET_MODE_CLASS (tmode
) == MODE_UACCUM
)
1352 new_mode
= MIN_MODE_VECTOR_UACCUM
;
1354 new_mode
= MIN_MODE_VECTOR_INT
;
1356 for (; new_mode
!= VOIDmode
; new_mode
= GET_MODE_WIDER_MODE (new_mode
))
1357 if (GET_MODE_SIZE (new_mode
) == GET_MODE_SIZE (GET_MODE (op0
))
1358 && targetm
.vector_mode_supported_p (new_mode
))
1360 if (new_mode
!= VOIDmode
)
1361 op0
= gen_lowpart (new_mode
, op0
);
1364 /* Use vec_extract patterns for extracting parts of vectors whenever
1366 if (VECTOR_MODE_P (GET_MODE (op0
))
1368 && optab_handler (vec_extract_optab
, GET_MODE (op0
)) != CODE_FOR_nothing
1369 && ((bitnum
+ bitsize
- 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))
1370 == bitnum
/ GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0
)))))
1372 struct expand_operand ops
[3];
1373 enum machine_mode outermode
= GET_MODE (op0
);
1374 enum machine_mode innermode
= GET_MODE_INNER (outermode
);
1375 enum insn_code icode
= optab_handler (vec_extract_optab
, outermode
);
1376 unsigned HOST_WIDE_INT pos
= bitnum
/ GET_MODE_BITSIZE (innermode
);
1378 create_output_operand (&ops
[0], target
, innermode
);
1379 create_input_operand (&ops
[1], op0
, outermode
);
1380 create_integer_operand (&ops
[2], pos
);
1381 if (maybe_expand_insn (icode
, 3, ops
))
1383 target
= ops
[0].value
;
1384 if (GET_MODE (target
) != mode
)
1385 return gen_lowpart (tmode
, target
);
1390 /* Make sure we are playing with integral modes. Pun with subregs
1393 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1394 if (imode
!= GET_MODE (op0
))
1397 op0
= adjust_bitfield_address_size (op0
, imode
, 0, MEM_SIZE (op0
));
1398 else if (imode
!= BLKmode
)
1400 op0
= gen_lowpart (imode
, op0
);
1402 /* If we got a SUBREG, force it into a register since we
1403 aren't going to be able to do another SUBREG on it. */
1404 if (GET_CODE (op0
) == SUBREG
)
1405 op0
= force_reg (imode
, op0
);
1407 else if (REG_P (op0
))
1410 imode
= smallest_mode_for_size (GET_MODE_BITSIZE (GET_MODE (op0
)),
1412 reg
= gen_reg_rtx (imode
);
1413 subreg
= gen_lowpart_SUBREG (GET_MODE (op0
), reg
);
1414 emit_move_insn (subreg
, op0
);
1416 bitnum
+= SUBREG_BYTE (subreg
) * BITS_PER_UNIT
;
1420 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (op0
));
1421 rtx mem
= assign_stack_temp (GET_MODE (op0
), size
);
1422 emit_move_insn (mem
, op0
);
1423 op0
= adjust_bitfield_address_size (mem
, BLKmode
, 0, size
);
1428 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1429 If that's wrong, the solution is to test for it and set TARGET to 0
1432 /* If the bitfield is volatile, we need to make sure the access
1433 remains on a type-aligned boundary. */
1434 if (GET_CODE (op0
) == MEM
1435 && MEM_VOLATILE_P (op0
)
1436 && GET_MODE_BITSIZE (GET_MODE (op0
)) > 0
1437 && flag_strict_volatile_bitfields
> 0)
1438 goto no_subreg_mode_swap
;
1440 /* Only scalar integer modes can be converted via subregs. There is an
1441 additional problem for FP modes here in that they can have a precision
1442 which is different from the size. mode_for_size uses precision, but
1443 we want a mode based on the size, so we must avoid calling it for FP
1446 if (SCALAR_INT_MODE_P (tmode
))
1448 enum machine_mode try_mode
= mode_for_size (bitsize
,
1449 GET_MODE_CLASS (tmode
), 0);
1450 if (try_mode
!= BLKmode
)
1453 gcc_assert (mode1
!= BLKmode
);
1455 /* Extraction of a full MODE1 value can be done with a subreg as long
1456 as the least significant bit of the value is the least significant
1457 bit of either OP0 or a word of OP0. */
1459 && lowpart_bit_field_p (bitnum
, bitsize
, GET_MODE (op0
))
1460 && bitsize
== GET_MODE_BITSIZE (mode1
)
1461 && TRULY_NOOP_TRUNCATION_MODES_P (mode1
, GET_MODE (op0
)))
1463 rtx sub
= simplify_gen_subreg (mode1
, op0
, GET_MODE (op0
),
1464 bitnum
/ BITS_PER_UNIT
);
1466 return convert_extracted_bit_field (sub
, mode
, tmode
, unsignedp
);
1469 /* Extraction of a full MODE1 value can be done with a load as long as
1470 the field is on a byte boundary and is sufficiently aligned. */
1471 if (simple_mem_bitfield_p (op0
, bitsize
, bitnum
, mode1
))
1473 op0
= adjust_bitfield_address (op0
, mode1
, bitnum
/ BITS_PER_UNIT
);
1474 return convert_extracted_bit_field (op0
, mode
, tmode
, unsignedp
);
1477 no_subreg_mode_swap
:
1479 /* Handle fields bigger than a word. */
1481 if (bitsize
> BITS_PER_WORD
)
1483 /* Here we transfer the words of the field
1484 in the order least significant first.
1485 This is because the most significant word is the one which may
1486 be less than full. */
1488 unsigned int backwards
= WORDS_BIG_ENDIAN
;
1489 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1493 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1494 target
= gen_reg_rtx (mode
);
1496 /* Indicate for flow that the entire target reg is being set. */
1497 emit_clobber (target
);
1499 last
= get_last_insn ();
1500 for (i
= 0; i
< nwords
; i
++)
1502 /* If I is 0, use the low-order word in both field and target;
1503 if I is 1, use the next to lowest word; and so on. */
1504 /* Word number in TARGET to use. */
1505 unsigned int wordnum
1507 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1509 /* Offset from start of field in OP0. */
1510 unsigned int bit_offset
= (backwards
1511 ? MAX ((int) bitsize
- ((int) i
+ 1)
1514 : (int) i
* BITS_PER_WORD
);
1515 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1517 = extract_bit_field_1 (op0
, MIN (BITS_PER_WORD
,
1518 bitsize
- i
* BITS_PER_WORD
),
1519 bitnum
+ bit_offset
, 1, target_part
,
1520 mode
, word_mode
, fallback_p
);
1522 gcc_assert (target_part
);
1525 delete_insns_since (last
);
1529 if (result_part
!= target_part
)
1530 emit_move_insn (target_part
, result_part
);
1535 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1536 need to be zero'd out. */
1537 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1539 unsigned int i
, total_words
;
1541 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1542 for (i
= nwords
; i
< total_words
; i
++)
1544 (operand_subword (target
,
1545 backwards
? total_words
- i
- 1 : i
,
1552 /* Signed bit field: sign-extend with two arithmetic shifts. */
1553 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1554 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1555 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1556 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1559 /* If OP0 is a multi-word register, narrow it to the affected word.
1560 If the region spans two words, defer to extract_split_bit_field. */
1561 if (!MEM_P (op0
) && GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1563 op0
= simplify_gen_subreg (word_mode
, op0
, GET_MODE (op0
),
1564 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
1565 bitnum
%= BITS_PER_WORD
;
1566 if (bitnum
+ bitsize
> BITS_PER_WORD
)
1570 target
= extract_split_bit_field (op0
, bitsize
, bitnum
, unsignedp
);
1571 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1575 /* From here on we know the desired field is smaller than a word.
1576 If OP0 is a register, it too fits within a word. */
1577 enum extraction_pattern pattern
= unsignedp
? EP_extzv
: EP_extv
;
1578 extraction_insn extv
;
1580 /* ??? We could limit the structure size to the part of OP0 that
1581 contains the field, with appropriate checks for endianness
1582 and TRULY_NOOP_TRUNCATION. */
1583 && get_best_reg_extraction_insn (&extv
, pattern
,
1584 GET_MODE_BITSIZE (GET_MODE (op0
)),
1587 rtx result
= extract_bit_field_using_extv (&extv
, op0
, bitsize
, bitnum
,
1588 unsignedp
, target
, mode
,
1594 /* If OP0 is a memory, try copying it to a register and seeing if a
1595 cheap register alternative is available. */
1598 /* Do not use extv/extzv for volatile bitfields when
1599 -fstrict-volatile-bitfields is in effect. */
1600 if (!(MEM_VOLATILE_P (op0
) && flag_strict_volatile_bitfields
> 0)
1601 && get_best_mem_extraction_insn (&extv
, pattern
, bitsize
, bitnum
,
1604 rtx result
= extract_bit_field_using_extv (&extv
, op0
, bitsize
,
1612 rtx last
= get_last_insn ();
1614 /* Try loading part of OP0 into a register and extracting the
1615 bitfield from that. */
1616 unsigned HOST_WIDE_INT bitpos
;
1617 rtx xop0
= adjust_bit_field_mem_for_reg (pattern
, op0
, bitsize
, bitnum
,
1618 0, 0, tmode
, &bitpos
);
1621 xop0
= copy_to_reg (xop0
);
1622 rtx result
= extract_bit_field_1 (xop0
, bitsize
, bitpos
,
1624 mode
, tmode
, false);
1627 delete_insns_since (last
);
1634 /* Find a correspondingly-sized integer field, so we can apply
1635 shifts and masks to it. */
1636 int_mode
= int_mode_for_mode (tmode
);
1637 if (int_mode
== BLKmode
)
1638 int_mode
= int_mode_for_mode (mode
);
1639 /* Should probably push op0 out to memory and then do a load. */
1640 gcc_assert (int_mode
!= BLKmode
);
1642 target
= extract_fixed_bit_field (int_mode
, op0
, bitsize
, bitnum
,
1644 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1647 /* Generate code to extract a byte-field from STR_RTX
1648 containing BITSIZE bits, starting at BITNUM,
1649 and put it in TARGET if possible (if TARGET is nonzero).
1650 Regardless of TARGET, we return the rtx for where the value is placed.
1652 STR_RTX is the structure containing the byte (a REG or MEM).
1653 UNSIGNEDP is nonzero if this is an unsigned bit field.
1654 MODE is the natural mode of the field value once extracted.
1655 TMODE is the mode the caller would like the value to have;
1656 but the value may be returned with type MODE instead.
1658 If a TARGET is specified and we can store in it at no extra cost,
1659 we do so, and return TARGET.
1660 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
1661 if they are equally easy. */
1664 extract_bit_field (rtx str_rtx
, unsigned HOST_WIDE_INT bitsize
,
1665 unsigned HOST_WIDE_INT bitnum
, int unsignedp
, rtx target
,
1666 enum machine_mode mode
, enum machine_mode tmode
)
1668 return extract_bit_field_1 (str_rtx
, bitsize
, bitnum
, unsignedp
,
1669 target
, mode
, tmode
, true);
1672 /* Use shifts and boolean operations to extract a field of BITSIZE bits
1673 from bit BITNUM of OP0.
1675 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1676 If TARGET is nonzero, attempts to store the value there
1677 and return TARGET, but this is not guaranteed.
1678 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1681 extract_fixed_bit_field (enum machine_mode tmode
, rtx op0
,
1682 unsigned HOST_WIDE_INT bitsize
,
1683 unsigned HOST_WIDE_INT bitnum
, rtx target
,
1686 enum machine_mode mode
;
1690 /* Get the proper mode to use for this field. We want a mode that
1691 includes the entire field. If such a mode would be larger than
1692 a word, we won't be doing the extraction the normal way. */
1694 if (MEM_VOLATILE_P (op0
)
1695 && flag_strict_volatile_bitfields
> 0)
1697 if (GET_MODE_BITSIZE (GET_MODE (op0
)) > 0)
1698 mode
= GET_MODE (op0
);
1699 else if (target
&& GET_MODE_BITSIZE (GET_MODE (target
)) > 0)
1700 mode
= GET_MODE (target
);
1705 mode
= get_best_mode (bitsize
, bitnum
, 0, 0,
1706 MEM_ALIGN (op0
), word_mode
, MEM_VOLATILE_P (op0
));
1708 if (mode
== VOIDmode
)
1709 /* The only way this should occur is if the field spans word
1711 return extract_split_bit_field (op0
, bitsize
, bitnum
, unsignedp
);
1713 unsigned int total_bits
= GET_MODE_BITSIZE (mode
);
1714 HOST_WIDE_INT bit_offset
= bitnum
- bitnum
% total_bits
;
1716 /* If we're accessing a volatile MEM, we can't apply BIT_OFFSET
1717 if it results in a multi-word access where we otherwise wouldn't
1718 have one. So, check for that case here. */
1720 && MEM_VOLATILE_P (op0
)
1721 && flag_strict_volatile_bitfields
> 0
1722 && bitnum
% BITS_PER_UNIT
+ bitsize
<= total_bits
1723 && bitnum
% GET_MODE_BITSIZE (mode
) + bitsize
> total_bits
)
1725 /* If the target doesn't support unaligned access, give up and
1726 split the access into two. */
1727 if (STRICT_ALIGNMENT
)
1728 return extract_split_bit_field (op0
, bitsize
, bitnum
, unsignedp
);
1729 bit_offset
= bitnum
- bitnum
% BITS_PER_UNIT
;
1731 op0
= adjust_bitfield_address (op0
, mode
, bit_offset
/ BITS_PER_UNIT
);
1732 bitnum
-= bit_offset
;
1735 mode
= GET_MODE (op0
);
1736 gcc_assert (SCALAR_INT_MODE_P (mode
));
1738 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1739 for invalid input, such as extract equivalent of f5 from
1740 gcc.dg/pr48335-2.c. */
1742 if (BYTES_BIG_ENDIAN
)
1743 /* BITNUM is the distance between our msb and that of OP0.
1744 Convert it to the distance from the lsb. */
1745 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
1747 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
1748 We have reduced the big-endian case to the little-endian case. */
1754 /* If the field does not already start at the lsb,
1755 shift it so it does. */
1756 /* Maybe propagate the target for the shift. */
1757 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1760 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, bitnum
, subtarget
, 1);
1762 /* Convert the value to the desired mode. */
1764 op0
= convert_to_mode (tmode
, op0
, 1);
1766 /* Unless the msb of the field used to be the msb when we shifted,
1767 mask out the upper bits. */
1769 if (GET_MODE_BITSIZE (mode
) != bitnum
+ bitsize
)
1770 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1771 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1772 target
, 1, OPTAB_LIB_WIDEN
);
1776 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1777 then arithmetic-shift its lsb to the lsb of the word. */
1778 op0
= force_reg (mode
, op0
);
1780 /* Find the narrowest integer mode that contains the field. */
1782 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1783 mode
= GET_MODE_WIDER_MODE (mode
))
1784 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitnum
)
1786 op0
= convert_to_mode (mode
, op0
, 0);
1793 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitnum
))
1795 int amount
= GET_MODE_BITSIZE (mode
) - (bitsize
+ bitnum
);
1796 /* Maybe propagate the target for the shift. */
1797 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
1798 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1801 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1802 GET_MODE_BITSIZE (mode
) - bitsize
, target
, 0);
1805 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1806 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1807 complement of that if COMPLEMENT. The mask is truncated if
1808 necessary to the width of mode MODE. The mask is zero-extended if
1809 BITSIZE+BITPOS is too small for MODE. */
1812 mask_rtx (enum machine_mode mode
, int bitpos
, int bitsize
, int complement
)
1816 mask
= double_int::mask (bitsize
);
1817 mask
= mask
.llshift (bitpos
, HOST_BITS_PER_DOUBLE_INT
);
1822 return immed_double_int_const (mask
, mode
);
1825 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1829 lshift_value (enum machine_mode mode
, unsigned HOST_WIDE_INT value
,
1834 val
= double_int::from_uhwi (value
);
1835 val
= val
.llshift (bitpos
, HOST_BITS_PER_DOUBLE_INT
);
1837 return immed_double_int_const (val
, mode
);
1840 /* Extract a bit field that is split across two words
1841 and return an RTX for the result.
1843 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1844 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1845 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1848 extract_split_bit_field (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
1849 unsigned HOST_WIDE_INT bitpos
, int unsignedp
)
1852 unsigned int bitsdone
= 0;
1853 rtx result
= NULL_RTX
;
1856 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1858 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1859 unit
= BITS_PER_WORD
;
1861 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1863 while (bitsdone
< bitsize
)
1865 unsigned HOST_WIDE_INT thissize
;
1867 unsigned HOST_WIDE_INT thispos
;
1868 unsigned HOST_WIDE_INT offset
;
1870 offset
= (bitpos
+ bitsdone
) / unit
;
1871 thispos
= (bitpos
+ bitsdone
) % unit
;
1873 /* THISSIZE must not overrun a word boundary. Otherwise,
1874 extract_fixed_bit_field will call us again, and we will mutually
1876 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1877 thissize
= MIN (thissize
, unit
- thispos
);
1879 /* If OP0 is a register, then handle OFFSET here.
1881 When handling multiword bitfields, extract_bit_field may pass
1882 down a word_mode SUBREG of a larger REG for a bitfield that actually
1883 crosses a word boundary. Thus, for a SUBREG, we must find
1884 the current word starting from the base register. */
1885 if (GET_CODE (op0
) == SUBREG
)
1887 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1888 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1889 GET_MODE (SUBREG_REG (op0
)));
1892 else if (REG_P (op0
))
1894 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1900 /* Extract the parts in bit-counting order,
1901 whose meaning is determined by BYTES_PER_UNIT.
1902 OFFSET is in UNITs, and UNIT is in bits. */
1903 part
= extract_fixed_bit_field (word_mode
, word
, thissize
,
1904 offset
* unit
+ thispos
, 0, 1);
1905 bitsdone
+= thissize
;
1907 /* Shift this part into place for the result. */
1908 if (BYTES_BIG_ENDIAN
)
1910 if (bitsize
!= bitsdone
)
1911 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1912 bitsize
- bitsdone
, 0, 1);
1916 if (bitsdone
!= thissize
)
1917 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1918 bitsdone
- thissize
, 0, 1);
1924 /* Combine the parts with bitwise or. This works
1925 because we extracted each part as an unsigned bit field. */
1926 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
1932 /* Unsigned bit field: we are done. */
1935 /* Signed bit field: sign-extend with two arithmetic shifts. */
1936 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
1937 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
1938 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
1939 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
1942 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
1943 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
1944 MODE, fill the upper bits with zeros. Fail if the layout of either
1945 mode is unknown (as for CC modes) or if the extraction would involve
1946 unprofitable mode punning. Return the value on success, otherwise
1949 This is different from gen_lowpart* in these respects:
1951 - the returned value must always be considered an rvalue
1953 - when MODE is wider than SRC_MODE, the extraction involves
1956 - when MODE is smaller than SRC_MODE, the extraction involves
1957 a truncation (and is thus subject to TRULY_NOOP_TRUNCATION).
1959 In other words, this routine performs a computation, whereas the
1960 gen_lowpart* routines are conceptually lvalue or rvalue subreg
1964 extract_low_bits (enum machine_mode mode
, enum machine_mode src_mode
, rtx src
)
1966 enum machine_mode int_mode
, src_int_mode
;
1968 if (mode
== src_mode
)
1971 if (CONSTANT_P (src
))
1973 /* simplify_gen_subreg can't be used here, as if simplify_subreg
1974 fails, it will happily create (subreg (symbol_ref)) or similar
1976 unsigned int byte
= subreg_lowpart_offset (mode
, src_mode
);
1977 rtx ret
= simplify_subreg (mode
, src
, src_mode
, byte
);
1981 if (GET_MODE (src
) == VOIDmode
1982 || !validate_subreg (mode
, src_mode
, src
, byte
))
1985 src
= force_reg (GET_MODE (src
), src
);
1986 return gen_rtx_SUBREG (mode
, src
, byte
);
1989 if (GET_MODE_CLASS (mode
) == MODE_CC
|| GET_MODE_CLASS (src_mode
) == MODE_CC
)
1992 if (GET_MODE_BITSIZE (mode
) == GET_MODE_BITSIZE (src_mode
)
1993 && MODES_TIEABLE_P (mode
, src_mode
))
1995 rtx x
= gen_lowpart_common (mode
, src
);
2000 src_int_mode
= int_mode_for_mode (src_mode
);
2001 int_mode
= int_mode_for_mode (mode
);
2002 if (src_int_mode
== BLKmode
|| int_mode
== BLKmode
)
2005 if (!MODES_TIEABLE_P (src_int_mode
, src_mode
))
2007 if (!MODES_TIEABLE_P (int_mode
, mode
))
2010 src
= gen_lowpart (src_int_mode
, src
);
2011 src
= convert_modes (int_mode
, src_int_mode
, src
, true);
2012 src
= gen_lowpart (mode
, src
);
2016 /* Add INC into TARGET. */
2019 expand_inc (rtx target
, rtx inc
)
2021 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
2023 target
, 0, OPTAB_LIB_WIDEN
);
2024 if (value
!= target
)
2025 emit_move_insn (target
, value
);
2028 /* Subtract DEC from TARGET. */
2031 expand_dec (rtx target
, rtx dec
)
2033 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
2035 target
, 0, OPTAB_LIB_WIDEN
);
2036 if (value
!= target
)
2037 emit_move_insn (target
, value
);
2040 /* Output a shift instruction for expression code CODE,
2041 with SHIFTED being the rtx for the value to shift,
2042 and AMOUNT the rtx for the amount to shift by.
2043 Store the result in the rtx TARGET, if that is convenient.
2044 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2045 Return the rtx for where the value is. */
2048 expand_shift_1 (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2049 rtx amount
, rtx target
, int unsignedp
)
2052 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2053 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2054 optab lshift_optab
= ashl_optab
;
2055 optab rshift_arith_optab
= ashr_optab
;
2056 optab rshift_uns_optab
= lshr_optab
;
2057 optab lrotate_optab
= rotl_optab
;
2058 optab rrotate_optab
= rotr_optab
;
2059 enum machine_mode op1_mode
;
2061 bool speed
= optimize_insn_for_speed_p ();
2064 op1_mode
= GET_MODE (op1
);
2066 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2067 shift amount is a vector, use the vector/vector shift patterns. */
2068 if (VECTOR_MODE_P (mode
) && VECTOR_MODE_P (op1_mode
))
2070 lshift_optab
= vashl_optab
;
2071 rshift_arith_optab
= vashr_optab
;
2072 rshift_uns_optab
= vlshr_optab
;
2073 lrotate_optab
= vrotl_optab
;
2074 rrotate_optab
= vrotr_optab
;
2077 /* Previously detected shift-counts computed by NEGATE_EXPR
2078 and shifted in the other direction; but that does not work
2081 if (SHIFT_COUNT_TRUNCATED
)
2083 if (CONST_INT_P (op1
)
2084 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2085 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
2086 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
2087 % GET_MODE_BITSIZE (mode
));
2088 else if (GET_CODE (op1
) == SUBREG
2089 && subreg_lowpart_p (op1
)
2090 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1
)))
2091 && SCALAR_INT_MODE_P (GET_MODE (op1
)))
2092 op1
= SUBREG_REG (op1
);
2095 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
2096 prefer left rotation, if op1 is from bitsize / 2 + 1 to
2097 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
2100 && CONST_INT_P (op1
)
2101 && IN_RANGE (INTVAL (op1
), GET_MODE_BITSIZE (mode
) / 2 + left
,
2102 GET_MODE_BITSIZE (mode
) - 1))
2104 op1
= GEN_INT (GET_MODE_BITSIZE (mode
) - INTVAL (op1
));
2106 code
= left
? LROTATE_EXPR
: RROTATE_EXPR
;
2109 if (op1
== const0_rtx
)
2112 /* Check whether its cheaper to implement a left shift by a constant
2113 bit count by a sequence of additions. */
2114 if (code
== LSHIFT_EXPR
2115 && CONST_INT_P (op1
)
2117 && INTVAL (op1
) < GET_MODE_PRECISION (mode
)
2118 && INTVAL (op1
) < MAX_BITS_PER_WORD
2119 && (shift_cost (speed
, mode
, INTVAL (op1
))
2120 > INTVAL (op1
) * add_cost (speed
, mode
))
2121 && shift_cost (speed
, mode
, INTVAL (op1
)) != MAX_COST
)
2124 for (i
= 0; i
< INTVAL (op1
); i
++)
2126 temp
= force_reg (mode
, shifted
);
2127 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2128 unsignedp
, OPTAB_LIB_WIDEN
);
2133 for (attempt
= 0; temp
== 0 && attempt
< 3; attempt
++)
2135 enum optab_methods methods
;
2138 methods
= OPTAB_DIRECT
;
2139 else if (attempt
== 1)
2140 methods
= OPTAB_WIDEN
;
2142 methods
= OPTAB_LIB_WIDEN
;
2146 /* Widening does not work for rotation. */
2147 if (methods
== OPTAB_WIDEN
)
2149 else if (methods
== OPTAB_LIB_WIDEN
)
2151 /* If we have been unable to open-code this by a rotation,
2152 do it as the IOR of two shifts. I.e., to rotate A
2154 (A << N) | ((unsigned) A >> ((-N) & (C - 1)))
2155 where C is the bitsize of A.
2157 It is theoretically possible that the target machine might
2158 not be able to perform either shift and hence we would
2159 be making two libcalls rather than just the one for the
2160 shift (similarly if IOR could not be done). We will allow
2161 this extremely unlikely lossage to avoid complicating the
2164 rtx subtarget
= target
== shifted
? 0 : target
;
2165 rtx new_amount
, other_amount
;
2169 if (op1
== const0_rtx
)
2171 else if (CONST_INT_P (op1
))
2172 other_amount
= GEN_INT (GET_MODE_BITSIZE (mode
)
2177 = simplify_gen_unary (NEG
, GET_MODE (op1
),
2178 op1
, GET_MODE (op1
));
2179 HOST_WIDE_INT mask
= GET_MODE_PRECISION (mode
) - 1;
2181 = simplify_gen_binary (AND
, GET_MODE (op1
), other_amount
,
2182 gen_int_mode (mask
, GET_MODE (op1
)));
2185 shifted
= force_reg (mode
, shifted
);
2187 temp
= expand_shift_1 (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2188 mode
, shifted
, new_amount
, 0, 1);
2189 temp1
= expand_shift_1 (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2190 mode
, shifted
, other_amount
,
2192 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2193 unsignedp
, methods
);
2196 temp
= expand_binop (mode
,
2197 left
? lrotate_optab
: rrotate_optab
,
2198 shifted
, op1
, target
, unsignedp
, methods
);
2201 temp
= expand_binop (mode
,
2202 left
? lshift_optab
: rshift_uns_optab
,
2203 shifted
, op1
, target
, unsignedp
, methods
);
2205 /* Do arithmetic shifts.
2206 Also, if we are going to widen the operand, we can just as well
2207 use an arithmetic right-shift instead of a logical one. */
2208 if (temp
== 0 && ! rotate
2209 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2211 enum optab_methods methods1
= methods
;
2213 /* If trying to widen a log shift to an arithmetic shift,
2214 don't accept an arithmetic shift of the same size. */
2216 methods1
= OPTAB_MUST_WIDEN
;
2218 /* Arithmetic shift */
2220 temp
= expand_binop (mode
,
2221 left
? lshift_optab
: rshift_arith_optab
,
2222 shifted
, op1
, target
, unsignedp
, methods1
);
2225 /* We used to try extzv here for logical right shifts, but that was
2226 only useful for one machine, the VAX, and caused poor code
2227 generation there for lshrdi3, so the code was deleted and a
2228 define_expand for lshrsi3 was added to vax.md. */
2235 /* Output a shift instruction for expression code CODE,
2236 with SHIFTED being the rtx for the value to shift,
2237 and AMOUNT the amount to shift by.
2238 Store the result in the rtx TARGET, if that is convenient.
2239 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2240 Return the rtx for where the value is. */
2243 expand_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2244 int amount
, rtx target
, int unsignedp
)
2246 return expand_shift_1 (code
, mode
,
2247 shifted
, GEN_INT (amount
), target
, unsignedp
);
2250 /* Output a shift instruction for expression code CODE,
2251 with SHIFTED being the rtx for the value to shift,
2252 and AMOUNT the tree for the amount to shift by.
2253 Store the result in the rtx TARGET, if that is convenient.
2254 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2255 Return the rtx for where the value is. */
2258 expand_variable_shift (enum tree_code code
, enum machine_mode mode
, rtx shifted
,
2259 tree amount
, rtx target
, int unsignedp
)
2261 return expand_shift_1 (code
, mode
,
2262 shifted
, expand_normal (amount
), target
, unsignedp
);
2266 /* Indicates the type of fixup needed after a constant multiplication.
2267 BASIC_VARIANT means no fixup is needed, NEGATE_VARIANT means that
2268 the result should be negated, and ADD_VARIANT means that the
2269 multiplicand should be added to the result. */
2270 enum mult_variant
{basic_variant
, negate_variant
, add_variant
};
2272 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2273 const struct mult_cost
*, enum machine_mode mode
);
2274 static bool choose_mult_variant (enum machine_mode
, HOST_WIDE_INT
,
2275 struct algorithm
*, enum mult_variant
*, int);
2276 static rtx
expand_mult_const (enum machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2277 const struct algorithm
*, enum mult_variant
);
2278 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2279 static rtx
extract_high_half (enum machine_mode
, rtx
);
2280 static rtx
expmed_mult_highpart (enum machine_mode
, rtx
, rtx
, rtx
, int, int);
2281 static rtx
expmed_mult_highpart_optab (enum machine_mode
, rtx
, rtx
, rtx
,
2283 /* Compute and return the best algorithm for multiplying by T.
2284 The algorithm must cost less than cost_limit
2285 If retval.cost >= COST_LIMIT, no algorithm was found and all
2286 other field of the returned struct are undefined.
2287 MODE is the machine mode of the multiplication. */
2290 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2291 const struct mult_cost
*cost_limit
, enum machine_mode mode
)
2294 struct algorithm
*alg_in
, *best_alg
;
2295 struct mult_cost best_cost
;
2296 struct mult_cost new_limit
;
2297 int op_cost
, op_latency
;
2298 unsigned HOST_WIDE_INT orig_t
= t
;
2299 unsigned HOST_WIDE_INT q
;
2300 int maxm
, hash_index
;
2301 bool cache_hit
= false;
2302 enum alg_code cache_alg
= alg_zero
;
2303 bool speed
= optimize_insn_for_speed_p ();
2304 enum machine_mode imode
;
2305 struct alg_hash_entry
*entry_ptr
;
2307 /* Indicate that no algorithm is yet found. If no algorithm
2308 is found, this value will be returned and indicate failure. */
2309 alg_out
->cost
.cost
= cost_limit
->cost
+ 1;
2310 alg_out
->cost
.latency
= cost_limit
->latency
+ 1;
2312 if (cost_limit
->cost
< 0
2313 || (cost_limit
->cost
== 0 && cost_limit
->latency
<= 0))
2316 /* Be prepared for vector modes. */
2317 imode
= GET_MODE_INNER (mode
);
2318 if (imode
== VOIDmode
)
2321 maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (imode
));
2323 /* Restrict the bits of "t" to the multiplication's mode. */
2324 t
&= GET_MODE_MASK (imode
);
2326 /* t == 1 can be done in zero cost. */
2330 alg_out
->cost
.cost
= 0;
2331 alg_out
->cost
.latency
= 0;
2332 alg_out
->op
[0] = alg_m
;
2336 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2340 if (MULT_COST_LESS (cost_limit
, zero_cost (speed
)))
2345 alg_out
->cost
.cost
= zero_cost (speed
);
2346 alg_out
->cost
.latency
= zero_cost (speed
);
2347 alg_out
->op
[0] = alg_zero
;
2352 /* We'll be needing a couple extra algorithm structures now. */
2354 alg_in
= XALLOCA (struct algorithm
);
2355 best_alg
= XALLOCA (struct algorithm
);
2356 best_cost
= *cost_limit
;
2358 /* Compute the hash index. */
2359 hash_index
= (t
^ (unsigned int) mode
^ (speed
* 256)) % NUM_ALG_HASH_ENTRIES
;
2361 /* See if we already know what to do for T. */
2362 entry_ptr
= alg_hash_entry_ptr (hash_index
);
2363 if (entry_ptr
->t
== t
2364 && entry_ptr
->mode
== mode
2365 && entry_ptr
->mode
== mode
2366 && entry_ptr
->speed
== speed
2367 && entry_ptr
->alg
!= alg_unknown
)
2369 cache_alg
= entry_ptr
->alg
;
2371 if (cache_alg
== alg_impossible
)
2373 /* The cache tells us that it's impossible to synthesize
2374 multiplication by T within entry_ptr->cost. */
2375 if (!CHEAPER_MULT_COST (&entry_ptr
->cost
, cost_limit
))
2376 /* COST_LIMIT is at least as restrictive as the one
2377 recorded in the hash table, in which case we have no
2378 hope of synthesizing a multiplication. Just
2382 /* If we get here, COST_LIMIT is less restrictive than the
2383 one recorded in the hash table, so we may be able to
2384 synthesize a multiplication. Proceed as if we didn't
2385 have the cache entry. */
2389 if (CHEAPER_MULT_COST (cost_limit
, &entry_ptr
->cost
))
2390 /* The cached algorithm shows that this multiplication
2391 requires more cost than COST_LIMIT. Just return. This
2392 way, we don't clobber this cache entry with
2393 alg_impossible but retain useful information. */
2405 goto do_alg_addsub_t_m2
;
2407 case alg_add_factor
:
2408 case alg_sub_factor
:
2409 goto do_alg_addsub_factor
;
2412 goto do_alg_add_t2_m
;
2415 goto do_alg_sub_t2_m
;
2423 /* If we have a group of zero bits at the low-order part of T, try
2424 multiplying by the remaining bits and then doing a shift. */
2429 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2433 /* The function expand_shift will choose between a shift and
2434 a sequence of additions, so the observed cost is given as
2435 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2436 op_cost
= m
* add_cost (speed
, mode
);
2437 if (shift_cost (speed
, mode
, m
) < op_cost
)
2438 op_cost
= shift_cost (speed
, mode
, m
);
2439 new_limit
.cost
= best_cost
.cost
- op_cost
;
2440 new_limit
.latency
= best_cost
.latency
- op_cost
;
2441 synth_mult (alg_in
, q
, &new_limit
, mode
);
2443 alg_in
->cost
.cost
+= op_cost
;
2444 alg_in
->cost
.latency
+= op_cost
;
2445 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2447 struct algorithm
*x
;
2448 best_cost
= alg_in
->cost
;
2449 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2450 best_alg
->log
[best_alg
->ops
] = m
;
2451 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2454 /* See if treating ORIG_T as a signed number yields a better
2455 sequence. Try this sequence only for a negative ORIG_T
2456 as it would be useless for a non-negative ORIG_T. */
2457 if ((HOST_WIDE_INT
) orig_t
< 0)
2459 /* Shift ORIG_T as follows because a right shift of a
2460 negative-valued signed type is implementation
2462 q
= ~(~orig_t
>> m
);
2463 /* The function expand_shift will choose between a shift
2464 and a sequence of additions, so the observed cost is
2465 given as MIN (m * add_cost(speed, mode),
2466 shift_cost(speed, mode, m)). */
2467 op_cost
= m
* add_cost (speed
, mode
);
2468 if (shift_cost (speed
, mode
, m
) < op_cost
)
2469 op_cost
= shift_cost (speed
, mode
, m
);
2470 new_limit
.cost
= best_cost
.cost
- op_cost
;
2471 new_limit
.latency
= best_cost
.latency
- op_cost
;
2472 synth_mult (alg_in
, q
, &new_limit
, mode
);
2474 alg_in
->cost
.cost
+= op_cost
;
2475 alg_in
->cost
.latency
+= op_cost
;
2476 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2478 struct algorithm
*x
;
2479 best_cost
= alg_in
->cost
;
2480 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2481 best_alg
->log
[best_alg
->ops
] = m
;
2482 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2490 /* If we have an odd number, add or subtract one. */
2493 unsigned HOST_WIDE_INT w
;
2496 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2498 /* If T was -1, then W will be zero after the loop. This is another
2499 case where T ends with ...111. Handling this with (T + 1) and
2500 subtract 1 produces slightly better code and results in algorithm
2501 selection much faster than treating it like the ...0111 case
2505 /* Reject the case where t is 3.
2506 Thus we prefer addition in that case. */
2509 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2511 op_cost
= add_cost (speed
, mode
);
2512 new_limit
.cost
= best_cost
.cost
- op_cost
;
2513 new_limit
.latency
= best_cost
.latency
- op_cost
;
2514 synth_mult (alg_in
, t
+ 1, &new_limit
, mode
);
2516 alg_in
->cost
.cost
+= op_cost
;
2517 alg_in
->cost
.latency
+= op_cost
;
2518 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2520 struct algorithm
*x
;
2521 best_cost
= alg_in
->cost
;
2522 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2523 best_alg
->log
[best_alg
->ops
] = 0;
2524 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2529 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2531 op_cost
= add_cost (speed
, mode
);
2532 new_limit
.cost
= best_cost
.cost
- op_cost
;
2533 new_limit
.latency
= best_cost
.latency
- op_cost
;
2534 synth_mult (alg_in
, t
- 1, &new_limit
, mode
);
2536 alg_in
->cost
.cost
+= op_cost
;
2537 alg_in
->cost
.latency
+= op_cost
;
2538 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2540 struct algorithm
*x
;
2541 best_cost
= alg_in
->cost
;
2542 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2543 best_alg
->log
[best_alg
->ops
] = 0;
2544 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2548 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2549 quickly with a - a * n for some appropriate constant n. */
2550 m
= exact_log2 (-orig_t
+ 1);
2551 if (m
>= 0 && m
< maxm
)
2553 op_cost
= shiftsub1_cost (speed
, mode
, m
);
2554 new_limit
.cost
= best_cost
.cost
- op_cost
;
2555 new_limit
.latency
= best_cost
.latency
- op_cost
;
2556 synth_mult (alg_in
, (unsigned HOST_WIDE_INT
) (-orig_t
+ 1) >> m
,
2559 alg_in
->cost
.cost
+= op_cost
;
2560 alg_in
->cost
.latency
+= op_cost
;
2561 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2563 struct algorithm
*x
;
2564 best_cost
= alg_in
->cost
;
2565 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2566 best_alg
->log
[best_alg
->ops
] = m
;
2567 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2575 /* Look for factors of t of the form
2576 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2577 If we find such a factor, we can multiply by t using an algorithm that
2578 multiplies by q, shift the result by m and add/subtract it to itself.
2580 We search for large factors first and loop down, even if large factors
2581 are less probable than small; if we find a large factor we will find a
2582 good sequence quickly, and therefore be able to prune (by decreasing
2583 COST_LIMIT) the search. */
2585 do_alg_addsub_factor
:
2586 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2588 unsigned HOST_WIDE_INT d
;
2590 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2591 if (t
% d
== 0 && t
> d
&& m
< maxm
2592 && (!cache_hit
|| cache_alg
== alg_add_factor
))
2594 /* If the target has a cheap shift-and-add instruction use
2595 that in preference to a shift insn followed by an add insn.
2596 Assume that the shift-and-add is "atomic" with a latency
2597 equal to its cost, otherwise assume that on superscalar
2598 hardware the shift may be executed concurrently with the
2599 earlier steps in the algorithm. */
2600 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2601 if (shiftadd_cost (speed
, mode
, m
) < op_cost
)
2603 op_cost
= shiftadd_cost (speed
, mode
, m
);
2604 op_latency
= op_cost
;
2607 op_latency
= add_cost (speed
, mode
);
2609 new_limit
.cost
= best_cost
.cost
- op_cost
;
2610 new_limit
.latency
= best_cost
.latency
- op_latency
;
2611 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2613 alg_in
->cost
.cost
+= op_cost
;
2614 alg_in
->cost
.latency
+= op_latency
;
2615 if (alg_in
->cost
.latency
< op_cost
)
2616 alg_in
->cost
.latency
= op_cost
;
2617 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2619 struct algorithm
*x
;
2620 best_cost
= alg_in
->cost
;
2621 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2622 best_alg
->log
[best_alg
->ops
] = m
;
2623 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2625 /* Other factors will have been taken care of in the recursion. */
2629 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2630 if (t
% d
== 0 && t
> d
&& m
< maxm
2631 && (!cache_hit
|| cache_alg
== alg_sub_factor
))
2633 /* If the target has a cheap shift-and-subtract insn use
2634 that in preference to a shift insn followed by a sub insn.
2635 Assume that the shift-and-sub is "atomic" with a latency
2636 equal to it's cost, otherwise assume that on superscalar
2637 hardware the shift may be executed concurrently with the
2638 earlier steps in the algorithm. */
2639 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2640 if (shiftsub0_cost (speed
, mode
, m
) < op_cost
)
2642 op_cost
= shiftsub0_cost (speed
, mode
, m
);
2643 op_latency
= op_cost
;
2646 op_latency
= add_cost (speed
, mode
);
2648 new_limit
.cost
= best_cost
.cost
- op_cost
;
2649 new_limit
.latency
= best_cost
.latency
- op_latency
;
2650 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
2652 alg_in
->cost
.cost
+= op_cost
;
2653 alg_in
->cost
.latency
+= op_latency
;
2654 if (alg_in
->cost
.latency
< op_cost
)
2655 alg_in
->cost
.latency
= op_cost
;
2656 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2658 struct algorithm
*x
;
2659 best_cost
= alg_in
->cost
;
2660 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2661 best_alg
->log
[best_alg
->ops
] = m
;
2662 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2670 /* Try shift-and-add (load effective address) instructions,
2671 i.e. do a*3, a*5, a*9. */
2678 if (m
>= 0 && m
< maxm
)
2680 op_cost
= shiftadd_cost (speed
, mode
, m
);
2681 new_limit
.cost
= best_cost
.cost
- op_cost
;
2682 new_limit
.latency
= best_cost
.latency
- op_cost
;
2683 synth_mult (alg_in
, (t
- 1) >> m
, &new_limit
, mode
);
2685 alg_in
->cost
.cost
+= op_cost
;
2686 alg_in
->cost
.latency
+= op_cost
;
2687 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2689 struct algorithm
*x
;
2690 best_cost
= alg_in
->cost
;
2691 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2692 best_alg
->log
[best_alg
->ops
] = m
;
2693 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2703 if (m
>= 0 && m
< maxm
)
2705 op_cost
= shiftsub0_cost (speed
, mode
, m
);
2706 new_limit
.cost
= best_cost
.cost
- op_cost
;
2707 new_limit
.latency
= best_cost
.latency
- op_cost
;
2708 synth_mult (alg_in
, (t
+ 1) >> m
, &new_limit
, mode
);
2710 alg_in
->cost
.cost
+= op_cost
;
2711 alg_in
->cost
.latency
+= op_cost
;
2712 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2714 struct algorithm
*x
;
2715 best_cost
= alg_in
->cost
;
2716 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2717 best_alg
->log
[best_alg
->ops
] = m
;
2718 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2726 /* If best_cost has not decreased, we have not found any algorithm. */
2727 if (!CHEAPER_MULT_COST (&best_cost
, cost_limit
))
2729 /* We failed to find an algorithm. Record alg_impossible for
2730 this case (that is, <T, MODE, COST_LIMIT>) so that next time
2731 we are asked to find an algorithm for T within the same or
2732 lower COST_LIMIT, we can immediately return to the
2735 entry_ptr
->mode
= mode
;
2736 entry_ptr
->speed
= speed
;
2737 entry_ptr
->alg
= alg_impossible
;
2738 entry_ptr
->cost
= *cost_limit
;
2742 /* Cache the result. */
2746 entry_ptr
->mode
= mode
;
2747 entry_ptr
->speed
= speed
;
2748 entry_ptr
->alg
= best_alg
->op
[best_alg
->ops
];
2749 entry_ptr
->cost
.cost
= best_cost
.cost
;
2750 entry_ptr
->cost
.latency
= best_cost
.latency
;
2753 /* If we are getting a too long sequence for `struct algorithm'
2754 to record, make this search fail. */
2755 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2758 /* Copy the algorithm from temporary space to the space at alg_out.
2759 We avoid using structure assignment because the majority of
2760 best_alg is normally undefined, and this is a critical function. */
2761 alg_out
->ops
= best_alg
->ops
+ 1;
2762 alg_out
->cost
= best_cost
;
2763 memcpy (alg_out
->op
, best_alg
->op
,
2764 alg_out
->ops
* sizeof *alg_out
->op
);
2765 memcpy (alg_out
->log
, best_alg
->log
,
2766 alg_out
->ops
* sizeof *alg_out
->log
);
2769 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
2770 Try three variations:
2772 - a shift/add sequence based on VAL itself
2773 - a shift/add sequence based on -VAL, followed by a negation
2774 - a shift/add sequence based on VAL - 1, followed by an addition.
2776 Return true if the cheapest of these cost less than MULT_COST,
2777 describing the algorithm in *ALG and final fixup in *VARIANT. */
2780 choose_mult_variant (enum machine_mode mode
, HOST_WIDE_INT val
,
2781 struct algorithm
*alg
, enum mult_variant
*variant
,
2784 struct algorithm alg2
;
2785 struct mult_cost limit
;
2787 bool speed
= optimize_insn_for_speed_p ();
2789 /* Fail quickly for impossible bounds. */
2793 /* Ensure that mult_cost provides a reasonable upper bound.
2794 Any constant multiplication can be performed with less
2795 than 2 * bits additions. */
2796 op_cost
= 2 * GET_MODE_UNIT_BITSIZE (mode
) * add_cost (speed
, mode
);
2797 if (mult_cost
> op_cost
)
2798 mult_cost
= op_cost
;
2800 *variant
= basic_variant
;
2801 limit
.cost
= mult_cost
;
2802 limit
.latency
= mult_cost
;
2803 synth_mult (alg
, val
, &limit
, mode
);
2805 /* This works only if the inverted value actually fits in an
2807 if (HOST_BITS_PER_INT
>= GET_MODE_UNIT_BITSIZE (mode
))
2809 op_cost
= neg_cost(speed
, mode
);
2810 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2812 limit
.cost
= alg
->cost
.cost
- op_cost
;
2813 limit
.latency
= alg
->cost
.latency
- op_cost
;
2817 limit
.cost
= mult_cost
- op_cost
;
2818 limit
.latency
= mult_cost
- op_cost
;
2821 synth_mult (&alg2
, -val
, &limit
, mode
);
2822 alg2
.cost
.cost
+= op_cost
;
2823 alg2
.cost
.latency
+= op_cost
;
2824 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2825 *alg
= alg2
, *variant
= negate_variant
;
2828 /* This proves very useful for division-by-constant. */
2829 op_cost
= add_cost (speed
, mode
);
2830 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
2832 limit
.cost
= alg
->cost
.cost
- op_cost
;
2833 limit
.latency
= alg
->cost
.latency
- op_cost
;
2837 limit
.cost
= mult_cost
- op_cost
;
2838 limit
.latency
= mult_cost
- op_cost
;
2841 synth_mult (&alg2
, val
- 1, &limit
, mode
);
2842 alg2
.cost
.cost
+= op_cost
;
2843 alg2
.cost
.latency
+= op_cost
;
2844 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
2845 *alg
= alg2
, *variant
= add_variant
;
2847 return MULT_COST_LESS (&alg
->cost
, mult_cost
);
2850 /* A subroutine of expand_mult, used for constant multiplications.
2851 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
2852 convenient. Use the shift/add sequence described by ALG and apply
2853 the final fixup specified by VARIANT. */
2856 expand_mult_const (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
2857 rtx target
, const struct algorithm
*alg
,
2858 enum mult_variant variant
)
2860 HOST_WIDE_INT val_so_far
;
2861 rtx insn
, accum
, tem
;
2863 enum machine_mode nmode
;
2865 /* Avoid referencing memory over and over and invalid sharing
2867 op0
= force_reg (mode
, op0
);
2869 /* ACCUM starts out either as OP0 or as a zero, depending on
2870 the first operation. */
2872 if (alg
->op
[0] == alg_zero
)
2874 accum
= copy_to_mode_reg (mode
, CONST0_RTX (mode
));
2877 else if (alg
->op
[0] == alg_m
)
2879 accum
= copy_to_mode_reg (mode
, op0
);
2885 for (opno
= 1; opno
< alg
->ops
; opno
++)
2887 int log
= alg
->log
[opno
];
2888 rtx shift_subtarget
= optimize
? 0 : accum
;
2890 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
2893 rtx accum_target
= optimize
? 0 : accum
;
2896 switch (alg
->op
[opno
])
2899 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
2900 /* REG_EQUAL note will be attached to the following insn. */
2901 emit_move_insn (accum
, tem
);
2906 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
2907 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2908 add_target
? add_target
: accum_target
);
2909 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2913 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
2914 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2915 add_target
? add_target
: accum_target
);
2916 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2920 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2921 log
, shift_subtarget
, 0);
2922 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2923 add_target
? add_target
: accum_target
);
2924 val_so_far
= (val_so_far
<< log
) + 1;
2928 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2929 log
, shift_subtarget
, 0);
2930 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2931 add_target
? add_target
: accum_target
);
2932 val_so_far
= (val_so_far
<< log
) - 1;
2935 case alg_add_factor
:
2936 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
2937 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2938 add_target
? add_target
: accum_target
);
2939 val_so_far
+= val_so_far
<< log
;
2942 case alg_sub_factor
:
2943 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
2944 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2946 ? add_target
: (optimize
? 0 : tem
)));
2947 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2954 if (SCALAR_INT_MODE_P (mode
))
2956 /* Write a REG_EQUAL note on the last insn so that we can cse
2957 multiplication sequences. Note that if ACCUM is a SUBREG,
2958 we've set the inner register and must properly indicate that. */
2959 tem
= op0
, nmode
= mode
;
2960 accum_inner
= accum
;
2961 if (GET_CODE (accum
) == SUBREG
)
2963 accum_inner
= SUBREG_REG (accum
);
2964 nmode
= GET_MODE (accum_inner
);
2965 tem
= gen_lowpart (nmode
, op0
);
2968 insn
= get_last_insn ();
2969 set_dst_reg_note (insn
, REG_EQUAL
,
2970 gen_rtx_MULT (nmode
, tem
,
2971 gen_int_mode (val_so_far
, nmode
)),
2976 if (variant
== negate_variant
)
2978 val_so_far
= -val_so_far
;
2979 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
2981 else if (variant
== add_variant
)
2983 val_so_far
= val_so_far
+ 1;
2984 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
2987 /* Compare only the bits of val and val_so_far that are significant
2988 in the result mode, to avoid sign-/zero-extension confusion. */
2989 nmode
= GET_MODE_INNER (mode
);
2990 if (nmode
== VOIDmode
)
2992 val
&= GET_MODE_MASK (nmode
);
2993 val_so_far
&= GET_MODE_MASK (nmode
);
2994 gcc_assert (val
== val_so_far
);
2999 /* Perform a multiplication and return an rtx for the result.
3000 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3001 TARGET is a suggestion for where to store the result (an rtx).
3003 We check specially for a constant integer as OP1.
3004 If you want this check for OP0 as well, then before calling
3005 you should swap the two operands if OP0 would be constant. */
3008 expand_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3011 enum mult_variant variant
;
3012 struct algorithm algorithm
;
3015 bool speed
= optimize_insn_for_speed_p ();
3016 bool do_trapv
= flag_trapv
&& SCALAR_INT_MODE_P (mode
) && !unsignedp
;
3018 if (CONSTANT_P (op0
))
3025 /* For vectors, there are several simplifications that can be made if
3026 all elements of the vector constant are identical. */
3028 if (GET_CODE (op1
) == CONST_VECTOR
)
3030 int i
, n
= CONST_VECTOR_NUNITS (op1
);
3031 scalar_op1
= CONST_VECTOR_ELT (op1
, 0);
3032 for (i
= 1; i
< n
; ++i
)
3033 if (!rtx_equal_p (scalar_op1
, CONST_VECTOR_ELT (op1
, i
)))
3037 if (INTEGRAL_MODE_P (mode
))
3040 HOST_WIDE_INT coeff
;
3044 if (op1
== CONST0_RTX (mode
))
3046 if (op1
== CONST1_RTX (mode
))
3048 if (op1
== CONSTM1_RTX (mode
))
3049 return expand_unop (mode
, do_trapv
? negv_optab
: neg_optab
,
3055 /* These are the operations that are potentially turned into
3056 a sequence of shifts and additions. */
3057 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
3059 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3060 less than or equal in size to `unsigned int' this doesn't matter.
3061 If the mode is larger than `unsigned int', then synth_mult works
3062 only if the constant value exactly fits in an `unsigned int' without
3063 any truncation. This means that multiplying by negative values does
3064 not work; results are off by 2^32 on a 32 bit machine. */
3066 if (CONST_INT_P (scalar_op1
))
3068 coeff
= INTVAL (scalar_op1
);
3071 else if (CONST_DOUBLE_AS_INT_P (scalar_op1
))
3073 /* If we are multiplying in DImode, it may still be a win
3074 to try to work with shifts and adds. */
3075 if (CONST_DOUBLE_HIGH (scalar_op1
) == 0
3076 && (CONST_DOUBLE_LOW (scalar_op1
) > 0
3077 || (CONST_DOUBLE_LOW (scalar_op1
) < 0
3078 && EXACT_POWER_OF_2_OR_ZERO_P
3079 (CONST_DOUBLE_LOW (scalar_op1
)))))
3081 coeff
= CONST_DOUBLE_LOW (scalar_op1
);
3084 else if (CONST_DOUBLE_LOW (scalar_op1
) == 0)
3086 coeff
= CONST_DOUBLE_HIGH (scalar_op1
);
3087 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3089 int shift
= floor_log2 (coeff
) + HOST_BITS_PER_WIDE_INT
;
3090 if (shift
< HOST_BITS_PER_DOUBLE_INT
- 1
3091 || mode_bitsize
<= HOST_BITS_PER_DOUBLE_INT
)
3092 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3093 shift
, target
, unsignedp
);
3103 /* We used to test optimize here, on the grounds that it's better to
3104 produce a smaller program when -O is not used. But this causes
3105 such a terrible slowdown sometimes that it seems better to always
3108 /* Special case powers of two. */
3109 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
)
3110 && !(is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
))
3111 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3112 floor_log2 (coeff
), target
, unsignedp
);
3114 fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3116 /* Attempt to handle multiplication of DImode values by negative
3117 coefficients, by performing the multiplication by a positive
3118 multiplier and then inverting the result. */
3119 if (is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
)
3121 /* Its safe to use -coeff even for INT_MIN, as the
3122 result is interpreted as an unsigned coefficient.
3123 Exclude cost of op0 from max_cost to match the cost
3124 calculation of the synth_mult. */
3125 coeff
= -(unsigned HOST_WIDE_INT
) coeff
;
3126 max_cost
= (set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), speed
)
3127 - neg_cost(speed
, mode
));
3131 /* Special case powers of two. */
3132 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3134 rtx temp
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
3135 floor_log2 (coeff
), target
, unsignedp
);
3136 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3139 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3142 rtx temp
= expand_mult_const (mode
, op0
, coeff
, NULL_RTX
,
3143 &algorithm
, variant
);
3144 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3149 /* Exclude cost of op0 from max_cost to match the cost
3150 calculation of the synth_mult. */
3151 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), speed
);
3152 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3153 return expand_mult_const (mode
, op0
, coeff
, target
,
3154 &algorithm
, variant
);
3158 /* Expand x*2.0 as x+x. */
3159 if (CONST_DOUBLE_AS_FLOAT_P (scalar_op1
))
3162 REAL_VALUE_FROM_CONST_DOUBLE (d
, scalar_op1
);
3164 if (REAL_VALUES_EQUAL (d
, dconst2
))
3166 op0
= force_reg (GET_MODE (op0
), op0
);
3167 return expand_binop (mode
, add_optab
, op0
, op0
,
3168 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3173 /* This used to use umul_optab if unsigned, but for non-widening multiply
3174 there is no difference between signed and unsigned. */
3175 op0
= expand_binop (mode
, do_trapv
? smulv_optab
: smul_optab
,
3176 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
3181 /* Return a cost estimate for multiplying a register by the given
3182 COEFFicient in the given MODE and SPEED. */
3185 mult_by_coeff_cost (HOST_WIDE_INT coeff
, enum machine_mode mode
, bool speed
)
3188 struct algorithm algorithm
;
3189 enum mult_variant variant
;
3191 rtx fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3192 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, fake_reg
), speed
);
3193 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3194 return algorithm
.cost
.cost
;
3199 /* Perform a widening multiplication and return an rtx for the result.
3200 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3201 TARGET is a suggestion for where to store the result (an rtx).
3202 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3203 or smul_widen_optab.
3205 We check specially for a constant integer as OP1, comparing the
3206 cost of a widening multiply against the cost of a sequence of shifts
3210 expand_widening_mult (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3211 int unsignedp
, optab this_optab
)
3213 bool speed
= optimize_insn_for_speed_p ();
3216 if (CONST_INT_P (op1
)
3217 && GET_MODE (op0
) != VOIDmode
3218 && (cop1
= convert_modes (mode
, GET_MODE (op0
), op1
,
3219 this_optab
== umul_widen_optab
))
3220 && CONST_INT_P (cop1
)
3221 && (INTVAL (cop1
) >= 0
3222 || HWI_COMPUTABLE_MODE_P (mode
)))
3224 HOST_WIDE_INT coeff
= INTVAL (cop1
);
3226 enum mult_variant variant
;
3227 struct algorithm algorithm
;
3229 /* Special case powers of two. */
3230 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3232 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3233 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3234 floor_log2 (coeff
), target
, unsignedp
);
3237 /* Exclude cost of op0 from max_cost to match the cost
3238 calculation of the synth_mult. */
3239 max_cost
= mul_widen_cost (speed
, mode
);
3240 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3243 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3244 return expand_mult_const (mode
, op0
, coeff
, target
,
3245 &algorithm
, variant
);
3248 return expand_binop (mode
, this_optab
, op0
, op1
, target
,
3249 unsignedp
, OPTAB_LIB_WIDEN
);
3252 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3253 replace division by D, and put the least significant N bits of the result
3254 in *MULTIPLIER_PTR and return the most significant bit.
3256 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3257 needed precision is in PRECISION (should be <= N).
3259 PRECISION should be as small as possible so this function can choose
3260 multiplier more freely.
3262 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3263 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3265 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3266 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3268 unsigned HOST_WIDE_INT
3269 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
3270 unsigned HOST_WIDE_INT
*multiplier_ptr
,
3271 int *post_shift_ptr
, int *lgup_ptr
)
3273 double_int mhigh
, mlow
;
3274 int lgup
, post_shift
;
3277 /* lgup = ceil(log2(divisor)); */
3278 lgup
= ceil_log2 (d
);
3280 gcc_assert (lgup
<= n
);
3283 pow2
= n
+ lgup
- precision
;
3285 /* We could handle this with some effort, but this case is much
3286 better handled directly with a scc insn, so rely on caller using
3288 gcc_assert (pow
!= HOST_BITS_PER_DOUBLE_INT
);
3290 /* mlow = 2^(N + lgup)/d */
3291 double_int val
= double_int_zero
.set_bit (pow
);
3292 mlow
= val
.div (double_int::from_uhwi (d
), true, TRUNC_DIV_EXPR
);
3294 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3295 val
|= double_int_zero
.set_bit (pow2
);
3296 mhigh
= val
.div (double_int::from_uhwi (d
), true, TRUNC_DIV_EXPR
);
3298 gcc_assert (!mhigh
.high
|| val
.high
- d
< d
);
3299 gcc_assert (mhigh
.high
<= 1 && mlow
.high
<= 1);
3300 /* Assert that mlow < mhigh. */
3301 gcc_assert (mlow
.ult (mhigh
));
3303 /* If precision == N, then mlow, mhigh exceed 2^N
3304 (but they do not exceed 2^(N+1)). */
3306 /* Reduce to lowest terms. */
3307 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
3309 int shft
= HOST_BITS_PER_WIDE_INT
- 1;
3310 unsigned HOST_WIDE_INT ml_lo
= (mlow
.high
<< shft
) | (mlow
.low
>> 1);
3311 unsigned HOST_WIDE_INT mh_lo
= (mhigh
.high
<< shft
) | (mhigh
.low
>> 1);
3315 mlow
= double_int::from_uhwi (ml_lo
);
3316 mhigh
= double_int::from_uhwi (mh_lo
);
3319 *post_shift_ptr
= post_shift
;
3321 if (n
< HOST_BITS_PER_WIDE_INT
)
3323 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
3324 *multiplier_ptr
= mhigh
.low
& mask
;
3325 return mhigh
.low
>= mask
;
3329 *multiplier_ptr
= mhigh
.low
;
3334 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3335 congruent to 1 (mod 2**N). */
3337 static unsigned HOST_WIDE_INT
3338 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
3340 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3342 /* The algorithm notes that the choice y = x satisfies
3343 x*y == 1 mod 2^3, since x is assumed odd.
3344 Each iteration doubles the number of bits of significance in y. */
3346 unsigned HOST_WIDE_INT mask
;
3347 unsigned HOST_WIDE_INT y
= x
;
3350 mask
= (n
== HOST_BITS_PER_WIDE_INT
3351 ? ~(unsigned HOST_WIDE_INT
) 0
3352 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
3356 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
3362 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3363 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3364 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3365 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3368 The result is put in TARGET if that is convenient.
3370 MODE is the mode of operation. */
3373 expand_mult_highpart_adjust (enum machine_mode mode
, rtx adj_operand
, rtx op0
,
3374 rtx op1
, rtx target
, int unsignedp
)
3377 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
3379 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3380 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3381 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
3383 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3386 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
3387 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3388 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
3389 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3395 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3398 extract_high_half (enum machine_mode mode
, rtx op
)
3400 enum machine_mode wider_mode
;
3402 if (mode
== word_mode
)
3403 return gen_highpart (mode
, op
);
3405 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3407 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3408 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
3409 GET_MODE_BITSIZE (mode
), 0, 1);
3410 return convert_modes (mode
, wider_mode
, op
, 0);
3413 /* Like expmed_mult_highpart, but only consider using a multiplication
3414 optab. OP1 is an rtx for the constant operand. */
3417 expmed_mult_highpart_optab (enum machine_mode mode
, rtx op0
, rtx op1
,
3418 rtx target
, int unsignedp
, int max_cost
)
3420 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
3421 enum machine_mode wider_mode
;
3425 bool speed
= optimize_insn_for_speed_p ();
3427 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3429 wider_mode
= GET_MODE_WIDER_MODE (mode
);
3430 size
= GET_MODE_BITSIZE (mode
);
3432 /* Firstly, try using a multiplication insn that only generates the needed
3433 high part of the product, and in the sign flavor of unsignedp. */
3434 if (mul_highpart_cost (speed
, mode
) < max_cost
)
3436 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
3437 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3438 unsignedp
, OPTAB_DIRECT
);
3443 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3444 Need to adjust the result after the multiplication. */
3445 if (size
- 1 < BITS_PER_WORD
3446 && (mul_highpart_cost (speed
, mode
)
3447 + 2 * shift_cost (speed
, mode
, size
-1)
3448 + 4 * add_cost (speed
, mode
) < max_cost
))
3450 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
3451 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3452 unsignedp
, OPTAB_DIRECT
);
3454 /* We used the wrong signedness. Adjust the result. */
3455 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3459 /* Try widening multiplication. */
3460 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
3461 if (widening_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3462 && mul_widen_cost (speed
, wider_mode
) < max_cost
)
3464 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
3465 unsignedp
, OPTAB_WIDEN
);
3467 return extract_high_half (mode
, tem
);
3470 /* Try widening the mode and perform a non-widening multiplication. */
3471 if (optab_handler (smul_optab
, wider_mode
) != CODE_FOR_nothing
3472 && size
- 1 < BITS_PER_WORD
3473 && (mul_cost (speed
, wider_mode
) + shift_cost (speed
, mode
, size
-1)
3476 rtx insns
, wop0
, wop1
;
3478 /* We need to widen the operands, for example to ensure the
3479 constant multiplier is correctly sign or zero extended.
3480 Use a sequence to clean-up any instructions emitted by
3481 the conversions if things don't work out. */
3483 wop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
3484 wop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
3485 tem
= expand_binop (wider_mode
, smul_optab
, wop0
, wop1
, 0,
3486 unsignedp
, OPTAB_WIDEN
);
3487 insns
= get_insns ();
3493 return extract_high_half (mode
, tem
);
3497 /* Try widening multiplication of opposite signedness, and adjust. */
3498 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3499 if (widening_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3500 && size
- 1 < BITS_PER_WORD
3501 && (mul_widen_cost (speed
, wider_mode
)
3502 + 2 * shift_cost (speed
, mode
, size
-1)
3503 + 4 * add_cost (speed
, mode
) < max_cost
))
3505 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3506 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3509 tem
= extract_high_half (mode
, tem
);
3510 /* We used the wrong signedness. Adjust the result. */
3511 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3519 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3520 putting the high half of the result in TARGET if that is convenient,
3521 and return where the result is. If the operation can not be performed,
3524 MODE is the mode of operation and result.
3526 UNSIGNEDP nonzero means unsigned multiply.
3528 MAX_COST is the total allowed cost for the expanded RTL. */
3531 expmed_mult_highpart (enum machine_mode mode
, rtx op0
, rtx op1
,
3532 rtx target
, int unsignedp
, int max_cost
)
3534 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
3535 unsigned HOST_WIDE_INT cnst1
;
3537 bool sign_adjust
= false;
3538 enum mult_variant variant
;
3539 struct algorithm alg
;
3541 bool speed
= optimize_insn_for_speed_p ();
3543 gcc_assert (!SCALAR_FLOAT_MODE_P (mode
));
3544 /* We can't support modes wider than HOST_BITS_PER_INT. */
3545 gcc_assert (HWI_COMPUTABLE_MODE_P (mode
));
3547 cnst1
= INTVAL (op1
) & GET_MODE_MASK (mode
);
3549 /* We can't optimize modes wider than BITS_PER_WORD.
3550 ??? We might be able to perform double-word arithmetic if
3551 mode == word_mode, however all the cost calculations in
3552 synth_mult etc. assume single-word operations. */
3553 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3554 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3555 unsignedp
, max_cost
);
3557 extra_cost
= shift_cost (speed
, mode
, GET_MODE_BITSIZE (mode
) - 1);
3559 /* Check whether we try to multiply by a negative constant. */
3560 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3563 extra_cost
+= add_cost (speed
, mode
);
3566 /* See whether shift/add multiplication is cheap enough. */
3567 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3568 max_cost
- extra_cost
))
3570 /* See whether the specialized multiplication optabs are
3571 cheaper than the shift/add version. */
3572 tem
= expmed_mult_highpart_optab (mode
, op0
, op1
, target
, unsignedp
,
3573 alg
.cost
.cost
+ extra_cost
);
3577 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3578 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3579 tem
= extract_high_half (mode
, tem
);
3581 /* Adjust result for signedness. */
3583 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3587 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3588 unsignedp
, max_cost
);
3592 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3595 expand_smod_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3597 unsigned HOST_WIDE_INT masklow
, maskhigh
;
3598 rtx result
, temp
, shift
, label
;
3601 logd
= floor_log2 (d
);
3602 result
= gen_reg_rtx (mode
);
3604 /* Avoid conditional branches when they're expensive. */
3605 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3606 && optimize_insn_for_speed_p ())
3608 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3612 signmask
= force_reg (mode
, signmask
);
3613 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3614 shift
= GEN_INT (GET_MODE_BITSIZE (mode
) - logd
);
3616 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3617 which instruction sequence to use. If logical right shifts
3618 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3619 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3621 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3622 if (optab_handler (lshr_optab
, mode
) == CODE_FOR_nothing
3623 || (set_src_cost (temp
, optimize_insn_for_speed_p ())
3624 > COSTS_N_INSNS (2)))
3626 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3627 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3628 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3629 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3630 temp
= expand_binop (mode
, and_optab
, temp
,
3631 gen_int_mode (masklow
, mode
),
3632 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3633 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3634 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3635 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3636 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3640 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3641 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3642 signmask
= force_reg (mode
, signmask
);
3644 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3645 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3646 temp
= expand_binop (mode
, and_optab
, temp
,
3647 gen_int_mode (masklow
, mode
),
3648 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3649 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3650 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3656 /* Mask contains the mode's signbit and the significant bits of the
3657 modulus. By including the signbit in the operation, many targets
3658 can avoid an explicit compare operation in the following comparison
3661 masklow
= ((HOST_WIDE_INT
) 1 << logd
) - 1;
3662 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3664 masklow
|= HOST_WIDE_INT_M1U
<< (GET_MODE_BITSIZE (mode
) - 1);
3668 maskhigh
= HOST_WIDE_INT_M1U
3669 << (GET_MODE_BITSIZE (mode
) - HOST_BITS_PER_WIDE_INT
- 1);
3671 temp
= expand_binop (mode
, and_optab
, op0
,
3672 immed_double_const (masklow
, maskhigh
, mode
),
3673 result
, 1, OPTAB_LIB_WIDEN
);
3675 emit_move_insn (result
, temp
);
3677 label
= gen_label_rtx ();
3678 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
3680 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
3681 0, OPTAB_LIB_WIDEN
);
3682 masklow
= HOST_WIDE_INT_M1U
<< logd
;
3684 temp
= expand_binop (mode
, ior_optab
, temp
,
3685 immed_double_const (masklow
, maskhigh
, mode
),
3686 result
, 1, OPTAB_LIB_WIDEN
);
3687 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
3688 0, OPTAB_LIB_WIDEN
);
3690 emit_move_insn (result
, temp
);
3695 /* Expand signed division of OP0 by a power of two D in mode MODE.
3696 This routine is only called for positive values of D. */
3699 expand_sdiv_pow2 (enum machine_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3704 logd
= floor_log2 (d
);
3707 && BRANCH_COST (optimize_insn_for_speed_p (),
3710 temp
= gen_reg_rtx (mode
);
3711 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
3712 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3713 0, OPTAB_LIB_WIDEN
);
3714 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3717 #ifdef HAVE_conditional_move
3718 if (BRANCH_COST (optimize_insn_for_speed_p (), false)
3723 /* ??? emit_conditional_move forces a stack adjustment via
3724 compare_from_rtx so, if the sequence is discarded, it will
3725 be lost. Do it now instead. */
3726 do_pending_stack_adjust ();
3729 temp2
= copy_to_mode_reg (mode
, op0
);
3730 temp
= expand_binop (mode
, add_optab
, temp2
, gen_int_mode (d
- 1, mode
),
3731 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3732 temp
= force_reg (mode
, temp
);
3734 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
3735 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
3736 mode
, temp
, temp2
, mode
, 0);
3739 rtx seq
= get_insns ();
3742 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, logd
, NULL_RTX
, 0);
3748 if (BRANCH_COST (optimize_insn_for_speed_p (),
3751 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
3753 temp
= gen_reg_rtx (mode
);
3754 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
3755 if (shift_cost (optimize_insn_for_speed_p (), mode
, ushift
)
3756 > COSTS_N_INSNS (1))
3757 temp
= expand_binop (mode
, and_optab
, temp
, gen_int_mode (d
- 1, mode
),
3758 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
3760 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
3761 ushift
, NULL_RTX
, 1);
3762 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
3763 0, OPTAB_LIB_WIDEN
);
3764 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3767 label
= gen_label_rtx ();
3768 temp
= copy_to_mode_reg (mode
, op0
);
3769 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
3770 expand_inc (temp
, gen_int_mode (d
- 1, mode
));
3772 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
3775 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
3776 if that is convenient, and returning where the result is.
3777 You may request either the quotient or the remainder as the result;
3778 specify REM_FLAG nonzero to get the remainder.
3780 CODE is the expression code for which kind of division this is;
3781 it controls how rounding is done. MODE is the machine mode to use.
3782 UNSIGNEDP nonzero means do unsigned division. */
3784 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
3785 and then correct it by or'ing in missing high bits
3786 if result of ANDI is nonzero.
3787 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
3788 This could optimize to a bfexts instruction.
3789 But C doesn't use these operations, so their optimizations are
3791 /* ??? For modulo, we don't actually need the highpart of the first product,
3792 the low part will do nicely. And for small divisors, the second multiply
3793 can also be a low-part only multiply or even be completely left out.
3794 E.g. to calculate the remainder of a division by 3 with a 32 bit
3795 multiply, multiply with 0x55555556 and extract the upper two bits;
3796 the result is exact for inputs up to 0x1fffffff.
3797 The input range can be reduced by using cross-sum rules.
3798 For odd divisors >= 3, the following table gives right shift counts
3799 so that if a number is shifted by an integer multiple of the given
3800 amount, the remainder stays the same:
3801 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
3802 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
3803 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
3804 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
3805 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
3807 Cross-sum rules for even numbers can be derived by leaving as many bits
3808 to the right alone as the divisor has zeros to the right.
3809 E.g. if x is an unsigned 32 bit number:
3810 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
3814 expand_divmod (int rem_flag
, enum tree_code code
, enum machine_mode mode
,
3815 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
3817 enum machine_mode compute_mode
;
3819 rtx quotient
= 0, remainder
= 0;
3823 optab optab1
, optab2
;
3824 int op1_is_constant
, op1_is_pow2
= 0;
3825 int max_cost
, extra_cost
;
3826 static HOST_WIDE_INT last_div_const
= 0;
3827 bool speed
= optimize_insn_for_speed_p ();
3829 op1_is_constant
= CONST_INT_P (op1
);
3830 if (op1_is_constant
)
3832 unsigned HOST_WIDE_INT ext_op1
= UINTVAL (op1
);
3834 ext_op1
&= GET_MODE_MASK (mode
);
3835 op1_is_pow2
= ((EXACT_POWER_OF_2_OR_ZERO_P (ext_op1
)
3836 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-ext_op1
))));
3840 This is the structure of expand_divmod:
3842 First comes code to fix up the operands so we can perform the operations
3843 correctly and efficiently.
3845 Second comes a switch statement with code specific for each rounding mode.
3846 For some special operands this code emits all RTL for the desired
3847 operation, for other cases, it generates only a quotient and stores it in
3848 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
3849 to indicate that it has not done anything.
3851 Last comes code that finishes the operation. If QUOTIENT is set and
3852 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
3853 QUOTIENT is not set, it is computed using trunc rounding.
3855 We try to generate special code for division and remainder when OP1 is a
3856 constant. If |OP1| = 2**n we can use shifts and some other fast
3857 operations. For other values of OP1, we compute a carefully selected
3858 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
3861 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
3862 half of the product. Different strategies for generating the product are
3863 implemented in expmed_mult_highpart.
3865 If what we actually want is the remainder, we generate that by another
3866 by-constant multiplication and a subtraction. */
3868 /* We shouldn't be called with OP1 == const1_rtx, but some of the
3869 code below will malfunction if we are, so check here and handle
3870 the special case if so. */
3871 if (op1
== const1_rtx
)
3872 return rem_flag
? const0_rtx
: op0
;
3874 /* When dividing by -1, we could get an overflow.
3875 negv_optab can handle overflows. */
3876 if (! unsignedp
&& op1
== constm1_rtx
)
3880 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
3881 ? negv_optab
: neg_optab
, op0
, target
, 0);
3885 /* Don't use the function value register as a target
3886 since we have to read it as well as write it,
3887 and function-inlining gets confused by this. */
3888 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
3889 /* Don't clobber an operand while doing a multi-step calculation. */
3890 || ((rem_flag
|| op1_is_constant
)
3891 && (reg_mentioned_p (target
, op0
)
3892 || (MEM_P (op0
) && MEM_P (target
))))
3893 || reg_mentioned_p (target
, op1
)
3894 || (MEM_P (op1
) && MEM_P (target
))))
3897 /* Get the mode in which to perform this computation. Normally it will
3898 be MODE, but sometimes we can't do the desired operation in MODE.
3899 If so, pick a wider mode in which we can do the operation. Convert
3900 to that mode at the start to avoid repeated conversions.
3902 First see what operations we need. These depend on the expression
3903 we are evaluating. (We assume that divxx3 insns exist under the
3904 same conditions that modxx3 insns and that these insns don't normally
3905 fail. If these assumptions are not correct, we may generate less
3906 efficient code in some cases.)
3908 Then see if we find a mode in which we can open-code that operation
3909 (either a division, modulus, or shift). Finally, check for the smallest
3910 mode for which we can do the operation with a library call. */
3912 /* We might want to refine this now that we have division-by-constant
3913 optimization. Since expmed_mult_highpart tries so many variants, it is
3914 not straightforward to generalize this. Maybe we should make an array
3915 of possible modes in init_expmed? Save this for GCC 2.7. */
3917 optab1
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3918 ? (unsignedp
? lshr_optab
: ashr_optab
)
3919 : (unsignedp
? udiv_optab
: sdiv_optab
));
3920 optab2
= ((op1_is_pow2
&& op1
!= const0_rtx
)
3922 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
3924 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3925 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3926 if (optab_handler (optab1
, compute_mode
) != CODE_FOR_nothing
3927 || optab_handler (optab2
, compute_mode
) != CODE_FOR_nothing
)
3930 if (compute_mode
== VOIDmode
)
3931 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3932 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3933 if (optab_libfunc (optab1
, compute_mode
)
3934 || optab_libfunc (optab2
, compute_mode
))
3937 /* If we still couldn't find a mode, use MODE, but expand_binop will
3939 if (compute_mode
== VOIDmode
)
3940 compute_mode
= mode
;
3942 if (target
&& GET_MODE (target
) == compute_mode
)
3945 tquotient
= gen_reg_rtx (compute_mode
);
3947 size
= GET_MODE_BITSIZE (compute_mode
);
3949 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3950 (mode), and thereby get better code when OP1 is a constant. Do that
3951 later. It will require going over all usages of SIZE below. */
3952 size
= GET_MODE_BITSIZE (mode
);
3955 /* Only deduct something for a REM if the last divide done was
3956 for a different constant. Then set the constant of the last
3958 max_cost
= (unsignedp
3959 ? udiv_cost (speed
, compute_mode
)
3960 : sdiv_cost (speed
, compute_mode
));
3961 if (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3962 && INTVAL (op1
) == last_div_const
))
3963 max_cost
-= (mul_cost (speed
, compute_mode
)
3964 + add_cost (speed
, compute_mode
));
3966 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3968 /* Now convert to the best mode to use. */
3969 if (compute_mode
!= mode
)
3971 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3972 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3974 /* convert_modes may have placed op1 into a register, so we
3975 must recompute the following. */
3976 op1_is_constant
= CONST_INT_P (op1
);
3977 op1_is_pow2
= (op1_is_constant
3978 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3980 && EXACT_POWER_OF_2_OR_ZERO_P (-UINTVAL (op1
))))));
3983 /* If one of the operands is a volatile MEM, copy it into a register. */
3985 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
3986 op0
= force_reg (compute_mode
, op0
);
3987 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
3988 op1
= force_reg (compute_mode
, op1
);
3990 /* If we need the remainder or if OP1 is constant, we need to
3991 put OP0 in a register in case it has any queued subexpressions. */
3992 if (rem_flag
|| op1_is_constant
)
3993 op0
= force_reg (compute_mode
, op0
);
3995 last
= get_last_insn ();
3997 /* Promote floor rounding to trunc rounding for unsigned operations. */
4000 if (code
== FLOOR_DIV_EXPR
)
4001 code
= TRUNC_DIV_EXPR
;
4002 if (code
== FLOOR_MOD_EXPR
)
4003 code
= TRUNC_MOD_EXPR
;
4004 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
4005 code
= TRUNC_DIV_EXPR
;
4008 if (op1
!= const0_rtx
)
4011 case TRUNC_MOD_EXPR
:
4012 case TRUNC_DIV_EXPR
:
4013 if (op1_is_constant
)
4017 unsigned HOST_WIDE_INT mh
, ml
;
4018 int pre_shift
, post_shift
;
4020 unsigned HOST_WIDE_INT d
= (INTVAL (op1
)
4021 & GET_MODE_MASK (compute_mode
));
4023 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4025 pre_shift
= floor_log2 (d
);
4028 unsigned HOST_WIDE_INT mask
4029 = ((unsigned HOST_WIDE_INT
) 1 << pre_shift
) - 1;
4031 = expand_binop (compute_mode
, and_optab
, op0
,
4032 gen_int_mode (mask
, compute_mode
),
4036 return gen_lowpart (mode
, remainder
);
4038 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4039 pre_shift
, tquotient
, 1);
4041 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4043 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
4045 /* Most significant bit of divisor is set; emit an scc
4047 quotient
= emit_store_flag_force (tquotient
, GEU
, op0
, op1
,
4048 compute_mode
, 1, 1);
4052 /* Find a suitable multiplier and right shift count
4053 instead of multiplying with D. */
4055 mh
= choose_multiplier (d
, size
, size
,
4056 &ml
, &post_shift
, &dummy
);
4058 /* If the suggested multiplier is more than SIZE bits,
4059 we can do better for even divisors, using an
4060 initial right shift. */
4061 if (mh
!= 0 && (d
& 1) == 0)
4063 pre_shift
= floor_log2 (d
& -d
);
4064 mh
= choose_multiplier (d
>> pre_shift
, size
,
4066 &ml
, &post_shift
, &dummy
);
4076 if (post_shift
- 1 >= BITS_PER_WORD
)
4080 = (shift_cost (speed
, compute_mode
, post_shift
- 1)
4081 + shift_cost (speed
, compute_mode
, 1)
4082 + 2 * add_cost (speed
, compute_mode
));
4083 t1
= expmed_mult_highpart
4085 gen_int_mode (ml
, compute_mode
),
4086 NULL_RTX
, 1, max_cost
- extra_cost
);
4089 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
4092 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
,
4093 t2
, 1, NULL_RTX
, 1);
4094 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
4097 quotient
= expand_shift
4098 (RSHIFT_EXPR
, compute_mode
, t4
,
4099 post_shift
- 1, tquotient
, 1);
4105 if (pre_shift
>= BITS_PER_WORD
4106 || post_shift
>= BITS_PER_WORD
)
4110 (RSHIFT_EXPR
, compute_mode
, op0
,
4111 pre_shift
, NULL_RTX
, 1);
4113 = (shift_cost (speed
, compute_mode
, pre_shift
)
4114 + shift_cost (speed
, compute_mode
, post_shift
));
4115 t2
= expmed_mult_highpart
4117 gen_int_mode (ml
, compute_mode
),
4118 NULL_RTX
, 1, max_cost
- extra_cost
);
4121 quotient
= expand_shift
4122 (RSHIFT_EXPR
, compute_mode
, t2
,
4123 post_shift
, tquotient
, 1);
4127 else /* Too wide mode to use tricky code */
4130 insn
= get_last_insn ();
4132 set_dst_reg_note (insn
, REG_EQUAL
,
4133 gen_rtx_UDIV (compute_mode
, op0
, op1
),
4136 else /* TRUNC_DIV, signed */
4138 unsigned HOST_WIDE_INT ml
;
4139 int lgup
, post_shift
;
4141 HOST_WIDE_INT d
= INTVAL (op1
);
4142 unsigned HOST_WIDE_INT abs_d
;
4144 /* Since d might be INT_MIN, we have to cast to
4145 unsigned HOST_WIDE_INT before negating to avoid
4146 undefined signed overflow. */
4148 ? (unsigned HOST_WIDE_INT
) d
4149 : - (unsigned HOST_WIDE_INT
) d
);
4151 /* n rem d = n rem -d */
4152 if (rem_flag
&& d
< 0)
4155 op1
= gen_int_mode (abs_d
, compute_mode
);
4161 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
4163 else if (HOST_BITS_PER_WIDE_INT
>= size
4164 && abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4166 /* This case is not handled correctly below. */
4167 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
4168 compute_mode
, 1, 1);
4172 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
4174 ? smod_pow2_cheap (speed
, compute_mode
)
4175 : sdiv_pow2_cheap (speed
, compute_mode
))
4176 /* We assume that cheap metric is true if the
4177 optab has an expander for this mode. */
4178 && ((optab_handler ((rem_flag
? smod_optab
4181 != CODE_FOR_nothing
)
4182 || (optab_handler (sdivmod_optab
,
4184 != CODE_FOR_nothing
)))
4186 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
4190 remainder
= expand_smod_pow2 (compute_mode
, op0
, d
);
4192 return gen_lowpart (mode
, remainder
);
4195 if (sdiv_pow2_cheap (speed
, compute_mode
)
4196 && ((optab_handler (sdiv_optab
, compute_mode
)
4197 != CODE_FOR_nothing
)
4198 || (optab_handler (sdivmod_optab
, compute_mode
)
4199 != CODE_FOR_nothing
)))
4200 quotient
= expand_divmod (0, TRUNC_DIV_EXPR
,
4202 gen_int_mode (abs_d
,
4206 quotient
= expand_sdiv_pow2 (compute_mode
, op0
, abs_d
);
4208 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4209 negate the quotient. */
4212 insn
= get_last_insn ();
4214 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
4215 << (HOST_BITS_PER_WIDE_INT
- 1)))
4216 set_dst_reg_note (insn
, REG_EQUAL
,
4217 gen_rtx_DIV (compute_mode
, op0
,
4223 quotient
= expand_unop (compute_mode
, neg_optab
,
4224 quotient
, quotient
, 0);
4227 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4229 choose_multiplier (abs_d
, size
, size
- 1,
4230 &ml
, &post_shift
, &lgup
);
4231 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
4235 if (post_shift
>= BITS_PER_WORD
4236 || size
- 1 >= BITS_PER_WORD
)
4239 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4240 + shift_cost (speed
, compute_mode
, size
- 1)
4241 + add_cost (speed
, compute_mode
));
4242 t1
= expmed_mult_highpart
4243 (compute_mode
, op0
, gen_int_mode (ml
, compute_mode
),
4244 NULL_RTX
, 0, max_cost
- extra_cost
);
4248 (RSHIFT_EXPR
, compute_mode
, t1
,
4249 post_shift
, NULL_RTX
, 0);
4251 (RSHIFT_EXPR
, compute_mode
, op0
,
4252 size
- 1, NULL_RTX
, 0);
4255 = force_operand (gen_rtx_MINUS (compute_mode
,
4260 = force_operand (gen_rtx_MINUS (compute_mode
,
4268 if (post_shift
>= BITS_PER_WORD
4269 || size
- 1 >= BITS_PER_WORD
)
4272 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
4273 mlr
= gen_int_mode (ml
, compute_mode
);
4274 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4275 + shift_cost (speed
, compute_mode
, size
- 1)
4276 + 2 * add_cost (speed
, compute_mode
));
4277 t1
= expmed_mult_highpart (compute_mode
, op0
, mlr
,
4279 max_cost
- extra_cost
);
4282 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
4286 (RSHIFT_EXPR
, compute_mode
, t2
,
4287 post_shift
, NULL_RTX
, 0);
4289 (RSHIFT_EXPR
, compute_mode
, op0
,
4290 size
- 1, NULL_RTX
, 0);
4293 = force_operand (gen_rtx_MINUS (compute_mode
,
4298 = force_operand (gen_rtx_MINUS (compute_mode
,
4303 else /* Too wide mode to use tricky code */
4306 insn
= get_last_insn ();
4308 set_dst_reg_note (insn
, REG_EQUAL
,
4309 gen_rtx_DIV (compute_mode
, op0
, op1
),
4315 delete_insns_since (last
);
4318 case FLOOR_DIV_EXPR
:
4319 case FLOOR_MOD_EXPR
:
4320 /* We will come here only for signed operations. */
4321 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4323 unsigned HOST_WIDE_INT mh
, ml
;
4324 int pre_shift
, lgup
, post_shift
;
4325 HOST_WIDE_INT d
= INTVAL (op1
);
4329 /* We could just as easily deal with negative constants here,
4330 but it does not seem worth the trouble for GCC 2.6. */
4331 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4333 pre_shift
= floor_log2 (d
);
4336 unsigned HOST_WIDE_INT mask
4337 = ((unsigned HOST_WIDE_INT
) 1 << pre_shift
) - 1;
4338 remainder
= expand_binop
4339 (compute_mode
, and_optab
, op0
,
4340 gen_int_mode (mask
, compute_mode
),
4341 remainder
, 0, OPTAB_LIB_WIDEN
);
4343 return gen_lowpart (mode
, remainder
);
4345 quotient
= expand_shift
4346 (RSHIFT_EXPR
, compute_mode
, op0
,
4347 pre_shift
, tquotient
, 0);
4353 mh
= choose_multiplier (d
, size
, size
- 1,
4354 &ml
, &post_shift
, &lgup
);
4357 if (post_shift
< BITS_PER_WORD
4358 && size
- 1 < BITS_PER_WORD
)
4361 (RSHIFT_EXPR
, compute_mode
, op0
,
4362 size
- 1, NULL_RTX
, 0);
4363 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
4364 NULL_RTX
, 0, OPTAB_WIDEN
);
4365 extra_cost
= (shift_cost (speed
, compute_mode
, post_shift
)
4366 + shift_cost (speed
, compute_mode
, size
- 1)
4367 + 2 * add_cost (speed
, compute_mode
));
4368 t3
= expmed_mult_highpart
4369 (compute_mode
, t2
, gen_int_mode (ml
, compute_mode
),
4370 NULL_RTX
, 1, max_cost
- extra_cost
);
4374 (RSHIFT_EXPR
, compute_mode
, t3
,
4375 post_shift
, NULL_RTX
, 1);
4376 quotient
= expand_binop (compute_mode
, xor_optab
,
4377 t4
, t1
, tquotient
, 0,
4385 rtx nsign
, t1
, t2
, t3
, t4
;
4386 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
4387 op0
, constm1_rtx
), NULL_RTX
);
4388 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
4390 nsign
= expand_shift
4391 (RSHIFT_EXPR
, compute_mode
, t2
,
4392 size
- 1, NULL_RTX
, 0);
4393 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
4395 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
4400 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
4402 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4411 delete_insns_since (last
);
4413 /* Try using an instruction that produces both the quotient and
4414 remainder, using truncation. We can easily compensate the quotient
4415 or remainder to get floor rounding, once we have the remainder.
4416 Notice that we compute also the final remainder value here,
4417 and return the result right away. */
4418 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4419 target
= gen_reg_rtx (compute_mode
);
4424 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4425 quotient
= gen_reg_rtx (compute_mode
);
4430 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4431 remainder
= gen_reg_rtx (compute_mode
);
4434 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
4435 quotient
, remainder
, 0))
4437 /* This could be computed with a branch-less sequence.
4438 Save that for later. */
4440 rtx label
= gen_label_rtx ();
4441 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
4442 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4443 NULL_RTX
, 0, OPTAB_WIDEN
);
4444 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
4445 expand_dec (quotient
, const1_rtx
);
4446 expand_inc (remainder
, op1
);
4448 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4451 /* No luck with division elimination or divmod. Have to do it
4452 by conditionally adjusting op0 *and* the result. */
4454 rtx label1
, label2
, label3
, label4
, label5
;
4458 quotient
= gen_reg_rtx (compute_mode
);
4459 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4460 label1
= gen_label_rtx ();
4461 label2
= gen_label_rtx ();
4462 label3
= gen_label_rtx ();
4463 label4
= gen_label_rtx ();
4464 label5
= gen_label_rtx ();
4465 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4466 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
4467 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4468 quotient
, 0, OPTAB_LIB_WIDEN
);
4469 if (tem
!= quotient
)
4470 emit_move_insn (quotient
, tem
);
4471 emit_jump_insn (gen_jump (label5
));
4473 emit_label (label1
);
4474 expand_inc (adjusted_op0
, const1_rtx
);
4475 emit_jump_insn (gen_jump (label4
));
4477 emit_label (label2
);
4478 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
4479 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4480 quotient
, 0, OPTAB_LIB_WIDEN
);
4481 if (tem
!= quotient
)
4482 emit_move_insn (quotient
, tem
);
4483 emit_jump_insn (gen_jump (label5
));
4485 emit_label (label3
);
4486 expand_dec (adjusted_op0
, const1_rtx
);
4487 emit_label (label4
);
4488 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4489 quotient
, 0, OPTAB_LIB_WIDEN
);
4490 if (tem
!= quotient
)
4491 emit_move_insn (quotient
, tem
);
4492 expand_dec (quotient
, const1_rtx
);
4493 emit_label (label5
);
4501 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
4504 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4505 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4506 floor_log2 (d
), tquotient
, 1);
4507 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4508 gen_int_mode (d
- 1, compute_mode
),
4509 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4510 t3
= gen_reg_rtx (compute_mode
);
4511 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4512 compute_mode
, 1, 1);
4516 lab
= gen_label_rtx ();
4517 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4518 expand_inc (t1
, const1_rtx
);
4523 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4529 /* Try using an instruction that produces both the quotient and
4530 remainder, using truncation. We can easily compensate the
4531 quotient or remainder to get ceiling rounding, once we have the
4532 remainder. Notice that we compute also the final remainder
4533 value here, and return the result right away. */
4534 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4535 target
= gen_reg_rtx (compute_mode
);
4539 remainder
= (REG_P (target
)
4540 ? target
: gen_reg_rtx (compute_mode
));
4541 quotient
= gen_reg_rtx (compute_mode
);
4545 quotient
= (REG_P (target
)
4546 ? target
: gen_reg_rtx (compute_mode
));
4547 remainder
= gen_reg_rtx (compute_mode
);
4550 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4553 /* This could be computed with a branch-less sequence.
4554 Save that for later. */
4555 rtx label
= gen_label_rtx ();
4556 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4557 compute_mode
, label
);
4558 expand_inc (quotient
, const1_rtx
);
4559 expand_dec (remainder
, op1
);
4561 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4564 /* No luck with division elimination or divmod. Have to do it
4565 by conditionally adjusting op0 *and* the result. */
4568 rtx adjusted_op0
, tem
;
4570 quotient
= gen_reg_rtx (compute_mode
);
4571 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4572 label1
= gen_label_rtx ();
4573 label2
= gen_label_rtx ();
4574 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4575 compute_mode
, label1
);
4576 emit_move_insn (quotient
, const0_rtx
);
4577 emit_jump_insn (gen_jump (label2
));
4579 emit_label (label1
);
4580 expand_dec (adjusted_op0
, const1_rtx
);
4581 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4582 quotient
, 1, OPTAB_LIB_WIDEN
);
4583 if (tem
!= quotient
)
4584 emit_move_insn (quotient
, tem
);
4585 expand_inc (quotient
, const1_rtx
);
4586 emit_label (label2
);
4591 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4592 && INTVAL (op1
) >= 0)
4594 /* This is extremely similar to the code for the unsigned case
4595 above. For 2.7 we should merge these variants, but for
4596 2.6.1 I don't want to touch the code for unsigned since that
4597 get used in C. The signed case will only be used by other
4601 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4602 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4603 floor_log2 (d
), tquotient
, 0);
4604 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4605 gen_int_mode (d
- 1, compute_mode
),
4606 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4607 t3
= gen_reg_rtx (compute_mode
);
4608 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4609 compute_mode
, 1, 1);
4613 lab
= gen_label_rtx ();
4614 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4615 expand_inc (t1
, const1_rtx
);
4620 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4626 /* Try using an instruction that produces both the quotient and
4627 remainder, using truncation. We can easily compensate the
4628 quotient or remainder to get ceiling rounding, once we have the
4629 remainder. Notice that we compute also the final remainder
4630 value here, and return the result right away. */
4631 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4632 target
= gen_reg_rtx (compute_mode
);
4635 remainder
= (REG_P (target
)
4636 ? target
: gen_reg_rtx (compute_mode
));
4637 quotient
= gen_reg_rtx (compute_mode
);
4641 quotient
= (REG_P (target
)
4642 ? target
: gen_reg_rtx (compute_mode
));
4643 remainder
= gen_reg_rtx (compute_mode
);
4646 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4649 /* This could be computed with a branch-less sequence.
4650 Save that for later. */
4652 rtx label
= gen_label_rtx ();
4653 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4654 compute_mode
, label
);
4655 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4656 NULL_RTX
, 0, OPTAB_WIDEN
);
4657 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4658 expand_inc (quotient
, const1_rtx
);
4659 expand_dec (remainder
, op1
);
4661 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4664 /* No luck with division elimination or divmod. Have to do it
4665 by conditionally adjusting op0 *and* the result. */
4667 rtx label1
, label2
, label3
, label4
, label5
;
4671 quotient
= gen_reg_rtx (compute_mode
);
4672 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4673 label1
= gen_label_rtx ();
4674 label2
= gen_label_rtx ();
4675 label3
= gen_label_rtx ();
4676 label4
= gen_label_rtx ();
4677 label5
= gen_label_rtx ();
4678 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4679 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
4680 compute_mode
, label1
);
4681 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4682 quotient
, 0, OPTAB_LIB_WIDEN
);
4683 if (tem
!= quotient
)
4684 emit_move_insn (quotient
, tem
);
4685 emit_jump_insn (gen_jump (label5
));
4687 emit_label (label1
);
4688 expand_dec (adjusted_op0
, const1_rtx
);
4689 emit_jump_insn (gen_jump (label4
));
4691 emit_label (label2
);
4692 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
4693 compute_mode
, label3
);
4694 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4695 quotient
, 0, OPTAB_LIB_WIDEN
);
4696 if (tem
!= quotient
)
4697 emit_move_insn (quotient
, tem
);
4698 emit_jump_insn (gen_jump (label5
));
4700 emit_label (label3
);
4701 expand_inc (adjusted_op0
, const1_rtx
);
4702 emit_label (label4
);
4703 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4704 quotient
, 0, OPTAB_LIB_WIDEN
);
4705 if (tem
!= quotient
)
4706 emit_move_insn (quotient
, tem
);
4707 expand_inc (quotient
, const1_rtx
);
4708 emit_label (label5
);
4713 case EXACT_DIV_EXPR
:
4714 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
4716 HOST_WIDE_INT d
= INTVAL (op1
);
4717 unsigned HOST_WIDE_INT ml
;
4721 pre_shift
= floor_log2 (d
& -d
);
4722 ml
= invert_mod2n (d
>> pre_shift
, size
);
4723 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4724 pre_shift
, NULL_RTX
, unsignedp
);
4725 quotient
= expand_mult (compute_mode
, t1
,
4726 gen_int_mode (ml
, compute_mode
),
4729 insn
= get_last_insn ();
4730 set_dst_reg_note (insn
, REG_EQUAL
,
4731 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
4732 compute_mode
, op0
, op1
),
4737 case ROUND_DIV_EXPR
:
4738 case ROUND_MOD_EXPR
:
4743 label
= gen_label_rtx ();
4744 quotient
= gen_reg_rtx (compute_mode
);
4745 remainder
= gen_reg_rtx (compute_mode
);
4746 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
4749 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
4750 quotient
, 1, OPTAB_LIB_WIDEN
);
4751 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
4752 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4753 remainder
, 1, OPTAB_LIB_WIDEN
);
4755 tem
= plus_constant (compute_mode
, op1
, -1);
4756 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
, 1, NULL_RTX
, 1);
4757 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
4758 expand_inc (quotient
, const1_rtx
);
4759 expand_dec (remainder
, op1
);
4764 rtx abs_rem
, abs_op1
, tem
, mask
;
4766 label
= gen_label_rtx ();
4767 quotient
= gen_reg_rtx (compute_mode
);
4768 remainder
= gen_reg_rtx (compute_mode
);
4769 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
4772 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
4773 quotient
, 0, OPTAB_LIB_WIDEN
);
4774 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
4775 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
4776 remainder
, 0, OPTAB_LIB_WIDEN
);
4778 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
4779 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
4780 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
4782 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
4783 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4784 NULL_RTX
, 0, OPTAB_WIDEN
);
4785 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
4786 size
- 1, NULL_RTX
, 0);
4787 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
4788 NULL_RTX
, 0, OPTAB_WIDEN
);
4789 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4790 NULL_RTX
, 0, OPTAB_WIDEN
);
4791 expand_inc (quotient
, tem
);
4792 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
4793 NULL_RTX
, 0, OPTAB_WIDEN
);
4794 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
4795 NULL_RTX
, 0, OPTAB_WIDEN
);
4796 expand_dec (remainder
, tem
);
4799 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4807 if (target
&& GET_MODE (target
) != compute_mode
)
4812 /* Try to produce the remainder without producing the quotient.
4813 If we seem to have a divmod pattern that does not require widening,
4814 don't try widening here. We should really have a WIDEN argument
4815 to expand_twoval_binop, since what we'd really like to do here is
4816 1) try a mod insn in compute_mode
4817 2) try a divmod insn in compute_mode
4818 3) try a div insn in compute_mode and multiply-subtract to get
4820 4) try the same things with widening allowed. */
4822 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4825 ((optab_handler (optab2
, compute_mode
)
4826 != CODE_FOR_nothing
)
4827 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4830 /* No luck there. Can we do remainder and divide at once
4831 without a library call? */
4832 remainder
= gen_reg_rtx (compute_mode
);
4833 if (! expand_twoval_binop ((unsignedp
4837 NULL_RTX
, remainder
, unsignedp
))
4842 return gen_lowpart (mode
, remainder
);
4845 /* Produce the quotient. Try a quotient insn, but not a library call.
4846 If we have a divmod in this mode, use it in preference to widening
4847 the div (for this test we assume it will not fail). Note that optab2
4848 is set to the one of the two optabs that the call below will use. */
4850 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
4851 op0
, op1
, rem_flag
? NULL_RTX
: target
,
4853 ((optab_handler (optab2
, compute_mode
)
4854 != CODE_FOR_nothing
)
4855 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
4859 /* No luck there. Try a quotient-and-remainder insn,
4860 keeping the quotient alone. */
4861 quotient
= gen_reg_rtx (compute_mode
);
4862 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
4864 quotient
, NULL_RTX
, unsignedp
))
4868 /* Still no luck. If we are not computing the remainder,
4869 use a library call for the quotient. */
4870 quotient
= sign_expand_binop (compute_mode
,
4871 udiv_optab
, sdiv_optab
,
4873 unsignedp
, OPTAB_LIB_WIDEN
);
4880 if (target
&& GET_MODE (target
) != compute_mode
)
4885 /* No divide instruction either. Use library for remainder. */
4886 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
4888 unsignedp
, OPTAB_LIB_WIDEN
);
4889 /* No remainder function. Try a quotient-and-remainder
4890 function, keeping the remainder. */
4893 remainder
= gen_reg_rtx (compute_mode
);
4894 if (!expand_twoval_binop_libfunc
4895 (unsignedp
? udivmod_optab
: sdivmod_optab
,
4897 NULL_RTX
, remainder
,
4898 unsignedp
? UMOD
: MOD
))
4899 remainder
= NULL_RTX
;
4904 /* We divided. Now finish doing X - Y * (X / Y). */
4905 remainder
= expand_mult (compute_mode
, quotient
, op1
,
4906 NULL_RTX
, unsignedp
);
4907 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
4908 remainder
, target
, unsignedp
,
4913 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4916 /* Return a tree node with data type TYPE, describing the value of X.
4917 Usually this is an VAR_DECL, if there is no obvious better choice.
4918 X may be an expression, however we only support those expressions
4919 generated by loop.c. */
4922 make_tree (tree type
, rtx x
)
4926 switch (GET_CODE (x
))
4930 HOST_WIDE_INT hi
= 0;
4933 && !(TYPE_UNSIGNED (type
)
4934 && (GET_MODE_BITSIZE (TYPE_MODE (type
))
4935 < HOST_BITS_PER_WIDE_INT
)))
4938 t
= build_int_cst_wide (type
, INTVAL (x
), hi
);
4944 if (GET_MODE (x
) == VOIDmode
)
4945 t
= build_int_cst_wide (type
,
4946 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4951 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4952 t
= build_real (type
, d
);
4959 int units
= CONST_VECTOR_NUNITS (x
);
4960 tree itype
= TREE_TYPE (type
);
4964 /* Build a tree with vector elements. */
4965 elts
= XALLOCAVEC (tree
, units
);
4966 for (i
= units
- 1; i
>= 0; --i
)
4968 rtx elt
= CONST_VECTOR_ELT (x
, i
);
4969 elts
[i
] = make_tree (itype
, elt
);
4972 return build_vector (type
, elts
);
4976 return fold_build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4977 make_tree (type
, XEXP (x
, 1)));
4980 return fold_build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4981 make_tree (type
, XEXP (x
, 1)));
4984 return fold_build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0)));
4987 return fold_build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4988 make_tree (type
, XEXP (x
, 1)));
4991 return fold_build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4992 make_tree (type
, XEXP (x
, 1)));
4995 t
= unsigned_type_for (type
);
4996 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
4997 make_tree (t
, XEXP (x
, 0)),
4998 make_tree (type
, XEXP (x
, 1))));
5001 t
= signed_type_for (type
);
5002 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5003 make_tree (t
, XEXP (x
, 0)),
5004 make_tree (type
, XEXP (x
, 1))));
5007 if (TREE_CODE (type
) != REAL_TYPE
)
5008 t
= signed_type_for (type
);
5012 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5013 make_tree (t
, XEXP (x
, 0)),
5014 make_tree (t
, XEXP (x
, 1))));
5016 t
= unsigned_type_for (type
);
5017 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5018 make_tree (t
, XEXP (x
, 0)),
5019 make_tree (t
, XEXP (x
, 1))));
5023 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
5024 GET_CODE (x
) == ZERO_EXTEND
);
5025 return fold_convert (type
, make_tree (t
, XEXP (x
, 0)));
5028 return make_tree (type
, XEXP (x
, 0));
5031 t
= SYMBOL_REF_DECL (x
);
5033 return fold_convert (type
, build_fold_addr_expr (t
));
5034 /* else fall through. */
5037 t
= build_decl (RTL_LOCATION (x
), VAR_DECL
, NULL_TREE
, type
);
5039 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5040 address mode to pointer mode. */
5041 if (POINTER_TYPE_P (type
))
5042 x
= convert_memory_address_addr_space
5043 (TYPE_MODE (type
), x
, TYPE_ADDR_SPACE (TREE_TYPE (type
)));
5045 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5046 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5047 t
->decl_with_rtl
.rtl
= x
;
5053 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5054 and returning TARGET.
5056 If TARGET is 0, a pseudo-register or constant is returned. */
5059 expand_and (enum machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
5063 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
5064 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
5066 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
5070 else if (tem
!= target
)
5071 emit_move_insn (target
, tem
);
5075 /* Helper function for emit_store_flag. */
5077 emit_cstore (rtx target
, enum insn_code icode
, enum rtx_code code
,
5078 enum machine_mode mode
, enum machine_mode compare_mode
,
5079 int unsignedp
, rtx x
, rtx y
, int normalizep
,
5080 enum machine_mode target_mode
)
5082 struct expand_operand ops
[4];
5083 rtx op0
, last
, comparison
, subtarget
;
5084 enum machine_mode result_mode
= targetm
.cstore_mode (icode
);
5086 last
= get_last_insn ();
5087 x
= prepare_operand (icode
, x
, 2, mode
, compare_mode
, unsignedp
);
5088 y
= prepare_operand (icode
, y
, 3, mode
, compare_mode
, unsignedp
);
5091 delete_insns_since (last
);
5095 if (target_mode
== VOIDmode
)
5096 target_mode
= result_mode
;
5098 target
= gen_reg_rtx (target_mode
);
5100 comparison
= gen_rtx_fmt_ee (code
, result_mode
, x
, y
);
5102 create_output_operand (&ops
[0], optimize
? NULL_RTX
: target
, result_mode
);
5103 create_fixed_operand (&ops
[1], comparison
);
5104 create_fixed_operand (&ops
[2], x
);
5105 create_fixed_operand (&ops
[3], y
);
5106 if (!maybe_expand_insn (icode
, 4, ops
))
5108 delete_insns_since (last
);
5111 subtarget
= ops
[0].value
;
5113 /* If we are converting to a wider mode, first convert to
5114 TARGET_MODE, then normalize. This produces better combining
5115 opportunities on machines that have a SIGN_EXTRACT when we are
5116 testing a single bit. This mostly benefits the 68k.
5118 If STORE_FLAG_VALUE does not have the sign bit set when
5119 interpreted in MODE, we can do this conversion as unsigned, which
5120 is usually more efficient. */
5121 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (result_mode
))
5123 convert_move (target
, subtarget
,
5124 val_signbit_known_clear_p (result_mode
,
5127 result_mode
= target_mode
;
5132 /* If we want to keep subexpressions around, don't reuse our last
5137 /* Now normalize to the proper value in MODE. Sometimes we don't
5138 have to do anything. */
5139 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
5141 /* STORE_FLAG_VALUE might be the most negative number, so write
5142 the comparison this way to avoid a compiler-time warning. */
5143 else if (- normalizep
== STORE_FLAG_VALUE
)
5144 op0
= expand_unop (result_mode
, neg_optab
, op0
, subtarget
, 0);
5146 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5147 it hard to use a value of just the sign bit due to ANSI integer
5148 constant typing rules. */
5149 else if (val_signbit_known_set_p (result_mode
, STORE_FLAG_VALUE
))
5150 op0
= expand_shift (RSHIFT_EXPR
, result_mode
, op0
,
5151 GET_MODE_BITSIZE (result_mode
) - 1, subtarget
,
5155 gcc_assert (STORE_FLAG_VALUE
& 1);
5157 op0
= expand_and (result_mode
, op0
, const1_rtx
, subtarget
);
5158 if (normalizep
== -1)
5159 op0
= expand_unop (result_mode
, neg_optab
, op0
, op0
, 0);
5162 /* If we were converting to a smaller mode, do the conversion now. */
5163 if (target_mode
!= result_mode
)
5165 convert_move (target
, op0
, 0);
5173 /* A subroutine of emit_store_flag only including "tricks" that do not
5174 need a recursive call. These are kept separate to avoid infinite
5178 emit_store_flag_1 (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5179 enum machine_mode mode
, int unsignedp
, int normalizep
,
5180 enum machine_mode target_mode
)
5183 enum insn_code icode
;
5184 enum machine_mode compare_mode
;
5185 enum mode_class mclass
;
5186 enum rtx_code scode
;
5190 code
= unsigned_condition (code
);
5191 scode
= swap_condition (code
);
5193 /* If one operand is constant, make it the second one. Only do this
5194 if the other operand is not constant as well. */
5196 if (swap_commutative_operands_p (op0
, op1
))
5201 code
= swap_condition (code
);
5204 if (mode
== VOIDmode
)
5205 mode
= GET_MODE (op0
);
5207 /* For some comparisons with 1 and -1, we can convert this to
5208 comparisons with zero. This will often produce more opportunities for
5209 store-flag insns. */
5214 if (op1
== const1_rtx
)
5215 op1
= const0_rtx
, code
= LE
;
5218 if (op1
== constm1_rtx
)
5219 op1
= const0_rtx
, code
= LT
;
5222 if (op1
== const1_rtx
)
5223 op1
= const0_rtx
, code
= GT
;
5226 if (op1
== constm1_rtx
)
5227 op1
= const0_rtx
, code
= GE
;
5230 if (op1
== const1_rtx
)
5231 op1
= const0_rtx
, code
= NE
;
5234 if (op1
== const1_rtx
)
5235 op1
= const0_rtx
, code
= EQ
;
5241 /* If we are comparing a double-word integer with zero or -1, we can
5242 convert the comparison into one involving a single word. */
5243 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
5244 && GET_MODE_CLASS (mode
) == MODE_INT
5245 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
5247 if ((code
== EQ
|| code
== NE
)
5248 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
5252 /* Do a logical OR or AND of the two words and compare the
5254 op00
= simplify_gen_subreg (word_mode
, op0
, mode
, 0);
5255 op01
= simplify_gen_subreg (word_mode
, op0
, mode
, UNITS_PER_WORD
);
5256 tem
= expand_binop (word_mode
,
5257 op1
== const0_rtx
? ior_optab
: and_optab
,
5258 op00
, op01
, NULL_RTX
, unsignedp
,
5262 tem
= emit_store_flag (NULL_RTX
, code
, tem
, op1
, word_mode
,
5263 unsignedp
, normalizep
);
5265 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
5269 /* If testing the sign bit, can just test on high word. */
5270 op0h
= simplify_gen_subreg (word_mode
, op0
, mode
,
5271 subreg_highpart_offset (word_mode
,
5273 tem
= emit_store_flag (NULL_RTX
, code
, op0h
, op1
, word_mode
,
5274 unsignedp
, normalizep
);
5281 if (target_mode
== VOIDmode
|| GET_MODE (tem
) == target_mode
)
5284 target
= gen_reg_rtx (target_mode
);
5286 convert_move (target
, tem
,
5287 !val_signbit_known_set_p (word_mode
,
5288 (normalizep
? normalizep
5289 : STORE_FLAG_VALUE
)));
5294 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5295 complement of A (for GE) and shifting the sign bit to the low bit. */
5296 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
5297 && GET_MODE_CLASS (mode
) == MODE_INT
5298 && (normalizep
|| STORE_FLAG_VALUE
== 1
5299 || val_signbit_p (mode
, STORE_FLAG_VALUE
)))
5306 /* If the result is to be wider than OP0, it is best to convert it
5307 first. If it is to be narrower, it is *incorrect* to convert it
5309 else if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
5311 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5315 if (target_mode
!= mode
)
5319 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
5320 ((STORE_FLAG_VALUE
== 1 || normalizep
)
5321 ? 0 : subtarget
), 0);
5323 if (STORE_FLAG_VALUE
== 1 || normalizep
)
5324 /* If we are supposed to produce a 0/1 value, we want to do
5325 a logical shift from the sign bit to the low-order bit; for
5326 a -1/0 value, we do an arithmetic shift. */
5327 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5328 GET_MODE_BITSIZE (mode
) - 1,
5329 subtarget
, normalizep
!= -1);
5331 if (mode
!= target_mode
)
5332 op0
= convert_modes (target_mode
, mode
, op0
, 0);
5337 mclass
= GET_MODE_CLASS (mode
);
5338 for (compare_mode
= mode
; compare_mode
!= VOIDmode
;
5339 compare_mode
= GET_MODE_WIDER_MODE (compare_mode
))
5341 enum machine_mode optab_mode
= mclass
== MODE_CC
? CCmode
: compare_mode
;
5342 icode
= optab_handler (cstore_optab
, optab_mode
);
5343 if (icode
!= CODE_FOR_nothing
)
5345 do_pending_stack_adjust ();
5346 tem
= emit_cstore (target
, icode
, code
, mode
, compare_mode
,
5347 unsignedp
, op0
, op1
, normalizep
, target_mode
);
5351 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5353 tem
= emit_cstore (target
, icode
, scode
, mode
, compare_mode
,
5354 unsignedp
, op1
, op0
, normalizep
, target_mode
);
5365 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5366 and storing in TARGET. Normally return TARGET.
5367 Return 0 if that cannot be done.
5369 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5370 it is VOIDmode, they cannot both be CONST_INT.
5372 UNSIGNEDP is for the case where we have to widen the operands
5373 to perform the operation. It says to use zero-extension.
5375 NORMALIZEP is 1 if we should convert the result to be either zero
5376 or one. Normalize is -1 if we should convert the result to be
5377 either zero or -1. If NORMALIZEP is zero, the result will be left
5378 "raw" out of the scc insn. */
5381 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5382 enum machine_mode mode
, int unsignedp
, int normalizep
)
5384 enum machine_mode target_mode
= target
? GET_MODE (target
) : VOIDmode
;
5385 enum rtx_code rcode
;
5387 rtx tem
, last
, trueval
;
5389 tem
= emit_store_flag_1 (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
,
5394 /* If we reached here, we can't do this with a scc insn, however there
5395 are some comparisons that can be done in other ways. Don't do any
5396 of these cases if branches are very cheap. */
5397 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5400 /* See what we need to return. We can only return a 1, -1, or the
5403 if (normalizep
== 0)
5405 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5406 normalizep
= STORE_FLAG_VALUE
;
5408 else if (val_signbit_p (mode
, STORE_FLAG_VALUE
))
5414 last
= get_last_insn ();
5416 /* If optimizing, use different pseudo registers for each insn, instead
5417 of reusing the same pseudo. This leads to better CSE, but slows
5418 down the compiler, since there are more pseudos */
5419 subtarget
= (!optimize
5420 && (target_mode
== mode
)) ? target
: NULL_RTX
;
5421 trueval
= GEN_INT (normalizep
? normalizep
: STORE_FLAG_VALUE
);
5423 /* For floating-point comparisons, try the reverse comparison or try
5424 changing the "orderedness" of the comparison. */
5425 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5427 enum rtx_code first_code
;
5430 rcode
= reverse_condition_maybe_unordered (code
);
5431 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5432 && (code
== ORDERED
|| code
== UNORDERED
5433 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5434 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5436 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5437 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5439 /* For the reverse comparison, use either an addition or a XOR. */
5441 && rtx_cost (GEN_INT (normalizep
), PLUS
, 1,
5442 optimize_insn_for_speed_p ()) == 0)
5444 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5445 STORE_FLAG_VALUE
, target_mode
);
5447 return expand_binop (target_mode
, add_optab
, tem
,
5448 gen_int_mode (normalizep
, target_mode
),
5449 target
, 0, OPTAB_WIDEN
);
5452 && rtx_cost (trueval
, XOR
, 1,
5453 optimize_insn_for_speed_p ()) == 0)
5455 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5456 normalizep
, target_mode
);
5458 return expand_binop (target_mode
, xor_optab
, tem
, trueval
,
5459 target
, INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5463 delete_insns_since (last
);
5465 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
5466 if (code
== ORDERED
|| code
== UNORDERED
)
5469 and_them
= split_comparison (code
, mode
, &first_code
, &code
);
5471 /* If there are no NaNs, the first comparison should always fall through.
5472 Effectively change the comparison to the other one. */
5473 if (!HONOR_NANS (mode
))
5475 gcc_assert (first_code
== (and_them
? ORDERED
: UNORDERED
));
5476 return emit_store_flag_1 (target
, code
, op0
, op1
, mode
, 0, normalizep
,
5480 #ifdef HAVE_conditional_move
5481 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
5482 conditional move. */
5483 tem
= emit_store_flag_1 (subtarget
, first_code
, op0
, op1
, mode
, 0,
5484 normalizep
, target_mode
);
5489 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
5490 tem
, const0_rtx
, GET_MODE (tem
), 0);
5492 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
5493 trueval
, tem
, GET_MODE (tem
), 0);
5496 delete_insns_since (last
);
5503 /* The remaining tricks only apply to integer comparisons. */
5505 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5508 /* If this is an equality comparison of integers, we can try to exclusive-or
5509 (or subtract) the two operands and use a recursive call to try the
5510 comparison with zero. Don't do any of these cases if branches are
5513 if ((code
== EQ
|| code
== NE
) && op1
!= const0_rtx
)
5515 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
5519 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
5522 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
5523 mode
, unsignedp
, normalizep
);
5527 delete_insns_since (last
);
5530 /* For integer comparisons, try the reverse comparison. However, for
5531 small X and if we'd have anyway to extend, implementing "X != 0"
5532 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5533 rcode
= reverse_condition (code
);
5534 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5535 && ! (optab_handler (cstore_optab
, mode
) == CODE_FOR_nothing
5537 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5538 && op1
== const0_rtx
))
5540 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5541 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5543 /* Again, for the reverse comparison, use either an addition or a XOR. */
5545 && rtx_cost (GEN_INT (normalizep
), PLUS
, 1,
5546 optimize_insn_for_speed_p ()) == 0)
5548 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5549 STORE_FLAG_VALUE
, target_mode
);
5551 tem
= expand_binop (target_mode
, add_optab
, tem
,
5552 gen_int_mode (normalizep
, target_mode
),
5553 target
, 0, OPTAB_WIDEN
);
5556 && rtx_cost (trueval
, XOR
, 1,
5557 optimize_insn_for_speed_p ()) == 0)
5559 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5560 normalizep
, target_mode
);
5562 tem
= expand_binop (target_mode
, xor_optab
, tem
, trueval
, target
,
5563 INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5568 delete_insns_since (last
);
5571 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5572 the constant zero. Reject all other comparisons at this point. Only
5573 do LE and GT if branches are expensive since they are expensive on
5574 2-operand machines. */
5576 if (op1
!= const0_rtx
5577 || (code
!= EQ
&& code
!= NE
5578 && (BRANCH_COST (optimize_insn_for_speed_p (),
5579 false) <= 1 || (code
!= LE
&& code
!= GT
))))
5582 /* Try to put the result of the comparison in the sign bit. Assume we can't
5583 do the necessary operation below. */
5587 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5588 the sign bit set. */
5592 /* This is destructive, so SUBTARGET can't be OP0. */
5593 if (rtx_equal_p (subtarget
, op0
))
5596 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
5599 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
5603 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5604 number of bits in the mode of OP0, minus one. */
5608 if (rtx_equal_p (subtarget
, op0
))
5611 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
5612 GET_MODE_BITSIZE (mode
) - 1,
5614 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5618 if (code
== EQ
|| code
== NE
)
5620 /* For EQ or NE, one way to do the comparison is to apply an operation
5621 that converts the operand into a positive number if it is nonzero
5622 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5623 for NE we negate. This puts the result in the sign bit. Then we
5624 normalize with a shift, if needed.
5626 Two operations that can do the above actions are ABS and FFS, so try
5627 them. If that doesn't work, and MODE is smaller than a full word,
5628 we can use zero-extension to the wider mode (an unsigned conversion)
5629 as the operation. */
5631 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5632 that is compensated by the subsequent overflow when subtracting
5635 if (optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)
5636 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5637 else if (optab_handler (ffs_optab
, mode
) != CODE_FOR_nothing
)
5638 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5639 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5641 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5648 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5651 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5654 /* If we couldn't do it that way, for NE we can "or" the two's complement
5655 of the value with itself. For EQ, we take the one's complement of
5656 that "or", which is an extra insn, so we only handle EQ if branches
5661 || BRANCH_COST (optimize_insn_for_speed_p (),
5664 if (rtx_equal_p (subtarget
, op0
))
5667 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5668 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5671 if (tem
&& code
== EQ
)
5672 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5676 if (tem
&& normalizep
)
5677 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
5678 GET_MODE_BITSIZE (mode
) - 1,
5679 subtarget
, normalizep
== 1);
5685 else if (GET_MODE (tem
) != target_mode
)
5687 convert_move (target
, tem
, 0);
5690 else if (!subtarget
)
5692 emit_move_insn (target
, tem
);
5697 delete_insns_since (last
);
5702 /* Like emit_store_flag, but always succeeds. */
5705 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5706 enum machine_mode mode
, int unsignedp
, int normalizep
)
5709 rtx trueval
, falseval
;
5711 /* First see if emit_store_flag can do the job. */
5712 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
5717 target
= gen_reg_rtx (word_mode
);
5719 /* If this failed, we have to do this with set/compare/jump/set code.
5720 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
5721 trueval
= normalizep
? GEN_INT (normalizep
) : const1_rtx
;
5723 && GET_MODE_CLASS (mode
) == MODE_INT
5726 && op1
== const0_rtx
)
5728 label
= gen_label_rtx ();
5729 do_compare_rtx_and_jump (target
, const0_rtx
, EQ
, unsignedp
,
5730 mode
, NULL_RTX
, NULL_RTX
, label
, -1);
5731 emit_move_insn (target
, trueval
);
5737 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
5738 target
= gen_reg_rtx (GET_MODE (target
));
5740 /* Jump in the right direction if the target cannot implement CODE
5741 but can jump on its reverse condition. */
5742 falseval
= const0_rtx
;
5743 if (! can_compare_p (code
, mode
, ccp_jump
)
5744 && (! FLOAT_MODE_P (mode
)
5745 || code
== ORDERED
|| code
== UNORDERED
5746 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5747 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5749 enum rtx_code rcode
;
5750 if (FLOAT_MODE_P (mode
))
5751 rcode
= reverse_condition_maybe_unordered (code
);
5753 rcode
= reverse_condition (code
);
5755 /* Canonicalize to UNORDERED for the libcall. */
5756 if (can_compare_p (rcode
, mode
, ccp_jump
)
5757 || (code
== ORDERED
&& ! can_compare_p (ORDERED
, mode
, ccp_jump
)))
5760 trueval
= const0_rtx
;
5765 emit_move_insn (target
, trueval
);
5766 label
= gen_label_rtx ();
5767 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
5768 NULL_RTX
, label
, -1);
5770 emit_move_insn (target
, falseval
);
5776 /* Perform possibly multi-word comparison and conditional jump to LABEL
5777 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
5778 now a thin wrapper around do_compare_rtx_and_jump. */
5781 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, enum machine_mode mode
,
5784 int unsignedp
= (op
== LTU
|| op
== LEU
|| op
== GTU
|| op
== GEU
);
5785 do_compare_rtx_and_jump (arg1
, arg2
, op
, unsignedp
, mode
,
5786 NULL_RTX
, NULL_RTX
, label
, -1);