1 /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "hash-table.h"
26 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "addresses.h"
34 #include "insn-config.h"
37 #include "diagnostic-core.h"
42 /* The flags is set up every time when we calculate pseudo register
43 classes through function ira_set_pseudo_classes. */
44 static bool pseudo_classes_defined_p
= false;
46 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
47 static bool allocno_p
;
49 /* Number of elements in array `costs'. */
50 static int cost_elements_num
;
52 /* The `costs' struct records the cost of using hard registers of each
53 class considered for the calculation and of using memory for each
58 /* Costs for register classes start here. We process only some
63 #define max_struct_costs_size \
64 (this_target_ira_int->x_max_struct_costs_size)
66 (this_target_ira_int->x_init_cost)
68 (this_target_ira_int->x_temp_costs)
70 (this_target_ira_int->x_op_costs)
71 #define this_op_costs \
72 (this_target_ira_int->x_this_op_costs)
74 /* Costs of each class for each allocno or pseudo. */
75 static struct costs
*costs
;
77 /* Accumulated costs of each class for each allocno. */
78 static struct costs
*total_allocno_costs
;
80 /* It is the current size of struct costs. */
81 static int struct_costs_size
;
83 /* Return pointer to structure containing costs of allocno or pseudo
84 with given NUM in array ARR. */
85 #define COSTS(arr, num) \
86 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
88 /* Return index in COSTS when processing reg with REGNO. */
89 #define COST_INDEX(regno) (allocno_p \
90 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
93 /* Record register class preferences of each allocno or pseudo. Null
94 value means no preferences. It happens on the 1st iteration of the
96 static enum reg_class
*pref
;
98 /* Allocated buffers for pref. */
99 static enum reg_class
*pref_buffer
;
101 /* Record allocno class of each allocno with the same regno. */
102 static enum reg_class
*regno_aclass
;
104 /* Record cost gains for not allocating a register with an invariant
106 static int *regno_equiv_gains
;
108 /* Execution frequency of the current insn. */
109 static int frequency
;
113 /* Info about reg classes whose costs are calculated for a pseudo. */
116 /* Number of the cost classes in the subsequent array. */
118 /* Container of the cost classes. */
119 enum reg_class classes
[N_REG_CLASSES
];
120 /* Map reg class -> index of the reg class in the previous array.
121 -1 if it is not a cost classe. */
122 int index
[N_REG_CLASSES
];
123 /* Map hard regno index of first class in array CLASSES containing
124 the hard regno, -1 otherwise. */
125 int hard_regno_index
[FIRST_PSEUDO_REGISTER
];
128 /* Types of pointers to the structure above. */
129 typedef struct cost_classes
*cost_classes_t
;
130 typedef const struct cost_classes
*const_cost_classes_t
;
132 /* Info about cost classes for each pseudo. */
133 static cost_classes_t
*regno_cost_classes
;
135 /* Helper for cost_classes hashing. */
137 struct cost_classes_hasher
139 typedef cost_classes value_type
;
140 typedef cost_classes compare_type
;
141 static inline hashval_t
hash (const value_type
*);
142 static inline bool equal (const value_type
*, const compare_type
*);
143 static inline void remove (value_type
*);
146 /* Returns hash value for cost classes info HV. */
148 cost_classes_hasher::hash (const value_type
*hv
)
150 return iterative_hash (&hv
->classes
, sizeof (enum reg_class
) * hv
->num
, 0);
153 /* Compares cost classes info HV1 and HV2. */
155 cost_classes_hasher::equal (const value_type
*hv1
, const compare_type
*hv2
)
157 return (hv1
->num
== hv2
->num
158 && memcmp (hv1
->classes
, hv2
->classes
,
159 sizeof (enum reg_class
) * hv1
->num
) == 0);
162 /* Delete cost classes info V from the hash table. */
164 cost_classes_hasher::remove (value_type
*v
)
169 /* Hash table of unique cost classes. */
170 static hash_table
<cost_classes_hasher
> cost_classes_htab
;
172 /* Map allocno class -> cost classes for pseudo of given allocno
174 static cost_classes_t cost_classes_aclass_cache
[N_REG_CLASSES
];
176 /* Map mode -> cost classes for pseudo of give mode. */
177 static cost_classes_t cost_classes_mode_cache
[MAX_MACHINE_MODE
];
179 /* Initialize info about the cost classes for each pseudo. */
181 initiate_regno_cost_classes (void)
183 int size
= sizeof (cost_classes_t
) * max_reg_num ();
185 regno_cost_classes
= (cost_classes_t
*) ira_allocate (size
);
186 memset (regno_cost_classes
, 0, size
);
187 memset (cost_classes_aclass_cache
, 0,
188 sizeof (cost_classes_t
) * N_REG_CLASSES
);
189 memset (cost_classes_mode_cache
, 0,
190 sizeof (cost_classes_t
) * MAX_MACHINE_MODE
);
191 cost_classes_htab
.create (200);
194 /* Create new cost classes from cost classes FROM and set up members
195 index and hard_regno_index. Return the new classes. The function
196 implements some common code of two functions
197 setup_regno_cost_classes_by_aclass and
198 setup_regno_cost_classes_by_mode. */
199 static cost_classes_t
200 setup_cost_classes (cost_classes_t from
)
202 cost_classes_t classes_ptr
;
204 int i
, j
, hard_regno
;
206 classes_ptr
= (cost_classes_t
) ira_allocate (sizeof (struct cost_classes
));
207 classes_ptr
->num
= from
->num
;
208 for (i
= 0; i
< N_REG_CLASSES
; i
++)
209 classes_ptr
->index
[i
] = -1;
210 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
211 classes_ptr
->hard_regno_index
[i
] = -1;
212 for (i
= 0; i
< from
->num
; i
++)
214 cl
= classes_ptr
->classes
[i
] = from
->classes
[i
];
215 classes_ptr
->index
[cl
] = i
;
216 for (j
= ira_class_hard_regs_num
[cl
] - 1; j
>= 0; j
--)
218 hard_regno
= ira_class_hard_regs
[cl
][j
];
219 if (classes_ptr
->hard_regno_index
[hard_regno
] < 0)
220 classes_ptr
->hard_regno_index
[hard_regno
] = i
;
226 /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.
227 This function is used when we know an initial approximation of
228 allocno class of the pseudo already, e.g. on the second iteration
229 of class cost calculation or after class cost calculation in
230 register-pressure sensitive insn scheduling or register-pressure
231 sensitive loop-invariant motion. */
233 setup_regno_cost_classes_by_aclass (int regno
, enum reg_class aclass
)
235 static struct cost_classes classes
;
236 cost_classes_t classes_ptr
;
240 HARD_REG_SET temp
, temp2
;
243 if ((classes_ptr
= cost_classes_aclass_cache
[aclass
]) == NULL
)
245 COPY_HARD_REG_SET (temp
, reg_class_contents
[aclass
]);
246 AND_COMPL_HARD_REG_SET (temp
, ira_no_alloc_regs
);
247 /* We exclude classes from consideration which are subsets of
248 ACLASS only if ACLASS is an uniform class. */
249 exclude_p
= ira_uniform_class_p
[aclass
];
251 for (i
= 0; i
< ira_important_classes_num
; i
++)
253 cl
= ira_important_classes
[i
];
256 /* Exclude non-uniform classes which are subsets of
258 COPY_HARD_REG_SET (temp2
, reg_class_contents
[cl
]);
259 AND_COMPL_HARD_REG_SET (temp2
, ira_no_alloc_regs
);
260 if (hard_reg_set_subset_p (temp2
, temp
) && cl
!= aclass
)
263 classes
.classes
[classes
.num
++] = cl
;
265 slot
= cost_classes_htab
.find_slot (&classes
, INSERT
);
268 classes_ptr
= setup_cost_classes (&classes
);
271 classes_ptr
= cost_classes_aclass_cache
[aclass
] = (cost_classes_t
) *slot
;
273 regno_cost_classes
[regno
] = classes_ptr
;
276 /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can
277 decrease number of cost classes for the pseudo, if hard registers
278 of some important classes can not hold a value of MODE. So the
279 pseudo can not get hard register of some important classes and cost
280 calculation for such important classes is only waisting CPU
283 setup_regno_cost_classes_by_mode (int regno
, enum machine_mode mode
)
285 static struct cost_classes classes
;
286 cost_classes_t classes_ptr
;
292 if ((classes_ptr
= cost_classes_mode_cache
[mode
]) == NULL
)
295 for (i
= 0; i
< ira_important_classes_num
; i
++)
297 cl
= ira_important_classes
[i
];
298 COPY_HARD_REG_SET (temp
, ira_prohibited_class_mode_regs
[cl
][mode
]);
299 IOR_HARD_REG_SET (temp
, ira_no_alloc_regs
);
300 if (hard_reg_set_subset_p (reg_class_contents
[cl
], temp
))
302 classes
.classes
[classes
.num
++] = cl
;
304 slot
= cost_classes_htab
.find_slot (&classes
, INSERT
);
307 classes_ptr
= setup_cost_classes (&classes
);
311 classes_ptr
= (cost_classes_t
) *slot
;
312 cost_classes_mode_cache
[mode
] = (cost_classes_t
) *slot
;
314 regno_cost_classes
[regno
] = classes_ptr
;
317 /* Finilize info about the cost classes for each pseudo. */
319 finish_regno_cost_classes (void)
321 ira_free (regno_cost_classes
);
322 cost_classes_htab
.dispose ();
327 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
328 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
329 be a pseudo register. */
331 copy_cost (rtx x
, enum machine_mode mode
, reg_class_t rclass
, bool to_p
,
332 secondary_reload_info
*prev_sri
)
334 secondary_reload_info sri
;
335 reg_class_t secondary_class
= NO_REGS
;
337 /* If X is a SCRATCH, there is actually nothing to move since we are
338 assuming optimal allocation. */
339 if (GET_CODE (x
) == SCRATCH
)
342 /* Get the class we will actually use for a reload. */
343 rclass
= targetm
.preferred_reload_class (x
, rclass
);
345 /* If we need a secondary reload for an intermediate, the cost is
346 that to load the input into the intermediate register, then to
348 sri
.prev_sri
= prev_sri
;
350 secondary_class
= targetm
.secondary_reload (to_p
, x
, rclass
, mode
, &sri
);
352 if (secondary_class
!= NO_REGS
)
354 ira_init_register_move_cost_if_necessary (mode
);
355 return (ira_register_move_cost
[mode
][(int) secondary_class
][(int) rclass
]
357 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
360 /* For memory, use the memory move cost, for (hard) registers, use
361 the cost to move between the register classes, and use 2 for
362 everything else (constants). */
363 if (MEM_P (x
) || rclass
== NO_REGS
)
364 return sri
.extra_cost
365 + ira_memory_move_cost
[mode
][(int) rclass
][to_p
!= 0];
368 reg_class_t x_class
= REGNO_REG_CLASS (REGNO (x
));
370 ira_init_register_move_cost_if_necessary (mode
);
371 return (sri
.extra_cost
372 + ira_register_move_cost
[mode
][(int) x_class
][(int) rclass
]);
375 /* If this is a constant, we may eventually want to call rtx_cost
377 return sri
.extra_cost
+ COSTS_N_INSNS (1);
382 /* Record the cost of using memory or hard registers of various
383 classes for the operands in INSN.
385 N_ALTS is the number of alternatives.
386 N_OPS is the number of operands.
387 OPS is an array of the operands.
388 MODES are the modes of the operands, in case any are VOIDmode.
389 CONSTRAINTS are the constraints to use for the operands. This array
390 is modified by this procedure.
392 This procedure works alternative by alternative. For each
393 alternative we assume that we will be able to allocate all allocnos
394 to their ideal register class and calculate the cost of using that
395 alternative. Then we compute, for each operand that is a
396 pseudo-register, the cost of having the allocno allocated to each
397 register class and using it in that alternative. To this cost is
398 added the cost of the alternative.
400 The cost of each class for this insn is its lowest cost among all
403 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
404 enum machine_mode
*modes
, const char **constraints
,
405 rtx insn
, enum reg_class
*pref
)
409 int insn_allows_mem
[MAX_RECOG_OPERANDS
];
410 move_table
*move_in_cost
, *move_out_cost
;
411 short (*mem_cost
)[2];
413 for (i
= 0; i
< n_ops
; i
++)
414 insn_allows_mem
[i
] = 0;
416 /* Process each alternative, each time minimizing an operand's cost
417 with the cost for each operand in that alternative. */
418 for (alt
= 0; alt
< n_alts
; alt
++)
420 enum reg_class classes
[MAX_RECOG_OPERANDS
];
421 int allows_mem
[MAX_RECOG_OPERANDS
];
422 enum reg_class rclass
;
424 int alt_cost
= 0, op_cost_add
;
426 if (!TEST_BIT (recog_data
.enabled_alternatives
, alt
))
428 for (i
= 0; i
< recog_data
.n_operands
; i
++)
429 constraints
[i
] = skip_alternative (constraints
[i
]);
434 for (i
= 0; i
< n_ops
; i
++)
437 const char *p
= constraints
[i
];
439 enum machine_mode mode
= modes
[i
];
443 /* Initially show we know nothing about the register class. */
444 classes
[i
] = NO_REGS
;
447 /* If this operand has no constraints at all, we can
448 conclude nothing about it since anything is valid. */
451 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
452 memset (this_op_costs
[i
], 0, struct_costs_size
);
456 /* If this alternative is only relevant when this operand
457 matches a previous operand, we do different things
458 depending on whether this operand is a allocno-reg or not.
459 We must process any modifiers for the operand before we
460 can make this test. */
461 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
464 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
466 /* Copy class and whether memory is allowed from the
467 matching alternative. Then perform any needed cost
468 computations and/or adjustments. */
470 classes
[i
] = classes
[j
];
471 allows_mem
[i
] = allows_mem
[j
];
473 insn_allows_mem
[i
] = 1;
475 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
477 /* If this matches the other operand, we have no
478 added cost and we win. */
479 if (rtx_equal_p (ops
[j
], op
))
481 /* If we can put the other operand into a register,
482 add to the cost of this alternative the cost to
483 copy this operand to the register used for the
485 else if (classes
[j
] != NO_REGS
)
487 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
491 else if (! REG_P (ops
[j
])
492 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
494 /* This op is an allocno but the one it matches is
497 /* If we can't put the other operand into a
498 register, this alternative can't be used. */
500 if (classes
[j
] == NO_REGS
)
502 /* Otherwise, add to the cost of this alternative
503 the cost to copy the other operand to the hard
504 register used for this operand. */
506 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
510 /* The costs of this operand are not the same as the
511 other operand since move costs are not symmetric.
512 Moreover, if we cannot tie them, this alternative
513 needs to do a copy, which is one insn. */
514 struct costs
*pp
= this_op_costs
[i
];
515 int *pp_costs
= pp
->cost
;
516 cost_classes_t cost_classes_ptr
517 = regno_cost_classes
[REGNO (op
)];
518 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
519 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
520 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
521 enum reg_class op_class
= classes
[i
];
523 ira_init_register_move_cost_if_necessary (mode
);
527 if (op_class
== NO_REGS
)
529 mem_cost
= ira_memory_move_cost
[mode
];
530 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
532 rclass
= cost_classes
[k
];
533 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
538 move_out_cost
= ira_may_move_out_cost
[mode
];
539 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
541 rclass
= cost_classes
[k
];
543 = move_out_cost
[op_class
][rclass
] * frequency
;
550 if (op_class
== NO_REGS
)
552 mem_cost
= ira_memory_move_cost
[mode
];
553 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
555 rclass
= cost_classes
[k
];
556 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
561 move_in_cost
= ira_may_move_in_cost
[mode
];
562 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
564 rclass
= cost_classes
[k
];
566 = move_in_cost
[rclass
][op_class
] * frequency
;
572 if (op_class
== NO_REGS
)
574 mem_cost
= ira_memory_move_cost
[mode
];
575 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
577 rclass
= cost_classes
[k
];
578 pp_costs
[k
] = ((mem_cost
[rclass
][0]
579 + mem_cost
[rclass
][1])
585 move_in_cost
= ira_may_move_in_cost
[mode
];
586 move_out_cost
= ira_may_move_out_cost
[mode
];
587 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
589 rclass
= cost_classes
[k
];
590 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
591 + move_out_cost
[op_class
][rclass
])
597 /* If the alternative actually allows memory, make
598 things a bit cheaper since we won't need an extra
601 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
602 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
603 - allows_mem
[i
]) * frequency
;
605 /* If we have assigned a class to this allocno in
606 our first pass, add a cost to this alternative
607 corresponding to what we would add if this
608 allocno were not in the appropriate class. */
611 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
613 if (pref_class
== NO_REGS
)
616 ? ira_memory_move_cost
[mode
][op_class
][0] : 0)
618 ? ira_memory_move_cost
[mode
][op_class
][1]
620 else if (ira_reg_class_intersect
621 [pref_class
][op_class
] == NO_REGS
)
623 += ira_register_move_cost
[mode
][pref_class
][op_class
];
625 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
626 && ! find_reg_note (insn
, REG_DEAD
, op
))
629 /* This is in place of ordinary cost computation for
630 this operand, so skip to the end of the
631 alternative (should be just one character). */
632 while (*p
&& *p
++ != ',')
640 /* Scan all the constraint letters. See if the operand
641 matches any of the constraints. Collect the valid
642 register classes and see if this operand accepts
651 /* Ignore the next letter for this pass. */
657 case '!': case '#': case '&':
658 case '0': case '1': case '2': case '3': case '4':
659 case '5': case '6': case '7': case '8': case '9':
664 win
= address_operand (op
, GET_MODE (op
));
665 /* We know this operand is an address, so we want it
666 to be allocated to a register that can be the
667 base of an address, i.e. BASE_REG_CLASS. */
669 = ira_reg_class_subunion
[classes
[i
]]
670 [base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
674 case 'm': case 'o': case 'V':
675 /* It doesn't seem worth distinguishing between
676 offsettable and non-offsettable addresses
678 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
685 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
686 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
692 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
693 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
699 if (CONST_DOUBLE_AS_FLOAT_P (op
)
700 || (GET_CODE (op
) == CONST_VECTOR
701 && (GET_MODE_CLASS (GET_MODE (op
))
702 == MODE_VECTOR_FLOAT
)))
708 if (CONST_DOUBLE_AS_FLOAT_P (op
)
709 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
714 if (CONST_SCALAR_INT_P (op
))
719 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
724 if (CONST_SCALAR_INT_P (op
))
737 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
748 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
750 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
752 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][GENERAL_REGS
];
756 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
757 classes
[i
] = ira_reg_class_subunion
[classes
[i
]]
758 [REG_CLASS_FROM_CONSTRAINT (c
, p
)];
759 #ifdef EXTRA_CONSTRAINT_STR
760 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
763 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
765 /* Every MEM can be reloaded to fit. */
766 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
770 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
772 /* Every address can be reloaded to fit. */
774 if (address_operand (op
, GET_MODE (op
)))
776 /* We know this operand is an address, so we
777 want it to be allocated to a hard register
778 that can be the base of an address,
779 i.e. BASE_REG_CLASS. */
781 = ira_reg_class_subunion
[classes
[i
]]
782 [base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
788 p
+= CONSTRAINT_LEN (c
, p
);
795 /* How we account for this operand now depends on whether it
796 is a pseudo register or not. If it is, we first check if
797 any register classes are valid. If not, we ignore this
798 alternative, since we want to assume that all allocnos get
799 allocated for register preferencing. If some register
800 class is valid, compute the costs of moving the allocno
802 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
804 if (classes
[i
] == NO_REGS
&& ! allows_mem
[i
])
806 /* We must always fail if the operand is a REG, but
807 we did not find a suitable class and memory is
810 Otherwise we may perform an uninitialized read
811 from this_op_costs after the `continue' statement
817 unsigned int regno
= REGNO (op
);
818 struct costs
*pp
= this_op_costs
[i
];
819 int *pp_costs
= pp
->cost
;
820 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
821 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
822 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
823 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
824 enum reg_class op_class
= classes
[i
];
826 ira_init_register_move_cost_if_necessary (mode
);
830 if (op_class
== NO_REGS
)
832 mem_cost
= ira_memory_move_cost
[mode
];
833 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
835 rclass
= cost_classes
[k
];
836 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
841 move_out_cost
= ira_may_move_out_cost
[mode
];
842 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
844 rclass
= cost_classes
[k
];
846 = move_out_cost
[op_class
][rclass
] * frequency
;
853 if (op_class
== NO_REGS
)
855 mem_cost
= ira_memory_move_cost
[mode
];
856 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
858 rclass
= cost_classes
[k
];
859 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
864 move_in_cost
= ira_may_move_in_cost
[mode
];
865 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
867 rclass
= cost_classes
[k
];
869 = move_in_cost
[rclass
][op_class
] * frequency
;
875 if (op_class
== NO_REGS
)
877 mem_cost
= ira_memory_move_cost
[mode
];
878 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
880 rclass
= cost_classes
[k
];
881 pp_costs
[k
] = ((mem_cost
[rclass
][0]
882 + mem_cost
[rclass
][1])
888 move_in_cost
= ira_may_move_in_cost
[mode
];
889 move_out_cost
= ira_may_move_out_cost
[mode
];
890 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
892 rclass
= cost_classes
[k
];
893 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
894 + move_out_cost
[op_class
][rclass
])
900 if (op_class
== NO_REGS
)
901 /* Although we don't need insn to reload from
902 memory, still accessing memory is usually more
903 expensive than a register. */
904 pp
->mem_cost
= frequency
;
906 /* If the alternative actually allows memory, make
907 things a bit cheaper since we won't need an
908 extra insn to load it. */
910 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
911 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
912 - allows_mem
[i
]) * frequency
;
913 /* If we have assigned a class to this allocno in
914 our first pass, add a cost to this alternative
915 corresponding to what we would add if this
916 allocno were not in the appropriate class. */
919 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
921 if (pref_class
== NO_REGS
)
923 if (op_class
!= NO_REGS
)
926 ? ira_memory_move_cost
[mode
][op_class
][0]
929 ? ira_memory_move_cost
[mode
][op_class
][1]
932 else if (op_class
== NO_REGS
)
935 ? ira_memory_move_cost
[mode
][pref_class
][1]
938 ? ira_memory_move_cost
[mode
][pref_class
][0]
940 else if (ira_reg_class_intersect
[pref_class
][op_class
]
942 alt_cost
+= (ira_register_move_cost
943 [mode
][pref_class
][op_class
]);
948 /* Otherwise, if this alternative wins, either because we
949 have already determined that or if we have a hard
950 register of the proper class, there is no cost for this
952 else if (win
|| (REG_P (op
)
953 && reg_fits_class_p (op
, classes
[i
],
957 /* If registers are valid, the cost of this alternative
958 includes copying the object to and/or from a
960 else if (classes
[i
] != NO_REGS
)
962 if (recog_data
.operand_type
[i
] != OP_OUT
)
963 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
965 if (recog_data
.operand_type
[i
] != OP_IN
)
966 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
968 /* The only other way this alternative can be used is if
969 this is a constant that could be placed into memory. */
970 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
971 alt_cost
+= ira_memory_move_cost
[mode
][classes
[i
]][1];
979 op_cost_add
= alt_cost
* frequency
;
980 /* Finally, update the costs with the information we've
981 calculated about this alternative. */
982 for (i
= 0; i
< n_ops
; i
++)
983 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
985 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
986 int *pp_costs
= pp
->cost
, *qq_costs
= qq
->cost
;
987 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
988 cost_classes_t cost_classes_ptr
989 = regno_cost_classes
[REGNO (ops
[i
])];
991 pp
->mem_cost
= MIN (pp
->mem_cost
,
992 (qq
->mem_cost
+ op_cost_add
) * scale
);
994 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
996 = MIN (pp_costs
[k
], (qq_costs
[k
] + op_cost_add
) * scale
);
1001 for (i
= 0; i
< n_ops
; i
++)
1006 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1008 a
= ira_curr_regno_allocno_map
[REGNO (op
)];
1009 if (! ALLOCNO_BAD_SPILL_P (a
) && insn_allows_mem
[i
] == 0)
1010 ALLOCNO_BAD_SPILL_P (a
) = true;
1017 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
1019 ok_for_index_p_nonstrict (rtx reg
)
1021 unsigned regno
= REGNO (reg
);
1023 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
1026 /* A version of regno_ok_for_base_p for use here, when all
1027 pseudo-registers should count as OK. Arguments as for
1028 regno_ok_for_base_p. */
1030 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
1031 enum rtx_code outer_code
, enum rtx_code index_code
)
1033 unsigned regno
= REGNO (reg
);
1035 if (regno
>= FIRST_PSEUDO_REGISTER
)
1037 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
1040 /* Record the pseudo registers we must reload into hard registers in a
1041 subexpression of a memory address, X.
1043 If CONTEXT is 0, we are looking at the base part of an address,
1044 otherwise we are looking at the index part.
1046 MODE and AS are the mode and address space of the memory reference;
1047 OUTER_CODE and INDEX_CODE give the context that the rtx appears in.
1048 These four arguments are passed down to base_reg_class.
1050 SCALE is twice the amount to multiply the cost by (it is twice so
1051 we can represent half-cost adjustments). */
1053 record_address_regs (enum machine_mode mode
, addr_space_t as
, rtx x
,
1054 int context
, enum rtx_code outer_code
,
1055 enum rtx_code index_code
, int scale
)
1057 enum rtx_code code
= GET_CODE (x
);
1058 enum reg_class rclass
;
1061 rclass
= INDEX_REG_CLASS
;
1063 rclass
= base_reg_class (mode
, as
, outer_code
, index_code
);
1076 /* When we have an address that is a sum, we must determine
1077 whether registers are "base" or "index" regs. If there is a
1078 sum of two registers, we must choose one to be the "base".
1079 Luckily, we can use the REG_POINTER to make a good choice
1080 most of the time. We only need to do this on machines that
1081 can have two registers in an address and where the base and
1082 index register classes are different.
1084 ??? This code used to set REGNO_POINTER_FLAG in some cases,
1085 but that seems bogus since it should only be set when we are
1086 sure the register is being used as a pointer. */
1088 rtx arg0
= XEXP (x
, 0);
1089 rtx arg1
= XEXP (x
, 1);
1090 enum rtx_code code0
= GET_CODE (arg0
);
1091 enum rtx_code code1
= GET_CODE (arg1
);
1093 /* Look inside subregs. */
1094 if (code0
== SUBREG
)
1095 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1096 if (code1
== SUBREG
)
1097 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1099 /* If this machine only allows one register per address, it
1100 must be in the first operand. */
1101 if (MAX_REGS_PER_ADDRESS
== 1)
1102 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1104 /* If index and base registers are the same on this machine,
1105 just record registers in any non-constant operands. We
1106 assume here, as well as in the tests below, that all
1107 addresses are in canonical form. */
1108 else if (INDEX_REG_CLASS
1109 == base_reg_class (VOIDmode
, as
, PLUS
, SCRATCH
))
1111 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1112 if (! CONSTANT_P (arg1
))
1113 record_address_regs (mode
, as
, arg1
, context
, PLUS
, code0
, scale
);
1116 /* If the second operand is a constant integer, it doesn't
1117 change what class the first operand must be. */
1118 else if (CONST_SCALAR_INT_P (arg1
))
1119 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1120 /* If the second operand is a symbolic constant, the first
1121 operand must be an index register. */
1122 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1123 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1124 /* If both operands are registers but one is already a hard
1125 register of index or reg-base class, give the other the
1126 class that the hard register is not. */
1127 else if (code0
== REG
&& code1
== REG
1128 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1129 && (ok_for_base_p_nonstrict (arg0
, mode
, as
, PLUS
, REG
)
1130 || ok_for_index_p_nonstrict (arg0
)))
1131 record_address_regs (mode
, as
, arg1
,
1132 ok_for_base_p_nonstrict (arg0
, mode
, as
,
1135 else if (code0
== REG
&& code1
== REG
1136 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1137 && (ok_for_base_p_nonstrict (arg1
, mode
, as
, PLUS
, REG
)
1138 || ok_for_index_p_nonstrict (arg1
)))
1139 record_address_regs (mode
, as
, arg0
,
1140 ok_for_base_p_nonstrict (arg1
, mode
, as
,
1143 /* If one operand is known to be a pointer, it must be the
1144 base with the other operand the index. Likewise if the
1145 other operand is a MULT. */
1146 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
1148 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1149 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
);
1151 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
1153 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1154 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
);
1156 /* Otherwise, count equal chances that each might be a base or
1157 index register. This case should be rare. */
1160 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
/ 2);
1161 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
/ 2);
1162 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
/ 2);
1163 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
/ 2);
1168 /* Double the importance of an allocno that is incremented or
1169 decremented, since it would take two extra insns if it ends
1170 up in the wrong place. */
1173 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
,
1174 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
1175 if (REG_P (XEXP (XEXP (x
, 1), 1)))
1176 record_address_regs (mode
, as
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
1184 /* Double the importance of an allocno that is incremented or
1185 decremented, since it would take two extra insns if it ends
1186 up in the wrong place. */
1187 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
1195 int k
, regno
, add_cost
;
1196 cost_classes_t cost_classes_ptr
;
1197 enum reg_class
*cost_classes
;
1198 move_table
*move_in_cost
;
1200 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1205 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map
[regno
]) = true;
1206 pp
= COSTS (costs
, COST_INDEX (regno
));
1207 add_cost
= (ira_memory_move_cost
[Pmode
][rclass
][1] * scale
) / 2;
1208 if (INT_MAX
- add_cost
< pp
->mem_cost
)
1209 pp
->mem_cost
= INT_MAX
;
1211 pp
->mem_cost
+= add_cost
;
1212 cost_classes_ptr
= regno_cost_classes
[regno
];
1213 cost_classes
= cost_classes_ptr
->classes
;
1214 pp_costs
= pp
->cost
;
1215 ira_init_register_move_cost_if_necessary (Pmode
);
1216 move_in_cost
= ira_may_move_in_cost
[Pmode
];
1217 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1219 i
= cost_classes
[k
];
1220 add_cost
= (move_in_cost
[i
][rclass
] * scale
) / 2;
1221 if (INT_MAX
- add_cost
< pp_costs
[k
])
1222 pp_costs
[k
] = INT_MAX
;
1224 pp_costs
[k
] += add_cost
;
1231 const char *fmt
= GET_RTX_FORMAT (code
);
1233 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1235 record_address_regs (mode
, as
, XEXP (x
, i
), context
, code
, SCRATCH
,
1243 /* Calculate the costs of insn operands. */
1245 record_operand_costs (rtx insn
, enum reg_class
*pref
)
1247 const char *constraints
[MAX_RECOG_OPERANDS
];
1248 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
1249 rtx ops
[MAX_RECOG_OPERANDS
];
1253 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1255 constraints
[i
] = recog_data
.constraints
[i
];
1256 modes
[i
] = recog_data
.operand_mode
[i
];
1259 /* If we get here, we are set up to record the costs of all the
1260 operands for this insn. Start by initializing the costs. Then
1261 handle any address registers. Finally record the desired classes
1262 for any allocnos, doing it twice if some pair of operands are
1264 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1266 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
1268 ops
[i
] = recog_data
.operand
[i
];
1269 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
1270 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
1272 if (MEM_P (recog_data
.operand
[i
]))
1273 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
1274 MEM_ADDR_SPACE (recog_data
.operand
[i
]),
1275 XEXP (recog_data
.operand
[i
], 0),
1276 0, MEM
, SCRATCH
, frequency
* 2);
1277 else if (constraints
[i
][0] == 'p'
1278 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0],
1280 record_address_regs (VOIDmode
, ADDR_SPACE_GENERIC
,
1281 recog_data
.operand
[i
], 0, ADDRESS
, SCRATCH
,
1285 /* Check for commutative in a separate loop so everything will have
1286 been initialized. We must do this even if one operand is a
1287 constant--see addsi3 in m68k.md. */
1288 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1289 if (constraints
[i
][0] == '%')
1291 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1294 /* Handle commutative operands by swapping the constraints.
1295 We assume the modes are the same. */
1296 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1297 xconstraints
[j
] = constraints
[j
];
1299 xconstraints
[i
] = constraints
[i
+1];
1300 xconstraints
[i
+1] = constraints
[i
];
1301 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1302 recog_data
.operand
, modes
,
1303 xconstraints
, insn
, pref
);
1305 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1306 recog_data
.operand
, modes
,
1307 constraints
, insn
, pref
);
1309 /* If this insn is a single set copying operand 1 to operand 0 and
1310 one operand is an allocno with the other a hard reg or an allocno
1311 that prefers a hard register that is in its own register class
1312 then we may want to adjust the cost of that register class to -1.
1314 Avoid the adjustment if the source does not die to avoid
1315 stressing of register allocator by preferrencing two colliding
1316 registers into single class.
1318 Also avoid the adjustment if a copy between hard registers of the
1319 class is expensive (ten times the cost of a default copy is
1320 considered arbitrarily expensive). This avoids losing when the
1321 preferred class is very expensive as the source of a copy
1323 if ((set
= single_set (insn
)) != NULL_RTX
1324 /* In rare cases the single set insn might have less 2 operands
1325 as the source can be a fixed special reg. */
1326 && recog_data
.n_operands
> 1
1327 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
))
1329 int regno
, other_regno
;
1330 rtx dest
= SET_DEST (set
);
1331 rtx src
= SET_SRC (set
);
1333 dest
= SET_DEST (set
);
1334 src
= SET_SRC (set
);
1335 if (GET_CODE (dest
) == SUBREG
1336 && (GET_MODE_SIZE (GET_MODE (dest
))
1337 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))))
1338 dest
= SUBREG_REG (dest
);
1339 if (GET_CODE (src
) == SUBREG
1340 && (GET_MODE_SIZE (GET_MODE (src
))
1341 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
1342 src
= SUBREG_REG (src
);
1343 if (REG_P (src
) && REG_P (dest
)
1344 && find_regno_note (insn
, REG_DEAD
, REGNO (src
))
1345 && (((regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
1346 && (other_regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
)
1347 || ((regno
= REGNO (dest
)) >= FIRST_PSEUDO_REGISTER
1348 && (other_regno
= REGNO (src
)) < FIRST_PSEUDO_REGISTER
)))
1350 enum machine_mode mode
= GET_MODE (src
);
1351 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1352 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1356 i
= regno
== (int) REGNO (src
) ? 1 : 0;
1357 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1359 rclass
= cost_classes
[k
];
1360 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], other_regno
)
1361 && (reg_class_size
[(int) rclass
]
1362 == ira_reg_class_max_nregs
[(int) rclass
][(int) mode
]))
1364 if (reg_class_size
[rclass
] == 1)
1365 op_costs
[i
]->cost
[k
] = -frequency
;
1369 nr
< hard_regno_nregs
[other_regno
][mode
];
1371 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
],
1375 if (nr
== hard_regno_nregs
[other_regno
][mode
])
1376 op_costs
[i
]->cost
[k
] = -frequency
;
1386 /* Process one insn INSN. Scan it and record each time it would save
1387 code to put a certain allocnos in a certain class. Return the last
1388 insn processed, so that the scan can be continued from there. */
1390 scan_one_insn (rtx insn
)
1392 enum rtx_code pat_code
;
1397 if (!NONDEBUG_INSN_P (insn
))
1400 pat_code
= GET_CODE (PATTERN (insn
));
1401 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
)
1404 counted_mem
= false;
1405 set
= single_set (insn
);
1406 extract_insn (insn
);
1408 /* If this insn loads a parameter from its stack slot, then it
1409 represents a savings, rather than a cost, if the parameter is
1410 stored in memory. Record this fact.
1412 Similarly if we're loading other constants from memory (constant
1413 pool, TOC references, small data areas, etc) and this is the only
1414 assignment to the destination pseudo.
1416 Don't do this if SET_SRC (set) isn't a general operand, if it is
1417 a memory requiring special instructions to load it, decreasing
1418 mem_cost might result in it being loaded using the specialized
1419 instruction into a register, then stored into stack and loaded
1420 again from the stack. See PR52208.
1422 Don't do this if SET_SRC (set) has side effect. See PR56124. */
1423 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
1424 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
1425 && ((MEM_P (XEXP (note
, 0))
1426 && !side_effects_p (SET_SRC (set
)))
1427 || (CONSTANT_P (XEXP (note
, 0))
1428 && targetm
.legitimate_constant_p (GET_MODE (SET_DEST (set
)),
1430 && REG_N_SETS (REGNO (SET_DEST (set
))) == 1))
1431 && general_operand (SET_SRC (set
), GET_MODE (SET_SRC (set
))))
1433 enum reg_class cl
= GENERAL_REGS
;
1434 rtx reg
= SET_DEST (set
);
1435 int num
= COST_INDEX (REGNO (reg
));
1437 COSTS (costs
, num
)->mem_cost
1438 -= ira_memory_move_cost
[GET_MODE (reg
)][cl
][1] * frequency
;
1439 record_address_regs (GET_MODE (SET_SRC (set
)),
1440 MEM_ADDR_SPACE (SET_SRC (set
)),
1441 XEXP (SET_SRC (set
), 0), 0, MEM
, SCRATCH
,
1446 record_operand_costs (insn
, pref
);
1448 /* Now add the cost for each operand to the total costs for its
1450 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1451 if (REG_P (recog_data
.operand
[i
])
1452 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1454 int regno
= REGNO (recog_data
.operand
[i
]);
1455 struct costs
*p
= COSTS (costs
, COST_INDEX (regno
));
1456 struct costs
*q
= op_costs
[i
];
1457 int *p_costs
= p
->cost
, *q_costs
= q
->cost
;
1458 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1461 /* If the already accounted for the memory "cost" above, don't
1465 add_cost
= q
->mem_cost
;
1466 if (add_cost
> 0 && INT_MAX
- add_cost
< p
->mem_cost
)
1467 p
->mem_cost
= INT_MAX
;
1469 p
->mem_cost
+= add_cost
;
1471 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1473 add_cost
= q_costs
[k
];
1474 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1475 p_costs
[k
] = INT_MAX
;
1477 p_costs
[k
] += add_cost
;
1486 /* Print allocnos costs to file F. */
1488 print_allocno_costs (FILE *f
)
1492 ira_allocno_iterator ai
;
1494 ira_assert (allocno_p
);
1496 FOR_EACH_ALLOCNO (a
, ai
)
1500 int regno
= ALLOCNO_REGNO (a
);
1501 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1502 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1504 i
= ALLOCNO_NUM (a
);
1505 fprintf (f
, " a%d(r%d,", i
, regno
);
1506 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1507 fprintf (f
, "b%d", bb
->index
);
1509 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1510 fprintf (f
, ") costs:");
1511 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1513 rclass
= cost_classes
[k
];
1514 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1515 #ifdef CANNOT_CHANGE_MODE_CLASS
1516 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
)
1520 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1521 COSTS (costs
, i
)->cost
[k
]);
1522 if (flag_ira_region
== IRA_REGION_ALL
1523 || flag_ira_region
== IRA_REGION_MIXED
)
1524 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->cost
[k
]);
1527 fprintf (f
, " MEM:%i", COSTS (costs
, i
)->mem_cost
);
1528 if (flag_ira_region
== IRA_REGION_ALL
1529 || flag_ira_region
== IRA_REGION_MIXED
)
1530 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->mem_cost
);
1535 /* Print pseudo costs to file F. */
1537 print_pseudo_costs (FILE *f
)
1541 cost_classes_t cost_classes_ptr
;
1542 enum reg_class
*cost_classes
;
1544 ira_assert (! allocno_p
);
1546 for (regno
= max_reg_num () - 1; regno
>= FIRST_PSEUDO_REGISTER
; regno
--)
1548 if (REG_N_REFS (regno
) <= 0)
1550 cost_classes_ptr
= regno_cost_classes
[regno
];
1551 cost_classes
= cost_classes_ptr
->classes
;
1552 fprintf (f
, " r%d costs:", regno
);
1553 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1555 rclass
= cost_classes
[k
];
1556 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1557 #ifdef CANNOT_CHANGE_MODE_CLASS
1558 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
)
1561 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1562 COSTS (costs
, regno
)->cost
[k
]);
1564 fprintf (f
, " MEM:%i\n", COSTS (costs
, regno
)->mem_cost
);
1568 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1571 process_bb_for_costs (basic_block bb
)
1575 frequency
= REG_FREQ_FROM_BB (bb
);
1578 FOR_BB_INSNS (bb
, insn
)
1579 insn
= scan_one_insn (insn
);
1582 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1585 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node
)
1589 bb
= loop_tree_node
->bb
;
1591 process_bb_for_costs (bb
);
1594 /* Find costs of register classes and memory for allocnos or pseudos
1595 and their best costs. Set up preferred, alternative and allocno
1596 classes for pseudos. */
1598 find_costs_and_classes (FILE *dump_file
)
1600 int i
, k
, start
, max_cost_classes_num
;
1603 enum reg_class
*regno_best_class
;
1607 = (enum reg_class
*) ira_allocate (max_reg_num ()
1608 * sizeof (enum reg_class
));
1609 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1610 regno_best_class
[i
] = NO_REGS
;
1611 if (!resize_reg_info () && allocno_p
1612 && pseudo_classes_defined_p
&& flag_expensive_optimizations
)
1615 ira_allocno_iterator ai
;
1618 max_cost_classes_num
= 1;
1619 FOR_EACH_ALLOCNO (a
, ai
)
1621 pref
[ALLOCNO_NUM (a
)] = reg_preferred_class (ALLOCNO_REGNO (a
));
1622 setup_regno_cost_classes_by_aclass
1623 (ALLOCNO_REGNO (a
), pref
[ALLOCNO_NUM (a
)]);
1624 max_cost_classes_num
1625 = MAX (max_cost_classes_num
,
1626 regno_cost_classes
[ALLOCNO_REGNO (a
)]->num
);
1633 max_cost_classes_num
= ira_important_classes_num
;
1634 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1635 if (regno_reg_rtx
[i
] != NULL_RTX
)
1636 setup_regno_cost_classes_by_mode (i
, PSEUDO_REGNO_MODE (i
));
1638 setup_regno_cost_classes_by_aclass (i
, ALL_REGS
);
1642 /* Clear the flag for the next compiled function. */
1643 pseudo_classes_defined_p
= false;
1644 /* Normally we scan the insns once and determine the best class to
1645 use for each allocno. However, if -fexpensive-optimizations are
1646 on, we do so twice, the second time using the tentative best
1647 classes to guide the selection. */
1648 for (pass
= start
; pass
<= flag_expensive_optimizations
; pass
++)
1650 if ((!allocno_p
|| internal_flag_ira_verbose
> 0) && dump_file
)
1652 "\nPass %i for finding pseudo/allocno costs\n\n", pass
);
1656 max_cost_classes_num
= 1;
1657 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1659 setup_regno_cost_classes_by_aclass (i
, regno_best_class
[i
]);
1660 max_cost_classes_num
1661 = MAX (max_cost_classes_num
, regno_cost_classes
[i
]->num
);
1666 = sizeof (struct costs
) + sizeof (int) * (max_cost_classes_num
- 1);
1667 /* Zero out our accumulation of the cost of each class for each
1669 memset (costs
, 0, cost_elements_num
* struct_costs_size
);
1673 /* Scan the instructions and record each time it would save code
1674 to put a certain allocno in a certain class. */
1675 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1676 process_bb_node_for_costs
, NULL
);
1678 memcpy (total_allocno_costs
, costs
,
1679 max_struct_costs_size
* ira_allocnos_num
);
1685 FOR_EACH_BB_FN (bb
, cfun
)
1686 process_bb_for_costs (bb
);
1692 /* Now for each allocno look at how desirable each class is and
1693 find which class is preferred. */
1694 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1696 ira_allocno_t a
, parent_a
;
1697 int rclass
, a_num
, parent_a_num
, add_cost
;
1698 ira_loop_tree_node_t parent
;
1699 int best_cost
, allocno_cost
;
1700 enum reg_class best
, alt_class
;
1701 cost_classes_t cost_classes_ptr
= regno_cost_classes
[i
];
1702 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1703 int *i_costs
= temp_costs
->cost
;
1705 int equiv_savings
= regno_equiv_gains
[i
];
1709 if (regno_reg_rtx
[i
] == NULL_RTX
)
1711 memcpy (temp_costs
, COSTS (costs
, i
), struct_costs_size
);
1712 i_mem_cost
= temp_costs
->mem_cost
;
1716 if (ira_regno_allocno_map
[i
] == NULL
)
1718 memset (temp_costs
, 0, struct_costs_size
);
1720 /* Find cost of all allocnos with the same regno. */
1721 for (a
= ira_regno_allocno_map
[i
];
1723 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1725 int *a_costs
, *p_costs
;
1727 a_num
= ALLOCNO_NUM (a
);
1728 if ((flag_ira_region
== IRA_REGION_ALL
1729 || flag_ira_region
== IRA_REGION_MIXED
)
1730 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1731 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
1732 /* There are no caps yet. */
1733 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
1734 (a
)->border_allocnos
,
1737 /* Propagate costs to upper levels in the region
1739 parent_a_num
= ALLOCNO_NUM (parent_a
);
1740 a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1741 p_costs
= COSTS (total_allocno_costs
, parent_a_num
)->cost
;
1742 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1744 add_cost
= a_costs
[k
];
1745 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1746 p_costs
[k
] = INT_MAX
;
1748 p_costs
[k
] += add_cost
;
1750 add_cost
= COSTS (total_allocno_costs
, a_num
)->mem_cost
;
1752 && (INT_MAX
- add_cost
1753 < COSTS (total_allocno_costs
,
1754 parent_a_num
)->mem_cost
))
1755 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1758 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1761 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1762 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
= 0;
1764 a_costs
= COSTS (costs
, a_num
)->cost
;
1765 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1767 add_cost
= a_costs
[k
];
1768 if (add_cost
> 0 && INT_MAX
- add_cost
< i_costs
[k
])
1769 i_costs
[k
] = INT_MAX
;
1771 i_costs
[k
] += add_cost
;
1773 add_cost
= COSTS (costs
, a_num
)->mem_cost
;
1774 if (add_cost
> 0 && INT_MAX
- add_cost
< i_mem_cost
)
1775 i_mem_cost
= INT_MAX
;
1777 i_mem_cost
+= add_cost
;
1780 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1782 else if (equiv_savings
< 0)
1783 i_mem_cost
= -equiv_savings
;
1784 else if (equiv_savings
> 0)
1787 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1788 i_costs
[k
] += equiv_savings
;
1791 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1793 alt_class
= NO_REGS
;
1794 /* Find best common class for all allocnos with the same
1796 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1798 rclass
= cost_classes
[k
];
1799 /* Ignore classes that are too small or invalid for this
1801 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1802 #ifdef CANNOT_CHANGE_MODE_CLASS
1803 || invalid_mode_change_p (i
, (enum reg_class
) rclass
)
1807 if (i_costs
[k
] < best_cost
)
1809 best_cost
= i_costs
[k
];
1810 best
= (enum reg_class
) rclass
;
1812 else if (i_costs
[k
] == best_cost
)
1813 best
= ira_reg_class_subunion
[best
][rclass
];
1814 if (pass
== flag_expensive_optimizations
1815 /* We still prefer registers to memory even at this
1816 stage if their costs are the same. We will make
1817 a final decision during assigning hard registers
1818 when we have all info including more accurate
1819 costs which might be affected by assigning hard
1820 registers to other pseudos because the pseudos
1821 involved in moves can be coalesced. */
1822 && i_costs
[k
] <= i_mem_cost
1823 && (reg_class_size
[reg_class_subunion
[alt_class
][rclass
]]
1824 > reg_class_size
[alt_class
]))
1825 alt_class
= reg_class_subunion
[alt_class
][rclass
];
1827 alt_class
= ira_allocno_class_translate
[alt_class
];
1828 if (best_cost
> i_mem_cost
)
1829 regno_aclass
[i
] = NO_REGS
;
1832 /* Make the common class the biggest class of best and
1835 = ira_reg_class_superunion
[best
][alt_class
];
1836 ira_assert (regno_aclass
[i
] != NO_REGS
1837 && ira_reg_allocno_class_p
[regno_aclass
[i
]]);
1839 if (pass
== flag_expensive_optimizations
)
1841 if (best_cost
> i_mem_cost
)
1842 best
= alt_class
= NO_REGS
;
1843 else if (best
== alt_class
)
1844 alt_class
= NO_REGS
;
1845 setup_reg_classes (i
, best
, alt_class
, regno_aclass
[i
]);
1846 if ((!allocno_p
|| internal_flag_ira_verbose
> 2)
1847 && dump_file
!= NULL
)
1849 " r%d: preferred %s, alternative %s, allocno %s\n",
1850 i
, reg_class_names
[best
], reg_class_names
[alt_class
],
1851 reg_class_names
[regno_aclass
[i
]]);
1853 regno_best_class
[i
] = best
;
1856 pref
[i
] = best_cost
> i_mem_cost
? NO_REGS
: best
;
1859 for (a
= ira_regno_allocno_map
[i
];
1861 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1863 enum reg_class aclass
= regno_aclass
[i
];
1864 int a_num
= ALLOCNO_NUM (a
);
1865 int *total_a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1866 int *a_costs
= COSTS (costs
, a_num
)->cost
;
1868 if (aclass
== NO_REGS
)
1872 /* Finding best class which is subset of the common
1874 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1875 allocno_cost
= best_cost
;
1877 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1879 rclass
= cost_classes
[k
];
1880 if (! ira_class_subset_p
[rclass
][aclass
])
1882 /* Ignore classes that are too small or invalid
1883 for this operand. */
1884 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1885 #ifdef CANNOT_CHANGE_MODE_CLASS
1886 || invalid_mode_change_p (i
, (enum reg_class
) rclass
)
1890 else if (total_a_costs
[k
] < best_cost
)
1892 best_cost
= total_a_costs
[k
];
1893 allocno_cost
= a_costs
[k
];
1894 best
= (enum reg_class
) rclass
;
1896 else if (total_a_costs
[k
] == best_cost
)
1898 best
= ira_reg_class_subunion
[best
][rclass
];
1899 allocno_cost
= MAX (allocno_cost
, a_costs
[k
]);
1902 ALLOCNO_CLASS_COST (a
) = allocno_cost
;
1904 if (internal_flag_ira_verbose
> 2 && dump_file
!= NULL
1905 && (pass
== 0 || pref
[a_num
] != best
))
1907 fprintf (dump_file
, " a%d (r%d,", a_num
, i
);
1908 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1909 fprintf (dump_file
, "b%d", bb
->index
);
1911 fprintf (dump_file
, "l%d",
1912 ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1913 fprintf (dump_file
, ") best %s, allocno %s\n",
1914 reg_class_names
[best
],
1915 reg_class_names
[aclass
]);
1918 if (pass
== flag_expensive_optimizations
&& best
!= aclass
1919 && ira_class_hard_regs_num
[best
] > 0
1920 && (ira_reg_class_max_nregs
[best
][ALLOCNO_MODE (a
)]
1921 >= ira_class_hard_regs_num
[best
]))
1923 int ind
= cost_classes_ptr
->index
[aclass
];
1925 ira_assert (ind
>= 0);
1926 ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a
));
1927 ira_add_allocno_pref (a
, ira_class_hard_regs
[best
][0],
1928 (a_costs
[ind
] - ALLOCNO_CLASS_COST (a
))
1929 / (ira_register_move_cost
1930 [ALLOCNO_MODE (a
)][best
][aclass
]));
1931 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1932 if (ira_class_subset_p
[cost_classes
[k
]][best
])
1933 a_costs
[k
] = a_costs
[ind
];
1938 if (internal_flag_ira_verbose
> 4 && dump_file
)
1941 print_allocno_costs (dump_file
);
1943 print_pseudo_costs (dump_file
);
1944 fprintf (dump_file
,"\n");
1947 ira_free (regno_best_class
);
1952 /* Process moves involving hard regs to modify allocno hard register
1953 costs. We can do this only after determining allocno class. If a
1954 hard register forms a register class, then moves with the hard
1955 register are already taken into account in class costs for the
1958 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node
)
1960 int i
, freq
, src_regno
, dst_regno
, hard_regno
, a_regno
;
1962 ira_allocno_t a
, curr_a
;
1963 ira_loop_tree_node_t curr_loop_tree_node
;
1964 enum reg_class rclass
;
1966 rtx insn
, set
, src
, dst
;
1968 bb
= loop_tree_node
->bb
;
1971 freq
= REG_FREQ_FROM_BB (bb
);
1974 FOR_BB_INSNS (bb
, insn
)
1976 if (!NONDEBUG_INSN_P (insn
))
1978 set
= single_set (insn
);
1979 if (set
== NULL_RTX
)
1981 dst
= SET_DEST (set
);
1982 src
= SET_SRC (set
);
1983 if (! REG_P (dst
) || ! REG_P (src
))
1985 dst_regno
= REGNO (dst
);
1986 src_regno
= REGNO (src
);
1987 if (dst_regno
>= FIRST_PSEUDO_REGISTER
1988 && src_regno
< FIRST_PSEUDO_REGISTER
)
1990 hard_regno
= src_regno
;
1991 a
= ira_curr_regno_allocno_map
[dst_regno
];
1994 else if (src_regno
>= FIRST_PSEUDO_REGISTER
1995 && dst_regno
< FIRST_PSEUDO_REGISTER
)
1997 hard_regno
= dst_regno
;
1998 a
= ira_curr_regno_allocno_map
[src_regno
];
2003 rclass
= ALLOCNO_CLASS (a
);
2004 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
], hard_regno
))
2006 i
= ira_class_hard_reg_index
[rclass
][hard_regno
];
2009 a_regno
= ALLOCNO_REGNO (a
);
2010 for (curr_loop_tree_node
= ALLOCNO_LOOP_TREE_NODE (a
);
2011 curr_loop_tree_node
!= NULL
;
2012 curr_loop_tree_node
= curr_loop_tree_node
->parent
)
2013 if ((curr_a
= curr_loop_tree_node
->regno_allocno_map
[a_regno
]) != NULL
)
2014 ira_add_allocno_pref (curr_a
, hard_regno
, freq
);
2017 enum reg_class hard_reg_class
;
2018 enum machine_mode mode
;
2020 mode
= ALLOCNO_MODE (a
);
2021 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
2022 ira_init_register_move_cost_if_necessary (mode
);
2023 cost
= (to_p
? ira_register_move_cost
[mode
][hard_reg_class
][rclass
]
2024 : ira_register_move_cost
[mode
][rclass
][hard_reg_class
]) * freq
;
2025 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), rclass
,
2026 ALLOCNO_CLASS_COST (a
));
2027 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
2029 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
2030 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
2031 ALLOCNO_CLASS_COST (a
) = MIN (ALLOCNO_CLASS_COST (a
),
2032 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
2037 /* After we find hard register and memory costs for allocnos, define
2038 its class and modify hard register cost because insns moving
2039 allocno to/from hard registers. */
2041 setup_allocno_class_and_costs (void)
2043 int i
, j
, n
, regno
, hard_regno
, num
;
2045 enum reg_class aclass
, rclass
;
2047 ira_allocno_iterator ai
;
2048 cost_classes_t cost_classes_ptr
;
2050 ira_assert (allocno_p
);
2051 FOR_EACH_ALLOCNO (a
, ai
)
2053 i
= ALLOCNO_NUM (a
);
2054 regno
= ALLOCNO_REGNO (a
);
2055 aclass
= regno_aclass
[regno
];
2056 cost_classes_ptr
= regno_cost_classes
[regno
];
2057 ira_assert (pref
[i
] == NO_REGS
|| aclass
!= NO_REGS
);
2058 ALLOCNO_MEMORY_COST (a
) = COSTS (costs
, i
)->mem_cost
;
2059 ira_set_allocno_class (a
, aclass
);
2060 if (aclass
== NO_REGS
)
2062 if (optimize
&& ALLOCNO_CLASS (a
) != pref
[i
])
2064 n
= ira_class_hard_regs_num
[aclass
];
2065 ALLOCNO_HARD_REG_COSTS (a
)
2066 = reg_costs
= ira_allocate_cost_vector (aclass
);
2067 for (j
= n
- 1; j
>= 0; j
--)
2069 hard_regno
= ira_class_hard_regs
[aclass
][j
];
2070 if (TEST_HARD_REG_BIT (reg_class_contents
[pref
[i
]], hard_regno
))
2071 reg_costs
[j
] = ALLOCNO_CLASS_COST (a
);
2074 rclass
= REGNO_REG_CLASS (hard_regno
);
2075 num
= cost_classes_ptr
->index
[rclass
];
2078 num
= cost_classes_ptr
->hard_regno_index
[hard_regno
];
2079 ira_assert (num
>= 0);
2081 reg_costs
[j
] = COSTS (costs
, i
)->cost
[num
];
2087 ira_traverse_loop_tree (true, ira_loop_tree_root
,
2088 process_bb_node_for_hard_reg_moves
, NULL
);
2093 /* Function called once during compiler work. */
2095 ira_init_costs_once (void)
2100 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2103 this_op_costs
[i
] = NULL
;
2108 /* Free allocated temporary cost vectors. */
2110 free_ira_costs (void)
2116 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2119 free (this_op_costs
[i
]);
2120 op_costs
[i
] = this_op_costs
[i
] = NULL
;
2126 /* This is called each time register related information is
2129 ira_init_costs (void)
2134 max_struct_costs_size
2135 = sizeof (struct costs
) + sizeof (int) * (ira_important_classes_num
- 1);
2136 /* Don't use ira_allocate because vectors live through several IRA
2138 init_cost
= (struct costs
*) xmalloc (max_struct_costs_size
);
2139 init_cost
->mem_cost
= 1000000;
2140 for (i
= 0; i
< ira_important_classes_num
; i
++)
2141 init_cost
->cost
[i
] = 1000000;
2142 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2144 op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2145 this_op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2147 temp_costs
= (struct costs
*) xmalloc (max_struct_costs_size
);
2150 /* Function called once at the end of compiler work. */
2152 ira_finish_costs_once (void)
2159 /* Common initialization function for ira_costs and
2160 ira_set_pseudo_classes. */
2164 init_subregs_of_mode ();
2165 costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2166 * cost_elements_num
);
2167 pref_buffer
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2168 * cost_elements_num
);
2169 regno_aclass
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2171 regno_equiv_gains
= (int *) ira_allocate (sizeof (int) * max_reg_num ());
2172 memset (regno_equiv_gains
, 0, sizeof (int) * max_reg_num ());
2175 /* Common finalization function for ira_costs and
2176 ira_set_pseudo_classes. */
2180 finish_subregs_of_mode ();
2181 ira_free (regno_equiv_gains
);
2182 ira_free (regno_aclass
);
2183 ira_free (pref_buffer
);
2187 /* Entry function which defines register class, memory and hard
2188 register costs for each allocno. */
2193 cost_elements_num
= ira_allocnos_num
;
2195 total_allocno_costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2196 * ira_allocnos_num
);
2197 initiate_regno_cost_classes ();
2198 calculate_elim_costs_all_insns ();
2199 find_costs_and_classes (ira_dump_file
);
2200 setup_allocno_class_and_costs ();
2201 finish_regno_cost_classes ();
2203 ira_free (total_allocno_costs
);
2206 /* Entry function which defines classes for pseudos.
2207 Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */
2209 ira_set_pseudo_classes (bool define_pseudo_classes
, FILE *dump_file
)
2212 internal_flag_ira_verbose
= flag_ira_verbose
;
2213 cost_elements_num
= max_reg_num ();
2215 initiate_regno_cost_classes ();
2216 find_costs_and_classes (dump_file
);
2217 finish_regno_cost_classes ();
2218 if (define_pseudo_classes
)
2219 pseudo_classes_defined_p
= true;
2226 /* Change hard register costs for allocnos which lives through
2227 function calls. This is called only when we found all intersected
2228 calls during building allocno live ranges. */
2230 ira_tune_allocno_costs (void)
2233 int cost
, min_cost
, *reg_costs
;
2234 enum reg_class aclass
, rclass
;
2235 enum machine_mode mode
;
2237 ira_allocno_iterator ai
;
2238 ira_allocno_object_iterator oi
;
2242 FOR_EACH_ALLOCNO (a
, ai
)
2244 aclass
= ALLOCNO_CLASS (a
);
2245 if (aclass
== NO_REGS
)
2247 mode
= ALLOCNO_MODE (a
);
2248 n
= ira_class_hard_regs_num
[aclass
];
2250 if (ALLOCNO_CALLS_CROSSED_NUM (a
)
2251 != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2253 ira_allocate_and_set_costs
2254 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
,
2255 ALLOCNO_CLASS_COST (a
));
2256 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2257 for (j
= n
- 1; j
>= 0; j
--)
2259 regno
= ira_class_hard_regs
[aclass
][j
];
2261 FOR_EACH_ALLOCNO_OBJECT (a
, obj
, oi
)
2263 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2264 OBJECT_CONFLICT_HARD_REGS
2273 rclass
= REGNO_REG_CLASS (regno
);
2275 if (ira_hard_reg_set_intersection_p (regno
, mode
, call_used_reg_set
)
2276 || HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
))
2277 cost
+= (ALLOCNO_CALL_FREQ (a
)
2278 * (ira_memory_move_cost
[mode
][rclass
][0]
2279 + ira_memory_move_cost
[mode
][rclass
][1]));
2280 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
2281 cost
+= ((ira_memory_move_cost
[mode
][rclass
][0]
2282 + ira_memory_move_cost
[mode
][rclass
][1])
2284 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
2286 if (INT_MAX
- cost
< reg_costs
[j
])
2287 reg_costs
[j
] = INT_MAX
;
2289 reg_costs
[j
] += cost
;
2290 if (min_cost
> reg_costs
[j
])
2291 min_cost
= reg_costs
[j
];
2294 if (min_cost
!= INT_MAX
)
2295 ALLOCNO_CLASS_COST (a
) = min_cost
;
2297 /* Some targets allow pseudos to be allocated to unaligned sequences
2298 of hard registers. However, selecting an unaligned sequence can
2299 unnecessarily restrict later allocations. So increase the cost of
2300 unaligned hard regs to encourage the use of aligned hard regs. */
2302 const int nregs
= ira_reg_class_max_nregs
[aclass
][ALLOCNO_MODE (a
)];
2306 ira_allocate_and_set_costs
2307 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
, ALLOCNO_CLASS_COST (a
));
2308 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2309 for (j
= n
- 1; j
>= 0; j
--)
2311 regno
= ira_non_ordered_class_hard_regs
[aclass
][j
];
2312 if ((regno
% nregs
) != 0)
2314 int index
= ira_class_hard_reg_index
[aclass
][regno
];
2315 ira_assert (index
!= -1);
2316 reg_costs
[index
] += ALLOCNO_FREQ (a
);
2324 /* Add COST to the estimated gain for eliminating REGNO with its
2325 equivalence. If COST is zero, record that no such elimination is
2329 ira_adjust_equiv_reg_cost (unsigned regno
, int cost
)
2332 regno_equiv_gains
[regno
] = 0;
2334 regno_equiv_gains
[regno
] += cost
;