1 /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "hash-table.h"
26 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "addresses.h"
34 #include "insn-config.h"
37 #include "diagnostic-core.h"
42 /* The flags is set up every time when we calculate pseudo register
43 classes through function ira_set_pseudo_classes. */
44 static bool pseudo_classes_defined_p
= false;
46 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
47 static bool allocno_p
;
49 /* Number of elements in array `costs'. */
50 static int cost_elements_num
;
52 /* The `costs' struct records the cost of using hard registers of each
53 class considered for the calculation and of using memory for each
58 /* Costs for register classes start here. We process only some
63 #define max_struct_costs_size \
64 (this_target_ira_int->x_max_struct_costs_size)
66 (this_target_ira_int->x_init_cost)
68 (this_target_ira_int->x_temp_costs)
70 (this_target_ira_int->x_op_costs)
71 #define this_op_costs \
72 (this_target_ira_int->x_this_op_costs)
74 /* Costs of each class for each allocno or pseudo. */
75 static struct costs
*costs
;
77 /* Accumulated costs of each class for each allocno. */
78 static struct costs
*total_allocno_costs
;
80 /* It is the current size of struct costs. */
81 static int struct_costs_size
;
83 /* Return pointer to structure containing costs of allocno or pseudo
84 with given NUM in array ARR. */
85 #define COSTS(arr, num) \
86 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
88 /* Return index in COSTS when processing reg with REGNO. */
89 #define COST_INDEX(regno) (allocno_p \
90 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
93 /* Record register class preferences of each allocno or pseudo. Null
94 value means no preferences. It happens on the 1st iteration of the
96 static enum reg_class
*pref
;
98 /* Allocated buffers for pref. */
99 static enum reg_class
*pref_buffer
;
101 /* Record allocno class of each allocno with the same regno. */
102 static enum reg_class
*regno_aclass
;
104 /* Record cost gains for not allocating a register with an invariant
106 static int *regno_equiv_gains
;
108 /* Execution frequency of the current insn. */
109 static int frequency
;
113 /* Info about reg classes whose costs are calculated for a pseudo. */
116 /* Number of the cost classes in the subsequent array. */
118 /* Container of the cost classes. */
119 enum reg_class classes
[N_REG_CLASSES
];
120 /* Map reg class -> index of the reg class in the previous array.
121 -1 if it is not a cost classe. */
122 int index
[N_REG_CLASSES
];
123 /* Map hard regno index of first class in array CLASSES containing
124 the hard regno, -1 otherwise. */
125 int hard_regno_index
[FIRST_PSEUDO_REGISTER
];
128 /* Types of pointers to the structure above. */
129 typedef struct cost_classes
*cost_classes_t
;
130 typedef const struct cost_classes
*const_cost_classes_t
;
132 /* Info about cost classes for each pseudo. */
133 static cost_classes_t
*regno_cost_classes
;
135 /* Helper for cost_classes hashing. */
137 struct cost_classes_hasher
139 typedef cost_classes value_type
;
140 typedef cost_classes compare_type
;
141 static inline hashval_t
hash (const value_type
*);
142 static inline bool equal (const value_type
*, const compare_type
*);
143 static inline void remove (value_type
*);
146 /* Returns hash value for cost classes info HV. */
148 cost_classes_hasher::hash (const value_type
*hv
)
150 return iterative_hash (&hv
->classes
, sizeof (enum reg_class
) * hv
->num
, 0);
153 /* Compares cost classes info HV1 and HV2. */
155 cost_classes_hasher::equal (const value_type
*hv1
, const compare_type
*hv2
)
157 return (hv1
->num
== hv2
->num
158 && memcmp (hv1
->classes
, hv2
->classes
,
159 sizeof (enum reg_class
) * hv1
->num
) == 0);
162 /* Delete cost classes info V from the hash table. */
164 cost_classes_hasher::remove (value_type
*v
)
169 /* Hash table of unique cost classes. */
170 static hash_table
<cost_classes_hasher
> cost_classes_htab
;
172 /* Map allocno class -> cost classes for pseudo of given allocno
174 static cost_classes_t cost_classes_aclass_cache
[N_REG_CLASSES
];
176 /* Map mode -> cost classes for pseudo of give mode. */
177 static cost_classes_t cost_classes_mode_cache
[MAX_MACHINE_MODE
];
179 /* Initialize info about the cost classes for each pseudo. */
181 initiate_regno_cost_classes (void)
183 int size
= sizeof (cost_classes_t
) * max_reg_num ();
185 regno_cost_classes
= (cost_classes_t
*) ira_allocate (size
);
186 memset (regno_cost_classes
, 0, size
);
187 memset (cost_classes_aclass_cache
, 0,
188 sizeof (cost_classes_t
) * N_REG_CLASSES
);
189 memset (cost_classes_mode_cache
, 0,
190 sizeof (cost_classes_t
) * MAX_MACHINE_MODE
);
191 cost_classes_htab
.create (200);
194 /* Create new cost classes from cost classes FROM and set up members
195 index and hard_regno_index. Return the new classes. The function
196 implements some common code of two functions
197 setup_regno_cost_classes_by_aclass and
198 setup_regno_cost_classes_by_mode. */
199 static cost_classes_t
200 setup_cost_classes (cost_classes_t from
)
202 cost_classes_t classes_ptr
;
204 int i
, j
, hard_regno
;
206 classes_ptr
= (cost_classes_t
) ira_allocate (sizeof (struct cost_classes
));
207 classes_ptr
->num
= from
->num
;
208 for (i
= 0; i
< N_REG_CLASSES
; i
++)
209 classes_ptr
->index
[i
] = -1;
210 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
211 classes_ptr
->hard_regno_index
[i
] = -1;
212 for (i
= 0; i
< from
->num
; i
++)
214 cl
= classes_ptr
->classes
[i
] = from
->classes
[i
];
215 classes_ptr
->index
[cl
] = i
;
216 for (j
= ira_class_hard_regs_num
[cl
] - 1; j
>= 0; j
--)
218 hard_regno
= ira_class_hard_regs
[cl
][j
];
219 if (classes_ptr
->hard_regno_index
[hard_regno
] < 0)
220 classes_ptr
->hard_regno_index
[hard_regno
] = i
;
226 /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.
227 This function is used when we know an initial approximation of
228 allocno class of the pseudo already, e.g. on the second iteration
229 of class cost calculation or after class cost calculation in
230 register-pressure sensitive insn scheduling or register-pressure
231 sensitive loop-invariant motion. */
233 setup_regno_cost_classes_by_aclass (int regno
, enum reg_class aclass
)
235 static struct cost_classes classes
;
236 cost_classes_t classes_ptr
;
240 HARD_REG_SET temp
, temp2
;
243 if ((classes_ptr
= cost_classes_aclass_cache
[aclass
]) == NULL
)
245 COPY_HARD_REG_SET (temp
, reg_class_contents
[aclass
]);
246 AND_COMPL_HARD_REG_SET (temp
, ira_no_alloc_regs
);
247 /* We exclude classes from consideration which are subsets of
248 ACLASS only if ACLASS is an uniform class. */
249 exclude_p
= ira_uniform_class_p
[aclass
];
251 for (i
= 0; i
< ira_important_classes_num
; i
++)
253 cl
= ira_important_classes
[i
];
256 /* Exclude non-uniform classes which are subsets of
258 COPY_HARD_REG_SET (temp2
, reg_class_contents
[cl
]);
259 AND_COMPL_HARD_REG_SET (temp2
, ira_no_alloc_regs
);
260 if (hard_reg_set_subset_p (temp2
, temp
) && cl
!= aclass
)
263 classes
.classes
[classes
.num
++] = cl
;
265 slot
= cost_classes_htab
.find_slot (&classes
, INSERT
);
268 classes_ptr
= setup_cost_classes (&classes
);
271 classes_ptr
= cost_classes_aclass_cache
[aclass
] = (cost_classes_t
) *slot
;
273 regno_cost_classes
[regno
] = classes_ptr
;
276 /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can
277 decrease number of cost classes for the pseudo, if hard registers
278 of some important classes can not hold a value of MODE. So the
279 pseudo can not get hard register of some important classes and cost
280 calculation for such important classes is only waisting CPU
283 setup_regno_cost_classes_by_mode (int regno
, enum machine_mode mode
)
285 static struct cost_classes classes
;
286 cost_classes_t classes_ptr
;
292 if ((classes_ptr
= cost_classes_mode_cache
[mode
]) == NULL
)
295 for (i
= 0; i
< ira_important_classes_num
; i
++)
297 cl
= ira_important_classes
[i
];
298 COPY_HARD_REG_SET (temp
, ira_prohibited_class_mode_regs
[cl
][mode
]);
299 IOR_HARD_REG_SET (temp
, ira_no_alloc_regs
);
300 if (hard_reg_set_subset_p (reg_class_contents
[cl
], temp
))
302 classes
.classes
[classes
.num
++] = cl
;
304 slot
= cost_classes_htab
.find_slot (&classes
, INSERT
);
307 classes_ptr
= setup_cost_classes (&classes
);
311 classes_ptr
= (cost_classes_t
) *slot
;
312 cost_classes_mode_cache
[mode
] = (cost_classes_t
) *slot
;
314 regno_cost_classes
[regno
] = classes_ptr
;
317 /* Finilize info about the cost classes for each pseudo. */
319 finish_regno_cost_classes (void)
321 ira_free (regno_cost_classes
);
322 cost_classes_htab
.dispose ();
327 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
328 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
329 be a pseudo register. */
331 copy_cost (rtx x
, enum machine_mode mode
, reg_class_t rclass
, bool to_p
,
332 secondary_reload_info
*prev_sri
)
334 secondary_reload_info sri
;
335 reg_class_t secondary_class
= NO_REGS
;
337 /* If X is a SCRATCH, there is actually nothing to move since we are
338 assuming optimal allocation. */
339 if (GET_CODE (x
) == SCRATCH
)
342 /* Get the class we will actually use for a reload. */
343 rclass
= targetm
.preferred_reload_class (x
, rclass
);
345 /* If we need a secondary reload for an intermediate, the cost is
346 that to load the input into the intermediate register, then to
348 sri
.prev_sri
= prev_sri
;
350 secondary_class
= targetm
.secondary_reload (to_p
, x
, rclass
, mode
, &sri
);
352 if (secondary_class
!= NO_REGS
)
354 ira_init_register_move_cost_if_necessary (mode
);
355 return (ira_register_move_cost
[mode
][(int) secondary_class
][(int) rclass
]
357 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
360 /* For memory, use the memory move cost, for (hard) registers, use
361 the cost to move between the register classes, and use 2 for
362 everything else (constants). */
363 if (MEM_P (x
) || rclass
== NO_REGS
)
364 return sri
.extra_cost
365 + ira_memory_move_cost
[mode
][(int) rclass
][to_p
!= 0];
368 reg_class_t x_class
= REGNO_REG_CLASS (REGNO (x
));
370 ira_init_register_move_cost_if_necessary (mode
);
371 return (sri
.extra_cost
372 + ira_register_move_cost
[mode
][(int) x_class
][(int) rclass
]);
375 /* If this is a constant, we may eventually want to call rtx_cost
377 return sri
.extra_cost
+ COSTS_N_INSNS (1);
382 /* Record the cost of using memory or hard registers of various
383 classes for the operands in INSN.
385 N_ALTS is the number of alternatives.
386 N_OPS is the number of operands.
387 OPS is an array of the operands.
388 MODES are the modes of the operands, in case any are VOIDmode.
389 CONSTRAINTS are the constraints to use for the operands. This array
390 is modified by this procedure.
392 This procedure works alternative by alternative. For each
393 alternative we assume that we will be able to allocate all allocnos
394 to their ideal register class and calculate the cost of using that
395 alternative. Then we compute, for each operand that is a
396 pseudo-register, the cost of having the allocno allocated to each
397 register class and using it in that alternative. To this cost is
398 added the cost of the alternative.
400 The cost of each class for this insn is its lowest cost among all
403 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
404 enum machine_mode
*modes
, const char **constraints
,
405 rtx insn
, enum reg_class
*pref
)
409 int insn_allows_mem
[MAX_RECOG_OPERANDS
];
410 move_table
*move_in_cost
, *move_out_cost
;
411 short (*mem_cost
)[2];
413 for (i
= 0; i
< n_ops
; i
++)
414 insn_allows_mem
[i
] = 0;
416 /* Process each alternative, each time minimizing an operand's cost
417 with the cost for each operand in that alternative. */
418 for (alt
= 0; alt
< n_alts
; alt
++)
420 enum reg_class classes
[MAX_RECOG_OPERANDS
];
421 int allows_mem
[MAX_RECOG_OPERANDS
];
422 enum reg_class rclass
;
424 int alt_cost
= 0, op_cost_add
;
426 if (!TEST_BIT (recog_data
.enabled_alternatives
, alt
))
428 for (i
= 0; i
< recog_data
.n_operands
; i
++)
429 constraints
[i
] = skip_alternative (constraints
[i
]);
434 for (i
= 0; i
< n_ops
; i
++)
437 const char *p
= constraints
[i
];
439 enum machine_mode mode
= modes
[i
];
443 /* Initially show we know nothing about the register class. */
444 classes
[i
] = NO_REGS
;
447 /* If this operand has no constraints at all, we can
448 conclude nothing about it since anything is valid. */
451 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
452 memset (this_op_costs
[i
], 0, struct_costs_size
);
456 /* If this alternative is only relevant when this operand
457 matches a previous operand, we do different things
458 depending on whether this operand is a allocno-reg or not.
459 We must process any modifiers for the operand before we
460 can make this test. */
461 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
464 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
466 /* Copy class and whether memory is allowed from the
467 matching alternative. Then perform any needed cost
468 computations and/or adjustments. */
470 classes
[i
] = classes
[j
];
471 allows_mem
[i
] = allows_mem
[j
];
473 insn_allows_mem
[i
] = 1;
475 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
477 /* If this matches the other operand, we have no
478 added cost and we win. */
479 if (rtx_equal_p (ops
[j
], op
))
481 /* If we can put the other operand into a register,
482 add to the cost of this alternative the cost to
483 copy this operand to the register used for the
485 else if (classes
[j
] != NO_REGS
)
487 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
491 else if (! REG_P (ops
[j
])
492 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
494 /* This op is an allocno but the one it matches is
497 /* If we can't put the other operand into a
498 register, this alternative can't be used. */
500 if (classes
[j
] == NO_REGS
)
502 /* Otherwise, add to the cost of this alternative
503 the cost to copy the other operand to the hard
504 register used for this operand. */
506 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
510 /* The costs of this operand are not the same as the
511 other operand since move costs are not symmetric.
512 Moreover, if we cannot tie them, this alternative
513 needs to do a copy, which is one insn. */
514 struct costs
*pp
= this_op_costs
[i
];
515 int *pp_costs
= pp
->cost
;
516 cost_classes_t cost_classes_ptr
517 = regno_cost_classes
[REGNO (op
)];
518 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
519 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
520 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
521 enum reg_class op_class
= classes
[i
];
523 ira_init_register_move_cost_if_necessary (mode
);
527 if (op_class
== NO_REGS
)
529 mem_cost
= ira_memory_move_cost
[mode
];
530 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
532 rclass
= cost_classes
[k
];
533 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
538 move_out_cost
= ira_may_move_out_cost
[mode
];
539 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
541 rclass
= cost_classes
[k
];
543 = move_out_cost
[op_class
][rclass
] * frequency
;
550 if (op_class
== NO_REGS
)
552 mem_cost
= ira_memory_move_cost
[mode
];
553 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
555 rclass
= cost_classes
[k
];
556 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
561 move_in_cost
= ira_may_move_in_cost
[mode
];
562 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
564 rclass
= cost_classes
[k
];
566 = move_in_cost
[rclass
][op_class
] * frequency
;
572 if (op_class
== NO_REGS
)
574 mem_cost
= ira_memory_move_cost
[mode
];
575 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
577 rclass
= cost_classes
[k
];
578 pp_costs
[k
] = ((mem_cost
[rclass
][0]
579 + mem_cost
[rclass
][1])
585 move_in_cost
= ira_may_move_in_cost
[mode
];
586 move_out_cost
= ira_may_move_out_cost
[mode
];
587 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
589 rclass
= cost_classes
[k
];
590 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
591 + move_out_cost
[op_class
][rclass
])
597 /* If the alternative actually allows memory, make
598 things a bit cheaper since we won't need an extra
601 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
602 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
603 - allows_mem
[i
]) * frequency
;
605 /* If we have assigned a class to this allocno in
606 our first pass, add a cost to this alternative
607 corresponding to what we would add if this
608 allocno were not in the appropriate class. */
611 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
613 if (pref_class
== NO_REGS
)
616 ? ira_memory_move_cost
[mode
][op_class
][0] : 0)
618 ? ira_memory_move_cost
[mode
][op_class
][1]
620 else if (ira_reg_class_intersect
621 [pref_class
][op_class
] == NO_REGS
)
623 += ira_register_move_cost
[mode
][pref_class
][op_class
];
625 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
626 && ! find_reg_note (insn
, REG_DEAD
, op
))
629 /* This is in place of ordinary cost computation for
630 this operand, so skip to the end of the
631 alternative (should be just one character). */
632 while (*p
&& *p
++ != ',')
640 /* Scan all the constraint letters. See if the operand
641 matches any of the constraints. Collect the valid
642 register classes and see if this operand accepts
651 /* Ignore the next letter for this pass. */
657 case '!': case '#': case '&':
658 case '0': case '1': case '2': case '3': case '4':
659 case '5': case '6': case '7': case '8': case '9':
664 win
= address_operand (op
, GET_MODE (op
));
665 /* We know this operand is an address, so we want it
666 to be allocated to a register that can be the
667 base of an address, i.e. BASE_REG_CLASS. */
669 = ira_reg_class_subunion
[classes
[i
]]
670 [base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
674 case 'm': case 'o': case 'V':
675 /* It doesn't seem worth distinguishing between
676 offsettable and non-offsettable addresses
678 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
685 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
686 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
692 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
693 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
699 if (CONST_DOUBLE_AS_FLOAT_P (op
)
700 || (GET_CODE (op
) == CONST_VECTOR
701 && (GET_MODE_CLASS (GET_MODE (op
))
702 == MODE_VECTOR_FLOAT
)))
708 if (CONST_DOUBLE_AS_FLOAT_P (op
)
709 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
714 if (CONST_SCALAR_INT_P (op
))
719 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
724 if (CONST_SCALAR_INT_P (op
))
737 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
748 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
750 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
752 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][GENERAL_REGS
];
756 enum constraint_num cn
= lookup_constraint (p
);
758 switch (get_constraint_type (cn
))
761 cl
= reg_class_for_constraint (cn
);
763 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][cl
];
768 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
773 /* Every MEM can be reloaded to fit. */
774 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
780 /* Every address can be reloaded to fit. */
782 if (address_operand (op
, GET_MODE (op
))
783 || constraint_satisfied_p (op
, cn
))
785 /* We know this operand is an address, so we
786 want it to be allocated to a hard register
787 that can be the base of an address,
788 i.e. BASE_REG_CLASS. */
790 = ira_reg_class_subunion
[classes
[i
]]
791 [base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
796 if (constraint_satisfied_p (op
, cn
))
802 p
+= CONSTRAINT_LEN (c
, p
);
809 /* How we account for this operand now depends on whether it
810 is a pseudo register or not. If it is, we first check if
811 any register classes are valid. If not, we ignore this
812 alternative, since we want to assume that all allocnos get
813 allocated for register preferencing. If some register
814 class is valid, compute the costs of moving the allocno
816 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
818 if (classes
[i
] == NO_REGS
&& ! allows_mem
[i
])
820 /* We must always fail if the operand is a REG, but
821 we did not find a suitable class and memory is
824 Otherwise we may perform an uninitialized read
825 from this_op_costs after the `continue' statement
831 unsigned int regno
= REGNO (op
);
832 struct costs
*pp
= this_op_costs
[i
];
833 int *pp_costs
= pp
->cost
;
834 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
835 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
836 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
837 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
838 enum reg_class op_class
= classes
[i
];
840 ira_init_register_move_cost_if_necessary (mode
);
844 if (op_class
== NO_REGS
)
846 mem_cost
= ira_memory_move_cost
[mode
];
847 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
849 rclass
= cost_classes
[k
];
850 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
855 move_out_cost
= ira_may_move_out_cost
[mode
];
856 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
858 rclass
= cost_classes
[k
];
860 = move_out_cost
[op_class
][rclass
] * frequency
;
867 if (op_class
== NO_REGS
)
869 mem_cost
= ira_memory_move_cost
[mode
];
870 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
872 rclass
= cost_classes
[k
];
873 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
878 move_in_cost
= ira_may_move_in_cost
[mode
];
879 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
881 rclass
= cost_classes
[k
];
883 = move_in_cost
[rclass
][op_class
] * frequency
;
889 if (op_class
== NO_REGS
)
891 mem_cost
= ira_memory_move_cost
[mode
];
892 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
894 rclass
= cost_classes
[k
];
895 pp_costs
[k
] = ((mem_cost
[rclass
][0]
896 + mem_cost
[rclass
][1])
902 move_in_cost
= ira_may_move_in_cost
[mode
];
903 move_out_cost
= ira_may_move_out_cost
[mode
];
904 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
906 rclass
= cost_classes
[k
];
907 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
908 + move_out_cost
[op_class
][rclass
])
914 if (op_class
== NO_REGS
)
915 /* Although we don't need insn to reload from
916 memory, still accessing memory is usually more
917 expensive than a register. */
918 pp
->mem_cost
= frequency
;
920 /* If the alternative actually allows memory, make
921 things a bit cheaper since we won't need an
922 extra insn to load it. */
924 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
925 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
926 - allows_mem
[i
]) * frequency
;
927 /* If we have assigned a class to this allocno in
928 our first pass, add a cost to this alternative
929 corresponding to what we would add if this
930 allocno were not in the appropriate class. */
933 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
935 if (pref_class
== NO_REGS
)
937 if (op_class
!= NO_REGS
)
940 ? ira_memory_move_cost
[mode
][op_class
][0]
943 ? ira_memory_move_cost
[mode
][op_class
][1]
946 else if (op_class
== NO_REGS
)
949 ? ira_memory_move_cost
[mode
][pref_class
][1]
952 ? ira_memory_move_cost
[mode
][pref_class
][0]
954 else if (ira_reg_class_intersect
[pref_class
][op_class
]
956 alt_cost
+= (ira_register_move_cost
957 [mode
][pref_class
][op_class
]);
962 /* Otherwise, if this alternative wins, either because we
963 have already determined that or if we have a hard
964 register of the proper class, there is no cost for this
966 else if (win
|| (REG_P (op
)
967 && reg_fits_class_p (op
, classes
[i
],
971 /* If registers are valid, the cost of this alternative
972 includes copying the object to and/or from a
974 else if (classes
[i
] != NO_REGS
)
976 if (recog_data
.operand_type
[i
] != OP_OUT
)
977 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
979 if (recog_data
.operand_type
[i
] != OP_IN
)
980 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
982 /* The only other way this alternative can be used is if
983 this is a constant that could be placed into memory. */
984 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
985 alt_cost
+= ira_memory_move_cost
[mode
][classes
[i
]][1];
993 op_cost_add
= alt_cost
* frequency
;
994 /* Finally, update the costs with the information we've
995 calculated about this alternative. */
996 for (i
= 0; i
< n_ops
; i
++)
997 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
999 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
1000 int *pp_costs
= pp
->cost
, *qq_costs
= qq
->cost
;
1001 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1002 cost_classes_t cost_classes_ptr
1003 = regno_cost_classes
[REGNO (ops
[i
])];
1005 pp
->mem_cost
= MIN (pp
->mem_cost
,
1006 (qq
->mem_cost
+ op_cost_add
) * scale
);
1008 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1010 = MIN (pp_costs
[k
], (qq_costs
[k
] + op_cost_add
) * scale
);
1015 for (i
= 0; i
< n_ops
; i
++)
1020 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1022 a
= ira_curr_regno_allocno_map
[REGNO (op
)];
1023 if (! ALLOCNO_BAD_SPILL_P (a
) && insn_allows_mem
[i
] == 0)
1024 ALLOCNO_BAD_SPILL_P (a
) = true;
1031 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
1033 ok_for_index_p_nonstrict (rtx reg
)
1035 unsigned regno
= REGNO (reg
);
1037 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
1040 /* A version of regno_ok_for_base_p for use here, when all
1041 pseudo-registers should count as OK. Arguments as for
1042 regno_ok_for_base_p. */
1044 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
1045 enum rtx_code outer_code
, enum rtx_code index_code
)
1047 unsigned regno
= REGNO (reg
);
1049 if (regno
>= FIRST_PSEUDO_REGISTER
)
1051 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
1054 /* Record the pseudo registers we must reload into hard registers in a
1055 subexpression of a memory address, X.
1057 If CONTEXT is 0, we are looking at the base part of an address,
1058 otherwise we are looking at the index part.
1060 MODE and AS are the mode and address space of the memory reference;
1061 OUTER_CODE and INDEX_CODE give the context that the rtx appears in.
1062 These four arguments are passed down to base_reg_class.
1064 SCALE is twice the amount to multiply the cost by (it is twice so
1065 we can represent half-cost adjustments). */
1067 record_address_regs (enum machine_mode mode
, addr_space_t as
, rtx x
,
1068 int context
, enum rtx_code outer_code
,
1069 enum rtx_code index_code
, int scale
)
1071 enum rtx_code code
= GET_CODE (x
);
1072 enum reg_class rclass
;
1075 rclass
= INDEX_REG_CLASS
;
1077 rclass
= base_reg_class (mode
, as
, outer_code
, index_code
);
1090 /* When we have an address that is a sum, we must determine
1091 whether registers are "base" or "index" regs. If there is a
1092 sum of two registers, we must choose one to be the "base".
1093 Luckily, we can use the REG_POINTER to make a good choice
1094 most of the time. We only need to do this on machines that
1095 can have two registers in an address and where the base and
1096 index register classes are different.
1098 ??? This code used to set REGNO_POINTER_FLAG in some cases,
1099 but that seems bogus since it should only be set when we are
1100 sure the register is being used as a pointer. */
1102 rtx arg0
= XEXP (x
, 0);
1103 rtx arg1
= XEXP (x
, 1);
1104 enum rtx_code code0
= GET_CODE (arg0
);
1105 enum rtx_code code1
= GET_CODE (arg1
);
1107 /* Look inside subregs. */
1108 if (code0
== SUBREG
)
1109 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1110 if (code1
== SUBREG
)
1111 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1113 /* If this machine only allows one register per address, it
1114 must be in the first operand. */
1115 if (MAX_REGS_PER_ADDRESS
== 1)
1116 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1118 /* If index and base registers are the same on this machine,
1119 just record registers in any non-constant operands. We
1120 assume here, as well as in the tests below, that all
1121 addresses are in canonical form. */
1122 else if (INDEX_REG_CLASS
1123 == base_reg_class (VOIDmode
, as
, PLUS
, SCRATCH
))
1125 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1126 if (! CONSTANT_P (arg1
))
1127 record_address_regs (mode
, as
, arg1
, context
, PLUS
, code0
, scale
);
1130 /* If the second operand is a constant integer, it doesn't
1131 change what class the first operand must be. */
1132 else if (CONST_SCALAR_INT_P (arg1
))
1133 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1134 /* If the second operand is a symbolic constant, the first
1135 operand must be an index register. */
1136 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1137 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1138 /* If both operands are registers but one is already a hard
1139 register of index or reg-base class, give the other the
1140 class that the hard register is not. */
1141 else if (code0
== REG
&& code1
== REG
1142 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1143 && (ok_for_base_p_nonstrict (arg0
, mode
, as
, PLUS
, REG
)
1144 || ok_for_index_p_nonstrict (arg0
)))
1145 record_address_regs (mode
, as
, arg1
,
1146 ok_for_base_p_nonstrict (arg0
, mode
, as
,
1149 else if (code0
== REG
&& code1
== REG
1150 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1151 && (ok_for_base_p_nonstrict (arg1
, mode
, as
, PLUS
, REG
)
1152 || ok_for_index_p_nonstrict (arg1
)))
1153 record_address_regs (mode
, as
, arg0
,
1154 ok_for_base_p_nonstrict (arg1
, mode
, as
,
1157 /* If one operand is known to be a pointer, it must be the
1158 base with the other operand the index. Likewise if the
1159 other operand is a MULT. */
1160 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
1162 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1163 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
);
1165 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
1167 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1168 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
);
1170 /* Otherwise, count equal chances that each might be a base or
1171 index register. This case should be rare. */
1174 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
/ 2);
1175 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
/ 2);
1176 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
/ 2);
1177 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
/ 2);
1182 /* Double the importance of an allocno that is incremented or
1183 decremented, since it would take two extra insns if it ends
1184 up in the wrong place. */
1187 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
,
1188 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
1189 if (REG_P (XEXP (XEXP (x
, 1), 1)))
1190 record_address_regs (mode
, as
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
1198 /* Double the importance of an allocno that is incremented or
1199 decremented, since it would take two extra insns if it ends
1200 up in the wrong place. */
1201 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
1209 int k
, regno
, add_cost
;
1210 cost_classes_t cost_classes_ptr
;
1211 enum reg_class
*cost_classes
;
1212 move_table
*move_in_cost
;
1214 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1219 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map
[regno
]) = true;
1220 pp
= COSTS (costs
, COST_INDEX (regno
));
1221 add_cost
= (ira_memory_move_cost
[Pmode
][rclass
][1] * scale
) / 2;
1222 if (INT_MAX
- add_cost
< pp
->mem_cost
)
1223 pp
->mem_cost
= INT_MAX
;
1225 pp
->mem_cost
+= add_cost
;
1226 cost_classes_ptr
= regno_cost_classes
[regno
];
1227 cost_classes
= cost_classes_ptr
->classes
;
1228 pp_costs
= pp
->cost
;
1229 ira_init_register_move_cost_if_necessary (Pmode
);
1230 move_in_cost
= ira_may_move_in_cost
[Pmode
];
1231 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1233 i
= cost_classes
[k
];
1234 add_cost
= (move_in_cost
[i
][rclass
] * scale
) / 2;
1235 if (INT_MAX
- add_cost
< pp_costs
[k
])
1236 pp_costs
[k
] = INT_MAX
;
1238 pp_costs
[k
] += add_cost
;
1245 const char *fmt
= GET_RTX_FORMAT (code
);
1247 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1249 record_address_regs (mode
, as
, XEXP (x
, i
), context
, code
, SCRATCH
,
1257 /* Calculate the costs of insn operands. */
1259 record_operand_costs (rtx insn
, enum reg_class
*pref
)
1261 const char *constraints
[MAX_RECOG_OPERANDS
];
1262 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
1263 rtx ops
[MAX_RECOG_OPERANDS
];
1267 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1269 constraints
[i
] = recog_data
.constraints
[i
];
1270 modes
[i
] = recog_data
.operand_mode
[i
];
1273 /* If we get here, we are set up to record the costs of all the
1274 operands for this insn. Start by initializing the costs. Then
1275 handle any address registers. Finally record the desired classes
1276 for any allocnos, doing it twice if some pair of operands are
1278 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1280 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
1282 ops
[i
] = recog_data
.operand
[i
];
1283 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
1284 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
1286 if (MEM_P (recog_data
.operand
[i
]))
1287 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
1288 MEM_ADDR_SPACE (recog_data
.operand
[i
]),
1289 XEXP (recog_data
.operand
[i
], 0),
1290 0, MEM
, SCRATCH
, frequency
* 2);
1291 else if (constraints
[i
][0] == 'p'
1292 || (insn_extra_address_constraint
1293 (lookup_constraint (constraints
[i
]))))
1294 record_address_regs (VOIDmode
, ADDR_SPACE_GENERIC
,
1295 recog_data
.operand
[i
], 0, ADDRESS
, SCRATCH
,
1299 /* Check for commutative in a separate loop so everything will have
1300 been initialized. We must do this even if one operand is a
1301 constant--see addsi3 in m68k.md. */
1302 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1303 if (constraints
[i
][0] == '%')
1305 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1308 /* Handle commutative operands by swapping the constraints.
1309 We assume the modes are the same. */
1310 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1311 xconstraints
[j
] = constraints
[j
];
1313 xconstraints
[i
] = constraints
[i
+1];
1314 xconstraints
[i
+1] = constraints
[i
];
1315 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1316 recog_data
.operand
, modes
,
1317 xconstraints
, insn
, pref
);
1319 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1320 recog_data
.operand
, modes
,
1321 constraints
, insn
, pref
);
1323 /* If this insn is a single set copying operand 1 to operand 0 and
1324 one operand is an allocno with the other a hard reg or an allocno
1325 that prefers a hard register that is in its own register class
1326 then we may want to adjust the cost of that register class to -1.
1328 Avoid the adjustment if the source does not die to avoid
1329 stressing of register allocator by preferrencing two colliding
1330 registers into single class.
1332 Also avoid the adjustment if a copy between hard registers of the
1333 class is expensive (ten times the cost of a default copy is
1334 considered arbitrarily expensive). This avoids losing when the
1335 preferred class is very expensive as the source of a copy
1337 if ((set
= single_set (insn
)) != NULL_RTX
1338 /* In rare cases the single set insn might have less 2 operands
1339 as the source can be a fixed special reg. */
1340 && recog_data
.n_operands
> 1
1341 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
))
1343 int regno
, other_regno
;
1344 rtx dest
= SET_DEST (set
);
1345 rtx src
= SET_SRC (set
);
1347 dest
= SET_DEST (set
);
1348 src
= SET_SRC (set
);
1349 if (GET_CODE (dest
) == SUBREG
1350 && (GET_MODE_SIZE (GET_MODE (dest
))
1351 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))))
1352 dest
= SUBREG_REG (dest
);
1353 if (GET_CODE (src
) == SUBREG
1354 && (GET_MODE_SIZE (GET_MODE (src
))
1355 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
1356 src
= SUBREG_REG (src
);
1357 if (REG_P (src
) && REG_P (dest
)
1358 && find_regno_note (insn
, REG_DEAD
, REGNO (src
))
1359 && (((regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
1360 && (other_regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
)
1361 || ((regno
= REGNO (dest
)) >= FIRST_PSEUDO_REGISTER
1362 && (other_regno
= REGNO (src
)) < FIRST_PSEUDO_REGISTER
)))
1364 enum machine_mode mode
= GET_MODE (src
);
1365 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1366 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1370 i
= regno
== (int) REGNO (src
) ? 1 : 0;
1371 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1373 rclass
= cost_classes
[k
];
1374 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], other_regno
)
1375 && (reg_class_size
[(int) rclass
]
1376 == ira_reg_class_max_nregs
[(int) rclass
][(int) mode
]))
1378 if (reg_class_size
[rclass
] == 1)
1379 op_costs
[i
]->cost
[k
] = -frequency
;
1383 nr
< hard_regno_nregs
[other_regno
][mode
];
1385 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
],
1389 if (nr
== hard_regno_nregs
[other_regno
][mode
])
1390 op_costs
[i
]->cost
[k
] = -frequency
;
1400 /* Process one insn INSN. Scan it and record each time it would save
1401 code to put a certain allocnos in a certain class. Return the last
1402 insn processed, so that the scan can be continued from there. */
1404 scan_one_insn (rtx insn
)
1406 enum rtx_code pat_code
;
1411 if (!NONDEBUG_INSN_P (insn
))
1414 pat_code
= GET_CODE (PATTERN (insn
));
1415 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
)
1418 counted_mem
= false;
1419 set
= single_set (insn
);
1420 extract_insn (insn
);
1422 /* If this insn loads a parameter from its stack slot, then it
1423 represents a savings, rather than a cost, if the parameter is
1424 stored in memory. Record this fact.
1426 Similarly if we're loading other constants from memory (constant
1427 pool, TOC references, small data areas, etc) and this is the only
1428 assignment to the destination pseudo.
1430 Don't do this if SET_SRC (set) isn't a general operand, if it is
1431 a memory requiring special instructions to load it, decreasing
1432 mem_cost might result in it being loaded using the specialized
1433 instruction into a register, then stored into stack and loaded
1434 again from the stack. See PR52208.
1436 Don't do this if SET_SRC (set) has side effect. See PR56124. */
1437 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
1438 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
1439 && ((MEM_P (XEXP (note
, 0))
1440 && !side_effects_p (SET_SRC (set
)))
1441 || (CONSTANT_P (XEXP (note
, 0))
1442 && targetm
.legitimate_constant_p (GET_MODE (SET_DEST (set
)),
1444 && REG_N_SETS (REGNO (SET_DEST (set
))) == 1))
1445 && general_operand (SET_SRC (set
), GET_MODE (SET_SRC (set
))))
1447 enum reg_class cl
= GENERAL_REGS
;
1448 rtx reg
= SET_DEST (set
);
1449 int num
= COST_INDEX (REGNO (reg
));
1451 COSTS (costs
, num
)->mem_cost
1452 -= ira_memory_move_cost
[GET_MODE (reg
)][cl
][1] * frequency
;
1453 record_address_regs (GET_MODE (SET_SRC (set
)),
1454 MEM_ADDR_SPACE (SET_SRC (set
)),
1455 XEXP (SET_SRC (set
), 0), 0, MEM
, SCRATCH
,
1460 record_operand_costs (insn
, pref
);
1462 /* Now add the cost for each operand to the total costs for its
1464 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1465 if (REG_P (recog_data
.operand
[i
])
1466 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1468 int regno
= REGNO (recog_data
.operand
[i
]);
1469 struct costs
*p
= COSTS (costs
, COST_INDEX (regno
));
1470 struct costs
*q
= op_costs
[i
];
1471 int *p_costs
= p
->cost
, *q_costs
= q
->cost
;
1472 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1475 /* If the already accounted for the memory "cost" above, don't
1479 add_cost
= q
->mem_cost
;
1480 if (add_cost
> 0 && INT_MAX
- add_cost
< p
->mem_cost
)
1481 p
->mem_cost
= INT_MAX
;
1483 p
->mem_cost
+= add_cost
;
1485 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1487 add_cost
= q_costs
[k
];
1488 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1489 p_costs
[k
] = INT_MAX
;
1491 p_costs
[k
] += add_cost
;
1500 /* Print allocnos costs to file F. */
1502 print_allocno_costs (FILE *f
)
1506 ira_allocno_iterator ai
;
1508 ira_assert (allocno_p
);
1510 FOR_EACH_ALLOCNO (a
, ai
)
1514 int regno
= ALLOCNO_REGNO (a
);
1515 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1516 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1518 i
= ALLOCNO_NUM (a
);
1519 fprintf (f
, " a%d(r%d,", i
, regno
);
1520 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1521 fprintf (f
, "b%d", bb
->index
);
1523 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1524 fprintf (f
, ") costs:");
1525 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1527 rclass
= cost_classes
[k
];
1528 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1529 #ifdef CANNOT_CHANGE_MODE_CLASS
1530 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
)
1534 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1535 COSTS (costs
, i
)->cost
[k
]);
1536 if (flag_ira_region
== IRA_REGION_ALL
1537 || flag_ira_region
== IRA_REGION_MIXED
)
1538 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->cost
[k
]);
1541 fprintf (f
, " MEM:%i", COSTS (costs
, i
)->mem_cost
);
1542 if (flag_ira_region
== IRA_REGION_ALL
1543 || flag_ira_region
== IRA_REGION_MIXED
)
1544 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->mem_cost
);
1549 /* Print pseudo costs to file F. */
1551 print_pseudo_costs (FILE *f
)
1555 cost_classes_t cost_classes_ptr
;
1556 enum reg_class
*cost_classes
;
1558 ira_assert (! allocno_p
);
1560 for (regno
= max_reg_num () - 1; regno
>= FIRST_PSEUDO_REGISTER
; regno
--)
1562 if (REG_N_REFS (regno
) <= 0)
1564 cost_classes_ptr
= regno_cost_classes
[regno
];
1565 cost_classes
= cost_classes_ptr
->classes
;
1566 fprintf (f
, " r%d costs:", regno
);
1567 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1569 rclass
= cost_classes
[k
];
1570 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1571 #ifdef CANNOT_CHANGE_MODE_CLASS
1572 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
)
1575 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1576 COSTS (costs
, regno
)->cost
[k
]);
1578 fprintf (f
, " MEM:%i\n", COSTS (costs
, regno
)->mem_cost
);
1582 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1585 process_bb_for_costs (basic_block bb
)
1589 frequency
= REG_FREQ_FROM_BB (bb
);
1592 FOR_BB_INSNS (bb
, insn
)
1593 insn
= scan_one_insn (insn
);
1596 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1599 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node
)
1603 bb
= loop_tree_node
->bb
;
1605 process_bb_for_costs (bb
);
1608 /* Find costs of register classes and memory for allocnos or pseudos
1609 and their best costs. Set up preferred, alternative and allocno
1610 classes for pseudos. */
1612 find_costs_and_classes (FILE *dump_file
)
1614 int i
, k
, start
, max_cost_classes_num
;
1617 enum reg_class
*regno_best_class
;
1621 = (enum reg_class
*) ira_allocate (max_reg_num ()
1622 * sizeof (enum reg_class
));
1623 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1624 regno_best_class
[i
] = NO_REGS
;
1625 if (!resize_reg_info () && allocno_p
1626 && pseudo_classes_defined_p
&& flag_expensive_optimizations
)
1629 ira_allocno_iterator ai
;
1632 max_cost_classes_num
= 1;
1633 FOR_EACH_ALLOCNO (a
, ai
)
1635 pref
[ALLOCNO_NUM (a
)] = reg_preferred_class (ALLOCNO_REGNO (a
));
1636 setup_regno_cost_classes_by_aclass
1637 (ALLOCNO_REGNO (a
), pref
[ALLOCNO_NUM (a
)]);
1638 max_cost_classes_num
1639 = MAX (max_cost_classes_num
,
1640 regno_cost_classes
[ALLOCNO_REGNO (a
)]->num
);
1647 max_cost_classes_num
= ira_important_classes_num
;
1648 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1649 if (regno_reg_rtx
[i
] != NULL_RTX
)
1650 setup_regno_cost_classes_by_mode (i
, PSEUDO_REGNO_MODE (i
));
1652 setup_regno_cost_classes_by_aclass (i
, ALL_REGS
);
1656 /* Clear the flag for the next compiled function. */
1657 pseudo_classes_defined_p
= false;
1658 /* Normally we scan the insns once and determine the best class to
1659 use for each allocno. However, if -fexpensive-optimizations are
1660 on, we do so twice, the second time using the tentative best
1661 classes to guide the selection. */
1662 for (pass
= start
; pass
<= flag_expensive_optimizations
; pass
++)
1664 if ((!allocno_p
|| internal_flag_ira_verbose
> 0) && dump_file
)
1666 "\nPass %i for finding pseudo/allocno costs\n\n", pass
);
1670 max_cost_classes_num
= 1;
1671 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1673 setup_regno_cost_classes_by_aclass (i
, regno_best_class
[i
]);
1674 max_cost_classes_num
1675 = MAX (max_cost_classes_num
, regno_cost_classes
[i
]->num
);
1680 = sizeof (struct costs
) + sizeof (int) * (max_cost_classes_num
- 1);
1681 /* Zero out our accumulation of the cost of each class for each
1683 memset (costs
, 0, cost_elements_num
* struct_costs_size
);
1687 /* Scan the instructions and record each time it would save code
1688 to put a certain allocno in a certain class. */
1689 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1690 process_bb_node_for_costs
, NULL
);
1692 memcpy (total_allocno_costs
, costs
,
1693 max_struct_costs_size
* ira_allocnos_num
);
1699 FOR_EACH_BB_FN (bb
, cfun
)
1700 process_bb_for_costs (bb
);
1706 /* Now for each allocno look at how desirable each class is and
1707 find which class is preferred. */
1708 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1710 ira_allocno_t a
, parent_a
;
1711 int rclass
, a_num
, parent_a_num
, add_cost
;
1712 ira_loop_tree_node_t parent
;
1713 int best_cost
, allocno_cost
;
1714 enum reg_class best
, alt_class
;
1715 cost_classes_t cost_classes_ptr
= regno_cost_classes
[i
];
1716 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1717 int *i_costs
= temp_costs
->cost
;
1719 int equiv_savings
= regno_equiv_gains
[i
];
1723 if (regno_reg_rtx
[i
] == NULL_RTX
)
1725 memcpy (temp_costs
, COSTS (costs
, i
), struct_costs_size
);
1726 i_mem_cost
= temp_costs
->mem_cost
;
1730 if (ira_regno_allocno_map
[i
] == NULL
)
1732 memset (temp_costs
, 0, struct_costs_size
);
1734 /* Find cost of all allocnos with the same regno. */
1735 for (a
= ira_regno_allocno_map
[i
];
1737 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1739 int *a_costs
, *p_costs
;
1741 a_num
= ALLOCNO_NUM (a
);
1742 if ((flag_ira_region
== IRA_REGION_ALL
1743 || flag_ira_region
== IRA_REGION_MIXED
)
1744 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1745 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
1746 /* There are no caps yet. */
1747 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
1748 (a
)->border_allocnos
,
1751 /* Propagate costs to upper levels in the region
1753 parent_a_num
= ALLOCNO_NUM (parent_a
);
1754 a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1755 p_costs
= COSTS (total_allocno_costs
, parent_a_num
)->cost
;
1756 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1758 add_cost
= a_costs
[k
];
1759 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1760 p_costs
[k
] = INT_MAX
;
1762 p_costs
[k
] += add_cost
;
1764 add_cost
= COSTS (total_allocno_costs
, a_num
)->mem_cost
;
1766 && (INT_MAX
- add_cost
1767 < COSTS (total_allocno_costs
,
1768 parent_a_num
)->mem_cost
))
1769 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1772 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1775 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1776 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
= 0;
1778 a_costs
= COSTS (costs
, a_num
)->cost
;
1779 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1781 add_cost
= a_costs
[k
];
1782 if (add_cost
> 0 && INT_MAX
- add_cost
< i_costs
[k
])
1783 i_costs
[k
] = INT_MAX
;
1785 i_costs
[k
] += add_cost
;
1787 add_cost
= COSTS (costs
, a_num
)->mem_cost
;
1788 if (add_cost
> 0 && INT_MAX
- add_cost
< i_mem_cost
)
1789 i_mem_cost
= INT_MAX
;
1791 i_mem_cost
+= add_cost
;
1794 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1796 else if (equiv_savings
< 0)
1797 i_mem_cost
= -equiv_savings
;
1798 else if (equiv_savings
> 0)
1801 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1802 i_costs
[k
] += equiv_savings
;
1805 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1807 alt_class
= NO_REGS
;
1808 /* Find best common class for all allocnos with the same
1810 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1812 rclass
= cost_classes
[k
];
1813 /* Ignore classes that are too small or invalid for this
1815 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1816 #ifdef CANNOT_CHANGE_MODE_CLASS
1817 || invalid_mode_change_p (i
, (enum reg_class
) rclass
)
1821 if (i_costs
[k
] < best_cost
)
1823 best_cost
= i_costs
[k
];
1824 best
= (enum reg_class
) rclass
;
1826 else if (i_costs
[k
] == best_cost
)
1827 best
= ira_reg_class_subunion
[best
][rclass
];
1828 if (pass
== flag_expensive_optimizations
1829 /* We still prefer registers to memory even at this
1830 stage if their costs are the same. We will make
1831 a final decision during assigning hard registers
1832 when we have all info including more accurate
1833 costs which might be affected by assigning hard
1834 registers to other pseudos because the pseudos
1835 involved in moves can be coalesced. */
1836 && i_costs
[k
] <= i_mem_cost
1837 && (reg_class_size
[reg_class_subunion
[alt_class
][rclass
]]
1838 > reg_class_size
[alt_class
]))
1839 alt_class
= reg_class_subunion
[alt_class
][rclass
];
1841 alt_class
= ira_allocno_class_translate
[alt_class
];
1842 if (best_cost
> i_mem_cost
)
1843 regno_aclass
[i
] = NO_REGS
;
1846 /* Make the common class the biggest class of best and
1849 = ira_reg_class_superunion
[best
][alt_class
];
1850 ira_assert (regno_aclass
[i
] != NO_REGS
1851 && ira_reg_allocno_class_p
[regno_aclass
[i
]]);
1853 if (pass
== flag_expensive_optimizations
)
1855 if (best_cost
> i_mem_cost
)
1856 best
= alt_class
= NO_REGS
;
1857 else if (best
== alt_class
)
1858 alt_class
= NO_REGS
;
1859 setup_reg_classes (i
, best
, alt_class
, regno_aclass
[i
]);
1860 if ((!allocno_p
|| internal_flag_ira_verbose
> 2)
1861 && dump_file
!= NULL
)
1863 " r%d: preferred %s, alternative %s, allocno %s\n",
1864 i
, reg_class_names
[best
], reg_class_names
[alt_class
],
1865 reg_class_names
[regno_aclass
[i
]]);
1867 regno_best_class
[i
] = best
;
1870 pref
[i
] = best_cost
> i_mem_cost
? NO_REGS
: best
;
1873 for (a
= ira_regno_allocno_map
[i
];
1875 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1877 enum reg_class aclass
= regno_aclass
[i
];
1878 int a_num
= ALLOCNO_NUM (a
);
1879 int *total_a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1880 int *a_costs
= COSTS (costs
, a_num
)->cost
;
1882 if (aclass
== NO_REGS
)
1886 /* Finding best class which is subset of the common
1888 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1889 allocno_cost
= best_cost
;
1891 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1893 rclass
= cost_classes
[k
];
1894 if (! ira_class_subset_p
[rclass
][aclass
])
1896 /* Ignore classes that are too small or invalid
1897 for this operand. */
1898 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1899 #ifdef CANNOT_CHANGE_MODE_CLASS
1900 || invalid_mode_change_p (i
, (enum reg_class
) rclass
)
1904 else if (total_a_costs
[k
] < best_cost
)
1906 best_cost
= total_a_costs
[k
];
1907 allocno_cost
= a_costs
[k
];
1908 best
= (enum reg_class
) rclass
;
1910 else if (total_a_costs
[k
] == best_cost
)
1912 best
= ira_reg_class_subunion
[best
][rclass
];
1913 allocno_cost
= MAX (allocno_cost
, a_costs
[k
]);
1916 ALLOCNO_CLASS_COST (a
) = allocno_cost
;
1918 if (internal_flag_ira_verbose
> 2 && dump_file
!= NULL
1919 && (pass
== 0 || pref
[a_num
] != best
))
1921 fprintf (dump_file
, " a%d (r%d,", a_num
, i
);
1922 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1923 fprintf (dump_file
, "b%d", bb
->index
);
1925 fprintf (dump_file
, "l%d",
1926 ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1927 fprintf (dump_file
, ") best %s, allocno %s\n",
1928 reg_class_names
[best
],
1929 reg_class_names
[aclass
]);
1932 if (pass
== flag_expensive_optimizations
&& best
!= aclass
1933 && ira_class_hard_regs_num
[best
] > 0
1934 && (ira_reg_class_max_nregs
[best
][ALLOCNO_MODE (a
)]
1935 >= ira_class_hard_regs_num
[best
]))
1937 int ind
= cost_classes_ptr
->index
[aclass
];
1939 ira_assert (ind
>= 0);
1940 ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a
));
1941 ira_add_allocno_pref (a
, ira_class_hard_regs
[best
][0],
1942 (a_costs
[ind
] - ALLOCNO_CLASS_COST (a
))
1943 / (ira_register_move_cost
1944 [ALLOCNO_MODE (a
)][best
][aclass
]));
1945 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1946 if (ira_class_subset_p
[cost_classes
[k
]][best
])
1947 a_costs
[k
] = a_costs
[ind
];
1952 if (internal_flag_ira_verbose
> 4 && dump_file
)
1955 print_allocno_costs (dump_file
);
1957 print_pseudo_costs (dump_file
);
1958 fprintf (dump_file
,"\n");
1961 ira_free (regno_best_class
);
1966 /* Process moves involving hard regs to modify allocno hard register
1967 costs. We can do this only after determining allocno class. If a
1968 hard register forms a register class, then moves with the hard
1969 register are already taken into account in class costs for the
1972 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node
)
1974 int i
, freq
, src_regno
, dst_regno
, hard_regno
, a_regno
;
1976 ira_allocno_t a
, curr_a
;
1977 ira_loop_tree_node_t curr_loop_tree_node
;
1978 enum reg_class rclass
;
1980 rtx insn
, set
, src
, dst
;
1982 bb
= loop_tree_node
->bb
;
1985 freq
= REG_FREQ_FROM_BB (bb
);
1988 FOR_BB_INSNS (bb
, insn
)
1990 if (!NONDEBUG_INSN_P (insn
))
1992 set
= single_set (insn
);
1993 if (set
== NULL_RTX
)
1995 dst
= SET_DEST (set
);
1996 src
= SET_SRC (set
);
1997 if (! REG_P (dst
) || ! REG_P (src
))
1999 dst_regno
= REGNO (dst
);
2000 src_regno
= REGNO (src
);
2001 if (dst_regno
>= FIRST_PSEUDO_REGISTER
2002 && src_regno
< FIRST_PSEUDO_REGISTER
)
2004 hard_regno
= src_regno
;
2005 a
= ira_curr_regno_allocno_map
[dst_regno
];
2008 else if (src_regno
>= FIRST_PSEUDO_REGISTER
2009 && dst_regno
< FIRST_PSEUDO_REGISTER
)
2011 hard_regno
= dst_regno
;
2012 a
= ira_curr_regno_allocno_map
[src_regno
];
2017 rclass
= ALLOCNO_CLASS (a
);
2018 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
], hard_regno
))
2020 i
= ira_class_hard_reg_index
[rclass
][hard_regno
];
2023 a_regno
= ALLOCNO_REGNO (a
);
2024 for (curr_loop_tree_node
= ALLOCNO_LOOP_TREE_NODE (a
);
2025 curr_loop_tree_node
!= NULL
;
2026 curr_loop_tree_node
= curr_loop_tree_node
->parent
)
2027 if ((curr_a
= curr_loop_tree_node
->regno_allocno_map
[a_regno
]) != NULL
)
2028 ira_add_allocno_pref (curr_a
, hard_regno
, freq
);
2031 enum reg_class hard_reg_class
;
2032 enum machine_mode mode
;
2034 mode
= ALLOCNO_MODE (a
);
2035 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
2036 ira_init_register_move_cost_if_necessary (mode
);
2037 cost
= (to_p
? ira_register_move_cost
[mode
][hard_reg_class
][rclass
]
2038 : ira_register_move_cost
[mode
][rclass
][hard_reg_class
]) * freq
;
2039 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), rclass
,
2040 ALLOCNO_CLASS_COST (a
));
2041 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
2043 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
2044 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
2045 ALLOCNO_CLASS_COST (a
) = MIN (ALLOCNO_CLASS_COST (a
),
2046 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
2051 /* After we find hard register and memory costs for allocnos, define
2052 its class and modify hard register cost because insns moving
2053 allocno to/from hard registers. */
2055 setup_allocno_class_and_costs (void)
2057 int i
, j
, n
, regno
, hard_regno
, num
;
2059 enum reg_class aclass
, rclass
;
2061 ira_allocno_iterator ai
;
2062 cost_classes_t cost_classes_ptr
;
2064 ira_assert (allocno_p
);
2065 FOR_EACH_ALLOCNO (a
, ai
)
2067 i
= ALLOCNO_NUM (a
);
2068 regno
= ALLOCNO_REGNO (a
);
2069 aclass
= regno_aclass
[regno
];
2070 cost_classes_ptr
= regno_cost_classes
[regno
];
2071 ira_assert (pref
[i
] == NO_REGS
|| aclass
!= NO_REGS
);
2072 ALLOCNO_MEMORY_COST (a
) = COSTS (costs
, i
)->mem_cost
;
2073 ira_set_allocno_class (a
, aclass
);
2074 if (aclass
== NO_REGS
)
2076 if (optimize
&& ALLOCNO_CLASS (a
) != pref
[i
])
2078 n
= ira_class_hard_regs_num
[aclass
];
2079 ALLOCNO_HARD_REG_COSTS (a
)
2080 = reg_costs
= ira_allocate_cost_vector (aclass
);
2081 for (j
= n
- 1; j
>= 0; j
--)
2083 hard_regno
= ira_class_hard_regs
[aclass
][j
];
2084 if (TEST_HARD_REG_BIT (reg_class_contents
[pref
[i
]], hard_regno
))
2085 reg_costs
[j
] = ALLOCNO_CLASS_COST (a
);
2088 rclass
= REGNO_REG_CLASS (hard_regno
);
2089 num
= cost_classes_ptr
->index
[rclass
];
2092 num
= cost_classes_ptr
->hard_regno_index
[hard_regno
];
2093 ira_assert (num
>= 0);
2095 reg_costs
[j
] = COSTS (costs
, i
)->cost
[num
];
2101 ira_traverse_loop_tree (true, ira_loop_tree_root
,
2102 process_bb_node_for_hard_reg_moves
, NULL
);
2107 /* Function called once during compiler work. */
2109 ira_init_costs_once (void)
2114 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2117 this_op_costs
[i
] = NULL
;
2122 /* Free allocated temporary cost vectors. */
2124 free_ira_costs (void)
2130 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2133 free (this_op_costs
[i
]);
2134 op_costs
[i
] = this_op_costs
[i
] = NULL
;
2140 /* This is called each time register related information is
2143 ira_init_costs (void)
2148 max_struct_costs_size
2149 = sizeof (struct costs
) + sizeof (int) * (ira_important_classes_num
- 1);
2150 /* Don't use ira_allocate because vectors live through several IRA
2152 init_cost
= (struct costs
*) xmalloc (max_struct_costs_size
);
2153 init_cost
->mem_cost
= 1000000;
2154 for (i
= 0; i
< ira_important_classes_num
; i
++)
2155 init_cost
->cost
[i
] = 1000000;
2156 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2158 op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2159 this_op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2161 temp_costs
= (struct costs
*) xmalloc (max_struct_costs_size
);
2164 /* Function called once at the end of compiler work. */
2166 ira_finish_costs_once (void)
2173 /* Common initialization function for ira_costs and
2174 ira_set_pseudo_classes. */
2178 init_subregs_of_mode ();
2179 costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2180 * cost_elements_num
);
2181 pref_buffer
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2182 * cost_elements_num
);
2183 regno_aclass
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2185 regno_equiv_gains
= (int *) ira_allocate (sizeof (int) * max_reg_num ());
2186 memset (regno_equiv_gains
, 0, sizeof (int) * max_reg_num ());
2189 /* Common finalization function for ira_costs and
2190 ira_set_pseudo_classes. */
2194 finish_subregs_of_mode ();
2195 ira_free (regno_equiv_gains
);
2196 ira_free (regno_aclass
);
2197 ira_free (pref_buffer
);
2201 /* Entry function which defines register class, memory and hard
2202 register costs for each allocno. */
2207 cost_elements_num
= ira_allocnos_num
;
2209 total_allocno_costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2210 * ira_allocnos_num
);
2211 initiate_regno_cost_classes ();
2212 calculate_elim_costs_all_insns ();
2213 find_costs_and_classes (ira_dump_file
);
2214 setup_allocno_class_and_costs ();
2215 finish_regno_cost_classes ();
2217 ira_free (total_allocno_costs
);
2220 /* Entry function which defines classes for pseudos.
2221 Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */
2223 ira_set_pseudo_classes (bool define_pseudo_classes
, FILE *dump_file
)
2226 internal_flag_ira_verbose
= flag_ira_verbose
;
2227 cost_elements_num
= max_reg_num ();
2229 initiate_regno_cost_classes ();
2230 find_costs_and_classes (dump_file
);
2231 finish_regno_cost_classes ();
2232 if (define_pseudo_classes
)
2233 pseudo_classes_defined_p
= true;
2240 /* Change hard register costs for allocnos which lives through
2241 function calls. This is called only when we found all intersected
2242 calls during building allocno live ranges. */
2244 ira_tune_allocno_costs (void)
2247 int cost
, min_cost
, *reg_costs
;
2248 enum reg_class aclass
, rclass
;
2249 enum machine_mode mode
;
2251 ira_allocno_iterator ai
;
2252 ira_allocno_object_iterator oi
;
2255 HARD_REG_SET
*crossed_calls_clobber_regs
;
2257 FOR_EACH_ALLOCNO (a
, ai
)
2259 aclass
= ALLOCNO_CLASS (a
);
2260 if (aclass
== NO_REGS
)
2262 mode
= ALLOCNO_MODE (a
);
2263 n
= ira_class_hard_regs_num
[aclass
];
2265 if (ALLOCNO_CALLS_CROSSED_NUM (a
)
2266 != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2268 ira_allocate_and_set_costs
2269 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
,
2270 ALLOCNO_CLASS_COST (a
));
2271 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2272 for (j
= n
- 1; j
>= 0; j
--)
2274 regno
= ira_class_hard_regs
[aclass
][j
];
2276 FOR_EACH_ALLOCNO_OBJECT (a
, obj
, oi
)
2278 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2279 OBJECT_CONFLICT_HARD_REGS
2288 rclass
= REGNO_REG_CLASS (regno
);
2290 crossed_calls_clobber_regs
2291 = &(ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
));
2292 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2293 *crossed_calls_clobber_regs
))
2295 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2297 || HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
))
2298 cost
+= (ALLOCNO_CALL_FREQ (a
)
2299 * (ira_memory_move_cost
[mode
][rclass
][0]
2300 + ira_memory_move_cost
[mode
][rclass
][1]));
2301 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
2302 cost
+= ((ira_memory_move_cost
[mode
][rclass
][0]
2303 + ira_memory_move_cost
[mode
][rclass
][1])
2305 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
2308 if (INT_MAX
- cost
< reg_costs
[j
])
2309 reg_costs
[j
] = INT_MAX
;
2311 reg_costs
[j
] += cost
;
2312 if (min_cost
> reg_costs
[j
])
2313 min_cost
= reg_costs
[j
];
2316 if (min_cost
!= INT_MAX
)
2317 ALLOCNO_CLASS_COST (a
) = min_cost
;
2319 /* Some targets allow pseudos to be allocated to unaligned sequences
2320 of hard registers. However, selecting an unaligned sequence can
2321 unnecessarily restrict later allocations. So increase the cost of
2322 unaligned hard regs to encourage the use of aligned hard regs. */
2324 const int nregs
= ira_reg_class_max_nregs
[aclass
][ALLOCNO_MODE (a
)];
2328 ira_allocate_and_set_costs
2329 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
, ALLOCNO_CLASS_COST (a
));
2330 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2331 for (j
= n
- 1; j
>= 0; j
--)
2333 regno
= ira_non_ordered_class_hard_regs
[aclass
][j
];
2334 if ((regno
% nregs
) != 0)
2336 int index
= ira_class_hard_reg_index
[aclass
][regno
];
2337 ira_assert (index
!= -1);
2338 reg_costs
[index
] += ALLOCNO_FREQ (a
);
2346 /* Add COST to the estimated gain for eliminating REGNO with its
2347 equivalence. If COST is zero, record that no such elimination is
2351 ira_adjust_equiv_reg_cost (unsigned regno
, int cost
)
2354 regno_equiv_gains
[regno
] = 0;
2356 regno_equiv_gains
[regno
] += cost
;