usage.adb: Change "pragma inline" to "pragma Inline" in information and error messages
[gcc.git] / gcc / local-alloc.c
1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
29
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
32
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
40
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
47
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
51
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
56 yet implemented. */
57
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
61
62 #include "config.h"
63 #include "system.h"
64 #include "coretypes.h"
65 #include "tm.h"
66 #include "hard-reg-set.h"
67 #include "rtl.h"
68 #include "tm_p.h"
69 #include "flags.h"
70 #include "basic-block.h"
71 #include "regs.h"
72 #include "function.h"
73 #include "insn-config.h"
74 #include "insn-attr.h"
75 #include "recog.h"
76 #include "output.h"
77 #include "toplev.h"
78 #include "except.h"
79 #include "integrate.h"
80 \f
81 /* Next quantity number available for allocation. */
82
83 static int next_qty;
84
85 /* Information we maintain about each quantity. */
86 struct qty
87 {
88 /* The number of refs to quantity Q. */
89
90 int n_refs;
91
92 /* The frequency of uses of quantity Q. */
93
94 int freq;
95
96 /* Insn number (counting from head of basic block)
97 where quantity Q was born. -1 if birth has not been recorded. */
98
99 int birth;
100
101 /* Insn number (counting from head of basic block)
102 where given quantity died. Due to the way tying is done,
103 and the fact that we consider in this pass only regs that die but once,
104 a quantity can die only once. Each quantity's life span
105 is a set of consecutive insns. -1 if death has not been recorded. */
106
107 int death;
108
109 /* Number of words needed to hold the data in given quantity.
110 This depends on its machine mode. It is used for these purposes:
111 1. It is used in computing the relative importance of qtys,
112 which determines the order in which we look for regs for them.
113 2. It is used in rules that prevent tying several registers of
114 different sizes in a way that is geometrically impossible
115 (see combine_regs). */
116
117 int size;
118
119 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
120
121 int n_calls_crossed;
122
123 /* The register number of one pseudo register whose reg_qty value is Q.
124 This register should be the head of the chain
125 maintained in reg_next_in_qty. */
126
127 int first_reg;
128
129 /* Reg class contained in (smaller than) the preferred classes of all
130 the pseudo regs that are tied in given quantity.
131 This is the preferred class for allocating that quantity. */
132
133 enum reg_class min_class;
134
135 /* Register class within which we allocate given qty if we can't get
136 its preferred class. */
137
138 enum reg_class alternate_class;
139
140 /* This holds the mode of the registers that are tied to given qty,
141 or VOIDmode if registers with differing modes are tied together. */
142
143 enum machine_mode mode;
144
145 /* the hard reg number chosen for given quantity,
146 or -1 if none was found. */
147
148 short phys_reg;
149 };
150
151 static struct qty *qty;
152
153 /* These fields are kept separately to speedup their clearing. */
154
155 /* We maintain two hard register sets that indicate suggested hard registers
156 for each quantity. The first, phys_copy_sugg, contains hard registers
157 that are tied to the quantity by a simple copy. The second contains all
158 hard registers that are tied to the quantity via an arithmetic operation.
159
160 The former register set is given priority for allocation. This tends to
161 eliminate copy insns. */
162
163 /* Element Q is a set of hard registers that are suggested for quantity Q by
164 copy insns. */
165
166 static HARD_REG_SET *qty_phys_copy_sugg;
167
168 /* Element Q is a set of hard registers that are suggested for quantity Q by
169 arithmetic insns. */
170
171 static HARD_REG_SET *qty_phys_sugg;
172
173 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
174
175 static short *qty_phys_num_copy_sugg;
176
177 /* Element Q is the number of suggested registers in qty_phys_sugg. */
178
179 static short *qty_phys_num_sugg;
180
181 /* If (REG N) has been assigned a quantity number, is a register number
182 of another register assigned the same quantity number, or -1 for the
183 end of the chain. qty->first_reg point to the head of this chain. */
184
185 static int *reg_next_in_qty;
186
187 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
188 if it is >= 0,
189 of -1 if this register cannot be allocated by local-alloc,
190 or -2 if not known yet.
191
192 Note that if we see a use or death of pseudo register N with
193 reg_qty[N] == -2, register N must be local to the current block. If
194 it were used in more than one block, we would have reg_qty[N] == -1.
195 This relies on the fact that if reg_basic_block[N] is >= 0, register N
196 will not appear in any other block. We save a considerable number of
197 tests by exploiting this.
198
199 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
200 be referenced. */
201
202 static int *reg_qty;
203
204 /* The offset (in words) of register N within its quantity.
205 This can be nonzero if register N is SImode, and has been tied
206 to a subreg of a DImode register. */
207
208 static char *reg_offset;
209
210 /* Vector of substitutions of register numbers,
211 used to map pseudo regs into hardware regs.
212 This is set up as a result of register allocation.
213 Element N is the hard reg assigned to pseudo reg N,
214 or is -1 if no hard reg was assigned.
215 If N is a hard reg number, element N is N. */
216
217 short *reg_renumber;
218
219 /* Set of hard registers live at the current point in the scan
220 of the instructions in a basic block. */
221
222 static HARD_REG_SET regs_live;
223
224 /* Each set of hard registers indicates registers live at a particular
225 point in the basic block. For N even, regs_live_at[N] says which
226 hard registers are needed *after* insn N/2 (i.e., they may not
227 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
228
229 If an object is to conflict with the inputs of insn J but not the
230 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
231 if it is to conflict with the outputs of insn J but not the inputs of
232 insn J + 1, it is said to die at index J*2 + 1. */
233
234 static HARD_REG_SET *regs_live_at;
235
236 /* Communicate local vars `insn_number' and `insn'
237 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
238 static int this_insn_number;
239 static rtx this_insn;
240
241 struct equivalence
242 {
243 /* Set when an attempt should be made to replace a register
244 with the associated src_p entry. */
245
246 char replace;
247
248 /* Set when a REG_EQUIV note is found or created. Use to
249 keep track of what memory accesses might be created later,
250 e.g. by reload. */
251
252 rtx replacement;
253
254 rtx *src_p;
255
256 /* Loop depth is used to recognize equivalences which appear
257 to be present within the same loop (or in an inner loop). */
258
259 int loop_depth;
260
261 /* The list of each instruction which initializes this register. */
262
263 rtx init_insns;
264 };
265
266 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
267 structure for that register. */
268
269 static struct equivalence *reg_equiv;
270
271 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
272 static int recorded_label_ref;
273
274 static void alloc_qty (int, enum machine_mode, int, int);
275 static void validate_equiv_mem_from_store (rtx, rtx, void *);
276 static int validate_equiv_mem (rtx, rtx, rtx);
277 static int equiv_init_varies_p (rtx);
278 static int equiv_init_movable_p (rtx, int);
279 static int contains_replace_regs (rtx);
280 static int memref_referenced_p (rtx, rtx);
281 static int memref_used_between_p (rtx, rtx, rtx);
282 static void update_equiv_regs (void);
283 static void no_equiv (rtx, rtx, void *);
284 static void block_alloc (int);
285 static int qty_sugg_compare (int, int);
286 static int qty_sugg_compare_1 (const void *, const void *);
287 static int qty_compare (int, int);
288 static int qty_compare_1 (const void *, const void *);
289 static int combine_regs (rtx, rtx, int, int, rtx, int);
290 static int reg_meets_class_p (int, enum reg_class);
291 static void update_qty_class (int, int);
292 static void reg_is_set (rtx, rtx, void *);
293 static void reg_is_born (rtx, int);
294 static void wipe_dead_reg (rtx, int);
295 static int find_free_reg (enum reg_class, enum machine_mode, int, int, int,
296 int, int);
297 static void mark_life (int, enum machine_mode, int);
298 static void post_mark_life (int, enum machine_mode, int, int, int);
299 static int no_conflict_p (rtx, rtx, rtx);
300 static int requires_inout (const char *);
301 \f
302 /* Allocate a new quantity (new within current basic block)
303 for register number REGNO which is born at index BIRTH
304 within the block. MODE and SIZE are info on reg REGNO. */
305
306 static void
307 alloc_qty (int regno, enum machine_mode mode, int size, int birth)
308 {
309 int qtyno = next_qty++;
310
311 reg_qty[regno] = qtyno;
312 reg_offset[regno] = 0;
313 reg_next_in_qty[regno] = -1;
314
315 qty[qtyno].first_reg = regno;
316 qty[qtyno].size = size;
317 qty[qtyno].mode = mode;
318 qty[qtyno].birth = birth;
319 qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno);
320 qty[qtyno].min_class = reg_preferred_class (regno);
321 qty[qtyno].alternate_class = reg_alternate_class (regno);
322 qty[qtyno].n_refs = REG_N_REFS (regno);
323 qty[qtyno].freq = REG_FREQ (regno);
324 }
325 \f
326 /* Main entry point of this file. */
327
328 int
329 local_alloc (void)
330 {
331 int i;
332 int max_qty;
333 basic_block b;
334
335 /* We need to keep track of whether or not we recorded a LABEL_REF so
336 that we know if the jump optimizer needs to be rerun. */
337 recorded_label_ref = 0;
338
339 /* Leaf functions and non-leaf functions have different needs.
340 If defined, let the machine say what kind of ordering we
341 should use. */
342 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
343 ORDER_REGS_FOR_LOCAL_ALLOC;
344 #endif
345
346 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
347 registers. */
348 if (optimize)
349 update_equiv_regs ();
350
351 /* This sets the maximum number of quantities we can have. Quantity
352 numbers start at zero and we can have one for each pseudo. */
353 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
354
355 /* Allocate vectors of temporary data.
356 See the declarations of these variables, above,
357 for what they mean. */
358
359 qty = xmalloc (max_qty * sizeof (struct qty));
360 qty_phys_copy_sugg = xmalloc (max_qty * sizeof (HARD_REG_SET));
361 qty_phys_num_copy_sugg = xmalloc (max_qty * sizeof (short));
362 qty_phys_sugg = xmalloc (max_qty * sizeof (HARD_REG_SET));
363 qty_phys_num_sugg = xmalloc (max_qty * sizeof (short));
364
365 reg_qty = xmalloc (max_regno * sizeof (int));
366 reg_offset = xmalloc (max_regno * sizeof (char));
367 reg_next_in_qty = xmalloc (max_regno * sizeof (int));
368
369 /* Determine which pseudo-registers can be allocated by local-alloc.
370 In general, these are the registers used only in a single block and
371 which only die once.
372
373 We need not be concerned with which block actually uses the register
374 since we will never see it outside that block. */
375
376 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
377 {
378 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1)
379 reg_qty[i] = -2;
380 else
381 reg_qty[i] = -1;
382 }
383
384 /* Force loop below to initialize entire quantity array. */
385 next_qty = max_qty;
386
387 /* Allocate each block's local registers, block by block. */
388
389 FOR_EACH_BB (b)
390 {
391 /* NEXT_QTY indicates which elements of the `qty_...'
392 vectors might need to be initialized because they were used
393 for the previous block; it is set to the entire array before
394 block 0. Initialize those, with explicit loop if there are few,
395 else with bzero and bcopy. Do not initialize vectors that are
396 explicit set by `alloc_qty'. */
397
398 if (next_qty < 6)
399 {
400 for (i = 0; i < next_qty; i++)
401 {
402 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
403 qty_phys_num_copy_sugg[i] = 0;
404 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
405 qty_phys_num_sugg[i] = 0;
406 }
407 }
408 else
409 {
410 #define CLEAR(vector) \
411 memset ((vector), 0, (sizeof (*(vector))) * next_qty);
412
413 CLEAR (qty_phys_copy_sugg);
414 CLEAR (qty_phys_num_copy_sugg);
415 CLEAR (qty_phys_sugg);
416 CLEAR (qty_phys_num_sugg);
417 }
418
419 next_qty = 0;
420
421 block_alloc (b->index);
422 }
423
424 free (qty);
425 free (qty_phys_copy_sugg);
426 free (qty_phys_num_copy_sugg);
427 free (qty_phys_sugg);
428 free (qty_phys_num_sugg);
429
430 free (reg_qty);
431 free (reg_offset);
432 free (reg_next_in_qty);
433
434 return recorded_label_ref;
435 }
436 \f
437 /* Used for communication between the following two functions: contains
438 a MEM that we wish to ensure remains unchanged. */
439 static rtx equiv_mem;
440
441 /* Set nonzero if EQUIV_MEM is modified. */
442 static int equiv_mem_modified;
443
444 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
445 Called via note_stores. */
446
447 static void
448 validate_equiv_mem_from_store (rtx dest, rtx set ATTRIBUTE_UNUSED,
449 void *data ATTRIBUTE_UNUSED)
450 {
451 if ((REG_P (dest)
452 && reg_overlap_mentioned_p (dest, equiv_mem))
453 || (MEM_P (dest)
454 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
455 equiv_mem_modified = 1;
456 }
457
458 /* Verify that no store between START and the death of REG invalidates
459 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
460 by storing into an overlapping memory location, or with a non-const
461 CALL_INSN.
462
463 Return 1 if MEMREF remains valid. */
464
465 static int
466 validate_equiv_mem (rtx start, rtx reg, rtx memref)
467 {
468 rtx insn;
469 rtx note;
470
471 equiv_mem = memref;
472 equiv_mem_modified = 0;
473
474 /* If the memory reference has side effects or is volatile, it isn't a
475 valid equivalence. */
476 if (side_effects_p (memref))
477 return 0;
478
479 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
480 {
481 if (! INSN_P (insn))
482 continue;
483
484 if (find_reg_note (insn, REG_DEAD, reg))
485 return 1;
486
487 if (CALL_P (insn) && ! MEM_READONLY_P (memref)
488 && ! CONST_OR_PURE_CALL_P (insn))
489 return 0;
490
491 note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
492
493 /* If a register mentioned in MEMREF is modified via an
494 auto-increment, we lose the equivalence. Do the same if one
495 dies; although we could extend the life, it doesn't seem worth
496 the trouble. */
497
498 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
499 if ((REG_NOTE_KIND (note) == REG_INC
500 || REG_NOTE_KIND (note) == REG_DEAD)
501 && REG_P (XEXP (note, 0))
502 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
503 return 0;
504 }
505
506 return 0;
507 }
508
509 /* Returns zero if X is known to be invariant. */
510
511 static int
512 equiv_init_varies_p (rtx x)
513 {
514 RTX_CODE code = GET_CODE (x);
515 int i;
516 const char *fmt;
517
518 switch (code)
519 {
520 case MEM:
521 return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0));
522
523 case CONST:
524 case CONST_INT:
525 case CONST_DOUBLE:
526 case CONST_VECTOR:
527 case SYMBOL_REF:
528 case LABEL_REF:
529 return 0;
530
531 case REG:
532 return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0);
533
534 case ASM_OPERANDS:
535 if (MEM_VOLATILE_P (x))
536 return 1;
537
538 /* Fall through. */
539
540 default:
541 break;
542 }
543
544 fmt = GET_RTX_FORMAT (code);
545 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
546 if (fmt[i] == 'e')
547 {
548 if (equiv_init_varies_p (XEXP (x, i)))
549 return 1;
550 }
551 else if (fmt[i] == 'E')
552 {
553 int j;
554 for (j = 0; j < XVECLEN (x, i); j++)
555 if (equiv_init_varies_p (XVECEXP (x, i, j)))
556 return 1;
557 }
558
559 return 0;
560 }
561
562 /* Returns nonzero if X (used to initialize register REGNO) is movable.
563 X is only movable if the registers it uses have equivalent initializations
564 which appear to be within the same loop (or in an inner loop) and movable
565 or if they are not candidates for local_alloc and don't vary. */
566
567 static int
568 equiv_init_movable_p (rtx x, int regno)
569 {
570 int i, j;
571 const char *fmt;
572 enum rtx_code code = GET_CODE (x);
573
574 switch (code)
575 {
576 case SET:
577 return equiv_init_movable_p (SET_SRC (x), regno);
578
579 case CC0:
580 case CLOBBER:
581 return 0;
582
583 case PRE_INC:
584 case PRE_DEC:
585 case POST_INC:
586 case POST_DEC:
587 case PRE_MODIFY:
588 case POST_MODIFY:
589 return 0;
590
591 case REG:
592 return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
593 && reg_equiv[REGNO (x)].replace)
594 || (REG_BASIC_BLOCK (REGNO (x)) < 0 && ! rtx_varies_p (x, 0));
595
596 case UNSPEC_VOLATILE:
597 return 0;
598
599 case ASM_OPERANDS:
600 if (MEM_VOLATILE_P (x))
601 return 0;
602
603 /* Fall through. */
604
605 default:
606 break;
607 }
608
609 fmt = GET_RTX_FORMAT (code);
610 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
611 switch (fmt[i])
612 {
613 case 'e':
614 if (! equiv_init_movable_p (XEXP (x, i), regno))
615 return 0;
616 break;
617 case 'E':
618 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
619 if (! equiv_init_movable_p (XVECEXP (x, i, j), regno))
620 return 0;
621 break;
622 }
623
624 return 1;
625 }
626
627 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
628
629 static int
630 contains_replace_regs (rtx x)
631 {
632 int i, j;
633 const char *fmt;
634 enum rtx_code code = GET_CODE (x);
635
636 switch (code)
637 {
638 case CONST_INT:
639 case CONST:
640 case LABEL_REF:
641 case SYMBOL_REF:
642 case CONST_DOUBLE:
643 case CONST_VECTOR:
644 case PC:
645 case CC0:
646 case HIGH:
647 return 0;
648
649 case REG:
650 return reg_equiv[REGNO (x)].replace;
651
652 default:
653 break;
654 }
655
656 fmt = GET_RTX_FORMAT (code);
657 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
658 switch (fmt[i])
659 {
660 case 'e':
661 if (contains_replace_regs (XEXP (x, i)))
662 return 1;
663 break;
664 case 'E':
665 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
666 if (contains_replace_regs (XVECEXP (x, i, j)))
667 return 1;
668 break;
669 }
670
671 return 0;
672 }
673 \f
674 /* TRUE if X references a memory location that would be affected by a store
675 to MEMREF. */
676
677 static int
678 memref_referenced_p (rtx memref, rtx x)
679 {
680 int i, j;
681 const char *fmt;
682 enum rtx_code code = GET_CODE (x);
683
684 switch (code)
685 {
686 case CONST_INT:
687 case CONST:
688 case LABEL_REF:
689 case SYMBOL_REF:
690 case CONST_DOUBLE:
691 case CONST_VECTOR:
692 case PC:
693 case CC0:
694 case HIGH:
695 case LO_SUM:
696 return 0;
697
698 case REG:
699 return (reg_equiv[REGNO (x)].replacement
700 && memref_referenced_p (memref,
701 reg_equiv[REGNO (x)].replacement));
702
703 case MEM:
704 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
705 return 1;
706 break;
707
708 case SET:
709 /* If we are setting a MEM, it doesn't count (its address does), but any
710 other SET_DEST that has a MEM in it is referencing the MEM. */
711 if (MEM_P (SET_DEST (x)))
712 {
713 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
714 return 1;
715 }
716 else if (memref_referenced_p (memref, SET_DEST (x)))
717 return 1;
718
719 return memref_referenced_p (memref, SET_SRC (x));
720
721 default:
722 break;
723 }
724
725 fmt = GET_RTX_FORMAT (code);
726 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
727 switch (fmt[i])
728 {
729 case 'e':
730 if (memref_referenced_p (memref, XEXP (x, i)))
731 return 1;
732 break;
733 case 'E':
734 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
735 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
736 return 1;
737 break;
738 }
739
740 return 0;
741 }
742
743 /* TRUE if some insn in the range (START, END] references a memory location
744 that would be affected by a store to MEMREF. */
745
746 static int
747 memref_used_between_p (rtx memref, rtx start, rtx end)
748 {
749 rtx insn;
750
751 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
752 insn = NEXT_INSN (insn))
753 if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn)))
754 return 1;
755
756 return 0;
757 }
758 \f
759 /* Find registers that are equivalent to a single value throughout the
760 compilation (either because they can be referenced in memory or are set once
761 from a single constant). Lower their priority for a register.
762
763 If such a register is only referenced once, try substituting its value
764 into the using insn. If it succeeds, we can eliminate the register
765 completely. */
766
767 static void
768 update_equiv_regs (void)
769 {
770 rtx insn;
771 basic_block bb;
772 int loop_depth;
773 regset_head cleared_regs;
774 int clear_regnos = 0;
775
776 reg_equiv = xcalloc (max_regno, sizeof *reg_equiv);
777 INIT_REG_SET (&cleared_regs);
778
779 init_alias_analysis ();
780
781 /* Scan the insns and find which registers have equivalences. Do this
782 in a separate scan of the insns because (due to -fcse-follow-jumps)
783 a register can be set below its use. */
784 FOR_EACH_BB (bb)
785 {
786 loop_depth = bb->loop_depth;
787
788 for (insn = BB_HEAD (bb);
789 insn != NEXT_INSN (BB_END (bb));
790 insn = NEXT_INSN (insn))
791 {
792 rtx note;
793 rtx set;
794 rtx dest, src;
795 int regno;
796
797 if (! INSN_P (insn))
798 continue;
799
800 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
801 if (REG_NOTE_KIND (note) == REG_INC)
802 no_equiv (XEXP (note, 0), note, NULL);
803
804 set = single_set (insn);
805
806 /* If this insn contains more (or less) than a single SET,
807 only mark all destinations as having no known equivalence. */
808 if (set == 0)
809 {
810 note_stores (PATTERN (insn), no_equiv, NULL);
811 continue;
812 }
813 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
814 {
815 int i;
816
817 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
818 {
819 rtx part = XVECEXP (PATTERN (insn), 0, i);
820 if (part != set)
821 note_stores (part, no_equiv, NULL);
822 }
823 }
824
825 dest = SET_DEST (set);
826 src = SET_SRC (set);
827
828 /* If this sets a MEM to the contents of a REG that is only used
829 in a single basic block, see if the register is always equivalent
830 to that memory location and if moving the store from INSN to the
831 insn that set REG is safe. If so, put a REG_EQUIV note on the
832 initializing insn.
833
834 Don't add a REG_EQUIV note if the insn already has one. The existing
835 REG_EQUIV is likely more useful than the one we are adding.
836
837 If one of the regs in the address has reg_equiv[REGNO].replace set,
838 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
839 optimization may move the set of this register immediately before
840 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
841 the mention in the REG_EQUIV note would be to an uninitialized
842 pseudo. */
843 /* ????? This test isn't good enough; we might see a MEM with a use of
844 a pseudo register before we see its setting insn that will cause
845 reg_equiv[].replace for that pseudo to be set.
846 Equivalences to MEMs should be made in another pass, after the
847 reg_equiv[].replace information has been gathered. */
848
849 if (MEM_P (dest) && REG_P (src)
850 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
851 && REG_BASIC_BLOCK (regno) >= 0
852 && REG_N_SETS (regno) == 1
853 && reg_equiv[regno].init_insns != 0
854 && reg_equiv[regno].init_insns != const0_rtx
855 && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0),
856 REG_EQUIV, NULL_RTX)
857 && ! contains_replace_regs (XEXP (dest, 0)))
858 {
859 rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0);
860 if (validate_equiv_mem (init_insn, src, dest)
861 && ! memref_used_between_p (dest, init_insn, insn))
862 REG_NOTES (init_insn)
863 = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn));
864 }
865
866 /* We only handle the case of a pseudo register being set
867 once, or always to the same value. */
868 /* ??? The mn10200 port breaks if we add equivalences for
869 values that need an ADDRESS_REGS register and set them equivalent
870 to a MEM of a pseudo. The actual problem is in the over-conservative
871 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
872 calculate_needs, but we traditionally work around this problem
873 here by rejecting equivalences when the destination is in a register
874 that's likely spilled. This is fragile, of course, since the
875 preferred class of a pseudo depends on all instructions that set
876 or use it. */
877
878 if (!REG_P (dest)
879 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
880 || reg_equiv[regno].init_insns == const0_rtx
881 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
882 && MEM_P (src)))
883 {
884 /* This might be setting a SUBREG of a pseudo, a pseudo that is
885 also set somewhere else to a constant. */
886 note_stores (set, no_equiv, NULL);
887 continue;
888 }
889
890 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
891
892 /* cse sometimes generates function invariants, but doesn't put a
893 REG_EQUAL note on the insn. Since this note would be redundant,
894 there's no point creating it earlier than here. */
895 if (! note && ! rtx_varies_p (src, 0))
896 note = set_unique_reg_note (insn, REG_EQUAL, src);
897
898 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
899 since it represents a function call */
900 if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST)
901 note = NULL_RTX;
902
903 if (REG_N_SETS (regno) != 1
904 && (! note
905 || rtx_varies_p (XEXP (note, 0), 0)
906 || (reg_equiv[regno].replacement
907 && ! rtx_equal_p (XEXP (note, 0),
908 reg_equiv[regno].replacement))))
909 {
910 no_equiv (dest, set, NULL);
911 continue;
912 }
913 /* Record this insn as initializing this register. */
914 reg_equiv[regno].init_insns
915 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns);
916
917 /* If this register is known to be equal to a constant, record that
918 it is always equivalent to the constant. */
919 if (note && ! rtx_varies_p (XEXP (note, 0), 0))
920 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
921
922 /* If this insn introduces a "constant" register, decrease the priority
923 of that register. Record this insn if the register is only used once
924 more and the equivalence value is the same as our source.
925
926 The latter condition is checked for two reasons: First, it is an
927 indication that it may be more efficient to actually emit the insn
928 as written (if no registers are available, reload will substitute
929 the equivalence). Secondly, it avoids problems with any registers
930 dying in this insn whose death notes would be missed.
931
932 If we don't have a REG_EQUIV note, see if this insn is loading
933 a register used only in one basic block from a MEM. If so, and the
934 MEM remains unchanged for the life of the register, add a REG_EQUIV
935 note. */
936
937 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
938
939 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
940 && MEM_P (SET_SRC (set))
941 && validate_equiv_mem (insn, dest, SET_SRC (set)))
942 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
943 REG_NOTES (insn));
944
945 if (note)
946 {
947 int regno = REGNO (dest);
948
949 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
950 We might end up substituting the LABEL_REF for uses of the
951 pseudo here or later. That kind of transformation may turn an
952 indirect jump into a direct jump, in which case we must rerun the
953 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
954 if (GET_CODE (XEXP (note, 0)) == LABEL_REF
955 || (GET_CODE (XEXP (note, 0)) == CONST
956 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
957 && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0))
958 == LABEL_REF)))
959 recorded_label_ref = 1;
960
961 reg_equiv[regno].replacement = XEXP (note, 0);
962 reg_equiv[regno].src_p = &SET_SRC (set);
963 reg_equiv[regno].loop_depth = loop_depth;
964
965 /* Don't mess with things live during setjmp. */
966 if (REG_LIVE_LENGTH (regno) >= 0 && optimize)
967 {
968 /* Note that the statement below does not affect the priority
969 in local-alloc! */
970 REG_LIVE_LENGTH (regno) *= 2;
971
972
973 /* If the register is referenced exactly twice, meaning it is
974 set once and used once, indicate that the reference may be
975 replaced by the equivalence we computed above. Do this
976 even if the register is only used in one block so that
977 dependencies can be handled where the last register is
978 used in a different block (i.e. HIGH / LO_SUM sequences)
979 and to reduce the number of registers alive across
980 calls. */
981
982 if (REG_N_REFS (regno) == 2
983 && (rtx_equal_p (XEXP (note, 0), src)
984 || ! equiv_init_varies_p (src))
985 && NONJUMP_INSN_P (insn)
986 && equiv_init_movable_p (PATTERN (insn), regno))
987 reg_equiv[regno].replace = 1;
988 }
989 }
990 }
991 }
992
993 /* Now scan all regs killed in an insn to see if any of them are
994 registers only used that once. If so, see if we can replace the
995 reference with the equivalent from. If we can, delete the
996 initializing reference and this register will go away. If we
997 can't replace the reference, and the initializing reference is
998 within the same loop (or in an inner loop), then move the register
999 initialization just before the use, so that they are in the same
1000 basic block. */
1001 FOR_EACH_BB_REVERSE (bb)
1002 {
1003 loop_depth = bb->loop_depth;
1004 for (insn = BB_END (bb);
1005 insn != PREV_INSN (BB_HEAD (bb));
1006 insn = PREV_INSN (insn))
1007 {
1008 rtx link;
1009
1010 if (! INSN_P (insn))
1011 continue;
1012
1013 /* Don't substitute into a non-local goto, this confuses CFG. */
1014 if (JUMP_P (insn)
1015 && find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
1016 continue;
1017
1018 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1019 {
1020 if (REG_NOTE_KIND (link) == REG_DEAD
1021 /* Make sure this insn still refers to the register. */
1022 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1023 {
1024 int regno = REGNO (XEXP (link, 0));
1025 rtx equiv_insn;
1026
1027 if (! reg_equiv[regno].replace
1028 || reg_equiv[regno].loop_depth < loop_depth)
1029 continue;
1030
1031 /* reg_equiv[REGNO].replace gets set only when
1032 REG_N_REFS[REGNO] is 2, i.e. the register is set
1033 once and used once. (If it were only set, but not used,
1034 flow would have deleted the setting insns.) Hence
1035 there can only be one insn in reg_equiv[REGNO].init_insns. */
1036 if (reg_equiv[regno].init_insns == NULL_RTX
1037 || XEXP (reg_equiv[regno].init_insns, 1) != NULL_RTX)
1038 abort ();
1039 equiv_insn = XEXP (reg_equiv[regno].init_insns, 0);
1040
1041 /* We may not move instructions that can throw, since
1042 that changes basic block boundaries and we are not
1043 prepared to adjust the CFG to match. */
1044 if (can_throw_internal (equiv_insn))
1045 continue;
1046
1047 if (asm_noperands (PATTERN (equiv_insn)) < 0
1048 && validate_replace_rtx (regno_reg_rtx[regno],
1049 *(reg_equiv[regno].src_p), insn))
1050 {
1051 rtx equiv_link;
1052 rtx last_link;
1053 rtx note;
1054
1055 /* Find the last note. */
1056 for (last_link = link; XEXP (last_link, 1);
1057 last_link = XEXP (last_link, 1))
1058 ;
1059
1060 /* Append the REG_DEAD notes from equiv_insn. */
1061 equiv_link = REG_NOTES (equiv_insn);
1062 while (equiv_link)
1063 {
1064 note = equiv_link;
1065 equiv_link = XEXP (equiv_link, 1);
1066 if (REG_NOTE_KIND (note) == REG_DEAD)
1067 {
1068 remove_note (equiv_insn, note);
1069 XEXP (last_link, 1) = note;
1070 XEXP (note, 1) = NULL_RTX;
1071 last_link = note;
1072 }
1073 }
1074
1075 remove_death (regno, insn);
1076 REG_N_REFS (regno) = 0;
1077 REG_FREQ (regno) = 0;
1078 delete_insn (equiv_insn);
1079
1080 reg_equiv[regno].init_insns
1081 = XEXP (reg_equiv[regno].init_insns, 1);
1082 }
1083 /* Move the initialization of the register to just before
1084 INSN. Update the flow information. */
1085 else if (PREV_INSN (insn) != equiv_insn)
1086 {
1087 rtx new_insn;
1088
1089 new_insn = emit_insn_before (PATTERN (equiv_insn), insn);
1090 REG_NOTES (new_insn) = REG_NOTES (equiv_insn);
1091 REG_NOTES (equiv_insn) = 0;
1092
1093 /* Make sure this insn is recognized before reload begins,
1094 otherwise eliminate_regs_in_insn will abort. */
1095 INSN_CODE (new_insn) = INSN_CODE (equiv_insn);
1096
1097 delete_insn (equiv_insn);
1098
1099 XEXP (reg_equiv[regno].init_insns, 0) = new_insn;
1100
1101 REG_BASIC_BLOCK (regno) = bb->index;
1102 REG_N_CALLS_CROSSED (regno) = 0;
1103 REG_LIVE_LENGTH (regno) = 2;
1104
1105 if (insn == BB_HEAD (bb))
1106 BB_HEAD (bb) = PREV_INSN (insn);
1107
1108 /* Remember to clear REGNO from all basic block's live
1109 info. */
1110 SET_REGNO_REG_SET (&cleared_regs, regno);
1111 clear_regnos++;
1112 }
1113 }
1114 }
1115 }
1116 }
1117
1118 /* Clear all dead REGNOs from all basic block's live info. */
1119 if (clear_regnos)
1120 {
1121 int j;
1122 if (clear_regnos > 8)
1123 {
1124 FOR_EACH_BB (bb)
1125 {
1126 AND_COMPL_REG_SET (bb->global_live_at_start, &cleared_regs);
1127 AND_COMPL_REG_SET (bb->global_live_at_end, &cleared_regs);
1128 }
1129 }
1130 else
1131 EXECUTE_IF_SET_IN_REG_SET (&cleared_regs, 0, j,
1132 {
1133 FOR_EACH_BB (bb)
1134 {
1135 CLEAR_REGNO_REG_SET (bb->global_live_at_start, j);
1136 CLEAR_REGNO_REG_SET (bb->global_live_at_end, j);
1137 }
1138 });
1139 }
1140
1141 /* Clean up. */
1142 end_alias_analysis ();
1143 CLEAR_REG_SET (&cleared_regs);
1144 free (reg_equiv);
1145 }
1146
1147 /* Mark REG as having no known equivalence.
1148 Some instructions might have been processed before and furnished
1149 with REG_EQUIV notes for this register; these notes will have to be
1150 removed.
1151 STORE is the piece of RTL that does the non-constant / conflicting
1152 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1153 but needs to be there because this function is called from note_stores. */
1154 static void
1155 no_equiv (rtx reg, rtx store ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED)
1156 {
1157 int regno;
1158 rtx list;
1159
1160 if (!REG_P (reg))
1161 return;
1162 regno = REGNO (reg);
1163 list = reg_equiv[regno].init_insns;
1164 if (list == const0_rtx)
1165 return;
1166 for (; list; list = XEXP (list, 1))
1167 {
1168 rtx insn = XEXP (list, 0);
1169 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
1170 }
1171 reg_equiv[regno].init_insns = const0_rtx;
1172 reg_equiv[regno].replacement = NULL_RTX;
1173 }
1174 \f
1175 /* Allocate hard regs to the pseudo regs used only within block number B.
1176 Only the pseudos that die but once can be handled. */
1177
1178 static void
1179 block_alloc (int b)
1180 {
1181 int i, q;
1182 rtx insn;
1183 rtx note, hard_reg;
1184 int insn_number = 0;
1185 int insn_count = 0;
1186 int max_uid = get_max_uid ();
1187 int *qty_order;
1188 int no_conflict_combined_regno = -1;
1189
1190 /* Count the instructions in the basic block. */
1191
1192 insn = BB_END (BASIC_BLOCK (b));
1193 while (1)
1194 {
1195 if (!NOTE_P (insn))
1196 if (++insn_count > max_uid)
1197 abort ();
1198 if (insn == BB_HEAD (BASIC_BLOCK (b)))
1199 break;
1200 insn = PREV_INSN (insn);
1201 }
1202
1203 /* +2 to leave room for a post_mark_life at the last insn and for
1204 the birth of a CLOBBER in the first insn. */
1205 regs_live_at = xcalloc ((2 * insn_count + 2), sizeof (HARD_REG_SET));
1206
1207 /* Initialize table of hardware registers currently live. */
1208
1209 REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start);
1210
1211 /* This loop scans the instructions of the basic block
1212 and assigns quantities to registers.
1213 It computes which registers to tie. */
1214
1215 insn = BB_HEAD (BASIC_BLOCK (b));
1216 while (1)
1217 {
1218 if (!NOTE_P (insn))
1219 insn_number++;
1220
1221 if (INSN_P (insn))
1222 {
1223 rtx link, set;
1224 int win = 0;
1225 rtx r0, r1 = NULL_RTX;
1226 int combined_regno = -1;
1227 int i;
1228
1229 this_insn_number = insn_number;
1230 this_insn = insn;
1231
1232 extract_insn (insn);
1233 which_alternative = -1;
1234
1235 /* Is this insn suitable for tying two registers?
1236 If so, try doing that.
1237 Suitable insns are those with at least two operands and where
1238 operand 0 is an output that is a register that is not
1239 earlyclobber.
1240
1241 We can tie operand 0 with some operand that dies in this insn.
1242 First look for operands that are required to be in the same
1243 register as operand 0. If we find such, only try tying that
1244 operand or one that can be put into that operand if the
1245 operation is commutative. If we don't find an operand
1246 that is required to be in the same register as operand 0,
1247 we can tie with any operand.
1248
1249 Subregs in place of regs are also ok.
1250
1251 If tying is done, WIN is set nonzero. */
1252
1253 if (optimize
1254 && recog_data.n_operands > 1
1255 && recog_data.constraints[0][0] == '='
1256 && recog_data.constraints[0][1] != '&')
1257 {
1258 /* If non-negative, is an operand that must match operand 0. */
1259 int must_match_0 = -1;
1260 /* Counts number of alternatives that require a match with
1261 operand 0. */
1262 int n_matching_alts = 0;
1263
1264 for (i = 1; i < recog_data.n_operands; i++)
1265 {
1266 const char *p = recog_data.constraints[i];
1267 int this_match = requires_inout (p);
1268
1269 n_matching_alts += this_match;
1270 if (this_match == recog_data.n_alternatives)
1271 must_match_0 = i;
1272 }
1273
1274 r0 = recog_data.operand[0];
1275 for (i = 1; i < recog_data.n_operands; i++)
1276 {
1277 /* Skip this operand if we found an operand that
1278 must match operand 0 and this operand isn't it
1279 and can't be made to be it by commutativity. */
1280
1281 if (must_match_0 >= 0 && i != must_match_0
1282 && ! (i == must_match_0 + 1
1283 && recog_data.constraints[i-1][0] == '%')
1284 && ! (i == must_match_0 - 1
1285 && recog_data.constraints[i][0] == '%'))
1286 continue;
1287
1288 /* Likewise if each alternative has some operand that
1289 must match operand zero. In that case, skip any
1290 operand that doesn't list operand 0 since we know that
1291 the operand always conflicts with operand 0. We
1292 ignore commutativity in this case to keep things simple. */
1293 if (n_matching_alts == recog_data.n_alternatives
1294 && 0 == requires_inout (recog_data.constraints[i]))
1295 continue;
1296
1297 r1 = recog_data.operand[i];
1298
1299 /* If the operand is an address, find a register in it.
1300 There may be more than one register, but we only try one
1301 of them. */
1302 if (recog_data.constraints[i][0] == 'p'
1303 || EXTRA_ADDRESS_CONSTRAINT (recog_data.constraints[i][0],
1304 recog_data.constraints[i]))
1305 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1306 r1 = XEXP (r1, 0);
1307
1308 /* Avoid making a call-saved register unnecessarily
1309 clobbered. */
1310 hard_reg = get_hard_reg_initial_reg (cfun, r1);
1311 if (hard_reg != NULL_RTX)
1312 {
1313 if (REG_P (hard_reg)
1314 && IN_RANGE (REGNO (hard_reg),
1315 0, FIRST_PSEUDO_REGISTER - 1)
1316 && ! call_used_regs[REGNO (hard_reg)])
1317 continue;
1318 }
1319
1320 if (REG_P (r0) || GET_CODE (r0) == SUBREG)
1321 {
1322 /* We have two priorities for hard register preferences.
1323 If we have a move insn or an insn whose first input
1324 can only be in the same register as the output, give
1325 priority to an equivalence found from that insn. */
1326 int may_save_copy
1327 = (r1 == recog_data.operand[i] && must_match_0 >= 0);
1328
1329 if (REG_P (r1) || GET_CODE (r1) == SUBREG)
1330 win = combine_regs (r1, r0, may_save_copy,
1331 insn_number, insn, 0);
1332 }
1333 if (win)
1334 break;
1335 }
1336 }
1337
1338 /* Recognize an insn sequence with an ultimate result
1339 which can safely overlap one of the inputs.
1340 The sequence begins with a CLOBBER of its result,
1341 and ends with an insn that copies the result to itself
1342 and has a REG_EQUAL note for an equivalent formula.
1343 That note indicates what the inputs are.
1344 The result and the input can overlap if each insn in
1345 the sequence either doesn't mention the input
1346 or has a REG_NO_CONFLICT note to inhibit the conflict.
1347
1348 We do the combining test at the CLOBBER so that the
1349 destination register won't have had a quantity number
1350 assigned, since that would prevent combining. */
1351
1352 if (optimize
1353 && GET_CODE (PATTERN (insn)) == CLOBBER
1354 && (r0 = XEXP (PATTERN (insn), 0),
1355 REG_P (r0))
1356 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1357 && XEXP (link, 0) != 0
1358 && NONJUMP_INSN_P (XEXP (link, 0))
1359 && (set = single_set (XEXP (link, 0))) != 0
1360 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1361 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1362 NULL_RTX)) != 0)
1363 {
1364 if (r1 = XEXP (note, 0), REG_P (r1)
1365 /* Check that we have such a sequence. */
1366 && no_conflict_p (insn, r0, r1))
1367 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1368 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1369 && (r1 = XEXP (XEXP (note, 0), 0),
1370 REG_P (r1) || GET_CODE (r1) == SUBREG)
1371 && no_conflict_p (insn, r0, r1))
1372 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1373
1374 /* Here we care if the operation to be computed is
1375 commutative. */
1376 else if (COMMUTATIVE_P (XEXP (note, 0))
1377 && (r1 = XEXP (XEXP (note, 0), 1),
1378 (REG_P (r1) || GET_CODE (r1) == SUBREG))
1379 && no_conflict_p (insn, r0, r1))
1380 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1381
1382 /* If we did combine something, show the register number
1383 in question so that we know to ignore its death. */
1384 if (win)
1385 no_conflict_combined_regno = REGNO (r1);
1386 }
1387
1388 /* If registers were just tied, set COMBINED_REGNO
1389 to the number of the register used in this insn
1390 that was tied to the register set in this insn.
1391 This register's qty should not be "killed". */
1392
1393 if (win)
1394 {
1395 while (GET_CODE (r1) == SUBREG)
1396 r1 = SUBREG_REG (r1);
1397 combined_regno = REGNO (r1);
1398 }
1399
1400 /* Mark the death of everything that dies in this instruction,
1401 except for anything that was just combined. */
1402
1403 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1404 if (REG_NOTE_KIND (link) == REG_DEAD
1405 && REG_P (XEXP (link, 0))
1406 && combined_regno != (int) REGNO (XEXP (link, 0))
1407 && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0))
1408 || ! find_reg_note (insn, REG_NO_CONFLICT,
1409 XEXP (link, 0))))
1410 wipe_dead_reg (XEXP (link, 0), 0);
1411
1412 /* Allocate qty numbers for all registers local to this block
1413 that are born (set) in this instruction.
1414 A pseudo that already has a qty is not changed. */
1415
1416 note_stores (PATTERN (insn), reg_is_set, NULL);
1417
1418 /* If anything is set in this insn and then unused, mark it as dying
1419 after this insn, so it will conflict with our outputs. This
1420 can't match with something that combined, and it doesn't matter
1421 if it did. Do this after the calls to reg_is_set since these
1422 die after, not during, the current insn. */
1423
1424 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1425 if (REG_NOTE_KIND (link) == REG_UNUSED
1426 && REG_P (XEXP (link, 0)))
1427 wipe_dead_reg (XEXP (link, 0), 1);
1428
1429 /* If this is an insn that has a REG_RETVAL note pointing at a
1430 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1431 block, so clear any register number that combined within it. */
1432 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1433 && NONJUMP_INSN_P (XEXP (note, 0))
1434 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1435 no_conflict_combined_regno = -1;
1436 }
1437
1438 /* Set the registers live after INSN_NUMBER. Note that we never
1439 record the registers live before the block's first insn, since no
1440 pseudos we care about are live before that insn. */
1441
1442 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1443 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1444
1445 if (insn == BB_END (BASIC_BLOCK (b)))
1446 break;
1447
1448 insn = NEXT_INSN (insn);
1449 }
1450
1451 /* Now every register that is local to this basic block
1452 should have been given a quantity, or else -1 meaning ignore it.
1453 Every quantity should have a known birth and death.
1454
1455 Order the qtys so we assign them registers in order of the
1456 number of suggested registers they need so we allocate those with
1457 the most restrictive needs first. */
1458
1459 qty_order = xmalloc (next_qty * sizeof (int));
1460 for (i = 0; i < next_qty; i++)
1461 qty_order[i] = i;
1462
1463 #define EXCHANGE(I1, I2) \
1464 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1465
1466 switch (next_qty)
1467 {
1468 case 3:
1469 /* Make qty_order[2] be the one to allocate last. */
1470 if (qty_sugg_compare (0, 1) > 0)
1471 EXCHANGE (0, 1);
1472 if (qty_sugg_compare (1, 2) > 0)
1473 EXCHANGE (2, 1);
1474
1475 /* ... Fall through ... */
1476 case 2:
1477 /* Put the best one to allocate in qty_order[0]. */
1478 if (qty_sugg_compare (0, 1) > 0)
1479 EXCHANGE (0, 1);
1480
1481 /* ... Fall through ... */
1482
1483 case 1:
1484 case 0:
1485 /* Nothing to do here. */
1486 break;
1487
1488 default:
1489 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1490 }
1491
1492 /* Try to put each quantity in a suggested physical register, if it has one.
1493 This may cause registers to be allocated that otherwise wouldn't be, but
1494 this seems acceptable in local allocation (unlike global allocation). */
1495 for (i = 0; i < next_qty; i++)
1496 {
1497 q = qty_order[i];
1498 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1499 qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q,
1500 0, 1, qty[q].birth, qty[q].death);
1501 else
1502 qty[q].phys_reg = -1;
1503 }
1504
1505 /* Order the qtys so we assign them registers in order of
1506 decreasing length of life. Normally call qsort, but if we
1507 have only a very small number of quantities, sort them ourselves. */
1508
1509 for (i = 0; i < next_qty; i++)
1510 qty_order[i] = i;
1511
1512 #define EXCHANGE(I1, I2) \
1513 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1514
1515 switch (next_qty)
1516 {
1517 case 3:
1518 /* Make qty_order[2] be the one to allocate last. */
1519 if (qty_compare (0, 1) > 0)
1520 EXCHANGE (0, 1);
1521 if (qty_compare (1, 2) > 0)
1522 EXCHANGE (2, 1);
1523
1524 /* ... Fall through ... */
1525 case 2:
1526 /* Put the best one to allocate in qty_order[0]. */
1527 if (qty_compare (0, 1) > 0)
1528 EXCHANGE (0, 1);
1529
1530 /* ... Fall through ... */
1531
1532 case 1:
1533 case 0:
1534 /* Nothing to do here. */
1535 break;
1536
1537 default:
1538 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1539 }
1540
1541 /* Now for each qty that is not a hardware register,
1542 look for a hardware register to put it in.
1543 First try the register class that is cheapest for this qty,
1544 if there is more than one class. */
1545
1546 for (i = 0; i < next_qty; i++)
1547 {
1548 q = qty_order[i];
1549 if (qty[q].phys_reg < 0)
1550 {
1551 #ifdef INSN_SCHEDULING
1552 /* These values represent the adjusted lifetime of a qty so
1553 that it conflicts with qtys which appear near the start/end
1554 of this qty's lifetime.
1555
1556 The purpose behind extending the lifetime of this qty is to
1557 discourage the register allocator from creating false
1558 dependencies.
1559
1560 The adjustment value is chosen to indicate that this qty
1561 conflicts with all the qtys in the instructions immediately
1562 before and after the lifetime of this qty.
1563
1564 Experiments have shown that higher values tend to hurt
1565 overall code performance.
1566
1567 If allocation using the extended lifetime fails we will try
1568 again with the qty's unadjusted lifetime. */
1569 int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2);
1570 int fake_death = MIN (insn_number * 2 + 1,
1571 qty[q].death + 2 - qty[q].death % 2);
1572 #endif
1573
1574 if (N_REG_CLASSES > 1)
1575 {
1576 #ifdef INSN_SCHEDULING
1577 /* We try to avoid using hard registers allocated to qtys which
1578 are born immediately after this qty or die immediately before
1579 this qty.
1580
1581 This optimization is only appropriate when we will run
1582 a scheduling pass after reload and we are not optimizing
1583 for code size. */
1584 if (flag_schedule_insns_after_reload
1585 && !optimize_size
1586 && !SMALL_REGISTER_CLASSES)
1587 {
1588 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1589 qty[q].mode, q, 0, 0,
1590 fake_birth, fake_death);
1591 if (qty[q].phys_reg >= 0)
1592 continue;
1593 }
1594 #endif
1595 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1596 qty[q].mode, q, 0, 0,
1597 qty[q].birth, qty[q].death);
1598 if (qty[q].phys_reg >= 0)
1599 continue;
1600 }
1601
1602 #ifdef INSN_SCHEDULING
1603 /* Similarly, avoid false dependencies. */
1604 if (flag_schedule_insns_after_reload
1605 && !optimize_size
1606 && !SMALL_REGISTER_CLASSES
1607 && qty[q].alternate_class != NO_REGS)
1608 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1609 qty[q].mode, q, 0, 0,
1610 fake_birth, fake_death);
1611 #endif
1612 if (qty[q].alternate_class != NO_REGS)
1613 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1614 qty[q].mode, q, 0, 0,
1615 qty[q].birth, qty[q].death);
1616 }
1617 }
1618
1619 /* Now propagate the register assignments
1620 to the pseudo regs belonging to the qtys. */
1621
1622 for (q = 0; q < next_qty; q++)
1623 if (qty[q].phys_reg >= 0)
1624 {
1625 for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i])
1626 reg_renumber[i] = qty[q].phys_reg + reg_offset[i];
1627 }
1628
1629 /* Clean up. */
1630 free (regs_live_at);
1631 free (qty_order);
1632 }
1633 \f
1634 /* Compare two quantities' priority for getting real registers.
1635 We give shorter-lived quantities higher priority.
1636 Quantities with more references are also preferred, as are quantities that
1637 require multiple registers. This is the identical prioritization as
1638 done by global-alloc.
1639
1640 We used to give preference to registers with *longer* lives, but using
1641 the same algorithm in both local- and global-alloc can speed up execution
1642 of some programs by as much as a factor of three! */
1643
1644 /* Note that the quotient will never be bigger than
1645 the value of floor_log2 times the maximum number of
1646 times a register can occur in one insn (surely less than 100)
1647 weighted by frequency (max REG_FREQ_MAX).
1648 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1649 QTY_CMP_PRI is also used by qty_sugg_compare. */
1650
1651 #define QTY_CMP_PRI(q) \
1652 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1653 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1654
1655 static int
1656 qty_compare (int q1, int q2)
1657 {
1658 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1659 }
1660
1661 static int
1662 qty_compare_1 (const void *q1p, const void *q2p)
1663 {
1664 int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1665 int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1666
1667 if (tem != 0)
1668 return tem;
1669
1670 /* If qtys are equally good, sort by qty number,
1671 so that the results of qsort leave nothing to chance. */
1672 return q1 - q2;
1673 }
1674 \f
1675 /* Compare two quantities' priority for getting real registers. This version
1676 is called for quantities that have suggested hard registers. First priority
1677 goes to quantities that have copy preferences, then to those that have
1678 normal preferences. Within those groups, quantities with the lower
1679 number of preferences have the highest priority. Of those, we use the same
1680 algorithm as above. */
1681
1682 #define QTY_CMP_SUGG(q) \
1683 (qty_phys_num_copy_sugg[q] \
1684 ? qty_phys_num_copy_sugg[q] \
1685 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1686
1687 static int
1688 qty_sugg_compare (int q1, int q2)
1689 {
1690 int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1691
1692 if (tem != 0)
1693 return tem;
1694
1695 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1696 }
1697
1698 static int
1699 qty_sugg_compare_1 (const void *q1p, const void *q2p)
1700 {
1701 int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1702 int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1703
1704 if (tem != 0)
1705 return tem;
1706
1707 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1708 if (tem != 0)
1709 return tem;
1710
1711 /* If qtys are equally good, sort by qty number,
1712 so that the results of qsort leave nothing to chance. */
1713 return q1 - q2;
1714 }
1715
1716 #undef QTY_CMP_SUGG
1717 #undef QTY_CMP_PRI
1718 \f
1719 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1720 Returns 1 if have done so, or 0 if cannot.
1721
1722 Combining registers means marking them as having the same quantity
1723 and adjusting the offsets within the quantity if either of
1724 them is a SUBREG.
1725
1726 We don't actually combine a hard reg with a pseudo; instead
1727 we just record the hard reg as the suggestion for the pseudo's quantity.
1728 If we really combined them, we could lose if the pseudo lives
1729 across an insn that clobbers the hard reg (eg, movmem).
1730
1731 ALREADY_DEAD is nonzero if USEDREG is known to be dead even though
1732 there is no REG_DEAD note on INSN. This occurs during the processing
1733 of REG_NO_CONFLICT blocks.
1734
1735 MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to
1736 SETREG or if the input and output must share a register.
1737 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1738
1739 There are elaborate checks for the validity of combining. */
1740
1741 static int
1742 combine_regs (rtx usedreg, rtx setreg, int may_save_copy, int insn_number,
1743 rtx insn, int already_dead)
1744 {
1745 int ureg, sreg;
1746 int offset = 0;
1747 int usize, ssize;
1748 int sqty;
1749
1750 /* Determine the numbers and sizes of registers being used. If a subreg
1751 is present that does not change the entire register, don't consider
1752 this a copy insn. */
1753
1754 while (GET_CODE (usedreg) == SUBREG)
1755 {
1756 rtx subreg = SUBREG_REG (usedreg);
1757
1758 if (REG_P (subreg))
1759 {
1760 if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
1761 may_save_copy = 0;
1762
1763 if (REGNO (subreg) < FIRST_PSEUDO_REGISTER)
1764 offset += subreg_regno_offset (REGNO (subreg),
1765 GET_MODE (subreg),
1766 SUBREG_BYTE (usedreg),
1767 GET_MODE (usedreg));
1768 else
1769 offset += (SUBREG_BYTE (usedreg)
1770 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg)));
1771 }
1772
1773 usedreg = subreg;
1774 }
1775
1776 if (!REG_P (usedreg))
1777 return 0;
1778
1779 ureg = REGNO (usedreg);
1780 if (ureg < FIRST_PSEUDO_REGISTER)
1781 usize = hard_regno_nregs[ureg][GET_MODE (usedreg)];
1782 else
1783 usize = ((GET_MODE_SIZE (GET_MODE (usedreg))
1784 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg)) - 1))
1785 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg)));
1786
1787 while (GET_CODE (setreg) == SUBREG)
1788 {
1789 rtx subreg = SUBREG_REG (setreg);
1790
1791 if (REG_P (subreg))
1792 {
1793 if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
1794 may_save_copy = 0;
1795
1796 if (REGNO (subreg) < FIRST_PSEUDO_REGISTER)
1797 offset -= subreg_regno_offset (REGNO (subreg),
1798 GET_MODE (subreg),
1799 SUBREG_BYTE (setreg),
1800 GET_MODE (setreg));
1801 else
1802 offset -= (SUBREG_BYTE (setreg)
1803 / REGMODE_NATURAL_SIZE (GET_MODE (setreg)));
1804 }
1805
1806 setreg = subreg;
1807 }
1808
1809 if (!REG_P (setreg))
1810 return 0;
1811
1812 sreg = REGNO (setreg);
1813 if (sreg < FIRST_PSEUDO_REGISTER)
1814 ssize = hard_regno_nregs[sreg][GET_MODE (setreg)];
1815 else
1816 ssize = ((GET_MODE_SIZE (GET_MODE (setreg))
1817 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg)) - 1))
1818 / REGMODE_NATURAL_SIZE (GET_MODE (setreg)));
1819
1820 /* If UREG is a pseudo-register that hasn't already been assigned a
1821 quantity number, it means that it is not local to this block or dies
1822 more than once. In either event, we can't do anything with it. */
1823 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1824 /* Do not combine registers unless one fits within the other. */
1825 || (offset > 0 && usize + offset > ssize)
1826 || (offset < 0 && usize + offset < ssize)
1827 /* Do not combine with a smaller already-assigned object
1828 if that smaller object is already combined with something bigger. */
1829 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1830 && usize < qty[reg_qty[ureg]].size)
1831 /* Can't combine if SREG is not a register we can allocate. */
1832 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1833 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1834 These have already been taken care of. This probably wouldn't
1835 combine anyway, but don't take any chances. */
1836 || (ureg >= FIRST_PSEUDO_REGISTER
1837 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1838 /* Don't tie something to itself. In most cases it would make no
1839 difference, but it would screw up if the reg being tied to itself
1840 also dies in this insn. */
1841 || ureg == sreg
1842 /* Don't try to connect two different hardware registers. */
1843 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1844 /* Don't connect two different machine modes if they have different
1845 implications as to which registers may be used. */
1846 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1847 return 0;
1848
1849 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1850 qty_phys_sugg for the pseudo instead of tying them.
1851
1852 Return "failure" so that the lifespan of UREG is terminated here;
1853 that way the two lifespans will be disjoint and nothing will prevent
1854 the pseudo reg from being given this hard reg. */
1855
1856 if (ureg < FIRST_PSEUDO_REGISTER)
1857 {
1858 /* Allocate a quantity number so we have a place to put our
1859 suggestions. */
1860 if (reg_qty[sreg] == -2)
1861 reg_is_born (setreg, 2 * insn_number);
1862
1863 if (reg_qty[sreg] >= 0)
1864 {
1865 if (may_save_copy
1866 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1867 {
1868 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1869 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1870 }
1871 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1872 {
1873 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1874 qty_phys_num_sugg[reg_qty[sreg]]++;
1875 }
1876 }
1877 return 0;
1878 }
1879
1880 /* Similarly for SREG a hard register and UREG a pseudo register. */
1881
1882 if (sreg < FIRST_PSEUDO_REGISTER)
1883 {
1884 if (may_save_copy
1885 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1886 {
1887 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1888 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1889 }
1890 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1891 {
1892 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1893 qty_phys_num_sugg[reg_qty[ureg]]++;
1894 }
1895 return 0;
1896 }
1897
1898 /* At this point we know that SREG and UREG are both pseudos.
1899 Do nothing if SREG already has a quantity or is a register that we
1900 don't allocate. */
1901 if (reg_qty[sreg] >= -1
1902 /* If we are not going to let any regs live across calls,
1903 don't tie a call-crossing reg to a non-call-crossing reg. */
1904 || (current_function_has_nonlocal_label
1905 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1906 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1907 return 0;
1908
1909 /* We don't already know about SREG, so tie it to UREG
1910 if this is the last use of UREG, provided the classes they want
1911 are compatible. */
1912
1913 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1914 && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class))
1915 {
1916 /* Add SREG to UREG's quantity. */
1917 sqty = reg_qty[ureg];
1918 reg_qty[sreg] = sqty;
1919 reg_offset[sreg] = reg_offset[ureg] + offset;
1920 reg_next_in_qty[sreg] = qty[sqty].first_reg;
1921 qty[sqty].first_reg = sreg;
1922
1923 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1924 update_qty_class (sqty, sreg);
1925
1926 /* Update info about quantity SQTY. */
1927 qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg);
1928 qty[sqty].n_refs += REG_N_REFS (sreg);
1929 qty[sqty].freq += REG_FREQ (sreg);
1930 if (usize < ssize)
1931 {
1932 int i;
1933
1934 for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i])
1935 reg_offset[i] -= offset;
1936
1937 qty[sqty].size = ssize;
1938 qty[sqty].mode = GET_MODE (setreg);
1939 }
1940 }
1941 else
1942 return 0;
1943
1944 return 1;
1945 }
1946 \f
1947 /* Return 1 if the preferred class of REG allows it to be tied
1948 to a quantity or register whose class is CLASS.
1949 True if REG's reg class either contains or is contained in CLASS. */
1950
1951 static int
1952 reg_meets_class_p (int reg, enum reg_class class)
1953 {
1954 enum reg_class rclass = reg_preferred_class (reg);
1955 return (reg_class_subset_p (rclass, class)
1956 || reg_class_subset_p (class, rclass));
1957 }
1958
1959 /* Update the class of QTYNO assuming that REG is being tied to it. */
1960
1961 static void
1962 update_qty_class (int qtyno, int reg)
1963 {
1964 enum reg_class rclass = reg_preferred_class (reg);
1965 if (reg_class_subset_p (rclass, qty[qtyno].min_class))
1966 qty[qtyno].min_class = rclass;
1967
1968 rclass = reg_alternate_class (reg);
1969 if (reg_class_subset_p (rclass, qty[qtyno].alternate_class))
1970 qty[qtyno].alternate_class = rclass;
1971 }
1972 \f
1973 /* Handle something which alters the value of an rtx REG.
1974
1975 REG is whatever is set or clobbered. SETTER is the rtx that
1976 is modifying the register.
1977
1978 If it is not really a register, we do nothing.
1979 The file-global variables `this_insn' and `this_insn_number'
1980 carry info from `block_alloc'. */
1981
1982 static void
1983 reg_is_set (rtx reg, rtx setter, void *data ATTRIBUTE_UNUSED)
1984 {
1985 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1986 a hard register. These may actually not exist any more. */
1987
1988 if (GET_CODE (reg) != SUBREG
1989 && !REG_P (reg))
1990 return;
1991
1992 /* Mark this register as being born. If it is used in a CLOBBER, mark
1993 it as being born halfway between the previous insn and this insn so that
1994 it conflicts with our inputs but not the outputs of the previous insn. */
1995
1996 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1997 }
1998 \f
1999 /* Handle beginning of the life of register REG.
2000 BIRTH is the index at which this is happening. */
2001
2002 static void
2003 reg_is_born (rtx reg, int birth)
2004 {
2005 int regno;
2006
2007 if (GET_CODE (reg) == SUBREG)
2008 {
2009 regno = REGNO (SUBREG_REG (reg));
2010 if (regno < FIRST_PSEUDO_REGISTER)
2011 regno = subreg_hard_regno (reg, 1);
2012 }
2013 else
2014 regno = REGNO (reg);
2015
2016 if (regno < FIRST_PSEUDO_REGISTER)
2017 {
2018 mark_life (regno, GET_MODE (reg), 1);
2019
2020 /* If the register was to have been born earlier that the present
2021 insn, mark it as live where it is actually born. */
2022 if (birth < 2 * this_insn_number)
2023 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
2024 }
2025 else
2026 {
2027 if (reg_qty[regno] == -2)
2028 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2029
2030 /* If this register has a quantity number, show that it isn't dead. */
2031 if (reg_qty[regno] >= 0)
2032 qty[reg_qty[regno]].death = -1;
2033 }
2034 }
2035
2036 /* Record the death of REG in the current insn. If OUTPUT_P is nonzero,
2037 REG is an output that is dying (i.e., it is never used), otherwise it
2038 is an input (the normal case).
2039 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2040
2041 static void
2042 wipe_dead_reg (rtx reg, int output_p)
2043 {
2044 int regno = REGNO (reg);
2045
2046 /* If this insn has multiple results,
2047 and the dead reg is used in one of the results,
2048 extend its life to after this insn,
2049 so it won't get allocated together with any other result of this insn.
2050
2051 It is unsafe to use !single_set here since it will ignore an unused
2052 output. Just because an output is unused does not mean the compiler
2053 can assume the side effect will not occur. Consider if REG appears
2054 in the address of an output and we reload the output. If we allocate
2055 REG to the same hard register as an unused output we could set the hard
2056 register before the output reload insn. */
2057 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2058 && multiple_sets (this_insn))
2059 {
2060 int i;
2061 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2062 {
2063 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2064 if (GET_CODE (set) == SET
2065 && !REG_P (SET_DEST (set))
2066 && !rtx_equal_p (reg, SET_DEST (set))
2067 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2068 output_p = 1;
2069 }
2070 }
2071
2072 /* If this register is used in an auto-increment address, then extend its
2073 life to after this insn, so that it won't get allocated together with
2074 the result of this insn. */
2075 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2076 output_p = 1;
2077
2078 if (regno < FIRST_PSEUDO_REGISTER)
2079 {
2080 mark_life (regno, GET_MODE (reg), 0);
2081
2082 /* If a hard register is dying as an output, mark it as in use at
2083 the beginning of this insn (the above statement would cause this
2084 not to happen). */
2085 if (output_p)
2086 post_mark_life (regno, GET_MODE (reg), 1,
2087 2 * this_insn_number, 2 * this_insn_number + 1);
2088 }
2089
2090 else if (reg_qty[regno] >= 0)
2091 qty[reg_qty[regno]].death = 2 * this_insn_number + output_p;
2092 }
2093 \f
2094 /* Find a block of SIZE words of hard regs in reg_class CLASS
2095 that can hold something of machine-mode MODE
2096 (but actually we test only the first of the block for holding MODE)
2097 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2098 and return the number of the first of them.
2099 Return -1 if such a block cannot be found.
2100 If QTYNO crosses calls, insist on a register preserved by calls,
2101 unless ACCEPT_CALL_CLOBBERED is nonzero.
2102
2103 If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested
2104 register is available. If not, return -1. */
2105
2106 static int
2107 find_free_reg (enum reg_class class, enum machine_mode mode, int qtyno,
2108 int accept_call_clobbered, int just_try_suggested,
2109 int born_index, int dead_index)
2110 {
2111 int i, ins;
2112 HARD_REG_SET first_used, used;
2113 #ifdef ELIMINABLE_REGS
2114 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
2115 #endif
2116
2117 /* Validate our parameters. */
2118 if (born_index < 0 || born_index > dead_index)
2119 abort ();
2120
2121 /* Don't let a pseudo live in a reg across a function call
2122 if we might get a nonlocal goto. */
2123 if (current_function_has_nonlocal_label
2124 && qty[qtyno].n_calls_crossed > 0)
2125 return -1;
2126
2127 if (accept_call_clobbered)
2128 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2129 else if (qty[qtyno].n_calls_crossed == 0)
2130 COPY_HARD_REG_SET (used, fixed_reg_set);
2131 else
2132 COPY_HARD_REG_SET (used, call_used_reg_set);
2133
2134 if (accept_call_clobbered)
2135 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2136
2137 for (ins = born_index; ins < dead_index; ins++)
2138 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2139
2140 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2141
2142 /* Don't use the frame pointer reg in local-alloc even if
2143 we may omit the frame pointer, because if we do that and then we
2144 need a frame pointer, reload won't know how to move the pseudo
2145 to another hard reg. It can move only regs made by global-alloc.
2146
2147 This is true of any register that can be eliminated. */
2148 #ifdef ELIMINABLE_REGS
2149 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
2150 SET_HARD_REG_BIT (used, eliminables[i].from);
2151 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2152 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2153 that it might be eliminated into. */
2154 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2155 #endif
2156 #else
2157 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2158 #endif
2159
2160 #ifdef CANNOT_CHANGE_MODE_CLASS
2161 cannot_change_mode_set_regs (&used, mode, qty[qtyno].first_reg);
2162 #endif
2163
2164 /* Normally, the registers that can be used for the first register in
2165 a multi-register quantity are the same as those that can be used for
2166 subsequent registers. However, if just trying suggested registers,
2167 restrict our consideration to them. If there are copy-suggested
2168 register, try them. Otherwise, try the arithmetic-suggested
2169 registers. */
2170 COPY_HARD_REG_SET (first_used, used);
2171
2172 if (just_try_suggested)
2173 {
2174 if (qty_phys_num_copy_sugg[qtyno] != 0)
2175 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]);
2176 else
2177 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]);
2178 }
2179
2180 /* If all registers are excluded, we can't do anything. */
2181 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2182
2183 /* If at least one would be suitable, test each hard reg. */
2184
2185 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2186 {
2187 #ifdef REG_ALLOC_ORDER
2188 int regno = reg_alloc_order[i];
2189 #else
2190 int regno = i;
2191 #endif
2192 if (! TEST_HARD_REG_BIT (first_used, regno)
2193 && HARD_REGNO_MODE_OK (regno, mode)
2194 && (qty[qtyno].n_calls_crossed == 0
2195 || accept_call_clobbered
2196 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
2197 {
2198 int j;
2199 int size1 = hard_regno_nregs[regno][mode];
2200 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2201 if (j == size1)
2202 {
2203 /* Mark that this register is in use between its birth and death
2204 insns. */
2205 post_mark_life (regno, mode, 1, born_index, dead_index);
2206 return regno;
2207 }
2208 #ifndef REG_ALLOC_ORDER
2209 /* Skip starting points we know will lose. */
2210 i += j;
2211 #endif
2212 }
2213 }
2214
2215 fail:
2216 /* If we are just trying suggested register, we have just tried copy-
2217 suggested registers, and there are arithmetic-suggested registers,
2218 try them. */
2219
2220 /* If it would be profitable to allocate a call-clobbered register
2221 and save and restore it around calls, do that. */
2222 if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0
2223 && qty_phys_num_sugg[qtyno] != 0)
2224 {
2225 /* Don't try the copy-suggested regs again. */
2226 qty_phys_num_copy_sugg[qtyno] = 0;
2227 return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1,
2228 born_index, dead_index);
2229 }
2230
2231 /* We need not check to see if the current function has nonlocal
2232 labels because we don't put any pseudos that are live over calls in
2233 registers in that case. */
2234
2235 if (! accept_call_clobbered
2236 && flag_caller_saves
2237 && ! just_try_suggested
2238 && qty[qtyno].n_calls_crossed != 0
2239 && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs,
2240 qty[qtyno].n_calls_crossed))
2241 {
2242 i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index);
2243 if (i >= 0)
2244 caller_save_needed = 1;
2245 return i;
2246 }
2247 return -1;
2248 }
2249 \f
2250 /* Mark that REGNO with machine-mode MODE is live starting from the current
2251 insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE
2252 is zero). */
2253
2254 static void
2255 mark_life (int regno, enum machine_mode mode, int life)
2256 {
2257 int j = hard_regno_nregs[regno][mode];
2258 if (life)
2259 while (--j >= 0)
2260 SET_HARD_REG_BIT (regs_live, regno + j);
2261 else
2262 while (--j >= 0)
2263 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2264 }
2265
2266 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2267 is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2268 to insn number DEATH (exclusive). */
2269
2270 static void
2271 post_mark_life (int regno, enum machine_mode mode, int life, int birth,
2272 int death)
2273 {
2274 int j = hard_regno_nregs[regno][mode];
2275 HARD_REG_SET this_reg;
2276
2277 CLEAR_HARD_REG_SET (this_reg);
2278 while (--j >= 0)
2279 SET_HARD_REG_BIT (this_reg, regno + j);
2280
2281 if (life)
2282 while (birth < death)
2283 {
2284 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2285 birth++;
2286 }
2287 else
2288 while (birth < death)
2289 {
2290 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2291 birth++;
2292 }
2293 }
2294 \f
2295 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2296 is the register being clobbered, and R1 is a register being used in
2297 the equivalent expression.
2298
2299 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2300 in which it is used, return 1.
2301
2302 Otherwise, return 0. */
2303
2304 static int
2305 no_conflict_p (rtx insn, rtx r0 ATTRIBUTE_UNUSED, rtx r1)
2306 {
2307 int ok = 0;
2308 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2309 rtx p, last;
2310
2311 /* If R1 is a hard register, return 0 since we handle this case
2312 when we scan the insns that actually use it. */
2313
2314 if (note == 0
2315 || (REG_P (r1) && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2316 || (GET_CODE (r1) == SUBREG && REG_P (SUBREG_REG (r1))
2317 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2318 return 0;
2319
2320 last = XEXP (note, 0);
2321
2322 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2323 if (INSN_P (p))
2324 {
2325 if (find_reg_note (p, REG_DEAD, r1))
2326 ok = 1;
2327
2328 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2329 some earlier optimization pass has inserted instructions into
2330 the sequence, and it is not safe to perform this optimization.
2331 Note that emit_no_conflict_block always ensures that this is
2332 true when these sequences are created. */
2333 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2334 return 0;
2335 }
2336
2337 return ok;
2338 }
2339 \f
2340 /* Return the number of alternatives for which the constraint string P
2341 indicates that the operand must be equal to operand 0 and that no register
2342 is acceptable. */
2343
2344 static int
2345 requires_inout (const char *p)
2346 {
2347 char c;
2348 int found_zero = 0;
2349 int reg_allowed = 0;
2350 int num_matching_alts = 0;
2351 int len;
2352
2353 for ( ; (c = *p); p += len)
2354 {
2355 len = CONSTRAINT_LEN (c, p);
2356 switch (c)
2357 {
2358 case '=': case '+': case '?':
2359 case '#': case '&': case '!':
2360 case '*': case '%':
2361 case 'm': case '<': case '>': case 'V': case 'o':
2362 case 'E': case 'F': case 'G': case 'H':
2363 case 's': case 'i': case 'n':
2364 case 'I': case 'J': case 'K': case 'L':
2365 case 'M': case 'N': case 'O': case 'P':
2366 case 'X':
2367 /* These don't say anything we care about. */
2368 break;
2369
2370 case ',':
2371 if (found_zero && ! reg_allowed)
2372 num_matching_alts++;
2373
2374 found_zero = reg_allowed = 0;
2375 break;
2376
2377 case '0':
2378 found_zero = 1;
2379 break;
2380
2381 case '1': case '2': case '3': case '4': case '5':
2382 case '6': case '7': case '8': case '9':
2383 /* Skip the balance of the matching constraint. */
2384 do
2385 p++;
2386 while (ISDIGIT (*p));
2387 len = 0;
2388 break;
2389
2390 default:
2391 if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS
2392 && !EXTRA_ADDRESS_CONSTRAINT (c, p))
2393 break;
2394 /* Fall through. */
2395 case 'p':
2396 case 'g': case 'r':
2397 reg_allowed = 1;
2398 break;
2399 }
2400 }
2401
2402 if (found_zero && ! reg_allowed)
2403 num_matching_alts++;
2404
2405 return num_matching_alts;
2406 }
2407 \f
2408 void
2409 dump_local_alloc (FILE *file)
2410 {
2411 int i;
2412 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2413 if (reg_renumber[i] != -1)
2414 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
2415 }