1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
64 #include "coretypes.h"
66 #include "hard-reg-set.h"
70 #include "basic-block.h"
73 #include "insn-config.h"
74 #include "insn-attr.h"
79 #include "integrate.h"
81 /* Next quantity number available for allocation. */
85 /* Information we maintain about each quantity. */
88 /* The number of refs to quantity Q. */
92 /* The frequency of uses of quantity Q. */
96 /* Insn number (counting from head of basic block)
97 where quantity Q was born. -1 if birth has not been recorded. */
101 /* Insn number (counting from head of basic block)
102 where given quantity died. Due to the way tying is done,
103 and the fact that we consider in this pass only regs that die but once,
104 a quantity can die only once. Each quantity's life span
105 is a set of consecutive insns. -1 if death has not been recorded. */
109 /* Number of words needed to hold the data in given quantity.
110 This depends on its machine mode. It is used for these purposes:
111 1. It is used in computing the relative importance of qtys,
112 which determines the order in which we look for regs for them.
113 2. It is used in rules that prevent tying several registers of
114 different sizes in a way that is geometrically impossible
115 (see combine_regs). */
119 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
123 /* The register number of one pseudo register whose reg_qty value is Q.
124 This register should be the head of the chain
125 maintained in reg_next_in_qty. */
129 /* Reg class contained in (smaller than) the preferred classes of all
130 the pseudo regs that are tied in given quantity.
131 This is the preferred class for allocating that quantity. */
133 enum reg_class min_class
;
135 /* Register class within which we allocate given qty if we can't get
136 its preferred class. */
138 enum reg_class alternate_class
;
140 /* This holds the mode of the registers that are tied to given qty,
141 or VOIDmode if registers with differing modes are tied together. */
143 enum machine_mode mode
;
145 /* the hard reg number chosen for given quantity,
146 or -1 if none was found. */
151 static struct qty
*qty
;
153 /* These fields are kept separately to speedup their clearing. */
155 /* We maintain two hard register sets that indicate suggested hard registers
156 for each quantity. The first, phys_copy_sugg, contains hard registers
157 that are tied to the quantity by a simple copy. The second contains all
158 hard registers that are tied to the quantity via an arithmetic operation.
160 The former register set is given priority for allocation. This tends to
161 eliminate copy insns. */
163 /* Element Q is a set of hard registers that are suggested for quantity Q by
166 static HARD_REG_SET
*qty_phys_copy_sugg
;
168 /* Element Q is a set of hard registers that are suggested for quantity Q by
171 static HARD_REG_SET
*qty_phys_sugg
;
173 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
175 static short *qty_phys_num_copy_sugg
;
177 /* Element Q is the number of suggested registers in qty_phys_sugg. */
179 static short *qty_phys_num_sugg
;
181 /* If (REG N) has been assigned a quantity number, is a register number
182 of another register assigned the same quantity number, or -1 for the
183 end of the chain. qty->first_reg point to the head of this chain. */
185 static int *reg_next_in_qty
;
187 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
189 of -1 if this register cannot be allocated by local-alloc,
190 or -2 if not known yet.
192 Note that if we see a use or death of pseudo register N with
193 reg_qty[N] == -2, register N must be local to the current block. If
194 it were used in more than one block, we would have reg_qty[N] == -1.
195 This relies on the fact that if reg_basic_block[N] is >= 0, register N
196 will not appear in any other block. We save a considerable number of
197 tests by exploiting this.
199 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
204 /* The offset (in words) of register N within its quantity.
205 This can be nonzero if register N is SImode, and has been tied
206 to a subreg of a DImode register. */
208 static char *reg_offset
;
210 /* Vector of substitutions of register numbers,
211 used to map pseudo regs into hardware regs.
212 This is set up as a result of register allocation.
213 Element N is the hard reg assigned to pseudo reg N,
214 or is -1 if no hard reg was assigned.
215 If N is a hard reg number, element N is N. */
219 /* Set of hard registers live at the current point in the scan
220 of the instructions in a basic block. */
222 static HARD_REG_SET regs_live
;
224 /* Each set of hard registers indicates registers live at a particular
225 point in the basic block. For N even, regs_live_at[N] says which
226 hard registers are needed *after* insn N/2 (i.e., they may not
227 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
229 If an object is to conflict with the inputs of insn J but not the
230 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
231 if it is to conflict with the outputs of insn J but not the inputs of
232 insn J + 1, it is said to die at index J*2 + 1. */
234 static HARD_REG_SET
*regs_live_at
;
236 /* Communicate local vars `insn_number' and `insn'
237 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
238 static int this_insn_number
;
239 static rtx this_insn
;
243 /* Set when an attempt should be made to replace a register
244 with the associated src_p entry. */
248 /* Set when a REG_EQUIV note is found or created. Use to
249 keep track of what memory accesses might be created later,
256 /* Loop depth is used to recognize equivalences which appear
257 to be present within the same loop (or in an inner loop). */
261 /* The list of each instruction which initializes this register. */
266 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
267 structure for that register. */
269 static struct equivalence
*reg_equiv
;
271 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
272 static int recorded_label_ref
;
274 static void alloc_qty (int, enum machine_mode
, int, int);
275 static void validate_equiv_mem_from_store (rtx
, rtx
, void *);
276 static int validate_equiv_mem (rtx
, rtx
, rtx
);
277 static int equiv_init_varies_p (rtx
);
278 static int equiv_init_movable_p (rtx
, int);
279 static int contains_replace_regs (rtx
);
280 static int memref_referenced_p (rtx
, rtx
);
281 static int memref_used_between_p (rtx
, rtx
, rtx
);
282 static void update_equiv_regs (void);
283 static void no_equiv (rtx
, rtx
, void *);
284 static void block_alloc (int);
285 static int qty_sugg_compare (int, int);
286 static int qty_sugg_compare_1 (const void *, const void *);
287 static int qty_compare (int, int);
288 static int qty_compare_1 (const void *, const void *);
289 static int combine_regs (rtx
, rtx
, int, int, rtx
, int);
290 static int reg_meets_class_p (int, enum reg_class
);
291 static void update_qty_class (int, int);
292 static void reg_is_set (rtx
, rtx
, void *);
293 static void reg_is_born (rtx
, int);
294 static void wipe_dead_reg (rtx
, int);
295 static int find_free_reg (enum reg_class
, enum machine_mode
, int, int, int,
297 static void mark_life (int, enum machine_mode
, int);
298 static void post_mark_life (int, enum machine_mode
, int, int, int);
299 static int no_conflict_p (rtx
, rtx
, rtx
);
300 static int requires_inout (const char *);
302 /* Allocate a new quantity (new within current basic block)
303 for register number REGNO which is born at index BIRTH
304 within the block. MODE and SIZE are info on reg REGNO. */
307 alloc_qty (int regno
, enum machine_mode mode
, int size
, int birth
)
309 int qtyno
= next_qty
++;
311 reg_qty
[regno
] = qtyno
;
312 reg_offset
[regno
] = 0;
313 reg_next_in_qty
[regno
] = -1;
315 qty
[qtyno
].first_reg
= regno
;
316 qty
[qtyno
].size
= size
;
317 qty
[qtyno
].mode
= mode
;
318 qty
[qtyno
].birth
= birth
;
319 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
320 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
321 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
322 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
323 qty
[qtyno
].freq
= REG_FREQ (regno
);
326 /* Main entry point of this file. */
335 /* We need to keep track of whether or not we recorded a LABEL_REF so
336 that we know if the jump optimizer needs to be rerun. */
337 recorded_label_ref
= 0;
339 /* Leaf functions and non-leaf functions have different needs.
340 If defined, let the machine say what kind of ordering we
342 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
343 ORDER_REGS_FOR_LOCAL_ALLOC
;
346 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
349 update_equiv_regs ();
351 /* This sets the maximum number of quantities we can have. Quantity
352 numbers start at zero and we can have one for each pseudo. */
353 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
355 /* Allocate vectors of temporary data.
356 See the declarations of these variables, above,
357 for what they mean. */
359 qty
= xmalloc (max_qty
* sizeof (struct qty
));
360 qty_phys_copy_sugg
= xmalloc (max_qty
* sizeof (HARD_REG_SET
));
361 qty_phys_num_copy_sugg
= xmalloc (max_qty
* sizeof (short));
362 qty_phys_sugg
= xmalloc (max_qty
* sizeof (HARD_REG_SET
));
363 qty_phys_num_sugg
= xmalloc (max_qty
* sizeof (short));
365 reg_qty
= xmalloc (max_regno
* sizeof (int));
366 reg_offset
= xmalloc (max_regno
* sizeof (char));
367 reg_next_in_qty
= xmalloc (max_regno
* sizeof (int));
369 /* Determine which pseudo-registers can be allocated by local-alloc.
370 In general, these are the registers used only in a single block and
373 We need not be concerned with which block actually uses the register
374 since we will never see it outside that block. */
376 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
378 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1)
384 /* Force loop below to initialize entire quantity array. */
387 /* Allocate each block's local registers, block by block. */
391 /* NEXT_QTY indicates which elements of the `qty_...'
392 vectors might need to be initialized because they were used
393 for the previous block; it is set to the entire array before
394 block 0. Initialize those, with explicit loop if there are few,
395 else with bzero and bcopy. Do not initialize vectors that are
396 explicit set by `alloc_qty'. */
400 for (i
= 0; i
< next_qty
; i
++)
402 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
403 qty_phys_num_copy_sugg
[i
] = 0;
404 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
405 qty_phys_num_sugg
[i
] = 0;
410 #define CLEAR(vector) \
411 memset ((vector), 0, (sizeof (*(vector))) * next_qty);
413 CLEAR (qty_phys_copy_sugg
);
414 CLEAR (qty_phys_num_copy_sugg
);
415 CLEAR (qty_phys_sugg
);
416 CLEAR (qty_phys_num_sugg
);
421 block_alloc (b
->index
);
425 free (qty_phys_copy_sugg
);
426 free (qty_phys_num_copy_sugg
);
427 free (qty_phys_sugg
);
428 free (qty_phys_num_sugg
);
432 free (reg_next_in_qty
);
434 return recorded_label_ref
;
437 /* Used for communication between the following two functions: contains
438 a MEM that we wish to ensure remains unchanged. */
439 static rtx equiv_mem
;
441 /* Set nonzero if EQUIV_MEM is modified. */
442 static int equiv_mem_modified
;
444 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
445 Called via note_stores. */
448 validate_equiv_mem_from_store (rtx dest
, rtx set ATTRIBUTE_UNUSED
,
449 void *data ATTRIBUTE_UNUSED
)
452 && reg_overlap_mentioned_p (dest
, equiv_mem
))
454 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
455 equiv_mem_modified
= 1;
458 /* Verify that no store between START and the death of REG invalidates
459 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
460 by storing into an overlapping memory location, or with a non-const
463 Return 1 if MEMREF remains valid. */
466 validate_equiv_mem (rtx start
, rtx reg
, rtx memref
)
472 equiv_mem_modified
= 0;
474 /* If the memory reference has side effects or is volatile, it isn't a
475 valid equivalence. */
476 if (side_effects_p (memref
))
479 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
484 if (find_reg_note (insn
, REG_DEAD
, reg
))
487 if (CALL_P (insn
) && ! RTX_UNCHANGING_P (memref
)
488 && ! CONST_OR_PURE_CALL_P (insn
))
491 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
493 /* If a register mentioned in MEMREF is modified via an
494 auto-increment, we lose the equivalence. Do the same if one
495 dies; although we could extend the life, it doesn't seem worth
498 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
499 if ((REG_NOTE_KIND (note
) == REG_INC
500 || REG_NOTE_KIND (note
) == REG_DEAD
)
501 && REG_P (XEXP (note
, 0))
502 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
509 /* Returns zero if X is known to be invariant. */
512 equiv_init_varies_p (rtx x
)
514 RTX_CODE code
= GET_CODE (x
);
521 return ! RTX_UNCHANGING_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
535 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
538 if (MEM_VOLATILE_P (x
))
547 fmt
= GET_RTX_FORMAT (code
);
548 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
551 if (equiv_init_varies_p (XEXP (x
, i
)))
554 else if (fmt
[i
] == 'E')
557 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
558 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
565 /* Returns nonzero if X (used to initialize register REGNO) is movable.
566 X is only movable if the registers it uses have equivalent initializations
567 which appear to be within the same loop (or in an inner loop) and movable
568 or if they are not candidates for local_alloc and don't vary. */
571 equiv_init_movable_p (rtx x
, int regno
)
575 enum rtx_code code
= GET_CODE (x
);
580 return equiv_init_movable_p (SET_SRC (x
), regno
);
595 return (reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
596 && reg_equiv
[REGNO (x
)].replace
)
597 || (REG_BASIC_BLOCK (REGNO (x
)) < 0 && ! rtx_varies_p (x
, 0));
599 case UNSPEC_VOLATILE
:
603 if (MEM_VOLATILE_P (x
))
612 fmt
= GET_RTX_FORMAT (code
);
613 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
617 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
621 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
622 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
630 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
633 contains_replace_regs (rtx x
)
637 enum rtx_code code
= GET_CODE (x
);
653 return reg_equiv
[REGNO (x
)].replace
;
659 fmt
= GET_RTX_FORMAT (code
);
660 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
664 if (contains_replace_regs (XEXP (x
, i
)))
668 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
669 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
677 /* TRUE if X references a memory location that would be affected by a store
681 memref_referenced_p (rtx memref
, rtx x
)
685 enum rtx_code code
= GET_CODE (x
);
702 return (reg_equiv
[REGNO (x
)].replacement
703 && memref_referenced_p (memref
,
704 reg_equiv
[REGNO (x
)].replacement
));
707 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
712 /* If we are setting a MEM, it doesn't count (its address does), but any
713 other SET_DEST that has a MEM in it is referencing the MEM. */
714 if (MEM_P (SET_DEST (x
)))
716 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
719 else if (memref_referenced_p (memref
, SET_DEST (x
)))
722 return memref_referenced_p (memref
, SET_SRC (x
));
728 fmt
= GET_RTX_FORMAT (code
);
729 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
733 if (memref_referenced_p (memref
, XEXP (x
, i
)))
737 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
738 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
746 /* TRUE if some insn in the range (START, END] references a memory location
747 that would be affected by a store to MEMREF. */
750 memref_used_between_p (rtx memref
, rtx start
, rtx end
)
754 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
755 insn
= NEXT_INSN (insn
))
756 if (INSN_P (insn
) && memref_referenced_p (memref
, PATTERN (insn
)))
762 /* Find registers that are equivalent to a single value throughout the
763 compilation (either because they can be referenced in memory or are set once
764 from a single constant). Lower their priority for a register.
766 If such a register is only referenced once, try substituting its value
767 into the using insn. If it succeeds, we can eliminate the register
771 update_equiv_regs (void)
776 regset_head cleared_regs
;
777 int clear_regnos
= 0;
779 reg_equiv
= xcalloc (max_regno
, sizeof *reg_equiv
);
780 INIT_REG_SET (&cleared_regs
);
782 init_alias_analysis ();
784 /* Scan the insns and find which registers have equivalences. Do this
785 in a separate scan of the insns because (due to -fcse-follow-jumps)
786 a register can be set below its use. */
789 loop_depth
= bb
->loop_depth
;
791 for (insn
= BB_HEAD (bb
);
792 insn
!= NEXT_INSN (BB_END (bb
));
793 insn
= NEXT_INSN (insn
))
803 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
804 if (REG_NOTE_KIND (note
) == REG_INC
)
805 no_equiv (XEXP (note
, 0), note
, NULL
);
807 set
= single_set (insn
);
809 /* If this insn contains more (or less) than a single SET,
810 only mark all destinations as having no known equivalence. */
813 note_stores (PATTERN (insn
), no_equiv
, NULL
);
816 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
820 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
822 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
824 note_stores (part
, no_equiv
, NULL
);
828 dest
= SET_DEST (set
);
831 /* If this sets a MEM to the contents of a REG that is only used
832 in a single basic block, see if the register is always equivalent
833 to that memory location and if moving the store from INSN to the
834 insn that set REG is safe. If so, put a REG_EQUIV note on the
837 Don't add a REG_EQUIV note if the insn already has one. The existing
838 REG_EQUIV is likely more useful than the one we are adding.
840 If one of the regs in the address has reg_equiv[REGNO].replace set,
841 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
842 optimization may move the set of this register immediately before
843 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
844 the mention in the REG_EQUIV note would be to an uninitialized
846 /* ????? This test isn't good enough; we might see a MEM with a use of
847 a pseudo register before we see its setting insn that will cause
848 reg_equiv[].replace for that pseudo to be set.
849 Equivalences to MEMs should be made in another pass, after the
850 reg_equiv[].replace information has been gathered. */
852 if (MEM_P (dest
) && REG_P (src
)
853 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
854 && REG_BASIC_BLOCK (regno
) >= 0
855 && REG_N_SETS (regno
) == 1
856 && reg_equiv
[regno
].init_insns
!= 0
857 && reg_equiv
[regno
].init_insns
!= const0_rtx
858 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
860 && ! contains_replace_regs (XEXP (dest
, 0)))
862 rtx init_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
863 if (validate_equiv_mem (init_insn
, src
, dest
)
864 && ! memref_used_between_p (dest
, init_insn
, insn
))
865 REG_NOTES (init_insn
)
866 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
869 /* We only handle the case of a pseudo register being set
870 once, or always to the same value. */
871 /* ??? The mn10200 port breaks if we add equivalences for
872 values that need an ADDRESS_REGS register and set them equivalent
873 to a MEM of a pseudo. The actual problem is in the over-conservative
874 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
875 calculate_needs, but we traditionally work around this problem
876 here by rejecting equivalences when the destination is in a register
877 that's likely spilled. This is fragile, of course, since the
878 preferred class of a pseudo depends on all instructions that set
882 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
883 || reg_equiv
[regno
].init_insns
== const0_rtx
884 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
887 /* This might be setting a SUBREG of a pseudo, a pseudo that is
888 also set somewhere else to a constant. */
889 note_stores (set
, no_equiv
, NULL
);
893 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
895 /* cse sometimes generates function invariants, but doesn't put a
896 REG_EQUAL note on the insn. Since this note would be redundant,
897 there's no point creating it earlier than here. */
898 if (! note
&& ! rtx_varies_p (src
, 0))
899 note
= set_unique_reg_note (insn
, REG_EQUAL
, src
);
901 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
902 since it represents a function call */
903 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
906 if (REG_N_SETS (regno
) != 1
908 || rtx_varies_p (XEXP (note
, 0), 0)
909 || (reg_equiv
[regno
].replacement
910 && ! rtx_equal_p (XEXP (note
, 0),
911 reg_equiv
[regno
].replacement
))))
913 no_equiv (dest
, set
, NULL
);
916 /* Record this insn as initializing this register. */
917 reg_equiv
[regno
].init_insns
918 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
920 /* If this register is known to be equal to a constant, record that
921 it is always equivalent to the constant. */
922 if (note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
923 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
925 /* If this insn introduces a "constant" register, decrease the priority
926 of that register. Record this insn if the register is only used once
927 more and the equivalence value is the same as our source.
929 The latter condition is checked for two reasons: First, it is an
930 indication that it may be more efficient to actually emit the insn
931 as written (if no registers are available, reload will substitute
932 the equivalence). Secondly, it avoids problems with any registers
933 dying in this insn whose death notes would be missed.
935 If we don't have a REG_EQUIV note, see if this insn is loading
936 a register used only in one basic block from a MEM. If so, and the
937 MEM remains unchanged for the life of the register, add a REG_EQUIV
940 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
942 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
943 && MEM_P (SET_SRC (set
))
944 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
945 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
950 int regno
= REGNO (dest
);
952 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
953 We might end up substituting the LABEL_REF for uses of the
954 pseudo here or later. That kind of transformation may turn an
955 indirect jump into a direct jump, in which case we must rerun the
956 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
957 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
958 || (GET_CODE (XEXP (note
, 0)) == CONST
959 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
960 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
962 recorded_label_ref
= 1;
964 reg_equiv
[regno
].replacement
= XEXP (note
, 0);
965 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
966 reg_equiv
[regno
].loop_depth
= loop_depth
;
968 /* Don't mess with things live during setjmp. */
969 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
971 /* Note that the statement below does not affect the priority
973 REG_LIVE_LENGTH (regno
) *= 2;
976 /* If the register is referenced exactly twice, meaning it is
977 set once and used once, indicate that the reference may be
978 replaced by the equivalence we computed above. Do this
979 even if the register is only used in one block so that
980 dependencies can be handled where the last register is
981 used in a different block (i.e. HIGH / LO_SUM sequences)
982 and to reduce the number of registers alive across
985 if (REG_N_REFS (regno
) == 2
986 && (rtx_equal_p (XEXP (note
, 0), src
)
987 || ! equiv_init_varies_p (src
))
988 && NONJUMP_INSN_P (insn
)
989 && equiv_init_movable_p (PATTERN (insn
), regno
))
990 reg_equiv
[regno
].replace
= 1;
996 /* Now scan all regs killed in an insn to see if any of them are
997 registers only used that once. If so, see if we can replace the
998 reference with the equivalent from. If we can, delete the
999 initializing reference and this register will go away. If we
1000 can't replace the reference, and the initializing reference is
1001 within the same loop (or in an inner loop), then move the register
1002 initialization just before the use, so that they are in the same
1004 FOR_EACH_BB_REVERSE (bb
)
1006 loop_depth
= bb
->loop_depth
;
1007 for (insn
= BB_END (bb
);
1008 insn
!= PREV_INSN (BB_HEAD (bb
));
1009 insn
= PREV_INSN (insn
))
1013 if (! INSN_P (insn
))
1016 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1018 if (REG_NOTE_KIND (link
) == REG_DEAD
1019 /* Make sure this insn still refers to the register. */
1020 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
1022 int regno
= REGNO (XEXP (link
, 0));
1025 if (! reg_equiv
[regno
].replace
1026 || reg_equiv
[regno
].loop_depth
< loop_depth
)
1029 /* reg_equiv[REGNO].replace gets set only when
1030 REG_N_REFS[REGNO] is 2, i.e. the register is set
1031 once and used once. (If it were only set, but not used,
1032 flow would have deleted the setting insns.) Hence
1033 there can only be one insn in reg_equiv[REGNO].init_insns. */
1034 if (reg_equiv
[regno
].init_insns
== NULL_RTX
1035 || XEXP (reg_equiv
[regno
].init_insns
, 1) != NULL_RTX
)
1037 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
1039 /* We may not move instructions that can throw, since
1040 that changes basic block boundaries and we are not
1041 prepared to adjust the CFG to match. */
1042 if (can_throw_internal (equiv_insn
))
1045 if (asm_noperands (PATTERN (equiv_insn
)) < 0
1046 && validate_replace_rtx (regno_reg_rtx
[regno
],
1047 *(reg_equiv
[regno
].src_p
), insn
))
1053 /* Find the last note. */
1054 for (last_link
= link
; XEXP (last_link
, 1);
1055 last_link
= XEXP (last_link
, 1))
1058 /* Append the REG_DEAD notes from equiv_insn. */
1059 equiv_link
= REG_NOTES (equiv_insn
);
1063 equiv_link
= XEXP (equiv_link
, 1);
1064 if (REG_NOTE_KIND (note
) == REG_DEAD
)
1066 remove_note (equiv_insn
, note
);
1067 XEXP (last_link
, 1) = note
;
1068 XEXP (note
, 1) = NULL_RTX
;
1073 remove_death (regno
, insn
);
1074 REG_N_REFS (regno
) = 0;
1075 REG_FREQ (regno
) = 0;
1076 delete_insn (equiv_insn
);
1078 reg_equiv
[regno
].init_insns
1079 = XEXP (reg_equiv
[regno
].init_insns
, 1);
1081 /* Move the initialization of the register to just before
1082 INSN. Update the flow information. */
1083 else if (PREV_INSN (insn
) != equiv_insn
)
1087 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
1088 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
1089 REG_NOTES (equiv_insn
) = 0;
1091 /* Make sure this insn is recognized before reload begins,
1092 otherwise eliminate_regs_in_insn will abort. */
1093 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
1095 delete_insn (equiv_insn
);
1097 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
1099 REG_BASIC_BLOCK (regno
) = bb
->index
;
1100 REG_N_CALLS_CROSSED (regno
) = 0;
1101 REG_LIVE_LENGTH (regno
) = 2;
1103 if (insn
== BB_HEAD (bb
))
1104 BB_HEAD (bb
) = PREV_INSN (insn
);
1106 /* Remember to clear REGNO from all basic block's live
1108 SET_REGNO_REG_SET (&cleared_regs
, regno
);
1116 /* Clear all dead REGNOs from all basic block's live info. */
1120 if (clear_regnos
> 8)
1124 AND_COMPL_REG_SET (bb
->global_live_at_start
, &cleared_regs
);
1125 AND_COMPL_REG_SET (bb
->global_live_at_end
, &cleared_regs
);
1129 EXECUTE_IF_SET_IN_REG_SET (&cleared_regs
, 0, j
,
1133 CLEAR_REGNO_REG_SET (bb
->global_live_at_start
, j
);
1134 CLEAR_REGNO_REG_SET (bb
->global_live_at_end
, j
);
1140 end_alias_analysis ();
1141 CLEAR_REG_SET (&cleared_regs
);
1145 /* Mark REG as having no known equivalence.
1146 Some instructions might have been processed before and furnished
1147 with REG_EQUIV notes for this register; these notes will have to be
1149 STORE is the piece of RTL that does the non-constant / conflicting
1150 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1151 but needs to be there because this function is called from note_stores. */
1153 no_equiv (rtx reg
, rtx store ATTRIBUTE_UNUSED
, void *data ATTRIBUTE_UNUSED
)
1160 regno
= REGNO (reg
);
1161 list
= reg_equiv
[regno
].init_insns
;
1162 if (list
== const0_rtx
)
1164 for (; list
; list
= XEXP (list
, 1))
1166 rtx insn
= XEXP (list
, 0);
1167 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1169 reg_equiv
[regno
].init_insns
= const0_rtx
;
1170 reg_equiv
[regno
].replacement
= NULL_RTX
;
1173 /* Allocate hard regs to the pseudo regs used only within block number B.
1174 Only the pseudos that die but once can be handled. */
1182 int insn_number
= 0;
1184 int max_uid
= get_max_uid ();
1186 int no_conflict_combined_regno
= -1;
1188 /* Count the instructions in the basic block. */
1190 insn
= BB_END (BASIC_BLOCK (b
));
1194 if (++insn_count
> max_uid
)
1196 if (insn
== BB_HEAD (BASIC_BLOCK (b
)))
1198 insn
= PREV_INSN (insn
);
1201 /* +2 to leave room for a post_mark_life at the last insn and for
1202 the birth of a CLOBBER in the first insn. */
1203 regs_live_at
= xcalloc ((2 * insn_count
+ 2), sizeof (HARD_REG_SET
));
1205 /* Initialize table of hardware registers currently live. */
1207 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1209 /* This loop scans the instructions of the basic block
1210 and assigns quantities to registers.
1211 It computes which registers to tie. */
1213 insn
= BB_HEAD (BASIC_BLOCK (b
));
1223 rtx r0
, r1
= NULL_RTX
;
1224 int combined_regno
= -1;
1227 this_insn_number
= insn_number
;
1230 extract_insn (insn
);
1231 which_alternative
= -1;
1233 /* Is this insn suitable for tying two registers?
1234 If so, try doing that.
1235 Suitable insns are those with at least two operands and where
1236 operand 0 is an output that is a register that is not
1239 We can tie operand 0 with some operand that dies in this insn.
1240 First look for operands that are required to be in the same
1241 register as operand 0. If we find such, only try tying that
1242 operand or one that can be put into that operand if the
1243 operation is commutative. If we don't find an operand
1244 that is required to be in the same register as operand 0,
1245 we can tie with any operand.
1247 Subregs in place of regs are also ok.
1249 If tying is done, WIN is set nonzero. */
1252 && recog_data
.n_operands
> 1
1253 && recog_data
.constraints
[0][0] == '='
1254 && recog_data
.constraints
[0][1] != '&')
1256 /* If non-negative, is an operand that must match operand 0. */
1257 int must_match_0
= -1;
1258 /* Counts number of alternatives that require a match with
1260 int n_matching_alts
= 0;
1262 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1264 const char *p
= recog_data
.constraints
[i
];
1265 int this_match
= requires_inout (p
);
1267 n_matching_alts
+= this_match
;
1268 if (this_match
== recog_data
.n_alternatives
)
1272 r0
= recog_data
.operand
[0];
1273 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1275 /* Skip this operand if we found an operand that
1276 must match operand 0 and this operand isn't it
1277 and can't be made to be it by commutativity. */
1279 if (must_match_0
>= 0 && i
!= must_match_0
1280 && ! (i
== must_match_0
+ 1
1281 && recog_data
.constraints
[i
-1][0] == '%')
1282 && ! (i
== must_match_0
- 1
1283 && recog_data
.constraints
[i
][0] == '%'))
1286 /* Likewise if each alternative has some operand that
1287 must match operand zero. In that case, skip any
1288 operand that doesn't list operand 0 since we know that
1289 the operand always conflicts with operand 0. We
1290 ignore commutativity in this case to keep things simple. */
1291 if (n_matching_alts
== recog_data
.n_alternatives
1292 && 0 == requires_inout (recog_data
.constraints
[i
]))
1295 r1
= recog_data
.operand
[i
];
1297 /* If the operand is an address, find a register in it.
1298 There may be more than one register, but we only try one
1300 if (recog_data
.constraints
[i
][0] == 'p'
1301 || EXTRA_ADDRESS_CONSTRAINT (recog_data
.constraints
[i
][0],
1302 recog_data
.constraints
[i
]))
1303 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1306 /* Avoid making a call-saved register unnecessarily
1308 hard_reg
= get_hard_reg_initial_reg (cfun
, r1
);
1309 if (hard_reg
!= NULL_RTX
)
1311 if (REG_P (hard_reg
)
1312 && IN_RANGE (REGNO (hard_reg
),
1313 0, FIRST_PSEUDO_REGISTER
- 1)
1314 && ! call_used_regs
[REGNO (hard_reg
)])
1318 if (REG_P (r0
) || GET_CODE (r0
) == SUBREG
)
1320 /* We have two priorities for hard register preferences.
1321 If we have a move insn or an insn whose first input
1322 can only be in the same register as the output, give
1323 priority to an equivalence found from that insn. */
1325 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1327 if (REG_P (r1
) || GET_CODE (r1
) == SUBREG
)
1328 win
= combine_regs (r1
, r0
, may_save_copy
,
1329 insn_number
, insn
, 0);
1336 /* Recognize an insn sequence with an ultimate result
1337 which can safely overlap one of the inputs.
1338 The sequence begins with a CLOBBER of its result,
1339 and ends with an insn that copies the result to itself
1340 and has a REG_EQUAL note for an equivalent formula.
1341 That note indicates what the inputs are.
1342 The result and the input can overlap if each insn in
1343 the sequence either doesn't mention the input
1344 or has a REG_NO_CONFLICT note to inhibit the conflict.
1346 We do the combining test at the CLOBBER so that the
1347 destination register won't have had a quantity number
1348 assigned, since that would prevent combining. */
1351 && GET_CODE (PATTERN (insn
)) == CLOBBER
1352 && (r0
= XEXP (PATTERN (insn
), 0),
1354 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1355 && XEXP (link
, 0) != 0
1356 && NONJUMP_INSN_P (XEXP (link
, 0))
1357 && (set
= single_set (XEXP (link
, 0))) != 0
1358 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1359 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1362 if (r1
= XEXP (note
, 0), REG_P (r1
)
1363 /* Check that we have such a sequence. */
1364 && no_conflict_p (insn
, r0
, r1
))
1365 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1366 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1367 && (r1
= XEXP (XEXP (note
, 0), 0),
1368 REG_P (r1
) || GET_CODE (r1
) == SUBREG
)
1369 && no_conflict_p (insn
, r0
, r1
))
1370 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1372 /* Here we care if the operation to be computed is
1374 else if (COMMUTATIVE_P (XEXP (note
, 0))
1375 && (r1
= XEXP (XEXP (note
, 0), 1),
1376 (REG_P (r1
) || GET_CODE (r1
) == SUBREG
))
1377 && no_conflict_p (insn
, r0
, r1
))
1378 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1380 /* If we did combine something, show the register number
1381 in question so that we know to ignore its death. */
1383 no_conflict_combined_regno
= REGNO (r1
);
1386 /* If registers were just tied, set COMBINED_REGNO
1387 to the number of the register used in this insn
1388 that was tied to the register set in this insn.
1389 This register's qty should not be "killed". */
1393 while (GET_CODE (r1
) == SUBREG
)
1394 r1
= SUBREG_REG (r1
);
1395 combined_regno
= REGNO (r1
);
1398 /* Mark the death of everything that dies in this instruction,
1399 except for anything that was just combined. */
1401 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1402 if (REG_NOTE_KIND (link
) == REG_DEAD
1403 && REG_P (XEXP (link
, 0))
1404 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1405 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1406 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1408 wipe_dead_reg (XEXP (link
, 0), 0);
1410 /* Allocate qty numbers for all registers local to this block
1411 that are born (set) in this instruction.
1412 A pseudo that already has a qty is not changed. */
1414 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1416 /* If anything is set in this insn and then unused, mark it as dying
1417 after this insn, so it will conflict with our outputs. This
1418 can't match with something that combined, and it doesn't matter
1419 if it did. Do this after the calls to reg_is_set since these
1420 die after, not during, the current insn. */
1422 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1423 if (REG_NOTE_KIND (link
) == REG_UNUSED
1424 && REG_P (XEXP (link
, 0)))
1425 wipe_dead_reg (XEXP (link
, 0), 1);
1427 /* If this is an insn that has a REG_RETVAL note pointing at a
1428 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1429 block, so clear any register number that combined within it. */
1430 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1431 && NONJUMP_INSN_P (XEXP (note
, 0))
1432 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1433 no_conflict_combined_regno
= -1;
1436 /* Set the registers live after INSN_NUMBER. Note that we never
1437 record the registers live before the block's first insn, since no
1438 pseudos we care about are live before that insn. */
1440 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1441 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1443 if (insn
== BB_END (BASIC_BLOCK (b
)))
1446 insn
= NEXT_INSN (insn
);
1449 /* Now every register that is local to this basic block
1450 should have been given a quantity, or else -1 meaning ignore it.
1451 Every quantity should have a known birth and death.
1453 Order the qtys so we assign them registers in order of the
1454 number of suggested registers they need so we allocate those with
1455 the most restrictive needs first. */
1457 qty_order
= xmalloc (next_qty
* sizeof (int));
1458 for (i
= 0; i
< next_qty
; i
++)
1461 #define EXCHANGE(I1, I2) \
1462 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1467 /* Make qty_order[2] be the one to allocate last. */
1468 if (qty_sugg_compare (0, 1) > 0)
1470 if (qty_sugg_compare (1, 2) > 0)
1473 /* ... Fall through ... */
1475 /* Put the best one to allocate in qty_order[0]. */
1476 if (qty_sugg_compare (0, 1) > 0)
1479 /* ... Fall through ... */
1483 /* Nothing to do here. */
1487 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1490 /* Try to put each quantity in a suggested physical register, if it has one.
1491 This may cause registers to be allocated that otherwise wouldn't be, but
1492 this seems acceptable in local allocation (unlike global allocation). */
1493 for (i
= 0; i
< next_qty
; i
++)
1496 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1497 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1498 0, 1, qty
[q
].birth
, qty
[q
].death
);
1500 qty
[q
].phys_reg
= -1;
1503 /* Order the qtys so we assign them registers in order of
1504 decreasing length of life. Normally call qsort, but if we
1505 have only a very small number of quantities, sort them ourselves. */
1507 for (i
= 0; i
< next_qty
; i
++)
1510 #define EXCHANGE(I1, I2) \
1511 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1516 /* Make qty_order[2] be the one to allocate last. */
1517 if (qty_compare (0, 1) > 0)
1519 if (qty_compare (1, 2) > 0)
1522 /* ... Fall through ... */
1524 /* Put the best one to allocate in qty_order[0]. */
1525 if (qty_compare (0, 1) > 0)
1528 /* ... Fall through ... */
1532 /* Nothing to do here. */
1536 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1539 /* Now for each qty that is not a hardware register,
1540 look for a hardware register to put it in.
1541 First try the register class that is cheapest for this qty,
1542 if there is more than one class. */
1544 for (i
= 0; i
< next_qty
; i
++)
1547 if (qty
[q
].phys_reg
< 0)
1549 #ifdef INSN_SCHEDULING
1550 /* These values represent the adjusted lifetime of a qty so
1551 that it conflicts with qtys which appear near the start/end
1552 of this qty's lifetime.
1554 The purpose behind extending the lifetime of this qty is to
1555 discourage the register allocator from creating false
1558 The adjustment value is chosen to indicate that this qty
1559 conflicts with all the qtys in the instructions immediately
1560 before and after the lifetime of this qty.
1562 Experiments have shown that higher values tend to hurt
1563 overall code performance.
1565 If allocation using the extended lifetime fails we will try
1566 again with the qty's unadjusted lifetime. */
1567 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1568 int fake_death
= MIN (insn_number
* 2 + 1,
1569 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1572 if (N_REG_CLASSES
> 1)
1574 #ifdef INSN_SCHEDULING
1575 /* We try to avoid using hard registers allocated to qtys which
1576 are born immediately after this qty or die immediately before
1579 This optimization is only appropriate when we will run
1580 a scheduling pass after reload and we are not optimizing
1582 if (flag_schedule_insns_after_reload
1584 && !SMALL_REGISTER_CLASSES
)
1586 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1587 qty
[q
].mode
, q
, 0, 0,
1588 fake_birth
, fake_death
);
1589 if (qty
[q
].phys_reg
>= 0)
1593 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1594 qty
[q
].mode
, q
, 0, 0,
1595 qty
[q
].birth
, qty
[q
].death
);
1596 if (qty
[q
].phys_reg
>= 0)
1600 #ifdef INSN_SCHEDULING
1601 /* Similarly, avoid false dependencies. */
1602 if (flag_schedule_insns_after_reload
1604 && !SMALL_REGISTER_CLASSES
1605 && qty
[q
].alternate_class
!= NO_REGS
)
1606 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1607 qty
[q
].mode
, q
, 0, 0,
1608 fake_birth
, fake_death
);
1610 if (qty
[q
].alternate_class
!= NO_REGS
)
1611 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1612 qty
[q
].mode
, q
, 0, 0,
1613 qty
[q
].birth
, qty
[q
].death
);
1617 /* Now propagate the register assignments
1618 to the pseudo regs belonging to the qtys. */
1620 for (q
= 0; q
< next_qty
; q
++)
1621 if (qty
[q
].phys_reg
>= 0)
1623 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1624 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1628 free (regs_live_at
);
1632 /* Compare two quantities' priority for getting real registers.
1633 We give shorter-lived quantities higher priority.
1634 Quantities with more references are also preferred, as are quantities that
1635 require multiple registers. This is the identical prioritization as
1636 done by global-alloc.
1638 We used to give preference to registers with *longer* lives, but using
1639 the same algorithm in both local- and global-alloc can speed up execution
1640 of some programs by as much as a factor of three! */
1642 /* Note that the quotient will never be bigger than
1643 the value of floor_log2 times the maximum number of
1644 times a register can occur in one insn (surely less than 100)
1645 weighted by frequency (max REG_FREQ_MAX).
1646 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1647 QTY_CMP_PRI is also used by qty_sugg_compare. */
1649 #define QTY_CMP_PRI(q) \
1650 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1651 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1654 qty_compare (int q1
, int q2
)
1656 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1660 qty_compare_1 (const void *q1p
, const void *q2p
)
1662 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1663 int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1668 /* If qtys are equally good, sort by qty number,
1669 so that the results of qsort leave nothing to chance. */
1673 /* Compare two quantities' priority for getting real registers. This version
1674 is called for quantities that have suggested hard registers. First priority
1675 goes to quantities that have copy preferences, then to those that have
1676 normal preferences. Within those groups, quantities with the lower
1677 number of preferences have the highest priority. Of those, we use the same
1678 algorithm as above. */
1680 #define QTY_CMP_SUGG(q) \
1681 (qty_phys_num_copy_sugg[q] \
1682 ? qty_phys_num_copy_sugg[q] \
1683 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1686 qty_sugg_compare (int q1
, int q2
)
1688 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1693 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1697 qty_sugg_compare_1 (const void *q1p
, const void *q2p
)
1699 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1700 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1705 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1709 /* If qtys are equally good, sort by qty number,
1710 so that the results of qsort leave nothing to chance. */
1717 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1718 Returns 1 if have done so, or 0 if cannot.
1720 Combining registers means marking them as having the same quantity
1721 and adjusting the offsets within the quantity if either of
1724 We don't actually combine a hard reg with a pseudo; instead
1725 we just record the hard reg as the suggestion for the pseudo's quantity.
1726 If we really combined them, we could lose if the pseudo lives
1727 across an insn that clobbers the hard reg (eg, movmem).
1729 ALREADY_DEAD is nonzero if USEDREG is known to be dead even though
1730 there is no REG_DEAD note on INSN. This occurs during the processing
1731 of REG_NO_CONFLICT blocks.
1733 MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to
1734 SETREG or if the input and output must share a register.
1735 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1737 There are elaborate checks for the validity of combining. */
1740 combine_regs (rtx usedreg
, rtx setreg
, int may_save_copy
, int insn_number
,
1741 rtx insn
, int already_dead
)
1748 /* Determine the numbers and sizes of registers being used. If a subreg
1749 is present that does not change the entire register, don't consider
1750 this a copy insn. */
1752 while (GET_CODE (usedreg
) == SUBREG
)
1754 rtx subreg
= SUBREG_REG (usedreg
);
1758 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1761 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1762 offset
+= subreg_regno_offset (REGNO (subreg
),
1764 SUBREG_BYTE (usedreg
),
1765 GET_MODE (usedreg
));
1767 offset
+= (SUBREG_BYTE (usedreg
)
1768 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1774 if (!REG_P (usedreg
))
1777 ureg
= REGNO (usedreg
);
1778 if (ureg
< FIRST_PSEUDO_REGISTER
)
1779 usize
= hard_regno_nregs
[ureg
][GET_MODE (usedreg
)];
1781 usize
= ((GET_MODE_SIZE (GET_MODE (usedreg
))
1782 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)) - 1))
1783 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1785 while (GET_CODE (setreg
) == SUBREG
)
1787 rtx subreg
= SUBREG_REG (setreg
);
1791 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1794 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1795 offset
-= subreg_regno_offset (REGNO (subreg
),
1797 SUBREG_BYTE (setreg
),
1800 offset
-= (SUBREG_BYTE (setreg
)
1801 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1807 if (!REG_P (setreg
))
1810 sreg
= REGNO (setreg
);
1811 if (sreg
< FIRST_PSEUDO_REGISTER
)
1812 ssize
= hard_regno_nregs
[sreg
][GET_MODE (setreg
)];
1814 ssize
= ((GET_MODE_SIZE (GET_MODE (setreg
))
1815 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg
)) - 1))
1816 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1818 /* If UREG is a pseudo-register that hasn't already been assigned a
1819 quantity number, it means that it is not local to this block or dies
1820 more than once. In either event, we can't do anything with it. */
1821 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1822 /* Do not combine registers unless one fits within the other. */
1823 || (offset
> 0 && usize
+ offset
> ssize
)
1824 || (offset
< 0 && usize
+ offset
< ssize
)
1825 /* Do not combine with a smaller already-assigned object
1826 if that smaller object is already combined with something bigger. */
1827 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1828 && usize
< qty
[reg_qty
[ureg
]].size
)
1829 /* Can't combine if SREG is not a register we can allocate. */
1830 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1831 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1832 These have already been taken care of. This probably wouldn't
1833 combine anyway, but don't take any chances. */
1834 || (ureg
>= FIRST_PSEUDO_REGISTER
1835 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1836 /* Don't tie something to itself. In most cases it would make no
1837 difference, but it would screw up if the reg being tied to itself
1838 also dies in this insn. */
1840 /* Don't try to connect two different hardware registers. */
1841 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1842 /* Don't connect two different machine modes if they have different
1843 implications as to which registers may be used. */
1844 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1847 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1848 qty_phys_sugg for the pseudo instead of tying them.
1850 Return "failure" so that the lifespan of UREG is terminated here;
1851 that way the two lifespans will be disjoint and nothing will prevent
1852 the pseudo reg from being given this hard reg. */
1854 if (ureg
< FIRST_PSEUDO_REGISTER
)
1856 /* Allocate a quantity number so we have a place to put our
1858 if (reg_qty
[sreg
] == -2)
1859 reg_is_born (setreg
, 2 * insn_number
);
1861 if (reg_qty
[sreg
] >= 0)
1864 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1866 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1867 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1869 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1871 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1872 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1878 /* Similarly for SREG a hard register and UREG a pseudo register. */
1880 if (sreg
< FIRST_PSEUDO_REGISTER
)
1883 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1885 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1886 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1888 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1890 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1891 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1896 /* At this point we know that SREG and UREG are both pseudos.
1897 Do nothing if SREG already has a quantity or is a register that we
1899 if (reg_qty
[sreg
] >= -1
1900 /* If we are not going to let any regs live across calls,
1901 don't tie a call-crossing reg to a non-call-crossing reg. */
1902 || (current_function_has_nonlocal_label
1903 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1904 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1907 /* We don't already know about SREG, so tie it to UREG
1908 if this is the last use of UREG, provided the classes they want
1911 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1912 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
1914 /* Add SREG to UREG's quantity. */
1915 sqty
= reg_qty
[ureg
];
1916 reg_qty
[sreg
] = sqty
;
1917 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1918 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
1919 qty
[sqty
].first_reg
= sreg
;
1921 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1922 update_qty_class (sqty
, sreg
);
1924 /* Update info about quantity SQTY. */
1925 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
1926 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
1927 qty
[sqty
].freq
+= REG_FREQ (sreg
);
1932 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1933 reg_offset
[i
] -= offset
;
1935 qty
[sqty
].size
= ssize
;
1936 qty
[sqty
].mode
= GET_MODE (setreg
);
1945 /* Return 1 if the preferred class of REG allows it to be tied
1946 to a quantity or register whose class is CLASS.
1947 True if REG's reg class either contains or is contained in CLASS. */
1950 reg_meets_class_p (int reg
, enum reg_class
class)
1952 enum reg_class rclass
= reg_preferred_class (reg
);
1953 return (reg_class_subset_p (rclass
, class)
1954 || reg_class_subset_p (class, rclass
));
1957 /* Update the class of QTYNO assuming that REG is being tied to it. */
1960 update_qty_class (int qtyno
, int reg
)
1962 enum reg_class rclass
= reg_preferred_class (reg
);
1963 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
1964 qty
[qtyno
].min_class
= rclass
;
1966 rclass
= reg_alternate_class (reg
);
1967 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
1968 qty
[qtyno
].alternate_class
= rclass
;
1971 /* Handle something which alters the value of an rtx REG.
1973 REG is whatever is set or clobbered. SETTER is the rtx that
1974 is modifying the register.
1976 If it is not really a register, we do nothing.
1977 The file-global variables `this_insn' and `this_insn_number'
1978 carry info from `block_alloc'. */
1981 reg_is_set (rtx reg
, rtx setter
, void *data ATTRIBUTE_UNUSED
)
1983 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1984 a hard register. These may actually not exist any more. */
1986 if (GET_CODE (reg
) != SUBREG
1990 /* Mark this register as being born. If it is used in a CLOBBER, mark
1991 it as being born halfway between the previous insn and this insn so that
1992 it conflicts with our inputs but not the outputs of the previous insn. */
1994 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
1997 /* Handle beginning of the life of register REG.
1998 BIRTH is the index at which this is happening. */
2001 reg_is_born (rtx reg
, int birth
)
2005 if (GET_CODE (reg
) == SUBREG
)
2007 regno
= REGNO (SUBREG_REG (reg
));
2008 if (regno
< FIRST_PSEUDO_REGISTER
)
2009 regno
= subreg_hard_regno (reg
, 1);
2012 regno
= REGNO (reg
);
2014 if (regno
< FIRST_PSEUDO_REGISTER
)
2016 mark_life (regno
, GET_MODE (reg
), 1);
2018 /* If the register was to have been born earlier that the present
2019 insn, mark it as live where it is actually born. */
2020 if (birth
< 2 * this_insn_number
)
2021 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
2025 if (reg_qty
[regno
] == -2)
2026 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
2028 /* If this register has a quantity number, show that it isn't dead. */
2029 if (reg_qty
[regno
] >= 0)
2030 qty
[reg_qty
[regno
]].death
= -1;
2034 /* Record the death of REG in the current insn. If OUTPUT_P is nonzero,
2035 REG is an output that is dying (i.e., it is never used), otherwise it
2036 is an input (the normal case).
2037 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2040 wipe_dead_reg (rtx reg
, int output_p
)
2042 int regno
= REGNO (reg
);
2044 /* If this insn has multiple results,
2045 and the dead reg is used in one of the results,
2046 extend its life to after this insn,
2047 so it won't get allocated together with any other result of this insn.
2049 It is unsafe to use !single_set here since it will ignore an unused
2050 output. Just because an output is unused does not mean the compiler
2051 can assume the side effect will not occur. Consider if REG appears
2052 in the address of an output and we reload the output. If we allocate
2053 REG to the same hard register as an unused output we could set the hard
2054 register before the output reload insn. */
2055 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
2056 && multiple_sets (this_insn
))
2059 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
2061 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
2062 if (GET_CODE (set
) == SET
2063 && !REG_P (SET_DEST (set
))
2064 && !rtx_equal_p (reg
, SET_DEST (set
))
2065 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2070 /* If this register is used in an auto-increment address, then extend its
2071 life to after this insn, so that it won't get allocated together with
2072 the result of this insn. */
2073 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
2076 if (regno
< FIRST_PSEUDO_REGISTER
)
2078 mark_life (regno
, GET_MODE (reg
), 0);
2080 /* If a hard register is dying as an output, mark it as in use at
2081 the beginning of this insn (the above statement would cause this
2084 post_mark_life (regno
, GET_MODE (reg
), 1,
2085 2 * this_insn_number
, 2 * this_insn_number
+ 1);
2088 else if (reg_qty
[regno
] >= 0)
2089 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
2092 /* Find a block of SIZE words of hard regs in reg_class CLASS
2093 that can hold something of machine-mode MODE
2094 (but actually we test only the first of the block for holding MODE)
2095 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2096 and return the number of the first of them.
2097 Return -1 if such a block cannot be found.
2098 If QTYNO crosses calls, insist on a register preserved by calls,
2099 unless ACCEPT_CALL_CLOBBERED is nonzero.
2101 If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested
2102 register is available. If not, return -1. */
2105 find_free_reg (enum reg_class
class, enum machine_mode mode
, int qtyno
,
2106 int accept_call_clobbered
, int just_try_suggested
,
2107 int born_index
, int dead_index
)
2110 HARD_REG_SET first_used
, used
;
2111 #ifdef ELIMINABLE_REGS
2112 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2115 /* Validate our parameters. */
2116 if (born_index
< 0 || born_index
> dead_index
)
2119 /* Don't let a pseudo live in a reg across a function call
2120 if we might get a nonlocal goto. */
2121 if (current_function_has_nonlocal_label
2122 && qty
[qtyno
].n_calls_crossed
> 0)
2125 if (accept_call_clobbered
)
2126 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
2127 else if (qty
[qtyno
].n_calls_crossed
== 0)
2128 COPY_HARD_REG_SET (used
, fixed_reg_set
);
2130 COPY_HARD_REG_SET (used
, call_used_reg_set
);
2132 if (accept_call_clobbered
)
2133 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
2135 for (ins
= born_index
; ins
< dead_index
; ins
++)
2136 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
2138 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
2140 /* Don't use the frame pointer reg in local-alloc even if
2141 we may omit the frame pointer, because if we do that and then we
2142 need a frame pointer, reload won't know how to move the pseudo
2143 to another hard reg. It can move only regs made by global-alloc.
2145 This is true of any register that can be eliminated. */
2146 #ifdef ELIMINABLE_REGS
2147 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2148 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
2149 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2150 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2151 that it might be eliminated into. */
2152 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
2155 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
2158 #ifdef CANNOT_CHANGE_MODE_CLASS
2159 cannot_change_mode_set_regs (&used
, mode
, qty
[qtyno
].first_reg
);
2162 /* Normally, the registers that can be used for the first register in
2163 a multi-register quantity are the same as those that can be used for
2164 subsequent registers. However, if just trying suggested registers,
2165 restrict our consideration to them. If there are copy-suggested
2166 register, try them. Otherwise, try the arithmetic-suggested
2168 COPY_HARD_REG_SET (first_used
, used
);
2170 if (just_try_suggested
)
2172 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2173 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2175 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2178 /* If all registers are excluded, we can't do anything. */
2179 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2181 /* If at least one would be suitable, test each hard reg. */
2183 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2185 #ifdef REG_ALLOC_ORDER
2186 int regno
= reg_alloc_order
[i
];
2190 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2191 && HARD_REGNO_MODE_OK (regno
, mode
)
2192 && (qty
[qtyno
].n_calls_crossed
== 0
2193 || accept_call_clobbered
2194 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2197 int size1
= hard_regno_nregs
[regno
][mode
];
2198 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2201 /* Mark that this register is in use between its birth and death
2203 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2206 #ifndef REG_ALLOC_ORDER
2207 /* Skip starting points we know will lose. */
2214 /* If we are just trying suggested register, we have just tried copy-
2215 suggested registers, and there are arithmetic-suggested registers,
2218 /* If it would be profitable to allocate a call-clobbered register
2219 and save and restore it around calls, do that. */
2220 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2221 && qty_phys_num_sugg
[qtyno
] != 0)
2223 /* Don't try the copy-suggested regs again. */
2224 qty_phys_num_copy_sugg
[qtyno
] = 0;
2225 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2226 born_index
, dead_index
);
2229 /* We need not check to see if the current function has nonlocal
2230 labels because we don't put any pseudos that are live over calls in
2231 registers in that case. */
2233 if (! accept_call_clobbered
2234 && flag_caller_saves
2235 && ! just_try_suggested
2236 && qty
[qtyno
].n_calls_crossed
!= 0
2237 && CALLER_SAVE_PROFITABLE (qty
[qtyno
].n_refs
,
2238 qty
[qtyno
].n_calls_crossed
))
2240 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2242 caller_save_needed
= 1;
2248 /* Mark that REGNO with machine-mode MODE is live starting from the current
2249 insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE
2253 mark_life (int regno
, enum machine_mode mode
, int life
)
2255 int j
= hard_regno_nregs
[regno
][mode
];
2258 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2261 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2264 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2265 is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2266 to insn number DEATH (exclusive). */
2269 post_mark_life (int regno
, enum machine_mode mode
, int life
, int birth
,
2272 int j
= hard_regno_nregs
[regno
][mode
];
2273 HARD_REG_SET this_reg
;
2275 CLEAR_HARD_REG_SET (this_reg
);
2277 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2280 while (birth
< death
)
2282 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2286 while (birth
< death
)
2288 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2293 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2294 is the register being clobbered, and R1 is a register being used in
2295 the equivalent expression.
2297 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2298 in which it is used, return 1.
2300 Otherwise, return 0. */
2303 no_conflict_p (rtx insn
, rtx r0 ATTRIBUTE_UNUSED
, rtx r1
)
2306 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2309 /* If R1 is a hard register, return 0 since we handle this case
2310 when we scan the insns that actually use it. */
2313 || (REG_P (r1
) && REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2314 || (GET_CODE (r1
) == SUBREG
&& REG_P (SUBREG_REG (r1
))
2315 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2318 last
= XEXP (note
, 0);
2320 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2323 if (find_reg_note (p
, REG_DEAD
, r1
))
2326 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2327 some earlier optimization pass has inserted instructions into
2328 the sequence, and it is not safe to perform this optimization.
2329 Note that emit_no_conflict_block always ensures that this is
2330 true when these sequences are created. */
2331 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2338 /* Return the number of alternatives for which the constraint string P
2339 indicates that the operand must be equal to operand 0 and that no register
2343 requires_inout (const char *p
)
2347 int reg_allowed
= 0;
2348 int num_matching_alts
= 0;
2351 for ( ; (c
= *p
); p
+= len
)
2353 len
= CONSTRAINT_LEN (c
, p
);
2356 case '=': case '+': case '?':
2357 case '#': case '&': case '!':
2359 case 'm': case '<': case '>': case 'V': case 'o':
2360 case 'E': case 'F': case 'G': case 'H':
2361 case 's': case 'i': case 'n':
2362 case 'I': case 'J': case 'K': case 'L':
2363 case 'M': case 'N': case 'O': case 'P':
2365 /* These don't say anything we care about. */
2369 if (found_zero
&& ! reg_allowed
)
2370 num_matching_alts
++;
2372 found_zero
= reg_allowed
= 0;
2379 case '1': case '2': case '3': case '4': case '5':
2380 case '6': case '7': case '8': case '9':
2381 /* Skip the balance of the matching constraint. */
2384 while (ISDIGIT (*p
));
2389 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
2390 && !EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2400 if (found_zero
&& ! reg_allowed
)
2401 num_matching_alts
++;
2403 return num_matching_alts
;
2407 dump_local_alloc (FILE *file
)
2410 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2411 if (reg_renumber
[i
] != -1)
2412 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);