1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "hard-reg-set.h"
68 #include "basic-block.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
77 /* Next quantity number available for allocation. */
81 /* Information we maitain about each quantity. */
84 /* The number of refs to quantity Q. */
88 /* Insn number (counting from head of basic block)
89 where quantity Q was born. -1 if birth has not been recorded. */
93 /* Insn number (counting from head of basic block)
94 where given quantity died. Due to the way tying is done,
95 and the fact that we consider in this pass only regs that die but once,
96 a quantity can die only once. Each quantity's life span
97 is a set of consecutive insns. -1 if death has not been recorded. */
101 /* Number of words needed to hold the data in given quantity.
102 This depends on its machine mode. It is used for these purposes:
103 1. It is used in computing the relative importances of qtys,
104 which determines the order in which we look for regs for them.
105 2. It is used in rules that prevent tying several registers of
106 different sizes in a way that is geometrically impossible
107 (see combine_regs). */
111 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
115 /* The register number of one pseudo register whose reg_qty value is Q.
116 This register should be the head of the chain
117 maintained in reg_next_in_qty. */
121 /* Reg class contained in (smaller than) the preferred classes of all
122 the pseudo regs that are tied in given quantity.
123 This is the preferred class for allocating that quantity. */
125 enum reg_class min_class
;
127 /* Register class within which we allocate given qty if we can't get
128 its preferred class. */
130 enum reg_class alternate_class
;
132 /* This holds the mode of the registers that are tied to given qty,
133 or VOIDmode if registers with differing modes are tied together. */
135 enum machine_mode mode
;
137 /* the hard reg number chosen for given quantity,
138 or -1 if none was found. */
142 /* Nonzero if this quantity has been used in a SUBREG in some
143 way that is illegal. */
149 static struct qty
*qty
;
151 /* These fields are kept separately to speedup their clearing. */
153 /* We maintain two hard register sets that indicate suggested hard registers
154 for each quantity. The first, phys_copy_sugg, contains hard registers
155 that are tied to the quantity by a simple copy. The second contains all
156 hard registers that are tied to the quantity via an arithmetic operation.
158 The former register set is given priority for allocation. This tends to
159 eliminate copy insns. */
161 /* Element Q is a set of hard registers that are suggested for quantity Q by
164 static HARD_REG_SET
*qty_phys_copy_sugg
;
166 /* Element Q is a set of hard registers that are suggested for quantity Q by
169 static HARD_REG_SET
*qty_phys_sugg
;
171 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
173 static short *qty_phys_num_copy_sugg
;
175 /* Element Q is the number of suggested registers in qty_phys_sugg. */
177 static short *qty_phys_num_sugg
;
179 /* If (REG N) has been assigned a quantity number, is a register number
180 of another register assigned the same quantity number, or -1 for the
181 end of the chain. qty->first_reg point to the head of this chain. */
183 static int *reg_next_in_qty
;
185 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
187 of -1 if this register cannot be allocated by local-alloc,
188 or -2 if not known yet.
190 Note that if we see a use or death of pseudo register N with
191 reg_qty[N] == -2, register N must be local to the current block. If
192 it were used in more than one block, we would have reg_qty[N] == -1.
193 This relies on the fact that if reg_basic_block[N] is >= 0, register N
194 will not appear in any other block. We save a considerable number of
195 tests by exploiting this.
197 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
202 /* The offset (in words) of register N within its quantity.
203 This can be nonzero if register N is SImode, and has been tied
204 to a subreg of a DImode register. */
206 static char *reg_offset
;
208 /* Vector of substitutions of register numbers,
209 used to map pseudo regs into hardware regs.
210 This is set up as a result of register allocation.
211 Element N is the hard reg assigned to pseudo reg N,
212 or is -1 if no hard reg was assigned.
213 If N is a hard reg number, element N is N. */
217 /* Set of hard registers live at the current point in the scan
218 of the instructions in a basic block. */
220 static HARD_REG_SET regs_live
;
222 /* Each set of hard registers indicates registers live at a particular
223 point in the basic block. For N even, regs_live_at[N] says which
224 hard registers are needed *after* insn N/2 (i.e., they may not
225 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
227 If an object is to conflict with the inputs of insn J but not the
228 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
229 if it is to conflict with the outputs of insn J but not the inputs of
230 insn J + 1, it is said to die at index J*2 + 1. */
232 static HARD_REG_SET
*regs_live_at
;
234 /* Communicate local vars `insn_number' and `insn'
235 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
236 static int this_insn_number
;
237 static rtx this_insn
;
239 /* Used to communicate changes made by update_equiv_regs to
240 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
241 found or created, so that we can keep track of what memory accesses might
242 be created later, e.g. by reload. */
244 static rtx
*reg_equiv_replacement
;
246 /* Used for communication between update_equiv_regs and no_equiv. */
247 static rtx
*reg_equiv_init_insns
;
249 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
250 static int recorded_label_ref
;
252 static void alloc_qty
PARAMS ((int, enum machine_mode
, int, int));
253 static void validate_equiv_mem_from_store
PARAMS ((rtx
, rtx
, void *));
254 static int validate_equiv_mem
PARAMS ((rtx
, rtx
, rtx
));
255 static int contains_replace_regs
PARAMS ((rtx
, char *));
256 static int memref_referenced_p
PARAMS ((rtx
, rtx
));
257 static int memref_used_between_p
PARAMS ((rtx
, rtx
, rtx
));
258 static void update_equiv_regs
PARAMS ((void));
259 static void no_equiv
PARAMS ((rtx
, rtx
, void *));
260 static void block_alloc
PARAMS ((int));
261 static int qty_sugg_compare
PARAMS ((int, int));
262 static int qty_sugg_compare_1
PARAMS ((const PTR
, const PTR
));
263 static int qty_compare
PARAMS ((int, int));
264 static int qty_compare_1
PARAMS ((const PTR
, const PTR
));
265 static int combine_regs
PARAMS ((rtx
, rtx
, int, int, rtx
, int));
266 static int reg_meets_class_p
PARAMS ((int, enum reg_class
));
267 static void update_qty_class
PARAMS ((int, int));
268 static void reg_is_set
PARAMS ((rtx
, rtx
, void *));
269 static void reg_is_born
PARAMS ((rtx
, int));
270 static void wipe_dead_reg
PARAMS ((rtx
, int));
271 static int find_free_reg
PARAMS ((enum reg_class
, enum machine_mode
,
272 int, int, int, int, int));
273 static void mark_life
PARAMS ((int, enum machine_mode
, int));
274 static void post_mark_life
PARAMS ((int, enum machine_mode
, int, int, int));
275 static int no_conflict_p
PARAMS ((rtx
, rtx
, rtx
));
276 static int requires_inout
PARAMS ((const char *));
278 /* Allocate a new quantity (new within current basic block)
279 for register number REGNO which is born at index BIRTH
280 within the block. MODE and SIZE are info on reg REGNO. */
283 alloc_qty (regno
, mode
, size
, birth
)
285 enum machine_mode mode
;
288 register int qtyno
= next_qty
++;
290 reg_qty
[regno
] = qtyno
;
291 reg_offset
[regno
] = 0;
292 reg_next_in_qty
[regno
] = -1;
294 qty
[qtyno
].first_reg
= regno
;
295 qty
[qtyno
].size
= size
;
296 qty
[qtyno
].mode
= mode
;
297 qty
[qtyno
].birth
= birth
;
298 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
299 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
300 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
301 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
302 qty
[qtyno
].changes_mode
= REG_CHANGES_MODE (regno
);
305 /* Main entry point of this file. */
313 /* We need to keep track of whether or not we recorded a LABEL_REF so
314 that we know if the jump optimizer needs to be rerun. */
315 recorded_label_ref
= 0;
317 /* Leaf functions and non-leaf functions have different needs.
318 If defined, let the machine say what kind of ordering we
320 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
321 ORDER_REGS_FOR_LOCAL_ALLOC
;
324 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
326 update_equiv_regs ();
328 /* This sets the maximum number of quantities we can have. Quantity
329 numbers start at zero and we can have one for each pseudo. */
330 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
332 /* Allocate vectors of temporary data.
333 See the declarations of these variables, above,
334 for what they mean. */
336 qty
= (struct qty
*) xmalloc (max_qty
* sizeof (struct qty
));
338 = (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
339 qty_phys_num_copy_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
340 qty_phys_sugg
= (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
341 qty_phys_num_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
343 reg_qty
= (int *) xmalloc (max_regno
* sizeof (int));
344 reg_offset
= (char *) xmalloc (max_regno
* sizeof (char));
345 reg_next_in_qty
= (int *) xmalloc (max_regno
* sizeof (int));
347 /* Allocate the reg_renumber array. */
348 allocate_reg_info (max_regno
, FALSE
, TRUE
);
350 /* Determine which pseudo-registers can be allocated by local-alloc.
351 In general, these are the registers used only in a single block and
352 which only die once. However, if a register's preferred class has only
353 a few entries, don't allocate this register here unless it is preferred
354 or nothing since retry_global_alloc won't be able to move it to
355 GENERAL_REGS if a reload register of this class is needed.
357 We need not be concerned with which block actually uses the register
358 since we will never see it outside that block. */
360 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
362 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1
363 && (reg_alternate_class (i
) == NO_REGS
364 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i
))))
370 /* Force loop below to initialize entire quantity array. */
373 /* Allocate each block's local registers, block by block. */
375 for (b
= 0; b
< n_basic_blocks
; b
++)
377 /* NEXT_QTY indicates which elements of the `qty_...'
378 vectors might need to be initialized because they were used
379 for the previous block; it is set to the entire array before
380 block 0. Initialize those, with explicit loop if there are few,
381 else with bzero and bcopy. Do not initialize vectors that are
382 explicit set by `alloc_qty'. */
386 for (i
= 0; i
< next_qty
; i
++)
388 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
389 qty_phys_num_copy_sugg
[i
] = 0;
390 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
391 qty_phys_num_sugg
[i
] = 0;
396 #define CLEAR(vector) \
397 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
399 CLEAR (qty_phys_copy_sugg
);
400 CLEAR (qty_phys_num_copy_sugg
);
401 CLEAR (qty_phys_sugg
);
402 CLEAR (qty_phys_num_sugg
);
411 free (qty_phys_copy_sugg
);
412 free (qty_phys_num_copy_sugg
);
413 free (qty_phys_sugg
);
414 free (qty_phys_num_sugg
);
418 free (reg_next_in_qty
);
420 return recorded_label_ref
;
423 /* Depth of loops we are in while in update_equiv_regs. */
424 static int loop_depth
;
426 /* Used for communication between the following two functions: contains
427 a MEM that we wish to ensure remains unchanged. */
428 static rtx equiv_mem
;
430 /* Set nonzero if EQUIV_MEM is modified. */
431 static int equiv_mem_modified
;
433 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
434 Called via note_stores. */
437 validate_equiv_mem_from_store (dest
, set
, data
)
439 rtx set ATTRIBUTE_UNUSED
;
440 void *data ATTRIBUTE_UNUSED
;
442 if ((GET_CODE (dest
) == REG
443 && reg_overlap_mentioned_p (dest
, equiv_mem
))
444 || (GET_CODE (dest
) == MEM
445 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
446 equiv_mem_modified
= 1;
449 /* Verify that no store between START and the death of REG invalidates
450 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
451 by storing into an overlapping memory location, or with a non-const
454 Return 1 if MEMREF remains valid. */
457 validate_equiv_mem (start
, reg
, memref
)
466 equiv_mem_modified
= 0;
468 /* If the memory reference has side effects or is volatile, it isn't a
469 valid equivalence. */
470 if (side_effects_p (memref
))
473 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
475 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
478 if (find_reg_note (insn
, REG_DEAD
, reg
))
481 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
482 && ! CONST_CALL_P (insn
))
485 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
487 /* If a register mentioned in MEMREF is modified via an
488 auto-increment, we lose the equivalence. Do the same if one
489 dies; although we could extend the life, it doesn't seem worth
492 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
493 if ((REG_NOTE_KIND (note
) == REG_INC
494 || REG_NOTE_KIND (note
) == REG_DEAD
)
495 && GET_CODE (XEXP (note
, 0)) == REG
496 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
503 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
506 contains_replace_regs (x
, reg_equiv_replace
)
508 char *reg_equiv_replace
;
512 enum rtx_code code
= GET_CODE (x
);
528 return reg_equiv_replace
[REGNO (x
)];
534 fmt
= GET_RTX_FORMAT (code
);
535 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
539 if (contains_replace_regs (XEXP (x
, i
), reg_equiv_replace
))
543 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
544 if (contains_replace_regs (XVECEXP (x
, i
, j
), reg_equiv_replace
))
552 /* TRUE if X references a memory location that would be affected by a store
556 memref_referenced_p (memref
, x
)
562 enum rtx_code code
= GET_CODE (x
);
578 return (reg_equiv_replacement
[REGNO (x
)]
579 && memref_referenced_p (memref
,
580 reg_equiv_replacement
[REGNO (x
)]));
583 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
588 /* If we are setting a MEM, it doesn't count (its address does), but any
589 other SET_DEST that has a MEM in it is referencing the MEM. */
590 if (GET_CODE (SET_DEST (x
)) == MEM
)
592 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
595 else if (memref_referenced_p (memref
, SET_DEST (x
)))
598 return memref_referenced_p (memref
, SET_SRC (x
));
604 fmt
= GET_RTX_FORMAT (code
);
605 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
609 if (memref_referenced_p (memref
, XEXP (x
, i
)))
613 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
614 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
622 /* TRUE if some insn in the range (START, END] references a memory location
623 that would be affected by a store to MEMREF. */
626 memref_used_between_p (memref
, start
, end
)
633 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
634 insn
= NEXT_INSN (insn
))
635 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
636 && memref_referenced_p (memref
, PATTERN (insn
)))
642 /* Return nonzero if the rtx X is invariant over the current function. */
644 function_invariant_p (x
)
649 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
651 if (GET_CODE (x
) == PLUS
652 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
653 && CONSTANT_P (XEXP (x
, 1)))
658 /* Find registers that are equivalent to a single value throughout the
659 compilation (either because they can be referenced in memory or are set once
660 from a single constant). Lower their priority for a register.
662 If such a register is only referenced once, try substituting its value
663 into the using insn. If it succeeds, we can eliminate the register
669 /* Set when an attempt should be made to replace a register with the
670 associated reg_equiv_replacement entry at the end of this function. */
671 char *reg_equiv_replace
;
675 reg_equiv_replace
= (char *) xcalloc (max_regno
, sizeof *reg_equiv_replace
);
676 reg_equiv_init_insns
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
677 reg_equiv_replacement
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
679 init_alias_analysis ();
683 /* Scan the insns and find which registers have equivalences. Do this
684 in a separate scan of the insns because (due to -fcse-follow-jumps)
685 a register can be set below its use. */
686 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
693 if (GET_CODE (insn
) == NOTE
)
695 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
697 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
701 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
704 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
705 if (REG_NOTE_KIND (note
) == REG_INC
)
706 no_equiv (XEXP (note
, 0), note
, NULL
);
708 set
= single_set (insn
);
710 /* If this insn contains more (or less) than a single SET,
711 only mark all destinations as having no known equivalence. */
714 note_stores (PATTERN (insn
), no_equiv
, NULL
);
717 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
721 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
723 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
725 note_stores (part
, no_equiv
, NULL
);
729 dest
= SET_DEST (set
);
732 /* If this sets a MEM to the contents of a REG that is only used
733 in a single basic block, see if the register is always equivalent
734 to that memory location and if moving the store from INSN to the
735 insn that set REG is safe. If so, put a REG_EQUIV note on the
738 Don't add a REG_EQUIV note if the insn already has one. The existing
739 REG_EQUIV is likely more useful than the one we are adding.
741 If one of the regs in the address is marked as reg_equiv_replace,
742 then we can't add this REG_EQUIV note. The reg_equiv_replace
743 optimization may move the set of this register immediately before
744 insn, which puts it after reg_equiv_init_insns[regno], and hence
745 the mention in the REG_EQUIV note would be to an uninitialized
747 /* ????? This test isn't good enough; we might see a MEM with a use of
748 a pseudo register before we see its setting insn that will cause
749 reg_equiv_replace for that pseudo to be set.
750 Equivalences to MEMs should be made in another pass, after the
751 reg_equiv_replace information has been gathered. */
753 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
754 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
755 && REG_BASIC_BLOCK (regno
) >= 0
756 && REG_N_SETS (regno
) == 1
757 && reg_equiv_init_insns
[regno
] != 0
758 && reg_equiv_init_insns
[regno
] != const0_rtx
759 && ! find_reg_note (XEXP (reg_equiv_init_insns
[regno
], 0),
761 && ! contains_replace_regs (XEXP (dest
, 0), reg_equiv_replace
))
763 rtx init_insn
= XEXP (reg_equiv_init_insns
[regno
], 0);
764 if (validate_equiv_mem (init_insn
, src
, dest
)
765 && ! memref_used_between_p (dest
, init_insn
, insn
))
766 REG_NOTES (init_insn
)
767 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
770 /* We only handle the case of a pseudo register being set
771 once, or always to the same value. */
772 /* ??? The mn10200 port breaks if we add equivalences for
773 values that need an ADDRESS_REGS register and set them equivalent
774 to a MEM of a pseudo. The actual problem is in the over-conservative
775 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
776 calculate_needs, but we traditionally work around this problem
777 here by rejecting equivalences when the destination is in a register
778 that's likely spilled. This is fragile, of course, since the
779 preferred class of a pseudo depends on all instructions that set
782 if (GET_CODE (dest
) != REG
783 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
784 || reg_equiv_init_insns
[regno
] == const0_rtx
785 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
786 && GET_CODE (src
) == MEM
))
788 /* This might be seting a SUBREG of a pseudo, a pseudo that is
789 also set somewhere else to a constant. */
790 note_stores (set
, no_equiv
, NULL
);
793 /* Don't handle the equivalence if the source is in a register
794 class that's likely to be spilled. */
795 if (GET_CODE (src
) == REG
796 && REGNO (src
) >= FIRST_PSEUDO_REGISTER
797 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src
))))
799 no_equiv (dest
, set
, NULL
);
803 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
805 if (REG_N_SETS (regno
) != 1
807 || ! function_invariant_p (XEXP (note
, 0))
808 || (reg_equiv_replacement
[regno
]
809 && ! rtx_equal_p (XEXP (note
, 0),
810 reg_equiv_replacement
[regno
]))))
812 no_equiv (dest
, set
, NULL
);
815 /* Record this insn as initializing this register. */
816 reg_equiv_init_insns
[regno
]
817 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init_insns
[regno
]);
819 /* If this register is known to be equal to a constant, record that
820 it is always equivalent to the constant. */
821 if (note
&& function_invariant_p (XEXP (note
, 0)))
822 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
824 /* If this insn introduces a "constant" register, decrease the priority
825 of that register. Record this insn if the register is only used once
826 more and the equivalence value is the same as our source.
828 The latter condition is checked for two reasons: First, it is an
829 indication that it may be more efficient to actually emit the insn
830 as written (if no registers are available, reload will substitute
831 the equivalence). Secondly, it avoids problems with any registers
832 dying in this insn whose death notes would be missed.
834 If we don't have a REG_EQUIV note, see if this insn is loading
835 a register used only in one basic block from a MEM. If so, and the
836 MEM remains unchanged for the life of the register, add a REG_EQUIV
839 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
841 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
842 && GET_CODE (SET_SRC (set
)) == MEM
843 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
844 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
849 int regno
= REGNO (dest
);
851 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
852 We might end up substituting the LABEL_REF for uses of the
853 pseudo here or later. That kind of transformation may turn an
854 indirect jump into a direct jump, in which case we must rerun the
855 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
856 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
857 || (GET_CODE (XEXP (note
, 0)) == CONST
858 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
859 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
861 recorded_label_ref
= 1;
863 reg_equiv_replacement
[regno
] = XEXP (note
, 0);
865 /* Don't mess with things live during setjmp. */
866 if (REG_LIVE_LENGTH (regno
) >= 0)
868 /* Note that the statement below does not affect the priority
870 REG_LIVE_LENGTH (regno
) *= 2;
873 /* If the register is referenced exactly twice, meaning it is
874 set once and used once, indicate that the reference may be
875 replaced by the equivalence we computed above. If the
876 register is only used in one basic block, this can't succeed
877 or combine would have done it.
879 It would be nice to use "loop_depth * 2" in the compare
880 below. Unfortunately, LOOP_DEPTH need not be constant within
881 a basic block so this would be too complicated.
883 This case normally occurs when a parameter is read from
884 memory and then used exactly once, not in a loop. */
886 if (REG_N_REFS (regno
) == 2
887 && REG_BASIC_BLOCK (regno
) < 0
888 && rtx_equal_p (XEXP (note
, 0), SET_SRC (set
)))
889 reg_equiv_replace
[regno
] = 1;
894 /* Now scan all regs killed in an insn to see if any of them are
895 registers only used that once. If so, see if we can replace the
896 reference with the equivalent from. If we can, delete the
897 initializing reference and this register will go away. If we
898 can't replace the reference, and the instruction is not in a
899 loop, then move the register initialization just before the use,
900 so that they are in the same basic block. */
903 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
907 /* Keep track of which basic block we are in. */
908 if (block
+ 1 < n_basic_blocks
909 && BLOCK_HEAD (block
+ 1) == insn
)
912 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
914 if (GET_CODE (insn
) == NOTE
)
916 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
918 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
929 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
931 if (REG_NOTE_KIND (link
) == REG_DEAD
932 /* Make sure this insn still refers to the register. */
933 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
935 int regno
= REGNO (XEXP (link
, 0));
938 if (! reg_equiv_replace
[regno
])
941 /* reg_equiv_replace[REGNO] gets set only when
942 REG_N_REFS[REGNO] is 2, i.e. the register is set
943 once and used once. (If it were only set, but not used,
944 flow would have deleted the setting insns.) Hence
945 there can only be one insn in reg_equiv_init_insns. */
946 equiv_insn
= XEXP (reg_equiv_init_insns
[regno
], 0);
948 if (validate_replace_rtx (regno_reg_rtx
[regno
],
949 reg_equiv_replacement
[regno
], insn
))
951 remove_death (regno
, insn
);
952 REG_N_REFS (regno
) = 0;
953 PUT_CODE (equiv_insn
, NOTE
);
954 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
955 NOTE_SOURCE_FILE (equiv_insn
) = 0;
957 /* If we aren't in a loop, and there are no calls in
958 INSN or in the initialization of the register, then
959 move the initialization of the register to just
960 before INSN. Update the flow information. */
962 && GET_CODE (equiv_insn
) == INSN
963 && GET_CODE (insn
) == INSN
964 && REG_BASIC_BLOCK (regno
) < 0)
968 emit_insn_before (copy_rtx (PATTERN (equiv_insn
)), insn
);
969 REG_NOTES (PREV_INSN (insn
)) = REG_NOTES (equiv_insn
);
970 REG_NOTES (equiv_insn
) = 0;
972 PUT_CODE (equiv_insn
, NOTE
);
973 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
974 NOTE_SOURCE_FILE (equiv_insn
) = 0;
977 REG_BASIC_BLOCK (regno
) = 0;
979 REG_BASIC_BLOCK (regno
) = block
;
980 REG_N_CALLS_CROSSED (regno
) = 0;
981 REG_LIVE_LENGTH (regno
) = 2;
983 if (block
>= 0 && insn
== BLOCK_HEAD (block
))
984 BLOCK_HEAD (block
) = PREV_INSN (insn
);
986 for (l
= 0; l
< n_basic_blocks
; l
++)
987 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l
)->global_live_at_start
,
995 end_alias_analysis ();
996 free (reg_equiv_replace
);
997 free (reg_equiv_init_insns
);
998 free (reg_equiv_replacement
);
1001 /* Mark REG as having no known equivalence.
1002 Some instructions might have been proceessed before and furnished
1003 with REG_EQUIV notes for this register; these notes will have to be
1005 STORE is the piece of RTL that does the non-constant / conflicting
1006 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1007 but needs to be there because this function is called from note_stores. */
1009 no_equiv (reg
, store
, data
)
1010 rtx reg
, store ATTRIBUTE_UNUSED
;
1011 void *data ATTRIBUTE_UNUSED
;
1016 if (GET_CODE (reg
) != REG
)
1018 regno
= REGNO (reg
);
1019 list
= reg_equiv_init_insns
[regno
];
1020 if (list
== const0_rtx
)
1022 for (; list
; list
= XEXP (list
, 1))
1024 rtx insn
= XEXP (list
, 0);
1025 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1027 reg_equiv_init_insns
[regno
] = const0_rtx
;
1028 reg_equiv_replacement
[regno
] = NULL_RTX
;
1031 /* Allocate hard regs to the pseudo regs used only within block number B.
1032 Only the pseudos that die but once can be handled. */
1041 int insn_number
= 0;
1043 int max_uid
= get_max_uid ();
1045 int no_conflict_combined_regno
= -1;
1047 /* Count the instructions in the basic block. */
1049 insn
= BLOCK_END (b
);
1052 if (GET_CODE (insn
) != NOTE
)
1053 if (++insn_count
> max_uid
)
1055 if (insn
== BLOCK_HEAD (b
))
1057 insn
= PREV_INSN (insn
);
1060 /* +2 to leave room for a post_mark_life at the last insn and for
1061 the birth of a CLOBBER in the first insn. */
1062 regs_live_at
= (HARD_REG_SET
*) xcalloc ((2 * insn_count
+ 2),
1063 sizeof (HARD_REG_SET
));
1065 /* Initialize table of hardware registers currently live. */
1067 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1069 /* This loop scans the instructions of the basic block
1070 and assigns quantities to registers.
1071 It computes which registers to tie. */
1073 insn
= BLOCK_HEAD (b
);
1076 if (GET_CODE (insn
) != NOTE
)
1079 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1081 register rtx link
, set
;
1082 register int win
= 0;
1083 register rtx r0
, r1
= NULL_RTX
;
1084 int combined_regno
= -1;
1087 this_insn_number
= insn_number
;
1090 extract_insn (insn
);
1091 which_alternative
= -1;
1093 /* Is this insn suitable for tying two registers?
1094 If so, try doing that.
1095 Suitable insns are those with at least two operands and where
1096 operand 0 is an output that is a register that is not
1099 We can tie operand 0 with some operand that dies in this insn.
1100 First look for operands that are required to be in the same
1101 register as operand 0. If we find such, only try tying that
1102 operand or one that can be put into that operand if the
1103 operation is commutative. If we don't find an operand
1104 that is required to be in the same register as operand 0,
1105 we can tie with any operand.
1107 Subregs in place of regs are also ok.
1109 If tying is done, WIN is set nonzero. */
1112 && recog_data
.n_operands
> 1
1113 && recog_data
.constraints
[0][0] == '='
1114 && recog_data
.constraints
[0][1] != '&')
1116 /* If non-negative, is an operand that must match operand 0. */
1117 int must_match_0
= -1;
1118 /* Counts number of alternatives that require a match with
1120 int n_matching_alts
= 0;
1122 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1124 const char *p
= recog_data
.constraints
[i
];
1125 int this_match
= (requires_inout (p
));
1127 n_matching_alts
+= this_match
;
1128 if (this_match
== recog_data
.n_alternatives
)
1132 r0
= recog_data
.operand
[0];
1133 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1135 /* Skip this operand if we found an operand that
1136 must match operand 0 and this operand isn't it
1137 and can't be made to be it by commutativity. */
1139 if (must_match_0
>= 0 && i
!= must_match_0
1140 && ! (i
== must_match_0
+ 1
1141 && recog_data
.constraints
[i
-1][0] == '%')
1142 && ! (i
== must_match_0
- 1
1143 && recog_data
.constraints
[i
][0] == '%'))
1146 /* Likewise if each alternative has some operand that
1147 must match operand zero. In that case, skip any
1148 operand that doesn't list operand 0 since we know that
1149 the operand always conflicts with operand 0. We
1150 ignore commutatity in this case to keep things simple. */
1151 if (n_matching_alts
== recog_data
.n_alternatives
1152 && 0 == requires_inout (recog_data
.constraints
[i
]))
1155 r1
= recog_data
.operand
[i
];
1157 /* If the operand is an address, find a register in it.
1158 There may be more than one register, but we only try one
1160 if (recog_data
.constraints
[i
][0] == 'p')
1161 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1164 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1166 /* We have two priorities for hard register preferences.
1167 If we have a move insn or an insn whose first input
1168 can only be in the same register as the output, give
1169 priority to an equivalence found from that insn. */
1171 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1173 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1174 win
= combine_regs (r1
, r0
, may_save_copy
,
1175 insn_number
, insn
, 0);
1182 /* Recognize an insn sequence with an ultimate result
1183 which can safely overlap one of the inputs.
1184 The sequence begins with a CLOBBER of its result,
1185 and ends with an insn that copies the result to itself
1186 and has a REG_EQUAL note for an equivalent formula.
1187 That note indicates what the inputs are.
1188 The result and the input can overlap if each insn in
1189 the sequence either doesn't mention the input
1190 or has a REG_NO_CONFLICT note to inhibit the conflict.
1192 We do the combining test at the CLOBBER so that the
1193 destination register won't have had a quantity number
1194 assigned, since that would prevent combining. */
1197 && GET_CODE (PATTERN (insn
)) == CLOBBER
1198 && (r0
= XEXP (PATTERN (insn
), 0),
1199 GET_CODE (r0
) == REG
)
1200 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1201 && XEXP (link
, 0) != 0
1202 && GET_CODE (XEXP (link
, 0)) == INSN
1203 && (set
= single_set (XEXP (link
, 0))) != 0
1204 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1205 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1208 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1209 /* Check that we have such a sequence. */
1210 && no_conflict_p (insn
, r0
, r1
))
1211 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1212 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1213 && (r1
= XEXP (XEXP (note
, 0), 0),
1214 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1215 && no_conflict_p (insn
, r0
, r1
))
1216 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1218 /* Here we care if the operation to be computed is
1220 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1221 || GET_CODE (XEXP (note
, 0)) == NE
1222 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1223 && (r1
= XEXP (XEXP (note
, 0), 1),
1224 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1225 && no_conflict_p (insn
, r0
, r1
))
1226 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1228 /* If we did combine something, show the register number
1229 in question so that we know to ignore its death. */
1231 no_conflict_combined_regno
= REGNO (r1
);
1234 /* If registers were just tied, set COMBINED_REGNO
1235 to the number of the register used in this insn
1236 that was tied to the register set in this insn.
1237 This register's qty should not be "killed". */
1241 while (GET_CODE (r1
) == SUBREG
)
1242 r1
= SUBREG_REG (r1
);
1243 combined_regno
= REGNO (r1
);
1246 /* Mark the death of everything that dies in this instruction,
1247 except for anything that was just combined. */
1249 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1250 if (REG_NOTE_KIND (link
) == REG_DEAD
1251 && GET_CODE (XEXP (link
, 0)) == REG
1252 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1253 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1254 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1256 wipe_dead_reg (XEXP (link
, 0), 0);
1258 /* Allocate qty numbers for all registers local to this block
1259 that are born (set) in this instruction.
1260 A pseudo that already has a qty is not changed. */
1262 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1264 /* If anything is set in this insn and then unused, mark it as dying
1265 after this insn, so it will conflict with our outputs. This
1266 can't match with something that combined, and it doesn't matter
1267 if it did. Do this after the calls to reg_is_set since these
1268 die after, not during, the current insn. */
1270 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1271 if (REG_NOTE_KIND (link
) == REG_UNUSED
1272 && GET_CODE (XEXP (link
, 0)) == REG
)
1273 wipe_dead_reg (XEXP (link
, 0), 1);
1275 /* If this is an insn that has a REG_RETVAL note pointing at a
1276 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1277 block, so clear any register number that combined within it. */
1278 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1279 && GET_CODE (XEXP (note
, 0)) == INSN
1280 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1281 no_conflict_combined_regno
= -1;
1284 /* Set the registers live after INSN_NUMBER. Note that we never
1285 record the registers live before the block's first insn, since no
1286 pseudos we care about are live before that insn. */
1288 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1289 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1291 if (insn
== BLOCK_END (b
))
1294 insn
= NEXT_INSN (insn
);
1297 /* Now every register that is local to this basic block
1298 should have been given a quantity, or else -1 meaning ignore it.
1299 Every quantity should have a known birth and death.
1301 Order the qtys so we assign them registers in order of the
1302 number of suggested registers they need so we allocate those with
1303 the most restrictive needs first. */
1305 qty_order
= (int *) xmalloc (next_qty
* sizeof (int));
1306 for (i
= 0; i
< next_qty
; i
++)
1309 #define EXCHANGE(I1, I2) \
1310 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1315 /* Make qty_order[2] be the one to allocate last. */
1316 if (qty_sugg_compare (0, 1) > 0)
1318 if (qty_sugg_compare (1, 2) > 0)
1321 /* ... Fall through ... */
1323 /* Put the best one to allocate in qty_order[0]. */
1324 if (qty_sugg_compare (0, 1) > 0)
1327 /* ... Fall through ... */
1331 /* Nothing to do here. */
1335 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1338 /* Try to put each quantity in a suggested physical register, if it has one.
1339 This may cause registers to be allocated that otherwise wouldn't be, but
1340 this seems acceptable in local allocation (unlike global allocation). */
1341 for (i
= 0; i
< next_qty
; i
++)
1344 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1345 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1346 0, 1, qty
[q
].birth
, qty
[q
].death
);
1348 qty
[q
].phys_reg
= -1;
1351 /* Order the qtys so we assign them registers in order of
1352 decreasing length of life. Normally call qsort, but if we
1353 have only a very small number of quantities, sort them ourselves. */
1355 for (i
= 0; i
< next_qty
; i
++)
1358 #define EXCHANGE(I1, I2) \
1359 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1364 /* Make qty_order[2] be the one to allocate last. */
1365 if (qty_compare (0, 1) > 0)
1367 if (qty_compare (1, 2) > 0)
1370 /* ... Fall through ... */
1372 /* Put the best one to allocate in qty_order[0]. */
1373 if (qty_compare (0, 1) > 0)
1376 /* ... Fall through ... */
1380 /* Nothing to do here. */
1384 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1387 /* Now for each qty that is not a hardware register,
1388 look for a hardware register to put it in.
1389 First try the register class that is cheapest for this qty,
1390 if there is more than one class. */
1392 for (i
= 0; i
< next_qty
; i
++)
1395 if (qty
[q
].phys_reg
< 0)
1397 #ifdef INSN_SCHEDULING
1398 /* These values represent the adjusted lifetime of a qty so
1399 that it conflicts with qtys which appear near the start/end
1400 of this qty's lifetime.
1402 The purpose behind extending the lifetime of this qty is to
1403 discourage the register allocator from creating false
1406 The adjustment value is choosen to indicate that this qty
1407 conflicts with all the qtys in the instructions immediately
1408 before and after the lifetime of this qty.
1410 Experiments have shown that higher values tend to hurt
1411 overall code performance.
1413 If allocation using the extended lifetime fails we will try
1414 again with the qty's unadjusted lifetime. */
1415 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1416 int fake_death
= MIN (insn_number
* 2 + 1,
1417 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1420 if (N_REG_CLASSES
> 1)
1422 #ifdef INSN_SCHEDULING
1423 /* We try to avoid using hard registers allocated to qtys which
1424 are born immediately after this qty or die immediately before
1427 This optimization is only appropriate when we will run
1428 a scheduling pass after reload and we are not optimizing
1430 if (flag_schedule_insns_after_reload
1432 && !SMALL_REGISTER_CLASSES
)
1434 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1435 qty
[q
].mode
, q
, 0, 0,
1436 fake_birth
, fake_death
);
1437 if (qty
[q
].phys_reg
>= 0)
1441 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1442 qty
[q
].mode
, q
, 0, 0,
1443 qty
[q
].birth
, qty
[q
].death
);
1444 if (qty
[q
].phys_reg
>= 0)
1448 #ifdef INSN_SCHEDULING
1449 /* Similarly, avoid false dependencies. */
1450 if (flag_schedule_insns_after_reload
1452 && !SMALL_REGISTER_CLASSES
1453 && qty
[q
].alternate_class
!= NO_REGS
)
1454 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1455 qty
[q
].mode
, q
, 0, 0,
1456 fake_birth
, fake_death
);
1458 if (qty
[q
].alternate_class
!= NO_REGS
)
1459 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1460 qty
[q
].mode
, q
, 0, 0,
1461 qty
[q
].birth
, qty
[q
].death
);
1465 /* Now propagate the register assignments
1466 to the pseudo regs belonging to the qtys. */
1468 for (q
= 0; q
< next_qty
; q
++)
1469 if (qty
[q
].phys_reg
>= 0)
1471 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1472 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1476 free (regs_live_at
);
1480 /* Compare two quantities' priority for getting real registers.
1481 We give shorter-lived quantities higher priority.
1482 Quantities with more references are also preferred, as are quantities that
1483 require multiple registers. This is the identical prioritization as
1484 done by global-alloc.
1486 We used to give preference to registers with *longer* lives, but using
1487 the same algorithm in both local- and global-alloc can speed up execution
1488 of some programs by as much as a factor of three! */
1490 /* Note that the quotient will never be bigger than
1491 the value of floor_log2 times the maximum number of
1492 times a register can occur in one insn (surely less than 100).
1493 Multiplying this by 10000 can't overflow.
1494 QTY_CMP_PRI is also used by qty_sugg_compare. */
1496 #define QTY_CMP_PRI(q) \
1497 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].n_refs * qty[q].size) \
1498 / (qty[q].death - qty[q].birth)) * 10000))
1501 qty_compare (q1
, q2
)
1504 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1508 qty_compare_1 (q1p
, q2p
)
1512 register int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1513 register int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1518 /* If qtys are equally good, sort by qty number,
1519 so that the results of qsort leave nothing to chance. */
1523 /* Compare two quantities' priority for getting real registers. This version
1524 is called for quantities that have suggested hard registers. First priority
1525 goes to quantities that have copy preferences, then to those that have
1526 normal preferences. Within those groups, quantities with the lower
1527 number of preferences have the highest priority. Of those, we use the same
1528 algorithm as above. */
1530 #define QTY_CMP_SUGG(q) \
1531 (qty_phys_num_copy_sugg[q] \
1532 ? qty_phys_num_copy_sugg[q] \
1533 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1536 qty_sugg_compare (q1
, q2
)
1539 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1544 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1548 qty_sugg_compare_1 (q1p
, q2p
)
1552 register int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1553 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1558 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1562 /* If qtys are equally good, sort by qty number,
1563 so that the results of qsort leave nothing to chance. */
1570 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1571 Returns 1 if have done so, or 0 if cannot.
1573 Combining registers means marking them as having the same quantity
1574 and adjusting the offsets within the quantity if either of
1577 We don't actually combine a hard reg with a pseudo; instead
1578 we just record the hard reg as the suggestion for the pseudo's quantity.
1579 If we really combined them, we could lose if the pseudo lives
1580 across an insn that clobbers the hard reg (eg, movstr).
1582 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1583 there is no REG_DEAD note on INSN. This occurs during the processing
1584 of REG_NO_CONFLICT blocks.
1586 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1587 SETREG or if the input and output must share a register.
1588 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1590 There are elaborate checks for the validity of combining. */
1593 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1594 rtx usedreg
, setreg
;
1600 register int ureg
, sreg
;
1601 register int offset
= 0;
1605 /* Determine the numbers and sizes of registers being used. If a subreg
1606 is present that does not change the entire register, don't consider
1607 this a copy insn. */
1609 while (GET_CODE (usedreg
) == SUBREG
)
1611 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg
))) > UNITS_PER_WORD
)
1613 offset
+= SUBREG_WORD (usedreg
);
1614 usedreg
= SUBREG_REG (usedreg
);
1616 if (GET_CODE (usedreg
) != REG
)
1618 ureg
= REGNO (usedreg
);
1619 usize
= REG_SIZE (usedreg
);
1621 while (GET_CODE (setreg
) == SUBREG
)
1623 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg
))) > UNITS_PER_WORD
)
1625 offset
-= SUBREG_WORD (setreg
);
1626 setreg
= SUBREG_REG (setreg
);
1628 if (GET_CODE (setreg
) != REG
)
1630 sreg
= REGNO (setreg
);
1631 ssize
= REG_SIZE (setreg
);
1633 /* If UREG is a pseudo-register that hasn't already been assigned a
1634 quantity number, it means that it is not local to this block or dies
1635 more than once. In either event, we can't do anything with it. */
1636 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1637 /* Do not combine registers unless one fits within the other. */
1638 || (offset
> 0 && usize
+ offset
> ssize
)
1639 || (offset
< 0 && usize
+ offset
< ssize
)
1640 /* Do not combine with a smaller already-assigned object
1641 if that smaller object is already combined with something bigger. */
1642 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1643 && usize
< qty
[reg_qty
[ureg
]].size
)
1644 /* Can't combine if SREG is not a register we can allocate. */
1645 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1646 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1647 These have already been taken care of. This probably wouldn't
1648 combine anyway, but don't take any chances. */
1649 || (ureg
>= FIRST_PSEUDO_REGISTER
1650 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1651 /* Don't tie something to itself. In most cases it would make no
1652 difference, but it would screw up if the reg being tied to itself
1653 also dies in this insn. */
1655 /* Don't try to connect two different hardware registers. */
1656 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1657 /* Don't use a hard reg that might be spilled. */
1658 || (ureg
< FIRST_PSEUDO_REGISTER
1659 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (ureg
)))
1660 || (sreg
< FIRST_PSEUDO_REGISTER
1661 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (sreg
)))
1662 /* Don't connect two different machine modes if they have different
1663 implications as to which registers may be used. */
1664 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1667 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1668 qty_phys_sugg for the pseudo instead of tying them.
1670 Return "failure" so that the lifespan of UREG is terminated here;
1671 that way the two lifespans will be disjoint and nothing will prevent
1672 the pseudo reg from being given this hard reg. */
1674 if (ureg
< FIRST_PSEUDO_REGISTER
)
1676 /* Allocate a quantity number so we have a place to put our
1678 if (reg_qty
[sreg
] == -2)
1679 reg_is_born (setreg
, 2 * insn_number
);
1681 if (reg_qty
[sreg
] >= 0)
1684 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1686 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1687 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1689 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1691 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1692 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1698 /* Similarly for SREG a hard register and UREG a pseudo register. */
1700 if (sreg
< FIRST_PSEUDO_REGISTER
)
1703 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1705 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1706 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1708 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1710 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1711 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1716 /* At this point we know that SREG and UREG are both pseudos.
1717 Do nothing if SREG already has a quantity or is a register that we
1719 if (reg_qty
[sreg
] >= -1
1720 /* If we are not going to let any regs live across calls,
1721 don't tie a call-crossing reg to a non-call-crossing reg. */
1722 || (current_function_has_nonlocal_label
1723 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1724 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1727 /* We don't already know about SREG, so tie it to UREG
1728 if this is the last use of UREG, provided the classes they want
1731 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1732 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
1734 /* Add SREG to UREG's quantity. */
1735 sqty
= reg_qty
[ureg
];
1736 reg_qty
[sreg
] = sqty
;
1737 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1738 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
1739 qty
[sqty
].first_reg
= sreg
;
1741 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1742 update_qty_class (sqty
, sreg
);
1744 /* Update info about quantity SQTY. */
1745 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
1746 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
1751 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1752 reg_offset
[i
] -= offset
;
1754 qty
[sqty
].size
= ssize
;
1755 qty
[sqty
].mode
= GET_MODE (setreg
);
1764 /* Return 1 if the preferred class of REG allows it to be tied
1765 to a quantity or register whose class is CLASS.
1766 True if REG's reg class either contains or is contained in CLASS. */
1769 reg_meets_class_p (reg
, class)
1771 enum reg_class
class;
1773 register enum reg_class rclass
= reg_preferred_class (reg
);
1774 return (reg_class_subset_p (rclass
, class)
1775 || reg_class_subset_p (class, rclass
));
1778 /* Update the class of QTYNO assuming that REG is being tied to it. */
1781 update_qty_class (qtyno
, reg
)
1785 enum reg_class rclass
= reg_preferred_class (reg
);
1786 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
1787 qty
[qtyno
].min_class
= rclass
;
1789 rclass
= reg_alternate_class (reg
);
1790 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
1791 qty
[qtyno
].alternate_class
= rclass
;
1793 if (REG_CHANGES_MODE (reg
))
1794 qty
[qtyno
].changes_mode
= 1;
1797 /* Handle something which alters the value of an rtx REG.
1799 REG is whatever is set or clobbered. SETTER is the rtx that
1800 is modifying the register.
1802 If it is not really a register, we do nothing.
1803 The file-global variables `this_insn' and `this_insn_number'
1804 carry info from `block_alloc'. */
1807 reg_is_set (reg
, setter
, data
)
1810 void *data ATTRIBUTE_UNUSED
;
1812 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1813 a hard register. These may actually not exist any more. */
1815 if (GET_CODE (reg
) != SUBREG
1816 && GET_CODE (reg
) != REG
)
1819 /* Mark this register as being born. If it is used in a CLOBBER, mark
1820 it as being born halfway between the previous insn and this insn so that
1821 it conflicts with our inputs but not the outputs of the previous insn. */
1823 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
1826 /* Handle beginning of the life of register REG.
1827 BIRTH is the index at which this is happening. */
1830 reg_is_born (reg
, birth
)
1836 if (GET_CODE (reg
) == SUBREG
)
1837 regno
= REGNO (SUBREG_REG (reg
)) + SUBREG_WORD (reg
);
1839 regno
= REGNO (reg
);
1841 if (regno
< FIRST_PSEUDO_REGISTER
)
1843 mark_life (regno
, GET_MODE (reg
), 1);
1845 /* If the register was to have been born earlier that the present
1846 insn, mark it as live where it is actually born. */
1847 if (birth
< 2 * this_insn_number
)
1848 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
1852 if (reg_qty
[regno
] == -2)
1853 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
1855 /* If this register has a quantity number, show that it isn't dead. */
1856 if (reg_qty
[regno
] >= 0)
1857 qty
[reg_qty
[regno
]].death
= -1;
1861 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1862 REG is an output that is dying (i.e., it is never used), otherwise it
1863 is an input (the normal case).
1864 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1867 wipe_dead_reg (reg
, output_p
)
1871 register int regno
= REGNO (reg
);
1873 /* If this insn has multiple results,
1874 and the dead reg is used in one of the results,
1875 extend its life to after this insn,
1876 so it won't get allocated together with any other result of this insn.
1878 It is unsafe to use !single_set here since it will ignore an unused
1879 output. Just because an output is unused does not mean the compiler
1880 can assume the side effect will not occur. Consider if REG appears
1881 in the address of an output and we reload the output. If we allocate
1882 REG to the same hard register as an unused output we could set the hard
1883 register before the output reload insn. */
1884 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
1885 && multiple_sets (this_insn
))
1888 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
1890 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
1891 if (GET_CODE (set
) == SET
1892 && GET_CODE (SET_DEST (set
)) != REG
1893 && !rtx_equal_p (reg
, SET_DEST (set
))
1894 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1899 /* If this register is used in an auto-increment address, then extend its
1900 life to after this insn, so that it won't get allocated together with
1901 the result of this insn. */
1902 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
1905 if (regno
< FIRST_PSEUDO_REGISTER
)
1907 mark_life (regno
, GET_MODE (reg
), 0);
1909 /* If a hard register is dying as an output, mark it as in use at
1910 the beginning of this insn (the above statement would cause this
1913 post_mark_life (regno
, GET_MODE (reg
), 1,
1914 2 * this_insn_number
, 2 * this_insn_number
+ 1);
1917 else if (reg_qty
[regno
] >= 0)
1918 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
1921 /* Find a block of SIZE words of hard regs in reg_class CLASS
1922 that can hold something of machine-mode MODE
1923 (but actually we test only the first of the block for holding MODE)
1924 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1925 and return the number of the first of them.
1926 Return -1 if such a block cannot be found.
1927 If QTYNO crosses calls, insist on a register preserved by calls,
1928 unless ACCEPT_CALL_CLOBBERED is nonzero.
1930 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1931 register is available. If not, return -1. */
1934 find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, just_try_suggested
,
1935 born_index
, dead_index
)
1936 enum reg_class
class;
1937 enum machine_mode mode
;
1939 int accept_call_clobbered
;
1940 int just_try_suggested
;
1941 int born_index
, dead_index
;
1943 register int i
, ins
;
1945 /* Declare it register if it's a scalar. */
1948 HARD_REG_SET used
, first_used
;
1949 #ifdef ELIMINABLE_REGS
1950 static struct {int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
1953 /* Validate our parameters. */
1954 if (born_index
< 0 || born_index
> dead_index
)
1957 /* Don't let a pseudo live in a reg across a function call
1958 if we might get a nonlocal goto. */
1959 if (current_function_has_nonlocal_label
1960 && qty
[qtyno
].n_calls_crossed
> 0)
1963 if (accept_call_clobbered
)
1964 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
1965 else if (qty
[qtyno
].n_calls_crossed
== 0)
1966 COPY_HARD_REG_SET (used
, fixed_reg_set
);
1968 COPY_HARD_REG_SET (used
, call_used_reg_set
);
1970 if (accept_call_clobbered
)
1971 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
1973 for (ins
= born_index
; ins
< dead_index
; ins
++)
1974 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
1976 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
1978 /* Don't use the frame pointer reg in local-alloc even if
1979 we may omit the frame pointer, because if we do that and then we
1980 need a frame pointer, reload won't know how to move the pseudo
1981 to another hard reg. It can move only regs made by global-alloc.
1983 This is true of any register that can be eliminated. */
1984 #ifdef ELIMINABLE_REGS
1985 for (i
= 0; i
< (int) (sizeof eliminables
/ sizeof eliminables
[0]); i
++)
1986 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
1987 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1988 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1989 that it might be eliminated into. */
1990 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
1993 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
1996 #ifdef CLASS_CANNOT_CHANGE_MODE
1997 if (qty
[qtyno
].changes_mode
)
1998 IOR_HARD_REG_SET (used
,
1999 reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
]);
2002 /* Normally, the registers that can be used for the first register in
2003 a multi-register quantity are the same as those that can be used for
2004 subsequent registers. However, if just trying suggested registers,
2005 restrict our consideration to them. If there are copy-suggested
2006 register, try them. Otherwise, try the arithmetic-suggested
2008 COPY_HARD_REG_SET (first_used
, used
);
2010 if (just_try_suggested
)
2012 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2013 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2015 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2018 /* If all registers are excluded, we can't do anything. */
2019 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2021 /* If at least one would be suitable, test each hard reg. */
2023 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2025 #ifdef REG_ALLOC_ORDER
2026 int regno
= reg_alloc_order
[i
];
2030 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2031 && HARD_REGNO_MODE_OK (regno
, mode
)
2032 && (qty
[qtyno
].n_calls_crossed
== 0
2033 || accept_call_clobbered
2034 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2037 register int size1
= HARD_REGNO_NREGS (regno
, mode
);
2038 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2041 /* Mark that this register is in use between its birth and death
2043 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2046 #ifndef REG_ALLOC_ORDER
2047 /* Skip starting points we know will lose. */
2054 /* If we are just trying suggested register, we have just tried copy-
2055 suggested registers, and there are arithmetic-suggested registers,
2058 /* If it would be profitable to allocate a call-clobbered register
2059 and save and restore it around calls, do that. */
2060 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2061 && qty_phys_num_sugg
[qtyno
] != 0)
2063 /* Don't try the copy-suggested regs again. */
2064 qty_phys_num_copy_sugg
[qtyno
] = 0;
2065 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2066 born_index
, dead_index
);
2069 /* We need not check to see if the current function has nonlocal
2070 labels because we don't put any pseudos that are live over calls in
2071 registers in that case. */
2073 if (! accept_call_clobbered
2074 && flag_caller_saves
2075 && ! just_try_suggested
2076 && qty
[qtyno
].n_calls_crossed
!= 0
2077 && CALLER_SAVE_PROFITABLE (qty
[qtyno
].n_refs
,
2078 qty
[qtyno
].n_calls_crossed
))
2080 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2082 caller_save_needed
= 1;
2088 /* Mark that REGNO with machine-mode MODE is live starting from the current
2089 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2093 mark_life (regno
, mode
, life
)
2095 enum machine_mode mode
;
2098 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2101 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2104 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2107 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2108 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2109 to insn number DEATH (exclusive). */
2112 post_mark_life (regno
, mode
, life
, birth
, death
)
2114 enum machine_mode mode
;
2115 int life
, birth
, death
;
2117 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2119 /* Declare it register if it's a scalar. */
2122 HARD_REG_SET this_reg
;
2124 CLEAR_HARD_REG_SET (this_reg
);
2126 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2129 while (birth
< death
)
2131 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2135 while (birth
< death
)
2137 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2142 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2143 is the register being clobbered, and R1 is a register being used in
2144 the equivalent expression.
2146 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2147 in which it is used, return 1.
2149 Otherwise, return 0. */
2152 no_conflict_p (insn
, r0
, r1
)
2153 rtx insn
, r0 ATTRIBUTE_UNUSED
, r1
;
2156 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2159 /* If R1 is a hard register, return 0 since we handle this case
2160 when we scan the insns that actually use it. */
2163 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2164 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2165 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2168 last
= XEXP (note
, 0);
2170 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2171 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
2173 if (find_reg_note (p
, REG_DEAD
, r1
))
2176 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2177 some earlier optimization pass has inserted instructions into
2178 the sequence, and it is not safe to perform this optimization.
2179 Note that emit_no_conflict_block always ensures that this is
2180 true when these sequences are created. */
2181 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2188 /* Return the number of alternatives for which the constraint string P
2189 indicates that the operand must be equal to operand 0 and that no register
2198 int reg_allowed
= 0;
2199 int num_matching_alts
= 0;
2204 case '=': case '+': case '?':
2205 case '#': case '&': case '!':
2207 case '1': case '2': case '3': case '4': case '5':
2208 case '6': case '7': case '8': case '9':
2209 case 'm': case '<': case '>': case 'V': case 'o':
2210 case 'E': case 'F': case 'G': case 'H':
2211 case 's': case 'i': case 'n':
2212 case 'I': case 'J': case 'K': case 'L':
2213 case 'M': case 'N': case 'O': case 'P':
2214 #ifdef EXTRA_CONSTRAINT
2215 case 'Q': case 'R': case 'S': case 'T': case 'U':
2218 /* These don't say anything we care about. */
2222 if (found_zero
&& ! reg_allowed
)
2223 num_matching_alts
++;
2225 found_zero
= reg_allowed
= 0;
2239 if (found_zero
&& ! reg_allowed
)
2240 num_matching_alts
++;
2242 return num_matching_alts
;
2246 dump_local_alloc (file
)
2250 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2251 if (reg_renumber
[i
] != -1)
2252 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);