1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Allocation of hard register numbers to pseudo registers is done in
22 two passes. In this pass we consider only regs that are born and
23 die once within one basic block. We do this one basic block at a
24 time. Then the next pass allocates the registers that remain.
25 Two passes are used because this pass uses methods that work only
26 on linear code, but that do a better job than the general methods
27 used in global_alloc, and more quickly too.
29 The assignments made are recorded in the vector reg_renumber
30 whose space is allocated here. The rtl code itself is not altered.
32 We assign each instruction in the basic block a number
33 which is its order from the beginning of the block.
34 Then we can represent the lifetime of a pseudo register with
35 a pair of numbers, and check for conflicts easily.
36 We can record the availability of hard registers with a
37 HARD_REG_SET for each instruction. The HARD_REG_SET
38 contains 0 or 1 for each hard reg.
40 To avoid register shuffling, we tie registers together when one
41 dies by being copied into another, or dies in an instruction that
42 does arithmetic to produce another. The tied registers are
43 allocated as one. Registers with different reg class preferences
44 can never be tied unless the class preferred by one is a subclass
45 of the one preferred by the other.
47 Tying is represented with "quantity numbers".
48 A non-tied register is given a new quantity number.
49 Tied registers have the same quantity number.
51 We have provision to exempt registers, even when they are contained
52 within the block, that can be tied to others that are not contained in it.
53 This is so that global_alloc could process them both and tie them then.
54 But this is currently disabled since tying in global_alloc is not
61 #include "basic-block.h"
63 #include "hard-reg-set.h"
64 #include "insn-config.h"
68 /* Next quantity number available for allocation. */
72 /* In all the following vectors indexed by quantity number. */
74 /* Element Q is the hard reg number chosen for quantity Q,
75 or -1 if none was found. */
77 static short *qty_phys_reg
;
79 /* We maintain two hard register sets that indicate suggested hard registers
80 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
81 that are tied to the quantity by a simple copy. The second contains all
82 hard registers that are tied to the quantity via an arithmetic operation.
84 The former register set is given priority for allocation. This tends to
85 eliminate copy insns. */
87 /* Element Q is a set of hard registers that are suggested for quantity Q by
90 static HARD_REG_SET
*qty_phys_copy_sugg
;
92 /* Element Q is a set of hard registers that are suggested for quantity Q by
95 static HARD_REG_SET
*qty_phys_sugg
;
97 /* Element Q is non-zero if there is a suggested register in
98 qty_phys_copy_sugg. */
100 static char *qty_phys_has_copy_sugg
;
102 /* Element Q is non-zero if there is a suggested register in qty_phys_sugg. */
104 static char *qty_phys_has_sugg
;
106 /* Element Q is the number of refs to quantity Q. */
108 static short *qty_n_refs
;
110 /* Element Q is a reg class contained in (smaller than) the
111 preferred classes of all the pseudo regs that are tied in quantity Q.
112 This is the preferred class for allocating that quantity. */
114 static enum reg_class
*qty_min_class
;
116 /* Insn number (counting from head of basic block)
117 where quantity Q was born. -1 if birth has not been recorded. */
119 static int *qty_birth
;
121 /* Insn number (counting from head of basic block)
122 where quantity Q died. Due to the way tying is done,
123 and the fact that we consider in this pass only regs that die but once,
124 a quantity can die only once. Each quantity's life span
125 is a set of consecutive insns. -1 if death has not been recorded. */
127 static int *qty_death
;
129 /* Number of words needed to hold the data in quantity Q.
130 This depends on its machine mode. It is used for these purposes:
131 1. It is used in computing the relative importances of qtys,
132 which determines the order in which we look for regs for them.
133 2. It is used in rules that prevent tying several registers of
134 different sizes in a way that is geometrically impossible
135 (see combine_regs). */
137 static int *qty_size
;
139 /* This holds the mode of the registers that are tied to qty Q,
140 or VOIDmode if registers with differing modes are tied together. */
142 static enum machine_mode
*qty_mode
;
144 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
146 static int *qty_n_calls_crossed
;
148 /* Register class within which we allocate qty Q if we can't get
149 its preferred class. */
151 static enum reg_class
*qty_alternate_class
;
153 /* Element Q is the SCRATCH expression for which this quantity is being
154 allocated or 0 if this quantity is allocating registers. */
156 static rtx
*qty_scratch_rtx
;
158 /* Element Q is the register number of one pseudo register whose
159 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
160 register should be the head of the chain maintained in reg_next_in_qty. */
162 static short *qty_first_reg
;
164 /* If (REG N) has been assigned a quantity number, is a register number
165 of another register assigned the same quantity number, or -1 for the
166 end of the chain. qty_first_reg point to the head of this chain. */
168 static short *reg_next_in_qty
;
170 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
172 of -1 if this register cannot be allocated by local-alloc,
173 or -2 if not known yet.
175 Note that if we see a use or death of pseudo register N with
176 reg_qty[N] == -2, register N must be local to the current block. If
177 it were used in more than one block, we would have reg_qty[N] == -1.
178 This relies on the fact that if reg_basic_block[N] is >= 0, register N
179 will not appear in any other block. We save a considerable number of
180 tests by exploiting this.
182 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
187 /* The offset (in words) of register N within its quantity.
188 This can be nonzero if register N is SImode, and has been tied
189 to a subreg of a DImode register. */
191 static char *reg_offset
;
193 /* Vector of substitutions of register numbers,
194 used to map pseudo regs into hardware regs.
195 This is set up as a result of register allocation.
196 Element N is the hard reg assigned to pseudo reg N,
197 or is -1 if no hard reg was assigned.
198 If N is a hard reg number, element N is N. */
202 /* Set of hard registers live at the current point in the scan
203 of the instructions in a basic block. */
205 static HARD_REG_SET regs_live
;
207 /* Each set of hard registers indicates registers live at a particular
208 point in the basic block. For N even, regs_live_at[N] says which
209 hard registers are needed *after* insn N/2 (i.e., they may not
210 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
212 If an object is to conflict with the inputs of insn J but not the
213 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
214 if it is to conflict with the outputs of insn J but not the inputs of
215 insn J + 1, it is said to die at index J*2 + 1. */
217 static HARD_REG_SET
*regs_live_at
;
219 /* Communicate local vars `insn_number' and `insn'
220 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
221 static int this_insn_number
;
222 static rtx this_insn
;
224 static void block_alloc ();
225 static void update_equiv_regs ();
226 static int no_conflict_p ();
227 static int combine_regs ();
228 static void wipe_dead_reg ();
229 static int find_free_reg ();
230 static void reg_is_born ();
231 static void reg_is_set ();
232 static void mark_life ();
233 static void post_mark_life ();
234 static int qty_compare ();
235 static int qty_compare_1 ();
236 static int reg_meets_class_p ();
237 static void update_qty_class ();
238 static int requires_inout_p ();
240 /* Allocate a new quantity (new within current basic block)
241 for register number REGNO which is born at index BIRTH
242 within the block. MODE and SIZE are info on reg REGNO. */
245 alloc_qty (regno
, mode
, size
, birth
)
247 enum machine_mode mode
;
250 register int qty
= next_qty
++;
252 reg_qty
[regno
] = qty
;
253 reg_offset
[regno
] = 0;
254 reg_next_in_qty
[regno
] = -1;
256 qty_first_reg
[qty
] = regno
;
257 qty_size
[qty
] = size
;
258 qty_mode
[qty
] = mode
;
259 qty_birth
[qty
] = birth
;
260 qty_n_calls_crossed
[qty
] = reg_n_calls_crossed
[regno
];
261 qty_min_class
[qty
] = reg_preferred_class (regno
);
262 qty_alternate_class
[qty
] = reg_alternate_class (regno
);
263 qty_n_refs
[qty
] = reg_n_refs
[regno
];
266 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
267 used as operand N in INSN. We assume here that the SCRATCH is used in
271 alloc_qty_for_scratch (scratch
, n
, insn
, insn_code_num
, insn_number
)
275 int insn_code_num
, insn_number
;
278 enum reg_class
class;
282 #ifdef REGISTER_CONSTRAINTS
283 /* If we haven't yet computed which alternative will be used, do so now.
284 Then set P to the constraints for that alternative. */
285 if (which_alternative
== -1)
286 if (! constrain_operands (insn_code_num
, 0))
289 for (p
= insn_operand_constraint
[insn_code_num
][n
], i
= 0;
290 *p
&& i
< which_alternative
; p
++)
294 /* Compute the class required for this SCRATCH. If we don't need a
295 register, the class will remain NO_REGS. If we guessed the alternative
296 number incorrectly, reload will fix things up for us. */
299 while ((c
= *p
++) != '\0' && c
!= ',')
302 case '=': case '+': case '?':
303 case '#': case '&': case '!':
305 case '0': case '1': case '2': case '3': case '4':
306 case 'm': case '<': case '>': case 'V': case 'o':
307 case 'E': case 'F': case 'G': case 'H':
308 case 's': case 'i': case 'n':
309 case 'I': case 'J': case 'K': case 'L':
310 case 'M': case 'N': case 'O': case 'P':
311 #ifdef EXTRA_CONSTRAINT
312 case 'Q': case 'R': case 'S': case 'T': case 'U':
315 /* These don't say anything we care about. */
319 /* We don't need to allocate this SCRATCH. */
323 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
328 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER (c
)];
332 /* If CLASS has only one register, don't allocate the SCRATCH here since
333 it will prevent that register from being used as a spill register.
334 reload will do the allocation. */
336 if (class == NO_REGS
|| reg_class_size
[(int) class] == 1)
339 #else /* REGISTER_CONSTRAINTS */
341 class = GENERAL_REGS
;
347 qty_first_reg
[qty
] = -1;
348 qty_scratch_rtx
[qty
] = scratch
;
349 qty_size
[qty
] = GET_MODE_SIZE (GET_MODE (scratch
));
350 qty_mode
[qty
] = GET_MODE (scratch
);
351 qty_birth
[qty
] = 2 * insn_number
- 1;
352 qty_death
[qty
] = 2 * insn_number
+ 1;
353 qty_n_calls_crossed
[qty
] = 0;
354 qty_min_class
[qty
] = class;
355 qty_alternate_class
[qty
] = NO_REGS
;
359 /* Main entry point of this file. */
367 /* Leaf functions and non-leaf functions have different needs.
368 If defined, let the machine say what kind of ordering we
370 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
371 ORDER_REGS_FOR_LOCAL_ALLOC
;
374 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
376 update_equiv_regs ();
378 /* This sets the maximum number of quantities we can have. Quantity
379 numbers start at zero and we can have one for each pseudo plus the
380 number of SCRATCHes in the largest block, in the worst case. */
381 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
) + max_scratch
;
383 /* Allocate vectors of temporary data.
384 See the declarations of these variables, above,
385 for what they mean. */
387 qty_phys_reg
= (short *) alloca (max_qty
* sizeof (short));
388 qty_phys_copy_sugg
= (HARD_REG_SET
*) alloca (max_qty
* sizeof (HARD_REG_SET
));
389 qty_phys_has_copy_sugg
= (char *) alloca (max_qty
* sizeof (char));
390 qty_phys_sugg
= (HARD_REG_SET
*) alloca (max_qty
* sizeof (HARD_REG_SET
));
391 qty_phys_has_sugg
= (char *) alloca (max_qty
* sizeof (char));
392 qty_birth
= (int *) alloca (max_qty
* sizeof (int));
393 qty_death
= (int *) alloca (max_qty
* sizeof (int));
394 qty_scratch_rtx
= (rtx
*) alloca (max_qty
* sizeof (rtx
));
395 qty_first_reg
= (short *) alloca (max_qty
* sizeof (short));
396 qty_size
= (int *) alloca (max_qty
* sizeof (int));
397 qty_mode
= (enum machine_mode
*) alloca (max_qty
* sizeof (enum machine_mode
));
398 qty_n_calls_crossed
= (int *) alloca (max_qty
* sizeof (int));
399 qty_min_class
= (enum reg_class
*) alloca (max_qty
* sizeof (enum reg_class
));
400 qty_alternate_class
= (enum reg_class
*) alloca (max_qty
* sizeof (enum reg_class
));
401 qty_n_refs
= (short *) alloca (max_qty
* sizeof (short));
403 reg_qty
= (int *) alloca (max_regno
* sizeof (int));
404 reg_offset
= (char *) alloca (max_regno
* sizeof (char));
405 reg_next_in_qty
= (short *) alloca (max_regno
* sizeof (short));
407 reg_renumber
= (short *) oballoc (max_regno
* sizeof (short));
408 for (i
= 0; i
< max_regno
; i
++)
409 reg_renumber
[i
] = -1;
411 /* Determine which pseudo-registers can be allocated by local-alloc.
412 In general, these are the registers used only in a single block and
413 which only die once. However, if a register's preferred class has only
414 one entry, don't allocate this register here unless it is preferred
415 or nothing since retry_global_alloc won't be able to move it to
416 GENERAL_REGS if a reload register of this class is needed.
418 We need not be concerned with which block actually uses the register
419 since we will never see it outside that block. */
421 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
423 if (reg_basic_block
[i
] >= 0 && reg_n_deaths
[i
] == 1
424 && (reg_alternate_class (i
) == NO_REGS
425 || reg_class_size
[(int) reg_preferred_class (i
)] > 1))
431 /* Force loop below to initialize entire quantity array. */
434 /* Allocate each block's local registers, block by block. */
436 for (b
= 0; b
< n_basic_blocks
; b
++)
438 /* NEXT_QTY indicates which elements of the `qty_...'
439 vectors might need to be initialized because they were used
440 for the previous block; it is set to the entire array before
441 block 0. Initialize those, with explicit loop if there are few,
442 else with bzero and bcopy. Do not initialize vectors that are
443 explicit set by `alloc_qty'. */
447 for (i
= 0; i
< next_qty
; i
++)
449 qty_scratch_rtx
[i
] = 0;
450 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
451 qty_phys_has_copy_sugg
[i
] = 0;
452 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
453 qty_phys_has_sugg
[i
] = 0;
458 #define CLEAR(vector) \
459 bzero ((vector), (sizeof (*(vector))) * next_qty);
461 CLEAR (qty_scratch_rtx
);
462 CLEAR (qty_phys_copy_sugg
);
463 CLEAR (qty_phys_has_copy_sugg
);
464 CLEAR (qty_phys_sugg
);
465 CLEAR (qty_phys_has_sugg
);
477 /* Depth of loops we are in while in update_equiv_regs. */
478 static int loop_depth
;
480 /* Used for communication between the following two functions: contains
481 a MEM that we wish to ensure remains unchanged. */
482 static rtx equiv_mem
;
484 /* Set nonzero if EQUIV_MEM is modified. */
485 static int equiv_mem_modified
;
487 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
488 Called via note_stores. */
491 validate_equiv_mem_from_store (dest
, set
)
495 if ((GET_CODE (dest
) == REG
496 && reg_overlap_mentioned_p (dest
, equiv_mem
))
497 || (GET_CODE (dest
) == MEM
498 && true_dependence (dest
, equiv_mem
)))
499 equiv_mem_modified
= 1;
502 /* Verify that no store between START and the death of REG invalidates
503 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
504 by storing into an overlapping memory location, or with a non-const
507 Return 1 if MEMREF remains valid. */
510 validate_equiv_mem (start
, reg
, memref
)
519 equiv_mem_modified
= 0;
521 /* If the memory reference has side effects or is volatile, it isn't a
522 valid equivalence. */
523 if (side_effects_p (memref
))
526 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
528 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
531 if (find_reg_note (insn
, REG_DEAD
, reg
))
534 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
535 && ! CONST_CALL_P (insn
))
538 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
);
540 /* If a register mentioned in MEMREF is modified via an
541 auto-increment, we lose the equivalence. Do the same if one
542 dies; although we could extend the life, it doesn't seem worth
545 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
546 if ((REG_NOTE_KIND (note
) == REG_INC
547 || REG_NOTE_KIND (note
) == REG_DEAD
)
548 && GET_CODE (XEXP (note
, 0)) == REG
549 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
556 /* TRUE if X references a memory location that would be affected by a store
560 memref_referenced_p (memref
, x
)
566 enum rtx_code code
= GET_CODE (x
);
583 if (true_dependence (memref
, x
))
588 /* If we are setting a MEM, it doesn't count (its address does), but any
589 other SET_DEST that has a MEM in it is referencing the MEM. */
590 if (GET_CODE (SET_DEST (x
)) == MEM
)
592 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
595 else if (memref_referenced_p (memref
, SET_DEST (x
)))
598 return memref_referenced_p (memref
, SET_SRC (x
));
601 fmt
= GET_RTX_FORMAT (code
);
602 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
606 if (memref_referenced_p (memref
, XEXP (x
, i
)))
610 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
611 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
619 /* TRUE if some insn in the range (START, END] references a memory location
620 that would be affected by a store to MEMREF. */
623 memref_used_between_p (memref
, start
, end
)
630 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
631 insn
= NEXT_INSN (insn
))
632 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
633 && memref_referenced_p (memref
, PATTERN (insn
)))
639 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
642 Search forward to see if SRC dies before either it or DEST is modified,
643 but don't scan past the end of a basic block. If so, we can replace SRC
644 with DEST and let SRC die in INSN.
646 This will reduce the number of registers live in that range and may enable
647 DEST to be tied to SRC, thus often saving one register in addition to a
648 register-register copy. */
651 optimize_reg_copy_1 (insn
, dest
, src
)
659 int sregno
= REGNO (src
);
660 int dregno
= REGNO (dest
);
663 #ifdef SMALL_REGISTER_CLASSES
664 /* We don't want to mess with hard regs if register classes are small. */
665 || sregno
< FIRST_PSEUDO_REGISTER
|| dregno
< FIRST_PSEUDO_REGISTER
667 /* We don't see all updates to SP if they are in an auto-inc memory
668 reference, so we must disallow this optimization on them. */
669 || sregno
== STACK_POINTER_REGNUM
|| dregno
== STACK_POINTER_REGNUM
)
672 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
674 if (GET_CODE (p
) == CODE_LABEL
|| GET_CODE (p
) == JUMP_INSN
675 || (GET_CODE (p
) == NOTE
676 && (NOTE_LINE_NUMBER (p
) == NOTE_INSN_LOOP_BEG
677 || NOTE_LINE_NUMBER (p
) == NOTE_INSN_LOOP_END
)))
680 if (GET_RTX_CLASS (GET_CODE (p
)) != 'i')
683 if (reg_set_p (src
, p
) || reg_set_p (dest
, p
)
684 /* Don't change a USE of a register. */
685 || (GET_CODE (PATTERN (p
)) == USE
686 && reg_overlap_mentioned_p (src
, XEXP (PATTERN (p
), 0))))
689 if ((note
= find_regno_note (p
, REG_DEAD
, sregno
)) != 0)
695 /* We can do the optimization. Scan forward from INSN again,
696 replacing regs as we go. Set FAILED if a replacement can't
697 be done. In that case, we can't move the death note for SRC.
698 This should be rare. */
700 /* Set to stop at next insn. */
701 for (q
= next_real_insn (insn
);
702 q
!= next_real_insn (p
);
703 q
= next_real_insn (q
))
705 if (reg_mentioned_p (src
, PATTERN (q
)))
707 if (validate_replace_rtx (src
, dest
, q
))
709 /* We assume that a register is used exactly once per
710 insn in the updates below. If this is not correct,
711 no great harm is done. */
712 if (sregno
>= FIRST_PSEUDO_REGISTER
)
713 reg_n_refs
[sregno
] -= loop_depth
;
714 if (dregno
>= FIRST_PSEUDO_REGISTER
)
715 reg_n_refs
[dregno
] += loop_depth
;
721 /* Count the insns and CALL_INSNs passed. If we passed the
722 death note of DEST, show increased live length. */
725 reg_live_length
[dregno
]++;
727 if (GET_CODE (q
) == CALL_INSN
)
731 reg_n_calls_crossed
[dregno
]++;
734 /* If DEST dies here, remove the death note and save it for
737 && (dest_death
= find_regno_note (q
, REG_DEAD
, dregno
)) != 0)
738 remove_note (q
, dest_death
);
743 if (sregno
>= FIRST_PSEUDO_REGISTER
)
745 reg_live_length
[sregno
] -= length
;
746 reg_n_calls_crossed
[sregno
] -= n_calls
;
749 /* Move death note of SRC from P to INSN. */
750 remove_note (p
, note
);
751 XEXP (note
, 1) = REG_NOTES (insn
);
752 REG_NOTES (insn
) = note
;
755 /* Put death note of DEST on P if we saw it die. */
758 XEXP (dest_death
, 1) = REG_NOTES (p
);
759 REG_NOTES (p
) = dest_death
;
767 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
768 a sequence of insns that modify DEST followed by an insn that sets
769 SRC to DEST in which DEST dies, with no prior modification of DEST.
770 (There is no need to check if the insns in between actually modify
771 DEST. We should not have cases where DEST is not modified, but
772 the optimization is safe if no such modification is detected.)
773 In that case, we can replace all uses of DEST, starting with INSN and
774 ending with the set of SRC to DEST, with SRC. We do not do this
775 optimization if a CALL_INSN is crossed unless SRC already crosses a
778 It is assumed that DEST and SRC are pseudos; it is too complicated to do
779 this for hard registers since the substitutions we may make might fail. */
782 optimize_reg_copy_2 (insn
, dest
, src
)
789 int sregno
= REGNO (src
);
790 int dregno
= REGNO (dest
);
792 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
794 if (GET_CODE (p
) == CODE_LABEL
|| GET_CODE (p
) == JUMP_INSN
795 || (GET_CODE (p
) == NOTE
796 && (NOTE_LINE_NUMBER (p
) == NOTE_INSN_LOOP_BEG
797 || NOTE_LINE_NUMBER (p
) == NOTE_INSN_LOOP_END
)))
800 if (GET_RTX_CLASS (GET_CODE (p
)) != 'i')
803 set
= single_set (p
);
804 if (set
&& SET_SRC (set
) == dest
&& SET_DEST (set
) == src
805 && find_reg_note (p
, REG_DEAD
, dest
))
807 /* We can do the optimization. Scan forward from INSN again,
808 replacing regs as we go. */
810 /* Set to stop at next insn. */
811 for (q
= insn
; q
!= NEXT_INSN (p
); q
= NEXT_INSN (q
))
812 if (GET_RTX_CLASS (GET_CODE (q
)) == 'i')
814 if (reg_mentioned_p (dest
, PATTERN (q
)))
816 PATTERN (q
) = replace_rtx (PATTERN (q
), dest
, src
);
818 /* We assume that a register is used exactly once per
819 insn in the updates below. If this is not correct,
820 no great harm is done. */
821 reg_n_refs
[sregno
] -= loop_depth
;
822 reg_n_refs
[dregno
] += loop_depth
;
826 if (GET_CODE (q
) == CALL_INSN
)
828 reg_n_calls_crossed
[dregno
]--;
829 reg_n_calls_crossed
[sregno
]++;
833 remove_note (p
, find_reg_note (p
, REG_DEAD
, dest
));
834 reg_n_deaths
[dregno
]--;
835 remove_note (insn
, find_reg_note (insn
, REG_DEAD
, src
));
836 reg_n_deaths
[sregno
]--;
840 if (reg_set_p (src
, p
)
841 || (GET_CODE (p
) == CALL_INSN
&& reg_n_calls_crossed
[sregno
] == 0))
846 /* Find registers that are equivalent to a single value throughout the
847 compilation (either because they can be referenced in memory or are set once
848 from a single constant). Lower their priority for a register.
850 If such a register is only referenced once, try substituting its value
851 into the using insn. If it succeeds, we can eliminate the register
857 rtx
*reg_equiv_init_insn
= (rtx
*) alloca (max_regno
* sizeof (rtx
*));
858 rtx
*reg_equiv_replacement
= (rtx
*) alloca (max_regno
* sizeof (rtx
*));
861 bzero (reg_equiv_init_insn
, max_regno
* sizeof (rtx
*));
862 bzero (reg_equiv_replacement
, max_regno
* sizeof (rtx
*));
864 init_alias_analysis ();
868 /* Scan the insns and find which registers have equivalences. Do this
869 in a separate scan of the insns because (due to -fcse-follow-jumps)
870 a register can be set below its use. */
871 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
874 rtx set
= single_set (insn
);
878 if (GET_CODE (insn
) == NOTE
)
880 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
882 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
886 /* If this insn contains more (or less) than a single SET, ignore it. */
890 dest
= SET_DEST (set
);
892 /* If this sets a MEM to the contents of a REG that is only used
893 in a single basic block, see if the register is always equivalent
894 to that memory location and if moving the store from INSN to the
895 insn that set REG is safe. If so, put a REG_EQUIV note on the
896 initializing insn. */
898 if (GET_CODE (dest
) == MEM
&& GET_CODE (SET_SRC (set
)) == REG
899 && (regno
= REGNO (SET_SRC (set
))) >= FIRST_PSEUDO_REGISTER
900 && reg_basic_block
[regno
] >= 0
901 && reg_equiv_init_insn
[regno
] != 0
902 && validate_equiv_mem (reg_equiv_init_insn
[regno
], SET_SRC (set
),
904 && ! memref_used_between_p (SET_DEST (set
),
905 reg_equiv_init_insn
[regno
], insn
))
906 REG_NOTES (reg_equiv_init_insn
[regno
])
907 = gen_rtx (EXPR_LIST
, REG_EQUIV
, dest
,
908 REG_NOTES (reg_equiv_init_insn
[regno
]));
910 /* If this is a register-register copy where SRC is not dead, see if we
912 if (flag_expensive_optimizations
&& GET_CODE (dest
) == REG
913 && GET_CODE (SET_SRC (set
)) == REG
914 && ! find_reg_note (insn
, REG_DEAD
, SET_SRC (set
)))
915 optimize_reg_copy_1 (insn
, dest
, SET_SRC (set
));
917 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
918 else if (flag_expensive_optimizations
&& GET_CODE (dest
) == REG
919 && REGNO (dest
) >= FIRST_PSEUDO_REGISTER
920 && GET_CODE (SET_SRC (set
)) == REG
921 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
922 && find_reg_note (insn
, REG_DEAD
, SET_SRC (set
)))
923 optimize_reg_copy_2 (insn
, dest
, SET_SRC (set
));
925 /* Otherwise, we only handle the case of a pseudo register being set
927 if (GET_CODE (dest
) != REG
928 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
929 || reg_n_sets
[regno
] != 1)
932 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
934 /* Record this insn as initializing this register. */
935 reg_equiv_init_insn
[regno
] = insn
;
937 /* If this register is known to be equal to a constant, record that
938 it is always equivalent to the constant. */
939 if (note
&& CONSTANT_P (XEXP (note
, 0)))
940 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
942 /* If this insn introduces a "constant" register, decrease the priority
943 of that register. Record this insn if the register is only used once
944 more and the equivalence value is the same as our source.
946 The latter condition is checked for two reasons: First, it is an
947 indication that it may be more efficient to actually emit the insn
948 as written (if no registers are available, reload will substitute
949 the equivalence). Secondly, it avoids problems with any registers
950 dying in this insn whose death notes would be missed.
952 If we don't have a REG_EQUIV note, see if this insn is loading
953 a register used only in one basic block from a MEM. If so, and the
954 MEM remains unchanged for the life of the register, add a REG_EQUIV
957 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
959 if (note
== 0 && reg_basic_block
[regno
] >= 0
960 && GET_CODE (SET_SRC (set
)) == MEM
961 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
962 REG_NOTES (insn
) = note
= gen_rtx (EXPR_LIST
, REG_EQUIV
, SET_SRC (set
),
965 /* Don't mess with things live during setjmp. */
966 if (note
&& reg_live_length
[regno
] >= 0)
968 int regno
= REGNO (dest
);
970 /* Note that the statement below does not affect the priority
972 reg_live_length
[regno
] *= 2;
974 /* If the register is referenced exactly twice, meaning it is set
975 once and used once, indicate that the reference may be replaced
976 by the equivalence we computed above. If the register is only
977 used in one basic block, this can't succeed or combine would
980 It would be nice to use "loop_depth * 2" in the compare
981 below. Unfortunately, LOOP_DEPTH need not be constant within
982 a basic block so this would be too complicated.
984 This case normally occurs when a parameter is read from memory
985 and then used exactly once, not in a loop. */
987 if (reg_n_refs
[regno
] == 2
988 && reg_basic_block
[regno
] < 0
989 && rtx_equal_p (XEXP (note
, 0), SET_SRC (set
)))
990 reg_equiv_replacement
[regno
] = SET_SRC (set
);
994 /* Now scan all regs killed in an insn to see if any of them are registers
995 only used that once. If so, see if we can replace the reference with
996 the equivalent from. If we can, delete the initializing reference
997 and this register will go away. */
998 for (insn
= next_active_insn (get_insns ());
1000 insn
= next_active_insn (insn
))
1004 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1005 if (REG_NOTE_KIND (link
) == REG_DEAD
1006 /* Make sure this insn still refers to the register. */
1007 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
1009 int regno
= REGNO (XEXP (link
, 0));
1011 if (reg_equiv_replacement
[regno
]
1012 && validate_replace_rtx (regno_reg_rtx
[regno
],
1013 reg_equiv_replacement
[regno
], insn
))
1015 rtx equiv_insn
= reg_equiv_init_insn
[regno
];
1017 remove_death (regno
, insn
);
1018 reg_n_refs
[regno
] = 0;
1019 PUT_CODE (equiv_insn
, NOTE
);
1020 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1021 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1027 /* Allocate hard regs to the pseudo regs used only within block number B.
1028 Only the pseudos that die but once can be handled. */
1037 int insn_number
= 0;
1039 int max_uid
= get_max_uid ();
1041 int no_conflict_combined_regno
= -1;
1043 /* Count the instructions in the basic block. */
1045 insn
= basic_block_end
[b
];
1048 if (GET_CODE (insn
) != NOTE
)
1049 if (++insn_count
> max_uid
)
1051 if (insn
== basic_block_head
[b
])
1053 insn
= PREV_INSN (insn
);
1056 /* +2 to leave room for a post_mark_life at the last insn and for
1057 the birth of a CLOBBER in the first insn. */
1058 regs_live_at
= (HARD_REG_SET
*) alloca ((2 * insn_count
+ 2)
1059 * sizeof (HARD_REG_SET
));
1060 bzero (regs_live_at
, (2 * insn_count
+ 2) * sizeof (HARD_REG_SET
));
1062 /* Initialize table of hardware registers currently live. */
1065 regs_live
= *basic_block_live_at_start
[b
];
1067 COPY_HARD_REG_SET (regs_live
, basic_block_live_at_start
[b
]);
1070 /* This loop scans the instructions of the basic block
1071 and assigns quantities to registers.
1072 It computes which registers to tie. */
1074 insn
= basic_block_head
[b
];
1077 register rtx body
= PATTERN (insn
);
1079 if (GET_CODE (insn
) != NOTE
)
1082 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1084 register rtx link
, set
;
1085 register int win
= 0;
1086 register rtx r0
, r1
;
1087 int combined_regno
= -1;
1089 int insn_code_number
= recog_memoized (insn
);
1091 this_insn_number
= insn_number
;
1094 if (insn_code_number
>= 0)
1095 insn_extract (insn
);
1096 which_alternative
= -1;
1098 /* Is this insn suitable for tying two registers?
1099 If so, try doing that.
1100 Suitable insns are those with at least two operands and where
1101 operand 0 is an output that is a register that is not
1103 For a commutative operation, try (set reg0 (arithop ... reg1)).
1104 Subregs in place of regs are also ok.
1106 If tying is done, WIN is set nonzero. */
1108 if (insn_code_number
>= 0
1109 #ifdef REGISTER_CONSTRAINTS
1110 && insn_n_operands
[insn_code_number
] > 1
1111 && insn_operand_constraint
[insn_code_number
][0][0] == '='
1112 && insn_operand_constraint
[insn_code_number
][0][1] != '&'
1114 && GET_CODE (PATTERN (insn
)) == SET
1115 && rtx_equal_p (SET_DEST (PATTERN (insn
)), recog_operand
[0])
1119 r0
= recog_operand
[0];
1120 r1
= recog_operand
[1];
1122 /* If the first operand is an address, find a register in it.
1123 There may be more than one register, but we only try one of
1126 #ifdef REGISTER_CONSTRAINTS
1127 insn_operand_constraint
[insn_code_number
][1][0] == 'p'
1129 insn_operand_address_p
[insn_code_number
][1]
1132 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1135 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1137 /* We have two priorities for hard register preferences.
1138 If we have a move insn or an insn whose first input can
1139 only be in the same register as the output, give
1140 priority to an equivalence found from that insn. */
1141 #ifdef REGISTER_CONSTRAINTS
1143 = ((SET_DEST (body
) == r0
&& SET_SRC (body
) == r1
)
1144 || (r1
== recog_operand
[1]
1145 && (requires_inout_p (insn_operand_constraint
[insn_code_number
][1]))));
1147 int may_save_copy
= 0;
1150 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1151 win
= combine_regs (r1
, r0
, may_save_copy
,
1152 insn_number
, insn
, 0);
1155 && insn_n_operands
[insn_code_number
] > 2
1156 #ifdef REGISTER_CONSTRAINTS
1157 && insn_operand_constraint
[insn_code_number
][1][0] == '%'
1159 && GET_CODE (PATTERN (insn
)) == SET
1160 && (GET_RTX_CLASS (GET_CODE (SET_SRC (PATTERN (insn
))))
1162 && rtx_equal_p (recog_operand
[2],
1163 XEXP (SET_SRC (PATTERN (insn
)), 0))
1165 && (r1
= recog_operand
[2],
1166 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1167 win
= combine_regs (r1
, r0
, may_save_copy
,
1168 insn_number
, insn
, 0);
1172 /* Recognize an insn sequence with an ultimate result
1173 which can safely overlap one of the inputs.
1174 The sequence begins with a CLOBBER of its result,
1175 and ends with an insn that copies the result to itself
1176 and has a REG_EQUAL note for an equivalent formula.
1177 That note indicates what the inputs are.
1178 The result and the input can overlap if each insn in
1179 the sequence either doesn't mention the input
1180 or has a REG_NO_CONFLICT note to inhibit the conflict.
1182 We do the combining test at the CLOBBER so that the
1183 destination register won't have had a quantity number
1184 assigned, since that would prevent combining. */
1186 if (GET_CODE (PATTERN (insn
)) == CLOBBER
1187 && (r0
= XEXP (PATTERN (insn
), 0),
1188 GET_CODE (r0
) == REG
)
1189 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1190 && GET_CODE (XEXP (link
, 0)) == INSN
1191 && (set
= single_set (XEXP (link
, 0))) != 0
1192 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1193 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1196 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1197 /* Check that we have such a sequence. */
1198 && no_conflict_p (insn
, r0
, r1
))
1199 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1200 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1201 && (r1
= XEXP (XEXP (note
, 0), 0),
1202 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1203 && no_conflict_p (insn
, r0
, r1
))
1204 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1206 /* Here we care if the operation to be computed is
1208 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1209 || GET_CODE (XEXP (note
, 0)) == NE
1210 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1211 && (r1
= XEXP (XEXP (note
, 0), 1),
1212 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1213 && no_conflict_p (insn
, r0
, r1
))
1214 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1216 /* If we did combine something, show the register number
1217 in question so that we know to ignore its death. */
1219 no_conflict_combined_regno
= REGNO (r1
);
1222 /* If registers were just tied, set COMBINED_REGNO
1223 to the number of the register used in this insn
1224 that was tied to the register set in this insn.
1225 This register's qty should not be "killed". */
1229 while (GET_CODE (r1
) == SUBREG
)
1230 r1
= SUBREG_REG (r1
);
1231 combined_regno
= REGNO (r1
);
1234 /* Mark the death of everything that dies in this instruction,
1235 except for anything that was just combined. */
1237 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1238 if (REG_NOTE_KIND (link
) == REG_DEAD
1239 && GET_CODE (XEXP (link
, 0)) == REG
1240 && combined_regno
!= REGNO (XEXP (link
, 0))
1241 && (no_conflict_combined_regno
!= REGNO (XEXP (link
, 0))
1242 || ! find_reg_note (insn
, REG_NO_CONFLICT
, XEXP (link
, 0))))
1243 wipe_dead_reg (XEXP (link
, 0), 0);
1245 /* Allocate qty numbers for all registers local to this block
1246 that are born (set) in this instruction.
1247 A pseudo that already has a qty is not changed. */
1249 note_stores (PATTERN (insn
), reg_is_set
);
1251 /* If anything is set in this insn and then unused, mark it as dying
1252 after this insn, so it will conflict with our outputs. This
1253 can't match with something that combined, and it doesn't matter
1254 if it did. Do this after the calls to reg_is_set since these
1255 die after, not during, the current insn. */
1257 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1258 if (REG_NOTE_KIND (link
) == REG_UNUSED
1259 && GET_CODE (XEXP (link
, 0)) == REG
)
1260 wipe_dead_reg (XEXP (link
, 0), 1);
1262 #ifndef SMALL_REGISTER_CLASSES
1263 /* Allocate quantities for any SCRATCH operands of this insn. We
1264 don't do this for machines with small register classes because
1265 those machines can use registers explicitly mentioned in the
1266 RTL as spill registers and our usage of hard registers
1267 explicitly for SCRATCH operands will conflict. On those machines,
1268 reload will allocate the SCRATCH. */
1270 if (insn_code_number
>= 0)
1271 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1272 if (GET_CODE (recog_operand
[i
]) == SCRATCH
)
1273 alloc_qty_for_scratch (recog_operand
[i
], i
, insn
,
1274 insn_code_number
, insn_number
);
1277 /* If this is an insn that has a REG_RETVAL note pointing at a
1278 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1279 block, so clear any register number that combined within it. */
1280 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1281 && GET_CODE (XEXP (note
, 0)) == INSN
1282 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1283 no_conflict_combined_regno
= -1;
1286 /* Set the registers live after INSN_NUMBER. Note that we never
1287 record the registers live before the block's first insn, since no
1288 pseudos we care about are live before that insn. */
1290 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1291 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1293 if (insn
== basic_block_end
[b
])
1296 insn
= NEXT_INSN (insn
);
1299 /* Now every register that is local to this basic block
1300 should have been given a quantity, or else -1 meaning ignore it.
1301 Every quantity should have a known birth and death.
1303 Order the qtys so we assign them registers in order of
1304 decreasing length of life. Normally call qsort, but if we
1305 have only a very small number of quantities, sort them ourselves. */
1307 qty_order
= (short *) alloca (next_qty
* sizeof (short));
1308 for (i
= 0; i
< next_qty
; i
++)
1311 #define EXCHANGE(I1, I2) \
1312 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1317 /* Make qty_order[2] be the one to allocate last. */
1318 if (qty_compare (0, 1) > 0)
1320 if (qty_compare (1, 2) > 0)
1323 /* ... Fall through ... */
1325 /* Put the best one to allocate in qty_order[0]. */
1326 if (qty_compare (0, 1) > 0)
1329 /* ... Fall through ... */
1333 /* Nothing to do here. */
1337 qsort (qty_order
, next_qty
, sizeof (short), qty_compare_1
);
1340 /* Try to put each quantity in a suggested physical register, if it has one.
1341 This may cause registers to be allocated that otherwise wouldn't be, but
1342 this seems acceptable in local allocation (unlike global allocation). */
1343 for (i
= 0; i
< next_qty
; i
++)
1346 if (qty_phys_has_sugg
[q
] || qty_phys_has_copy_sugg
[q
])
1347 qty_phys_reg
[q
] = find_free_reg (qty_min_class
[q
], qty_mode
[q
], q
,
1348 0, 1, qty_birth
[q
], qty_death
[q
]);
1350 qty_phys_reg
[q
] = -1;
1353 /* Now for each qty that is not a hardware register,
1354 look for a hardware register to put it in.
1355 First try the register class that is cheapest for this qty,
1356 if there is more than one class. */
1358 for (i
= 0; i
< next_qty
; i
++)
1361 if (qty_phys_reg
[q
] < 0)
1363 if (N_REG_CLASSES
> 1)
1365 qty_phys_reg
[q
] = find_free_reg (qty_min_class
[q
],
1366 qty_mode
[q
], q
, 0, 0,
1367 qty_birth
[q
], qty_death
[q
]);
1368 if (qty_phys_reg
[q
] >= 0)
1372 if (qty_alternate_class
[q
] != NO_REGS
)
1373 qty_phys_reg
[q
] = find_free_reg (qty_alternate_class
[q
],
1374 qty_mode
[q
], q
, 0, 0,
1375 qty_birth
[q
], qty_death
[q
]);
1379 /* Now propagate the register assignments
1380 to the pseudo regs belonging to the qtys. */
1382 for (q
= 0; q
< next_qty
; q
++)
1383 if (qty_phys_reg
[q
] >= 0)
1385 for (i
= qty_first_reg
[q
]; i
>= 0; i
= reg_next_in_qty
[i
])
1386 reg_renumber
[i
] = qty_phys_reg
[q
] + reg_offset
[i
];
1387 if (qty_scratch_rtx
[q
])
1389 PUT_CODE (qty_scratch_rtx
[q
], REG
);
1390 REGNO (qty_scratch_rtx
[q
]) = qty_phys_reg
[q
];
1392 for (i
= HARD_REGNO_NREGS (qty_phys_reg
[q
],
1393 GET_MODE (qty_scratch_rtx
[q
])) - 1;
1395 regs_ever_live
[qty_phys_reg
[q
] + i
] = 1;
1397 /* Must clear the USED field, because it will have been set by
1398 copy_rtx_if_shared, but the leaf_register code expects that
1399 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1400 used bit for REGs, but does for SCRATCHes. */
1401 qty_scratch_rtx
[q
]->used
= 0;
1406 /* Compare two quantities' priority for getting real registers.
1407 We give shorter-lived quantities higher priority.
1408 Quantities with more references are also preferred, as are quantities that
1409 require multiple registers. This is the identical prioritization as
1410 done by global-alloc.
1412 We used to give preference to registers with *longer* lives, but using
1413 the same algorithm in both local- and global-alloc can speed up execution
1414 of some programs by as much as a factor of three! */
1417 qty_compare (q1
, q2
)
1420 /* Note that the quotient will never be bigger than
1421 the value of floor_log2 times the maximum number of
1422 times a register can occur in one insn (surely less than 100).
1423 Multiplying this by 10000 can't overflow. */
1425 = (((double) (floor_log2 (qty_n_refs
[q1
]) * qty_n_refs
[q1
])
1426 / ((qty_death
[q1
] - qty_birth
[q1
]) * qty_size
[q1
]))
1429 = (((double) (floor_log2 (qty_n_refs
[q2
]) * qty_n_refs
[q2
])
1430 / ((qty_death
[q2
] - qty_birth
[q2
]) * qty_size
[q2
]))
1436 qty_compare_1 (q1
, q2
)
1441 /* Note that the quotient will never be bigger than
1442 the value of floor_log2 times the maximum number of
1443 times a register can occur in one insn (surely less than 100).
1444 Multiplying this by 10000 can't overflow. */
1446 = (((double) (floor_log2 (qty_n_refs
[*q1
]) * qty_n_refs
[*q1
])
1447 / ((qty_death
[*q1
] - qty_birth
[*q1
]) * qty_size
[*q1
]))
1450 = (((double) (floor_log2 (qty_n_refs
[*q2
]) * qty_n_refs
[*q2
])
1451 / ((qty_death
[*q2
] - qty_birth
[*q2
]) * qty_size
[*q2
]))
1455 if (tem
!= 0) return tem
;
1456 /* If qtys are equally good, sort by qty number,
1457 so that the results of qsort leave nothing to chance. */
1461 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1462 Returns 1 if have done so, or 0 if cannot.
1464 Combining registers means marking them as having the same quantity
1465 and adjusting the offsets within the quantity if either of
1468 We don't actually combine a hard reg with a pseudo; instead
1469 we just record the hard reg as the suggestion for the pseudo's quantity.
1470 If we really combined them, we could lose if the pseudo lives
1471 across an insn that clobbers the hard reg (eg, movstr).
1473 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1474 there is no REG_DEAD note on INSN. This occurs during the processing
1475 of REG_NO_CONFLICT blocks.
1477 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1478 SETREG or if the input and output must share a register.
1479 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1481 There are elaborate checks for the validity of combining. */
1485 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1486 rtx usedreg
, setreg
;
1492 register int ureg
, sreg
;
1493 register int offset
= 0;
1497 /* Determine the numbers and sizes of registers being used. If a subreg
1498 is present that does not change the entire register, don't consider
1499 this a copy insn. */
1501 while (GET_CODE (usedreg
) == SUBREG
)
1503 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg
))) > UNITS_PER_WORD
)
1505 offset
+= SUBREG_WORD (usedreg
);
1506 usedreg
= SUBREG_REG (usedreg
);
1508 if (GET_CODE (usedreg
) != REG
)
1510 ureg
= REGNO (usedreg
);
1511 usize
= REG_SIZE (usedreg
);
1513 while (GET_CODE (setreg
) == SUBREG
)
1515 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg
))) > UNITS_PER_WORD
)
1517 offset
-= SUBREG_WORD (setreg
);
1518 setreg
= SUBREG_REG (setreg
);
1520 if (GET_CODE (setreg
) != REG
)
1522 sreg
= REGNO (setreg
);
1523 ssize
= REG_SIZE (setreg
);
1525 /* If UREG is a pseudo-register that hasn't already been assigned a
1526 quantity number, it means that it is not local to this block or dies
1527 more than once. In either event, we can't do anything with it. */
1528 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1529 /* Do not combine registers unless one fits within the other. */
1530 || (offset
> 0 && usize
+ offset
> ssize
)
1531 || (offset
< 0 && usize
+ offset
< ssize
)
1532 /* Do not combine with a smaller already-assigned object
1533 if that smaller object is already combined with something bigger. */
1534 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1535 && usize
< qty_size
[reg_qty
[ureg
]])
1536 /* Can't combine if SREG is not a register we can allocate. */
1537 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1538 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1539 These have already been taken care of. This probably wouldn't
1540 combine anyway, but don't take any chances. */
1541 || (ureg
>= FIRST_PSEUDO_REGISTER
1542 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1543 /* Don't tie something to itself. In most cases it would make no
1544 difference, but it would screw up if the reg being tied to itself
1545 also dies in this insn. */
1547 /* Don't try to connect two different hardware registers. */
1548 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1549 /* Don't connect two different machine modes if they have different
1550 implications as to which registers may be used. */
1551 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1554 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1555 qty_phys_sugg for the pseudo instead of tying them.
1557 Return "failure" so that the lifespan of UREG is terminated here;
1558 that way the two lifespans will be disjoint and nothing will prevent
1559 the pseudo reg from being given this hard reg. */
1561 if (ureg
< FIRST_PSEUDO_REGISTER
)
1563 /* Allocate a quantity number so we have a place to put our
1565 if (reg_qty
[sreg
] == -2)
1566 reg_is_born (setreg
, 2 * insn_number
);
1568 if (reg_qty
[sreg
] >= 0)
1572 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1573 qty_phys_has_copy_sugg
[reg_qty
[sreg
]] = 1;
1577 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1578 qty_phys_has_sugg
[reg_qty
[sreg
]] = 1;
1584 /* Similarly for SREG a hard register and UREG a pseudo register. */
1586 if (sreg
< FIRST_PSEUDO_REGISTER
)
1590 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1591 qty_phys_has_copy_sugg
[reg_qty
[ureg
]] = 1;
1595 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1596 qty_phys_has_sugg
[reg_qty
[ureg
]] = 1;
1601 /* At this point we know that SREG and UREG are both pseudos.
1602 Do nothing if SREG already has a quantity or is a register that we
1604 if (reg_qty
[sreg
] >= -1
1605 /* If we are not going to let any regs live across calls,
1606 don't tie a call-crossing reg to a non-call-crossing reg. */
1607 || (current_function_has_nonlocal_label
1608 && ((reg_n_calls_crossed
[ureg
] > 0)
1609 != (reg_n_calls_crossed
[sreg
] > 0))))
1612 /* We don't already know about SREG, so tie it to UREG
1613 if this is the last use of UREG, provided the classes they want
1616 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1617 && reg_meets_class_p (sreg
, qty_min_class
[reg_qty
[ureg
]]))
1619 /* Add SREG to UREG's quantity. */
1620 sqty
= reg_qty
[ureg
];
1621 reg_qty
[sreg
] = sqty
;
1622 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1623 reg_next_in_qty
[sreg
] = qty_first_reg
[sqty
];
1624 qty_first_reg
[sqty
] = sreg
;
1626 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1627 update_qty_class (sqty
, sreg
);
1629 /* Update info about quantity SQTY. */
1630 qty_n_calls_crossed
[sqty
] += reg_n_calls_crossed
[sreg
];
1631 qty_n_refs
[sqty
] += reg_n_refs
[sreg
];
1636 for (i
= qty_first_reg
[sqty
]; i
>= 0; i
= reg_next_in_qty
[i
])
1637 reg_offset
[i
] -= offset
;
1639 qty_size
[sqty
] = ssize
;
1640 qty_mode
[sqty
] = GET_MODE (setreg
);
1649 /* Return 1 if the preferred class of REG allows it to be tied
1650 to a quantity or register whose class is CLASS.
1651 True if REG's reg class either contains or is contained in CLASS. */
1654 reg_meets_class_p (reg
, class)
1656 enum reg_class
class;
1658 register enum reg_class rclass
= reg_preferred_class (reg
);
1659 return (reg_class_subset_p (rclass
, class)
1660 || reg_class_subset_p (class, rclass
));
1663 /* Return 1 if the two specified classes have registers in common.
1664 If CALL_SAVED, then consider only call-saved registers. */
1667 reg_classes_overlap_p (c1
, c2
, call_saved
)
1668 register enum reg_class c1
;
1669 register enum reg_class c2
;
1675 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
1676 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
1678 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1679 if (TEST_HARD_REG_BIT (c
, i
)
1680 && (! call_saved
|| ! call_used_regs
[i
]))
1686 /* Update the class of QTY assuming that REG is being tied to it. */
1689 update_qty_class (qty
, reg
)
1693 enum reg_class rclass
= reg_preferred_class (reg
);
1694 if (reg_class_subset_p (rclass
, qty_min_class
[qty
]))
1695 qty_min_class
[qty
] = rclass
;
1697 rclass
= reg_alternate_class (reg
);
1698 if (reg_class_subset_p (rclass
, qty_alternate_class
[qty
]))
1699 qty_alternate_class
[qty
] = rclass
;
1702 /* Handle something which alters the value of an rtx REG.
1704 REG is whatever is set or clobbered. SETTER is the rtx that
1705 is modifying the register.
1707 If it is not really a register, we do nothing.
1708 The file-global variables `this_insn' and `this_insn_number'
1709 carry info from `block_alloc'. */
1712 reg_is_set (reg
, setter
)
1716 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1717 a hard register. These may actually not exist any more. */
1719 if (GET_CODE (reg
) != SUBREG
1720 && GET_CODE (reg
) != REG
)
1723 /* Mark this register as being born. If it is used in a CLOBBER, mark
1724 it as being born halfway between the previous insn and this insn so that
1725 it conflicts with our inputs but not the outputs of the previous insn. */
1727 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
1730 /* Handle beginning of the life of register REG.
1731 BIRTH is the index at which this is happening. */
1734 reg_is_born (reg
, birth
)
1740 if (GET_CODE (reg
) == SUBREG
)
1741 regno
= REGNO (SUBREG_REG (reg
)) + SUBREG_WORD (reg
);
1743 regno
= REGNO (reg
);
1745 if (regno
< FIRST_PSEUDO_REGISTER
)
1747 mark_life (regno
, GET_MODE (reg
), 1);
1749 /* If the register was to have been born earlier that the present
1750 insn, mark it as live where it is actually born. */
1751 if (birth
< 2 * this_insn_number
)
1752 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
1756 if (reg_qty
[regno
] == -2)
1757 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
1759 /* If this register has a quantity number, show that it isn't dead. */
1760 if (reg_qty
[regno
] >= 0)
1761 qty_death
[reg_qty
[regno
]] = -1;
1765 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1766 REG is an output that is dying (i.e., it is never used), otherwise it
1767 is an input (the normal case).
1768 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1771 wipe_dead_reg (reg
, output_p
)
1775 register int regno
= REGNO (reg
);
1777 /* If this insn has multiple results,
1778 and the dead reg is used in one of the results,
1779 extend its life to after this insn,
1780 so it won't get allocated together with any other result of this insn. */
1781 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
1782 && !single_set (this_insn
))
1785 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
1787 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
1788 if (GET_CODE (set
) == SET
1789 && GET_CODE (SET_DEST (set
)) != REG
1790 && !rtx_equal_p (reg
, SET_DEST (set
))
1791 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1796 if (regno
< FIRST_PSEUDO_REGISTER
)
1798 mark_life (regno
, GET_MODE (reg
), 0);
1800 /* If a hard register is dying as an output, mark it as in use at
1801 the beginning of this insn (the above statement would cause this
1804 post_mark_life (regno
, GET_MODE (reg
), 1,
1805 2 * this_insn_number
, 2 * this_insn_number
+ 1);
1808 else if (reg_qty
[regno
] >= 0)
1809 qty_death
[reg_qty
[regno
]] = 2 * this_insn_number
+ output_p
;
1812 /* Find a block of SIZE words of hard regs in reg_class CLASS
1813 that can hold something of machine-mode MODE
1814 (but actually we test only the first of the block for holding MODE)
1815 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1816 and return the number of the first of them.
1817 Return -1 if such a block cannot be found.
1818 If QTY crosses calls, insist on a register preserved by calls,
1819 unless ACCEPT_CALL_CLOBBERED is nonzero.
1821 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1822 register is available. If not, return -1. */
1825 find_free_reg (class, mode
, qty
, accept_call_clobbered
, just_try_suggested
,
1826 born_index
, dead_index
)
1827 enum reg_class
class;
1828 enum machine_mode mode
;
1829 int accept_call_clobbered
;
1830 int just_try_suggested
;
1832 int born_index
, dead_index
;
1834 register int i
, ins
;
1836 register /* Declare it register if it's a scalar. */
1838 HARD_REG_SET used
, first_used
;
1839 #ifdef ELIMINABLE_REGS
1840 static struct {int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
1843 /* Validate our parameters. */
1844 if (born_index
< 0 || born_index
> dead_index
)
1847 /* Don't let a pseudo live in a reg across a function call
1848 if we might get a nonlocal goto. */
1849 if (current_function_has_nonlocal_label
1850 && qty_n_calls_crossed
[qty
] > 0)
1853 if (accept_call_clobbered
)
1854 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
1855 else if (qty_n_calls_crossed
[qty
] == 0)
1856 COPY_HARD_REG_SET (used
, fixed_reg_set
);
1858 COPY_HARD_REG_SET (used
, call_used_reg_set
);
1860 for (ins
= born_index
; ins
< dead_index
; ins
++)
1861 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
1863 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
1865 /* Don't use the frame pointer reg in local-alloc even if
1866 we may omit the frame pointer, because if we do that and then we
1867 need a frame pointer, reload won't know how to move the pseudo
1868 to another hard reg. It can move only regs made by global-alloc.
1870 This is true of any register that can be eliminated. */
1871 #ifdef ELIMINABLE_REGS
1872 for (i
= 0; i
< sizeof eliminables
/ sizeof eliminables
[0]; i
++)
1873 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
1875 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
1878 /* Normally, the registers that can be used for the first register in
1879 a multi-register quantity are the same as those that can be used for
1880 subsequent registers. However, if just trying suggested registers,
1881 restrict our consideration to them. If there are copy-suggested
1882 register, try them. Otherwise, try the arithmetic-suggested
1884 COPY_HARD_REG_SET (first_used
, used
);
1886 if (just_try_suggested
)
1888 if (qty_phys_has_copy_sugg
[qty
])
1889 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qty
]);
1891 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qty
]);
1894 /* If all registers are excluded, we can't do anything. */
1895 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
1897 /* If at least one would be suitable, test each hard reg. */
1899 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1901 #ifdef REG_ALLOC_ORDER
1902 int regno
= reg_alloc_order
[i
];
1906 if (! TEST_HARD_REG_BIT (first_used
, regno
)
1907 && HARD_REGNO_MODE_OK (regno
, mode
))
1910 register int size1
= HARD_REGNO_NREGS (regno
, mode
);
1911 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
1914 /* Mark that this register is in use between its birth and death
1916 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
1919 #ifndef REG_ALLOC_ORDER
1920 i
+= j
; /* Skip starting points we know will lose */
1927 /* If we are just trying suggested register, we have just tried copy-
1928 suggested registers, and there are arithmetic-suggested registers,
1931 /* If it would be profitable to allocate a call-clobbered register
1932 and save and restore it around calls, do that. */
1933 if (just_try_suggested
&& qty_phys_has_copy_sugg
[qty
]
1934 && qty_phys_has_sugg
[qty
])
1936 /* Don't try the copy-suggested regs again. */
1937 qty_phys_has_copy_sugg
[qty
] = 0;
1938 return find_free_reg (class, mode
, qty
, accept_call_clobbered
, 1,
1939 born_index
, dead_index
);
1942 if (! accept_call_clobbered
1943 && flag_caller_saves
1944 && ! just_try_suggested
1945 && qty_n_calls_crossed
[qty
] != 0
1946 && CALLER_SAVE_PROFITABLE (qty_n_refs
[qty
], qty_n_calls_crossed
[qty
]))
1948 i
= find_free_reg (class, mode
, qty
, 1, 0, born_index
, dead_index
);
1950 caller_save_needed
= 1;
1956 /* Mark that REGNO with machine-mode MODE is live starting from the current
1957 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
1961 mark_life (regno
, mode
, life
)
1963 enum machine_mode mode
;
1966 register int j
= HARD_REGNO_NREGS (regno
, mode
);
1969 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
1972 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
1975 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
1976 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
1977 to insn number DEATH (exclusive). */
1980 post_mark_life (regno
, mode
, life
, birth
, death
)
1981 register int regno
, life
, birth
;
1982 enum machine_mode mode
;
1985 register int j
= HARD_REGNO_NREGS (regno
, mode
);
1987 register /* Declare it register if it's a scalar. */
1989 HARD_REG_SET this_reg
;
1991 CLEAR_HARD_REG_SET (this_reg
);
1993 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
1996 while (birth
< death
)
1998 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2002 while (birth
< death
)
2004 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2009 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2010 is the register being clobbered, and R1 is a register being used in
2011 the equivalent expression.
2013 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2014 in which it is used, return 1.
2016 Otherwise, return 0. */
2019 no_conflict_p (insn
, r0
, r1
)
2023 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2026 /* If R1 is a hard register, return 0 since we handle this case
2027 when we scan the insns that actually use it. */
2030 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2031 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2032 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2035 last
= XEXP (note
, 0);
2037 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2038 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
2040 if (find_reg_note (p
, REG_DEAD
, r1
))
2043 if (reg_mentioned_p (r1
, PATTERN (p
))
2044 && ! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2051 #ifdef REGISTER_CONSTRAINTS
2053 /* Return 1 if the constraint string P indicates that the a the operand
2054 must be equal to operand 0 and that no register is acceptable. */
2057 requires_inout_p (p
)
2070 case '=': case '+': case '?':
2071 case '#': case '&': case '!':
2072 case '*': case '%': case ',':
2073 case '1': case '2': case '3': case '4':
2074 case 'm': case '<': case '>': case 'V': case 'o':
2075 case 'E': case 'F': case 'G': case 'H':
2076 case 's': case 'i': case 'n':
2077 case 'I': case 'J': case 'K': case 'L':
2078 case 'M': case 'N': case 'O': case 'P':
2079 #ifdef EXTRA_CONSTRAINT
2080 case 'Q': case 'R': case 'S': case 'T': case 'U':
2083 /* These don't say anything we care about. */
2089 /* These mean a register is allowed. Fail if so. */
2095 #endif /* REGISTER_CONSTRAINTS */
2098 dump_local_alloc (file
)
2102 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2103 if (reg_renumber
[i
] != -1)
2104 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);