1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
64 #include "coretypes.h"
66 #include "hard-reg-set.h"
70 #include "basic-block.h"
73 #include "insn-config.h"
74 #include "insn-attr.h"
79 #include "integrate.h"
81 /* Next quantity number available for allocation. */
85 /* Information we maintain about each quantity. */
88 /* The number of refs to quantity Q. */
92 /* The frequency of uses of quantity Q. */
96 /* Insn number (counting from head of basic block)
97 where quantity Q was born. -1 if birth has not been recorded. */
101 /* Insn number (counting from head of basic block)
102 where given quantity died. Due to the way tying is done,
103 and the fact that we consider in this pass only regs that die but once,
104 a quantity can die only once. Each quantity's life span
105 is a set of consecutive insns. -1 if death has not been recorded. */
109 /* Number of words needed to hold the data in given quantity.
110 This depends on its machine mode. It is used for these purposes:
111 1. It is used in computing the relative importances of qtys,
112 which determines the order in which we look for regs for them.
113 2. It is used in rules that prevent tying several registers of
114 different sizes in a way that is geometrically impossible
115 (see combine_regs). */
119 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
123 /* The register number of one pseudo register whose reg_qty value is Q.
124 This register should be the head of the chain
125 maintained in reg_next_in_qty. */
129 /* Reg class contained in (smaller than) the preferred classes of all
130 the pseudo regs that are tied in given quantity.
131 This is the preferred class for allocating that quantity. */
133 enum reg_class min_class
;
135 /* Register class within which we allocate given qty if we can't get
136 its preferred class. */
138 enum reg_class alternate_class
;
140 /* This holds the mode of the registers that are tied to given qty,
141 or VOIDmode if registers with differing modes are tied together. */
143 enum machine_mode mode
;
145 /* the hard reg number chosen for given quantity,
146 or -1 if none was found. */
151 static struct qty
*qty
;
153 /* These fields are kept separately to speedup their clearing. */
155 /* We maintain two hard register sets that indicate suggested hard registers
156 for each quantity. The first, phys_copy_sugg, contains hard registers
157 that are tied to the quantity by a simple copy. The second contains all
158 hard registers that are tied to the quantity via an arithmetic operation.
160 The former register set is given priority for allocation. This tends to
161 eliminate copy insns. */
163 /* Element Q is a set of hard registers that are suggested for quantity Q by
166 static HARD_REG_SET
*qty_phys_copy_sugg
;
168 /* Element Q is a set of hard registers that are suggested for quantity Q by
171 static HARD_REG_SET
*qty_phys_sugg
;
173 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
175 static short *qty_phys_num_copy_sugg
;
177 /* Element Q is the number of suggested registers in qty_phys_sugg. */
179 static short *qty_phys_num_sugg
;
181 /* If (REG N) has been assigned a quantity number, is a register number
182 of another register assigned the same quantity number, or -1 for the
183 end of the chain. qty->first_reg point to the head of this chain. */
185 static int *reg_next_in_qty
;
187 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
189 of -1 if this register cannot be allocated by local-alloc,
190 or -2 if not known yet.
192 Note that if we see a use or death of pseudo register N with
193 reg_qty[N] == -2, register N must be local to the current block. If
194 it were used in more than one block, we would have reg_qty[N] == -1.
195 This relies on the fact that if reg_basic_block[N] is >= 0, register N
196 will not appear in any other block. We save a considerable number of
197 tests by exploiting this.
199 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
204 /* The offset (in words) of register N within its quantity.
205 This can be nonzero if register N is SImode, and has been tied
206 to a subreg of a DImode register. */
208 static char *reg_offset
;
210 /* Vector of substitutions of register numbers,
211 used to map pseudo regs into hardware regs.
212 This is set up as a result of register allocation.
213 Element N is the hard reg assigned to pseudo reg N,
214 or is -1 if no hard reg was assigned.
215 If N is a hard reg number, element N is N. */
219 /* Set of hard registers live at the current point in the scan
220 of the instructions in a basic block. */
222 static HARD_REG_SET regs_live
;
224 /* Each set of hard registers indicates registers live at a particular
225 point in the basic block. For N even, regs_live_at[N] says which
226 hard registers are needed *after* insn N/2 (i.e., they may not
227 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
229 If an object is to conflict with the inputs of insn J but not the
230 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
231 if it is to conflict with the outputs of insn J but not the inputs of
232 insn J + 1, it is said to die at index J*2 + 1. */
234 static HARD_REG_SET
*regs_live_at
;
236 /* Communicate local vars `insn_number' and `insn'
237 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
238 static int this_insn_number
;
239 static rtx this_insn
;
243 /* Set when an attempt should be made to replace a register
244 with the associated src_p entry. */
248 /* Set when a REG_EQUIV note is found or created. Use to
249 keep track of what memory accesses might be created later,
256 /* Loop depth is used to recognize equivalences which appear
257 to be present within the same loop (or in an inner loop). */
261 /* The list of each instruction which initializes this register. */
266 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
267 structure for that register. */
269 static struct equivalence
*reg_equiv
;
271 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
272 static int recorded_label_ref
;
274 static void alloc_qty (int, enum machine_mode
, int, int);
275 static void validate_equiv_mem_from_store (rtx
, rtx
, void *);
276 static int validate_equiv_mem (rtx
, rtx
, rtx
);
277 static int equiv_init_varies_p (rtx
);
278 static int equiv_init_movable_p (rtx
, int);
279 static int contains_replace_regs (rtx
);
280 static int memref_referenced_p (rtx
, rtx
);
281 static int memref_used_between_p (rtx
, rtx
, rtx
);
282 static void update_equiv_regs (void);
283 static void no_equiv (rtx
, rtx
, void *);
284 static void block_alloc (int);
285 static int qty_sugg_compare (int, int);
286 static int qty_sugg_compare_1 (const void *, const void *);
287 static int qty_compare (int, int);
288 static int qty_compare_1 (const void *, const void *);
289 static int combine_regs (rtx
, rtx
, int, int, rtx
, int);
290 static int reg_meets_class_p (int, enum reg_class
);
291 static void update_qty_class (int, int);
292 static void reg_is_set (rtx
, rtx
, void *);
293 static void reg_is_born (rtx
, int);
294 static void wipe_dead_reg (rtx
, int);
295 static int find_free_reg (enum reg_class
, enum machine_mode
, int, int, int,
297 static void mark_life (int, enum machine_mode
, int);
298 static void post_mark_life (int, enum machine_mode
, int, int, int);
299 static int no_conflict_p (rtx
, rtx
, rtx
);
300 static int requires_inout (const char *);
302 /* Allocate a new quantity (new within current basic block)
303 for register number REGNO which is born at index BIRTH
304 within the block. MODE and SIZE are info on reg REGNO. */
307 alloc_qty (int regno
, enum machine_mode mode
, int size
, int birth
)
309 int qtyno
= next_qty
++;
311 reg_qty
[regno
] = qtyno
;
312 reg_offset
[regno
] = 0;
313 reg_next_in_qty
[regno
] = -1;
315 qty
[qtyno
].first_reg
= regno
;
316 qty
[qtyno
].size
= size
;
317 qty
[qtyno
].mode
= mode
;
318 qty
[qtyno
].birth
= birth
;
319 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
320 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
321 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
322 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
323 qty
[qtyno
].freq
= REG_FREQ (regno
);
326 /* Main entry point of this file. */
335 /* We need to keep track of whether or not we recorded a LABEL_REF so
336 that we know if the jump optimizer needs to be rerun. */
337 recorded_label_ref
= 0;
339 /* Leaf functions and non-leaf functions have different needs.
340 If defined, let the machine say what kind of ordering we
342 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
343 ORDER_REGS_FOR_LOCAL_ALLOC
;
346 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
349 update_equiv_regs ();
351 /* This sets the maximum number of quantities we can have. Quantity
352 numbers start at zero and we can have one for each pseudo. */
353 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
355 /* Allocate vectors of temporary data.
356 See the declarations of these variables, above,
357 for what they mean. */
359 qty
= xmalloc (max_qty
* sizeof (struct qty
));
360 qty_phys_copy_sugg
= xmalloc (max_qty
* sizeof (HARD_REG_SET
));
361 qty_phys_num_copy_sugg
= xmalloc (max_qty
* sizeof (short));
362 qty_phys_sugg
= xmalloc (max_qty
* sizeof (HARD_REG_SET
));
363 qty_phys_num_sugg
= xmalloc (max_qty
* sizeof (short));
365 reg_qty
= xmalloc (max_regno
* sizeof (int));
366 reg_offset
= xmalloc (max_regno
* sizeof (char));
367 reg_next_in_qty
= xmalloc (max_regno
* sizeof (int));
369 /* Determine which pseudo-registers can be allocated by local-alloc.
370 In general, these are the registers used only in a single block and
373 We need not be concerned with which block actually uses the register
374 since we will never see it outside that block. */
376 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
378 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1)
384 /* Force loop below to initialize entire quantity array. */
387 /* Allocate each block's local registers, block by block. */
391 /* NEXT_QTY indicates which elements of the `qty_...'
392 vectors might need to be initialized because they were used
393 for the previous block; it is set to the entire array before
394 block 0. Initialize those, with explicit loop if there are few,
395 else with bzero and bcopy. Do not initialize vectors that are
396 explicit set by `alloc_qty'. */
400 for (i
= 0; i
< next_qty
; i
++)
402 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
403 qty_phys_num_copy_sugg
[i
] = 0;
404 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
405 qty_phys_num_sugg
[i
] = 0;
410 #define CLEAR(vector) \
411 memset ((vector), 0, (sizeof (*(vector))) * next_qty);
413 CLEAR (qty_phys_copy_sugg
);
414 CLEAR (qty_phys_num_copy_sugg
);
415 CLEAR (qty_phys_sugg
);
416 CLEAR (qty_phys_num_sugg
);
421 block_alloc (b
->index
);
425 free (qty_phys_copy_sugg
);
426 free (qty_phys_num_copy_sugg
);
427 free (qty_phys_sugg
);
428 free (qty_phys_num_sugg
);
432 free (reg_next_in_qty
);
434 return recorded_label_ref
;
437 /* Used for communication between the following two functions: contains
438 a MEM that we wish to ensure remains unchanged. */
439 static rtx equiv_mem
;
441 /* Set nonzero if EQUIV_MEM is modified. */
442 static int equiv_mem_modified
;
444 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
445 Called via note_stores. */
448 validate_equiv_mem_from_store (rtx dest
, rtx set ATTRIBUTE_UNUSED
,
449 void *data ATTRIBUTE_UNUSED
)
451 if ((GET_CODE (dest
) == REG
452 && reg_overlap_mentioned_p (dest
, equiv_mem
))
453 || (GET_CODE (dest
) == MEM
454 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
455 equiv_mem_modified
= 1;
458 /* Verify that no store between START and the death of REG invalidates
459 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
460 by storing into an overlapping memory location, or with a non-const
463 Return 1 if MEMREF remains valid. */
466 validate_equiv_mem (rtx start
, rtx reg
, rtx memref
)
472 equiv_mem_modified
= 0;
474 /* If the memory reference has side effects or is volatile, it isn't a
475 valid equivalence. */
476 if (side_effects_p (memref
))
479 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
484 if (find_reg_note (insn
, REG_DEAD
, reg
))
487 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
488 && ! CONST_OR_PURE_CALL_P (insn
))
491 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
493 /* If a register mentioned in MEMREF is modified via an
494 auto-increment, we lose the equivalence. Do the same if one
495 dies; although we could extend the life, it doesn't seem worth
498 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
499 if ((REG_NOTE_KIND (note
) == REG_INC
500 || REG_NOTE_KIND (note
) == REG_DEAD
)
501 && GET_CODE (XEXP (note
, 0)) == REG
502 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
509 /* Returns zero if X is known to be invariant. */
512 equiv_init_varies_p (rtx x
)
514 RTX_CODE code
= GET_CODE (x
);
521 return ! RTX_UNCHANGING_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
535 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
538 if (MEM_VOLATILE_P (x
))
547 fmt
= GET_RTX_FORMAT (code
);
548 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
551 if (equiv_init_varies_p (XEXP (x
, i
)))
554 else if (fmt
[i
] == 'E')
557 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
558 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
565 /* Returns nonzero if X (used to initialize register REGNO) is movable.
566 X is only movable if the registers it uses have equivalent initializations
567 which appear to be within the same loop (or in an inner loop) and movable
568 or if they are not candidates for local_alloc and don't vary. */
571 equiv_init_movable_p (rtx x
, int regno
)
575 enum rtx_code code
= GET_CODE (x
);
580 return equiv_init_movable_p (SET_SRC (x
), regno
);
595 return (reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
596 && reg_equiv
[REGNO (x
)].replace
)
597 || (REG_BASIC_BLOCK (REGNO (x
)) < 0 && ! rtx_varies_p (x
, 0));
599 case UNSPEC_VOLATILE
:
603 if (MEM_VOLATILE_P (x
))
612 fmt
= GET_RTX_FORMAT (code
);
613 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
617 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
621 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
622 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
630 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
633 contains_replace_regs (rtx x
)
637 enum rtx_code code
= GET_CODE (x
);
653 return reg_equiv
[REGNO (x
)].replace
;
659 fmt
= GET_RTX_FORMAT (code
);
660 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
664 if (contains_replace_regs (XEXP (x
, i
)))
668 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
669 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
677 /* TRUE if X references a memory location that would be affected by a store
681 memref_referenced_p (rtx memref
, rtx x
)
685 enum rtx_code code
= GET_CODE (x
);
702 return (reg_equiv
[REGNO (x
)].replacement
703 && memref_referenced_p (memref
,
704 reg_equiv
[REGNO (x
)].replacement
));
707 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
712 /* If we are setting a MEM, it doesn't count (its address does), but any
713 other SET_DEST that has a MEM in it is referencing the MEM. */
714 if (GET_CODE (SET_DEST (x
)) == MEM
)
716 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
719 else if (memref_referenced_p (memref
, SET_DEST (x
)))
722 return memref_referenced_p (memref
, SET_SRC (x
));
728 fmt
= GET_RTX_FORMAT (code
);
729 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
733 if (memref_referenced_p (memref
, XEXP (x
, i
)))
737 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
738 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
746 /* TRUE if some insn in the range (START, END] references a memory location
747 that would be affected by a store to MEMREF. */
750 memref_used_between_p (rtx memref
, rtx start
, rtx end
)
754 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
755 insn
= NEXT_INSN (insn
))
756 if (INSN_P (insn
) && memref_referenced_p (memref
, PATTERN (insn
)))
762 /* Return nonzero if the rtx X is invariant over the current function. */
763 /* ??? Actually, the places this is used in reload expect exactly what
764 is tested here, and not everything that is function invariant. In
765 particular, the frame pointer and arg pointer are special cased;
766 pic_offset_table_rtx is not, and this will cause aborts when we
767 go to spill these things to memory. */
770 function_invariant_p (rtx x
)
774 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
776 if (GET_CODE (x
) == PLUS
777 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
778 && CONSTANT_P (XEXP (x
, 1)))
783 /* Find registers that are equivalent to a single value throughout the
784 compilation (either because they can be referenced in memory or are set once
785 from a single constant). Lower their priority for a register.
787 If such a register is only referenced once, try substituting its value
788 into the using insn. If it succeeds, we can eliminate the register
792 update_equiv_regs (void)
797 regset_head cleared_regs
;
798 int clear_regnos
= 0;
800 reg_equiv
= xcalloc (max_regno
, sizeof *reg_equiv
);
801 INIT_REG_SET (&cleared_regs
);
803 init_alias_analysis ();
805 /* Scan the insns and find which registers have equivalences. Do this
806 in a separate scan of the insns because (due to -fcse-follow-jumps)
807 a register can be set below its use. */
810 loop_depth
= bb
->loop_depth
;
812 for (insn
= BB_HEAD (bb
);
813 insn
!= NEXT_INSN (BB_END (bb
));
814 insn
= NEXT_INSN (insn
))
824 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
825 if (REG_NOTE_KIND (note
) == REG_INC
)
826 no_equiv (XEXP (note
, 0), note
, NULL
);
828 set
= single_set (insn
);
830 /* If this insn contains more (or less) than a single SET,
831 only mark all destinations as having no known equivalence. */
834 note_stores (PATTERN (insn
), no_equiv
, NULL
);
837 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
841 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
843 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
845 note_stores (part
, no_equiv
, NULL
);
849 dest
= SET_DEST (set
);
852 /* If this sets a MEM to the contents of a REG that is only used
853 in a single basic block, see if the register is always equivalent
854 to that memory location and if moving the store from INSN to the
855 insn that set REG is safe. If so, put a REG_EQUIV note on the
858 Don't add a REG_EQUIV note if the insn already has one. The existing
859 REG_EQUIV is likely more useful than the one we are adding.
861 If one of the regs in the address has reg_equiv[REGNO].replace set,
862 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
863 optimization may move the set of this register immediately before
864 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
865 the mention in the REG_EQUIV note would be to an uninitialized
867 /* ????? This test isn't good enough; we might see a MEM with a use of
868 a pseudo register before we see its setting insn that will cause
869 reg_equiv[].replace for that pseudo to be set.
870 Equivalences to MEMs should be made in another pass, after the
871 reg_equiv[].replace information has been gathered. */
873 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
874 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
875 && REG_BASIC_BLOCK (regno
) >= 0
876 && REG_N_SETS (regno
) == 1
877 && reg_equiv
[regno
].init_insns
!= 0
878 && reg_equiv
[regno
].init_insns
!= const0_rtx
879 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
881 && ! contains_replace_regs (XEXP (dest
, 0)))
883 rtx init_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
884 if (validate_equiv_mem (init_insn
, src
, dest
)
885 && ! memref_used_between_p (dest
, init_insn
, insn
))
886 REG_NOTES (init_insn
)
887 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
890 /* We only handle the case of a pseudo register being set
891 once, or always to the same value. */
892 /* ??? The mn10200 port breaks if we add equivalences for
893 values that need an ADDRESS_REGS register and set them equivalent
894 to a MEM of a pseudo. The actual problem is in the over-conservative
895 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
896 calculate_needs, but we traditionally work around this problem
897 here by rejecting equivalences when the destination is in a register
898 that's likely spilled. This is fragile, of course, since the
899 preferred class of a pseudo depends on all instructions that set
902 if (GET_CODE (dest
) != REG
903 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
904 || reg_equiv
[regno
].init_insns
== const0_rtx
905 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
906 && GET_CODE (src
) == MEM
))
908 /* This might be setting a SUBREG of a pseudo, a pseudo that is
909 also set somewhere else to a constant. */
910 note_stores (set
, no_equiv
, NULL
);
914 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
916 /* cse sometimes generates function invariants, but doesn't put a
917 REG_EQUAL note on the insn. Since this note would be redundant,
918 there's no point creating it earlier than here. */
919 if (! note
&& ! rtx_varies_p (src
, 0))
920 note
= set_unique_reg_note (insn
, REG_EQUAL
, src
);
922 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
923 since it represents a function call */
924 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
927 if (REG_N_SETS (regno
) != 1
929 || rtx_varies_p (XEXP (note
, 0), 0)
930 || (reg_equiv
[regno
].replacement
931 && ! rtx_equal_p (XEXP (note
, 0),
932 reg_equiv
[regno
].replacement
))))
934 no_equiv (dest
, set
, NULL
);
937 /* Record this insn as initializing this register. */
938 reg_equiv
[regno
].init_insns
939 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
941 /* If this register is known to be equal to a constant, record that
942 it is always equivalent to the constant. */
943 if (note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
944 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
946 /* If this insn introduces a "constant" register, decrease the priority
947 of that register. Record this insn if the register is only used once
948 more and the equivalence value is the same as our source.
950 The latter condition is checked for two reasons: First, it is an
951 indication that it may be more efficient to actually emit the insn
952 as written (if no registers are available, reload will substitute
953 the equivalence). Secondly, it avoids problems with any registers
954 dying in this insn whose death notes would be missed.
956 If we don't have a REG_EQUIV note, see if this insn is loading
957 a register used only in one basic block from a MEM. If so, and the
958 MEM remains unchanged for the life of the register, add a REG_EQUIV
961 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
963 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
964 && GET_CODE (SET_SRC (set
)) == MEM
965 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
966 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
971 int regno
= REGNO (dest
);
973 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
974 We might end up substituting the LABEL_REF for uses of the
975 pseudo here or later. That kind of transformation may turn an
976 indirect jump into a direct jump, in which case we must rerun the
977 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
978 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
979 || (GET_CODE (XEXP (note
, 0)) == CONST
980 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
981 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
983 recorded_label_ref
= 1;
985 reg_equiv
[regno
].replacement
= XEXP (note
, 0);
986 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
987 reg_equiv
[regno
].loop_depth
= loop_depth
;
989 /* Don't mess with things live during setjmp. */
990 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
992 /* Note that the statement below does not affect the priority
994 REG_LIVE_LENGTH (regno
) *= 2;
997 /* If the register is referenced exactly twice, meaning it is
998 set once and used once, indicate that the reference may be
999 replaced by the equivalence we computed above. Do this
1000 even if the register is only used in one block so that
1001 dependencies can be handled where the last register is
1002 used in a different block (i.e. HIGH / LO_SUM sequences)
1003 and to reduce the number of registers alive across
1006 if (REG_N_REFS (regno
) == 2
1007 && (rtx_equal_p (XEXP (note
, 0), src
)
1008 || ! equiv_init_varies_p (src
))
1009 && GET_CODE (insn
) == INSN
1010 && equiv_init_movable_p (PATTERN (insn
), regno
))
1011 reg_equiv
[regno
].replace
= 1;
1017 /* Now scan all regs killed in an insn to see if any of them are
1018 registers only used that once. If so, see if we can replace the
1019 reference with the equivalent from. If we can, delete the
1020 initializing reference and this register will go away. If we
1021 can't replace the reference, and the initializing reference is
1022 within the same loop (or in an inner loop), then move the register
1023 initialization just before the use, so that they are in the same
1025 FOR_EACH_BB_REVERSE (bb
)
1027 loop_depth
= bb
->loop_depth
;
1028 for (insn
= BB_END (bb
);
1029 insn
!= PREV_INSN (BB_HEAD (bb
));
1030 insn
= PREV_INSN (insn
))
1034 if (! INSN_P (insn
))
1037 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1039 if (REG_NOTE_KIND (link
) == REG_DEAD
1040 /* Make sure this insn still refers to the register. */
1041 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
1043 int regno
= REGNO (XEXP (link
, 0));
1046 if (! reg_equiv
[regno
].replace
1047 || reg_equiv
[regno
].loop_depth
< loop_depth
)
1050 /* reg_equiv[REGNO].replace gets set only when
1051 REG_N_REFS[REGNO] is 2, i.e. the register is set
1052 once and used once. (If it were only set, but not used,
1053 flow would have deleted the setting insns.) Hence
1054 there can only be one insn in reg_equiv[REGNO].init_insns. */
1055 if (reg_equiv
[regno
].init_insns
== NULL_RTX
1056 || XEXP (reg_equiv
[regno
].init_insns
, 1) != NULL_RTX
)
1058 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
1060 /* We may not move instructions that can throw, since
1061 that changes basic block boundaries and we are not
1062 prepared to adjust the CFG to match. */
1063 if (can_throw_internal (equiv_insn
))
1066 if (asm_noperands (PATTERN (equiv_insn
)) < 0
1067 && validate_replace_rtx (regno_reg_rtx
[regno
],
1068 *(reg_equiv
[regno
].src_p
), insn
))
1074 /* Find the last note. */
1075 for (last_link
= link
; XEXP (last_link
, 1);
1076 last_link
= XEXP (last_link
, 1))
1079 /* Append the REG_DEAD notes from equiv_insn. */
1080 equiv_link
= REG_NOTES (equiv_insn
);
1084 equiv_link
= XEXP (equiv_link
, 1);
1085 if (REG_NOTE_KIND (note
) == REG_DEAD
)
1087 remove_note (equiv_insn
, note
);
1088 XEXP (last_link
, 1) = note
;
1089 XEXP (note
, 1) = NULL_RTX
;
1094 remove_death (regno
, insn
);
1095 REG_N_REFS (regno
) = 0;
1096 REG_FREQ (regno
) = 0;
1097 delete_insn (equiv_insn
);
1099 reg_equiv
[regno
].init_insns
1100 = XEXP (reg_equiv
[regno
].init_insns
, 1);
1102 /* Move the initialization of the register to just before
1103 INSN. Update the flow information. */
1104 else if (PREV_INSN (insn
) != equiv_insn
)
1108 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
1109 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
1110 REG_NOTES (equiv_insn
) = 0;
1112 /* Make sure this insn is recognized before reload begins,
1113 otherwise eliminate_regs_in_insn will abort. */
1114 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
1116 delete_insn (equiv_insn
);
1118 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
1120 REG_BASIC_BLOCK (regno
) = bb
->index
;
1121 REG_N_CALLS_CROSSED (regno
) = 0;
1122 REG_LIVE_LENGTH (regno
) = 2;
1124 if (insn
== BB_HEAD (bb
))
1125 BB_HEAD (bb
) = PREV_INSN (insn
);
1127 /* Remember to clear REGNO from all basic block's live
1129 SET_REGNO_REG_SET (&cleared_regs
, regno
);
1137 /* Clear all dead REGNOs from all basic block's live info. */
1141 if (clear_regnos
> 8)
1145 AND_COMPL_REG_SET (bb
->global_live_at_start
, &cleared_regs
);
1146 AND_COMPL_REG_SET (bb
->global_live_at_end
, &cleared_regs
);
1150 EXECUTE_IF_SET_IN_REG_SET (&cleared_regs
, 0, j
,
1154 CLEAR_REGNO_REG_SET (bb
->global_live_at_start
, j
);
1155 CLEAR_REGNO_REG_SET (bb
->global_live_at_end
, j
);
1161 end_alias_analysis ();
1162 CLEAR_REG_SET (&cleared_regs
);
1166 /* Mark REG as having no known equivalence.
1167 Some instructions might have been processed before and furnished
1168 with REG_EQUIV notes for this register; these notes will have to be
1170 STORE is the piece of RTL that does the non-constant / conflicting
1171 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1172 but needs to be there because this function is called from note_stores. */
1174 no_equiv (rtx reg
, rtx store ATTRIBUTE_UNUSED
, void *data ATTRIBUTE_UNUSED
)
1179 if (GET_CODE (reg
) != REG
)
1181 regno
= REGNO (reg
);
1182 list
= reg_equiv
[regno
].init_insns
;
1183 if (list
== const0_rtx
)
1185 for (; list
; list
= XEXP (list
, 1))
1187 rtx insn
= XEXP (list
, 0);
1188 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1190 reg_equiv
[regno
].init_insns
= const0_rtx
;
1191 reg_equiv
[regno
].replacement
= NULL_RTX
;
1194 /* Allocate hard regs to the pseudo regs used only within block number B.
1195 Only the pseudos that die but once can be handled. */
1203 int insn_number
= 0;
1205 int max_uid
= get_max_uid ();
1207 int no_conflict_combined_regno
= -1;
1209 /* Count the instructions in the basic block. */
1211 insn
= BB_END (BASIC_BLOCK (b
));
1214 if (GET_CODE (insn
) != NOTE
)
1215 if (++insn_count
> max_uid
)
1217 if (insn
== BB_HEAD (BASIC_BLOCK (b
)))
1219 insn
= PREV_INSN (insn
);
1222 /* +2 to leave room for a post_mark_life at the last insn and for
1223 the birth of a CLOBBER in the first insn. */
1224 regs_live_at
= xcalloc ((2 * insn_count
+ 2), sizeof (HARD_REG_SET
));
1226 /* Initialize table of hardware registers currently live. */
1228 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1230 /* This loop scans the instructions of the basic block
1231 and assigns quantities to registers.
1232 It computes which registers to tie. */
1234 insn
= BB_HEAD (BASIC_BLOCK (b
));
1237 if (GET_CODE (insn
) != NOTE
)
1244 rtx r0
, r1
= NULL_RTX
;
1245 int combined_regno
= -1;
1248 this_insn_number
= insn_number
;
1251 extract_insn (insn
);
1252 which_alternative
= -1;
1254 /* Is this insn suitable for tying two registers?
1255 If so, try doing that.
1256 Suitable insns are those with at least two operands and where
1257 operand 0 is an output that is a register that is not
1260 We can tie operand 0 with some operand that dies in this insn.
1261 First look for operands that are required to be in the same
1262 register as operand 0. If we find such, only try tying that
1263 operand or one that can be put into that operand if the
1264 operation is commutative. If we don't find an operand
1265 that is required to be in the same register as operand 0,
1266 we can tie with any operand.
1268 Subregs in place of regs are also ok.
1270 If tying is done, WIN is set nonzero. */
1273 && recog_data
.n_operands
> 1
1274 && recog_data
.constraints
[0][0] == '='
1275 && recog_data
.constraints
[0][1] != '&')
1277 /* If non-negative, is an operand that must match operand 0. */
1278 int must_match_0
= -1;
1279 /* Counts number of alternatives that require a match with
1281 int n_matching_alts
= 0;
1283 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1285 const char *p
= recog_data
.constraints
[i
];
1286 int this_match
= requires_inout (p
);
1288 n_matching_alts
+= this_match
;
1289 if (this_match
== recog_data
.n_alternatives
)
1293 r0
= recog_data
.operand
[0];
1294 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1296 /* Skip this operand if we found an operand that
1297 must match operand 0 and this operand isn't it
1298 and can't be made to be it by commutativity. */
1300 if (must_match_0
>= 0 && i
!= must_match_0
1301 && ! (i
== must_match_0
+ 1
1302 && recog_data
.constraints
[i
-1][0] == '%')
1303 && ! (i
== must_match_0
- 1
1304 && recog_data
.constraints
[i
][0] == '%'))
1307 /* Likewise if each alternative has some operand that
1308 must match operand zero. In that case, skip any
1309 operand that doesn't list operand 0 since we know that
1310 the operand always conflicts with operand 0. We
1311 ignore commutativity in this case to keep things simple. */
1312 if (n_matching_alts
== recog_data
.n_alternatives
1313 && 0 == requires_inout (recog_data
.constraints
[i
]))
1316 r1
= recog_data
.operand
[i
];
1318 /* If the operand is an address, find a register in it.
1319 There may be more than one register, but we only try one
1321 if (recog_data
.constraints
[i
][0] == 'p'
1322 || EXTRA_ADDRESS_CONSTRAINT (recog_data
.constraints
[i
][0],
1323 recog_data
.constraints
[i
]))
1324 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1327 /* Avoid making a call-saved register unnecessarily
1329 hard_reg
= get_hard_reg_initial_reg (cfun
, r1
);
1330 if (hard_reg
!= NULL_RTX
)
1332 if (GET_CODE (hard_reg
) == REG
1333 && IN_RANGE (REGNO (hard_reg
),
1334 0, FIRST_PSEUDO_REGISTER
- 1)
1335 && ! call_used_regs
[REGNO (hard_reg
)])
1339 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1341 /* We have two priorities for hard register preferences.
1342 If we have a move insn or an insn whose first input
1343 can only be in the same register as the output, give
1344 priority to an equivalence found from that insn. */
1346 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1348 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1349 win
= combine_regs (r1
, r0
, may_save_copy
,
1350 insn_number
, insn
, 0);
1357 /* Recognize an insn sequence with an ultimate result
1358 which can safely overlap one of the inputs.
1359 The sequence begins with a CLOBBER of its result,
1360 and ends with an insn that copies the result to itself
1361 and has a REG_EQUAL note for an equivalent formula.
1362 That note indicates what the inputs are.
1363 The result and the input can overlap if each insn in
1364 the sequence either doesn't mention the input
1365 or has a REG_NO_CONFLICT note to inhibit the conflict.
1367 We do the combining test at the CLOBBER so that the
1368 destination register won't have had a quantity number
1369 assigned, since that would prevent combining. */
1372 && GET_CODE (PATTERN (insn
)) == CLOBBER
1373 && (r0
= XEXP (PATTERN (insn
), 0),
1374 GET_CODE (r0
) == REG
)
1375 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1376 && XEXP (link
, 0) != 0
1377 && GET_CODE (XEXP (link
, 0)) == INSN
1378 && (set
= single_set (XEXP (link
, 0))) != 0
1379 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1380 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1383 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1384 /* Check that we have such a sequence. */
1385 && no_conflict_p (insn
, r0
, r1
))
1386 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1387 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1388 && (r1
= XEXP (XEXP (note
, 0), 0),
1389 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1390 && no_conflict_p (insn
, r0
, r1
))
1391 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1393 /* Here we care if the operation to be computed is
1395 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1396 || GET_CODE (XEXP (note
, 0)) == NE
1397 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1398 && (r1
= XEXP (XEXP (note
, 0), 1),
1399 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1400 && no_conflict_p (insn
, r0
, r1
))
1401 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1403 /* If we did combine something, show the register number
1404 in question so that we know to ignore its death. */
1406 no_conflict_combined_regno
= REGNO (r1
);
1409 /* If registers were just tied, set COMBINED_REGNO
1410 to the number of the register used in this insn
1411 that was tied to the register set in this insn.
1412 This register's qty should not be "killed". */
1416 while (GET_CODE (r1
) == SUBREG
)
1417 r1
= SUBREG_REG (r1
);
1418 combined_regno
= REGNO (r1
);
1421 /* Mark the death of everything that dies in this instruction,
1422 except for anything that was just combined. */
1424 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1425 if (REG_NOTE_KIND (link
) == REG_DEAD
1426 && GET_CODE (XEXP (link
, 0)) == REG
1427 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1428 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1429 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1431 wipe_dead_reg (XEXP (link
, 0), 0);
1433 /* Allocate qty numbers for all registers local to this block
1434 that are born (set) in this instruction.
1435 A pseudo that already has a qty is not changed. */
1437 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1439 /* If anything is set in this insn and then unused, mark it as dying
1440 after this insn, so it will conflict with our outputs. This
1441 can't match with something that combined, and it doesn't matter
1442 if it did. Do this after the calls to reg_is_set since these
1443 die after, not during, the current insn. */
1445 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1446 if (REG_NOTE_KIND (link
) == REG_UNUSED
1447 && GET_CODE (XEXP (link
, 0)) == REG
)
1448 wipe_dead_reg (XEXP (link
, 0), 1);
1450 /* If this is an insn that has a REG_RETVAL note pointing at a
1451 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1452 block, so clear any register number that combined within it. */
1453 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1454 && GET_CODE (XEXP (note
, 0)) == INSN
1455 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1456 no_conflict_combined_regno
= -1;
1459 /* Set the registers live after INSN_NUMBER. Note that we never
1460 record the registers live before the block's first insn, since no
1461 pseudos we care about are live before that insn. */
1463 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1464 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1466 if (insn
== BB_END (BASIC_BLOCK (b
)))
1469 insn
= NEXT_INSN (insn
);
1472 /* Now every register that is local to this basic block
1473 should have been given a quantity, or else -1 meaning ignore it.
1474 Every quantity should have a known birth and death.
1476 Order the qtys so we assign them registers in order of the
1477 number of suggested registers they need so we allocate those with
1478 the most restrictive needs first. */
1480 qty_order
= xmalloc (next_qty
* sizeof (int));
1481 for (i
= 0; i
< next_qty
; i
++)
1484 #define EXCHANGE(I1, I2) \
1485 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1490 /* Make qty_order[2] be the one to allocate last. */
1491 if (qty_sugg_compare (0, 1) > 0)
1493 if (qty_sugg_compare (1, 2) > 0)
1496 /* ... Fall through ... */
1498 /* Put the best one to allocate in qty_order[0]. */
1499 if (qty_sugg_compare (0, 1) > 0)
1502 /* ... Fall through ... */
1506 /* Nothing to do here. */
1510 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1513 /* Try to put each quantity in a suggested physical register, if it has one.
1514 This may cause registers to be allocated that otherwise wouldn't be, but
1515 this seems acceptable in local allocation (unlike global allocation). */
1516 for (i
= 0; i
< next_qty
; i
++)
1519 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1520 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1521 0, 1, qty
[q
].birth
, qty
[q
].death
);
1523 qty
[q
].phys_reg
= -1;
1526 /* Order the qtys so we assign them registers in order of
1527 decreasing length of life. Normally call qsort, but if we
1528 have only a very small number of quantities, sort them ourselves. */
1530 for (i
= 0; i
< next_qty
; i
++)
1533 #define EXCHANGE(I1, I2) \
1534 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1539 /* Make qty_order[2] be the one to allocate last. */
1540 if (qty_compare (0, 1) > 0)
1542 if (qty_compare (1, 2) > 0)
1545 /* ... Fall through ... */
1547 /* Put the best one to allocate in qty_order[0]. */
1548 if (qty_compare (0, 1) > 0)
1551 /* ... Fall through ... */
1555 /* Nothing to do here. */
1559 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1562 /* Now for each qty that is not a hardware register,
1563 look for a hardware register to put it in.
1564 First try the register class that is cheapest for this qty,
1565 if there is more than one class. */
1567 for (i
= 0; i
< next_qty
; i
++)
1570 if (qty
[q
].phys_reg
< 0)
1572 #ifdef INSN_SCHEDULING
1573 /* These values represent the adjusted lifetime of a qty so
1574 that it conflicts with qtys which appear near the start/end
1575 of this qty's lifetime.
1577 The purpose behind extending the lifetime of this qty is to
1578 discourage the register allocator from creating false
1581 The adjustment value is chosen to indicate that this qty
1582 conflicts with all the qtys in the instructions immediately
1583 before and after the lifetime of this qty.
1585 Experiments have shown that higher values tend to hurt
1586 overall code performance.
1588 If allocation using the extended lifetime fails we will try
1589 again with the qty's unadjusted lifetime. */
1590 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1591 int fake_death
= MIN (insn_number
* 2 + 1,
1592 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1595 if (N_REG_CLASSES
> 1)
1597 #ifdef INSN_SCHEDULING
1598 /* We try to avoid using hard registers allocated to qtys which
1599 are born immediately after this qty or die immediately before
1602 This optimization is only appropriate when we will run
1603 a scheduling pass after reload and we are not optimizing
1605 if (flag_schedule_insns_after_reload
1607 && !SMALL_REGISTER_CLASSES
)
1609 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1610 qty
[q
].mode
, q
, 0, 0,
1611 fake_birth
, fake_death
);
1612 if (qty
[q
].phys_reg
>= 0)
1616 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1617 qty
[q
].mode
, q
, 0, 0,
1618 qty
[q
].birth
, qty
[q
].death
);
1619 if (qty
[q
].phys_reg
>= 0)
1623 #ifdef INSN_SCHEDULING
1624 /* Similarly, avoid false dependencies. */
1625 if (flag_schedule_insns_after_reload
1627 && !SMALL_REGISTER_CLASSES
1628 && qty
[q
].alternate_class
!= NO_REGS
)
1629 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1630 qty
[q
].mode
, q
, 0, 0,
1631 fake_birth
, fake_death
);
1633 if (qty
[q
].alternate_class
!= NO_REGS
)
1634 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1635 qty
[q
].mode
, q
, 0, 0,
1636 qty
[q
].birth
, qty
[q
].death
);
1640 /* Now propagate the register assignments
1641 to the pseudo regs belonging to the qtys. */
1643 for (q
= 0; q
< next_qty
; q
++)
1644 if (qty
[q
].phys_reg
>= 0)
1646 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1647 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1651 free (regs_live_at
);
1655 /* Compare two quantities' priority for getting real registers.
1656 We give shorter-lived quantities higher priority.
1657 Quantities with more references are also preferred, as are quantities that
1658 require multiple registers. This is the identical prioritization as
1659 done by global-alloc.
1661 We used to give preference to registers with *longer* lives, but using
1662 the same algorithm in both local- and global-alloc can speed up execution
1663 of some programs by as much as a factor of three! */
1665 /* Note that the quotient will never be bigger than
1666 the value of floor_log2 times the maximum number of
1667 times a register can occur in one insn (surely less than 100)
1668 weighted by frequency (max REG_FREQ_MAX).
1669 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1670 QTY_CMP_PRI is also used by qty_sugg_compare. */
1672 #define QTY_CMP_PRI(q) \
1673 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1674 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1677 qty_compare (int q1
, int q2
)
1679 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1683 qty_compare_1 (const void *q1p
, const void *q2p
)
1685 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1686 int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1691 /* If qtys are equally good, sort by qty number,
1692 so that the results of qsort leave nothing to chance. */
1696 /* Compare two quantities' priority for getting real registers. This version
1697 is called for quantities that have suggested hard registers. First priority
1698 goes to quantities that have copy preferences, then to those that have
1699 normal preferences. Within those groups, quantities with the lower
1700 number of preferences have the highest priority. Of those, we use the same
1701 algorithm as above. */
1703 #define QTY_CMP_SUGG(q) \
1704 (qty_phys_num_copy_sugg[q] \
1705 ? qty_phys_num_copy_sugg[q] \
1706 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1709 qty_sugg_compare (int q1
, int q2
)
1711 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1716 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1720 qty_sugg_compare_1 (const void *q1p
, const void *q2p
)
1722 int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1723 int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1728 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1732 /* If qtys are equally good, sort by qty number,
1733 so that the results of qsort leave nothing to chance. */
1740 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1741 Returns 1 if have done so, or 0 if cannot.
1743 Combining registers means marking them as having the same quantity
1744 and adjusting the offsets within the quantity if either of
1747 We don't actually combine a hard reg with a pseudo; instead
1748 we just record the hard reg as the suggestion for the pseudo's quantity.
1749 If we really combined them, we could lose if the pseudo lives
1750 across an insn that clobbers the hard reg (eg, movstr).
1752 ALREADY_DEAD is nonzero if USEDREG is known to be dead even though
1753 there is no REG_DEAD note on INSN. This occurs during the processing
1754 of REG_NO_CONFLICT blocks.
1756 MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to
1757 SETREG or if the input and output must share a register.
1758 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1760 There are elaborate checks for the validity of combining. */
1763 combine_regs (rtx usedreg
, rtx setreg
, int may_save_copy
, int insn_number
,
1764 rtx insn
, int already_dead
)
1771 /* Determine the numbers and sizes of registers being used. If a subreg
1772 is present that does not change the entire register, don't consider
1773 this a copy insn. */
1775 while (GET_CODE (usedreg
) == SUBREG
)
1777 rtx subreg
= SUBREG_REG (usedreg
);
1779 if (GET_CODE (subreg
) == REG
)
1781 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1784 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1785 offset
+= subreg_regno_offset (REGNO (subreg
),
1787 SUBREG_BYTE (usedreg
),
1788 GET_MODE (usedreg
));
1790 offset
+= (SUBREG_BYTE (usedreg
)
1791 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1797 if (GET_CODE (usedreg
) != REG
)
1800 ureg
= REGNO (usedreg
);
1801 if (ureg
< FIRST_PSEUDO_REGISTER
)
1802 usize
= HARD_REGNO_NREGS (ureg
, GET_MODE (usedreg
));
1804 usize
= ((GET_MODE_SIZE (GET_MODE (usedreg
))
1805 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)) - 1))
1806 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1808 while (GET_CODE (setreg
) == SUBREG
)
1810 rtx subreg
= SUBREG_REG (setreg
);
1812 if (GET_CODE (subreg
) == REG
)
1814 if (GET_MODE_SIZE (GET_MODE (subreg
)) > UNITS_PER_WORD
)
1817 if (REGNO (subreg
) < FIRST_PSEUDO_REGISTER
)
1818 offset
-= subreg_regno_offset (REGNO (subreg
),
1820 SUBREG_BYTE (setreg
),
1823 offset
-= (SUBREG_BYTE (setreg
)
1824 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1830 if (GET_CODE (setreg
) != REG
)
1833 sreg
= REGNO (setreg
);
1834 if (sreg
< FIRST_PSEUDO_REGISTER
)
1835 ssize
= HARD_REGNO_NREGS (sreg
, GET_MODE (setreg
));
1837 ssize
= ((GET_MODE_SIZE (GET_MODE (setreg
))
1838 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg
)) - 1))
1839 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1841 /* If UREG is a pseudo-register that hasn't already been assigned a
1842 quantity number, it means that it is not local to this block or dies
1843 more than once. In either event, we can't do anything with it. */
1844 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1845 /* Do not combine registers unless one fits within the other. */
1846 || (offset
> 0 && usize
+ offset
> ssize
)
1847 || (offset
< 0 && usize
+ offset
< ssize
)
1848 /* Do not combine with a smaller already-assigned object
1849 if that smaller object is already combined with something bigger. */
1850 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1851 && usize
< qty
[reg_qty
[ureg
]].size
)
1852 /* Can't combine if SREG is not a register we can allocate. */
1853 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1854 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1855 These have already been taken care of. This probably wouldn't
1856 combine anyway, but don't take any chances. */
1857 || (ureg
>= FIRST_PSEUDO_REGISTER
1858 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1859 /* Don't tie something to itself. In most cases it would make no
1860 difference, but it would screw up if the reg being tied to itself
1861 also dies in this insn. */
1863 /* Don't try to connect two different hardware registers. */
1864 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1865 /* Don't connect two different machine modes if they have different
1866 implications as to which registers may be used. */
1867 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1870 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1871 qty_phys_sugg for the pseudo instead of tying them.
1873 Return "failure" so that the lifespan of UREG is terminated here;
1874 that way the two lifespans will be disjoint and nothing will prevent
1875 the pseudo reg from being given this hard reg. */
1877 if (ureg
< FIRST_PSEUDO_REGISTER
)
1879 /* Allocate a quantity number so we have a place to put our
1881 if (reg_qty
[sreg
] == -2)
1882 reg_is_born (setreg
, 2 * insn_number
);
1884 if (reg_qty
[sreg
] >= 0)
1887 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1889 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1890 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1892 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1894 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1895 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1901 /* Similarly for SREG a hard register and UREG a pseudo register. */
1903 if (sreg
< FIRST_PSEUDO_REGISTER
)
1906 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1908 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1909 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1911 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1913 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1914 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1919 /* At this point we know that SREG and UREG are both pseudos.
1920 Do nothing if SREG already has a quantity or is a register that we
1922 if (reg_qty
[sreg
] >= -1
1923 /* If we are not going to let any regs live across calls,
1924 don't tie a call-crossing reg to a non-call-crossing reg. */
1925 || (current_function_has_nonlocal_label
1926 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1927 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1930 /* We don't already know about SREG, so tie it to UREG
1931 if this is the last use of UREG, provided the classes they want
1934 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1935 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
1937 /* Add SREG to UREG's quantity. */
1938 sqty
= reg_qty
[ureg
];
1939 reg_qty
[sreg
] = sqty
;
1940 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1941 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
1942 qty
[sqty
].first_reg
= sreg
;
1944 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1945 update_qty_class (sqty
, sreg
);
1947 /* Update info about quantity SQTY. */
1948 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
1949 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
1950 qty
[sqty
].freq
+= REG_FREQ (sreg
);
1955 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1956 reg_offset
[i
] -= offset
;
1958 qty
[sqty
].size
= ssize
;
1959 qty
[sqty
].mode
= GET_MODE (setreg
);
1968 /* Return 1 if the preferred class of REG allows it to be tied
1969 to a quantity or register whose class is CLASS.
1970 True if REG's reg class either contains or is contained in CLASS. */
1973 reg_meets_class_p (int reg
, enum reg_class
class)
1975 enum reg_class rclass
= reg_preferred_class (reg
);
1976 return (reg_class_subset_p (rclass
, class)
1977 || reg_class_subset_p (class, rclass
));
1980 /* Update the class of QTYNO assuming that REG is being tied to it. */
1983 update_qty_class (int qtyno
, int reg
)
1985 enum reg_class rclass
= reg_preferred_class (reg
);
1986 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
1987 qty
[qtyno
].min_class
= rclass
;
1989 rclass
= reg_alternate_class (reg
);
1990 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
1991 qty
[qtyno
].alternate_class
= rclass
;
1994 /* Handle something which alters the value of an rtx REG.
1996 REG is whatever is set or clobbered. SETTER is the rtx that
1997 is modifying the register.
1999 If it is not really a register, we do nothing.
2000 The file-global variables `this_insn' and `this_insn_number'
2001 carry info from `block_alloc'. */
2004 reg_is_set (rtx reg
, rtx setter
, void *data ATTRIBUTE_UNUSED
)
2006 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2007 a hard register. These may actually not exist any more. */
2009 if (GET_CODE (reg
) != SUBREG
2010 && GET_CODE (reg
) != REG
)
2013 /* Mark this register as being born. If it is used in a CLOBBER, mark
2014 it as being born halfway between the previous insn and this insn so that
2015 it conflicts with our inputs but not the outputs of the previous insn. */
2017 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
2020 /* Handle beginning of the life of register REG.
2021 BIRTH is the index at which this is happening. */
2024 reg_is_born (rtx reg
, int birth
)
2028 if (GET_CODE (reg
) == SUBREG
)
2030 regno
= REGNO (SUBREG_REG (reg
));
2031 if (regno
< FIRST_PSEUDO_REGISTER
)
2032 regno
= subreg_hard_regno (reg
, 1);
2035 regno
= REGNO (reg
);
2037 if (regno
< FIRST_PSEUDO_REGISTER
)
2039 mark_life (regno
, GET_MODE (reg
), 1);
2041 /* If the register was to have been born earlier that the present
2042 insn, mark it as live where it is actually born. */
2043 if (birth
< 2 * this_insn_number
)
2044 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
2048 if (reg_qty
[regno
] == -2)
2049 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
2051 /* If this register has a quantity number, show that it isn't dead. */
2052 if (reg_qty
[regno
] >= 0)
2053 qty
[reg_qty
[regno
]].death
= -1;
2057 /* Record the death of REG in the current insn. If OUTPUT_P is nonzero,
2058 REG is an output that is dying (i.e., it is never used), otherwise it
2059 is an input (the normal case).
2060 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2063 wipe_dead_reg (rtx reg
, int output_p
)
2065 int regno
= REGNO (reg
);
2067 /* If this insn has multiple results,
2068 and the dead reg is used in one of the results,
2069 extend its life to after this insn,
2070 so it won't get allocated together with any other result of this insn.
2072 It is unsafe to use !single_set here since it will ignore an unused
2073 output. Just because an output is unused does not mean the compiler
2074 can assume the side effect will not occur. Consider if REG appears
2075 in the address of an output and we reload the output. If we allocate
2076 REG to the same hard register as an unused output we could set the hard
2077 register before the output reload insn. */
2078 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
2079 && multiple_sets (this_insn
))
2082 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
2084 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
2085 if (GET_CODE (set
) == SET
2086 && GET_CODE (SET_DEST (set
)) != REG
2087 && !rtx_equal_p (reg
, SET_DEST (set
))
2088 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2093 /* If this register is used in an auto-increment address, then extend its
2094 life to after this insn, so that it won't get allocated together with
2095 the result of this insn. */
2096 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
2099 if (regno
< FIRST_PSEUDO_REGISTER
)
2101 mark_life (regno
, GET_MODE (reg
), 0);
2103 /* If a hard register is dying as an output, mark it as in use at
2104 the beginning of this insn (the above statement would cause this
2107 post_mark_life (regno
, GET_MODE (reg
), 1,
2108 2 * this_insn_number
, 2 * this_insn_number
+ 1);
2111 else if (reg_qty
[regno
] >= 0)
2112 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
2115 /* Find a block of SIZE words of hard regs in reg_class CLASS
2116 that can hold something of machine-mode MODE
2117 (but actually we test only the first of the block for holding MODE)
2118 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2119 and return the number of the first of them.
2120 Return -1 if such a block cannot be found.
2121 If QTYNO crosses calls, insist on a register preserved by calls,
2122 unless ACCEPT_CALL_CLOBBERED is nonzero.
2124 If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested
2125 register is available. If not, return -1. */
2128 find_free_reg (enum reg_class
class, enum machine_mode mode
, int qtyno
,
2129 int accept_call_clobbered
, int just_try_suggested
,
2130 int born_index
, int dead_index
)
2133 HARD_REG_SET first_used
, used
;
2134 #ifdef ELIMINABLE_REGS
2135 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2138 /* Validate our parameters. */
2139 if (born_index
< 0 || born_index
> dead_index
)
2142 /* Don't let a pseudo live in a reg across a function call
2143 if we might get a nonlocal goto. */
2144 if (current_function_has_nonlocal_label
2145 && qty
[qtyno
].n_calls_crossed
> 0)
2148 if (accept_call_clobbered
)
2149 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
2150 else if (qty
[qtyno
].n_calls_crossed
== 0)
2151 COPY_HARD_REG_SET (used
, fixed_reg_set
);
2153 COPY_HARD_REG_SET (used
, call_used_reg_set
);
2155 if (accept_call_clobbered
)
2156 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
2158 for (ins
= born_index
; ins
< dead_index
; ins
++)
2159 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
2161 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
2163 /* Don't use the frame pointer reg in local-alloc even if
2164 we may omit the frame pointer, because if we do that and then we
2165 need a frame pointer, reload won't know how to move the pseudo
2166 to another hard reg. It can move only regs made by global-alloc.
2168 This is true of any register that can be eliminated. */
2169 #ifdef ELIMINABLE_REGS
2170 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2171 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
2172 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2173 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2174 that it might be eliminated into. */
2175 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
2178 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
2181 #ifdef CANNOT_CHANGE_MODE_CLASS
2182 cannot_change_mode_set_regs (&used
, mode
, qty
[qtyno
].first_reg
);
2185 /* Normally, the registers that can be used for the first register in
2186 a multi-register quantity are the same as those that can be used for
2187 subsequent registers. However, if just trying suggested registers,
2188 restrict our consideration to them. If there are copy-suggested
2189 register, try them. Otherwise, try the arithmetic-suggested
2191 COPY_HARD_REG_SET (first_used
, used
);
2193 if (just_try_suggested
)
2195 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2196 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2198 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2201 /* If all registers are excluded, we can't do anything. */
2202 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2204 /* If at least one would be suitable, test each hard reg. */
2206 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2208 #ifdef REG_ALLOC_ORDER
2209 int regno
= reg_alloc_order
[i
];
2213 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2214 && HARD_REGNO_MODE_OK (regno
, mode
)
2215 && (qty
[qtyno
].n_calls_crossed
== 0
2216 || accept_call_clobbered
2217 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2220 int size1
= HARD_REGNO_NREGS (regno
, mode
);
2221 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2224 /* Mark that this register is in use between its birth and death
2226 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2229 #ifndef REG_ALLOC_ORDER
2230 /* Skip starting points we know will lose. */
2237 /* If we are just trying suggested register, we have just tried copy-
2238 suggested registers, and there are arithmetic-suggested registers,
2241 /* If it would be profitable to allocate a call-clobbered register
2242 and save and restore it around calls, do that. */
2243 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2244 && qty_phys_num_sugg
[qtyno
] != 0)
2246 /* Don't try the copy-suggested regs again. */
2247 qty_phys_num_copy_sugg
[qtyno
] = 0;
2248 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2249 born_index
, dead_index
);
2252 /* We need not check to see if the current function has nonlocal
2253 labels because we don't put any pseudos that are live over calls in
2254 registers in that case. */
2256 if (! accept_call_clobbered
2257 && flag_caller_saves
2258 && ! just_try_suggested
2259 && qty
[qtyno
].n_calls_crossed
!= 0
2260 && CALLER_SAVE_PROFITABLE (qty
[qtyno
].n_refs
,
2261 qty
[qtyno
].n_calls_crossed
))
2263 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2265 caller_save_needed
= 1;
2271 /* Mark that REGNO with machine-mode MODE is live starting from the current
2272 insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE
2276 mark_life (int regno
, enum machine_mode mode
, int life
)
2278 int j
= HARD_REGNO_NREGS (regno
, mode
);
2281 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2284 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2287 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2288 is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2289 to insn number DEATH (exclusive). */
2292 post_mark_life (int regno
, enum machine_mode mode
, int life
, int birth
,
2295 int j
= HARD_REGNO_NREGS (regno
, mode
);
2297 /* Declare it register if it's a scalar. */
2300 HARD_REG_SET this_reg
;
2302 CLEAR_HARD_REG_SET (this_reg
);
2304 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2307 while (birth
< death
)
2309 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2313 while (birth
< death
)
2315 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2320 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2321 is the register being clobbered, and R1 is a register being used in
2322 the equivalent expression.
2324 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2325 in which it is used, return 1.
2327 Otherwise, return 0. */
2330 no_conflict_p (rtx insn
, rtx r0 ATTRIBUTE_UNUSED
, rtx r1
)
2333 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2336 /* If R1 is a hard register, return 0 since we handle this case
2337 when we scan the insns that actually use it. */
2340 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2341 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2342 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2345 last
= XEXP (note
, 0);
2347 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2350 if (find_reg_note (p
, REG_DEAD
, r1
))
2353 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2354 some earlier optimization pass has inserted instructions into
2355 the sequence, and it is not safe to perform this optimization.
2356 Note that emit_no_conflict_block always ensures that this is
2357 true when these sequences are created. */
2358 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2365 /* Return the number of alternatives for which the constraint string P
2366 indicates that the operand must be equal to operand 0 and that no register
2370 requires_inout (const char *p
)
2374 int reg_allowed
= 0;
2375 int num_matching_alts
= 0;
2378 for ( ; (c
= *p
); p
+= len
)
2380 len
= CONSTRAINT_LEN (c
, p
);
2383 case '=': case '+': case '?':
2384 case '#': case '&': case '!':
2386 case 'm': case '<': case '>': case 'V': case 'o':
2387 case 'E': case 'F': case 'G': case 'H':
2388 case 's': case 'i': case 'n':
2389 case 'I': case 'J': case 'K': case 'L':
2390 case 'M': case 'N': case 'O': case 'P':
2392 /* These don't say anything we care about. */
2396 if (found_zero
&& ! reg_allowed
)
2397 num_matching_alts
++;
2399 found_zero
= reg_allowed
= 0;
2406 case '1': case '2': case '3': case '4': case '5':
2407 case '6': case '7': case '8': case '9':
2408 /* Skip the balance of the matching constraint. */
2411 while (ISDIGIT (*p
));
2416 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
2417 && !EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2427 if (found_zero
&& ! reg_allowed
)
2428 num_matching_alts
++;
2430 return num_matching_alts
;
2434 dump_local_alloc (FILE *file
)
2437 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2438 if (reg_renumber
[i
] != -1)
2439 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);