1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "hard-reg-set.h"
68 #include "basic-block.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
77 /* Next quantity number available for allocation. */
81 /* Information we maitain about each quantity. */
84 /* The number of refs to quantity Q. */
88 /* Insn number (counting from head of basic block)
89 where quantity Q was born. -1 if birth has not been recorded. */
93 /* Insn number (counting from head of basic block)
94 where given quantity died. Due to the way tying is done,
95 and the fact that we consider in this pass only regs that die but once,
96 a quantity can die only once. Each quantity's life span
97 is a set of consecutive insns. -1 if death has not been recorded. */
101 /* Number of words needed to hold the data in given quantity.
102 This depends on its machine mode. It is used for these purposes:
103 1. It is used in computing the relative importances of qtys,
104 which determines the order in which we look for regs for them.
105 2. It is used in rules that prevent tying several registers of
106 different sizes in a way that is geometrically impossible
107 (see combine_regs). */
111 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
115 /* The register number of one pseudo register whose reg_qty value is Q.
116 This register should be the head of the chain
117 maintained in reg_next_in_qty. */
121 /* Reg class contained in (smaller than) the preferred classes of all
122 the pseudo regs that are tied in given quantity.
123 This is the preferred class for allocating that quantity. */
125 enum reg_class min_class
;
127 /* Register class within which we allocate given qty if we can't get
128 its preferred class. */
130 enum reg_class alternate_class
;
132 /* This holds the mode of the registers that are tied to given qty,
133 or VOIDmode if registers with differing modes are tied together. */
135 enum machine_mode mode
;
137 /* the hard reg number chosen for given quantity,
138 or -1 if none was found. */
142 /* Nonzero if this quantity has been used in a SUBREG in some
143 way that is illegal. */
149 static struct qty
*qty
;
151 /* These fields are kept separately to speedup their clearing. */
153 /* We maintain two hard register sets that indicate suggested hard registers
154 for each quantity. The first, phys_copy_sugg, contains hard registers
155 that are tied to the quantity by a simple copy. The second contains all
156 hard registers that are tied to the quantity via an arithmetic operation.
158 The former register set is given priority for allocation. This tends to
159 eliminate copy insns. */
161 /* Element Q is a set of hard registers that are suggested for quantity Q by
164 static HARD_REG_SET
*qty_phys_copy_sugg
;
166 /* Element Q is a set of hard registers that are suggested for quantity Q by
169 static HARD_REG_SET
*qty_phys_sugg
;
171 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
173 static short *qty_phys_num_copy_sugg
;
175 /* Element Q is the number of suggested registers in qty_phys_sugg. */
177 static short *qty_phys_num_sugg
;
179 /* If (REG N) has been assigned a quantity number, is a register number
180 of another register assigned the same quantity number, or -1 for the
181 end of the chain. qty->first_reg point to the head of this chain. */
183 static int *reg_next_in_qty
;
185 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
187 of -1 if this register cannot be allocated by local-alloc,
188 or -2 if not known yet.
190 Note that if we see a use or death of pseudo register N with
191 reg_qty[N] == -2, register N must be local to the current block. If
192 it were used in more than one block, we would have reg_qty[N] == -1.
193 This relies on the fact that if reg_basic_block[N] is >= 0, register N
194 will not appear in any other block. We save a considerable number of
195 tests by exploiting this.
197 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
202 /* The offset (in words) of register N within its quantity.
203 This can be nonzero if register N is SImode, and has been tied
204 to a subreg of a DImode register. */
206 static char *reg_offset
;
208 /* Vector of substitutions of register numbers,
209 used to map pseudo regs into hardware regs.
210 This is set up as a result of register allocation.
211 Element N is the hard reg assigned to pseudo reg N,
212 or is -1 if no hard reg was assigned.
213 If N is a hard reg number, element N is N. */
217 /* Set of hard registers live at the current point in the scan
218 of the instructions in a basic block. */
220 static HARD_REG_SET regs_live
;
222 /* Each set of hard registers indicates registers live at a particular
223 point in the basic block. For N even, regs_live_at[N] says which
224 hard registers are needed *after* insn N/2 (i.e., they may not
225 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
227 If an object is to conflict with the inputs of insn J but not the
228 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
229 if it is to conflict with the outputs of insn J but not the inputs of
230 insn J + 1, it is said to die at index J*2 + 1. */
232 static HARD_REG_SET
*regs_live_at
;
234 /* Communicate local vars `insn_number' and `insn'
235 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
236 static int this_insn_number
;
237 static rtx this_insn
;
241 /* Set when an attempt should be made to replace a register
242 with the associated src entry. */
246 /* Set when a REG_EQUIV note is found or created. Use to
247 keep track of what memory accesses might be created later,
254 /* Loop depth is used to recognize equivalences which appear
255 to be present within the same loop (or in an inner loop). */
259 /* The list of each instruction which initializes this register. */
264 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
265 structure for that register. */
267 static struct equivalence
*reg_equiv
;
269 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
270 static int recorded_label_ref
;
272 static void alloc_qty
PARAMS ((int, enum machine_mode
, int, int));
273 static void validate_equiv_mem_from_store
PARAMS ((rtx
, rtx
, void *));
274 static int validate_equiv_mem
PARAMS ((rtx
, rtx
, rtx
));
275 static int equiv_init_varies_p
PARAMS ((rtx
));
276 static int equiv_init_movable_p
PARAMS ((rtx
, int));
277 static int contains_replace_regs
PARAMS ((rtx
));
278 static int memref_referenced_p
PARAMS ((rtx
, rtx
));
279 static int memref_used_between_p
PARAMS ((rtx
, rtx
, rtx
));
280 static void update_equiv_regs
PARAMS ((void));
281 static void no_equiv
PARAMS ((rtx
, rtx
, void *));
282 static void block_alloc
PARAMS ((int));
283 static int qty_sugg_compare
PARAMS ((int, int));
284 static int qty_sugg_compare_1
PARAMS ((const PTR
, const PTR
));
285 static int qty_compare
PARAMS ((int, int));
286 static int qty_compare_1
PARAMS ((const PTR
, const PTR
));
287 static int combine_regs
PARAMS ((rtx
, rtx
, int, int, rtx
, int));
288 static int reg_meets_class_p
PARAMS ((int, enum reg_class
));
289 static void update_qty_class
PARAMS ((int, int));
290 static void reg_is_set
PARAMS ((rtx
, rtx
, void *));
291 static void reg_is_born
PARAMS ((rtx
, int));
292 static void wipe_dead_reg
PARAMS ((rtx
, int));
293 static int find_free_reg
PARAMS ((enum reg_class
, enum machine_mode
,
294 int, int, int, int, int));
295 static void mark_life
PARAMS ((int, enum machine_mode
, int));
296 static void post_mark_life
PARAMS ((int, enum machine_mode
, int, int, int));
297 static int no_conflict_p
PARAMS ((rtx
, rtx
, rtx
));
298 static int requires_inout
PARAMS ((const char *));
300 /* Allocate a new quantity (new within current basic block)
301 for register number REGNO which is born at index BIRTH
302 within the block. MODE and SIZE are info on reg REGNO. */
305 alloc_qty (regno
, mode
, size
, birth
)
307 enum machine_mode mode
;
310 register int qtyno
= next_qty
++;
312 reg_qty
[regno
] = qtyno
;
313 reg_offset
[regno
] = 0;
314 reg_next_in_qty
[regno
] = -1;
316 qty
[qtyno
].first_reg
= regno
;
317 qty
[qtyno
].size
= size
;
318 qty
[qtyno
].mode
= mode
;
319 qty
[qtyno
].birth
= birth
;
320 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
321 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
322 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
323 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
324 qty
[qtyno
].changes_mode
= REG_CHANGES_MODE (regno
);
327 /* Main entry point of this file. */
335 /* We need to keep track of whether or not we recorded a LABEL_REF so
336 that we know if the jump optimizer needs to be rerun. */
337 recorded_label_ref
= 0;
339 /* Leaf functions and non-leaf functions have different needs.
340 If defined, let the machine say what kind of ordering we
342 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
343 ORDER_REGS_FOR_LOCAL_ALLOC
;
346 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
348 update_equiv_regs ();
350 /* This sets the maximum number of quantities we can have. Quantity
351 numbers start at zero and we can have one for each pseudo. */
352 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
354 /* Allocate vectors of temporary data.
355 See the declarations of these variables, above,
356 for what they mean. */
358 qty
= (struct qty
*) xmalloc (max_qty
* sizeof (struct qty
));
360 = (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
361 qty_phys_num_copy_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
362 qty_phys_sugg
= (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
363 qty_phys_num_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
365 reg_qty
= (int *) xmalloc (max_regno
* sizeof (int));
366 reg_offset
= (char *) xmalloc (max_regno
* sizeof (char));
367 reg_next_in_qty
= (int *) xmalloc (max_regno
* sizeof (int));
369 /* Allocate the reg_renumber array. */
370 allocate_reg_info (max_regno
, FALSE
, TRUE
);
372 /* Determine which pseudo-registers can be allocated by local-alloc.
373 In general, these are the registers used only in a single block and
376 We need not be concerned with which block actually uses the register
377 since we will never see it outside that block. */
379 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
381 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1)
387 /* Force loop below to initialize entire quantity array. */
390 /* Allocate each block's local registers, block by block. */
392 for (b
= 0; b
< n_basic_blocks
; b
++)
394 /* NEXT_QTY indicates which elements of the `qty_...'
395 vectors might need to be initialized because they were used
396 for the previous block; it is set to the entire array before
397 block 0. Initialize those, with explicit loop if there are few,
398 else with bzero and bcopy. Do not initialize vectors that are
399 explicit set by `alloc_qty'. */
403 for (i
= 0; i
< next_qty
; i
++)
405 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
406 qty_phys_num_copy_sugg
[i
] = 0;
407 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
408 qty_phys_num_sugg
[i
] = 0;
413 #define CLEAR(vector) \
414 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
416 CLEAR (qty_phys_copy_sugg
);
417 CLEAR (qty_phys_num_copy_sugg
);
418 CLEAR (qty_phys_sugg
);
419 CLEAR (qty_phys_num_sugg
);
428 free (qty_phys_copy_sugg
);
429 free (qty_phys_num_copy_sugg
);
430 free (qty_phys_sugg
);
431 free (qty_phys_num_sugg
);
435 free (reg_next_in_qty
);
437 return recorded_label_ref
;
440 /* Used for communication between the following two functions: contains
441 a MEM that we wish to ensure remains unchanged. */
442 static rtx equiv_mem
;
444 /* Set nonzero if EQUIV_MEM is modified. */
445 static int equiv_mem_modified
;
447 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
448 Called via note_stores. */
451 validate_equiv_mem_from_store (dest
, set
, data
)
453 rtx set ATTRIBUTE_UNUSED
;
454 void *data ATTRIBUTE_UNUSED
;
456 if ((GET_CODE (dest
) == REG
457 && reg_overlap_mentioned_p (dest
, equiv_mem
))
458 || (GET_CODE (dest
) == MEM
459 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
460 equiv_mem_modified
= 1;
463 /* Verify that no store between START and the death of REG invalidates
464 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
465 by storing into an overlapping memory location, or with a non-const
468 Return 1 if MEMREF remains valid. */
471 validate_equiv_mem (start
, reg
, memref
)
480 equiv_mem_modified
= 0;
482 /* If the memory reference has side effects or is volatile, it isn't a
483 valid equivalence. */
484 if (side_effects_p (memref
))
487 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
492 if (find_reg_note (insn
, REG_DEAD
, reg
))
495 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
496 && ! CONST_CALL_P (insn
))
499 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
501 /* If a register mentioned in MEMREF is modified via an
502 auto-increment, we lose the equivalence. Do the same if one
503 dies; although we could extend the life, it doesn't seem worth
506 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
507 if ((REG_NOTE_KIND (note
) == REG_INC
508 || REG_NOTE_KIND (note
) == REG_DEAD
)
509 && GET_CODE (XEXP (note
, 0)) == REG
510 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
517 /* Returns zero if X is known to be invariant. */
520 equiv_init_varies_p (x
)
523 register RTX_CODE code
= GET_CODE (x
);
525 register const char *fmt
;
530 return ! RTX_UNCHANGING_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
543 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
);
546 if (MEM_VOLATILE_P (x
))
555 fmt
= GET_RTX_FORMAT (code
);
556 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
559 if (equiv_init_varies_p (XEXP (x
, i
)))
562 else if (fmt
[i
] == 'E')
565 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
566 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
573 /* Returns non-zero if X (used to initialize register REGNO) is movable.
574 X is only movable if the registers it uses have equivalent initializations
575 which appear to be within the same loop (or in an inner loop) and movable
576 or if they are not candidates for local_alloc and don't vary. */
579 equiv_init_movable_p (x
, regno
)
585 enum rtx_code code
= GET_CODE (x
);
590 return equiv_init_movable_p (SET_SRC (x
), regno
);
604 return (reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
605 && reg_equiv
[REGNO (x
)].replace
)
606 || (REG_BASIC_BLOCK (REGNO (x
)) < 0 && ! rtx_varies_p (x
));
608 case UNSPEC_VOLATILE
:
612 if (MEM_VOLATILE_P (x
))
621 fmt
= GET_RTX_FORMAT (code
);
622 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
626 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
630 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
631 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
639 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
642 contains_replace_regs (x
)
647 enum rtx_code code
= GET_CODE (x
);
663 return reg_equiv
[REGNO (x
)].replace
;
669 fmt
= GET_RTX_FORMAT (code
);
670 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
674 if (contains_replace_regs (XEXP (x
, i
)))
678 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
679 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
687 /* TRUE if X references a memory location that would be affected by a store
691 memref_referenced_p (memref
, x
)
697 enum rtx_code code
= GET_CODE (x
);
713 return (reg_equiv
[REGNO (x
)].replacement
714 && memref_referenced_p (memref
,
715 reg_equiv
[REGNO (x
)].replacement
));
718 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
723 /* If we are setting a MEM, it doesn't count (its address does), but any
724 other SET_DEST that has a MEM in it is referencing the MEM. */
725 if (GET_CODE (SET_DEST (x
)) == MEM
)
727 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
730 else if (memref_referenced_p (memref
, SET_DEST (x
)))
733 return memref_referenced_p (memref
, SET_SRC (x
));
739 fmt
= GET_RTX_FORMAT (code
);
740 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
744 if (memref_referenced_p (memref
, XEXP (x
, i
)))
748 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
749 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
757 /* TRUE if some insn in the range (START, END] references a memory location
758 that would be affected by a store to MEMREF. */
761 memref_used_between_p (memref
, start
, end
)
768 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
769 insn
= NEXT_INSN (insn
))
770 if (INSN_P (insn
) && memref_referenced_p (memref
, PATTERN (insn
)))
776 /* Return nonzero if the rtx X is invariant over the current function. */
778 function_invariant_p (x
)
783 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
785 if (GET_CODE (x
) == PLUS
786 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
787 && CONSTANT_P (XEXP (x
, 1)))
792 /* Find registers that are equivalent to a single value throughout the
793 compilation (either because they can be referenced in memory or are set once
794 from a single constant). Lower their priority for a register.
796 If such a register is only referenced once, try substituting its value
797 into the using insn. If it succeeds, we can eliminate the register
807 reg_equiv
= (struct equivalence
*) xcalloc (max_regno
, sizeof *reg_equiv
);
809 init_alias_analysis ();
811 /* Scan the insns and find which registers have equivalences. Do this
812 in a separate scan of the insns because (due to -fcse-follow-jumps)
813 a register can be set below its use. */
815 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
822 if (GET_CODE (insn
) == NOTE
)
824 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
826 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
837 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
838 if (REG_NOTE_KIND (note
) == REG_INC
)
839 no_equiv (XEXP (note
, 0), note
, NULL
);
841 set
= single_set (insn
);
843 /* If this insn contains more (or less) than a single SET,
844 only mark all destinations as having no known equivalence. */
847 note_stores (PATTERN (insn
), no_equiv
, NULL
);
850 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
854 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
856 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
858 note_stores (part
, no_equiv
, NULL
);
862 dest
= SET_DEST (set
);
865 /* If this sets a MEM to the contents of a REG that is only used
866 in a single basic block, see if the register is always equivalent
867 to that memory location and if moving the store from INSN to the
868 insn that set REG is safe. If so, put a REG_EQUIV note on the
871 Don't add a REG_EQUIV note if the insn already has one. The existing
872 REG_EQUIV is likely more useful than the one we are adding.
874 If one of the regs in the address has reg_equiv[REGNO].replace set,
875 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
876 optimization may move the set of this register immediately before
877 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
878 the mention in the REG_EQUIV note would be to an uninitialized
880 /* ????? This test isn't good enough; we might see a MEM with a use of
881 a pseudo register before we see its setting insn that will cause
882 reg_equiv[].replace for that pseudo to be set.
883 Equivalences to MEMs should be made in another pass, after the
884 reg_equiv[].replace information has been gathered. */
886 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
887 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
888 && REG_BASIC_BLOCK (regno
) >= 0
889 && REG_N_SETS (regno
) == 1
890 && reg_equiv
[regno
].init_insns
!= 0
891 && reg_equiv
[regno
].init_insns
!= const0_rtx
892 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
894 && ! contains_replace_regs (XEXP (dest
, 0)))
896 rtx init_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
897 if (validate_equiv_mem (init_insn
, src
, dest
)
898 && ! memref_used_between_p (dest
, init_insn
, insn
))
899 REG_NOTES (init_insn
)
900 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
903 /* We only handle the case of a pseudo register being set
904 once, or always to the same value. */
905 /* ??? The mn10200 port breaks if we add equivalences for
906 values that need an ADDRESS_REGS register and set them equivalent
907 to a MEM of a pseudo. The actual problem is in the over-conservative
908 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
909 calculate_needs, but we traditionally work around this problem
910 here by rejecting equivalences when the destination is in a register
911 that's likely spilled. This is fragile, of course, since the
912 preferred class of a pseudo depends on all instructions that set
915 if (GET_CODE (dest
) != REG
916 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
917 || reg_equiv
[regno
].init_insns
== const0_rtx
918 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
919 && GET_CODE (src
) == MEM
))
921 /* This might be seting a SUBREG of a pseudo, a pseudo that is
922 also set somewhere else to a constant. */
923 note_stores (set
, no_equiv
, NULL
);
927 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
929 /* cse sometimes generates function invariants, but doesn't put a
930 REG_EQUAL note on the insn. Since this note would be redundant,
931 there's no point creating it earlier than here. */
932 if (! note
&& ! rtx_varies_p (src
))
934 = note
= gen_rtx_EXPR_LIST (REG_EQUAL
, src
, REG_NOTES (insn
));
936 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
937 since it represents a function call */
938 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
941 if (REG_N_SETS (regno
) != 1
943 || rtx_varies_p (XEXP (note
, 0))
944 || (reg_equiv
[regno
].replacement
945 && ! rtx_equal_p (XEXP (note
, 0),
946 reg_equiv
[regno
].replacement
))))
948 no_equiv (dest
, set
, NULL
);
951 /* Record this insn as initializing this register. */
952 reg_equiv
[regno
].init_insns
953 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
955 /* If this register is known to be equal to a constant, record that
956 it is always equivalent to the constant. */
957 if (note
&& ! rtx_varies_p (XEXP (note
, 0)))
958 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
960 /* If this insn introduces a "constant" register, decrease the priority
961 of that register. Record this insn if the register is only used once
962 more and the equivalence value is the same as our source.
964 The latter condition is checked for two reasons: First, it is an
965 indication that it may be more efficient to actually emit the insn
966 as written (if no registers are available, reload will substitute
967 the equivalence). Secondly, it avoids problems with any registers
968 dying in this insn whose death notes would be missed.
970 If we don't have a REG_EQUIV note, see if this insn is loading
971 a register used only in one basic block from a MEM. If so, and the
972 MEM remains unchanged for the life of the register, add a REG_EQUIV
975 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
977 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
978 && GET_CODE (SET_SRC (set
)) == MEM
979 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
980 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
985 int regno
= REGNO (dest
);
987 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
988 We might end up substituting the LABEL_REF for uses of the
989 pseudo here or later. That kind of transformation may turn an
990 indirect jump into a direct jump, in which case we must rerun the
991 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
992 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
993 || (GET_CODE (XEXP (note
, 0)) == CONST
994 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
995 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
997 recorded_label_ref
= 1;
999 reg_equiv
[regno
].replacement
= XEXP (note
, 0);
1000 reg_equiv
[regno
].src
= src
;
1001 reg_equiv
[regno
].loop_depth
= loop_depth
;
1003 /* Don't mess with things live during setjmp. */
1004 if (REG_LIVE_LENGTH (regno
) >= 0)
1006 /* Note that the statement below does not affect the priority
1008 REG_LIVE_LENGTH (regno
) *= 2;
1011 /* If the register is referenced exactly twice, meaning it is
1012 set once and used once, indicate that the reference may be
1013 replaced by the equivalence we computed above. Do this
1014 even if the register is only used in one block so that
1015 dependencies can be handled where the last register is
1016 used in a different block (i.e. HIGH / LO_SUM sequences)
1017 and to reduce the number of registers alive across calls.
1019 It would be nice to use "loop_depth * 2" in the compare
1020 below. Unfortunately, LOOP_DEPTH need not be constant within
1021 a basic block so this would be too complicated.
1023 This case normally occurs when a parameter is read from
1024 memory and then used exactly once, not in a loop. */
1026 if (REG_N_REFS (regno
) == 2
1027 && (rtx_equal_p (XEXP (note
, 0), src
)
1028 || ! equiv_init_varies_p (src
))
1029 && GET_CODE (insn
) == INSN
1030 && equiv_init_movable_p (PATTERN (insn
), regno
))
1031 reg_equiv
[regno
].replace
= 1;
1036 /* Now scan all regs killed in an insn to see if any of them are
1037 registers only used that once. If so, see if we can replace the
1038 reference with the equivalent from. If we can, delete the
1039 initializing reference and this register will go away. If we
1040 can't replace the reference, and the initialzing reference is
1041 within the same loop (or in an inner loop), then move the register
1042 initialization just before the use, so that they are in the same
1045 Skip this optimization if loop_depth isn't initially zero since
1046 that indicates a mismatch between loop begin and loop end notes
1047 (i.e. gcc.dg/noncompile/920721-2.c). */
1048 block
= n_basic_blocks
- 1;
1049 for (insn
= (loop_depth
== 0) ? get_last_insn () : NULL_RTX
;
1050 insn
; insn
= PREV_INSN (insn
))
1054 if (! INSN_P (insn
))
1056 if (GET_CODE (insn
) == NOTE
)
1058 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
1059 block
= NOTE_BASIC_BLOCK (insn
)->index
- 1;
1060 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
1066 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
1073 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1075 if (REG_NOTE_KIND (link
) == REG_DEAD
1076 /* Make sure this insn still refers to the register. */
1077 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
1079 int regno
= REGNO (XEXP (link
, 0));
1082 if (! reg_equiv
[regno
].replace
1083 || reg_equiv
[regno
].loop_depth
< loop_depth
)
1086 /* reg_equiv[REGNO].replace gets set only when
1087 REG_N_REFS[REGNO] is 2, i.e. the register is set
1088 once and used once. (If it were only set, but not used,
1089 flow would have deleted the setting insns.) Hence
1090 there can only be one insn in reg_equiv[REGNO].init_insns. */
1091 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
1093 if (asm_noperands (PATTERN (equiv_insn
)) < 0
1094 && validate_replace_rtx (regno_reg_rtx
[regno
],
1095 reg_equiv
[regno
].src
, insn
))
1101 /* Find the last note. */
1102 for (last_link
= link
; XEXP (last_link
, 1);
1103 last_link
= XEXP (last_link
, 1))
1106 /* Append the REG_DEAD notes from equiv_insn. */
1107 equiv_link
= REG_NOTES (equiv_insn
);
1111 equiv_link
= XEXP (equiv_link
, 1);
1112 if (REG_NOTE_KIND (note
) == REG_DEAD
)
1114 remove_note (equiv_insn
, note
);
1115 XEXP (last_link
, 1) = note
;
1116 XEXP (note
, 1) = NULL_RTX
;
1121 remove_death (regno
, insn
);
1122 REG_N_REFS (regno
) = 0;
1123 PUT_CODE (equiv_insn
, NOTE
);
1124 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1125 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1127 /* Move the initialization of the register to just before
1128 INSN. Update the flow information. */
1129 else if (PREV_INSN (insn
) != equiv_insn
)
1133 emit_insn_before (copy_rtx (PATTERN (equiv_insn
)), insn
);
1134 REG_NOTES (PREV_INSN (insn
)) = REG_NOTES (equiv_insn
);
1135 REG_NOTES (equiv_insn
) = 0;
1137 PUT_CODE (equiv_insn
, NOTE
);
1138 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1139 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1141 REG_BASIC_BLOCK (regno
) = block
>= 0 ? block
: 0;
1142 REG_N_CALLS_CROSSED (regno
) = 0;
1143 REG_LIVE_LENGTH (regno
) = 2;
1145 if (block
>= 0 && insn
== BLOCK_HEAD (block
))
1146 BLOCK_HEAD (block
) = PREV_INSN (insn
);
1148 for (l
= 0; l
< n_basic_blocks
; l
++)
1150 CLEAR_REGNO_REG_SET (
1151 BASIC_BLOCK (l
)->global_live_at_start
,
1153 CLEAR_REGNO_REG_SET (
1154 BASIC_BLOCK (l
)->global_live_at_end
,
1163 end_alias_analysis ();
1167 /* Mark REG as having no known equivalence.
1168 Some instructions might have been proceessed before and furnished
1169 with REG_EQUIV notes for this register; these notes will have to be
1171 STORE is the piece of RTL that does the non-constant / conflicting
1172 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1173 but needs to be there because this function is called from note_stores. */
1175 no_equiv (reg
, store
, data
)
1176 rtx reg
, store ATTRIBUTE_UNUSED
;
1177 void *data ATTRIBUTE_UNUSED
;
1182 if (GET_CODE (reg
) != REG
)
1184 regno
= REGNO (reg
);
1185 list
= reg_equiv
[regno
].init_insns
;
1186 if (list
== const0_rtx
)
1188 for (; list
; list
= XEXP (list
, 1))
1190 rtx insn
= XEXP (list
, 0);
1191 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1193 reg_equiv
[regno
].init_insns
= const0_rtx
;
1194 reg_equiv
[regno
].replacement
= NULL_RTX
;
1197 /* Allocate hard regs to the pseudo regs used only within block number B.
1198 Only the pseudos that die but once can be handled. */
1207 int insn_number
= 0;
1209 int max_uid
= get_max_uid ();
1211 int no_conflict_combined_regno
= -1;
1213 /* Count the instructions in the basic block. */
1215 insn
= BLOCK_END (b
);
1218 if (GET_CODE (insn
) != NOTE
)
1219 if (++insn_count
> max_uid
)
1221 if (insn
== BLOCK_HEAD (b
))
1223 insn
= PREV_INSN (insn
);
1226 /* +2 to leave room for a post_mark_life at the last insn and for
1227 the birth of a CLOBBER in the first insn. */
1228 regs_live_at
= (HARD_REG_SET
*) xcalloc ((2 * insn_count
+ 2),
1229 sizeof (HARD_REG_SET
));
1231 /* Initialize table of hardware registers currently live. */
1233 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1235 /* This loop scans the instructions of the basic block
1236 and assigns quantities to registers.
1237 It computes which registers to tie. */
1239 insn
= BLOCK_HEAD (b
);
1242 if (GET_CODE (insn
) != NOTE
)
1247 register rtx link
, set
;
1248 register int win
= 0;
1249 register rtx r0
, r1
= NULL_RTX
;
1250 int combined_regno
= -1;
1253 this_insn_number
= insn_number
;
1256 extract_insn (insn
);
1257 which_alternative
= -1;
1259 /* Is this insn suitable for tying two registers?
1260 If so, try doing that.
1261 Suitable insns are those with at least two operands and where
1262 operand 0 is an output that is a register that is not
1265 We can tie operand 0 with some operand that dies in this insn.
1266 First look for operands that are required to be in the same
1267 register as operand 0. If we find such, only try tying that
1268 operand or one that can be put into that operand if the
1269 operation is commutative. If we don't find an operand
1270 that is required to be in the same register as operand 0,
1271 we can tie with any operand.
1273 Subregs in place of regs are also ok.
1275 If tying is done, WIN is set nonzero. */
1278 && recog_data
.n_operands
> 1
1279 && recog_data
.constraints
[0][0] == '='
1280 && recog_data
.constraints
[0][1] != '&')
1282 /* If non-negative, is an operand that must match operand 0. */
1283 int must_match_0
= -1;
1284 /* Counts number of alternatives that require a match with
1286 int n_matching_alts
= 0;
1288 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1290 const char *p
= recog_data
.constraints
[i
];
1291 int this_match
= (requires_inout (p
));
1293 n_matching_alts
+= this_match
;
1294 if (this_match
== recog_data
.n_alternatives
)
1298 r0
= recog_data
.operand
[0];
1299 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1301 /* Skip this operand if we found an operand that
1302 must match operand 0 and this operand isn't it
1303 and can't be made to be it by commutativity. */
1305 if (must_match_0
>= 0 && i
!= must_match_0
1306 && ! (i
== must_match_0
+ 1
1307 && recog_data
.constraints
[i
-1][0] == '%')
1308 && ! (i
== must_match_0
- 1
1309 && recog_data
.constraints
[i
][0] == '%'))
1312 /* Likewise if each alternative has some operand that
1313 must match operand zero. In that case, skip any
1314 operand that doesn't list operand 0 since we know that
1315 the operand always conflicts with operand 0. We
1316 ignore commutatity in this case to keep things simple. */
1317 if (n_matching_alts
== recog_data
.n_alternatives
1318 && 0 == requires_inout (recog_data
.constraints
[i
]))
1321 r1
= recog_data
.operand
[i
];
1323 /* If the operand is an address, find a register in it.
1324 There may be more than one register, but we only try one
1326 if (recog_data
.constraints
[i
][0] == 'p')
1327 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1330 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1332 /* We have two priorities for hard register preferences.
1333 If we have a move insn or an insn whose first input
1334 can only be in the same register as the output, give
1335 priority to an equivalence found from that insn. */
1337 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1339 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1340 win
= combine_regs (r1
, r0
, may_save_copy
,
1341 insn_number
, insn
, 0);
1348 /* Recognize an insn sequence with an ultimate result
1349 which can safely overlap one of the inputs.
1350 The sequence begins with a CLOBBER of its result,
1351 and ends with an insn that copies the result to itself
1352 and has a REG_EQUAL note for an equivalent formula.
1353 That note indicates what the inputs are.
1354 The result and the input can overlap if each insn in
1355 the sequence either doesn't mention the input
1356 or has a REG_NO_CONFLICT note to inhibit the conflict.
1358 We do the combining test at the CLOBBER so that the
1359 destination register won't have had a quantity number
1360 assigned, since that would prevent combining. */
1363 && GET_CODE (PATTERN (insn
)) == CLOBBER
1364 && (r0
= XEXP (PATTERN (insn
), 0),
1365 GET_CODE (r0
) == REG
)
1366 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1367 && XEXP (link
, 0) != 0
1368 && GET_CODE (XEXP (link
, 0)) == INSN
1369 && (set
= single_set (XEXP (link
, 0))) != 0
1370 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1371 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1374 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1375 /* Check that we have such a sequence. */
1376 && no_conflict_p (insn
, r0
, r1
))
1377 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1378 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1379 && (r1
= XEXP (XEXP (note
, 0), 0),
1380 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1381 && no_conflict_p (insn
, r0
, r1
))
1382 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1384 /* Here we care if the operation to be computed is
1386 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1387 || GET_CODE (XEXP (note
, 0)) == NE
1388 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1389 && (r1
= XEXP (XEXP (note
, 0), 1),
1390 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1391 && no_conflict_p (insn
, r0
, r1
))
1392 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1394 /* If we did combine something, show the register number
1395 in question so that we know to ignore its death. */
1397 no_conflict_combined_regno
= REGNO (r1
);
1400 /* If registers were just tied, set COMBINED_REGNO
1401 to the number of the register used in this insn
1402 that was tied to the register set in this insn.
1403 This register's qty should not be "killed". */
1407 while (GET_CODE (r1
) == SUBREG
)
1408 r1
= SUBREG_REG (r1
);
1409 combined_regno
= REGNO (r1
);
1412 /* Mark the death of everything that dies in this instruction,
1413 except for anything that was just combined. */
1415 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1416 if (REG_NOTE_KIND (link
) == REG_DEAD
1417 && GET_CODE (XEXP (link
, 0)) == REG
1418 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1419 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1420 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1422 wipe_dead_reg (XEXP (link
, 0), 0);
1424 /* Allocate qty numbers for all registers local to this block
1425 that are born (set) in this instruction.
1426 A pseudo that already has a qty is not changed. */
1428 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1430 /* If anything is set in this insn and then unused, mark it as dying
1431 after this insn, so it will conflict with our outputs. This
1432 can't match with something that combined, and it doesn't matter
1433 if it did. Do this after the calls to reg_is_set since these
1434 die after, not during, the current insn. */
1436 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1437 if (REG_NOTE_KIND (link
) == REG_UNUSED
1438 && GET_CODE (XEXP (link
, 0)) == REG
)
1439 wipe_dead_reg (XEXP (link
, 0), 1);
1441 /* If this is an insn that has a REG_RETVAL note pointing at a
1442 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1443 block, so clear any register number that combined within it. */
1444 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1445 && GET_CODE (XEXP (note
, 0)) == INSN
1446 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1447 no_conflict_combined_regno
= -1;
1450 /* Set the registers live after INSN_NUMBER. Note that we never
1451 record the registers live before the block's first insn, since no
1452 pseudos we care about are live before that insn. */
1454 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1455 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1457 if (insn
== BLOCK_END (b
))
1460 insn
= NEXT_INSN (insn
);
1463 /* Now every register that is local to this basic block
1464 should have been given a quantity, or else -1 meaning ignore it.
1465 Every quantity should have a known birth and death.
1467 Order the qtys so we assign them registers in order of the
1468 number of suggested registers they need so we allocate those with
1469 the most restrictive needs first. */
1471 qty_order
= (int *) xmalloc (next_qty
* sizeof (int));
1472 for (i
= 0; i
< next_qty
; i
++)
1475 #define EXCHANGE(I1, I2) \
1476 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1481 /* Make qty_order[2] be the one to allocate last. */
1482 if (qty_sugg_compare (0, 1) > 0)
1484 if (qty_sugg_compare (1, 2) > 0)
1487 /* ... Fall through ... */
1489 /* Put the best one to allocate in qty_order[0]. */
1490 if (qty_sugg_compare (0, 1) > 0)
1493 /* ... Fall through ... */
1497 /* Nothing to do here. */
1501 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1504 /* Try to put each quantity in a suggested physical register, if it has one.
1505 This may cause registers to be allocated that otherwise wouldn't be, but
1506 this seems acceptable in local allocation (unlike global allocation). */
1507 for (i
= 0; i
< next_qty
; i
++)
1510 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1511 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1512 0, 1, qty
[q
].birth
, qty
[q
].death
);
1514 qty
[q
].phys_reg
= -1;
1517 /* Order the qtys so we assign them registers in order of
1518 decreasing length of life. Normally call qsort, but if we
1519 have only a very small number of quantities, sort them ourselves. */
1521 for (i
= 0; i
< next_qty
; i
++)
1524 #define EXCHANGE(I1, I2) \
1525 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1530 /* Make qty_order[2] be the one to allocate last. */
1531 if (qty_compare (0, 1) > 0)
1533 if (qty_compare (1, 2) > 0)
1536 /* ... Fall through ... */
1538 /* Put the best one to allocate in qty_order[0]. */
1539 if (qty_compare (0, 1) > 0)
1542 /* ... Fall through ... */
1546 /* Nothing to do here. */
1550 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1553 /* Now for each qty that is not a hardware register,
1554 look for a hardware register to put it in.
1555 First try the register class that is cheapest for this qty,
1556 if there is more than one class. */
1558 for (i
= 0; i
< next_qty
; i
++)
1561 if (qty
[q
].phys_reg
< 0)
1563 #ifdef INSN_SCHEDULING
1564 /* These values represent the adjusted lifetime of a qty so
1565 that it conflicts with qtys which appear near the start/end
1566 of this qty's lifetime.
1568 The purpose behind extending the lifetime of this qty is to
1569 discourage the register allocator from creating false
1572 The adjustment value is choosen to indicate that this qty
1573 conflicts with all the qtys in the instructions immediately
1574 before and after the lifetime of this qty.
1576 Experiments have shown that higher values tend to hurt
1577 overall code performance.
1579 If allocation using the extended lifetime fails we will try
1580 again with the qty's unadjusted lifetime. */
1581 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1582 int fake_death
= MIN (insn_number
* 2 + 1,
1583 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1586 if (N_REG_CLASSES
> 1)
1588 #ifdef INSN_SCHEDULING
1589 /* We try to avoid using hard registers allocated to qtys which
1590 are born immediately after this qty or die immediately before
1593 This optimization is only appropriate when we will run
1594 a scheduling pass after reload and we are not optimizing
1596 if (flag_schedule_insns_after_reload
1598 && !SMALL_REGISTER_CLASSES
)
1600 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1601 qty
[q
].mode
, q
, 0, 0,
1602 fake_birth
, fake_death
);
1603 if (qty
[q
].phys_reg
>= 0)
1607 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1608 qty
[q
].mode
, q
, 0, 0,
1609 qty
[q
].birth
, qty
[q
].death
);
1610 if (qty
[q
].phys_reg
>= 0)
1614 #ifdef INSN_SCHEDULING
1615 /* Similarly, avoid false dependencies. */
1616 if (flag_schedule_insns_after_reload
1618 && !SMALL_REGISTER_CLASSES
1619 && qty
[q
].alternate_class
!= NO_REGS
)
1620 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1621 qty
[q
].mode
, q
, 0, 0,
1622 fake_birth
, fake_death
);
1624 if (qty
[q
].alternate_class
!= NO_REGS
)
1625 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1626 qty
[q
].mode
, q
, 0, 0,
1627 qty
[q
].birth
, qty
[q
].death
);
1631 /* Now propagate the register assignments
1632 to the pseudo regs belonging to the qtys. */
1634 for (q
= 0; q
< next_qty
; q
++)
1635 if (qty
[q
].phys_reg
>= 0)
1637 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1638 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1642 free (regs_live_at
);
1646 /* Compare two quantities' priority for getting real registers.
1647 We give shorter-lived quantities higher priority.
1648 Quantities with more references are also preferred, as are quantities that
1649 require multiple registers. This is the identical prioritization as
1650 done by global-alloc.
1652 We used to give preference to registers with *longer* lives, but using
1653 the same algorithm in both local- and global-alloc can speed up execution
1654 of some programs by as much as a factor of three! */
1656 /* Note that the quotient will never be bigger than
1657 the value of floor_log2 times the maximum number of
1658 times a register can occur in one insn (surely less than 100).
1659 Multiplying this by 10000 can't overflow.
1660 QTY_CMP_PRI is also used by qty_sugg_compare. */
1662 #define QTY_CMP_PRI(q) \
1663 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].n_refs * qty[q].size) \
1664 / (qty[q].death - qty[q].birth)) * 10000))
1667 qty_compare (q1
, q2
)
1670 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1674 qty_compare_1 (q1p
, q2p
)
1678 register int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1679 register int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1684 /* If qtys are equally good, sort by qty number,
1685 so that the results of qsort leave nothing to chance. */
1689 /* Compare two quantities' priority for getting real registers. This version
1690 is called for quantities that have suggested hard registers. First priority
1691 goes to quantities that have copy preferences, then to those that have
1692 normal preferences. Within those groups, quantities with the lower
1693 number of preferences have the highest priority. Of those, we use the same
1694 algorithm as above. */
1696 #define QTY_CMP_SUGG(q) \
1697 (qty_phys_num_copy_sugg[q] \
1698 ? qty_phys_num_copy_sugg[q] \
1699 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1702 qty_sugg_compare (q1
, q2
)
1705 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1710 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1714 qty_sugg_compare_1 (q1p
, q2p
)
1718 register int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1719 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1724 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1728 /* If qtys are equally good, sort by qty number,
1729 so that the results of qsort leave nothing to chance. */
1736 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1737 Returns 1 if have done so, or 0 if cannot.
1739 Combining registers means marking them as having the same quantity
1740 and adjusting the offsets within the quantity if either of
1743 We don't actually combine a hard reg with a pseudo; instead
1744 we just record the hard reg as the suggestion for the pseudo's quantity.
1745 If we really combined them, we could lose if the pseudo lives
1746 across an insn that clobbers the hard reg (eg, movstr).
1748 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1749 there is no REG_DEAD note on INSN. This occurs during the processing
1750 of REG_NO_CONFLICT blocks.
1752 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1753 SETREG or if the input and output must share a register.
1754 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1756 There are elaborate checks for the validity of combining. */
1759 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1760 rtx usedreg
, setreg
;
1766 register int ureg
, sreg
;
1767 register int offset
= 0;
1771 /* Determine the numbers and sizes of registers being used. If a subreg
1772 is present that does not change the entire register, don't consider
1773 this a copy insn. */
1775 while (GET_CODE (usedreg
) == SUBREG
)
1777 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg
))) > UNITS_PER_WORD
)
1779 offset
+= SUBREG_WORD (usedreg
);
1780 usedreg
= SUBREG_REG (usedreg
);
1782 if (GET_CODE (usedreg
) != REG
)
1784 ureg
= REGNO (usedreg
);
1785 usize
= REG_SIZE (usedreg
);
1787 while (GET_CODE (setreg
) == SUBREG
)
1789 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg
))) > UNITS_PER_WORD
)
1791 offset
-= SUBREG_WORD (setreg
);
1792 setreg
= SUBREG_REG (setreg
);
1794 if (GET_CODE (setreg
) != REG
)
1796 sreg
= REGNO (setreg
);
1797 ssize
= REG_SIZE (setreg
);
1799 /* If UREG is a pseudo-register that hasn't already been assigned a
1800 quantity number, it means that it is not local to this block or dies
1801 more than once. In either event, we can't do anything with it. */
1802 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1803 /* Do not combine registers unless one fits within the other. */
1804 || (offset
> 0 && usize
+ offset
> ssize
)
1805 || (offset
< 0 && usize
+ offset
< ssize
)
1806 /* Do not combine with a smaller already-assigned object
1807 if that smaller object is already combined with something bigger. */
1808 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1809 && usize
< qty
[reg_qty
[ureg
]].size
)
1810 /* Can't combine if SREG is not a register we can allocate. */
1811 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1812 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1813 These have already been taken care of. This probably wouldn't
1814 combine anyway, but don't take any chances. */
1815 || (ureg
>= FIRST_PSEUDO_REGISTER
1816 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1817 /* Don't tie something to itself. In most cases it would make no
1818 difference, but it would screw up if the reg being tied to itself
1819 also dies in this insn. */
1821 /* Don't try to connect two different hardware registers. */
1822 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1823 /* Don't connect two different machine modes if they have different
1824 implications as to which registers may be used. */
1825 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1828 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1829 qty_phys_sugg for the pseudo instead of tying them.
1831 Return "failure" so that the lifespan of UREG is terminated here;
1832 that way the two lifespans will be disjoint and nothing will prevent
1833 the pseudo reg from being given this hard reg. */
1835 if (ureg
< FIRST_PSEUDO_REGISTER
)
1837 /* Allocate a quantity number so we have a place to put our
1839 if (reg_qty
[sreg
] == -2)
1840 reg_is_born (setreg
, 2 * insn_number
);
1842 if (reg_qty
[sreg
] >= 0)
1845 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1847 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1848 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1850 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1852 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1853 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1859 /* Similarly for SREG a hard register and UREG a pseudo register. */
1861 if (sreg
< FIRST_PSEUDO_REGISTER
)
1864 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1866 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1867 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1869 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1871 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1872 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1877 /* At this point we know that SREG and UREG are both pseudos.
1878 Do nothing if SREG already has a quantity or is a register that we
1880 if (reg_qty
[sreg
] >= -1
1881 /* If we are not going to let any regs live across calls,
1882 don't tie a call-crossing reg to a non-call-crossing reg. */
1883 || (current_function_has_nonlocal_label
1884 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1885 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1888 /* We don't already know about SREG, so tie it to UREG
1889 if this is the last use of UREG, provided the classes they want
1892 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1893 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
1895 /* Add SREG to UREG's quantity. */
1896 sqty
= reg_qty
[ureg
];
1897 reg_qty
[sreg
] = sqty
;
1898 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1899 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
1900 qty
[sqty
].first_reg
= sreg
;
1902 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1903 update_qty_class (sqty
, sreg
);
1905 /* Update info about quantity SQTY. */
1906 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
1907 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
1912 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1913 reg_offset
[i
] -= offset
;
1915 qty
[sqty
].size
= ssize
;
1916 qty
[sqty
].mode
= GET_MODE (setreg
);
1925 /* Return 1 if the preferred class of REG allows it to be tied
1926 to a quantity or register whose class is CLASS.
1927 True if REG's reg class either contains or is contained in CLASS. */
1930 reg_meets_class_p (reg
, class)
1932 enum reg_class
class;
1934 register enum reg_class rclass
= reg_preferred_class (reg
);
1935 return (reg_class_subset_p (rclass
, class)
1936 || reg_class_subset_p (class, rclass
));
1939 /* Update the class of QTYNO assuming that REG is being tied to it. */
1942 update_qty_class (qtyno
, reg
)
1946 enum reg_class rclass
= reg_preferred_class (reg
);
1947 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
1948 qty
[qtyno
].min_class
= rclass
;
1950 rclass
= reg_alternate_class (reg
);
1951 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
1952 qty
[qtyno
].alternate_class
= rclass
;
1954 if (REG_CHANGES_MODE (reg
))
1955 qty
[qtyno
].changes_mode
= 1;
1958 /* Handle something which alters the value of an rtx REG.
1960 REG is whatever is set or clobbered. SETTER is the rtx that
1961 is modifying the register.
1963 If it is not really a register, we do nothing.
1964 The file-global variables `this_insn' and `this_insn_number'
1965 carry info from `block_alloc'. */
1968 reg_is_set (reg
, setter
, data
)
1971 void *data ATTRIBUTE_UNUSED
;
1973 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1974 a hard register. These may actually not exist any more. */
1976 if (GET_CODE (reg
) != SUBREG
1977 && GET_CODE (reg
) != REG
)
1980 /* Mark this register as being born. If it is used in a CLOBBER, mark
1981 it as being born halfway between the previous insn and this insn so that
1982 it conflicts with our inputs but not the outputs of the previous insn. */
1984 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
1987 /* Handle beginning of the life of register REG.
1988 BIRTH is the index at which this is happening. */
1991 reg_is_born (reg
, birth
)
1997 if (GET_CODE (reg
) == SUBREG
)
1998 regno
= REGNO (SUBREG_REG (reg
)) + SUBREG_WORD (reg
);
2000 regno
= REGNO (reg
);
2002 if (regno
< FIRST_PSEUDO_REGISTER
)
2004 mark_life (regno
, GET_MODE (reg
), 1);
2006 /* If the register was to have been born earlier that the present
2007 insn, mark it as live where it is actually born. */
2008 if (birth
< 2 * this_insn_number
)
2009 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
2013 if (reg_qty
[regno
] == -2)
2014 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
2016 /* If this register has a quantity number, show that it isn't dead. */
2017 if (reg_qty
[regno
] >= 0)
2018 qty
[reg_qty
[regno
]].death
= -1;
2022 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2023 REG is an output that is dying (i.e., it is never used), otherwise it
2024 is an input (the normal case).
2025 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2028 wipe_dead_reg (reg
, output_p
)
2032 register int regno
= REGNO (reg
);
2034 /* If this insn has multiple results,
2035 and the dead reg is used in one of the results,
2036 extend its life to after this insn,
2037 so it won't get allocated together with any other result of this insn.
2039 It is unsafe to use !single_set here since it will ignore an unused
2040 output. Just because an output is unused does not mean the compiler
2041 can assume the side effect will not occur. Consider if REG appears
2042 in the address of an output and we reload the output. If we allocate
2043 REG to the same hard register as an unused output we could set the hard
2044 register before the output reload insn. */
2045 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
2046 && multiple_sets (this_insn
))
2049 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
2051 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
2052 if (GET_CODE (set
) == SET
2053 && GET_CODE (SET_DEST (set
)) != REG
2054 && !rtx_equal_p (reg
, SET_DEST (set
))
2055 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2060 /* If this register is used in an auto-increment address, then extend its
2061 life to after this insn, so that it won't get allocated together with
2062 the result of this insn. */
2063 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
2066 if (regno
< FIRST_PSEUDO_REGISTER
)
2068 mark_life (regno
, GET_MODE (reg
), 0);
2070 /* If a hard register is dying as an output, mark it as in use at
2071 the beginning of this insn (the above statement would cause this
2074 post_mark_life (regno
, GET_MODE (reg
), 1,
2075 2 * this_insn_number
, 2 * this_insn_number
+ 1);
2078 else if (reg_qty
[regno
] >= 0)
2079 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
2082 /* Find a block of SIZE words of hard regs in reg_class CLASS
2083 that can hold something of machine-mode MODE
2084 (but actually we test only the first of the block for holding MODE)
2085 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2086 and return the number of the first of them.
2087 Return -1 if such a block cannot be found.
2088 If QTYNO crosses calls, insist on a register preserved by calls,
2089 unless ACCEPT_CALL_CLOBBERED is nonzero.
2091 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2092 register is available. If not, return -1. */
2095 find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, just_try_suggested
,
2096 born_index
, dead_index
)
2097 enum reg_class
class;
2098 enum machine_mode mode
;
2100 int accept_call_clobbered
;
2101 int just_try_suggested
;
2102 int born_index
, dead_index
;
2104 register int i
, ins
;
2106 /* Declare it register if it's a scalar. */
2109 HARD_REG_SET used
, first_used
;
2110 #ifdef ELIMINABLE_REGS
2111 static struct {int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2114 /* Validate our parameters. */
2115 if (born_index
< 0 || born_index
> dead_index
)
2118 /* Don't let a pseudo live in a reg across a function call
2119 if we might get a nonlocal goto. */
2120 if (current_function_has_nonlocal_label
2121 && qty
[qtyno
].n_calls_crossed
> 0)
2124 if (accept_call_clobbered
)
2125 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
2126 else if (qty
[qtyno
].n_calls_crossed
== 0)
2127 COPY_HARD_REG_SET (used
, fixed_reg_set
);
2129 COPY_HARD_REG_SET (used
, call_used_reg_set
);
2131 if (accept_call_clobbered
)
2132 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
2134 for (ins
= born_index
; ins
< dead_index
; ins
++)
2135 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
2137 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
2139 /* Don't use the frame pointer reg in local-alloc even if
2140 we may omit the frame pointer, because if we do that and then we
2141 need a frame pointer, reload won't know how to move the pseudo
2142 to another hard reg. It can move only regs made by global-alloc.
2144 This is true of any register that can be eliminated. */
2145 #ifdef ELIMINABLE_REGS
2146 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2147 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
2148 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2149 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2150 that it might be eliminated into. */
2151 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
2154 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
2157 #ifdef CLASS_CANNOT_CHANGE_MODE
2158 if (qty
[qtyno
].changes_mode
)
2159 IOR_HARD_REG_SET (used
,
2160 reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
]);
2163 /* Normally, the registers that can be used for the first register in
2164 a multi-register quantity are the same as those that can be used for
2165 subsequent registers. However, if just trying suggested registers,
2166 restrict our consideration to them. If there are copy-suggested
2167 register, try them. Otherwise, try the arithmetic-suggested
2169 COPY_HARD_REG_SET (first_used
, used
);
2171 if (just_try_suggested
)
2173 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2174 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2176 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2179 /* If all registers are excluded, we can't do anything. */
2180 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2182 /* If at least one would be suitable, test each hard reg. */
2184 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2186 #ifdef REG_ALLOC_ORDER
2187 int regno
= reg_alloc_order
[i
];
2191 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2192 && HARD_REGNO_MODE_OK (regno
, mode
)
2193 && (qty
[qtyno
].n_calls_crossed
== 0
2194 || accept_call_clobbered
2195 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2198 register int size1
= HARD_REGNO_NREGS (regno
, mode
);
2199 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2202 /* Mark that this register is in use between its birth and death
2204 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2207 #ifndef REG_ALLOC_ORDER
2208 /* Skip starting points we know will lose. */
2215 /* If we are just trying suggested register, we have just tried copy-
2216 suggested registers, and there are arithmetic-suggested registers,
2219 /* If it would be profitable to allocate a call-clobbered register
2220 and save and restore it around calls, do that. */
2221 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2222 && qty_phys_num_sugg
[qtyno
] != 0)
2224 /* Don't try the copy-suggested regs again. */
2225 qty_phys_num_copy_sugg
[qtyno
] = 0;
2226 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2227 born_index
, dead_index
);
2230 /* We need not check to see if the current function has nonlocal
2231 labels because we don't put any pseudos that are live over calls in
2232 registers in that case. */
2234 if (! accept_call_clobbered
2235 && flag_caller_saves
2236 && ! just_try_suggested
2237 && qty
[qtyno
].n_calls_crossed
!= 0
2238 && CALLER_SAVE_PROFITABLE (qty
[qtyno
].n_refs
,
2239 qty
[qtyno
].n_calls_crossed
))
2241 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2243 caller_save_needed
= 1;
2249 /* Mark that REGNO with machine-mode MODE is live starting from the current
2250 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2254 mark_life (regno
, mode
, life
)
2256 enum machine_mode mode
;
2259 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2262 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2265 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2268 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2269 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2270 to insn number DEATH (exclusive). */
2273 post_mark_life (regno
, mode
, life
, birth
, death
)
2275 enum machine_mode mode
;
2276 int life
, birth
, death
;
2278 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2280 /* Declare it register if it's a scalar. */
2283 HARD_REG_SET this_reg
;
2285 CLEAR_HARD_REG_SET (this_reg
);
2287 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2290 while (birth
< death
)
2292 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2296 while (birth
< death
)
2298 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2303 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2304 is the register being clobbered, and R1 is a register being used in
2305 the equivalent expression.
2307 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2308 in which it is used, return 1.
2310 Otherwise, return 0. */
2313 no_conflict_p (insn
, r0
, r1
)
2314 rtx insn
, r0 ATTRIBUTE_UNUSED
, r1
;
2317 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2320 /* If R1 is a hard register, return 0 since we handle this case
2321 when we scan the insns that actually use it. */
2324 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2325 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2326 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2329 last
= XEXP (note
, 0);
2331 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2334 if (find_reg_note (p
, REG_DEAD
, r1
))
2337 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2338 some earlier optimization pass has inserted instructions into
2339 the sequence, and it is not safe to perform this optimization.
2340 Note that emit_no_conflict_block always ensures that this is
2341 true when these sequences are created. */
2342 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2349 /* Return the number of alternatives for which the constraint string P
2350 indicates that the operand must be equal to operand 0 and that no register
2359 int reg_allowed
= 0;
2360 int num_matching_alts
= 0;
2365 case '=': case '+': case '?':
2366 case '#': case '&': case '!':
2368 case '1': case '2': case '3': case '4': case '5':
2369 case '6': case '7': case '8': case '9':
2370 case 'm': case '<': case '>': case 'V': case 'o':
2371 case 'E': case 'F': case 'G': case 'H':
2372 case 's': case 'i': case 'n':
2373 case 'I': case 'J': case 'K': case 'L':
2374 case 'M': case 'N': case 'O': case 'P':
2376 /* These don't say anything we care about. */
2380 if (found_zero
&& ! reg_allowed
)
2381 num_matching_alts
++;
2383 found_zero
= reg_allowed
= 0;
2391 if (REG_CLASS_FROM_LETTER (c
) == NO_REGS
)
2400 if (found_zero
&& ! reg_allowed
)
2401 num_matching_alts
++;
2403 return num_matching_alts
;
2407 dump_local_alloc (file
)
2411 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2412 if (reg_renumber
[i
] != -1)
2413 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);