1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Allocation of hard register numbers to pseudo registers is done in
22 two passes. In this pass we consider only regs that are born and
23 die once within one basic block. We do this one basic block at a
24 time. Then the next pass allocates the registers that remain.
25 Two passes are used because this pass uses methods that work only
26 on linear code, but that do a better job than the general methods
27 used in global_alloc, and more quickly too.
29 The assignments made are recorded in the vector reg_renumber
30 whose space is allocated here. The rtl code itself is not altered.
32 We assign each instruction in the basic block a number
33 which is its order from the beginning of the block.
34 Then we can represent the lifetime of a pseudo register with
35 a pair of numbers, and check for conflicts easily.
36 We can record the availability of hard registers with a
37 HARD_REG_SET for each instruction. The HARD_REG_SET
38 contains 0 or 1 for each hard reg.
40 To avoid register shuffling, we tie registers together when one
41 dies by being copied into another, or dies in an instruction that
42 does arithmetic to produce another. The tied registers are
43 allocated as one. Registers with different reg class preferences
44 can never be tied unless the class preferred by one is a subclass
45 of the one preferred by the other.
47 Tying is represented with "quantity numbers".
48 A non-tied register is given a new quantity number.
49 Tied registers have the same quantity number.
51 We have provision to exempt registers, even when they are contained
52 within the block, that can be tied to others that are not contained in it.
53 This is so that global_alloc could process them both and tie them then.
54 But this is currently disabled since tying in global_alloc is not
61 #include "basic-block.h"
63 #include "hard-reg-set.h"
64 #include "insn-config.h"
68 /* Next quantity number available for allocation. */
72 /* In all the following vectors indexed by quantity number. */
74 /* Element Q is the hard reg number chosen for quantity Q,
75 or -1 if none was found. */
77 static short *qty_phys_reg
;
79 /* We maintain two hard register sets that indicate suggested hard registers
80 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
81 that are tied to the quantity by a simple copy. The second contains all
82 hard registers that are tied to the quantity via an arithmetic operation.
84 The former register set is given priority for allocation. This tends to
85 eliminate copy insns. */
87 /* Element Q is a set of hard registers that are suggested for quantity Q by
90 static HARD_REG_SET
*qty_phys_copy_sugg
;
92 /* Element Q is a set of hard registers that are suggested for quantity Q by
95 static HARD_REG_SET
*qty_phys_sugg
;
97 /* Element Q is non-zero if there is a suggested register in
98 qty_phys_copy_sugg. */
100 static char *qty_phys_has_copy_sugg
;
102 /* Element Q is non-zero if there is a suggested register in qty_phys_sugg. */
104 static char *qty_phys_has_sugg
;
106 /* Element Q is the number of refs to quantity Q. */
108 static short *qty_n_refs
;
110 /* Element Q is a reg class contained in (smaller than) the
111 preferred classes of all the pseudo regs that are tied in quantity Q.
112 This is the preferred class for allocating that quantity. */
114 static enum reg_class
*qty_min_class
;
116 /* Insn number (counting from head of basic block)
117 where quantity Q was born. -1 if birth has not been recorded. */
119 static int *qty_birth
;
121 /* Insn number (counting from head of basic block)
122 where quantity Q died. Due to the way tying is done,
123 and the fact that we consider in this pass only regs that die but once,
124 a quantity can die only once. Each quantity's life span
125 is a set of consecutive insns. -1 if death has not been recorded. */
127 static int *qty_death
;
129 /* Number of words needed to hold the data in quantity Q.
130 This depends on its machine mode. It is used for these purposes:
131 1. It is used in computing the relative importances of qtys,
132 which determines the order in which we look for regs for them.
133 2. It is used in rules that prevent tying several registers of
134 different sizes in a way that is geometrically impossible
135 (see combine_regs). */
137 static int *qty_size
;
139 /* This holds the mode of the registers that are tied to qty Q,
140 or VOIDmode if registers with differing modes are tied together. */
142 static enum machine_mode
*qty_mode
;
144 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
146 static int *qty_n_calls_crossed
;
148 /* Register class within which we allocate qty Q if we can't get
149 its preferred class. */
151 static enum reg_class
*qty_alternate_class
;
153 /* Element Q is the SCRATCH expression for which this quantity is being
154 allocated or 0 if this quantity is allocating registers. */
156 static rtx
*qty_scratch_rtx
;
158 /* Element Q is the register number of one pseudo register whose
159 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
160 register should be the head of the chain maintained in reg_next_in_qty. */
162 static short *qty_first_reg
;
164 /* If (REG N) has been assigned a quantity number, is a register number
165 of another register assigned the same quantity number, or -1 for the
166 end of the chain. qty_first_reg point to the head of this chain. */
168 static short *reg_next_in_qty
;
170 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
172 of -1 if this register cannot be allocated by local-alloc,
173 or -2 if not known yet.
175 Note that if we see a use or death of pseudo register N with
176 reg_qty[N] == -2, register N must be local to the current block. If
177 it were used in more than one block, we would have reg_qty[N] == -1.
178 This relies on the fact that if reg_basic_block[N] is >= 0, register N
179 will not appear in any other block. We save a considerable number of
180 tests by exploiting this.
182 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
187 /* The offset (in words) of register N within its quantity.
188 This can be nonzero if register N is SImode, and has been tied
189 to a subreg of a DImode register. */
191 static char *reg_offset
;
193 /* Vector of substitutions of register numbers,
194 used to map pseudo regs into hardware regs.
195 This is set up as a result of register allocation.
196 Element N is the hard reg assigned to pseudo reg N,
197 or is -1 if no hard reg was assigned.
198 If N is a hard reg number, element N is N. */
202 /* Set of hard registers live at the current point in the scan
203 of the instructions in a basic block. */
205 static HARD_REG_SET regs_live
;
207 /* Each set of hard registers indicates registers live at a particular
208 point in the basic block. For N even, regs_live_at[N] says which
209 hard registers are needed *after* insn N/2 (i.e., they may not
210 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
212 If an object is to conflict with the inputs of insn J but not the
213 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
214 if it is to conflict with the outputs of insn J but not the inputs of
215 insn J + 1, it is said to die at index J*2 + 1. */
217 static HARD_REG_SET
*regs_live_at
;
219 /* Communicate local vars `insn_number' and `insn'
220 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
221 static int this_insn_number
;
222 static rtx this_insn
;
224 static void block_alloc ();
225 static void update_equiv_regs ();
226 static int no_conflict_p ();
227 static int combine_regs ();
228 static void wipe_dead_reg ();
229 static int find_free_reg ();
230 static void reg_is_born ();
231 static void reg_is_set ();
232 static void mark_life ();
233 static void post_mark_life ();
234 static int qty_compare ();
235 static int qty_compare_1 ();
236 static int reg_meets_class_p ();
237 static void update_qty_class ();
238 static int requires_inout_p ();
240 /* Allocate a new quantity (new within current basic block)
241 for register number REGNO which is born at index BIRTH
242 within the block. MODE and SIZE are info on reg REGNO. */
245 alloc_qty (regno
, mode
, size
, birth
)
247 enum machine_mode mode
;
250 register int qty
= next_qty
++;
252 reg_qty
[regno
] = qty
;
253 reg_offset
[regno
] = 0;
254 reg_next_in_qty
[regno
] = -1;
256 qty_first_reg
[qty
] = regno
;
257 qty_size
[qty
] = size
;
258 qty_mode
[qty
] = mode
;
259 qty_birth
[qty
] = birth
;
260 qty_n_calls_crossed
[qty
] = reg_n_calls_crossed
[regno
];
261 qty_min_class
[qty
] = reg_preferred_class (regno
);
262 qty_alternate_class
[qty
] = reg_alternate_class (regno
);
263 qty_n_refs
[qty
] = reg_n_refs
[regno
];
266 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
267 used as operand N in INSN. We assume here that the SCRATCH is used in
271 alloc_qty_for_scratch (scratch
, n
, insn
, insn_code_num
, insn_number
)
275 int insn_code_num
, insn_number
;
278 enum reg_class
class;
282 #ifdef REGISTER_CONSTRAINTS
283 /* If we haven't yet computed which alternative will be used, do so now.
284 Then set P to the constraints for that alternative. */
285 if (which_alternative
== -1)
286 if (! constrain_operands (insn_code_num
, 0))
289 for (p
= insn_operand_constraint
[insn_code_num
][n
], i
= 0;
290 *p
&& i
< which_alternative
; p
++)
294 /* Compute the class required for this SCRATCH. If we don't need a
295 register, the class will remain NO_REGS. If we guessed the alternative
296 number incorrectly, reload will fix things up for us. */
299 while ((c
= *p
++) != '\0' && c
!= ',')
302 case '=': case '+': case '?':
303 case '#': case '&': case '!':
305 case '0': case '1': case '2': case '3': case '4':
306 case 'm': case '<': case '>': case 'V': case 'o':
307 case 'E': case 'F': case 'G': case 'H':
308 case 's': case 'i': case 'n':
309 case 'I': case 'J': case 'K': case 'L':
310 case 'M': case 'N': case 'O': case 'P':
311 #ifdef EXTRA_CONSTRAINT
312 case 'Q': case 'R': case 'S': case 'T': case 'U':
315 /* These don't say anything we care about. */
319 /* We don't need to allocate this SCRATCH. */
323 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
328 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER (c
)];
332 /* If CLASS has only one register, don't allocate the SCRATCH here since
333 it will prevent that register from being used as a spill register.
334 reload will do the allocation. */
336 if (class == NO_REGS
|| reg_class_size
[(int) class] == 1)
339 #else /* REGISTER_CONSTRAINTS */
341 class = GENERAL_REGS
;
347 qty_first_reg
[qty
] = -1;
348 qty_scratch_rtx
[qty
] = scratch
;
349 qty_size
[qty
] = GET_MODE_SIZE (GET_MODE (scratch
));
350 qty_mode
[qty
] = GET_MODE (scratch
);
351 qty_birth
[qty
] = 2 * insn_number
- 1;
352 qty_death
[qty
] = 2 * insn_number
+ 1;
353 qty_n_calls_crossed
[qty
] = 0;
354 qty_min_class
[qty
] = class;
355 qty_alternate_class
[qty
] = NO_REGS
;
359 /* Main entry point of this file. */
367 /* Leaf functions and non-leaf functions have different needs.
368 If defined, let the machine say what kind of ordering we
370 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
371 ORDER_REGS_FOR_LOCAL_ALLOC
;
374 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
376 update_equiv_regs ();
378 /* This sets the maximum number of quantities we can have. Quantity
379 numbers start at zero and we can have one for each pseudo plus the
380 number of SCRATCHes in the largest block, in the worst case. */
381 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
) + max_scratch
;
383 /* Allocate vectors of temporary data.
384 See the declarations of these variables, above,
385 for what they mean. */
387 qty_phys_reg
= (short *) alloca (max_qty
* sizeof (short));
388 qty_phys_copy_sugg
= (HARD_REG_SET
*) alloca (max_qty
* sizeof (HARD_REG_SET
));
389 qty_phys_has_copy_sugg
= (char *) alloca (max_qty
* sizeof (char));
390 qty_phys_sugg
= (HARD_REG_SET
*) alloca (max_qty
* sizeof (HARD_REG_SET
));
391 qty_phys_has_sugg
= (char *) alloca (max_qty
* sizeof (char));
392 qty_birth
= (int *) alloca (max_qty
* sizeof (int));
393 qty_death
= (int *) alloca (max_qty
* sizeof (int));
394 qty_scratch_rtx
= (rtx
*) alloca (max_qty
* sizeof (rtx
));
395 qty_first_reg
= (short *) alloca (max_qty
* sizeof (short));
396 qty_size
= (int *) alloca (max_qty
* sizeof (int));
397 qty_mode
= (enum machine_mode
*) alloca (max_qty
* sizeof (enum machine_mode
));
398 qty_n_calls_crossed
= (int *) alloca (max_qty
* sizeof (int));
399 qty_min_class
= (enum reg_class
*) alloca (max_qty
* sizeof (enum reg_class
));
400 qty_alternate_class
= (enum reg_class
*) alloca (max_qty
* sizeof (enum reg_class
));
401 qty_n_refs
= (short *) alloca (max_qty
* sizeof (short));
403 reg_qty
= (int *) alloca (max_regno
* sizeof (int));
404 reg_offset
= (char *) alloca (max_regno
* sizeof (char));
405 reg_next_in_qty
= (short *) alloca (max_regno
* sizeof (short));
407 reg_renumber
= (short *) oballoc (max_regno
* sizeof (short));
408 for (i
= 0; i
< max_regno
; i
++)
409 reg_renumber
[i
] = -1;
411 /* Determine which pseudo-registers can be allocated by local-alloc.
412 In general, these are the registers used only in a single block and
413 which only die once. However, if a register's preferred class has only
414 one entry, don't allocate this register here unless it is preferred
415 or nothing since retry_global_alloc won't be able to move it to
416 GENERAL_REGS if a reload register of this class is needed.
418 We need not be concerned with which block actually uses the register
419 since we will never see it outside that block. */
421 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
423 if (reg_basic_block
[i
] >= 0 && reg_n_deaths
[i
] == 1
424 && (reg_alternate_class (i
) == NO_REGS
425 || reg_class_size
[(int) reg_preferred_class (i
)] > 1))
431 /* Force loop below to initialize entire quantity array. */
434 /* Allocate each block's local registers, block by block. */
436 for (b
= 0; b
< n_basic_blocks
; b
++)
438 /* NEXT_QTY indicates which elements of the `qty_...'
439 vectors might need to be initialized because they were used
440 for the previous block; it is set to the entire array before
441 block 0. Initialize those, with explicit loop if there are few,
442 else with bzero and bcopy. Do not initialize vectors that are
443 explicit set by `alloc_qty'. */
447 for (i
= 0; i
< next_qty
; i
++)
449 qty_scratch_rtx
[i
] = 0;
450 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
451 qty_phys_has_copy_sugg
[i
] = 0;
452 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
453 qty_phys_has_sugg
[i
] = 0;
458 #define CLEAR(vector) \
459 bzero ((vector), (sizeof (*(vector))) * next_qty);
461 CLEAR (qty_scratch_rtx
);
462 CLEAR (qty_phys_copy_sugg
);
463 CLEAR (qty_phys_has_copy_sugg
);
464 CLEAR (qty_phys_sugg
);
465 CLEAR (qty_phys_has_sugg
);
477 /* Depth of loops we are in while in update_equiv_regs. */
478 static int loop_depth
;
480 /* Used for communication between the following two functions: contains
481 a MEM that we wish to ensure remains unchanged. */
482 static rtx equiv_mem
;
484 /* Set nonzero if EQUIV_MEM is modified. */
485 static int equiv_mem_modified
;
487 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
488 Called via note_stores. */
491 validate_equiv_mem_from_store (dest
, set
)
495 if ((GET_CODE (dest
) == REG
496 && reg_overlap_mentioned_p (dest
, equiv_mem
))
497 || (GET_CODE (dest
) == MEM
498 && true_dependence (dest
, equiv_mem
)))
499 equiv_mem_modified
= 1;
502 /* Verify that no store between START and the death of REG invalidates
503 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
504 by storing into an overlapping memory location, or with a non-const
507 Return 1 if MEMREF remains valid. */
510 validate_equiv_mem (start
, reg
, memref
)
519 equiv_mem_modified
= 0;
521 /* If the memory reference has side effects or is volatile, it isn't a
522 valid equivalence. */
523 if (side_effects_p (memref
))
526 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
528 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
531 if (find_reg_note (insn
, REG_DEAD
, reg
))
534 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
535 && ! CONST_CALL_P (insn
))
538 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
);
540 /* If a register mentioned in MEMREF is modified via an
541 auto-increment, we lose the equivalence. Do the same if one
542 dies; although we could extend the life, it doesn't seem worth
545 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
546 if ((REG_NOTE_KIND (note
) == REG_INC
547 || REG_NOTE_KIND (note
) == REG_DEAD
)
548 && GET_CODE (XEXP (note
, 0)) == REG
549 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
556 /* TRUE if X references a memory location that would be affected by a store
560 memref_referenced_p (memref
, x
)
566 enum rtx_code code
= GET_CODE (x
);
583 if (true_dependence (memref
, x
))
588 /* If we are setting a MEM, it doesn't count (its address does), but any
589 other SET_DEST that has a MEM in it is referencing the MEM. */
590 if (GET_CODE (SET_DEST (x
)) == MEM
)
592 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
595 else if (memref_referenced_p (memref
, SET_DEST (x
)))
598 return memref_referenced_p (memref
, SET_SRC (x
));
601 fmt
= GET_RTX_FORMAT (code
);
602 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
606 if (memref_referenced_p (memref
, XEXP (x
, i
)))
610 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
611 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
619 /* TRUE if some insn in the range (START, END] references a memory location
620 that would be affected by a store to MEMREF. */
623 memref_used_between_p (memref
, start
, end
)
630 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
631 insn
= NEXT_INSN (insn
))
632 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
633 && memref_referenced_p (memref
, PATTERN (insn
)))
639 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
642 Search forward to see if SRC dies before either it or DEST is modified,
643 but don't scan past the end of a basic block. If so, we can replace SRC
644 with DEST and let SRC die in INSN.
646 This will reduce the number of registers live in that range and may enable
647 DEST to be tied to SRC, thus often saving one register in addition to a
648 register-register copy. */
651 optimize_reg_copy_1 (insn
, dest
, src
)
659 int sregno
= REGNO (src
);
660 int dregno
= REGNO (dest
);
663 #ifdef SMALL_REGISTER_CLASSES
664 /* We don't want to mess with hard regs if register classes are small. */
665 || sregno
< FIRST_PSEUDO_REGISTER
|| dregno
< FIRST_PSEUDO_REGISTER
667 /* We don't see all updates to SP if they are in an auto-inc memory
668 reference, so we must disallow this optimization on them. */
669 || sregno
== STACK_POINTER_REGNUM
|| dregno
== STACK_POINTER_REGNUM
)
672 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
674 if (GET_CODE (p
) == CODE_LABEL
|| GET_CODE (p
) == JUMP_INSN
675 || (GET_CODE (p
) == NOTE
676 && (NOTE_LINE_NUMBER (p
) == NOTE_INSN_LOOP_BEG
677 || NOTE_LINE_NUMBER (p
) == NOTE_INSN_LOOP_END
)))
680 if (GET_RTX_CLASS (GET_CODE (p
)) != 'i')
683 if (reg_set_p (src
, p
) || reg_set_p (dest
, p
)
684 /* Don't change a USE of a register. */
685 || (GET_CODE (PATTERN (p
)) == USE
686 && reg_overlap_mentioned_p (src
, XEXP (PATTERN (p
), 0))))
689 /* See if all of SRC dies in P. This test is slightly more
690 conservative than it needs to be. */
691 if ((note
= find_regno_note (p
, REG_DEAD
, sregno
)) != 0
692 && GET_MODE (XEXP (note
, 0)) == GET_MODE (src
))
700 /* If P is a CALL_INSN, SRC crosses one more call, since it
701 used to die there. */
703 if (GET_CODE (p
) == CALL_INSN
)
706 /* We can do the optimization. Scan forward from INSN again,
707 replacing regs as we go. Set FAILED if a replacement can't
708 be done. In that case, we can't move the death note for SRC.
709 This should be rare. */
711 /* Set to stop at next insn. */
712 for (q
= next_real_insn (insn
);
713 q
!= next_real_insn (p
);
714 q
= next_real_insn (q
))
716 if (reg_overlap_mentioned_p (src
, PATTERN (q
)))
718 /* If SRC is a hard register, we might miss some
719 overlapping registers with validate_replace_rtx,
720 so we would have to undo it. We can't if DEST is
721 present in the insn, so fail in that combination
723 if (sregno
< FIRST_PSEUDO_REGISTER
724 && reg_mentioned_p (dest
, PATTERN (q
)))
727 /* Replace all uses and make sure that the register
728 isn't still present. */
729 else if (validate_replace_rtx (src
, dest
, q
)
730 && (sregno
>= FIRST_PSEUDO_REGISTER
731 || ! reg_overlap_mentioned_p (src
,
734 /* We assume that a register is used exactly once per
735 insn in the updates below. If this is not correct,
736 no great harm is done. */
737 if (sregno
>= FIRST_PSEUDO_REGISTER
)
738 reg_n_refs
[sregno
] -= loop_depth
;
739 if (dregno
>= FIRST_PSEUDO_REGISTER
)
740 reg_n_refs
[dregno
] += loop_depth
;
744 validate_replace_rtx (dest
, src
, q
);
749 /* Count the insns and CALL_INSNs passed. If we passed the
750 death note of DEST, show increased live length. */
755 if (GET_CODE (q
) == CALL_INSN
)
762 /* If DEST dies here, remove the death note and save it for
763 later. Make sure ALL of DEST dies here; again, this is
764 overly conservative. */
766 && (dest_death
= find_regno_note (q
, REG_DEAD
, dregno
)) != 0
767 && GET_MODE (XEXP (dest_death
, 0)) == GET_MODE (dest
))
768 remove_note (q
, dest_death
);
773 if (sregno
>= FIRST_PSEUDO_REGISTER
)
775 reg_live_length
[sregno
] -= length
;
776 reg_n_calls_crossed
[sregno
] -= n_calls
;
779 if (dregno
>= FIRST_PSEUDO_REGISTER
)
781 reg_live_length
[dregno
] += d_length
;
782 reg_n_calls_crossed
[dregno
] += d_n_calls
;
785 /* Move death note of SRC from P to INSN. */
786 remove_note (p
, note
);
787 XEXP (note
, 1) = REG_NOTES (insn
);
788 REG_NOTES (insn
) = note
;
791 /* Put death note of DEST on P if we saw it die. */
794 XEXP (dest_death
, 1) = REG_NOTES (p
);
795 REG_NOTES (p
) = dest_death
;
801 /* If SRC is a hard register which is set or killed in some other
802 way, we can't do this optimization. */
803 else if (sregno
< FIRST_PSEUDO_REGISTER
804 && dead_or_set_p (p
, src
))
809 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
810 a sequence of insns that modify DEST followed by an insn that sets
811 SRC to DEST in which DEST dies, with no prior modification of DEST.
812 (There is no need to check if the insns in between actually modify
813 DEST. We should not have cases where DEST is not modified, but
814 the optimization is safe if no such modification is detected.)
815 In that case, we can replace all uses of DEST, starting with INSN and
816 ending with the set of SRC to DEST, with SRC. We do not do this
817 optimization if a CALL_INSN is crossed unless SRC already crosses a
820 It is assumed that DEST and SRC are pseudos; it is too complicated to do
821 this for hard registers since the substitutions we may make might fail. */
824 optimize_reg_copy_2 (insn
, dest
, src
)
831 int sregno
= REGNO (src
);
832 int dregno
= REGNO (dest
);
834 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
836 if (GET_CODE (p
) == CODE_LABEL
|| GET_CODE (p
) == JUMP_INSN
837 || (GET_CODE (p
) == NOTE
838 && (NOTE_LINE_NUMBER (p
) == NOTE_INSN_LOOP_BEG
839 || NOTE_LINE_NUMBER (p
) == NOTE_INSN_LOOP_END
)))
842 if (GET_RTX_CLASS (GET_CODE (p
)) != 'i')
845 set
= single_set (p
);
846 if (set
&& SET_SRC (set
) == dest
&& SET_DEST (set
) == src
847 && find_reg_note (p
, REG_DEAD
, dest
))
849 /* We can do the optimization. Scan forward from INSN again,
850 replacing regs as we go. */
852 /* Set to stop at next insn. */
853 for (q
= insn
; q
!= NEXT_INSN (p
); q
= NEXT_INSN (q
))
854 if (GET_RTX_CLASS (GET_CODE (q
)) == 'i')
856 if (reg_mentioned_p (dest
, PATTERN (q
)))
858 PATTERN (q
) = replace_rtx (PATTERN (q
), dest
, src
);
860 /* We assume that a register is used exactly once per
861 insn in the updates below. If this is not correct,
862 no great harm is done. */
863 reg_n_refs
[dregno
] -= loop_depth
;
864 reg_n_refs
[sregno
] += loop_depth
;
868 if (GET_CODE (q
) == CALL_INSN
)
870 reg_n_calls_crossed
[dregno
]--;
871 reg_n_calls_crossed
[sregno
]++;
875 remove_note (p
, find_reg_note (p
, REG_DEAD
, dest
));
876 reg_n_deaths
[dregno
]--;
877 remove_note (insn
, find_reg_note (insn
, REG_DEAD
, src
));
878 reg_n_deaths
[sregno
]--;
882 if (reg_set_p (src
, p
)
883 || (GET_CODE (p
) == CALL_INSN
&& reg_n_calls_crossed
[sregno
] == 0))
888 /* Find registers that are equivalent to a single value throughout the
889 compilation (either because they can be referenced in memory or are set once
890 from a single constant). Lower their priority for a register.
892 If such a register is only referenced once, try substituting its value
893 into the using insn. If it succeeds, we can eliminate the register
899 rtx
*reg_equiv_init_insn
= (rtx
*) alloca (max_regno
* sizeof (rtx
*));
900 rtx
*reg_equiv_replacement
= (rtx
*) alloca (max_regno
* sizeof (rtx
*));
903 bzero (reg_equiv_init_insn
, max_regno
* sizeof (rtx
*));
904 bzero (reg_equiv_replacement
, max_regno
* sizeof (rtx
*));
906 init_alias_analysis ();
910 /* Scan the insns and find which registers have equivalences. Do this
911 in a separate scan of the insns because (due to -fcse-follow-jumps)
912 a register can be set below its use. */
913 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
916 rtx set
= single_set (insn
);
920 if (GET_CODE (insn
) == NOTE
)
922 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
924 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
928 /* If this insn contains more (or less) than a single SET, ignore it. */
932 dest
= SET_DEST (set
);
934 /* If this sets a MEM to the contents of a REG that is only used
935 in a single basic block, see if the register is always equivalent
936 to that memory location and if moving the store from INSN to the
937 insn that set REG is safe. If so, put a REG_EQUIV note on the
938 initializing insn. */
940 if (GET_CODE (dest
) == MEM
&& GET_CODE (SET_SRC (set
)) == REG
941 && (regno
= REGNO (SET_SRC (set
))) >= FIRST_PSEUDO_REGISTER
942 && reg_basic_block
[regno
] >= 0
943 && reg_equiv_init_insn
[regno
] != 0
944 && validate_equiv_mem (reg_equiv_init_insn
[regno
], SET_SRC (set
),
946 && ! memref_used_between_p (SET_DEST (set
),
947 reg_equiv_init_insn
[regno
], insn
))
948 REG_NOTES (reg_equiv_init_insn
[regno
])
949 = gen_rtx (EXPR_LIST
, REG_EQUIV
, dest
,
950 REG_NOTES (reg_equiv_init_insn
[regno
]));
952 /* If this is a register-register copy where SRC is not dead, see if we
954 if (flag_expensive_optimizations
&& GET_CODE (dest
) == REG
955 && GET_CODE (SET_SRC (set
)) == REG
956 && ! find_reg_note (insn
, REG_DEAD
, SET_SRC (set
)))
957 optimize_reg_copy_1 (insn
, dest
, SET_SRC (set
));
959 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
960 else if (flag_expensive_optimizations
&& GET_CODE (dest
) == REG
961 && REGNO (dest
) >= FIRST_PSEUDO_REGISTER
962 && GET_CODE (SET_SRC (set
)) == REG
963 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
964 && find_reg_note (insn
, REG_DEAD
, SET_SRC (set
)))
965 optimize_reg_copy_2 (insn
, dest
, SET_SRC (set
));
967 /* Otherwise, we only handle the case of a pseudo register being set
969 if (GET_CODE (dest
) != REG
970 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
971 || reg_n_sets
[regno
] != 1)
974 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
976 /* Record this insn as initializing this register. */
977 reg_equiv_init_insn
[regno
] = insn
;
979 /* If this register is known to be equal to a constant, record that
980 it is always equivalent to the constant. */
981 if (note
&& CONSTANT_P (XEXP (note
, 0)))
982 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
984 /* If this insn introduces a "constant" register, decrease the priority
985 of that register. Record this insn if the register is only used once
986 more and the equivalence value is the same as our source.
988 The latter condition is checked for two reasons: First, it is an
989 indication that it may be more efficient to actually emit the insn
990 as written (if no registers are available, reload will substitute
991 the equivalence). Secondly, it avoids problems with any registers
992 dying in this insn whose death notes would be missed.
994 If we don't have a REG_EQUIV note, see if this insn is loading
995 a register used only in one basic block from a MEM. If so, and the
996 MEM remains unchanged for the life of the register, add a REG_EQUIV
999 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
1001 if (note
== 0 && reg_basic_block
[regno
] >= 0
1002 && GET_CODE (SET_SRC (set
)) == MEM
1003 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
1004 REG_NOTES (insn
) = note
= gen_rtx (EXPR_LIST
, REG_EQUIV
, SET_SRC (set
),
1007 /* Don't mess with things live during setjmp. */
1008 if (note
&& reg_live_length
[regno
] >= 0)
1010 int regno
= REGNO (dest
);
1012 /* Note that the statement below does not affect the priority
1014 reg_live_length
[regno
] *= 2;
1016 /* If the register is referenced exactly twice, meaning it is set
1017 once and used once, indicate that the reference may be replaced
1018 by the equivalence we computed above. If the register is only
1019 used in one basic block, this can't succeed or combine would
1022 It would be nice to use "loop_depth * 2" in the compare
1023 below. Unfortunately, LOOP_DEPTH need not be constant within
1024 a basic block so this would be too complicated.
1026 This case normally occurs when a parameter is read from memory
1027 and then used exactly once, not in a loop. */
1029 if (reg_n_refs
[regno
] == 2
1030 && reg_basic_block
[regno
] < 0
1031 && rtx_equal_p (XEXP (note
, 0), SET_SRC (set
)))
1032 reg_equiv_replacement
[regno
] = SET_SRC (set
);
1036 /* Now scan all regs killed in an insn to see if any of them are registers
1037 only used that once. If so, see if we can replace the reference with
1038 the equivalent from. If we can, delete the initializing reference
1039 and this register will go away. */
1040 for (insn
= next_active_insn (get_insns ());
1042 insn
= next_active_insn (insn
))
1046 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1047 if (REG_NOTE_KIND (link
) == REG_DEAD
1048 /* Make sure this insn still refers to the register. */
1049 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
1051 int regno
= REGNO (XEXP (link
, 0));
1053 if (reg_equiv_replacement
[regno
]
1054 && validate_replace_rtx (regno_reg_rtx
[regno
],
1055 reg_equiv_replacement
[regno
], insn
))
1057 rtx equiv_insn
= reg_equiv_init_insn
[regno
];
1059 remove_death (regno
, insn
);
1060 reg_n_refs
[regno
] = 0;
1061 PUT_CODE (equiv_insn
, NOTE
);
1062 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1063 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1069 /* Allocate hard regs to the pseudo regs used only within block number B.
1070 Only the pseudos that die but once can be handled. */
1079 int insn_number
= 0;
1081 int max_uid
= get_max_uid ();
1083 int no_conflict_combined_regno
= -1;
1085 /* Count the instructions in the basic block. */
1087 insn
= basic_block_end
[b
];
1090 if (GET_CODE (insn
) != NOTE
)
1091 if (++insn_count
> max_uid
)
1093 if (insn
== basic_block_head
[b
])
1095 insn
= PREV_INSN (insn
);
1098 /* +2 to leave room for a post_mark_life at the last insn and for
1099 the birth of a CLOBBER in the first insn. */
1100 regs_live_at
= (HARD_REG_SET
*) alloca ((2 * insn_count
+ 2)
1101 * sizeof (HARD_REG_SET
));
1102 bzero (regs_live_at
, (2 * insn_count
+ 2) * sizeof (HARD_REG_SET
));
1104 /* Initialize table of hardware registers currently live. */
1107 regs_live
= *basic_block_live_at_start
[b
];
1109 COPY_HARD_REG_SET (regs_live
, basic_block_live_at_start
[b
]);
1112 /* This loop scans the instructions of the basic block
1113 and assigns quantities to registers.
1114 It computes which registers to tie. */
1116 insn
= basic_block_head
[b
];
1119 register rtx body
= PATTERN (insn
);
1121 if (GET_CODE (insn
) != NOTE
)
1124 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1126 register rtx link
, set
;
1127 register int win
= 0;
1128 register rtx r0
, r1
;
1129 int combined_regno
= -1;
1131 int insn_code_number
= recog_memoized (insn
);
1133 this_insn_number
= insn_number
;
1136 if (insn_code_number
>= 0)
1137 insn_extract (insn
);
1138 which_alternative
= -1;
1140 /* Is this insn suitable for tying two registers?
1141 If so, try doing that.
1142 Suitable insns are those with at least two operands and where
1143 operand 0 is an output that is a register that is not
1146 We can tie operand 0 with some operand that dies in this insn.
1147 First look for operands that are required to be in the same
1148 register as operand 0. If we find such, only try tying that
1149 operand or one that can be put into that operand if the
1150 operation is commutative. If we don't find an operand
1151 that is required to be in the same register as operand 0,
1152 we can tie with any operand.
1154 Subregs in place of regs are also ok.
1156 If tying is done, WIN is set nonzero. */
1158 if (insn_code_number
>= 0
1159 #ifdef REGISTER_CONSTRAINTS
1160 && insn_n_operands
[insn_code_number
] > 1
1161 && insn_operand_constraint
[insn_code_number
][0][0] == '='
1162 && insn_operand_constraint
[insn_code_number
][0][1] != '&'
1164 && GET_CODE (PATTERN (insn
)) == SET
1165 && rtx_equal_p (SET_DEST (PATTERN (insn
)), recog_operand
[0])
1169 #ifdef REGISTER_CONSTRAINTS
1170 int must_match_0
= -1;
1173 for (i
= 1; i
< insn_n_operands
[insn_code_number
]; i
++)
1174 if (requires_inout_p
1175 (insn_operand_constraint
[insn_code_number
][i
]))
1179 r0
= recog_operand
[0];
1180 for (i
= 1; i
< insn_n_operands
[insn_code_number
]; i
++)
1182 #ifdef REGISTER_CONSTRAINTS
1183 /* Skip this operand if we found an operand that
1184 must match operand 0 and this operand isn't it
1185 and can't be made to be it by commutativity. */
1187 if (must_match_0
>= 0 && i
!= must_match_0
1188 && ! (i
== must_match_0
+ 1
1189 && insn_operand_constraint
[insn_code_number
][i
-1][0] == '%')
1190 && ! (i
== must_match_0
- 1
1191 && insn_operand_constraint
[insn_code_number
][i
][0] == '%'))
1195 r1
= recog_operand
[i
];
1197 /* If the operand is an address, find a register in it.
1198 There may be more than one register, but we only try one
1201 #ifdef REGISTER_CONSTRAINTS
1202 insn_operand_constraint
[insn_code_number
][i
][0] == 'p'
1204 insn_operand_address_p
[insn_code_number
][i
]
1207 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1210 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1212 /* We have two priorities for hard register preferences.
1213 If we have a move insn or an insn whose first input
1214 can only be in the same register as the output, give
1215 priority to an equivalence found from that insn. */
1217 = ((SET_DEST (body
) == r0
&& SET_SRC (body
) == r1
)
1218 #ifdef REGISTER_CONSTRAINTS
1219 || (r1
== recog_operand
[i
] && must_match_0
>= 0)
1223 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1224 win
= combine_regs (r1
, r0
, may_save_copy
,
1225 insn_number
, insn
, 0);
1230 /* Recognize an insn sequence with an ultimate result
1231 which can safely overlap one of the inputs.
1232 The sequence begins with a CLOBBER of its result,
1233 and ends with an insn that copies the result to itself
1234 and has a REG_EQUAL note for an equivalent formula.
1235 That note indicates what the inputs are.
1236 The result and the input can overlap if each insn in
1237 the sequence either doesn't mention the input
1238 or has a REG_NO_CONFLICT note to inhibit the conflict.
1240 We do the combining test at the CLOBBER so that the
1241 destination register won't have had a quantity number
1242 assigned, since that would prevent combining. */
1244 if (GET_CODE (PATTERN (insn
)) == CLOBBER
1245 && (r0
= XEXP (PATTERN (insn
), 0),
1246 GET_CODE (r0
) == REG
)
1247 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1248 && GET_CODE (XEXP (link
, 0)) == INSN
1249 && (set
= single_set (XEXP (link
, 0))) != 0
1250 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1251 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1254 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1255 /* Check that we have such a sequence. */
1256 && no_conflict_p (insn
, r0
, r1
))
1257 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1258 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1259 && (r1
= XEXP (XEXP (note
, 0), 0),
1260 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1261 && no_conflict_p (insn
, r0
, r1
))
1262 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1264 /* Here we care if the operation to be computed is
1266 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1267 || GET_CODE (XEXP (note
, 0)) == NE
1268 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1269 && (r1
= XEXP (XEXP (note
, 0), 1),
1270 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1271 && no_conflict_p (insn
, r0
, r1
))
1272 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1274 /* If we did combine something, show the register number
1275 in question so that we know to ignore its death. */
1277 no_conflict_combined_regno
= REGNO (r1
);
1280 /* If registers were just tied, set COMBINED_REGNO
1281 to the number of the register used in this insn
1282 that was tied to the register set in this insn.
1283 This register's qty should not be "killed". */
1287 while (GET_CODE (r1
) == SUBREG
)
1288 r1
= SUBREG_REG (r1
);
1289 combined_regno
= REGNO (r1
);
1292 /* Mark the death of everything that dies in this instruction,
1293 except for anything that was just combined. */
1295 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1296 if (REG_NOTE_KIND (link
) == REG_DEAD
1297 && GET_CODE (XEXP (link
, 0)) == REG
1298 && combined_regno
!= REGNO (XEXP (link
, 0))
1299 && (no_conflict_combined_regno
!= REGNO (XEXP (link
, 0))
1300 || ! find_reg_note (insn
, REG_NO_CONFLICT
, XEXP (link
, 0))))
1301 wipe_dead_reg (XEXP (link
, 0), 0);
1303 /* Allocate qty numbers for all registers local to this block
1304 that are born (set) in this instruction.
1305 A pseudo that already has a qty is not changed. */
1307 note_stores (PATTERN (insn
), reg_is_set
);
1309 /* If anything is set in this insn and then unused, mark it as dying
1310 after this insn, so it will conflict with our outputs. This
1311 can't match with something that combined, and it doesn't matter
1312 if it did. Do this after the calls to reg_is_set since these
1313 die after, not during, the current insn. */
1315 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1316 if (REG_NOTE_KIND (link
) == REG_UNUSED
1317 && GET_CODE (XEXP (link
, 0)) == REG
)
1318 wipe_dead_reg (XEXP (link
, 0), 1);
1320 #ifndef SMALL_REGISTER_CLASSES
1321 /* Allocate quantities for any SCRATCH operands of this insn. We
1322 don't do this for machines with small register classes because
1323 those machines can use registers explicitly mentioned in the
1324 RTL as spill registers and our usage of hard registers
1325 explicitly for SCRATCH operands will conflict. On those machines,
1326 reload will allocate the SCRATCH. */
1328 if (insn_code_number
>= 0)
1329 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1330 if (GET_CODE (recog_operand
[i
]) == SCRATCH
)
1331 alloc_qty_for_scratch (recog_operand
[i
], i
, insn
,
1332 insn_code_number
, insn_number
);
1335 /* If this is an insn that has a REG_RETVAL note pointing at a
1336 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1337 block, so clear any register number that combined within it. */
1338 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1339 && GET_CODE (XEXP (note
, 0)) == INSN
1340 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1341 no_conflict_combined_regno
= -1;
1344 /* Set the registers live after INSN_NUMBER. Note that we never
1345 record the registers live before the block's first insn, since no
1346 pseudos we care about are live before that insn. */
1348 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1349 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1351 if (insn
== basic_block_end
[b
])
1354 insn
= NEXT_INSN (insn
);
1357 /* Now every register that is local to this basic block
1358 should have been given a quantity, or else -1 meaning ignore it.
1359 Every quantity should have a known birth and death.
1361 Order the qtys so we assign them registers in order of
1362 decreasing length of life. Normally call qsort, but if we
1363 have only a very small number of quantities, sort them ourselves. */
1365 qty_order
= (short *) alloca (next_qty
* sizeof (short));
1366 for (i
= 0; i
< next_qty
; i
++)
1369 #define EXCHANGE(I1, I2) \
1370 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1375 /* Make qty_order[2] be the one to allocate last. */
1376 if (qty_compare (0, 1) > 0)
1378 if (qty_compare (1, 2) > 0)
1381 /* ... Fall through ... */
1383 /* Put the best one to allocate in qty_order[0]. */
1384 if (qty_compare (0, 1) > 0)
1387 /* ... Fall through ... */
1391 /* Nothing to do here. */
1395 qsort (qty_order
, next_qty
, sizeof (short), qty_compare_1
);
1398 /* Try to put each quantity in a suggested physical register, if it has one.
1399 This may cause registers to be allocated that otherwise wouldn't be, but
1400 this seems acceptable in local allocation (unlike global allocation). */
1401 for (i
= 0; i
< next_qty
; i
++)
1404 if (qty_phys_has_sugg
[q
] || qty_phys_has_copy_sugg
[q
])
1405 qty_phys_reg
[q
] = find_free_reg (qty_min_class
[q
], qty_mode
[q
], q
,
1406 0, 1, qty_birth
[q
], qty_death
[q
]);
1408 qty_phys_reg
[q
] = -1;
1411 /* Now for each qty that is not a hardware register,
1412 look for a hardware register to put it in.
1413 First try the register class that is cheapest for this qty,
1414 if there is more than one class. */
1416 for (i
= 0; i
< next_qty
; i
++)
1419 if (qty_phys_reg
[q
] < 0)
1421 if (N_REG_CLASSES
> 1)
1423 qty_phys_reg
[q
] = find_free_reg (qty_min_class
[q
],
1424 qty_mode
[q
], q
, 0, 0,
1425 qty_birth
[q
], qty_death
[q
]);
1426 if (qty_phys_reg
[q
] >= 0)
1430 if (qty_alternate_class
[q
] != NO_REGS
)
1431 qty_phys_reg
[q
] = find_free_reg (qty_alternate_class
[q
],
1432 qty_mode
[q
], q
, 0, 0,
1433 qty_birth
[q
], qty_death
[q
]);
1437 /* Now propagate the register assignments
1438 to the pseudo regs belonging to the qtys. */
1440 for (q
= 0; q
< next_qty
; q
++)
1441 if (qty_phys_reg
[q
] >= 0)
1443 for (i
= qty_first_reg
[q
]; i
>= 0; i
= reg_next_in_qty
[i
])
1444 reg_renumber
[i
] = qty_phys_reg
[q
] + reg_offset
[i
];
1445 if (qty_scratch_rtx
[q
])
1447 PUT_CODE (qty_scratch_rtx
[q
], REG
);
1448 REGNO (qty_scratch_rtx
[q
]) = qty_phys_reg
[q
];
1450 for (i
= HARD_REGNO_NREGS (qty_phys_reg
[q
],
1451 GET_MODE (qty_scratch_rtx
[q
])) - 1;
1453 regs_ever_live
[qty_phys_reg
[q
] + i
] = 1;
1455 /* Must clear the USED field, because it will have been set by
1456 copy_rtx_if_shared, but the leaf_register code expects that
1457 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1458 used bit for REGs, but does for SCRATCHes. */
1459 qty_scratch_rtx
[q
]->used
= 0;
1464 /* Compare two quantities' priority for getting real registers.
1465 We give shorter-lived quantities higher priority.
1466 Quantities with more references are also preferred, as are quantities that
1467 require multiple registers. This is the identical prioritization as
1468 done by global-alloc.
1470 We used to give preference to registers with *longer* lives, but using
1471 the same algorithm in both local- and global-alloc can speed up execution
1472 of some programs by as much as a factor of three! */
1475 qty_compare (q1
, q2
)
1478 /* Note that the quotient will never be bigger than
1479 the value of floor_log2 times the maximum number of
1480 times a register can occur in one insn (surely less than 100).
1481 Multiplying this by 10000 can't overflow. */
1483 = (((double) (floor_log2 (qty_n_refs
[q1
]) * qty_n_refs
[q1
])
1484 / ((qty_death
[q1
] - qty_birth
[q1
]) * qty_size
[q1
]))
1487 = (((double) (floor_log2 (qty_n_refs
[q2
]) * qty_n_refs
[q2
])
1488 / ((qty_death
[q2
] - qty_birth
[q2
]) * qty_size
[q2
]))
1494 qty_compare_1 (q1
, q2
)
1499 /* Note that the quotient will never be bigger than
1500 the value of floor_log2 times the maximum number of
1501 times a register can occur in one insn (surely less than 100).
1502 Multiplying this by 10000 can't overflow. */
1504 = (((double) (floor_log2 (qty_n_refs
[*q1
]) * qty_n_refs
[*q1
])
1505 / ((qty_death
[*q1
] - qty_birth
[*q1
]) * qty_size
[*q1
]))
1508 = (((double) (floor_log2 (qty_n_refs
[*q2
]) * qty_n_refs
[*q2
])
1509 / ((qty_death
[*q2
] - qty_birth
[*q2
]) * qty_size
[*q2
]))
1513 if (tem
!= 0) return tem
;
1514 /* If qtys are equally good, sort by qty number,
1515 so that the results of qsort leave nothing to chance. */
1519 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1520 Returns 1 if have done so, or 0 if cannot.
1522 Combining registers means marking them as having the same quantity
1523 and adjusting the offsets within the quantity if either of
1526 We don't actually combine a hard reg with a pseudo; instead
1527 we just record the hard reg as the suggestion for the pseudo's quantity.
1528 If we really combined them, we could lose if the pseudo lives
1529 across an insn that clobbers the hard reg (eg, movstr).
1531 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1532 there is no REG_DEAD note on INSN. This occurs during the processing
1533 of REG_NO_CONFLICT blocks.
1535 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1536 SETREG or if the input and output must share a register.
1537 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1539 There are elaborate checks for the validity of combining. */
1543 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1544 rtx usedreg
, setreg
;
1550 register int ureg
, sreg
;
1551 register int offset
= 0;
1555 /* Determine the numbers and sizes of registers being used. If a subreg
1556 is present that does not change the entire register, don't consider
1557 this a copy insn. */
1559 while (GET_CODE (usedreg
) == SUBREG
)
1561 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg
))) > UNITS_PER_WORD
)
1563 offset
+= SUBREG_WORD (usedreg
);
1564 usedreg
= SUBREG_REG (usedreg
);
1566 if (GET_CODE (usedreg
) != REG
)
1568 ureg
= REGNO (usedreg
);
1569 usize
= REG_SIZE (usedreg
);
1571 while (GET_CODE (setreg
) == SUBREG
)
1573 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg
))) > UNITS_PER_WORD
)
1575 offset
-= SUBREG_WORD (setreg
);
1576 setreg
= SUBREG_REG (setreg
);
1578 if (GET_CODE (setreg
) != REG
)
1580 sreg
= REGNO (setreg
);
1581 ssize
= REG_SIZE (setreg
);
1583 /* If UREG is a pseudo-register that hasn't already been assigned a
1584 quantity number, it means that it is not local to this block or dies
1585 more than once. In either event, we can't do anything with it. */
1586 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1587 /* Do not combine registers unless one fits within the other. */
1588 || (offset
> 0 && usize
+ offset
> ssize
)
1589 || (offset
< 0 && usize
+ offset
< ssize
)
1590 /* Do not combine with a smaller already-assigned object
1591 if that smaller object is already combined with something bigger. */
1592 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1593 && usize
< qty_size
[reg_qty
[ureg
]])
1594 /* Can't combine if SREG is not a register we can allocate. */
1595 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1596 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1597 These have already been taken care of. This probably wouldn't
1598 combine anyway, but don't take any chances. */
1599 || (ureg
>= FIRST_PSEUDO_REGISTER
1600 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1601 /* Don't tie something to itself. In most cases it would make no
1602 difference, but it would screw up if the reg being tied to itself
1603 also dies in this insn. */
1605 /* Don't try to connect two different hardware registers. */
1606 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1607 /* Don't connect two different machine modes if they have different
1608 implications as to which registers may be used. */
1609 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1612 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1613 qty_phys_sugg for the pseudo instead of tying them.
1615 Return "failure" so that the lifespan of UREG is terminated here;
1616 that way the two lifespans will be disjoint and nothing will prevent
1617 the pseudo reg from being given this hard reg. */
1619 if (ureg
< FIRST_PSEUDO_REGISTER
)
1621 /* Allocate a quantity number so we have a place to put our
1623 if (reg_qty
[sreg
] == -2)
1624 reg_is_born (setreg
, 2 * insn_number
);
1626 if (reg_qty
[sreg
] >= 0)
1630 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1631 qty_phys_has_copy_sugg
[reg_qty
[sreg
]] = 1;
1635 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1636 qty_phys_has_sugg
[reg_qty
[sreg
]] = 1;
1642 /* Similarly for SREG a hard register and UREG a pseudo register. */
1644 if (sreg
< FIRST_PSEUDO_REGISTER
)
1648 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1649 qty_phys_has_copy_sugg
[reg_qty
[ureg
]] = 1;
1653 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1654 qty_phys_has_sugg
[reg_qty
[ureg
]] = 1;
1659 /* At this point we know that SREG and UREG are both pseudos.
1660 Do nothing if SREG already has a quantity or is a register that we
1662 if (reg_qty
[sreg
] >= -1
1663 /* If we are not going to let any regs live across calls,
1664 don't tie a call-crossing reg to a non-call-crossing reg. */
1665 || (current_function_has_nonlocal_label
1666 && ((reg_n_calls_crossed
[ureg
] > 0)
1667 != (reg_n_calls_crossed
[sreg
] > 0))))
1670 /* We don't already know about SREG, so tie it to UREG
1671 if this is the last use of UREG, provided the classes they want
1674 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1675 && reg_meets_class_p (sreg
, qty_min_class
[reg_qty
[ureg
]]))
1677 /* Add SREG to UREG's quantity. */
1678 sqty
= reg_qty
[ureg
];
1679 reg_qty
[sreg
] = sqty
;
1680 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1681 reg_next_in_qty
[sreg
] = qty_first_reg
[sqty
];
1682 qty_first_reg
[sqty
] = sreg
;
1684 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1685 update_qty_class (sqty
, sreg
);
1687 /* Update info about quantity SQTY. */
1688 qty_n_calls_crossed
[sqty
] += reg_n_calls_crossed
[sreg
];
1689 qty_n_refs
[sqty
] += reg_n_refs
[sreg
];
1694 for (i
= qty_first_reg
[sqty
]; i
>= 0; i
= reg_next_in_qty
[i
])
1695 reg_offset
[i
] -= offset
;
1697 qty_size
[sqty
] = ssize
;
1698 qty_mode
[sqty
] = GET_MODE (setreg
);
1707 /* Return 1 if the preferred class of REG allows it to be tied
1708 to a quantity or register whose class is CLASS.
1709 True if REG's reg class either contains or is contained in CLASS. */
1712 reg_meets_class_p (reg
, class)
1714 enum reg_class
class;
1716 register enum reg_class rclass
= reg_preferred_class (reg
);
1717 return (reg_class_subset_p (rclass
, class)
1718 || reg_class_subset_p (class, rclass
));
1721 /* Return 1 if the two specified classes have registers in common.
1722 If CALL_SAVED, then consider only call-saved registers. */
1725 reg_classes_overlap_p (c1
, c2
, call_saved
)
1726 register enum reg_class c1
;
1727 register enum reg_class c2
;
1733 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
1734 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
1736 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1737 if (TEST_HARD_REG_BIT (c
, i
)
1738 && (! call_saved
|| ! call_used_regs
[i
]))
1744 /* Update the class of QTY assuming that REG is being tied to it. */
1747 update_qty_class (qty
, reg
)
1751 enum reg_class rclass
= reg_preferred_class (reg
);
1752 if (reg_class_subset_p (rclass
, qty_min_class
[qty
]))
1753 qty_min_class
[qty
] = rclass
;
1755 rclass
= reg_alternate_class (reg
);
1756 if (reg_class_subset_p (rclass
, qty_alternate_class
[qty
]))
1757 qty_alternate_class
[qty
] = rclass
;
1760 /* Handle something which alters the value of an rtx REG.
1762 REG is whatever is set or clobbered. SETTER is the rtx that
1763 is modifying the register.
1765 If it is not really a register, we do nothing.
1766 The file-global variables `this_insn' and `this_insn_number'
1767 carry info from `block_alloc'. */
1770 reg_is_set (reg
, setter
)
1774 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1775 a hard register. These may actually not exist any more. */
1777 if (GET_CODE (reg
) != SUBREG
1778 && GET_CODE (reg
) != REG
)
1781 /* Mark this register as being born. If it is used in a CLOBBER, mark
1782 it as being born halfway between the previous insn and this insn so that
1783 it conflicts with our inputs but not the outputs of the previous insn. */
1785 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
1788 /* Handle beginning of the life of register REG.
1789 BIRTH is the index at which this is happening. */
1792 reg_is_born (reg
, birth
)
1798 if (GET_CODE (reg
) == SUBREG
)
1799 regno
= REGNO (SUBREG_REG (reg
)) + SUBREG_WORD (reg
);
1801 regno
= REGNO (reg
);
1803 if (regno
< FIRST_PSEUDO_REGISTER
)
1805 mark_life (regno
, GET_MODE (reg
), 1);
1807 /* If the register was to have been born earlier that the present
1808 insn, mark it as live where it is actually born. */
1809 if (birth
< 2 * this_insn_number
)
1810 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
1814 if (reg_qty
[regno
] == -2)
1815 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
1817 /* If this register has a quantity number, show that it isn't dead. */
1818 if (reg_qty
[regno
] >= 0)
1819 qty_death
[reg_qty
[regno
]] = -1;
1823 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1824 REG is an output that is dying (i.e., it is never used), otherwise it
1825 is an input (the normal case).
1826 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1829 wipe_dead_reg (reg
, output_p
)
1833 register int regno
= REGNO (reg
);
1835 /* If this insn has multiple results,
1836 and the dead reg is used in one of the results,
1837 extend its life to after this insn,
1838 so it won't get allocated together with any other result of this insn. */
1839 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
1840 && !single_set (this_insn
))
1843 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
1845 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
1846 if (GET_CODE (set
) == SET
1847 && GET_CODE (SET_DEST (set
)) != REG
1848 && !rtx_equal_p (reg
, SET_DEST (set
))
1849 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1854 if (regno
< FIRST_PSEUDO_REGISTER
)
1856 mark_life (regno
, GET_MODE (reg
), 0);
1858 /* If a hard register is dying as an output, mark it as in use at
1859 the beginning of this insn (the above statement would cause this
1862 post_mark_life (regno
, GET_MODE (reg
), 1,
1863 2 * this_insn_number
, 2 * this_insn_number
+ 1);
1866 else if (reg_qty
[regno
] >= 0)
1867 qty_death
[reg_qty
[regno
]] = 2 * this_insn_number
+ output_p
;
1870 /* Find a block of SIZE words of hard regs in reg_class CLASS
1871 that can hold something of machine-mode MODE
1872 (but actually we test only the first of the block for holding MODE)
1873 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1874 and return the number of the first of them.
1875 Return -1 if such a block cannot be found.
1876 If QTY crosses calls, insist on a register preserved by calls,
1877 unless ACCEPT_CALL_CLOBBERED is nonzero.
1879 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1880 register is available. If not, return -1. */
1883 find_free_reg (class, mode
, qty
, accept_call_clobbered
, just_try_suggested
,
1884 born_index
, dead_index
)
1885 enum reg_class
class;
1886 enum machine_mode mode
;
1887 int accept_call_clobbered
;
1888 int just_try_suggested
;
1890 int born_index
, dead_index
;
1892 register int i
, ins
;
1894 register /* Declare it register if it's a scalar. */
1896 HARD_REG_SET used
, first_used
;
1897 #ifdef ELIMINABLE_REGS
1898 static struct {int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
1901 /* Validate our parameters. */
1902 if (born_index
< 0 || born_index
> dead_index
)
1905 /* Don't let a pseudo live in a reg across a function call
1906 if we might get a nonlocal goto. */
1907 if (current_function_has_nonlocal_label
1908 && qty_n_calls_crossed
[qty
] > 0)
1911 if (accept_call_clobbered
)
1912 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
1913 else if (qty_n_calls_crossed
[qty
] == 0)
1914 COPY_HARD_REG_SET (used
, fixed_reg_set
);
1916 COPY_HARD_REG_SET (used
, call_used_reg_set
);
1918 for (ins
= born_index
; ins
< dead_index
; ins
++)
1919 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
1921 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
1923 /* Don't use the frame pointer reg in local-alloc even if
1924 we may omit the frame pointer, because if we do that and then we
1925 need a frame pointer, reload won't know how to move the pseudo
1926 to another hard reg. It can move only regs made by global-alloc.
1928 This is true of any register that can be eliminated. */
1929 #ifdef ELIMINABLE_REGS
1930 for (i
= 0; i
< sizeof eliminables
/ sizeof eliminables
[0]; i
++)
1931 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
1933 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
1936 /* Normally, the registers that can be used for the first register in
1937 a multi-register quantity are the same as those that can be used for
1938 subsequent registers. However, if just trying suggested registers,
1939 restrict our consideration to them. If there are copy-suggested
1940 register, try them. Otherwise, try the arithmetic-suggested
1942 COPY_HARD_REG_SET (first_used
, used
);
1944 if (just_try_suggested
)
1946 if (qty_phys_has_copy_sugg
[qty
])
1947 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qty
]);
1949 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qty
]);
1952 /* If all registers are excluded, we can't do anything. */
1953 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
1955 /* If at least one would be suitable, test each hard reg. */
1957 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1959 #ifdef REG_ALLOC_ORDER
1960 int regno
= reg_alloc_order
[i
];
1964 if (! TEST_HARD_REG_BIT (first_used
, regno
)
1965 && HARD_REGNO_MODE_OK (regno
, mode
))
1968 register int size1
= HARD_REGNO_NREGS (regno
, mode
);
1969 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
1972 /* Mark that this register is in use between its birth and death
1974 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
1977 #ifndef REG_ALLOC_ORDER
1978 i
+= j
; /* Skip starting points we know will lose */
1985 /* If we are just trying suggested register, we have just tried copy-
1986 suggested registers, and there are arithmetic-suggested registers,
1989 /* If it would be profitable to allocate a call-clobbered register
1990 and save and restore it around calls, do that. */
1991 if (just_try_suggested
&& qty_phys_has_copy_sugg
[qty
]
1992 && qty_phys_has_sugg
[qty
])
1994 /* Don't try the copy-suggested regs again. */
1995 qty_phys_has_copy_sugg
[qty
] = 0;
1996 return find_free_reg (class, mode
, qty
, accept_call_clobbered
, 1,
1997 born_index
, dead_index
);
2000 /* We need not check to see if the current function has nonlocal
2001 labels because we don't put any pseudos that are live over calls in
2002 registers in that case. */
2004 if (! accept_call_clobbered
2005 && flag_caller_saves
2006 && ! just_try_suggested
2007 && qty_n_calls_crossed
[qty
] != 0
2008 && CALLER_SAVE_PROFITABLE (qty_n_refs
[qty
], qty_n_calls_crossed
[qty
]))
2010 i
= find_free_reg (class, mode
, qty
, 1, 0, born_index
, dead_index
);
2012 caller_save_needed
= 1;
2018 /* Mark that REGNO with machine-mode MODE is live starting from the current
2019 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2023 mark_life (regno
, mode
, life
)
2025 enum machine_mode mode
;
2028 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2031 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2034 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2037 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2038 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2039 to insn number DEATH (exclusive). */
2042 post_mark_life (regno
, mode
, life
, birth
, death
)
2043 register int regno
, life
, birth
;
2044 enum machine_mode mode
;
2047 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2049 register /* Declare it register if it's a scalar. */
2051 HARD_REG_SET this_reg
;
2053 CLEAR_HARD_REG_SET (this_reg
);
2055 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2058 while (birth
< death
)
2060 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2064 while (birth
< death
)
2066 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2071 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2072 is the register being clobbered, and R1 is a register being used in
2073 the equivalent expression.
2075 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2076 in which it is used, return 1.
2078 Otherwise, return 0. */
2081 no_conflict_p (insn
, r0
, r1
)
2085 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2088 /* If R1 is a hard register, return 0 since we handle this case
2089 when we scan the insns that actually use it. */
2092 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2093 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2094 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2097 last
= XEXP (note
, 0);
2099 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2100 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
2102 if (find_reg_note (p
, REG_DEAD
, r1
))
2105 if (reg_mentioned_p (r1
, PATTERN (p
))
2106 && ! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2113 #ifdef REGISTER_CONSTRAINTS
2115 /* Return 1 if the constraint string P indicates that the a the operand
2116 must be equal to operand 0 and that no register is acceptable. */
2119 requires_inout_p (p
)
2132 case '=': case '+': case '?':
2133 case '#': case '&': case '!':
2134 case '*': case '%': case ',':
2135 case '1': case '2': case '3': case '4':
2136 case 'm': case '<': case '>': case 'V': case 'o':
2137 case 'E': case 'F': case 'G': case 'H':
2138 case 's': case 'i': case 'n':
2139 case 'I': case 'J': case 'K': case 'L':
2140 case 'M': case 'N': case 'O': case 'P':
2141 #ifdef EXTRA_CONSTRAINT
2142 case 'Q': case 'R': case 'S': case 'T': case 'U':
2145 /* These don't say anything we care about. */
2151 /* These mean a register is allowed. Fail if so. */
2157 #endif /* REGISTER_CONSTRAINTS */
2160 dump_local_alloc (file
)
2164 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2165 if (reg_renumber
[i
] != -1)
2166 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);