1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010, 2011, 2012
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* This file contains code for 3 passes: constraint pass,
24 inheritance/split pass, and pass for undoing failed inheritance and
27 The major goal of constraint pass is to transform RTL to satisfy
28 insn and address constraints by:
29 o choosing insn alternatives;
30 o generating *reload insns* (or reloads in brief) and *reload
31 pseudos* which will get necessary hard registers later;
32 o substituting pseudos with equivalent values and removing the
33 instructions that initialized those pseudos.
35 The constraint pass has biggest and most complicated code in LRA.
36 There are a lot of important details like:
37 o reuse of input reload pseudos to simplify reload pseudo
39 o some heuristics to choose insn alternative to improve the
43 The pass is mimicking former reload pass in alternative choosing
44 because the reload pass is oriented to current machine description
45 model. It might be changed if the machine description model is
48 There is special code for preventing all LRA and this pass cycling
51 On the first iteration of the pass we process every instruction and
52 choose an alternative for each one. On subsequent iterations we try
53 to avoid reprocessing instructions if we can be sure that the old
54 choice is still valid.
56 The inheritance/spilt pass is to transform code to achieve
57 ineheritance and live range splitting. It is done on backward
60 The inheritance optimization goal is to reuse values in hard
61 registers. There is analogous optimization in old reload pass. The
62 inheritance is achieved by following transformation:
64 reload_p1 <- p reload_p1 <- p
65 ... new_p <- reload_p1
67 reload_p2 <- p reload_p2 <- new_p
69 where p is spilled and not changed between the insns. Reload_p1 is
70 also called *original pseudo* and new_p is called *inheritance
73 The subsequent assignment pass will try to assign the same (or
74 another if it is not possible) hard register to new_p as to
75 reload_p1 or reload_p2.
77 If the assignment pass fails to assign a hard register to new_p,
78 this file will undo the inheritance and restore the original code.
79 This is because implementing the above sequence with a spilled
80 new_p would make the code much worse. The inheritance is done in
81 EBB scope. The above is just a simplified example to get an idea
82 of the inheritance as the inheritance is also done for non-reload
85 Splitting (transformation) is also done in EBB scope on the same
86 pass as the inheritance:
88 r <- ... or ... <- r r <- ... or ... <- r
89 ... s <- r (new insn -- save)
91 ... r <- s (new insn -- restore)
94 The *split pseudo* s is assigned to the hard register of the
95 original pseudo or hard register r.
98 o In EBBs with high register pressure for global pseudos (living
99 in at least 2 BBs) and assigned to hard registers when there
100 are more one reloads needing the hard registers;
101 o for pseudos needing save/restore code around calls.
103 If the split pseudo still has the same hard register as the
104 original pseudo after the subsequent assignment pass or the
105 original pseudo was split, the opposite transformation is done on
106 the same pass for undoing inheritance. */
112 #include "coretypes.h"
114 #include "hard-reg-set.h"
118 #include "insn-config.h"
119 #include "insn-codes.h"
122 #include "addresses.h"
124 #include "function.h"
126 #include "basic-block.h"
131 #include "rtl-error.h"
134 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
135 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 static int bb_reload_num
;
139 /* The current insn being processed and corresponding its data (basic
140 block, the insn data, the insn static data, and the mode of each
142 static rtx curr_insn
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || INSN_UID (curr_insn
) >= new_insn_uid_start
)
273 /* When we don't know what class will be used finally for reload
274 pseudos, we use ALL_REGS. */
275 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
276 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
277 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
278 lra_no_alloc_regs
)));
281 common_class
= ira_reg_class_subset
[rclass
][cl
];
282 if (new_class
!= NULL
)
283 *new_class
= common_class
;
284 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
287 /* Check that there are enough allocatable regs. */
288 class_size
= ira_class_hard_regs_num
[common_class
];
289 for (i
= 0; i
< class_size
; i
++)
291 hard_regno
= ira_class_hard_regs
[common_class
][i
];
292 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
295 for (j
= 0; j
< nregs
; j
++)
296 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
))
305 /* Return true if REGNO satisfies a memory constraint. */
309 return get_reg_class (regno
) == NO_REGS
;
312 /* If we have decided to substitute X with another value, return that
313 value, otherwise return X. */
315 get_equiv_substitution (rtx x
)
320 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
321 || ! ira_reg_equiv
[regno
].defined_p
322 || ! ira_reg_equiv
[regno
].profitable_p
323 || lra_get_regno_hard_regno (regno
) >= 0)
325 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
327 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
329 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
334 /* Set up curr_operand_mode. */
336 init_curr_operand_mode (void)
338 int nop
= curr_static_id
->n_operands
;
339 for (int i
= 0; i
< nop
; i
++)
341 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
342 if (mode
== VOIDmode
)
344 /* The .md mode for address operands is the mode of the
345 addressed value rather than the mode of the address itself. */
346 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
349 mode
= curr_static_id
->operand
[i
].mode
;
351 curr_operand_mode
[i
] = mode
;
357 /* The page contains code to reuse input reloads. */
359 /* Structure describes input reload of the current insns. */
362 /* Reloaded value. */
364 /* Reload pseudo used. */
368 /* The number of elements in the following array. */
369 static int curr_insn_input_reloads_num
;
370 /* Array containing info about input reloads. It is used to find the
371 same input reload and reuse the reload pseudo in this case. */
372 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
374 /* Initiate data concerning reuse of input reloads for the current
377 init_curr_insn_input_reloads (void)
379 curr_insn_input_reloads_num
= 0;
382 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
383 using TITLE. Output a new line if NL_P. */
385 change_class (int regno
, enum reg_class new_class
,
386 const char *title
, bool nl_p
)
388 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
);
389 if (lra_dump_file
!= NULL
)
390 fprintf (lra_dump_file
, "%s to class %s for r%d",
391 title
, reg_class_names
[new_class
], regno
);
392 setup_reg_classes (regno
, new_class
, NO_REGS
, new_class
);
393 if (lra_dump_file
!= NULL
&& nl_p
)
394 fprintf (lra_dump_file
, "\n");
397 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
398 created input reload pseudo (only if TYPE is not OP_OUT). The
399 result pseudo is returned through RESULT_REG. Return TRUE if we
400 created a new pseudo, FALSE if we reused the already created input
401 reload pseudo. Use TITLE to describe new registers for debug
404 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
405 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
408 enum reg_class new_class
;
413 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
416 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
417 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
418 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
420 lra_assert (! side_effects_p (original
));
421 *result_reg
= curr_insn_input_reloads
[i
].reg
;
422 regno
= REGNO (*result_reg
);
423 if (lra_dump_file
!= NULL
)
425 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
426 print_value_slim (lra_dump_file
, original
, 1);
428 if (rclass
!= new_class
)
429 change_class (regno
, new_class
, ", change", false);
430 if (lra_dump_file
!= NULL
)
431 fprintf (lra_dump_file
, "\n");
434 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
435 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
436 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
437 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
443 /* The page contains code to extract memory address parts. */
445 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
447 ok_for_index_p_nonstrict (rtx reg
)
449 unsigned regno
= REGNO (reg
);
451 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
454 /* A version of regno_ok_for_base_p for use here, when all pseudos
455 should count as OK. Arguments as for regno_ok_for_base_p. */
457 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
458 enum rtx_code outer_code
, enum rtx_code index_code
)
460 unsigned regno
= REGNO (reg
);
462 if (regno
>= FIRST_PSEUDO_REGISTER
)
464 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
469 /* The page contains major code to choose the current insn alternative
470 and generate reloads for it. */
472 /* Return the offset from REGNO of the least significant register
475 This function is used to tell whether two registers satisfy
476 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
478 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
479 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
481 lra_constraint_offset (int regno
, enum machine_mode mode
)
483 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
484 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
485 && SCALAR_INT_MODE_P (mode
))
486 return hard_regno_nregs
[regno
][mode
] - 1;
490 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
491 if they are the same hard reg, and has special hacks for
492 auto-increment and auto-decrement. This is specifically intended for
493 process_alt_operands to use in determining whether two operands
494 match. X is the operand whose number is the lower of the two.
496 It is supposed that X is the output operand and Y is the input
497 operand. Y_HARD_REGNO is the final hard regno of register Y or
498 register in subreg Y as we know it now. Otherwise, it is a
501 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
504 RTX_CODE code
= GET_CODE (x
);
509 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
510 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
514 i
= get_hard_regno (x
);
518 if ((j
= y_hard_regno
) < 0)
521 i
+= lra_constraint_offset (i
, GET_MODE (x
));
522 j
+= lra_constraint_offset (j
, GET_MODE (y
));
527 /* If two operands must match, because they are really a single
528 operand of an assembler insn, then two post-increments are invalid
529 because the assembler insn would increment only once. On the
530 other hand, a post-increment matches ordinary indexing if the
531 post-increment is the output operand. */
532 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
533 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
535 /* Two pre-increments are invalid because the assembler insn would
536 increment only once. On the other hand, a pre-increment matches
537 ordinary indexing if the pre-increment is the input operand. */
538 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
539 || GET_CODE (y
) == PRE_MODIFY
)
540 return operands_match_p (x
, XEXP (y
, 0), -1);
544 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
545 && x
== SUBREG_REG (y
))
547 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
548 && SUBREG_REG (x
) == y
)
551 /* Now we have disposed of all the cases in which different rtx
553 if (code
!= GET_CODE (y
))
556 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
557 if (GET_MODE (x
) != GET_MODE (y
))
566 return XEXP (x
, 0) == XEXP (y
, 0);
568 return XSTR (x
, 0) == XSTR (y
, 0);
574 /* Compare the elements. If any pair of corresponding elements fail
575 to match, return false for the whole things. */
577 fmt
= GET_RTX_FORMAT (code
);
578 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
584 if (XWINT (x
, i
) != XWINT (y
, i
))
589 if (XINT (x
, i
) != XINT (y
, i
))
594 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
603 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
605 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
607 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
613 /* It is believed that rtx's at this level will never
614 contain anything but integers and other rtx's, except for
615 within LABEL_REFs and SYMBOL_REFs. */
623 /* True if X is a constant that can be forced into the constant pool.
624 MODE is the mode of the operand, or VOIDmode if not known. */
625 #define CONST_POOL_OK_P(MODE, X) \
626 ((MODE) != VOIDmode \
628 && GET_CODE (X) != HIGH \
629 && !targetm.cannot_force_const_mem (MODE, X))
631 /* True if C is a non-empty register class that has too few registers
632 to be safely used as a reload target class. */
633 #define SMALL_REGISTER_CLASS_P(C) \
634 (reg_class_size [(C)] == 1 \
635 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
637 /* If REG is a reload pseudo, try to make its class satisfying CL. */
639 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
641 enum reg_class rclass
;
643 /* Do not make more accurate class from reloads generated. They are
644 mostly moves with a lot of constraints. Making more accurate
645 class may results in very narrow class and impossibility of find
646 registers for several reloads of one insn. */
647 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
649 if (GET_CODE (reg
) == SUBREG
)
650 reg
= SUBREG_REG (reg
);
651 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
653 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
654 change_class (REGNO (reg
), rclass
, " Change", true);
657 /* Generate reloads for matching OUT and INS (array of input operand
658 numbers with end marker -1) with reg class GOAL_CLASS. Add input
659 and output reloads correspondingly to the lists *BEFORE and
662 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
663 rtx
*before
, rtx
*after
)
666 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
667 enum machine_mode inmode
, outmode
;
668 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
669 rtx out_rtx
= *curr_id
->operand_loc
[out
];
671 outmode
= curr_operand_mode
[out
];
672 inmode
= curr_operand_mode
[ins
[0]];
673 push_to_sequence (*before
);
674 if (inmode
!= outmode
)
676 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
679 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
681 if (SCALAR_INT_MODE_P (inmode
))
682 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
684 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
685 /* If the input reg is dying here, we can use the same hard
686 register for REG and IN_RTX. */
688 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
689 lra_reg_info
[REGNO (reg
)].val
= lra_reg_info
[REGNO (in_rtx
)].val
;
694 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
696 if (SCALAR_INT_MODE_P (outmode
))
697 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
699 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
700 /* NEW_IN_REG is non-paradoxical subreg. We don't want
701 NEW_OUT_REG living above. We add clobber clause for
702 this. This is just a temporary clobber. We can remove
703 it at the end of LRA work. */
704 clobber
= emit_clobber (new_out_reg
);
705 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
706 if (GET_CODE (in_rtx
) == SUBREG
)
708 rtx subreg_reg
= SUBREG_REG (in_rtx
);
710 /* If SUBREG_REG is dying here and sub-registers IN_RTX
711 and NEW_IN_REG are similar, we can use the same hard
712 register for REG and SUBREG_REG. */
713 if (REG_P (subreg_reg
) && GET_MODE (subreg_reg
) == outmode
714 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
715 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
716 lra_reg_info
[REGNO (reg
)].val
717 = lra_reg_info
[REGNO (subreg_reg
)].val
;
723 /* Pseudos have values -- see comments for lra_reg_info.
724 Different pseudos with the same value do not conflict even if
725 they live in the same place. When we create a pseudo we
726 assign value of original pseudo (if any) from which we
727 created the new pseudo. If we create the pseudo from the
728 input pseudo, the new pseudo will no conflict with the input
729 pseudo which is wrong when the input pseudo lives after the
730 insn and as the new pseudo value is changed by the insn
731 output. Therefore we create the new pseudo from the output.
733 We cannot reuse the current output register because we might
734 have a situation like "a <- a op b", where the constraints
735 force the second input operand ("b") to match the output
736 operand ("a"). "b" must then be copied into a new register
737 so that it doesn't clobber the current value of "a". */
739 new_in_reg
= new_out_reg
740 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
743 /* In and out operand can be got from transformations before
744 processing insn constraints. One example of such transformations
745 is subreg reloading (see function simplify_operand_subreg). The
746 new pseudos created by the transformations might have inaccurate
747 class (ALL_REGS) and we should make their classes more
749 narrow_reload_pseudo_class (in_rtx
, goal_class
);
750 narrow_reload_pseudo_class (out_rtx
, goal_class
);
751 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
752 *before
= get_insns ();
754 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
757 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
758 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
759 *curr_id
->operand_loc
[in
] = new_in_reg
;
761 lra_update_dups (curr_id
, ins
);
762 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
765 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
767 *after
= get_insns ();
770 *curr_id
->operand_loc
[out
] = new_out_reg
;
771 lra_update_dup (curr_id
, out
);
774 /* Return register class which is union of all reg classes in insn
775 constraint alternative string starting with P. */
776 static enum reg_class
777 reg_class_from_constraints (const char *p
)
780 enum reg_class op_class
= NO_REGS
;
783 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
790 op_class
= (reg_class_subunion
791 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
797 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
801 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
803 #ifdef EXTRA_CONSTRAINT_STR
804 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
806 = (reg_class_subunion
807 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
814 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
817 while ((p
+= len
), c
);
821 /* If OP is a register, return the class of the register as per
822 get_reg_class, otherwise return NO_REGS. */
823 static inline enum reg_class
824 get_op_class (rtx op
)
826 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
829 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
830 otherwise. If modes of MEM_PSEUDO and VAL are different, use
831 SUBREG for VAL to make them equal. */
833 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
835 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
836 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
837 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
840 ? gen_move_insn (mem_pseudo
, val
)
841 : gen_move_insn (val
, mem_pseudo
));
844 /* Process a special case insn (register move), return true if we
845 don't need to process it anymore. Return that RTL was changed
846 through CHANGE_P and macro SECONDARY_MEMORY_NEEDED says to use
847 secondary memory through SEC_MEM_P. */
849 check_and_process_move (bool *change_p
, bool *sec_mem_p
)
852 rtx set
, dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
853 enum reg_class dclass
, sclass
, secondary_class
;
854 enum machine_mode sreg_mode
;
855 secondary_reload_info sri
;
857 *sec_mem_p
= *change_p
= false;
858 if ((set
= single_set (curr_insn
)) == NULL
)
860 dreg
= dest
= SET_DEST (set
);
861 sreg
= src
= SET_SRC (set
);
862 /* Quick check on the right move insn which does not need
864 if ((dclass
= get_op_class (dest
)) != NO_REGS
865 && (sclass
= get_op_class (src
)) != NO_REGS
866 /* The backend guarantees that register moves of cost 2 never
868 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2)
870 if (GET_CODE (dest
) == SUBREG
)
871 dreg
= SUBREG_REG (dest
);
872 if (GET_CODE (src
) == SUBREG
)
873 sreg
= SUBREG_REG (src
);
874 if (! REG_P (dreg
) || ! REG_P (sreg
))
876 sclass
= dclass
= NO_REGS
;
877 dreg
= get_equiv_substitution (dreg
);
879 dclass
= get_reg_class (REGNO (dreg
));
880 if (dclass
== ALL_REGS
)
881 /* ALL_REGS is used for new pseudos created by transformations
882 like reload of SUBREG_REG (see function
883 simplify_operand_subreg). We don't know their class yet. We
884 should figure out the class from processing the insn
885 constraints not in this fast path function. Even if ALL_REGS
886 were a right class for the pseudo, secondary_... hooks usually
887 are not define for ALL_REGS. */
889 sreg_mode
= GET_MODE (sreg
);
891 sreg
= get_equiv_substitution (sreg
);
893 sclass
= get_reg_class (REGNO (sreg
));
894 if (sclass
== ALL_REGS
)
895 /* See comments above. */
897 #ifdef SECONDARY_MEMORY_NEEDED
898 if (dclass
!= NO_REGS
&& sclass
!= NO_REGS
899 && SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
)))
906 sri
.icode
= CODE_FOR_nothing
;
908 secondary_class
= NO_REGS
;
909 /* Set up hard register for a reload pseudo for hook
910 secondary_reload because some targets just ignore unassigned
911 pseudos in the hook. */
912 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
914 dregno
= REGNO (dreg
);
915 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
919 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
921 sregno
= REGNO (sreg
);
922 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
926 if (sclass
!= NO_REGS
)
928 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
929 (reg_class_t
) sclass
,
930 GET_MODE (src
), &sri
);
931 if (sclass
== NO_REGS
932 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
933 && dclass
!= NO_REGS
))
935 enum reg_class old_sclass
= secondary_class
;
936 secondary_reload_info old_sri
= sri
;
939 sri
.icode
= CODE_FOR_nothing
;
942 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
943 (reg_class_t
) dclass
,
945 /* Check the target hook consistency. */
947 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
948 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
949 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
952 reg_renumber
[sregno
] = -1;
954 reg_renumber
[dregno
] = -1;
955 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
959 if (secondary_class
!= NO_REGS
)
960 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
964 if (old_sreg
!= sreg
)
965 sreg
= copy_rtx (sreg
);
966 if (sri
.icode
== CODE_FOR_nothing
)
967 lra_emit_move (new_reg
, sreg
);
970 enum reg_class scratch_class
;
972 scratch_class
= (reg_class_from_constraints
973 (insn_data
[sri
.icode
].operand
[2].constraint
));
974 scratch_reg
= (lra_create_new_reg_with_unique_value
975 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
976 scratch_class
, "scratch"));
977 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
980 before
= get_insns ();
982 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
983 if (new_reg
!= NULL_RTX
)
985 if (GET_CODE (src
) == SUBREG
)
986 SUBREG_REG (src
) = new_reg
;
988 SET_SRC (set
) = new_reg
;
992 if (lra_dump_file
!= NULL
)
994 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
995 debug_rtl_slim (lra_dump_file
, curr_insn
, curr_insn
, -1, 0);
997 lra_set_insn_deleted (curr_insn
);
1003 /* The following data describe the result of process_alt_operands.
1004 The data are used in curr_insn_transform to generate reloads. */
1006 /* The chosen reg classes which should be used for the corresponding
1008 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1009 /* True if the operand should be the same as another operand and that
1010 other operand does not need a reload. */
1011 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1012 /* True if the operand does not need a reload. */
1013 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1014 /* True if the operand can be offsetable memory. */
1015 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1016 /* The number of an operand to which given operand can be matched to. */
1017 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1018 /* The number of elements in the following array. */
1019 static int goal_alt_dont_inherit_ops_num
;
1020 /* Numbers of operands whose reload pseudos should not be inherited. */
1021 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1022 /* True if the insn commutative operands should be swapped. */
1023 static bool goal_alt_swapped
;
1024 /* The chosen insn alternative. */
1025 static int goal_alt_number
;
1027 /* The following five variables are used to choose the best insn
1028 alternative. They reflect final characteristics of the best
1031 /* Number of necessary reloads and overall cost reflecting the
1032 previous value and other unpleasantness of the best alternative. */
1033 static int best_losers
, best_overall
;
1034 /* Number of small register classes used for operands of the best
1036 static int best_small_class_operands_num
;
1037 /* Overall number hard registers used for reloads. For example, on
1038 some targets we need 2 general registers to reload DFmode and only
1039 one floating point register. */
1040 static int best_reload_nregs
;
1041 /* Overall number reflecting distances of previous reloading the same
1042 value. The distances are counted from the current BB start. It is
1043 used to improve inheritance chances. */
1044 static int best_reload_sum
;
1046 /* True if the current insn should have no correspondingly input or
1048 static bool no_input_reloads_p
, no_output_reloads_p
;
1050 /* True if we swapped the commutative operands in the current
1052 static int curr_swapped
;
1054 /* Arrange for address element *LOC to be a register of class CL.
1055 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1056 automodified value; handle that case by adding the required output
1057 reloads to list AFTER. Return true if the RTL was changed. */
1059 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1062 enum reg_class rclass
, new_class
;
1065 enum machine_mode mode
;
1066 bool before_p
= false;
1068 loc
= strip_subreg (loc
);
1070 mode
= GET_MODE (reg
);
1073 /* Always reload memory in an address even if the target supports
1075 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1080 regno
= REGNO (reg
);
1081 rclass
= get_reg_class (regno
);
1082 if ((*loc
= get_equiv_substitution (reg
)) != reg
)
1084 if (lra_dump_file
!= NULL
)
1086 fprintf (lra_dump_file
,
1087 "Changing pseudo %d in address of insn %u on equiv ",
1088 REGNO (reg
), INSN_UID (curr_insn
));
1089 print_value_slim (lra_dump_file
, *loc
, 1);
1090 fprintf (lra_dump_file
, "\n");
1092 *loc
= copy_rtx (*loc
);
1094 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1097 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1098 mode
, reg
, cl
, "address", &new_reg
))
1101 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1103 change_class (regno
, new_class
, " Change", true);
1111 push_to_sequence (*before
);
1112 lra_emit_move (new_reg
, reg
);
1113 *before
= get_insns ();
1120 lra_emit_move (reg
, new_reg
);
1122 *after
= get_insns ();
1128 /* Make reloads for subreg in operand NOP with internal subreg mode
1129 REG_MODE, add new reloads for further processing. Return true if
1130 any reload was generated. */
1132 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1136 enum machine_mode mode
;
1138 rtx operand
= *curr_id
->operand_loc
[nop
];
1140 before
= after
= NULL_RTX
;
1142 if (GET_CODE (operand
) != SUBREG
)
1145 mode
= GET_MODE (operand
);
1146 reg
= SUBREG_REG (operand
);
1147 /* If we change address for paradoxical subreg of memory, the
1148 address might violate the necessary alignment or the access might
1149 be slow. So take this into consideration. */
1151 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1152 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1153 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1155 alter_subreg (curr_id
->operand_loc
[nop
], false);
1158 /* Put constant into memory when we have mixed modes. It generates
1159 a better code in most cases as it does not need a secondary
1160 reload memory. It also prevents LRA looping when LRA is using
1161 secondary reload memory again and again. */
1162 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1163 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1165 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1166 alter_subreg (curr_id
->operand_loc
[nop
], false);
1169 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1170 if there may be a problem accessing OPERAND in the outer
1173 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1174 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1175 /* Don't reload paradoxical subregs because we could be looping
1176 having repeatedly final regno out of hard regs range. */
1177 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1178 >= hard_regno_nregs
[hard_regno
][mode
])
1179 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1180 SUBREG_BYTE (operand
), mode
) < 0)
1181 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1183 enum op_type type
= curr_static_id
->operand
[nop
].type
;
1184 /* The class will be defined later in curr_insn_transform. */
1185 enum reg_class rclass
1186 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1188 new_reg
= lra_create_new_reg_with_unique_value (reg_mode
, reg
, rclass
,
1190 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (new_reg
));
1192 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
))
1194 push_to_sequence (before
);
1195 lra_emit_move (new_reg
, reg
);
1196 before
= get_insns ();
1202 lra_emit_move (reg
, new_reg
);
1204 after
= get_insns ();
1207 SUBREG_REG (operand
) = new_reg
;
1208 lra_process_new_insns (curr_insn
, before
, after
,
1209 "Inserting subreg reload");
1215 /* Return TRUE if X refers for a hard register from SET. */
1217 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1219 int i
, j
, x_hard_regno
;
1220 enum machine_mode mode
;
1226 code
= GET_CODE (x
);
1227 mode
= GET_MODE (x
);
1231 code
= GET_CODE (x
);
1232 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1233 mode
= GET_MODE (x
);
1238 x_hard_regno
= get_hard_regno (x
);
1239 return (x_hard_regno
>= 0
1240 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1244 struct address_info ad
;
1246 decompose_mem_address (&ad
, x
);
1247 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1249 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1252 fmt
= GET_RTX_FORMAT (code
);
1253 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1257 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1260 else if (fmt
[i
] == 'E')
1262 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1263 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1270 /* Return true if OP is a spilled pseudo. */
1272 spilled_pseudo_p (rtx op
)
1275 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1278 /* Return true if X is a general constant. */
1280 general_constant_p (rtx x
)
1282 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1285 /* Major function to choose the current insn alternative and what
1286 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1287 negative we should consider only this alternative. Return false if
1288 we can not choose the alternative or find how to reload the
1291 process_alt_operands (int only_alternative
)
1294 int nop
, small_class_operands_num
, overall
, nalt
;
1295 int n_alternatives
= curr_static_id
->n_alternatives
;
1296 int n_operands
= curr_static_id
->n_operands
;
1297 /* LOSERS counts the operands that don't fit this alternative and
1298 would require loading. */
1300 /* REJECT is a count of how undesirable this alternative says it is
1301 if any reloading is required. If the alternative matches exactly
1302 then REJECT is ignored, but otherwise it gets this much counted
1303 against it in addition to the reloading needed. */
1305 /* The number of elements in the following array. */
1306 int early_clobbered_regs_num
;
1307 /* Numbers of operands which are early clobber registers. */
1308 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1309 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1310 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1311 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1312 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1313 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1314 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1315 /* The number of elements in the following array. */
1316 int curr_alt_dont_inherit_ops_num
;
1317 /* Numbers of operands whose reload pseudos should not be inherited. */
1318 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1320 /* The register when the operand is a subreg of register, otherwise the
1322 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1323 /* The register if the operand is a register or subreg of register,
1325 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1326 int hard_regno
[MAX_RECOG_OPERANDS
];
1327 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1328 int reload_nregs
, reload_sum
;
1332 /* Calculate some data common for all alternatives to speed up the
1334 for (nop
= 0; nop
< n_operands
; nop
++)
1336 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1337 /* The real hard regno of the operand after the allocation. */
1338 hard_regno
[nop
] = get_hard_regno (op
);
1340 operand_reg
[nop
] = op
;
1341 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1342 if (GET_CODE (operand_reg
[nop
]) == SUBREG
)
1344 operand_reg
[nop
] = SUBREG_REG (operand_reg
[nop
]);
1345 if (GET_MODE_SIZE (biggest_mode
[nop
])
1346 < GET_MODE_SIZE (GET_MODE (operand_reg
[nop
])))
1347 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1349 if (REG_P (operand_reg
[nop
]))
1350 no_subreg_reg_operand
[nop
] = operand_reg
[nop
];
1352 operand_reg
[nop
] = NULL_RTX
;
1355 /* The constraints are made of several alternatives. Each operand's
1356 constraint looks like foo,bar,... with commas separating the
1357 alternatives. The first alternatives for all operands go
1358 together, the second alternatives go together, etc.
1360 First loop over alternatives. */
1361 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1363 /* Loop over operands for one constraint alternative. */
1364 #ifdef HAVE_ATTR_enabled
1365 if (curr_id
->alternative_enabled_p
!= NULL
1366 && ! curr_id
->alternative_enabled_p
[nalt
])
1370 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1373 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1374 for (nop
= 0; nop
< n_operands
; nop
++)
1375 reject
+= (curr_static_id
1376 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1377 early_clobbered_regs_num
= 0;
1379 for (nop
= 0; nop
< n_operands
; nop
++)
1383 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1384 bool win
, did_match
, offmemok
, early_clobber_p
;
1385 /* false => this operand can be reloaded somehow for this
1388 /* true => this operand can be reloaded if the alternative
1391 /* True if a constant forced into memory would be OK for
1394 enum reg_class this_alternative
, this_costly_alternative
;
1395 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1396 bool this_alternative_match_win
, this_alternative_win
;
1397 bool this_alternative_offmemok
;
1398 enum machine_mode mode
;
1400 opalt_num
= nalt
* n_operands
+ nop
;
1401 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1403 /* Fast track for no constraints at all. */
1404 curr_alt
[nop
] = NO_REGS
;
1405 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1406 curr_alt_win
[nop
] = true;
1407 curr_alt_match_win
[nop
] = false;
1408 curr_alt_offmemok
[nop
] = false;
1409 curr_alt_matches
[nop
] = -1;
1413 op
= no_subreg_reg_operand
[nop
];
1414 mode
= curr_operand_mode
[nop
];
1416 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1419 early_clobber_p
= false;
1420 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1422 this_costly_alternative
= this_alternative
= NO_REGS
;
1423 /* We update set of possible hard regs besides its class
1424 because reg class might be inaccurate. For example,
1425 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1426 is translated in HI_REGS because classes are merged by
1427 pairs and there is no accurate intermediate class. */
1428 CLEAR_HARD_REG_SET (this_alternative_set
);
1429 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1430 this_alternative_win
= false;
1431 this_alternative_match_win
= false;
1432 this_alternative_offmemok
= false;
1433 this_alternative_matches
= -1;
1435 /* An empty constraint should be excluded by the fast
1437 lra_assert (*p
!= 0 && *p
!= ',');
1439 /* Scan this alternative's specs for this operand; set WIN
1440 if the operand fits any letter in this alternative.
1441 Otherwise, clear BADOP if this operand could fit some
1442 letter after reloads, or set WINREG if this operand could
1443 fit after reloads provided the constraint allows some
1448 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1457 case '=': case '+': case '?': case '*': case '!':
1458 case ' ': case '\t':
1462 /* We only support one commutative marker, the first
1463 one. We already set commutative above. */
1467 early_clobber_p
= true;
1471 /* Ignore rest of this alternative. */
1475 case '0': case '1': case '2': case '3': case '4':
1476 case '5': case '6': case '7': case '8': case '9':
1481 m
= strtoul (p
, &end
, 10);
1484 lra_assert (nop
> m
);
1486 this_alternative_matches
= m
;
1487 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1488 /* We are supposed to match a previous operand.
1489 If we do, we win if that one did. If we do
1490 not, count both of the operands as losers.
1491 (This is too conservative, since most of the
1492 time only a single reload insn will be needed
1493 to make the two operands win. As a result,
1494 this alternative may be rejected when it is
1495 actually desirable.) */
1497 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1498 *curr_id
->operand_loc
[m
], m_hregno
))
1500 /* We should reject matching of an early
1501 clobber operand if the matching operand is
1502 not dying in the insn. */
1503 if (! curr_static_id
->operand
[m
].early_clobber
1504 || operand_reg
[nop
] == NULL_RTX
1505 || (find_regno_note (curr_insn
, REG_DEAD
,
1506 REGNO (operand_reg
[nop
]))
1512 /* If we are matching a non-offsettable
1513 address where an offsettable address was
1514 expected, then we must reject this
1515 combination, because we can't reload
1517 if (curr_alt_offmemok
[m
]
1518 && MEM_P (*curr_id
->operand_loc
[m
])
1519 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1525 /* Operands don't match. Both operands must
1526 allow a reload register, otherwise we
1527 cannot make them match. */
1528 if (curr_alt
[m
] == NO_REGS
)
1530 /* Retroactively mark the operand we had to
1531 match as a loser, if it wasn't already and
1532 it wasn't matched to a register constraint
1533 (e.g it might be matched by memory). */
1535 && (operand_reg
[m
] == NULL_RTX
1536 || hard_regno
[m
] < 0))
1540 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1541 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1544 /* We prefer no matching alternatives because
1545 it gives more freedom in RA. */
1546 if (operand_reg
[nop
] == NULL_RTX
1547 || (find_regno_note (curr_insn
, REG_DEAD
,
1548 REGNO (operand_reg
[nop
]))
1552 /* If we have to reload this operand and some
1553 previous operand also had to match the same
1554 thing as this operand, we don't know how to do
1556 if (!match_p
|| !curr_alt_win
[m
])
1558 for (i
= 0; i
< nop
; i
++)
1559 if (curr_alt_matches
[i
] == m
)
1567 /* This can be fixed with reloads if the operand
1568 we are supposed to match can be fixed with
1571 this_alternative
= curr_alt
[m
];
1572 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1573 winreg
= this_alternative
!= NO_REGS
;
1578 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1580 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1581 IOR_HARD_REG_SET (this_alternative_set
,
1582 reg_class_contents
[cl
]);
1585 this_costly_alternative
1586 = reg_class_subunion
[this_costly_alternative
][cl
];
1587 IOR_HARD_REG_SET (this_costly_alternative_set
,
1588 reg_class_contents
[cl
]);
1594 case TARGET_MEM_CONSTRAINT
:
1595 if (MEM_P (op
) || spilled_pseudo_p (op
))
1597 /* We can put constant or pseudo value into memory
1598 to satisfy the constraint. */
1599 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1606 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1607 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1613 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1614 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1618 /* Memory op whose address is not offsettable. */
1621 && ! offsettable_nonstrict_memref_p (op
))
1625 /* Memory operand whose address is offsettable. */
1628 && offsettable_nonstrict_memref_p (op
))
1629 || spilled_pseudo_p (op
))
1631 /* We can put constant or pseudo value into memory
1632 or make memory address offsetable to satisfy the
1634 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1642 if (GET_CODE (op
) == CONST_DOUBLE
1643 || (GET_CODE (op
) == CONST_VECTOR
1644 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1650 if (GET_CODE (op
) == CONST_DOUBLE
1651 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1656 if (CONST_INT_P (op
)
1657 || (GET_CODE (op
) == CONST_DOUBLE
&& mode
== VOIDmode
))
1661 if (general_constant_p (op
))
1666 if (CONST_INT_P (op
)
1667 || (GET_CODE (op
) == CONST_DOUBLE
&& mode
== VOIDmode
))
1679 if (CONST_INT_P (op
)
1680 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1685 /* This constraint should be excluded by the fast
1692 || general_constant_p (op
)
1693 || spilled_pseudo_p (op
))
1695 /* Drop through into 'r' case. */
1699 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1700 IOR_HARD_REG_SET (this_alternative_set
,
1701 reg_class_contents
[GENERAL_REGS
]);
1704 this_costly_alternative
1705 = (reg_class_subunion
1706 [this_costly_alternative
][GENERAL_REGS
]);
1707 IOR_HARD_REG_SET (this_costly_alternative_set
,
1708 reg_class_contents
[GENERAL_REGS
]);
1713 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1715 #ifdef EXTRA_CONSTRAINT_STR
1716 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1718 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1720 else if (spilled_pseudo_p (op
))
1723 /* If we didn't already win, we can reload
1724 constants via force_const_mem or put the
1725 pseudo value into memory, or make other
1726 memory by reloading the address like for
1728 if (CONST_POOL_OK_P (mode
, op
)
1729 || MEM_P (op
) || REG_P (op
))
1735 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1737 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1740 /* If we didn't already win, we can reload
1741 the address into a base register. */
1742 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1745 = reg_class_subunion
[this_alternative
][cl
];
1746 IOR_HARD_REG_SET (this_alternative_set
,
1747 reg_class_contents
[cl
]);
1750 this_costly_alternative
1751 = (reg_class_subunion
1752 [this_costly_alternative
][cl
]);
1753 IOR_HARD_REG_SET (this_costly_alternative_set
,
1754 reg_class_contents
[cl
]);
1760 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1766 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1767 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1768 IOR_HARD_REG_SET (this_alternative_set
,
1769 reg_class_contents
[cl
]);
1772 this_costly_alternative
1773 = reg_class_subunion
[this_costly_alternative
][cl
];
1774 IOR_HARD_REG_SET (this_costly_alternative_set
,
1775 reg_class_contents
[cl
]);
1778 if (mode
== BLKmode
)
1783 if (hard_regno
[nop
] >= 0
1784 && in_hard_reg_set_p (this_alternative_set
,
1785 mode
, hard_regno
[nop
]))
1787 else if (hard_regno
[nop
] < 0
1788 && in_class_p (op
, this_alternative
, NULL
))
1793 if (c
!= ' ' && c
!= '\t')
1794 costly_p
= c
== '*';
1796 while ((p
+= len
), c
);
1798 /* Record which operands fit this alternative. */
1801 this_alternative_win
= true;
1802 if (operand_reg
[nop
] != NULL_RTX
)
1804 if (hard_regno
[nop
] >= 0)
1806 if (in_hard_reg_set_p (this_costly_alternative_set
,
1807 mode
, hard_regno
[nop
]))
1812 /* Prefer won reg to spilled pseudo under other equal
1815 if (in_class_p (operand_reg
[nop
],
1816 this_costly_alternative
, NULL
))
1819 /* We simulate the behaviour of old reload here.
1820 Although scratches need hard registers and it
1821 might result in spilling other pseudos, no reload
1822 insns are generated for the scratches. So it
1823 might cost something but probably less than old
1824 reload pass believes. */
1825 if (lra_former_scratch_p (REGNO (operand_reg
[nop
])))
1826 reject
+= LRA_LOSER_COST_FACTOR
;
1830 this_alternative_match_win
= true;
1833 int const_to_mem
= 0;
1837 = (this_alternative
== NO_REGS
1838 || (hard_reg_set_subset_p
1839 (reg_class_contents
[this_alternative
],
1840 lra_no_alloc_regs
)));
1841 /* If this operand accepts a register, and if the
1842 register class has at least one allocatable register,
1843 then this operand can be reloaded. */
1844 if (winreg
&& !no_regs_p
)
1850 this_alternative_offmemok
= offmemok
;
1851 if (this_costly_alternative
!= NO_REGS
)
1853 /* If the operand is dying, has a matching constraint,
1854 and satisfies constraints of the matched operand
1855 which failed to satisfy the own constraints, we do
1856 not need to generate a reload insn for this
1858 if (!(this_alternative_matches
>= 0
1859 && !curr_alt_win
[this_alternative_matches
]
1861 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
1862 && (hard_regno
[nop
] >= 0
1863 ? in_hard_reg_set_p (this_alternative_set
,
1864 mode
, hard_regno
[nop
])
1865 : in_class_p (op
, this_alternative
, NULL
))))
1867 if (operand_reg
[nop
] != NULL_RTX
1868 /* Output operands and matched input operands are
1869 not inherited. The following conditions do not
1870 exactly describe the previous statement but they
1871 are pretty close. */
1872 && curr_static_id
->operand
[nop
].type
!= OP_OUT
1873 && (this_alternative_matches
< 0
1874 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
1876 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
1880 if (last_reload
> bb_reload_num
)
1881 reload_sum
+= last_reload
- bb_reload_num
;
1883 /* If this is a constant that is reloaded into the
1884 desired class by copying it to memory first, count
1885 that as another reload. This is consistent with
1886 other code and is required to avoid choosing another
1887 alternative when the constant is moved into memory.
1888 Note that the test here is precisely the same as in
1889 the code below that calls force_const_mem. */
1890 if (CONST_POOL_OK_P (mode
, op
)
1891 && ((targetm
.preferred_reload_class
1892 (op
, this_alternative
) == NO_REGS
)
1893 || no_input_reloads_p
))
1900 /* Alternative loses if it requires a type of reload not
1901 permitted for this insn. We can always reload
1902 objects with a REG_UNUSED note. */
1903 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
1904 && no_output_reloads_p
1905 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
1906 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
1907 && no_input_reloads_p
&& ! const_to_mem
))
1910 /* Check strong discouragement of reload of non-constant
1911 into class THIS_ALTERNATIVE. */
1912 if (! CONSTANT_P (op
) && ! no_regs_p
1913 && (targetm
.preferred_reload_class
1914 (op
, this_alternative
) == NO_REGS
1915 || (curr_static_id
->operand
[nop
].type
== OP_OUT
1916 && (targetm
.preferred_output_reload_class
1917 (op
, this_alternative
) == NO_REGS
))))
1918 reject
+= LRA_MAX_REJECT
;
1920 if (! ((const_to_mem
&& constmemok
)
1921 || (MEM_P (op
) && offmemok
)))
1923 /* We prefer to reload pseudos over reloading other
1924 things, since such reloads may be able to be
1925 eliminated later. So bump REJECT in other cases.
1926 Don't do this in the case where we are forcing a
1927 constant into memory and it will then win since
1928 we don't want to have a different alternative
1930 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
1935 += ira_reg_class_max_nregs
[this_alternative
][mode
];
1938 /* We are trying to spill pseudo into memory. It is
1939 usually more costly than moving to a hard register
1940 although it might takes the same number of
1942 if (no_regs_p
&& REG_P (op
))
1945 #ifdef SECONDARY_MEMORY_NEEDED
1946 /* If reload requires moving value through secondary
1947 memory, it will need one more insn at least. */
1948 if (this_alternative
!= NO_REGS
1949 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
1950 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
1951 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
1953 || (curr_static_id
->operand
[nop
].type
!= OP_IN
1954 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
1958 /* Input reloads can be inherited more often than output
1959 reloads can be removed, so penalize output
1961 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
1965 if (early_clobber_p
)
1967 /* ??? We check early clobbers after processing all operands
1968 (see loop below) and there we update the costs more.
1969 Should we update the cost (may be approximately) here
1970 because of early clobber register reloads or it is a rare
1971 or non-important thing to be worth to do it. */
1972 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
1973 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
1976 curr_alt
[nop
] = this_alternative
;
1977 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
1978 curr_alt_win
[nop
] = this_alternative_win
;
1979 curr_alt_match_win
[nop
] = this_alternative_match_win
;
1980 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
1981 curr_alt_matches
[nop
] = this_alternative_matches
;
1983 if (this_alternative_matches
>= 0
1984 && !did_match
&& !this_alternative_win
)
1985 curr_alt_win
[this_alternative_matches
] = false;
1987 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
1988 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
1991 curr_alt_dont_inherit_ops_num
= 0;
1992 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
1994 int i
, j
, clobbered_hard_regno
;
1995 HARD_REG_SET temp_set
;
1997 i
= early_clobbered_nops
[nop
];
1998 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
1999 || hard_regno
[i
] < 0)
2001 clobbered_hard_regno
= hard_regno
[i
];
2002 CLEAR_HARD_REG_SET (temp_set
);
2003 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2004 for (j
= 0; j
< n_operands
; j
++)
2006 /* We don't want process insides of match_operator and
2007 match_parallel because otherwise we would process
2008 their operands once again generating a wrong
2010 || curr_static_id
->operand
[j
].is_operator
)
2012 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2013 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2015 else if (uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2017 if (j
>= n_operands
)
2019 /* We need to reload early clobbered register. */
2020 for (j
= 0; j
< n_operands
; j
++)
2021 if (curr_alt_matches
[j
] == i
)
2023 curr_alt_match_win
[j
] = false;
2025 overall
+= LRA_LOSER_COST_FACTOR
;
2027 if (! curr_alt_match_win
[i
])
2028 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2031 /* Remember pseudos used for match reloads are never
2033 lra_assert (curr_alt_matches
[i
] >= 0);
2034 curr_alt_win
[curr_alt_matches
[i
]] = false;
2036 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2038 overall
+= LRA_LOSER_COST_FACTOR
;
2040 small_class_operands_num
= 0;
2041 for (nop
= 0; nop
< n_operands
; nop
++)
2042 small_class_operands_num
2043 += SMALL_REGISTER_CLASS_P (curr_alt
[nop
]) ? 1 : 0;
2045 /* If this alternative can be made to work by reloading, and it
2046 needs less reloading than the others checked so far, record
2047 it as the chosen goal for reloading. */
2048 if ((best_losers
!= 0 && losers
== 0)
2049 || (((best_losers
== 0 && losers
== 0)
2050 || (best_losers
!= 0 && losers
!= 0))
2051 && (best_overall
> overall
2052 || (best_overall
== overall
2053 /* If the cost of the reloads is the same,
2054 prefer alternative which requires minimal
2055 number of small register classes for the
2056 operands. This improves chances of reloads
2057 for insn requiring small register
2059 && (small_class_operands_num
2060 < best_small_class_operands_num
2061 || (small_class_operands_num
2062 == best_small_class_operands_num
2063 && (reload_nregs
< best_reload_nregs
2064 || (reload_nregs
== best_reload_nregs
2065 && best_reload_sum
< reload_sum
))))))))
2067 for (nop
= 0; nop
< n_operands
; nop
++)
2069 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2070 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2071 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2072 goal_alt
[nop
] = curr_alt
[nop
];
2073 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2075 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2076 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2077 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2078 goal_alt_swapped
= curr_swapped
;
2079 best_overall
= overall
;
2080 best_losers
= losers
;
2081 best_small_class_operands_num
= small_class_operands_num
;
2082 best_reload_nregs
= reload_nregs
;
2083 best_reload_sum
= reload_sum
;
2084 goal_alt_number
= nalt
;
2087 /* Everything is satisfied. Do not process alternatives
2096 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2097 space AS, and check that each pseudo has the proper kind of hard
2100 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2101 rtx addr
, addr_space_t as
)
2103 #ifdef GO_IF_LEGITIMATE_ADDRESS
2104 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2105 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2111 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2115 /* Return whether address AD is valid. */
2118 valid_address_p (struct address_info
*ad
)
2120 /* Some ports do not check displacements for eliminable registers,
2121 so we replace them temporarily with the elimination target. */
2122 rtx saved_base_reg
= NULL_RTX
;
2123 rtx saved_index_reg
= NULL_RTX
;
2124 rtx
*base_term
= strip_subreg (ad
->base_term
);
2125 rtx
*index_term
= strip_subreg (ad
->index_term
);
2126 if (base_term
!= NULL
)
2128 saved_base_reg
= *base_term
;
2129 lra_eliminate_reg_if_possible (base_term
);
2130 if (ad
->base_term2
!= NULL
)
2131 *ad
->base_term2
= *ad
->base_term
;
2133 if (index_term
!= NULL
)
2135 saved_index_reg
= *index_term
;
2136 lra_eliminate_reg_if_possible (index_term
);
2138 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2139 if (saved_base_reg
!= NULL_RTX
)
2141 *base_term
= saved_base_reg
;
2142 if (ad
->base_term2
!= NULL
)
2143 *ad
->base_term2
= *ad
->base_term
;
2145 if (saved_index_reg
!= NULL_RTX
)
2146 *index_term
= saved_index_reg
;
2150 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2152 base_plus_disp_to_reg (struct address_info
*ad
)
2157 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2158 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2159 get_index_code (ad
));
2160 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2162 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2166 /* Return true if we can add a displacement to address AD, even if that
2167 makes the address invalid. The fix-up code requires any new address
2168 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2170 can_add_disp_p (struct address_info
*ad
)
2172 return (!ad
->autoinc_p
2173 && ad
->segment
== NULL
2174 && ad
->base
== ad
->base_term
2175 && ad
->disp
== ad
->disp_term
);
2178 /* Make equiv substitution in address AD. Return true if a substitution
2181 equiv_address_substitution (struct address_info
*ad
)
2183 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2184 HOST_WIDE_INT disp
, scale
;
2187 base_term
= strip_subreg (ad
->base_term
);
2188 if (base_term
== NULL
)
2189 base_reg
= new_base_reg
= NULL_RTX
;
2192 base_reg
= *base_term
;
2193 new_base_reg
= get_equiv_substitution (base_reg
);
2195 index_term
= strip_subreg (ad
->index_term
);
2196 if (index_term
== NULL
)
2197 index_reg
= new_index_reg
= NULL_RTX
;
2200 index_reg
= *index_term
;
2201 new_index_reg
= get_equiv_substitution (index_reg
);
2203 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2207 if (lra_dump_file
!= NULL
)
2209 fprintf (lra_dump_file
, "Changing address in insn %d ",
2210 INSN_UID (curr_insn
));
2211 print_value_slim (lra_dump_file
, *ad
->outer
, 1);
2213 if (base_reg
!= new_base_reg
)
2215 if (REG_P (new_base_reg
))
2217 *base_term
= new_base_reg
;
2220 else if (GET_CODE (new_base_reg
) == PLUS
2221 && REG_P (XEXP (new_base_reg
, 0))
2222 && CONST_INT_P (XEXP (new_base_reg
, 1))
2223 && can_add_disp_p (ad
))
2225 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2226 *base_term
= XEXP (new_base_reg
, 0);
2229 if (ad
->base_term2
!= NULL
)
2230 *ad
->base_term2
= *ad
->base_term
;
2232 if (index_reg
!= new_index_reg
)
2234 if (REG_P (new_index_reg
))
2236 *index_term
= new_index_reg
;
2239 else if (GET_CODE (new_index_reg
) == PLUS
2240 && REG_P (XEXP (new_index_reg
, 0))
2241 && CONST_INT_P (XEXP (new_index_reg
, 1))
2242 && can_add_disp_p (ad
)
2243 && (scale
= get_index_scale (ad
)))
2245 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2246 *index_term
= XEXP (new_index_reg
, 0);
2252 if (ad
->disp
!= NULL
)
2253 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2256 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2257 update_address (ad
);
2261 if (lra_dump_file
!= NULL
)
2264 fprintf (lra_dump_file
, " -- no change\n");
2267 fprintf (lra_dump_file
, " on equiv ");
2268 print_value_slim (lra_dump_file
, *ad
->outer
, 1);
2269 fprintf (lra_dump_file
, "\n");
2275 /* Major function to make reloads for an address in operand NOP.
2276 The supported cases are:
2278 1) an address that existed before LRA started, at which point it must
2279 have been valid. These addresses are subject to elimination and
2280 may have become invalid due to the elimination offset being out
2283 2) an address created by forcing a constant to memory (force_const_to_mem).
2284 The initial form of these addresses might not be valid, and it is this
2285 function's job to make them valid.
2287 3) a frame address formed from a register and a (possibly zero)
2288 constant offset. As above, these addresses might not be valid
2289 and this function must make them so.
2291 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2292 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2293 address. Return true for any RTL change. */
2295 process_address (int nop
, rtx
*before
, rtx
*after
)
2297 struct address_info ad
;
2299 rtx op
= *curr_id
->operand_loc
[nop
];
2300 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2303 if (constraint
[0] == 'p'
2304 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2305 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2306 else if (MEM_P (op
))
2307 decompose_mem_address (&ad
, op
);
2308 else if (GET_CODE (op
) == SUBREG
2309 && MEM_P (SUBREG_REG (op
)))
2310 decompose_mem_address (&ad
, SUBREG_REG (op
));
2313 change_p
= equiv_address_substitution (&ad
);
2314 if (ad
.base_term
!= NULL
2315 && (process_addr_reg
2316 (ad
.base_term
, before
,
2318 && !(REG_P (*ad
.base_term
)
2319 && find_regno_note (curr_insn
, REG_DEAD
,
2320 REGNO (*ad
.base_term
)) != NULL_RTX
)
2322 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2323 get_index_code (&ad
)))))
2326 if (ad
.base_term2
!= NULL
)
2327 *ad
.base_term2
= *ad
.base_term
;
2329 if (ad
.index_term
!= NULL
2330 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2333 /* There are three cases where the shape of *AD.INNER may now be invalid:
2335 1) the original address was valid, but either elimination or
2336 equiv_address_substitution applied a displacement that made
2339 2) the address is an invalid symbolic address created by
2342 3) the address is a frame address with an invalid offset.
2344 All these cases involve a displacement and a non-autoinc address,
2345 so there is no point revalidating other types. */
2346 if (ad
.disp
== NULL
|| ad
.autoinc_p
|| valid_address_p (&ad
))
2349 /* Any index existed before LRA started, so we can assume that the
2350 presence and shape of the index is valid. */
2351 push_to_sequence (*before
);
2352 gcc_assert (ad
.segment
== NULL
);
2353 gcc_assert (ad
.disp
== ad
.disp_term
);
2354 if (ad
.base
== NULL
)
2356 if (ad
.index
== NULL
)
2359 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2361 rtx disp
= *ad
.disp
;
2363 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2367 rtx last
= get_last_insn ();
2369 /* disp => lo_sum (new_base, disp), case (2) above. */
2370 insn
= emit_insn (gen_rtx_SET
2372 gen_rtx_HIGH (Pmode
, copy_rtx (disp
))));
2373 code
= recog_memoized (insn
);
2376 *ad
.disp
= gen_rtx_LO_SUM (Pmode
, new_reg
, disp
);
2377 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2384 delete_insns_since (last
);
2389 /* disp => new_base, case (2) above. */
2390 lra_emit_move (new_reg
, disp
);
2396 /* index * scale + disp => new base + index * scale,
2398 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2399 GET_CODE (*ad
.index
));
2401 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2402 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2403 lra_emit_move (new_reg
, *ad
.disp
);
2404 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2405 new_reg
, *ad
.index
);
2408 else if (ad
.index
== NULL
)
2410 /* base + disp => new base, cases (1) and (3) above. */
2411 /* Another option would be to reload the displacement into an
2412 index register. However, postreload has code to optimize
2413 address reloads that have the same base and different
2414 displacements, so reloading into an index register would
2415 not necessarily be a win. */
2416 new_reg
= base_plus_disp_to_reg (&ad
);
2417 *ad
.inner
= new_reg
;
2421 /* base + scale * index + disp => new base + scale * index,
2423 new_reg
= base_plus_disp_to_reg (&ad
);
2424 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2425 new_reg
, *ad
.index
);
2427 *before
= get_insns ();
2432 /* Emit insns to reload VALUE into a new register. VALUE is an
2433 auto-increment or auto-decrement RTX whose operand is a register or
2434 memory location; so reloading involves incrementing that location.
2435 IN is either identical to VALUE, or some cheaper place to reload
2436 value being incremented/decremented from.
2438 INC_AMOUNT is the number to increment or decrement by (always
2439 positive and ignored for POST_MODIFY/PRE_MODIFY).
2441 Return pseudo containing the result. */
2443 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2445 /* REG or MEM to be copied and incremented. */
2446 rtx incloc
= XEXP (value
, 0);
2447 /* Nonzero if increment after copying. */
2448 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2449 || GET_CODE (value
) == POST_MODIFY
);
2454 rtx real_in
= in
== value
? incloc
: in
;
2458 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2460 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2461 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2462 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2463 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2464 inc
= XEXP (XEXP (value
, 1), 1);
2468 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2469 inc_amount
= -inc_amount
;
2471 inc
= GEN_INT (inc_amount
);
2474 if (! post
&& REG_P (incloc
))
2477 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2480 if (real_in
!= result
)
2482 /* First copy the location to the result register. */
2483 lra_assert (REG_P (result
));
2484 emit_insn (gen_move_insn (result
, real_in
));
2487 /* We suppose that there are insns to add/sub with the constant
2488 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2489 old reload worked with this assumption. If the assumption
2490 becomes wrong, we should use approach in function
2491 base_plus_disp_to_reg. */
2494 /* See if we can directly increment INCLOC. */
2495 last
= get_last_insn ();
2496 add_insn
= emit_insn (plus_p
2497 ? gen_add2_insn (incloc
, inc
)
2498 : gen_sub2_insn (incloc
, inc
));
2500 code
= recog_memoized (add_insn
);
2503 if (! post
&& result
!= incloc
)
2504 emit_insn (gen_move_insn (result
, incloc
));
2507 delete_insns_since (last
);
2510 /* If couldn't do the increment directly, must increment in RESULT.
2511 The way we do this depends on whether this is pre- or
2512 post-increment. For pre-increment, copy INCLOC to the reload
2513 register, increment it there, then save back. */
2516 if (real_in
!= result
)
2517 emit_insn (gen_move_insn (result
, real_in
));
2519 emit_insn (gen_add2_insn (result
, inc
));
2521 emit_insn (gen_sub2_insn (result
, inc
));
2522 if (result
!= incloc
)
2523 emit_insn (gen_move_insn (incloc
, result
));
2529 Because this might be a jump insn or a compare, and because
2530 RESULT may not be available after the insn in an input
2531 reload, we must do the incrementing before the insn being
2534 We have already copied IN to RESULT. Increment the copy in
2535 RESULT, save that back, then decrement RESULT so it has
2536 the original value. */
2538 emit_insn (gen_add2_insn (result
, inc
));
2540 emit_insn (gen_sub2_insn (result
, inc
));
2541 emit_insn (gen_move_insn (incloc
, result
));
2542 /* Restore non-modified value for the result. We prefer this
2543 way because it does not require an additional hard
2547 if (CONST_INT_P (inc
))
2548 emit_insn (gen_add2_insn (result
, GEN_INT (-INTVAL (inc
))));
2550 emit_insn (gen_sub2_insn (result
, inc
));
2553 emit_insn (gen_add2_insn (result
, inc
));
2558 /* Swap operands NOP and NOP + 1. */
2560 swap_operands (int nop
)
2562 enum machine_mode mode
= curr_operand_mode
[nop
];
2563 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
2564 curr_operand_mode
[nop
+ 1] = mode
;
2565 rtx x
= *curr_id
->operand_loc
[nop
];
2566 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
2567 *curr_id
->operand_loc
[nop
+ 1] = x
;
2568 /* Swap the duplicates too. */
2569 lra_update_dup (curr_id
, nop
);
2570 lra_update_dup (curr_id
, nop
+ 1);
2573 /* Main entry point of the constraint code: search the body of the
2574 current insn to choose the best alternative. It is mimicking insn
2575 alternative cost calculation model of former reload pass. That is
2576 because machine descriptions were written to use this model. This
2577 model can be changed in future. Make commutative operand exchange
2580 Return true if some RTL changes happened during function call. */
2582 curr_insn_transform (void)
2588 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
2591 /* Flag that the insn has been changed through a transformation. */
2594 #ifdef SECONDARY_MEMORY_NEEDED
2597 int max_regno_before
;
2598 int reused_alternative_num
;
2600 no_input_reloads_p
= no_output_reloads_p
= false;
2601 goal_alt_number
= -1;
2603 if (check_and_process_move (&change_p
, &sec_mem_p
))
2606 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
2607 reloads; neither are insns that SET cc0. Insns that use CC0 are
2608 not allowed to have any input reloads. */
2609 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
2610 no_output_reloads_p
= true;
2613 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
2614 no_input_reloads_p
= true;
2615 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
2616 no_output_reloads_p
= true;
2619 n_operands
= curr_static_id
->n_operands
;
2620 n_alternatives
= curr_static_id
->n_alternatives
;
2622 /* Just return "no reloads" if insn has no operands with
2624 if (n_operands
== 0 || n_alternatives
== 0)
2627 max_regno_before
= max_reg_num ();
2629 for (i
= 0; i
< n_operands
; i
++)
2631 goal_alt_matched
[i
][0] = -1;
2632 goal_alt_matches
[i
] = -1;
2635 commutative
= curr_static_id
->commutative
;
2637 /* Now see what we need for pseudos that didn't get hard regs or got
2638 the wrong kind of hard reg. For this, we must consider all the
2639 operands together against the register constraints. */
2641 best_losers
= best_overall
= INT_MAX
;
2642 best_small_class_operands_num
= best_reload_sum
= 0;
2644 curr_swapped
= false;
2645 goal_alt_swapped
= false;
2647 /* Make equivalence substitution and memory subreg elimination
2648 before address processing because an address legitimacy can
2649 depend on memory mode. */
2650 for (i
= 0; i
< n_operands
; i
++)
2652 rtx op
= *curr_id
->operand_loc
[i
];
2653 rtx subst
, old
= op
;
2654 bool op_change_p
= false;
2656 if (GET_CODE (old
) == SUBREG
)
2657 old
= SUBREG_REG (old
);
2658 subst
= get_equiv_substitution (old
);
2661 subst
= copy_rtx (subst
);
2662 lra_assert (REG_P (old
));
2663 if (GET_CODE (op
) == SUBREG
)
2664 SUBREG_REG (op
) = subst
;
2666 *curr_id
->operand_loc
[i
] = subst
;
2667 if (lra_dump_file
!= NULL
)
2669 fprintf (lra_dump_file
,
2670 "Changing pseudo %d in operand %i of insn %u on equiv ",
2671 REGNO (old
), i
, INSN_UID (curr_insn
));
2672 print_value_slim (lra_dump_file
, subst
, 1);
2673 fprintf (lra_dump_file
, "\n");
2675 op_change_p
= change_p
= true;
2677 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
2680 lra_update_dup (curr_id
, i
);
2684 /* Reload address registers and displacements. We do it before
2685 finding an alternative because of memory constraints. */
2686 before
= after
= NULL_RTX
;
2687 for (i
= 0; i
< n_operands
; i
++)
2688 if (! curr_static_id
->operand
[i
].is_operator
2689 && process_address (i
, &before
, &after
))
2692 lra_update_dup (curr_id
, i
);
2696 /* If we've changed the instruction then any alternative that
2697 we chose previously may no longer be valid. */
2698 lra_set_used_insn_alternative (curr_insn
, -1);
2702 reused_alternative_num
= curr_id
->used_insn_alternative
;
2703 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
2704 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
2705 reused_alternative_num
, INSN_UID (curr_insn
));
2707 if (process_alt_operands (reused_alternative_num
))
2710 /* If insn is commutative (it's safe to exchange a certain pair of
2711 operands) then we need to try each alternative twice, the second
2712 time matching those two operands as if we had exchanged them. To
2713 do this, really exchange them in operands.
2715 If we have just tried the alternatives the second time, return
2716 operands to normal and drop through. */
2718 if (reused_alternative_num
< 0 && commutative
>= 0)
2720 curr_swapped
= !curr_swapped
;
2723 swap_operands (commutative
);
2727 swap_operands (commutative
);
2730 /* The operands don't meet the constraints. goal_alt describes the
2731 alternative that we could reach by reloading the fewest operands.
2732 Reload so as to fit it. */
2734 if (! alt_p
&& ! sec_mem_p
)
2736 /* No alternative works with reloads?? */
2737 if (INSN_CODE (curr_insn
) >= 0)
2738 fatal_insn ("unable to generate reloads for:", curr_insn
);
2739 error_for_asm (curr_insn
,
2740 "inconsistent operand constraints in an %<asm%>");
2741 /* Avoid further trouble with this insn. */
2742 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
2743 lra_invalidate_insn_data (curr_insn
);
2747 /* If the best alternative is with operands 1 and 2 swapped, swap
2748 them. Update the operand numbers of any reloads already
2751 if (goal_alt_swapped
)
2753 if (lra_dump_file
!= NULL
)
2754 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
2755 INSN_UID (curr_insn
));
2757 /* Swap the duplicates too. */
2758 swap_operands (commutative
);
2762 #ifdef SECONDARY_MEMORY_NEEDED
2763 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
2764 too conservatively. So we use the secondary memory only if there
2765 is no any alternative without reloads. */
2766 use_sec_mem_p
= false;
2768 use_sec_mem_p
= true;
2771 for (i
= 0; i
< n_operands
; i
++)
2772 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
2774 use_sec_mem_p
= i
< n_operands
;
2779 rtx new_reg
, set
, src
, dest
;
2780 enum machine_mode sec_mode
;
2782 lra_assert (sec_mem_p
);
2783 set
= single_set (curr_insn
);
2784 lra_assert (set
!= NULL_RTX
&& ! side_effects_p (set
));
2785 dest
= SET_DEST (set
);
2786 src
= SET_SRC (set
);
2787 #ifdef SECONDARY_MEMORY_NEEDED_MODE
2788 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
));
2790 sec_mode
= GET_MODE (src
);
2792 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
2793 NO_REGS
, "secondary");
2794 /* If the mode is changed, it should be wider. */
2795 lra_assert (GET_MODE_SIZE (GET_MODE (new_reg
))
2796 >= GET_MODE_SIZE (GET_MODE (src
)));
2797 after
= emit_spill_move (false, new_reg
, dest
);
2798 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
2799 "Inserting the sec. move");
2800 before
= emit_spill_move (true, new_reg
, src
);
2801 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
2802 lra_set_insn_deleted (curr_insn
);
2807 lra_assert (goal_alt_number
>= 0);
2808 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
2810 if (lra_dump_file
!= NULL
)
2814 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
2815 goal_alt_number
, INSN_UID (curr_insn
));
2816 for (i
= 0; i
< n_operands
; i
++)
2818 p
= (curr_static_id
->operand_alternative
2819 [goal_alt_number
* n_operands
+ i
].constraint
);
2822 fprintf (lra_dump_file
, " (%d) ", i
);
2823 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
2824 fputc (*p
, lra_dump_file
);
2826 fprintf (lra_dump_file
, "\n");
2829 /* Right now, for any pair of operands I and J that are required to
2830 match, with J < I, goal_alt_matches[I] is J. Add I to
2831 goal_alt_matched[J]. */
2833 for (i
= 0; i
< n_operands
; i
++)
2834 if ((j
= goal_alt_matches
[i
]) >= 0)
2836 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
2838 /* We allow matching one output operand and several input
2841 || (curr_static_id
->operand
[j
].type
== OP_OUT
2842 && curr_static_id
->operand
[i
].type
== OP_IN
2843 && (curr_static_id
->operand
2844 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
2845 goal_alt_matched
[j
][k
] = i
;
2846 goal_alt_matched
[j
][k
+ 1] = -1;
2849 for (i
= 0; i
< n_operands
; i
++)
2850 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
2852 /* Any constants that aren't allowed and can't be reloaded into
2853 registers are here changed into memory references. */
2854 for (i
= 0; i
< n_operands
; i
++)
2855 if (goal_alt_win
[i
])
2858 enum reg_class new_class
;
2859 rtx reg
= *curr_id
->operand_loc
[i
];
2861 if (GET_CODE (reg
) == SUBREG
)
2862 reg
= SUBREG_REG (reg
);
2864 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
2866 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
2868 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
2871 change_class (regno
, new_class
, " Change", true);
2877 const char *constraint
;
2879 rtx op
= *curr_id
->operand_loc
[i
];
2880 rtx subreg
= NULL_RTX
;
2881 enum machine_mode mode
= curr_operand_mode
[i
];
2883 if (GET_CODE (op
) == SUBREG
)
2886 op
= SUBREG_REG (op
);
2887 mode
= GET_MODE (op
);
2890 if (CONST_POOL_OK_P (mode
, op
)
2891 && ((targetm
.preferred_reload_class
2892 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
2893 || no_input_reloads_p
))
2895 rtx tem
= force_const_mem (mode
, op
);
2898 if (subreg
!= NULL_RTX
)
2899 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
2901 *curr_id
->operand_loc
[i
] = tem
;
2902 lra_update_dup (curr_id
, i
);
2903 process_address (i
, &before
, &after
);
2905 /* If the alternative accepts constant pool refs directly
2906 there will be no reload needed at all. */
2907 if (subreg
!= NULL_RTX
)
2909 /* Skip alternatives before the one requested. */
2910 constraint
= (curr_static_id
->operand_alternative
2911 [goal_alt_number
* n_operands
+ i
].constraint
);
2913 (c
= *constraint
) && c
!= ',' && c
!= '#';
2914 constraint
+= CONSTRAINT_LEN (c
, constraint
))
2916 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
2918 #ifdef EXTRA_CONSTRAINT_STR
2919 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
2920 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
2924 if (c
== '\0' || c
== ',' || c
== '#')
2927 goal_alt_win
[i
] = true;
2931 for (i
= 0; i
< n_operands
; i
++)
2934 rtx op
= *curr_id
->operand_loc
[i
];
2936 if (goal_alt_win
[i
])
2938 if (goal_alt
[i
] == NO_REGS
2940 /* When we assign NO_REGS it means that we will not
2941 assign a hard register to the scratch pseudo by
2942 assigment pass and the scratch pseudo will be
2943 spilled. Spilled scratch pseudos are transformed
2944 back to scratches at the LRA end. */
2945 && lra_former_scratch_operand_p (curr_insn
, i
))
2946 change_class (REGNO (op
), NO_REGS
, " Change", true);
2950 /* Operands that match previous ones have already been handled. */
2951 if (goal_alt_matches
[i
] >= 0)
2954 /* We should not have an operand with a non-offsettable address
2955 appearing where an offsettable address will do. It also may
2956 be a case when the address should be special in other words
2957 not a general one (e.g. it needs no index reg). */
2958 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
2960 enum reg_class rclass
;
2961 rtx
*loc
= &XEXP (op
, 0);
2962 enum rtx_code code
= GET_CODE (*loc
);
2964 push_to_sequence (before
);
2965 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
2967 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
2968 new_reg
= emit_inc (rclass
, *loc
, *loc
,
2969 /* This value does not matter for MODIFY. */
2970 GET_MODE_SIZE (GET_MODE (op
)));
2971 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
2972 "offsetable address", &new_reg
))
2973 lra_emit_move (new_reg
, *loc
);
2974 before
= get_insns ();
2977 lra_update_dup (curr_id
, i
);
2979 else if (goal_alt_matched
[i
][0] == -1)
2981 enum machine_mode mode
;
2983 int hard_regno
, byte
;
2984 enum op_type type
= curr_static_id
->operand
[i
].type
;
2986 loc
= curr_id
->operand_loc
[i
];
2987 mode
= curr_operand_mode
[i
];
2988 if (GET_CODE (*loc
) == SUBREG
)
2990 reg
= SUBREG_REG (*loc
);
2991 byte
= SUBREG_BYTE (*loc
);
2993 /* Strict_low_part requires reload the register not
2994 the sub-register. */
2995 && (curr_static_id
->operand
[i
].strict_low
2996 || (GET_MODE_SIZE (mode
)
2997 <= GET_MODE_SIZE (GET_MODE (reg
))
2999 = get_try_hard_regno (REGNO (reg
))) >= 0
3000 && (simplify_subreg_regno
3002 GET_MODE (reg
), byte
, mode
) < 0)
3003 && (goal_alt
[i
] == NO_REGS
3004 || (simplify_subreg_regno
3005 (ira_class_hard_regs
[goal_alt
[i
]][0],
3006 GET_MODE (reg
), byte
, mode
) >= 0)))))
3008 loc
= &SUBREG_REG (*loc
);
3009 mode
= GET_MODE (*loc
);
3013 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3016 push_to_sequence (before
);
3017 lra_emit_move (new_reg
, old
);
3018 before
= get_insns ();
3023 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3026 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3028 after
= get_insns ();
3032 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3033 if (goal_alt_dont_inherit_ops
[j
] == i
)
3035 lra_set_regno_unique_value (REGNO (new_reg
));
3038 lra_update_dup (curr_id
, i
);
3040 else if (curr_static_id
->operand
[i
].type
== OP_IN
3041 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3048 match_reload (goal_alt_matched
[i
][0], arr
,
3049 goal_alt
[i
], &before
, &after
);
3051 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3052 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3054 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3056 /* We must generate code in any case when function
3057 process_alt_operands decides that it is possible. */
3060 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3061 || max_regno_before
!= max_reg_num ())
3065 lra_update_operator_dups (curr_id
);
3066 /* Something changes -- process the insn. */
3067 lra_update_insn_regno_info (curr_insn
);
3069 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3073 /* Return true if X is in LIST. */
3075 in_list_p (rtx x
, rtx list
)
3077 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3078 if (XEXP (list
, 0) == x
)
3083 /* Return true if X contains an allocatable hard register (if
3084 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3086 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3092 code
= GET_CODE (x
);
3095 int regno
= REGNO (x
);
3096 HARD_REG_SET alloc_regs
;
3100 if (regno
>= FIRST_PSEUDO_REGISTER
)
3101 regno
= lra_get_regno_hard_regno (regno
);
3104 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3105 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3109 if (regno
< FIRST_PSEUDO_REGISTER
)
3113 return lra_get_regno_hard_regno (regno
) < 0;
3116 fmt
= GET_RTX_FORMAT (code
);
3117 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3121 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3124 else if (fmt
[i
] == 'E')
3126 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3127 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3134 /* Process all regs in location *LOC and change them on equivalent
3135 substitution. Return true if any change was done. */
3137 loc_equivalence_change_p (rtx
*loc
)
3139 rtx subst
, reg
, x
= *loc
;
3140 bool result
= false;
3141 enum rtx_code code
= GET_CODE (x
);
3147 reg
= SUBREG_REG (x
);
3148 if ((subst
= get_equiv_substitution (reg
)) != reg
3149 && GET_MODE (subst
) == VOIDmode
)
3151 /* We cannot reload debug location. Simplify subreg here
3152 while we know the inner mode. */
3153 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3154 GET_MODE (reg
), SUBREG_BYTE (x
));
3158 if (code
== REG
&& (subst
= get_equiv_substitution (x
)) != x
)
3164 /* Scan all the operand sub-expressions. */
3165 fmt
= GET_RTX_FORMAT (code
);
3166 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3169 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3170 else if (fmt
[i
] == 'E')
3171 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3173 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3178 /* Maximum allowed number of constraint pass iterations after the last
3179 spill pass. It is for preventing LRA cycling in a bug case. */
3180 #define MAX_CONSTRAINT_ITERATION_NUMBER 15
3182 /* Maximum number of generated reload insns per an insn. It is for
3183 preventing this pass cycling in a bug case. */
3184 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3186 /* The current iteration number of this LRA pass. */
3187 int lra_constraint_iter
;
3189 /* The current iteration number of this LRA pass after the last spill
3191 int lra_constraint_iter_after_spill
;
3193 /* True if we substituted equiv which needs checking register
3194 allocation correctness because the equivalent value contains
3195 allocatable hard registers or when we restore multi-register
3197 bool lra_risky_transformations_p
;
3199 /* Return true if REGNO is referenced in more than one block. */
3201 multi_block_pseudo_p (int regno
)
3203 basic_block bb
= NULL
;
3207 if (regno
< FIRST_PSEUDO_REGISTER
)
3210 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3212 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3213 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3218 /* Return true if X contains a pseudo dying in INSN. */
3220 dead_pseudo_p (rtx x
, rtx insn
)
3227 return (insn
!= NULL_RTX
3228 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3229 code
= GET_CODE (x
);
3230 fmt
= GET_RTX_FORMAT (code
);
3231 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3235 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3238 else if (fmt
[i
] == 'E')
3240 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3241 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3248 /* Return true if INSN contains a dying pseudo in INSN right hand
3251 insn_rhs_dead_pseudo_p (rtx insn
)
3253 rtx set
= single_set (insn
);
3255 gcc_assert (set
!= NULL
);
3256 return dead_pseudo_p (SET_SRC (set
), insn
);
3259 /* Return true if any init insn of REGNO contains a dying pseudo in
3260 insn right hand side. */
3262 init_insn_rhs_dead_pseudo_p (int regno
)
3264 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3269 return insn_rhs_dead_pseudo_p (insns
);
3270 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3271 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3276 /* Entry function of LRA constraint pass. Return true if the
3277 constraint pass did change the code. */
3279 lra_constraints (bool first_p
)
3282 int i
, hard_regno
, new_insns_num
;
3283 unsigned int min_len
, new_min_len
, uid
;
3284 rtx set
, x
, reg
, dest_reg
;
3285 basic_block last_bb
;
3286 bitmap_head equiv_insn_bitmap
;
3289 lra_constraint_iter
++;
3290 if (lra_dump_file
!= NULL
)
3291 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3292 lra_constraint_iter
);
3293 lra_constraint_iter_after_spill
++;
3294 if (lra_constraint_iter_after_spill
> MAX_CONSTRAINT_ITERATION_NUMBER
)
3296 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3297 MAX_CONSTRAINT_ITERATION_NUMBER
);
3299 lra_risky_transformations_p
= false;
3300 new_insn_uid_start
= get_max_uid ();
3301 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3302 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3303 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3304 if (lra_reg_info
[i
].nrefs
!= 0)
3306 ira_reg_equiv
[i
].profitable_p
= true;
3307 reg
= regno_reg_rtx
[i
];
3308 if ((hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3310 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3312 for (j
= 0; j
< nregs
; j
++)
3313 df_set_regs_ever_live (hard_regno
+ j
, true);
3315 else if ((x
= get_equiv_substitution (reg
)) != reg
)
3317 bool pseudo_p
= contains_reg_p (x
, false, false);
3320 /* We don't use DF for compilation speed sake. So it is
3321 problematic to update live info when we use an
3322 equivalence containing pseudos in more than one BB. */
3323 if ((pseudo_p
&& multi_block_pseudo_p (i
))
3324 /* If it is not a reverse equivalence, we check that a
3325 pseudo in rhs of the init insn is not dying in the
3326 insn. Otherwise, the live info at the beginning of
3327 the corresponding BB might be wrong after we
3328 removed the insn. When the equiv can be a
3329 constant, the right hand side of the init insn can
3331 || (! ((insn
= ira_reg_equiv
[i
].init_insns
) != NULL_RTX
3333 && (set
= single_set (insn
)) != NULL_RTX
3334 && REG_P (SET_DEST (set
))
3335 && (int) REGNO (SET_DEST (set
)) == i
)
3336 && init_insn_rhs_dead_pseudo_p (i
)))
3337 ira_reg_equiv
[i
].defined_p
= false;
3338 else if (! first_p
&& pseudo_p
)
3339 /* After RTL transformation, we can not guarantee that
3340 pseudo in the substitution was not reloaded which
3341 might make equivalence invalid. For example, in
3348 the memory address register was reloaded before the
3350 ira_reg_equiv
[i
].defined_p
= false;
3351 if (contains_reg_p (x
, false, true))
3352 ira_reg_equiv
[i
].profitable_p
= false;
3353 if (get_equiv_substitution (reg
) != reg
)
3354 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
3357 /* We should add all insns containing pseudos which should be
3358 substituted by their equivalences. */
3359 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
3360 lra_push_insn_by_uid (uid
);
3361 lra_eliminate (false);
3362 min_len
= lra_insn_stack_length ();
3366 while ((new_min_len
= lra_insn_stack_length ()) != 0)
3368 curr_insn
= lra_pop_insn ();
3370 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
3371 if (curr_bb
!= last_bb
)
3374 bb_reload_num
= lra_curr_reload_num
;
3376 if (min_len
> new_min_len
)
3378 min_len
= new_min_len
;
3381 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
3383 ("Max. number of generated reload insns per insn is achieved (%d)\n",
3384 MAX_RELOAD_INSNS_NUMBER
);
3386 if (DEBUG_INSN_P (curr_insn
))
3388 /* We need to check equivalence in debug insn and change
3389 pseudo to the equivalent value if necessary. */
3390 curr_id
= lra_get_insn_recog_data (curr_insn
);
3391 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
3392 && loc_equivalence_change_p (curr_id
->operand_loc
[0]))
3394 lra_update_insn_regno_info (curr_insn
);
3398 else if (INSN_P (curr_insn
))
3400 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
3402 dest_reg
= SET_DEST (set
);
3403 /* The equivalence pseudo could be set up as SUBREG in a
3404 case when it is a call restore insn in a mode
3405 different from the pseudo mode. */
3406 if (GET_CODE (dest_reg
) == SUBREG
)
3407 dest_reg
= SUBREG_REG (dest_reg
);
3408 if ((REG_P (dest_reg
)
3409 && (x
= get_equiv_substitution (dest_reg
)) != dest_reg
3410 /* Remove insns which set up a pseudo whose value
3411 can not be changed. Such insns might be not in
3412 init_insns because we don't update equiv data
3413 during insn transformations.
3415 As an example, let suppose that a pseudo got
3416 hard register and on the 1st pass was not
3417 changed to equivalent constant. We generate an
3418 additional insn setting up the pseudo because of
3419 secondary memory movement. Then the pseudo is
3420 spilled and we use the equiv constant. In this
3421 case we should remove the additional insn and
3422 this insn is not init_insns list. */
3423 && (! MEM_P (x
) || MEM_READONLY_P (x
)
3424 || in_list_p (curr_insn
,
3426 [REGNO (dest_reg
)].init_insns
)))
3427 || (((x
= get_equiv_substitution (SET_SRC (set
)))
3429 && in_list_p (curr_insn
,
3431 [REGNO (SET_SRC (set
))].init_insns
)))
3433 /* This is equiv init insn of pseudo which did not get a
3434 hard register -- remove the insn. */
3435 if (lra_dump_file
!= NULL
)
3437 fprintf (lra_dump_file
,
3438 " Removing equiv init insn %i (freq=%d)\n",
3439 INSN_UID (curr_insn
),
3440 BLOCK_FOR_INSN (curr_insn
)->frequency
);
3441 debug_rtl_slim (lra_dump_file
,
3442 curr_insn
, curr_insn
, -1, 0);
3444 if (contains_reg_p (x
, true, false))
3445 lra_risky_transformations_p
= true;
3446 lra_set_insn_deleted (curr_insn
);
3450 curr_id
= lra_get_insn_recog_data (curr_insn
);
3451 curr_static_id
= curr_id
->insn_static_data
;
3452 init_curr_insn_input_reloads ();
3453 init_curr_operand_mode ();
3454 if (curr_insn_transform ())
3456 /* Check non-transformed insns too for equiv change as USE
3457 or CLOBBER don't need reloads but can contain pseudos
3458 being changed on their equivalences. */
3459 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
3460 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
3462 lra_update_insn_regno_info (curr_insn
);
3467 bitmap_clear (&equiv_insn_bitmap
);
3468 /* If we used a new hard regno, changed_p should be true because the
3469 hard reg is assigned to a new pseudo. */
3470 #ifdef ENABLE_CHECKING
3473 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3474 if (lra_reg_info
[i
].nrefs
!= 0
3475 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3477 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3479 for (j
= 0; j
< nregs
; j
++)
3480 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
3487 /* Initiate the LRA constraint pass. It is done once per
3490 lra_constraints_init (void)
3494 /* Finalize the LRA constraint pass. It is done once per
3497 lra_constraints_finish (void)
3503 /* This page contains code to do inheritance/split
3506 /* Number of reloads passed so far in current EBB. */
3507 static int reloads_num
;
3509 /* Number of calls passed so far in current EBB. */
3510 static int calls_num
;
3512 /* Current reload pseudo check for validity of elements in
3514 static int curr_usage_insns_check
;
3516 /* Info about last usage of registers in EBB to do inheritance/split
3517 transformation. Inheritance transformation is done from a spilled
3518 pseudo and split transformations from a hard register or a pseudo
3519 assigned to a hard register. */
3522 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
3523 value INSNS is valid. The insns is chain of optional debug insns
3524 and a finishing non-debug insn using the corresponding reg. */
3526 /* Value of global reloads_num at the last insn in INSNS. */
3528 /* Value of global reloads_nums at the last insn in INSNS. */
3530 /* It can be true only for splitting. And it means that the restore
3531 insn should be put after insn given by the following member. */
3533 /* Next insns in the current EBB which use the original reg and the
3534 original reg value is not changed between the current insn and
3535 the next insns. In order words, e.g. for inheritance, if we need
3536 to use the original reg value again in the next insns we can try
3537 to use the value in a hard register from a reload insn of the
3542 /* Map: regno -> corresponding pseudo usage insns. */
3543 static struct usage_insns
*usage_insns
;
3546 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
3548 usage_insns
[regno
].check
= curr_usage_insns_check
;
3549 usage_insns
[regno
].insns
= insn
;
3550 usage_insns
[regno
].reloads_num
= reloads_num
;
3551 usage_insns
[regno
].calls_num
= calls_num
;
3552 usage_insns
[regno
].after_p
= after_p
;
3555 /* The function is used to form list REGNO usages which consists of
3556 optional debug insns finished by a non-debug insn using REGNO.
3557 RELOADS_NUM is current number of reload insns processed so far. */
3559 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
3561 rtx next_usage_insns
;
3563 if (usage_insns
[regno
].check
== curr_usage_insns_check
3564 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
3565 && DEBUG_INSN_P (insn
))
3567 /* Check that we did not add the debug insn yet. */
3568 if (next_usage_insns
!= insn
3569 && (GET_CODE (next_usage_insns
) != INSN_LIST
3570 || XEXP (next_usage_insns
, 0) != insn
))
3571 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
3574 else if (NONDEBUG_INSN_P (insn
))
3575 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
3577 usage_insns
[regno
].check
= 0;
3580 /* Replace all references to register OLD_REGNO in *LOC with pseudo
3581 register NEW_REG. Return true if any change was made. */
3583 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
3586 bool result
= false;
3594 code
= GET_CODE (x
);
3595 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
3597 enum machine_mode mode
= GET_MODE (*loc
);
3598 enum machine_mode inner_mode
= GET_MODE (new_reg
);
3600 if (mode
!= inner_mode
)
3602 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
3603 || ! SCALAR_INT_MODE_P (inner_mode
))
3604 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
3606 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
3612 /* Scan all the operand sub-expressions. */
3613 fmt
= GET_RTX_FORMAT (code
);
3614 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3618 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
3621 else if (fmt
[i
] == 'E')
3623 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3624 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
3631 /* Return first non-debug insn in list USAGE_INSNS. */
3633 skip_usage_debug_insns (rtx usage_insns
)
3637 /* Skip debug insns. */
3638 for (insn
= usage_insns
;
3639 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
3640 insn
= XEXP (insn
, 1))
3645 /* Return true if we need secondary memory moves for insn in
3646 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
3649 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
3650 rtx usage_insns ATTRIBUTE_UNUSED
)
3652 #ifndef SECONDARY_MEMORY_NEEDED
3655 rtx insn
, set
, dest
;
3658 if (inher_cl
== ALL_REGS
3659 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
3661 lra_assert (INSN_P (insn
));
3662 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
3664 dest
= SET_DEST (set
);
3667 lra_assert (inher_cl
!= NO_REGS
);
3668 cl
= get_reg_class (REGNO (dest
));
3669 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
3670 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
3674 /* Registers involved in inheritance/split in the current EBB
3675 (inheritance/split pseudos and original registers). */
3676 static bitmap_head check_only_regs
;
3678 /* Do inheritance transformations for insn INSN, which defines (if
3679 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
3680 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
3681 form as the "insns" field of usage_insns. Return true if we
3682 succeed in such transformation.
3684 The transformations look like:
3687 ... p <- i (new insn)
3689 <- ... p ... <- ... i ...
3691 ... i <- p (new insn)
3692 <- ... p ... <- ... i ...
3694 <- ... p ... <- ... i ...
3695 where p is a spilled original pseudo and i is a new inheritance pseudo.
3698 The inheritance pseudo has the smallest class of two classes CL and
3699 class of ORIGINAL REGNO. */
3701 inherit_reload_reg (bool def_p
, int original_regno
,
3702 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
3704 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
3705 rtx original_reg
= regno_reg_rtx
[original_regno
];
3706 rtx new_reg
, new_insns
, usage_insn
;
3708 lra_assert (! usage_insns
[original_regno
].after_p
);
3709 if (lra_dump_file
!= NULL
)
3710 fprintf (lra_dump_file
,
3711 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
3712 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
3714 if (lra_dump_file
!= NULL
)
3716 fprintf (lra_dump_file
,
3717 " Rejecting inheritance for %d "
3718 "because of disjoint classes %s and %s\n",
3719 original_regno
, reg_class_names
[cl
],
3720 reg_class_names
[rclass
]);
3721 fprintf (lra_dump_file
,
3722 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3726 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
3727 /* We don't use a subset of two classes because it can be
3728 NO_REGS. This transformation is still profitable in most
3729 cases even if the classes are not intersected as register
3730 move is probably cheaper than a memory load. */
3731 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
3733 if (lra_dump_file
!= NULL
)
3734 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
3735 reg_class_names
[cl
], reg_class_names
[rclass
]);
3739 if (check_secondary_memory_needed_p (cl
, next_usage_insns
))
3741 /* Reject inheritance resulting in secondary memory moves.
3742 Otherwise, there is a danger in LRA cycling. Also such
3743 transformation will be unprofitable. */
3744 if (lra_dump_file
!= NULL
)
3746 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
3747 rtx set
= single_set (insn
);
3749 lra_assert (set
!= NULL_RTX
);
3751 rtx dest
= SET_DEST (set
);
3753 lra_assert (REG_P (dest
));
3754 fprintf (lra_dump_file
,
3755 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
3756 "as secondary mem is needed\n",
3757 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
3758 original_regno
, reg_class_names
[cl
]);
3759 fprintf (lra_dump_file
,
3760 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3764 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
3765 rclass
, "inheritance");
3768 emit_move_insn (original_reg
, new_reg
);
3770 emit_move_insn (new_reg
, original_reg
);
3771 new_insns
= get_insns ();
3773 if (NEXT_INSN (new_insns
) != NULL_RTX
)
3775 if (lra_dump_file
!= NULL
)
3777 fprintf (lra_dump_file
,
3778 " Rejecting inheritance %d->%d "
3779 "as it results in 2 or more insns:\n",
3780 original_regno
, REGNO (new_reg
));
3781 debug_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
3782 fprintf (lra_dump_file
,
3783 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3787 substitute_pseudo (&insn
, original_regno
, new_reg
);
3788 lra_update_insn_regno_info (insn
);
3790 /* We now have a new usage insn for original regno. */
3791 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
3792 if (lra_dump_file
!= NULL
)
3793 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
3794 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
3795 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
3796 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
3797 bitmap_set_bit (&check_only_regs
, original_regno
);
3798 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
3800 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
3801 "Add original<-inheritance");
3803 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
3804 "Add inheritance<-original");
3805 while (next_usage_insns
!= NULL_RTX
)
3807 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
3809 usage_insn
= next_usage_insns
;
3810 lra_assert (NONDEBUG_INSN_P (usage_insn
));
3811 next_usage_insns
= NULL
;
3815 usage_insn
= XEXP (next_usage_insns
, 0);
3816 lra_assert (DEBUG_INSN_P (usage_insn
));
3817 next_usage_insns
= XEXP (next_usage_insns
, 1);
3819 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
3820 lra_update_insn_regno_info (usage_insn
);
3821 if (lra_dump_file
!= NULL
)
3823 fprintf (lra_dump_file
,
3824 " Inheritance reuse change %d->%d (bb%d):\n",
3825 original_regno
, REGNO (new_reg
),
3826 BLOCK_FOR_INSN (usage_insn
)->index
);
3827 debug_rtl_slim (lra_dump_file
, usage_insn
, usage_insn
,
3831 if (lra_dump_file
!= NULL
)
3832 fprintf (lra_dump_file
,
3833 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3837 /* Return true if we need a caller save/restore for pseudo REGNO which
3838 was assigned to a hard register. */
3840 need_for_call_save_p (int regno
)
3842 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
3843 return (usage_insns
[regno
].calls_num
< calls_num
3844 && (overlaps_hard_reg_set_p
3846 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])));
3849 /* Global registers occuring in the current EBB. */
3850 static bitmap_head ebb_global_regs
;
3852 /* Return true if we need a split for hard register REGNO or pseudo
3853 REGNO which was assigned to a hard register.
3854 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
3855 used for reloads since the EBB end. It is an approximation of the
3856 used hard registers in the split range. The exact value would
3857 require expensive calculations. If we were aggressive with
3858 splitting because of the approximation, the split pseudo will save
3859 the same hard register assignment and will be removed in the undo
3860 pass. We still need the approximation because too aggressive
3861 splitting would result in too inaccurate cost calculation in the
3862 assignment pass because of too many generated moves which will be
3863 probably removed in the undo pass. */
3865 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
3867 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
3869 lra_assert (hard_regno
>= 0);
3870 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
3871 /* Don't split eliminable hard registers, otherwise we can
3872 split hard registers like hard frame pointer, which
3873 lives on BB start/end according to DF-infrastructure,
3874 when there is a pseudo assigned to the register and
3875 living in the same BB. */
3876 && (regno
>= FIRST_PSEUDO_REGISTER
3877 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
3878 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
3879 /* We need at least 2 reloads to make pseudo splitting
3880 profitable. We should provide hard regno splitting in
3881 any case to solve 1st insn scheduling problem when
3882 moving hard register definition up might result in
3883 impossibility to find hard register for reload pseudo of
3884 small register class. */
3885 && (usage_insns
[regno
].reloads_num
3886 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
3887 && (regno
< FIRST_PSEUDO_REGISTER
3888 /* For short living pseudos, spilling + inheritance can
3889 be considered a substitution for splitting.
3890 Therefore we do not splitting for local pseudos. It
3891 decreases also aggressiveness of splitting. The
3892 minimal number of references is chosen taking into
3893 account that for 2 references splitting has no sense
3894 as we can just spill the pseudo. */
3895 || (regno
>= FIRST_PSEUDO_REGISTER
3896 && lra_reg_info
[regno
].nrefs
> 3
3897 && bitmap_bit_p (&ebb_global_regs
, regno
))))
3898 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
3901 /* Return class for the split pseudo created from original pseudo with
3902 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
3903 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
3904 results in no secondary memory movements. */
3905 static enum reg_class
3906 choose_split_class (enum reg_class allocno_class
,
3907 int hard_regno ATTRIBUTE_UNUSED
,
3908 enum machine_mode mode ATTRIBUTE_UNUSED
)
3910 #ifndef SECONDARY_MEMORY_NEEDED
3911 return allocno_class
;
3914 enum reg_class cl
, best_cl
= NO_REGS
;
3915 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
3916 = REGNO_REG_CLASS (hard_regno
);
3918 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
3919 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
3920 return allocno_class
;
3922 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
3924 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
3925 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
3926 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
3927 && (best_cl
== NO_REGS
3928 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
3934 /* Do split transformations for insn INSN, which defines or uses
3935 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
3936 the EBB next uses ORIGINAL_REGNO; it has the same form as the
3937 "insns" field of usage_insns.
3939 The transformations look like:
3942 ... s <- p (new insn -- save)
3944 ... p <- s (new insn -- restore)
3945 <- ... p ... <- ... p ...
3947 <- ... p ... <- ... p ...
3948 ... s <- p (new insn -- save)
3950 ... p <- s (new insn -- restore)
3951 <- ... p ... <- ... p ...
3953 where p is an original pseudo got a hard register or a hard
3954 register and s is a new split pseudo. The save is put before INSN
3955 if BEFORE_P is true. Return true if we succeed in such
3958 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
3960 enum reg_class rclass
;
3963 rtx new_reg
, save
, restore
, usage_insn
;
3967 if (original_regno
< FIRST_PSEUDO_REGISTER
)
3969 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
3970 hard_regno
= original_regno
;
3971 call_save_p
= false;
3975 hard_regno
= reg_renumber
[original_regno
];
3976 rclass
= lra_get_allocno_class (original_regno
);
3977 original_reg
= regno_reg_rtx
[original_regno
];
3978 call_save_p
= need_for_call_save_p (original_regno
);
3980 original_reg
= regno_reg_rtx
[original_regno
];
3981 lra_assert (hard_regno
>= 0);
3982 if (lra_dump_file
!= NULL
)
3983 fprintf (lra_dump_file
,
3984 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
3987 enum machine_mode sec_mode
;
3989 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3990 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (original_reg
));
3992 sec_mode
= GET_MODE (original_reg
);
3994 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3999 rclass
= choose_split_class (rclass
, hard_regno
,
4000 GET_MODE (original_reg
));
4001 if (rclass
== NO_REGS
)
4003 if (lra_dump_file
!= NULL
)
4005 fprintf (lra_dump_file
,
4006 " Rejecting split of %d(%s): "
4007 "no good reg class for %d(%s)\n",
4009 reg_class_names
[lra_get_allocno_class (original_regno
)],
4011 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4014 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4018 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4020 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4022 save
= emit_spill_move (true, new_reg
, original_reg
);
4023 if (NEXT_INSN (save
) != NULL_RTX
)
4025 lra_assert (! call_save_p
);
4026 if (lra_dump_file
!= NULL
)
4030 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4031 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4032 debug_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4033 fprintf (lra_dump_file
,
4034 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4038 restore
= emit_spill_move (false, new_reg
, original_reg
);
4039 if (NEXT_INSN (restore
) != NULL_RTX
)
4041 lra_assert (! call_save_p
);
4042 if (lra_dump_file
!= NULL
)
4044 fprintf (lra_dump_file
,
4045 " Rejecting split %d->%d "
4046 "resulting in > 2 %s restore insns:\n",
4047 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4048 debug_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4049 fprintf (lra_dump_file
,
4050 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4054 after_p
= usage_insns
[original_regno
].after_p
;
4055 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4056 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4057 bitmap_set_bit (&check_only_regs
, original_regno
);
4058 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4061 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4063 usage_insn
= next_usage_insns
;
4066 usage_insn
= XEXP (next_usage_insns
, 0);
4067 lra_assert (DEBUG_INSN_P (usage_insn
));
4068 next_usage_insns
= XEXP (next_usage_insns
, 1);
4069 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4070 lra_update_insn_regno_info (usage_insn
);
4071 if (lra_dump_file
!= NULL
)
4073 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4074 original_regno
, REGNO (new_reg
));
4075 debug_rtl_slim (lra_dump_file
, usage_insn
, usage_insn
,
4079 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4080 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4081 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4082 after_p
? restore
: NULL_RTX
,
4084 ? "Add reg<-save" : "Add reg<-split");
4085 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4086 before_p
? NULL_RTX
: save
,
4088 ? "Add save<-reg" : "Add split<-reg");
4089 if (lra_dump_file
!= NULL
)
4090 fprintf (lra_dump_file
,
4091 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4095 /* Recognize that we need a split transformation for insn INSN, which
4096 defines or uses REGNO in its insn biggest MODE (we use it only if
4097 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4098 hard registers which might be used for reloads since the EBB end.
4099 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4100 uid before starting INSN processing. Return true if we succeed in
4101 such transformation. */
4103 split_if_necessary (int regno
, enum machine_mode mode
,
4104 HARD_REG_SET potential_reload_hard_regs
,
4105 bool before_p
, rtx insn
, int max_uid
)
4109 rtx next_usage_insns
;
4111 if (regno
< FIRST_PSEUDO_REGISTER
)
4112 nregs
= hard_regno_nregs
[regno
][mode
];
4113 for (i
= 0; i
< nregs
; i
++)
4114 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4115 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4116 /* To avoid processing the register twice or more. */
4117 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4118 && INSN_UID (next_usage_insns
) < max_uid
)
4119 || (GET_CODE (next_usage_insns
) == INSN_LIST
4120 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4121 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4122 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4127 /* Check only registers living at the current program point in the
4129 static bitmap_head live_regs
;
4131 /* Update live info in EBB given by its HEAD and TAIL insns after
4132 inheritance/split transformation. The function removes dead moves
4135 update_ebb_live_info (rtx head
, rtx tail
)
4142 basic_block last_bb
, prev_bb
, curr_bb
;
4144 struct lra_insn_reg
*reg
;
4148 last_bb
= BLOCK_FOR_INSN (tail
);
4150 for (curr_insn
= tail
;
4151 curr_insn
!= PREV_INSN (head
);
4152 curr_insn
= prev_insn
)
4154 prev_insn
= PREV_INSN (curr_insn
);
4155 /* We need to process empty blocks too. They contain
4156 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4157 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4159 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4160 if (curr_bb
!= prev_bb
)
4162 if (prev_bb
!= NULL
)
4164 /* Update df_get_live_in (prev_bb): */
4165 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4166 if (bitmap_bit_p (&live_regs
, j
))
4167 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4169 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4171 if (curr_bb
!= last_bb
)
4173 /* Update df_get_live_out (curr_bb): */
4174 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4176 live_p
= bitmap_bit_p (&live_regs
, j
);
4178 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4179 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4185 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4187 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4191 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4193 if (! NONDEBUG_INSN_P (curr_insn
))
4195 curr_id
= lra_get_insn_recog_data (curr_insn
);
4197 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4198 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4199 && bitmap_bit_p (&check_only_regs
, regno
)
4200 && ! bitmap_bit_p (&live_regs
, regno
))
4202 /* See which defined values die here. */
4203 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4204 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4205 bitmap_clear_bit (&live_regs
, reg
->regno
);
4206 /* Mark each used value as live. */
4207 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4208 if (reg
->type
== OP_IN
4209 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4210 bitmap_set_bit (&live_regs
, reg
->regno
);
4211 /* It is quite important to remove dead move insns because it
4212 means removing dead store. We don't need to process them for
4216 if (lra_dump_file
!= NULL
)
4218 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4219 debug_rtl_slim (lra_dump_file
, curr_insn
, curr_insn
, -1, 0);
4221 lra_set_insn_deleted (curr_insn
);
4226 /* The structure describes info to do an inheritance for the current
4227 insn. We need to collect such info first before doing the
4228 transformations because the transformations change the insn
4229 internal representation. */
4232 /* Original regno. */
4234 /* Subsequent insns which can inherit original reg value. */
4238 /* Array containing all info for doing inheritance from the current
4240 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4242 /* Number elements in the previous array. */
4243 static int to_inherit_num
;
4245 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4246 structure to_inherit. */
4248 add_to_inherit (int regno
, rtx insns
)
4252 for (i
= 0; i
< to_inherit_num
; i
++)
4253 if (to_inherit
[i
].regno
== regno
)
4255 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4256 to_inherit
[to_inherit_num
].regno
= regno
;
4257 to_inherit
[to_inherit_num
++].insns
= insns
;
4260 /* Return the last non-debug insn in basic block BB, or the block begin
4263 get_last_insertion_point (basic_block bb
)
4267 FOR_BB_INSNS_REVERSE (bb
, insn
)
4268 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4273 /* Set up RES by registers living on edges FROM except the edge (FROM,
4274 TO) or by registers set up in a jump insn in BB FROM. */
4276 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4279 struct lra_insn_reg
*reg
;
4283 lra_assert (to
!= NULL
);
4285 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4287 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4288 last
= get_last_insertion_point (from
);
4289 if (! JUMP_P (last
))
4291 curr_id
= lra_get_insn_recog_data (last
);
4292 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4293 if (reg
->type
!= OP_IN
)
4294 bitmap_set_bit (res
, reg
->regno
);
4297 /* Used as a temporary results of some bitmap calculations. */
4298 static bitmap_head temp_bitmap
;
4300 /* Do inheritance/split transformations in EBB starting with HEAD and
4301 finishing on TAIL. We process EBB insns in the reverse order.
4302 Return true if we did any inheritance/split transformation in the
4305 We should avoid excessive splitting which results in worse code
4306 because of inaccurate cost calculations for spilling new split
4307 pseudos in such case. To achieve this we do splitting only if
4308 register pressure is high in given basic block and there are reload
4309 pseudos requiring hard registers. We could do more register
4310 pressure calculations at any given program point to avoid necessary
4311 splitting even more but it is to expensive and the current approach
4312 works well enough. */
4314 inherit_in_ebb (rtx head
, rtx tail
)
4316 int i
, src_regno
, dst_regno
, nregs
;
4317 bool change_p
, succ_p
;
4318 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4320 struct lra_insn_reg
*reg
;
4321 basic_block last_processed_bb
, curr_bb
= NULL
;
4322 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
4326 bool head_p
, after_p
;
4329 curr_usage_insns_check
++;
4330 reloads_num
= calls_num
= 0;
4331 bitmap_clear (&check_only_regs
);
4332 last_processed_bb
= NULL
;
4333 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4334 CLEAR_HARD_REG_SET (live_hard_regs
);
4335 /* We don't process new insns generated in the loop. */
4336 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
4338 prev_insn
= PREV_INSN (curr_insn
);
4339 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
4340 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4341 if (last_processed_bb
!= curr_bb
)
4343 /* We are at the end of BB. Add qualified living
4344 pseudos for potential splitting. */
4345 to_process
= df_get_live_out (curr_bb
);
4346 if (last_processed_bb
!= NULL
)
4348 /* We are somewhere in the middle of EBB. */
4349 get_live_on_other_edges (curr_bb
, last_processed_bb
,
4351 to_process
= &temp_bitmap
;
4353 last_processed_bb
= curr_bb
;
4354 last_insn
= get_last_insertion_point (curr_bb
);
4355 after_p
= (! JUMP_P (last_insn
)
4356 && (! CALL_P (last_insn
)
4357 || (find_reg_note (last_insn
,
4358 REG_NORETURN
, NULL_RTX
) == NULL_RTX
4359 && ! SIBLING_CALL_P (last_insn
))));
4360 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
4361 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
4362 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
4363 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4364 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4366 if ((int) j
>= lra_constraint_new_regno_start
)
4368 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4370 if (j
< FIRST_PSEUDO_REGISTER
)
4371 SET_HARD_REG_BIT (live_hard_regs
, j
);
4373 add_to_hard_reg_set (&live_hard_regs
,
4374 PSEUDO_REGNO_MODE (j
),
4376 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
4380 src_regno
= dst_regno
= -1;
4381 if (NONDEBUG_INSN_P (curr_insn
)
4382 && (set
= single_set (curr_insn
)) != NULL_RTX
4383 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
4385 src_regno
= REGNO (SET_SRC (set
));
4386 dst_regno
= REGNO (SET_DEST (set
));
4388 if (src_regno
< lra_constraint_new_regno_start
4389 && src_regno
>= FIRST_PSEUDO_REGISTER
4390 && reg_renumber
[src_regno
] < 0
4391 && dst_regno
>= lra_constraint_new_regno_start
4392 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
4394 /* 'reload_pseudo <- original_pseudo'. */
4397 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4398 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
4399 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
4400 curr_insn
, next_usage_insns
);
4404 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4405 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4406 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4407 reg_class_contents
[cl
]);
4409 else if (src_regno
>= lra_constraint_new_regno_start
4410 && dst_regno
< lra_constraint_new_regno_start
4411 && dst_regno
>= FIRST_PSEUDO_REGISTER
4412 && reg_renumber
[dst_regno
] < 0
4413 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
4414 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4415 && (next_usage_insns
4416 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4419 /* 'original_pseudo <- reload_pseudo'. */
4420 if (! JUMP_P (curr_insn
)
4421 && inherit_reload_reg (true, dst_regno
, cl
,
4422 curr_insn
, next_usage_insns
))
4425 usage_insns
[dst_regno
].check
= 0;
4426 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4427 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4428 reg_class_contents
[cl
]);
4430 else if (INSN_P (curr_insn
))
4432 int max_uid
= get_max_uid ();
4434 curr_id
= lra_get_insn_recog_data (curr_insn
);
4436 /* Process insn definitions. */
4437 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4438 if (reg
->type
!= OP_IN
4439 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4441 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
4442 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
4443 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4444 && (next_usage_insns
4445 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4447 struct lra_insn_reg
*r
;
4449 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
4450 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
4452 /* Don't do inheritance if the pseudo is also
4453 used in the insn. */
4455 /* We can not do inheritance right now
4456 because the current insn reg info (chain
4457 regs) can change after that. */
4458 add_to_inherit (dst_regno
, next_usage_insns
);
4460 /* We can not process one reg twice here because of
4461 usage_insns invalidation. */
4462 if ((dst_regno
< FIRST_PSEUDO_REGISTER
4463 || reg_renumber
[dst_regno
] >= 0)
4464 && ! reg
->subreg_p
&& reg
->type
== OP_OUT
)
4468 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
4469 potential_reload_hard_regs
,
4470 false, curr_insn
, max_uid
))
4472 CLEAR_HARD_REG_SET (s
);
4473 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
4474 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
4476 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
4477 reg_renumber
[dst_regno
]);
4478 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
4480 /* We should invalidate potential inheritance or
4481 splitting for the current insn usages to the next
4482 usage insns (see code below) as the output pseudo
4484 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
4485 && reg_renumber
[dst_regno
] < 0)
4486 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
4487 && (dst_regno
< FIRST_PSEUDO_REGISTER
4488 || reg_renumber
[dst_regno
] >= 0)))
4491 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
4492 usage_insns
[dst_regno
].check
= 0;
4495 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
4496 for (i
= 0; i
< nregs
; i
++)
4497 usage_insns
[dst_regno
+ i
].check
= 0;
4501 if (! JUMP_P (curr_insn
))
4502 for (i
= 0; i
< to_inherit_num
; i
++)
4503 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
4504 ALL_REGS
, curr_insn
,
4505 to_inherit
[i
].insns
))
4507 if (CALL_P (curr_insn
))
4509 rtx cheap
, pat
, dest
, restore
;
4510 int regno
, hard_regno
;
4513 if ((cheap
= find_reg_note (curr_insn
,
4514 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
4515 && ((cheap
= XEXP (cheap
, 0)), true)
4516 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
4517 && (hard_regno
= reg_renumber
[regno
]) >= 0
4518 /* If there are pending saves/restores, the
4519 optimization is not worth. */
4520 && usage_insns
[regno
].calls_num
== calls_num
- 1
4521 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
4523 /* Restore the pseudo from the call result as
4524 REG_RETURNED note says that the pseudo value is
4525 in the call result and the pseudo is an argument
4527 pat
= PATTERN (curr_insn
);
4528 if (GET_CODE (pat
) == PARALLEL
)
4529 pat
= XVECEXP (pat
, 0, 0);
4530 dest
= SET_DEST (pat
);
4532 emit_move_insn (cheap
, copy_rtx (dest
));
4533 restore
= get_insns ();
4535 lra_process_new_insns (curr_insn
, NULL
, restore
,
4536 "Inserting call parameter restore");
4537 /* We don't need to save/restore of the pseudo from
4539 usage_insns
[regno
].calls_num
= calls_num
;
4540 bitmap_set_bit (&check_only_regs
, regno
);
4544 /* Process insn usages. */
4545 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4546 if ((reg
->type
!= OP_OUT
4547 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
4548 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4550 if (src_regno
>= FIRST_PSEUDO_REGISTER
4551 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
4553 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4554 && (next_usage_insns
4555 = usage_insns
[src_regno
].insns
) != NULL_RTX
4556 && NONDEBUG_INSN_P (curr_insn
))
4557 add_to_inherit (src_regno
, next_usage_insns
);
4560 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
4562 else if (src_regno
< FIRST_PSEUDO_REGISTER
4563 || reg_renumber
[src_regno
] >= 0)
4566 rtx use_insn
= curr_insn
;
4568 before_p
= (JUMP_P (curr_insn
)
4569 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
4570 if (NONDEBUG_INSN_P (curr_insn
)
4571 && split_if_necessary (src_regno
, reg
->biggest_mode
,
4572 potential_reload_hard_regs
,
4573 before_p
, curr_insn
, max_uid
))
4576 lra_risky_transformations_p
= true;
4579 usage_insns
[src_regno
].check
= 0;
4581 use_insn
= PREV_INSN (curr_insn
);
4583 if (NONDEBUG_INSN_P (curr_insn
))
4585 if (src_regno
< FIRST_PSEUDO_REGISTER
)
4586 add_to_hard_reg_set (&live_hard_regs
,
4587 reg
->biggest_mode
, src_regno
);
4589 add_to_hard_reg_set (&live_hard_regs
,
4590 PSEUDO_REGNO_MODE (src_regno
),
4591 reg_renumber
[src_regno
]);
4593 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
4596 for (i
= 0; i
< to_inherit_num
; i
++)
4598 src_regno
= to_inherit
[i
].regno
;
4599 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
4600 curr_insn
, to_inherit
[i
].insns
))
4603 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4606 /* We reached the start of the current basic block. */
4607 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
4608 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
4610 /* We reached the beginning of the current block -- do
4611 rest of spliting in the current BB. */
4612 to_process
= df_get_live_in (curr_bb
);
4613 if (BLOCK_FOR_INSN (head
) != curr_bb
)
4615 /* We are somewhere in the middle of EBB. */
4616 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
4617 curr_bb
, &temp_bitmap
);
4618 to_process
= &temp_bitmap
;
4621 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4623 if ((int) j
>= lra_constraint_new_regno_start
)
4625 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4626 && usage_insns
[j
].check
== curr_usage_insns_check
4627 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
4629 if (need_for_split_p (potential_reload_hard_regs
, j
))
4631 if (lra_dump_file
!= NULL
&& head_p
)
4633 fprintf (lra_dump_file
,
4634 " ----------------------------------\n");
4637 if (split_reg (false, j
, bb_note (curr_bb
),
4641 usage_insns
[j
].check
= 0;
4649 /* The maximal number of inheritance/split passes in LRA. It should
4650 be more 1 in order to perform caller saves transformations and much
4651 less MAX_CONSTRAINT_ITERATION_NUMBER to prevent LRA to do as many
4652 as permitted constraint passes in some complicated cases. The
4653 first inheritance/split pass has a biggest impact on generated code
4654 quality. Each subsequent affects generated code in less degree.
4655 For example, the 3rd pass does not change generated SPEC2000 code
4656 at all on x86-64. */
4657 #define MAX_INHERITANCE_PASSES 2
4659 #if MAX_INHERITANCE_PASSES <= 0 \
4660 || MAX_INHERITANCE_PASSES >= MAX_CONSTRAINT_ITERATION_NUMBER - 8
4661 #error wrong MAX_INHERITANCE_PASSES value
4664 /* This value affects EBB forming. If probability of edge from EBB to
4665 a BB is not greater than the following value, we don't add the BB
4667 #define EBB_PROBABILITY_CUTOFF (REG_BR_PROB_BASE / 2)
4669 /* Current number of inheritance/split iteration. */
4670 int lra_inheritance_iter
;
4672 /* Entry function for inheritance/split pass. */
4674 lra_inheritance (void)
4677 basic_block bb
, start_bb
;
4680 lra_inheritance_iter
++;
4681 if (lra_inheritance_iter
> MAX_INHERITANCE_PASSES
)
4683 timevar_push (TV_LRA_INHERITANCE
);
4684 if (lra_dump_file
!= NULL
)
4685 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
4686 lra_inheritance_iter
);
4687 curr_usage_insns_check
= 0;
4688 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
4689 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
4690 usage_insns
[i
].check
= 0;
4691 bitmap_initialize (&check_only_regs
, ®_obstack
);
4692 bitmap_initialize (&live_regs
, ®_obstack
);
4693 bitmap_initialize (&temp_bitmap
, ®_obstack
);
4694 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
4698 if (lra_dump_file
!= NULL
)
4699 fprintf (lra_dump_file
, "EBB");
4700 /* Form a EBB starting with BB. */
4701 bitmap_clear (&ebb_global_regs
);
4702 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
4705 if (lra_dump_file
!= NULL
)
4706 fprintf (lra_dump_file
, " %d", bb
->index
);
4707 if (bb
->next_bb
== EXIT_BLOCK_PTR
|| LABEL_P (BB_HEAD (bb
->next_bb
)))
4709 e
= find_fallthru_edge (bb
->succs
);
4712 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
4716 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
4717 if (lra_dump_file
!= NULL
)
4718 fprintf (lra_dump_file
, "\n");
4719 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
4720 /* Remember that the EBB head and tail can change in
4722 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
4724 bitmap_clear (&ebb_global_regs
);
4725 bitmap_clear (&temp_bitmap
);
4726 bitmap_clear (&live_regs
);
4727 bitmap_clear (&check_only_regs
);
4730 timevar_pop (TV_LRA_INHERITANCE
);
4735 /* This page contains code to undo failed inheritance/split
4738 /* Current number of iteration undoing inheritance/split. */
4739 int lra_undo_inheritance_iter
;
4741 /* Fix BB live info LIVE after removing pseudos created on pass doing
4742 inheritance/split which are REMOVED_PSEUDOS. */
4744 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
4749 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
4750 if (bitmap_clear_bit (live
, regno
))
4751 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
4754 /* Return regno of the (subreg of) REG. Otherwise, return a negative
4759 if (GET_CODE (reg
) == SUBREG
)
4760 reg
= SUBREG_REG (reg
);
4766 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
4767 return true if we did any change. The undo transformations for
4768 inheritance looks like
4772 p <- i, i <- p, and i <- i3
4773 where p is original pseudo from which inheritance pseudo i was
4774 created, i and i3 are removed inheritance pseudos, i2 is another
4775 not removed inheritance pseudo. All split pseudos or other
4776 occurrences of removed inheritance pseudos are changed on the
4777 corresponding original pseudos.
4779 The function also schedules insns changed and created during
4780 inheritance/split pass for processing by the subsequent constraint
4783 remove_inheritance_pseudos (bitmap remove_pseudos
)
4786 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
4787 rtx set
, prev_set
, prev_insn
;
4788 bool change_p
, done_p
;
4790 change_p
= ! bitmap_empty_p (remove_pseudos
);
4791 /* We can not finish the function right away if CHANGE_P is true
4792 because we need to marks insns affected by previous
4793 inheritance/split pass for processing by the subsequent
4797 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
4798 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
4799 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
4801 if (! INSN_P (curr_insn
))
4804 sregno
= dregno
= -1;
4805 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
4806 && (set
= single_set (curr_insn
)) != NULL_RTX
)
4808 dregno
= get_regno (SET_DEST (set
));
4809 sregno
= get_regno (SET_SRC (set
));
4812 if (sregno
>= 0 && dregno
>= 0)
4814 if ((bitmap_bit_p (remove_pseudos
, sregno
)
4815 && (lra_reg_info
[sregno
].restore_regno
== dregno
4816 || (bitmap_bit_p (remove_pseudos
, dregno
)
4817 && (lra_reg_info
[sregno
].restore_regno
4818 == lra_reg_info
[dregno
].restore_regno
))))
4819 || (bitmap_bit_p (remove_pseudos
, dregno
)
4820 && lra_reg_info
[dregno
].restore_regno
== sregno
))
4821 /* One of the following cases:
4822 original <- removed inheritance pseudo
4823 removed inherit pseudo <- another removed inherit pseudo
4824 removed inherit pseudo <- original pseudo
4826 removed_split_pseudo <- original_reg
4827 original_reg <- removed_split_pseudo */
4829 if (lra_dump_file
!= NULL
)
4831 fprintf (lra_dump_file
, " Removing %s:\n",
4832 bitmap_bit_p (&lra_split_regs
, sregno
)
4833 || bitmap_bit_p (&lra_split_regs
, dregno
)
4834 ? "split" : "inheritance");
4835 debug_rtl_slim (lra_dump_file
,
4836 curr_insn
, curr_insn
, -1, 0);
4838 lra_set_insn_deleted (curr_insn
);
4841 else if (bitmap_bit_p (remove_pseudos
, sregno
)
4842 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
4844 /* Search the following pattern:
4845 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
4846 original_pseudo <- inherit_or_split_pseudo1
4847 where the 2nd insn is the current insn and
4848 inherit_or_split_pseudo2 is not removed. If it is found,
4849 change the current insn onto:
4850 original_pseudo <- inherit_or_split_pseudo2. */
4851 for (prev_insn
= PREV_INSN (curr_insn
);
4852 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
4853 prev_insn
= PREV_INSN (prev_insn
))
4855 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
4856 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
4857 /* There should be no subregs in insn we are
4858 searching because only the original reg might
4859 be in subreg when we changed the mode of
4860 load/store for splitting. */
4861 && REG_P (SET_DEST (prev_set
))
4862 && REG_P (SET_SRC (prev_set
))
4863 && (int) REGNO (SET_DEST (prev_set
)) == sregno
4864 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
4865 >= FIRST_PSEUDO_REGISTER
)
4866 /* As we consider chain of inheritance or
4867 splitting described in above comment we should
4868 check that sregno and prev_sregno were
4869 inheritance/split pseudos created from the
4870 same original regno. */
4871 && (lra_reg_info
[sregno
].restore_regno
4872 == lra_reg_info
[prev_sregno
].restore_regno
)
4873 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
4875 lra_assert (GET_MODE (SET_SRC (prev_set
))
4876 == GET_MODE (regno_reg_rtx
[sregno
]));
4877 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
4878 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
4880 SET_SRC (set
) = SET_SRC (prev_set
);
4881 lra_push_insn_and_update_insn_regno_info (curr_insn
);
4882 lra_set_used_insn_alternative_by_uid
4883 (INSN_UID (curr_insn
), -1);
4885 if (lra_dump_file
!= NULL
)
4887 fprintf (lra_dump_file
, " Change reload insn:\n");
4888 debug_rtl_slim (lra_dump_file
,
4889 curr_insn
, curr_insn
, -1, 0);
4896 struct lra_insn_reg
*reg
;
4897 bool restored_regs_p
= false;
4898 bool kept_regs_p
= false;
4900 curr_id
= lra_get_insn_recog_data (curr_insn
);
4901 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4904 restore_regno
= lra_reg_info
[regno
].restore_regno
;
4905 if (restore_regno
>= 0)
4907 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
4909 substitute_pseudo (&curr_insn
, regno
,
4910 regno_reg_rtx
[restore_regno
]);
4911 restored_regs_p
= true;
4917 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
4919 /* The instruction has changed since the previous
4920 constraints pass. */
4921 lra_push_insn_and_update_insn_regno_info (curr_insn
);
4922 lra_set_used_insn_alternative_by_uid
4923 (INSN_UID (curr_insn
), -1);
4925 else if (restored_regs_p
)
4926 /* The instruction has been restored to the form that
4927 it had during the previous constraints pass. */
4928 lra_update_insn_regno_info (curr_insn
);
4929 if (restored_regs_p
&& lra_dump_file
!= NULL
)
4931 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
4932 debug_rtl_slim (lra_dump_file
, curr_insn
, curr_insn
, -1, 0);
4940 /* Entry function for undoing inheritance/split transformation. Return true
4941 if we did any RTL change in this pass. */
4943 lra_undo_inheritance (void)
4946 int restore_regno
, hard_regno
;
4947 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
4948 bitmap_head remove_pseudos
;
4952 lra_undo_inheritance_iter
++;
4953 if (lra_undo_inheritance_iter
> MAX_INHERITANCE_PASSES
)
4955 if (lra_dump_file
!= NULL
)
4956 fprintf (lra_dump_file
,
4957 "\n********** Undoing inheritance #%d: **********\n\n",
4958 lra_undo_inheritance_iter
);
4959 bitmap_initialize (&remove_pseudos
, ®_obstack
);
4960 n_inherit
= n_all_inherit
= 0;
4961 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
4962 if (lra_reg_info
[regno
].restore_regno
>= 0)
4965 if (reg_renumber
[regno
] < 0)
4966 bitmap_set_bit (&remove_pseudos
, regno
);
4970 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
4971 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
4972 n_inherit
, n_all_inherit
,
4973 (double) n_inherit
/ n_all_inherit
* 100);
4974 n_split
= n_all_split
= 0;
4975 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
4976 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
4979 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
4980 ? reg_renumber
[restore_regno
] : restore_regno
);
4981 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
4982 bitmap_set_bit (&remove_pseudos
, regno
);
4986 if (lra_dump_file
!= NULL
)
4987 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
4988 regno
, restore_regno
);
4991 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
4992 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
4993 n_split
, n_all_split
,
4994 (double) n_split
/ n_all_split
* 100);
4995 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
4996 bitmap_clear (&remove_pseudos
);
4997 /* Clear restore_regnos. */
4998 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
4999 lra_reg_info
[regno
].restore_regno
= -1;
5000 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5001 lra_reg_info
[regno
].restore_regno
= -1;