1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || INSN_UID (curr_insn
) >= new_insn_uid_start
)
273 /* When we don't know what class will be used finally for reload
274 pseudos, we use ALL_REGS. */
275 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
276 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
277 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
278 lra_no_alloc_regs
)));
281 common_class
= ira_reg_class_subset
[rclass
][cl
];
282 if (new_class
!= NULL
)
283 *new_class
= common_class
;
284 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
287 /* Check that there are enough allocatable regs. */
288 class_size
= ira_class_hard_regs_num
[common_class
];
289 for (i
= 0; i
< class_size
; i
++)
291 hard_regno
= ira_class_hard_regs
[common_class
][i
];
292 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
295 for (j
= 0; j
< nregs
; j
++)
296 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
297 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
307 /* Return true if REGNO satisfies a memory constraint. */
311 return get_reg_class (regno
) == NO_REGS
;
314 /* If we have decided to substitute X with another value, return that
315 value, otherwise return X. */
317 get_equiv_substitution (rtx x
)
322 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
323 || ! ira_reg_equiv
[regno
].defined_p
324 || ! ira_reg_equiv
[regno
].profitable_p
325 || lra_get_regno_hard_regno (regno
) >= 0)
327 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
329 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
331 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
336 /* Set up curr_operand_mode. */
338 init_curr_operand_mode (void)
340 int nop
= curr_static_id
->n_operands
;
341 for (int i
= 0; i
< nop
; i
++)
343 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
344 if (mode
== VOIDmode
)
346 /* The .md mode for address operands is the mode of the
347 addressed value rather than the mode of the address itself. */
348 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
351 mode
= curr_static_id
->operand
[i
].mode
;
353 curr_operand_mode
[i
] = mode
;
359 /* The page contains code to reuse input reloads. */
361 /* Structure describes input reload of the current insns. */
364 /* Reloaded value. */
366 /* Reload pseudo used. */
370 /* The number of elements in the following array. */
371 static int curr_insn_input_reloads_num
;
372 /* Array containing info about input reloads. It is used to find the
373 same input reload and reuse the reload pseudo in this case. */
374 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
376 /* Initiate data concerning reuse of input reloads for the current
379 init_curr_insn_input_reloads (void)
381 curr_insn_input_reloads_num
= 0;
384 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
385 using TITLE. Output a new line if NL_P. */
387 change_class (int regno
, enum reg_class new_class
,
388 const char *title
, bool nl_p
)
390 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
);
391 if (lra_dump_file
!= NULL
)
392 fprintf (lra_dump_file
, "%s to class %s for r%d",
393 title
, reg_class_names
[new_class
], regno
);
394 setup_reg_classes (regno
, new_class
, NO_REGS
, new_class
);
395 if (lra_dump_file
!= NULL
&& nl_p
)
396 fprintf (lra_dump_file
, "\n");
399 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
400 created input reload pseudo (only if TYPE is not OP_OUT). The
401 result pseudo is returned through RESULT_REG. Return TRUE if we
402 created a new pseudo, FALSE if we reused the already created input
403 reload pseudo. Use TITLE to describe new registers for debug
406 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
407 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
410 enum reg_class new_class
;
415 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
418 /* Prevent reuse value of expression with side effects,
419 e.g. volatile memory. */
420 if (! side_effects_p (original
))
421 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
422 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
423 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
425 rtx reg
= curr_insn_input_reloads
[i
].reg
;
427 /* If input is equal to original and both are VOIDmode,
428 GET_MODE (reg) might be still different from mode.
429 Ensure we don't return *result_reg with wrong mode. */
430 if (GET_MODE (reg
) != mode
)
432 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
434 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
435 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
439 if (lra_dump_file
!= NULL
)
441 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
442 dump_value_slim (lra_dump_file
, original
, 1);
444 if (new_class
!= lra_get_allocno_class (regno
))
445 change_class (regno
, new_class
, ", change", false);
446 if (lra_dump_file
!= NULL
)
447 fprintf (lra_dump_file
, "\n");
450 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
451 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
452 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
453 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
459 /* The page contains code to extract memory address parts. */
461 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
463 ok_for_index_p_nonstrict (rtx reg
)
465 unsigned regno
= REGNO (reg
);
467 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
470 /* A version of regno_ok_for_base_p for use here, when all pseudos
471 should count as OK. Arguments as for regno_ok_for_base_p. */
473 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
474 enum rtx_code outer_code
, enum rtx_code index_code
)
476 unsigned regno
= REGNO (reg
);
478 if (regno
>= FIRST_PSEUDO_REGISTER
)
480 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
485 /* The page contains major code to choose the current insn alternative
486 and generate reloads for it. */
488 /* Return the offset from REGNO of the least significant register
491 This function is used to tell whether two registers satisfy
492 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
494 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
495 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
497 lra_constraint_offset (int regno
, enum machine_mode mode
)
499 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
500 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
501 && SCALAR_INT_MODE_P (mode
))
502 return hard_regno_nregs
[regno
][mode
] - 1;
506 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
507 if they are the same hard reg, and has special hacks for
508 auto-increment and auto-decrement. This is specifically intended for
509 process_alt_operands to use in determining whether two operands
510 match. X is the operand whose number is the lower of the two.
512 It is supposed that X is the output operand and Y is the input
513 operand. Y_HARD_REGNO is the final hard regno of register Y or
514 register in subreg Y as we know it now. Otherwise, it is a
517 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
520 RTX_CODE code
= GET_CODE (x
);
525 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
526 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
530 i
= get_hard_regno (x
);
534 if ((j
= y_hard_regno
) < 0)
537 i
+= lra_constraint_offset (i
, GET_MODE (x
));
538 j
+= lra_constraint_offset (j
, GET_MODE (y
));
543 /* If two operands must match, because they are really a single
544 operand of an assembler insn, then two post-increments are invalid
545 because the assembler insn would increment only once. On the
546 other hand, a post-increment matches ordinary indexing if the
547 post-increment is the output operand. */
548 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
549 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
551 /* Two pre-increments are invalid because the assembler insn would
552 increment only once. On the other hand, a pre-increment matches
553 ordinary indexing if the pre-increment is the input operand. */
554 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
555 || GET_CODE (y
) == PRE_MODIFY
)
556 return operands_match_p (x
, XEXP (y
, 0), -1);
560 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
561 && x
== SUBREG_REG (y
))
563 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
564 && SUBREG_REG (x
) == y
)
567 /* Now we have disposed of all the cases in which different rtx
569 if (code
!= GET_CODE (y
))
572 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
573 if (GET_MODE (x
) != GET_MODE (y
))
582 return XEXP (x
, 0) == XEXP (y
, 0);
584 return XSTR (x
, 0) == XSTR (y
, 0);
590 /* Compare the elements. If any pair of corresponding elements fail
591 to match, return false for the whole things. */
593 fmt
= GET_RTX_FORMAT (code
);
594 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
600 if (XWINT (x
, i
) != XWINT (y
, i
))
605 if (XINT (x
, i
) != XINT (y
, i
))
610 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
619 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
621 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
623 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
629 /* It is believed that rtx's at this level will never
630 contain anything but integers and other rtx's, except for
631 within LABEL_REFs and SYMBOL_REFs. */
639 /* True if X is a constant that can be forced into the constant pool.
640 MODE is the mode of the operand, or VOIDmode if not known. */
641 #define CONST_POOL_OK_P(MODE, X) \
642 ((MODE) != VOIDmode \
644 && GET_CODE (X) != HIGH \
645 && !targetm.cannot_force_const_mem (MODE, X))
647 /* True if C is a non-empty register class that has too few registers
648 to be safely used as a reload target class. */
649 #define SMALL_REGISTER_CLASS_P(C) \
650 (reg_class_size [(C)] == 1 \
651 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
653 /* If REG is a reload pseudo, try to make its class satisfying CL. */
655 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
657 enum reg_class rclass
;
659 /* Do not make more accurate class from reloads generated. They are
660 mostly moves with a lot of constraints. Making more accurate
661 class may results in very narrow class and impossibility of find
662 registers for several reloads of one insn. */
663 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
665 if (GET_CODE (reg
) == SUBREG
)
666 reg
= SUBREG_REG (reg
);
667 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
669 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
670 change_class (REGNO (reg
), rclass
, " Change", true);
673 /* Generate reloads for matching OUT and INS (array of input operand
674 numbers with end marker -1) with reg class GOAL_CLASS. Add input
675 and output reloads correspondingly to the lists *BEFORE and *AFTER.
676 OUT might be negative. In this case we generate input reloads for
677 matched input operands INS. */
679 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
680 rtx
*before
, rtx
*after
)
683 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
684 enum machine_mode inmode
, outmode
;
685 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
686 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
688 inmode
= curr_operand_mode
[ins
[0]];
689 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
690 push_to_sequence (*before
);
691 if (inmode
!= outmode
)
693 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
696 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
698 if (SCALAR_INT_MODE_P (inmode
))
699 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
701 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
702 LRA_SUBREG_P (new_out_reg
) = 1;
703 /* If the input reg is dying here, we can use the same hard
704 register for REG and IN_RTX. We do it only for original
705 pseudos as reload pseudos can die although original
706 pseudos still live where reload pseudos dies. */
707 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
708 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
709 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
714 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
716 if (SCALAR_INT_MODE_P (outmode
))
717 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
719 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
720 /* NEW_IN_REG is non-paradoxical subreg. We don't want
721 NEW_OUT_REG living above. We add clobber clause for
722 this. This is just a temporary clobber. We can remove
723 it at the end of LRA work. */
724 clobber
= emit_clobber (new_out_reg
);
725 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
726 LRA_SUBREG_P (new_in_reg
) = 1;
727 if (GET_CODE (in_rtx
) == SUBREG
)
729 rtx subreg_reg
= SUBREG_REG (in_rtx
);
731 /* If SUBREG_REG is dying here and sub-registers IN_RTX
732 and NEW_IN_REG are similar, we can use the same hard
733 register for REG and SUBREG_REG. */
734 if (REG_P (subreg_reg
)
735 && (int) REGNO (subreg_reg
) < lra_new_regno_start
736 && GET_MODE (subreg_reg
) == outmode
737 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
738 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
739 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
745 /* Pseudos have values -- see comments for lra_reg_info.
746 Different pseudos with the same value do not conflict even if
747 they live in the same place. When we create a pseudo we
748 assign value of original pseudo (if any) from which we
749 created the new pseudo. If we create the pseudo from the
750 input pseudo, the new pseudo will no conflict with the input
751 pseudo which is wrong when the input pseudo lives after the
752 insn and as the new pseudo value is changed by the insn
753 output. Therefore we create the new pseudo from the output.
755 We cannot reuse the current output register because we might
756 have a situation like "a <- a op b", where the constraints
757 force the second input operand ("b") to match the output
758 operand ("a"). "b" must then be copied into a new register
759 so that it doesn't clobber the current value of "a". */
761 new_in_reg
= new_out_reg
762 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
765 /* In operand can be got from transformations before processing insn
766 constraints. One example of such transformations is subreg
767 reloading (see function simplify_operand_subreg). The new
768 pseudos created by the transformations might have inaccurate
769 class (ALL_REGS) and we should make their classes more
771 narrow_reload_pseudo_class (in_rtx
, goal_class
);
772 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
773 *before
= get_insns ();
775 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
778 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
779 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
780 *curr_id
->operand_loc
[in
] = new_in_reg
;
782 lra_update_dups (curr_id
, ins
);
785 /* See a comment for the input operand above. */
786 narrow_reload_pseudo_class (out_rtx
, goal_class
);
787 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
790 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
792 *after
= get_insns ();
795 *curr_id
->operand_loc
[out
] = new_out_reg
;
796 lra_update_dup (curr_id
, out
);
799 /* Return register class which is union of all reg classes in insn
800 constraint alternative string starting with P. */
801 static enum reg_class
802 reg_class_from_constraints (const char *p
)
805 enum reg_class op_class
= NO_REGS
;
808 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
815 op_class
= (reg_class_subunion
816 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
822 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
826 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
828 #ifdef EXTRA_CONSTRAINT_STR
829 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
831 = (reg_class_subunion
832 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
839 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
842 while ((p
+= len
), c
);
846 /* If OP is a register, return the class of the register as per
847 get_reg_class, otherwise return NO_REGS. */
848 static inline enum reg_class
849 get_op_class (rtx op
)
851 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
854 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
855 otherwise. If modes of MEM_PSEUDO and VAL are different, use
856 SUBREG for VAL to make them equal. */
858 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
860 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
862 lra_assert (GET_MODE_SIZE (GET_MODE (mem_pseudo
))
863 >= GET_MODE_SIZE (GET_MODE (val
)));
866 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
867 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
869 LRA_SUBREG_P (val
) = 1;
873 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
874 LRA_SUBREG_P (mem_pseudo
) = 1;
878 ? gen_move_insn (mem_pseudo
, val
)
879 : gen_move_insn (val
, mem_pseudo
));
882 /* Process a special case insn (register move), return true if we
883 don't need to process it anymore. INSN should be a single set
884 insn. Set up that RTL was changed through CHANGE_P and macro
885 SECONDARY_MEMORY_NEEDED says to use secondary memory through
888 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
891 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
892 enum reg_class dclass
, sclass
, secondary_class
;
893 enum machine_mode sreg_mode
;
894 secondary_reload_info sri
;
896 lra_assert (curr_insn_set
!= NULL_RTX
);
897 dreg
= dest
= SET_DEST (curr_insn_set
);
898 sreg
= src
= SET_SRC (curr_insn_set
);
899 if (GET_CODE (dest
) == SUBREG
)
900 dreg
= SUBREG_REG (dest
);
901 if (GET_CODE (src
) == SUBREG
)
902 sreg
= SUBREG_REG (src
);
903 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
905 sclass
= dclass
= NO_REGS
;
907 dclass
= get_reg_class (REGNO (dreg
));
908 if (dclass
== ALL_REGS
)
909 /* ALL_REGS is used for new pseudos created by transformations
910 like reload of SUBREG_REG (see function
911 simplify_operand_subreg). We don't know their class yet. We
912 should figure out the class from processing the insn
913 constraints not in this fast path function. Even if ALL_REGS
914 were a right class for the pseudo, secondary_... hooks usually
915 are not define for ALL_REGS. */
917 sreg_mode
= GET_MODE (sreg
);
920 sclass
= get_reg_class (REGNO (sreg
));
921 if (sclass
== ALL_REGS
)
922 /* See comments above. */
924 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
926 #ifdef SECONDARY_MEMORY_NEEDED
927 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
928 #ifdef SECONDARY_MEMORY_NEEDED_MODE
929 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
930 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
938 if (! REG_P (dreg
) || ! REG_P (sreg
))
941 sri
.icode
= CODE_FOR_nothing
;
943 secondary_class
= NO_REGS
;
944 /* Set up hard register for a reload pseudo for hook
945 secondary_reload because some targets just ignore unassigned
946 pseudos in the hook. */
947 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
949 dregno
= REGNO (dreg
);
950 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
954 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
956 sregno
= REGNO (sreg
);
957 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
961 if (sclass
!= NO_REGS
)
963 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
964 (reg_class_t
) sclass
,
965 GET_MODE (src
), &sri
);
966 if (sclass
== NO_REGS
967 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
968 && dclass
!= NO_REGS
))
970 enum reg_class old_sclass
= secondary_class
;
971 secondary_reload_info old_sri
= sri
;
974 sri
.icode
= CODE_FOR_nothing
;
977 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
978 (reg_class_t
) dclass
,
980 /* Check the target hook consistency. */
982 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
983 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
984 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
987 reg_renumber
[sregno
] = -1;
989 reg_renumber
[dregno
] = -1;
990 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
994 if (secondary_class
!= NO_REGS
)
995 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
999 if (old_sreg
!= sreg
)
1000 sreg
= copy_rtx (sreg
);
1001 if (sri
.icode
== CODE_FOR_nothing
)
1002 lra_emit_move (new_reg
, sreg
);
1005 enum reg_class scratch_class
;
1007 scratch_class
= (reg_class_from_constraints
1008 (insn_data
[sri
.icode
].operand
[2].constraint
));
1009 scratch_reg
= (lra_create_new_reg_with_unique_value
1010 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1011 scratch_class
, "scratch"));
1012 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1013 sreg
, scratch_reg
));
1015 before
= get_insns ();
1017 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1018 if (new_reg
!= NULL_RTX
)
1020 if (GET_CODE (src
) == SUBREG
)
1021 SUBREG_REG (src
) = new_reg
;
1023 SET_SRC (curr_insn_set
) = new_reg
;
1027 if (lra_dump_file
!= NULL
)
1029 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1030 dump_insn_slim (lra_dump_file
, curr_insn
);
1032 lra_set_insn_deleted (curr_insn
);
1038 /* The following data describe the result of process_alt_operands.
1039 The data are used in curr_insn_transform to generate reloads. */
1041 /* The chosen reg classes which should be used for the corresponding
1043 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1044 /* True if the operand should be the same as another operand and that
1045 other operand does not need a reload. */
1046 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1047 /* True if the operand does not need a reload. */
1048 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1049 /* True if the operand can be offsetable memory. */
1050 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1051 /* The number of an operand to which given operand can be matched to. */
1052 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1053 /* The number of elements in the following array. */
1054 static int goal_alt_dont_inherit_ops_num
;
1055 /* Numbers of operands whose reload pseudos should not be inherited. */
1056 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1057 /* True if the insn commutative operands should be swapped. */
1058 static bool goal_alt_swapped
;
1059 /* The chosen insn alternative. */
1060 static int goal_alt_number
;
1062 /* The following five variables are used to choose the best insn
1063 alternative. They reflect final characteristics of the best
1066 /* Number of necessary reloads and overall cost reflecting the
1067 previous value and other unpleasantness of the best alternative. */
1068 static int best_losers
, best_overall
;
1069 /* Overall number hard registers used for reloads. For example, on
1070 some targets we need 2 general registers to reload DFmode and only
1071 one floating point register. */
1072 static int best_reload_nregs
;
1073 /* Overall number reflecting distances of previous reloading the same
1074 value. The distances are counted from the current BB start. It is
1075 used to improve inheritance chances. */
1076 static int best_reload_sum
;
1078 /* True if the current insn should have no correspondingly input or
1080 static bool no_input_reloads_p
, no_output_reloads_p
;
1082 /* True if we swapped the commutative operands in the current
1084 static int curr_swapped
;
1086 /* Arrange for address element *LOC to be a register of class CL.
1087 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1088 automodified value; handle that case by adding the required output
1089 reloads to list AFTER. Return true if the RTL was changed. */
1091 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1094 enum reg_class rclass
, new_class
;
1097 enum machine_mode mode
;
1098 bool before_p
= false;
1100 loc
= strip_subreg (loc
);
1102 mode
= GET_MODE (reg
);
1105 /* Always reload memory in an address even if the target supports
1107 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1112 regno
= REGNO (reg
);
1113 rclass
= get_reg_class (regno
);
1114 if ((*loc
= get_equiv_substitution (reg
)) != reg
)
1116 if (lra_dump_file
!= NULL
)
1118 fprintf (lra_dump_file
,
1119 "Changing pseudo %d in address of insn %u on equiv ",
1120 REGNO (reg
), INSN_UID (curr_insn
));
1121 dump_value_slim (lra_dump_file
, *loc
, 1);
1122 fprintf (lra_dump_file
, "\n");
1124 *loc
= copy_rtx (*loc
);
1126 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1129 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1130 mode
, reg
, cl
, "address", &new_reg
))
1133 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1135 change_class (regno
, new_class
, " Change", true);
1143 push_to_sequence (*before
);
1144 lra_emit_move (new_reg
, reg
);
1145 *before
= get_insns ();
1152 lra_emit_move (reg
, new_reg
);
1154 *after
= get_insns ();
1160 /* Make reloads for subreg in operand NOP with internal subreg mode
1161 REG_MODE, add new reloads for further processing. Return true if
1162 any reload was generated. */
1164 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1168 enum machine_mode mode
;
1170 rtx operand
= *curr_id
->operand_loc
[nop
];
1172 before
= after
= NULL_RTX
;
1174 if (GET_CODE (operand
) != SUBREG
)
1177 mode
= GET_MODE (operand
);
1178 reg
= SUBREG_REG (operand
);
1179 /* If we change address for paradoxical subreg of memory, the
1180 address might violate the necessary alignment or the access might
1181 be slow. So take this into consideration. We should not worry
1182 about access beyond allocated memory for paradoxical memory
1183 subregs as we don't substitute such equiv memory (see processing
1184 equivalences in function lra_constraints) and because for spilled
1185 pseudos we allocate stack memory enough for the biggest
1186 corresponding paradoxical subreg. */
1188 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1189 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1190 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1192 alter_subreg (curr_id
->operand_loc
[nop
], false);
1195 /* Put constant into memory when we have mixed modes. It generates
1196 a better code in most cases as it does not need a secondary
1197 reload memory. It also prevents LRA looping when LRA is using
1198 secondary reload memory again and again. */
1199 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1200 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1202 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1203 alter_subreg (curr_id
->operand_loc
[nop
], false);
1206 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1207 if there may be a problem accessing OPERAND in the outer
1210 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1211 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1212 /* Don't reload paradoxical subregs because we could be looping
1213 having repeatedly final regno out of hard regs range. */
1214 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1215 >= hard_regno_nregs
[hard_regno
][mode
])
1216 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1217 SUBREG_BYTE (operand
), mode
) < 0
1218 /* Don't reload subreg for matching reload. It is actually
1219 valid subreg in LRA. */
1220 && ! LRA_SUBREG_P (operand
))
1221 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1223 enum op_type type
= curr_static_id
->operand
[nop
].type
;
1224 /* The class will be defined later in curr_insn_transform. */
1225 enum reg_class rclass
1226 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1228 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1229 rclass
, "subreg reg", &new_reg
))
1231 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (new_reg
));
1233 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
))
1235 push_to_sequence (before
);
1236 lra_emit_move (new_reg
, reg
);
1237 before
= get_insns ();
1243 lra_emit_move (reg
, new_reg
);
1245 after
= get_insns ();
1249 SUBREG_REG (operand
) = new_reg
;
1250 lra_process_new_insns (curr_insn
, before
, after
,
1251 "Inserting subreg reload");
1257 /* Return TRUE if X refers for a hard register from SET. */
1259 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1261 int i
, j
, x_hard_regno
;
1262 enum machine_mode mode
;
1268 code
= GET_CODE (x
);
1269 mode
= GET_MODE (x
);
1273 code
= GET_CODE (x
);
1274 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1275 mode
= GET_MODE (x
);
1280 x_hard_regno
= get_hard_regno (x
);
1281 return (x_hard_regno
>= 0
1282 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1286 struct address_info ad
;
1288 decompose_mem_address (&ad
, x
);
1289 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1291 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1294 fmt
= GET_RTX_FORMAT (code
);
1295 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1299 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1302 else if (fmt
[i
] == 'E')
1304 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1305 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1312 /* Return true if OP is a spilled pseudo. */
1314 spilled_pseudo_p (rtx op
)
1317 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1320 /* Return true if X is a general constant. */
1322 general_constant_p (rtx x
)
1324 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1328 reg_in_class_p (rtx reg
, enum reg_class cl
)
1331 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1332 return in_class_p (reg
, cl
, NULL
);
1335 /* Major function to choose the current insn alternative and what
1336 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1337 negative we should consider only this alternative. Return false if
1338 we can not choose the alternative or find how to reload the
1341 process_alt_operands (int only_alternative
)
1344 int nop
, overall
, nalt
;
1345 int n_alternatives
= curr_static_id
->n_alternatives
;
1346 int n_operands
= curr_static_id
->n_operands
;
1347 /* LOSERS counts the operands that don't fit this alternative and
1348 would require loading. */
1350 /* REJECT is a count of how undesirable this alternative says it is
1351 if any reloading is required. If the alternative matches exactly
1352 then REJECT is ignored, but otherwise it gets this much counted
1353 against it in addition to the reloading needed. */
1355 /* The number of elements in the following array. */
1356 int early_clobbered_regs_num
;
1357 /* Numbers of operands which are early clobber registers. */
1358 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1359 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1360 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1361 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1362 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1363 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1364 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1365 /* The number of elements in the following array. */
1366 int curr_alt_dont_inherit_ops_num
;
1367 /* Numbers of operands whose reload pseudos should not be inherited. */
1368 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1370 /* The register when the operand is a subreg of register, otherwise the
1372 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1373 /* The register if the operand is a register or subreg of register,
1375 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1376 int hard_regno
[MAX_RECOG_OPERANDS
];
1377 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1378 int reload_nregs
, reload_sum
;
1382 /* Calculate some data common for all alternatives to speed up the
1384 for (nop
= 0; nop
< n_operands
; nop
++)
1386 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1387 /* The real hard regno of the operand after the allocation. */
1388 hard_regno
[nop
] = get_hard_regno (op
);
1390 operand_reg
[nop
] = op
;
1391 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1392 if (GET_CODE (operand_reg
[nop
]) == SUBREG
)
1394 operand_reg
[nop
] = SUBREG_REG (operand_reg
[nop
]);
1395 if (GET_MODE_SIZE (biggest_mode
[nop
])
1396 < GET_MODE_SIZE (GET_MODE (operand_reg
[nop
])))
1397 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1399 if (REG_P (operand_reg
[nop
]))
1400 no_subreg_reg_operand
[nop
] = operand_reg
[nop
];
1402 operand_reg
[nop
] = NULL_RTX
;
1405 /* The constraints are made of several alternatives. Each operand's
1406 constraint looks like foo,bar,... with commas separating the
1407 alternatives. The first alternatives for all operands go
1408 together, the second alternatives go together, etc.
1410 First loop over alternatives. */
1411 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1413 /* Loop over operands for one constraint alternative. */
1414 #if HAVE_ATTR_enabled
1415 if (curr_id
->alternative_enabled_p
!= NULL
1416 && ! curr_id
->alternative_enabled_p
[nalt
])
1420 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1424 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1425 for (nop
= 0; nop
< n_operands
; nop
++)
1426 reject
+= (curr_static_id
1427 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1428 early_clobbered_regs_num
= 0;
1430 for (nop
= 0; nop
< n_operands
; nop
++)
1434 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1435 bool win
, did_match
, offmemok
, early_clobber_p
;
1436 /* false => this operand can be reloaded somehow for this
1439 /* true => this operand can be reloaded if the alternative
1442 /* True if a constant forced into memory would be OK for
1445 enum reg_class this_alternative
, this_costly_alternative
;
1446 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1447 bool this_alternative_match_win
, this_alternative_win
;
1448 bool this_alternative_offmemok
;
1449 enum machine_mode mode
;
1451 opalt_num
= nalt
* n_operands
+ nop
;
1452 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1454 /* Fast track for no constraints at all. */
1455 curr_alt
[nop
] = NO_REGS
;
1456 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1457 curr_alt_win
[nop
] = true;
1458 curr_alt_match_win
[nop
] = false;
1459 curr_alt_offmemok
[nop
] = false;
1460 curr_alt_matches
[nop
] = -1;
1464 op
= no_subreg_reg_operand
[nop
];
1465 mode
= curr_operand_mode
[nop
];
1467 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1470 early_clobber_p
= false;
1471 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1473 this_costly_alternative
= this_alternative
= NO_REGS
;
1474 /* We update set of possible hard regs besides its class
1475 because reg class might be inaccurate. For example,
1476 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1477 is translated in HI_REGS because classes are merged by
1478 pairs and there is no accurate intermediate class. */
1479 CLEAR_HARD_REG_SET (this_alternative_set
);
1480 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1481 this_alternative_win
= false;
1482 this_alternative_match_win
= false;
1483 this_alternative_offmemok
= false;
1484 this_alternative_matches
= -1;
1486 /* An empty constraint should be excluded by the fast
1488 lra_assert (*p
!= 0 && *p
!= ',');
1490 /* Scan this alternative's specs for this operand; set WIN
1491 if the operand fits any letter in this alternative.
1492 Otherwise, clear BADOP if this operand could fit some
1493 letter after reloads, or set WINREG if this operand could
1494 fit after reloads provided the constraint allows some
1499 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1508 case '=': case '+': case '?': case '*': case '!':
1509 case ' ': case '\t':
1513 /* We only support one commutative marker, the first
1514 one. We already set commutative above. */
1518 early_clobber_p
= true;
1522 /* Ignore rest of this alternative. */
1526 case '0': case '1': case '2': case '3': case '4':
1527 case '5': case '6': case '7': case '8': case '9':
1532 m
= strtoul (p
, &end
, 10);
1535 lra_assert (nop
> m
);
1537 this_alternative_matches
= m
;
1538 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1539 /* We are supposed to match a previous operand.
1540 If we do, we win if that one did. If we do
1541 not, count both of the operands as losers.
1542 (This is too conservative, since most of the
1543 time only a single reload insn will be needed
1544 to make the two operands win. As a result,
1545 this alternative may be rejected when it is
1546 actually desirable.) */
1548 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1549 *curr_id
->operand_loc
[m
], m_hregno
))
1551 /* We should reject matching of an early
1552 clobber operand if the matching operand is
1553 not dying in the insn. */
1554 if (! curr_static_id
->operand
[m
].early_clobber
1555 || operand_reg
[nop
] == NULL_RTX
1556 || (find_regno_note (curr_insn
, REG_DEAD
,
1558 || REGNO (op
) == REGNO (operand_reg
[m
])))
1563 /* If we are matching a non-offsettable
1564 address where an offsettable address was
1565 expected, then we must reject this
1566 combination, because we can't reload
1568 if (curr_alt_offmemok
[m
]
1569 && MEM_P (*curr_id
->operand_loc
[m
])
1570 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1576 /* Operands don't match. Both operands must
1577 allow a reload register, otherwise we
1578 cannot make them match. */
1579 if (curr_alt
[m
] == NO_REGS
)
1581 /* Retroactively mark the operand we had to
1582 match as a loser, if it wasn't already and
1583 it wasn't matched to a register constraint
1584 (e.g it might be matched by memory). */
1586 && (operand_reg
[m
] == NULL_RTX
1587 || hard_regno
[m
] < 0))
1591 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1592 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1595 /* We prefer no matching alternatives because
1596 it gives more freedom in RA. */
1597 if (operand_reg
[nop
] == NULL_RTX
1598 || (find_regno_note (curr_insn
, REG_DEAD
,
1599 REGNO (operand_reg
[nop
]))
1603 /* If we have to reload this operand and some
1604 previous operand also had to match the same
1605 thing as this operand, we don't know how to do
1607 if (!match_p
|| !curr_alt_win
[m
])
1609 for (i
= 0; i
< nop
; i
++)
1610 if (curr_alt_matches
[i
] == m
)
1618 /* This can be fixed with reloads if the operand
1619 we are supposed to match can be fixed with
1622 this_alternative
= curr_alt
[m
];
1623 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1624 winreg
= this_alternative
!= NO_REGS
;
1629 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1631 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1632 IOR_HARD_REG_SET (this_alternative_set
,
1633 reg_class_contents
[cl
]);
1636 this_costly_alternative
1637 = reg_class_subunion
[this_costly_alternative
][cl
];
1638 IOR_HARD_REG_SET (this_costly_alternative_set
,
1639 reg_class_contents
[cl
]);
1645 case TARGET_MEM_CONSTRAINT
:
1646 if (MEM_P (op
) || spilled_pseudo_p (op
))
1648 /* We can put constant or pseudo value into memory
1649 to satisfy the constraint. */
1650 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1657 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1658 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1664 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1665 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1669 /* Memory op whose address is not offsettable. */
1672 && ! offsettable_nonstrict_memref_p (op
))
1676 /* Memory operand whose address is offsettable. */
1679 && offsettable_nonstrict_memref_p (op
))
1680 || spilled_pseudo_p (op
))
1682 /* We can put constant or pseudo value into memory
1683 or make memory address offsetable to satisfy the
1685 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1693 if (GET_CODE (op
) == CONST_DOUBLE
1694 || (GET_CODE (op
) == CONST_VECTOR
1695 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1701 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1702 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1707 if (CONST_SCALAR_INT_P (op
))
1711 if (general_constant_p (op
))
1716 if (CONST_SCALAR_INT_P (op
))
1728 if (CONST_INT_P (op
)
1729 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1734 /* This constraint should be excluded by the fast
1741 || general_constant_p (op
)
1742 || spilled_pseudo_p (op
))
1744 /* Drop through into 'r' case. */
1748 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1749 IOR_HARD_REG_SET (this_alternative_set
,
1750 reg_class_contents
[GENERAL_REGS
]);
1753 this_costly_alternative
1754 = (reg_class_subunion
1755 [this_costly_alternative
][GENERAL_REGS
]);
1756 IOR_HARD_REG_SET (this_costly_alternative_set
,
1757 reg_class_contents
[GENERAL_REGS
]);
1762 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1764 #ifdef EXTRA_CONSTRAINT_STR
1765 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1767 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1769 else if (spilled_pseudo_p (op
))
1772 /* If we didn't already win, we can reload
1773 constants via force_const_mem or put the
1774 pseudo value into memory, or make other
1775 memory by reloading the address like for
1777 if (CONST_POOL_OK_P (mode
, op
)
1778 || MEM_P (op
) || REG_P (op
))
1784 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1786 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1789 /* If we didn't already win, we can reload
1790 the address into a base register. */
1791 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1794 = reg_class_subunion
[this_alternative
][cl
];
1795 IOR_HARD_REG_SET (this_alternative_set
,
1796 reg_class_contents
[cl
]);
1799 this_costly_alternative
1800 = (reg_class_subunion
1801 [this_costly_alternative
][cl
]);
1802 IOR_HARD_REG_SET (this_costly_alternative_set
,
1803 reg_class_contents
[cl
]);
1809 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1815 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1816 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1817 IOR_HARD_REG_SET (this_alternative_set
,
1818 reg_class_contents
[cl
]);
1821 this_costly_alternative
1822 = reg_class_subunion
[this_costly_alternative
][cl
];
1823 IOR_HARD_REG_SET (this_costly_alternative_set
,
1824 reg_class_contents
[cl
]);
1827 if (mode
== BLKmode
)
1832 if (hard_regno
[nop
] >= 0
1833 && in_hard_reg_set_p (this_alternative_set
,
1834 mode
, hard_regno
[nop
]))
1836 else if (hard_regno
[nop
] < 0
1837 && in_class_p (op
, this_alternative
, NULL
))
1842 if (c
!= ' ' && c
!= '\t')
1843 costly_p
= c
== '*';
1845 while ((p
+= len
), c
);
1847 /* Record which operands fit this alternative. */
1850 this_alternative_win
= true;
1851 if (operand_reg
[nop
] != NULL_RTX
)
1853 if (hard_regno
[nop
] >= 0)
1855 if (in_hard_reg_set_p (this_costly_alternative_set
,
1856 mode
, hard_regno
[nop
]))
1861 /* Prefer won reg to spilled pseudo under other equal
1864 if (in_class_p (operand_reg
[nop
],
1865 this_costly_alternative
, NULL
))
1868 /* We simulate the behaviour of old reload here.
1869 Although scratches need hard registers and it
1870 might result in spilling other pseudos, no reload
1871 insns are generated for the scratches. So it
1872 might cost something but probably less than old
1873 reload pass believes. */
1874 if (lra_former_scratch_p (REGNO (operand_reg
[nop
])))
1875 reject
+= LRA_LOSER_COST_FACTOR
;
1879 this_alternative_match_win
= true;
1882 int const_to_mem
= 0;
1885 /* If this alternative asks for a specific reg class, see if there
1886 is at least one allocatable register in that class. */
1888 = (this_alternative
== NO_REGS
1889 || (hard_reg_set_subset_p
1890 (reg_class_contents
[this_alternative
],
1891 lra_no_alloc_regs
)));
1893 /* For asms, verify that the class for this alternative is possible
1894 for the mode that is specified. */
1895 if (!no_regs_p
&& REG_P (op
) && INSN_CODE (curr_insn
) < 0)
1898 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1899 if (HARD_REGNO_MODE_OK (i
, mode
)
1900 && in_hard_reg_set_p (reg_class_contents
[this_alternative
], mode
, i
))
1902 if (i
== FIRST_PSEUDO_REGISTER
)
1906 /* If this operand accepts a register, and if the
1907 register class has at least one allocatable register,
1908 then this operand can be reloaded. */
1909 if (winreg
&& !no_regs_p
)
1915 this_alternative_offmemok
= offmemok
;
1916 if (this_costly_alternative
!= NO_REGS
)
1918 /* If the operand is dying, has a matching constraint,
1919 and satisfies constraints of the matched operand
1920 which failed to satisfy the own constraints, we do
1921 not need to generate a reload insn for this
1923 if (!(this_alternative_matches
>= 0
1924 && !curr_alt_win
[this_alternative_matches
]
1926 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
1927 && (hard_regno
[nop
] >= 0
1928 ? in_hard_reg_set_p (this_alternative_set
,
1929 mode
, hard_regno
[nop
])
1930 : in_class_p (op
, this_alternative
, NULL
))))
1932 /* Strict_low_part requires to reload the register
1933 not the sub-register. In this case we should
1934 check that a final reload hard reg can hold the
1936 if (curr_static_id
->operand
[nop
].strict_low
1938 && hard_regno
[nop
] < 0
1939 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
1940 && ira_class_hard_regs_num
[this_alternative
] > 0
1941 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
1942 [this_alternative
][0],
1947 if (operand_reg
[nop
] != NULL_RTX
1948 /* Output operands and matched input operands are
1949 not inherited. The following conditions do not
1950 exactly describe the previous statement but they
1951 are pretty close. */
1952 && curr_static_id
->operand
[nop
].type
!= OP_OUT
1953 && (this_alternative_matches
< 0
1954 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
1956 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
1960 if (last_reload
> bb_reload_num
)
1961 reload_sum
+= last_reload
- bb_reload_num
;
1963 /* If this is a constant that is reloaded into the
1964 desired class by copying it to memory first, count
1965 that as another reload. This is consistent with
1966 other code and is required to avoid choosing another
1967 alternative when the constant is moved into memory.
1968 Note that the test here is precisely the same as in
1969 the code below that calls force_const_mem. */
1970 if (CONST_POOL_OK_P (mode
, op
)
1971 && ((targetm
.preferred_reload_class
1972 (op
, this_alternative
) == NO_REGS
)
1973 || no_input_reloads_p
))
1980 /* Alternative loses if it requires a type of reload not
1981 permitted for this insn. We can always reload
1982 objects with a REG_UNUSED note. */
1983 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
1984 && no_output_reloads_p
1985 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
1986 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
1987 && no_input_reloads_p
&& ! const_to_mem
))
1990 /* Check strong discouragement of reload of non-constant
1991 into class THIS_ALTERNATIVE. */
1992 if (! CONSTANT_P (op
) && ! no_regs_p
1993 && (targetm
.preferred_reload_class
1994 (op
, this_alternative
) == NO_REGS
1995 || (curr_static_id
->operand
[nop
].type
== OP_OUT
1996 && (targetm
.preferred_output_reload_class
1997 (op
, this_alternative
) == NO_REGS
))))
1998 reject
+= LRA_MAX_REJECT
;
2000 if (MEM_P (op
) && offmemok
)
2002 /* If we know offset and this non-offsetable memory,
2003 something wrong with this memory and it is better
2004 to try other memory possibilities. */
2005 if (MEM_OFFSET_KNOWN_P (op
))
2006 reject
+= LRA_MAX_REJECT
;
2008 else if (! (const_to_mem
&& constmemok
))
2010 /* We prefer to reload pseudos over reloading other
2011 things, since such reloads may be able to be
2012 eliminated later. So bump REJECT in other cases.
2013 Don't do this in the case where we are forcing a
2014 constant into memory and it will then win since
2015 we don't want to have a different alternative
2017 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2022 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2024 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2025 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2028 /* We are trying to spill pseudo into memory. It is
2029 usually more costly than moving to a hard register
2030 although it might takes the same number of
2032 if (no_regs_p
&& REG_P (op
))
2035 #ifdef SECONDARY_MEMORY_NEEDED
2036 /* If reload requires moving value through secondary
2037 memory, it will need one more insn at least. */
2038 if (this_alternative
!= NO_REGS
2039 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2040 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2041 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2043 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2044 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2048 /* Input reloads can be inherited more often than output
2049 reloads can be removed, so penalize output
2051 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2056 if (early_clobber_p
)
2058 /* ??? We check early clobbers after processing all operands
2059 (see loop below) and there we update the costs more.
2060 Should we update the cost (may be approximately) here
2061 because of early clobber register reloads or it is a rare
2062 or non-important thing to be worth to do it. */
2063 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2064 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2066 if (lra_dump_file
!= NULL
)
2067 fprintf (lra_dump_file
,
2068 " alt=%d,overall=%d,losers=%d -- reject\n",
2069 nalt
, overall
, losers
);
2073 curr_alt
[nop
] = this_alternative
;
2074 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2075 curr_alt_win
[nop
] = this_alternative_win
;
2076 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2077 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2078 curr_alt_matches
[nop
] = this_alternative_matches
;
2080 if (this_alternative_matches
>= 0
2081 && !did_match
&& !this_alternative_win
)
2082 curr_alt_win
[this_alternative_matches
] = false;
2084 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2085 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2087 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2088 /* Prevent processing non-move insns. */
2089 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2090 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2091 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2092 && REG_P (no_subreg_reg_operand
[0])
2093 && REG_P (no_subreg_reg_operand
[1])
2094 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2095 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2096 || (! curr_alt_win
[0] && curr_alt_win
[1]
2097 && REG_P (no_subreg_reg_operand
[1])
2098 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2099 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2100 && REG_P (no_subreg_reg_operand
[0])
2101 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2102 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2103 no_subreg_reg_operand
[1])
2104 || (targetm
.preferred_reload_class
2105 (no_subreg_reg_operand
[1],
2106 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2107 /* If it is a result of recent elimination in move
2108 insn we can transform it into an add still by
2109 using this alternative. */
2110 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2111 /* We have a move insn and a new reload insn will be similar
2112 to the current insn. We should avoid such situation as it
2113 results in LRA cycling. */
2114 overall
+= LRA_MAX_REJECT
;
2116 curr_alt_dont_inherit_ops_num
= 0;
2117 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2119 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2120 HARD_REG_SET temp_set
;
2122 i
= early_clobbered_nops
[nop
];
2123 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2124 || hard_regno
[i
] < 0)
2126 lra_assert (operand_reg
[i
] != NULL_RTX
);
2127 clobbered_hard_regno
= hard_regno
[i
];
2128 CLEAR_HARD_REG_SET (temp_set
);
2129 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2130 first_conflict_j
= last_conflict_j
= -1;
2131 for (j
= 0; j
< n_operands
; j
++)
2133 /* We don't want process insides of match_operator and
2134 match_parallel because otherwise we would process
2135 their operands once again generating a wrong
2137 || curr_static_id
->operand
[j
].is_operator
)
2139 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2140 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2142 /* If we don't reload j-th operand, check conflicts. */
2143 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2144 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2146 if (first_conflict_j
< 0)
2147 first_conflict_j
= j
;
2148 last_conflict_j
= j
;
2150 if (last_conflict_j
< 0)
2152 /* If earlyclobber operand conflicts with another
2153 non-matching operand which is actually the same register
2154 as the earlyclobber operand, it is better to reload the
2155 another operand as an operand matching the earlyclobber
2156 operand can be also the same. */
2157 if (first_conflict_j
== last_conflict_j
2158 && operand_reg
[last_conflict_j
]
2159 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2160 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2162 curr_alt_win
[last_conflict_j
] = false;
2163 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2166 /* Early clobber was already reflected in REJECT. */
2167 lra_assert (reject
> 0);
2169 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2173 /* We need to reload early clobbered register and the
2174 matched registers. */
2175 for (j
= 0; j
< n_operands
; j
++)
2176 if (curr_alt_matches
[j
] == i
)
2178 curr_alt_match_win
[j
] = false;
2180 overall
+= LRA_LOSER_COST_FACTOR
;
2182 if (! curr_alt_match_win
[i
])
2183 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2186 /* Remember pseudos used for match reloads are never
2188 lra_assert (curr_alt_matches
[i
] >= 0);
2189 curr_alt_win
[curr_alt_matches
[i
]] = false;
2191 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2193 /* Early clobber was already reflected in REJECT. */
2194 lra_assert (reject
> 0);
2196 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2199 if (lra_dump_file
!= NULL
)
2200 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2201 nalt
, overall
, losers
, reload_nregs
);
2203 /* If this alternative can be made to work by reloading, and it
2204 needs less reloading than the others checked so far, record
2205 it as the chosen goal for reloading. */
2206 if ((best_losers
!= 0 && losers
== 0)
2207 || (((best_losers
== 0 && losers
== 0)
2208 || (best_losers
!= 0 && losers
!= 0))
2209 && (best_overall
> overall
2210 || (best_overall
== overall
2211 /* If the cost of the reloads is the same,
2212 prefer alternative which requires minimal
2213 number of reload regs. */
2214 && (reload_nregs
< best_reload_nregs
2215 || (reload_nregs
== best_reload_nregs
2216 && (best_reload_sum
< reload_sum
2217 || (best_reload_sum
== reload_sum
2218 && nalt
< goal_alt_number
))))))))
2220 for (nop
= 0; nop
< n_operands
; nop
++)
2222 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2223 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2224 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2225 goal_alt
[nop
] = curr_alt
[nop
];
2226 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2228 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2229 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2230 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2231 goal_alt_swapped
= curr_swapped
;
2232 best_overall
= overall
;
2233 best_losers
= losers
;
2234 best_reload_nregs
= reload_nregs
;
2235 best_reload_sum
= reload_sum
;
2236 goal_alt_number
= nalt
;
2239 /* Everything is satisfied. Do not process alternatives
2248 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2249 space AS, and check that each pseudo has the proper kind of hard
2252 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2253 rtx addr
, addr_space_t as
)
2255 #ifdef GO_IF_LEGITIMATE_ADDRESS
2256 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2257 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2263 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2267 /* Return whether address AD is valid. */
2270 valid_address_p (struct address_info
*ad
)
2272 /* Some ports do not check displacements for eliminable registers,
2273 so we replace them temporarily with the elimination target. */
2274 rtx saved_base_reg
= NULL_RTX
;
2275 rtx saved_index_reg
= NULL_RTX
;
2276 rtx
*base_term
= strip_subreg (ad
->base_term
);
2277 rtx
*index_term
= strip_subreg (ad
->index_term
);
2278 if (base_term
!= NULL
)
2280 saved_base_reg
= *base_term
;
2281 lra_eliminate_reg_if_possible (base_term
);
2282 if (ad
->base_term2
!= NULL
)
2283 *ad
->base_term2
= *ad
->base_term
;
2285 if (index_term
!= NULL
)
2287 saved_index_reg
= *index_term
;
2288 lra_eliminate_reg_if_possible (index_term
);
2290 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2291 if (saved_base_reg
!= NULL_RTX
)
2293 *base_term
= saved_base_reg
;
2294 if (ad
->base_term2
!= NULL
)
2295 *ad
->base_term2
= *ad
->base_term
;
2297 if (saved_index_reg
!= NULL_RTX
)
2298 *index_term
= saved_index_reg
;
2302 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2304 base_plus_disp_to_reg (struct address_info
*ad
)
2309 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2310 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2311 get_index_code (ad
));
2312 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2314 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2318 /* Return true if we can add a displacement to address AD, even if that
2319 makes the address invalid. The fix-up code requires any new address
2320 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2322 can_add_disp_p (struct address_info
*ad
)
2324 return (!ad
->autoinc_p
2325 && ad
->segment
== NULL
2326 && ad
->base
== ad
->base_term
2327 && ad
->disp
== ad
->disp_term
);
2330 /* Make equiv substitution in address AD. Return true if a substitution
2333 equiv_address_substitution (struct address_info
*ad
)
2335 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2336 HOST_WIDE_INT disp
, scale
;
2339 base_term
= strip_subreg (ad
->base_term
);
2340 if (base_term
== NULL
)
2341 base_reg
= new_base_reg
= NULL_RTX
;
2344 base_reg
= *base_term
;
2345 new_base_reg
= get_equiv_substitution (base_reg
);
2347 index_term
= strip_subreg (ad
->index_term
);
2348 if (index_term
== NULL
)
2349 index_reg
= new_index_reg
= NULL_RTX
;
2352 index_reg
= *index_term
;
2353 new_index_reg
= get_equiv_substitution (index_reg
);
2355 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2359 if (lra_dump_file
!= NULL
)
2361 fprintf (lra_dump_file
, "Changing address in insn %d ",
2362 INSN_UID (curr_insn
));
2363 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2365 if (base_reg
!= new_base_reg
)
2367 if (REG_P (new_base_reg
))
2369 *base_term
= new_base_reg
;
2372 else if (GET_CODE (new_base_reg
) == PLUS
2373 && REG_P (XEXP (new_base_reg
, 0))
2374 && CONST_INT_P (XEXP (new_base_reg
, 1))
2375 && can_add_disp_p (ad
))
2377 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2378 *base_term
= XEXP (new_base_reg
, 0);
2381 if (ad
->base_term2
!= NULL
)
2382 *ad
->base_term2
= *ad
->base_term
;
2384 if (index_reg
!= new_index_reg
)
2386 if (REG_P (new_index_reg
))
2388 *index_term
= new_index_reg
;
2391 else if (GET_CODE (new_index_reg
) == PLUS
2392 && REG_P (XEXP (new_index_reg
, 0))
2393 && CONST_INT_P (XEXP (new_index_reg
, 1))
2394 && can_add_disp_p (ad
)
2395 && (scale
= get_index_scale (ad
)))
2397 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2398 *index_term
= XEXP (new_index_reg
, 0);
2404 if (ad
->disp
!= NULL
)
2405 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2408 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2409 update_address (ad
);
2413 if (lra_dump_file
!= NULL
)
2416 fprintf (lra_dump_file
, " -- no change\n");
2419 fprintf (lra_dump_file
, " on equiv ");
2420 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2421 fprintf (lra_dump_file
, "\n");
2427 /* Major function to make reloads for an address in operand NOP.
2428 The supported cases are:
2430 1) an address that existed before LRA started, at which point it
2431 must have been valid. These addresses are subject to elimination
2432 and may have become invalid due to the elimination offset being out
2435 2) an address created by forcing a constant to memory
2436 (force_const_to_mem). The initial form of these addresses might
2437 not be valid, and it is this function's job to make them valid.
2439 3) a frame address formed from a register and a (possibly zero)
2440 constant offset. As above, these addresses might not be valid and
2441 this function must make them so.
2443 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2444 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2445 address. Return true for any RTL change. */
2447 process_address (int nop
, rtx
*before
, rtx
*after
)
2449 struct address_info ad
;
2451 rtx op
= *curr_id
->operand_loc
[nop
];
2452 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2455 if (constraint
[0] == 'p'
2456 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2457 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2458 else if (MEM_P (op
))
2459 decompose_mem_address (&ad
, op
);
2460 else if (GET_CODE (op
) == SUBREG
2461 && MEM_P (SUBREG_REG (op
)))
2462 decompose_mem_address (&ad
, SUBREG_REG (op
));
2465 change_p
= equiv_address_substitution (&ad
);
2466 if (ad
.base_term
!= NULL
2467 && (process_addr_reg
2468 (ad
.base_term
, before
,
2470 && !(REG_P (*ad
.base_term
)
2471 && find_regno_note (curr_insn
, REG_DEAD
,
2472 REGNO (*ad
.base_term
)) != NULL_RTX
)
2474 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2475 get_index_code (&ad
)))))
2478 if (ad
.base_term2
!= NULL
)
2479 *ad
.base_term2
= *ad
.base_term
;
2481 if (ad
.index_term
!= NULL
2482 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2485 #ifdef EXTRA_CONSTRAINT_STR
2486 /* Target hooks sometimes reject extra constraint addresses -- use
2487 EXTRA_CONSTRAINT_STR for the validation. */
2488 if (constraint
[0] != 'p'
2489 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2490 && EXTRA_CONSTRAINT_STR (op
, constraint
[0], constraint
))
2494 /* There are three cases where the shape of *AD.INNER may now be invalid:
2496 1) the original address was valid, but either elimination or
2497 equiv_address_substitution was applied and that made
2498 the address invalid.
2500 2) the address is an invalid symbolic address created by
2503 3) the address is a frame address with an invalid offset.
2505 All these cases involve a non-autoinc address, so there is no
2506 point revalidating other types. */
2507 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2510 /* Any index existed before LRA started, so we can assume that the
2511 presence and shape of the index is valid. */
2512 push_to_sequence (*before
);
2513 lra_assert (ad
.disp
== ad
.disp_term
);
2514 if (ad
.base
== NULL
)
2516 if (ad
.index
== NULL
)
2519 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2521 rtx addr
= *ad
.inner
;
2523 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2527 rtx last
= get_last_insn ();
2529 /* addr => lo_sum (new_base, addr), case (2) above. */
2530 insn
= emit_insn (gen_rtx_SET
2532 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2533 code
= recog_memoized (insn
);
2536 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2537 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2539 /* Try to put lo_sum into register. */
2540 insn
= emit_insn (gen_rtx_SET
2542 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2543 code
= recog_memoized (insn
);
2546 *ad
.inner
= new_reg
;
2547 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2557 delete_insns_since (last
);
2562 /* addr => new_base, case (2) above. */
2563 lra_emit_move (new_reg
, addr
);
2564 *ad
.inner
= new_reg
;
2569 /* index * scale + disp => new base + index * scale,
2571 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2572 GET_CODE (*ad
.index
));
2574 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2575 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2576 lra_emit_move (new_reg
, *ad
.disp
);
2577 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2578 new_reg
, *ad
.index
);
2581 else if (ad
.index
== NULL
)
2585 rtx set
, insns
, last_insn
;
2586 /* base + disp => new base, cases (1) and (3) above. */
2587 /* Another option would be to reload the displacement into an
2588 index register. However, postreload has code to optimize
2589 address reloads that have the same base and different
2590 displacements, so reloading into an index register would
2591 not necessarily be a win. */
2593 new_reg
= base_plus_disp_to_reg (&ad
);
2594 insns
= get_insns ();
2595 last_insn
= get_last_insn ();
2596 /* If we generated at least two insns, try last insn source as
2597 an address. If we succeed, we generate one less insn. */
2598 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2599 && GET_CODE (SET_SRC (set
)) == PLUS
2600 && REG_P (XEXP (SET_SRC (set
), 0))
2601 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2603 *ad
.inner
= SET_SRC (set
);
2604 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2606 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2607 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2608 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2609 get_index_code (&ad
));
2610 regno
= REGNO (*ad
.base_term
);
2611 if (regno
>= FIRST_PSEUDO_REGISTER
2612 && cl
!= lra_get_allocno_class (regno
))
2613 change_class (regno
, cl
, " Change", true);
2614 new_reg
= SET_SRC (set
);
2615 delete_insns_since (PREV_INSN (last_insn
));
2620 *ad
.inner
= new_reg
;
2624 /* base + scale * index + disp => new base + scale * index,
2626 new_reg
= base_plus_disp_to_reg (&ad
);
2627 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2628 new_reg
, *ad
.index
);
2630 *before
= get_insns ();
2635 /* Emit insns to reload VALUE into a new register. VALUE is an
2636 auto-increment or auto-decrement RTX whose operand is a register or
2637 memory location; so reloading involves incrementing that location.
2638 IN is either identical to VALUE, or some cheaper place to reload
2639 value being incremented/decremented from.
2641 INC_AMOUNT is the number to increment or decrement by (always
2642 positive and ignored for POST_MODIFY/PRE_MODIFY).
2644 Return pseudo containing the result. */
2646 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2648 /* REG or MEM to be copied and incremented. */
2649 rtx incloc
= XEXP (value
, 0);
2650 /* Nonzero if increment after copying. */
2651 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2652 || GET_CODE (value
) == POST_MODIFY
);
2657 rtx real_in
= in
== value
? incloc
: in
;
2661 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2663 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2664 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2665 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2666 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2667 inc
= XEXP (XEXP (value
, 1), 1);
2671 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2672 inc_amount
= -inc_amount
;
2674 inc
= GEN_INT (inc_amount
);
2677 if (! post
&& REG_P (incloc
))
2680 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2683 if (real_in
!= result
)
2685 /* First copy the location to the result register. */
2686 lra_assert (REG_P (result
));
2687 emit_insn (gen_move_insn (result
, real_in
));
2690 /* We suppose that there are insns to add/sub with the constant
2691 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2692 old reload worked with this assumption. If the assumption
2693 becomes wrong, we should use approach in function
2694 base_plus_disp_to_reg. */
2697 /* See if we can directly increment INCLOC. */
2698 last
= get_last_insn ();
2699 add_insn
= emit_insn (plus_p
2700 ? gen_add2_insn (incloc
, inc
)
2701 : gen_sub2_insn (incloc
, inc
));
2703 code
= recog_memoized (add_insn
);
2706 if (! post
&& result
!= incloc
)
2707 emit_insn (gen_move_insn (result
, incloc
));
2710 delete_insns_since (last
);
2713 /* If couldn't do the increment directly, must increment in RESULT.
2714 The way we do this depends on whether this is pre- or
2715 post-increment. For pre-increment, copy INCLOC to the reload
2716 register, increment it there, then save back. */
2719 if (real_in
!= result
)
2720 emit_insn (gen_move_insn (result
, real_in
));
2722 emit_insn (gen_add2_insn (result
, inc
));
2724 emit_insn (gen_sub2_insn (result
, inc
));
2725 if (result
!= incloc
)
2726 emit_insn (gen_move_insn (incloc
, result
));
2732 Because this might be a jump insn or a compare, and because
2733 RESULT may not be available after the insn in an input
2734 reload, we must do the incrementing before the insn being
2737 We have already copied IN to RESULT. Increment the copy in
2738 RESULT, save that back, then decrement RESULT so it has
2739 the original value. */
2741 emit_insn (gen_add2_insn (result
, inc
));
2743 emit_insn (gen_sub2_insn (result
, inc
));
2744 emit_insn (gen_move_insn (incloc
, result
));
2745 /* Restore non-modified value for the result. We prefer this
2746 way because it does not require an additional hard
2750 if (CONST_INT_P (inc
))
2751 emit_insn (gen_add2_insn (result
, GEN_INT (-INTVAL (inc
))));
2753 emit_insn (gen_sub2_insn (result
, inc
));
2756 emit_insn (gen_add2_insn (result
, inc
));
2761 /* Return true if the current move insn does not need processing as we
2762 already know that it satisfies its constraints. */
2764 simple_move_p (void)
2767 enum reg_class dclass
, sclass
;
2769 lra_assert (curr_insn_set
!= NULL_RTX
);
2770 dest
= SET_DEST (curr_insn_set
);
2771 src
= SET_SRC (curr_insn_set
);
2772 return ((dclass
= get_op_class (dest
)) != NO_REGS
2773 && (sclass
= get_op_class (src
)) != NO_REGS
2774 /* The backend guarantees that register moves of cost 2
2775 never need reloads. */
2776 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
2779 /* Swap operands NOP and NOP + 1. */
2781 swap_operands (int nop
)
2783 enum machine_mode mode
= curr_operand_mode
[nop
];
2784 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
2785 curr_operand_mode
[nop
+ 1] = mode
;
2786 rtx x
= *curr_id
->operand_loc
[nop
];
2787 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
2788 *curr_id
->operand_loc
[nop
+ 1] = x
;
2789 /* Swap the duplicates too. */
2790 lra_update_dup (curr_id
, nop
);
2791 lra_update_dup (curr_id
, nop
+ 1);
2794 /* Main entry point of the constraint code: search the body of the
2795 current insn to choose the best alternative. It is mimicking insn
2796 alternative cost calculation model of former reload pass. That is
2797 because machine descriptions were written to use this model. This
2798 model can be changed in future. Make commutative operand exchange
2801 Return true if some RTL changes happened during function call. */
2803 curr_insn_transform (void)
2809 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
2810 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
2813 /* Flag that the insn has been changed through a transformation. */
2816 #ifdef SECONDARY_MEMORY_NEEDED
2819 int max_regno_before
;
2820 int reused_alternative_num
;
2822 curr_insn_set
= single_set (curr_insn
);
2823 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
2826 no_input_reloads_p
= no_output_reloads_p
= false;
2827 goal_alt_number
= -1;
2828 change_p
= sec_mem_p
= false;
2829 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
2830 reloads; neither are insns that SET cc0. Insns that use CC0 are
2831 not allowed to have any input reloads. */
2832 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
2833 no_output_reloads_p
= true;
2836 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
2837 no_input_reloads_p
= true;
2838 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
2839 no_output_reloads_p
= true;
2842 n_operands
= curr_static_id
->n_operands
;
2843 n_alternatives
= curr_static_id
->n_alternatives
;
2845 /* Just return "no reloads" if insn has no operands with
2847 if (n_operands
== 0 || n_alternatives
== 0)
2850 max_regno_before
= max_reg_num ();
2852 for (i
= 0; i
< n_operands
; i
++)
2854 goal_alt_matched
[i
][0] = -1;
2855 goal_alt_matches
[i
] = -1;
2858 commutative
= curr_static_id
->commutative
;
2860 /* Now see what we need for pseudos that didn't get hard regs or got
2861 the wrong kind of hard reg. For this, we must consider all the
2862 operands together against the register constraints. */
2864 best_losers
= best_overall
= INT_MAX
;
2865 best_reload_sum
= 0;
2867 curr_swapped
= false;
2868 goal_alt_swapped
= false;
2870 /* Make equivalence substitution and memory subreg elimination
2871 before address processing because an address legitimacy can
2872 depend on memory mode. */
2873 for (i
= 0; i
< n_operands
; i
++)
2875 rtx op
= *curr_id
->operand_loc
[i
];
2876 rtx subst
, old
= op
;
2877 bool op_change_p
= false;
2879 if (GET_CODE (old
) == SUBREG
)
2880 old
= SUBREG_REG (old
);
2881 subst
= get_equiv_substitution (old
);
2884 subst
= copy_rtx (subst
);
2885 lra_assert (REG_P (old
));
2886 if (GET_CODE (op
) == SUBREG
)
2887 SUBREG_REG (op
) = subst
;
2889 *curr_id
->operand_loc
[i
] = subst
;
2890 if (lra_dump_file
!= NULL
)
2892 fprintf (lra_dump_file
,
2893 "Changing pseudo %d in operand %i of insn %u on equiv ",
2894 REGNO (old
), i
, INSN_UID (curr_insn
));
2895 dump_value_slim (lra_dump_file
, subst
, 1);
2896 fprintf (lra_dump_file
, "\n");
2898 op_change_p
= change_p
= true;
2900 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
2903 lra_update_dup (curr_id
, i
);
2907 /* Reload address registers and displacements. We do it before
2908 finding an alternative because of memory constraints. */
2909 before
= after
= NULL_RTX
;
2910 for (i
= 0; i
< n_operands
; i
++)
2911 if (! curr_static_id
->operand
[i
].is_operator
2912 && process_address (i
, &before
, &after
))
2915 lra_update_dup (curr_id
, i
);
2919 /* If we've changed the instruction then any alternative that
2920 we chose previously may no longer be valid. */
2921 lra_set_used_insn_alternative (curr_insn
, -1);
2923 if (curr_insn_set
!= NULL_RTX
2924 && check_and_process_move (&change_p
, &sec_mem_p
))
2929 reused_alternative_num
= curr_id
->used_insn_alternative
;
2930 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
2931 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
2932 reused_alternative_num
, INSN_UID (curr_insn
));
2934 if (process_alt_operands (reused_alternative_num
))
2937 /* If insn is commutative (it's safe to exchange a certain pair of
2938 operands) then we need to try each alternative twice, the second
2939 time matching those two operands as if we had exchanged them. To
2940 do this, really exchange them in operands.
2942 If we have just tried the alternatives the second time, return
2943 operands to normal and drop through. */
2945 if (reused_alternative_num
< 0 && commutative
>= 0)
2947 curr_swapped
= !curr_swapped
;
2950 swap_operands (commutative
);
2954 swap_operands (commutative
);
2957 if (! alt_p
&& ! sec_mem_p
)
2959 /* No alternative works with reloads?? */
2960 if (INSN_CODE (curr_insn
) >= 0)
2961 fatal_insn ("unable to generate reloads for:", curr_insn
);
2962 error_for_asm (curr_insn
,
2963 "inconsistent operand constraints in an %<asm%>");
2964 /* Avoid further trouble with this insn. */
2965 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
2966 lra_invalidate_insn_data (curr_insn
);
2970 /* If the best alternative is with operands 1 and 2 swapped, swap
2971 them. Update the operand numbers of any reloads already
2974 if (goal_alt_swapped
)
2976 if (lra_dump_file
!= NULL
)
2977 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
2978 INSN_UID (curr_insn
));
2980 /* Swap the duplicates too. */
2981 swap_operands (commutative
);
2985 #ifdef SECONDARY_MEMORY_NEEDED
2986 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
2987 too conservatively. So we use the secondary memory only if there
2988 is no any alternative without reloads. */
2989 use_sec_mem_p
= false;
2991 use_sec_mem_p
= true;
2994 for (i
= 0; i
< n_operands
; i
++)
2995 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
2997 use_sec_mem_p
= i
< n_operands
;
3002 rtx new_reg
, src
, dest
, rld
;
3003 enum machine_mode sec_mode
, rld_mode
;
3005 lra_assert (sec_mem_p
);
3006 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3007 && curr_static_id
->operand
[1].type
== OP_IN
);
3008 dest
= *curr_id
->operand_loc
[0];
3009 src
= *curr_id
->operand_loc
[1];
3010 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3012 rld_mode
= GET_MODE (rld
);
3013 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3014 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3016 sec_mode
= rld_mode
;
3018 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3019 NO_REGS
, "secondary");
3020 /* If the mode is changed, it should be wider. */
3021 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3022 if (sec_mode
!= rld_mode
)
3024 /* If the target says specifically to use another mode for
3025 secondary memory moves we can not reuse the original
3027 after
= emit_spill_move (false, new_reg
, dest
);
3028 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3029 "Inserting the sec. move");
3030 /* We may have non null BEFORE here (e.g. after address
3032 push_to_sequence (before
);
3033 before
= emit_spill_move (true, new_reg
, src
);
3035 before
= get_insns ();
3037 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3038 lra_set_insn_deleted (curr_insn
);
3040 else if (dest
== rld
)
3042 *curr_id
->operand_loc
[0] = new_reg
;
3043 after
= emit_spill_move (false, new_reg
, dest
);
3044 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3045 "Inserting the sec. move");
3049 *curr_id
->operand_loc
[1] = new_reg
;
3050 /* See comments above. */
3051 push_to_sequence (before
);
3052 before
= emit_spill_move (true, new_reg
, src
);
3054 before
= get_insns ();
3056 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3057 "Inserting the sec. move");
3059 lra_update_insn_regno_info (curr_insn
);
3064 lra_assert (goal_alt_number
>= 0);
3065 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3067 if (lra_dump_file
!= NULL
)
3071 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3072 goal_alt_number
, INSN_UID (curr_insn
));
3073 for (i
= 0; i
< n_operands
; i
++)
3075 p
= (curr_static_id
->operand_alternative
3076 [goal_alt_number
* n_operands
+ i
].constraint
);
3079 fprintf (lra_dump_file
, " (%d) ", i
);
3080 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3081 fputc (*p
, lra_dump_file
);
3083 if (INSN_CODE (curr_insn
) >= 0
3084 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3085 fprintf (lra_dump_file
, " {%s}", p
);
3086 fprintf (lra_dump_file
, "\n");
3089 /* Right now, for any pair of operands I and J that are required to
3090 match, with J < I, goal_alt_matches[I] is J. Add I to
3091 goal_alt_matched[J]. */
3093 for (i
= 0; i
< n_operands
; i
++)
3094 if ((j
= goal_alt_matches
[i
]) >= 0)
3096 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3098 /* We allow matching one output operand and several input
3101 || (curr_static_id
->operand
[j
].type
== OP_OUT
3102 && curr_static_id
->operand
[i
].type
== OP_IN
3103 && (curr_static_id
->operand
3104 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3105 goal_alt_matched
[j
][k
] = i
;
3106 goal_alt_matched
[j
][k
+ 1] = -1;
3109 for (i
= 0; i
< n_operands
; i
++)
3110 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3112 /* Any constants that aren't allowed and can't be reloaded into
3113 registers are here changed into memory references. */
3114 for (i
= 0; i
< n_operands
; i
++)
3115 if (goal_alt_win
[i
])
3118 enum reg_class new_class
;
3119 rtx reg
= *curr_id
->operand_loc
[i
];
3121 if (GET_CODE (reg
) == SUBREG
)
3122 reg
= SUBREG_REG (reg
);
3124 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3126 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3128 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3131 change_class (regno
, new_class
, " Change", true);
3137 const char *constraint
;
3139 rtx op
= *curr_id
->operand_loc
[i
];
3140 rtx subreg
= NULL_RTX
;
3141 enum machine_mode mode
= curr_operand_mode
[i
];
3143 if (GET_CODE (op
) == SUBREG
)
3146 op
= SUBREG_REG (op
);
3147 mode
= GET_MODE (op
);
3150 if (CONST_POOL_OK_P (mode
, op
)
3151 && ((targetm
.preferred_reload_class
3152 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3153 || no_input_reloads_p
))
3155 rtx tem
= force_const_mem (mode
, op
);
3158 if (subreg
!= NULL_RTX
)
3159 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3161 *curr_id
->operand_loc
[i
] = tem
;
3162 lra_update_dup (curr_id
, i
);
3163 process_address (i
, &before
, &after
);
3165 /* If the alternative accepts constant pool refs directly
3166 there will be no reload needed at all. */
3167 if (subreg
!= NULL_RTX
)
3169 /* Skip alternatives before the one requested. */
3170 constraint
= (curr_static_id
->operand_alternative
3171 [goal_alt_number
* n_operands
+ i
].constraint
);
3173 (c
= *constraint
) && c
!= ',' && c
!= '#';
3174 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3176 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3178 #ifdef EXTRA_CONSTRAINT_STR
3179 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3180 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3184 if (c
== '\0' || c
== ',' || c
== '#')
3187 goal_alt_win
[i
] = true;
3191 for (i
= 0; i
< n_operands
; i
++)
3194 rtx op
= *curr_id
->operand_loc
[i
];
3196 if (goal_alt_win
[i
])
3198 if (goal_alt
[i
] == NO_REGS
3200 /* When we assign NO_REGS it means that we will not
3201 assign a hard register to the scratch pseudo by
3202 assigment pass and the scratch pseudo will be
3203 spilled. Spilled scratch pseudos are transformed
3204 back to scratches at the LRA end. */
3205 && lra_former_scratch_operand_p (curr_insn
, i
))
3207 int regno
= REGNO (op
);
3208 change_class (regno
, NO_REGS
, " Change", true);
3209 if (lra_get_regno_hard_regno (regno
) >= 0)
3210 /* We don't have to mark all insn affected by the
3211 spilled pseudo as there is only one such insn, the
3213 reg_renumber
[regno
] = -1;
3218 /* Operands that match previous ones have already been handled. */
3219 if (goal_alt_matches
[i
] >= 0)
3222 /* We should not have an operand with a non-offsettable address
3223 appearing where an offsettable address will do. It also may
3224 be a case when the address should be special in other words
3225 not a general one (e.g. it needs no index reg). */
3226 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3228 enum reg_class rclass
;
3229 rtx
*loc
= &XEXP (op
, 0);
3230 enum rtx_code code
= GET_CODE (*loc
);
3232 push_to_sequence (before
);
3233 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3235 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3236 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3237 /* This value does not matter for MODIFY. */
3238 GET_MODE_SIZE (GET_MODE (op
)));
3239 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
3240 "offsetable address", &new_reg
))
3241 lra_emit_move (new_reg
, *loc
);
3242 before
= get_insns ();
3245 lra_update_dup (curr_id
, i
);
3247 else if (goal_alt_matched
[i
][0] == -1)
3249 enum machine_mode mode
;
3251 int hard_regno
, byte
;
3252 enum op_type type
= curr_static_id
->operand
[i
].type
;
3254 loc
= curr_id
->operand_loc
[i
];
3255 mode
= curr_operand_mode
[i
];
3256 if (GET_CODE (*loc
) == SUBREG
)
3258 reg
= SUBREG_REG (*loc
);
3259 byte
= SUBREG_BYTE (*loc
);
3261 /* Strict_low_part requires reload the register not
3262 the sub-register. */
3263 && (curr_static_id
->operand
[i
].strict_low
3264 || (GET_MODE_SIZE (mode
)
3265 <= GET_MODE_SIZE (GET_MODE (reg
))
3267 = get_try_hard_regno (REGNO (reg
))) >= 0
3268 && (simplify_subreg_regno
3270 GET_MODE (reg
), byte
, mode
) < 0)
3271 && (goal_alt
[i
] == NO_REGS
3272 || (simplify_subreg_regno
3273 (ira_class_hard_regs
[goal_alt
[i
]][0],
3274 GET_MODE (reg
), byte
, mode
) >= 0)))))
3276 loc
= &SUBREG_REG (*loc
);
3277 mode
= GET_MODE (*loc
);
3281 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3284 push_to_sequence (before
);
3285 lra_emit_move (new_reg
, old
);
3286 before
= get_insns ();
3291 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3294 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3296 after
= get_insns ();
3300 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3301 if (goal_alt_dont_inherit_ops
[j
] == i
)
3303 lra_set_regno_unique_value (REGNO (new_reg
));
3306 lra_update_dup (curr_id
, i
);
3308 else if (curr_static_id
->operand
[i
].type
== OP_IN
3309 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3312 /* generate reloads for input and matched outputs. */
3313 match_inputs
[0] = i
;
3314 match_inputs
[1] = -1;
3315 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3316 goal_alt
[i
], &before
, &after
);
3318 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3319 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3321 /* Generate reloads for output and matched inputs. */
3322 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3323 else if (curr_static_id
->operand
[i
].type
== OP_IN
3324 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3327 /* Generate reloads for matched inputs. */
3328 match_inputs
[0] = i
;
3329 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3330 match_inputs
[j
+ 1] = k
;
3331 match_inputs
[j
+ 1] = -1;
3332 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3335 /* We must generate code in any case when function
3336 process_alt_operands decides that it is possible. */
3339 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3340 || max_regno_before
!= max_reg_num ())
3344 lra_update_operator_dups (curr_id
);
3345 /* Something changes -- process the insn. */
3346 lra_update_insn_regno_info (curr_insn
);
3348 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3352 /* Return true if X is in LIST. */
3354 in_list_p (rtx x
, rtx list
)
3356 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3357 if (XEXP (list
, 0) == x
)
3362 /* Return true if X contains an allocatable hard register (if
3363 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3365 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3371 code
= GET_CODE (x
);
3374 int regno
= REGNO (x
);
3375 HARD_REG_SET alloc_regs
;
3379 if (regno
>= FIRST_PSEUDO_REGISTER
)
3380 regno
= lra_get_regno_hard_regno (regno
);
3383 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3384 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3388 if (regno
< FIRST_PSEUDO_REGISTER
)
3392 return lra_get_regno_hard_regno (regno
) < 0;
3395 fmt
= GET_RTX_FORMAT (code
);
3396 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3400 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3403 else if (fmt
[i
] == 'E')
3405 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3406 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3413 /* Process all regs in location *LOC and change them on equivalent
3414 substitution. Return true if any change was done. */
3416 loc_equivalence_change_p (rtx
*loc
)
3418 rtx subst
, reg
, x
= *loc
;
3419 bool result
= false;
3420 enum rtx_code code
= GET_CODE (x
);
3426 reg
= SUBREG_REG (x
);
3427 if ((subst
= get_equiv_substitution (reg
)) != reg
3428 && GET_MODE (subst
) == VOIDmode
)
3430 /* We cannot reload debug location. Simplify subreg here
3431 while we know the inner mode. */
3432 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3433 GET_MODE (reg
), SUBREG_BYTE (x
));
3437 if (code
== REG
&& (subst
= get_equiv_substitution (x
)) != x
)
3443 /* Scan all the operand sub-expressions. */
3444 fmt
= GET_RTX_FORMAT (code
);
3445 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3448 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3449 else if (fmt
[i
] == 'E')
3450 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3452 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3457 /* Similar to loc_equivalence_change_p, but for use as
3458 simplify_replace_fn_rtx callback. */
3460 loc_equivalence_callback (rtx loc
, const_rtx
, void *)
3465 rtx subst
= get_equiv_substitution (loc
);
3472 /* Maximum number of generated reload insns per an insn. It is for
3473 preventing this pass cycling in a bug case. */
3474 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3476 /* The current iteration number of this LRA pass. */
3477 int lra_constraint_iter
;
3479 /* The current iteration number of this LRA pass after the last spill
3481 int lra_constraint_iter_after_spill
;
3483 /* True if we substituted equiv which needs checking register
3484 allocation correctness because the equivalent value contains
3485 allocatable hard registers or when we restore multi-register
3487 bool lra_risky_transformations_p
;
3489 /* Return true if REGNO is referenced in more than one block. */
3491 multi_block_pseudo_p (int regno
)
3493 basic_block bb
= NULL
;
3497 if (regno
< FIRST_PSEUDO_REGISTER
)
3500 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3502 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3503 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3508 /* Return true if LIST contains a deleted insn. */
3510 contains_deleted_insn_p (rtx list
)
3512 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3513 if (NOTE_P (XEXP (list
, 0))
3514 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3519 /* Return true if X contains a pseudo dying in INSN. */
3521 dead_pseudo_p (rtx x
, rtx insn
)
3528 return (insn
!= NULL_RTX
3529 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3530 code
= GET_CODE (x
);
3531 fmt
= GET_RTX_FORMAT (code
);
3532 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3536 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3539 else if (fmt
[i
] == 'E')
3541 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3542 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3549 /* Return true if INSN contains a dying pseudo in INSN right hand
3552 insn_rhs_dead_pseudo_p (rtx insn
)
3554 rtx set
= single_set (insn
);
3556 gcc_assert (set
!= NULL
);
3557 return dead_pseudo_p (SET_SRC (set
), insn
);
3560 /* Return true if any init insn of REGNO contains a dying pseudo in
3561 insn right hand side. */
3563 init_insn_rhs_dead_pseudo_p (int regno
)
3565 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3570 return insn_rhs_dead_pseudo_p (insns
);
3571 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3572 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3577 /* Entry function of LRA constraint pass. Return true if the
3578 constraint pass did change the code. */
3580 lra_constraints (bool first_p
)
3583 int i
, hard_regno
, new_insns_num
;
3584 unsigned int min_len
, new_min_len
, uid
;
3585 rtx set
, x
, reg
, dest_reg
;
3586 basic_block last_bb
;
3587 bitmap_head equiv_insn_bitmap
;
3590 lra_constraint_iter
++;
3591 if (lra_dump_file
!= NULL
)
3592 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3593 lra_constraint_iter
);
3594 lra_constraint_iter_after_spill
++;
3595 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3597 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3598 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3600 lra_risky_transformations_p
= false;
3601 new_insn_uid_start
= get_max_uid ();
3602 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3603 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3604 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3605 if (lra_reg_info
[i
].nrefs
!= 0)
3607 ira_reg_equiv
[i
].profitable_p
= true;
3608 reg
= regno_reg_rtx
[i
];
3609 if ((hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3613 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3614 for (j
= 0; j
< nregs
; j
++)
3615 df_set_regs_ever_live (hard_regno
+ j
, true);
3617 else if ((x
= get_equiv_substitution (reg
)) != reg
)
3619 bool pseudo_p
= contains_reg_p (x
, false, false);
3622 /* After RTL transformation, we can not guarantee that
3623 pseudo in the substitution was not reloaded which might
3624 make equivalence invalid. For example, in reverse
3631 the memory address register was reloaded before the 2nd
3633 if ((! first_p
&& pseudo_p
)
3634 /* We don't use DF for compilation speed sake. So it
3635 is problematic to update live info when we use an
3636 equivalence containing pseudos in more than one
3638 || (pseudo_p
&& multi_block_pseudo_p (i
))
3639 /* If an init insn was deleted for some reason, cancel
3640 the equiv. We could update the equiv insns after
3641 transformations including an equiv insn deletion
3642 but it is not worthy as such cases are extremely
3644 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
3645 /* If it is not a reverse equivalence, we check that a
3646 pseudo in rhs of the init insn is not dying in the
3647 insn. Otherwise, the live info at the beginning of
3648 the corresponding BB might be wrong after we
3649 removed the insn. When the equiv can be a
3650 constant, the right hand side of the init insn can
3652 || (! ((insns
= ira_reg_equiv
[i
].init_insns
) != NULL_RTX
3653 && INSN_P (XEXP (insns
, 0))
3654 && XEXP (insns
, 1) == NULL_RTX
3655 && (set
= single_set (XEXP (insns
, 0))) != NULL_RTX
3656 && REG_P (SET_SRC (set
))
3657 && (int) REGNO (SET_SRC (set
)) == i
)
3658 && init_insn_rhs_dead_pseudo_p (i
))
3659 /* Prevent access beyond equivalent memory for
3660 paradoxical subregs. */
3662 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
3663 > GET_MODE_SIZE (GET_MODE (x
)))))
3664 ira_reg_equiv
[i
].defined_p
= false;
3665 if (contains_reg_p (x
, false, true))
3666 ira_reg_equiv
[i
].profitable_p
= false;
3667 if (get_equiv_substitution (reg
) != reg
)
3668 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
3671 /* We should add all insns containing pseudos which should be
3672 substituted by their equivalences. */
3673 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
3674 lra_push_insn_by_uid (uid
);
3675 lra_eliminate (false);
3676 min_len
= lra_insn_stack_length ();
3680 while ((new_min_len
= lra_insn_stack_length ()) != 0)
3682 curr_insn
= lra_pop_insn ();
3684 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
3685 if (curr_bb
!= last_bb
)
3688 bb_reload_num
= lra_curr_reload_num
;
3690 if (min_len
> new_min_len
)
3692 min_len
= new_min_len
;
3695 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
3697 ("Max. number of generated reload insns per insn is achieved (%d)\n",
3698 MAX_RELOAD_INSNS_NUMBER
);
3700 if (DEBUG_INSN_P (curr_insn
))
3702 /* We need to check equivalence in debug insn and change
3703 pseudo to the equivalent value if necessary. */
3704 curr_id
= lra_get_insn_recog_data (curr_insn
);
3705 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
3707 rtx old
= *curr_id
->operand_loc
[0];
3708 *curr_id
->operand_loc
[0]
3709 = simplify_replace_fn_rtx (old
, NULL_RTX
,
3710 loc_equivalence_callback
, NULL
);
3711 if (old
!= *curr_id
->operand_loc
[0])
3713 lra_update_insn_regno_info (curr_insn
);
3718 else if (INSN_P (curr_insn
))
3720 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
3722 dest_reg
= SET_DEST (set
);
3723 /* The equivalence pseudo could be set up as SUBREG in a
3724 case when it is a call restore insn in a mode
3725 different from the pseudo mode. */
3726 if (GET_CODE (dest_reg
) == SUBREG
)
3727 dest_reg
= SUBREG_REG (dest_reg
);
3728 if ((REG_P (dest_reg
)
3729 && (x
= get_equiv_substitution (dest_reg
)) != dest_reg
3730 /* Check that this is actually an insn setting up
3732 && (in_list_p (curr_insn
,
3734 [REGNO (dest_reg
)].init_insns
)
3735 /* Init insns may contain not all insns setting
3736 up equivalence as we have live range
3737 splitting. So here we use another condition
3738 to check insn setting up the equivalence
3739 which should be removed, e.g. in case when
3740 the equivalence is a constant. */
3742 /* Remove insns which set up a pseudo whose value
3743 can not be changed. Such insns might be not in
3744 init_insns because we don't update equiv data
3745 during insn transformations.
3747 As an example, let suppose that a pseudo got
3748 hard register and on the 1st pass was not
3749 changed to equivalent constant. We generate an
3750 additional insn setting up the pseudo because of
3751 secondary memory movement. Then the pseudo is
3752 spilled and we use the equiv constant. In this
3753 case we should remove the additional insn and
3754 this insn is not init_insns list. */
3755 && (! MEM_P (x
) || MEM_READONLY_P (x
)
3756 || in_list_p (curr_insn
,
3758 [REGNO (dest_reg
)].init_insns
)))
3759 || (((x
= get_equiv_substitution (SET_SRC (set
)))
3761 && in_list_p (curr_insn
,
3763 [REGNO (SET_SRC (set
))].init_insns
)))
3765 /* This is equiv init insn of pseudo which did not get a
3766 hard register -- remove the insn. */
3767 if (lra_dump_file
!= NULL
)
3769 fprintf (lra_dump_file
,
3770 " Removing equiv init insn %i (freq=%d)\n",
3771 INSN_UID (curr_insn
),
3772 BLOCK_FOR_INSN (curr_insn
)->frequency
);
3773 dump_insn_slim (lra_dump_file
, curr_insn
);
3775 if (contains_reg_p (x
, true, false))
3776 lra_risky_transformations_p
= true;
3777 lra_set_insn_deleted (curr_insn
);
3781 curr_id
= lra_get_insn_recog_data (curr_insn
);
3782 curr_static_id
= curr_id
->insn_static_data
;
3783 init_curr_insn_input_reloads ();
3784 init_curr_operand_mode ();
3785 if (curr_insn_transform ())
3787 /* Check non-transformed insns too for equiv change as USE
3788 or CLOBBER don't need reloads but can contain pseudos
3789 being changed on their equivalences. */
3790 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
3791 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
3793 lra_update_insn_regno_info (curr_insn
);
3798 bitmap_clear (&equiv_insn_bitmap
);
3799 /* If we used a new hard regno, changed_p should be true because the
3800 hard reg is assigned to a new pseudo. */
3801 #ifdef ENABLE_CHECKING
3804 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3805 if (lra_reg_info
[i
].nrefs
!= 0
3806 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3808 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3810 for (j
= 0; j
< nregs
; j
++)
3811 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
3818 /* Initiate the LRA constraint pass. It is done once per
3821 lra_constraints_init (void)
3825 /* Finalize the LRA constraint pass. It is done once per
3828 lra_constraints_finish (void)
3834 /* This page contains code to do inheritance/split
3837 /* Number of reloads passed so far in current EBB. */
3838 static int reloads_num
;
3840 /* Number of calls passed so far in current EBB. */
3841 static int calls_num
;
3843 /* Current reload pseudo check for validity of elements in
3845 static int curr_usage_insns_check
;
3847 /* Info about last usage of registers in EBB to do inheritance/split
3848 transformation. Inheritance transformation is done from a spilled
3849 pseudo and split transformations from a hard register or a pseudo
3850 assigned to a hard register. */
3853 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
3854 value INSNS is valid. The insns is chain of optional debug insns
3855 and a finishing non-debug insn using the corresponding reg. The
3856 value is also used to mark the registers which are set up in the
3857 current insn. The negated insn uid is used for this. */
3859 /* Value of global reloads_num at the last insn in INSNS. */
3861 /* Value of global reloads_nums at the last insn in INSNS. */
3863 /* It can be true only for splitting. And it means that the restore
3864 insn should be put after insn given by the following member. */
3866 /* Next insns in the current EBB which use the original reg and the
3867 original reg value is not changed between the current insn and
3868 the next insns. In order words, e.g. for inheritance, if we need
3869 to use the original reg value again in the next insns we can try
3870 to use the value in a hard register from a reload insn of the
3875 /* Map: regno -> corresponding pseudo usage insns. */
3876 static struct usage_insns
*usage_insns
;
3879 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
3881 usage_insns
[regno
].check
= curr_usage_insns_check
;
3882 usage_insns
[regno
].insns
= insn
;
3883 usage_insns
[regno
].reloads_num
= reloads_num
;
3884 usage_insns
[regno
].calls_num
= calls_num
;
3885 usage_insns
[regno
].after_p
= after_p
;
3888 /* The function is used to form list REGNO usages which consists of
3889 optional debug insns finished by a non-debug insn using REGNO.
3890 RELOADS_NUM is current number of reload insns processed so far. */
3892 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
3894 rtx next_usage_insns
;
3896 if (usage_insns
[regno
].check
== curr_usage_insns_check
3897 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
3898 && DEBUG_INSN_P (insn
))
3900 /* Check that we did not add the debug insn yet. */
3901 if (next_usage_insns
!= insn
3902 && (GET_CODE (next_usage_insns
) != INSN_LIST
3903 || XEXP (next_usage_insns
, 0) != insn
))
3904 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
3907 else if (NONDEBUG_INSN_P (insn
))
3908 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
3910 usage_insns
[regno
].check
= 0;
3913 /* Replace all references to register OLD_REGNO in *LOC with pseudo
3914 register NEW_REG. Return true if any change was made. */
3916 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
3919 bool result
= false;
3927 code
= GET_CODE (x
);
3928 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
3930 enum machine_mode mode
= GET_MODE (*loc
);
3931 enum machine_mode inner_mode
= GET_MODE (new_reg
);
3933 if (mode
!= inner_mode
)
3935 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
3936 || ! SCALAR_INT_MODE_P (inner_mode
))
3937 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
3939 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
3945 /* Scan all the operand sub-expressions. */
3946 fmt
= GET_RTX_FORMAT (code
);
3947 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3951 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
3954 else if (fmt
[i
] == 'E')
3956 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3957 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
3964 /* Return first non-debug insn in list USAGE_INSNS. */
3966 skip_usage_debug_insns (rtx usage_insns
)
3970 /* Skip debug insns. */
3971 for (insn
= usage_insns
;
3972 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
3973 insn
= XEXP (insn
, 1))
3978 /* Return true if we need secondary memory moves for insn in
3979 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
3982 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
3983 rtx usage_insns ATTRIBUTE_UNUSED
)
3985 #ifndef SECONDARY_MEMORY_NEEDED
3988 rtx insn
, set
, dest
;
3991 if (inher_cl
== ALL_REGS
3992 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
3994 lra_assert (INSN_P (insn
));
3995 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
3997 dest
= SET_DEST (set
);
4000 lra_assert (inher_cl
!= NO_REGS
);
4001 cl
= get_reg_class (REGNO (dest
));
4002 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4003 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4007 /* Registers involved in inheritance/split in the current EBB
4008 (inheritance/split pseudos and original registers). */
4009 static bitmap_head check_only_regs
;
4011 /* Do inheritance transformations for insn INSN, which defines (if
4012 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4013 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4014 form as the "insns" field of usage_insns. Return true if we
4015 succeed in such transformation.
4017 The transformations look like:
4020 ... p <- i (new insn)
4022 <- ... p ... <- ... i ...
4024 ... i <- p (new insn)
4025 <- ... p ... <- ... i ...
4027 <- ... p ... <- ... i ...
4028 where p is a spilled original pseudo and i is a new inheritance pseudo.
4031 The inheritance pseudo has the smallest class of two classes CL and
4032 class of ORIGINAL REGNO. */
4034 inherit_reload_reg (bool def_p
, int original_regno
,
4035 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4037 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4038 rtx original_reg
= regno_reg_rtx
[original_regno
];
4039 rtx new_reg
, new_insns
, usage_insn
;
4041 lra_assert (! usage_insns
[original_regno
].after_p
);
4042 if (lra_dump_file
!= NULL
)
4043 fprintf (lra_dump_file
,
4044 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4045 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4047 if (lra_dump_file
!= NULL
)
4049 fprintf (lra_dump_file
,
4050 " Rejecting inheritance for %d "
4051 "because of disjoint classes %s and %s\n",
4052 original_regno
, reg_class_names
[cl
],
4053 reg_class_names
[rclass
]);
4054 fprintf (lra_dump_file
,
4055 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4059 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4060 /* We don't use a subset of two classes because it can be
4061 NO_REGS. This transformation is still profitable in most
4062 cases even if the classes are not intersected as register
4063 move is probably cheaper than a memory load. */
4064 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4066 if (lra_dump_file
!= NULL
)
4067 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4068 reg_class_names
[cl
], reg_class_names
[rclass
]);
4072 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4074 /* Reject inheritance resulting in secondary memory moves.
4075 Otherwise, there is a danger in LRA cycling. Also such
4076 transformation will be unprofitable. */
4077 if (lra_dump_file
!= NULL
)
4079 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4080 rtx set
= single_set (insn
);
4082 lra_assert (set
!= NULL_RTX
);
4084 rtx dest
= SET_DEST (set
);
4086 lra_assert (REG_P (dest
));
4087 fprintf (lra_dump_file
,
4088 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4089 "as secondary mem is needed\n",
4090 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4091 original_regno
, reg_class_names
[rclass
]);
4092 fprintf (lra_dump_file
,
4093 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4097 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4098 rclass
, "inheritance");
4101 emit_move_insn (original_reg
, new_reg
);
4103 emit_move_insn (new_reg
, original_reg
);
4104 new_insns
= get_insns ();
4106 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4108 if (lra_dump_file
!= NULL
)
4110 fprintf (lra_dump_file
,
4111 " Rejecting inheritance %d->%d "
4112 "as it results in 2 or more insns:\n",
4113 original_regno
, REGNO (new_reg
));
4114 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4115 fprintf (lra_dump_file
,
4116 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4120 substitute_pseudo (&insn
, original_regno
, new_reg
);
4121 lra_update_insn_regno_info (insn
);
4123 /* We now have a new usage insn for original regno. */
4124 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4125 if (lra_dump_file
!= NULL
)
4126 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4127 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4128 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4129 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4130 bitmap_set_bit (&check_only_regs
, original_regno
);
4131 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4133 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4134 "Add original<-inheritance");
4136 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4137 "Add inheritance<-original");
4138 while (next_usage_insns
!= NULL_RTX
)
4140 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4142 usage_insn
= next_usage_insns
;
4143 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4144 next_usage_insns
= NULL
;
4148 usage_insn
= XEXP (next_usage_insns
, 0);
4149 lra_assert (DEBUG_INSN_P (usage_insn
));
4150 next_usage_insns
= XEXP (next_usage_insns
, 1);
4152 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4153 lra_update_insn_regno_info (usage_insn
);
4154 if (lra_dump_file
!= NULL
)
4156 fprintf (lra_dump_file
,
4157 " Inheritance reuse change %d->%d (bb%d):\n",
4158 original_regno
, REGNO (new_reg
),
4159 BLOCK_FOR_INSN (usage_insn
)->index
);
4160 dump_insn_slim (lra_dump_file
, usage_insn
);
4163 if (lra_dump_file
!= NULL
)
4164 fprintf (lra_dump_file
,
4165 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4169 /* Return true if we need a caller save/restore for pseudo REGNO which
4170 was assigned to a hard register. */
4172 need_for_call_save_p (int regno
)
4174 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4175 return (usage_insns
[regno
].calls_num
< calls_num
4176 && (overlaps_hard_reg_set_p
4178 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])));
4181 /* Global registers occuring in the current EBB. */
4182 static bitmap_head ebb_global_regs
;
4184 /* Return true if we need a split for hard register REGNO or pseudo
4185 REGNO which was assigned to a hard register.
4186 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4187 used for reloads since the EBB end. It is an approximation of the
4188 used hard registers in the split range. The exact value would
4189 require expensive calculations. If we were aggressive with
4190 splitting because of the approximation, the split pseudo will save
4191 the same hard register assignment and will be removed in the undo
4192 pass. We still need the approximation because too aggressive
4193 splitting would result in too inaccurate cost calculation in the
4194 assignment pass because of too many generated moves which will be
4195 probably removed in the undo pass. */
4197 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4199 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4201 lra_assert (hard_regno
>= 0);
4202 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4203 /* Don't split eliminable hard registers, otherwise we can
4204 split hard registers like hard frame pointer, which
4205 lives on BB start/end according to DF-infrastructure,
4206 when there is a pseudo assigned to the register and
4207 living in the same BB. */
4208 && (regno
>= FIRST_PSEUDO_REGISTER
4209 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4210 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4211 /* We need at least 2 reloads to make pseudo splitting
4212 profitable. We should provide hard regno splitting in
4213 any case to solve 1st insn scheduling problem when
4214 moving hard register definition up might result in
4215 impossibility to find hard register for reload pseudo of
4216 small register class. */
4217 && (usage_insns
[regno
].reloads_num
4218 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
4219 && (regno
< FIRST_PSEUDO_REGISTER
4220 /* For short living pseudos, spilling + inheritance can
4221 be considered a substitution for splitting.
4222 Therefore we do not splitting for local pseudos. It
4223 decreases also aggressiveness of splitting. The
4224 minimal number of references is chosen taking into
4225 account that for 2 references splitting has no sense
4226 as we can just spill the pseudo. */
4227 || (regno
>= FIRST_PSEUDO_REGISTER
4228 && lra_reg_info
[regno
].nrefs
> 3
4229 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4230 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4233 /* Return class for the split pseudo created from original pseudo with
4234 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4235 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4236 results in no secondary memory movements. */
4237 static enum reg_class
4238 choose_split_class (enum reg_class allocno_class
,
4239 int hard_regno ATTRIBUTE_UNUSED
,
4240 enum machine_mode mode ATTRIBUTE_UNUSED
)
4242 #ifndef SECONDARY_MEMORY_NEEDED
4243 return allocno_class
;
4246 enum reg_class cl
, best_cl
= NO_REGS
;
4247 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4248 = REGNO_REG_CLASS (hard_regno
);
4250 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4251 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4252 return allocno_class
;
4254 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4256 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4257 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4258 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4259 && (best_cl
== NO_REGS
4260 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4266 /* Do split transformations for insn INSN, which defines or uses
4267 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4268 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4269 "insns" field of usage_insns.
4271 The transformations look like:
4274 ... s <- p (new insn -- save)
4276 ... p <- s (new insn -- restore)
4277 <- ... p ... <- ... p ...
4279 <- ... p ... <- ... p ...
4280 ... s <- p (new insn -- save)
4282 ... p <- s (new insn -- restore)
4283 <- ... p ... <- ... p ...
4285 where p is an original pseudo got a hard register or a hard
4286 register and s is a new split pseudo. The save is put before INSN
4287 if BEFORE_P is true. Return true if we succeed in such
4290 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4292 enum reg_class rclass
;
4294 int hard_regno
, nregs
;
4295 rtx new_reg
, save
, restore
, usage_insn
;
4299 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4301 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4302 hard_regno
= original_regno
;
4303 call_save_p
= false;
4308 hard_regno
= reg_renumber
[original_regno
];
4309 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4310 rclass
= lra_get_allocno_class (original_regno
);
4311 original_reg
= regno_reg_rtx
[original_regno
];
4312 call_save_p
= need_for_call_save_p (original_regno
);
4314 original_reg
= regno_reg_rtx
[original_regno
];
4315 lra_assert (hard_regno
>= 0);
4316 if (lra_dump_file
!= NULL
)
4317 fprintf (lra_dump_file
,
4318 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4321 enum machine_mode sec_mode
;
4323 #ifdef SECONDARY_MEMORY_NEEDED_MODE
4324 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (original_reg
));
4326 sec_mode
= GET_MODE (original_reg
);
4328 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
4333 rclass
= choose_split_class (rclass
, hard_regno
,
4334 GET_MODE (original_reg
));
4335 if (rclass
== NO_REGS
)
4337 if (lra_dump_file
!= NULL
)
4339 fprintf (lra_dump_file
,
4340 " Rejecting split of %d(%s): "
4341 "no good reg class for %d(%s)\n",
4343 reg_class_names
[lra_get_allocno_class (original_regno
)],
4345 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4348 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4352 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4354 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4356 save
= emit_spill_move (true, new_reg
, original_reg
);
4357 if (NEXT_INSN (save
) != NULL_RTX
)
4359 lra_assert (! call_save_p
);
4360 if (lra_dump_file
!= NULL
)
4364 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4365 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4366 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4367 fprintf (lra_dump_file
,
4368 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4372 restore
= emit_spill_move (false, new_reg
, original_reg
);
4373 if (NEXT_INSN (restore
) != NULL_RTX
)
4375 lra_assert (! call_save_p
);
4376 if (lra_dump_file
!= NULL
)
4378 fprintf (lra_dump_file
,
4379 " Rejecting split %d->%d "
4380 "resulting in > 2 %s restore insns:\n",
4381 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4382 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4383 fprintf (lra_dump_file
,
4384 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4388 after_p
= usage_insns
[original_regno
].after_p
;
4389 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4390 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4391 bitmap_set_bit (&check_only_regs
, original_regno
);
4392 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4395 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4397 usage_insn
= next_usage_insns
;
4400 usage_insn
= XEXP (next_usage_insns
, 0);
4401 lra_assert (DEBUG_INSN_P (usage_insn
));
4402 next_usage_insns
= XEXP (next_usage_insns
, 1);
4403 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4404 lra_update_insn_regno_info (usage_insn
);
4405 if (lra_dump_file
!= NULL
)
4407 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4408 original_regno
, REGNO (new_reg
));
4409 dump_insn_slim (lra_dump_file
, usage_insn
);
4412 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4413 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4414 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4415 after_p
? restore
: NULL_RTX
,
4417 ? "Add reg<-save" : "Add reg<-split");
4418 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4419 before_p
? NULL_RTX
: save
,
4421 ? "Add save<-reg" : "Add split<-reg");
4423 /* If we are trying to split multi-register. We should check
4424 conflicts on the next assignment sub-pass. IRA can allocate on
4425 sub-register levels, LRA do this on pseudos level right now and
4426 this discrepancy may create allocation conflicts after
4428 lra_risky_transformations_p
= true;
4429 if (lra_dump_file
!= NULL
)
4430 fprintf (lra_dump_file
,
4431 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4435 /* Recognize that we need a split transformation for insn INSN, which
4436 defines or uses REGNO in its insn biggest MODE (we use it only if
4437 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4438 hard registers which might be used for reloads since the EBB end.
4439 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4440 uid before starting INSN processing. Return true if we succeed in
4441 such transformation. */
4443 split_if_necessary (int regno
, enum machine_mode mode
,
4444 HARD_REG_SET potential_reload_hard_regs
,
4445 bool before_p
, rtx insn
, int max_uid
)
4449 rtx next_usage_insns
;
4451 if (regno
< FIRST_PSEUDO_REGISTER
)
4452 nregs
= hard_regno_nregs
[regno
][mode
];
4453 for (i
= 0; i
< nregs
; i
++)
4454 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4455 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4456 /* To avoid processing the register twice or more. */
4457 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4458 && INSN_UID (next_usage_insns
) < max_uid
)
4459 || (GET_CODE (next_usage_insns
) == INSN_LIST
4460 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4461 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4462 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4467 /* Check only registers living at the current program point in the
4469 static bitmap_head live_regs
;
4471 /* Update live info in EBB given by its HEAD and TAIL insns after
4472 inheritance/split transformation. The function removes dead moves
4475 update_ebb_live_info (rtx head
, rtx tail
)
4482 basic_block last_bb
, prev_bb
, curr_bb
;
4484 struct lra_insn_reg
*reg
;
4488 last_bb
= BLOCK_FOR_INSN (tail
);
4490 for (curr_insn
= tail
;
4491 curr_insn
!= PREV_INSN (head
);
4492 curr_insn
= prev_insn
)
4494 prev_insn
= PREV_INSN (curr_insn
);
4495 /* We need to process empty blocks too. They contain
4496 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4497 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4499 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4500 if (curr_bb
!= prev_bb
)
4502 if (prev_bb
!= NULL
)
4504 /* Update df_get_live_in (prev_bb): */
4505 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4506 if (bitmap_bit_p (&live_regs
, j
))
4507 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4509 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4511 if (curr_bb
!= last_bb
)
4513 /* Update df_get_live_out (curr_bb): */
4514 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4516 live_p
= bitmap_bit_p (&live_regs
, j
);
4518 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4519 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4525 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4527 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4531 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4533 if (! NONDEBUG_INSN_P (curr_insn
))
4535 curr_id
= lra_get_insn_recog_data (curr_insn
);
4537 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4538 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4539 && bitmap_bit_p (&check_only_regs
, regno
)
4540 && ! bitmap_bit_p (&live_regs
, regno
))
4542 /* See which defined values die here. */
4543 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4544 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4545 bitmap_clear_bit (&live_regs
, reg
->regno
);
4546 /* Mark each used value as live. */
4547 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4548 if (reg
->type
== OP_IN
4549 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4550 bitmap_set_bit (&live_regs
, reg
->regno
);
4551 /* It is quite important to remove dead move insns because it
4552 means removing dead store. We don't need to process them for
4556 if (lra_dump_file
!= NULL
)
4558 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4559 dump_insn_slim (lra_dump_file
, curr_insn
);
4561 lra_set_insn_deleted (curr_insn
);
4566 /* The structure describes info to do an inheritance for the current
4567 insn. We need to collect such info first before doing the
4568 transformations because the transformations change the insn
4569 internal representation. */
4572 /* Original regno. */
4574 /* Subsequent insns which can inherit original reg value. */
4578 /* Array containing all info for doing inheritance from the current
4580 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4582 /* Number elements in the previous array. */
4583 static int to_inherit_num
;
4585 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4586 structure to_inherit. */
4588 add_to_inherit (int regno
, rtx insns
)
4592 for (i
= 0; i
< to_inherit_num
; i
++)
4593 if (to_inherit
[i
].regno
== regno
)
4595 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4596 to_inherit
[to_inherit_num
].regno
= regno
;
4597 to_inherit
[to_inherit_num
++].insns
= insns
;
4600 /* Return the last non-debug insn in basic block BB, or the block begin
4603 get_last_insertion_point (basic_block bb
)
4607 FOR_BB_INSNS_REVERSE (bb
, insn
)
4608 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4613 /* Set up RES by registers living on edges FROM except the edge (FROM,
4614 TO) or by registers set up in a jump insn in BB FROM. */
4616 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4619 struct lra_insn_reg
*reg
;
4623 lra_assert (to
!= NULL
);
4625 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4627 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4628 last
= get_last_insertion_point (from
);
4629 if (! JUMP_P (last
))
4631 curr_id
= lra_get_insn_recog_data (last
);
4632 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4633 if (reg
->type
!= OP_IN
)
4634 bitmap_set_bit (res
, reg
->regno
);
4637 /* Used as a temporary results of some bitmap calculations. */
4638 static bitmap_head temp_bitmap
;
4640 /* Do inheritance/split transformations in EBB starting with HEAD and
4641 finishing on TAIL. We process EBB insns in the reverse order.
4642 Return true if we did any inheritance/split transformation in the
4645 We should avoid excessive splitting which results in worse code
4646 because of inaccurate cost calculations for spilling new split
4647 pseudos in such case. To achieve this we do splitting only if
4648 register pressure is high in given basic block and there are reload
4649 pseudos requiring hard registers. We could do more register
4650 pressure calculations at any given program point to avoid necessary
4651 splitting even more but it is to expensive and the current approach
4652 works well enough. */
4654 inherit_in_ebb (rtx head
, rtx tail
)
4656 int i
, src_regno
, dst_regno
, nregs
;
4657 bool change_p
, succ_p
;
4658 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4660 struct lra_insn_reg
*reg
;
4661 basic_block last_processed_bb
, curr_bb
= NULL
;
4662 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
4666 bool head_p
, after_p
;
4669 curr_usage_insns_check
++;
4670 reloads_num
= calls_num
= 0;
4671 bitmap_clear (&check_only_regs
);
4672 last_processed_bb
= NULL
;
4673 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4674 CLEAR_HARD_REG_SET (live_hard_regs
);
4675 /* We don't process new insns generated in the loop. */
4676 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
4678 prev_insn
= PREV_INSN (curr_insn
);
4679 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
4680 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4681 if (last_processed_bb
!= curr_bb
)
4683 /* We are at the end of BB. Add qualified living
4684 pseudos for potential splitting. */
4685 to_process
= df_get_live_out (curr_bb
);
4686 if (last_processed_bb
!= NULL
)
4688 /* We are somewhere in the middle of EBB. */
4689 get_live_on_other_edges (curr_bb
, last_processed_bb
,
4691 to_process
= &temp_bitmap
;
4693 last_processed_bb
= curr_bb
;
4694 last_insn
= get_last_insertion_point (curr_bb
);
4695 after_p
= (! JUMP_P (last_insn
)
4696 && (! CALL_P (last_insn
)
4697 || (find_reg_note (last_insn
,
4698 REG_NORETURN
, NULL_RTX
) == NULL_RTX
4699 && ! SIBLING_CALL_P (last_insn
))));
4700 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
4701 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
4702 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
4703 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4704 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4706 if ((int) j
>= lra_constraint_new_regno_start
)
4708 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4710 if (j
< FIRST_PSEUDO_REGISTER
)
4711 SET_HARD_REG_BIT (live_hard_regs
, j
);
4713 add_to_hard_reg_set (&live_hard_regs
,
4714 PSEUDO_REGNO_MODE (j
),
4716 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
4720 src_regno
= dst_regno
= -1;
4721 if (NONDEBUG_INSN_P (curr_insn
)
4722 && (set
= single_set (curr_insn
)) != NULL_RTX
4723 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
4725 src_regno
= REGNO (SET_SRC (set
));
4726 dst_regno
= REGNO (SET_DEST (set
));
4728 if (src_regno
< lra_constraint_new_regno_start
4729 && src_regno
>= FIRST_PSEUDO_REGISTER
4730 && reg_renumber
[src_regno
] < 0
4731 && dst_regno
>= lra_constraint_new_regno_start
4732 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
4734 /* 'reload_pseudo <- original_pseudo'. */
4737 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4738 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
4739 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
4740 curr_insn
, next_usage_insns
);
4744 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4745 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4746 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4747 reg_class_contents
[cl
]);
4749 else if (src_regno
>= lra_constraint_new_regno_start
4750 && dst_regno
< lra_constraint_new_regno_start
4751 && dst_regno
>= FIRST_PSEUDO_REGISTER
4752 && reg_renumber
[dst_regno
] < 0
4753 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
4754 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4755 && (next_usage_insns
4756 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4759 /* 'original_pseudo <- reload_pseudo'. */
4760 if (! JUMP_P (curr_insn
)
4761 && inherit_reload_reg (true, dst_regno
, cl
,
4762 curr_insn
, next_usage_insns
))
4765 usage_insns
[dst_regno
].check
= 0;
4766 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4767 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4768 reg_class_contents
[cl
]);
4770 else if (INSN_P (curr_insn
))
4772 int max_uid
= get_max_uid ();
4774 curr_id
= lra_get_insn_recog_data (curr_insn
);
4776 /* Process insn definitions. */
4777 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4778 if (reg
->type
!= OP_IN
4779 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4781 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
4782 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
4783 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4784 && (next_usage_insns
4785 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4787 struct lra_insn_reg
*r
;
4789 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
4790 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
4792 /* Don't do inheritance if the pseudo is also
4793 used in the insn. */
4795 /* We can not do inheritance right now
4796 because the current insn reg info (chain
4797 regs) can change after that. */
4798 add_to_inherit (dst_regno
, next_usage_insns
);
4800 /* We can not process one reg twice here because of
4801 usage_insns invalidation. */
4802 if ((dst_regno
< FIRST_PSEUDO_REGISTER
4803 || reg_renumber
[dst_regno
] >= 0)
4804 && ! reg
->subreg_p
&& reg
->type
== OP_OUT
)
4808 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
4809 potential_reload_hard_regs
,
4810 false, curr_insn
, max_uid
))
4812 CLEAR_HARD_REG_SET (s
);
4813 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
4814 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
4816 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
4817 reg_renumber
[dst_regno
]);
4818 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
4820 /* We should invalidate potential inheritance or
4821 splitting for the current insn usages to the next
4822 usage insns (see code below) as the output pseudo
4824 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
4825 && reg_renumber
[dst_regno
] < 0)
4826 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
4827 && (dst_regno
< FIRST_PSEUDO_REGISTER
4828 || reg_renumber
[dst_regno
] >= 0)))
4830 /* Invalidate and mark definitions. */
4831 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
4832 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
4835 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
4836 for (i
= 0; i
< nregs
; i
++)
4837 usage_insns
[dst_regno
+ i
].check
4838 = -(int) INSN_UID (curr_insn
);
4842 if (! JUMP_P (curr_insn
))
4843 for (i
= 0; i
< to_inherit_num
; i
++)
4844 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
4845 ALL_REGS
, curr_insn
,
4846 to_inherit
[i
].insns
))
4848 if (CALL_P (curr_insn
))
4850 rtx cheap
, pat
, dest
, restore
;
4851 int regno
, hard_regno
;
4854 if ((cheap
= find_reg_note (curr_insn
,
4855 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
4856 && ((cheap
= XEXP (cheap
, 0)), true)
4857 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
4858 && (hard_regno
= reg_renumber
[regno
]) >= 0
4859 /* If there are pending saves/restores, the
4860 optimization is not worth. */
4861 && usage_insns
[regno
].calls_num
== calls_num
- 1
4862 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
4864 /* Restore the pseudo from the call result as
4865 REG_RETURNED note says that the pseudo value is
4866 in the call result and the pseudo is an argument
4868 pat
= PATTERN (curr_insn
);
4869 if (GET_CODE (pat
) == PARALLEL
)
4870 pat
= XVECEXP (pat
, 0, 0);
4871 dest
= SET_DEST (pat
);
4873 emit_move_insn (cheap
, copy_rtx (dest
));
4874 restore
= get_insns ();
4876 lra_process_new_insns (curr_insn
, NULL
, restore
,
4877 "Inserting call parameter restore");
4878 /* We don't need to save/restore of the pseudo from
4880 usage_insns
[regno
].calls_num
= calls_num
;
4881 bitmap_set_bit (&check_only_regs
, regno
);
4885 /* Process insn usages. */
4886 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4887 if ((reg
->type
!= OP_OUT
4888 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
4889 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4891 if (src_regno
>= FIRST_PSEUDO_REGISTER
4892 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
4894 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4895 && (next_usage_insns
4896 = usage_insns
[src_regno
].insns
) != NULL_RTX
4897 && NONDEBUG_INSN_P (curr_insn
))
4898 add_to_inherit (src_regno
, next_usage_insns
);
4899 else if (usage_insns
[src_regno
].check
4900 != -(int) INSN_UID (curr_insn
))
4901 /* Add usages but only if the reg is not set up
4902 in the same insn. */
4903 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
4905 else if (src_regno
< FIRST_PSEUDO_REGISTER
4906 || reg_renumber
[src_regno
] >= 0)
4909 rtx use_insn
= curr_insn
;
4911 before_p
= (JUMP_P (curr_insn
)
4912 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
4913 if (NONDEBUG_INSN_P (curr_insn
)
4914 && split_if_necessary (src_regno
, reg
->biggest_mode
,
4915 potential_reload_hard_regs
,
4916 before_p
, curr_insn
, max_uid
))
4919 lra_risky_transformations_p
= true;
4922 usage_insns
[src_regno
].check
= 0;
4924 use_insn
= PREV_INSN (curr_insn
);
4926 if (NONDEBUG_INSN_P (curr_insn
))
4928 if (src_regno
< FIRST_PSEUDO_REGISTER
)
4929 add_to_hard_reg_set (&live_hard_regs
,
4930 reg
->biggest_mode
, src_regno
);
4932 add_to_hard_reg_set (&live_hard_regs
,
4933 PSEUDO_REGNO_MODE (src_regno
),
4934 reg_renumber
[src_regno
]);
4936 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
4939 for (i
= 0; i
< to_inherit_num
; i
++)
4941 src_regno
= to_inherit
[i
].regno
;
4942 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
4943 curr_insn
, to_inherit
[i
].insns
))
4946 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4949 /* We reached the start of the current basic block. */
4950 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
4951 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
4953 /* We reached the beginning of the current block -- do
4954 rest of spliting in the current BB. */
4955 to_process
= df_get_live_in (curr_bb
);
4956 if (BLOCK_FOR_INSN (head
) != curr_bb
)
4958 /* We are somewhere in the middle of EBB. */
4959 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
4960 curr_bb
, &temp_bitmap
);
4961 to_process
= &temp_bitmap
;
4964 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4966 if ((int) j
>= lra_constraint_new_regno_start
)
4968 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4969 && usage_insns
[j
].check
== curr_usage_insns_check
4970 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
4972 if (need_for_split_p (potential_reload_hard_regs
, j
))
4974 if (lra_dump_file
!= NULL
&& head_p
)
4976 fprintf (lra_dump_file
,
4977 " ----------------------------------\n");
4980 if (split_reg (false, j
, bb_note (curr_bb
),
4984 usage_insns
[j
].check
= 0;
4992 /* This value affects EBB forming. If probability of edge from EBB to
4993 a BB is not greater than the following value, we don't add the BB
4995 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
4997 /* Current number of inheritance/split iteration. */
4998 int lra_inheritance_iter
;
5000 /* Entry function for inheritance/split pass. */
5002 lra_inheritance (void)
5005 basic_block bb
, start_bb
;
5008 lra_inheritance_iter
++;
5009 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5011 timevar_push (TV_LRA_INHERITANCE
);
5012 if (lra_dump_file
!= NULL
)
5013 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5014 lra_inheritance_iter
);
5015 curr_usage_insns_check
= 0;
5016 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5017 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5018 usage_insns
[i
].check
= 0;
5019 bitmap_initialize (&check_only_regs
, ®_obstack
);
5020 bitmap_initialize (&live_regs
, ®_obstack
);
5021 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5022 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5026 if (lra_dump_file
!= NULL
)
5027 fprintf (lra_dump_file
, "EBB");
5028 /* Form a EBB starting with BB. */
5029 bitmap_clear (&ebb_global_regs
);
5030 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5033 if (lra_dump_file
!= NULL
)
5034 fprintf (lra_dump_file
, " %d", bb
->index
);
5035 if (bb
->next_bb
== EXIT_BLOCK_PTR
|| LABEL_P (BB_HEAD (bb
->next_bb
)))
5037 e
= find_fallthru_edge (bb
->succs
);
5040 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5044 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5045 if (lra_dump_file
!= NULL
)
5046 fprintf (lra_dump_file
, "\n");
5047 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5048 /* Remember that the EBB head and tail can change in
5050 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5052 bitmap_clear (&ebb_global_regs
);
5053 bitmap_clear (&temp_bitmap
);
5054 bitmap_clear (&live_regs
);
5055 bitmap_clear (&check_only_regs
);
5058 timevar_pop (TV_LRA_INHERITANCE
);
5063 /* This page contains code to undo failed inheritance/split
5066 /* Current number of iteration undoing inheritance/split. */
5067 int lra_undo_inheritance_iter
;
5069 /* Fix BB live info LIVE after removing pseudos created on pass doing
5070 inheritance/split which are REMOVED_PSEUDOS. */
5072 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5077 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5078 if (bitmap_clear_bit (live
, regno
))
5079 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5082 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5087 if (GET_CODE (reg
) == SUBREG
)
5088 reg
= SUBREG_REG (reg
);
5094 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5095 return true if we did any change. The undo transformations for
5096 inheritance looks like
5100 p <- i, i <- p, and i <- i3
5101 where p is original pseudo from which inheritance pseudo i was
5102 created, i and i3 are removed inheritance pseudos, i2 is another
5103 not removed inheritance pseudo. All split pseudos or other
5104 occurrences of removed inheritance pseudos are changed on the
5105 corresponding original pseudos.
5107 The function also schedules insns changed and created during
5108 inheritance/split pass for processing by the subsequent constraint
5111 remove_inheritance_pseudos (bitmap remove_pseudos
)
5114 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5115 rtx set
, prev_set
, prev_insn
;
5116 bool change_p
, done_p
;
5118 change_p
= ! bitmap_empty_p (remove_pseudos
);
5119 /* We can not finish the function right away if CHANGE_P is true
5120 because we need to marks insns affected by previous
5121 inheritance/split pass for processing by the subsequent
5125 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5126 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5127 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5129 if (! INSN_P (curr_insn
))
5132 sregno
= dregno
= -1;
5133 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5134 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5136 dregno
= get_regno (SET_DEST (set
));
5137 sregno
= get_regno (SET_SRC (set
));
5140 if (sregno
>= 0 && dregno
>= 0)
5142 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5143 && (lra_reg_info
[sregno
].restore_regno
== dregno
5144 || (bitmap_bit_p (remove_pseudos
, dregno
)
5145 && (lra_reg_info
[sregno
].restore_regno
5146 == lra_reg_info
[dregno
].restore_regno
))))
5147 || (bitmap_bit_p (remove_pseudos
, dregno
)
5148 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5149 /* One of the following cases:
5150 original <- removed inheritance pseudo
5151 removed inherit pseudo <- another removed inherit pseudo
5152 removed inherit pseudo <- original pseudo
5154 removed_split_pseudo <- original_reg
5155 original_reg <- removed_split_pseudo */
5157 if (lra_dump_file
!= NULL
)
5159 fprintf (lra_dump_file
, " Removing %s:\n",
5160 bitmap_bit_p (&lra_split_regs
, sregno
)
5161 || bitmap_bit_p (&lra_split_regs
, dregno
)
5162 ? "split" : "inheritance");
5163 dump_insn_slim (lra_dump_file
, curr_insn
);
5165 lra_set_insn_deleted (curr_insn
);
5168 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5169 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5171 /* Search the following pattern:
5172 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5173 original_pseudo <- inherit_or_split_pseudo1
5174 where the 2nd insn is the current insn and
5175 inherit_or_split_pseudo2 is not removed. If it is found,
5176 change the current insn onto:
5177 original_pseudo <- inherit_or_split_pseudo2. */
5178 for (prev_insn
= PREV_INSN (curr_insn
);
5179 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5180 prev_insn
= PREV_INSN (prev_insn
))
5182 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5183 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5184 /* There should be no subregs in insn we are
5185 searching because only the original reg might
5186 be in subreg when we changed the mode of
5187 load/store for splitting. */
5188 && REG_P (SET_DEST (prev_set
))
5189 && REG_P (SET_SRC (prev_set
))
5190 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5191 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5192 >= FIRST_PSEUDO_REGISTER
)
5193 /* As we consider chain of inheritance or
5194 splitting described in above comment we should
5195 check that sregno and prev_sregno were
5196 inheritance/split pseudos created from the
5197 same original regno. */
5198 && (lra_reg_info
[sregno
].restore_regno
5199 == lra_reg_info
[prev_sregno
].restore_regno
)
5200 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5202 lra_assert (GET_MODE (SET_SRC (prev_set
))
5203 == GET_MODE (regno_reg_rtx
[sregno
]));
5204 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5205 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5207 SET_SRC (set
) = SET_SRC (prev_set
);
5208 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5209 lra_set_used_insn_alternative_by_uid
5210 (INSN_UID (curr_insn
), -1);
5212 if (lra_dump_file
!= NULL
)
5214 fprintf (lra_dump_file
, " Change reload insn:\n");
5215 dump_insn_slim (lra_dump_file
, curr_insn
);
5222 struct lra_insn_reg
*reg
;
5223 bool restored_regs_p
= false;
5224 bool kept_regs_p
= false;
5226 curr_id
= lra_get_insn_recog_data (curr_insn
);
5227 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5230 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5231 if (restore_regno
>= 0)
5233 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5235 substitute_pseudo (&curr_insn
, regno
,
5236 regno_reg_rtx
[restore_regno
]);
5237 restored_regs_p
= true;
5243 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5245 /* The instruction has changed since the previous
5246 constraints pass. */
5247 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5248 lra_set_used_insn_alternative_by_uid
5249 (INSN_UID (curr_insn
), -1);
5251 else if (restored_regs_p
)
5252 /* The instruction has been restored to the form that
5253 it had during the previous constraints pass. */
5254 lra_update_insn_regno_info (curr_insn
);
5255 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5257 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5258 dump_insn_slim (lra_dump_file
, curr_insn
);
5266 /* Entry function for undoing inheritance/split transformation. Return true
5267 if we did any RTL change in this pass. */
5269 lra_undo_inheritance (void)
5272 int restore_regno
, hard_regno
;
5273 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5274 bitmap_head remove_pseudos
;
5278 lra_undo_inheritance_iter
++;
5279 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5281 if (lra_dump_file
!= NULL
)
5282 fprintf (lra_dump_file
,
5283 "\n********** Undoing inheritance #%d: **********\n\n",
5284 lra_undo_inheritance_iter
);
5285 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5286 n_inherit
= n_all_inherit
= 0;
5287 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5288 if (lra_reg_info
[regno
].restore_regno
>= 0)
5291 if (reg_renumber
[regno
] < 0)
5292 bitmap_set_bit (&remove_pseudos
, regno
);
5296 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5297 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5298 n_inherit
, n_all_inherit
,
5299 (double) n_inherit
/ n_all_inherit
* 100);
5300 n_split
= n_all_split
= 0;
5301 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5302 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5305 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5306 ? reg_renumber
[restore_regno
] : restore_regno
);
5307 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5308 bitmap_set_bit (&remove_pseudos
, regno
);
5312 if (lra_dump_file
!= NULL
)
5313 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5314 regno
, restore_regno
);
5317 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5318 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5319 n_split
, n_all_split
,
5320 (double) n_split
/ n_all_split
* 100);
5321 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5322 bitmap_clear (&remove_pseudos
);
5323 /* Clear restore_regnos. */
5324 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5325 lra_reg_info
[regno
].restore_regno
= -1;
5326 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5327 lra_reg_info
[regno
].restore_regno
= -1;