1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
124 #include "hash-set.h"
126 #include "machmode.h"
128 #include "function.h"
131 #include "statistics.h"
132 #include "double-int.h"
134 #include "fixed-value.h"
136 #include "wide-int.h"
143 #include "emit-rtl.h"
148 #include "dominance.h"
151 #include "basic-block.h"
156 #include "rtl-error.h"
159 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
160 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
162 static int bb_reload_num
;
164 /* The current insn being processed and corresponding its single set
165 (NULL otherwise), its data (basic block, the insn data, the insn
166 static data, and the mode of each operand). */
167 static rtx_insn
*curr_insn
;
168 static rtx curr_insn_set
;
169 static basic_block curr_bb
;
170 static lra_insn_recog_data_t curr_id
;
171 static struct lra_static_insn_data
*curr_static_id
;
172 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
176 /* Start numbers for new registers and insns at the current constraints
178 static int new_regno_start
;
179 static int new_insn_uid_start
;
181 /* If LOC is nonnull, strip any outer subreg from it. */
183 strip_subreg (rtx
*loc
)
185 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
188 /* Return hard regno of REGNO or if it is was not assigned to a hard
189 register, use a hard register from its allocno class. */
191 get_try_hard_regno (int regno
)
194 enum reg_class rclass
;
196 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
197 hard_regno
= lra_get_regno_hard_regno (regno
);
200 rclass
= lra_get_allocno_class (regno
);
201 if (rclass
== NO_REGS
)
203 return ira_class_hard_regs
[rclass
][0];
206 /* Return final hard regno (plus offset) which will be after
207 elimination. We do this for matching constraints because the final
208 hard regno could have a different class. */
210 get_final_hard_regno (int hard_regno
, int offset
)
214 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
215 return hard_regno
+ offset
;
218 /* Return hard regno of X after removing subreg and making
219 elimination. If X is not a register or subreg of register, return
220 -1. For pseudo use its assignment. */
222 get_hard_regno (rtx x
)
225 int offset
, hard_regno
;
228 if (GET_CODE (x
) == SUBREG
)
229 reg
= SUBREG_REG (x
);
232 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
233 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
237 if (GET_CODE (x
) == SUBREG
)
238 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
239 SUBREG_BYTE (x
), GET_MODE (x
));
240 return get_final_hard_regno (hard_regno
, offset
);
243 /* If REGNO is a hard register or has been allocated a hard register,
244 return the class of that register. If REGNO is a reload pseudo
245 created by the current constraints pass, return its allocno class.
246 Return NO_REGS otherwise. */
247 static enum reg_class
248 get_reg_class (int regno
)
252 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
253 hard_regno
= lra_get_regno_hard_regno (regno
);
256 hard_regno
= get_final_hard_regno (hard_regno
, 0);
257 return REGNO_REG_CLASS (hard_regno
);
259 if (regno
>= new_regno_start
)
260 return lra_get_allocno_class (regno
);
264 /* Return true if REG satisfies (or will satisfy) reg class constraint
265 CL. Use elimination first if REG is a hard register. If REG is a
266 reload pseudo created by this constraints pass, assume that it will
267 be allocated a hard register from its allocno class, but allow that
268 class to be narrowed to CL if it is currently a superset of CL.
270 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
271 REGNO (reg), or NO_REGS if no change in its class was needed. */
273 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
275 enum reg_class rclass
, common_class
;
276 machine_mode reg_mode
;
277 int class_size
, hard_regno
, nregs
, i
, j
;
278 int regno
= REGNO (reg
);
280 if (new_class
!= NULL
)
281 *new_class
= NO_REGS
;
282 if (regno
< FIRST_PSEUDO_REGISTER
)
285 rtx
*final_loc
= &final_reg
;
287 lra_eliminate_reg_if_possible (final_loc
);
288 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
290 reg_mode
= GET_MODE (reg
);
291 rclass
= get_reg_class (regno
);
292 if (regno
< new_regno_start
293 /* Do not allow the constraints for reload instructions to
294 influence the classes of new pseudos. These reloads are
295 typically moves that have many alternatives, and restricting
296 reload pseudos for one alternative may lead to situations
297 where other reload pseudos are no longer allocatable. */
298 || (INSN_UID (curr_insn
) >= new_insn_uid_start
299 && curr_insn_set
!= NULL
300 && ((OBJECT_P (SET_SRC (curr_insn_set
))
301 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
302 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
303 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
304 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
305 /* When we don't know what class will be used finally for reload
306 pseudos, we use ALL_REGS. */
307 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
308 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
309 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
310 lra_no_alloc_regs
)));
313 common_class
= ira_reg_class_subset
[rclass
][cl
];
314 if (new_class
!= NULL
)
315 *new_class
= common_class
;
316 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
319 /* Check that there are enough allocatable regs. */
320 class_size
= ira_class_hard_regs_num
[common_class
];
321 for (i
= 0; i
< class_size
; i
++)
323 hard_regno
= ira_class_hard_regs
[common_class
][i
];
324 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
327 for (j
= 0; j
< nregs
; j
++)
328 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
329 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
339 /* Return true if REGNO satisfies a memory constraint. */
343 return get_reg_class (regno
) == NO_REGS
;
346 /* Return 1 if ADDR is a valid memory address for mode MODE in address
347 space AS, and check that each pseudo has the proper kind of hard
350 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
351 rtx addr
, addr_space_t as
)
353 #ifdef GO_IF_LEGITIMATE_ADDRESS
354 lra_assert (ADDR_SPACE_GENERIC_P (as
));
355 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
361 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
366 /* Temporarily eliminates registers in an address (for the lifetime of
368 class address_eliminator
{
370 address_eliminator (struct address_info
*ad
);
371 ~address_eliminator ();
374 struct address_info
*m_ad
;
382 address_eliminator::address_eliminator (struct address_info
*ad
)
384 m_base_loc (strip_subreg (ad
->base_term
)),
385 m_base_reg (NULL_RTX
),
386 m_index_loc (strip_subreg (ad
->index_term
)),
387 m_index_reg (NULL_RTX
)
389 if (m_base_loc
!= NULL
)
391 m_base_reg
= *m_base_loc
;
392 lra_eliminate_reg_if_possible (m_base_loc
);
393 if (m_ad
->base_term2
!= NULL
)
394 *m_ad
->base_term2
= *m_ad
->base_term
;
396 if (m_index_loc
!= NULL
)
398 m_index_reg
= *m_index_loc
;
399 lra_eliminate_reg_if_possible (m_index_loc
);
403 address_eliminator::~address_eliminator ()
405 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
407 *m_base_loc
= m_base_reg
;
408 if (m_ad
->base_term2
!= NULL
)
409 *m_ad
->base_term2
= *m_ad
->base_term
;
411 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
412 *m_index_loc
= m_index_reg
;
415 /* Return true if the eliminated form of AD is a legitimate target address. */
417 valid_address_p (struct address_info
*ad
)
419 address_eliminator
eliminator (ad
);
420 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
423 /* Return true if the eliminated form of memory reference OP satisfies
424 extra memory constraint CONSTRAINT. */
426 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
428 struct address_info ad
;
430 decompose_mem_address (&ad
, op
);
431 address_eliminator
eliminator (&ad
);
432 return constraint_satisfied_p (op
, constraint
);
435 /* Return true if the eliminated form of address AD satisfies extra
436 address constraint CONSTRAINT. */
438 satisfies_address_constraint_p (struct address_info
*ad
,
439 enum constraint_num constraint
)
441 address_eliminator
eliminator (ad
);
442 return constraint_satisfied_p (*ad
->outer
, constraint
);
445 /* Return true if the eliminated form of address OP satisfies extra
446 address constraint CONSTRAINT. */
448 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
450 struct address_info ad
;
452 decompose_lea_address (&ad
, &op
);
453 return satisfies_address_constraint_p (&ad
, constraint
);
456 /* Initiate equivalences for LRA. As we keep original equivalences
457 before any elimination, we need to make copies otherwise any change
458 in insns might change the equivalences. */
460 lra_init_equiv (void)
462 ira_expand_reg_equiv ();
463 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
467 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
468 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
469 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
470 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
474 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
476 /* Update equivalence for REGNO. We need to this as the equivalence
477 might contain other pseudos which are changed by their
480 update_equiv (int regno
)
484 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
485 ira_reg_equiv
[regno
].memory
486 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
488 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
489 ira_reg_equiv
[regno
].invariant
490 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
494 /* If we have decided to substitute X with another value, return that
495 value, otherwise return X. */
502 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
503 || ! ira_reg_equiv
[regno
].defined_p
504 || ! ira_reg_equiv
[regno
].profitable_p
505 || lra_get_regno_hard_regno (regno
) >= 0)
507 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
509 if (targetm
.cannot_substitute_mem_equiv_p (res
))
513 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
515 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
520 /* If we have decided to substitute X with the equivalent value,
521 return that value after elimination for INSN, otherwise return
524 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
526 rtx res
= get_equiv (x
);
528 if (x
== res
|| CONSTANT_P (res
))
530 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
531 0, false, false, true);
534 /* Set up curr_operand_mode. */
536 init_curr_operand_mode (void)
538 int nop
= curr_static_id
->n_operands
;
539 for (int i
= 0; i
< nop
; i
++)
541 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
542 if (mode
== VOIDmode
)
544 /* The .md mode for address operands is the mode of the
545 addressed value rather than the mode of the address itself. */
546 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
549 mode
= curr_static_id
->operand
[i
].mode
;
551 curr_operand_mode
[i
] = mode
;
557 /* The page contains code to reuse input reloads. */
559 /* Structure describes input reload of the current insns. */
562 /* Reloaded value. */
564 /* Reload pseudo used. */
568 /* The number of elements in the following array. */
569 static int curr_insn_input_reloads_num
;
570 /* Array containing info about input reloads. It is used to find the
571 same input reload and reuse the reload pseudo in this case. */
572 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
574 /* Initiate data concerning reuse of input reloads for the current
577 init_curr_insn_input_reloads (void)
579 curr_insn_input_reloads_num
= 0;
582 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
583 created input reload pseudo (only if TYPE is not OP_OUT). Don't
584 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
585 wrapped up in SUBREG. The result pseudo is returned through
586 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
587 reused the already created input reload pseudo. Use TITLE to
588 describe new registers for debug purposes. */
590 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
591 enum reg_class rclass
, bool in_subreg_p
,
592 const char *title
, rtx
*result_reg
)
595 enum reg_class new_class
;
600 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
603 /* Prevent reuse value of expression with side effects,
604 e.g. volatile memory. */
605 if (! side_effects_p (original
))
606 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
607 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
608 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
610 rtx reg
= curr_insn_input_reloads
[i
].reg
;
612 /* If input is equal to original and both are VOIDmode,
613 GET_MODE (reg) might be still different from mode.
614 Ensure we don't return *result_reg with wrong mode. */
615 if (GET_MODE (reg
) != mode
)
619 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
621 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
622 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
626 if (lra_dump_file
!= NULL
)
628 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
629 dump_value_slim (lra_dump_file
, original
, 1);
631 if (new_class
!= lra_get_allocno_class (regno
))
632 lra_change_class (regno
, new_class
, ", change to", false);
633 if (lra_dump_file
!= NULL
)
634 fprintf (lra_dump_file
, "\n");
637 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
638 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
639 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
640 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
646 /* The page contains code to extract memory address parts. */
648 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
650 ok_for_index_p_nonstrict (rtx reg
)
652 unsigned regno
= REGNO (reg
);
654 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
657 /* A version of regno_ok_for_base_p for use here, when all pseudos
658 should count as OK. Arguments as for regno_ok_for_base_p. */
660 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
661 enum rtx_code outer_code
, enum rtx_code index_code
)
663 unsigned regno
= REGNO (reg
);
665 if (regno
>= FIRST_PSEUDO_REGISTER
)
667 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
672 /* The page contains major code to choose the current insn alternative
673 and generate reloads for it. */
675 /* Return the offset from REGNO of the least significant register
678 This function is used to tell whether two registers satisfy
679 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
681 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
682 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
684 lra_constraint_offset (int regno
, machine_mode mode
)
686 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
687 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
688 && SCALAR_INT_MODE_P (mode
))
689 return hard_regno_nregs
[regno
][mode
] - 1;
693 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
694 if they are the same hard reg, and has special hacks for
695 auto-increment and auto-decrement. This is specifically intended for
696 process_alt_operands to use in determining whether two operands
697 match. X is the operand whose number is the lower of the two.
699 It is supposed that X is the output operand and Y is the input
700 operand. Y_HARD_REGNO is the final hard regno of register Y or
701 register in subreg Y as we know it now. Otherwise, it is a
704 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
707 RTX_CODE code
= GET_CODE (x
);
712 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
713 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
717 i
= get_hard_regno (x
);
721 if ((j
= y_hard_regno
) < 0)
724 i
+= lra_constraint_offset (i
, GET_MODE (x
));
725 j
+= lra_constraint_offset (j
, GET_MODE (y
));
730 /* If two operands must match, because they are really a single
731 operand of an assembler insn, then two post-increments are invalid
732 because the assembler insn would increment only once. On the
733 other hand, a post-increment matches ordinary indexing if the
734 post-increment is the output operand. */
735 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
736 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
738 /* Two pre-increments are invalid because the assembler insn would
739 increment only once. On the other hand, a pre-increment matches
740 ordinary indexing if the pre-increment is the input operand. */
741 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
742 || GET_CODE (y
) == PRE_MODIFY
)
743 return operands_match_p (x
, XEXP (y
, 0), -1);
747 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
748 && x
== SUBREG_REG (y
))
750 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
751 && SUBREG_REG (x
) == y
)
754 /* Now we have disposed of all the cases in which different rtx
756 if (code
!= GET_CODE (y
))
759 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
760 if (GET_MODE (x
) != GET_MODE (y
))
769 return LABEL_REF_LABEL (x
) == LABEL_REF_LABEL (y
);
771 return XSTR (x
, 0) == XSTR (y
, 0);
777 /* Compare the elements. If any pair of corresponding elements fail
778 to match, return false for the whole things. */
780 fmt
= GET_RTX_FORMAT (code
);
781 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
787 if (XWINT (x
, i
) != XWINT (y
, i
))
792 if (XINT (x
, i
) != XINT (y
, i
))
797 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
806 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
808 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
810 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
816 /* It is believed that rtx's at this level will never
817 contain anything but integers and other rtx's, except for
818 within LABEL_REFs and SYMBOL_REFs. */
826 /* True if X is a constant that can be forced into the constant pool.
827 MODE is the mode of the operand, or VOIDmode if not known. */
828 #define CONST_POOL_OK_P(MODE, X) \
829 ((MODE) != VOIDmode \
831 && GET_CODE (X) != HIGH \
832 && !targetm.cannot_force_const_mem (MODE, X))
834 /* True if C is a non-empty register class that has too few registers
835 to be safely used as a reload target class. */
836 #define SMALL_REGISTER_CLASS_P(C) \
837 (ira_class_hard_regs_num [(C)] == 1 \
838 || (ira_class_hard_regs_num [(C)] >= 1 \
839 && targetm.class_likely_spilled_p (C)))
841 /* If REG is a reload pseudo, try to make its class satisfying CL. */
843 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
845 enum reg_class rclass
;
847 /* Do not make more accurate class from reloads generated. They are
848 mostly moves with a lot of constraints. Making more accurate
849 class may results in very narrow class and impossibility of find
850 registers for several reloads of one insn. */
851 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
853 if (GET_CODE (reg
) == SUBREG
)
854 reg
= SUBREG_REG (reg
);
855 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
857 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
858 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
861 /* Generate reloads for matching OUT and INS (array of input operand
862 numbers with end marker -1) with reg class GOAL_CLASS. Add input
863 and output reloads correspondingly to the lists *BEFORE and *AFTER.
864 OUT might be negative. In this case we generate input reloads for
865 matched input operands INS. */
867 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
868 rtx_insn
**before
, rtx_insn
**after
)
871 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
872 machine_mode inmode
, outmode
;
873 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
874 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
876 inmode
= curr_operand_mode
[ins
[0]];
877 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
878 push_to_sequence (*before
);
879 if (inmode
!= outmode
)
881 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
884 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
886 if (SCALAR_INT_MODE_P (inmode
))
887 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
889 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
890 LRA_SUBREG_P (new_out_reg
) = 1;
891 /* If the input reg is dying here, we can use the same hard
892 register for REG and IN_RTX. We do it only for original
893 pseudos as reload pseudos can die although original
894 pseudos still live where reload pseudos dies. */
895 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
896 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
897 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
902 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
904 if (SCALAR_INT_MODE_P (outmode
))
905 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
907 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
908 /* NEW_IN_REG is non-paradoxical subreg. We don't want
909 NEW_OUT_REG living above. We add clobber clause for
910 this. This is just a temporary clobber. We can remove
911 it at the end of LRA work. */
912 clobber
= emit_clobber (new_out_reg
);
913 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
914 LRA_SUBREG_P (new_in_reg
) = 1;
915 if (GET_CODE (in_rtx
) == SUBREG
)
917 rtx subreg_reg
= SUBREG_REG (in_rtx
);
919 /* If SUBREG_REG is dying here and sub-registers IN_RTX
920 and NEW_IN_REG are similar, we can use the same hard
921 register for REG and SUBREG_REG. */
922 if (REG_P (subreg_reg
)
923 && (int) REGNO (subreg_reg
) < lra_new_regno_start
924 && GET_MODE (subreg_reg
) == outmode
925 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
926 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
927 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
933 /* Pseudos have values -- see comments for lra_reg_info.
934 Different pseudos with the same value do not conflict even if
935 they live in the same place. When we create a pseudo we
936 assign value of original pseudo (if any) from which we
937 created the new pseudo. If we create the pseudo from the
938 input pseudo, the new pseudo will no conflict with the input
939 pseudo which is wrong when the input pseudo lives after the
940 insn and as the new pseudo value is changed by the insn
941 output. Therefore we create the new pseudo from the output.
943 We cannot reuse the current output register because we might
944 have a situation like "a <- a op b", where the constraints
945 force the second input operand ("b") to match the output
946 operand ("a"). "b" must then be copied into a new register
947 so that it doesn't clobber the current value of "a". */
949 new_in_reg
= new_out_reg
950 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
953 /* In operand can be got from transformations before processing insn
954 constraints. One example of such transformations is subreg
955 reloading (see function simplify_operand_subreg). The new
956 pseudos created by the transformations might have inaccurate
957 class (ALL_REGS) and we should make their classes more
959 narrow_reload_pseudo_class (in_rtx
, goal_class
);
960 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
961 *before
= get_insns ();
963 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
966 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
967 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
968 *curr_id
->operand_loc
[in
] = new_in_reg
;
970 lra_update_dups (curr_id
, ins
);
973 /* See a comment for the input operand above. */
974 narrow_reload_pseudo_class (out_rtx
, goal_class
);
975 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
978 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
980 *after
= get_insns ();
983 *curr_id
->operand_loc
[out
] = new_out_reg
;
984 lra_update_dup (curr_id
, out
);
987 /* Return register class which is union of all reg classes in insn
988 constraint alternative string starting with P. */
989 static enum reg_class
990 reg_class_from_constraints (const char *p
)
993 enum reg_class op_class
= NO_REGS
;
996 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1003 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1007 enum constraint_num cn
= lookup_constraint (p
);
1008 enum reg_class cl
= reg_class_for_constraint (cn
);
1011 if (insn_extra_address_constraint (cn
))
1013 = (reg_class_subunion
1014 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1015 ADDRESS
, SCRATCH
)]);
1019 op_class
= reg_class_subunion
[op_class
][cl
];
1022 while ((p
+= len
), c
);
1026 /* If OP is a register, return the class of the register as per
1027 get_reg_class, otherwise return NO_REGS. */
1028 static inline enum reg_class
1029 get_op_class (rtx op
)
1031 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1034 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1035 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1036 SUBREG for VAL to make them equal. */
1038 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1040 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1042 /* Usually size of mem_pseudo is greater than val size but in
1043 rare cases it can be less as it can be defined by target
1044 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1047 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1048 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1050 LRA_SUBREG_P (val
) = 1;
1054 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1055 LRA_SUBREG_P (mem_pseudo
) = 1;
1058 return as_a
<rtx_insn
*> (to_p
1059 ? gen_move_insn (mem_pseudo
, val
)
1060 : gen_move_insn (val
, mem_pseudo
));
1063 /* Process a special case insn (register move), return true if we
1064 don't need to process it anymore. INSN should be a single set
1065 insn. Set up that RTL was changed through CHANGE_P and macro
1066 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1069 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1072 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, scratch_reg
;
1074 enum reg_class dclass
, sclass
, secondary_class
;
1075 machine_mode sreg_mode
;
1076 secondary_reload_info sri
;
1078 lra_assert (curr_insn_set
!= NULL_RTX
);
1079 dreg
= dest
= SET_DEST (curr_insn_set
);
1080 sreg
= src
= SET_SRC (curr_insn_set
);
1081 if (GET_CODE (dest
) == SUBREG
)
1082 dreg
= SUBREG_REG (dest
);
1083 if (GET_CODE (src
) == SUBREG
)
1084 sreg
= SUBREG_REG (src
);
1085 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1087 sclass
= dclass
= NO_REGS
;
1089 dclass
= get_reg_class (REGNO (dreg
));
1090 if (dclass
== ALL_REGS
)
1091 /* ALL_REGS is used for new pseudos created by transformations
1092 like reload of SUBREG_REG (see function
1093 simplify_operand_subreg). We don't know their class yet. We
1094 should figure out the class from processing the insn
1095 constraints not in this fast path function. Even if ALL_REGS
1096 were a right class for the pseudo, secondary_... hooks usually
1097 are not define for ALL_REGS. */
1099 sreg_mode
= GET_MODE (sreg
);
1102 sclass
= get_reg_class (REGNO (sreg
));
1103 if (sclass
== ALL_REGS
)
1104 /* See comments above. */
1106 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1108 #ifdef SECONDARY_MEMORY_NEEDED
1109 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1110 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1111 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1112 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1120 if (! REG_P (dreg
) || ! REG_P (sreg
))
1122 sri
.prev_sri
= NULL
;
1123 sri
.icode
= CODE_FOR_nothing
;
1125 secondary_class
= NO_REGS
;
1126 /* Set up hard register for a reload pseudo for hook
1127 secondary_reload because some targets just ignore unassigned
1128 pseudos in the hook. */
1129 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1131 dregno
= REGNO (dreg
);
1132 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1136 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1138 sregno
= REGNO (sreg
);
1139 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1143 if (sclass
!= NO_REGS
)
1145 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1146 (reg_class_t
) sclass
,
1147 GET_MODE (src
), &sri
);
1148 if (sclass
== NO_REGS
1149 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1150 && dclass
!= NO_REGS
))
1152 enum reg_class old_sclass
= secondary_class
;
1153 secondary_reload_info old_sri
= sri
;
1155 sri
.prev_sri
= NULL
;
1156 sri
.icode
= CODE_FOR_nothing
;
1159 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1160 (reg_class_t
) dclass
,
1162 /* Check the target hook consistency. */
1164 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1165 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1166 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1169 reg_renumber
[sregno
] = -1;
1171 reg_renumber
[dregno
] = -1;
1172 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1176 if (secondary_class
!= NO_REGS
)
1177 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1181 if (old_sreg
!= sreg
)
1182 sreg
= copy_rtx (sreg
);
1183 if (sri
.icode
== CODE_FOR_nothing
)
1184 lra_emit_move (new_reg
, sreg
);
1187 enum reg_class scratch_class
;
1189 scratch_class
= (reg_class_from_constraints
1190 (insn_data
[sri
.icode
].operand
[2].constraint
));
1191 scratch_reg
= (lra_create_new_reg_with_unique_value
1192 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1193 scratch_class
, "scratch"));
1194 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1195 sreg
, scratch_reg
));
1197 before
= get_insns ();
1199 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1200 if (new_reg
!= NULL_RTX
)
1202 if (GET_CODE (src
) == SUBREG
)
1203 SUBREG_REG (src
) = new_reg
;
1205 SET_SRC (curr_insn_set
) = new_reg
;
1209 if (lra_dump_file
!= NULL
)
1211 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1212 dump_insn_slim (lra_dump_file
, curr_insn
);
1214 lra_set_insn_deleted (curr_insn
);
1220 /* The following data describe the result of process_alt_operands.
1221 The data are used in curr_insn_transform to generate reloads. */
1223 /* The chosen reg classes which should be used for the corresponding
1225 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1226 /* True if the operand should be the same as another operand and that
1227 other operand does not need a reload. */
1228 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1229 /* True if the operand does not need a reload. */
1230 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1231 /* True if the operand can be offsetable memory. */
1232 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1233 /* The number of an operand to which given operand can be matched to. */
1234 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1235 /* The number of elements in the following array. */
1236 static int goal_alt_dont_inherit_ops_num
;
1237 /* Numbers of operands whose reload pseudos should not be inherited. */
1238 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1239 /* True if the insn commutative operands should be swapped. */
1240 static bool goal_alt_swapped
;
1241 /* The chosen insn alternative. */
1242 static int goal_alt_number
;
1244 /* The following five variables are used to choose the best insn
1245 alternative. They reflect final characteristics of the best
1248 /* Number of necessary reloads and overall cost reflecting the
1249 previous value and other unpleasantness of the best alternative. */
1250 static int best_losers
, best_overall
;
1251 /* Overall number hard registers used for reloads. For example, on
1252 some targets we need 2 general registers to reload DFmode and only
1253 one floating point register. */
1254 static int best_reload_nregs
;
1255 /* Overall number reflecting distances of previous reloading the same
1256 value. The distances are counted from the current BB start. It is
1257 used to improve inheritance chances. */
1258 static int best_reload_sum
;
1260 /* True if the current insn should have no correspondingly input or
1262 static bool no_input_reloads_p
, no_output_reloads_p
;
1264 /* True if we swapped the commutative operands in the current
1266 static int curr_swapped
;
1268 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1269 register of class CL. Add any input reloads to list BEFORE. AFTER
1270 is nonnull if *LOC is an automodified value; handle that case by
1271 adding the required output reloads to list AFTER. Return true if
1272 the RTL was changed.
1274 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1275 register. Return false if the address register is correct. */
1277 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1281 enum reg_class rclass
, new_class
;
1285 bool subreg_p
, before_p
= false;
1287 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1289 loc
= &SUBREG_REG (*loc
);
1291 mode
= GET_MODE (reg
);
1296 /* Always reload memory in an address even if the target supports
1298 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1303 regno
= REGNO (reg
);
1304 rclass
= get_reg_class (regno
);
1306 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1308 if (lra_dump_file
!= NULL
)
1310 fprintf (lra_dump_file
,
1311 "Changing pseudo %d in address of insn %u on equiv ",
1312 REGNO (reg
), INSN_UID (curr_insn
));
1313 dump_value_slim (lra_dump_file
, *loc
, 1);
1314 fprintf (lra_dump_file
, "\n");
1316 *loc
= copy_rtx (*loc
);
1318 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1323 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1324 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1327 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1331 lra_change_class (regno
, new_class
, " Change to", true);
1339 push_to_sequence (*before
);
1340 lra_emit_move (new_reg
, reg
);
1341 *before
= get_insns ();
1348 lra_emit_move (reg
, new_reg
);
1350 *after
= get_insns ();
1356 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1357 the insn to be inserted before curr insn. AFTER returns the
1358 the insn to be inserted after curr insn. ORIGREG and NEWREG
1359 are the original reg and new reg for reload. */
1361 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1366 push_to_sequence (*before
);
1367 lra_emit_move (newreg
, origreg
);
1368 *before
= get_insns ();
1374 lra_emit_move (origreg
, newreg
);
1376 *after
= get_insns ();
1381 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1383 /* Make reloads for subreg in operand NOP with internal subreg mode
1384 REG_MODE, add new reloads for further processing. Return true if
1385 any reload was generated. */
1387 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1390 rtx_insn
*before
, *after
;
1393 rtx operand
= *curr_id
->operand_loc
[nop
];
1394 enum reg_class regclass
;
1397 before
= after
= NULL
;
1399 if (GET_CODE (operand
) != SUBREG
)
1402 mode
= GET_MODE (operand
);
1403 reg
= SUBREG_REG (operand
);
1404 type
= curr_static_id
->operand
[nop
].type
;
1405 /* If we change address for paradoxical subreg of memory, the
1406 address might violate the necessary alignment or the access might
1407 be slow. So take this into consideration. We should not worry
1408 about access beyond allocated memory for paradoxical memory
1409 subregs as we don't substitute such equiv memory (see processing
1410 equivalences in function lra_constraints) and because for spilled
1411 pseudos we allocate stack memory enough for the biggest
1412 corresponding paradoxical subreg. */
1414 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1415 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1417 rtx subst
, old
= *curr_id
->operand_loc
[nop
];
1419 alter_subreg (curr_id
->operand_loc
[nop
], false);
1420 subst
= *curr_id
->operand_loc
[nop
];
1421 lra_assert (MEM_P (subst
));
1422 if (! valid_address_p (GET_MODE (reg
), XEXP (reg
, 0),
1423 MEM_ADDR_SPACE (reg
))
1424 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1425 MEM_ADDR_SPACE (subst
)))
1427 /* If the address was valid and became invalid, prefer to reload
1428 the memory. Typical case is when the index scale should
1429 correspond the memory. */
1430 *curr_id
->operand_loc
[nop
] = old
;
1432 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1434 alter_subreg (curr_id
->operand_loc
[nop
], false);
1437 /* Put constant into memory when we have mixed modes. It generates
1438 a better code in most cases as it does not need a secondary
1439 reload memory. It also prevents LRA looping when LRA is using
1440 secondary reload memory again and again. */
1441 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1442 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1444 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1445 alter_subreg (curr_id
->operand_loc
[nop
], false);
1448 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1449 if there may be a problem accessing OPERAND in the outer
1452 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1453 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1454 /* Don't reload paradoxical subregs because we could be looping
1455 having repeatedly final regno out of hard regs range. */
1456 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1457 >= hard_regno_nregs
[hard_regno
][mode
])
1458 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1459 SUBREG_BYTE (operand
), mode
) < 0
1460 /* Don't reload subreg for matching reload. It is actually
1461 valid subreg in LRA. */
1462 && ! LRA_SUBREG_P (operand
))
1463 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1465 enum reg_class rclass
;
1468 /* There is a big probability that we will get the same class
1469 for the new pseudo and we will get the same insn which
1470 means infinite looping. So spill the new pseudo. */
1473 /* The class will be defined later in curr_insn_transform. */
1475 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1477 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1478 rclass
, TRUE
, "subreg reg", &new_reg
))
1480 bool insert_before
, insert_after
;
1481 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1483 insert_before
= (type
!= OP_OUT
1484 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1485 insert_after
= (type
!= OP_IN
);
1486 insert_move_for_subreg (insert_before
? &before
: NULL
,
1487 insert_after
? &after
: NULL
,
1490 SUBREG_REG (operand
) = new_reg
;
1491 lra_process_new_insns (curr_insn
, before
, after
,
1492 "Inserting subreg reload");
1495 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1496 IRA allocates hardreg to the inner pseudo reg according to its mode
1497 instead of the outermode, so the size of the hardreg may not be enough
1498 to contain the outermode operand, in that case we may need to insert
1499 reload for the reg. For the following two types of paradoxical subreg,
1500 we need to insert reload:
1501 1. If the op_type is OP_IN, and the hardreg could not be paired with
1502 other hardreg to contain the outermode operand
1503 (checked by in_hard_reg_set_p), we need to insert the reload.
1504 2. If the op_type is OP_OUT or OP_INOUT.
1506 Here is a paradoxical subreg example showing how the reload is generated:
1508 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1509 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1511 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1512 here, if reg107 is assigned to hardreg R15, because R15 is the last
1513 hardreg, compiler cannot find another hardreg to pair with R15 to
1514 contain TImode data. So we insert a TImode reload reg180 for it.
1515 After reload is inserted:
1517 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1518 (reg:DI 107 [ __comp ])) -1
1519 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1520 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1522 Two reload hard registers will be allocated to reg180 to save TImode data
1524 else if (REG_P (reg
)
1525 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1526 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1527 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1528 < hard_regno_nregs
[hard_regno
][mode
])
1529 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1531 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1534 /* The class will be defined later in curr_insn_transform. */
1535 enum reg_class rclass
1536 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1538 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1539 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1542 bool insert_before
, insert_after
;
1544 PUT_MODE (new_reg
, mode
);
1545 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1546 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1548 insert_before
= (type
!= OP_OUT
);
1549 insert_after
= (type
!= OP_IN
);
1550 insert_move_for_subreg (insert_before
? &before
: NULL
,
1551 insert_after
? &after
: NULL
,
1554 SUBREG_REG (operand
) = new_reg
;
1555 lra_process_new_insns (curr_insn
, before
, after
,
1556 "Inserting paradoxical subreg reload");
1562 /* Return TRUE if X refers for a hard register from SET. */
1564 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1566 int i
, j
, x_hard_regno
;
1573 code
= GET_CODE (x
);
1574 mode
= GET_MODE (x
);
1578 code
= GET_CODE (x
);
1579 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1580 mode
= GET_MODE (x
);
1585 x_hard_regno
= get_hard_regno (x
);
1586 return (x_hard_regno
>= 0
1587 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1591 struct address_info ad
;
1593 decompose_mem_address (&ad
, x
);
1594 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1596 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1599 fmt
= GET_RTX_FORMAT (code
);
1600 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1604 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1607 else if (fmt
[i
] == 'E')
1609 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1610 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1617 /* Return true if OP is a spilled pseudo. */
1619 spilled_pseudo_p (rtx op
)
1622 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1625 /* Return true if X is a general constant. */
1627 general_constant_p (rtx x
)
1629 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1633 reg_in_class_p (rtx reg
, enum reg_class cl
)
1636 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1637 return in_class_p (reg
, cl
, NULL
);
1640 /* Major function to choose the current insn alternative and what
1641 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1642 negative we should consider only this alternative. Return false if
1643 we can not choose the alternative or find how to reload the
1646 process_alt_operands (int only_alternative
)
1649 int nop
, overall
, nalt
;
1650 int n_alternatives
= curr_static_id
->n_alternatives
;
1651 int n_operands
= curr_static_id
->n_operands
;
1652 /* LOSERS counts the operands that don't fit this alternative and
1653 would require loading. */
1655 /* REJECT is a count of how undesirable this alternative says it is
1656 if any reloading is required. If the alternative matches exactly
1657 then REJECT is ignored, but otherwise it gets this much counted
1658 against it in addition to the reloading needed. */
1660 /* The number of elements in the following array. */
1661 int early_clobbered_regs_num
;
1662 /* Numbers of operands which are early clobber registers. */
1663 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1664 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1665 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1666 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1667 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1668 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1669 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1670 /* The number of elements in the following array. */
1671 int curr_alt_dont_inherit_ops_num
;
1672 /* Numbers of operands whose reload pseudos should not be inherited. */
1673 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1675 /* The register when the operand is a subreg of register, otherwise the
1677 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1678 /* The register if the operand is a register or subreg of register,
1680 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1681 int hard_regno
[MAX_RECOG_OPERANDS
];
1682 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1683 int reload_nregs
, reload_sum
;
1687 /* Calculate some data common for all alternatives to speed up the
1689 for (nop
= 0; nop
< n_operands
; nop
++)
1693 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1694 /* The real hard regno of the operand after the allocation. */
1695 hard_regno
[nop
] = get_hard_regno (op
);
1697 operand_reg
[nop
] = reg
= op
;
1698 biggest_mode
[nop
] = GET_MODE (op
);
1699 if (GET_CODE (op
) == SUBREG
)
1701 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1702 if (GET_MODE_SIZE (biggest_mode
[nop
])
1703 < GET_MODE_SIZE (GET_MODE (reg
)))
1704 biggest_mode
[nop
] = GET_MODE (reg
);
1707 operand_reg
[nop
] = NULL_RTX
;
1708 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1709 || ((int) REGNO (reg
)
1710 == lra_get_elimination_hard_regno (REGNO (reg
))))
1711 no_subreg_reg_operand
[nop
] = reg
;
1713 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1714 /* Just use natural mode for elimination result. It should
1715 be enough for extra constraints hooks. */
1716 = regno_reg_rtx
[hard_regno
[nop
]];
1719 /* The constraints are made of several alternatives. Each operand's
1720 constraint looks like foo,bar,... with commas separating the
1721 alternatives. The first alternatives for all operands go
1722 together, the second alternatives go together, etc.
1724 First loop over alternatives. */
1725 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1726 if (only_alternative
>= 0)
1727 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1729 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1731 /* Loop over operands for one constraint alternative. */
1732 if (!TEST_BIT (preferred
, nalt
))
1735 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1736 for (nop
= 0; nop
< n_operands
; nop
++)
1738 int inc
= (curr_static_id
1739 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1740 if (lra_dump_file
!= NULL
&& inc
!= 0)
1741 fprintf (lra_dump_file
,
1742 " Staticly defined alt reject+=%d\n", inc
);
1745 early_clobbered_regs_num
= 0;
1747 for (nop
= 0; nop
< n_operands
; nop
++)
1751 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1752 bool win
, did_match
, offmemok
, early_clobber_p
;
1753 /* false => this operand can be reloaded somehow for this
1756 /* true => this operand can be reloaded if the alternative
1759 /* True if a constant forced into memory would be OK for
1762 enum reg_class this_alternative
, this_costly_alternative
;
1763 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1764 bool this_alternative_match_win
, this_alternative_win
;
1765 bool this_alternative_offmemok
;
1768 enum constraint_num cn
;
1770 opalt_num
= nalt
* n_operands
+ nop
;
1771 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1773 /* Fast track for no constraints at all. */
1774 curr_alt
[nop
] = NO_REGS
;
1775 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1776 curr_alt_win
[nop
] = true;
1777 curr_alt_match_win
[nop
] = false;
1778 curr_alt_offmemok
[nop
] = false;
1779 curr_alt_matches
[nop
] = -1;
1783 op
= no_subreg_reg_operand
[nop
];
1784 mode
= curr_operand_mode
[nop
];
1786 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1789 early_clobber_p
= false;
1790 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1792 this_costly_alternative
= this_alternative
= NO_REGS
;
1793 /* We update set of possible hard regs besides its class
1794 because reg class might be inaccurate. For example,
1795 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1796 is translated in HI_REGS because classes are merged by
1797 pairs and there is no accurate intermediate class. */
1798 CLEAR_HARD_REG_SET (this_alternative_set
);
1799 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1800 this_alternative_win
= false;
1801 this_alternative_match_win
= false;
1802 this_alternative_offmemok
= false;
1803 this_alternative_matches
= -1;
1805 /* An empty constraint should be excluded by the fast
1807 lra_assert (*p
!= 0 && *p
!= ',');
1809 /* Scan this alternative's specs for this operand; set WIN
1810 if the operand fits any letter in this alternative.
1811 Otherwise, clear BADOP if this operand could fit some
1812 letter after reloads, or set WINREG if this operand could
1813 fit after reloads provided the constraint allows some
1818 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1828 early_clobber_p
= true;
1832 /* Ignore rest of this alternative. */
1836 case '0': case '1': case '2': case '3': case '4':
1837 case '5': case '6': case '7': case '8': case '9':
1842 m
= strtoul (p
, &end
, 10);
1845 lra_assert (nop
> m
);
1847 this_alternative_matches
= m
;
1848 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1849 /* We are supposed to match a previous operand.
1850 If we do, we win if that one did. If we do
1851 not, count both of the operands as losers.
1852 (This is too conservative, since most of the
1853 time only a single reload insn will be needed
1854 to make the two operands win. As a result,
1855 this alternative may be rejected when it is
1856 actually desirable.) */
1858 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1859 *curr_id
->operand_loc
[m
], m_hregno
))
1861 /* We should reject matching of an early
1862 clobber operand if the matching operand is
1863 not dying in the insn. */
1864 if (! curr_static_id
->operand
[m
].early_clobber
1865 || operand_reg
[nop
] == NULL_RTX
1866 || (find_regno_note (curr_insn
, REG_DEAD
,
1868 || REGNO (op
) == REGNO (operand_reg
[m
])))
1873 /* If we are matching a non-offsettable
1874 address where an offsettable address was
1875 expected, then we must reject this
1876 combination, because we can't reload
1878 if (curr_alt_offmemok
[m
]
1879 && MEM_P (*curr_id
->operand_loc
[m
])
1880 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1885 /* Operands don't match. Both operands must
1886 allow a reload register, otherwise we
1887 cannot make them match. */
1888 if (curr_alt
[m
] == NO_REGS
)
1890 /* Retroactively mark the operand we had to
1891 match as a loser, if it wasn't already and
1892 it wasn't matched to a register constraint
1893 (e.g it might be matched by memory). */
1895 && (operand_reg
[m
] == NULL_RTX
1896 || hard_regno
[m
] < 0))
1900 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1901 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1904 /* Prefer matching earlyclobber alternative as
1905 it results in less hard regs required for
1906 the insn than a non-matching earlyclobber
1908 if (curr_static_id
->operand
[m
].early_clobber
)
1910 if (lra_dump_file
!= NULL
)
1913 " %d Matching earlyclobber alt:"
1918 /* Otherwise we prefer no matching
1919 alternatives because it gives more freedom
1921 else if (operand_reg
[nop
] == NULL_RTX
1922 || (find_regno_note (curr_insn
, REG_DEAD
,
1923 REGNO (operand_reg
[nop
]))
1926 if (lra_dump_file
!= NULL
)
1929 " %d Matching alt: reject+=2\n",
1934 /* If we have to reload this operand and some
1935 previous operand also had to match the same
1936 thing as this operand, we don't know how to do
1938 if (!match_p
|| !curr_alt_win
[m
])
1940 for (i
= 0; i
< nop
; i
++)
1941 if (curr_alt_matches
[i
] == m
)
1949 /* This can be fixed with reloads if the operand
1950 we are supposed to match can be fixed with
1953 this_alternative
= curr_alt
[m
];
1954 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1955 winreg
= this_alternative
!= NO_REGS
;
1961 || general_constant_p (op
)
1962 || spilled_pseudo_p (op
))
1968 cn
= lookup_constraint (p
);
1969 switch (get_constraint_type (cn
))
1972 cl
= reg_class_for_constraint (cn
);
1978 if (CONST_INT_P (op
)
1979 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1985 && satisfies_memory_constraint_p (op
, cn
))
1987 else if (spilled_pseudo_p (op
))
1990 /* If we didn't already win, we can reload constants
1991 via force_const_mem or put the pseudo value into
1992 memory, or make other memory by reloading the
1993 address like for 'o'. */
1994 if (CONST_POOL_OK_P (mode
, op
)
1995 || MEM_P (op
) || REG_P (op
))
2002 /* If we didn't already win, we can reload the address
2003 into a base register. */
2004 if (satisfies_address_constraint_p (op
, cn
))
2006 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2012 if (constraint_satisfied_p (op
, cn
))
2019 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2020 IOR_HARD_REG_SET (this_alternative_set
,
2021 reg_class_contents
[cl
]);
2024 this_costly_alternative
2025 = reg_class_subunion
[this_costly_alternative
][cl
];
2026 IOR_HARD_REG_SET (this_costly_alternative_set
,
2027 reg_class_contents
[cl
]);
2029 if (mode
== BLKmode
)
2034 if (hard_regno
[nop
] >= 0
2035 && in_hard_reg_set_p (this_alternative_set
,
2036 mode
, hard_regno
[nop
]))
2038 else if (hard_regno
[nop
] < 0
2039 && in_class_p (op
, this_alternative
, NULL
))
2044 if (c
!= ' ' && c
!= '\t')
2045 costly_p
= c
== '*';
2047 while ((p
+= len
), c
);
2049 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2050 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2051 /* Record which operands fit this alternative. */
2054 this_alternative_win
= true;
2055 if (operand_reg
[nop
] != NULL_RTX
)
2057 if (hard_regno
[nop
] >= 0)
2059 if (in_hard_reg_set_p (this_costly_alternative_set
,
2060 mode
, hard_regno
[nop
]))
2062 if (lra_dump_file
!= NULL
)
2063 fprintf (lra_dump_file
,
2064 " %d Costly set: reject++\n",
2071 /* Prefer won reg to spilled pseudo under other
2072 equal conditions for possibe inheritance. */
2075 if (lra_dump_file
!= NULL
)
2078 " %d Non pseudo reload: reject++\n",
2082 if (in_class_p (operand_reg
[nop
],
2083 this_costly_alternative
, NULL
))
2085 if (lra_dump_file
!= NULL
)
2088 " %d Non pseudo costly reload:"
2094 /* We simulate the behaviour of old reload here.
2095 Although scratches need hard registers and it
2096 might result in spilling other pseudos, no reload
2097 insns are generated for the scratches. So it
2098 might cost something but probably less than old
2099 reload pass believes. */
2102 if (lra_dump_file
!= NULL
)
2103 fprintf (lra_dump_file
,
2104 " %d Scratch win: reject+=2\n",
2111 this_alternative_match_win
= true;
2114 int const_to_mem
= 0;
2117 /* Never do output reload of stack pointer. It makes
2118 impossible to do elimination when SP is changed in
2120 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2121 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2124 /* If this alternative asks for a specific reg class, see if there
2125 is at least one allocatable register in that class. */
2127 = (this_alternative
== NO_REGS
2128 || (hard_reg_set_subset_p
2129 (reg_class_contents
[this_alternative
],
2130 lra_no_alloc_regs
)));
2132 /* For asms, verify that the class for this alternative is possible
2133 for the mode that is specified. */
2134 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2137 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2138 if (HARD_REGNO_MODE_OK (i
, mode
)
2139 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2142 if (i
== FIRST_PSEUDO_REGISTER
)
2146 /* If this operand accepts a register, and if the
2147 register class has at least one allocatable register,
2148 then this operand can be reloaded. */
2149 if (winreg
&& !no_regs_p
)
2154 if (lra_dump_file
!= NULL
)
2155 fprintf (lra_dump_file
,
2156 " alt=%d: Bad operand -- refuse\n",
2161 /* If not assigned pseudo has a class which a subset of
2162 required reg class, it is a less costly alternative
2163 as the pseudo still can get a hard reg of necessary
2165 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2166 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2167 && ira_class_subset_p
[this_alternative
][cl
])
2169 if (lra_dump_file
!= NULL
)
2172 " %d Super set class reg: reject-=3\n", nop
);
2176 this_alternative_offmemok
= offmemok
;
2177 if (this_costly_alternative
!= NO_REGS
)
2179 if (lra_dump_file
!= NULL
)
2180 fprintf (lra_dump_file
,
2181 " %d Costly loser: reject++\n", nop
);
2184 /* If the operand is dying, has a matching constraint,
2185 and satisfies constraints of the matched operand
2186 which failed to satisfy the own constraints, most probably
2187 the reload for this operand will be gone. */
2188 if (this_alternative_matches
>= 0
2189 && !curr_alt_win
[this_alternative_matches
]
2191 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2192 && (hard_regno
[nop
] >= 0
2193 ? in_hard_reg_set_p (this_alternative_set
,
2194 mode
, hard_regno
[nop
])
2195 : in_class_p (op
, this_alternative
, NULL
)))
2197 if (lra_dump_file
!= NULL
)
2200 " %d Dying matched operand reload: reject++\n",
2206 /* Strict_low_part requires to reload the register
2207 not the sub-register. In this case we should
2208 check that a final reload hard reg can hold the
2210 if (curr_static_id
->operand
[nop
].strict_low
2212 && hard_regno
[nop
] < 0
2213 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2214 && ira_class_hard_regs_num
[this_alternative
] > 0
2215 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2216 [this_alternative
][0],
2218 (*curr_id
->operand_loc
[nop
])))
2220 if (lra_dump_file
!= NULL
)
2223 " alt=%d: Strict low subreg reload -- refuse\n",
2229 if (operand_reg
[nop
] != NULL_RTX
2230 /* Output operands and matched input operands are
2231 not inherited. The following conditions do not
2232 exactly describe the previous statement but they
2233 are pretty close. */
2234 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2235 && (this_alternative_matches
< 0
2236 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2238 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2242 /* The value of reload_sum has sense only if we
2243 process insns in their order. It happens only on
2244 the first constraints sub-pass when we do most of
2246 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2247 reload_sum
+= last_reload
- bb_reload_num
;
2249 /* If this is a constant that is reloaded into the
2250 desired class by copying it to memory first, count
2251 that as another reload. This is consistent with
2252 other code and is required to avoid choosing another
2253 alternative when the constant is moved into memory.
2254 Note that the test here is precisely the same as in
2255 the code below that calls force_const_mem. */
2256 if (CONST_POOL_OK_P (mode
, op
)
2257 && ((targetm
.preferred_reload_class
2258 (op
, this_alternative
) == NO_REGS
)
2259 || no_input_reloads_p
))
2266 /* Alternative loses if it requires a type of reload not
2267 permitted for this insn. We can always reload
2268 objects with a REG_UNUSED note. */
2269 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2270 && no_output_reloads_p
2271 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2272 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2273 && no_input_reloads_p
&& ! const_to_mem
)
2274 || (this_alternative_matches
>= 0
2275 && (no_input_reloads_p
2276 || (no_output_reloads_p
2277 && (curr_static_id
->operand
2278 [this_alternative_matches
].type
!= OP_IN
)
2279 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2280 no_subreg_reg_operand
2281 [this_alternative_matches
])))))
2283 if (lra_dump_file
!= NULL
)
2286 " alt=%d: No input/otput reload -- refuse\n",
2291 /* Alternative loses if it required class pseudo can not
2292 hold value of required mode. Such insns can be
2293 described by insn definitions with mode iterators. */
2294 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2295 && ! hard_reg_set_empty_p (this_alternative_set
)
2296 /* It is common practice for constraints to use a
2297 class which does not have actually enough regs to
2298 hold the value (e.g. x86 AREG for mode requiring
2299 more one general reg). Therefore we have 2
2300 conditions to check that the reload pseudo can
2301 not hold the mode value. */
2302 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2303 [this_alternative
][0],
2304 GET_MODE (*curr_id
->operand_loc
[nop
])))
2308 COPY_HARD_REG_SET (temp
, this_alternative_set
);
2309 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
2310 /* The above condition is not enough as the first
2311 reg in ira_class_hard_regs can be not aligned for
2312 multi-words mode values. */
2313 if (hard_reg_set_subset_p (temp
,
2314 ira_prohibited_class_mode_regs
2316 [GET_MODE (*curr_id
->operand_loc
[nop
])]))
2318 if (lra_dump_file
!= NULL
)
2321 " alt=%d: reload pseudo for op %d "
2322 " can not hold the mode value -- refuse\n",
2328 /* Check strong discouragement of reload of non-constant
2329 into class THIS_ALTERNATIVE. */
2330 if (! CONSTANT_P (op
) && ! no_regs_p
2331 && (targetm
.preferred_reload_class
2332 (op
, this_alternative
) == NO_REGS
2333 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2334 && (targetm
.preferred_output_reload_class
2335 (op
, this_alternative
) == NO_REGS
))))
2337 if (lra_dump_file
!= NULL
)
2338 fprintf (lra_dump_file
,
2339 " %d Non-prefered reload: reject+=%d\n",
2340 nop
, LRA_MAX_REJECT
);
2341 reject
+= LRA_MAX_REJECT
;
2344 if (! (MEM_P (op
) && offmemok
)
2345 && ! (const_to_mem
&& constmemok
))
2347 /* We prefer to reload pseudos over reloading other
2348 things, since such reloads may be able to be
2349 eliminated later. So bump REJECT in other cases.
2350 Don't do this in the case where we are forcing a
2351 constant into memory and it will then win since
2352 we don't want to have a different alternative
2354 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2356 if (lra_dump_file
!= NULL
)
2359 " %d Non-pseudo reload: reject+=2\n",
2366 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2368 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2370 if (lra_dump_file
!= NULL
)
2373 " %d Small class reload: reject+=%d\n",
2374 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2375 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2379 /* We are trying to spill pseudo into memory. It is
2380 usually more costly than moving to a hard register
2381 although it might takes the same number of
2383 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2385 if (lra_dump_file
!= NULL
)
2388 " %d Spill pseudo into memory: reject+=3\n",
2391 if (VECTOR_MODE_P (mode
))
2393 /* Spilling vectors into memory is usually more
2394 costly as they contain big values. */
2395 if (lra_dump_file
!= NULL
)
2398 " %d Spill vector pseudo: reject+=2\n",
2404 #ifdef SECONDARY_MEMORY_NEEDED
2405 /* If reload requires moving value through secondary
2406 memory, it will need one more insn at least. */
2407 if (this_alternative
!= NO_REGS
2408 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2409 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2410 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2412 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2413 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2417 /* Input reloads can be inherited more often than output
2418 reloads can be removed, so penalize output
2420 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2422 if (lra_dump_file
!= NULL
)
2425 " %d Non input pseudo reload: reject++\n",
2431 if (early_clobber_p
&& ! scratch_p
)
2433 if (lra_dump_file
!= NULL
)
2434 fprintf (lra_dump_file
,
2435 " %d Early clobber: reject++\n", nop
);
2438 /* ??? We check early clobbers after processing all operands
2439 (see loop below) and there we update the costs more.
2440 Should we update the cost (may be approximately) here
2441 because of early clobber register reloads or it is a rare
2442 or non-important thing to be worth to do it. */
2443 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2444 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2446 if (lra_dump_file
!= NULL
)
2447 fprintf (lra_dump_file
,
2448 " alt=%d,overall=%d,losers=%d -- refuse\n",
2449 nalt
, overall
, losers
);
2453 curr_alt
[nop
] = this_alternative
;
2454 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2455 curr_alt_win
[nop
] = this_alternative_win
;
2456 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2457 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2458 curr_alt_matches
[nop
] = this_alternative_matches
;
2460 if (this_alternative_matches
>= 0
2461 && !did_match
&& !this_alternative_win
)
2462 curr_alt_win
[this_alternative_matches
] = false;
2464 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2465 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2467 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2468 /* Prevent processing non-move insns. */
2469 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2470 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2471 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2472 && REG_P (no_subreg_reg_operand
[0])
2473 && REG_P (no_subreg_reg_operand
[1])
2474 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2475 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2476 || (! curr_alt_win
[0] && curr_alt_win
[1]
2477 && REG_P (no_subreg_reg_operand
[1])
2478 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2479 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2480 && REG_P (no_subreg_reg_operand
[0])
2481 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2482 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2483 no_subreg_reg_operand
[1])
2484 || (targetm
.preferred_reload_class
2485 (no_subreg_reg_operand
[1],
2486 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2487 /* If it is a result of recent elimination in move
2488 insn we can transform it into an add still by
2489 using this alternative. */
2490 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2492 /* We have a move insn and a new reload insn will be similar
2493 to the current insn. We should avoid such situation as it
2494 results in LRA cycling. */
2495 overall
+= LRA_MAX_REJECT
;
2498 curr_alt_dont_inherit_ops_num
= 0;
2499 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2501 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2502 HARD_REG_SET temp_set
;
2504 i
= early_clobbered_nops
[nop
];
2505 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2506 || hard_regno
[i
] < 0)
2508 lra_assert (operand_reg
[i
] != NULL_RTX
);
2509 clobbered_hard_regno
= hard_regno
[i
];
2510 CLEAR_HARD_REG_SET (temp_set
);
2511 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2512 first_conflict_j
= last_conflict_j
= -1;
2513 for (j
= 0; j
< n_operands
; j
++)
2515 /* We don't want process insides of match_operator and
2516 match_parallel because otherwise we would process
2517 their operands once again generating a wrong
2519 || curr_static_id
->operand
[j
].is_operator
)
2521 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2522 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2524 /* If we don't reload j-th operand, check conflicts. */
2525 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2526 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2528 if (first_conflict_j
< 0)
2529 first_conflict_j
= j
;
2530 last_conflict_j
= j
;
2532 if (last_conflict_j
< 0)
2534 /* If earlyclobber operand conflicts with another
2535 non-matching operand which is actually the same register
2536 as the earlyclobber operand, it is better to reload the
2537 another operand as an operand matching the earlyclobber
2538 operand can be also the same. */
2539 if (first_conflict_j
== last_conflict_j
2540 && operand_reg
[last_conflict_j
]
2541 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2542 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2544 curr_alt_win
[last_conflict_j
] = false;
2545 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2548 /* Early clobber was already reflected in REJECT. */
2549 lra_assert (reject
> 0);
2550 if (lra_dump_file
!= NULL
)
2553 " %d Conflict early clobber reload: reject--\n",
2556 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2560 /* We need to reload early clobbered register and the
2561 matched registers. */
2562 for (j
= 0; j
< n_operands
; j
++)
2563 if (curr_alt_matches
[j
] == i
)
2565 curr_alt_match_win
[j
] = false;
2567 overall
+= LRA_LOSER_COST_FACTOR
;
2569 if (! curr_alt_match_win
[i
])
2570 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2573 /* Remember pseudos used for match reloads are never
2575 lra_assert (curr_alt_matches
[i
] >= 0);
2576 curr_alt_win
[curr_alt_matches
[i
]] = false;
2578 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2580 /* Early clobber was already reflected in REJECT. */
2581 lra_assert (reject
> 0);
2582 if (lra_dump_file
!= NULL
)
2585 " %d Matched conflict early clobber reloads:"
2589 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2592 if (lra_dump_file
!= NULL
)
2593 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2594 nalt
, overall
, losers
, reload_nregs
);
2596 /* If this alternative can be made to work by reloading, and it
2597 needs less reloading than the others checked so far, record
2598 it as the chosen goal for reloading. */
2599 if ((best_losers
!= 0 && losers
== 0)
2600 || (((best_losers
== 0 && losers
== 0)
2601 || (best_losers
!= 0 && losers
!= 0))
2602 && (best_overall
> overall
2603 || (best_overall
== overall
2604 /* If the cost of the reloads is the same,
2605 prefer alternative which requires minimal
2606 number of reload regs. */
2607 && (reload_nregs
< best_reload_nregs
2608 || (reload_nregs
== best_reload_nregs
2609 && (best_reload_sum
< reload_sum
2610 || (best_reload_sum
== reload_sum
2611 && nalt
< goal_alt_number
))))))))
2613 for (nop
= 0; nop
< n_operands
; nop
++)
2615 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2616 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2617 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2618 goal_alt
[nop
] = curr_alt
[nop
];
2619 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2621 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2622 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2623 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2624 goal_alt_swapped
= curr_swapped
;
2625 best_overall
= overall
;
2626 best_losers
= losers
;
2627 best_reload_nregs
= reload_nregs
;
2628 best_reload_sum
= reload_sum
;
2629 goal_alt_number
= nalt
;
2632 /* Everything is satisfied. Do not process alternatives
2641 /* Make reload base reg from address AD. */
2643 base_to_reg (struct address_info
*ad
)
2647 rtx new_inner
= NULL_RTX
;
2648 rtx new_reg
= NULL_RTX
;
2650 rtx_insn
*last_insn
= get_last_insn();
2652 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2653 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2654 get_index_code (ad
));
2655 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2657 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2658 ad
->disp_term
== NULL
2659 ? gen_int_mode (0, ad
->mode
)
2661 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2663 insn
= emit_insn (gen_rtx_SET (ad
->mode
, new_reg
, *ad
->base_term
));
2664 code
= recog_memoized (insn
);
2667 delete_insns_since (last_insn
);
2674 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2676 base_plus_disp_to_reg (struct address_info
*ad
)
2681 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2682 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2683 get_index_code (ad
));
2684 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2686 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2690 /* Make reload of index part of address AD. Return the new
2693 index_part_to_reg (struct address_info
*ad
)
2697 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2698 INDEX_REG_CLASS
, "index term");
2699 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2700 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2704 /* Return true if we can add a displacement to address AD, even if that
2705 makes the address invalid. The fix-up code requires any new address
2706 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2708 can_add_disp_p (struct address_info
*ad
)
2710 return (!ad
->autoinc_p
2711 && ad
->segment
== NULL
2712 && ad
->base
== ad
->base_term
2713 && ad
->disp
== ad
->disp_term
);
2716 /* Make equiv substitution in address AD. Return true if a substitution
2719 equiv_address_substitution (struct address_info
*ad
)
2721 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2722 HOST_WIDE_INT disp
, scale
;
2725 base_term
= strip_subreg (ad
->base_term
);
2726 if (base_term
== NULL
)
2727 base_reg
= new_base_reg
= NULL_RTX
;
2730 base_reg
= *base_term
;
2731 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2733 index_term
= strip_subreg (ad
->index_term
);
2734 if (index_term
== NULL
)
2735 index_reg
= new_index_reg
= NULL_RTX
;
2738 index_reg
= *index_term
;
2739 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2741 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2745 if (lra_dump_file
!= NULL
)
2747 fprintf (lra_dump_file
, "Changing address in insn %d ",
2748 INSN_UID (curr_insn
));
2749 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2751 if (base_reg
!= new_base_reg
)
2753 if (REG_P (new_base_reg
))
2755 *base_term
= new_base_reg
;
2758 else if (GET_CODE (new_base_reg
) == PLUS
2759 && REG_P (XEXP (new_base_reg
, 0))
2760 && CONST_INT_P (XEXP (new_base_reg
, 1))
2761 && can_add_disp_p (ad
))
2763 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2764 *base_term
= XEXP (new_base_reg
, 0);
2767 if (ad
->base_term2
!= NULL
)
2768 *ad
->base_term2
= *ad
->base_term
;
2770 if (index_reg
!= new_index_reg
)
2772 if (REG_P (new_index_reg
))
2774 *index_term
= new_index_reg
;
2777 else if (GET_CODE (new_index_reg
) == PLUS
2778 && REG_P (XEXP (new_index_reg
, 0))
2779 && CONST_INT_P (XEXP (new_index_reg
, 1))
2780 && can_add_disp_p (ad
)
2781 && (scale
= get_index_scale (ad
)))
2783 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2784 *index_term
= XEXP (new_index_reg
, 0);
2790 if (ad
->disp
!= NULL
)
2791 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2794 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2795 update_address (ad
);
2799 if (lra_dump_file
!= NULL
)
2802 fprintf (lra_dump_file
, " -- no change\n");
2805 fprintf (lra_dump_file
, " on equiv ");
2806 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2807 fprintf (lra_dump_file
, "\n");
2813 /* Major function to make reloads for an address in operand NOP or
2814 check its correctness (If CHECK_ONLY_P is true). The supported
2817 1) an address that existed before LRA started, at which point it
2818 must have been valid. These addresses are subject to elimination
2819 and may have become invalid due to the elimination offset being out
2822 2) an address created by forcing a constant to memory
2823 (force_const_to_mem). The initial form of these addresses might
2824 not be valid, and it is this function's job to make them valid.
2826 3) a frame address formed from a register and a (possibly zero)
2827 constant offset. As above, these addresses might not be valid and
2828 this function must make them so.
2830 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2831 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2832 address. Return true for any RTL change.
2834 The function is a helper function which does not produce all
2835 transformations (when CHECK_ONLY_P is false) which can be
2836 necessary. It does just basic steps. To do all necessary
2837 transformations use function process_address. */
2839 process_address_1 (int nop
, bool check_only_p
,
2840 rtx_insn
**before
, rtx_insn
**after
)
2842 struct address_info ad
;
2844 rtx op
= *curr_id
->operand_loc
[nop
];
2845 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2846 enum constraint_num cn
= lookup_constraint (constraint
);
2847 bool change_p
= false;
2849 if (insn_extra_address_constraint (cn
))
2850 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2851 else if (MEM_P (op
))
2852 decompose_mem_address (&ad
, op
);
2853 else if (GET_CODE (op
) == SUBREG
2854 && MEM_P (SUBREG_REG (op
)))
2855 decompose_mem_address (&ad
, SUBREG_REG (op
));
2858 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
2859 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
2860 when INDEX_REG_CLASS is a single register class. */
2861 if (ad
.base_term
!= NULL
2862 && ad
.index_term
!= NULL
2863 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
2864 && REG_P (*ad
.base_term
)
2865 && REG_P (*ad
.index_term
)
2866 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
2867 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
2869 std::swap (ad
.base
, ad
.index
);
2870 std::swap (ad
.base_term
, ad
.index_term
);
2873 change_p
= equiv_address_substitution (&ad
);
2874 if (ad
.base_term
!= NULL
2875 && (process_addr_reg
2876 (ad
.base_term
, check_only_p
, before
,
2878 && !(REG_P (*ad
.base_term
)
2879 && find_regno_note (curr_insn
, REG_DEAD
,
2880 REGNO (*ad
.base_term
)) != NULL_RTX
)
2882 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2883 get_index_code (&ad
)))))
2886 if (ad
.base_term2
!= NULL
)
2887 *ad
.base_term2
= *ad
.base_term
;
2889 if (ad
.index_term
!= NULL
2890 && process_addr_reg (ad
.index_term
, check_only_p
,
2891 before
, NULL
, INDEX_REG_CLASS
))
2894 /* Target hooks sometimes don't treat extra-constraint addresses as
2895 legitimate address_operands, so handle them specially. */
2896 if (insn_extra_address_constraint (cn
)
2897 && satisfies_address_constraint_p (&ad
, cn
))
2903 /* There are three cases where the shape of *AD.INNER may now be invalid:
2905 1) the original address was valid, but either elimination or
2906 equiv_address_substitution was applied and that made
2907 the address invalid.
2909 2) the address is an invalid symbolic address created by
2912 3) the address is a frame address with an invalid offset.
2914 4) the address is a frame address with an invalid base.
2916 All these cases involve a non-autoinc address, so there is no
2917 point revalidating other types. */
2918 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2921 /* Any index existed before LRA started, so we can assume that the
2922 presence and shape of the index is valid. */
2923 push_to_sequence (*before
);
2924 lra_assert (ad
.disp
== ad
.disp_term
);
2925 if (ad
.base
== NULL
)
2927 if (ad
.index
== NULL
)
2930 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2932 rtx addr
= *ad
.inner
;
2934 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2938 rtx_insn
*last
= get_last_insn ();
2940 /* addr => lo_sum (new_base, addr), case (2) above. */
2941 insn
= emit_insn (gen_rtx_SET
2943 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2944 code
= recog_memoized (insn
);
2947 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2948 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2950 /* Try to put lo_sum into register. */
2951 insn
= emit_insn (gen_rtx_SET
2953 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2954 code
= recog_memoized (insn
);
2957 *ad
.inner
= new_reg
;
2958 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2968 delete_insns_since (last
);
2973 /* addr => new_base, case (2) above. */
2974 lra_emit_move (new_reg
, addr
);
2975 *ad
.inner
= new_reg
;
2980 /* index * scale + disp => new base + index * scale,
2982 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2983 GET_CODE (*ad
.index
));
2985 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2986 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2987 lra_emit_move (new_reg
, *ad
.disp
);
2988 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2989 new_reg
, *ad
.index
);
2992 else if (ad
.index
== NULL
)
2997 rtx_insn
*insns
, *last_insn
;
2998 /* Try to reload base into register only if the base is invalid
2999 for the address but with valid offset, case (4) above. */
3001 new_reg
= base_to_reg (&ad
);
3003 /* base + disp => new base, cases (1) and (3) above. */
3004 /* Another option would be to reload the displacement into an
3005 index register. However, postreload has code to optimize
3006 address reloads that have the same base and different
3007 displacements, so reloading into an index register would
3008 not necessarily be a win. */
3009 if (new_reg
== NULL_RTX
)
3010 new_reg
= base_plus_disp_to_reg (&ad
);
3011 insns
= get_insns ();
3012 last_insn
= get_last_insn ();
3013 /* If we generated at least two insns, try last insn source as
3014 an address. If we succeed, we generate one less insn. */
3015 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3016 && GET_CODE (SET_SRC (set
)) == PLUS
3017 && REG_P (XEXP (SET_SRC (set
), 0))
3018 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3020 *ad
.inner
= SET_SRC (set
);
3021 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3023 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3024 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3025 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3026 get_index_code (&ad
));
3027 regno
= REGNO (*ad
.base_term
);
3028 if (regno
>= FIRST_PSEUDO_REGISTER
3029 && cl
!= lra_get_allocno_class (regno
))
3030 lra_change_class (regno
, cl
, " Change to", true);
3031 new_reg
= SET_SRC (set
);
3032 delete_insns_since (PREV_INSN (last_insn
));
3035 /* Try if target can split displacement into legitimite new disp
3036 and offset. If it's the case, we replace the last insn with
3037 insns for base + offset => new_reg and set new_reg + new disp
3039 last_insn
= get_last_insn ();
3040 if ((set
= single_set (last_insn
)) != NULL_RTX
3041 && GET_CODE (SET_SRC (set
)) == PLUS
3042 && REG_P (XEXP (SET_SRC (set
), 0))
3043 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3044 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3046 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3047 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3050 rtx_insn
*new_insns
;
3052 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3053 new_insns
= get_insns ();
3055 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3056 delete_insns_since (PREV_INSN (last_insn
));
3057 add_insn (new_insns
);
3058 insns
= get_insns ();
3063 *ad
.inner
= new_reg
;
3065 else if (ad
.disp_term
!= NULL
)
3067 /* base + scale * index + disp => new base + scale * index,
3069 new_reg
= base_plus_disp_to_reg (&ad
);
3070 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3071 new_reg
, *ad
.index
);
3073 else if (get_index_scale (&ad
) == 1)
3075 /* The last transformation to one reg will be made in
3076 curr_insn_transform function. */
3082 /* base + scale * index => base + new_reg,
3084 Index part of address may become invalid. For example, we
3085 changed pseudo on the equivalent memory and a subreg of the
3086 pseudo onto the memory of different mode for which the scale is
3088 new_reg
= index_part_to_reg (&ad
);
3089 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3090 *ad
.base_term
, new_reg
);
3092 *before
= get_insns ();
3097 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3098 Use process_address_1 as a helper function. Return true for any
3101 If CHECK_ONLY_P is true, just check address correctness. Return
3102 false if the address correct. */
3104 process_address (int nop
, bool check_only_p
,
3105 rtx_insn
**before
, rtx_insn
**after
)
3109 while (process_address_1 (nop
, check_only_p
, before
, after
))
3118 /* Emit insns to reload VALUE into a new register. VALUE is an
3119 auto-increment or auto-decrement RTX whose operand is a register or
3120 memory location; so reloading involves incrementing that location.
3121 IN is either identical to VALUE, or some cheaper place to reload
3122 value being incremented/decremented from.
3124 INC_AMOUNT is the number to increment or decrement by (always
3125 positive and ignored for POST_MODIFY/PRE_MODIFY).
3127 Return pseudo containing the result. */
3129 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3131 /* REG or MEM to be copied and incremented. */
3132 rtx incloc
= XEXP (value
, 0);
3133 /* Nonzero if increment after copying. */
3134 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3135 || GET_CODE (value
) == POST_MODIFY
);
3140 rtx real_in
= in
== value
? incloc
: in
;
3144 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3146 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3147 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3148 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3149 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3150 inc
= XEXP (XEXP (value
, 1), 1);
3154 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3155 inc_amount
= -inc_amount
;
3157 inc
= GEN_INT (inc_amount
);
3160 if (! post
&& REG_P (incloc
))
3163 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3166 if (real_in
!= result
)
3168 /* First copy the location to the result register. */
3169 lra_assert (REG_P (result
));
3170 emit_insn (gen_move_insn (result
, real_in
));
3173 /* We suppose that there are insns to add/sub with the constant
3174 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3175 old reload worked with this assumption. If the assumption
3176 becomes wrong, we should use approach in function
3177 base_plus_disp_to_reg. */
3180 /* See if we can directly increment INCLOC. */
3181 last
= get_last_insn ();
3182 add_insn
= emit_insn (plus_p
3183 ? gen_add2_insn (incloc
, inc
)
3184 : gen_sub2_insn (incloc
, inc
));
3186 code
= recog_memoized (add_insn
);
3189 if (! post
&& result
!= incloc
)
3190 emit_insn (gen_move_insn (result
, incloc
));
3193 delete_insns_since (last
);
3196 /* If couldn't do the increment directly, must increment in RESULT.
3197 The way we do this depends on whether this is pre- or
3198 post-increment. For pre-increment, copy INCLOC to the reload
3199 register, increment it there, then save back. */
3202 if (real_in
!= result
)
3203 emit_insn (gen_move_insn (result
, real_in
));
3205 emit_insn (gen_add2_insn (result
, inc
));
3207 emit_insn (gen_sub2_insn (result
, inc
));
3208 if (result
!= incloc
)
3209 emit_insn (gen_move_insn (incloc
, result
));
3215 Because this might be a jump insn or a compare, and because
3216 RESULT may not be available after the insn in an input
3217 reload, we must do the incrementing before the insn being
3220 We have already copied IN to RESULT. Increment the copy in
3221 RESULT, save that back, then decrement RESULT so it has
3222 the original value. */
3224 emit_insn (gen_add2_insn (result
, inc
));
3226 emit_insn (gen_sub2_insn (result
, inc
));
3227 emit_insn (gen_move_insn (incloc
, result
));
3228 /* Restore non-modified value for the result. We prefer this
3229 way because it does not require an additional hard
3233 if (CONST_INT_P (inc
))
3234 emit_insn (gen_add2_insn (result
,
3235 gen_int_mode (-INTVAL (inc
),
3236 GET_MODE (result
))));
3238 emit_insn (gen_sub2_insn (result
, inc
));
3241 emit_insn (gen_add2_insn (result
, inc
));
3246 /* Return true if the current move insn does not need processing as we
3247 already know that it satisfies its constraints. */
3249 simple_move_p (void)
3252 enum reg_class dclass
, sclass
;
3254 lra_assert (curr_insn_set
!= NULL_RTX
);
3255 dest
= SET_DEST (curr_insn_set
);
3256 src
= SET_SRC (curr_insn_set
);
3257 return ((dclass
= get_op_class (dest
)) != NO_REGS
3258 && (sclass
= get_op_class (src
)) != NO_REGS
3259 /* The backend guarantees that register moves of cost 2
3260 never need reloads. */
3261 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3264 /* Swap operands NOP and NOP + 1. */
3266 swap_operands (int nop
)
3268 machine_mode mode
= curr_operand_mode
[nop
];
3269 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3270 curr_operand_mode
[nop
+ 1] = mode
;
3271 rtx x
= *curr_id
->operand_loc
[nop
];
3272 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3273 *curr_id
->operand_loc
[nop
+ 1] = x
;
3274 /* Swap the duplicates too. */
3275 lra_update_dup (curr_id
, nop
);
3276 lra_update_dup (curr_id
, nop
+ 1);
3279 /* Main entry point of the constraint code: search the body of the
3280 current insn to choose the best alternative. It is mimicking insn
3281 alternative cost calculation model of former reload pass. That is
3282 because machine descriptions were written to use this model. This
3283 model can be changed in future. Make commutative operand exchange
3286 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3287 constraints. Return true if any change happened during function
3290 If CHECK_ONLY_P is true then don't do any transformation. Just
3291 check that the insn satisfies all constraints. If the insn does
3292 not satisfy any constraint, return true. */
3294 curr_insn_transform (bool check_only_p
)
3300 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3301 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3302 rtx_insn
*before
, *after
;
3304 /* Flag that the insn has been changed through a transformation. */
3307 #ifdef SECONDARY_MEMORY_NEEDED
3310 int max_regno_before
;
3311 int reused_alternative_num
;
3313 curr_insn_set
= single_set (curr_insn
);
3314 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3317 no_input_reloads_p
= no_output_reloads_p
= false;
3318 goal_alt_number
= -1;
3319 change_p
= sec_mem_p
= false;
3320 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3321 reloads; neither are insns that SET cc0. Insns that use CC0 are
3322 not allowed to have any input reloads. */
3323 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3324 no_output_reloads_p
= true;
3327 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3328 no_input_reloads_p
= true;
3329 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3330 no_output_reloads_p
= true;
3333 n_operands
= curr_static_id
->n_operands
;
3334 n_alternatives
= curr_static_id
->n_alternatives
;
3336 /* Just return "no reloads" if insn has no operands with
3338 if (n_operands
== 0 || n_alternatives
== 0)
3341 max_regno_before
= max_reg_num ();
3343 for (i
= 0; i
< n_operands
; i
++)
3345 goal_alt_matched
[i
][0] = -1;
3346 goal_alt_matches
[i
] = -1;
3349 commutative
= curr_static_id
->commutative
;
3351 /* Now see what we need for pseudos that didn't get hard regs or got
3352 the wrong kind of hard reg. For this, we must consider all the
3353 operands together against the register constraints. */
3355 best_losers
= best_overall
= INT_MAX
;
3356 best_reload_sum
= 0;
3358 curr_swapped
= false;
3359 goal_alt_swapped
= false;
3362 /* Make equivalence substitution and memory subreg elimination
3363 before address processing because an address legitimacy can
3364 depend on memory mode. */
3365 for (i
= 0; i
< n_operands
; i
++)
3367 rtx op
= *curr_id
->operand_loc
[i
];
3368 rtx subst
, old
= op
;
3369 bool op_change_p
= false;
3371 if (GET_CODE (old
) == SUBREG
)
3372 old
= SUBREG_REG (old
);
3373 subst
= get_equiv_with_elimination (old
, curr_insn
);
3376 subst
= copy_rtx (subst
);
3377 lra_assert (REG_P (old
));
3378 if (GET_CODE (op
) == SUBREG
)
3379 SUBREG_REG (op
) = subst
;
3381 *curr_id
->operand_loc
[i
] = subst
;
3382 if (lra_dump_file
!= NULL
)
3384 fprintf (lra_dump_file
,
3385 "Changing pseudo %d in operand %i of insn %u on equiv ",
3386 REGNO (old
), i
, INSN_UID (curr_insn
));
3387 dump_value_slim (lra_dump_file
, subst
, 1);
3388 fprintf (lra_dump_file
, "\n");
3390 op_change_p
= change_p
= true;
3392 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3395 lra_update_dup (curr_id
, i
);
3399 /* Reload address registers and displacements. We do it before
3400 finding an alternative because of memory constraints. */
3401 before
= after
= NULL
;
3402 for (i
= 0; i
< n_operands
; i
++)
3403 if (! curr_static_id
->operand
[i
].is_operator
3404 && process_address (i
, check_only_p
, &before
, &after
))
3409 lra_update_dup (curr_id
, i
);
3413 /* If we've changed the instruction then any alternative that
3414 we chose previously may no longer be valid. */
3415 lra_set_used_insn_alternative (curr_insn
, -1);
3417 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3418 && check_and_process_move (&change_p
, &sec_mem_p
))
3423 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3424 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3425 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3426 reused_alternative_num
, INSN_UID (curr_insn
));
3428 if (process_alt_operands (reused_alternative_num
))
3432 return ! alt_p
|| best_losers
!= 0;
3434 /* If insn is commutative (it's safe to exchange a certain pair of
3435 operands) then we need to try each alternative twice, the second
3436 time matching those two operands as if we had exchanged them. To
3437 do this, really exchange them in operands.
3439 If we have just tried the alternatives the second time, return
3440 operands to normal and drop through. */
3442 if (reused_alternative_num
< 0 && commutative
>= 0)
3444 curr_swapped
= !curr_swapped
;
3447 swap_operands (commutative
);
3451 swap_operands (commutative
);
3454 if (! alt_p
&& ! sec_mem_p
)
3456 /* No alternative works with reloads?? */
3457 if (INSN_CODE (curr_insn
) >= 0)
3458 fatal_insn ("unable to generate reloads for:", curr_insn
);
3459 error_for_asm (curr_insn
,
3460 "inconsistent operand constraints in an %<asm%>");
3461 /* Avoid further trouble with this insn. */
3462 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3463 lra_invalidate_insn_data (curr_insn
);
3467 /* If the best alternative is with operands 1 and 2 swapped, swap
3468 them. Update the operand numbers of any reloads already
3471 if (goal_alt_swapped
)
3473 if (lra_dump_file
!= NULL
)
3474 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3475 INSN_UID (curr_insn
));
3477 /* Swap the duplicates too. */
3478 swap_operands (commutative
);
3482 #ifdef SECONDARY_MEMORY_NEEDED
3483 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3484 too conservatively. So we use the secondary memory only if there
3485 is no any alternative without reloads. */
3486 use_sec_mem_p
= false;
3488 use_sec_mem_p
= true;
3491 for (i
= 0; i
< n_operands
; i
++)
3492 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3494 use_sec_mem_p
= i
< n_operands
;
3499 rtx new_reg
, src
, dest
, rld
;
3500 machine_mode sec_mode
, rld_mode
;
3502 lra_assert (sec_mem_p
);
3503 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3504 && curr_static_id
->operand
[1].type
== OP_IN
);
3505 dest
= *curr_id
->operand_loc
[0];
3506 src
= *curr_id
->operand_loc
[1];
3507 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3509 rld_mode
= GET_MODE (rld
);
3510 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3511 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3513 sec_mode
= rld_mode
;
3515 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3516 NO_REGS
, "secondary");
3517 /* If the mode is changed, it should be wider. */
3518 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3519 if (sec_mode
!= rld_mode
)
3521 /* If the target says specifically to use another mode for
3522 secondary memory moves we can not reuse the original
3524 after
= emit_spill_move (false, new_reg
, dest
);
3525 lra_process_new_insns (curr_insn
, NULL
, after
,
3526 "Inserting the sec. move");
3527 /* We may have non null BEFORE here (e.g. after address
3529 push_to_sequence (before
);
3530 before
= emit_spill_move (true, new_reg
, src
);
3532 before
= get_insns ();
3534 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3535 lra_set_insn_deleted (curr_insn
);
3537 else if (dest
== rld
)
3539 *curr_id
->operand_loc
[0] = new_reg
;
3540 after
= emit_spill_move (false, new_reg
, dest
);
3541 lra_process_new_insns (curr_insn
, NULL
, after
,
3542 "Inserting the sec. move");
3546 *curr_id
->operand_loc
[1] = new_reg
;
3547 /* See comments above. */
3548 push_to_sequence (before
);
3549 before
= emit_spill_move (true, new_reg
, src
);
3551 before
= get_insns ();
3553 lra_process_new_insns (curr_insn
, before
, NULL
,
3554 "Inserting the sec. move");
3556 lra_update_insn_regno_info (curr_insn
);
3561 lra_assert (goal_alt_number
>= 0);
3562 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3564 if (lra_dump_file
!= NULL
)
3568 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3569 goal_alt_number
, INSN_UID (curr_insn
));
3570 for (i
= 0; i
< n_operands
; i
++)
3572 p
= (curr_static_id
->operand_alternative
3573 [goal_alt_number
* n_operands
+ i
].constraint
);
3576 fprintf (lra_dump_file
, " (%d) ", i
);
3577 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3578 fputc (*p
, lra_dump_file
);
3580 if (INSN_CODE (curr_insn
) >= 0
3581 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3582 fprintf (lra_dump_file
, " {%s}", p
);
3583 if (curr_id
->sp_offset
!= 0)
3584 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3585 curr_id
->sp_offset
);
3586 fprintf (lra_dump_file
, "\n");
3589 /* Right now, for any pair of operands I and J that are required to
3590 match, with J < I, goal_alt_matches[I] is J. Add I to
3591 goal_alt_matched[J]. */
3593 for (i
= 0; i
< n_operands
; i
++)
3594 if ((j
= goal_alt_matches
[i
]) >= 0)
3596 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3598 /* We allow matching one output operand and several input
3601 || (curr_static_id
->operand
[j
].type
== OP_OUT
3602 && curr_static_id
->operand
[i
].type
== OP_IN
3603 && (curr_static_id
->operand
3604 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3605 goal_alt_matched
[j
][k
] = i
;
3606 goal_alt_matched
[j
][k
+ 1] = -1;
3609 for (i
= 0; i
< n_operands
; i
++)
3610 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3612 /* Any constants that aren't allowed and can't be reloaded into
3613 registers are here changed into memory references. */
3614 for (i
= 0; i
< n_operands
; i
++)
3615 if (goal_alt_win
[i
])
3618 enum reg_class new_class
;
3619 rtx reg
= *curr_id
->operand_loc
[i
];
3621 if (GET_CODE (reg
) == SUBREG
)
3622 reg
= SUBREG_REG (reg
);
3624 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3626 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3628 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3631 lra_change_class (regno
, new_class
, " Change to", true);
3637 const char *constraint
;
3639 rtx op
= *curr_id
->operand_loc
[i
];
3640 rtx subreg
= NULL_RTX
;
3641 machine_mode mode
= curr_operand_mode
[i
];
3643 if (GET_CODE (op
) == SUBREG
)
3646 op
= SUBREG_REG (op
);
3647 mode
= GET_MODE (op
);
3650 if (CONST_POOL_OK_P (mode
, op
)
3651 && ((targetm
.preferred_reload_class
3652 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3653 || no_input_reloads_p
))
3655 rtx tem
= force_const_mem (mode
, op
);
3658 if (subreg
!= NULL_RTX
)
3659 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3661 *curr_id
->operand_loc
[i
] = tem
;
3662 lra_update_dup (curr_id
, i
);
3663 process_address (i
, false, &before
, &after
);
3665 /* If the alternative accepts constant pool refs directly
3666 there will be no reload needed at all. */
3667 if (subreg
!= NULL_RTX
)
3669 /* Skip alternatives before the one requested. */
3670 constraint
= (curr_static_id
->operand_alternative
3671 [goal_alt_number
* n_operands
+ i
].constraint
);
3673 (c
= *constraint
) && c
!= ',' && c
!= '#';
3674 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3676 enum constraint_num cn
= lookup_constraint (constraint
);
3677 if (insn_extra_memory_constraint (cn
)
3678 && satisfies_memory_constraint_p (tem
, cn
))
3681 if (c
== '\0' || c
== ',' || c
== '#')
3684 goal_alt_win
[i
] = true;
3688 for (i
= 0; i
< n_operands
; i
++)
3691 bool optional_p
= false;
3693 rtx op
= *curr_id
->operand_loc
[i
];
3695 if (goal_alt_win
[i
])
3697 if (goal_alt
[i
] == NO_REGS
3699 /* When we assign NO_REGS it means that we will not
3700 assign a hard register to the scratch pseudo by
3701 assigment pass and the scratch pseudo will be
3702 spilled. Spilled scratch pseudos are transformed
3703 back to scratches at the LRA end. */
3704 && lra_former_scratch_operand_p (curr_insn
, i
))
3706 int regno
= REGNO (op
);
3707 lra_change_class (regno
, NO_REGS
, " Change to", true);
3708 if (lra_get_regno_hard_regno (regno
) >= 0)
3709 /* We don't have to mark all insn affected by the
3710 spilled pseudo as there is only one such insn, the
3712 reg_renumber
[regno
] = -1;
3714 /* We can do an optional reload. If the pseudo got a hard
3715 reg, we might improve the code through inheritance. If
3716 it does not get a hard register we coalesce memory/memory
3717 moves later. Ignore move insns to avoid cycling. */
3719 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3720 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3721 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3722 && regno
< new_regno_start
3723 && ! lra_former_scratch_p (regno
)
3724 && reg_renumber
[regno
] < 0
3725 && (curr_insn_set
== NULL_RTX
3726 || !((REG_P (SET_SRC (curr_insn_set
))
3727 || MEM_P (SET_SRC (curr_insn_set
))
3728 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3729 && (REG_P (SET_DEST (curr_insn_set
))
3730 || MEM_P (SET_DEST (curr_insn_set
))
3731 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3737 /* Operands that match previous ones have already been handled. */
3738 if (goal_alt_matches
[i
] >= 0)
3741 /* We should not have an operand with a non-offsettable address
3742 appearing where an offsettable address will do. It also may
3743 be a case when the address should be special in other words
3744 not a general one (e.g. it needs no index reg). */
3745 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3747 enum reg_class rclass
;
3748 rtx
*loc
= &XEXP (op
, 0);
3749 enum rtx_code code
= GET_CODE (*loc
);
3751 push_to_sequence (before
);
3752 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3754 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3755 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3756 /* This value does not matter for MODIFY. */
3757 GET_MODE_SIZE (GET_MODE (op
)));
3758 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3759 "offsetable address", &new_reg
))
3760 lra_emit_move (new_reg
, *loc
);
3761 before
= get_insns ();
3764 lra_update_dup (curr_id
, i
);
3766 else if (goal_alt_matched
[i
][0] == -1)
3770 int hard_regno
, byte
;
3771 enum op_type type
= curr_static_id
->operand
[i
].type
;
3773 loc
= curr_id
->operand_loc
[i
];
3774 mode
= curr_operand_mode
[i
];
3775 if (GET_CODE (*loc
) == SUBREG
)
3777 reg
= SUBREG_REG (*loc
);
3778 byte
= SUBREG_BYTE (*loc
);
3780 /* Strict_low_part requires reload the register not
3781 the sub-register. */
3782 && (curr_static_id
->operand
[i
].strict_low
3783 || (GET_MODE_SIZE (mode
)
3784 <= GET_MODE_SIZE (GET_MODE (reg
))
3786 = get_try_hard_regno (REGNO (reg
))) >= 0
3787 && (simplify_subreg_regno
3789 GET_MODE (reg
), byte
, mode
) < 0)
3790 && (goal_alt
[i
] == NO_REGS
3791 || (simplify_subreg_regno
3792 (ira_class_hard_regs
[goal_alt
[i
]][0],
3793 GET_MODE (reg
), byte
, mode
) >= 0)))))
3795 loc
= &SUBREG_REG (*loc
);
3796 mode
= GET_MODE (*loc
);
3800 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3801 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3804 push_to_sequence (before
);
3805 lra_emit_move (new_reg
, old
);
3806 before
= get_insns ();
3811 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3814 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3816 after
= get_insns ();
3820 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3821 if (goal_alt_dont_inherit_ops
[j
] == i
)
3823 lra_set_regno_unique_value (REGNO (new_reg
));
3826 lra_update_dup (curr_id
, i
);
3828 else if (curr_static_id
->operand
[i
].type
== OP_IN
3829 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3832 /* generate reloads for input and matched outputs. */
3833 match_inputs
[0] = i
;
3834 match_inputs
[1] = -1;
3835 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3836 goal_alt
[i
], &before
, &after
);
3838 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3839 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3841 /* Generate reloads for output and matched inputs. */
3842 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3843 else if (curr_static_id
->operand
[i
].type
== OP_IN
3844 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3847 /* Generate reloads for matched inputs. */
3848 match_inputs
[0] = i
;
3849 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3850 match_inputs
[j
+ 1] = k
;
3851 match_inputs
[j
+ 1] = -1;
3852 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3855 /* We must generate code in any case when function
3856 process_alt_operands decides that it is possible. */
3860 lra_assert (REG_P (op
));
3862 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3863 if (GET_CODE (op
) == SUBREG
)
3864 op
= SUBREG_REG (op
);
3865 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3866 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3867 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3868 if (lra_dump_file
!= NULL
)
3869 fprintf (lra_dump_file
,
3870 " Making reload reg %d for reg %d optional\n",
3874 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3875 || max_regno_before
!= max_reg_num ())
3879 lra_update_operator_dups (curr_id
);
3880 /* Something changes -- process the insn. */
3881 lra_update_insn_regno_info (curr_insn
);
3883 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3887 /* Return true if INSN satisfies all constraints. In other words, no
3888 reload insns are needed. */
3890 lra_constrain_insn (rtx_insn
*insn
)
3892 int saved_new_regno_start
= new_regno_start
;
3893 int saved_new_insn_uid_start
= new_insn_uid_start
;
3897 curr_id
= lra_get_insn_recog_data (curr_insn
);
3898 curr_static_id
= curr_id
->insn_static_data
;
3899 new_insn_uid_start
= get_max_uid ();
3900 new_regno_start
= max_reg_num ();
3901 change_p
= curr_insn_transform (true);
3902 new_regno_start
= saved_new_regno_start
;
3903 new_insn_uid_start
= saved_new_insn_uid_start
;
3907 /* Return true if X is in LIST. */
3909 in_list_p (rtx x
, rtx list
)
3911 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3912 if (XEXP (list
, 0) == x
)
3917 /* Return true if X contains an allocatable hard register (if
3918 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3920 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3926 code
= GET_CODE (x
);
3929 int regno
= REGNO (x
);
3930 HARD_REG_SET alloc_regs
;
3934 if (regno
>= FIRST_PSEUDO_REGISTER
)
3935 regno
= lra_get_regno_hard_regno (regno
);
3938 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3939 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3943 if (regno
< FIRST_PSEUDO_REGISTER
)
3947 return lra_get_regno_hard_regno (regno
) < 0;
3950 fmt
= GET_RTX_FORMAT (code
);
3951 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3955 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3958 else if (fmt
[i
] == 'E')
3960 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3961 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3968 /* Return true if X contains a symbol reg. */
3970 contains_symbol_ref_p (rtx x
)
3976 code
= GET_CODE (x
);
3977 if (code
== SYMBOL_REF
)
3979 fmt
= GET_RTX_FORMAT (code
);
3980 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3984 if (contains_symbol_ref_p (XEXP (x
, i
)))
3987 else if (fmt
[i
] == 'E')
3989 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3990 if (contains_symbol_ref_p (XVECEXP (x
, i
, j
)))
3997 /* Process all regs in location *LOC and change them on equivalent
3998 substitution. Return true if any change was done. */
4000 loc_equivalence_change_p (rtx
*loc
)
4002 rtx subst
, reg
, x
= *loc
;
4003 bool result
= false;
4004 enum rtx_code code
= GET_CODE (x
);
4010 reg
= SUBREG_REG (x
);
4011 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4012 && GET_MODE (subst
) == VOIDmode
)
4014 /* We cannot reload debug location. Simplify subreg here
4015 while we know the inner mode. */
4016 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4017 GET_MODE (reg
), SUBREG_BYTE (x
));
4021 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4027 /* Scan all the operand sub-expressions. */
4028 fmt
= GET_RTX_FORMAT (code
);
4029 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4032 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4033 else if (fmt
[i
] == 'E')
4034 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4036 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4041 /* Similar to loc_equivalence_change_p, but for use as
4042 simplify_replace_fn_rtx callback. DATA is insn for which the
4043 elimination is done. If it null we don't do the elimination. */
4045 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4050 rtx subst
= (data
== NULL
4051 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4058 /* Maximum number of generated reload insns per an insn. It is for
4059 preventing this pass cycling in a bug case. */
4060 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4062 /* The current iteration number of this LRA pass. */
4063 int lra_constraint_iter
;
4065 /* True if we substituted equiv which needs checking register
4066 allocation correctness because the equivalent value contains
4067 allocatable hard registers or when we restore multi-register
4069 bool lra_risky_transformations_p
;
4071 /* Return true if REGNO is referenced in more than one block. */
4073 multi_block_pseudo_p (int regno
)
4075 basic_block bb
= NULL
;
4079 if (regno
< FIRST_PSEUDO_REGISTER
)
4082 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4084 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4085 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4090 /* Return true if LIST contains a deleted insn. */
4092 contains_deleted_insn_p (rtx_insn_list
*list
)
4094 for (; list
!= NULL_RTX
; list
= list
->next ())
4095 if (NOTE_P (list
->insn ())
4096 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4101 /* Return true if X contains a pseudo dying in INSN. */
4103 dead_pseudo_p (rtx x
, rtx insn
)
4110 return (insn
!= NULL_RTX
4111 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4112 code
= GET_CODE (x
);
4113 fmt
= GET_RTX_FORMAT (code
);
4114 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4118 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4121 else if (fmt
[i
] == 'E')
4123 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4124 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4131 /* Return true if INSN contains a dying pseudo in INSN right hand
4134 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4136 rtx set
= single_set (insn
);
4138 gcc_assert (set
!= NULL
);
4139 return dead_pseudo_p (SET_SRC (set
), insn
);
4142 /* Return true if any init insn of REGNO contains a dying pseudo in
4143 insn right hand side. */
4145 init_insn_rhs_dead_pseudo_p (int regno
)
4147 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4151 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4152 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4157 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4158 reverse only if we have one init insn with given REGNO as a
4161 reverse_equiv_p (int regno
)
4163 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4168 if (! INSN_P (insns
->insn ())
4169 || insns
->next () != NULL
)
4171 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4173 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4176 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4177 call this function only for non-reverse equivalence. */
4179 contains_reloaded_insn_p (int regno
)
4182 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4184 for (; list
!= NULL
; list
= list
->next ())
4185 if ((set
= single_set (list
->insn ())) == NULL_RTX
4186 || ! REG_P (SET_DEST (set
))
4187 || (int) REGNO (SET_DEST (set
)) != regno
)
4192 /* Entry function of LRA constraint pass. Return true if the
4193 constraint pass did change the code. */
4195 lra_constraints (bool first_p
)
4198 int i
, hard_regno
, new_insns_num
;
4199 unsigned int min_len
, new_min_len
, uid
;
4200 rtx set
, x
, reg
, dest_reg
;
4201 basic_block last_bb
;
4202 bitmap_head equiv_insn_bitmap
;
4205 lra_constraint_iter
++;
4206 if (lra_dump_file
!= NULL
)
4207 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4208 lra_constraint_iter
);
4210 if (pic_offset_table_rtx
4211 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4212 lra_risky_transformations_p
= true;
4214 lra_risky_transformations_p
= false;
4215 new_insn_uid_start
= get_max_uid ();
4216 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4217 /* Mark used hard regs for target stack size calulations. */
4218 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4219 if (lra_reg_info
[i
].nrefs
!= 0
4220 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4224 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4225 for (j
= 0; j
< nregs
; j
++)
4226 df_set_regs_ever_live (hard_regno
+ j
, true);
4228 /* Do elimination before the equivalence processing as we can spill
4229 some pseudos during elimination. */
4230 lra_eliminate (false, first_p
);
4231 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4232 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4233 if (lra_reg_info
[i
].nrefs
!= 0)
4235 ira_reg_equiv
[i
].profitable_p
= true;
4236 reg
= regno_reg_rtx
[i
];
4237 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4239 bool pseudo_p
= contains_reg_p (x
, false, false);
4241 /* After RTL transformation, we can not guarantee that
4242 pseudo in the substitution was not reloaded which might
4243 make equivalence invalid. For example, in reverse
4250 the memory address register was reloaded before the 2nd
4252 if ((! first_p
&& pseudo_p
)
4253 /* We don't use DF for compilation speed sake. So it
4254 is problematic to update live info when we use an
4255 equivalence containing pseudos in more than one
4257 || (pseudo_p
&& multi_block_pseudo_p (i
))
4258 /* If an init insn was deleted for some reason, cancel
4259 the equiv. We could update the equiv insns after
4260 transformations including an equiv insn deletion
4261 but it is not worthy as such cases are extremely
4263 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4264 /* If it is not a reverse equivalence, we check that a
4265 pseudo in rhs of the init insn is not dying in the
4266 insn. Otherwise, the live info at the beginning of
4267 the corresponding BB might be wrong after we
4268 removed the insn. When the equiv can be a
4269 constant, the right hand side of the init insn can
4271 || (! reverse_equiv_p (i
)
4272 && (init_insn_rhs_dead_pseudo_p (i
)
4273 /* If we reloaded the pseudo in an equivalence
4274 init insn, we can not remove the equiv init
4275 insns and the init insns might write into
4276 const memory in this case. */
4277 || contains_reloaded_insn_p (i
)))
4278 /* Prevent access beyond equivalent memory for
4279 paradoxical subregs. */
4281 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4282 > GET_MODE_SIZE (GET_MODE (x
))))
4283 || (pic_offset_table_rtx
4284 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4285 && (targetm
.preferred_reload_class
4286 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4287 || contains_symbol_ref_p (x
))))
4288 ira_reg_equiv
[i
].defined_p
= false;
4289 if (contains_reg_p (x
, false, true))
4290 ira_reg_equiv
[i
].profitable_p
= false;
4291 if (get_equiv (reg
) != reg
)
4292 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4295 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4297 /* We should add all insns containing pseudos which should be
4298 substituted by their equivalences. */
4299 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4300 lra_push_insn_by_uid (uid
);
4301 min_len
= lra_insn_stack_length ();
4305 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4307 curr_insn
= lra_pop_insn ();
4309 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4310 if (curr_bb
!= last_bb
)
4313 bb_reload_num
= lra_curr_reload_num
;
4315 if (min_len
> new_min_len
)
4317 min_len
= new_min_len
;
4320 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4322 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4323 MAX_RELOAD_INSNS_NUMBER
);
4325 if (DEBUG_INSN_P (curr_insn
))
4327 /* We need to check equivalence in debug insn and change
4328 pseudo to the equivalent value if necessary. */
4329 curr_id
= lra_get_insn_recog_data (curr_insn
);
4330 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4332 rtx old
= *curr_id
->operand_loc
[0];
4333 *curr_id
->operand_loc
[0]
4334 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4335 loc_equivalence_callback
, curr_insn
);
4336 if (old
!= *curr_id
->operand_loc
[0])
4338 lra_update_insn_regno_info (curr_insn
);
4343 else if (INSN_P (curr_insn
))
4345 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4347 dest_reg
= SET_DEST (set
);
4348 /* The equivalence pseudo could be set up as SUBREG in a
4349 case when it is a call restore insn in a mode
4350 different from the pseudo mode. */
4351 if (GET_CODE (dest_reg
) == SUBREG
)
4352 dest_reg
= SUBREG_REG (dest_reg
);
4353 if ((REG_P (dest_reg
)
4354 && (x
= get_equiv (dest_reg
)) != dest_reg
4355 /* Remove insns which set up a pseudo whose value
4356 can not be changed. Such insns might be not in
4357 init_insns because we don't update equiv data
4358 during insn transformations.
4360 As an example, let suppose that a pseudo got
4361 hard register and on the 1st pass was not
4362 changed to equivalent constant. We generate an
4363 additional insn setting up the pseudo because of
4364 secondary memory movement. Then the pseudo is
4365 spilled and we use the equiv constant. In this
4366 case we should remove the additional insn and
4367 this insn is not init_insns list. */
4368 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4369 /* Check that this is actually an insn setting
4370 up the equivalence. */
4371 || in_list_p (curr_insn
,
4373 [REGNO (dest_reg
)].init_insns
)))
4374 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4375 && in_list_p (curr_insn
,
4377 [REGNO (SET_SRC (set
))].init_insns
)))
4379 /* This is equiv init insn of pseudo which did not get a
4380 hard register -- remove the insn. */
4381 if (lra_dump_file
!= NULL
)
4383 fprintf (lra_dump_file
,
4384 " Removing equiv init insn %i (freq=%d)\n",
4385 INSN_UID (curr_insn
),
4386 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4387 dump_insn_slim (lra_dump_file
, curr_insn
);
4389 if (contains_reg_p (x
, true, false))
4390 lra_risky_transformations_p
= true;
4391 lra_set_insn_deleted (curr_insn
);
4395 curr_id
= lra_get_insn_recog_data (curr_insn
);
4396 curr_static_id
= curr_id
->insn_static_data
;
4397 init_curr_insn_input_reloads ();
4398 init_curr_operand_mode ();
4399 if (curr_insn_transform (false))
4401 /* Check non-transformed insns too for equiv change as USE
4402 or CLOBBER don't need reloads but can contain pseudos
4403 being changed on their equivalences. */
4404 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4405 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4407 lra_update_insn_regno_info (curr_insn
);
4412 bitmap_clear (&equiv_insn_bitmap
);
4413 /* If we used a new hard regno, changed_p should be true because the
4414 hard reg is assigned to a new pseudo. */
4415 #ifdef ENABLE_CHECKING
4418 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4419 if (lra_reg_info
[i
].nrefs
!= 0
4420 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4422 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4424 for (j
= 0; j
< nregs
; j
++)
4425 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4432 /* Initiate the LRA constraint pass. It is done once per
4435 lra_constraints_init (void)
4439 /* Finalize the LRA constraint pass. It is done once per
4442 lra_constraints_finish (void)
4448 /* This page contains code to do inheritance/split
4451 /* Number of reloads passed so far in current EBB. */
4452 static int reloads_num
;
4454 /* Number of calls passed so far in current EBB. */
4455 static int calls_num
;
4457 /* Current reload pseudo check for validity of elements in
4459 static int curr_usage_insns_check
;
4461 /* Info about last usage of registers in EBB to do inheritance/split
4462 transformation. Inheritance transformation is done from a spilled
4463 pseudo and split transformations from a hard register or a pseudo
4464 assigned to a hard register. */
4467 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4468 value INSNS is valid. The insns is chain of optional debug insns
4469 and a finishing non-debug insn using the corresponding reg. The
4470 value is also used to mark the registers which are set up in the
4471 current insn. The negated insn uid is used for this. */
4473 /* Value of global reloads_num at the last insn in INSNS. */
4475 /* Value of global reloads_nums at the last insn in INSNS. */
4477 /* It can be true only for splitting. And it means that the restore
4478 insn should be put after insn given by the following member. */
4480 /* Next insns in the current EBB which use the original reg and the
4481 original reg value is not changed between the current insn and
4482 the next insns. In order words, e.g. for inheritance, if we need
4483 to use the original reg value again in the next insns we can try
4484 to use the value in a hard register from a reload insn of the
4489 /* Map: regno -> corresponding pseudo usage insns. */
4490 static struct usage_insns
*usage_insns
;
4493 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4495 usage_insns
[regno
].check
= curr_usage_insns_check
;
4496 usage_insns
[regno
].insns
= insn
;
4497 usage_insns
[regno
].reloads_num
= reloads_num
;
4498 usage_insns
[regno
].calls_num
= calls_num
;
4499 usage_insns
[regno
].after_p
= after_p
;
4502 /* The function is used to form list REGNO usages which consists of
4503 optional debug insns finished by a non-debug insn using REGNO.
4504 RELOADS_NUM is current number of reload insns processed so far. */
4506 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4508 rtx next_usage_insns
;
4510 if (usage_insns
[regno
].check
== curr_usage_insns_check
4511 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4512 && DEBUG_INSN_P (insn
))
4514 /* Check that we did not add the debug insn yet. */
4515 if (next_usage_insns
!= insn
4516 && (GET_CODE (next_usage_insns
) != INSN_LIST
4517 || XEXP (next_usage_insns
, 0) != insn
))
4518 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4521 else if (NONDEBUG_INSN_P (insn
))
4522 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4524 usage_insns
[regno
].check
= 0;
4527 /* Return first non-debug insn in list USAGE_INSNS. */
4529 skip_usage_debug_insns (rtx usage_insns
)
4533 /* Skip debug insns. */
4534 for (insn
= usage_insns
;
4535 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4536 insn
= XEXP (insn
, 1))
4538 return safe_as_a
<rtx_insn
*> (insn
);
4541 /* Return true if we need secondary memory moves for insn in
4542 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4545 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4546 rtx usage_insns ATTRIBUTE_UNUSED
)
4548 #ifndef SECONDARY_MEMORY_NEEDED
4555 if (inher_cl
== ALL_REGS
4556 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4558 lra_assert (INSN_P (insn
));
4559 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4561 dest
= SET_DEST (set
);
4564 lra_assert (inher_cl
!= NO_REGS
);
4565 cl
= get_reg_class (REGNO (dest
));
4566 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4567 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4571 /* Registers involved in inheritance/split in the current EBB
4572 (inheritance/split pseudos and original registers). */
4573 static bitmap_head check_only_regs
;
4575 /* Do inheritance transformations for insn INSN, which defines (if
4576 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4577 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4578 form as the "insns" field of usage_insns. Return true if we
4579 succeed in such transformation.
4581 The transformations look like:
4584 ... p <- i (new insn)
4586 <- ... p ... <- ... i ...
4588 ... i <- p (new insn)
4589 <- ... p ... <- ... i ...
4591 <- ... p ... <- ... i ...
4592 where p is a spilled original pseudo and i is a new inheritance pseudo.
4595 The inheritance pseudo has the smallest class of two classes CL and
4596 class of ORIGINAL REGNO. */
4598 inherit_reload_reg (bool def_p
, int original_regno
,
4599 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
4601 if (optimize_function_for_size_p (cfun
))
4604 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4605 rtx original_reg
= regno_reg_rtx
[original_regno
];
4606 rtx new_reg
, usage_insn
;
4607 rtx_insn
*new_insns
;
4609 lra_assert (! usage_insns
[original_regno
].after_p
);
4610 if (lra_dump_file
!= NULL
)
4611 fprintf (lra_dump_file
,
4612 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4613 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4615 if (lra_dump_file
!= NULL
)
4617 fprintf (lra_dump_file
,
4618 " Rejecting inheritance for %d "
4619 "because of disjoint classes %s and %s\n",
4620 original_regno
, reg_class_names
[cl
],
4621 reg_class_names
[rclass
]);
4622 fprintf (lra_dump_file
,
4623 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4627 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4628 /* We don't use a subset of two classes because it can be
4629 NO_REGS. This transformation is still profitable in most
4630 cases even if the classes are not intersected as register
4631 move is probably cheaper than a memory load. */
4632 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4634 if (lra_dump_file
!= NULL
)
4635 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4636 reg_class_names
[cl
], reg_class_names
[rclass
]);
4640 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4642 /* Reject inheritance resulting in secondary memory moves.
4643 Otherwise, there is a danger in LRA cycling. Also such
4644 transformation will be unprofitable. */
4645 if (lra_dump_file
!= NULL
)
4647 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
4648 rtx set
= single_set (insn
);
4650 lra_assert (set
!= NULL_RTX
);
4652 rtx dest
= SET_DEST (set
);
4654 lra_assert (REG_P (dest
));
4655 fprintf (lra_dump_file
,
4656 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4657 "as secondary mem is needed\n",
4658 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4659 original_regno
, reg_class_names
[rclass
]);
4660 fprintf (lra_dump_file
,
4661 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4665 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4666 rclass
, "inheritance");
4669 lra_emit_move (original_reg
, new_reg
);
4671 lra_emit_move (new_reg
, original_reg
);
4672 new_insns
= get_insns ();
4674 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4676 if (lra_dump_file
!= NULL
)
4678 fprintf (lra_dump_file
,
4679 " Rejecting inheritance %d->%d "
4680 "as it results in 2 or more insns:\n",
4681 original_regno
, REGNO (new_reg
));
4682 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
4683 fprintf (lra_dump_file
,
4684 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4688 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
);
4689 lra_update_insn_regno_info (insn
);
4691 /* We now have a new usage insn for original regno. */
4692 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4693 if (lra_dump_file
!= NULL
)
4694 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4695 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4696 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4697 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4698 bitmap_set_bit (&check_only_regs
, original_regno
);
4699 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4701 lra_process_new_insns (insn
, NULL
, new_insns
,
4702 "Add original<-inheritance");
4704 lra_process_new_insns (insn
, new_insns
, NULL
,
4705 "Add inheritance<-original");
4706 while (next_usage_insns
!= NULL_RTX
)
4708 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4710 usage_insn
= next_usage_insns
;
4711 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4712 next_usage_insns
= NULL
;
4716 usage_insn
= XEXP (next_usage_insns
, 0);
4717 lra_assert (DEBUG_INSN_P (usage_insn
));
4718 next_usage_insns
= XEXP (next_usage_insns
, 1);
4720 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4721 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4722 if (lra_dump_file
!= NULL
)
4724 fprintf (lra_dump_file
,
4725 " Inheritance reuse change %d->%d (bb%d):\n",
4726 original_regno
, REGNO (new_reg
),
4727 BLOCK_FOR_INSN (usage_insn
)->index
);
4728 dump_insn_slim (lra_dump_file
, usage_insn
);
4731 if (lra_dump_file
!= NULL
)
4732 fprintf (lra_dump_file
,
4733 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4737 /* Return true if we need a caller save/restore for pseudo REGNO which
4738 was assigned to a hard register. */
4740 need_for_call_save_p (int regno
)
4742 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4743 return (usage_insns
[regno
].calls_num
< calls_num
4744 && (overlaps_hard_reg_set_p
4746 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4747 ? lra_reg_info
[regno
].actual_call_used_reg_set
4748 : call_used_reg_set
,
4749 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4750 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4751 PSEUDO_REGNO_MODE (regno
))));
4754 /* Global registers occurring in the current EBB. */
4755 static bitmap_head ebb_global_regs
;
4757 /* Return true if we need a split for hard register REGNO or pseudo
4758 REGNO which was assigned to a hard register.
4759 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4760 used for reloads since the EBB end. It is an approximation of the
4761 used hard registers in the split range. The exact value would
4762 require expensive calculations. If we were aggressive with
4763 splitting because of the approximation, the split pseudo will save
4764 the same hard register assignment and will be removed in the undo
4765 pass. We still need the approximation because too aggressive
4766 splitting would result in too inaccurate cost calculation in the
4767 assignment pass because of too many generated moves which will be
4768 probably removed in the undo pass. */
4770 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4772 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4774 lra_assert (hard_regno
>= 0);
4775 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4776 /* Don't split eliminable hard registers, otherwise we can
4777 split hard registers like hard frame pointer, which
4778 lives on BB start/end according to DF-infrastructure,
4779 when there is a pseudo assigned to the register and
4780 living in the same BB. */
4781 && (regno
>= FIRST_PSEUDO_REGISTER
4782 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4783 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4784 /* Don't split call clobbered hard regs living through
4785 calls, otherwise we might have a check problem in the
4786 assign sub-pass as in the most cases (exception is a
4787 situation when lra_risky_transformations_p value is
4788 true) the assign pass assumes that all pseudos living
4789 through calls are assigned to call saved hard regs. */
4790 && (regno
>= FIRST_PSEUDO_REGISTER
4791 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4792 || usage_insns
[regno
].calls_num
== calls_num
)
4793 /* We need at least 2 reloads to make pseudo splitting
4794 profitable. We should provide hard regno splitting in
4795 any case to solve 1st insn scheduling problem when
4796 moving hard register definition up might result in
4797 impossibility to find hard register for reload pseudo of
4798 small register class. */
4799 && (usage_insns
[regno
].reloads_num
4800 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4801 && (regno
< FIRST_PSEUDO_REGISTER
4802 /* For short living pseudos, spilling + inheritance can
4803 be considered a substitution for splitting.
4804 Therefore we do not splitting for local pseudos. It
4805 decreases also aggressiveness of splitting. The
4806 minimal number of references is chosen taking into
4807 account that for 2 references splitting has no sense
4808 as we can just spill the pseudo. */
4809 || (regno
>= FIRST_PSEUDO_REGISTER
4810 && lra_reg_info
[regno
].nrefs
> 3
4811 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4812 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4815 /* Return class for the split pseudo created from original pseudo with
4816 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4817 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4818 results in no secondary memory movements. */
4819 static enum reg_class
4820 choose_split_class (enum reg_class allocno_class
,
4821 int hard_regno ATTRIBUTE_UNUSED
,
4822 machine_mode mode ATTRIBUTE_UNUSED
)
4824 #ifndef SECONDARY_MEMORY_NEEDED
4825 return allocno_class
;
4828 enum reg_class cl
, best_cl
= NO_REGS
;
4829 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4830 = REGNO_REG_CLASS (hard_regno
);
4832 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4833 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4834 return allocno_class
;
4836 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4838 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4839 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4840 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4841 && (best_cl
== NO_REGS
4842 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4848 /* Do split transformations for insn INSN, which defines or uses
4849 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4850 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4851 "insns" field of usage_insns.
4853 The transformations look like:
4856 ... s <- p (new insn -- save)
4858 ... p <- s (new insn -- restore)
4859 <- ... p ... <- ... p ...
4861 <- ... p ... <- ... p ...
4862 ... s <- p (new insn -- save)
4864 ... p <- s (new insn -- restore)
4865 <- ... p ... <- ... p ...
4867 where p is an original pseudo got a hard register or a hard
4868 register and s is a new split pseudo. The save is put before INSN
4869 if BEFORE_P is true. Return true if we succeed in such
4872 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
4873 rtx next_usage_insns
)
4875 enum reg_class rclass
;
4877 int hard_regno
, nregs
;
4878 rtx new_reg
, usage_insn
;
4879 rtx_insn
*restore
, *save
;
4883 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4885 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4886 hard_regno
= original_regno
;
4887 call_save_p
= false;
4892 hard_regno
= reg_renumber
[original_regno
];
4893 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4894 rclass
= lra_get_allocno_class (original_regno
);
4895 original_reg
= regno_reg_rtx
[original_regno
];
4896 call_save_p
= need_for_call_save_p (original_regno
);
4898 original_reg
= regno_reg_rtx
[original_regno
];
4899 lra_assert (hard_regno
>= 0);
4900 if (lra_dump_file
!= NULL
)
4901 fprintf (lra_dump_file
,
4902 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4905 machine_mode mode
= GET_MODE (original_reg
);
4907 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4908 hard_regno_nregs
[hard_regno
][mode
],
4910 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4914 rclass
= choose_split_class (rclass
, hard_regno
,
4915 GET_MODE (original_reg
));
4916 if (rclass
== NO_REGS
)
4918 if (lra_dump_file
!= NULL
)
4920 fprintf (lra_dump_file
,
4921 " Rejecting split of %d(%s): "
4922 "no good reg class for %d(%s)\n",
4924 reg_class_names
[lra_get_allocno_class (original_regno
)],
4926 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4929 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4933 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4935 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4937 save
= emit_spill_move (true, new_reg
, original_reg
);
4938 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
4940 if (lra_dump_file
!= NULL
)
4944 " Rejecting split %d->%d resulting in > 2 save insns:\n",
4945 original_regno
, REGNO (new_reg
));
4946 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
4947 fprintf (lra_dump_file
,
4948 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4952 restore
= emit_spill_move (false, new_reg
, original_reg
);
4953 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
4955 if (lra_dump_file
!= NULL
)
4957 fprintf (lra_dump_file
,
4958 " Rejecting split %d->%d "
4959 "resulting in > 2 restore insns:\n",
4960 original_regno
, REGNO (new_reg
));
4961 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
4962 fprintf (lra_dump_file
,
4963 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4967 after_p
= usage_insns
[original_regno
].after_p
;
4968 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4969 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4970 bitmap_set_bit (&check_only_regs
, original_regno
);
4971 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4974 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4976 usage_insn
= next_usage_insns
;
4979 usage_insn
= XEXP (next_usage_insns
, 0);
4980 lra_assert (DEBUG_INSN_P (usage_insn
));
4981 next_usage_insns
= XEXP (next_usage_insns
, 1);
4982 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4983 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4984 if (lra_dump_file
!= NULL
)
4986 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4987 original_regno
, REGNO (new_reg
));
4988 dump_insn_slim (lra_dump_file
, usage_insn
);
4991 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4992 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4993 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
4994 after_p
? NULL
: restore
,
4995 after_p
? restore
: NULL
,
4997 ? "Add reg<-save" : "Add reg<-split");
4998 lra_process_new_insns (insn
, before_p
? save
: NULL
,
4999 before_p
? NULL
: save
,
5001 ? "Add save<-reg" : "Add split<-reg");
5003 /* If we are trying to split multi-register. We should check
5004 conflicts on the next assignment sub-pass. IRA can allocate on
5005 sub-register levels, LRA do this on pseudos level right now and
5006 this discrepancy may create allocation conflicts after
5008 lra_risky_transformations_p
= true;
5009 if (lra_dump_file
!= NULL
)
5010 fprintf (lra_dump_file
,
5011 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5015 /* Recognize that we need a split transformation for insn INSN, which
5016 defines or uses REGNO in its insn biggest MODE (we use it only if
5017 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5018 hard registers which might be used for reloads since the EBB end.
5019 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5020 uid before starting INSN processing. Return true if we succeed in
5021 such transformation. */
5023 split_if_necessary (int regno
, machine_mode mode
,
5024 HARD_REG_SET potential_reload_hard_regs
,
5025 bool before_p
, rtx_insn
*insn
, int max_uid
)
5029 rtx next_usage_insns
;
5031 if (regno
< FIRST_PSEUDO_REGISTER
)
5032 nregs
= hard_regno_nregs
[regno
][mode
];
5033 for (i
= 0; i
< nregs
; i
++)
5034 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5035 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5036 /* To avoid processing the register twice or more. */
5037 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5038 && INSN_UID (next_usage_insns
) < max_uid
)
5039 || (GET_CODE (next_usage_insns
) == INSN_LIST
5040 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5041 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5042 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5047 /* Check only registers living at the current program point in the
5049 static bitmap_head live_regs
;
5051 /* Update live info in EBB given by its HEAD and TAIL insns after
5052 inheritance/split transformation. The function removes dead moves
5055 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5060 rtx_insn
*prev_insn
;
5063 basic_block last_bb
, prev_bb
, curr_bb
;
5065 struct lra_insn_reg
*reg
;
5069 last_bb
= BLOCK_FOR_INSN (tail
);
5071 for (curr_insn
= tail
;
5072 curr_insn
!= PREV_INSN (head
);
5073 curr_insn
= prev_insn
)
5075 prev_insn
= PREV_INSN (curr_insn
);
5076 /* We need to process empty blocks too. They contain
5077 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5078 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5080 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5081 if (curr_bb
!= prev_bb
)
5083 if (prev_bb
!= NULL
)
5085 /* Update df_get_live_in (prev_bb): */
5086 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5087 if (bitmap_bit_p (&live_regs
, j
))
5088 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5090 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5092 if (curr_bb
!= last_bb
)
5094 /* Update df_get_live_out (curr_bb): */
5095 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5097 live_p
= bitmap_bit_p (&live_regs
, j
);
5099 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5100 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5106 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5108 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5112 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5114 if (! NONDEBUG_INSN_P (curr_insn
))
5116 curr_id
= lra_get_insn_recog_data (curr_insn
);
5117 curr_static_id
= curr_id
->insn_static_data
;
5119 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
5120 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5121 && bitmap_bit_p (&check_only_regs
, regno
)
5122 && ! bitmap_bit_p (&live_regs
, regno
))
5124 /* See which defined values die here. */
5125 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5126 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5127 bitmap_clear_bit (&live_regs
, reg
->regno
);
5128 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5129 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5130 bitmap_clear_bit (&live_regs
, reg
->regno
);
5131 /* Mark each used value as live. */
5132 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5133 if (reg
->type
!= OP_OUT
5134 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5135 bitmap_set_bit (&live_regs
, reg
->regno
);
5136 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5137 if (reg
->type
!= OP_OUT
5138 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5139 bitmap_set_bit (&live_regs
, reg
->regno
);
5140 if (curr_id
->arg_hard_regs
!= NULL
)
5141 /* Make argument hard registers live. */
5142 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5143 if (bitmap_bit_p (&check_only_regs
, regno
))
5144 bitmap_set_bit (&live_regs
, regno
);
5145 /* It is quite important to remove dead move insns because it
5146 means removing dead store. We don't need to process them for
5150 if (lra_dump_file
!= NULL
)
5152 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5153 dump_insn_slim (lra_dump_file
, curr_insn
);
5155 lra_set_insn_deleted (curr_insn
);
5160 /* The structure describes info to do an inheritance for the current
5161 insn. We need to collect such info first before doing the
5162 transformations because the transformations change the insn
5163 internal representation. */
5166 /* Original regno. */
5168 /* Subsequent insns which can inherit original reg value. */
5172 /* Array containing all info for doing inheritance from the current
5174 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5176 /* Number elements in the previous array. */
5177 static int to_inherit_num
;
5179 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5180 structure to_inherit. */
5182 add_to_inherit (int regno
, rtx insns
)
5186 for (i
= 0; i
< to_inherit_num
; i
++)
5187 if (to_inherit
[i
].regno
== regno
)
5189 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5190 to_inherit
[to_inherit_num
].regno
= regno
;
5191 to_inherit
[to_inherit_num
++].insns
= insns
;
5194 /* Return the last non-debug insn in basic block BB, or the block begin
5197 get_last_insertion_point (basic_block bb
)
5201 FOR_BB_INSNS_REVERSE (bb
, insn
)
5202 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5207 /* Set up RES by registers living on edges FROM except the edge (FROM,
5208 TO) or by registers set up in a jump insn in BB FROM. */
5210 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5213 struct lra_insn_reg
*reg
;
5217 lra_assert (to
!= NULL
);
5219 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5221 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5222 last
= get_last_insertion_point (from
);
5223 if (! JUMP_P (last
))
5225 curr_id
= lra_get_insn_recog_data (last
);
5226 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5227 if (reg
->type
!= OP_IN
)
5228 bitmap_set_bit (res
, reg
->regno
);
5231 /* Used as a temporary results of some bitmap calculations. */
5232 static bitmap_head temp_bitmap
;
5234 /* We split for reloads of small class of hard regs. The following
5235 defines how many hard regs the class should have to be qualified as
5236 small. The code is mostly oriented to x86/x86-64 architecture
5237 where some insns need to use only specific register or pair of
5238 registers and these register can live in RTL explicitly, e.g. for
5239 parameter passing. */
5240 static const int max_small_class_regs_num
= 2;
5242 /* Do inheritance/split transformations in EBB starting with HEAD and
5243 finishing on TAIL. We process EBB insns in the reverse order.
5244 Return true if we did any inheritance/split transformation in the
5247 We should avoid excessive splitting which results in worse code
5248 because of inaccurate cost calculations for spilling new split
5249 pseudos in such case. To achieve this we do splitting only if
5250 register pressure is high in given basic block and there are reload
5251 pseudos requiring hard registers. We could do more register
5252 pressure calculations at any given program point to avoid necessary
5253 splitting even more but it is to expensive and the current approach
5254 works well enough. */
5256 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5258 int i
, src_regno
, dst_regno
, nregs
;
5259 bool change_p
, succ_p
, update_reloads_num_p
;
5260 rtx_insn
*prev_insn
, *last_insn
;
5261 rtx next_usage_insns
, set
;
5263 struct lra_insn_reg
*reg
;
5264 basic_block last_processed_bb
, curr_bb
= NULL
;
5265 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5269 bool head_p
, after_p
;
5272 curr_usage_insns_check
++;
5273 reloads_num
= calls_num
= 0;
5274 bitmap_clear (&check_only_regs
);
5275 last_processed_bb
= NULL
;
5276 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5277 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5278 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5279 /* We don't process new insns generated in the loop. */
5280 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5282 prev_insn
= PREV_INSN (curr_insn
);
5283 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5284 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5285 if (last_processed_bb
!= curr_bb
)
5287 /* We are at the end of BB. Add qualified living
5288 pseudos for potential splitting. */
5289 to_process
= df_get_live_out (curr_bb
);
5290 if (last_processed_bb
!= NULL
)
5292 /* We are somewhere in the middle of EBB. */
5293 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5295 to_process
= &temp_bitmap
;
5297 last_processed_bb
= curr_bb
;
5298 last_insn
= get_last_insertion_point (curr_bb
);
5299 after_p
= (! JUMP_P (last_insn
)
5300 && (! CALL_P (last_insn
)
5301 || (find_reg_note (last_insn
,
5302 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5303 && ! SIBLING_CALL_P (last_insn
))));
5304 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5305 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5307 if ((int) j
>= lra_constraint_new_regno_start
)
5309 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5311 if (j
< FIRST_PSEUDO_REGISTER
)
5312 SET_HARD_REG_BIT (live_hard_regs
, j
);
5314 add_to_hard_reg_set (&live_hard_regs
,
5315 PSEUDO_REGNO_MODE (j
),
5317 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5321 src_regno
= dst_regno
= -1;
5322 if (NONDEBUG_INSN_P (curr_insn
)
5323 && (set
= single_set (curr_insn
)) != NULL_RTX
5324 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5326 src_regno
= REGNO (SET_SRC (set
));
5327 dst_regno
= REGNO (SET_DEST (set
));
5329 update_reloads_num_p
= true;
5330 if (src_regno
< lra_constraint_new_regno_start
5331 && src_regno
>= FIRST_PSEUDO_REGISTER
5332 && reg_renumber
[src_regno
] < 0
5333 && dst_regno
>= lra_constraint_new_regno_start
5334 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5336 /* 'reload_pseudo <- original_pseudo'. */
5337 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5339 update_reloads_num_p
= false;
5341 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5342 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5343 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5344 curr_insn
, next_usage_insns
);
5348 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5349 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5350 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5351 reg_class_contents
[cl
]);
5353 else if (src_regno
>= lra_constraint_new_regno_start
5354 && dst_regno
< lra_constraint_new_regno_start
5355 && dst_regno
>= FIRST_PSEUDO_REGISTER
5356 && reg_renumber
[dst_regno
] < 0
5357 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5358 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5359 && (next_usage_insns
5360 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5362 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5364 update_reloads_num_p
= false;
5365 /* 'original_pseudo <- reload_pseudo'. */
5366 if (! JUMP_P (curr_insn
)
5367 && inherit_reload_reg (true, dst_regno
, cl
,
5368 curr_insn
, next_usage_insns
))
5371 usage_insns
[dst_regno
].check
= 0;
5372 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5373 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5374 reg_class_contents
[cl
]);
5376 else if (INSN_P (curr_insn
))
5379 int max_uid
= get_max_uid ();
5381 curr_id
= lra_get_insn_recog_data (curr_insn
);
5382 curr_static_id
= curr_id
->insn_static_data
;
5384 /* Process insn definitions. */
5385 for (iter
= 0; iter
< 2; iter
++)
5386 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5389 if (reg
->type
!= OP_IN
5390 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5392 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5393 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5394 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5395 && (next_usage_insns
5396 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5398 struct lra_insn_reg
*r
;
5400 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5401 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5403 /* Don't do inheritance if the pseudo is also
5404 used in the insn. */
5406 /* We can not do inheritance right now
5407 because the current insn reg info (chain
5408 regs) can change after that. */
5409 add_to_inherit (dst_regno
, next_usage_insns
);
5411 /* We can not process one reg twice here because of
5412 usage_insns invalidation. */
5413 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5414 || reg_renumber
[dst_regno
] >= 0)
5415 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5419 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5420 potential_reload_hard_regs
,
5421 false, curr_insn
, max_uid
))
5423 CLEAR_HARD_REG_SET (s
);
5424 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5425 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5427 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5428 reg_renumber
[dst_regno
]);
5429 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5431 /* We should invalidate potential inheritance or
5432 splitting for the current insn usages to the next
5433 usage insns (see code below) as the output pseudo
5435 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5436 && reg_renumber
[dst_regno
] < 0)
5437 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5438 && (dst_regno
< FIRST_PSEUDO_REGISTER
5439 || reg_renumber
[dst_regno
] >= 0)))
5441 /* Invalidate and mark definitions. */
5442 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5443 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5446 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5447 for (i
= 0; i
< nregs
; i
++)
5448 usage_insns
[dst_regno
+ i
].check
5449 = -(int) INSN_UID (curr_insn
);
5453 if (! JUMP_P (curr_insn
))
5454 for (i
= 0; i
< to_inherit_num
; i
++)
5455 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5456 ALL_REGS
, curr_insn
,
5457 to_inherit
[i
].insns
))
5459 if (CALL_P (curr_insn
))
5461 rtx cheap
, pat
, dest
;
5463 int regno
, hard_regno
;
5466 if ((cheap
= find_reg_note (curr_insn
,
5467 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5468 && ((cheap
= XEXP (cheap
, 0)), true)
5469 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5470 && (hard_regno
= reg_renumber
[regno
]) >= 0
5471 /* If there are pending saves/restores, the
5472 optimization is not worth. */
5473 && usage_insns
[regno
].calls_num
== calls_num
- 1
5474 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5476 /* Restore the pseudo from the call result as
5477 REG_RETURNED note says that the pseudo value is
5478 in the call result and the pseudo is an argument
5480 pat
= PATTERN (curr_insn
);
5481 if (GET_CODE (pat
) == PARALLEL
)
5482 pat
= XVECEXP (pat
, 0, 0);
5483 dest
= SET_DEST (pat
);
5484 /* For multiple return values dest is PARALLEL.
5485 Currently we handle only single return value case. */
5489 emit_move_insn (cheap
, copy_rtx (dest
));
5490 restore
= get_insns ();
5492 lra_process_new_insns (curr_insn
, NULL
, restore
,
5493 "Inserting call parameter restore");
5494 /* We don't need to save/restore of the pseudo from
5496 usage_insns
[regno
].calls_num
= calls_num
;
5497 bitmap_set_bit (&check_only_regs
, regno
);
5502 /* Process insn usages. */
5503 for (iter
= 0; iter
< 2; iter
++)
5504 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5507 if ((reg
->type
!= OP_OUT
5508 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5509 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5511 if (src_regno
>= FIRST_PSEUDO_REGISTER
5512 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5514 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5515 && (next_usage_insns
5516 = usage_insns
[src_regno
].insns
) != NULL_RTX
5517 && NONDEBUG_INSN_P (curr_insn
))
5518 add_to_inherit (src_regno
, next_usage_insns
);
5519 else if (usage_insns
[src_regno
].check
5520 != -(int) INSN_UID (curr_insn
))
5521 /* Add usages but only if the reg is not set up
5522 in the same insn. */
5523 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5525 else if (src_regno
< FIRST_PSEUDO_REGISTER
5526 || reg_renumber
[src_regno
] >= 0)
5529 rtx use_insn
= curr_insn
;
5531 before_p
= (JUMP_P (curr_insn
)
5532 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5533 if (NONDEBUG_INSN_P (curr_insn
)
5534 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5535 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5536 potential_reload_hard_regs
,
5537 before_p
, curr_insn
, max_uid
))
5540 lra_risky_transformations_p
= true;
5543 usage_insns
[src_regno
].check
= 0;
5545 use_insn
= PREV_INSN (curr_insn
);
5547 if (NONDEBUG_INSN_P (curr_insn
))
5549 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5550 add_to_hard_reg_set (&live_hard_regs
,
5551 reg
->biggest_mode
, src_regno
);
5553 add_to_hard_reg_set (&live_hard_regs
,
5554 PSEUDO_REGNO_MODE (src_regno
),
5555 reg_renumber
[src_regno
]);
5557 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5560 /* Process call args. */
5561 if (curr_id
->arg_hard_regs
!= NULL
)
5562 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5563 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5565 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5566 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5568 for (i
= 0; i
< to_inherit_num
; i
++)
5570 src_regno
= to_inherit
[i
].regno
;
5571 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5572 curr_insn
, to_inherit
[i
].insns
))
5575 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5578 if (update_reloads_num_p
5579 && NONDEBUG_INSN_P (curr_insn
)
5580 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5583 if ((REG_P (SET_DEST (set
))
5584 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5585 && reg_renumber
[regno
] < 0
5586 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5587 || (REG_P (SET_SRC (set
))
5588 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5589 && reg_renumber
[regno
] < 0
5590 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5592 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5594 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5595 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5596 reg_class_contents
[cl
]);
5599 /* We reached the start of the current basic block. */
5600 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5601 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5603 /* We reached the beginning of the current block -- do
5604 rest of spliting in the current BB. */
5605 to_process
= df_get_live_in (curr_bb
);
5606 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5608 /* We are somewhere in the middle of EBB. */
5609 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5610 curr_bb
, &temp_bitmap
);
5611 to_process
= &temp_bitmap
;
5614 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5616 if ((int) j
>= lra_constraint_new_regno_start
)
5618 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5619 && usage_insns
[j
].check
== curr_usage_insns_check
5620 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5622 if (need_for_split_p (potential_reload_hard_regs
, j
))
5624 if (lra_dump_file
!= NULL
&& head_p
)
5626 fprintf (lra_dump_file
,
5627 " ----------------------------------\n");
5630 if (split_reg (false, j
, bb_note (curr_bb
),
5634 usage_insns
[j
].check
= 0;
5642 /* This value affects EBB forming. If probability of edge from EBB to
5643 a BB is not greater than the following value, we don't add the BB
5645 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5647 /* Current number of inheritance/split iteration. */
5648 int lra_inheritance_iter
;
5650 /* Entry function for inheritance/split pass. */
5652 lra_inheritance (void)
5655 basic_block bb
, start_bb
;
5658 lra_inheritance_iter
++;
5659 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5661 timevar_push (TV_LRA_INHERITANCE
);
5662 if (lra_dump_file
!= NULL
)
5663 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5664 lra_inheritance_iter
);
5665 curr_usage_insns_check
= 0;
5666 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5667 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5668 usage_insns
[i
].check
= 0;
5669 bitmap_initialize (&check_only_regs
, ®_obstack
);
5670 bitmap_initialize (&live_regs
, ®_obstack
);
5671 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5672 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5673 FOR_EACH_BB_FN (bb
, cfun
)
5676 if (lra_dump_file
!= NULL
)
5677 fprintf (lra_dump_file
, "EBB");
5678 /* Form a EBB starting with BB. */
5679 bitmap_clear (&ebb_global_regs
);
5680 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5683 if (lra_dump_file
!= NULL
)
5684 fprintf (lra_dump_file
, " %d", bb
->index
);
5685 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5686 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5688 e
= find_fallthru_edge (bb
->succs
);
5691 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5695 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5696 if (lra_dump_file
!= NULL
)
5697 fprintf (lra_dump_file
, "\n");
5698 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5699 /* Remember that the EBB head and tail can change in
5701 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5703 bitmap_clear (&ebb_global_regs
);
5704 bitmap_clear (&temp_bitmap
);
5705 bitmap_clear (&live_regs
);
5706 bitmap_clear (&check_only_regs
);
5709 timevar_pop (TV_LRA_INHERITANCE
);
5714 /* This page contains code to undo failed inheritance/split
5717 /* Current number of iteration undoing inheritance/split. */
5718 int lra_undo_inheritance_iter
;
5720 /* Fix BB live info LIVE after removing pseudos created on pass doing
5721 inheritance/split which are REMOVED_PSEUDOS. */
5723 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5728 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5729 if (bitmap_clear_bit (live
, regno
))
5730 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5733 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5738 if (GET_CODE (reg
) == SUBREG
)
5739 reg
= SUBREG_REG (reg
);
5745 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5746 return true if we did any change. The undo transformations for
5747 inheritance looks like
5751 p <- i, i <- p, and i <- i3
5752 where p is original pseudo from which inheritance pseudo i was
5753 created, i and i3 are removed inheritance pseudos, i2 is another
5754 not removed inheritance pseudo. All split pseudos or other
5755 occurrences of removed inheritance pseudos are changed on the
5756 corresponding original pseudos.
5758 The function also schedules insns changed and created during
5759 inheritance/split pass for processing by the subsequent constraint
5762 remove_inheritance_pseudos (bitmap remove_pseudos
)
5765 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5767 rtx_insn
*prev_insn
;
5768 bool change_p
, done_p
;
5770 change_p
= ! bitmap_empty_p (remove_pseudos
);
5771 /* We can not finish the function right away if CHANGE_P is true
5772 because we need to marks insns affected by previous
5773 inheritance/split pass for processing by the subsequent
5775 FOR_EACH_BB_FN (bb
, cfun
)
5777 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5778 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5779 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5781 if (! INSN_P (curr_insn
))
5784 sregno
= dregno
= -1;
5785 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5786 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5788 dregno
= get_regno (SET_DEST (set
));
5789 sregno
= get_regno (SET_SRC (set
));
5792 if (sregno
>= 0 && dregno
>= 0)
5794 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5795 && (lra_reg_info
[sregno
].restore_regno
== dregno
5796 || (bitmap_bit_p (remove_pseudos
, dregno
)
5797 && (lra_reg_info
[sregno
].restore_regno
5798 == lra_reg_info
[dregno
].restore_regno
))))
5799 || (bitmap_bit_p (remove_pseudos
, dregno
)
5800 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5801 /* One of the following cases:
5802 original <- removed inheritance pseudo
5803 removed inherit pseudo <- another removed inherit pseudo
5804 removed inherit pseudo <- original pseudo
5806 removed_split_pseudo <- original_reg
5807 original_reg <- removed_split_pseudo */
5809 if (lra_dump_file
!= NULL
)
5811 fprintf (lra_dump_file
, " Removing %s:\n",
5812 bitmap_bit_p (&lra_split_regs
, sregno
)
5813 || bitmap_bit_p (&lra_split_regs
, dregno
)
5814 ? "split" : "inheritance");
5815 dump_insn_slim (lra_dump_file
, curr_insn
);
5817 lra_set_insn_deleted (curr_insn
);
5820 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5821 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5823 /* Search the following pattern:
5824 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5825 original_pseudo <- inherit_or_split_pseudo1
5826 where the 2nd insn is the current insn and
5827 inherit_or_split_pseudo2 is not removed. If it is found,
5828 change the current insn onto:
5829 original_pseudo <- inherit_or_split_pseudo2. */
5830 for (prev_insn
= PREV_INSN (curr_insn
);
5831 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5832 prev_insn
= PREV_INSN (prev_insn
))
5834 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5835 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5836 /* There should be no subregs in insn we are
5837 searching because only the original reg might
5838 be in subreg when we changed the mode of
5839 load/store for splitting. */
5840 && REG_P (SET_DEST (prev_set
))
5841 && REG_P (SET_SRC (prev_set
))
5842 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5843 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5844 >= FIRST_PSEUDO_REGISTER
)
5845 /* As we consider chain of inheritance or
5846 splitting described in above comment we should
5847 check that sregno and prev_sregno were
5848 inheritance/split pseudos created from the
5849 same original regno. */
5850 && (lra_reg_info
[sregno
].restore_regno
5851 == lra_reg_info
[prev_sregno
].restore_regno
)
5852 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5854 lra_assert (GET_MODE (SET_SRC (prev_set
))
5855 == GET_MODE (regno_reg_rtx
[sregno
]));
5856 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5857 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5859 SET_SRC (set
) = SET_SRC (prev_set
);
5860 /* As we are finishing with processing the insn
5861 here, check the destination too as it might
5862 inheritance pseudo for another pseudo. */
5863 if (bitmap_bit_p (remove_pseudos
, dregno
)
5864 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
5866 = lra_reg_info
[dregno
].restore_regno
) >= 0)
5868 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
5869 SUBREG_REG (SET_DEST (set
))
5870 = regno_reg_rtx
[restore_regno
];
5872 SET_DEST (set
) = regno_reg_rtx
[restore_regno
];
5874 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5875 lra_set_used_insn_alternative_by_uid
5876 (INSN_UID (curr_insn
), -1);
5878 if (lra_dump_file
!= NULL
)
5880 fprintf (lra_dump_file
, " Change reload insn:\n");
5881 dump_insn_slim (lra_dump_file
, curr_insn
);
5888 struct lra_insn_reg
*reg
;
5889 bool restored_regs_p
= false;
5890 bool kept_regs_p
= false;
5892 curr_id
= lra_get_insn_recog_data (curr_insn
);
5893 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5896 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5897 if (restore_regno
>= 0)
5899 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5901 lra_substitute_pseudo_within_insn (
5902 curr_insn
, regno
, regno_reg_rtx
[restore_regno
]);
5903 restored_regs_p
= true;
5909 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5911 /* The instruction has changed since the previous
5912 constraints pass. */
5913 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5914 lra_set_used_insn_alternative_by_uid
5915 (INSN_UID (curr_insn
), -1);
5917 else if (restored_regs_p
)
5918 /* The instruction has been restored to the form that
5919 it had during the previous constraints pass. */
5920 lra_update_insn_regno_info (curr_insn
);
5921 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5923 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5924 dump_insn_slim (lra_dump_file
, curr_insn
);
5932 /* If optional reload pseudos failed to get a hard register or was not
5933 inherited, it is better to remove optional reloads. We do this
5934 transformation after undoing inheritance to figure out necessity to
5935 remove optional reloads easier. Return true if we do any
5938 undo_optional_reloads (void)
5940 bool change_p
, keep_p
;
5941 unsigned int regno
, uid
;
5942 bitmap_iterator bi
, bi2
;
5945 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5947 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5948 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5949 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5952 /* Keep optional reloads from previous subpasses. */
5953 if (lra_reg_info
[regno
].restore_regno
< 0
5954 /* If the original pseudo changed its allocation, just
5955 removing the optional pseudo is dangerous as the original
5956 pseudo will have longer live range. */
5957 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5959 else if (reg_renumber
[regno
] >= 0)
5960 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5962 insn
= lra_insn_recog_data
[uid
]->insn
;
5963 if ((set
= single_set (insn
)) == NULL_RTX
)
5965 src
= SET_SRC (set
);
5966 dest
= SET_DEST (set
);
5967 if (! REG_P (src
) || ! REG_P (dest
))
5969 if (REGNO (dest
) == regno
5970 /* Ignore insn for optional reloads itself. */
5971 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5972 /* Check only inheritance on last inheritance pass. */
5973 && (int) REGNO (src
) >= new_regno_start
5974 /* Check that the optional reload was inherited. */
5975 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5983 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5984 if (lra_dump_file
!= NULL
)
5985 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5988 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5989 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5990 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5992 if (lra_dump_file
!= NULL
)
5993 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5994 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5995 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5997 insn
= lra_insn_recog_data
[uid
]->insn
;
5998 if ((set
= single_set (insn
)) != NULL_RTX
)
6000 src
= SET_SRC (set
);
6001 dest
= SET_DEST (set
);
6002 if (REG_P (src
) && REG_P (dest
)
6003 && ((REGNO (src
) == regno
6004 && (lra_reg_info
[regno
].restore_regno
6005 == (int) REGNO (dest
)))
6006 || (REGNO (dest
) == regno
6007 && (lra_reg_info
[regno
].restore_regno
6008 == (int) REGNO (src
)))))
6010 if (lra_dump_file
!= NULL
)
6012 fprintf (lra_dump_file
, " Deleting move %u\n",
6014 dump_insn_slim (lra_dump_file
, insn
);
6016 lra_set_insn_deleted (insn
);
6019 /* We should not worry about generation memory-memory
6020 moves here as if the corresponding inheritance did
6021 not work (inheritance pseudo did not get a hard reg),
6022 we remove the inheritance pseudo and the optional
6025 lra_substitute_pseudo_within_insn (
6027 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
6028 lra_update_insn_regno_info (insn
);
6029 if (lra_dump_file
!= NULL
)
6031 fprintf (lra_dump_file
,
6032 " Restoring original insn:\n");
6033 dump_insn_slim (lra_dump_file
, insn
);
6037 /* Clear restore_regnos. */
6038 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6039 lra_reg_info
[regno
].restore_regno
= -1;
6040 bitmap_clear (&insn_bitmap
);
6041 bitmap_clear (&removed_optional_reload_pseudos
);
6045 /* Entry function for undoing inheritance/split transformation. Return true
6046 if we did any RTL change in this pass. */
6048 lra_undo_inheritance (void)
6051 int restore_regno
, hard_regno
;
6052 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6053 bitmap_head remove_pseudos
;
6057 lra_undo_inheritance_iter
++;
6058 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6060 if (lra_dump_file
!= NULL
)
6061 fprintf (lra_dump_file
,
6062 "\n********** Undoing inheritance #%d: **********\n\n",
6063 lra_undo_inheritance_iter
);
6064 bitmap_initialize (&remove_pseudos
, ®_obstack
);
6065 n_inherit
= n_all_inherit
= 0;
6066 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6067 if (lra_reg_info
[regno
].restore_regno
>= 0)
6070 if (reg_renumber
[regno
] < 0
6071 /* If the original pseudo changed its allocation, just
6072 removing inheritance is dangerous as for changing
6073 allocation we used shorter live-ranges. */
6074 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
6075 bitmap_set_bit (&remove_pseudos
, regno
);
6079 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6080 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6081 n_inherit
, n_all_inherit
,
6082 (double) n_inherit
/ n_all_inherit
* 100);
6083 n_split
= n_all_split
= 0;
6084 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6085 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
6088 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6089 ? reg_renumber
[restore_regno
] : restore_regno
);
6090 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6091 bitmap_set_bit (&remove_pseudos
, regno
);
6095 if (lra_dump_file
!= NULL
)
6096 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6097 regno
, restore_regno
);
6100 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6101 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6102 n_split
, n_all_split
,
6103 (double) n_split
/ n_all_split
* 100);
6104 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6105 bitmap_clear (&remove_pseudos
);
6106 /* Clear restore_regnos. */
6107 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6108 lra_reg_info
[regno
].restore_regno
= -1;
6109 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6110 lra_reg_info
[regno
].restore_regno
= -1;
6111 change_p
= undo_optional_reloads () || change_p
;