1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
124 #include "hash-set.h"
126 #include "machmode.h"
128 #include "function.h"
132 #include "dominance.h"
135 #include "basic-block.h"
140 #include "rtl-error.h"
143 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
144 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
146 static int bb_reload_num
;
148 /* The current insn being processed and corresponding its single set
149 (NULL otherwise), its data (basic block, the insn data, the insn
150 static data, and the mode of each operand). */
151 static rtx_insn
*curr_insn
;
152 static rtx curr_insn_set
;
153 static basic_block curr_bb
;
154 static lra_insn_recog_data_t curr_id
;
155 static struct lra_static_insn_data
*curr_static_id
;
156 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
160 /* Start numbers for new registers and insns at the current constraints
162 static int new_regno_start
;
163 static int new_insn_uid_start
;
165 /* If LOC is nonnull, strip any outer subreg from it. */
167 strip_subreg (rtx
*loc
)
169 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
172 /* Return hard regno of REGNO or if it is was not assigned to a hard
173 register, use a hard register from its allocno class. */
175 get_try_hard_regno (int regno
)
178 enum reg_class rclass
;
180 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
181 hard_regno
= lra_get_regno_hard_regno (regno
);
184 rclass
= lra_get_allocno_class (regno
);
185 if (rclass
== NO_REGS
)
187 return ira_class_hard_regs
[rclass
][0];
190 /* Return final hard regno (plus offset) which will be after
191 elimination. We do this for matching constraints because the final
192 hard regno could have a different class. */
194 get_final_hard_regno (int hard_regno
, int offset
)
198 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
199 return hard_regno
+ offset
;
202 /* Return hard regno of X after removing subreg and making
203 elimination. If X is not a register or subreg of register, return
204 -1. For pseudo use its assignment. */
206 get_hard_regno (rtx x
)
209 int offset
, hard_regno
;
212 if (GET_CODE (x
) == SUBREG
)
213 reg
= SUBREG_REG (x
);
216 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
217 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
221 if (GET_CODE (x
) == SUBREG
)
222 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
223 SUBREG_BYTE (x
), GET_MODE (x
));
224 return get_final_hard_regno (hard_regno
, offset
);
227 /* If REGNO is a hard register or has been allocated a hard register,
228 return the class of that register. If REGNO is a reload pseudo
229 created by the current constraints pass, return its allocno class.
230 Return NO_REGS otherwise. */
231 static enum reg_class
232 get_reg_class (int regno
)
236 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
237 hard_regno
= lra_get_regno_hard_regno (regno
);
240 hard_regno
= get_final_hard_regno (hard_regno
, 0);
241 return REGNO_REG_CLASS (hard_regno
);
243 if (regno
>= new_regno_start
)
244 return lra_get_allocno_class (regno
);
248 /* Return true if REG satisfies (or will satisfy) reg class constraint
249 CL. Use elimination first if REG is a hard register. If REG is a
250 reload pseudo created by this constraints pass, assume that it will
251 be allocated a hard register from its allocno class, but allow that
252 class to be narrowed to CL if it is currently a superset of CL.
254 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
255 REGNO (reg), or NO_REGS if no change in its class was needed. */
257 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
259 enum reg_class rclass
, common_class
;
260 machine_mode reg_mode
;
261 int class_size
, hard_regno
, nregs
, i
, j
;
262 int regno
= REGNO (reg
);
264 if (new_class
!= NULL
)
265 *new_class
= NO_REGS
;
266 if (regno
< FIRST_PSEUDO_REGISTER
)
269 rtx
*final_loc
= &final_reg
;
271 lra_eliminate_reg_if_possible (final_loc
);
272 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
274 reg_mode
= GET_MODE (reg
);
275 rclass
= get_reg_class (regno
);
276 if (regno
< new_regno_start
277 /* Do not allow the constraints for reload instructions to
278 influence the classes of new pseudos. These reloads are
279 typically moves that have many alternatives, and restricting
280 reload pseudos for one alternative may lead to situations
281 where other reload pseudos are no longer allocatable. */
282 || (INSN_UID (curr_insn
) >= new_insn_uid_start
283 && curr_insn_set
!= NULL
284 && ((OBJECT_P (SET_SRC (curr_insn_set
))
285 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
286 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
287 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
288 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
289 /* When we don't know what class will be used finally for reload
290 pseudos, we use ALL_REGS. */
291 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
292 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
293 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
294 lra_no_alloc_regs
)));
297 common_class
= ira_reg_class_subset
[rclass
][cl
];
298 if (new_class
!= NULL
)
299 *new_class
= common_class
;
300 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
303 /* Check that there are enough allocatable regs. */
304 class_size
= ira_class_hard_regs_num
[common_class
];
305 for (i
= 0; i
< class_size
; i
++)
307 hard_regno
= ira_class_hard_regs
[common_class
][i
];
308 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
311 for (j
= 0; j
< nregs
; j
++)
312 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
313 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
323 /* Return true if REGNO satisfies a memory constraint. */
327 return get_reg_class (regno
) == NO_REGS
;
330 /* Return 1 if ADDR is a valid memory address for mode MODE in address
331 space AS, and check that each pseudo has the proper kind of hard
334 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
335 rtx addr
, addr_space_t as
)
337 #ifdef GO_IF_LEGITIMATE_ADDRESS
338 lra_assert (ADDR_SPACE_GENERIC_P (as
));
339 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
345 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
350 /* Temporarily eliminates registers in an address (for the lifetime of
352 class address_eliminator
{
354 address_eliminator (struct address_info
*ad
);
355 ~address_eliminator ();
358 struct address_info
*m_ad
;
366 address_eliminator::address_eliminator (struct address_info
*ad
)
368 m_base_loc (strip_subreg (ad
->base_term
)),
369 m_base_reg (NULL_RTX
),
370 m_index_loc (strip_subreg (ad
->index_term
)),
371 m_index_reg (NULL_RTX
)
373 if (m_base_loc
!= NULL
)
375 m_base_reg
= *m_base_loc
;
376 lra_eliminate_reg_if_possible (m_base_loc
);
377 if (m_ad
->base_term2
!= NULL
)
378 *m_ad
->base_term2
= *m_ad
->base_term
;
380 if (m_index_loc
!= NULL
)
382 m_index_reg
= *m_index_loc
;
383 lra_eliminate_reg_if_possible (m_index_loc
);
387 address_eliminator::~address_eliminator ()
389 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
391 *m_base_loc
= m_base_reg
;
392 if (m_ad
->base_term2
!= NULL
)
393 *m_ad
->base_term2
= *m_ad
->base_term
;
395 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
396 *m_index_loc
= m_index_reg
;
399 /* Return true if the eliminated form of AD is a legitimate target address. */
401 valid_address_p (struct address_info
*ad
)
403 address_eliminator
eliminator (ad
);
404 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
407 /* Return true if the eliminated form of memory reference OP satisfies
408 extra memory constraint CONSTRAINT. */
410 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
412 struct address_info ad
;
414 decompose_mem_address (&ad
, op
);
415 address_eliminator
eliminator (&ad
);
416 return constraint_satisfied_p (op
, constraint
);
419 /* Return true if the eliminated form of address AD satisfies extra
420 address constraint CONSTRAINT. */
422 satisfies_address_constraint_p (struct address_info
*ad
,
423 enum constraint_num constraint
)
425 address_eliminator
eliminator (ad
);
426 return constraint_satisfied_p (*ad
->outer
, constraint
);
429 /* Return true if the eliminated form of address OP satisfies extra
430 address constraint CONSTRAINT. */
432 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
434 struct address_info ad
;
436 decompose_lea_address (&ad
, &op
);
437 return satisfies_address_constraint_p (&ad
, constraint
);
440 /* Initiate equivalences for LRA. As we keep original equivalences
441 before any elimination, we need to make copies otherwise any change
442 in insns might change the equivalences. */
444 lra_init_equiv (void)
446 ira_expand_reg_equiv ();
447 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
451 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
452 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
453 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
454 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
458 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
460 /* Update equivalence for REGNO. We need to this as the equivalence
461 might contain other pseudos which are changed by their
464 update_equiv (int regno
)
468 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
469 ira_reg_equiv
[regno
].memory
470 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
472 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
473 ira_reg_equiv
[regno
].invariant
474 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
478 /* If we have decided to substitute X with another value, return that
479 value, otherwise return X. */
486 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
487 || ! ira_reg_equiv
[regno
].defined_p
488 || ! ira_reg_equiv
[regno
].profitable_p
489 || lra_get_regno_hard_regno (regno
) >= 0)
491 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
493 if (targetm
.cannot_substitute_mem_equiv_p (res
))
497 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
499 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
504 /* If we have decided to substitute X with the equivalent value,
505 return that value after elimination for INSN, otherwise return
508 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
510 rtx res
= get_equiv (x
);
512 if (x
== res
|| CONSTANT_P (res
))
514 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
515 0, false, false, true);
518 /* Set up curr_operand_mode. */
520 init_curr_operand_mode (void)
522 int nop
= curr_static_id
->n_operands
;
523 for (int i
= 0; i
< nop
; i
++)
525 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
526 if (mode
== VOIDmode
)
528 /* The .md mode for address operands is the mode of the
529 addressed value rather than the mode of the address itself. */
530 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
533 mode
= curr_static_id
->operand
[i
].mode
;
535 curr_operand_mode
[i
] = mode
;
541 /* The page contains code to reuse input reloads. */
543 /* Structure describes input reload of the current insns. */
546 /* Reloaded value. */
548 /* Reload pseudo used. */
552 /* The number of elements in the following array. */
553 static int curr_insn_input_reloads_num
;
554 /* Array containing info about input reloads. It is used to find the
555 same input reload and reuse the reload pseudo in this case. */
556 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
558 /* Initiate data concerning reuse of input reloads for the current
561 init_curr_insn_input_reloads (void)
563 curr_insn_input_reloads_num
= 0;
566 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
567 created input reload pseudo (only if TYPE is not OP_OUT). Don't
568 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
569 wrapped up in SUBREG. The result pseudo is returned through
570 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
571 reused the already created input reload pseudo. Use TITLE to
572 describe new registers for debug purposes. */
574 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
575 enum reg_class rclass
, bool in_subreg_p
,
576 const char *title
, rtx
*result_reg
)
579 enum reg_class new_class
;
584 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
587 /* Prevent reuse value of expression with side effects,
588 e.g. volatile memory. */
589 if (! side_effects_p (original
))
590 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
591 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
592 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
594 rtx reg
= curr_insn_input_reloads
[i
].reg
;
596 /* If input is equal to original and both are VOIDmode,
597 GET_MODE (reg) might be still different from mode.
598 Ensure we don't return *result_reg with wrong mode. */
599 if (GET_MODE (reg
) != mode
)
603 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
605 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
606 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
610 if (lra_dump_file
!= NULL
)
612 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
613 dump_value_slim (lra_dump_file
, original
, 1);
615 if (new_class
!= lra_get_allocno_class (regno
))
616 lra_change_class (regno
, new_class
, ", change to", false);
617 if (lra_dump_file
!= NULL
)
618 fprintf (lra_dump_file
, "\n");
621 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
622 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
623 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
624 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
630 /* The page contains code to extract memory address parts. */
632 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
634 ok_for_index_p_nonstrict (rtx reg
)
636 unsigned regno
= REGNO (reg
);
638 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
641 /* A version of regno_ok_for_base_p for use here, when all pseudos
642 should count as OK. Arguments as for regno_ok_for_base_p. */
644 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
645 enum rtx_code outer_code
, enum rtx_code index_code
)
647 unsigned regno
= REGNO (reg
);
649 if (regno
>= FIRST_PSEUDO_REGISTER
)
651 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
656 /* The page contains major code to choose the current insn alternative
657 and generate reloads for it. */
659 /* Return the offset from REGNO of the least significant register
662 This function is used to tell whether two registers satisfy
663 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
665 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
666 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
668 lra_constraint_offset (int regno
, machine_mode mode
)
670 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
671 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
672 && SCALAR_INT_MODE_P (mode
))
673 return hard_regno_nregs
[regno
][mode
] - 1;
677 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
678 if they are the same hard reg, and has special hacks for
679 auto-increment and auto-decrement. This is specifically intended for
680 process_alt_operands to use in determining whether two operands
681 match. X is the operand whose number is the lower of the two.
683 It is supposed that X is the output operand and Y is the input
684 operand. Y_HARD_REGNO is the final hard regno of register Y or
685 register in subreg Y as we know it now. Otherwise, it is a
688 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
691 RTX_CODE code
= GET_CODE (x
);
696 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
697 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
701 i
= get_hard_regno (x
);
705 if ((j
= y_hard_regno
) < 0)
708 i
+= lra_constraint_offset (i
, GET_MODE (x
));
709 j
+= lra_constraint_offset (j
, GET_MODE (y
));
714 /* If two operands must match, because they are really a single
715 operand of an assembler insn, then two post-increments are invalid
716 because the assembler insn would increment only once. On the
717 other hand, a post-increment matches ordinary indexing if the
718 post-increment is the output operand. */
719 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
720 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
722 /* Two pre-increments are invalid because the assembler insn would
723 increment only once. On the other hand, a pre-increment matches
724 ordinary indexing if the pre-increment is the input operand. */
725 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
726 || GET_CODE (y
) == PRE_MODIFY
)
727 return operands_match_p (x
, XEXP (y
, 0), -1);
731 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
732 && x
== SUBREG_REG (y
))
734 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
735 && SUBREG_REG (x
) == y
)
738 /* Now we have disposed of all the cases in which different rtx
740 if (code
!= GET_CODE (y
))
743 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
744 if (GET_MODE (x
) != GET_MODE (y
))
753 return LABEL_REF_LABEL (x
) == LABEL_REF_LABEL (y
);
755 return XSTR (x
, 0) == XSTR (y
, 0);
761 /* Compare the elements. If any pair of corresponding elements fail
762 to match, return false for the whole things. */
764 fmt
= GET_RTX_FORMAT (code
);
765 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
771 if (XWINT (x
, i
) != XWINT (y
, i
))
776 if (XINT (x
, i
) != XINT (y
, i
))
781 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
790 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
792 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
794 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
800 /* It is believed that rtx's at this level will never
801 contain anything but integers and other rtx's, except for
802 within LABEL_REFs and SYMBOL_REFs. */
810 /* True if X is a constant that can be forced into the constant pool.
811 MODE is the mode of the operand, or VOIDmode if not known. */
812 #define CONST_POOL_OK_P(MODE, X) \
813 ((MODE) != VOIDmode \
815 && GET_CODE (X) != HIGH \
816 && !targetm.cannot_force_const_mem (MODE, X))
818 /* True if C is a non-empty register class that has too few registers
819 to be safely used as a reload target class. */
820 #define SMALL_REGISTER_CLASS_P(C) \
821 (ira_class_hard_regs_num [(C)] == 1 \
822 || (ira_class_hard_regs_num [(C)] >= 1 \
823 && targetm.class_likely_spilled_p (C)))
825 /* If REG is a reload pseudo, try to make its class satisfying CL. */
827 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
829 enum reg_class rclass
;
831 /* Do not make more accurate class from reloads generated. They are
832 mostly moves with a lot of constraints. Making more accurate
833 class may results in very narrow class and impossibility of find
834 registers for several reloads of one insn. */
835 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
837 if (GET_CODE (reg
) == SUBREG
)
838 reg
= SUBREG_REG (reg
);
839 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
841 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
842 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
845 /* Generate reloads for matching OUT and INS (array of input operand
846 numbers with end marker -1) with reg class GOAL_CLASS. Add input
847 and output reloads correspondingly to the lists *BEFORE and *AFTER.
848 OUT might be negative. In this case we generate input reloads for
849 matched input operands INS. */
851 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
852 rtx_insn
**before
, rtx_insn
**after
)
855 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
856 machine_mode inmode
, outmode
;
857 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
858 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
860 inmode
= curr_operand_mode
[ins
[0]];
861 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
862 push_to_sequence (*before
);
863 if (inmode
!= outmode
)
865 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
868 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
870 if (SCALAR_INT_MODE_P (inmode
))
871 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
873 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
874 LRA_SUBREG_P (new_out_reg
) = 1;
875 /* If the input reg is dying here, we can use the same hard
876 register for REG and IN_RTX. We do it only for original
877 pseudos as reload pseudos can die although original
878 pseudos still live where reload pseudos dies. */
879 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
880 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
881 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
886 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
888 if (SCALAR_INT_MODE_P (outmode
))
889 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
891 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
892 /* NEW_IN_REG is non-paradoxical subreg. We don't want
893 NEW_OUT_REG living above. We add clobber clause for
894 this. This is just a temporary clobber. We can remove
895 it at the end of LRA work. */
896 clobber
= emit_clobber (new_out_reg
);
897 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
898 LRA_SUBREG_P (new_in_reg
) = 1;
899 if (GET_CODE (in_rtx
) == SUBREG
)
901 rtx subreg_reg
= SUBREG_REG (in_rtx
);
903 /* If SUBREG_REG is dying here and sub-registers IN_RTX
904 and NEW_IN_REG are similar, we can use the same hard
905 register for REG and SUBREG_REG. */
906 if (REG_P (subreg_reg
)
907 && (int) REGNO (subreg_reg
) < lra_new_regno_start
908 && GET_MODE (subreg_reg
) == outmode
909 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
910 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
911 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
917 /* Pseudos have values -- see comments for lra_reg_info.
918 Different pseudos with the same value do not conflict even if
919 they live in the same place. When we create a pseudo we
920 assign value of original pseudo (if any) from which we
921 created the new pseudo. If we create the pseudo from the
922 input pseudo, the new pseudo will no conflict with the input
923 pseudo which is wrong when the input pseudo lives after the
924 insn and as the new pseudo value is changed by the insn
925 output. Therefore we create the new pseudo from the output.
927 We cannot reuse the current output register because we might
928 have a situation like "a <- a op b", where the constraints
929 force the second input operand ("b") to match the output
930 operand ("a"). "b" must then be copied into a new register
931 so that it doesn't clobber the current value of "a". */
933 new_in_reg
= new_out_reg
934 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
937 /* In operand can be got from transformations before processing insn
938 constraints. One example of such transformations is subreg
939 reloading (see function simplify_operand_subreg). The new
940 pseudos created by the transformations might have inaccurate
941 class (ALL_REGS) and we should make their classes more
943 narrow_reload_pseudo_class (in_rtx
, goal_class
);
944 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
945 *before
= get_insns ();
947 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
950 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
951 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
952 *curr_id
->operand_loc
[in
] = new_in_reg
;
954 lra_update_dups (curr_id
, ins
);
957 /* See a comment for the input operand above. */
958 narrow_reload_pseudo_class (out_rtx
, goal_class
);
959 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
962 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
964 *after
= get_insns ();
967 *curr_id
->operand_loc
[out
] = new_out_reg
;
968 lra_update_dup (curr_id
, out
);
971 /* Return register class which is union of all reg classes in insn
972 constraint alternative string starting with P. */
973 static enum reg_class
974 reg_class_from_constraints (const char *p
)
977 enum reg_class op_class
= NO_REGS
;
980 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
987 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
991 enum constraint_num cn
= lookup_constraint (p
);
992 enum reg_class cl
= reg_class_for_constraint (cn
);
995 if (insn_extra_address_constraint (cn
))
997 = (reg_class_subunion
998 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1003 op_class
= reg_class_subunion
[op_class
][cl
];
1006 while ((p
+= len
), c
);
1010 /* If OP is a register, return the class of the register as per
1011 get_reg_class, otherwise return NO_REGS. */
1012 static inline enum reg_class
1013 get_op_class (rtx op
)
1015 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1018 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1019 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1020 SUBREG for VAL to make them equal. */
1022 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1024 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1026 /* Usually size of mem_pseudo is greater than val size but in
1027 rare cases it can be less as it can be defined by target
1028 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1031 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1032 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1034 LRA_SUBREG_P (val
) = 1;
1038 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1039 LRA_SUBREG_P (mem_pseudo
) = 1;
1042 return as_a
<rtx_insn
*> (to_p
1043 ? gen_move_insn (mem_pseudo
, val
)
1044 : gen_move_insn (val
, mem_pseudo
));
1047 /* Process a special case insn (register move), return true if we
1048 don't need to process it anymore. INSN should be a single set
1049 insn. Set up that RTL was changed through CHANGE_P and macro
1050 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1053 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1056 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, scratch_reg
;
1058 enum reg_class dclass
, sclass
, secondary_class
;
1059 machine_mode sreg_mode
;
1060 secondary_reload_info sri
;
1062 lra_assert (curr_insn_set
!= NULL_RTX
);
1063 dreg
= dest
= SET_DEST (curr_insn_set
);
1064 sreg
= src
= SET_SRC (curr_insn_set
);
1065 if (GET_CODE (dest
) == SUBREG
)
1066 dreg
= SUBREG_REG (dest
);
1067 if (GET_CODE (src
) == SUBREG
)
1068 sreg
= SUBREG_REG (src
);
1069 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1071 sclass
= dclass
= NO_REGS
;
1073 dclass
= get_reg_class (REGNO (dreg
));
1074 if (dclass
== ALL_REGS
)
1075 /* ALL_REGS is used for new pseudos created by transformations
1076 like reload of SUBREG_REG (see function
1077 simplify_operand_subreg). We don't know their class yet. We
1078 should figure out the class from processing the insn
1079 constraints not in this fast path function. Even if ALL_REGS
1080 were a right class for the pseudo, secondary_... hooks usually
1081 are not define for ALL_REGS. */
1083 sreg_mode
= GET_MODE (sreg
);
1086 sclass
= get_reg_class (REGNO (sreg
));
1087 if (sclass
== ALL_REGS
)
1088 /* See comments above. */
1090 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1092 #ifdef SECONDARY_MEMORY_NEEDED
1093 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1094 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1095 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1096 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1104 if (! REG_P (dreg
) || ! REG_P (sreg
))
1106 sri
.prev_sri
= NULL
;
1107 sri
.icode
= CODE_FOR_nothing
;
1109 secondary_class
= NO_REGS
;
1110 /* Set up hard register for a reload pseudo for hook
1111 secondary_reload because some targets just ignore unassigned
1112 pseudos in the hook. */
1113 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1115 dregno
= REGNO (dreg
);
1116 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1120 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1122 sregno
= REGNO (sreg
);
1123 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1127 if (sclass
!= NO_REGS
)
1129 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1130 (reg_class_t
) sclass
,
1131 GET_MODE (src
), &sri
);
1132 if (sclass
== NO_REGS
1133 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1134 && dclass
!= NO_REGS
))
1136 enum reg_class old_sclass
= secondary_class
;
1137 secondary_reload_info old_sri
= sri
;
1139 sri
.prev_sri
= NULL
;
1140 sri
.icode
= CODE_FOR_nothing
;
1143 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1144 (reg_class_t
) dclass
,
1146 /* Check the target hook consistency. */
1148 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1149 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1150 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1153 reg_renumber
[sregno
] = -1;
1155 reg_renumber
[dregno
] = -1;
1156 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1160 if (secondary_class
!= NO_REGS
)
1161 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1165 if (old_sreg
!= sreg
)
1166 sreg
= copy_rtx (sreg
);
1167 if (sri
.icode
== CODE_FOR_nothing
)
1168 lra_emit_move (new_reg
, sreg
);
1171 enum reg_class scratch_class
;
1173 scratch_class
= (reg_class_from_constraints
1174 (insn_data
[sri
.icode
].operand
[2].constraint
));
1175 scratch_reg
= (lra_create_new_reg_with_unique_value
1176 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1177 scratch_class
, "scratch"));
1178 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1179 sreg
, scratch_reg
));
1181 before
= get_insns ();
1183 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1184 if (new_reg
!= NULL_RTX
)
1186 if (GET_CODE (src
) == SUBREG
)
1187 SUBREG_REG (src
) = new_reg
;
1189 SET_SRC (curr_insn_set
) = new_reg
;
1193 if (lra_dump_file
!= NULL
)
1195 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1196 dump_insn_slim (lra_dump_file
, curr_insn
);
1198 lra_set_insn_deleted (curr_insn
);
1204 /* The following data describe the result of process_alt_operands.
1205 The data are used in curr_insn_transform to generate reloads. */
1207 /* The chosen reg classes which should be used for the corresponding
1209 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1210 /* True if the operand should be the same as another operand and that
1211 other operand does not need a reload. */
1212 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1213 /* True if the operand does not need a reload. */
1214 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1215 /* True if the operand can be offsetable memory. */
1216 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1217 /* The number of an operand to which given operand can be matched to. */
1218 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1219 /* The number of elements in the following array. */
1220 static int goal_alt_dont_inherit_ops_num
;
1221 /* Numbers of operands whose reload pseudos should not be inherited. */
1222 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1223 /* True if the insn commutative operands should be swapped. */
1224 static bool goal_alt_swapped
;
1225 /* The chosen insn alternative. */
1226 static int goal_alt_number
;
1228 /* The following five variables are used to choose the best insn
1229 alternative. They reflect final characteristics of the best
1232 /* Number of necessary reloads and overall cost reflecting the
1233 previous value and other unpleasantness of the best alternative. */
1234 static int best_losers
, best_overall
;
1235 /* Overall number hard registers used for reloads. For example, on
1236 some targets we need 2 general registers to reload DFmode and only
1237 one floating point register. */
1238 static int best_reload_nregs
;
1239 /* Overall number reflecting distances of previous reloading the same
1240 value. The distances are counted from the current BB start. It is
1241 used to improve inheritance chances. */
1242 static int best_reload_sum
;
1244 /* True if the current insn should have no correspondingly input or
1246 static bool no_input_reloads_p
, no_output_reloads_p
;
1248 /* True if we swapped the commutative operands in the current
1250 static int curr_swapped
;
1252 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1253 register of class CL. Add any input reloads to list BEFORE. AFTER
1254 is nonnull if *LOC is an automodified value; handle that case by
1255 adding the required output reloads to list AFTER. Return true if
1256 the RTL was changed.
1258 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1259 register. Return false if the address register is correct. */
1261 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1265 enum reg_class rclass
, new_class
;
1269 bool subreg_p
, before_p
= false;
1271 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1273 loc
= &SUBREG_REG (*loc
);
1275 mode
= GET_MODE (reg
);
1280 /* Always reload memory in an address even if the target supports
1282 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1287 regno
= REGNO (reg
);
1288 rclass
= get_reg_class (regno
);
1290 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1292 if (lra_dump_file
!= NULL
)
1294 fprintf (lra_dump_file
,
1295 "Changing pseudo %d in address of insn %u on equiv ",
1296 REGNO (reg
), INSN_UID (curr_insn
));
1297 dump_value_slim (lra_dump_file
, *loc
, 1);
1298 fprintf (lra_dump_file
, "\n");
1300 *loc
= copy_rtx (*loc
);
1302 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1307 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1308 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1311 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1315 lra_change_class (regno
, new_class
, " Change to", true);
1323 push_to_sequence (*before
);
1324 lra_emit_move (new_reg
, reg
);
1325 *before
= get_insns ();
1332 lra_emit_move (reg
, new_reg
);
1334 *after
= get_insns ();
1340 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1341 the insn to be inserted before curr insn. AFTER returns the
1342 the insn to be inserted after curr insn. ORIGREG and NEWREG
1343 are the original reg and new reg for reload. */
1345 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1350 push_to_sequence (*before
);
1351 lra_emit_move (newreg
, origreg
);
1352 *before
= get_insns ();
1358 lra_emit_move (origreg
, newreg
);
1360 *after
= get_insns ();
1365 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1367 /* Make reloads for subreg in operand NOP with internal subreg mode
1368 REG_MODE, add new reloads for further processing. Return true if
1369 any reload was generated. */
1371 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1374 rtx_insn
*before
, *after
;
1377 rtx operand
= *curr_id
->operand_loc
[nop
];
1378 enum reg_class regclass
;
1381 before
= after
= NULL
;
1383 if (GET_CODE (operand
) != SUBREG
)
1386 mode
= GET_MODE (operand
);
1387 reg
= SUBREG_REG (operand
);
1388 type
= curr_static_id
->operand
[nop
].type
;
1389 /* If we change address for paradoxical subreg of memory, the
1390 address might violate the necessary alignment or the access might
1391 be slow. So take this into consideration. We should not worry
1392 about access beyond allocated memory for paradoxical memory
1393 subregs as we don't substitute such equiv memory (see processing
1394 equivalences in function lra_constraints) and because for spilled
1395 pseudos we allocate stack memory enough for the biggest
1396 corresponding paradoxical subreg. */
1398 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1399 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1401 rtx subst
, old
= *curr_id
->operand_loc
[nop
];
1403 alter_subreg (curr_id
->operand_loc
[nop
], false);
1404 subst
= *curr_id
->operand_loc
[nop
];
1405 lra_assert (MEM_P (subst
));
1406 if (! valid_address_p (GET_MODE (reg
), XEXP (reg
, 0),
1407 MEM_ADDR_SPACE (reg
))
1408 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1409 MEM_ADDR_SPACE (subst
)))
1411 /* If the address was valid and became invalid, prefer to reload
1412 the memory. Typical case is when the index scale should
1413 correspond the memory. */
1414 *curr_id
->operand_loc
[nop
] = old
;
1416 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1418 alter_subreg (curr_id
->operand_loc
[nop
], false);
1421 /* Put constant into memory when we have mixed modes. It generates
1422 a better code in most cases as it does not need a secondary
1423 reload memory. It also prevents LRA looping when LRA is using
1424 secondary reload memory again and again. */
1425 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1426 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1428 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1429 alter_subreg (curr_id
->operand_loc
[nop
], false);
1432 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1433 if there may be a problem accessing OPERAND in the outer
1436 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1437 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1438 /* Don't reload paradoxical subregs because we could be looping
1439 having repeatedly final regno out of hard regs range. */
1440 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1441 >= hard_regno_nregs
[hard_regno
][mode
])
1442 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1443 SUBREG_BYTE (operand
), mode
) < 0
1444 /* Don't reload subreg for matching reload. It is actually
1445 valid subreg in LRA. */
1446 && ! LRA_SUBREG_P (operand
))
1447 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1449 enum reg_class rclass
;
1452 /* There is a big probability that we will get the same class
1453 for the new pseudo and we will get the same insn which
1454 means infinite looping. So spill the new pseudo. */
1457 /* The class will be defined later in curr_insn_transform. */
1459 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1461 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1462 rclass
, TRUE
, "subreg reg", &new_reg
))
1464 bool insert_before
, insert_after
;
1465 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1467 insert_before
= (type
!= OP_OUT
1468 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1469 insert_after
= (type
!= OP_IN
);
1470 insert_move_for_subreg (insert_before
? &before
: NULL
,
1471 insert_after
? &after
: NULL
,
1474 SUBREG_REG (operand
) = new_reg
;
1475 lra_process_new_insns (curr_insn
, before
, after
,
1476 "Inserting subreg reload");
1479 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1480 IRA allocates hardreg to the inner pseudo reg according to its mode
1481 instead of the outermode, so the size of the hardreg may not be enough
1482 to contain the outermode operand, in that case we may need to insert
1483 reload for the reg. For the following two types of paradoxical subreg,
1484 we need to insert reload:
1485 1. If the op_type is OP_IN, and the hardreg could not be paired with
1486 other hardreg to contain the outermode operand
1487 (checked by in_hard_reg_set_p), we need to insert the reload.
1488 2. If the op_type is OP_OUT or OP_INOUT.
1490 Here is a paradoxical subreg example showing how the reload is generated:
1492 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1493 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1495 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1496 here, if reg107 is assigned to hardreg R15, because R15 is the last
1497 hardreg, compiler cannot find another hardreg to pair with R15 to
1498 contain TImode data. So we insert a TImode reload reg180 for it.
1499 After reload is inserted:
1501 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1502 (reg:DI 107 [ __comp ])) -1
1503 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1504 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1506 Two reload hard registers will be allocated to reg180 to save TImode data
1508 else if (REG_P (reg
)
1509 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1510 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1511 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1512 < hard_regno_nregs
[hard_regno
][mode
])
1513 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1515 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1518 /* The class will be defined later in curr_insn_transform. */
1519 enum reg_class rclass
1520 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1522 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1523 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1526 bool insert_before
, insert_after
;
1528 PUT_MODE (new_reg
, mode
);
1529 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1530 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1532 insert_before
= (type
!= OP_OUT
);
1533 insert_after
= (type
!= OP_IN
);
1534 insert_move_for_subreg (insert_before
? &before
: NULL
,
1535 insert_after
? &after
: NULL
,
1538 SUBREG_REG (operand
) = new_reg
;
1539 lra_process_new_insns (curr_insn
, before
, after
,
1540 "Inserting paradoxical subreg reload");
1546 /* Return TRUE if X refers for a hard register from SET. */
1548 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1550 int i
, j
, x_hard_regno
;
1557 code
= GET_CODE (x
);
1558 mode
= GET_MODE (x
);
1562 code
= GET_CODE (x
);
1563 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1564 mode
= GET_MODE (x
);
1569 x_hard_regno
= get_hard_regno (x
);
1570 return (x_hard_regno
>= 0
1571 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1575 struct address_info ad
;
1577 decompose_mem_address (&ad
, x
);
1578 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1580 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1583 fmt
= GET_RTX_FORMAT (code
);
1584 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1588 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1591 else if (fmt
[i
] == 'E')
1593 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1594 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1601 /* Return true if OP is a spilled pseudo. */
1603 spilled_pseudo_p (rtx op
)
1606 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1609 /* Return true if X is a general constant. */
1611 general_constant_p (rtx x
)
1613 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1617 reg_in_class_p (rtx reg
, enum reg_class cl
)
1620 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1621 return in_class_p (reg
, cl
, NULL
);
1624 /* Major function to choose the current insn alternative and what
1625 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1626 negative we should consider only this alternative. Return false if
1627 we can not choose the alternative or find how to reload the
1630 process_alt_operands (int only_alternative
)
1633 int nop
, overall
, nalt
;
1634 int n_alternatives
= curr_static_id
->n_alternatives
;
1635 int n_operands
= curr_static_id
->n_operands
;
1636 /* LOSERS counts the operands that don't fit this alternative and
1637 would require loading. */
1639 /* REJECT is a count of how undesirable this alternative says it is
1640 if any reloading is required. If the alternative matches exactly
1641 then REJECT is ignored, but otherwise it gets this much counted
1642 against it in addition to the reloading needed. */
1644 /* The number of elements in the following array. */
1645 int early_clobbered_regs_num
;
1646 /* Numbers of operands which are early clobber registers. */
1647 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1648 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1649 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1650 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1651 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1652 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1653 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1654 /* The number of elements in the following array. */
1655 int curr_alt_dont_inherit_ops_num
;
1656 /* Numbers of operands whose reload pseudos should not be inherited. */
1657 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1659 /* The register when the operand is a subreg of register, otherwise the
1661 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1662 /* The register if the operand is a register or subreg of register,
1664 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1665 int hard_regno
[MAX_RECOG_OPERANDS
];
1666 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1667 int reload_nregs
, reload_sum
;
1671 /* Calculate some data common for all alternatives to speed up the
1673 for (nop
= 0; nop
< n_operands
; nop
++)
1677 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1678 /* The real hard regno of the operand after the allocation. */
1679 hard_regno
[nop
] = get_hard_regno (op
);
1681 operand_reg
[nop
] = reg
= op
;
1682 biggest_mode
[nop
] = GET_MODE (op
);
1683 if (GET_CODE (op
) == SUBREG
)
1685 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1686 if (GET_MODE_SIZE (biggest_mode
[nop
])
1687 < GET_MODE_SIZE (GET_MODE (reg
)))
1688 biggest_mode
[nop
] = GET_MODE (reg
);
1691 operand_reg
[nop
] = NULL_RTX
;
1692 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1693 || ((int) REGNO (reg
)
1694 == lra_get_elimination_hard_regno (REGNO (reg
))))
1695 no_subreg_reg_operand
[nop
] = reg
;
1697 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1698 /* Just use natural mode for elimination result. It should
1699 be enough for extra constraints hooks. */
1700 = regno_reg_rtx
[hard_regno
[nop
]];
1703 /* The constraints are made of several alternatives. Each operand's
1704 constraint looks like foo,bar,... with commas separating the
1705 alternatives. The first alternatives for all operands go
1706 together, the second alternatives go together, etc.
1708 First loop over alternatives. */
1709 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1710 if (only_alternative
>= 0)
1711 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1713 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1715 /* Loop over operands for one constraint alternative. */
1716 if (!TEST_BIT (preferred
, nalt
))
1719 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1720 for (nop
= 0; nop
< n_operands
; nop
++)
1722 int inc
= (curr_static_id
1723 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1724 if (lra_dump_file
!= NULL
&& inc
!= 0)
1725 fprintf (lra_dump_file
,
1726 " Staticly defined alt reject+=%d\n", inc
);
1729 early_clobbered_regs_num
= 0;
1731 for (nop
= 0; nop
< n_operands
; nop
++)
1735 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1736 bool win
, did_match
, offmemok
, early_clobber_p
;
1737 /* false => this operand can be reloaded somehow for this
1740 /* true => this operand can be reloaded if the alternative
1743 /* True if a constant forced into memory would be OK for
1746 enum reg_class this_alternative
, this_costly_alternative
;
1747 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1748 bool this_alternative_match_win
, this_alternative_win
;
1749 bool this_alternative_offmemok
;
1752 enum constraint_num cn
;
1754 opalt_num
= nalt
* n_operands
+ nop
;
1755 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1757 /* Fast track for no constraints at all. */
1758 curr_alt
[nop
] = NO_REGS
;
1759 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1760 curr_alt_win
[nop
] = true;
1761 curr_alt_match_win
[nop
] = false;
1762 curr_alt_offmemok
[nop
] = false;
1763 curr_alt_matches
[nop
] = -1;
1767 op
= no_subreg_reg_operand
[nop
];
1768 mode
= curr_operand_mode
[nop
];
1770 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1773 early_clobber_p
= false;
1774 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1776 this_costly_alternative
= this_alternative
= NO_REGS
;
1777 /* We update set of possible hard regs besides its class
1778 because reg class might be inaccurate. For example,
1779 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1780 is translated in HI_REGS because classes are merged by
1781 pairs and there is no accurate intermediate class. */
1782 CLEAR_HARD_REG_SET (this_alternative_set
);
1783 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1784 this_alternative_win
= false;
1785 this_alternative_match_win
= false;
1786 this_alternative_offmemok
= false;
1787 this_alternative_matches
= -1;
1789 /* An empty constraint should be excluded by the fast
1791 lra_assert (*p
!= 0 && *p
!= ',');
1793 /* Scan this alternative's specs for this operand; set WIN
1794 if the operand fits any letter in this alternative.
1795 Otherwise, clear BADOP if this operand could fit some
1796 letter after reloads, or set WINREG if this operand could
1797 fit after reloads provided the constraint allows some
1802 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1812 early_clobber_p
= true;
1816 /* Ignore rest of this alternative. */
1820 case '0': case '1': case '2': case '3': case '4':
1821 case '5': case '6': case '7': case '8': case '9':
1826 m
= strtoul (p
, &end
, 10);
1829 lra_assert (nop
> m
);
1831 this_alternative_matches
= m
;
1832 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1833 /* We are supposed to match a previous operand.
1834 If we do, we win if that one did. If we do
1835 not, count both of the operands as losers.
1836 (This is too conservative, since most of the
1837 time only a single reload insn will be needed
1838 to make the two operands win. As a result,
1839 this alternative may be rejected when it is
1840 actually desirable.) */
1842 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1843 *curr_id
->operand_loc
[m
], m_hregno
))
1845 /* We should reject matching of an early
1846 clobber operand if the matching operand is
1847 not dying in the insn. */
1848 if (! curr_static_id
->operand
[m
].early_clobber
1849 || operand_reg
[nop
] == NULL_RTX
1850 || (find_regno_note (curr_insn
, REG_DEAD
,
1852 || REGNO (op
) == REGNO (operand_reg
[m
])))
1857 /* If we are matching a non-offsettable
1858 address where an offsettable address was
1859 expected, then we must reject this
1860 combination, because we can't reload
1862 if (curr_alt_offmemok
[m
]
1863 && MEM_P (*curr_id
->operand_loc
[m
])
1864 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1869 /* Operands don't match. Both operands must
1870 allow a reload register, otherwise we
1871 cannot make them match. */
1872 if (curr_alt
[m
] == NO_REGS
)
1874 /* Retroactively mark the operand we had to
1875 match as a loser, if it wasn't already and
1876 it wasn't matched to a register constraint
1877 (e.g it might be matched by memory). */
1879 && (operand_reg
[m
] == NULL_RTX
1880 || hard_regno
[m
] < 0))
1884 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1885 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1888 /* Prefer matching earlyclobber alternative as
1889 it results in less hard regs required for
1890 the insn than a non-matching earlyclobber
1892 if (curr_static_id
->operand
[m
].early_clobber
)
1894 if (lra_dump_file
!= NULL
)
1897 " %d Matching earlyclobber alt:"
1902 /* Otherwise we prefer no matching
1903 alternatives because it gives more freedom
1905 else if (operand_reg
[nop
] == NULL_RTX
1906 || (find_regno_note (curr_insn
, REG_DEAD
,
1907 REGNO (operand_reg
[nop
]))
1910 if (lra_dump_file
!= NULL
)
1913 " %d Matching alt: reject+=2\n",
1918 /* If we have to reload this operand and some
1919 previous operand also had to match the same
1920 thing as this operand, we don't know how to do
1922 if (!match_p
|| !curr_alt_win
[m
])
1924 for (i
= 0; i
< nop
; i
++)
1925 if (curr_alt_matches
[i
] == m
)
1933 /* This can be fixed with reloads if the operand
1934 we are supposed to match can be fixed with
1937 this_alternative
= curr_alt
[m
];
1938 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1939 winreg
= this_alternative
!= NO_REGS
;
1945 || general_constant_p (op
)
1946 || spilled_pseudo_p (op
))
1952 cn
= lookup_constraint (p
);
1953 switch (get_constraint_type (cn
))
1956 cl
= reg_class_for_constraint (cn
);
1962 if (CONST_INT_P (op
)
1963 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1969 && satisfies_memory_constraint_p (op
, cn
))
1971 else if (spilled_pseudo_p (op
))
1974 /* If we didn't already win, we can reload constants
1975 via force_const_mem or put the pseudo value into
1976 memory, or make other memory by reloading the
1977 address like for 'o'. */
1978 if (CONST_POOL_OK_P (mode
, op
)
1979 || MEM_P (op
) || REG_P (op
))
1986 /* If we didn't already win, we can reload the address
1987 into a base register. */
1988 if (satisfies_address_constraint_p (op
, cn
))
1990 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1996 if (constraint_satisfied_p (op
, cn
))
2003 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2004 IOR_HARD_REG_SET (this_alternative_set
,
2005 reg_class_contents
[cl
]);
2008 this_costly_alternative
2009 = reg_class_subunion
[this_costly_alternative
][cl
];
2010 IOR_HARD_REG_SET (this_costly_alternative_set
,
2011 reg_class_contents
[cl
]);
2013 if (mode
== BLKmode
)
2018 if (hard_regno
[nop
] >= 0
2019 && in_hard_reg_set_p (this_alternative_set
,
2020 mode
, hard_regno
[nop
]))
2022 else if (hard_regno
[nop
] < 0
2023 && in_class_p (op
, this_alternative
, NULL
))
2028 if (c
!= ' ' && c
!= '\t')
2029 costly_p
= c
== '*';
2031 while ((p
+= len
), c
);
2033 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2034 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2035 /* Record which operands fit this alternative. */
2038 this_alternative_win
= true;
2039 if (operand_reg
[nop
] != NULL_RTX
)
2041 if (hard_regno
[nop
] >= 0)
2043 if (in_hard_reg_set_p (this_costly_alternative_set
,
2044 mode
, hard_regno
[nop
]))
2046 if (lra_dump_file
!= NULL
)
2047 fprintf (lra_dump_file
,
2048 " %d Costly set: reject++\n",
2055 /* Prefer won reg to spilled pseudo under other
2056 equal conditions for possibe inheritance. */
2059 if (lra_dump_file
!= NULL
)
2062 " %d Non pseudo reload: reject++\n",
2066 if (in_class_p (operand_reg
[nop
],
2067 this_costly_alternative
, NULL
))
2069 if (lra_dump_file
!= NULL
)
2072 " %d Non pseudo costly reload:"
2078 /* We simulate the behaviour of old reload here.
2079 Although scratches need hard registers and it
2080 might result in spilling other pseudos, no reload
2081 insns are generated for the scratches. So it
2082 might cost something but probably less than old
2083 reload pass believes. */
2086 if (lra_dump_file
!= NULL
)
2087 fprintf (lra_dump_file
,
2088 " %d Scratch win: reject+=2\n",
2095 this_alternative_match_win
= true;
2098 int const_to_mem
= 0;
2101 /* Never do output reload of stack pointer. It makes
2102 impossible to do elimination when SP is changed in
2104 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2105 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2108 /* If this alternative asks for a specific reg class, see if there
2109 is at least one allocatable register in that class. */
2111 = (this_alternative
== NO_REGS
2112 || (hard_reg_set_subset_p
2113 (reg_class_contents
[this_alternative
],
2114 lra_no_alloc_regs
)));
2116 /* For asms, verify that the class for this alternative is possible
2117 for the mode that is specified. */
2118 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2121 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2122 if (HARD_REGNO_MODE_OK (i
, mode
)
2123 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2126 if (i
== FIRST_PSEUDO_REGISTER
)
2130 /* If this operand accepts a register, and if the
2131 register class has at least one allocatable register,
2132 then this operand can be reloaded. */
2133 if (winreg
&& !no_regs_p
)
2138 if (lra_dump_file
!= NULL
)
2139 fprintf (lra_dump_file
,
2140 " alt=%d: Bad operand -- refuse\n",
2145 /* If not assigned pseudo has a class which a subset of
2146 required reg class, it is a less costly alternative
2147 as the pseudo still can get a hard reg of necessary
2149 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2150 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2151 && ira_class_subset_p
[this_alternative
][cl
])
2153 if (lra_dump_file
!= NULL
)
2156 " %d Super set class reg: reject-=3\n", nop
);
2160 this_alternative_offmemok
= offmemok
;
2161 if (this_costly_alternative
!= NO_REGS
)
2163 if (lra_dump_file
!= NULL
)
2164 fprintf (lra_dump_file
,
2165 " %d Costly loser: reject++\n", nop
);
2168 /* If the operand is dying, has a matching constraint,
2169 and satisfies constraints of the matched operand
2170 which failed to satisfy the own constraints, most probably
2171 the reload for this operand will be gone. */
2172 if (this_alternative_matches
>= 0
2173 && !curr_alt_win
[this_alternative_matches
]
2175 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2176 && (hard_regno
[nop
] >= 0
2177 ? in_hard_reg_set_p (this_alternative_set
,
2178 mode
, hard_regno
[nop
])
2179 : in_class_p (op
, this_alternative
, NULL
)))
2181 if (lra_dump_file
!= NULL
)
2184 " %d Dying matched operand reload: reject++\n",
2190 /* Strict_low_part requires to reload the register
2191 not the sub-register. In this case we should
2192 check that a final reload hard reg can hold the
2194 if (curr_static_id
->operand
[nop
].strict_low
2196 && hard_regno
[nop
] < 0
2197 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2198 && ira_class_hard_regs_num
[this_alternative
] > 0
2199 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2200 [this_alternative
][0],
2202 (*curr_id
->operand_loc
[nop
])))
2204 if (lra_dump_file
!= NULL
)
2207 " alt=%d: Strict low subreg reload -- refuse\n",
2213 if (operand_reg
[nop
] != NULL_RTX
2214 /* Output operands and matched input operands are
2215 not inherited. The following conditions do not
2216 exactly describe the previous statement but they
2217 are pretty close. */
2218 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2219 && (this_alternative_matches
< 0
2220 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2222 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2226 /* The value of reload_sum has sense only if we
2227 process insns in their order. It happens only on
2228 the first constraints sub-pass when we do most of
2230 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2231 reload_sum
+= last_reload
- bb_reload_num
;
2233 /* If this is a constant that is reloaded into the
2234 desired class by copying it to memory first, count
2235 that as another reload. This is consistent with
2236 other code and is required to avoid choosing another
2237 alternative when the constant is moved into memory.
2238 Note that the test here is precisely the same as in
2239 the code below that calls force_const_mem. */
2240 if (CONST_POOL_OK_P (mode
, op
)
2241 && ((targetm
.preferred_reload_class
2242 (op
, this_alternative
) == NO_REGS
)
2243 || no_input_reloads_p
))
2250 /* Alternative loses if it requires a type of reload not
2251 permitted for this insn. We can always reload
2252 objects with a REG_UNUSED note. */
2253 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2254 && no_output_reloads_p
2255 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2256 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2257 && no_input_reloads_p
&& ! const_to_mem
)
2258 || (this_alternative_matches
>= 0
2259 && (no_input_reloads_p
2260 || (no_output_reloads_p
2261 && (curr_static_id
->operand
2262 [this_alternative_matches
].type
!= OP_IN
)
2263 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2264 no_subreg_reg_operand
2265 [this_alternative_matches
])))))
2267 if (lra_dump_file
!= NULL
)
2270 " alt=%d: No input/otput reload -- refuse\n",
2275 /* Alternative loses if it required class pseudo can not
2276 hold value of required mode. Such insns can be
2277 described by insn definitions with mode iterators. */
2278 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2279 && ! hard_reg_set_empty_p (this_alternative_set
)
2280 /* It is common practice for constraints to use a
2281 class which does not have actually enough regs to
2282 hold the value (e.g. x86 AREG for mode requiring
2283 more one general reg). Therefore we have 2
2284 conditions to check that the reload pseudo can
2285 not hold the mode value. */
2286 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2287 [this_alternative
][0],
2288 GET_MODE (*curr_id
->operand_loc
[nop
])))
2292 COPY_HARD_REG_SET (temp
, this_alternative_set
);
2293 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
2294 /* The above condition is not enough as the first
2295 reg in ira_class_hard_regs can be not aligned for
2296 multi-words mode values. */
2297 if (hard_reg_set_subset_p (temp
,
2298 ira_prohibited_class_mode_regs
2300 [GET_MODE (*curr_id
->operand_loc
[nop
])]))
2302 if (lra_dump_file
!= NULL
)
2305 " alt=%d: reload pseudo for op %d "
2306 " can not hold the mode value -- refuse\n",
2312 /* Check strong discouragement of reload of non-constant
2313 into class THIS_ALTERNATIVE. */
2314 if (! CONSTANT_P (op
) && ! no_regs_p
2315 && (targetm
.preferred_reload_class
2316 (op
, this_alternative
) == NO_REGS
2317 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2318 && (targetm
.preferred_output_reload_class
2319 (op
, this_alternative
) == NO_REGS
))))
2321 if (lra_dump_file
!= NULL
)
2322 fprintf (lra_dump_file
,
2323 " %d Non-prefered reload: reject+=%d\n",
2324 nop
, LRA_MAX_REJECT
);
2325 reject
+= LRA_MAX_REJECT
;
2328 if (! (MEM_P (op
) && offmemok
)
2329 && ! (const_to_mem
&& constmemok
))
2331 /* We prefer to reload pseudos over reloading other
2332 things, since such reloads may be able to be
2333 eliminated later. So bump REJECT in other cases.
2334 Don't do this in the case where we are forcing a
2335 constant into memory and it will then win since
2336 we don't want to have a different alternative
2338 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2340 if (lra_dump_file
!= NULL
)
2343 " %d Non-pseudo reload: reject+=2\n",
2350 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2352 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2354 if (lra_dump_file
!= NULL
)
2357 " %d Small class reload: reject+=%d\n",
2358 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2359 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2363 /* We are trying to spill pseudo into memory. It is
2364 usually more costly than moving to a hard register
2365 although it might takes the same number of
2367 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2369 if (lra_dump_file
!= NULL
)
2372 " %d Spill pseudo into memory: reject+=3\n",
2375 if (VECTOR_MODE_P (mode
))
2377 /* Spilling vectors into memory is usually more
2378 costly as they contain big values. */
2379 if (lra_dump_file
!= NULL
)
2382 " %d Spill vector pseudo: reject+=2\n",
2388 #ifdef SECONDARY_MEMORY_NEEDED
2389 /* If reload requires moving value through secondary
2390 memory, it will need one more insn at least. */
2391 if (this_alternative
!= NO_REGS
2392 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2393 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2394 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2396 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2397 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2401 /* Input reloads can be inherited more often than output
2402 reloads can be removed, so penalize output
2404 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2406 if (lra_dump_file
!= NULL
)
2409 " %d Non input pseudo reload: reject++\n",
2415 if (early_clobber_p
&& ! scratch_p
)
2417 if (lra_dump_file
!= NULL
)
2418 fprintf (lra_dump_file
,
2419 " %d Early clobber: reject++\n", nop
);
2422 /* ??? We check early clobbers after processing all operands
2423 (see loop below) and there we update the costs more.
2424 Should we update the cost (may be approximately) here
2425 because of early clobber register reloads or it is a rare
2426 or non-important thing to be worth to do it. */
2427 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2428 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2430 if (lra_dump_file
!= NULL
)
2431 fprintf (lra_dump_file
,
2432 " alt=%d,overall=%d,losers=%d -- refuse\n",
2433 nalt
, overall
, losers
);
2437 curr_alt
[nop
] = this_alternative
;
2438 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2439 curr_alt_win
[nop
] = this_alternative_win
;
2440 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2441 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2442 curr_alt_matches
[nop
] = this_alternative_matches
;
2444 if (this_alternative_matches
>= 0
2445 && !did_match
&& !this_alternative_win
)
2446 curr_alt_win
[this_alternative_matches
] = false;
2448 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2449 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2451 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2452 /* Prevent processing non-move insns. */
2453 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2454 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2455 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2456 && REG_P (no_subreg_reg_operand
[0])
2457 && REG_P (no_subreg_reg_operand
[1])
2458 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2459 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2460 || (! curr_alt_win
[0] && curr_alt_win
[1]
2461 && REG_P (no_subreg_reg_operand
[1])
2462 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2463 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2464 && REG_P (no_subreg_reg_operand
[0])
2465 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2466 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2467 no_subreg_reg_operand
[1])
2468 || (targetm
.preferred_reload_class
2469 (no_subreg_reg_operand
[1],
2470 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2471 /* If it is a result of recent elimination in move
2472 insn we can transform it into an add still by
2473 using this alternative. */
2474 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2476 /* We have a move insn and a new reload insn will be similar
2477 to the current insn. We should avoid such situation as it
2478 results in LRA cycling. */
2479 overall
+= LRA_MAX_REJECT
;
2482 curr_alt_dont_inherit_ops_num
= 0;
2483 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2485 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2486 HARD_REG_SET temp_set
;
2488 i
= early_clobbered_nops
[nop
];
2489 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2490 || hard_regno
[i
] < 0)
2492 lra_assert (operand_reg
[i
] != NULL_RTX
);
2493 clobbered_hard_regno
= hard_regno
[i
];
2494 CLEAR_HARD_REG_SET (temp_set
);
2495 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2496 first_conflict_j
= last_conflict_j
= -1;
2497 for (j
= 0; j
< n_operands
; j
++)
2499 /* We don't want process insides of match_operator and
2500 match_parallel because otherwise we would process
2501 their operands once again generating a wrong
2503 || curr_static_id
->operand
[j
].is_operator
)
2505 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2506 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2508 /* If we don't reload j-th operand, check conflicts. */
2509 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2510 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2512 if (first_conflict_j
< 0)
2513 first_conflict_j
= j
;
2514 last_conflict_j
= j
;
2516 if (last_conflict_j
< 0)
2518 /* If earlyclobber operand conflicts with another
2519 non-matching operand which is actually the same register
2520 as the earlyclobber operand, it is better to reload the
2521 another operand as an operand matching the earlyclobber
2522 operand can be also the same. */
2523 if (first_conflict_j
== last_conflict_j
2524 && operand_reg
[last_conflict_j
]
2525 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2526 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2528 curr_alt_win
[last_conflict_j
] = false;
2529 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2532 /* Early clobber was already reflected in REJECT. */
2533 lra_assert (reject
> 0);
2534 if (lra_dump_file
!= NULL
)
2537 " %d Conflict early clobber reload: reject--\n",
2540 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2544 /* We need to reload early clobbered register and the
2545 matched registers. */
2546 for (j
= 0; j
< n_operands
; j
++)
2547 if (curr_alt_matches
[j
] == i
)
2549 curr_alt_match_win
[j
] = false;
2551 overall
+= LRA_LOSER_COST_FACTOR
;
2553 if (! curr_alt_match_win
[i
])
2554 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2557 /* Remember pseudos used for match reloads are never
2559 lra_assert (curr_alt_matches
[i
] >= 0);
2560 curr_alt_win
[curr_alt_matches
[i
]] = false;
2562 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2564 /* Early clobber was already reflected in REJECT. */
2565 lra_assert (reject
> 0);
2566 if (lra_dump_file
!= NULL
)
2569 " %d Matched conflict early clobber reloads:"
2573 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2576 if (lra_dump_file
!= NULL
)
2577 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2578 nalt
, overall
, losers
, reload_nregs
);
2580 /* If this alternative can be made to work by reloading, and it
2581 needs less reloading than the others checked so far, record
2582 it as the chosen goal for reloading. */
2583 if ((best_losers
!= 0 && losers
== 0)
2584 || (((best_losers
== 0 && losers
== 0)
2585 || (best_losers
!= 0 && losers
!= 0))
2586 && (best_overall
> overall
2587 || (best_overall
== overall
2588 /* If the cost of the reloads is the same,
2589 prefer alternative which requires minimal
2590 number of reload regs. */
2591 && (reload_nregs
< best_reload_nregs
2592 || (reload_nregs
== best_reload_nregs
2593 && (best_reload_sum
< reload_sum
2594 || (best_reload_sum
== reload_sum
2595 && nalt
< goal_alt_number
))))))))
2597 for (nop
= 0; nop
< n_operands
; nop
++)
2599 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2600 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2601 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2602 goal_alt
[nop
] = curr_alt
[nop
];
2603 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2605 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2606 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2607 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2608 goal_alt_swapped
= curr_swapped
;
2609 best_overall
= overall
;
2610 best_losers
= losers
;
2611 best_reload_nregs
= reload_nregs
;
2612 best_reload_sum
= reload_sum
;
2613 goal_alt_number
= nalt
;
2616 /* Everything is satisfied. Do not process alternatives
2625 /* Make reload base reg from address AD. */
2627 base_to_reg (struct address_info
*ad
)
2631 rtx new_inner
= NULL_RTX
;
2632 rtx new_reg
= NULL_RTX
;
2634 rtx_insn
*last_insn
= get_last_insn();
2636 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2637 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2638 get_index_code (ad
));
2639 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2641 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
2642 ad
->disp_term
== NULL
2643 ? gen_int_mode (0, ad
->mode
)
2645 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
2647 insn
= emit_insn (gen_rtx_SET (ad
->mode
, new_reg
, *ad
->base_term
));
2648 code
= recog_memoized (insn
);
2651 delete_insns_since (last_insn
);
2658 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2660 base_plus_disp_to_reg (struct address_info
*ad
)
2665 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2666 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2667 get_index_code (ad
));
2668 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2670 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2674 /* Make reload of index part of address AD. Return the new
2677 index_part_to_reg (struct address_info
*ad
)
2681 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2682 INDEX_REG_CLASS
, "index term");
2683 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2684 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2688 /* Return true if we can add a displacement to address AD, even if that
2689 makes the address invalid. The fix-up code requires any new address
2690 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2692 can_add_disp_p (struct address_info
*ad
)
2694 return (!ad
->autoinc_p
2695 && ad
->segment
== NULL
2696 && ad
->base
== ad
->base_term
2697 && ad
->disp
== ad
->disp_term
);
2700 /* Make equiv substitution in address AD. Return true if a substitution
2703 equiv_address_substitution (struct address_info
*ad
)
2705 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2706 HOST_WIDE_INT disp
, scale
;
2709 base_term
= strip_subreg (ad
->base_term
);
2710 if (base_term
== NULL
)
2711 base_reg
= new_base_reg
= NULL_RTX
;
2714 base_reg
= *base_term
;
2715 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2717 index_term
= strip_subreg (ad
->index_term
);
2718 if (index_term
== NULL
)
2719 index_reg
= new_index_reg
= NULL_RTX
;
2722 index_reg
= *index_term
;
2723 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2725 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2729 if (lra_dump_file
!= NULL
)
2731 fprintf (lra_dump_file
, "Changing address in insn %d ",
2732 INSN_UID (curr_insn
));
2733 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2735 if (base_reg
!= new_base_reg
)
2737 if (REG_P (new_base_reg
))
2739 *base_term
= new_base_reg
;
2742 else if (GET_CODE (new_base_reg
) == PLUS
2743 && REG_P (XEXP (new_base_reg
, 0))
2744 && CONST_INT_P (XEXP (new_base_reg
, 1))
2745 && can_add_disp_p (ad
))
2747 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2748 *base_term
= XEXP (new_base_reg
, 0);
2751 if (ad
->base_term2
!= NULL
)
2752 *ad
->base_term2
= *ad
->base_term
;
2754 if (index_reg
!= new_index_reg
)
2756 if (REG_P (new_index_reg
))
2758 *index_term
= new_index_reg
;
2761 else if (GET_CODE (new_index_reg
) == PLUS
2762 && REG_P (XEXP (new_index_reg
, 0))
2763 && CONST_INT_P (XEXP (new_index_reg
, 1))
2764 && can_add_disp_p (ad
)
2765 && (scale
= get_index_scale (ad
)))
2767 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2768 *index_term
= XEXP (new_index_reg
, 0);
2774 if (ad
->disp
!= NULL
)
2775 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2778 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2779 update_address (ad
);
2783 if (lra_dump_file
!= NULL
)
2786 fprintf (lra_dump_file
, " -- no change\n");
2789 fprintf (lra_dump_file
, " on equiv ");
2790 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2791 fprintf (lra_dump_file
, "\n");
2797 /* Major function to make reloads for an address in operand NOP or
2798 check its correctness (If CHECK_ONLY_P is true). The supported
2801 1) an address that existed before LRA started, at which point it
2802 must have been valid. These addresses are subject to elimination
2803 and may have become invalid due to the elimination offset being out
2806 2) an address created by forcing a constant to memory
2807 (force_const_to_mem). The initial form of these addresses might
2808 not be valid, and it is this function's job to make them valid.
2810 3) a frame address formed from a register and a (possibly zero)
2811 constant offset. As above, these addresses might not be valid and
2812 this function must make them so.
2814 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2815 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2816 address. Return true for any RTL change.
2818 The function is a helper function which does not produce all
2819 transformations (when CHECK_ONLY_P is false) which can be
2820 necessary. It does just basic steps. To do all necessary
2821 transformations use function process_address. */
2823 process_address_1 (int nop
, bool check_only_p
,
2824 rtx_insn
**before
, rtx_insn
**after
)
2826 struct address_info ad
;
2828 rtx op
= *curr_id
->operand_loc
[nop
];
2829 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2830 enum constraint_num cn
= lookup_constraint (constraint
);
2831 bool change_p
= false;
2833 if (insn_extra_address_constraint (cn
))
2834 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2835 else if (MEM_P (op
))
2836 decompose_mem_address (&ad
, op
);
2837 else if (GET_CODE (op
) == SUBREG
2838 && MEM_P (SUBREG_REG (op
)))
2839 decompose_mem_address (&ad
, SUBREG_REG (op
));
2842 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
2843 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
2844 when INDEX_REG_CLASS is a single register class. */
2845 if (ad
.base_term
!= NULL
2846 && ad
.index_term
!= NULL
2847 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
2848 && REG_P (*ad
.base_term
)
2849 && REG_P (*ad
.index_term
)
2850 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
2851 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
2853 std::swap (ad
.base
, ad
.index
);
2854 std::swap (ad
.base_term
, ad
.index_term
);
2857 change_p
= equiv_address_substitution (&ad
);
2858 if (ad
.base_term
!= NULL
2859 && (process_addr_reg
2860 (ad
.base_term
, check_only_p
, before
,
2862 && !(REG_P (*ad
.base_term
)
2863 && find_regno_note (curr_insn
, REG_DEAD
,
2864 REGNO (*ad
.base_term
)) != NULL_RTX
)
2866 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2867 get_index_code (&ad
)))))
2870 if (ad
.base_term2
!= NULL
)
2871 *ad
.base_term2
= *ad
.base_term
;
2873 if (ad
.index_term
!= NULL
2874 && process_addr_reg (ad
.index_term
, check_only_p
,
2875 before
, NULL
, INDEX_REG_CLASS
))
2878 /* Target hooks sometimes don't treat extra-constraint addresses as
2879 legitimate address_operands, so handle them specially. */
2880 if (insn_extra_address_constraint (cn
)
2881 && satisfies_address_constraint_p (&ad
, cn
))
2887 /* There are three cases where the shape of *AD.INNER may now be invalid:
2889 1) the original address was valid, but either elimination or
2890 equiv_address_substitution was applied and that made
2891 the address invalid.
2893 2) the address is an invalid symbolic address created by
2896 3) the address is a frame address with an invalid offset.
2898 4) the address is a frame address with an invalid base.
2900 All these cases involve a non-autoinc address, so there is no
2901 point revalidating other types. */
2902 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2905 /* Any index existed before LRA started, so we can assume that the
2906 presence and shape of the index is valid. */
2907 push_to_sequence (*before
);
2908 lra_assert (ad
.disp
== ad
.disp_term
);
2909 if (ad
.base
== NULL
)
2911 if (ad
.index
== NULL
)
2914 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2916 rtx addr
= *ad
.inner
;
2918 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2922 rtx_insn
*last
= get_last_insn ();
2924 /* addr => lo_sum (new_base, addr), case (2) above. */
2925 insn
= emit_insn (gen_rtx_SET
2927 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2928 code
= recog_memoized (insn
);
2931 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2932 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2934 /* Try to put lo_sum into register. */
2935 insn
= emit_insn (gen_rtx_SET
2937 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2938 code
= recog_memoized (insn
);
2941 *ad
.inner
= new_reg
;
2942 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2952 delete_insns_since (last
);
2957 /* addr => new_base, case (2) above. */
2958 lra_emit_move (new_reg
, addr
);
2959 *ad
.inner
= new_reg
;
2964 /* index * scale + disp => new base + index * scale,
2966 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2967 GET_CODE (*ad
.index
));
2969 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2970 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2971 lra_emit_move (new_reg
, *ad
.disp
);
2972 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2973 new_reg
, *ad
.index
);
2976 else if (ad
.index
== NULL
)
2981 rtx_insn
*insns
, *last_insn
;
2982 /* Try to reload base into register only if the base is invalid
2983 for the address but with valid offset, case (4) above. */
2985 new_reg
= base_to_reg (&ad
);
2987 /* base + disp => new base, cases (1) and (3) above. */
2988 /* Another option would be to reload the displacement into an
2989 index register. However, postreload has code to optimize
2990 address reloads that have the same base and different
2991 displacements, so reloading into an index register would
2992 not necessarily be a win. */
2993 if (new_reg
== NULL_RTX
)
2994 new_reg
= base_plus_disp_to_reg (&ad
);
2995 insns
= get_insns ();
2996 last_insn
= get_last_insn ();
2997 /* If we generated at least two insns, try last insn source as
2998 an address. If we succeed, we generate one less insn. */
2999 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3000 && GET_CODE (SET_SRC (set
)) == PLUS
3001 && REG_P (XEXP (SET_SRC (set
), 0))
3002 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3004 *ad
.inner
= SET_SRC (set
);
3005 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3007 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3008 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3009 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3010 get_index_code (&ad
));
3011 regno
= REGNO (*ad
.base_term
);
3012 if (regno
>= FIRST_PSEUDO_REGISTER
3013 && cl
!= lra_get_allocno_class (regno
))
3014 lra_change_class (regno
, cl
, " Change to", true);
3015 new_reg
= SET_SRC (set
);
3016 delete_insns_since (PREV_INSN (last_insn
));
3019 /* Try if target can split displacement into legitimite new disp
3020 and offset. If it's the case, we replace the last insn with
3021 insns for base + offset => new_reg and set new_reg + new disp
3023 last_insn
= get_last_insn ();
3024 if ((set
= single_set (last_insn
)) != NULL_RTX
3025 && GET_CODE (SET_SRC (set
)) == PLUS
3026 && REG_P (XEXP (SET_SRC (set
), 0))
3027 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3028 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3030 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3031 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3034 rtx_insn
*new_insns
;
3036 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3037 new_insns
= get_insns ();
3039 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3040 delete_insns_since (PREV_INSN (last_insn
));
3041 add_insn (new_insns
);
3042 insns
= get_insns ();
3047 *ad
.inner
= new_reg
;
3049 else if (ad
.disp_term
!= NULL
)
3051 /* base + scale * index + disp => new base + scale * index,
3053 new_reg
= base_plus_disp_to_reg (&ad
);
3054 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3055 new_reg
, *ad
.index
);
3057 else if (get_index_scale (&ad
) == 1)
3059 /* The last transformation to one reg will be made in
3060 curr_insn_transform function. */
3066 /* base + scale * index => base + new_reg,
3068 Index part of address may become invalid. For example, we
3069 changed pseudo on the equivalent memory and a subreg of the
3070 pseudo onto the memory of different mode for which the scale is
3072 new_reg
= index_part_to_reg (&ad
);
3073 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3074 *ad
.base_term
, new_reg
);
3076 *before
= get_insns ();
3081 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3082 Use process_address_1 as a helper function. Return true for any
3085 If CHECK_ONLY_P is true, just check address correctness. Return
3086 false if the address correct. */
3088 process_address (int nop
, bool check_only_p
,
3089 rtx_insn
**before
, rtx_insn
**after
)
3093 while (process_address_1 (nop
, check_only_p
, before
, after
))
3102 /* Emit insns to reload VALUE into a new register. VALUE is an
3103 auto-increment or auto-decrement RTX whose operand is a register or
3104 memory location; so reloading involves incrementing that location.
3105 IN is either identical to VALUE, or some cheaper place to reload
3106 value being incremented/decremented from.
3108 INC_AMOUNT is the number to increment or decrement by (always
3109 positive and ignored for POST_MODIFY/PRE_MODIFY).
3111 Return pseudo containing the result. */
3113 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3115 /* REG or MEM to be copied and incremented. */
3116 rtx incloc
= XEXP (value
, 0);
3117 /* Nonzero if increment after copying. */
3118 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3119 || GET_CODE (value
) == POST_MODIFY
);
3124 rtx real_in
= in
== value
? incloc
: in
;
3128 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3130 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3131 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3132 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3133 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3134 inc
= XEXP (XEXP (value
, 1), 1);
3138 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3139 inc_amount
= -inc_amount
;
3141 inc
= GEN_INT (inc_amount
);
3144 if (! post
&& REG_P (incloc
))
3147 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3150 if (real_in
!= result
)
3152 /* First copy the location to the result register. */
3153 lra_assert (REG_P (result
));
3154 emit_insn (gen_move_insn (result
, real_in
));
3157 /* We suppose that there are insns to add/sub with the constant
3158 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3159 old reload worked with this assumption. If the assumption
3160 becomes wrong, we should use approach in function
3161 base_plus_disp_to_reg. */
3164 /* See if we can directly increment INCLOC. */
3165 last
= get_last_insn ();
3166 add_insn
= emit_insn (plus_p
3167 ? gen_add2_insn (incloc
, inc
)
3168 : gen_sub2_insn (incloc
, inc
));
3170 code
= recog_memoized (add_insn
);
3173 if (! post
&& result
!= incloc
)
3174 emit_insn (gen_move_insn (result
, incloc
));
3177 delete_insns_since (last
);
3180 /* If couldn't do the increment directly, must increment in RESULT.
3181 The way we do this depends on whether this is pre- or
3182 post-increment. For pre-increment, copy INCLOC to the reload
3183 register, increment it there, then save back. */
3186 if (real_in
!= result
)
3187 emit_insn (gen_move_insn (result
, real_in
));
3189 emit_insn (gen_add2_insn (result
, inc
));
3191 emit_insn (gen_sub2_insn (result
, inc
));
3192 if (result
!= incloc
)
3193 emit_insn (gen_move_insn (incloc
, result
));
3199 Because this might be a jump insn or a compare, and because
3200 RESULT may not be available after the insn in an input
3201 reload, we must do the incrementing before the insn being
3204 We have already copied IN to RESULT. Increment the copy in
3205 RESULT, save that back, then decrement RESULT so it has
3206 the original value. */
3208 emit_insn (gen_add2_insn (result
, inc
));
3210 emit_insn (gen_sub2_insn (result
, inc
));
3211 emit_insn (gen_move_insn (incloc
, result
));
3212 /* Restore non-modified value for the result. We prefer this
3213 way because it does not require an additional hard
3217 if (CONST_INT_P (inc
))
3218 emit_insn (gen_add2_insn (result
,
3219 gen_int_mode (-INTVAL (inc
),
3220 GET_MODE (result
))));
3222 emit_insn (gen_sub2_insn (result
, inc
));
3225 emit_insn (gen_add2_insn (result
, inc
));
3230 /* Return true if the current move insn does not need processing as we
3231 already know that it satisfies its constraints. */
3233 simple_move_p (void)
3236 enum reg_class dclass
, sclass
;
3238 lra_assert (curr_insn_set
!= NULL_RTX
);
3239 dest
= SET_DEST (curr_insn_set
);
3240 src
= SET_SRC (curr_insn_set
);
3241 return ((dclass
= get_op_class (dest
)) != NO_REGS
3242 && (sclass
= get_op_class (src
)) != NO_REGS
3243 /* The backend guarantees that register moves of cost 2
3244 never need reloads. */
3245 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3248 /* Swap operands NOP and NOP + 1. */
3250 swap_operands (int nop
)
3252 machine_mode mode
= curr_operand_mode
[nop
];
3253 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3254 curr_operand_mode
[nop
+ 1] = mode
;
3255 rtx x
= *curr_id
->operand_loc
[nop
];
3256 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3257 *curr_id
->operand_loc
[nop
+ 1] = x
;
3258 /* Swap the duplicates too. */
3259 lra_update_dup (curr_id
, nop
);
3260 lra_update_dup (curr_id
, nop
+ 1);
3263 /* Main entry point of the constraint code: search the body of the
3264 current insn to choose the best alternative. It is mimicking insn
3265 alternative cost calculation model of former reload pass. That is
3266 because machine descriptions were written to use this model. This
3267 model can be changed in future. Make commutative operand exchange
3270 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3271 constraints. Return true if any change happened during function
3274 If CHECK_ONLY_P is true then don't do any transformation. Just
3275 check that the insn satisfies all constraints. If the insn does
3276 not satisfy any constraint, return true. */
3278 curr_insn_transform (bool check_only_p
)
3284 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3285 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3286 rtx_insn
*before
, *after
;
3288 /* Flag that the insn has been changed through a transformation. */
3291 #ifdef SECONDARY_MEMORY_NEEDED
3294 int max_regno_before
;
3295 int reused_alternative_num
;
3297 curr_insn_set
= single_set (curr_insn
);
3298 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3301 no_input_reloads_p
= no_output_reloads_p
= false;
3302 goal_alt_number
= -1;
3303 change_p
= sec_mem_p
= false;
3304 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3305 reloads; neither are insns that SET cc0. Insns that use CC0 are
3306 not allowed to have any input reloads. */
3307 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3308 no_output_reloads_p
= true;
3311 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3312 no_input_reloads_p
= true;
3313 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3314 no_output_reloads_p
= true;
3317 n_operands
= curr_static_id
->n_operands
;
3318 n_alternatives
= curr_static_id
->n_alternatives
;
3320 /* Just return "no reloads" if insn has no operands with
3322 if (n_operands
== 0 || n_alternatives
== 0)
3325 max_regno_before
= max_reg_num ();
3327 for (i
= 0; i
< n_operands
; i
++)
3329 goal_alt_matched
[i
][0] = -1;
3330 goal_alt_matches
[i
] = -1;
3333 commutative
= curr_static_id
->commutative
;
3335 /* Now see what we need for pseudos that didn't get hard regs or got
3336 the wrong kind of hard reg. For this, we must consider all the
3337 operands together against the register constraints. */
3339 best_losers
= best_overall
= INT_MAX
;
3340 best_reload_sum
= 0;
3342 curr_swapped
= false;
3343 goal_alt_swapped
= false;
3346 /* Make equivalence substitution and memory subreg elimination
3347 before address processing because an address legitimacy can
3348 depend on memory mode. */
3349 for (i
= 0; i
< n_operands
; i
++)
3351 rtx op
= *curr_id
->operand_loc
[i
];
3352 rtx subst
, old
= op
;
3353 bool op_change_p
= false;
3355 if (GET_CODE (old
) == SUBREG
)
3356 old
= SUBREG_REG (old
);
3357 subst
= get_equiv_with_elimination (old
, curr_insn
);
3360 subst
= copy_rtx (subst
);
3361 lra_assert (REG_P (old
));
3362 if (GET_CODE (op
) == SUBREG
)
3363 SUBREG_REG (op
) = subst
;
3365 *curr_id
->operand_loc
[i
] = subst
;
3366 if (lra_dump_file
!= NULL
)
3368 fprintf (lra_dump_file
,
3369 "Changing pseudo %d in operand %i of insn %u on equiv ",
3370 REGNO (old
), i
, INSN_UID (curr_insn
));
3371 dump_value_slim (lra_dump_file
, subst
, 1);
3372 fprintf (lra_dump_file
, "\n");
3374 op_change_p
= change_p
= true;
3376 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3379 lra_update_dup (curr_id
, i
);
3383 /* Reload address registers and displacements. We do it before
3384 finding an alternative because of memory constraints. */
3385 before
= after
= NULL
;
3386 for (i
= 0; i
< n_operands
; i
++)
3387 if (! curr_static_id
->operand
[i
].is_operator
3388 && process_address (i
, check_only_p
, &before
, &after
))
3393 lra_update_dup (curr_id
, i
);
3397 /* If we've changed the instruction then any alternative that
3398 we chose previously may no longer be valid. */
3399 lra_set_used_insn_alternative (curr_insn
, -1);
3401 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3402 && check_and_process_move (&change_p
, &sec_mem_p
))
3407 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3408 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3409 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3410 reused_alternative_num
, INSN_UID (curr_insn
));
3412 if (process_alt_operands (reused_alternative_num
))
3416 return ! alt_p
|| best_losers
!= 0;
3418 /* If insn is commutative (it's safe to exchange a certain pair of
3419 operands) then we need to try each alternative twice, the second
3420 time matching those two operands as if we had exchanged them. To
3421 do this, really exchange them in operands.
3423 If we have just tried the alternatives the second time, return
3424 operands to normal and drop through. */
3426 if (reused_alternative_num
< 0 && commutative
>= 0)
3428 curr_swapped
= !curr_swapped
;
3431 swap_operands (commutative
);
3435 swap_operands (commutative
);
3438 if (! alt_p
&& ! sec_mem_p
)
3440 /* No alternative works with reloads?? */
3441 if (INSN_CODE (curr_insn
) >= 0)
3442 fatal_insn ("unable to generate reloads for:", curr_insn
);
3443 error_for_asm (curr_insn
,
3444 "inconsistent operand constraints in an %<asm%>");
3445 /* Avoid further trouble with this insn. */
3446 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3447 lra_invalidate_insn_data (curr_insn
);
3451 /* If the best alternative is with operands 1 and 2 swapped, swap
3452 them. Update the operand numbers of any reloads already
3455 if (goal_alt_swapped
)
3457 if (lra_dump_file
!= NULL
)
3458 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3459 INSN_UID (curr_insn
));
3461 /* Swap the duplicates too. */
3462 swap_operands (commutative
);
3466 #ifdef SECONDARY_MEMORY_NEEDED
3467 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3468 too conservatively. So we use the secondary memory only if there
3469 is no any alternative without reloads. */
3470 use_sec_mem_p
= false;
3472 use_sec_mem_p
= true;
3475 for (i
= 0; i
< n_operands
; i
++)
3476 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3478 use_sec_mem_p
= i
< n_operands
;
3483 rtx new_reg
, src
, dest
, rld
;
3484 machine_mode sec_mode
, rld_mode
;
3486 lra_assert (sec_mem_p
);
3487 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3488 && curr_static_id
->operand
[1].type
== OP_IN
);
3489 dest
= *curr_id
->operand_loc
[0];
3490 src
= *curr_id
->operand_loc
[1];
3491 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3493 rld_mode
= GET_MODE (rld
);
3494 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3495 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3497 sec_mode
= rld_mode
;
3499 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3500 NO_REGS
, "secondary");
3501 /* If the mode is changed, it should be wider. */
3502 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3503 if (sec_mode
!= rld_mode
)
3505 /* If the target says specifically to use another mode for
3506 secondary memory moves we can not reuse the original
3508 after
= emit_spill_move (false, new_reg
, dest
);
3509 lra_process_new_insns (curr_insn
, NULL
, after
,
3510 "Inserting the sec. move");
3511 /* We may have non null BEFORE here (e.g. after address
3513 push_to_sequence (before
);
3514 before
= emit_spill_move (true, new_reg
, src
);
3516 before
= get_insns ();
3518 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3519 lra_set_insn_deleted (curr_insn
);
3521 else if (dest
== rld
)
3523 *curr_id
->operand_loc
[0] = new_reg
;
3524 after
= emit_spill_move (false, new_reg
, dest
);
3525 lra_process_new_insns (curr_insn
, NULL
, after
,
3526 "Inserting the sec. move");
3530 *curr_id
->operand_loc
[1] = new_reg
;
3531 /* See comments above. */
3532 push_to_sequence (before
);
3533 before
= emit_spill_move (true, new_reg
, src
);
3535 before
= get_insns ();
3537 lra_process_new_insns (curr_insn
, before
, NULL
,
3538 "Inserting the sec. move");
3540 lra_update_insn_regno_info (curr_insn
);
3545 lra_assert (goal_alt_number
>= 0);
3546 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3548 if (lra_dump_file
!= NULL
)
3552 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3553 goal_alt_number
, INSN_UID (curr_insn
));
3554 for (i
= 0; i
< n_operands
; i
++)
3556 p
= (curr_static_id
->operand_alternative
3557 [goal_alt_number
* n_operands
+ i
].constraint
);
3560 fprintf (lra_dump_file
, " (%d) ", i
);
3561 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3562 fputc (*p
, lra_dump_file
);
3564 if (INSN_CODE (curr_insn
) >= 0
3565 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3566 fprintf (lra_dump_file
, " {%s}", p
);
3567 if (curr_id
->sp_offset
!= 0)
3568 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3569 curr_id
->sp_offset
);
3570 fprintf (lra_dump_file
, "\n");
3573 /* Right now, for any pair of operands I and J that are required to
3574 match, with J < I, goal_alt_matches[I] is J. Add I to
3575 goal_alt_matched[J]. */
3577 for (i
= 0; i
< n_operands
; i
++)
3578 if ((j
= goal_alt_matches
[i
]) >= 0)
3580 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3582 /* We allow matching one output operand and several input
3585 || (curr_static_id
->operand
[j
].type
== OP_OUT
3586 && curr_static_id
->operand
[i
].type
== OP_IN
3587 && (curr_static_id
->operand
3588 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3589 goal_alt_matched
[j
][k
] = i
;
3590 goal_alt_matched
[j
][k
+ 1] = -1;
3593 for (i
= 0; i
< n_operands
; i
++)
3594 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3596 /* Any constants that aren't allowed and can't be reloaded into
3597 registers are here changed into memory references. */
3598 for (i
= 0; i
< n_operands
; i
++)
3599 if (goal_alt_win
[i
])
3602 enum reg_class new_class
;
3603 rtx reg
= *curr_id
->operand_loc
[i
];
3605 if (GET_CODE (reg
) == SUBREG
)
3606 reg
= SUBREG_REG (reg
);
3608 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3610 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3612 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3615 lra_change_class (regno
, new_class
, " Change to", true);
3621 const char *constraint
;
3623 rtx op
= *curr_id
->operand_loc
[i
];
3624 rtx subreg
= NULL_RTX
;
3625 machine_mode mode
= curr_operand_mode
[i
];
3627 if (GET_CODE (op
) == SUBREG
)
3630 op
= SUBREG_REG (op
);
3631 mode
= GET_MODE (op
);
3634 if (CONST_POOL_OK_P (mode
, op
)
3635 && ((targetm
.preferred_reload_class
3636 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3637 || no_input_reloads_p
))
3639 rtx tem
= force_const_mem (mode
, op
);
3642 if (subreg
!= NULL_RTX
)
3643 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3645 *curr_id
->operand_loc
[i
] = tem
;
3646 lra_update_dup (curr_id
, i
);
3647 process_address (i
, false, &before
, &after
);
3649 /* If the alternative accepts constant pool refs directly
3650 there will be no reload needed at all. */
3651 if (subreg
!= NULL_RTX
)
3653 /* Skip alternatives before the one requested. */
3654 constraint
= (curr_static_id
->operand_alternative
3655 [goal_alt_number
* n_operands
+ i
].constraint
);
3657 (c
= *constraint
) && c
!= ',' && c
!= '#';
3658 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3660 enum constraint_num cn
= lookup_constraint (constraint
);
3661 if (insn_extra_memory_constraint (cn
)
3662 && satisfies_memory_constraint_p (tem
, cn
))
3665 if (c
== '\0' || c
== ',' || c
== '#')
3668 goal_alt_win
[i
] = true;
3672 for (i
= 0; i
< n_operands
; i
++)
3675 bool optional_p
= false;
3677 rtx op
= *curr_id
->operand_loc
[i
];
3679 if (goal_alt_win
[i
])
3681 if (goal_alt
[i
] == NO_REGS
3683 /* When we assign NO_REGS it means that we will not
3684 assign a hard register to the scratch pseudo by
3685 assigment pass and the scratch pseudo will be
3686 spilled. Spilled scratch pseudos are transformed
3687 back to scratches at the LRA end. */
3688 && lra_former_scratch_operand_p (curr_insn
, i
))
3690 int regno
= REGNO (op
);
3691 lra_change_class (regno
, NO_REGS
, " Change to", true);
3692 if (lra_get_regno_hard_regno (regno
) >= 0)
3693 /* We don't have to mark all insn affected by the
3694 spilled pseudo as there is only one such insn, the
3696 reg_renumber
[regno
] = -1;
3698 /* We can do an optional reload. If the pseudo got a hard
3699 reg, we might improve the code through inheritance. If
3700 it does not get a hard register we coalesce memory/memory
3701 moves later. Ignore move insns to avoid cycling. */
3703 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3704 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3705 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3706 && regno
< new_regno_start
3707 && ! lra_former_scratch_p (regno
)
3708 && reg_renumber
[regno
] < 0
3709 && (curr_insn_set
== NULL_RTX
3710 || !((REG_P (SET_SRC (curr_insn_set
))
3711 || MEM_P (SET_SRC (curr_insn_set
))
3712 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3713 && (REG_P (SET_DEST (curr_insn_set
))
3714 || MEM_P (SET_DEST (curr_insn_set
))
3715 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3721 /* Operands that match previous ones have already been handled. */
3722 if (goal_alt_matches
[i
] >= 0)
3725 /* We should not have an operand with a non-offsettable address
3726 appearing where an offsettable address will do. It also may
3727 be a case when the address should be special in other words
3728 not a general one (e.g. it needs no index reg). */
3729 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3731 enum reg_class rclass
;
3732 rtx
*loc
= &XEXP (op
, 0);
3733 enum rtx_code code
= GET_CODE (*loc
);
3735 push_to_sequence (before
);
3736 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3738 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3739 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3740 /* This value does not matter for MODIFY. */
3741 GET_MODE_SIZE (GET_MODE (op
)));
3742 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3743 "offsetable address", &new_reg
))
3744 lra_emit_move (new_reg
, *loc
);
3745 before
= get_insns ();
3748 lra_update_dup (curr_id
, i
);
3750 else if (goal_alt_matched
[i
][0] == -1)
3754 int hard_regno
, byte
;
3755 enum op_type type
= curr_static_id
->operand
[i
].type
;
3757 loc
= curr_id
->operand_loc
[i
];
3758 mode
= curr_operand_mode
[i
];
3759 if (GET_CODE (*loc
) == SUBREG
)
3761 reg
= SUBREG_REG (*loc
);
3762 byte
= SUBREG_BYTE (*loc
);
3764 /* Strict_low_part requires reload the register not
3765 the sub-register. */
3766 && (curr_static_id
->operand
[i
].strict_low
3767 || (GET_MODE_SIZE (mode
)
3768 <= GET_MODE_SIZE (GET_MODE (reg
))
3770 = get_try_hard_regno (REGNO (reg
))) >= 0
3771 && (simplify_subreg_regno
3773 GET_MODE (reg
), byte
, mode
) < 0)
3774 && (goal_alt
[i
] == NO_REGS
3775 || (simplify_subreg_regno
3776 (ira_class_hard_regs
[goal_alt
[i
]][0],
3777 GET_MODE (reg
), byte
, mode
) >= 0)))))
3779 loc
= &SUBREG_REG (*loc
);
3780 mode
= GET_MODE (*loc
);
3784 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3785 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3788 push_to_sequence (before
);
3789 lra_emit_move (new_reg
, old
);
3790 before
= get_insns ();
3795 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3798 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3800 after
= get_insns ();
3804 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3805 if (goal_alt_dont_inherit_ops
[j
] == i
)
3807 lra_set_regno_unique_value (REGNO (new_reg
));
3810 lra_update_dup (curr_id
, i
);
3812 else if (curr_static_id
->operand
[i
].type
== OP_IN
3813 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3816 /* generate reloads for input and matched outputs. */
3817 match_inputs
[0] = i
;
3818 match_inputs
[1] = -1;
3819 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3820 goal_alt
[i
], &before
, &after
);
3822 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3823 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3825 /* Generate reloads for output and matched inputs. */
3826 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3827 else if (curr_static_id
->operand
[i
].type
== OP_IN
3828 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3831 /* Generate reloads for matched inputs. */
3832 match_inputs
[0] = i
;
3833 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3834 match_inputs
[j
+ 1] = k
;
3835 match_inputs
[j
+ 1] = -1;
3836 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3839 /* We must generate code in any case when function
3840 process_alt_operands decides that it is possible. */
3844 lra_assert (REG_P (op
));
3846 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3847 if (GET_CODE (op
) == SUBREG
)
3848 op
= SUBREG_REG (op
);
3849 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3850 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3851 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3852 if (lra_dump_file
!= NULL
)
3853 fprintf (lra_dump_file
,
3854 " Making reload reg %d for reg %d optional\n",
3858 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3859 || max_regno_before
!= max_reg_num ())
3863 lra_update_operator_dups (curr_id
);
3864 /* Something changes -- process the insn. */
3865 lra_update_insn_regno_info (curr_insn
);
3867 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3871 /* Return true if INSN satisfies all constraints. In other words, no
3872 reload insns are needed. */
3874 lra_constrain_insn (rtx_insn
*insn
)
3876 int saved_new_regno_start
= new_regno_start
;
3877 int saved_new_insn_uid_start
= new_insn_uid_start
;
3881 curr_id
= lra_get_insn_recog_data (curr_insn
);
3882 curr_static_id
= curr_id
->insn_static_data
;
3883 new_insn_uid_start
= get_max_uid ();
3884 new_regno_start
= max_reg_num ();
3885 change_p
= curr_insn_transform (true);
3886 new_regno_start
= saved_new_regno_start
;
3887 new_insn_uid_start
= saved_new_insn_uid_start
;
3891 /* Return true if X is in LIST. */
3893 in_list_p (rtx x
, rtx list
)
3895 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3896 if (XEXP (list
, 0) == x
)
3901 /* Return true if X contains an allocatable hard register (if
3902 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3904 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3910 code
= GET_CODE (x
);
3913 int regno
= REGNO (x
);
3914 HARD_REG_SET alloc_regs
;
3918 if (regno
>= FIRST_PSEUDO_REGISTER
)
3919 regno
= lra_get_regno_hard_regno (regno
);
3922 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3923 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3927 if (regno
< FIRST_PSEUDO_REGISTER
)
3931 return lra_get_regno_hard_regno (regno
) < 0;
3934 fmt
= GET_RTX_FORMAT (code
);
3935 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3939 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3942 else if (fmt
[i
] == 'E')
3944 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3945 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3952 /* Return true if X contains a symbol reg. */
3954 contains_symbol_ref_p (rtx x
)
3960 code
= GET_CODE (x
);
3961 if (code
== SYMBOL_REF
)
3963 fmt
= GET_RTX_FORMAT (code
);
3964 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3968 if (contains_symbol_ref_p (XEXP (x
, i
)))
3971 else if (fmt
[i
] == 'E')
3973 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3974 if (contains_symbol_ref_p (XVECEXP (x
, i
, j
)))
3981 /* Process all regs in location *LOC and change them on equivalent
3982 substitution. Return true if any change was done. */
3984 loc_equivalence_change_p (rtx
*loc
)
3986 rtx subst
, reg
, x
= *loc
;
3987 bool result
= false;
3988 enum rtx_code code
= GET_CODE (x
);
3994 reg
= SUBREG_REG (x
);
3995 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3996 && GET_MODE (subst
) == VOIDmode
)
3998 /* We cannot reload debug location. Simplify subreg here
3999 while we know the inner mode. */
4000 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4001 GET_MODE (reg
), SUBREG_BYTE (x
));
4005 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4011 /* Scan all the operand sub-expressions. */
4012 fmt
= GET_RTX_FORMAT (code
);
4013 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4016 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4017 else if (fmt
[i
] == 'E')
4018 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4020 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4025 /* Similar to loc_equivalence_change_p, but for use as
4026 simplify_replace_fn_rtx callback. DATA is insn for which the
4027 elimination is done. If it null we don't do the elimination. */
4029 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4034 rtx subst
= (data
== NULL
4035 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4042 /* Maximum number of generated reload insns per an insn. It is for
4043 preventing this pass cycling in a bug case. */
4044 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4046 /* The current iteration number of this LRA pass. */
4047 int lra_constraint_iter
;
4049 /* True if we substituted equiv which needs checking register
4050 allocation correctness because the equivalent value contains
4051 allocatable hard registers or when we restore multi-register
4053 bool lra_risky_transformations_p
;
4055 /* Return true if REGNO is referenced in more than one block. */
4057 multi_block_pseudo_p (int regno
)
4059 basic_block bb
= NULL
;
4063 if (regno
< FIRST_PSEUDO_REGISTER
)
4066 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4068 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4069 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4074 /* Return true if LIST contains a deleted insn. */
4076 contains_deleted_insn_p (rtx_insn_list
*list
)
4078 for (; list
!= NULL_RTX
; list
= list
->next ())
4079 if (NOTE_P (list
->insn ())
4080 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4085 /* Return true if X contains a pseudo dying in INSN. */
4087 dead_pseudo_p (rtx x
, rtx insn
)
4094 return (insn
!= NULL_RTX
4095 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4096 code
= GET_CODE (x
);
4097 fmt
= GET_RTX_FORMAT (code
);
4098 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4102 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4105 else if (fmt
[i
] == 'E')
4107 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4108 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4115 /* Return true if INSN contains a dying pseudo in INSN right hand
4118 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4120 rtx set
= single_set (insn
);
4122 gcc_assert (set
!= NULL
);
4123 return dead_pseudo_p (SET_SRC (set
), insn
);
4126 /* Return true if any init insn of REGNO contains a dying pseudo in
4127 insn right hand side. */
4129 init_insn_rhs_dead_pseudo_p (int regno
)
4131 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4135 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4136 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4141 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4142 reverse only if we have one init insn with given REGNO as a
4145 reverse_equiv_p (int regno
)
4147 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4152 if (! INSN_P (insns
->insn ())
4153 || insns
->next () != NULL
)
4155 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4157 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4160 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4161 call this function only for non-reverse equivalence. */
4163 contains_reloaded_insn_p (int regno
)
4166 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4168 for (; list
!= NULL
; list
= list
->next ())
4169 if ((set
= single_set (list
->insn ())) == NULL_RTX
4170 || ! REG_P (SET_DEST (set
))
4171 || (int) REGNO (SET_DEST (set
)) != regno
)
4176 /* Entry function of LRA constraint pass. Return true if the
4177 constraint pass did change the code. */
4179 lra_constraints (bool first_p
)
4182 int i
, hard_regno
, new_insns_num
;
4183 unsigned int min_len
, new_min_len
, uid
;
4184 rtx set
, x
, reg
, dest_reg
;
4185 basic_block last_bb
;
4186 bitmap_head equiv_insn_bitmap
;
4189 lra_constraint_iter
++;
4190 if (lra_dump_file
!= NULL
)
4191 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4192 lra_constraint_iter
);
4194 if (pic_offset_table_rtx
4195 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4196 lra_risky_transformations_p
= true;
4198 lra_risky_transformations_p
= false;
4199 new_insn_uid_start
= get_max_uid ();
4200 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4201 /* Mark used hard regs for target stack size calulations. */
4202 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4203 if (lra_reg_info
[i
].nrefs
!= 0
4204 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4208 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4209 for (j
= 0; j
< nregs
; j
++)
4210 df_set_regs_ever_live (hard_regno
+ j
, true);
4212 /* Do elimination before the equivalence processing as we can spill
4213 some pseudos during elimination. */
4214 lra_eliminate (false, first_p
);
4215 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4216 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4217 if (lra_reg_info
[i
].nrefs
!= 0)
4219 ira_reg_equiv
[i
].profitable_p
= true;
4220 reg
= regno_reg_rtx
[i
];
4221 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4223 bool pseudo_p
= contains_reg_p (x
, false, false);
4225 /* After RTL transformation, we can not guarantee that
4226 pseudo in the substitution was not reloaded which might
4227 make equivalence invalid. For example, in reverse
4234 the memory address register was reloaded before the 2nd
4236 if ((! first_p
&& pseudo_p
)
4237 /* We don't use DF for compilation speed sake. So it
4238 is problematic to update live info when we use an
4239 equivalence containing pseudos in more than one
4241 || (pseudo_p
&& multi_block_pseudo_p (i
))
4242 /* If an init insn was deleted for some reason, cancel
4243 the equiv. We could update the equiv insns after
4244 transformations including an equiv insn deletion
4245 but it is not worthy as such cases are extremely
4247 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4248 /* If it is not a reverse equivalence, we check that a
4249 pseudo in rhs of the init insn is not dying in the
4250 insn. Otherwise, the live info at the beginning of
4251 the corresponding BB might be wrong after we
4252 removed the insn. When the equiv can be a
4253 constant, the right hand side of the init insn can
4255 || (! reverse_equiv_p (i
)
4256 && (init_insn_rhs_dead_pseudo_p (i
)
4257 /* If we reloaded the pseudo in an equivalence
4258 init insn, we can not remove the equiv init
4259 insns and the init insns might write into
4260 const memory in this case. */
4261 || contains_reloaded_insn_p (i
)))
4262 /* Prevent access beyond equivalent memory for
4263 paradoxical subregs. */
4265 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4266 > GET_MODE_SIZE (GET_MODE (x
))))
4267 || (pic_offset_table_rtx
4268 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4269 && (targetm
.preferred_reload_class
4270 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4271 || contains_symbol_ref_p (x
))))
4272 ira_reg_equiv
[i
].defined_p
= false;
4273 if (contains_reg_p (x
, false, true))
4274 ira_reg_equiv
[i
].profitable_p
= false;
4275 if (get_equiv (reg
) != reg
)
4276 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4279 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4281 /* We should add all insns containing pseudos which should be
4282 substituted by their equivalences. */
4283 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4284 lra_push_insn_by_uid (uid
);
4285 min_len
= lra_insn_stack_length ();
4289 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4291 curr_insn
= lra_pop_insn ();
4293 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4294 if (curr_bb
!= last_bb
)
4297 bb_reload_num
= lra_curr_reload_num
;
4299 if (min_len
> new_min_len
)
4301 min_len
= new_min_len
;
4304 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4306 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4307 MAX_RELOAD_INSNS_NUMBER
);
4309 if (DEBUG_INSN_P (curr_insn
))
4311 /* We need to check equivalence in debug insn and change
4312 pseudo to the equivalent value if necessary. */
4313 curr_id
= lra_get_insn_recog_data (curr_insn
);
4314 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4316 rtx old
= *curr_id
->operand_loc
[0];
4317 *curr_id
->operand_loc
[0]
4318 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4319 loc_equivalence_callback
, curr_insn
);
4320 if (old
!= *curr_id
->operand_loc
[0])
4322 lra_update_insn_regno_info (curr_insn
);
4327 else if (INSN_P (curr_insn
))
4329 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4331 dest_reg
= SET_DEST (set
);
4332 /* The equivalence pseudo could be set up as SUBREG in a
4333 case when it is a call restore insn in a mode
4334 different from the pseudo mode. */
4335 if (GET_CODE (dest_reg
) == SUBREG
)
4336 dest_reg
= SUBREG_REG (dest_reg
);
4337 if ((REG_P (dest_reg
)
4338 && (x
= get_equiv (dest_reg
)) != dest_reg
4339 /* Remove insns which set up a pseudo whose value
4340 can not be changed. Such insns might be not in
4341 init_insns because we don't update equiv data
4342 during insn transformations.
4344 As an example, let suppose that a pseudo got
4345 hard register and on the 1st pass was not
4346 changed to equivalent constant. We generate an
4347 additional insn setting up the pseudo because of
4348 secondary memory movement. Then the pseudo is
4349 spilled and we use the equiv constant. In this
4350 case we should remove the additional insn and
4351 this insn is not init_insns list. */
4352 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4353 /* Check that this is actually an insn setting
4354 up the equivalence. */
4355 || in_list_p (curr_insn
,
4357 [REGNO (dest_reg
)].init_insns
)))
4358 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4359 && in_list_p (curr_insn
,
4361 [REGNO (SET_SRC (set
))].init_insns
)))
4363 /* This is equiv init insn of pseudo which did not get a
4364 hard register -- remove the insn. */
4365 if (lra_dump_file
!= NULL
)
4367 fprintf (lra_dump_file
,
4368 " Removing equiv init insn %i (freq=%d)\n",
4369 INSN_UID (curr_insn
),
4370 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4371 dump_insn_slim (lra_dump_file
, curr_insn
);
4373 if (contains_reg_p (x
, true, false))
4374 lra_risky_transformations_p
= true;
4375 lra_set_insn_deleted (curr_insn
);
4379 curr_id
= lra_get_insn_recog_data (curr_insn
);
4380 curr_static_id
= curr_id
->insn_static_data
;
4381 init_curr_insn_input_reloads ();
4382 init_curr_operand_mode ();
4383 if (curr_insn_transform (false))
4385 /* Check non-transformed insns too for equiv change as USE
4386 or CLOBBER don't need reloads but can contain pseudos
4387 being changed on their equivalences. */
4388 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4389 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4391 lra_update_insn_regno_info (curr_insn
);
4396 bitmap_clear (&equiv_insn_bitmap
);
4397 /* If we used a new hard regno, changed_p should be true because the
4398 hard reg is assigned to a new pseudo. */
4399 #ifdef ENABLE_CHECKING
4402 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4403 if (lra_reg_info
[i
].nrefs
!= 0
4404 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4406 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4408 for (j
= 0; j
< nregs
; j
++)
4409 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4416 /* Initiate the LRA constraint pass. It is done once per
4419 lra_constraints_init (void)
4423 /* Finalize the LRA constraint pass. It is done once per
4426 lra_constraints_finish (void)
4432 /* This page contains code to do inheritance/split
4435 /* Number of reloads passed so far in current EBB. */
4436 static int reloads_num
;
4438 /* Number of calls passed so far in current EBB. */
4439 static int calls_num
;
4441 /* Current reload pseudo check for validity of elements in
4443 static int curr_usage_insns_check
;
4445 /* Info about last usage of registers in EBB to do inheritance/split
4446 transformation. Inheritance transformation is done from a spilled
4447 pseudo and split transformations from a hard register or a pseudo
4448 assigned to a hard register. */
4451 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4452 value INSNS is valid. The insns is chain of optional debug insns
4453 and a finishing non-debug insn using the corresponding reg. The
4454 value is also used to mark the registers which are set up in the
4455 current insn. The negated insn uid is used for this. */
4457 /* Value of global reloads_num at the last insn in INSNS. */
4459 /* Value of global reloads_nums at the last insn in INSNS. */
4461 /* It can be true only for splitting. And it means that the restore
4462 insn should be put after insn given by the following member. */
4464 /* Next insns in the current EBB which use the original reg and the
4465 original reg value is not changed between the current insn and
4466 the next insns. In order words, e.g. for inheritance, if we need
4467 to use the original reg value again in the next insns we can try
4468 to use the value in a hard register from a reload insn of the
4473 /* Map: regno -> corresponding pseudo usage insns. */
4474 static struct usage_insns
*usage_insns
;
4477 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4479 usage_insns
[regno
].check
= curr_usage_insns_check
;
4480 usage_insns
[regno
].insns
= insn
;
4481 usage_insns
[regno
].reloads_num
= reloads_num
;
4482 usage_insns
[regno
].calls_num
= calls_num
;
4483 usage_insns
[regno
].after_p
= after_p
;
4486 /* The function is used to form list REGNO usages which consists of
4487 optional debug insns finished by a non-debug insn using REGNO.
4488 RELOADS_NUM is current number of reload insns processed so far. */
4490 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4492 rtx next_usage_insns
;
4494 if (usage_insns
[regno
].check
== curr_usage_insns_check
4495 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4496 && DEBUG_INSN_P (insn
))
4498 /* Check that we did not add the debug insn yet. */
4499 if (next_usage_insns
!= insn
4500 && (GET_CODE (next_usage_insns
) != INSN_LIST
4501 || XEXP (next_usage_insns
, 0) != insn
))
4502 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4505 else if (NONDEBUG_INSN_P (insn
))
4506 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4508 usage_insns
[regno
].check
= 0;
4511 /* Return first non-debug insn in list USAGE_INSNS. */
4513 skip_usage_debug_insns (rtx usage_insns
)
4517 /* Skip debug insns. */
4518 for (insn
= usage_insns
;
4519 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4520 insn
= XEXP (insn
, 1))
4522 return safe_as_a
<rtx_insn
*> (insn
);
4525 /* Return true if we need secondary memory moves for insn in
4526 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4529 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4530 rtx usage_insns ATTRIBUTE_UNUSED
)
4532 #ifndef SECONDARY_MEMORY_NEEDED
4539 if (inher_cl
== ALL_REGS
4540 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4542 lra_assert (INSN_P (insn
));
4543 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4545 dest
= SET_DEST (set
);
4548 lra_assert (inher_cl
!= NO_REGS
);
4549 cl
= get_reg_class (REGNO (dest
));
4550 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4551 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4555 /* Registers involved in inheritance/split in the current EBB
4556 (inheritance/split pseudos and original registers). */
4557 static bitmap_head check_only_regs
;
4559 /* Do inheritance transformations for insn INSN, which defines (if
4560 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4561 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4562 form as the "insns" field of usage_insns. Return true if we
4563 succeed in such transformation.
4565 The transformations look like:
4568 ... p <- i (new insn)
4570 <- ... p ... <- ... i ...
4572 ... i <- p (new insn)
4573 <- ... p ... <- ... i ...
4575 <- ... p ... <- ... i ...
4576 where p is a spilled original pseudo and i is a new inheritance pseudo.
4579 The inheritance pseudo has the smallest class of two classes CL and
4580 class of ORIGINAL REGNO. */
4582 inherit_reload_reg (bool def_p
, int original_regno
,
4583 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
4585 if (optimize_function_for_size_p (cfun
))
4588 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4589 rtx original_reg
= regno_reg_rtx
[original_regno
];
4590 rtx new_reg
, usage_insn
;
4591 rtx_insn
*new_insns
;
4593 lra_assert (! usage_insns
[original_regno
].after_p
);
4594 if (lra_dump_file
!= NULL
)
4595 fprintf (lra_dump_file
,
4596 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4597 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4599 if (lra_dump_file
!= NULL
)
4601 fprintf (lra_dump_file
,
4602 " Rejecting inheritance for %d "
4603 "because of disjoint classes %s and %s\n",
4604 original_regno
, reg_class_names
[cl
],
4605 reg_class_names
[rclass
]);
4606 fprintf (lra_dump_file
,
4607 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4611 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4612 /* We don't use a subset of two classes because it can be
4613 NO_REGS. This transformation is still profitable in most
4614 cases even if the classes are not intersected as register
4615 move is probably cheaper than a memory load. */
4616 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4618 if (lra_dump_file
!= NULL
)
4619 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4620 reg_class_names
[cl
], reg_class_names
[rclass
]);
4624 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4626 /* Reject inheritance resulting in secondary memory moves.
4627 Otherwise, there is a danger in LRA cycling. Also such
4628 transformation will be unprofitable. */
4629 if (lra_dump_file
!= NULL
)
4631 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
4632 rtx set
= single_set (insn
);
4634 lra_assert (set
!= NULL_RTX
);
4636 rtx dest
= SET_DEST (set
);
4638 lra_assert (REG_P (dest
));
4639 fprintf (lra_dump_file
,
4640 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4641 "as secondary mem is needed\n",
4642 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4643 original_regno
, reg_class_names
[rclass
]);
4644 fprintf (lra_dump_file
,
4645 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4649 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4650 rclass
, "inheritance");
4653 lra_emit_move (original_reg
, new_reg
);
4655 lra_emit_move (new_reg
, original_reg
);
4656 new_insns
= get_insns ();
4658 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4660 if (lra_dump_file
!= NULL
)
4662 fprintf (lra_dump_file
,
4663 " Rejecting inheritance %d->%d "
4664 "as it results in 2 or more insns:\n",
4665 original_regno
, REGNO (new_reg
));
4666 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
4667 fprintf (lra_dump_file
,
4668 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4672 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
);
4673 lra_update_insn_regno_info (insn
);
4675 /* We now have a new usage insn for original regno. */
4676 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4677 if (lra_dump_file
!= NULL
)
4678 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4679 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4680 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4681 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4682 bitmap_set_bit (&check_only_regs
, original_regno
);
4683 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4685 lra_process_new_insns (insn
, NULL
, new_insns
,
4686 "Add original<-inheritance");
4688 lra_process_new_insns (insn
, new_insns
, NULL
,
4689 "Add inheritance<-original");
4690 while (next_usage_insns
!= NULL_RTX
)
4692 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4694 usage_insn
= next_usage_insns
;
4695 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4696 next_usage_insns
= NULL
;
4700 usage_insn
= XEXP (next_usage_insns
, 0);
4701 lra_assert (DEBUG_INSN_P (usage_insn
));
4702 next_usage_insns
= XEXP (next_usage_insns
, 1);
4704 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4705 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4706 if (lra_dump_file
!= NULL
)
4708 fprintf (lra_dump_file
,
4709 " Inheritance reuse change %d->%d (bb%d):\n",
4710 original_regno
, REGNO (new_reg
),
4711 BLOCK_FOR_INSN (usage_insn
)->index
);
4712 dump_insn_slim (lra_dump_file
, usage_insn
);
4715 if (lra_dump_file
!= NULL
)
4716 fprintf (lra_dump_file
,
4717 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4721 /* Return true if we need a caller save/restore for pseudo REGNO which
4722 was assigned to a hard register. */
4724 need_for_call_save_p (int regno
)
4726 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4727 return (usage_insns
[regno
].calls_num
< calls_num
4728 && (overlaps_hard_reg_set_p
4730 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4731 ? lra_reg_info
[regno
].actual_call_used_reg_set
4732 : call_used_reg_set
,
4733 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4734 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4735 PSEUDO_REGNO_MODE (regno
))));
4738 /* Global registers occurring in the current EBB. */
4739 static bitmap_head ebb_global_regs
;
4741 /* Return true if we need a split for hard register REGNO or pseudo
4742 REGNO which was assigned to a hard register.
4743 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4744 used for reloads since the EBB end. It is an approximation of the
4745 used hard registers in the split range. The exact value would
4746 require expensive calculations. If we were aggressive with
4747 splitting because of the approximation, the split pseudo will save
4748 the same hard register assignment and will be removed in the undo
4749 pass. We still need the approximation because too aggressive
4750 splitting would result in too inaccurate cost calculation in the
4751 assignment pass because of too many generated moves which will be
4752 probably removed in the undo pass. */
4754 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4756 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4758 lra_assert (hard_regno
>= 0);
4759 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4760 /* Don't split eliminable hard registers, otherwise we can
4761 split hard registers like hard frame pointer, which
4762 lives on BB start/end according to DF-infrastructure,
4763 when there is a pseudo assigned to the register and
4764 living in the same BB. */
4765 && (regno
>= FIRST_PSEUDO_REGISTER
4766 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4767 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4768 /* Don't split call clobbered hard regs living through
4769 calls, otherwise we might have a check problem in the
4770 assign sub-pass as in the most cases (exception is a
4771 situation when lra_risky_transformations_p value is
4772 true) the assign pass assumes that all pseudos living
4773 through calls are assigned to call saved hard regs. */
4774 && (regno
>= FIRST_PSEUDO_REGISTER
4775 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4776 || usage_insns
[regno
].calls_num
== calls_num
)
4777 /* We need at least 2 reloads to make pseudo splitting
4778 profitable. We should provide hard regno splitting in
4779 any case to solve 1st insn scheduling problem when
4780 moving hard register definition up might result in
4781 impossibility to find hard register for reload pseudo of
4782 small register class. */
4783 && (usage_insns
[regno
].reloads_num
4784 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4785 && (regno
< FIRST_PSEUDO_REGISTER
4786 /* For short living pseudos, spilling + inheritance can
4787 be considered a substitution for splitting.
4788 Therefore we do not splitting for local pseudos. It
4789 decreases also aggressiveness of splitting. The
4790 minimal number of references is chosen taking into
4791 account that for 2 references splitting has no sense
4792 as we can just spill the pseudo. */
4793 || (regno
>= FIRST_PSEUDO_REGISTER
4794 && lra_reg_info
[regno
].nrefs
> 3
4795 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4796 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4799 /* Return class for the split pseudo created from original pseudo with
4800 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4801 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4802 results in no secondary memory movements. */
4803 static enum reg_class
4804 choose_split_class (enum reg_class allocno_class
,
4805 int hard_regno ATTRIBUTE_UNUSED
,
4806 machine_mode mode ATTRIBUTE_UNUSED
)
4808 #ifndef SECONDARY_MEMORY_NEEDED
4809 return allocno_class
;
4812 enum reg_class cl
, best_cl
= NO_REGS
;
4813 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4814 = REGNO_REG_CLASS (hard_regno
);
4816 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4817 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4818 return allocno_class
;
4820 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4822 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4823 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4824 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4825 && (best_cl
== NO_REGS
4826 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4832 /* Do split transformations for insn INSN, which defines or uses
4833 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4834 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4835 "insns" field of usage_insns.
4837 The transformations look like:
4840 ... s <- p (new insn -- save)
4842 ... p <- s (new insn -- restore)
4843 <- ... p ... <- ... p ...
4845 <- ... p ... <- ... p ...
4846 ... s <- p (new insn -- save)
4848 ... p <- s (new insn -- restore)
4849 <- ... p ... <- ... p ...
4851 where p is an original pseudo got a hard register or a hard
4852 register and s is a new split pseudo. The save is put before INSN
4853 if BEFORE_P is true. Return true if we succeed in such
4856 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
4857 rtx next_usage_insns
)
4859 enum reg_class rclass
;
4861 int hard_regno
, nregs
;
4862 rtx new_reg
, usage_insn
;
4863 rtx_insn
*restore
, *save
;
4867 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4869 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4870 hard_regno
= original_regno
;
4871 call_save_p
= false;
4876 hard_regno
= reg_renumber
[original_regno
];
4877 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4878 rclass
= lra_get_allocno_class (original_regno
);
4879 original_reg
= regno_reg_rtx
[original_regno
];
4880 call_save_p
= need_for_call_save_p (original_regno
);
4882 original_reg
= regno_reg_rtx
[original_regno
];
4883 lra_assert (hard_regno
>= 0);
4884 if (lra_dump_file
!= NULL
)
4885 fprintf (lra_dump_file
,
4886 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4889 machine_mode mode
= GET_MODE (original_reg
);
4891 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4892 hard_regno_nregs
[hard_regno
][mode
],
4894 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4898 rclass
= choose_split_class (rclass
, hard_regno
,
4899 GET_MODE (original_reg
));
4900 if (rclass
== NO_REGS
)
4902 if (lra_dump_file
!= NULL
)
4904 fprintf (lra_dump_file
,
4905 " Rejecting split of %d(%s): "
4906 "no good reg class for %d(%s)\n",
4908 reg_class_names
[lra_get_allocno_class (original_regno
)],
4910 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4913 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4917 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4919 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4921 save
= emit_spill_move (true, new_reg
, original_reg
);
4922 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
4924 if (lra_dump_file
!= NULL
)
4928 " Rejecting split %d->%d resulting in > 2 save insns:\n",
4929 original_regno
, REGNO (new_reg
));
4930 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
4931 fprintf (lra_dump_file
,
4932 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4936 restore
= emit_spill_move (false, new_reg
, original_reg
);
4937 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
4939 if (lra_dump_file
!= NULL
)
4941 fprintf (lra_dump_file
,
4942 " Rejecting split %d->%d "
4943 "resulting in > 2 restore insns:\n",
4944 original_regno
, REGNO (new_reg
));
4945 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
4946 fprintf (lra_dump_file
,
4947 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4951 after_p
= usage_insns
[original_regno
].after_p
;
4952 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4953 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4954 bitmap_set_bit (&check_only_regs
, original_regno
);
4955 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4958 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4960 usage_insn
= next_usage_insns
;
4963 usage_insn
= XEXP (next_usage_insns
, 0);
4964 lra_assert (DEBUG_INSN_P (usage_insn
));
4965 next_usage_insns
= XEXP (next_usage_insns
, 1);
4966 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4967 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
4968 if (lra_dump_file
!= NULL
)
4970 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4971 original_regno
, REGNO (new_reg
));
4972 dump_insn_slim (lra_dump_file
, usage_insn
);
4975 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4976 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4977 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
4978 after_p
? NULL
: restore
,
4979 after_p
? restore
: NULL
,
4981 ? "Add reg<-save" : "Add reg<-split");
4982 lra_process_new_insns (insn
, before_p
? save
: NULL
,
4983 before_p
? NULL
: save
,
4985 ? "Add save<-reg" : "Add split<-reg");
4987 /* If we are trying to split multi-register. We should check
4988 conflicts on the next assignment sub-pass. IRA can allocate on
4989 sub-register levels, LRA do this on pseudos level right now and
4990 this discrepancy may create allocation conflicts after
4992 lra_risky_transformations_p
= true;
4993 if (lra_dump_file
!= NULL
)
4994 fprintf (lra_dump_file
,
4995 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4999 /* Recognize that we need a split transformation for insn INSN, which
5000 defines or uses REGNO in its insn biggest MODE (we use it only if
5001 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5002 hard registers which might be used for reloads since the EBB end.
5003 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5004 uid before starting INSN processing. Return true if we succeed in
5005 such transformation. */
5007 split_if_necessary (int regno
, machine_mode mode
,
5008 HARD_REG_SET potential_reload_hard_regs
,
5009 bool before_p
, rtx_insn
*insn
, int max_uid
)
5013 rtx next_usage_insns
;
5015 if (regno
< FIRST_PSEUDO_REGISTER
)
5016 nregs
= hard_regno_nregs
[regno
][mode
];
5017 for (i
= 0; i
< nregs
; i
++)
5018 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5019 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5020 /* To avoid processing the register twice or more. */
5021 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5022 && INSN_UID (next_usage_insns
) < max_uid
)
5023 || (GET_CODE (next_usage_insns
) == INSN_LIST
5024 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5025 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5026 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5031 /* Check only registers living at the current program point in the
5033 static bitmap_head live_regs
;
5035 /* Update live info in EBB given by its HEAD and TAIL insns after
5036 inheritance/split transformation. The function removes dead moves
5039 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5044 rtx_insn
*prev_insn
;
5047 basic_block last_bb
, prev_bb
, curr_bb
;
5049 struct lra_insn_reg
*reg
;
5053 last_bb
= BLOCK_FOR_INSN (tail
);
5055 for (curr_insn
= tail
;
5056 curr_insn
!= PREV_INSN (head
);
5057 curr_insn
= prev_insn
)
5059 prev_insn
= PREV_INSN (curr_insn
);
5060 /* We need to process empty blocks too. They contain
5061 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5062 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5064 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5065 if (curr_bb
!= prev_bb
)
5067 if (prev_bb
!= NULL
)
5069 /* Update df_get_live_in (prev_bb): */
5070 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5071 if (bitmap_bit_p (&live_regs
, j
))
5072 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5074 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5076 if (curr_bb
!= last_bb
)
5078 /* Update df_get_live_out (curr_bb): */
5079 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5081 live_p
= bitmap_bit_p (&live_regs
, j
);
5083 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5084 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5090 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5092 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5096 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5098 if (! NONDEBUG_INSN_P (curr_insn
))
5100 curr_id
= lra_get_insn_recog_data (curr_insn
);
5101 curr_static_id
= curr_id
->insn_static_data
;
5103 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
5104 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5105 && bitmap_bit_p (&check_only_regs
, regno
)
5106 && ! bitmap_bit_p (&live_regs
, regno
))
5108 /* See which defined values die here. */
5109 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5110 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5111 bitmap_clear_bit (&live_regs
, reg
->regno
);
5112 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5113 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5114 bitmap_clear_bit (&live_regs
, reg
->regno
);
5115 /* Mark each used value as live. */
5116 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5117 if (reg
->type
!= OP_OUT
5118 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5119 bitmap_set_bit (&live_regs
, reg
->regno
);
5120 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5121 if (reg
->type
!= OP_OUT
5122 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5123 bitmap_set_bit (&live_regs
, reg
->regno
);
5124 if (curr_id
->arg_hard_regs
!= NULL
)
5125 /* Make argument hard registers live. */
5126 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5127 if (bitmap_bit_p (&check_only_regs
, regno
))
5128 bitmap_set_bit (&live_regs
, regno
);
5129 /* It is quite important to remove dead move insns because it
5130 means removing dead store. We don't need to process them for
5134 if (lra_dump_file
!= NULL
)
5136 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5137 dump_insn_slim (lra_dump_file
, curr_insn
);
5139 lra_set_insn_deleted (curr_insn
);
5144 /* The structure describes info to do an inheritance for the current
5145 insn. We need to collect such info first before doing the
5146 transformations because the transformations change the insn
5147 internal representation. */
5150 /* Original regno. */
5152 /* Subsequent insns which can inherit original reg value. */
5156 /* Array containing all info for doing inheritance from the current
5158 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5160 /* Number elements in the previous array. */
5161 static int to_inherit_num
;
5163 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5164 structure to_inherit. */
5166 add_to_inherit (int regno
, rtx insns
)
5170 for (i
= 0; i
< to_inherit_num
; i
++)
5171 if (to_inherit
[i
].regno
== regno
)
5173 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5174 to_inherit
[to_inherit_num
].regno
= regno
;
5175 to_inherit
[to_inherit_num
++].insns
= insns
;
5178 /* Return the last non-debug insn in basic block BB, or the block begin
5181 get_last_insertion_point (basic_block bb
)
5185 FOR_BB_INSNS_REVERSE (bb
, insn
)
5186 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5191 /* Set up RES by registers living on edges FROM except the edge (FROM,
5192 TO) or by registers set up in a jump insn in BB FROM. */
5194 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5197 struct lra_insn_reg
*reg
;
5201 lra_assert (to
!= NULL
);
5203 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5205 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5206 last
= get_last_insertion_point (from
);
5207 if (! JUMP_P (last
))
5209 curr_id
= lra_get_insn_recog_data (last
);
5210 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5211 if (reg
->type
!= OP_IN
)
5212 bitmap_set_bit (res
, reg
->regno
);
5215 /* Used as a temporary results of some bitmap calculations. */
5216 static bitmap_head temp_bitmap
;
5218 /* We split for reloads of small class of hard regs. The following
5219 defines how many hard regs the class should have to be qualified as
5220 small. The code is mostly oriented to x86/x86-64 architecture
5221 where some insns need to use only specific register or pair of
5222 registers and these register can live in RTL explicitly, e.g. for
5223 parameter passing. */
5224 static const int max_small_class_regs_num
= 2;
5226 /* Do inheritance/split transformations in EBB starting with HEAD and
5227 finishing on TAIL. We process EBB insns in the reverse order.
5228 Return true if we did any inheritance/split transformation in the
5231 We should avoid excessive splitting which results in worse code
5232 because of inaccurate cost calculations for spilling new split
5233 pseudos in such case. To achieve this we do splitting only if
5234 register pressure is high in given basic block and there are reload
5235 pseudos requiring hard registers. We could do more register
5236 pressure calculations at any given program point to avoid necessary
5237 splitting even more but it is to expensive and the current approach
5238 works well enough. */
5240 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
5242 int i
, src_regno
, dst_regno
, nregs
;
5243 bool change_p
, succ_p
, update_reloads_num_p
;
5244 rtx_insn
*prev_insn
, *last_insn
;
5245 rtx next_usage_insns
, set
;
5247 struct lra_insn_reg
*reg
;
5248 basic_block last_processed_bb
, curr_bb
= NULL
;
5249 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5253 bool head_p
, after_p
;
5256 curr_usage_insns_check
++;
5257 reloads_num
= calls_num
= 0;
5258 bitmap_clear (&check_only_regs
);
5259 last_processed_bb
= NULL
;
5260 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5261 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5262 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5263 /* We don't process new insns generated in the loop. */
5264 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5266 prev_insn
= PREV_INSN (curr_insn
);
5267 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5268 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5269 if (last_processed_bb
!= curr_bb
)
5271 /* We are at the end of BB. Add qualified living
5272 pseudos for potential splitting. */
5273 to_process
= df_get_live_out (curr_bb
);
5274 if (last_processed_bb
!= NULL
)
5276 /* We are somewhere in the middle of EBB. */
5277 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5279 to_process
= &temp_bitmap
;
5281 last_processed_bb
= curr_bb
;
5282 last_insn
= get_last_insertion_point (curr_bb
);
5283 after_p
= (! JUMP_P (last_insn
)
5284 && (! CALL_P (last_insn
)
5285 || (find_reg_note (last_insn
,
5286 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5287 && ! SIBLING_CALL_P (last_insn
))));
5288 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5289 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5291 if ((int) j
>= lra_constraint_new_regno_start
)
5293 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5295 if (j
< FIRST_PSEUDO_REGISTER
)
5296 SET_HARD_REG_BIT (live_hard_regs
, j
);
5298 add_to_hard_reg_set (&live_hard_regs
,
5299 PSEUDO_REGNO_MODE (j
),
5301 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5305 src_regno
= dst_regno
= -1;
5306 if (NONDEBUG_INSN_P (curr_insn
)
5307 && (set
= single_set (curr_insn
)) != NULL_RTX
5308 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5310 src_regno
= REGNO (SET_SRC (set
));
5311 dst_regno
= REGNO (SET_DEST (set
));
5313 update_reloads_num_p
= true;
5314 if (src_regno
< lra_constraint_new_regno_start
5315 && src_regno
>= FIRST_PSEUDO_REGISTER
5316 && reg_renumber
[src_regno
] < 0
5317 && dst_regno
>= lra_constraint_new_regno_start
5318 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5320 /* 'reload_pseudo <- original_pseudo'. */
5321 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5323 update_reloads_num_p
= false;
5325 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5326 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5327 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5328 curr_insn
, next_usage_insns
);
5332 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5333 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5334 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5335 reg_class_contents
[cl
]);
5337 else if (src_regno
>= lra_constraint_new_regno_start
5338 && dst_regno
< lra_constraint_new_regno_start
5339 && dst_regno
>= FIRST_PSEUDO_REGISTER
5340 && reg_renumber
[dst_regno
] < 0
5341 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5342 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5343 && (next_usage_insns
5344 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5346 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5348 update_reloads_num_p
= false;
5349 /* 'original_pseudo <- reload_pseudo'. */
5350 if (! JUMP_P (curr_insn
)
5351 && inherit_reload_reg (true, dst_regno
, cl
,
5352 curr_insn
, next_usage_insns
))
5355 usage_insns
[dst_regno
].check
= 0;
5356 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5357 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5358 reg_class_contents
[cl
]);
5360 else if (INSN_P (curr_insn
))
5363 int max_uid
= get_max_uid ();
5365 curr_id
= lra_get_insn_recog_data (curr_insn
);
5366 curr_static_id
= curr_id
->insn_static_data
;
5368 /* Process insn definitions. */
5369 for (iter
= 0; iter
< 2; iter
++)
5370 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5373 if (reg
->type
!= OP_IN
5374 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5376 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5377 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5378 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5379 && (next_usage_insns
5380 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5382 struct lra_insn_reg
*r
;
5384 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5385 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5387 /* Don't do inheritance if the pseudo is also
5388 used in the insn. */
5390 /* We can not do inheritance right now
5391 because the current insn reg info (chain
5392 regs) can change after that. */
5393 add_to_inherit (dst_regno
, next_usage_insns
);
5395 /* We can not process one reg twice here because of
5396 usage_insns invalidation. */
5397 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5398 || reg_renumber
[dst_regno
] >= 0)
5399 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5403 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5404 potential_reload_hard_regs
,
5405 false, curr_insn
, max_uid
))
5407 CLEAR_HARD_REG_SET (s
);
5408 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5409 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5411 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5412 reg_renumber
[dst_regno
]);
5413 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5415 /* We should invalidate potential inheritance or
5416 splitting for the current insn usages to the next
5417 usage insns (see code below) as the output pseudo
5419 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5420 && reg_renumber
[dst_regno
] < 0)
5421 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5422 && (dst_regno
< FIRST_PSEUDO_REGISTER
5423 || reg_renumber
[dst_regno
] >= 0)))
5425 /* Invalidate and mark definitions. */
5426 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5427 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5430 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5431 for (i
= 0; i
< nregs
; i
++)
5432 usage_insns
[dst_regno
+ i
].check
5433 = -(int) INSN_UID (curr_insn
);
5437 if (! JUMP_P (curr_insn
))
5438 for (i
= 0; i
< to_inherit_num
; i
++)
5439 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5440 ALL_REGS
, curr_insn
,
5441 to_inherit
[i
].insns
))
5443 if (CALL_P (curr_insn
))
5445 rtx cheap
, pat
, dest
;
5447 int regno
, hard_regno
;
5450 if ((cheap
= find_reg_note (curr_insn
,
5451 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5452 && ((cheap
= XEXP (cheap
, 0)), true)
5453 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5454 && (hard_regno
= reg_renumber
[regno
]) >= 0
5455 /* If there are pending saves/restores, the
5456 optimization is not worth. */
5457 && usage_insns
[regno
].calls_num
== calls_num
- 1
5458 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5460 /* Restore the pseudo from the call result as
5461 REG_RETURNED note says that the pseudo value is
5462 in the call result and the pseudo is an argument
5464 pat
= PATTERN (curr_insn
);
5465 if (GET_CODE (pat
) == PARALLEL
)
5466 pat
= XVECEXP (pat
, 0, 0);
5467 dest
= SET_DEST (pat
);
5468 /* For multiple return values dest is PARALLEL.
5469 Currently we handle only single return value case. */
5473 emit_move_insn (cheap
, copy_rtx (dest
));
5474 restore
= get_insns ();
5476 lra_process_new_insns (curr_insn
, NULL
, restore
,
5477 "Inserting call parameter restore");
5478 /* We don't need to save/restore of the pseudo from
5480 usage_insns
[regno
].calls_num
= calls_num
;
5481 bitmap_set_bit (&check_only_regs
, regno
);
5486 /* Process insn usages. */
5487 for (iter
= 0; iter
< 2; iter
++)
5488 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5491 if ((reg
->type
!= OP_OUT
5492 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5493 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5495 if (src_regno
>= FIRST_PSEUDO_REGISTER
5496 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5498 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5499 && (next_usage_insns
5500 = usage_insns
[src_regno
].insns
) != NULL_RTX
5501 && NONDEBUG_INSN_P (curr_insn
))
5502 add_to_inherit (src_regno
, next_usage_insns
);
5503 else if (usage_insns
[src_regno
].check
5504 != -(int) INSN_UID (curr_insn
))
5505 /* Add usages but only if the reg is not set up
5506 in the same insn. */
5507 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5509 else if (src_regno
< FIRST_PSEUDO_REGISTER
5510 || reg_renumber
[src_regno
] >= 0)
5513 rtx use_insn
= curr_insn
;
5515 before_p
= (JUMP_P (curr_insn
)
5516 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5517 if (NONDEBUG_INSN_P (curr_insn
)
5518 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5519 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5520 potential_reload_hard_regs
,
5521 before_p
, curr_insn
, max_uid
))
5524 lra_risky_transformations_p
= true;
5527 usage_insns
[src_regno
].check
= 0;
5529 use_insn
= PREV_INSN (curr_insn
);
5531 if (NONDEBUG_INSN_P (curr_insn
))
5533 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5534 add_to_hard_reg_set (&live_hard_regs
,
5535 reg
->biggest_mode
, src_regno
);
5537 add_to_hard_reg_set (&live_hard_regs
,
5538 PSEUDO_REGNO_MODE (src_regno
),
5539 reg_renumber
[src_regno
]);
5541 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5544 /* Process call args. */
5545 if (curr_id
->arg_hard_regs
!= NULL
)
5546 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5547 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5549 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5550 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5552 for (i
= 0; i
< to_inherit_num
; i
++)
5554 src_regno
= to_inherit
[i
].regno
;
5555 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5556 curr_insn
, to_inherit
[i
].insns
))
5559 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5562 if (update_reloads_num_p
5563 && NONDEBUG_INSN_P (curr_insn
)
5564 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5567 if ((REG_P (SET_DEST (set
))
5568 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5569 && reg_renumber
[regno
] < 0
5570 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5571 || (REG_P (SET_SRC (set
))
5572 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5573 && reg_renumber
[regno
] < 0
5574 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5576 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5578 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5579 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5580 reg_class_contents
[cl
]);
5583 /* We reached the start of the current basic block. */
5584 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5585 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5587 /* We reached the beginning of the current block -- do
5588 rest of spliting in the current BB. */
5589 to_process
= df_get_live_in (curr_bb
);
5590 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5592 /* We are somewhere in the middle of EBB. */
5593 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5594 curr_bb
, &temp_bitmap
);
5595 to_process
= &temp_bitmap
;
5598 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5600 if ((int) j
>= lra_constraint_new_regno_start
)
5602 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5603 && usage_insns
[j
].check
== curr_usage_insns_check
5604 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5606 if (need_for_split_p (potential_reload_hard_regs
, j
))
5608 if (lra_dump_file
!= NULL
&& head_p
)
5610 fprintf (lra_dump_file
,
5611 " ----------------------------------\n");
5614 if (split_reg (false, j
, bb_note (curr_bb
),
5618 usage_insns
[j
].check
= 0;
5626 /* This value affects EBB forming. If probability of edge from EBB to
5627 a BB is not greater than the following value, we don't add the BB
5629 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5631 /* Current number of inheritance/split iteration. */
5632 int lra_inheritance_iter
;
5634 /* Entry function for inheritance/split pass. */
5636 lra_inheritance (void)
5639 basic_block bb
, start_bb
;
5642 lra_inheritance_iter
++;
5643 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5645 timevar_push (TV_LRA_INHERITANCE
);
5646 if (lra_dump_file
!= NULL
)
5647 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5648 lra_inheritance_iter
);
5649 curr_usage_insns_check
= 0;
5650 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5651 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5652 usage_insns
[i
].check
= 0;
5653 bitmap_initialize (&check_only_regs
, ®_obstack
);
5654 bitmap_initialize (&live_regs
, ®_obstack
);
5655 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5656 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5657 FOR_EACH_BB_FN (bb
, cfun
)
5660 if (lra_dump_file
!= NULL
)
5661 fprintf (lra_dump_file
, "EBB");
5662 /* Form a EBB starting with BB. */
5663 bitmap_clear (&ebb_global_regs
);
5664 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5667 if (lra_dump_file
!= NULL
)
5668 fprintf (lra_dump_file
, " %d", bb
->index
);
5669 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5670 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5672 e
= find_fallthru_edge (bb
->succs
);
5675 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5679 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5680 if (lra_dump_file
!= NULL
)
5681 fprintf (lra_dump_file
, "\n");
5682 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5683 /* Remember that the EBB head and tail can change in
5685 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5687 bitmap_clear (&ebb_global_regs
);
5688 bitmap_clear (&temp_bitmap
);
5689 bitmap_clear (&live_regs
);
5690 bitmap_clear (&check_only_regs
);
5693 timevar_pop (TV_LRA_INHERITANCE
);
5698 /* This page contains code to undo failed inheritance/split
5701 /* Current number of iteration undoing inheritance/split. */
5702 int lra_undo_inheritance_iter
;
5704 /* Fix BB live info LIVE after removing pseudos created on pass doing
5705 inheritance/split which are REMOVED_PSEUDOS. */
5707 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5712 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5713 if (bitmap_clear_bit (live
, regno
))
5714 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5717 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5722 if (GET_CODE (reg
) == SUBREG
)
5723 reg
= SUBREG_REG (reg
);
5729 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5730 return true if we did any change. The undo transformations for
5731 inheritance looks like
5735 p <- i, i <- p, and i <- i3
5736 where p is original pseudo from which inheritance pseudo i was
5737 created, i and i3 are removed inheritance pseudos, i2 is another
5738 not removed inheritance pseudo. All split pseudos or other
5739 occurrences of removed inheritance pseudos are changed on the
5740 corresponding original pseudos.
5742 The function also schedules insns changed and created during
5743 inheritance/split pass for processing by the subsequent constraint
5746 remove_inheritance_pseudos (bitmap remove_pseudos
)
5749 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5751 rtx_insn
*prev_insn
;
5752 bool change_p
, done_p
;
5754 change_p
= ! bitmap_empty_p (remove_pseudos
);
5755 /* We can not finish the function right away if CHANGE_P is true
5756 because we need to marks insns affected by previous
5757 inheritance/split pass for processing by the subsequent
5759 FOR_EACH_BB_FN (bb
, cfun
)
5761 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5762 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5763 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5765 if (! INSN_P (curr_insn
))
5768 sregno
= dregno
= -1;
5769 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5770 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5772 dregno
= get_regno (SET_DEST (set
));
5773 sregno
= get_regno (SET_SRC (set
));
5776 if (sregno
>= 0 && dregno
>= 0)
5778 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5779 && (lra_reg_info
[sregno
].restore_regno
== dregno
5780 || (bitmap_bit_p (remove_pseudos
, dregno
)
5781 && (lra_reg_info
[sregno
].restore_regno
5782 == lra_reg_info
[dregno
].restore_regno
))))
5783 || (bitmap_bit_p (remove_pseudos
, dregno
)
5784 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5785 /* One of the following cases:
5786 original <- removed inheritance pseudo
5787 removed inherit pseudo <- another removed inherit pseudo
5788 removed inherit pseudo <- original pseudo
5790 removed_split_pseudo <- original_reg
5791 original_reg <- removed_split_pseudo */
5793 if (lra_dump_file
!= NULL
)
5795 fprintf (lra_dump_file
, " Removing %s:\n",
5796 bitmap_bit_p (&lra_split_regs
, sregno
)
5797 || bitmap_bit_p (&lra_split_regs
, dregno
)
5798 ? "split" : "inheritance");
5799 dump_insn_slim (lra_dump_file
, curr_insn
);
5801 lra_set_insn_deleted (curr_insn
);
5804 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5805 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5807 /* Search the following pattern:
5808 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5809 original_pseudo <- inherit_or_split_pseudo1
5810 where the 2nd insn is the current insn and
5811 inherit_or_split_pseudo2 is not removed. If it is found,
5812 change the current insn onto:
5813 original_pseudo <- inherit_or_split_pseudo2. */
5814 for (prev_insn
= PREV_INSN (curr_insn
);
5815 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5816 prev_insn
= PREV_INSN (prev_insn
))
5818 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5819 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5820 /* There should be no subregs in insn we are
5821 searching because only the original reg might
5822 be in subreg when we changed the mode of
5823 load/store for splitting. */
5824 && REG_P (SET_DEST (prev_set
))
5825 && REG_P (SET_SRC (prev_set
))
5826 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5827 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5828 >= FIRST_PSEUDO_REGISTER
)
5829 /* As we consider chain of inheritance or
5830 splitting described in above comment we should
5831 check that sregno and prev_sregno were
5832 inheritance/split pseudos created from the
5833 same original regno. */
5834 && (lra_reg_info
[sregno
].restore_regno
5835 == lra_reg_info
[prev_sregno
].restore_regno
)
5836 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5838 lra_assert (GET_MODE (SET_SRC (prev_set
))
5839 == GET_MODE (regno_reg_rtx
[sregno
]));
5840 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5841 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5843 SET_SRC (set
) = SET_SRC (prev_set
);
5844 /* As we are finishing with processing the insn
5845 here, check the destination too as it might
5846 inheritance pseudo for another pseudo. */
5847 if (bitmap_bit_p (remove_pseudos
, dregno
)
5848 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
5850 = lra_reg_info
[dregno
].restore_regno
) >= 0)
5852 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
5853 SUBREG_REG (SET_DEST (set
))
5854 = regno_reg_rtx
[restore_regno
];
5856 SET_DEST (set
) = regno_reg_rtx
[restore_regno
];
5858 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5859 lra_set_used_insn_alternative_by_uid
5860 (INSN_UID (curr_insn
), -1);
5862 if (lra_dump_file
!= NULL
)
5864 fprintf (lra_dump_file
, " Change reload insn:\n");
5865 dump_insn_slim (lra_dump_file
, curr_insn
);
5872 struct lra_insn_reg
*reg
;
5873 bool restored_regs_p
= false;
5874 bool kept_regs_p
= false;
5876 curr_id
= lra_get_insn_recog_data (curr_insn
);
5877 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5880 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5881 if (restore_regno
>= 0)
5883 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5885 lra_substitute_pseudo_within_insn (
5886 curr_insn
, regno
, regno_reg_rtx
[restore_regno
]);
5887 restored_regs_p
= true;
5893 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5895 /* The instruction has changed since the previous
5896 constraints pass. */
5897 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5898 lra_set_used_insn_alternative_by_uid
5899 (INSN_UID (curr_insn
), -1);
5901 else if (restored_regs_p
)
5902 /* The instruction has been restored to the form that
5903 it had during the previous constraints pass. */
5904 lra_update_insn_regno_info (curr_insn
);
5905 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5907 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5908 dump_insn_slim (lra_dump_file
, curr_insn
);
5916 /* If optional reload pseudos failed to get a hard register or was not
5917 inherited, it is better to remove optional reloads. We do this
5918 transformation after undoing inheritance to figure out necessity to
5919 remove optional reloads easier. Return true if we do any
5922 undo_optional_reloads (void)
5924 bool change_p
, keep_p
;
5925 unsigned int regno
, uid
;
5926 bitmap_iterator bi
, bi2
;
5929 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5931 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5932 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5933 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5936 /* Keep optional reloads from previous subpasses. */
5937 if (lra_reg_info
[regno
].restore_regno
< 0
5938 /* If the original pseudo changed its allocation, just
5939 removing the optional pseudo is dangerous as the original
5940 pseudo will have longer live range. */
5941 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5943 else if (reg_renumber
[regno
] >= 0)
5944 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5946 insn
= lra_insn_recog_data
[uid
]->insn
;
5947 if ((set
= single_set (insn
)) == NULL_RTX
)
5949 src
= SET_SRC (set
);
5950 dest
= SET_DEST (set
);
5951 if (! REG_P (src
) || ! REG_P (dest
))
5953 if (REGNO (dest
) == regno
5954 /* Ignore insn for optional reloads itself. */
5955 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5956 /* Check only inheritance on last inheritance pass. */
5957 && (int) REGNO (src
) >= new_regno_start
5958 /* Check that the optional reload was inherited. */
5959 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5967 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5968 if (lra_dump_file
!= NULL
)
5969 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5972 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5973 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5974 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5976 if (lra_dump_file
!= NULL
)
5977 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5978 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5979 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5981 insn
= lra_insn_recog_data
[uid
]->insn
;
5982 if ((set
= single_set (insn
)) != NULL_RTX
)
5984 src
= SET_SRC (set
);
5985 dest
= SET_DEST (set
);
5986 if (REG_P (src
) && REG_P (dest
)
5987 && ((REGNO (src
) == regno
5988 && (lra_reg_info
[regno
].restore_regno
5989 == (int) REGNO (dest
)))
5990 || (REGNO (dest
) == regno
5991 && (lra_reg_info
[regno
].restore_regno
5992 == (int) REGNO (src
)))))
5994 if (lra_dump_file
!= NULL
)
5996 fprintf (lra_dump_file
, " Deleting move %u\n",
5998 dump_insn_slim (lra_dump_file
, insn
);
6000 lra_set_insn_deleted (insn
);
6003 /* We should not worry about generation memory-memory
6004 moves here as if the corresponding inheritance did
6005 not work (inheritance pseudo did not get a hard reg),
6006 we remove the inheritance pseudo and the optional
6009 lra_substitute_pseudo_within_insn (
6011 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
6012 lra_update_insn_regno_info (insn
);
6013 if (lra_dump_file
!= NULL
)
6015 fprintf (lra_dump_file
,
6016 " Restoring original insn:\n");
6017 dump_insn_slim (lra_dump_file
, insn
);
6021 /* Clear restore_regnos. */
6022 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6023 lra_reg_info
[regno
].restore_regno
= -1;
6024 bitmap_clear (&insn_bitmap
);
6025 bitmap_clear (&removed_optional_reload_pseudos
);
6029 /* Entry function for undoing inheritance/split transformation. Return true
6030 if we did any RTL change in this pass. */
6032 lra_undo_inheritance (void)
6035 int restore_regno
, hard_regno
;
6036 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6037 bitmap_head remove_pseudos
;
6041 lra_undo_inheritance_iter
++;
6042 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6044 if (lra_dump_file
!= NULL
)
6045 fprintf (lra_dump_file
,
6046 "\n********** Undoing inheritance #%d: **********\n\n",
6047 lra_undo_inheritance_iter
);
6048 bitmap_initialize (&remove_pseudos
, ®_obstack
);
6049 n_inherit
= n_all_inherit
= 0;
6050 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6051 if (lra_reg_info
[regno
].restore_regno
>= 0)
6054 if (reg_renumber
[regno
] < 0
6055 /* If the original pseudo changed its allocation, just
6056 removing inheritance is dangerous as for changing
6057 allocation we used shorter live-ranges. */
6058 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
6059 bitmap_set_bit (&remove_pseudos
, regno
);
6063 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6064 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6065 n_inherit
, n_all_inherit
,
6066 (double) n_inherit
/ n_all_inherit
* 100);
6067 n_split
= n_all_split
= 0;
6068 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6069 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
6072 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6073 ? reg_renumber
[restore_regno
] : restore_regno
);
6074 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6075 bitmap_set_bit (&remove_pseudos
, regno
);
6079 if (lra_dump_file
!= NULL
)
6080 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6081 regno
, restore_regno
);
6084 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6085 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6086 n_split
, n_all_split
,
6087 (double) n_split
/ n_all_split
* 100);
6088 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
6089 bitmap_clear (&remove_pseudos
);
6090 /* Clear restore_regnos. */
6091 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6092 lra_reg_info
[regno
].restore_regno
= -1;
6093 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6094 lra_reg_info
[regno
].restore_regno
= -1;
6095 change_p
= undo_optional_reloads () || change_p
;