1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2020 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
132 #include "print-rtl.h"
133 #include "function-abi.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 /* If we have non-legitimate address which is decomposed not in
363 the way we expected, don't do elimination here. In such case
364 the address will be reloaded and elimination will be done in
365 reload insn finally. */
366 if (REG_P (m_base_reg
))
367 lra_eliminate_reg_if_possible (m_base_loc
);
368 if (m_ad
->base_term2
!= NULL
)
369 *m_ad
->base_term2
= *m_ad
->base_term
;
371 if (m_index_loc
!= NULL
)
373 m_index_reg
= *m_index_loc
;
374 if (REG_P (m_index_reg
))
375 lra_eliminate_reg_if_possible (m_index_loc
);
379 address_eliminator::~address_eliminator ()
381 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
383 *m_base_loc
= m_base_reg
;
384 if (m_ad
->base_term2
!= NULL
)
385 *m_ad
->base_term2
= *m_ad
->base_term
;
387 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
388 *m_index_loc
= m_index_reg
;
391 /* Return true if the eliminated form of AD is a legitimate target address.
392 If OP is a MEM, AD is the address within OP, otherwise OP should be
393 ignored. CONSTRAINT is one constraint that the operand may need
396 valid_address_p (rtx op
, struct address_info
*ad
,
397 enum constraint_num constraint
)
399 address_eliminator
eliminator (ad
);
401 /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more
402 forgiving than "m". */
404 && (insn_extra_memory_constraint (constraint
)
405 || insn_extra_special_memory_constraint (constraint
))
406 && constraint_satisfied_p (op
, constraint
))
409 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
412 /* Return true if the eliminated form of memory reference OP satisfies
413 extra (special) memory constraint CONSTRAINT. */
415 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
417 struct address_info ad
;
419 decompose_mem_address (&ad
, op
);
420 address_eliminator
eliminator (&ad
);
421 return constraint_satisfied_p (op
, constraint
);
424 /* Return true if the eliminated form of address AD satisfies extra
425 address constraint CONSTRAINT. */
427 satisfies_address_constraint_p (struct address_info
*ad
,
428 enum constraint_num constraint
)
430 address_eliminator
eliminator (ad
);
431 return constraint_satisfied_p (*ad
->outer
, constraint
);
434 /* Return true if the eliminated form of address OP satisfies extra
435 address constraint CONSTRAINT. */
437 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
439 struct address_info ad
;
441 decompose_lea_address (&ad
, &op
);
442 return satisfies_address_constraint_p (&ad
, constraint
);
445 /* Initiate equivalences for LRA. As we keep original equivalences
446 before any elimination, we need to make copies otherwise any change
447 in insns might change the equivalences. */
449 lra_init_equiv (void)
451 ira_expand_reg_equiv ();
452 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
456 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
457 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
458 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
459 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
463 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
465 /* Update equivalence for REGNO. We need to this as the equivalence
466 might contain other pseudos which are changed by their
469 update_equiv (int regno
)
473 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
474 ira_reg_equiv
[regno
].memory
475 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
477 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
478 ira_reg_equiv
[regno
].invariant
479 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
483 /* If we have decided to substitute X with another value, return that
484 value, otherwise return X. */
491 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
492 || ! ira_reg_equiv
[regno
].defined_p
493 || ! ira_reg_equiv
[regno
].profitable_p
494 || lra_get_regno_hard_regno (regno
) >= 0)
496 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
498 if (targetm
.cannot_substitute_mem_equiv_p (res
))
502 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
504 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
509 /* If we have decided to substitute X with the equivalent value,
510 return that value after elimination for INSN, otherwise return
513 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
515 rtx res
= get_equiv (x
);
517 if (x
== res
|| CONSTANT_P (res
))
519 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
520 false, false, 0, true);
523 /* Set up curr_operand_mode. */
525 init_curr_operand_mode (void)
527 int nop
= curr_static_id
->n_operands
;
528 for (int i
= 0; i
< nop
; i
++)
530 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
531 if (mode
== VOIDmode
)
533 /* The .md mode for address operands is the mode of the
534 addressed value rather than the mode of the address itself. */
535 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
538 mode
= curr_static_id
->operand
[i
].mode
;
540 curr_operand_mode
[i
] = mode
;
546 /* The page contains code to reuse input reloads. */
548 /* Structure describes input reload of the current insns. */
551 /* True for input reload of matched operands. */
553 /* Reloaded value. */
555 /* Reload pseudo used. */
559 /* The number of elements in the following array. */
560 static int curr_insn_input_reloads_num
;
561 /* Array containing info about input reloads. It is used to find the
562 same input reload and reuse the reload pseudo in this case. */
563 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
565 /* Initiate data concerning reuse of input reloads for the current
568 init_curr_insn_input_reloads (void)
570 curr_insn_input_reloads_num
= 0;
573 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
574 created input reload pseudo (only if TYPE is not OP_OUT). Don't
575 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
576 wrapped up in SUBREG. The result pseudo is returned through
577 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
578 reused the already created input reload pseudo. Use TITLE to
579 describe new registers for debug purposes. */
581 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
582 enum reg_class rclass
, bool in_subreg_p
,
583 const char *title
, rtx
*result_reg
)
586 enum reg_class new_class
;
587 bool unique_p
= false;
592 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
595 /* Prevent reuse value of expression with side effects,
596 e.g. volatile memory. */
597 if (! side_effects_p (original
))
598 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
600 if (! curr_insn_input_reloads
[i
].match_p
601 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
602 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
604 rtx reg
= curr_insn_input_reloads
[i
].reg
;
606 /* If input is equal to original and both are VOIDmode,
607 GET_MODE (reg) might be still different from mode.
608 Ensure we don't return *result_reg with wrong mode. */
609 if (GET_MODE (reg
) != mode
)
613 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg
)),
614 GET_MODE_SIZE (mode
)))
616 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
617 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
621 if (lra_dump_file
!= NULL
)
623 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
624 dump_value_slim (lra_dump_file
, original
, 1);
626 if (new_class
!= lra_get_allocno_class (regno
))
627 lra_change_class (regno
, new_class
, ", change to", false);
628 if (lra_dump_file
!= NULL
)
629 fprintf (lra_dump_file
, "\n");
632 /* If we have an input reload with a different mode, make sure it
633 will get a different hard reg. */
634 else if (REG_P (original
)
635 && REG_P (curr_insn_input_reloads
[i
].input
)
636 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
637 && (GET_MODE (original
)
638 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
641 *result_reg
= (unique_p
642 ? lra_create_new_reg_with_unique_value
643 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
644 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
645 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
646 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
647 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
652 /* The page contains major code to choose the current insn alternative
653 and generate reloads for it. */
655 /* Return the offset from REGNO of the least significant register
658 This function is used to tell whether two registers satisfy
659 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
661 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
662 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
664 lra_constraint_offset (int regno
, machine_mode mode
)
666 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
668 scalar_int_mode int_mode
;
670 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
671 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
672 return hard_regno_nregs (regno
, mode
) - 1;
676 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
677 if they are the same hard reg, and has special hacks for
678 auto-increment and auto-decrement. This is specifically intended for
679 process_alt_operands to use in determining whether two operands
680 match. X is the operand whose number is the lower of the two.
682 It is supposed that X is the output operand and Y is the input
683 operand. Y_HARD_REGNO is the final hard regno of register Y or
684 register in subreg Y as we know it now. Otherwise, it is a
687 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
690 RTX_CODE code
= GET_CODE (x
);
695 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
696 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
700 i
= get_hard_regno (x
, false);
704 if ((j
= y_hard_regno
) < 0)
707 i
+= lra_constraint_offset (i
, GET_MODE (x
));
708 j
+= lra_constraint_offset (j
, GET_MODE (y
));
713 /* If two operands must match, because they are really a single
714 operand of an assembler insn, then two post-increments are invalid
715 because the assembler insn would increment only once. On the
716 other hand, a post-increment matches ordinary indexing if the
717 post-increment is the output operand. */
718 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
719 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
721 /* Two pre-increments are invalid because the assembler insn would
722 increment only once. On the other hand, a pre-increment matches
723 ordinary indexing if the pre-increment is the input operand. */
724 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
725 || GET_CODE (y
) == PRE_MODIFY
)
726 return operands_match_p (x
, XEXP (y
, 0), -1);
730 if (code
== REG
&& REG_P (y
))
731 return REGNO (x
) == REGNO (y
);
733 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
734 && x
== SUBREG_REG (y
))
736 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
737 && SUBREG_REG (x
) == y
)
740 /* Now we have disposed of all the cases in which different rtx
742 if (code
!= GET_CODE (y
))
745 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
746 if (GET_MODE (x
) != GET_MODE (y
))
755 return label_ref_label (x
) == label_ref_label (y
);
757 return XSTR (x
, 0) == XSTR (y
, 0);
763 /* Compare the elements. If any pair of corresponding elements fail
764 to match, return false for the whole things. */
766 fmt
= GET_RTX_FORMAT (code
);
767 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
773 if (XWINT (x
, i
) != XWINT (y
, i
))
778 if (XINT (x
, i
) != XINT (y
, i
))
783 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
788 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
797 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
799 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
801 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
807 /* It is believed that rtx's at this level will never
808 contain anything but integers and other rtx's, except for
809 within LABEL_REFs and SYMBOL_REFs. */
817 /* True if X is a constant that can be forced into the constant pool.
818 MODE is the mode of the operand, or VOIDmode if not known. */
819 #define CONST_POOL_OK_P(MODE, X) \
820 ((MODE) != VOIDmode \
822 && GET_CODE (X) != HIGH \
823 && GET_MODE_SIZE (MODE).is_constant () \
824 && !targetm.cannot_force_const_mem (MODE, X))
826 /* True if C is a non-empty register class that has too few registers
827 to be safely used as a reload target class. */
828 #define SMALL_REGISTER_CLASS_P(C) \
829 (ira_class_hard_regs_num [(C)] == 1 \
830 || (ira_class_hard_regs_num [(C)] >= 1 \
831 && targetm.class_likely_spilled_p (C)))
833 /* If REG is a reload pseudo, try to make its class satisfying CL. */
835 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
837 enum reg_class rclass
;
839 /* Do not make more accurate class from reloads generated. They are
840 mostly moves with a lot of constraints. Making more accurate
841 class may results in very narrow class and impossibility of find
842 registers for several reloads of one insn. */
843 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
845 if (GET_CODE (reg
) == SUBREG
)
846 reg
= SUBREG_REG (reg
);
847 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
849 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
850 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
853 /* Searches X for any reference to a reg with the same value as REGNO,
854 returning the rtx of the reference found if any. Otherwise,
857 regno_val_use_in (unsigned int regno
, rtx x
)
863 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
866 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
867 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
871 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
874 else if (fmt
[i
] == 'E')
875 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
876 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
883 /* Return true if all current insn non-output operands except INS (it
884 has a negaitve end marker) do not use pseudos with the same value
887 check_conflict_input_operands (int regno
, signed char *ins
)
890 int n_operands
= curr_static_id
->n_operands
;
892 for (int nop
= 0; nop
< n_operands
; nop
++)
893 if (! curr_static_id
->operand
[nop
].is_operator
894 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
896 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
900 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
906 /* Generate reloads for matching OUT and INS (array of input operand
907 numbers with end marker -1) with reg class GOAL_CLASS, considering
908 output operands OUTS (similar array to INS) needing to be in different
909 registers. Add input and output reloads correspondingly to the lists
910 *BEFORE and *AFTER. OUT might be negative. In this case we generate
911 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
912 that the output operand is early clobbered for chosen alternative. */
914 match_reload (signed char out
, signed char *ins
, signed char *outs
,
915 enum reg_class goal_class
, rtx_insn
**before
,
916 rtx_insn
**after
, bool early_clobber_p
)
920 rtx new_in_reg
, new_out_reg
, reg
;
921 machine_mode inmode
, outmode
;
922 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
923 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
925 inmode
= curr_operand_mode
[ins
[0]];
926 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
927 push_to_sequence (*before
);
928 if (inmode
!= outmode
)
930 /* process_alt_operands has already checked that the mode sizes
932 if (partial_subreg_p (outmode
, inmode
))
935 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
937 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
938 LRA_SUBREG_P (new_out_reg
) = 1;
939 /* If the input reg is dying here, we can use the same hard
940 register for REG and IN_RTX. We do it only for original
941 pseudos as reload pseudos can die although original
942 pseudos still live where reload pseudos dies. */
943 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
944 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
946 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
947 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
952 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
954 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
955 /* NEW_IN_REG is non-paradoxical subreg. We don't want
956 NEW_OUT_REG living above. We add clobber clause for
957 this. This is just a temporary clobber. We can remove
958 it at the end of LRA work. */
959 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
960 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
961 LRA_SUBREG_P (new_in_reg
) = 1;
962 if (GET_CODE (in_rtx
) == SUBREG
)
964 rtx subreg_reg
= SUBREG_REG (in_rtx
);
966 /* If SUBREG_REG is dying here and sub-registers IN_RTX
967 and NEW_IN_REG are similar, we can use the same hard
968 register for REG and SUBREG_REG. */
969 if (REG_P (subreg_reg
)
970 && (int) REGNO (subreg_reg
) < lra_new_regno_start
971 && GET_MODE (subreg_reg
) == outmode
972 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
973 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
974 && (! early_clobber_p
975 || check_conflict_input_operands (REGNO (subreg_reg
),
977 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
983 /* Pseudos have values -- see comments for lra_reg_info.
984 Different pseudos with the same value do not conflict even if
985 they live in the same place. When we create a pseudo we
986 assign value of original pseudo (if any) from which we
987 created the new pseudo. If we create the pseudo from the
988 input pseudo, the new pseudo will have no conflict with the
989 input pseudo which is wrong when the input pseudo lives after
990 the insn and as the new pseudo value is changed by the insn
991 output. Therefore we create the new pseudo from the output
992 except the case when we have single matched dying input
995 We cannot reuse the current output register because we might
996 have a situation like "a <- a op b", where the constraints
997 force the second input operand ("b") to match the output
998 operand ("a"). "b" must then be copied into a new register
999 so that it doesn't clobber the current value of "a".
1001 We cannot use the same value if the output pseudo is
1002 early clobbered or the input pseudo is mentioned in the
1003 output, e.g. as an address part in memory, because
1004 output reload will actually extend the pseudo liveness.
1005 We don't care about eliminable hard regs here as we are
1006 interesting only in pseudos. */
1008 /* Matching input's register value is the same as one of the other
1009 output operand. Output operands in a parallel insn must be in
1010 different registers. */
1011 out_conflict
= false;
1014 for (i
= 0; outs
[i
] >= 0; i
++)
1016 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1017 if (REG_P (other_out_rtx
)
1018 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1021 out_conflict
= true;
1027 new_in_reg
= new_out_reg
1028 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1029 && (int) REGNO (in_rtx
) < lra_new_regno_start
1030 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1031 && (! early_clobber_p
1032 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1034 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1036 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1037 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1040 /* In operand can be got from transformations before processing insn
1041 constraints. One example of such transformations is subreg
1042 reloading (see function simplify_operand_subreg). The new
1043 pseudos created by the transformations might have inaccurate
1044 class (ALL_REGS) and we should make their classes more
1046 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1047 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1048 *before
= get_insns ();
1050 /* Add the new pseudo to consider values of subsequent input reload
1052 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1053 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1054 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1055 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1056 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1057 if (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1058 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]))
1059 *curr_id
->operand_loc
[in
] = new_in_reg
;
1063 (GET_MODE (new_out_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1064 *curr_id
->operand_loc
[in
] = new_out_reg
;
1066 lra_update_dups (curr_id
, ins
);
1069 /* See a comment for the input operand above. */
1070 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1071 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1074 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1076 *after
= get_insns ();
1079 *curr_id
->operand_loc
[out
] = new_out_reg
;
1080 lra_update_dup (curr_id
, out
);
1083 /* Return register class which is union of all reg classes in insn
1084 constraint alternative string starting with P. */
1085 static enum reg_class
1086 reg_class_from_constraints (const char *p
)
1089 enum reg_class op_class
= NO_REGS
;
1092 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1099 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1103 enum constraint_num cn
= lookup_constraint (p
);
1104 enum reg_class cl
= reg_class_for_constraint (cn
);
1107 if (insn_extra_address_constraint (cn
))
1109 = (reg_class_subunion
1110 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1111 ADDRESS
, SCRATCH
)]);
1115 op_class
= reg_class_subunion
[op_class
][cl
];
1118 while ((p
+= len
), c
);
1122 /* If OP is a register, return the class of the register as per
1123 get_reg_class, otherwise return NO_REGS. */
1124 static inline enum reg_class
1125 get_op_class (rtx op
)
1127 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1130 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1131 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1132 SUBREG for VAL to make them equal. */
1134 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1136 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1138 /* Usually size of mem_pseudo is greater than val size but in
1139 rare cases it can be less as it can be defined by target
1140 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1143 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1144 GET_CODE (val
) == SUBREG
1145 ? SUBREG_REG (val
) : val
);
1146 LRA_SUBREG_P (val
) = 1;
1150 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1151 LRA_SUBREG_P (mem_pseudo
) = 1;
1154 return to_p
? gen_move_insn (mem_pseudo
, val
)
1155 : gen_move_insn (val
, mem_pseudo
);
1158 /* Process a special case insn (register move), return true if we
1159 don't need to process it anymore. INSN should be a single set
1160 insn. Set up that RTL was changed through CHANGE_P and that hook
1161 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1164 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1167 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1169 enum reg_class dclass
, sclass
, secondary_class
;
1170 secondary_reload_info sri
;
1172 lra_assert (curr_insn_set
!= NULL_RTX
);
1173 dreg
= dest
= SET_DEST (curr_insn_set
);
1174 sreg
= src
= SET_SRC (curr_insn_set
);
1175 if (GET_CODE (dest
) == SUBREG
)
1176 dreg
= SUBREG_REG (dest
);
1177 if (GET_CODE (src
) == SUBREG
)
1178 sreg
= SUBREG_REG (src
);
1179 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1181 sclass
= dclass
= NO_REGS
;
1183 dclass
= get_reg_class (REGNO (dreg
));
1184 gcc_assert (dclass
< LIM_REG_CLASSES
);
1185 if (dclass
== ALL_REGS
)
1186 /* ALL_REGS is used for new pseudos created by transformations
1187 like reload of SUBREG_REG (see function
1188 simplify_operand_subreg). We don't know their class yet. We
1189 should figure out the class from processing the insn
1190 constraints not in this fast path function. Even if ALL_REGS
1191 were a right class for the pseudo, secondary_... hooks usually
1192 are not define for ALL_REGS. */
1195 sclass
= get_reg_class (REGNO (sreg
));
1196 gcc_assert (sclass
< LIM_REG_CLASSES
);
1197 if (sclass
== ALL_REGS
)
1198 /* See comments above. */
1200 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1202 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1203 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1205 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1210 if (! REG_P (dreg
) || ! REG_P (sreg
))
1212 sri
.prev_sri
= NULL
;
1213 sri
.icode
= CODE_FOR_nothing
;
1215 secondary_class
= NO_REGS
;
1216 /* Set up hard register for a reload pseudo for hook
1217 secondary_reload because some targets just ignore unassigned
1218 pseudos in the hook. */
1219 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1221 dregno
= REGNO (dreg
);
1222 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1226 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1228 sregno
= REGNO (sreg
);
1229 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1233 if (sclass
!= NO_REGS
)
1235 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1236 (reg_class_t
) sclass
,
1237 GET_MODE (src
), &sri
);
1238 if (sclass
== NO_REGS
1239 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1240 && dclass
!= NO_REGS
))
1242 enum reg_class old_sclass
= secondary_class
;
1243 secondary_reload_info old_sri
= sri
;
1245 sri
.prev_sri
= NULL
;
1246 sri
.icode
= CODE_FOR_nothing
;
1249 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1250 (reg_class_t
) dclass
,
1251 GET_MODE (src
), &sri
);
1252 /* Check the target hook consistency. */
1254 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1255 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1256 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1259 reg_renumber
[sregno
] = -1;
1261 reg_renumber
[dregno
] = -1;
1262 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1266 if (secondary_class
!= NO_REGS
)
1267 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1271 if (sri
.icode
== CODE_FOR_nothing
)
1272 lra_emit_move (new_reg
, src
);
1275 enum reg_class scratch_class
;
1277 scratch_class
= (reg_class_from_constraints
1278 (insn_data
[sri
.icode
].operand
[2].constraint
));
1279 scratch_reg
= (lra_create_new_reg_with_unique_value
1280 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1281 scratch_class
, "scratch"));
1282 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1285 before
= get_insns ();
1287 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1288 if (new_reg
!= NULL_RTX
)
1289 SET_SRC (curr_insn_set
) = new_reg
;
1292 if (lra_dump_file
!= NULL
)
1294 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1295 dump_insn_slim (lra_dump_file
, curr_insn
);
1297 lra_set_insn_deleted (curr_insn
);
1303 /* The following data describe the result of process_alt_operands.
1304 The data are used in curr_insn_transform to generate reloads. */
1306 /* The chosen reg classes which should be used for the corresponding
1308 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1309 /* True if the operand should be the same as another operand and that
1310 other operand does not need a reload. */
1311 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1312 /* True if the operand does not need a reload. */
1313 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1314 /* True if the operand can be offsetable memory. */
1315 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1316 /* The number of an operand to which given operand can be matched to. */
1317 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1318 /* The number of elements in the following array. */
1319 static int goal_alt_dont_inherit_ops_num
;
1320 /* Numbers of operands whose reload pseudos should not be inherited. */
1321 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1322 /* True if the insn commutative operands should be swapped. */
1323 static bool goal_alt_swapped
;
1324 /* The chosen insn alternative. */
1325 static int goal_alt_number
;
1327 /* True if the corresponding operand is the result of an equivalence
1329 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1331 /* The following five variables are used to choose the best insn
1332 alternative. They reflect final characteristics of the best
1335 /* Number of necessary reloads and overall cost reflecting the
1336 previous value and other unpleasantness of the best alternative. */
1337 static int best_losers
, best_overall
;
1338 /* Overall number hard registers used for reloads. For example, on
1339 some targets we need 2 general registers to reload DFmode and only
1340 one floating point register. */
1341 static int best_reload_nregs
;
1342 /* Overall number reflecting distances of previous reloading the same
1343 value. The distances are counted from the current BB start. It is
1344 used to improve inheritance chances. */
1345 static int best_reload_sum
;
1347 /* True if the current insn should have no correspondingly input or
1349 static bool no_input_reloads_p
, no_output_reloads_p
;
1351 /* True if we swapped the commutative operands in the current
1353 static int curr_swapped
;
1355 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1356 register of class CL. Add any input reloads to list BEFORE. AFTER
1357 is nonnull if *LOC is an automodified value; handle that case by
1358 adding the required output reloads to list AFTER. Return true if
1359 the RTL was changed.
1361 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1362 register. Return false if the address register is correct. */
1364 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1368 enum reg_class rclass
, new_class
;
1372 bool subreg_p
, before_p
= false;
1374 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1377 reg
= SUBREG_REG (*loc
);
1378 mode
= GET_MODE (reg
);
1380 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1381 between two registers with different classes, but there normally will
1382 be "mov" which transfers element of vector register into the general
1383 register, and this normally will be a subreg which should be reloaded
1384 as a whole. This is particularly likely to be triggered when
1385 -fno-split-wide-types specified. */
1387 || in_class_p (reg
, cl
, &new_class
)
1388 || known_le (GET_MODE_SIZE (mode
), GET_MODE_SIZE (ptr_mode
)))
1389 loc
= &SUBREG_REG (*loc
);
1393 mode
= GET_MODE (reg
);
1398 /* Always reload memory in an address even if the target supports
1400 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1405 regno
= REGNO (reg
);
1406 rclass
= get_reg_class (regno
);
1408 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1410 if (lra_dump_file
!= NULL
)
1412 fprintf (lra_dump_file
,
1413 "Changing pseudo %d in address of insn %u on equiv ",
1414 REGNO (reg
), INSN_UID (curr_insn
));
1415 dump_value_slim (lra_dump_file
, *loc
, 1);
1416 fprintf (lra_dump_file
, "\n");
1418 *loc
= copy_rtx (*loc
);
1420 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1425 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1426 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1429 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1433 lra_change_class (regno
, new_class
, " Change to", true);
1441 push_to_sequence (*before
);
1442 lra_emit_move (new_reg
, reg
);
1443 *before
= get_insns ();
1450 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1452 *after
= get_insns ();
1458 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1459 the insn to be inserted before curr insn. AFTER returns the
1460 the insn to be inserted after curr insn. ORIGREG and NEWREG
1461 are the original reg and new reg for reload. */
1463 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1468 push_to_sequence (*before
);
1469 lra_emit_move (newreg
, origreg
);
1470 *before
= get_insns ();
1476 lra_emit_move (origreg
, newreg
);
1478 *after
= get_insns ();
1483 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1484 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1486 /* Make reloads for subreg in operand NOP with internal subreg mode
1487 REG_MODE, add new reloads for further processing. Return true if
1488 any change was done. */
1490 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1492 int hard_regno
, inner_hard_regno
;
1493 rtx_insn
*before
, *after
;
1494 machine_mode mode
, innermode
;
1496 rtx operand
= *curr_id
->operand_loc
[nop
];
1497 enum reg_class regclass
;
1500 before
= after
= NULL
;
1502 if (GET_CODE (operand
) != SUBREG
)
1505 mode
= GET_MODE (operand
);
1506 reg
= SUBREG_REG (operand
);
1507 innermode
= GET_MODE (reg
);
1508 type
= curr_static_id
->operand
[nop
].type
;
1511 const bool addr_was_valid
1512 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1513 alter_subreg (curr_id
->operand_loc
[nop
], false);
1514 rtx subst
= *curr_id
->operand_loc
[nop
];
1515 lra_assert (MEM_P (subst
));
1516 const bool addr_is_valid
= valid_address_p (GET_MODE (subst
),
1518 MEM_ADDR_SPACE (subst
));
1521 || ((get_constraint_type (lookup_constraint
1522 (curr_static_id
->operand
[nop
].constraint
))
1523 != CT_SPECIAL_MEMORY
)
1524 /* We still can reload address and if the address is
1525 valid, we can remove subreg without reloading its
1527 && valid_address_p (GET_MODE (subst
),
1529 [ira_class_hard_regs
1530 [base_reg_class (GET_MODE (subst
),
1531 MEM_ADDR_SPACE (subst
),
1532 ADDRESS
, SCRATCH
)][0]],
1533 MEM_ADDR_SPACE (subst
))))
1535 /* If we change the address for a paradoxical subreg of memory, the
1536 new address might violate the necessary alignment or the access
1537 might be slow; take this into consideration. We need not worry
1538 about accesses beyond allocated memory for paradoxical memory
1539 subregs as we don't substitute such equiv memory (see processing
1540 equivalences in function lra_constraints) and because for spilled
1541 pseudos we allocate stack memory enough for the biggest
1542 corresponding paradoxical subreg.
1544 However, do not blindly simplify a (subreg (mem ...)) for
1545 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1546 data into a register when the inner is narrower than outer or
1547 missing important data from memory when the inner is wider than
1548 outer. This rule only applies to modes that are no wider than
1551 If valid memory becomes invalid after subreg elimination
1552 and address might be different we still have to reload
1555 if ((! addr_was_valid
1557 || known_eq (GET_MODE_SIZE (mode
), GET_MODE_SIZE (innermode
)))
1558 && !(maybe_ne (GET_MODE_PRECISION (mode
),
1559 GET_MODE_PRECISION (innermode
))
1560 && known_le (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
1561 && known_le (GET_MODE_SIZE (innermode
), UNITS_PER_WORD
)
1562 && WORD_REGISTER_OPERATIONS
)
1563 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1564 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1565 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1566 && targetm
.slow_unaligned_access (innermode
,
1570 *curr_id
->operand_loc
[nop
] = operand
;
1572 /* But if the address was not valid, we cannot reload the MEM without
1573 reloading the address first. */
1574 if (!addr_was_valid
)
1575 process_address (nop
, false, &before
, &after
);
1577 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1578 enum reg_class rclass
1579 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1580 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1581 reg
, rclass
, TRUE
, "slow/invalid mem", &new_reg
))
1583 bool insert_before
, insert_after
;
1584 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1586 insert_before
= (type
!= OP_OUT
1587 || partial_subreg_p (mode
, innermode
));
1588 insert_after
= type
!= OP_IN
;
1589 insert_move_for_subreg (insert_before
? &before
: NULL
,
1590 insert_after
? &after
: NULL
,
1593 SUBREG_REG (operand
) = new_reg
;
1595 /* Convert to MODE. */
1598 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1599 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1600 rclass
, TRUE
, "slow/invalid mem", &new_reg
))
1602 bool insert_before
, insert_after
;
1603 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1605 insert_before
= type
!= OP_OUT
;
1606 insert_after
= type
!= OP_IN
;
1607 insert_move_for_subreg (insert_before
? &before
: NULL
,
1608 insert_after
? &after
: NULL
,
1611 *curr_id
->operand_loc
[nop
] = new_reg
;
1612 lra_process_new_insns (curr_insn
, before
, after
,
1613 "Inserting slow/invalid mem reload");
1617 /* If the address was valid and became invalid, prefer to reload
1618 the memory. Typical case is when the index scale should
1619 correspond the memory. */
1620 *curr_id
->operand_loc
[nop
] = operand
;
1621 /* Do not return false here as the MEM_P (reg) will be processed
1622 later in this function. */
1624 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1626 alter_subreg (curr_id
->operand_loc
[nop
], false);
1629 else if (CONSTANT_P (reg
))
1631 /* Try to simplify subreg of constant. It is usually result of
1632 equivalence substitution. */
1633 if (innermode
== VOIDmode
1634 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1635 innermode
= curr_static_id
->operand
[nop
].mode
;
1636 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1637 SUBREG_BYTE (operand
))) != NULL_RTX
)
1639 *curr_id
->operand_loc
[nop
] = new_reg
;
1643 /* Put constant into memory when we have mixed modes. It generates
1644 a better code in most cases as it does not need a secondary
1645 reload memory. It also prevents LRA looping when LRA is using
1646 secondary reload memory again and again. */
1647 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1648 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1650 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1651 alter_subreg (curr_id
->operand_loc
[nop
], false);
1654 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1655 if there may be a problem accessing OPERAND in the outer
1658 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1659 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1660 /* Don't reload paradoxical subregs because we could be looping
1661 having repeatedly final regno out of hard regs range. */
1662 && (hard_regno_nregs (hard_regno
, innermode
)
1663 >= hard_regno_nregs (hard_regno
, mode
))
1664 && simplify_subreg_regno (hard_regno
, innermode
,
1665 SUBREG_BYTE (operand
), mode
) < 0
1666 /* Don't reload subreg for matching reload. It is actually
1667 valid subreg in LRA. */
1668 && ! LRA_SUBREG_P (operand
))
1669 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1671 enum reg_class rclass
;
1674 /* There is a big probability that we will get the same class
1675 for the new pseudo and we will get the same insn which
1676 means infinite looping. So spill the new pseudo. */
1679 /* The class will be defined later in curr_insn_transform. */
1681 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1683 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1684 rclass
, TRUE
, "subreg reg", &new_reg
))
1686 bool insert_before
, insert_after
;
1687 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1689 insert_before
= (type
!= OP_OUT
1690 || read_modify_subreg_p (operand
));
1691 insert_after
= (type
!= OP_IN
);
1692 insert_move_for_subreg (insert_before
? &before
: NULL
,
1693 insert_after
? &after
: NULL
,
1696 SUBREG_REG (operand
) = new_reg
;
1697 lra_process_new_insns (curr_insn
, before
, after
,
1698 "Inserting subreg reload");
1701 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1702 IRA allocates hardreg to the inner pseudo reg according to its mode
1703 instead of the outermode, so the size of the hardreg may not be enough
1704 to contain the outermode operand, in that case we may need to insert
1705 reload for the reg. For the following two types of paradoxical subreg,
1706 we need to insert reload:
1707 1. If the op_type is OP_IN, and the hardreg could not be paired with
1708 other hardreg to contain the outermode operand
1709 (checked by in_hard_reg_set_p), we need to insert the reload.
1710 2. If the op_type is OP_OUT or OP_INOUT.
1712 Here is a paradoxical subreg example showing how the reload is generated:
1714 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1715 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1717 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1718 here, if reg107 is assigned to hardreg R15, because R15 is the last
1719 hardreg, compiler cannot find another hardreg to pair with R15 to
1720 contain TImode data. So we insert a TImode reload reg180 for it.
1721 After reload is inserted:
1723 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1724 (reg:DI 107 [ __comp ])) -1
1725 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1726 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1728 Two reload hard registers will be allocated to reg180 to save TImode data
1731 For LRA pseudos this should normally be handled by the biggest_mode
1732 mechanism. However, it's possible for new uses of an LRA pseudo
1733 to be introduced after we've allocated it, such as when undoing
1734 inheritance, and the allocated register might not then be appropriate
1735 for the new uses. */
1736 else if (REG_P (reg
)
1737 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1738 && paradoxical_subreg_p (operand
)
1739 && (inner_hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1741 = simplify_subreg_regno (inner_hard_regno
, innermode
,
1742 SUBREG_BYTE (operand
), mode
)) < 0
1743 || ((hard_regno_nregs (inner_hard_regno
, innermode
)
1744 < hard_regno_nregs (hard_regno
, mode
))
1745 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1747 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1749 || overlaps_hard_reg_set_p (lra_no_alloc_regs
,
1750 mode
, hard_regno
)))))
1752 /* The class will be defined later in curr_insn_transform. */
1753 enum reg_class rclass
1754 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1756 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1757 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1760 bool insert_before
, insert_after
;
1762 PUT_MODE (new_reg
, mode
);
1763 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1764 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1766 insert_before
= (type
!= OP_OUT
);
1767 insert_after
= (type
!= OP_IN
);
1768 insert_move_for_subreg (insert_before
? &before
: NULL
,
1769 insert_after
? &after
: NULL
,
1772 SUBREG_REG (operand
) = new_reg
;
1773 lra_process_new_insns (curr_insn
, before
, after
,
1774 "Inserting paradoxical subreg reload");
1780 /* Return TRUE if X refers for a hard register from SET. */
1782 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1784 int i
, j
, x_hard_regno
;
1791 code
= GET_CODE (x
);
1792 mode
= GET_MODE (x
);
1796 /* For all SUBREGs we want to check whether the full multi-register
1797 overlaps the set. For normal SUBREGs this means 'get_hard_regno' of
1798 the inner register, for paradoxical SUBREGs this means the
1799 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
1800 fine. Use the wider mode for all cases. */
1801 rtx subreg
= SUBREG_REG (x
);
1802 mode
= wider_subreg_mode (x
);
1803 if (mode
== GET_MODE (subreg
))
1806 code
= GET_CODE (x
);
1810 if (REG_P (x
) || SUBREG_P (x
))
1812 x_hard_regno
= get_hard_regno (x
, true);
1813 return (x_hard_regno
>= 0
1814 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1818 struct address_info ad
;
1820 decompose_mem_address (&ad
, x
);
1821 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1823 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1826 fmt
= GET_RTX_FORMAT (code
);
1827 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1831 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1834 else if (fmt
[i
] == 'E')
1836 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1837 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1844 /* Return true if OP is a spilled pseudo. */
1846 spilled_pseudo_p (rtx op
)
1849 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1852 /* Return true if X is a general constant. */
1854 general_constant_p (rtx x
)
1856 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1860 reg_in_class_p (rtx reg
, enum reg_class cl
)
1863 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1864 return in_class_p (reg
, cl
, NULL
);
1867 /* Return true if SET of RCLASS contains no hard regs which can be
1870 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1876 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1877 temp
= set
& ~lra_no_alloc_regs
;
1878 return (hard_reg_set_subset_p
1879 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1883 /* Used to check validity info about small class input operands. It
1884 should be incremented at start of processing an insn
1886 static unsigned int curr_small_class_check
= 0;
1888 /* Update number of used inputs of class OP_CLASS for operand NOP
1889 of alternative NALT. Return true if we have more such class operands
1890 than the number of available regs. */
1892 update_and_check_small_class_inputs (int nop
, int nalt
,
1893 enum reg_class op_class
)
1895 static unsigned int small_class_check
[LIM_REG_CLASSES
];
1896 static int small_class_input_nums
[LIM_REG_CLASSES
];
1898 if (SMALL_REGISTER_CLASS_P (op_class
)
1899 /* We are interesting in classes became small because of fixing
1900 some hard regs, e.g. by an user through GCC options. */
1901 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
1903 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
1904 || TEST_BIT (curr_static_id
->operand
[nop
].early_clobber_alts
, nalt
)))
1906 if (small_class_check
[op_class
] == curr_small_class_check
)
1907 small_class_input_nums
[op_class
]++;
1910 small_class_check
[op_class
] = curr_small_class_check
;
1911 small_class_input_nums
[op_class
] = 1;
1913 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
1919 /* Major function to choose the current insn alternative and what
1920 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1921 negative we should consider only this alternative. Return false if
1922 we cannot choose the alternative or find how to reload the
1925 process_alt_operands (int only_alternative
)
1928 int nop
, overall
, nalt
;
1929 int n_alternatives
= curr_static_id
->n_alternatives
;
1930 int n_operands
= curr_static_id
->n_operands
;
1931 /* LOSERS counts the operands that don't fit this alternative and
1932 would require loading. */
1935 /* REJECT is a count of how undesirable this alternative says it is
1936 if any reloading is required. If the alternative matches exactly
1937 then REJECT is ignored, but otherwise it gets this much counted
1938 against it in addition to the reloading needed. */
1940 /* This is defined by '!' or '?' alternative constraint and added to
1941 reject. But in some cases it can be ignored. */
1944 /* The number of elements in the following array. */
1945 int early_clobbered_regs_num
;
1946 /* Numbers of operands which are early clobber registers. */
1947 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1948 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1949 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1950 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1951 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1952 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1953 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1954 /* The number of elements in the following array. */
1955 int curr_alt_dont_inherit_ops_num
;
1956 /* Numbers of operands whose reload pseudos should not be inherited. */
1957 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1959 /* The register when the operand is a subreg of register, otherwise the
1961 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1962 /* The register if the operand is a register or subreg of register,
1964 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1965 int hard_regno
[MAX_RECOG_OPERANDS
];
1966 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1967 int reload_nregs
, reload_sum
;
1971 /* Calculate some data common for all alternatives to speed up the
1973 for (nop
= 0; nop
< n_operands
; nop
++)
1977 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1978 /* The real hard regno of the operand after the allocation. */
1979 hard_regno
[nop
] = get_hard_regno (op
, true);
1981 operand_reg
[nop
] = reg
= op
;
1982 biggest_mode
[nop
] = GET_MODE (op
);
1983 if (GET_CODE (op
) == SUBREG
)
1985 biggest_mode
[nop
] = wider_subreg_mode (op
);
1986 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1989 operand_reg
[nop
] = NULL_RTX
;
1990 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1991 || ((int) REGNO (reg
)
1992 == lra_get_elimination_hard_regno (REGNO (reg
))))
1993 no_subreg_reg_operand
[nop
] = reg
;
1995 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1996 /* Just use natural mode for elimination result. It should
1997 be enough for extra constraints hooks. */
1998 = regno_reg_rtx
[hard_regno
[nop
]];
2001 /* The constraints are made of several alternatives. Each operand's
2002 constraint looks like foo,bar,... with commas separating the
2003 alternatives. The first alternatives for all operands go
2004 together, the second alternatives go together, etc.
2006 First loop over alternatives. */
2007 alternative_mask preferred
= curr_id
->preferred_alternatives
;
2008 if (only_alternative
>= 0)
2009 preferred
&= ALTERNATIVE_BIT (only_alternative
);
2011 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
2013 /* Loop over operands for one constraint alternative. */
2014 if (!TEST_BIT (preferred
, nalt
))
2017 bool matching_early_clobber
[MAX_RECOG_OPERANDS
];
2018 curr_small_class_check
++;
2019 overall
= losers
= addr_losers
= 0;
2020 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
2021 for (nop
= 0; nop
< n_operands
; nop
++)
2023 int inc
= (curr_static_id
2024 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
2025 if (lra_dump_file
!= NULL
&& inc
!= 0)
2026 fprintf (lra_dump_file
,
2027 " Staticly defined alt reject+=%d\n", inc
);
2028 static_reject
+= inc
;
2029 matching_early_clobber
[nop
] = 0;
2031 reject
+= static_reject
;
2032 early_clobbered_regs_num
= 0;
2034 for (nop
= 0; nop
< n_operands
; nop
++)
2038 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2039 bool win
, did_match
, offmemok
, early_clobber_p
;
2040 /* false => this operand can be reloaded somehow for this
2043 /* true => this operand can be reloaded if the alternative
2046 /* True if a constant forced into memory would be OK for
2049 enum reg_class this_alternative
, this_costly_alternative
;
2050 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2051 bool this_alternative_match_win
, this_alternative_win
;
2052 bool this_alternative_offmemok
;
2055 enum constraint_num cn
;
2057 opalt_num
= nalt
* n_operands
+ nop
;
2058 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2060 /* Fast track for no constraints at all. */
2061 curr_alt
[nop
] = NO_REGS
;
2062 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2063 curr_alt_win
[nop
] = true;
2064 curr_alt_match_win
[nop
] = false;
2065 curr_alt_offmemok
[nop
] = false;
2066 curr_alt_matches
[nop
] = -1;
2070 op
= no_subreg_reg_operand
[nop
];
2071 mode
= curr_operand_mode
[nop
];
2073 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2076 early_clobber_p
= false;
2077 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2079 this_costly_alternative
= this_alternative
= NO_REGS
;
2080 /* We update set of possible hard regs besides its class
2081 because reg class might be inaccurate. For example,
2082 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2083 is translated in HI_REGS because classes are merged by
2084 pairs and there is no accurate intermediate class. */
2085 CLEAR_HARD_REG_SET (this_alternative_set
);
2086 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2087 this_alternative_win
= false;
2088 this_alternative_match_win
= false;
2089 this_alternative_offmemok
= false;
2090 this_alternative_matches
= -1;
2092 /* An empty constraint should be excluded by the fast
2094 lra_assert (*p
!= 0 && *p
!= ',');
2097 /* Scan this alternative's specs for this operand; set WIN
2098 if the operand fits any letter in this alternative.
2099 Otherwise, clear BADOP if this operand could fit some
2100 letter after reloads, or set WINREG if this operand could
2101 fit after reloads provided the constraint allows some
2106 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2116 early_clobber_p
= true;
2120 op_reject
+= LRA_MAX_REJECT
;
2123 op_reject
+= LRA_LOSER_COST_FACTOR
;
2127 /* Ignore rest of this alternative. */
2131 case '0': case '1': case '2': case '3': case '4':
2132 case '5': case '6': case '7': case '8': case '9':
2137 m
= strtoul (p
, &end
, 10);
2140 lra_assert (nop
> m
);
2142 /* Reject matches if we don't know which operand is
2143 bigger. This situation would arguably be a bug in
2144 an .md pattern, but could also occur in a user asm. */
2145 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2146 GET_MODE_SIZE (biggest_mode
[nop
])))
2149 /* Don't match wrong asm insn operands for proper
2150 diagnostic later. */
2151 if (INSN_CODE (curr_insn
) < 0
2152 && (curr_operand_mode
[m
] == BLKmode
2153 || curr_operand_mode
[nop
] == BLKmode
)
2154 && curr_operand_mode
[m
] != curr_operand_mode
[nop
])
2157 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2158 /* We are supposed to match a previous operand.
2159 If we do, we win if that one did. If we do
2160 not, count both of the operands as losers.
2161 (This is too conservative, since most of the
2162 time only a single reload insn will be needed
2163 to make the two operands win. As a result,
2164 this alternative may be rejected when it is
2165 actually desirable.) */
2167 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2168 *curr_id
->operand_loc
[m
], m_hregno
))
2170 /* We should reject matching of an early
2171 clobber operand if the matching operand is
2172 not dying in the insn. */
2173 if (!TEST_BIT (curr_static_id
->operand
[m
]
2174 .early_clobber_alts
, nalt
)
2175 || operand_reg
[nop
] == NULL_RTX
2176 || (find_regno_note (curr_insn
, REG_DEAD
,
2178 || REGNO (op
) == REGNO (operand_reg
[m
])))
2183 /* If we are matching a non-offsettable
2184 address where an offsettable address was
2185 expected, then we must reject this
2186 combination, because we can't reload
2188 if (curr_alt_offmemok
[m
]
2189 && MEM_P (*curr_id
->operand_loc
[m
])
2190 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2195 /* If the operands do not match and one
2196 operand is INOUT, we can not match them.
2197 Try other possibilities, e.g. other
2198 alternatives or commutative operand
2200 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
2201 || curr_static_id
->operand
[m
].type
== OP_INOUT
)
2203 /* Operands don't match. If the operands are
2204 different user defined explicit hard
2205 registers, then we cannot make them match
2206 when one is early clobber operand. */
2207 if ((REG_P (*curr_id
->operand_loc
[nop
])
2208 || SUBREG_P (*curr_id
->operand_loc
[nop
]))
2209 && (REG_P (*curr_id
->operand_loc
[m
])
2210 || SUBREG_P (*curr_id
->operand_loc
[m
])))
2212 rtx nop_reg
= *curr_id
->operand_loc
[nop
];
2213 if (SUBREG_P (nop_reg
))
2214 nop_reg
= SUBREG_REG (nop_reg
);
2215 rtx m_reg
= *curr_id
->operand_loc
[m
];
2216 if (SUBREG_P (m_reg
))
2217 m_reg
= SUBREG_REG (m_reg
);
2220 && HARD_REGISTER_P (nop_reg
)
2221 && REG_USERVAR_P (nop_reg
)
2223 && HARD_REGISTER_P (m_reg
)
2224 && REG_USERVAR_P (m_reg
))
2228 for (i
= 0; i
< early_clobbered_regs_num
; i
++)
2229 if (m
== early_clobbered_nops
[i
])
2231 if (i
< early_clobbered_regs_num
2236 /* Both operands must allow a reload register,
2237 otherwise we cannot make them match. */
2238 if (curr_alt
[m
] == NO_REGS
)
2240 /* Retroactively mark the operand we had to
2241 match as a loser, if it wasn't already and
2242 it wasn't matched to a register constraint
2243 (e.g it might be matched by memory). */
2245 && (operand_reg
[m
] == NULL_RTX
2246 || hard_regno
[m
] < 0))
2250 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2251 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2254 /* Prefer matching earlyclobber alternative as
2255 it results in less hard regs required for
2256 the insn than a non-matching earlyclobber
2258 if (TEST_BIT (curr_static_id
->operand
[m
]
2259 .early_clobber_alts
, nalt
))
2261 if (lra_dump_file
!= NULL
)
2264 " %d Matching earlyclobber alt:"
2267 if (!matching_early_clobber
[m
])
2270 matching_early_clobber
[m
] = 1;
2273 /* Otherwise we prefer no matching
2274 alternatives because it gives more freedom
2276 else if (operand_reg
[nop
] == NULL_RTX
2277 || (find_regno_note (curr_insn
, REG_DEAD
,
2278 REGNO (operand_reg
[nop
]))
2281 if (lra_dump_file
!= NULL
)
2284 " %d Matching alt: reject+=2\n",
2289 /* If we have to reload this operand and some
2290 previous operand also had to match the same
2291 thing as this operand, we don't know how to do
2293 if (!match_p
|| !curr_alt_win
[m
])
2295 for (i
= 0; i
< nop
; i
++)
2296 if (curr_alt_matches
[i
] == m
)
2304 this_alternative_matches
= m
;
2305 /* This can be fixed with reloads if the operand
2306 we are supposed to match can be fixed with
2309 this_alternative
= curr_alt
[m
];
2310 this_alternative_set
= curr_alt_set
[m
];
2311 winreg
= this_alternative
!= NO_REGS
;
2317 || general_constant_p (op
)
2318 || spilled_pseudo_p (op
))
2324 cn
= lookup_constraint (p
);
2325 switch (get_constraint_type (cn
))
2328 cl
= reg_class_for_constraint (cn
);
2334 if (CONST_INT_P (op
)
2335 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2341 && satisfies_memory_constraint_p (op
, cn
))
2343 else if (spilled_pseudo_p (op
))
2346 /* If we didn't already win, we can reload constants
2347 via force_const_mem or put the pseudo value into
2348 memory, or make other memory by reloading the
2349 address like for 'o'. */
2350 if (CONST_POOL_OK_P (mode
, op
)
2351 || MEM_P (op
) || REG_P (op
)
2352 /* We can restore the equiv insn by a
2354 || equiv_substition_p
[nop
])
2361 /* An asm operand with an address constraint
2362 that doesn't satisfy address_operand has
2363 is_address cleared, so that we don't try to
2364 make a non-address fit. */
2365 if (!curr_static_id
->operand
[nop
].is_address
)
2367 /* If we didn't already win, we can reload the address
2368 into a base register. */
2369 if (satisfies_address_constraint_p (op
, cn
))
2371 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2377 if (constraint_satisfied_p (op
, cn
))
2381 case CT_SPECIAL_MEMORY
:
2383 && satisfies_memory_constraint_p (op
, cn
))
2385 else if (spilled_pseudo_p (op
))
2392 if (mode
== BLKmode
)
2394 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2395 this_alternative_set
|= reg_class_contents
[cl
];
2398 this_costly_alternative
2399 = reg_class_subunion
[this_costly_alternative
][cl
];
2400 this_costly_alternative_set
|= reg_class_contents
[cl
];
2405 if (hard_regno
[nop
] >= 0
2406 && in_hard_reg_set_p (this_alternative_set
,
2407 mode
, hard_regno
[nop
]))
2409 else if (hard_regno
[nop
] < 0
2410 && in_class_p (op
, this_alternative
, NULL
))
2415 if (c
!= ' ' && c
!= '\t')
2416 costly_p
= c
== '*';
2418 while ((p
+= len
), c
);
2420 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2421 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2422 /* Record which operands fit this alternative. */
2425 this_alternative_win
= true;
2426 if (operand_reg
[nop
] != NULL_RTX
)
2428 if (hard_regno
[nop
] >= 0)
2430 if (in_hard_reg_set_p (this_costly_alternative_set
,
2431 mode
, hard_regno
[nop
]))
2433 if (lra_dump_file
!= NULL
)
2434 fprintf (lra_dump_file
,
2435 " %d Costly set: reject++\n",
2442 /* Prefer won reg to spilled pseudo under other
2443 equal conditions for possibe inheritance. */
2446 if (lra_dump_file
!= NULL
)
2449 " %d Non pseudo reload: reject++\n",
2453 if (in_class_p (operand_reg
[nop
],
2454 this_costly_alternative
, NULL
))
2456 if (lra_dump_file
!= NULL
)
2459 " %d Non pseudo costly reload:"
2465 /* We simulate the behavior of old reload here.
2466 Although scratches need hard registers and it
2467 might result in spilling other pseudos, no reload
2468 insns are generated for the scratches. So it
2469 might cost something but probably less than old
2470 reload pass believes. */
2473 if (lra_dump_file
!= NULL
)
2474 fprintf (lra_dump_file
,
2475 " %d Scratch win: reject+=2\n",
2482 this_alternative_match_win
= true;
2485 int const_to_mem
= 0;
2488 reject
+= op_reject
;
2489 /* Never do output reload of stack pointer. It makes
2490 impossible to do elimination when SP is changed in
2492 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2493 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2496 /* If this alternative asks for a specific reg class, see if there
2497 is at least one allocatable register in that class. */
2499 = (this_alternative
== NO_REGS
2500 || (hard_reg_set_subset_p
2501 (reg_class_contents
[this_alternative
],
2502 lra_no_alloc_regs
)));
2504 /* For asms, verify that the class for this alternative is possible
2505 for the mode that is specified. */
2506 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2509 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2510 if (targetm
.hard_regno_mode_ok (i
, mode
)
2511 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2514 if (i
== FIRST_PSEUDO_REGISTER
)
2518 /* If this operand accepts a register, and if the
2519 register class has at least one allocatable register,
2520 then this operand can be reloaded. */
2521 if (winreg
&& !no_regs_p
)
2526 if (lra_dump_file
!= NULL
)
2527 fprintf (lra_dump_file
,
2528 " alt=%d: Bad operand -- refuse\n",
2533 if (this_alternative
!= NO_REGS
)
2535 HARD_REG_SET available_regs
2536 = (reg_class_contents
[this_alternative
]
2537 & ~((ira_prohibited_class_mode_regs
2538 [this_alternative
][mode
])
2539 | lra_no_alloc_regs
));
2540 if (hard_reg_set_empty_p (available_regs
))
2542 /* There are no hard regs holding a value of given
2546 this_alternative
= NO_REGS
;
2547 if (lra_dump_file
!= NULL
)
2548 fprintf (lra_dump_file
,
2549 " %d Using memory because of"
2550 " a bad mode: reject+=2\n",
2556 if (lra_dump_file
!= NULL
)
2557 fprintf (lra_dump_file
,
2558 " alt=%d: Wrong mode -- refuse\n",
2565 /* If not assigned pseudo has a class which a subset of
2566 required reg class, it is a less costly alternative
2567 as the pseudo still can get a hard reg of necessary
2569 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2570 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2571 && ira_class_subset_p
[this_alternative
][cl
])
2573 if (lra_dump_file
!= NULL
)
2576 " %d Super set class reg: reject-=3\n", nop
);
2580 this_alternative_offmemok
= offmemok
;
2581 if (this_costly_alternative
!= NO_REGS
)
2583 if (lra_dump_file
!= NULL
)
2584 fprintf (lra_dump_file
,
2585 " %d Costly loser: reject++\n", nop
);
2588 /* If the operand is dying, has a matching constraint,
2589 and satisfies constraints of the matched operand
2590 which failed to satisfy the own constraints, most probably
2591 the reload for this operand will be gone. */
2592 if (this_alternative_matches
>= 0
2593 && !curr_alt_win
[this_alternative_matches
]
2595 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2596 && (hard_regno
[nop
] >= 0
2597 ? in_hard_reg_set_p (this_alternative_set
,
2598 mode
, hard_regno
[nop
])
2599 : in_class_p (op
, this_alternative
, NULL
)))
2601 if (lra_dump_file
!= NULL
)
2604 " %d Dying matched operand reload: reject++\n",
2610 /* Strict_low_part requires to reload the register
2611 not the sub-register. In this case we should
2612 check that a final reload hard reg can hold the
2614 if (curr_static_id
->operand
[nop
].strict_low
2616 && hard_regno
[nop
] < 0
2617 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2618 && ira_class_hard_regs_num
[this_alternative
] > 0
2619 && (!targetm
.hard_regno_mode_ok
2620 (ira_class_hard_regs
[this_alternative
][0],
2621 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2623 if (lra_dump_file
!= NULL
)
2626 " alt=%d: Strict low subreg reload -- refuse\n",
2632 if (operand_reg
[nop
] != NULL_RTX
2633 /* Output operands and matched input operands are
2634 not inherited. The following conditions do not
2635 exactly describe the previous statement but they
2636 are pretty close. */
2637 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2638 && (this_alternative_matches
< 0
2639 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2641 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2645 /* The value of reload_sum has sense only if we
2646 process insns in their order. It happens only on
2647 the first constraints sub-pass when we do most of
2649 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2650 reload_sum
+= last_reload
- bb_reload_num
;
2652 /* If this is a constant that is reloaded into the
2653 desired class by copying it to memory first, count
2654 that as another reload. This is consistent with
2655 other code and is required to avoid choosing another
2656 alternative when the constant is moved into memory.
2657 Note that the test here is precisely the same as in
2658 the code below that calls force_const_mem. */
2659 if (CONST_POOL_OK_P (mode
, op
)
2660 && ((targetm
.preferred_reload_class
2661 (op
, this_alternative
) == NO_REGS
)
2662 || no_input_reloads_p
))
2669 /* Alternative loses if it requires a type of reload not
2670 permitted for this insn. We can always reload
2671 objects with a REG_UNUSED note. */
2672 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2673 && no_output_reloads_p
2674 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2675 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2676 && no_input_reloads_p
&& ! const_to_mem
)
2677 || (this_alternative_matches
>= 0
2678 && (no_input_reloads_p
2679 || (no_output_reloads_p
2680 && (curr_static_id
->operand
2681 [this_alternative_matches
].type
!= OP_IN
)
2682 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2683 no_subreg_reg_operand
2684 [this_alternative_matches
])))))
2686 if (lra_dump_file
!= NULL
)
2689 " alt=%d: No input/otput reload -- refuse\n",
2694 /* Alternative loses if it required class pseudo cannot
2695 hold value of required mode. Such insns can be
2696 described by insn definitions with mode iterators. */
2697 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2698 && ! hard_reg_set_empty_p (this_alternative_set
)
2699 /* It is common practice for constraints to use a
2700 class which does not have actually enough regs to
2701 hold the value (e.g. x86 AREG for mode requiring
2702 more one general reg). Therefore we have 2
2703 conditions to check that the reload pseudo cannot
2704 hold the mode value. */
2705 && (!targetm
.hard_regno_mode_ok
2706 (ira_class_hard_regs
[this_alternative
][0],
2707 GET_MODE (*curr_id
->operand_loc
[nop
])))
2708 /* The above condition is not enough as the first
2709 reg in ira_class_hard_regs can be not aligned for
2710 multi-words mode values. */
2711 && (prohibited_class_reg_set_mode_p
2712 (this_alternative
, this_alternative_set
,
2713 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2715 if (lra_dump_file
!= NULL
)
2716 fprintf (lra_dump_file
,
2717 " alt=%d: reload pseudo for op %d "
2718 "cannot hold the mode value -- refuse\n",
2723 /* Check strong discouragement of reload of non-constant
2724 into class THIS_ALTERNATIVE. */
2725 if (! CONSTANT_P (op
) && ! no_regs_p
2726 && (targetm
.preferred_reload_class
2727 (op
, this_alternative
) == NO_REGS
2728 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2729 && (targetm
.preferred_output_reload_class
2730 (op
, this_alternative
) == NO_REGS
))))
2732 if (offmemok
&& REG_P (op
))
2734 if (lra_dump_file
!= NULL
)
2737 " %d Spill pseudo into memory: reject+=3\n",
2743 if (lra_dump_file
!= NULL
)
2746 " %d Non-prefered reload: reject+=%d\n",
2747 nop
, LRA_MAX_REJECT
);
2748 reject
+= LRA_MAX_REJECT
;
2752 if (! (MEM_P (op
) && offmemok
)
2753 && ! (const_to_mem
&& constmemok
))
2755 /* We prefer to reload pseudos over reloading other
2756 things, since such reloads may be able to be
2757 eliminated later. So bump REJECT in other cases.
2758 Don't do this in the case where we are forcing a
2759 constant into memory and it will then win since
2760 we don't want to have a different alternative
2762 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2764 if (lra_dump_file
!= NULL
)
2767 " %d Non-pseudo reload: reject+=2\n",
2774 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2776 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2778 if (lra_dump_file
!= NULL
)
2781 " %d Small class reload: reject+=%d\n",
2782 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2783 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2787 /* We are trying to spill pseudo into memory. It is
2788 usually more costly than moving to a hard register
2789 although it might takes the same number of
2792 Non-pseudo spill may happen also. Suppose a target allows both
2793 register and memory in the operand constraint alternatives,
2794 then it's typical that an eliminable register has a substition
2795 of "base + offset" which can either be reloaded by a simple
2796 "new_reg <= base + offset" which will match the register
2797 constraint, or a similar reg addition followed by further spill
2798 to and reload from memory which will match the memory
2799 constraint, but this memory spill will be much more costly
2802 Code below increases the reject for both pseudo and non-pseudo
2805 && !(MEM_P (op
) && offmemok
)
2806 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2808 if (lra_dump_file
!= NULL
)
2811 " %d Spill %spseudo into memory: reject+=3\n",
2812 nop
, REG_P (op
) ? "" : "Non-");
2814 if (VECTOR_MODE_P (mode
))
2816 /* Spilling vectors into memory is usually more
2817 costly as they contain big values. */
2818 if (lra_dump_file
!= NULL
)
2821 " %d Spill vector pseudo: reject+=2\n",
2827 /* When we use an operand requiring memory in given
2828 alternative, the insn should write *and* read the
2829 value to/from memory it is costly in comparison with
2830 an insn alternative which does not use memory
2831 (e.g. register or immediate operand). We exclude
2832 memory operand for such case as we can satisfy the
2833 memory constraints by reloading address. */
2834 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
2836 if (lra_dump_file
!= NULL
)
2839 " Using memory insn operand %d: reject+=3\n",
2844 /* If reload requires moving value through secondary
2845 memory, it will need one more insn at least. */
2846 if (this_alternative
!= NO_REGS
2847 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2848 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2849 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
2851 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2852 && (targetm
.secondary_memory_needed
2853 (GET_MODE (op
), this_alternative
, cl
)))))
2856 if (MEM_P (op
) && offmemok
)
2860 /* Input reloads can be inherited more often than
2861 output reloads can be removed, so penalize output
2863 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2865 if (lra_dump_file
!= NULL
)
2868 " %d Non input pseudo reload: reject++\n",
2873 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
2875 if (lra_dump_file
!= NULL
)
2878 " %d Input/Output reload: reject+=%d\n",
2879 nop
, LRA_LOSER_COST_FACTOR
);
2880 reject
+= LRA_LOSER_COST_FACTOR
;
2885 if (early_clobber_p
&& ! scratch_p
)
2887 if (lra_dump_file
!= NULL
)
2888 fprintf (lra_dump_file
,
2889 " %d Early clobber: reject++\n", nop
);
2892 /* ??? We check early clobbers after processing all operands
2893 (see loop below) and there we update the costs more.
2894 Should we update the cost (may be approximately) here
2895 because of early clobber register reloads or it is a rare
2896 or non-important thing to be worth to do it. */
2897 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
2898 - (addr_losers
== losers
? static_reject
: 0));
2899 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2901 if (lra_dump_file
!= NULL
)
2902 fprintf (lra_dump_file
,
2903 " alt=%d,overall=%d,losers=%d -- refuse\n",
2904 nalt
, overall
, losers
);
2908 if (update_and_check_small_class_inputs (nop
, nalt
,
2911 if (lra_dump_file
!= NULL
)
2912 fprintf (lra_dump_file
,
2913 " alt=%d, not enough small class regs -- refuse\n",
2917 curr_alt
[nop
] = this_alternative
;
2918 curr_alt_set
[nop
] = this_alternative_set
;
2919 curr_alt_win
[nop
] = this_alternative_win
;
2920 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2921 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2922 curr_alt_matches
[nop
] = this_alternative_matches
;
2924 if (this_alternative_matches
>= 0
2925 && !did_match
&& !this_alternative_win
)
2926 curr_alt_win
[this_alternative_matches
] = false;
2928 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2929 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2932 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2933 /* Prevent processing non-move insns. */
2934 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2935 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2936 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2937 && REG_P (no_subreg_reg_operand
[0])
2938 && REG_P (no_subreg_reg_operand
[1])
2939 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2940 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2941 || (! curr_alt_win
[0] && curr_alt_win
[1]
2942 && REG_P (no_subreg_reg_operand
[1])
2943 /* Check that we reload memory not the memory
2945 && ! (curr_alt_offmemok
[0]
2946 && MEM_P (no_subreg_reg_operand
[0]))
2947 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2948 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2949 && REG_P (no_subreg_reg_operand
[0])
2950 /* Check that we reload memory not the memory
2952 && ! (curr_alt_offmemok
[1]
2953 && MEM_P (no_subreg_reg_operand
[1]))
2954 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2955 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2956 no_subreg_reg_operand
[1])
2957 || (targetm
.preferred_reload_class
2958 (no_subreg_reg_operand
[1],
2959 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2960 /* If it is a result of recent elimination in move
2961 insn we can transform it into an add still by
2962 using this alternative. */
2963 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
2964 /* Likewise if the source has been replaced with an
2965 equivalent value. This only happens once -- the reload
2966 will use the equivalent value instead of the register it
2967 replaces -- so there should be no danger of cycling. */
2968 && !equiv_substition_p
[1])))
2970 /* We have a move insn and a new reload insn will be similar
2971 to the current insn. We should avoid such situation as
2972 it results in LRA cycling. */
2973 if (lra_dump_file
!= NULL
)
2974 fprintf (lra_dump_file
,
2975 " Cycle danger: overall += LRA_MAX_REJECT\n");
2976 overall
+= LRA_MAX_REJECT
;
2979 curr_alt_dont_inherit_ops_num
= 0;
2980 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2982 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2983 HARD_REG_SET temp_set
;
2985 i
= early_clobbered_nops
[nop
];
2986 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2987 || hard_regno
[i
] < 0)
2989 lra_assert (operand_reg
[i
] != NULL_RTX
);
2990 clobbered_hard_regno
= hard_regno
[i
];
2991 CLEAR_HARD_REG_SET (temp_set
);
2992 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2993 first_conflict_j
= last_conflict_j
= -1;
2994 for (j
= 0; j
< n_operands
; j
++)
2996 /* We don't want process insides of match_operator and
2997 match_parallel because otherwise we would process
2998 their operands once again generating a wrong
3000 || curr_static_id
->operand
[j
].is_operator
)
3002 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
3003 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
3005 /* If we don't reload j-th operand, check conflicts. */
3006 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
3007 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
3009 if (first_conflict_j
< 0)
3010 first_conflict_j
= j
;
3011 last_conflict_j
= j
;
3012 /* Both the earlyclobber operand and conflicting operand
3013 cannot both be user defined hard registers. */
3014 if (HARD_REGISTER_P (operand_reg
[i
])
3015 && REG_USERVAR_P (operand_reg
[i
])
3016 && operand_reg
[j
] != NULL_RTX
3017 && HARD_REGISTER_P (operand_reg
[j
])
3018 && REG_USERVAR_P (operand_reg
[j
]))
3019 fatal_insn ("unable to generate reloads for "
3020 "impossible constraints:", curr_insn
);
3022 if (last_conflict_j
< 0)
3025 /* If an earlyclobber operand conflicts with another non-matching
3026 operand (ie, they have been assigned the same hard register),
3027 then it is better to reload the other operand, as there may
3028 exist yet another operand with a matching constraint associated
3029 with the earlyclobber operand. However, if one of the operands
3030 is an explicit use of a hard register, then we must reload the
3031 other non-hard register operand. */
3032 if (HARD_REGISTER_P (operand_reg
[i
])
3033 || (first_conflict_j
== last_conflict_j
3034 && operand_reg
[last_conflict_j
] != NULL_RTX
3035 && !curr_alt_match_win
[last_conflict_j
]
3036 && !HARD_REGISTER_P (operand_reg
[last_conflict_j
])))
3038 curr_alt_win
[last_conflict_j
] = false;
3039 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
3042 if (lra_dump_file
!= NULL
)
3045 " %d Conflict early clobber reload: reject--\n",
3050 /* We need to reload early clobbered register and the
3051 matched registers. */
3052 for (j
= 0; j
< n_operands
; j
++)
3053 if (curr_alt_matches
[j
] == i
)
3055 curr_alt_match_win
[j
] = false;
3057 overall
+= LRA_LOSER_COST_FACTOR
;
3059 if (! curr_alt_match_win
[i
])
3060 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
3063 /* Remember pseudos used for match reloads are never
3065 lra_assert (curr_alt_matches
[i
] >= 0);
3066 curr_alt_win
[curr_alt_matches
[i
]] = false;
3068 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
3070 if (lra_dump_file
!= NULL
)
3073 " %d Matched conflict early clobber reloads: "
3077 /* Early clobber was already reflected in REJECT. */
3078 if (!matching_early_clobber
[i
])
3080 lra_assert (reject
> 0);
3082 matching_early_clobber
[i
] = 1;
3084 overall
+= LRA_LOSER_COST_FACTOR
- 1;
3086 if (lra_dump_file
!= NULL
)
3087 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
3088 nalt
, overall
, losers
, reload_nregs
);
3090 /* If this alternative can be made to work by reloading, and it
3091 needs less reloading than the others checked so far, record
3092 it as the chosen goal for reloading. */
3093 if ((best_losers
!= 0 && losers
== 0)
3094 || (((best_losers
== 0 && losers
== 0)
3095 || (best_losers
!= 0 && losers
!= 0))
3096 && (best_overall
> overall
3097 || (best_overall
== overall
3098 /* If the cost of the reloads is the same,
3099 prefer alternative which requires minimal
3100 number of reload regs. */
3101 && (reload_nregs
< best_reload_nregs
3102 || (reload_nregs
== best_reload_nregs
3103 && (best_reload_sum
< reload_sum
3104 || (best_reload_sum
== reload_sum
3105 && nalt
< goal_alt_number
))))))))
3107 for (nop
= 0; nop
< n_operands
; nop
++)
3109 goal_alt_win
[nop
] = curr_alt_win
[nop
];
3110 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
3111 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
3112 goal_alt
[nop
] = curr_alt
[nop
];
3113 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3115 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3116 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3117 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3118 goal_alt_swapped
= curr_swapped
;
3119 best_overall
= overall
;
3120 best_losers
= losers
;
3121 best_reload_nregs
= reload_nregs
;
3122 best_reload_sum
= reload_sum
;
3123 goal_alt_number
= nalt
;
3126 /* Everything is satisfied. Do not process alternatives
3135 /* Make reload base reg from address AD. */
3137 base_to_reg (struct address_info
*ad
)
3141 rtx new_inner
= NULL_RTX
;
3142 rtx new_reg
= NULL_RTX
;
3144 rtx_insn
*last_insn
= get_last_insn();
3146 lra_assert (ad
->disp
== ad
->disp_term
);
3147 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3148 get_index_code (ad
));
3149 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
,
3151 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3152 ad
->disp_term
== NULL
3155 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3157 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3158 code
= recog_memoized (insn
);
3161 delete_insns_since (last_insn
);
3168 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3170 base_plus_disp_to_reg (struct address_info
*ad
, rtx disp
)
3175 lra_assert (ad
->base
== ad
->base_term
);
3176 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3177 get_index_code (ad
));
3178 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
3180 lra_emit_add (new_reg
, *ad
->base_term
, disp
);
3184 /* Make reload of index part of address AD. Return the new
3187 index_part_to_reg (struct address_info
*ad
)
3191 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3192 INDEX_REG_CLASS
, "index term");
3193 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3194 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3198 /* Return true if we can add a displacement to address AD, even if that
3199 makes the address invalid. The fix-up code requires any new address
3200 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3202 can_add_disp_p (struct address_info
*ad
)
3204 return (!ad
->autoinc_p
3205 && ad
->segment
== NULL
3206 && ad
->base
== ad
->base_term
3207 && ad
->disp
== ad
->disp_term
);
3210 /* Make equiv substitution in address AD. Return true if a substitution
3213 equiv_address_substitution (struct address_info
*ad
)
3215 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3217 HOST_WIDE_INT scale
;
3220 base_term
= strip_subreg (ad
->base_term
);
3221 if (base_term
== NULL
)
3222 base_reg
= new_base_reg
= NULL_RTX
;
3225 base_reg
= *base_term
;
3226 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3228 index_term
= strip_subreg (ad
->index_term
);
3229 if (index_term
== NULL
)
3230 index_reg
= new_index_reg
= NULL_RTX
;
3233 index_reg
= *index_term
;
3234 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3236 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3240 if (lra_dump_file
!= NULL
)
3242 fprintf (lra_dump_file
, "Changing address in insn %d ",
3243 INSN_UID (curr_insn
));
3244 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3246 if (base_reg
!= new_base_reg
)
3249 if (REG_P (new_base_reg
))
3251 *base_term
= new_base_reg
;
3254 else if (GET_CODE (new_base_reg
) == PLUS
3255 && REG_P (XEXP (new_base_reg
, 0))
3256 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3257 && can_add_disp_p (ad
))
3260 *base_term
= XEXP (new_base_reg
, 0);
3263 if (ad
->base_term2
!= NULL
)
3264 *ad
->base_term2
= *ad
->base_term
;
3266 if (index_reg
!= new_index_reg
)
3269 if (REG_P (new_index_reg
))
3271 *index_term
= new_index_reg
;
3274 else if (GET_CODE (new_index_reg
) == PLUS
3275 && REG_P (XEXP (new_index_reg
, 0))
3276 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3277 && can_add_disp_p (ad
)
3278 && (scale
= get_index_scale (ad
)))
3280 disp
+= offset
* scale
;
3281 *index_term
= XEXP (new_index_reg
, 0);
3285 if (maybe_ne (disp
, 0))
3287 if (ad
->disp
!= NULL
)
3288 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3291 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3292 update_address (ad
);
3296 if (lra_dump_file
!= NULL
)
3299 fprintf (lra_dump_file
, " -- no change\n");
3302 fprintf (lra_dump_file
, " on equiv ");
3303 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3304 fprintf (lra_dump_file
, "\n");
3310 /* Major function to make reloads for an address in operand NOP or
3311 check its correctness (If CHECK_ONLY_P is true). The supported
3314 1) an address that existed before LRA started, at which point it
3315 must have been valid. These addresses are subject to elimination
3316 and may have become invalid due to the elimination offset being out
3319 2) an address created by forcing a constant to memory
3320 (force_const_to_mem). The initial form of these addresses might
3321 not be valid, and it is this function's job to make them valid.
3323 3) a frame address formed from a register and a (possibly zero)
3324 constant offset. As above, these addresses might not be valid and
3325 this function must make them so.
3327 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3328 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3329 address. Return true for any RTL change.
3331 The function is a helper function which does not produce all
3332 transformations (when CHECK_ONLY_P is false) which can be
3333 necessary. It does just basic steps. To do all necessary
3334 transformations use function process_address. */
3336 process_address_1 (int nop
, bool check_only_p
,
3337 rtx_insn
**before
, rtx_insn
**after
)
3339 struct address_info ad
;
3341 HOST_WIDE_INT scale
;
3342 rtx op
= *curr_id
->operand_loc
[nop
];
3343 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3344 enum constraint_num cn
= lookup_constraint (constraint
);
3345 bool change_p
= false;
3348 && GET_MODE (op
) == BLKmode
3349 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3352 if (insn_extra_address_constraint (cn
)
3353 /* When we find an asm operand with an address constraint that
3354 doesn't satisfy address_operand to begin with, we clear
3355 is_address, so that we don't try to make a non-address fit.
3356 If the asm statement got this far, it's because other
3357 constraints are available, and we'll use them, disregarding
3358 the unsatisfiable address ones. */
3359 && curr_static_id
->operand
[nop
].is_address
)
3360 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3361 /* Do not attempt to decompose arbitrary addresses generated by combine
3362 for asm operands with loose constraints, e.g 'X'. */
3364 && !(INSN_CODE (curr_insn
) < 0
3365 && get_constraint_type (cn
) == CT_FIXED_FORM
3366 && constraint_satisfied_p (op
, cn
)))
3367 decompose_mem_address (&ad
, op
);
3368 else if (GET_CODE (op
) == SUBREG
3369 && MEM_P (SUBREG_REG (op
)))
3370 decompose_mem_address (&ad
, SUBREG_REG (op
));
3373 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3374 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3375 when INDEX_REG_CLASS is a single register class. */
3376 if (ad
.base_term
!= NULL
3377 && ad
.index_term
!= NULL
3378 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3379 && REG_P (*ad
.base_term
)
3380 && REG_P (*ad
.index_term
)
3381 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3382 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3384 std::swap (ad
.base
, ad
.index
);
3385 std::swap (ad
.base_term
, ad
.index_term
);
3388 change_p
= equiv_address_substitution (&ad
);
3389 if (ad
.base_term
!= NULL
3390 && (process_addr_reg
3391 (ad
.base_term
, check_only_p
, before
,
3393 && !(REG_P (*ad
.base_term
)
3394 && find_regno_note (curr_insn
, REG_DEAD
,
3395 REGNO (*ad
.base_term
)) != NULL_RTX
)
3397 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3398 get_index_code (&ad
)))))
3401 if (ad
.base_term2
!= NULL
)
3402 *ad
.base_term2
= *ad
.base_term
;
3404 if (ad
.index_term
!= NULL
3405 && process_addr_reg (ad
.index_term
, check_only_p
,
3406 before
, NULL
, INDEX_REG_CLASS
))
3409 /* Target hooks sometimes don't treat extra-constraint addresses as
3410 legitimate address_operands, so handle them specially. */
3411 if (insn_extra_address_constraint (cn
)
3412 && satisfies_address_constraint_p (&ad
, cn
))
3418 /* There are three cases where the shape of *AD.INNER may now be invalid:
3420 1) the original address was valid, but either elimination or
3421 equiv_address_substitution was applied and that made
3422 the address invalid.
3424 2) the address is an invalid symbolic address created by
3427 3) the address is a frame address with an invalid offset.
3429 4) the address is a frame address with an invalid base.
3431 All these cases involve a non-autoinc address, so there is no
3432 point revalidating other types. */
3433 if (ad
.autoinc_p
|| valid_address_p (op
, &ad
, cn
))
3436 /* Any index existed before LRA started, so we can assume that the
3437 presence and shape of the index is valid. */
3438 push_to_sequence (*before
);
3439 lra_assert (ad
.disp
== ad
.disp_term
);
3440 if (ad
.base
== NULL
)
3442 if (ad
.index
== NULL
)
3445 rtx_insn
*last
= get_last_insn ();
3447 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3449 rtx addr
= *ad
.inner
;
3451 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3454 /* addr => lo_sum (new_base, addr), case (2) above. */
3455 insn
= emit_insn (gen_rtx_SET
3457 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3458 code
= recog_memoized (insn
);
3461 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3462 if (!valid_address_p (op
, &ad
, cn
))
3464 /* Try to put lo_sum into register. */
3465 insn
= emit_insn (gen_rtx_SET
3467 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3468 code
= recog_memoized (insn
);
3471 *ad
.inner
= new_reg
;
3472 if (!valid_address_p (op
, &ad
, cn
))
3482 delete_insns_since (last
);
3487 /* addr => new_base, case (2) above. */
3488 lra_emit_move (new_reg
, addr
);
3490 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3492 insn
= NEXT_INSN (insn
))
3493 if (recog_memoized (insn
) < 0)
3495 if (insn
!= NULL_RTX
)
3497 /* Do nothing if we cannot generate right insns.
3498 This is analogous to reload pass behavior. */
3499 delete_insns_since (last
);
3503 *ad
.inner
= new_reg
;
3508 /* index * scale + disp => new base + index * scale,
3510 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3511 GET_CODE (*ad
.index
));
3513 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3514 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3515 lra_emit_move (new_reg
, *ad
.disp
);
3516 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3517 new_reg
, *ad
.index
);
3520 else if (ad
.index
== NULL
)
3525 rtx_insn
*insns
, *last_insn
;
3526 /* Try to reload base into register only if the base is invalid
3527 for the address but with valid offset, case (4) above. */
3529 new_reg
= base_to_reg (&ad
);
3531 /* base + disp => new base, cases (1) and (3) above. */
3532 /* Another option would be to reload the displacement into an
3533 index register. However, postreload has code to optimize
3534 address reloads that have the same base and different
3535 displacements, so reloading into an index register would
3536 not necessarily be a win. */
3537 if (new_reg
== NULL_RTX
)
3539 /* See if the target can split the displacement into a
3540 legitimate new displacement from a local anchor. */
3541 gcc_assert (ad
.disp
== ad
.disp_term
);
3542 poly_int64 orig_offset
;
3543 rtx offset1
, offset2
;
3544 if (poly_int_rtx_p (*ad
.disp
, &orig_offset
)
3545 && targetm
.legitimize_address_displacement (&offset1
, &offset2
,
3549 new_reg
= base_plus_disp_to_reg (&ad
, offset1
);
3550 new_reg
= gen_rtx_PLUS (GET_MODE (new_reg
), new_reg
, offset2
);
3553 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3555 insns
= get_insns ();
3556 last_insn
= get_last_insn ();
3557 /* If we generated at least two insns, try last insn source as
3558 an address. If we succeed, we generate one less insn. */
3560 && last_insn
!= insns
3561 && (set
= single_set (last_insn
)) != NULL_RTX
3562 && GET_CODE (SET_SRC (set
)) == PLUS
3563 && REG_P (XEXP (SET_SRC (set
), 0))
3564 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3566 *ad
.inner
= SET_SRC (set
);
3567 if (valid_address_p (op
, &ad
, cn
))
3569 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3570 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3571 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3572 get_index_code (&ad
));
3573 regno
= REGNO (*ad
.base_term
);
3574 if (regno
>= FIRST_PSEUDO_REGISTER
3575 && cl
!= lra_get_allocno_class (regno
))
3576 lra_change_class (regno
, cl
, " Change to", true);
3577 new_reg
= SET_SRC (set
);
3578 delete_insns_since (PREV_INSN (last_insn
));
3583 *ad
.inner
= new_reg
;
3585 else if (ad
.disp_term
!= NULL
)
3587 /* base + scale * index + disp => new base + scale * index,
3589 gcc_assert (ad
.disp
== ad
.disp_term
);
3590 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3591 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3592 new_reg
, *ad
.index
);
3594 else if ((scale
= get_index_scale (&ad
)) == 1)
3596 /* The last transformation to one reg will be made in
3597 curr_insn_transform function. */
3601 else if (scale
!= 0)
3603 /* base + scale * index => base + new_reg,
3605 Index part of address may become invalid. For example, we
3606 changed pseudo on the equivalent memory and a subreg of the
3607 pseudo onto the memory of different mode for which the scale is
3609 new_reg
= index_part_to_reg (&ad
);
3610 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3611 *ad
.base_term
, new_reg
);
3615 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3617 rtx addr
= *ad
.inner
;
3619 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3620 /* addr => new_base. */
3621 lra_emit_move (new_reg
, addr
);
3622 *ad
.inner
= new_reg
;
3624 *before
= get_insns ();
3629 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3630 Use process_address_1 as a helper function. Return true for any
3633 If CHECK_ONLY_P is true, just check address correctness. Return
3634 false if the address correct. */
3636 process_address (int nop
, bool check_only_p
,
3637 rtx_insn
**before
, rtx_insn
**after
)
3641 while (process_address_1 (nop
, check_only_p
, before
, after
))
3650 /* Emit insns to reload VALUE into a new register. VALUE is an
3651 auto-increment or auto-decrement RTX whose operand is a register or
3652 memory location; so reloading involves incrementing that location.
3653 IN is either identical to VALUE, or some cheaper place to reload
3654 value being incremented/decremented from.
3656 INC_AMOUNT is the number to increment or decrement by (always
3657 positive and ignored for POST_MODIFY/PRE_MODIFY).
3659 Return pseudo containing the result. */
3661 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, poly_int64 inc_amount
)
3663 /* REG or MEM to be copied and incremented. */
3664 rtx incloc
= XEXP (value
, 0);
3665 /* Nonzero if increment after copying. */
3666 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3667 || GET_CODE (value
) == POST_MODIFY
);
3672 rtx real_in
= in
== value
? incloc
: in
;
3676 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3678 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3679 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3680 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3681 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3682 inc
= XEXP (XEXP (value
, 1), 1);
3686 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3687 inc_amount
= -inc_amount
;
3689 inc
= gen_int_mode (inc_amount
, GET_MODE (value
));
3692 if (! post
&& REG_P (incloc
))
3695 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3698 if (real_in
!= result
)
3700 /* First copy the location to the result register. */
3701 lra_assert (REG_P (result
));
3702 emit_insn (gen_move_insn (result
, real_in
));
3705 /* We suppose that there are insns to add/sub with the constant
3706 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3707 old reload worked with this assumption. If the assumption
3708 becomes wrong, we should use approach in function
3709 base_plus_disp_to_reg. */
3712 /* See if we can directly increment INCLOC. */
3713 last
= get_last_insn ();
3714 add_insn
= emit_insn (plus_p
3715 ? gen_add2_insn (incloc
, inc
)
3716 : gen_sub2_insn (incloc
, inc
));
3718 code
= recog_memoized (add_insn
);
3721 if (! post
&& result
!= incloc
)
3722 emit_insn (gen_move_insn (result
, incloc
));
3725 delete_insns_since (last
);
3728 /* If couldn't do the increment directly, must increment in RESULT.
3729 The way we do this depends on whether this is pre- or
3730 post-increment. For pre-increment, copy INCLOC to the reload
3731 register, increment it there, then save back. */
3734 if (real_in
!= result
)
3735 emit_insn (gen_move_insn (result
, real_in
));
3737 emit_insn (gen_add2_insn (result
, inc
));
3739 emit_insn (gen_sub2_insn (result
, inc
));
3740 if (result
!= incloc
)
3741 emit_insn (gen_move_insn (incloc
, result
));
3747 Because this might be a jump insn or a compare, and because
3748 RESULT may not be available after the insn in an input
3749 reload, we must do the incrementing before the insn being
3752 We have already copied IN to RESULT. Increment the copy in
3753 RESULT, save that back, then decrement RESULT so it has
3754 the original value. */
3756 emit_insn (gen_add2_insn (result
, inc
));
3758 emit_insn (gen_sub2_insn (result
, inc
));
3759 emit_insn (gen_move_insn (incloc
, result
));
3760 /* Restore non-modified value for the result. We prefer this
3761 way because it does not require an additional hard
3766 if (poly_int_rtx_p (inc
, &offset
))
3767 emit_insn (gen_add2_insn (result
,
3768 gen_int_mode (-offset
,
3769 GET_MODE (result
))));
3771 emit_insn (gen_sub2_insn (result
, inc
));
3774 emit_insn (gen_add2_insn (result
, inc
));
3779 /* Return true if the current move insn does not need processing as we
3780 already know that it satisfies its constraints. */
3782 simple_move_p (void)
3785 enum reg_class dclass
, sclass
;
3787 lra_assert (curr_insn_set
!= NULL_RTX
);
3788 dest
= SET_DEST (curr_insn_set
);
3789 src
= SET_SRC (curr_insn_set
);
3791 /* If the instruction has multiple sets we need to process it even if it
3792 is single_set. This can happen if one or more of the SETs are dead.
3794 if (multiple_sets (curr_insn
))
3797 return ((dclass
= get_op_class (dest
)) != NO_REGS
3798 && (sclass
= get_op_class (src
)) != NO_REGS
3799 /* The backend guarantees that register moves of cost 2
3800 never need reloads. */
3801 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3804 /* Swap operands NOP and NOP + 1. */
3806 swap_operands (int nop
)
3808 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3809 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3810 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3811 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3812 /* Swap the duplicates too. */
3813 lra_update_dup (curr_id
, nop
);
3814 lra_update_dup (curr_id
, nop
+ 1);
3817 /* Main entry point of the constraint code: search the body of the
3818 current insn to choose the best alternative. It is mimicking insn
3819 alternative cost calculation model of former reload pass. That is
3820 because machine descriptions were written to use this model. This
3821 model can be changed in future. Make commutative operand exchange
3824 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3825 constraints. Return true if any change happened during function
3828 If CHECK_ONLY_P is true then don't do any transformation. Just
3829 check that the insn satisfies all constraints. If the insn does
3830 not satisfy any constraint, return true. */
3832 curr_insn_transform (bool check_only_p
)
3839 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3840 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3841 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3842 rtx_insn
*before
, *after
;
3844 /* Flag that the insn has been changed through a transformation. */
3848 int max_regno_before
;
3849 int reused_alternative_num
;
3851 curr_insn_set
= single_set (curr_insn
);
3852 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3854 /* We assume that the corresponding insn alternative has no
3855 earlier clobbers. If it is not the case, don't define move
3856 cost equal to 2 for the corresponding register classes. */
3857 lra_set_used_insn_alternative (curr_insn
, LRA_NON_CLOBBERED_ALT
);
3861 no_input_reloads_p
= no_output_reloads_p
= false;
3862 goal_alt_number
= -1;
3863 change_p
= sec_mem_p
= false;
3864 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3865 reloads; neither are insns that SET cc0. Insns that use CC0 are
3866 not allowed to have any input reloads. */
3867 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3868 no_output_reloads_p
= true;
3870 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3871 no_input_reloads_p
= true;
3872 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3873 no_output_reloads_p
= true;
3875 n_operands
= curr_static_id
->n_operands
;
3876 n_alternatives
= curr_static_id
->n_alternatives
;
3878 /* Just return "no reloads" if insn has no operands with
3880 if (n_operands
== 0 || n_alternatives
== 0)
3883 max_regno_before
= max_reg_num ();
3885 for (i
= 0; i
< n_operands
; i
++)
3887 goal_alt_matched
[i
][0] = -1;
3888 goal_alt_matches
[i
] = -1;
3891 commutative
= curr_static_id
->commutative
;
3893 /* Now see what we need for pseudos that didn't get hard regs or got
3894 the wrong kind of hard reg. For this, we must consider all the
3895 operands together against the register constraints. */
3897 best_losers
= best_overall
= INT_MAX
;
3898 best_reload_sum
= 0;
3900 curr_swapped
= false;
3901 goal_alt_swapped
= false;
3904 /* Make equivalence substitution and memory subreg elimination
3905 before address processing because an address legitimacy can
3906 depend on memory mode. */
3907 for (i
= 0; i
< n_operands
; i
++)
3910 bool op_change_p
= false;
3912 if (curr_static_id
->operand
[i
].is_operator
)
3915 old
= op
= *curr_id
->operand_loc
[i
];
3916 if (GET_CODE (old
) == SUBREG
)
3917 old
= SUBREG_REG (old
);
3918 subst
= get_equiv_with_elimination (old
, curr_insn
);
3919 original_subreg_reg_mode
[i
] = VOIDmode
;
3920 equiv_substition_p
[i
] = false;
3923 equiv_substition_p
[i
] = true;
3924 subst
= copy_rtx (subst
);
3925 lra_assert (REG_P (old
));
3926 if (GET_CODE (op
) != SUBREG
)
3927 *curr_id
->operand_loc
[i
] = subst
;
3930 SUBREG_REG (op
) = subst
;
3931 if (GET_MODE (subst
) == VOIDmode
)
3932 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3934 if (lra_dump_file
!= NULL
)
3936 fprintf (lra_dump_file
,
3937 "Changing pseudo %d in operand %i of insn %u on equiv ",
3938 REGNO (old
), i
, INSN_UID (curr_insn
));
3939 dump_value_slim (lra_dump_file
, subst
, 1);
3940 fprintf (lra_dump_file
, "\n");
3942 op_change_p
= change_p
= true;
3944 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3947 lra_update_dup (curr_id
, i
);
3951 /* Reload address registers and displacements. We do it before
3952 finding an alternative because of memory constraints. */
3953 before
= after
= NULL
;
3954 for (i
= 0; i
< n_operands
; i
++)
3955 if (! curr_static_id
->operand
[i
].is_operator
3956 && process_address (i
, check_only_p
, &before
, &after
))
3961 lra_update_dup (curr_id
, i
);
3965 /* If we've changed the instruction then any alternative that
3966 we chose previously may no longer be valid. */
3967 lra_set_used_insn_alternative (curr_insn
, LRA_UNKNOWN_ALT
);
3969 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3970 && check_and_process_move (&change_p
, &sec_mem_p
))
3975 reused_alternative_num
= check_only_p
? LRA_UNKNOWN_ALT
: curr_id
->used_insn_alternative
;
3976 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3977 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3978 reused_alternative_num
, INSN_UID (curr_insn
));
3980 if (process_alt_operands (reused_alternative_num
))
3984 return ! alt_p
|| best_losers
!= 0;
3986 /* If insn is commutative (it's safe to exchange a certain pair of
3987 operands) then we need to try each alternative twice, the second
3988 time matching those two operands as if we had exchanged them. To
3989 do this, really exchange them in operands.
3991 If we have just tried the alternatives the second time, return
3992 operands to normal and drop through. */
3994 if (reused_alternative_num
< 0 && commutative
>= 0)
3996 curr_swapped
= !curr_swapped
;
3999 swap_operands (commutative
);
4003 swap_operands (commutative
);
4006 if (! alt_p
&& ! sec_mem_p
)
4008 /* No alternative works with reloads?? */
4009 if (INSN_CODE (curr_insn
) >= 0)
4010 fatal_insn ("unable to generate reloads for:", curr_insn
);
4011 error_for_asm (curr_insn
,
4012 "inconsistent operand constraints in an %<asm%>");
4013 lra_asm_error_p
= true;
4014 /* Avoid further trouble with this insn. Don't generate use
4015 pattern here as we could use the insn SP offset. */
4016 lra_set_insn_deleted (curr_insn
);
4020 /* If the best alternative is with operands 1 and 2 swapped, swap
4021 them. Update the operand numbers of any reloads already
4024 if (goal_alt_swapped
)
4026 if (lra_dump_file
!= NULL
)
4027 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
4028 INSN_UID (curr_insn
));
4030 /* Swap the duplicates too. */
4031 swap_operands (commutative
);
4035 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
4036 too conservatively. So we use the secondary memory only if there
4037 is no any alternative without reloads. */
4038 use_sec_mem_p
= false;
4040 use_sec_mem_p
= true;
4043 for (i
= 0; i
< n_operands
; i
++)
4044 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
4046 use_sec_mem_p
= i
< n_operands
;
4051 int in
= -1, out
= -1;
4052 rtx new_reg
, src
, dest
, rld
;
4053 machine_mode sec_mode
, rld_mode
;
4055 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
4056 dest
= SET_DEST (curr_insn_set
);
4057 src
= SET_SRC (curr_insn_set
);
4058 for (i
= 0; i
< n_operands
; i
++)
4059 if (*curr_id
->operand_loc
[i
] == dest
)
4061 else if (*curr_id
->operand_loc
[i
] == src
)
4063 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
4064 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
4065 out
= curr_static_id
->dup_num
[i
];
4066 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
4067 in
= curr_static_id
->dup_num
[i
];
4068 lra_assert (out
>= 0 && in
>= 0
4069 && curr_static_id
->operand
[out
].type
== OP_OUT
4070 && curr_static_id
->operand
[in
].type
== OP_IN
);
4071 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
4072 rld_mode
= GET_MODE (rld
);
4073 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
4074 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
4075 NO_REGS
, "secondary");
4076 /* If the mode is changed, it should be wider. */
4077 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
4078 if (sec_mode
!= rld_mode
)
4080 /* If the target says specifically to use another mode for
4081 secondary memory moves we cannot reuse the original
4083 after
= emit_spill_move (false, new_reg
, dest
);
4084 lra_process_new_insns (curr_insn
, NULL
, after
,
4085 "Inserting the sec. move");
4086 /* We may have non null BEFORE here (e.g. after address
4088 push_to_sequence (before
);
4089 before
= emit_spill_move (true, new_reg
, src
);
4091 before
= get_insns ();
4093 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
4094 lra_set_insn_deleted (curr_insn
);
4096 else if (dest
== rld
)
4098 *curr_id
->operand_loc
[out
] = new_reg
;
4099 lra_update_dup (curr_id
, out
);
4100 after
= emit_spill_move (false, new_reg
, dest
);
4101 lra_process_new_insns (curr_insn
, NULL
, after
,
4102 "Inserting the sec. move");
4106 *curr_id
->operand_loc
[in
] = new_reg
;
4107 lra_update_dup (curr_id
, in
);
4108 /* See comments above. */
4109 push_to_sequence (before
);
4110 before
= emit_spill_move (true, new_reg
, src
);
4112 before
= get_insns ();
4114 lra_process_new_insns (curr_insn
, before
, NULL
,
4115 "Inserting the sec. move");
4117 lra_update_insn_regno_info (curr_insn
);
4121 lra_assert (goal_alt_number
>= 0);
4122 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
4124 if (lra_dump_file
!= NULL
)
4128 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4129 goal_alt_number
, INSN_UID (curr_insn
));
4130 for (i
= 0; i
< n_operands
; i
++)
4132 p
= (curr_static_id
->operand_alternative
4133 [goal_alt_number
* n_operands
+ i
].constraint
);
4136 fprintf (lra_dump_file
, " (%d) ", i
);
4137 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
4138 fputc (*p
, lra_dump_file
);
4140 if (INSN_CODE (curr_insn
) >= 0
4141 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4142 fprintf (lra_dump_file
, " {%s}", p
);
4143 if (maybe_ne (curr_id
->sp_offset
, 0))
4145 fprintf (lra_dump_file
, " (sp_off=");
4146 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4147 fprintf (lra_dump_file
, ")");
4149 fprintf (lra_dump_file
, "\n");
4152 /* Right now, for any pair of operands I and J that are required to
4153 match, with J < I, goal_alt_matches[I] is J. Add I to
4154 goal_alt_matched[J]. */
4156 for (i
= 0; i
< n_operands
; i
++)
4157 if ((j
= goal_alt_matches
[i
]) >= 0)
4159 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4161 /* We allow matching one output operand and several input
4164 || (curr_static_id
->operand
[j
].type
== OP_OUT
4165 && curr_static_id
->operand
[i
].type
== OP_IN
4166 && (curr_static_id
->operand
4167 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4168 goal_alt_matched
[j
][k
] = i
;
4169 goal_alt_matched
[j
][k
+ 1] = -1;
4172 for (i
= 0; i
< n_operands
; i
++)
4173 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4175 /* Any constants that aren't allowed and can't be reloaded into
4176 registers are here changed into memory references. */
4177 for (i
= 0; i
< n_operands
; i
++)
4178 if (goal_alt_win
[i
])
4181 enum reg_class new_class
;
4182 rtx reg
= *curr_id
->operand_loc
[i
];
4184 if (GET_CODE (reg
) == SUBREG
)
4185 reg
= SUBREG_REG (reg
);
4187 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4189 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4191 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4194 lra_change_class (regno
, new_class
, " Change to", true);
4200 const char *constraint
;
4202 rtx op
= *curr_id
->operand_loc
[i
];
4203 rtx subreg
= NULL_RTX
;
4204 machine_mode mode
= curr_operand_mode
[i
];
4206 if (GET_CODE (op
) == SUBREG
)
4209 op
= SUBREG_REG (op
);
4210 mode
= GET_MODE (op
);
4213 if (CONST_POOL_OK_P (mode
, op
)
4214 && ((targetm
.preferred_reload_class
4215 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4216 || no_input_reloads_p
))
4218 rtx tem
= force_const_mem (mode
, op
);
4221 if (subreg
!= NULL_RTX
)
4222 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4224 *curr_id
->operand_loc
[i
] = tem
;
4225 lra_update_dup (curr_id
, i
);
4226 process_address (i
, false, &before
, &after
);
4228 /* If the alternative accepts constant pool refs directly
4229 there will be no reload needed at all. */
4230 if (subreg
!= NULL_RTX
)
4232 /* Skip alternatives before the one requested. */
4233 constraint
= (curr_static_id
->operand_alternative
4234 [goal_alt_number
* n_operands
+ i
].constraint
);
4236 (c
= *constraint
) && c
!= ',' && c
!= '#';
4237 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4239 enum constraint_num cn
= lookup_constraint (constraint
);
4240 if ((insn_extra_memory_constraint (cn
)
4241 || insn_extra_special_memory_constraint (cn
))
4242 && satisfies_memory_constraint_p (tem
, cn
))
4245 if (c
== '\0' || c
== ',' || c
== '#')
4248 goal_alt_win
[i
] = true;
4254 for (i
= 0; i
< n_operands
; i
++)
4257 bool optional_p
= false;
4259 rtx op
= *curr_id
->operand_loc
[i
];
4261 if (goal_alt_win
[i
])
4263 if (goal_alt
[i
] == NO_REGS
4265 /* When we assign NO_REGS it means that we will not
4266 assign a hard register to the scratch pseudo by
4267 assigment pass and the scratch pseudo will be
4268 spilled. Spilled scratch pseudos are transformed
4269 back to scratches at the LRA end. */
4270 && lra_former_scratch_operand_p (curr_insn
, i
)
4271 && lra_former_scratch_p (REGNO (op
)))
4273 int regno
= REGNO (op
);
4274 lra_change_class (regno
, NO_REGS
, " Change to", true);
4275 if (lra_get_regno_hard_regno (regno
) >= 0)
4276 /* We don't have to mark all insn affected by the
4277 spilled pseudo as there is only one such insn, the
4279 reg_renumber
[regno
] = -1;
4280 lra_assert (bitmap_single_bit_set_p
4281 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4283 /* We can do an optional reload. If the pseudo got a hard
4284 reg, we might improve the code through inheritance. If
4285 it does not get a hard register we coalesce memory/memory
4286 moves later. Ignore move insns to avoid cycling. */
4288 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4289 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4290 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4291 && regno
< new_regno_start
4292 && ! lra_former_scratch_p (regno
)
4293 && reg_renumber
[regno
] < 0
4294 /* Check that the optional reload pseudo will be able to
4295 hold given mode value. */
4296 && ! (prohibited_class_reg_set_mode_p
4297 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4298 PSEUDO_REGNO_MODE (regno
)))
4299 && (curr_insn_set
== NULL_RTX
4300 || !((REG_P (SET_SRC (curr_insn_set
))
4301 || MEM_P (SET_SRC (curr_insn_set
))
4302 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4303 && (REG_P (SET_DEST (curr_insn_set
))
4304 || MEM_P (SET_DEST (curr_insn_set
))
4305 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4307 else if (goal_alt_matched
[i
][0] != -1
4308 && curr_static_id
->operand
[i
].type
== OP_OUT
4309 && (curr_static_id
->operand_alternative
4310 [goal_alt_number
* n_operands
+ i
].earlyclobber
)
4313 for (j
= 0; goal_alt_matched
[i
][j
] != -1; j
++)
4315 rtx op2
= *curr_id
->operand_loc
[goal_alt_matched
[i
][j
]];
4317 if (REG_P (op2
) && REGNO (op
) != REGNO (op2
))
4320 if (goal_alt_matched
[i
][j
] != -1)
4322 /* Generate reloads for different output and matched
4323 input registers. This is the easiest way to avoid
4324 creation of non-existing register conflicts in
4326 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4328 outputs
[n_outputs
++] = i
;
4329 outputs
[n_outputs
] = -1;
4337 /* Operands that match previous ones have already been handled. */
4338 if (goal_alt_matches
[i
] >= 0)
4341 /* We should not have an operand with a non-offsettable address
4342 appearing where an offsettable address will do. It also may
4343 be a case when the address should be special in other words
4344 not a general one (e.g. it needs no index reg). */
4345 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4347 enum reg_class rclass
;
4348 rtx
*loc
= &XEXP (op
, 0);
4349 enum rtx_code code
= GET_CODE (*loc
);
4351 push_to_sequence (before
);
4352 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4354 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4355 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4356 /* This value does not matter for MODIFY. */
4357 GET_MODE_SIZE (GET_MODE (op
)));
4358 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4359 "offsetable address", &new_reg
))
4362 enum rtx_code code
= GET_CODE (addr
);
4364 if (code
== AND
&& CONST_INT_P (XEXP (addr
, 1)))
4365 /* (and ... (const_int -X)) is used to align to X bytes. */
4366 addr
= XEXP (*loc
, 0);
4367 lra_emit_move (new_reg
, addr
);
4369 emit_move_insn (new_reg
, gen_rtx_AND (GET_MODE (new_reg
), new_reg
, XEXP (*loc
, 1)));
4371 before
= get_insns ();
4374 lra_update_dup (curr_id
, i
);
4376 else if (goal_alt_matched
[i
][0] == -1)
4381 enum op_type type
= curr_static_id
->operand
[i
].type
;
4383 loc
= curr_id
->operand_loc
[i
];
4384 mode
= curr_operand_mode
[i
];
4385 if (GET_CODE (*loc
) == SUBREG
)
4387 reg
= SUBREG_REG (*loc
);
4388 poly_int64 byte
= SUBREG_BYTE (*loc
);
4390 /* Strict_low_part requires reloading the register and not
4391 just the subreg. Likewise for a strict subreg no wider
4392 than a word for WORD_REGISTER_OPERATIONS targets. */
4393 && (curr_static_id
->operand
[i
].strict_low
4394 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4396 = get_try_hard_regno (REGNO (reg
))) >= 0
4397 && (simplify_subreg_regno
4399 GET_MODE (reg
), byte
, mode
) < 0)
4400 && (goal_alt
[i
] == NO_REGS
4401 || (simplify_subreg_regno
4402 (ira_class_hard_regs
[goal_alt
[i
]][0],
4403 GET_MODE (reg
), byte
, mode
) >= 0)))
4404 || (partial_subreg_p (mode
, GET_MODE (reg
))
4405 && known_le (GET_MODE_SIZE (GET_MODE (reg
)),
4407 && WORD_REGISTER_OPERATIONS
)))
4409 /* An OP_INOUT is required when reloading a subreg of a
4410 mode wider than a word to ensure that data beyond the
4411 word being reloaded is preserved. Also automatically
4412 ensure that strict_low_part reloads are made into
4413 OP_INOUT which should already be true from the backend
4416 && (curr_static_id
->operand
[i
].strict_low
4417 || read_modify_subreg_p (*loc
)))
4419 loc
= &SUBREG_REG (*loc
);
4420 mode
= GET_MODE (*loc
);
4424 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4425 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4428 push_to_sequence (before
);
4429 lra_emit_move (new_reg
, old
);
4430 before
= get_insns ();
4435 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4438 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4440 after
= get_insns ();
4444 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4445 if (goal_alt_dont_inherit_ops
[j
] == i
)
4447 lra_set_regno_unique_value (REGNO (new_reg
));
4450 lra_update_dup (curr_id
, i
);
4452 else if (curr_static_id
->operand
[i
].type
== OP_IN
4453 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4455 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4457 && (operands_match_p
4458 (*curr_id
->operand_loc
[i
],
4459 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4462 /* generate reloads for input and matched outputs. */
4463 match_inputs
[0] = i
;
4464 match_inputs
[1] = -1;
4465 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4466 goal_alt
[i
], &before
, &after
,
4467 curr_static_id
->operand_alternative
4468 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4471 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4472 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4473 && (operands_match_p
4474 (*curr_id
->operand_loc
[i
],
4475 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4477 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4479 /* Generate reloads for output and matched inputs. */
4480 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4481 &after
, curr_static_id
->operand_alternative
4482 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4483 else if (curr_static_id
->operand
[i
].type
== OP_IN
4484 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4487 /* Generate reloads for matched inputs. */
4488 match_inputs
[0] = i
;
4489 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4490 match_inputs
[j
+ 1] = k
;
4491 match_inputs
[j
+ 1] = -1;
4492 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4496 /* We must generate code in any case when function
4497 process_alt_operands decides that it is possible. */
4500 /* Memorise processed outputs so that output remaining to be processed
4501 can avoid using the same register value (see match_reload). */
4502 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4504 outputs
[n_outputs
++] = i
;
4505 outputs
[n_outputs
] = -1;
4512 lra_assert (REG_P (reg
));
4513 regno
= REGNO (reg
);
4514 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4515 if (GET_CODE (op
) == SUBREG
)
4516 op
= SUBREG_REG (op
);
4517 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4518 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4519 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4520 if (lra_dump_file
!= NULL
)
4521 fprintf (lra_dump_file
,
4522 " Making reload reg %d for reg %d optional\n",
4526 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4527 || max_regno_before
!= max_reg_num ())
4531 lra_update_operator_dups (curr_id
);
4532 /* Something changes -- process the insn. */
4533 lra_update_insn_regno_info (curr_insn
);
4535 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4539 /* Return true if INSN satisfies all constraints. In other words, no
4540 reload insns are needed. */
4542 lra_constrain_insn (rtx_insn
*insn
)
4544 int saved_new_regno_start
= new_regno_start
;
4545 int saved_new_insn_uid_start
= new_insn_uid_start
;
4549 curr_id
= lra_get_insn_recog_data (curr_insn
);
4550 curr_static_id
= curr_id
->insn_static_data
;
4551 new_insn_uid_start
= get_max_uid ();
4552 new_regno_start
= max_reg_num ();
4553 change_p
= curr_insn_transform (true);
4554 new_regno_start
= saved_new_regno_start
;
4555 new_insn_uid_start
= saved_new_insn_uid_start
;
4559 /* Return true if X is in LIST. */
4561 in_list_p (rtx x
, rtx list
)
4563 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4564 if (XEXP (list
, 0) == x
)
4569 /* Return true if X contains an allocatable hard register (if
4570 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4572 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4578 code
= GET_CODE (x
);
4581 int regno
= REGNO (x
);
4582 HARD_REG_SET alloc_regs
;
4586 if (regno
>= FIRST_PSEUDO_REGISTER
)
4587 regno
= lra_get_regno_hard_regno (regno
);
4590 alloc_regs
= ~lra_no_alloc_regs
;
4591 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4595 if (regno
< FIRST_PSEUDO_REGISTER
)
4599 return lra_get_regno_hard_regno (regno
) < 0;
4602 fmt
= GET_RTX_FORMAT (code
);
4603 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4607 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4610 else if (fmt
[i
] == 'E')
4612 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4613 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4620 /* Process all regs in location *LOC and change them on equivalent
4621 substitution. Return true if any change was done. */
4623 loc_equivalence_change_p (rtx
*loc
)
4625 rtx subst
, reg
, x
= *loc
;
4626 bool result
= false;
4627 enum rtx_code code
= GET_CODE (x
);
4633 reg
= SUBREG_REG (x
);
4634 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4635 && GET_MODE (subst
) == VOIDmode
)
4637 /* We cannot reload debug location. Simplify subreg here
4638 while we know the inner mode. */
4639 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4640 GET_MODE (reg
), SUBREG_BYTE (x
));
4644 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4650 /* Scan all the operand sub-expressions. */
4651 fmt
= GET_RTX_FORMAT (code
);
4652 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4655 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4656 else if (fmt
[i
] == 'E')
4657 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4659 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4664 /* Similar to loc_equivalence_change_p, but for use as
4665 simplify_replace_fn_rtx callback. DATA is insn for which the
4666 elimination is done. If it null we don't do the elimination. */
4668 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4673 rtx subst
= (data
== NULL
4674 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4681 /* Maximum number of generated reload insns per an insn. It is for
4682 preventing this pass cycling in a bug case. */
4683 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4685 /* The current iteration number of this LRA pass. */
4686 int lra_constraint_iter
;
4688 /* True if we should during assignment sub-pass check assignment
4689 correctness for all pseudos and spill some of them to correct
4690 conflicts. It can be necessary when we substitute equiv which
4691 needs checking register allocation correctness because the
4692 equivalent value contains allocatable hard registers, or when we
4693 restore multi-register pseudo, or when we change the insn code and
4694 its operand became INOUT operand when it was IN one before. */
4695 bool check_and_force_assignment_correctness_p
;
4697 /* Return true if REGNO is referenced in more than one block. */
4699 multi_block_pseudo_p (int regno
)
4701 basic_block bb
= NULL
;
4705 if (regno
< FIRST_PSEUDO_REGISTER
)
4708 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4710 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4711 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4716 /* Return true if LIST contains a deleted insn. */
4718 contains_deleted_insn_p (rtx_insn_list
*list
)
4720 for (; list
!= NULL_RTX
; list
= list
->next ())
4721 if (NOTE_P (list
->insn ())
4722 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4727 /* Return true if X contains a pseudo dying in INSN. */
4729 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4736 return (insn
!= NULL_RTX
4737 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4738 code
= GET_CODE (x
);
4739 fmt
= GET_RTX_FORMAT (code
);
4740 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4744 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4747 else if (fmt
[i
] == 'E')
4749 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4750 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4757 /* Return true if INSN contains a dying pseudo in INSN right hand
4760 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4762 rtx set
= single_set (insn
);
4764 gcc_assert (set
!= NULL
);
4765 return dead_pseudo_p (SET_SRC (set
), insn
);
4768 /* Return true if any init insn of REGNO contains a dying pseudo in
4769 insn right hand side. */
4771 init_insn_rhs_dead_pseudo_p (int regno
)
4773 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4777 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4778 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4783 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4784 reverse only if we have one init insn with given REGNO as a
4787 reverse_equiv_p (int regno
)
4789 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4794 if (! INSN_P (insns
->insn ())
4795 || insns
->next () != NULL
)
4797 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4799 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4802 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4803 call this function only for non-reverse equivalence. */
4805 contains_reloaded_insn_p (int regno
)
4808 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4810 for (; list
!= NULL
; list
= list
->next ())
4811 if ((set
= single_set (list
->insn ())) == NULL_RTX
4812 || ! REG_P (SET_DEST (set
))
4813 || (int) REGNO (SET_DEST (set
)) != regno
)
4818 /* Entry function of LRA constraint pass. Return true if the
4819 constraint pass did change the code. */
4821 lra_constraints (bool first_p
)
4824 int i
, hard_regno
, new_insns_num
;
4825 unsigned int min_len
, new_min_len
, uid
;
4826 rtx set
, x
, reg
, dest_reg
;
4827 basic_block last_bb
;
4830 lra_constraint_iter
++;
4831 if (lra_dump_file
!= NULL
)
4832 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4833 lra_constraint_iter
);
4835 if (pic_offset_table_rtx
4836 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4837 check_and_force_assignment_correctness_p
= true;
4839 /* On the first iteration we should check IRA assignment
4840 correctness. In rare cases, the assignments can be wrong as
4841 early clobbers operands are ignored in IRA or usages of
4842 paradoxical sub-registers are not taken into account by
4844 check_and_force_assignment_correctness_p
= true;
4845 new_insn_uid_start
= get_max_uid ();
4846 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4847 /* Mark used hard regs for target stack size calulations. */
4848 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4849 if (lra_reg_info
[i
].nrefs
!= 0
4850 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4854 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
4855 for (j
= 0; j
< nregs
; j
++)
4856 df_set_regs_ever_live (hard_regno
+ j
, true);
4858 /* Do elimination before the equivalence processing as we can spill
4859 some pseudos during elimination. */
4860 lra_eliminate (false, first_p
);
4861 auto_bitmap
equiv_insn_bitmap (®_obstack
);
4862 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4863 if (lra_reg_info
[i
].nrefs
!= 0)
4865 ira_reg_equiv
[i
].profitable_p
= true;
4866 reg
= regno_reg_rtx
[i
];
4867 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4869 bool pseudo_p
= contains_reg_p (x
, false, false);
4871 /* After RTL transformation, we cannot guarantee that
4872 pseudo in the substitution was not reloaded which might
4873 make equivalence invalid. For example, in reverse
4880 the memory address register was reloaded before the 2nd
4882 if ((! first_p
&& pseudo_p
)
4883 /* We don't use DF for compilation speed sake. So it
4884 is problematic to update live info when we use an
4885 equivalence containing pseudos in more than one
4887 || (pseudo_p
&& multi_block_pseudo_p (i
))
4888 /* If an init insn was deleted for some reason, cancel
4889 the equiv. We could update the equiv insns after
4890 transformations including an equiv insn deletion
4891 but it is not worthy as such cases are extremely
4893 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4894 /* If it is not a reverse equivalence, we check that a
4895 pseudo in rhs of the init insn is not dying in the
4896 insn. Otherwise, the live info at the beginning of
4897 the corresponding BB might be wrong after we
4898 removed the insn. When the equiv can be a
4899 constant, the right hand side of the init insn can
4901 || (! reverse_equiv_p (i
)
4902 && (init_insn_rhs_dead_pseudo_p (i
)
4903 /* If we reloaded the pseudo in an equivalence
4904 init insn, we cannot remove the equiv init
4905 insns and the init insns might write into
4906 const memory in this case. */
4907 || contains_reloaded_insn_p (i
)))
4908 /* Prevent access beyond equivalent memory for
4909 paradoxical subregs. */
4911 && maybe_gt (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
),
4912 GET_MODE_SIZE (GET_MODE (x
))))
4913 || (pic_offset_table_rtx
4914 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4915 && (targetm
.preferred_reload_class
4916 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4917 || contains_symbol_ref_p (x
))))
4918 ira_reg_equiv
[i
].defined_p
= false;
4919 if (contains_reg_p (x
, false, true))
4920 ira_reg_equiv
[i
].profitable_p
= false;
4921 if (get_equiv (reg
) != reg
)
4922 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4925 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4927 /* We should add all insns containing pseudos which should be
4928 substituted by their equivalences. */
4929 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
4930 lra_push_insn_by_uid (uid
);
4931 min_len
= lra_insn_stack_length ();
4935 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4937 curr_insn
= lra_pop_insn ();
4939 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4940 if (curr_bb
!= last_bb
)
4943 bb_reload_num
= lra_curr_reload_num
;
4945 if (min_len
> new_min_len
)
4947 min_len
= new_min_len
;
4950 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4952 ("maximum number of generated reload insns per insn achieved (%d)",
4953 MAX_RELOAD_INSNS_NUMBER
);
4955 if (DEBUG_INSN_P (curr_insn
))
4957 /* We need to check equivalence in debug insn and change
4958 pseudo to the equivalent value if necessary. */
4959 curr_id
= lra_get_insn_recog_data (curr_insn
);
4960 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4962 rtx old
= *curr_id
->operand_loc
[0];
4963 *curr_id
->operand_loc
[0]
4964 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4965 loc_equivalence_callback
, curr_insn
);
4966 if (old
!= *curr_id
->operand_loc
[0])
4968 lra_update_insn_regno_info (curr_insn
);
4973 else if (INSN_P (curr_insn
))
4975 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4977 dest_reg
= SET_DEST (set
);
4978 /* The equivalence pseudo could be set up as SUBREG in a
4979 case when it is a call restore insn in a mode
4980 different from the pseudo mode. */
4981 if (GET_CODE (dest_reg
) == SUBREG
)
4982 dest_reg
= SUBREG_REG (dest_reg
);
4983 if ((REG_P (dest_reg
)
4984 && (x
= get_equiv (dest_reg
)) != dest_reg
4985 /* Remove insns which set up a pseudo whose value
4986 cannot be changed. Such insns might be not in
4987 init_insns because we don't update equiv data
4988 during insn transformations.
4990 As an example, let suppose that a pseudo got
4991 hard register and on the 1st pass was not
4992 changed to equivalent constant. We generate an
4993 additional insn setting up the pseudo because of
4994 secondary memory movement. Then the pseudo is
4995 spilled and we use the equiv constant. In this
4996 case we should remove the additional insn and
4997 this insn is not init_insns list. */
4998 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4999 /* Check that this is actually an insn setting
5000 up the equivalence. */
5001 || in_list_p (curr_insn
,
5003 [REGNO (dest_reg
)].init_insns
)))
5004 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
5005 && in_list_p (curr_insn
,
5007 [REGNO (SET_SRC (set
))].init_insns
)))
5009 /* This is equiv init insn of pseudo which did not get a
5010 hard register -- remove the insn. */
5011 if (lra_dump_file
!= NULL
)
5013 fprintf (lra_dump_file
,
5014 " Removing equiv init insn %i (freq=%d)\n",
5015 INSN_UID (curr_insn
),
5016 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
5017 dump_insn_slim (lra_dump_file
, curr_insn
);
5019 if (contains_reg_p (x
, true, false))
5020 check_and_force_assignment_correctness_p
= true;
5021 lra_set_insn_deleted (curr_insn
);
5025 curr_id
= lra_get_insn_recog_data (curr_insn
);
5026 curr_static_id
= curr_id
->insn_static_data
;
5027 init_curr_insn_input_reloads ();
5028 init_curr_operand_mode ();
5029 if (curr_insn_transform (false))
5031 /* Check non-transformed insns too for equiv change as USE
5032 or CLOBBER don't need reloads but can contain pseudos
5033 being changed on their equivalences. */
5034 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
5035 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
5037 lra_update_insn_regno_info (curr_insn
);
5043 /* If we used a new hard regno, changed_p should be true because the
5044 hard reg is assigned to a new pseudo. */
5045 if (flag_checking
&& !changed_p
)
5047 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5048 if (lra_reg_info
[i
].nrefs
!= 0
5049 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
5051 int j
, nregs
= hard_regno_nregs (hard_regno
,
5052 PSEUDO_REGNO_MODE (i
));
5054 for (j
= 0; j
< nregs
; j
++)
5055 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
5061 static void initiate_invariants (void);
5062 static void finish_invariants (void);
5064 /* Initiate the LRA constraint pass. It is done once per
5067 lra_constraints_init (void)
5069 initiate_invariants ();
5072 /* Finalize the LRA constraint pass. It is done once per
5075 lra_constraints_finish (void)
5077 finish_invariants ();
5082 /* Structure describes invariants for ineheritance. */
5083 struct lra_invariant
5085 /* The order number of the invariant. */
5087 /* The invariant RTX. */
5089 /* The origin insn of the invariant. */
5093 typedef lra_invariant invariant_t
;
5094 typedef invariant_t
*invariant_ptr_t
;
5095 typedef const invariant_t
*const_invariant_ptr_t
;
5097 /* Pointer to the inheritance invariants. */
5098 static vec
<invariant_ptr_t
> invariants
;
5100 /* Allocation pool for the invariants. */
5101 static object_allocator
<lra_invariant
> *invariants_pool
;
5103 /* Hash table for the invariants. */
5104 static htab_t invariant_table
;
5106 /* Hash function for INVARIANT. */
5108 invariant_hash (const void *invariant
)
5110 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
5111 return lra_rtx_hash (inv
);
5114 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
5116 invariant_eq_p (const void *invariant1
, const void *invariant2
)
5118 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
5119 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
5121 return rtx_equal_p (inv1
, inv2
);
5124 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5125 invariant which is in the table. */
5126 static invariant_ptr_t
5127 insert_invariant (rtx invariant_rtx
)
5130 invariant_t invariant
;
5131 invariant_ptr_t invariant_ptr
;
5133 invariant
.invariant_rtx
= invariant_rtx
;
5134 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
5135 if (*entry_ptr
== NULL
)
5137 invariant_ptr
= invariants_pool
->allocate ();
5138 invariant_ptr
->invariant_rtx
= invariant_rtx
;
5139 invariant_ptr
->insn
= NULL
;
5140 invariants
.safe_push (invariant_ptr
);
5141 *entry_ptr
= (void *) invariant_ptr
;
5143 return (invariant_ptr_t
) *entry_ptr
;
5146 /* Initiate the invariant table. */
5148 initiate_invariants (void)
5150 invariants
.create (100);
5152 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
5153 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
5156 /* Finish the invariant table. */
5158 finish_invariants (void)
5160 htab_delete (invariant_table
);
5161 delete invariants_pool
;
5162 invariants
.release ();
5165 /* Make the invariant table empty. */
5167 clear_invariants (void)
5169 htab_empty (invariant_table
);
5170 invariants_pool
->release ();
5171 invariants
.truncate (0);
5176 /* This page contains code to do inheritance/split
5179 /* Number of reloads passed so far in current EBB. */
5180 static int reloads_num
;
5182 /* Number of calls passed so far in current EBB. */
5183 static int calls_num
;
5185 /* Index ID is the CALLS_NUM associated the last call we saw with
5186 ABI identifier ID. */
5187 static int last_call_for_abi
[NUM_ABI_IDS
];
5189 /* Which registers have been fully or partially clobbered by a call
5190 since they were last used. */
5191 static HARD_REG_SET full_and_partial_call_clobbers
;
5193 /* Current reload pseudo check for validity of elements in
5195 static int curr_usage_insns_check
;
5197 /* Info about last usage of registers in EBB to do inheritance/split
5198 transformation. Inheritance transformation is done from a spilled
5199 pseudo and split transformations from a hard register or a pseudo
5200 assigned to a hard register. */
5203 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5204 value INSNS is valid. The insns is chain of optional debug insns
5205 and a finishing non-debug insn using the corresponding reg. The
5206 value is also used to mark the registers which are set up in the
5207 current insn. The negated insn uid is used for this. */
5209 /* Value of global reloads_num at the last insn in INSNS. */
5211 /* Value of global reloads_nums at the last insn in INSNS. */
5213 /* It can be true only for splitting. And it means that the restore
5214 insn should be put after insn given by the following member. */
5216 /* Next insns in the current EBB which use the original reg and the
5217 original reg value is not changed between the current insn and
5218 the next insns. In order words, e.g. for inheritance, if we need
5219 to use the original reg value again in the next insns we can try
5220 to use the value in a hard register from a reload insn of the
5225 /* Map: regno -> corresponding pseudo usage insns. */
5226 static struct usage_insns
*usage_insns
;
5229 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5231 usage_insns
[regno
].check
= curr_usage_insns_check
;
5232 usage_insns
[regno
].insns
= insn
;
5233 usage_insns
[regno
].reloads_num
= reloads_num
;
5234 usage_insns
[regno
].calls_num
= calls_num
;
5235 usage_insns
[regno
].after_p
= after_p
;
5236 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0)
5237 remove_from_hard_reg_set (&full_and_partial_call_clobbers
,
5238 PSEUDO_REGNO_MODE (regno
),
5239 reg_renumber
[regno
]);
5242 /* The function is used to form list REGNO usages which consists of
5243 optional debug insns finished by a non-debug insn using REGNO.
5244 RELOADS_NUM is current number of reload insns processed so far. */
5246 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5248 rtx next_usage_insns
;
5250 if (usage_insns
[regno
].check
== curr_usage_insns_check
5251 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5252 && DEBUG_INSN_P (insn
))
5254 /* Check that we did not add the debug insn yet. */
5255 if (next_usage_insns
!= insn
5256 && (GET_CODE (next_usage_insns
) != INSN_LIST
5257 || XEXP (next_usage_insns
, 0) != insn
))
5258 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5261 else if (NONDEBUG_INSN_P (insn
))
5262 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5264 usage_insns
[regno
].check
= 0;
5267 /* Return first non-debug insn in list USAGE_INSNS. */
5269 skip_usage_debug_insns (rtx usage_insns
)
5273 /* Skip debug insns. */
5274 for (insn
= usage_insns
;
5275 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5276 insn
= XEXP (insn
, 1))
5278 return safe_as_a
<rtx_insn
*> (insn
);
5281 /* Return true if we need secondary memory moves for insn in
5282 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5285 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5286 rtx usage_insns ATTRIBUTE_UNUSED
)
5292 if (inher_cl
== ALL_REGS
5293 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5295 lra_assert (INSN_P (insn
));
5296 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5298 dest
= SET_DEST (set
);
5301 lra_assert (inher_cl
!= NO_REGS
);
5302 cl
= get_reg_class (REGNO (dest
));
5303 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5304 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5307 /* Registers involved in inheritance/split in the current EBB
5308 (inheritance/split pseudos and original registers). */
5309 static bitmap_head check_only_regs
;
5311 /* Reload pseudos cannot be involded in invariant inheritance in the
5313 static bitmap_head invalid_invariant_regs
;
5315 /* Do inheritance transformations for insn INSN, which defines (if
5316 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5317 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5318 form as the "insns" field of usage_insns. Return true if we
5319 succeed in such transformation.
5321 The transformations look like:
5324 ... p <- i (new insn)
5326 <- ... p ... <- ... i ...
5328 ... i <- p (new insn)
5329 <- ... p ... <- ... i ...
5331 <- ... p ... <- ... i ...
5332 where p is a spilled original pseudo and i is a new inheritance pseudo.
5335 The inheritance pseudo has the smallest class of two classes CL and
5336 class of ORIGINAL REGNO. */
5338 inherit_reload_reg (bool def_p
, int original_regno
,
5339 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5341 if (optimize_function_for_size_p (cfun
))
5344 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5345 rtx original_reg
= regno_reg_rtx
[original_regno
];
5346 rtx new_reg
, usage_insn
;
5347 rtx_insn
*new_insns
;
5349 lra_assert (! usage_insns
[original_regno
].after_p
);
5350 if (lra_dump_file
!= NULL
)
5351 fprintf (lra_dump_file
,
5352 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5353 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5355 if (lra_dump_file
!= NULL
)
5357 fprintf (lra_dump_file
,
5358 " Rejecting inheritance for %d "
5359 "because of disjoint classes %s and %s\n",
5360 original_regno
, reg_class_names
[cl
],
5361 reg_class_names
[rclass
]);
5362 fprintf (lra_dump_file
,
5363 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5367 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5368 /* We don't use a subset of two classes because it can be
5369 NO_REGS. This transformation is still profitable in most
5370 cases even if the classes are not intersected as register
5371 move is probably cheaper than a memory load. */
5372 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5374 if (lra_dump_file
!= NULL
)
5375 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5376 reg_class_names
[cl
], reg_class_names
[rclass
]);
5380 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5382 /* Reject inheritance resulting in secondary memory moves.
5383 Otherwise, there is a danger in LRA cycling. Also such
5384 transformation will be unprofitable. */
5385 if (lra_dump_file
!= NULL
)
5387 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5388 rtx set
= single_set (insn
);
5390 lra_assert (set
!= NULL_RTX
);
5392 rtx dest
= SET_DEST (set
);
5394 lra_assert (REG_P (dest
));
5395 fprintf (lra_dump_file
,
5396 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5397 "as secondary mem is needed\n",
5398 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5399 original_regno
, reg_class_names
[rclass
]);
5400 fprintf (lra_dump_file
,
5401 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5405 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5406 rclass
, "inheritance");
5409 lra_emit_move (original_reg
, new_reg
);
5411 lra_emit_move (new_reg
, original_reg
);
5412 new_insns
= get_insns ();
5414 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5416 if (lra_dump_file
!= NULL
)
5418 fprintf (lra_dump_file
,
5419 " Rejecting inheritance %d->%d "
5420 "as it results in 2 or more insns:\n",
5421 original_regno
, REGNO (new_reg
));
5422 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5423 fprintf (lra_dump_file
,
5424 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5428 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5429 lra_update_insn_regno_info (insn
);
5431 /* We now have a new usage insn for original regno. */
5432 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5433 if (lra_dump_file
!= NULL
)
5434 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5435 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5436 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5437 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5438 bitmap_set_bit (&check_only_regs
, original_regno
);
5439 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5441 lra_process_new_insns (insn
, NULL
, new_insns
,
5442 "Add original<-inheritance");
5444 lra_process_new_insns (insn
, new_insns
, NULL
,
5445 "Add inheritance<-original");
5446 while (next_usage_insns
!= NULL_RTX
)
5448 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5450 usage_insn
= next_usage_insns
;
5451 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5452 next_usage_insns
= NULL
;
5456 usage_insn
= XEXP (next_usage_insns
, 0);
5457 lra_assert (DEBUG_INSN_P (usage_insn
));
5458 next_usage_insns
= XEXP (next_usage_insns
, 1);
5460 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5461 DEBUG_INSN_P (usage_insn
));
5462 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5463 if (lra_dump_file
!= NULL
)
5465 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5466 fprintf (lra_dump_file
,
5467 " Inheritance reuse change %d->%d (bb%d):\n",
5468 original_regno
, REGNO (new_reg
),
5469 bb
? bb
->index
: -1);
5470 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5473 if (lra_dump_file
!= NULL
)
5474 fprintf (lra_dump_file
,
5475 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5479 /* Return true if we need a caller save/restore for pseudo REGNO which
5480 was assigned to a hard register. */
5482 need_for_call_save_p (int regno
)
5484 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5485 if (usage_insns
[regno
].calls_num
< calls_num
)
5487 unsigned int abis
= 0;
5488 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
5489 if (last_call_for_abi
[i
] > usage_insns
[regno
].calls_num
)
5492 if (call_clobbered_in_region_p (abis
, full_and_partial_call_clobbers
,
5493 PSEUDO_REGNO_MODE (regno
),
5494 reg_renumber
[regno
]))
5500 /* Global registers occurring in the current EBB. */
5501 static bitmap_head ebb_global_regs
;
5503 /* Return true if we need a split for hard register REGNO or pseudo
5504 REGNO which was assigned to a hard register.
5505 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5506 used for reloads since the EBB end. It is an approximation of the
5507 used hard registers in the split range. The exact value would
5508 require expensive calculations. If we were aggressive with
5509 splitting because of the approximation, the split pseudo will save
5510 the same hard register assignment and will be removed in the undo
5511 pass. We still need the approximation because too aggressive
5512 splitting would result in too inaccurate cost calculation in the
5513 assignment pass because of too many generated moves which will be
5514 probably removed in the undo pass. */
5516 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5518 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5520 lra_assert (hard_regno
>= 0);
5521 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5522 /* Don't split eliminable hard registers, otherwise we can
5523 split hard registers like hard frame pointer, which
5524 lives on BB start/end according to DF-infrastructure,
5525 when there is a pseudo assigned to the register and
5526 living in the same BB. */
5527 && (regno
>= FIRST_PSEUDO_REGISTER
5528 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5529 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5530 /* Don't split call clobbered hard regs living through
5531 calls, otherwise we might have a check problem in the
5532 assign sub-pass as in the most cases (exception is a
5533 situation when check_and_force_assignment_correctness_p value is
5534 true) the assign pass assumes that all pseudos living
5535 through calls are assigned to call saved hard regs. */
5536 && (regno
>= FIRST_PSEUDO_REGISTER
5537 || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers
, regno
))
5538 /* We need at least 2 reloads to make pseudo splitting
5539 profitable. We should provide hard regno splitting in
5540 any case to solve 1st insn scheduling problem when
5541 moving hard register definition up might result in
5542 impossibility to find hard register for reload pseudo of
5543 small register class. */
5544 && (usage_insns
[regno
].reloads_num
5545 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5546 && (regno
< FIRST_PSEUDO_REGISTER
5547 /* For short living pseudos, spilling + inheritance can
5548 be considered a substitution for splitting.
5549 Therefore we do not splitting for local pseudos. It
5550 decreases also aggressiveness of splitting. The
5551 minimal number of references is chosen taking into
5552 account that for 2 references splitting has no sense
5553 as we can just spill the pseudo. */
5554 || (regno
>= FIRST_PSEUDO_REGISTER
5555 && lra_reg_info
[regno
].nrefs
> 3
5556 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5557 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5560 /* Return class for the split pseudo created from original pseudo with
5561 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5562 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5563 results in no secondary memory movements. */
5564 static enum reg_class
5565 choose_split_class (enum reg_class allocno_class
,
5566 int hard_regno ATTRIBUTE_UNUSED
,
5567 machine_mode mode ATTRIBUTE_UNUSED
)
5570 enum reg_class cl
, best_cl
= NO_REGS
;
5571 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5572 = REGNO_REG_CLASS (hard_regno
);
5574 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
5575 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5576 return allocno_class
;
5578 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5580 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
5581 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
5582 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5583 && (best_cl
== NO_REGS
5584 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5589 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5590 It only makes sense to call this function if NEW_REGNO is always
5591 equal to ORIGINAL_REGNO. */
5594 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
)
5596 if (!ira_reg_equiv
[original_regno
].defined_p
)
5599 ira_expand_reg_equiv ();
5600 ira_reg_equiv
[new_regno
].defined_p
= true;
5601 if (ira_reg_equiv
[original_regno
].memory
)
5602 ira_reg_equiv
[new_regno
].memory
5603 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5604 if (ira_reg_equiv
[original_regno
].constant
)
5605 ira_reg_equiv
[new_regno
].constant
5606 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5607 if (ira_reg_equiv
[original_regno
].invariant
)
5608 ira_reg_equiv
[new_regno
].invariant
5609 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
5612 /* Do split transformations for insn INSN, which defines or uses
5613 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5614 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5615 "insns" field of usage_insns. If TO is not NULL, we don't use
5616 usage_insns, we put restore insns after TO insn. It is a case when
5617 we call it from lra_split_hard_reg_for, outside the inheritance
5620 The transformations look like:
5623 ... s <- p (new insn -- save)
5625 ... p <- s (new insn -- restore)
5626 <- ... p ... <- ... p ...
5628 <- ... p ... <- ... p ...
5629 ... s <- p (new insn -- save)
5631 ... p <- s (new insn -- restore)
5632 <- ... p ... <- ... p ...
5634 where p is an original pseudo got a hard register or a hard
5635 register and s is a new split pseudo. The save is put before INSN
5636 if BEFORE_P is true. Return true if we succeed in such
5639 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5640 rtx next_usage_insns
, rtx_insn
*to
)
5642 enum reg_class rclass
;
5644 int hard_regno
, nregs
;
5645 rtx new_reg
, usage_insn
;
5646 rtx_insn
*restore
, *save
;
5651 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5653 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5654 hard_regno
= original_regno
;
5655 call_save_p
= false;
5657 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5658 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5659 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5660 as part of a multi-word register. In that case, or if the biggest
5661 mode was larger than a register, just use the reg_rtx. Otherwise,
5662 limit the size to that of the biggest access in the function. */
5663 if (mode
== VOIDmode
5664 || paradoxical_subreg_p (mode
, reg_rtx_mode
))
5666 original_reg
= regno_reg_rtx
[hard_regno
];
5667 mode
= reg_rtx_mode
;
5670 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5674 mode
= PSEUDO_REGNO_MODE (original_regno
);
5675 hard_regno
= reg_renumber
[original_regno
];
5676 nregs
= hard_regno_nregs (hard_regno
, mode
);
5677 rclass
= lra_get_allocno_class (original_regno
);
5678 original_reg
= regno_reg_rtx
[original_regno
];
5679 call_save_p
= need_for_call_save_p (original_regno
);
5681 lra_assert (hard_regno
>= 0);
5682 if (lra_dump_file
!= NULL
)
5683 fprintf (lra_dump_file
,
5684 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5688 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5689 hard_regno_nregs (hard_regno
, mode
),
5691 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5695 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5696 if (rclass
== NO_REGS
)
5698 if (lra_dump_file
!= NULL
)
5700 fprintf (lra_dump_file
,
5701 " Rejecting split of %d(%s): "
5702 "no good reg class for %d(%s)\n",
5704 reg_class_names
[lra_get_allocno_class (original_regno
)],
5706 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5709 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5713 /* Split_if_necessary can split hard registers used as part of a
5714 multi-register mode but splits each register individually. The
5715 mode used for each independent register may not be supported
5716 so reject the split. Splitting the wider mode should theoretically
5717 be possible but is not implemented. */
5718 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
5720 if (lra_dump_file
!= NULL
)
5722 fprintf (lra_dump_file
,
5723 " Rejecting split of %d(%s): unsuitable mode %s\n",
5725 reg_class_names
[lra_get_allocno_class (original_regno
)],
5726 GET_MODE_NAME (mode
));
5729 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5733 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5734 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5736 int new_regno
= REGNO (new_reg
);
5737 save
= emit_spill_move (true, new_reg
, original_reg
);
5738 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5740 if (lra_dump_file
!= NULL
)
5744 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5745 original_regno
, new_regno
);
5746 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5747 fprintf (lra_dump_file
,
5748 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5752 restore
= emit_spill_move (false, new_reg
, original_reg
);
5753 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5755 if (lra_dump_file
!= NULL
)
5757 fprintf (lra_dump_file
,
5758 " Rejecting split %d->%d "
5759 "resulting in > 2 restore insns:\n",
5760 original_regno
, new_regno
);
5761 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5762 fprintf (lra_dump_file
,
5763 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5767 /* Transfer equivalence information to the spill register, so that
5768 if we fail to allocate the spill register, we have the option of
5769 rematerializing the original value instead of spilling to the stack. */
5770 if (!HARD_REGISTER_NUM_P (original_regno
)
5771 && mode
== PSEUDO_REGNO_MODE (original_regno
))
5772 lra_copy_reg_equiv (new_regno
, original_regno
);
5773 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
5774 bitmap_set_bit (&lra_split_regs
, new_regno
);
5777 lra_assert (next_usage_insns
== NULL
);
5783 /* We need check_only_regs only inside the inheritance pass. */
5784 bitmap_set_bit (&check_only_regs
, new_regno
);
5785 bitmap_set_bit (&check_only_regs
, original_regno
);
5786 after_p
= usage_insns
[original_regno
].after_p
;
5789 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5791 usage_insn
= next_usage_insns
;
5794 usage_insn
= XEXP (next_usage_insns
, 0);
5795 lra_assert (DEBUG_INSN_P (usage_insn
));
5796 next_usage_insns
= XEXP (next_usage_insns
, 1);
5797 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5799 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5800 if (lra_dump_file
!= NULL
)
5802 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5803 original_regno
, new_regno
);
5804 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5808 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5809 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5810 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5811 after_p
? NULL
: restore
,
5812 after_p
? restore
: NULL
,
5814 ? "Add reg<-save" : "Add reg<-split");
5815 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5816 before_p
? NULL
: save
,
5818 ? "Add save<-reg" : "Add split<-reg");
5820 /* If we are trying to split multi-register. We should check
5821 conflicts on the next assignment sub-pass. IRA can allocate on
5822 sub-register levels, LRA do this on pseudos level right now and
5823 this discrepancy may create allocation conflicts after
5825 check_and_force_assignment_correctness_p
= true;
5826 if (lra_dump_file
!= NULL
)
5827 fprintf (lra_dump_file
,
5828 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5832 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
5833 in the range [FROM, TO]. Return true if did a split. Otherwise,
5836 spill_hard_reg_in_range (int regno
, enum reg_class rclass
, rtx_insn
*from
, rtx_insn
*to
)
5843 HARD_REG_SET ignore
;
5845 lra_assert (from
!= NULL
&& to
!= NULL
);
5846 CLEAR_HARD_REG_SET (ignore
);
5847 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
5849 lra_insn_recog_data_t id
= lra_insn_recog_data
[uid
];
5850 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
5851 struct lra_insn_reg
*reg
;
5853 for (reg
= id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5854 if (reg
->regno
< FIRST_PSEUDO_REGISTER
)
5855 SET_HARD_REG_BIT (ignore
, reg
->regno
);
5856 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5857 SET_HARD_REG_BIT (ignore
, reg
->regno
);
5859 rclass_size
= ira_class_hard_regs_num
[rclass
];
5860 for (i
= 0; i
< rclass_size
; i
++)
5862 hard_regno
= ira_class_hard_regs
[rclass
][i
];
5863 if (! TEST_HARD_REG_BIT (lra_reg_info
[regno
].conflict_hard_regs
, hard_regno
)
5864 || TEST_HARD_REG_BIT (ignore
, hard_regno
))
5866 for (insn
= from
; insn
!= NEXT_INSN (to
); insn
= NEXT_INSN (insn
))
5868 struct lra_static_insn_data
*static_id
;
5869 struct lra_insn_reg
*reg
;
5873 if (bitmap_bit_p (&lra_reg_info
[hard_regno
].insn_bitmap
,
5876 static_id
= lra_get_insn_recog_data (insn
)->insn_static_data
;
5877 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5878 if (reg
->regno
== hard_regno
)
5883 if (insn
!= NEXT_INSN (to
))
5885 if (split_reg (TRUE
, hard_regno
, from
, NULL
, to
))
5891 /* Recognize that we need a split transformation for insn INSN, which
5892 defines or uses REGNO in its insn biggest MODE (we use it only if
5893 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5894 hard registers which might be used for reloads since the EBB end.
5895 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5896 uid before starting INSN processing. Return true if we succeed in
5897 such transformation. */
5899 split_if_necessary (int regno
, machine_mode mode
,
5900 HARD_REG_SET potential_reload_hard_regs
,
5901 bool before_p
, rtx_insn
*insn
, int max_uid
)
5905 rtx next_usage_insns
;
5907 if (regno
< FIRST_PSEUDO_REGISTER
)
5908 nregs
= hard_regno_nregs (regno
, mode
);
5909 for (i
= 0; i
< nregs
; i
++)
5910 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5911 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5912 /* To avoid processing the register twice or more. */
5913 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5914 && INSN_UID (next_usage_insns
) < max_uid
)
5915 || (GET_CODE (next_usage_insns
) == INSN_LIST
5916 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5917 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5918 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
, NULL
))
5923 /* Return TRUE if rtx X is considered as an invariant for
5926 invariant_p (const_rtx x
)
5933 if (side_effects_p (x
))
5936 code
= GET_CODE (x
);
5937 mode
= GET_MODE (x
);
5941 code
= GET_CODE (x
);
5942 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
5950 int i
, nregs
, regno
= REGNO (x
);
5952 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5953 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5954 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5956 nregs
= hard_regno_nregs (regno
, mode
);
5957 for (i
= 0; i
< nregs
; i
++)
5958 if (! fixed_regs
[regno
+ i
]
5959 /* A hard register may be clobbered in the current insn
5960 but we can ignore this case because if the hard
5961 register is used it should be set somewhere after the
5963 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5966 fmt
= GET_RTX_FORMAT (code
);
5967 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5971 if (! invariant_p (XEXP (x
, i
)))
5974 else if (fmt
[i
] == 'E')
5976 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5977 if (! invariant_p (XVECEXP (x
, i
, j
)))
5984 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5985 inheritance transformation (using dest_reg instead invariant in a
5986 subsequent insn). */
5988 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5990 invariant_ptr_t invariant_ptr
;
5991 rtx_insn
*insn
, *new_insns
;
5992 rtx insn_set
, insn_reg
, new_reg
;
5994 bool succ_p
= false;
5995 int dst_regno
= REGNO (dst_reg
);
5996 machine_mode dst_mode
= GET_MODE (dst_reg
);
5997 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5999 invariant_ptr
= insert_invariant (invariant_rtx
);
6000 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
6002 /* We have a subsequent insn using the invariant. */
6003 insn_set
= single_set (insn
);
6004 lra_assert (insn_set
!= NULL
);
6005 insn_reg
= SET_DEST (insn_set
);
6006 lra_assert (REG_P (insn_reg
));
6007 insn_regno
= REGNO (insn_reg
);
6008 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
6010 if (dst_mode
== GET_MODE (insn_reg
)
6011 /* We should consider only result move reg insns which are
6013 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
6014 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
6016 if (lra_dump_file
!= NULL
)
6017 fprintf (lra_dump_file
,
6018 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
6019 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
6020 cl
, "invariant inheritance");
6021 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
6022 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
6023 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
6025 lra_emit_move (new_reg
, dst_reg
);
6026 new_insns
= get_insns ();
6028 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6029 "Add invariant inheritance<-original");
6031 lra_emit_move (SET_DEST (insn_set
), new_reg
);
6032 new_insns
= get_insns ();
6034 lra_process_new_insns (insn
, NULL
, new_insns
,
6035 "Changing reload<-inheritance");
6036 lra_set_insn_deleted (insn
);
6038 if (lra_dump_file
!= NULL
)
6040 fprintf (lra_dump_file
,
6041 " Invariant inheritance reuse change %d (bb%d):\n",
6042 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
6043 dump_insn_slim (lra_dump_file
, insn
);
6044 fprintf (lra_dump_file
,
6045 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
6049 invariant_ptr
->insn
= curr_insn
;
6053 /* Check only registers living at the current program point in the
6055 static bitmap_head live_regs
;
6057 /* Update live info in EBB given by its HEAD and TAIL insns after
6058 inheritance/split transformation. The function removes dead moves
6061 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
6066 rtx_insn
*prev_insn
;
6069 basic_block last_bb
, prev_bb
, curr_bb
;
6071 struct lra_insn_reg
*reg
;
6075 last_bb
= BLOCK_FOR_INSN (tail
);
6077 for (curr_insn
= tail
;
6078 curr_insn
!= PREV_INSN (head
);
6079 curr_insn
= prev_insn
)
6081 prev_insn
= PREV_INSN (curr_insn
);
6082 /* We need to process empty blocks too. They contain
6083 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
6084 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
6086 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6087 if (curr_bb
!= prev_bb
)
6089 if (prev_bb
!= NULL
)
6091 /* Update df_get_live_in (prev_bb): */
6092 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6093 if (bitmap_bit_p (&live_regs
, j
))
6094 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
6096 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
6098 if (curr_bb
!= last_bb
)
6100 /* Update df_get_live_out (curr_bb): */
6101 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6103 live_p
= bitmap_bit_p (&live_regs
, j
);
6105 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
6106 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
6112 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
6114 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
6118 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
6120 if (! NONDEBUG_INSN_P (curr_insn
))
6122 curr_id
= lra_get_insn_recog_data (curr_insn
);
6123 curr_static_id
= curr_id
->insn_static_data
;
6125 if ((set
= single_set (curr_insn
)) != NULL_RTX
6126 && REG_P (SET_DEST (set
))
6127 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
6128 && SET_DEST (set
) != pic_offset_table_rtx
6129 && bitmap_bit_p (&check_only_regs
, regno
)
6130 && ! bitmap_bit_p (&live_regs
, regno
))
6132 /* See which defined values die here. */
6133 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6134 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6135 bitmap_clear_bit (&live_regs
, reg
->regno
);
6136 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6137 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6138 bitmap_clear_bit (&live_regs
, reg
->regno
);
6139 if (curr_id
->arg_hard_regs
!= NULL
)
6140 /* Make clobbered argument hard registers die. */
6141 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6142 if (regno
>= FIRST_PSEUDO_REGISTER
)
6143 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
6144 /* Mark each used value as live. */
6145 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6146 if (reg
->type
!= OP_OUT
6147 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6148 bitmap_set_bit (&live_regs
, reg
->regno
);
6149 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6150 if (reg
->type
!= OP_OUT
6151 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6152 bitmap_set_bit (&live_regs
, reg
->regno
);
6153 if (curr_id
->arg_hard_regs
!= NULL
)
6154 /* Make used argument hard registers live. */
6155 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6156 if (regno
< FIRST_PSEUDO_REGISTER
6157 && bitmap_bit_p (&check_only_regs
, regno
))
6158 bitmap_set_bit (&live_regs
, regno
);
6159 /* It is quite important to remove dead move insns because it
6160 means removing dead store. We don't need to process them for
6164 if (lra_dump_file
!= NULL
)
6166 fprintf (lra_dump_file
, " Removing dead insn:\n ");
6167 dump_insn_slim (lra_dump_file
, curr_insn
);
6169 lra_set_insn_deleted (curr_insn
);
6174 /* The structure describes info to do an inheritance for the current
6175 insn. We need to collect such info first before doing the
6176 transformations because the transformations change the insn
6177 internal representation. */
6180 /* Original regno. */
6182 /* Subsequent insns which can inherit original reg value. */
6186 /* Array containing all info for doing inheritance from the current
6188 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
6190 /* Number elements in the previous array. */
6191 static int to_inherit_num
;
6193 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6194 structure to_inherit. */
6196 add_to_inherit (int regno
, rtx insns
)
6200 for (i
= 0; i
< to_inherit_num
; i
++)
6201 if (to_inherit
[i
].regno
== regno
)
6203 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
6204 to_inherit
[to_inherit_num
].regno
= regno
;
6205 to_inherit
[to_inherit_num
++].insns
= insns
;
6208 /* Return the last non-debug insn in basic block BB, or the block begin
6211 get_last_insertion_point (basic_block bb
)
6215 FOR_BB_INSNS_REVERSE (bb
, insn
)
6216 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
6221 /* Set up RES by registers living on edges FROM except the edge (FROM,
6222 TO) or by registers set up in a jump insn in BB FROM. */
6224 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
6227 struct lra_insn_reg
*reg
;
6231 lra_assert (to
!= NULL
);
6233 FOR_EACH_EDGE (e
, ei
, from
->succs
)
6235 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
6236 last
= get_last_insertion_point (from
);
6237 if (! JUMP_P (last
))
6239 curr_id
= lra_get_insn_recog_data (last
);
6240 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6241 if (reg
->type
!= OP_IN
)
6242 bitmap_set_bit (res
, reg
->regno
);
6245 /* Used as a temporary results of some bitmap calculations. */
6246 static bitmap_head temp_bitmap
;
6248 /* We split for reloads of small class of hard regs. The following
6249 defines how many hard regs the class should have to be qualified as
6250 small. The code is mostly oriented to x86/x86-64 architecture
6251 where some insns need to use only specific register or pair of
6252 registers and these register can live in RTL explicitly, e.g. for
6253 parameter passing. */
6254 static const int max_small_class_regs_num
= 2;
6256 /* Do inheritance/split transformations in EBB starting with HEAD and
6257 finishing on TAIL. We process EBB insns in the reverse order.
6258 Return true if we did any inheritance/split transformation in the
6261 We should avoid excessive splitting which results in worse code
6262 because of inaccurate cost calculations for spilling new split
6263 pseudos in such case. To achieve this we do splitting only if
6264 register pressure is high in given basic block and there are reload
6265 pseudos requiring hard registers. We could do more register
6266 pressure calculations at any given program point to avoid necessary
6267 splitting even more but it is to expensive and the current approach
6268 works well enough. */
6270 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6272 int i
, src_regno
, dst_regno
, nregs
;
6273 bool change_p
, succ_p
, update_reloads_num_p
;
6274 rtx_insn
*prev_insn
, *last_insn
;
6275 rtx next_usage_insns
, curr_set
;
6277 struct lra_insn_reg
*reg
;
6278 basic_block last_processed_bb
, curr_bb
= NULL
;
6279 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6283 bool head_p
, after_p
;
6286 curr_usage_insns_check
++;
6287 clear_invariants ();
6288 reloads_num
= calls_num
= 0;
6289 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
6290 last_call_for_abi
[i
] = 0;
6291 CLEAR_HARD_REG_SET (full_and_partial_call_clobbers
);
6292 bitmap_clear (&check_only_regs
);
6293 bitmap_clear (&invalid_invariant_regs
);
6294 last_processed_bb
= NULL
;
6295 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6296 live_hard_regs
= eliminable_regset
| lra_no_alloc_regs
;
6297 /* We don't process new insns generated in the loop. */
6298 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6300 prev_insn
= PREV_INSN (curr_insn
);
6301 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6302 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6303 if (last_processed_bb
!= curr_bb
)
6305 /* We are at the end of BB. Add qualified living
6306 pseudos for potential splitting. */
6307 to_process
= df_get_live_out (curr_bb
);
6308 if (last_processed_bb
!= NULL
)
6310 /* We are somewhere in the middle of EBB. */
6311 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6313 to_process
= &temp_bitmap
;
6315 last_processed_bb
= curr_bb
;
6316 last_insn
= get_last_insertion_point (curr_bb
);
6317 after_p
= (! JUMP_P (last_insn
)
6318 && (! CALL_P (last_insn
)
6319 || (find_reg_note (last_insn
,
6320 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6321 && ! SIBLING_CALL_P (last_insn
))));
6322 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6323 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6325 if ((int) j
>= lra_constraint_new_regno_start
)
6327 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6329 if (j
< FIRST_PSEUDO_REGISTER
)
6330 SET_HARD_REG_BIT (live_hard_regs
, j
);
6332 add_to_hard_reg_set (&live_hard_regs
,
6333 PSEUDO_REGNO_MODE (j
),
6335 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6339 src_regno
= dst_regno
= -1;
6340 curr_set
= single_set (curr_insn
);
6341 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6342 dst_regno
= REGNO (SET_DEST (curr_set
));
6343 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6344 src_regno
= REGNO (SET_SRC (curr_set
));
6345 update_reloads_num_p
= true;
6346 if (src_regno
< lra_constraint_new_regno_start
6347 && src_regno
>= FIRST_PSEUDO_REGISTER
6348 && reg_renumber
[src_regno
] < 0
6349 && dst_regno
>= lra_constraint_new_regno_start
6350 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6352 /* 'reload_pseudo <- original_pseudo'. */
6353 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6355 update_reloads_num_p
= false;
6357 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6358 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6359 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6360 curr_insn
, next_usage_insns
);
6364 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6365 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6366 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6368 else if (src_regno
< 0
6369 && dst_regno
>= lra_constraint_new_regno_start
6370 && invariant_p (SET_SRC (curr_set
))
6371 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6372 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6373 && ! bitmap_bit_p (&invalid_invariant_regs
,
6374 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6376 /* 'reload_pseudo <- invariant'. */
6377 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6379 update_reloads_num_p
= false;
6380 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6382 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6383 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6385 else if (src_regno
>= lra_constraint_new_regno_start
6386 && dst_regno
< lra_constraint_new_regno_start
6387 && dst_regno
>= FIRST_PSEUDO_REGISTER
6388 && reg_renumber
[dst_regno
] < 0
6389 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6390 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6391 && (next_usage_insns
6392 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6394 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6396 update_reloads_num_p
= false;
6397 /* 'original_pseudo <- reload_pseudo'. */
6398 if (! JUMP_P (curr_insn
)
6399 && inherit_reload_reg (true, dst_regno
, cl
,
6400 curr_insn
, next_usage_insns
))
6403 usage_insns
[dst_regno
].check
= 0;
6404 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6405 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6407 else if (INSN_P (curr_insn
))
6410 int max_uid
= get_max_uid ();
6412 curr_id
= lra_get_insn_recog_data (curr_insn
);
6413 curr_static_id
= curr_id
->insn_static_data
;
6415 /* Process insn definitions. */
6416 for (iter
= 0; iter
< 2; iter
++)
6417 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6420 if (reg
->type
!= OP_IN
6421 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6423 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6424 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6425 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6426 && (next_usage_insns
6427 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6429 struct lra_insn_reg
*r
;
6431 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6432 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6434 /* Don't do inheritance if the pseudo is also
6435 used in the insn. */
6437 /* We cannot do inheritance right now
6438 because the current insn reg info (chain
6439 regs) can change after that. */
6440 add_to_inherit (dst_regno
, next_usage_insns
);
6442 /* We cannot process one reg twice here because of
6443 usage_insns invalidation. */
6444 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6445 || reg_renumber
[dst_regno
] >= 0)
6446 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6450 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6451 potential_reload_hard_regs
,
6452 false, curr_insn
, max_uid
))
6454 CLEAR_HARD_REG_SET (s
);
6455 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6456 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6458 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6459 reg_renumber
[dst_regno
]);
6460 live_hard_regs
&= ~s
;
6461 potential_reload_hard_regs
&= ~s
;
6463 /* We should invalidate potential inheritance or
6464 splitting for the current insn usages to the next
6465 usage insns (see code below) as the output pseudo
6467 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6468 && reg_renumber
[dst_regno
] < 0)
6469 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6470 && (dst_regno
< FIRST_PSEUDO_REGISTER
6471 || reg_renumber
[dst_regno
] >= 0)))
6473 /* Invalidate and mark definitions. */
6474 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6475 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6478 nregs
= hard_regno_nregs (dst_regno
,
6480 for (i
= 0; i
< nregs
; i
++)
6481 usage_insns
[dst_regno
+ i
].check
6482 = -(int) INSN_UID (curr_insn
);
6486 /* Process clobbered call regs. */
6487 if (curr_id
->arg_hard_regs
!= NULL
)
6488 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6489 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6490 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6491 = -(int) INSN_UID (curr_insn
);
6492 if (! JUMP_P (curr_insn
))
6493 for (i
= 0; i
< to_inherit_num
; i
++)
6494 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6495 ALL_REGS
, curr_insn
,
6496 to_inherit
[i
].insns
))
6498 if (CALL_P (curr_insn
))
6500 rtx cheap
, pat
, dest
;
6502 int regno
, hard_regno
;
6505 function_abi callee_abi
= insn_callee_abi (curr_insn
);
6506 last_call_for_abi
[callee_abi
.id ()] = calls_num
;
6507 full_and_partial_call_clobbers
6508 |= callee_abi
.full_and_partial_reg_clobbers ();
6509 if ((cheap
= find_reg_note (curr_insn
,
6510 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6511 && ((cheap
= XEXP (cheap
, 0)), true)
6512 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6513 && (hard_regno
= reg_renumber
[regno
]) >= 0
6514 && usage_insns
[regno
].check
== curr_usage_insns_check
6515 /* If there are pending saves/restores, the
6516 optimization is not worth. */
6517 && usage_insns
[regno
].calls_num
== calls_num
- 1
6518 && callee_abi
.clobbers_reg_p (GET_MODE (cheap
), hard_regno
))
6520 /* Restore the pseudo from the call result as
6521 REG_RETURNED note says that the pseudo value is
6522 in the call result and the pseudo is an argument
6524 pat
= PATTERN (curr_insn
);
6525 if (GET_CODE (pat
) == PARALLEL
)
6526 pat
= XVECEXP (pat
, 0, 0);
6527 dest
= SET_DEST (pat
);
6528 /* For multiple return values dest is PARALLEL.
6529 Currently we handle only single return value case. */
6533 emit_move_insn (cheap
, copy_rtx (dest
));
6534 restore
= get_insns ();
6536 lra_process_new_insns (curr_insn
, NULL
, restore
,
6537 "Inserting call parameter restore");
6538 /* We don't need to save/restore of the pseudo from
6540 usage_insns
[regno
].calls_num
= calls_num
;
6541 remove_from_hard_reg_set
6542 (&full_and_partial_call_clobbers
,
6543 GET_MODE (cheap
), hard_regno
);
6544 bitmap_set_bit (&check_only_regs
, regno
);
6549 /* Process insn usages. */
6550 for (iter
= 0; iter
< 2; iter
++)
6551 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6554 if ((reg
->type
!= OP_OUT
6555 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6556 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6558 if (src_regno
>= FIRST_PSEUDO_REGISTER
6559 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6561 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6562 && (next_usage_insns
6563 = usage_insns
[src_regno
].insns
) != NULL_RTX
6564 && NONDEBUG_INSN_P (curr_insn
))
6565 add_to_inherit (src_regno
, next_usage_insns
);
6566 else if (usage_insns
[src_regno
].check
6567 != -(int) INSN_UID (curr_insn
))
6568 /* Add usages but only if the reg is not set up
6569 in the same insn. */
6570 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6572 else if (src_regno
< FIRST_PSEUDO_REGISTER
6573 || reg_renumber
[src_regno
] >= 0)
6576 rtx_insn
*use_insn
= curr_insn
;
6578 before_p
= (JUMP_P (curr_insn
)
6579 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6580 if (NONDEBUG_INSN_P (curr_insn
)
6581 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6582 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6583 potential_reload_hard_regs
,
6584 before_p
, curr_insn
, max_uid
))
6587 check_and_force_assignment_correctness_p
= true;
6590 usage_insns
[src_regno
].check
= 0;
6592 use_insn
= PREV_INSN (curr_insn
);
6594 if (NONDEBUG_INSN_P (curr_insn
))
6596 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6597 add_to_hard_reg_set (&live_hard_regs
,
6598 reg
->biggest_mode
, src_regno
);
6600 add_to_hard_reg_set (&live_hard_regs
,
6601 PSEUDO_REGNO_MODE (src_regno
),
6602 reg_renumber
[src_regno
]);
6604 if (src_regno
>= FIRST_PSEUDO_REGISTER
)
6605 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6608 for (i
= 0; i
< hard_regno_nregs (src_regno
, reg
->biggest_mode
); i
++)
6609 add_next_usage_insn (src_regno
+ i
, use_insn
, reloads_num
);
6613 /* Process used call regs. */
6614 if (curr_id
->arg_hard_regs
!= NULL
)
6615 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6616 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6618 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6619 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6621 for (i
= 0; i
< to_inherit_num
; i
++)
6623 src_regno
= to_inherit
[i
].regno
;
6624 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6625 curr_insn
, to_inherit
[i
].insns
))
6628 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6631 if (update_reloads_num_p
6632 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6635 if ((REG_P (SET_DEST (curr_set
))
6636 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6637 && reg_renumber
[regno
] < 0
6638 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6639 || (REG_P (SET_SRC (curr_set
))
6640 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6641 && reg_renumber
[regno
] < 0
6642 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6644 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6646 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6647 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6650 if (NONDEBUG_INSN_P (curr_insn
))
6654 /* Invalidate invariants with changed regs. */
6655 curr_id
= lra_get_insn_recog_data (curr_insn
);
6656 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6657 if (reg
->type
!= OP_IN
)
6659 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6660 bitmap_set_bit (&invalid_invariant_regs
,
6661 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6663 curr_static_id
= curr_id
->insn_static_data
;
6664 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6665 if (reg
->type
!= OP_IN
)
6666 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6667 if (curr_id
->arg_hard_regs
!= NULL
)
6668 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6669 if (regno
>= FIRST_PSEUDO_REGISTER
)
6670 bitmap_set_bit (&invalid_invariant_regs
,
6671 regno
- FIRST_PSEUDO_REGISTER
);
6673 /* We reached the start of the current basic block. */
6674 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6675 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6677 /* We reached the beginning of the current block -- do
6678 rest of spliting in the current BB. */
6679 to_process
= df_get_live_in (curr_bb
);
6680 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6682 /* We are somewhere in the middle of EBB. */
6683 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6684 curr_bb
, &temp_bitmap
);
6685 to_process
= &temp_bitmap
;
6688 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6690 if ((int) j
>= lra_constraint_new_regno_start
)
6692 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6693 && usage_insns
[j
].check
== curr_usage_insns_check
6694 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6696 if (need_for_split_p (potential_reload_hard_regs
, j
))
6698 if (lra_dump_file
!= NULL
&& head_p
)
6700 fprintf (lra_dump_file
,
6701 " ----------------------------------\n");
6704 if (split_reg (false, j
, bb_note (curr_bb
),
6705 next_usage_insns
, NULL
))
6708 usage_insns
[j
].check
= 0;
6716 /* This value affects EBB forming. If probability of edge from EBB to
6717 a BB is not greater than the following value, we don't add the BB
6719 #define EBB_PROBABILITY_CUTOFF \
6720 ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100)
6722 /* Current number of inheritance/split iteration. */
6723 int lra_inheritance_iter
;
6725 /* Entry function for inheritance/split pass. */
6727 lra_inheritance (void)
6730 basic_block bb
, start_bb
;
6733 lra_inheritance_iter
++;
6734 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6736 timevar_push (TV_LRA_INHERITANCE
);
6737 if (lra_dump_file
!= NULL
)
6738 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6739 lra_inheritance_iter
);
6740 curr_usage_insns_check
= 0;
6741 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6742 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6743 usage_insns
[i
].check
= 0;
6744 bitmap_initialize (&check_only_regs
, ®_obstack
);
6745 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6746 bitmap_initialize (&live_regs
, ®_obstack
);
6747 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6748 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6749 FOR_EACH_BB_FN (bb
, cfun
)
6752 if (lra_dump_file
!= NULL
)
6753 fprintf (lra_dump_file
, "EBB");
6754 /* Form a EBB starting with BB. */
6755 bitmap_clear (&ebb_global_regs
);
6756 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6759 if (lra_dump_file
!= NULL
)
6760 fprintf (lra_dump_file
, " %d", bb
->index
);
6761 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6762 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6764 e
= find_fallthru_edge (bb
->succs
);
6767 if (e
->probability
.initialized_p ()
6768 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
6772 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6773 if (lra_dump_file
!= NULL
)
6774 fprintf (lra_dump_file
, "\n");
6775 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6776 /* Remember that the EBB head and tail can change in
6778 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6780 bitmap_release (&ebb_global_regs
);
6781 bitmap_release (&temp_bitmap
);
6782 bitmap_release (&live_regs
);
6783 bitmap_release (&invalid_invariant_regs
);
6784 bitmap_release (&check_only_regs
);
6787 timevar_pop (TV_LRA_INHERITANCE
);
6792 /* This page contains code to undo failed inheritance/split
6795 /* Current number of iteration undoing inheritance/split. */
6796 int lra_undo_inheritance_iter
;
6798 /* Fix BB live info LIVE after removing pseudos created on pass doing
6799 inheritance/split which are REMOVED_PSEUDOS. */
6801 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6806 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6807 if (bitmap_clear_bit (live
, regno
)
6808 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6809 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6812 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6817 if (GET_CODE (reg
) == SUBREG
)
6818 reg
= SUBREG_REG (reg
);
6824 /* Delete a move INSN with destination reg DREGNO and a previous
6825 clobber insn with the same regno. The inheritance/split code can
6826 generate moves with preceding clobber and when we delete such moves
6827 we should delete the clobber insn too to keep the correct life
6830 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6832 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6834 lra_set_insn_deleted (insn
);
6835 lra_assert (dregno
>= 0);
6836 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6837 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6838 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6839 lra_set_insn_deleted (prev_insn
);
6842 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6843 return true if we did any change. The undo transformations for
6844 inheritance looks like
6848 p <- i, i <- p, and i <- i3
6849 where p is original pseudo from which inheritance pseudo i was
6850 created, i and i3 are removed inheritance pseudos, i2 is another
6851 not removed inheritance pseudo. All split pseudos or other
6852 occurrences of removed inheritance pseudos are changed on the
6853 corresponding original pseudos.
6855 The function also schedules insns changed and created during
6856 inheritance/split pass for processing by the subsequent constraint
6859 remove_inheritance_pseudos (bitmap remove_pseudos
)
6862 int regno
, sregno
, prev_sregno
, dregno
;
6865 rtx_insn
*prev_insn
;
6866 bool change_p
, done_p
;
6868 change_p
= ! bitmap_empty_p (remove_pseudos
);
6869 /* We cannot finish the function right away if CHANGE_P is true
6870 because we need to marks insns affected by previous
6871 inheritance/split pass for processing by the subsequent
6873 FOR_EACH_BB_FN (bb
, cfun
)
6875 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6876 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6877 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6879 if (! INSN_P (curr_insn
))
6882 sregno
= dregno
= -1;
6883 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6884 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6886 dregno
= get_regno (SET_DEST (set
));
6887 sregno
= get_regno (SET_SRC (set
));
6890 if (sregno
>= 0 && dregno
>= 0)
6892 if (bitmap_bit_p (remove_pseudos
, dregno
)
6893 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6895 /* invariant inheritance pseudo <- original pseudo */
6896 if (lra_dump_file
!= NULL
)
6898 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6899 dump_insn_slim (lra_dump_file
, curr_insn
);
6900 fprintf (lra_dump_file
, "\n");
6902 delete_move_and_clobber (curr_insn
, dregno
);
6905 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6906 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6908 /* reload pseudo <- invariant inheritance pseudo */
6910 /* We cannot just change the source. It might be
6911 an insn different from the move. */
6912 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6913 rtx_insn
*new_insns
= get_insns ();
6915 lra_assert (single_set (new_insns
) != NULL
6916 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6917 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6918 "Changing reload<-invariant inheritance");
6919 delete_move_and_clobber (curr_insn
, dregno
);
6922 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6923 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6924 || (bitmap_bit_p (remove_pseudos
, dregno
)
6925 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6926 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6927 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6928 || (bitmap_bit_p (remove_pseudos
, dregno
)
6929 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6930 /* One of the following cases:
6931 original <- removed inheritance pseudo
6932 removed inherit pseudo <- another removed inherit pseudo
6933 removed inherit pseudo <- original pseudo
6935 removed_split_pseudo <- original_reg
6936 original_reg <- removed_split_pseudo */
6938 if (lra_dump_file
!= NULL
)
6940 fprintf (lra_dump_file
, " Removing %s:\n",
6941 bitmap_bit_p (&lra_split_regs
, sregno
)
6942 || bitmap_bit_p (&lra_split_regs
, dregno
)
6943 ? "split" : "inheritance");
6944 dump_insn_slim (lra_dump_file
, curr_insn
);
6946 delete_move_and_clobber (curr_insn
, dregno
);
6949 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6950 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6952 /* Search the following pattern:
6953 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6954 original_pseudo <- inherit_or_split_pseudo1
6955 where the 2nd insn is the current insn and
6956 inherit_or_split_pseudo2 is not removed. If it is found,
6957 change the current insn onto:
6958 original_pseudo <- inherit_or_split_pseudo2. */
6959 for (prev_insn
= PREV_INSN (curr_insn
);
6960 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6961 prev_insn
= PREV_INSN (prev_insn
))
6963 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6964 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6965 /* There should be no subregs in insn we are
6966 searching because only the original reg might
6967 be in subreg when we changed the mode of
6968 load/store for splitting. */
6969 && REG_P (SET_DEST (prev_set
))
6970 && REG_P (SET_SRC (prev_set
))
6971 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6972 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6973 >= FIRST_PSEUDO_REGISTER
)
6974 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6976 /* As we consider chain of inheritance or
6977 splitting described in above comment we should
6978 check that sregno and prev_sregno were
6979 inheritance/split pseudos created from the
6980 same original regno. */
6981 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6982 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6983 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6984 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6986 lra_assert (GET_MODE (SET_SRC (prev_set
))
6987 == GET_MODE (regno_reg_rtx
[sregno
]));
6988 /* Although we have a single set, the insn can
6989 contain more one sregno register occurrence
6990 as a source. Change all occurrences. */
6991 lra_substitute_pseudo_within_insn (curr_insn
, sregno
,
6994 /* As we are finishing with processing the insn
6995 here, check the destination too as it might
6996 inheritance pseudo for another pseudo. */
6997 if (bitmap_bit_p (remove_pseudos
, dregno
)
6998 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
7000 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
7002 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
7003 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
7005 SET_DEST (set
) = restore_rtx
;
7007 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7008 lra_set_used_insn_alternative_by_uid
7009 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7011 if (lra_dump_file
!= NULL
)
7013 fprintf (lra_dump_file
, " Change reload insn:\n");
7014 dump_insn_slim (lra_dump_file
, curr_insn
);
7021 struct lra_insn_reg
*reg
;
7022 bool restored_regs_p
= false;
7023 bool kept_regs_p
= false;
7025 curr_id
= lra_get_insn_recog_data (curr_insn
);
7026 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
7029 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
7030 if (restore_rtx
!= NULL_RTX
)
7032 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
7034 lra_substitute_pseudo_within_insn
7035 (curr_insn
, regno
, restore_rtx
, false);
7036 restored_regs_p
= true;
7042 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
7044 /* The instruction has changed since the previous
7045 constraints pass. */
7046 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7047 lra_set_used_insn_alternative_by_uid
7048 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7050 else if (restored_regs_p
)
7051 /* The instruction has been restored to the form that
7052 it had during the previous constraints pass. */
7053 lra_update_insn_regno_info (curr_insn
);
7054 if (restored_regs_p
&& lra_dump_file
!= NULL
)
7056 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
7057 dump_insn_slim (lra_dump_file
, curr_insn
);
7065 /* If optional reload pseudos failed to get a hard register or was not
7066 inherited, it is better to remove optional reloads. We do this
7067 transformation after undoing inheritance to figure out necessity to
7068 remove optional reloads easier. Return true if we do any
7071 undo_optional_reloads (void)
7073 bool change_p
, keep_p
;
7074 unsigned int regno
, uid
;
7075 bitmap_iterator bi
, bi2
;
7078 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
7080 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
7081 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7084 /* Keep optional reloads from previous subpasses. */
7085 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
7086 /* If the original pseudo changed its allocation, just
7087 removing the optional pseudo is dangerous as the original
7088 pseudo will have longer live range. */
7089 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
7091 else if (reg_renumber
[regno
] >= 0)
7092 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
7094 insn
= lra_insn_recog_data
[uid
]->insn
;
7095 if ((set
= single_set (insn
)) == NULL_RTX
)
7097 src
= SET_SRC (set
);
7098 dest
= SET_DEST (set
);
7099 if (! REG_P (src
) || ! REG_P (dest
))
7101 if (REGNO (dest
) == regno
7102 /* Ignore insn for optional reloads itself. */
7103 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
7104 /* Check only inheritance on last inheritance pass. */
7105 && (int) REGNO (src
) >= new_regno_start
7106 /* Check that the optional reload was inherited. */
7107 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
7115 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
7116 if (lra_dump_file
!= NULL
)
7117 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
7120 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
7121 auto_bitmap
insn_bitmap (®_obstack
);
7122 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
7124 if (lra_dump_file
!= NULL
)
7125 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
7126 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
7127 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
7129 insn
= lra_insn_recog_data
[uid
]->insn
;
7130 if ((set
= single_set (insn
)) != NULL_RTX
)
7132 src
= SET_SRC (set
);
7133 dest
= SET_DEST (set
);
7134 if (REG_P (src
) && REG_P (dest
)
7135 && ((REGNO (src
) == regno
7136 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
7138 || (REGNO (dest
) == regno
7139 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
7142 if (lra_dump_file
!= NULL
)
7144 fprintf (lra_dump_file
, " Deleting move %u\n",
7146 dump_insn_slim (lra_dump_file
, insn
);
7148 delete_move_and_clobber (insn
, REGNO (dest
));
7151 /* We should not worry about generation memory-memory
7152 moves here as if the corresponding inheritance did
7153 not work (inheritance pseudo did not get a hard reg),
7154 we remove the inheritance pseudo and the optional
7157 lra_substitute_pseudo_within_insn
7158 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
7159 lra_update_insn_regno_info (insn
);
7160 if (lra_dump_file
!= NULL
)
7162 fprintf (lra_dump_file
,
7163 " Restoring original insn:\n");
7164 dump_insn_slim (lra_dump_file
, insn
);
7168 /* Clear restore_regnos. */
7169 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7170 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7174 /* Entry function for undoing inheritance/split transformation. Return true
7175 if we did any RTL change in this pass. */
7177 lra_undo_inheritance (void)
7181 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
7186 lra_undo_inheritance_iter
++;
7187 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
7189 if (lra_dump_file
!= NULL
)
7190 fprintf (lra_dump_file
,
7191 "\n********** Undoing inheritance #%d: **********\n\n",
7192 lra_undo_inheritance_iter
);
7193 auto_bitmap
remove_pseudos (®_obstack
);
7194 n_inherit
= n_all_inherit
= 0;
7195 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7196 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
7199 if (reg_renumber
[regno
] < 0
7200 /* If the original pseudo changed its allocation, just
7201 removing inheritance is dangerous as for changing
7202 allocation we used shorter live-ranges. */
7203 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
7204 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
7205 bitmap_set_bit (remove_pseudos
, regno
);
7209 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
7210 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
7211 n_inherit
, n_all_inherit
,
7212 (double) n_inherit
/ n_all_inherit
* 100);
7213 n_split
= n_all_split
= 0;
7214 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7215 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
7217 int restore_regno
= REGNO (restore_rtx
);
7220 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
7221 ? reg_renumber
[restore_regno
] : restore_regno
);
7222 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
7223 bitmap_set_bit (remove_pseudos
, regno
);
7227 if (lra_dump_file
!= NULL
)
7228 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
7229 regno
, restore_regno
);
7232 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
7233 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
7234 n_split
, n_all_split
,
7235 (double) n_split
/ n_all_split
* 100);
7236 change_p
= remove_inheritance_pseudos (remove_pseudos
);
7237 /* Clear restore_regnos. */
7238 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7239 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7240 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7241 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7242 change_p
= undo_optional_reloads () || change_p
;