1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || (INSN_UID (curr_insn
) >= new_insn_uid_start
273 && curr_insn_set
!= NULL
274 && ((OBJECT_P (SET_SRC (curr_insn_set
))
275 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
276 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
277 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
278 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
279 /* When we don't know what class will be used finally for reload
280 pseudos, we use ALL_REGS. */
281 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
282 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
283 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
284 lra_no_alloc_regs
)));
287 common_class
= ira_reg_class_subset
[rclass
][cl
];
288 if (new_class
!= NULL
)
289 *new_class
= common_class
;
290 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
293 /* Check that there are enough allocatable regs. */
294 class_size
= ira_class_hard_regs_num
[common_class
];
295 for (i
= 0; i
< class_size
; i
++)
297 hard_regno
= ira_class_hard_regs
[common_class
][i
];
298 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
301 for (j
= 0; j
< nregs
; j
++)
302 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
303 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
313 /* Return true if REGNO satisfies a memory constraint. */
317 return get_reg_class (regno
) == NO_REGS
;
320 /* Initiate equivalences for LRA. As we keep original equivalences
321 before any elimination, we need to make copies otherwise any change
322 in insns might change the equivalences. */
324 lra_init_equiv (void)
326 ira_expand_reg_equiv ();
327 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
331 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
332 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
333 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
334 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
338 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
340 /* Update equivalence for REGNO. We need to this as the equivalence
341 might contain other pseudos which are changed by their
344 update_equiv (int regno
)
348 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
349 ira_reg_equiv
[regno
].memory
350 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
352 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
353 ira_reg_equiv
[regno
].invariant
354 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
358 /* If we have decided to substitute X with another value, return that
359 value, otherwise return X. */
366 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
367 || ! ira_reg_equiv
[regno
].defined_p
368 || ! ira_reg_equiv
[regno
].profitable_p
369 || lra_get_regno_hard_regno (regno
) >= 0)
371 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
373 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
375 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
380 /* If we have decided to substitute X with the equivalent value,
381 return that value after elimination for INSN, otherwise return
384 get_equiv_with_elimination (rtx x
, rtx insn
)
386 rtx res
= get_equiv (x
);
388 if (x
== res
|| CONSTANT_P (res
))
390 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
), false, false, true);
393 /* Set up curr_operand_mode. */
395 init_curr_operand_mode (void)
397 int nop
= curr_static_id
->n_operands
;
398 for (int i
= 0; i
< nop
; i
++)
400 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
401 if (mode
== VOIDmode
)
403 /* The .md mode for address operands is the mode of the
404 addressed value rather than the mode of the address itself. */
405 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
408 mode
= curr_static_id
->operand
[i
].mode
;
410 curr_operand_mode
[i
] = mode
;
416 /* The page contains code to reuse input reloads. */
418 /* Structure describes input reload of the current insns. */
421 /* Reloaded value. */
423 /* Reload pseudo used. */
427 /* The number of elements in the following array. */
428 static int curr_insn_input_reloads_num
;
429 /* Array containing info about input reloads. It is used to find the
430 same input reload and reuse the reload pseudo in this case. */
431 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
433 /* Initiate data concerning reuse of input reloads for the current
436 init_curr_insn_input_reloads (void)
438 curr_insn_input_reloads_num
= 0;
441 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
442 created input reload pseudo (only if TYPE is not OP_OUT). Don't
443 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
444 wrapped up in SUBREG. The result pseudo is returned through
445 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
446 reused the already created input reload pseudo. Use TITLE to
447 describe new registers for debug purposes. */
449 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
450 enum reg_class rclass
, bool in_subreg_p
,
451 const char *title
, rtx
*result_reg
)
454 enum reg_class new_class
;
459 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
462 /* Prevent reuse value of expression with side effects,
463 e.g. volatile memory. */
464 if (! side_effects_p (original
))
465 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
466 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
467 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
469 rtx reg
= curr_insn_input_reloads
[i
].reg
;
471 /* If input is equal to original and both are VOIDmode,
472 GET_MODE (reg) might be still different from mode.
473 Ensure we don't return *result_reg with wrong mode. */
474 if (GET_MODE (reg
) != mode
)
478 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
480 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
481 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
485 if (lra_dump_file
!= NULL
)
487 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
488 dump_value_slim (lra_dump_file
, original
, 1);
490 if (new_class
!= lra_get_allocno_class (regno
))
491 lra_change_class (regno
, new_class
, ", change to", false);
492 if (lra_dump_file
!= NULL
)
493 fprintf (lra_dump_file
, "\n");
496 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
497 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
498 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
499 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
505 /* The page contains code to extract memory address parts. */
507 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
509 ok_for_index_p_nonstrict (rtx reg
)
511 unsigned regno
= REGNO (reg
);
513 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
516 /* A version of regno_ok_for_base_p for use here, when all pseudos
517 should count as OK. Arguments as for regno_ok_for_base_p. */
519 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
520 enum rtx_code outer_code
, enum rtx_code index_code
)
522 unsigned regno
= REGNO (reg
);
524 if (regno
>= FIRST_PSEUDO_REGISTER
)
526 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
531 /* The page contains major code to choose the current insn alternative
532 and generate reloads for it. */
534 /* Return the offset from REGNO of the least significant register
537 This function is used to tell whether two registers satisfy
538 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
540 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
541 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
543 lra_constraint_offset (int regno
, enum machine_mode mode
)
545 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
546 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
547 && SCALAR_INT_MODE_P (mode
))
548 return hard_regno_nregs
[regno
][mode
] - 1;
552 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
553 if they are the same hard reg, and has special hacks for
554 auto-increment and auto-decrement. This is specifically intended for
555 process_alt_operands to use in determining whether two operands
556 match. X is the operand whose number is the lower of the two.
558 It is supposed that X is the output operand and Y is the input
559 operand. Y_HARD_REGNO is the final hard regno of register Y or
560 register in subreg Y as we know it now. Otherwise, it is a
563 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
566 RTX_CODE code
= GET_CODE (x
);
571 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
572 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
576 i
= get_hard_regno (x
);
580 if ((j
= y_hard_regno
) < 0)
583 i
+= lra_constraint_offset (i
, GET_MODE (x
));
584 j
+= lra_constraint_offset (j
, GET_MODE (y
));
589 /* If two operands must match, because they are really a single
590 operand of an assembler insn, then two post-increments are invalid
591 because the assembler insn would increment only once. On the
592 other hand, a post-increment matches ordinary indexing if the
593 post-increment is the output operand. */
594 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
595 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
597 /* Two pre-increments are invalid because the assembler insn would
598 increment only once. On the other hand, a pre-increment matches
599 ordinary indexing if the pre-increment is the input operand. */
600 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
601 || GET_CODE (y
) == PRE_MODIFY
)
602 return operands_match_p (x
, XEXP (y
, 0), -1);
606 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
607 && x
== SUBREG_REG (y
))
609 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
610 && SUBREG_REG (x
) == y
)
613 /* Now we have disposed of all the cases in which different rtx
615 if (code
!= GET_CODE (y
))
618 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
619 if (GET_MODE (x
) != GET_MODE (y
))
628 return XEXP (x
, 0) == XEXP (y
, 0);
630 return XSTR (x
, 0) == XSTR (y
, 0);
636 /* Compare the elements. If any pair of corresponding elements fail
637 to match, return false for the whole things. */
639 fmt
= GET_RTX_FORMAT (code
);
640 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
646 if (XWINT (x
, i
) != XWINT (y
, i
))
651 if (XINT (x
, i
) != XINT (y
, i
))
656 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
665 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
667 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
669 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
675 /* It is believed that rtx's at this level will never
676 contain anything but integers and other rtx's, except for
677 within LABEL_REFs and SYMBOL_REFs. */
685 /* True if X is a constant that can be forced into the constant pool.
686 MODE is the mode of the operand, or VOIDmode if not known. */
687 #define CONST_POOL_OK_P(MODE, X) \
688 ((MODE) != VOIDmode \
690 && GET_CODE (X) != HIGH \
691 && !targetm.cannot_force_const_mem (MODE, X))
693 /* True if C is a non-empty register class that has too few registers
694 to be safely used as a reload target class. */
695 #define SMALL_REGISTER_CLASS_P(C) \
696 (ira_class_hard_regs_num [(C)] == 1 \
697 || (ira_class_hard_regs_num [(C)] >= 1 \
698 && targetm.class_likely_spilled_p (C)))
700 /* If REG is a reload pseudo, try to make its class satisfying CL. */
702 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
704 enum reg_class rclass
;
706 /* Do not make more accurate class from reloads generated. They are
707 mostly moves with a lot of constraints. Making more accurate
708 class may results in very narrow class and impossibility of find
709 registers for several reloads of one insn. */
710 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
712 if (GET_CODE (reg
) == SUBREG
)
713 reg
= SUBREG_REG (reg
);
714 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
716 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
717 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
720 /* Generate reloads for matching OUT and INS (array of input operand
721 numbers with end marker -1) with reg class GOAL_CLASS. Add input
722 and output reloads correspondingly to the lists *BEFORE and *AFTER.
723 OUT might be negative. In this case we generate input reloads for
724 matched input operands INS. */
726 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
727 rtx
*before
, rtx
*after
)
730 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
731 enum machine_mode inmode
, outmode
;
732 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
733 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
735 inmode
= curr_operand_mode
[ins
[0]];
736 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
737 push_to_sequence (*before
);
738 if (inmode
!= outmode
)
740 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
743 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
745 if (SCALAR_INT_MODE_P (inmode
))
746 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
748 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
749 LRA_SUBREG_P (new_out_reg
) = 1;
750 /* If the input reg is dying here, we can use the same hard
751 register for REG and IN_RTX. We do it only for original
752 pseudos as reload pseudos can die although original
753 pseudos still live where reload pseudos dies. */
754 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
755 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
756 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
761 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
763 if (SCALAR_INT_MODE_P (outmode
))
764 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
766 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
767 /* NEW_IN_REG is non-paradoxical subreg. We don't want
768 NEW_OUT_REG living above. We add clobber clause for
769 this. This is just a temporary clobber. We can remove
770 it at the end of LRA work. */
771 clobber
= emit_clobber (new_out_reg
);
772 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
773 LRA_SUBREG_P (new_in_reg
) = 1;
774 if (GET_CODE (in_rtx
) == SUBREG
)
776 rtx subreg_reg
= SUBREG_REG (in_rtx
);
778 /* If SUBREG_REG is dying here and sub-registers IN_RTX
779 and NEW_IN_REG are similar, we can use the same hard
780 register for REG and SUBREG_REG. */
781 if (REG_P (subreg_reg
)
782 && (int) REGNO (subreg_reg
) < lra_new_regno_start
783 && GET_MODE (subreg_reg
) == outmode
784 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
785 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
786 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
792 /* Pseudos have values -- see comments for lra_reg_info.
793 Different pseudos with the same value do not conflict even if
794 they live in the same place. When we create a pseudo we
795 assign value of original pseudo (if any) from which we
796 created the new pseudo. If we create the pseudo from the
797 input pseudo, the new pseudo will no conflict with the input
798 pseudo which is wrong when the input pseudo lives after the
799 insn and as the new pseudo value is changed by the insn
800 output. Therefore we create the new pseudo from the output.
802 We cannot reuse the current output register because we might
803 have a situation like "a <- a op b", where the constraints
804 force the second input operand ("b") to match the output
805 operand ("a"). "b" must then be copied into a new register
806 so that it doesn't clobber the current value of "a". */
808 new_in_reg
= new_out_reg
809 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
812 /* In operand can be got from transformations before processing insn
813 constraints. One example of such transformations is subreg
814 reloading (see function simplify_operand_subreg). The new
815 pseudos created by the transformations might have inaccurate
816 class (ALL_REGS) and we should make their classes more
818 narrow_reload_pseudo_class (in_rtx
, goal_class
);
819 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
820 *before
= get_insns ();
822 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
825 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
826 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
827 *curr_id
->operand_loc
[in
] = new_in_reg
;
829 lra_update_dups (curr_id
, ins
);
832 /* See a comment for the input operand above. */
833 narrow_reload_pseudo_class (out_rtx
, goal_class
);
834 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
837 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
839 *after
= get_insns ();
842 *curr_id
->operand_loc
[out
] = new_out_reg
;
843 lra_update_dup (curr_id
, out
);
846 /* Return register class which is union of all reg classes in insn
847 constraint alternative string starting with P. */
848 static enum reg_class
849 reg_class_from_constraints (const char *p
)
852 enum reg_class op_class
= NO_REGS
;
855 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
862 op_class
= (reg_class_subunion
863 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
869 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
873 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
875 #ifdef EXTRA_CONSTRAINT_STR
876 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
878 = (reg_class_subunion
879 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
886 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
889 while ((p
+= len
), c
);
893 /* If OP is a register, return the class of the register as per
894 get_reg_class, otherwise return NO_REGS. */
895 static inline enum reg_class
896 get_op_class (rtx op
)
898 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
901 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
902 otherwise. If modes of MEM_PSEUDO and VAL are different, use
903 SUBREG for VAL to make them equal. */
905 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
907 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
909 /* Usually size of mem_pseudo is greater than val size but in
910 rare cases it can be less as it can be defined by target
911 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
914 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
915 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
917 LRA_SUBREG_P (val
) = 1;
921 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
922 LRA_SUBREG_P (mem_pseudo
) = 1;
926 ? gen_move_insn (mem_pseudo
, val
)
927 : gen_move_insn (val
, mem_pseudo
));
930 /* Process a special case insn (register move), return true if we
931 don't need to process it anymore. INSN should be a single set
932 insn. Set up that RTL was changed through CHANGE_P and macro
933 SECONDARY_MEMORY_NEEDED says to use secondary memory through
936 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
939 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
940 enum reg_class dclass
, sclass
, secondary_class
;
941 enum machine_mode sreg_mode
;
942 secondary_reload_info sri
;
944 lra_assert (curr_insn_set
!= NULL_RTX
);
945 dreg
= dest
= SET_DEST (curr_insn_set
);
946 sreg
= src
= SET_SRC (curr_insn_set
);
947 if (GET_CODE (dest
) == SUBREG
)
948 dreg
= SUBREG_REG (dest
);
949 if (GET_CODE (src
) == SUBREG
)
950 sreg
= SUBREG_REG (src
);
951 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
953 sclass
= dclass
= NO_REGS
;
955 dclass
= get_reg_class (REGNO (dreg
));
956 if (dclass
== ALL_REGS
)
957 /* ALL_REGS is used for new pseudos created by transformations
958 like reload of SUBREG_REG (see function
959 simplify_operand_subreg). We don't know their class yet. We
960 should figure out the class from processing the insn
961 constraints not in this fast path function. Even if ALL_REGS
962 were a right class for the pseudo, secondary_... hooks usually
963 are not define for ALL_REGS. */
965 sreg_mode
= GET_MODE (sreg
);
968 sclass
= get_reg_class (REGNO (sreg
));
969 if (sclass
== ALL_REGS
)
970 /* See comments above. */
972 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
974 #ifdef SECONDARY_MEMORY_NEEDED
975 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
976 #ifdef SECONDARY_MEMORY_NEEDED_MODE
977 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
978 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
986 if (! REG_P (dreg
) || ! REG_P (sreg
))
989 sri
.icode
= CODE_FOR_nothing
;
991 secondary_class
= NO_REGS
;
992 /* Set up hard register for a reload pseudo for hook
993 secondary_reload because some targets just ignore unassigned
994 pseudos in the hook. */
995 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
997 dregno
= REGNO (dreg
);
998 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1002 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1004 sregno
= REGNO (sreg
);
1005 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1009 if (sclass
!= NO_REGS
)
1011 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1012 (reg_class_t
) sclass
,
1013 GET_MODE (src
), &sri
);
1014 if (sclass
== NO_REGS
1015 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1016 && dclass
!= NO_REGS
))
1018 enum reg_class old_sclass
= secondary_class
;
1019 secondary_reload_info old_sri
= sri
;
1021 sri
.prev_sri
= NULL
;
1022 sri
.icode
= CODE_FOR_nothing
;
1025 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1026 (reg_class_t
) dclass
,
1028 /* Check the target hook consistency. */
1030 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1031 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1032 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1035 reg_renumber
[sregno
] = -1;
1037 reg_renumber
[dregno
] = -1;
1038 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1042 if (secondary_class
!= NO_REGS
)
1043 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1047 if (old_sreg
!= sreg
)
1048 sreg
= copy_rtx (sreg
);
1049 if (sri
.icode
== CODE_FOR_nothing
)
1050 lra_emit_move (new_reg
, sreg
);
1053 enum reg_class scratch_class
;
1055 scratch_class
= (reg_class_from_constraints
1056 (insn_data
[sri
.icode
].operand
[2].constraint
));
1057 scratch_reg
= (lra_create_new_reg_with_unique_value
1058 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1059 scratch_class
, "scratch"));
1060 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1061 sreg
, scratch_reg
));
1063 before
= get_insns ();
1065 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1066 if (new_reg
!= NULL_RTX
)
1068 if (GET_CODE (src
) == SUBREG
)
1069 SUBREG_REG (src
) = new_reg
;
1071 SET_SRC (curr_insn_set
) = new_reg
;
1075 if (lra_dump_file
!= NULL
)
1077 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1078 dump_insn_slim (lra_dump_file
, curr_insn
);
1080 lra_set_insn_deleted (curr_insn
);
1086 /* The following data describe the result of process_alt_operands.
1087 The data are used in curr_insn_transform to generate reloads. */
1089 /* The chosen reg classes which should be used for the corresponding
1091 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1092 /* True if the operand should be the same as another operand and that
1093 other operand does not need a reload. */
1094 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1095 /* True if the operand does not need a reload. */
1096 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1097 /* True if the operand can be offsetable memory. */
1098 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1099 /* The number of an operand to which given operand can be matched to. */
1100 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1101 /* The number of elements in the following array. */
1102 static int goal_alt_dont_inherit_ops_num
;
1103 /* Numbers of operands whose reload pseudos should not be inherited. */
1104 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1105 /* True if the insn commutative operands should be swapped. */
1106 static bool goal_alt_swapped
;
1107 /* The chosen insn alternative. */
1108 static int goal_alt_number
;
1110 /* The following five variables are used to choose the best insn
1111 alternative. They reflect final characteristics of the best
1114 /* Number of necessary reloads and overall cost reflecting the
1115 previous value and other unpleasantness of the best alternative. */
1116 static int best_losers
, best_overall
;
1117 /* Overall number hard registers used for reloads. For example, on
1118 some targets we need 2 general registers to reload DFmode and only
1119 one floating point register. */
1120 static int best_reload_nregs
;
1121 /* Overall number reflecting distances of previous reloading the same
1122 value. The distances are counted from the current BB start. It is
1123 used to improve inheritance chances. */
1124 static int best_reload_sum
;
1126 /* True if the current insn should have no correspondingly input or
1128 static bool no_input_reloads_p
, no_output_reloads_p
;
1130 /* True if we swapped the commutative operands in the current
1132 static int curr_swapped
;
1134 /* Arrange for address element *LOC to be a register of class CL.
1135 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1136 automodified value; handle that case by adding the required output
1137 reloads to list AFTER. Return true if the RTL was changed. */
1139 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1142 enum reg_class rclass
, new_class
;
1145 enum machine_mode mode
;
1146 bool subreg_p
, before_p
= false;
1148 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1150 loc
= &SUBREG_REG (*loc
);
1152 mode
= GET_MODE (reg
);
1155 /* Always reload memory in an address even if the target supports
1157 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1162 regno
= REGNO (reg
);
1163 rclass
= get_reg_class (regno
);
1164 if ((*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1166 if (lra_dump_file
!= NULL
)
1168 fprintf (lra_dump_file
,
1169 "Changing pseudo %d in address of insn %u on equiv ",
1170 REGNO (reg
), INSN_UID (curr_insn
));
1171 dump_value_slim (lra_dump_file
, *loc
, 1);
1172 fprintf (lra_dump_file
, "\n");
1174 *loc
= copy_rtx (*loc
);
1176 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1179 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1180 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1183 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1185 lra_change_class (regno
, new_class
, " Change to", true);
1193 push_to_sequence (*before
);
1194 lra_emit_move (new_reg
, reg
);
1195 *before
= get_insns ();
1202 lra_emit_move (reg
, new_reg
);
1204 *after
= get_insns ();
1210 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1211 the insn to be inserted before curr insn. AFTER returns the
1212 the insn to be inserted after curr insn. ORIGREG and NEWREG
1213 are the original reg and new reg for reload. */
1215 insert_move_for_subreg (rtx
*before
, rtx
*after
, rtx origreg
, rtx newreg
)
1219 push_to_sequence (*before
);
1220 lra_emit_move (newreg
, origreg
);
1221 *before
= get_insns ();
1227 lra_emit_move (origreg
, newreg
);
1229 *after
= get_insns ();
1234 /* Make reloads for subreg in operand NOP with internal subreg mode
1235 REG_MODE, add new reloads for further processing. Return true if
1236 any reload was generated. */
1238 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1242 enum machine_mode mode
;
1244 rtx operand
= *curr_id
->operand_loc
[nop
];
1245 enum reg_class regclass
;
1248 before
= after
= NULL_RTX
;
1250 if (GET_CODE (operand
) != SUBREG
)
1253 mode
= GET_MODE (operand
);
1254 reg
= SUBREG_REG (operand
);
1255 type
= curr_static_id
->operand
[nop
].type
;
1256 /* If we change address for paradoxical subreg of memory, the
1257 address might violate the necessary alignment or the access might
1258 be slow. So take this into consideration. We should not worry
1259 about access beyond allocated memory for paradoxical memory
1260 subregs as we don't substitute such equiv memory (see processing
1261 equivalences in function lra_constraints) and because for spilled
1262 pseudos we allocate stack memory enough for the biggest
1263 corresponding paradoxical subreg. */
1265 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1266 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1267 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1269 alter_subreg (curr_id
->operand_loc
[nop
], false);
1272 /* Put constant into memory when we have mixed modes. It generates
1273 a better code in most cases as it does not need a secondary
1274 reload memory. It also prevents LRA looping when LRA is using
1275 secondary reload memory again and again. */
1276 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1277 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1279 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1280 alter_subreg (curr_id
->operand_loc
[nop
], false);
1283 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1284 if there may be a problem accessing OPERAND in the outer
1287 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1288 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1289 /* Don't reload paradoxical subregs because we could be looping
1290 having repeatedly final regno out of hard regs range. */
1291 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1292 >= hard_regno_nregs
[hard_regno
][mode
])
1293 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1294 SUBREG_BYTE (operand
), mode
) < 0
1295 /* Don't reload subreg for matching reload. It is actually
1296 valid subreg in LRA. */
1297 && ! LRA_SUBREG_P (operand
))
1298 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1300 enum reg_class rclass
;
1303 /* There is a big probability that we will get the same class
1304 for the new pseudo and we will get the same insn which
1305 means infinite looping. So spill the new pseudo. */
1308 /* The class will be defined later in curr_insn_transform. */
1310 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1312 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1313 rclass
, TRUE
, "subreg reg", &new_reg
))
1315 bool insert_before
, insert_after
;
1316 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1318 insert_before
= (type
!= OP_OUT
1319 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1320 insert_after
= (type
!= OP_IN
);
1321 insert_move_for_subreg (insert_before
? &before
: NULL
,
1322 insert_after
? &after
: NULL
,
1325 SUBREG_REG (operand
) = new_reg
;
1326 lra_process_new_insns (curr_insn
, before
, after
,
1327 "Inserting subreg reload");
1330 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1331 IRA allocates hardreg to the inner pseudo reg according to its mode
1332 instead of the outermode, so the size of the hardreg may not be enough
1333 to contain the outermode operand, in that case we may need to insert
1334 reload for the reg. For the following two types of paradoxical subreg,
1335 we need to insert reload:
1336 1. If the op_type is OP_IN, and the hardreg could not be paired with
1337 other hardreg to contain the outermode operand
1338 (checked by in_hard_reg_set_p), we need to insert the reload.
1339 2. If the op_type is OP_OUT or OP_INOUT.
1341 Here is a paradoxical subreg example showing how the reload is generated:
1343 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1344 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1346 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1347 here, if reg107 is assigned to hardreg R15, because R15 is the last
1348 hardreg, compiler cannot find another hardreg to pair with R15 to
1349 contain TImode data. So we insert a TImode reload reg180 for it.
1350 After reload is inserted:
1352 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1353 (reg:DI 107 [ __comp ])) -1
1354 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1355 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1357 Two reload hard registers will be allocated to reg180 to save TImode data
1359 else if (REG_P (reg
)
1360 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1361 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1362 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1363 < hard_regno_nregs
[hard_regno
][mode
])
1364 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1366 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1369 /* The class will be defined later in curr_insn_transform. */
1370 enum reg_class rclass
1371 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1373 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1374 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1377 bool insert_before
, insert_after
;
1379 PUT_MODE (new_reg
, mode
);
1380 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1381 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1383 insert_before
= (type
!= OP_OUT
);
1384 insert_after
= (type
!= OP_IN
);
1385 insert_move_for_subreg (insert_before
? &before
: NULL
,
1386 insert_after
? &after
: NULL
,
1389 SUBREG_REG (operand
) = new_reg
;
1390 lra_process_new_insns (curr_insn
, before
, after
,
1391 "Inserting paradoxical subreg reload");
1397 /* Return TRUE if X refers for a hard register from SET. */
1399 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1401 int i
, j
, x_hard_regno
;
1402 enum machine_mode mode
;
1408 code
= GET_CODE (x
);
1409 mode
= GET_MODE (x
);
1413 code
= GET_CODE (x
);
1414 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1415 mode
= GET_MODE (x
);
1420 x_hard_regno
= get_hard_regno (x
);
1421 return (x_hard_regno
>= 0
1422 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1426 struct address_info ad
;
1428 decompose_mem_address (&ad
, x
);
1429 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1431 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1434 fmt
= GET_RTX_FORMAT (code
);
1435 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1439 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1442 else if (fmt
[i
] == 'E')
1444 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1445 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1452 /* Return true if OP is a spilled pseudo. */
1454 spilled_pseudo_p (rtx op
)
1457 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1460 /* Return true if X is a general constant. */
1462 general_constant_p (rtx x
)
1464 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1468 reg_in_class_p (rtx reg
, enum reg_class cl
)
1471 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1472 return in_class_p (reg
, cl
, NULL
);
1475 /* Major function to choose the current insn alternative and what
1476 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1477 negative we should consider only this alternative. Return false if
1478 we can not choose the alternative or find how to reload the
1481 process_alt_operands (int only_alternative
)
1484 int nop
, overall
, nalt
;
1485 int n_alternatives
= curr_static_id
->n_alternatives
;
1486 int n_operands
= curr_static_id
->n_operands
;
1487 /* LOSERS counts the operands that don't fit this alternative and
1488 would require loading. */
1490 /* REJECT is a count of how undesirable this alternative says it is
1491 if any reloading is required. If the alternative matches exactly
1492 then REJECT is ignored, but otherwise it gets this much counted
1493 against it in addition to the reloading needed. */
1495 /* The number of elements in the following array. */
1496 int early_clobbered_regs_num
;
1497 /* Numbers of operands which are early clobber registers. */
1498 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1499 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1500 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1501 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1502 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1503 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1504 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1505 /* The number of elements in the following array. */
1506 int curr_alt_dont_inherit_ops_num
;
1507 /* Numbers of operands whose reload pseudos should not be inherited. */
1508 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1510 /* The register when the operand is a subreg of register, otherwise the
1512 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1513 /* The register if the operand is a register or subreg of register,
1515 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1516 int hard_regno
[MAX_RECOG_OPERANDS
];
1517 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1518 int reload_nregs
, reload_sum
;
1522 /* Calculate some data common for all alternatives to speed up the
1524 for (nop
= 0; nop
< n_operands
; nop
++)
1528 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1529 /* The real hard regno of the operand after the allocation. */
1530 hard_regno
[nop
] = get_hard_regno (op
);
1532 operand_reg
[nop
] = reg
= op
;
1533 biggest_mode
[nop
] = GET_MODE (op
);
1534 if (GET_CODE (op
) == SUBREG
)
1536 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1537 if (GET_MODE_SIZE (biggest_mode
[nop
])
1538 < GET_MODE_SIZE (GET_MODE (reg
)))
1539 biggest_mode
[nop
] = GET_MODE (reg
);
1542 operand_reg
[nop
] = NULL_RTX
;
1543 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1544 || ((int) REGNO (reg
)
1545 == lra_get_elimination_hard_regno (REGNO (reg
))))
1546 no_subreg_reg_operand
[nop
] = reg
;
1548 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1549 /* Just use natural mode for elimination result. It should
1550 be enough for extra constraints hooks. */
1551 = regno_reg_rtx
[hard_regno
[nop
]];
1554 /* The constraints are made of several alternatives. Each operand's
1555 constraint looks like foo,bar,... with commas separating the
1556 alternatives. The first alternatives for all operands go
1557 together, the second alternatives go together, etc.
1559 First loop over alternatives. */
1560 alternative_mask enabled
= curr_id
->enabled_alternatives
;
1561 if (only_alternative
>= 0)
1562 enabled
&= ALTERNATIVE_BIT (only_alternative
);
1564 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1566 /* Loop over operands for one constraint alternative. */
1567 if (!TEST_BIT (enabled
, nalt
))
1570 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1571 for (nop
= 0; nop
< n_operands
; nop
++)
1573 int inc
= (curr_static_id
1574 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1575 if (lra_dump_file
!= NULL
&& inc
!= 0)
1576 fprintf (lra_dump_file
,
1577 " Staticly defined alt reject+=%d\n", inc
);
1580 early_clobbered_regs_num
= 0;
1582 for (nop
= 0; nop
< n_operands
; nop
++)
1586 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1587 bool win
, did_match
, offmemok
, early_clobber_p
;
1588 /* false => this operand can be reloaded somehow for this
1591 /* true => this operand can be reloaded if the alternative
1594 /* True if a constant forced into memory would be OK for
1597 enum reg_class this_alternative
, this_costly_alternative
;
1598 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1599 bool this_alternative_match_win
, this_alternative_win
;
1600 bool this_alternative_offmemok
;
1602 enum machine_mode mode
;
1604 opalt_num
= nalt
* n_operands
+ nop
;
1605 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1607 /* Fast track for no constraints at all. */
1608 curr_alt
[nop
] = NO_REGS
;
1609 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1610 curr_alt_win
[nop
] = true;
1611 curr_alt_match_win
[nop
] = false;
1612 curr_alt_offmemok
[nop
] = false;
1613 curr_alt_matches
[nop
] = -1;
1617 op
= no_subreg_reg_operand
[nop
];
1618 mode
= curr_operand_mode
[nop
];
1620 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1623 early_clobber_p
= false;
1624 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1626 this_costly_alternative
= this_alternative
= NO_REGS
;
1627 /* We update set of possible hard regs besides its class
1628 because reg class might be inaccurate. For example,
1629 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1630 is translated in HI_REGS because classes are merged by
1631 pairs and there is no accurate intermediate class. */
1632 CLEAR_HARD_REG_SET (this_alternative_set
);
1633 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1634 this_alternative_win
= false;
1635 this_alternative_match_win
= false;
1636 this_alternative_offmemok
= false;
1637 this_alternative_matches
= -1;
1639 /* An empty constraint should be excluded by the fast
1641 lra_assert (*p
!= 0 && *p
!= ',');
1643 /* Scan this alternative's specs for this operand; set WIN
1644 if the operand fits any letter in this alternative.
1645 Otherwise, clear BADOP if this operand could fit some
1646 letter after reloads, or set WINREG if this operand could
1647 fit after reloads provided the constraint allows some
1652 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1661 case '=': case '+': case '?': case '*': case '!':
1662 case ' ': case '\t':
1666 /* We only support one commutative marker, the first
1667 one. We already set commutative above. */
1671 early_clobber_p
= true;
1675 /* Ignore rest of this alternative. */
1679 case '0': case '1': case '2': case '3': case '4':
1680 case '5': case '6': case '7': case '8': case '9':
1685 m
= strtoul (p
, &end
, 10);
1688 lra_assert (nop
> m
);
1690 this_alternative_matches
= m
;
1691 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1692 /* We are supposed to match a previous operand.
1693 If we do, we win if that one did. If we do
1694 not, count both of the operands as losers.
1695 (This is too conservative, since most of the
1696 time only a single reload insn will be needed
1697 to make the two operands win. As a result,
1698 this alternative may be rejected when it is
1699 actually desirable.) */
1701 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1702 *curr_id
->operand_loc
[m
], m_hregno
))
1704 /* We should reject matching of an early
1705 clobber operand if the matching operand is
1706 not dying in the insn. */
1707 if (! curr_static_id
->operand
[m
].early_clobber
1708 || operand_reg
[nop
] == NULL_RTX
1709 || (find_regno_note (curr_insn
, REG_DEAD
,
1711 || REGNO (op
) == REGNO (operand_reg
[m
])))
1716 /* If we are matching a non-offsettable
1717 address where an offsettable address was
1718 expected, then we must reject this
1719 combination, because we can't reload
1721 if (curr_alt_offmemok
[m
]
1722 && MEM_P (*curr_id
->operand_loc
[m
])
1723 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1728 /* Operands don't match. Both operands must
1729 allow a reload register, otherwise we
1730 cannot make them match. */
1731 if (curr_alt
[m
] == NO_REGS
)
1733 /* Retroactively mark the operand we had to
1734 match as a loser, if it wasn't already and
1735 it wasn't matched to a register constraint
1736 (e.g it might be matched by memory). */
1738 && (operand_reg
[m
] == NULL_RTX
1739 || hard_regno
[m
] < 0))
1743 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1744 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1747 /* Prefer matching earlyclobber alternative as
1748 it results in less hard regs required for
1749 the insn than a non-matching earlyclobber
1751 if (curr_static_id
->operand
[m
].early_clobber
)
1753 if (lra_dump_file
!= NULL
)
1756 " %d Matching earlyclobber alt:"
1761 /* Otherwise we prefer no matching
1762 alternatives because it gives more freedom
1764 else if (operand_reg
[nop
] == NULL_RTX
1765 || (find_regno_note (curr_insn
, REG_DEAD
,
1766 REGNO (operand_reg
[nop
]))
1769 if (lra_dump_file
!= NULL
)
1772 " %d Matching alt: reject+=2\n",
1777 /* If we have to reload this operand and some
1778 previous operand also had to match the same
1779 thing as this operand, we don't know how to do
1781 if (!match_p
|| !curr_alt_win
[m
])
1783 for (i
= 0; i
< nop
; i
++)
1784 if (curr_alt_matches
[i
] == m
)
1792 /* This can be fixed with reloads if the operand
1793 we are supposed to match can be fixed with
1796 this_alternative
= curr_alt
[m
];
1797 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1798 winreg
= this_alternative
!= NO_REGS
;
1803 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1805 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1806 IOR_HARD_REG_SET (this_alternative_set
,
1807 reg_class_contents
[cl
]);
1810 this_costly_alternative
1811 = reg_class_subunion
[this_costly_alternative
][cl
];
1812 IOR_HARD_REG_SET (this_costly_alternative_set
,
1813 reg_class_contents
[cl
]);
1819 case TARGET_MEM_CONSTRAINT
:
1820 if (MEM_P (op
) || spilled_pseudo_p (op
))
1822 /* We can put constant or pseudo value into memory
1823 to satisfy the constraint. */
1824 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1831 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1832 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1838 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1839 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1843 /* Memory op whose address is not offsettable. */
1846 && ! offsettable_nonstrict_memref_p (op
))
1850 /* Memory operand whose address is offsettable. */
1853 && offsettable_nonstrict_memref_p (op
))
1854 || spilled_pseudo_p (op
))
1856 /* We can put constant or pseudo value into memory
1857 or make memory address offsetable to satisfy the
1859 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1867 if (GET_CODE (op
) == CONST_DOUBLE
1868 || (GET_CODE (op
) == CONST_VECTOR
1869 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1875 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1876 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1881 if (CONST_SCALAR_INT_P (op
))
1885 if (general_constant_p (op
))
1890 if (CONST_SCALAR_INT_P (op
))
1902 if (CONST_INT_P (op
)
1903 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1908 /* This constraint should be excluded by the fast
1915 || general_constant_p (op
)
1916 || spilled_pseudo_p (op
))
1918 /* Drop through into 'r' case. */
1922 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1923 IOR_HARD_REG_SET (this_alternative_set
,
1924 reg_class_contents
[GENERAL_REGS
]);
1927 this_costly_alternative
1928 = (reg_class_subunion
1929 [this_costly_alternative
][GENERAL_REGS
]);
1930 IOR_HARD_REG_SET (this_costly_alternative_set
,
1931 reg_class_contents
[GENERAL_REGS
]);
1936 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1938 #ifdef EXTRA_CONSTRAINT_STR
1939 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1941 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1943 else if (spilled_pseudo_p (op
))
1946 /* If we didn't already win, we can reload
1947 constants via force_const_mem or put the
1948 pseudo value into memory, or make other
1949 memory by reloading the address like for
1951 if (CONST_POOL_OK_P (mode
, op
)
1952 || MEM_P (op
) || REG_P (op
))
1958 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1960 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1963 /* If we didn't already win, we can reload
1964 the address into a base register. */
1965 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1968 = reg_class_subunion
[this_alternative
][cl
];
1969 IOR_HARD_REG_SET (this_alternative_set
,
1970 reg_class_contents
[cl
]);
1973 this_costly_alternative
1974 = (reg_class_subunion
1975 [this_costly_alternative
][cl
]);
1976 IOR_HARD_REG_SET (this_costly_alternative_set
,
1977 reg_class_contents
[cl
]);
1983 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1989 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1990 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1991 IOR_HARD_REG_SET (this_alternative_set
,
1992 reg_class_contents
[cl
]);
1995 this_costly_alternative
1996 = reg_class_subunion
[this_costly_alternative
][cl
];
1997 IOR_HARD_REG_SET (this_costly_alternative_set
,
1998 reg_class_contents
[cl
]);
2001 if (mode
== BLKmode
)
2006 if (hard_regno
[nop
] >= 0
2007 && in_hard_reg_set_p (this_alternative_set
,
2008 mode
, hard_regno
[nop
]))
2010 else if (hard_regno
[nop
] < 0
2011 && in_class_p (op
, this_alternative
, NULL
))
2016 if (c
!= ' ' && c
!= '\t')
2017 costly_p
= c
== '*';
2019 while ((p
+= len
), c
);
2021 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2022 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2023 /* Record which operands fit this alternative. */
2026 this_alternative_win
= true;
2027 if (operand_reg
[nop
] != NULL_RTX
)
2029 if (hard_regno
[nop
] >= 0)
2031 if (in_hard_reg_set_p (this_costly_alternative_set
,
2032 mode
, hard_regno
[nop
]))
2034 if (lra_dump_file
!= NULL
)
2035 fprintf (lra_dump_file
,
2036 " %d Costly set: reject++\n",
2043 /* Prefer won reg to spilled pseudo under other
2044 equal conditions for possibe inheritance. */
2047 if (lra_dump_file
!= NULL
)
2050 " %d Non pseudo reload: reject++\n",
2054 if (in_class_p (operand_reg
[nop
],
2055 this_costly_alternative
, NULL
))
2057 if (lra_dump_file
!= NULL
)
2060 " %d Non pseudo costly reload:"
2066 /* We simulate the behaviour of old reload here.
2067 Although scratches need hard registers and it
2068 might result in spilling other pseudos, no reload
2069 insns are generated for the scratches. So it
2070 might cost something but probably less than old
2071 reload pass believes. */
2074 if (lra_dump_file
!= NULL
)
2075 fprintf (lra_dump_file
,
2076 " %d Scratch win: reject+=2\n",
2083 this_alternative_match_win
= true;
2086 int const_to_mem
= 0;
2089 /* Never do output reload of stack pointer. It makes
2090 impossible to do elimination when SP is changed in
2092 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2093 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2096 /* If this alternative asks for a specific reg class, see if there
2097 is at least one allocatable register in that class. */
2099 = (this_alternative
== NO_REGS
2100 || (hard_reg_set_subset_p
2101 (reg_class_contents
[this_alternative
],
2102 lra_no_alloc_regs
)));
2104 /* For asms, verify that the class for this alternative is possible
2105 for the mode that is specified. */
2106 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2109 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2110 if (HARD_REGNO_MODE_OK (i
, mode
)
2111 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2114 if (i
== FIRST_PSEUDO_REGISTER
)
2118 /* If this operand accepts a register, and if the
2119 register class has at least one allocatable register,
2120 then this operand can be reloaded. */
2121 if (winreg
&& !no_regs_p
)
2126 if (lra_dump_file
!= NULL
)
2127 fprintf (lra_dump_file
,
2128 " alt=%d: Bad operand -- refuse\n",
2133 /* If not assigned pseudo has a class which a subset of
2134 required reg class, it is a less costly alternative
2135 as the pseudo still can get a hard reg of necessary
2137 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2138 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2139 && ira_class_subset_p
[this_alternative
][cl
])
2141 if (lra_dump_file
!= NULL
)
2144 " %d Super set class reg: reject-=3\n", nop
);
2148 this_alternative_offmemok
= offmemok
;
2149 if (this_costly_alternative
!= NO_REGS
)
2151 if (lra_dump_file
!= NULL
)
2152 fprintf (lra_dump_file
,
2153 " %d Costly loser: reject++\n", nop
);
2156 /* If the operand is dying, has a matching constraint,
2157 and satisfies constraints of the matched operand
2158 which failed to satisfy the own constraints, most probably
2159 the reload for this operand will be gone. */
2160 if (this_alternative_matches
>= 0
2161 && !curr_alt_win
[this_alternative_matches
]
2163 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2164 && (hard_regno
[nop
] >= 0
2165 ? in_hard_reg_set_p (this_alternative_set
,
2166 mode
, hard_regno
[nop
])
2167 : in_class_p (op
, this_alternative
, NULL
)))
2169 if (lra_dump_file
!= NULL
)
2172 " %d Dying matched operand reload: reject++\n",
2178 /* Strict_low_part requires to reload the register
2179 not the sub-register. In this case we should
2180 check that a final reload hard reg can hold the
2182 if (curr_static_id
->operand
[nop
].strict_low
2184 && hard_regno
[nop
] < 0
2185 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2186 && ira_class_hard_regs_num
[this_alternative
] > 0
2187 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2188 [this_alternative
][0],
2190 (*curr_id
->operand_loc
[nop
])))
2192 if (lra_dump_file
!= NULL
)
2195 " alt=%d: Strict low subreg reload -- refuse\n",
2201 if (operand_reg
[nop
] != NULL_RTX
2202 /* Output operands and matched input operands are
2203 not inherited. The following conditions do not
2204 exactly describe the previous statement but they
2205 are pretty close. */
2206 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2207 && (this_alternative_matches
< 0
2208 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2210 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2214 /* The value of reload_sum has sense only if we
2215 process insns in their order. It happens only on
2216 the first constraints sub-pass when we do most of
2218 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2219 reload_sum
+= last_reload
- bb_reload_num
;
2221 /* If this is a constant that is reloaded into the
2222 desired class by copying it to memory first, count
2223 that as another reload. This is consistent with
2224 other code and is required to avoid choosing another
2225 alternative when the constant is moved into memory.
2226 Note that the test here is precisely the same as in
2227 the code below that calls force_const_mem. */
2228 if (CONST_POOL_OK_P (mode
, op
)
2229 && ((targetm
.preferred_reload_class
2230 (op
, this_alternative
) == NO_REGS
)
2231 || no_input_reloads_p
))
2238 /* Alternative loses if it requires a type of reload not
2239 permitted for this insn. We can always reload
2240 objects with a REG_UNUSED note. */
2241 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2242 && no_output_reloads_p
2243 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2244 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2245 && no_input_reloads_p
&& ! const_to_mem
)
2246 || (this_alternative_matches
>= 0
2247 && (no_input_reloads_p
2248 || (no_output_reloads_p
2249 && (curr_static_id
->operand
2250 [this_alternative_matches
].type
!= OP_IN
)
2251 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2252 no_subreg_reg_operand
2253 [this_alternative_matches
])))))
2255 if (lra_dump_file
!= NULL
)
2258 " alt=%d: No input/otput reload -- refuse\n",
2263 /* Check strong discouragement of reload of non-constant
2264 into class THIS_ALTERNATIVE. */
2265 if (! CONSTANT_P (op
) && ! no_regs_p
2266 && (targetm
.preferred_reload_class
2267 (op
, this_alternative
) == NO_REGS
2268 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2269 && (targetm
.preferred_output_reload_class
2270 (op
, this_alternative
) == NO_REGS
))))
2272 if (lra_dump_file
!= NULL
)
2273 fprintf (lra_dump_file
,
2274 " %d Non-prefered reload: reject+=%d\n",
2275 nop
, LRA_MAX_REJECT
);
2276 reject
+= LRA_MAX_REJECT
;
2279 if (! (MEM_P (op
) && offmemok
)
2280 && ! (const_to_mem
&& constmemok
))
2282 /* We prefer to reload pseudos over reloading other
2283 things, since such reloads may be able to be
2284 eliminated later. So bump REJECT in other cases.
2285 Don't do this in the case where we are forcing a
2286 constant into memory and it will then win since
2287 we don't want to have a different alternative
2289 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2291 if (lra_dump_file
!= NULL
)
2294 " %d Non-pseudo reload: reject+=2\n",
2301 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2303 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2305 if (lra_dump_file
!= NULL
)
2308 " %d Small class reload: reject+=%d\n",
2309 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2310 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2314 /* We are trying to spill pseudo into memory. It is
2315 usually more costly than moving to a hard register
2316 although it might takes the same number of
2318 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2320 if (lra_dump_file
!= NULL
)
2323 " %d Spill pseudo into memory: reject+=3\n",
2326 if (VECTOR_MODE_P (mode
))
2328 /* Spilling vectors into memory is usually more
2329 costly as they contain big values. */
2330 if (lra_dump_file
!= NULL
)
2333 " %d Spill vector pseudo: reject+=2\n",
2339 #ifdef SECONDARY_MEMORY_NEEDED
2340 /* If reload requires moving value through secondary
2341 memory, it will need one more insn at least. */
2342 if (this_alternative
!= NO_REGS
2343 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2344 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2345 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2347 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2348 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2352 /* Input reloads can be inherited more often than output
2353 reloads can be removed, so penalize output
2355 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2357 if (lra_dump_file
!= NULL
)
2360 " %d Non input pseudo reload: reject++\n",
2366 if (early_clobber_p
&& ! scratch_p
)
2368 if (lra_dump_file
!= NULL
)
2369 fprintf (lra_dump_file
,
2370 " %d Early clobber: reject++\n", nop
);
2373 /* ??? We check early clobbers after processing all operands
2374 (see loop below) and there we update the costs more.
2375 Should we update the cost (may be approximately) here
2376 because of early clobber register reloads or it is a rare
2377 or non-important thing to be worth to do it. */
2378 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2379 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2381 if (lra_dump_file
!= NULL
)
2382 fprintf (lra_dump_file
,
2383 " alt=%d,overall=%d,losers=%d -- refuse\n",
2384 nalt
, overall
, losers
);
2388 curr_alt
[nop
] = this_alternative
;
2389 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2390 curr_alt_win
[nop
] = this_alternative_win
;
2391 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2392 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2393 curr_alt_matches
[nop
] = this_alternative_matches
;
2395 if (this_alternative_matches
>= 0
2396 && !did_match
&& !this_alternative_win
)
2397 curr_alt_win
[this_alternative_matches
] = false;
2399 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2400 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2402 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2403 /* Prevent processing non-move insns. */
2404 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2405 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2406 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2407 && REG_P (no_subreg_reg_operand
[0])
2408 && REG_P (no_subreg_reg_operand
[1])
2409 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2410 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2411 || (! curr_alt_win
[0] && curr_alt_win
[1]
2412 && REG_P (no_subreg_reg_operand
[1])
2413 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2414 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2415 && REG_P (no_subreg_reg_operand
[0])
2416 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2417 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2418 no_subreg_reg_operand
[1])
2419 || (targetm
.preferred_reload_class
2420 (no_subreg_reg_operand
[1],
2421 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2422 /* If it is a result of recent elimination in move
2423 insn we can transform it into an add still by
2424 using this alternative. */
2425 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2427 /* We have a move insn and a new reload insn will be similar
2428 to the current insn. We should avoid such situation as it
2429 results in LRA cycling. */
2430 overall
+= LRA_MAX_REJECT
;
2433 curr_alt_dont_inherit_ops_num
= 0;
2434 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2436 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2437 HARD_REG_SET temp_set
;
2439 i
= early_clobbered_nops
[nop
];
2440 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2441 || hard_regno
[i
] < 0)
2443 lra_assert (operand_reg
[i
] != NULL_RTX
);
2444 clobbered_hard_regno
= hard_regno
[i
];
2445 CLEAR_HARD_REG_SET (temp_set
);
2446 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2447 first_conflict_j
= last_conflict_j
= -1;
2448 for (j
= 0; j
< n_operands
; j
++)
2450 /* We don't want process insides of match_operator and
2451 match_parallel because otherwise we would process
2452 their operands once again generating a wrong
2454 || curr_static_id
->operand
[j
].is_operator
)
2456 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2457 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2459 /* If we don't reload j-th operand, check conflicts. */
2460 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2461 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2463 if (first_conflict_j
< 0)
2464 first_conflict_j
= j
;
2465 last_conflict_j
= j
;
2467 if (last_conflict_j
< 0)
2469 /* If earlyclobber operand conflicts with another
2470 non-matching operand which is actually the same register
2471 as the earlyclobber operand, it is better to reload the
2472 another operand as an operand matching the earlyclobber
2473 operand can be also the same. */
2474 if (first_conflict_j
== last_conflict_j
2475 && operand_reg
[last_conflict_j
]
2476 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2477 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2479 curr_alt_win
[last_conflict_j
] = false;
2480 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2483 /* Early clobber was already reflected in REJECT. */
2484 lra_assert (reject
> 0);
2485 if (lra_dump_file
!= NULL
)
2488 " %d Conflict early clobber reload: reject--\n",
2491 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2495 /* We need to reload early clobbered register and the
2496 matched registers. */
2497 for (j
= 0; j
< n_operands
; j
++)
2498 if (curr_alt_matches
[j
] == i
)
2500 curr_alt_match_win
[j
] = false;
2502 overall
+= LRA_LOSER_COST_FACTOR
;
2504 if (! curr_alt_match_win
[i
])
2505 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2508 /* Remember pseudos used for match reloads are never
2510 lra_assert (curr_alt_matches
[i
] >= 0);
2511 curr_alt_win
[curr_alt_matches
[i
]] = false;
2513 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2515 /* Early clobber was already reflected in REJECT. */
2516 lra_assert (reject
> 0);
2517 if (lra_dump_file
!= NULL
)
2520 " %d Matched conflict early clobber reloads:"
2524 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2527 if (lra_dump_file
!= NULL
)
2528 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2529 nalt
, overall
, losers
, reload_nregs
);
2531 /* If this alternative can be made to work by reloading, and it
2532 needs less reloading than the others checked so far, record
2533 it as the chosen goal for reloading. */
2534 if ((best_losers
!= 0 && losers
== 0)
2535 || (((best_losers
== 0 && losers
== 0)
2536 || (best_losers
!= 0 && losers
!= 0))
2537 && (best_overall
> overall
2538 || (best_overall
== overall
2539 /* If the cost of the reloads is the same,
2540 prefer alternative which requires minimal
2541 number of reload regs. */
2542 && (reload_nregs
< best_reload_nregs
2543 || (reload_nregs
== best_reload_nregs
2544 && (best_reload_sum
< reload_sum
2545 || (best_reload_sum
== reload_sum
2546 && nalt
< goal_alt_number
))))))))
2548 for (nop
= 0; nop
< n_operands
; nop
++)
2550 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2551 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2552 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2553 goal_alt
[nop
] = curr_alt
[nop
];
2554 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2556 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2557 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2558 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2559 goal_alt_swapped
= curr_swapped
;
2560 best_overall
= overall
;
2561 best_losers
= losers
;
2562 best_reload_nregs
= reload_nregs
;
2563 best_reload_sum
= reload_sum
;
2564 goal_alt_number
= nalt
;
2567 /* Everything is satisfied. Do not process alternatives
2576 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2577 space AS, and check that each pseudo has the proper kind of hard
2580 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2581 rtx addr
, addr_space_t as
)
2583 #ifdef GO_IF_LEGITIMATE_ADDRESS
2584 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2585 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2591 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2595 /* Return whether address AD is valid. */
2598 valid_address_p (struct address_info
*ad
)
2600 /* Some ports do not check displacements for eliminable registers,
2601 so we replace them temporarily with the elimination target. */
2602 rtx saved_base_reg
= NULL_RTX
;
2603 rtx saved_index_reg
= NULL_RTX
;
2604 rtx
*base_term
= strip_subreg (ad
->base_term
);
2605 rtx
*index_term
= strip_subreg (ad
->index_term
);
2606 if (base_term
!= NULL
)
2608 saved_base_reg
= *base_term
;
2609 lra_eliminate_reg_if_possible (base_term
);
2610 if (ad
->base_term2
!= NULL
)
2611 *ad
->base_term2
= *ad
->base_term
;
2613 if (index_term
!= NULL
)
2615 saved_index_reg
= *index_term
;
2616 lra_eliminate_reg_if_possible (index_term
);
2618 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2619 if (saved_base_reg
!= NULL_RTX
)
2621 *base_term
= saved_base_reg
;
2622 if (ad
->base_term2
!= NULL
)
2623 *ad
->base_term2
= *ad
->base_term
;
2625 if (saved_index_reg
!= NULL_RTX
)
2626 *index_term
= saved_index_reg
;
2630 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2632 base_plus_disp_to_reg (struct address_info
*ad
)
2637 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2638 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2639 get_index_code (ad
));
2640 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2642 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2646 /* Make reload of index part of address AD. Return the new
2649 index_part_to_reg (struct address_info
*ad
)
2653 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2654 INDEX_REG_CLASS
, "index term");
2655 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2656 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2660 /* Return true if we can add a displacement to address AD, even if that
2661 makes the address invalid. The fix-up code requires any new address
2662 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2664 can_add_disp_p (struct address_info
*ad
)
2666 return (!ad
->autoinc_p
2667 && ad
->segment
== NULL
2668 && ad
->base
== ad
->base_term
2669 && ad
->disp
== ad
->disp_term
);
2672 /* Make equiv substitution in address AD. Return true if a substitution
2675 equiv_address_substitution (struct address_info
*ad
)
2677 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2678 HOST_WIDE_INT disp
, scale
;
2681 base_term
= strip_subreg (ad
->base_term
);
2682 if (base_term
== NULL
)
2683 base_reg
= new_base_reg
= NULL_RTX
;
2686 base_reg
= *base_term
;
2687 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2689 index_term
= strip_subreg (ad
->index_term
);
2690 if (index_term
== NULL
)
2691 index_reg
= new_index_reg
= NULL_RTX
;
2694 index_reg
= *index_term
;
2695 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2697 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2701 if (lra_dump_file
!= NULL
)
2703 fprintf (lra_dump_file
, "Changing address in insn %d ",
2704 INSN_UID (curr_insn
));
2705 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2707 if (base_reg
!= new_base_reg
)
2709 if (REG_P (new_base_reg
))
2711 *base_term
= new_base_reg
;
2714 else if (GET_CODE (new_base_reg
) == PLUS
2715 && REG_P (XEXP (new_base_reg
, 0))
2716 && CONST_INT_P (XEXP (new_base_reg
, 1))
2717 && can_add_disp_p (ad
))
2719 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2720 *base_term
= XEXP (new_base_reg
, 0);
2723 if (ad
->base_term2
!= NULL
)
2724 *ad
->base_term2
= *ad
->base_term
;
2726 if (index_reg
!= new_index_reg
)
2728 if (REG_P (new_index_reg
))
2730 *index_term
= new_index_reg
;
2733 else if (GET_CODE (new_index_reg
) == PLUS
2734 && REG_P (XEXP (new_index_reg
, 0))
2735 && CONST_INT_P (XEXP (new_index_reg
, 1))
2736 && can_add_disp_p (ad
)
2737 && (scale
= get_index_scale (ad
)))
2739 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2740 *index_term
= XEXP (new_index_reg
, 0);
2746 if (ad
->disp
!= NULL
)
2747 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2750 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2751 update_address (ad
);
2755 if (lra_dump_file
!= NULL
)
2758 fprintf (lra_dump_file
, " -- no change\n");
2761 fprintf (lra_dump_file
, " on equiv ");
2762 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2763 fprintf (lra_dump_file
, "\n");
2769 /* Major function to make reloads for an address in operand NOP.
2770 The supported cases are:
2772 1) an address that existed before LRA started, at which point it
2773 must have been valid. These addresses are subject to elimination
2774 and may have become invalid due to the elimination offset being out
2777 2) an address created by forcing a constant to memory
2778 (force_const_to_mem). The initial form of these addresses might
2779 not be valid, and it is this function's job to make them valid.
2781 3) a frame address formed from a register and a (possibly zero)
2782 constant offset. As above, these addresses might not be valid and
2783 this function must make them so.
2785 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2786 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2787 address. Return true for any RTL change. */
2789 process_address (int nop
, rtx
*before
, rtx
*after
)
2791 struct address_info ad
;
2793 rtx op
= *curr_id
->operand_loc
[nop
];
2794 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2797 if (constraint
[0] == 'p'
2798 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2799 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2800 else if (MEM_P (op
))
2801 decompose_mem_address (&ad
, op
);
2802 else if (GET_CODE (op
) == SUBREG
2803 && MEM_P (SUBREG_REG (op
)))
2804 decompose_mem_address (&ad
, SUBREG_REG (op
));
2807 change_p
= equiv_address_substitution (&ad
);
2808 if (ad
.base_term
!= NULL
2809 && (process_addr_reg
2810 (ad
.base_term
, before
,
2812 && !(REG_P (*ad
.base_term
)
2813 && find_regno_note (curr_insn
, REG_DEAD
,
2814 REGNO (*ad
.base_term
)) != NULL_RTX
)
2816 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2817 get_index_code (&ad
)))))
2820 if (ad
.base_term2
!= NULL
)
2821 *ad
.base_term2
= *ad
.base_term
;
2823 if (ad
.index_term
!= NULL
2824 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2827 #ifdef EXTRA_CONSTRAINT_STR
2828 /* Target hooks sometimes reject extra constraint addresses -- use
2829 EXTRA_CONSTRAINT_STR for the validation. */
2830 if (constraint
[0] != 'p'
2831 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2832 && EXTRA_CONSTRAINT_STR (op
, constraint
[0], constraint
))
2836 /* There are three cases where the shape of *AD.INNER may now be invalid:
2838 1) the original address was valid, but either elimination or
2839 equiv_address_substitution was applied and that made
2840 the address invalid.
2842 2) the address is an invalid symbolic address created by
2845 3) the address is a frame address with an invalid offset.
2847 All these cases involve a non-autoinc address, so there is no
2848 point revalidating other types. */
2849 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2852 /* Any index existed before LRA started, so we can assume that the
2853 presence and shape of the index is valid. */
2854 push_to_sequence (*before
);
2855 lra_assert (ad
.disp
== ad
.disp_term
);
2856 if (ad
.base
== NULL
)
2858 if (ad
.index
== NULL
)
2861 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2863 rtx addr
= *ad
.inner
;
2865 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2869 rtx last
= get_last_insn ();
2871 /* addr => lo_sum (new_base, addr), case (2) above. */
2872 insn
= emit_insn (gen_rtx_SET
2874 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2875 code
= recog_memoized (insn
);
2878 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2879 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2881 /* Try to put lo_sum into register. */
2882 insn
= emit_insn (gen_rtx_SET
2884 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2885 code
= recog_memoized (insn
);
2888 *ad
.inner
= new_reg
;
2889 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2899 delete_insns_since (last
);
2904 /* addr => new_base, case (2) above. */
2905 lra_emit_move (new_reg
, addr
);
2906 *ad
.inner
= new_reg
;
2911 /* index * scale + disp => new base + index * scale,
2913 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2914 GET_CODE (*ad
.index
));
2916 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2917 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2918 lra_emit_move (new_reg
, *ad
.disp
);
2919 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2920 new_reg
, *ad
.index
);
2923 else if (ad
.index
== NULL
)
2927 rtx set
, insns
, last_insn
;
2928 /* base + disp => new base, cases (1) and (3) above. */
2929 /* Another option would be to reload the displacement into an
2930 index register. However, postreload has code to optimize
2931 address reloads that have the same base and different
2932 displacements, so reloading into an index register would
2933 not necessarily be a win. */
2935 new_reg
= base_plus_disp_to_reg (&ad
);
2936 insns
= get_insns ();
2937 last_insn
= get_last_insn ();
2938 /* If we generated at least two insns, try last insn source as
2939 an address. If we succeed, we generate one less insn. */
2940 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2941 && GET_CODE (SET_SRC (set
)) == PLUS
2942 && REG_P (XEXP (SET_SRC (set
), 0))
2943 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2945 *ad
.inner
= SET_SRC (set
);
2946 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2948 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2949 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2950 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2951 get_index_code (&ad
));
2952 regno
= REGNO (*ad
.base_term
);
2953 if (regno
>= FIRST_PSEUDO_REGISTER
2954 && cl
!= lra_get_allocno_class (regno
))
2955 lra_change_class (regno
, cl
, " Change to", true);
2956 new_reg
= SET_SRC (set
);
2957 delete_insns_since (PREV_INSN (last_insn
));
2962 *ad
.inner
= new_reg
;
2964 else if (ad
.disp_term
!= NULL
)
2966 /* base + scale * index + disp => new base + scale * index,
2968 new_reg
= base_plus_disp_to_reg (&ad
);
2969 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2970 new_reg
, *ad
.index
);
2974 /* base + scale * index => base + new_reg,
2976 Index part of address may become invalid. For example, we
2977 changed pseudo on the equivalent memory and a subreg of the
2978 pseudo onto the memory of different mode for which the scale is
2980 new_reg
= index_part_to_reg (&ad
);
2981 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2982 *ad
.base_term
, new_reg
);
2984 *before
= get_insns ();
2989 /* Emit insns to reload VALUE into a new register. VALUE is an
2990 auto-increment or auto-decrement RTX whose operand is a register or
2991 memory location; so reloading involves incrementing that location.
2992 IN is either identical to VALUE, or some cheaper place to reload
2993 value being incremented/decremented from.
2995 INC_AMOUNT is the number to increment or decrement by (always
2996 positive and ignored for POST_MODIFY/PRE_MODIFY).
2998 Return pseudo containing the result. */
3000 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3002 /* REG or MEM to be copied and incremented. */
3003 rtx incloc
= XEXP (value
, 0);
3004 /* Nonzero if increment after copying. */
3005 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3006 || GET_CODE (value
) == POST_MODIFY
);
3011 rtx real_in
= in
== value
? incloc
: in
;
3015 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3017 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3018 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3019 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3020 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3021 inc
= XEXP (XEXP (value
, 1), 1);
3025 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3026 inc_amount
= -inc_amount
;
3028 inc
= GEN_INT (inc_amount
);
3031 if (! post
&& REG_P (incloc
))
3034 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3037 if (real_in
!= result
)
3039 /* First copy the location to the result register. */
3040 lra_assert (REG_P (result
));
3041 emit_insn (gen_move_insn (result
, real_in
));
3044 /* We suppose that there are insns to add/sub with the constant
3045 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3046 old reload worked with this assumption. If the assumption
3047 becomes wrong, we should use approach in function
3048 base_plus_disp_to_reg. */
3051 /* See if we can directly increment INCLOC. */
3052 last
= get_last_insn ();
3053 add_insn
= emit_insn (plus_p
3054 ? gen_add2_insn (incloc
, inc
)
3055 : gen_sub2_insn (incloc
, inc
));
3057 code
= recog_memoized (add_insn
);
3060 if (! post
&& result
!= incloc
)
3061 emit_insn (gen_move_insn (result
, incloc
));
3064 delete_insns_since (last
);
3067 /* If couldn't do the increment directly, must increment in RESULT.
3068 The way we do this depends on whether this is pre- or
3069 post-increment. For pre-increment, copy INCLOC to the reload
3070 register, increment it there, then save back. */
3073 if (real_in
!= result
)
3074 emit_insn (gen_move_insn (result
, real_in
));
3076 emit_insn (gen_add2_insn (result
, inc
));
3078 emit_insn (gen_sub2_insn (result
, inc
));
3079 if (result
!= incloc
)
3080 emit_insn (gen_move_insn (incloc
, result
));
3086 Because this might be a jump insn or a compare, and because
3087 RESULT may not be available after the insn in an input
3088 reload, we must do the incrementing before the insn being
3091 We have already copied IN to RESULT. Increment the copy in
3092 RESULT, save that back, then decrement RESULT so it has
3093 the original value. */
3095 emit_insn (gen_add2_insn (result
, inc
));
3097 emit_insn (gen_sub2_insn (result
, inc
));
3098 emit_insn (gen_move_insn (incloc
, result
));
3099 /* Restore non-modified value for the result. We prefer this
3100 way because it does not require an additional hard
3104 if (CONST_INT_P (inc
))
3105 emit_insn (gen_add2_insn (result
,
3106 gen_int_mode (-INTVAL (inc
),
3107 GET_MODE (result
))));
3109 emit_insn (gen_sub2_insn (result
, inc
));
3112 emit_insn (gen_add2_insn (result
, inc
));
3117 /* Return true if the current move insn does not need processing as we
3118 already know that it satisfies its constraints. */
3120 simple_move_p (void)
3123 enum reg_class dclass
, sclass
;
3125 lra_assert (curr_insn_set
!= NULL_RTX
);
3126 dest
= SET_DEST (curr_insn_set
);
3127 src
= SET_SRC (curr_insn_set
);
3128 return ((dclass
= get_op_class (dest
)) != NO_REGS
3129 && (sclass
= get_op_class (src
)) != NO_REGS
3130 /* The backend guarantees that register moves of cost 2
3131 never need reloads. */
3132 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3135 /* Swap operands NOP and NOP + 1. */
3137 swap_operands (int nop
)
3139 enum machine_mode mode
= curr_operand_mode
[nop
];
3140 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3141 curr_operand_mode
[nop
+ 1] = mode
;
3142 rtx x
= *curr_id
->operand_loc
[nop
];
3143 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3144 *curr_id
->operand_loc
[nop
+ 1] = x
;
3145 /* Swap the duplicates too. */
3146 lra_update_dup (curr_id
, nop
);
3147 lra_update_dup (curr_id
, nop
+ 1);
3150 /* Main entry point of the constraint code: search the body of the
3151 current insn to choose the best alternative. It is mimicking insn
3152 alternative cost calculation model of former reload pass. That is
3153 because machine descriptions were written to use this model. This
3154 model can be changed in future. Make commutative operand exchange
3157 Return true if some RTL changes happened during function call. */
3159 curr_insn_transform (void)
3165 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3166 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3169 /* Flag that the insn has been changed through a transformation. */
3172 #ifdef SECONDARY_MEMORY_NEEDED
3175 int max_regno_before
;
3176 int reused_alternative_num
;
3178 curr_insn_set
= single_set (curr_insn
);
3179 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3182 no_input_reloads_p
= no_output_reloads_p
= false;
3183 goal_alt_number
= -1;
3184 change_p
= sec_mem_p
= false;
3185 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3186 reloads; neither are insns that SET cc0. Insns that use CC0 are
3187 not allowed to have any input reloads. */
3188 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3189 no_output_reloads_p
= true;
3192 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3193 no_input_reloads_p
= true;
3194 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3195 no_output_reloads_p
= true;
3198 n_operands
= curr_static_id
->n_operands
;
3199 n_alternatives
= curr_static_id
->n_alternatives
;
3201 /* Just return "no reloads" if insn has no operands with
3203 if (n_operands
== 0 || n_alternatives
== 0)
3206 max_regno_before
= max_reg_num ();
3208 for (i
= 0; i
< n_operands
; i
++)
3210 goal_alt_matched
[i
][0] = -1;
3211 goal_alt_matches
[i
] = -1;
3214 commutative
= curr_static_id
->commutative
;
3216 /* Now see what we need for pseudos that didn't get hard regs or got
3217 the wrong kind of hard reg. For this, we must consider all the
3218 operands together against the register constraints. */
3220 best_losers
= best_overall
= INT_MAX
;
3221 best_reload_sum
= 0;
3223 curr_swapped
= false;
3224 goal_alt_swapped
= false;
3226 /* Make equivalence substitution and memory subreg elimination
3227 before address processing because an address legitimacy can
3228 depend on memory mode. */
3229 for (i
= 0; i
< n_operands
; i
++)
3231 rtx op
= *curr_id
->operand_loc
[i
];
3232 rtx subst
, old
= op
;
3233 bool op_change_p
= false;
3235 if (GET_CODE (old
) == SUBREG
)
3236 old
= SUBREG_REG (old
);
3237 subst
= get_equiv_with_elimination (old
, curr_insn
);
3240 subst
= copy_rtx (subst
);
3241 lra_assert (REG_P (old
));
3242 if (GET_CODE (op
) == SUBREG
)
3243 SUBREG_REG (op
) = subst
;
3245 *curr_id
->operand_loc
[i
] = subst
;
3246 if (lra_dump_file
!= NULL
)
3248 fprintf (lra_dump_file
,
3249 "Changing pseudo %d in operand %i of insn %u on equiv ",
3250 REGNO (old
), i
, INSN_UID (curr_insn
));
3251 dump_value_slim (lra_dump_file
, subst
, 1);
3252 fprintf (lra_dump_file
, "\n");
3254 op_change_p
= change_p
= true;
3256 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3259 lra_update_dup (curr_id
, i
);
3263 /* Reload address registers and displacements. We do it before
3264 finding an alternative because of memory constraints. */
3265 before
= after
= NULL_RTX
;
3266 for (i
= 0; i
< n_operands
; i
++)
3267 if (! curr_static_id
->operand
[i
].is_operator
3268 && process_address (i
, &before
, &after
))
3271 lra_update_dup (curr_id
, i
);
3275 /* If we've changed the instruction then any alternative that
3276 we chose previously may no longer be valid. */
3277 lra_set_used_insn_alternative (curr_insn
, -1);
3279 if (curr_insn_set
!= NULL_RTX
3280 && check_and_process_move (&change_p
, &sec_mem_p
))
3285 reused_alternative_num
= curr_id
->used_insn_alternative
;
3286 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3287 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3288 reused_alternative_num
, INSN_UID (curr_insn
));
3290 if (process_alt_operands (reused_alternative_num
))
3293 /* If insn is commutative (it's safe to exchange a certain pair of
3294 operands) then we need to try each alternative twice, the second
3295 time matching those two operands as if we had exchanged them. To
3296 do this, really exchange them in operands.
3298 If we have just tried the alternatives the second time, return
3299 operands to normal and drop through. */
3301 if (reused_alternative_num
< 0 && commutative
>= 0)
3303 curr_swapped
= !curr_swapped
;
3306 swap_operands (commutative
);
3310 swap_operands (commutative
);
3313 if (! alt_p
&& ! sec_mem_p
)
3315 /* No alternative works with reloads?? */
3316 if (INSN_CODE (curr_insn
) >= 0)
3317 fatal_insn ("unable to generate reloads for:", curr_insn
);
3318 error_for_asm (curr_insn
,
3319 "inconsistent operand constraints in an %<asm%>");
3320 /* Avoid further trouble with this insn. */
3321 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3322 lra_invalidate_insn_data (curr_insn
);
3326 /* If the best alternative is with operands 1 and 2 swapped, swap
3327 them. Update the operand numbers of any reloads already
3330 if (goal_alt_swapped
)
3332 if (lra_dump_file
!= NULL
)
3333 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3334 INSN_UID (curr_insn
));
3336 /* Swap the duplicates too. */
3337 swap_operands (commutative
);
3341 #ifdef SECONDARY_MEMORY_NEEDED
3342 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3343 too conservatively. So we use the secondary memory only if there
3344 is no any alternative without reloads. */
3345 use_sec_mem_p
= false;
3347 use_sec_mem_p
= true;
3350 for (i
= 0; i
< n_operands
; i
++)
3351 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3353 use_sec_mem_p
= i
< n_operands
;
3358 rtx new_reg
, src
, dest
, rld
;
3359 enum machine_mode sec_mode
, rld_mode
;
3361 lra_assert (sec_mem_p
);
3362 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3363 && curr_static_id
->operand
[1].type
== OP_IN
);
3364 dest
= *curr_id
->operand_loc
[0];
3365 src
= *curr_id
->operand_loc
[1];
3366 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3368 rld_mode
= GET_MODE (rld
);
3369 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3370 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3372 sec_mode
= rld_mode
;
3374 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3375 NO_REGS
, "secondary");
3376 /* If the mode is changed, it should be wider. */
3377 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3378 if (sec_mode
!= rld_mode
)
3380 /* If the target says specifically to use another mode for
3381 secondary memory moves we can not reuse the original
3383 after
= emit_spill_move (false, new_reg
, dest
);
3384 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3385 "Inserting the sec. move");
3386 /* We may have non null BEFORE here (e.g. after address
3388 push_to_sequence (before
);
3389 before
= emit_spill_move (true, new_reg
, src
);
3391 before
= get_insns ();
3393 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3394 lra_set_insn_deleted (curr_insn
);
3396 else if (dest
== rld
)
3398 *curr_id
->operand_loc
[0] = new_reg
;
3399 after
= emit_spill_move (false, new_reg
, dest
);
3400 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3401 "Inserting the sec. move");
3405 *curr_id
->operand_loc
[1] = new_reg
;
3406 /* See comments above. */
3407 push_to_sequence (before
);
3408 before
= emit_spill_move (true, new_reg
, src
);
3410 before
= get_insns ();
3412 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3413 "Inserting the sec. move");
3415 lra_update_insn_regno_info (curr_insn
);
3420 lra_assert (goal_alt_number
>= 0);
3421 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3423 if (lra_dump_file
!= NULL
)
3427 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3428 goal_alt_number
, INSN_UID (curr_insn
));
3429 for (i
= 0; i
< n_operands
; i
++)
3431 p
= (curr_static_id
->operand_alternative
3432 [goal_alt_number
* n_operands
+ i
].constraint
);
3435 fprintf (lra_dump_file
, " (%d) ", i
);
3436 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3437 fputc (*p
, lra_dump_file
);
3439 if (INSN_CODE (curr_insn
) >= 0
3440 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3441 fprintf (lra_dump_file
, " {%s}", p
);
3442 if (curr_id
->sp_offset
!= 0)
3443 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3444 curr_id
->sp_offset
);
3445 fprintf (lra_dump_file
, "\n");
3448 /* Right now, for any pair of operands I and J that are required to
3449 match, with J < I, goal_alt_matches[I] is J. Add I to
3450 goal_alt_matched[J]. */
3452 for (i
= 0; i
< n_operands
; i
++)
3453 if ((j
= goal_alt_matches
[i
]) >= 0)
3455 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3457 /* We allow matching one output operand and several input
3460 || (curr_static_id
->operand
[j
].type
== OP_OUT
3461 && curr_static_id
->operand
[i
].type
== OP_IN
3462 && (curr_static_id
->operand
3463 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3464 goal_alt_matched
[j
][k
] = i
;
3465 goal_alt_matched
[j
][k
+ 1] = -1;
3468 for (i
= 0; i
< n_operands
; i
++)
3469 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3471 /* Any constants that aren't allowed and can't be reloaded into
3472 registers are here changed into memory references. */
3473 for (i
= 0; i
< n_operands
; i
++)
3474 if (goal_alt_win
[i
])
3477 enum reg_class new_class
;
3478 rtx reg
= *curr_id
->operand_loc
[i
];
3480 if (GET_CODE (reg
) == SUBREG
)
3481 reg
= SUBREG_REG (reg
);
3483 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3485 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3487 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3490 lra_change_class (regno
, new_class
, " Change to", true);
3496 const char *constraint
;
3498 rtx op
= *curr_id
->operand_loc
[i
];
3499 rtx subreg
= NULL_RTX
;
3500 enum machine_mode mode
= curr_operand_mode
[i
];
3502 if (GET_CODE (op
) == SUBREG
)
3505 op
= SUBREG_REG (op
);
3506 mode
= GET_MODE (op
);
3509 if (CONST_POOL_OK_P (mode
, op
)
3510 && ((targetm
.preferred_reload_class
3511 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3512 || no_input_reloads_p
))
3514 rtx tem
= force_const_mem (mode
, op
);
3517 if (subreg
!= NULL_RTX
)
3518 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3520 *curr_id
->operand_loc
[i
] = tem
;
3521 lra_update_dup (curr_id
, i
);
3522 process_address (i
, &before
, &after
);
3524 /* If the alternative accepts constant pool refs directly
3525 there will be no reload needed at all. */
3526 if (subreg
!= NULL_RTX
)
3528 /* Skip alternatives before the one requested. */
3529 constraint
= (curr_static_id
->operand_alternative
3530 [goal_alt_number
* n_operands
+ i
].constraint
);
3532 (c
= *constraint
) && c
!= ',' && c
!= '#';
3533 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3535 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3537 #ifdef EXTRA_CONSTRAINT_STR
3538 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3539 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3543 if (c
== '\0' || c
== ',' || c
== '#')
3546 goal_alt_win
[i
] = true;
3550 for (i
= 0; i
< n_operands
; i
++)
3553 bool optional_p
= false;
3555 rtx op
= *curr_id
->operand_loc
[i
];
3557 if (goal_alt_win
[i
])
3559 if (goal_alt
[i
] == NO_REGS
3561 /* When we assign NO_REGS it means that we will not
3562 assign a hard register to the scratch pseudo by
3563 assigment pass and the scratch pseudo will be
3564 spilled. Spilled scratch pseudos are transformed
3565 back to scratches at the LRA end. */
3566 && lra_former_scratch_operand_p (curr_insn
, i
))
3568 int regno
= REGNO (op
);
3569 lra_change_class (regno
, NO_REGS
, " Change to", true);
3570 if (lra_get_regno_hard_regno (regno
) >= 0)
3571 /* We don't have to mark all insn affected by the
3572 spilled pseudo as there is only one such insn, the
3574 reg_renumber
[regno
] = -1;
3576 /* We can do an optional reload. If the pseudo got a hard
3577 reg, we might improve the code through inheritance. If
3578 it does not get a hard register we coalesce memory/memory
3579 moves later. Ignore move insns to avoid cycling. */
3581 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3582 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3583 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3584 && regno
< new_regno_start
3585 && ! lra_former_scratch_p (regno
)
3586 && reg_renumber
[regno
] < 0
3587 && (curr_insn_set
== NULL_RTX
3588 || !((REG_P (SET_SRC (curr_insn_set
))
3589 || MEM_P (SET_SRC (curr_insn_set
))
3590 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3591 && (REG_P (SET_DEST (curr_insn_set
))
3592 || MEM_P (SET_DEST (curr_insn_set
))
3593 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3599 /* Operands that match previous ones have already been handled. */
3600 if (goal_alt_matches
[i
] >= 0)
3603 /* We should not have an operand with a non-offsettable address
3604 appearing where an offsettable address will do. It also may
3605 be a case when the address should be special in other words
3606 not a general one (e.g. it needs no index reg). */
3607 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3609 enum reg_class rclass
;
3610 rtx
*loc
= &XEXP (op
, 0);
3611 enum rtx_code code
= GET_CODE (*loc
);
3613 push_to_sequence (before
);
3614 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3616 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3617 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3618 /* This value does not matter for MODIFY. */
3619 GET_MODE_SIZE (GET_MODE (op
)));
3620 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3621 "offsetable address", &new_reg
))
3622 lra_emit_move (new_reg
, *loc
);
3623 before
= get_insns ();
3626 lra_update_dup (curr_id
, i
);
3628 else if (goal_alt_matched
[i
][0] == -1)
3630 enum machine_mode mode
;
3632 int hard_regno
, byte
;
3633 enum op_type type
= curr_static_id
->operand
[i
].type
;
3635 loc
= curr_id
->operand_loc
[i
];
3636 mode
= curr_operand_mode
[i
];
3637 if (GET_CODE (*loc
) == SUBREG
)
3639 reg
= SUBREG_REG (*loc
);
3640 byte
= SUBREG_BYTE (*loc
);
3642 /* Strict_low_part requires reload the register not
3643 the sub-register. */
3644 && (curr_static_id
->operand
[i
].strict_low
3645 || (GET_MODE_SIZE (mode
)
3646 <= GET_MODE_SIZE (GET_MODE (reg
))
3648 = get_try_hard_regno (REGNO (reg
))) >= 0
3649 && (simplify_subreg_regno
3651 GET_MODE (reg
), byte
, mode
) < 0)
3652 && (goal_alt
[i
] == NO_REGS
3653 || (simplify_subreg_regno
3654 (ira_class_hard_regs
[goal_alt
[i
]][0],
3655 GET_MODE (reg
), byte
, mode
) >= 0)))))
3657 loc
= &SUBREG_REG (*loc
);
3658 mode
= GET_MODE (*loc
);
3662 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3663 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3666 push_to_sequence (before
);
3667 lra_emit_move (new_reg
, old
);
3668 before
= get_insns ();
3673 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3676 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3678 after
= get_insns ();
3682 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3683 if (goal_alt_dont_inherit_ops
[j
] == i
)
3685 lra_set_regno_unique_value (REGNO (new_reg
));
3688 lra_update_dup (curr_id
, i
);
3690 else if (curr_static_id
->operand
[i
].type
== OP_IN
3691 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3694 /* generate reloads for input and matched outputs. */
3695 match_inputs
[0] = i
;
3696 match_inputs
[1] = -1;
3697 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3698 goal_alt
[i
], &before
, &after
);
3700 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3701 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3703 /* Generate reloads for output and matched inputs. */
3704 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3705 else if (curr_static_id
->operand
[i
].type
== OP_IN
3706 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3709 /* Generate reloads for matched inputs. */
3710 match_inputs
[0] = i
;
3711 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3712 match_inputs
[j
+ 1] = k
;
3713 match_inputs
[j
+ 1] = -1;
3714 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3717 /* We must generate code in any case when function
3718 process_alt_operands decides that it is possible. */
3722 lra_assert (REG_P (op
));
3724 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3725 if (GET_CODE (op
) == SUBREG
)
3726 op
= SUBREG_REG (op
);
3727 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3728 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3729 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3730 if (lra_dump_file
!= NULL
)
3731 fprintf (lra_dump_file
,
3732 " Making reload reg %d for reg %d optional\n",
3736 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3737 || max_regno_before
!= max_reg_num ())
3741 lra_update_operator_dups (curr_id
);
3742 /* Something changes -- process the insn. */
3743 lra_update_insn_regno_info (curr_insn
);
3745 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3749 /* Return true if X is in LIST. */
3751 in_list_p (rtx x
, rtx list
)
3753 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3754 if (XEXP (list
, 0) == x
)
3759 /* Return true if X contains an allocatable hard register (if
3760 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3762 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3768 code
= GET_CODE (x
);
3771 int regno
= REGNO (x
);
3772 HARD_REG_SET alloc_regs
;
3776 if (regno
>= FIRST_PSEUDO_REGISTER
)
3777 regno
= lra_get_regno_hard_regno (regno
);
3780 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3781 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3785 if (regno
< FIRST_PSEUDO_REGISTER
)
3789 return lra_get_regno_hard_regno (regno
) < 0;
3792 fmt
= GET_RTX_FORMAT (code
);
3793 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3797 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3800 else if (fmt
[i
] == 'E')
3802 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3803 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3810 /* Process all regs in location *LOC and change them on equivalent
3811 substitution. Return true if any change was done. */
3813 loc_equivalence_change_p (rtx
*loc
)
3815 rtx subst
, reg
, x
= *loc
;
3816 bool result
= false;
3817 enum rtx_code code
= GET_CODE (x
);
3823 reg
= SUBREG_REG (x
);
3824 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3825 && GET_MODE (subst
) == VOIDmode
)
3827 /* We cannot reload debug location. Simplify subreg here
3828 while we know the inner mode. */
3829 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3830 GET_MODE (reg
), SUBREG_BYTE (x
));
3834 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3840 /* Scan all the operand sub-expressions. */
3841 fmt
= GET_RTX_FORMAT (code
);
3842 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3845 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3846 else if (fmt
[i
] == 'E')
3847 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3849 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3854 /* Similar to loc_equivalence_change_p, but for use as
3855 simplify_replace_fn_rtx callback. DATA is insn for which the
3856 elimination is done. If it null we don't do the elimination. */
3858 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3863 rtx subst
= (data
== NULL
3864 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx
) data
));
3871 /* Maximum number of generated reload insns per an insn. It is for
3872 preventing this pass cycling in a bug case. */
3873 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3875 /* The current iteration number of this LRA pass. */
3876 int lra_constraint_iter
;
3878 /* The current iteration number of this LRA pass after the last spill
3880 int lra_constraint_iter_after_spill
;
3882 /* True if we substituted equiv which needs checking register
3883 allocation correctness because the equivalent value contains
3884 allocatable hard registers or when we restore multi-register
3886 bool lra_risky_transformations_p
;
3888 /* Return true if REGNO is referenced in more than one block. */
3890 multi_block_pseudo_p (int regno
)
3892 basic_block bb
= NULL
;
3896 if (regno
< FIRST_PSEUDO_REGISTER
)
3899 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3901 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3902 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3907 /* Return true if LIST contains a deleted insn. */
3909 contains_deleted_insn_p (rtx list
)
3911 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3912 if (NOTE_P (XEXP (list
, 0))
3913 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3918 /* Return true if X contains a pseudo dying in INSN. */
3920 dead_pseudo_p (rtx x
, rtx insn
)
3927 return (insn
!= NULL_RTX
3928 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3929 code
= GET_CODE (x
);
3930 fmt
= GET_RTX_FORMAT (code
);
3931 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3935 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3938 else if (fmt
[i
] == 'E')
3940 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3941 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3948 /* Return true if INSN contains a dying pseudo in INSN right hand
3951 insn_rhs_dead_pseudo_p (rtx insn
)
3953 rtx set
= single_set (insn
);
3955 gcc_assert (set
!= NULL
);
3956 return dead_pseudo_p (SET_SRC (set
), insn
);
3959 /* Return true if any init insn of REGNO contains a dying pseudo in
3960 insn right hand side. */
3962 init_insn_rhs_dead_pseudo_p (int regno
)
3964 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3969 return insn_rhs_dead_pseudo_p (insns
);
3970 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3971 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3976 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3977 reverse only if we have one init insn with given REGNO as a
3980 reverse_equiv_p (int regno
)
3984 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3986 if (! INSN_P (XEXP (insns
, 0))
3987 || XEXP (insns
, 1) != NULL_RTX
)
3989 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3991 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3994 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3995 call this function only for non-reverse equivalence. */
3997 contains_reloaded_insn_p (int regno
)
4000 rtx list
= ira_reg_equiv
[regno
].init_insns
;
4002 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4003 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
4004 || ! REG_P (SET_DEST (set
))
4005 || (int) REGNO (SET_DEST (set
)) != regno
)
4010 /* Entry function of LRA constraint pass. Return true if the
4011 constraint pass did change the code. */
4013 lra_constraints (bool first_p
)
4016 int i
, hard_regno
, new_insns_num
;
4017 unsigned int min_len
, new_min_len
, uid
;
4018 rtx set
, x
, reg
, dest_reg
;
4019 basic_block last_bb
;
4020 bitmap_head equiv_insn_bitmap
;
4023 lra_constraint_iter
++;
4024 if (lra_dump_file
!= NULL
)
4025 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4026 lra_constraint_iter
);
4027 lra_constraint_iter_after_spill
++;
4028 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
4030 ("Maximum number of LRA constraint passes is achieved (%d)\n",
4031 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
4033 lra_risky_transformations_p
= false;
4034 new_insn_uid_start
= get_max_uid ();
4035 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4036 /* Mark used hard regs for target stack size calulations. */
4037 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4038 if (lra_reg_info
[i
].nrefs
!= 0
4039 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4043 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4044 for (j
= 0; j
< nregs
; j
++)
4045 df_set_regs_ever_live (hard_regno
+ j
, true);
4047 /* Do elimination before the equivalence processing as we can spill
4048 some pseudos during elimination. */
4049 lra_eliminate (false, first_p
);
4050 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4051 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4052 if (lra_reg_info
[i
].nrefs
!= 0)
4054 ira_reg_equiv
[i
].profitable_p
= true;
4055 reg
= regno_reg_rtx
[i
];
4056 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4058 bool pseudo_p
= contains_reg_p (x
, false, false);
4060 /* After RTL transformation, we can not guarantee that
4061 pseudo in the substitution was not reloaded which might
4062 make equivalence invalid. For example, in reverse
4069 the memory address register was reloaded before the 2nd
4071 if ((! first_p
&& pseudo_p
)
4072 /* We don't use DF for compilation speed sake. So it
4073 is problematic to update live info when we use an
4074 equivalence containing pseudos in more than one
4076 || (pseudo_p
&& multi_block_pseudo_p (i
))
4077 /* If an init insn was deleted for some reason, cancel
4078 the equiv. We could update the equiv insns after
4079 transformations including an equiv insn deletion
4080 but it is not worthy as such cases are extremely
4082 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4083 /* If it is not a reverse equivalence, we check that a
4084 pseudo in rhs of the init insn is not dying in the
4085 insn. Otherwise, the live info at the beginning of
4086 the corresponding BB might be wrong after we
4087 removed the insn. When the equiv can be a
4088 constant, the right hand side of the init insn can
4090 || (! reverse_equiv_p (i
)
4091 && (init_insn_rhs_dead_pseudo_p (i
)
4092 /* If we reloaded the pseudo in an equivalence
4093 init insn, we can not remove the equiv init
4094 insns and the init insns might write into
4095 const memory in this case. */
4096 || contains_reloaded_insn_p (i
)))
4097 /* Prevent access beyond equivalent memory for
4098 paradoxical subregs. */
4100 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4101 > GET_MODE_SIZE (GET_MODE (x
)))))
4102 ira_reg_equiv
[i
].defined_p
= false;
4103 if (contains_reg_p (x
, false, true))
4104 ira_reg_equiv
[i
].profitable_p
= false;
4105 if (get_equiv (reg
) != reg
)
4106 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4109 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4111 /* We should add all insns containing pseudos which should be
4112 substituted by their equivalences. */
4113 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4114 lra_push_insn_by_uid (uid
);
4115 min_len
= lra_insn_stack_length ();
4119 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4121 curr_insn
= lra_pop_insn ();
4123 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4124 if (curr_bb
!= last_bb
)
4127 bb_reload_num
= lra_curr_reload_num
;
4129 if (min_len
> new_min_len
)
4131 min_len
= new_min_len
;
4134 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4136 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4137 MAX_RELOAD_INSNS_NUMBER
);
4139 if (DEBUG_INSN_P (curr_insn
))
4141 /* We need to check equivalence in debug insn and change
4142 pseudo to the equivalent value if necessary. */
4143 curr_id
= lra_get_insn_recog_data (curr_insn
);
4144 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4146 rtx old
= *curr_id
->operand_loc
[0];
4147 *curr_id
->operand_loc
[0]
4148 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4149 loc_equivalence_callback
, curr_insn
);
4150 if (old
!= *curr_id
->operand_loc
[0])
4152 lra_update_insn_regno_info (curr_insn
);
4157 else if (INSN_P (curr_insn
))
4159 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4161 dest_reg
= SET_DEST (set
);
4162 /* The equivalence pseudo could be set up as SUBREG in a
4163 case when it is a call restore insn in a mode
4164 different from the pseudo mode. */
4165 if (GET_CODE (dest_reg
) == SUBREG
)
4166 dest_reg
= SUBREG_REG (dest_reg
);
4167 if ((REG_P (dest_reg
)
4168 && (x
= get_equiv (dest_reg
)) != dest_reg
4169 /* Remove insns which set up a pseudo whose value
4170 can not be changed. Such insns might be not in
4171 init_insns because we don't update equiv data
4172 during insn transformations.
4174 As an example, let suppose that a pseudo got
4175 hard register and on the 1st pass was not
4176 changed to equivalent constant. We generate an
4177 additional insn setting up the pseudo because of
4178 secondary memory movement. Then the pseudo is
4179 spilled and we use the equiv constant. In this
4180 case we should remove the additional insn and
4181 this insn is not init_insns list. */
4182 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4183 /* Check that this is actually an insn setting
4184 up the equivalence. */
4185 || in_list_p (curr_insn
,
4187 [REGNO (dest_reg
)].init_insns
)))
4188 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4189 && in_list_p (curr_insn
,
4191 [REGNO (SET_SRC (set
))].init_insns
)))
4193 /* This is equiv init insn of pseudo which did not get a
4194 hard register -- remove the insn. */
4195 if (lra_dump_file
!= NULL
)
4197 fprintf (lra_dump_file
,
4198 " Removing equiv init insn %i (freq=%d)\n",
4199 INSN_UID (curr_insn
),
4200 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4201 dump_insn_slim (lra_dump_file
, curr_insn
);
4203 if (contains_reg_p (x
, true, false))
4204 lra_risky_transformations_p
= true;
4205 lra_set_insn_deleted (curr_insn
);
4209 curr_id
= lra_get_insn_recog_data (curr_insn
);
4210 curr_static_id
= curr_id
->insn_static_data
;
4211 init_curr_insn_input_reloads ();
4212 init_curr_operand_mode ();
4213 if (curr_insn_transform ())
4215 /* Check non-transformed insns too for equiv change as USE
4216 or CLOBBER don't need reloads but can contain pseudos
4217 being changed on their equivalences. */
4218 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4219 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4221 lra_update_insn_regno_info (curr_insn
);
4226 bitmap_clear (&equiv_insn_bitmap
);
4227 /* If we used a new hard regno, changed_p should be true because the
4228 hard reg is assigned to a new pseudo. */
4229 #ifdef ENABLE_CHECKING
4232 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4233 if (lra_reg_info
[i
].nrefs
!= 0
4234 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4236 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4238 for (j
= 0; j
< nregs
; j
++)
4239 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4246 /* Initiate the LRA constraint pass. It is done once per
4249 lra_constraints_init (void)
4253 /* Finalize the LRA constraint pass. It is done once per
4256 lra_constraints_finish (void)
4262 /* This page contains code to do inheritance/split
4265 /* Number of reloads passed so far in current EBB. */
4266 static int reloads_num
;
4268 /* Number of calls passed so far in current EBB. */
4269 static int calls_num
;
4271 /* Current reload pseudo check for validity of elements in
4273 static int curr_usage_insns_check
;
4275 /* Info about last usage of registers in EBB to do inheritance/split
4276 transformation. Inheritance transformation is done from a spilled
4277 pseudo and split transformations from a hard register or a pseudo
4278 assigned to a hard register. */
4281 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4282 value INSNS is valid. The insns is chain of optional debug insns
4283 and a finishing non-debug insn using the corresponding reg. The
4284 value is also used to mark the registers which are set up in the
4285 current insn. The negated insn uid is used for this. */
4287 /* Value of global reloads_num at the last insn in INSNS. */
4289 /* Value of global reloads_nums at the last insn in INSNS. */
4291 /* It can be true only for splitting. And it means that the restore
4292 insn should be put after insn given by the following member. */
4294 /* Next insns in the current EBB which use the original reg and the
4295 original reg value is not changed between the current insn and
4296 the next insns. In order words, e.g. for inheritance, if we need
4297 to use the original reg value again in the next insns we can try
4298 to use the value in a hard register from a reload insn of the
4303 /* Map: regno -> corresponding pseudo usage insns. */
4304 static struct usage_insns
*usage_insns
;
4307 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4309 usage_insns
[regno
].check
= curr_usage_insns_check
;
4310 usage_insns
[regno
].insns
= insn
;
4311 usage_insns
[regno
].reloads_num
= reloads_num
;
4312 usage_insns
[regno
].calls_num
= calls_num
;
4313 usage_insns
[regno
].after_p
= after_p
;
4316 /* The function is used to form list REGNO usages which consists of
4317 optional debug insns finished by a non-debug insn using REGNO.
4318 RELOADS_NUM is current number of reload insns processed so far. */
4320 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4322 rtx next_usage_insns
;
4324 if (usage_insns
[regno
].check
== curr_usage_insns_check
4325 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4326 && DEBUG_INSN_P (insn
))
4328 /* Check that we did not add the debug insn yet. */
4329 if (next_usage_insns
!= insn
4330 && (GET_CODE (next_usage_insns
) != INSN_LIST
4331 || XEXP (next_usage_insns
, 0) != insn
))
4332 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4335 else if (NONDEBUG_INSN_P (insn
))
4336 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4338 usage_insns
[regno
].check
= 0;
4341 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4342 register NEW_REG. Return true if any change was made. */
4344 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4347 bool result
= false;
4355 code
= GET_CODE (x
);
4356 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4358 enum machine_mode mode
= GET_MODE (*loc
);
4359 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4361 if (mode
!= inner_mode
)
4363 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4364 || ! SCALAR_INT_MODE_P (inner_mode
))
4365 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4367 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4373 /* Scan all the operand sub-expressions. */
4374 fmt
= GET_RTX_FORMAT (code
);
4375 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4379 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4382 else if (fmt
[i
] == 'E')
4384 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4385 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4392 /* Return first non-debug insn in list USAGE_INSNS. */
4394 skip_usage_debug_insns (rtx usage_insns
)
4398 /* Skip debug insns. */
4399 for (insn
= usage_insns
;
4400 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4401 insn
= XEXP (insn
, 1))
4406 /* Return true if we need secondary memory moves for insn in
4407 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4410 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4411 rtx usage_insns ATTRIBUTE_UNUSED
)
4413 #ifndef SECONDARY_MEMORY_NEEDED
4416 rtx insn
, set
, dest
;
4419 if (inher_cl
== ALL_REGS
4420 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4422 lra_assert (INSN_P (insn
));
4423 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4425 dest
= SET_DEST (set
);
4428 lra_assert (inher_cl
!= NO_REGS
);
4429 cl
= get_reg_class (REGNO (dest
));
4430 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4431 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4435 /* Registers involved in inheritance/split in the current EBB
4436 (inheritance/split pseudos and original registers). */
4437 static bitmap_head check_only_regs
;
4439 /* Do inheritance transformations for insn INSN, which defines (if
4440 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4441 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4442 form as the "insns" field of usage_insns. Return true if we
4443 succeed in such transformation.
4445 The transformations look like:
4448 ... p <- i (new insn)
4450 <- ... p ... <- ... i ...
4452 ... i <- p (new insn)
4453 <- ... p ... <- ... i ...
4455 <- ... p ... <- ... i ...
4456 where p is a spilled original pseudo and i is a new inheritance pseudo.
4459 The inheritance pseudo has the smallest class of two classes CL and
4460 class of ORIGINAL REGNO. */
4462 inherit_reload_reg (bool def_p
, int original_regno
,
4463 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4465 if (optimize_function_for_size_p (cfun
))
4468 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4469 rtx original_reg
= regno_reg_rtx
[original_regno
];
4470 rtx new_reg
, new_insns
, usage_insn
;
4472 lra_assert (! usage_insns
[original_regno
].after_p
);
4473 if (lra_dump_file
!= NULL
)
4474 fprintf (lra_dump_file
,
4475 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4476 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4478 if (lra_dump_file
!= NULL
)
4480 fprintf (lra_dump_file
,
4481 " Rejecting inheritance for %d "
4482 "because of disjoint classes %s and %s\n",
4483 original_regno
, reg_class_names
[cl
],
4484 reg_class_names
[rclass
]);
4485 fprintf (lra_dump_file
,
4486 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4490 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4491 /* We don't use a subset of two classes because it can be
4492 NO_REGS. This transformation is still profitable in most
4493 cases even if the classes are not intersected as register
4494 move is probably cheaper than a memory load. */
4495 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4497 if (lra_dump_file
!= NULL
)
4498 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4499 reg_class_names
[cl
], reg_class_names
[rclass
]);
4503 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4505 /* Reject inheritance resulting in secondary memory moves.
4506 Otherwise, there is a danger in LRA cycling. Also such
4507 transformation will be unprofitable. */
4508 if (lra_dump_file
!= NULL
)
4510 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4511 rtx set
= single_set (insn
);
4513 lra_assert (set
!= NULL_RTX
);
4515 rtx dest
= SET_DEST (set
);
4517 lra_assert (REG_P (dest
));
4518 fprintf (lra_dump_file
,
4519 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4520 "as secondary mem is needed\n",
4521 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4522 original_regno
, reg_class_names
[rclass
]);
4523 fprintf (lra_dump_file
,
4524 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4528 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4529 rclass
, "inheritance");
4532 lra_emit_move (original_reg
, new_reg
);
4534 lra_emit_move (new_reg
, original_reg
);
4535 new_insns
= get_insns ();
4537 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4539 if (lra_dump_file
!= NULL
)
4541 fprintf (lra_dump_file
,
4542 " Rejecting inheritance %d->%d "
4543 "as it results in 2 or more insns:\n",
4544 original_regno
, REGNO (new_reg
));
4545 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4546 fprintf (lra_dump_file
,
4547 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4551 substitute_pseudo (&insn
, original_regno
, new_reg
);
4552 lra_update_insn_regno_info (insn
);
4554 /* We now have a new usage insn for original regno. */
4555 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4556 if (lra_dump_file
!= NULL
)
4557 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4558 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4559 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4560 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4561 bitmap_set_bit (&check_only_regs
, original_regno
);
4562 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4564 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4565 "Add original<-inheritance");
4567 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4568 "Add inheritance<-original");
4569 while (next_usage_insns
!= NULL_RTX
)
4571 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4573 usage_insn
= next_usage_insns
;
4574 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4575 next_usage_insns
= NULL
;
4579 usage_insn
= XEXP (next_usage_insns
, 0);
4580 lra_assert (DEBUG_INSN_P (usage_insn
));
4581 next_usage_insns
= XEXP (next_usage_insns
, 1);
4583 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4584 lra_update_insn_regno_info (usage_insn
);
4585 if (lra_dump_file
!= NULL
)
4587 fprintf (lra_dump_file
,
4588 " Inheritance reuse change %d->%d (bb%d):\n",
4589 original_regno
, REGNO (new_reg
),
4590 BLOCK_FOR_INSN (usage_insn
)->index
);
4591 dump_insn_slim (lra_dump_file
, usage_insn
);
4594 if (lra_dump_file
!= NULL
)
4595 fprintf (lra_dump_file
,
4596 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4600 /* Return true if we need a caller save/restore for pseudo REGNO which
4601 was assigned to a hard register. */
4603 need_for_call_save_p (int regno
)
4605 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4606 return (usage_insns
[regno
].calls_num
< calls_num
4607 && (overlaps_hard_reg_set_p
4609 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4610 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4611 PSEUDO_REGNO_MODE (regno
))));
4614 /* Global registers occurring in the current EBB. */
4615 static bitmap_head ebb_global_regs
;
4617 /* Return true if we need a split for hard register REGNO or pseudo
4618 REGNO which was assigned to a hard register.
4619 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4620 used for reloads since the EBB end. It is an approximation of the
4621 used hard registers in the split range. The exact value would
4622 require expensive calculations. If we were aggressive with
4623 splitting because of the approximation, the split pseudo will save
4624 the same hard register assignment and will be removed in the undo
4625 pass. We still need the approximation because too aggressive
4626 splitting would result in too inaccurate cost calculation in the
4627 assignment pass because of too many generated moves which will be
4628 probably removed in the undo pass. */
4630 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4632 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4634 lra_assert (hard_regno
>= 0);
4635 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4636 /* Don't split eliminable hard registers, otherwise we can
4637 split hard registers like hard frame pointer, which
4638 lives on BB start/end according to DF-infrastructure,
4639 when there is a pseudo assigned to the register and
4640 living in the same BB. */
4641 && (regno
>= FIRST_PSEUDO_REGISTER
4642 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4643 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4644 /* Don't split call clobbered hard regs living through
4645 calls, otherwise we might have a check problem in the
4646 assign sub-pass as in the most cases (exception is a
4647 situation when lra_risky_transformations_p value is
4648 true) the assign pass assumes that all pseudos living
4649 through calls are assigned to call saved hard regs. */
4650 && (regno
>= FIRST_PSEUDO_REGISTER
4651 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4652 || usage_insns
[regno
].calls_num
== calls_num
)
4653 /* We need at least 2 reloads to make pseudo splitting
4654 profitable. We should provide hard regno splitting in
4655 any case to solve 1st insn scheduling problem when
4656 moving hard register definition up might result in
4657 impossibility to find hard register for reload pseudo of
4658 small register class. */
4659 && (usage_insns
[regno
].reloads_num
4660 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4661 && (regno
< FIRST_PSEUDO_REGISTER
4662 /* For short living pseudos, spilling + inheritance can
4663 be considered a substitution for splitting.
4664 Therefore we do not splitting for local pseudos. It
4665 decreases also aggressiveness of splitting. The
4666 minimal number of references is chosen taking into
4667 account that for 2 references splitting has no sense
4668 as we can just spill the pseudo. */
4669 || (regno
>= FIRST_PSEUDO_REGISTER
4670 && lra_reg_info
[regno
].nrefs
> 3
4671 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4672 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4675 /* Return class for the split pseudo created from original pseudo with
4676 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4677 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4678 results in no secondary memory movements. */
4679 static enum reg_class
4680 choose_split_class (enum reg_class allocno_class
,
4681 int hard_regno ATTRIBUTE_UNUSED
,
4682 enum machine_mode mode ATTRIBUTE_UNUSED
)
4684 #ifndef SECONDARY_MEMORY_NEEDED
4685 return allocno_class
;
4688 enum reg_class cl
, best_cl
= NO_REGS
;
4689 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4690 = REGNO_REG_CLASS (hard_regno
);
4692 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4693 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4694 return allocno_class
;
4696 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4698 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4699 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4700 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4701 && (best_cl
== NO_REGS
4702 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4708 /* Do split transformations for insn INSN, which defines or uses
4709 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4710 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4711 "insns" field of usage_insns.
4713 The transformations look like:
4716 ... s <- p (new insn -- save)
4718 ... p <- s (new insn -- restore)
4719 <- ... p ... <- ... p ...
4721 <- ... p ... <- ... p ...
4722 ... s <- p (new insn -- save)
4724 ... p <- s (new insn -- restore)
4725 <- ... p ... <- ... p ...
4727 where p is an original pseudo got a hard register or a hard
4728 register and s is a new split pseudo. The save is put before INSN
4729 if BEFORE_P is true. Return true if we succeed in such
4732 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4734 enum reg_class rclass
;
4736 int hard_regno
, nregs
;
4737 rtx new_reg
, save
, restore
, usage_insn
;
4741 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4743 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4744 hard_regno
= original_regno
;
4745 call_save_p
= false;
4750 hard_regno
= reg_renumber
[original_regno
];
4751 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4752 rclass
= lra_get_allocno_class (original_regno
);
4753 original_reg
= regno_reg_rtx
[original_regno
];
4754 call_save_p
= need_for_call_save_p (original_regno
);
4756 original_reg
= regno_reg_rtx
[original_regno
];
4757 lra_assert (hard_regno
>= 0);
4758 if (lra_dump_file
!= NULL
)
4759 fprintf (lra_dump_file
,
4760 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4763 enum machine_mode mode
= GET_MODE (original_reg
);
4765 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4766 hard_regno_nregs
[hard_regno
][mode
],
4768 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4772 rclass
= choose_split_class (rclass
, hard_regno
,
4773 GET_MODE (original_reg
));
4774 if (rclass
== NO_REGS
)
4776 if (lra_dump_file
!= NULL
)
4778 fprintf (lra_dump_file
,
4779 " Rejecting split of %d(%s): "
4780 "no good reg class for %d(%s)\n",
4782 reg_class_names
[lra_get_allocno_class (original_regno
)],
4784 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4787 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4791 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4793 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4795 save
= emit_spill_move (true, new_reg
, original_reg
);
4796 if (NEXT_INSN (save
) != NULL_RTX
)
4798 lra_assert (! call_save_p
);
4799 if (lra_dump_file
!= NULL
)
4803 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4804 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4805 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4806 fprintf (lra_dump_file
,
4807 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4811 restore
= emit_spill_move (false, new_reg
, original_reg
);
4812 if (NEXT_INSN (restore
) != NULL_RTX
)
4814 lra_assert (! call_save_p
);
4815 if (lra_dump_file
!= NULL
)
4817 fprintf (lra_dump_file
,
4818 " Rejecting split %d->%d "
4819 "resulting in > 2 %s restore insns:\n",
4820 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4821 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4822 fprintf (lra_dump_file
,
4823 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4827 after_p
= usage_insns
[original_regno
].after_p
;
4828 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4829 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4830 bitmap_set_bit (&check_only_regs
, original_regno
);
4831 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4834 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4836 usage_insn
= next_usage_insns
;
4839 usage_insn
= XEXP (next_usage_insns
, 0);
4840 lra_assert (DEBUG_INSN_P (usage_insn
));
4841 next_usage_insns
= XEXP (next_usage_insns
, 1);
4842 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4843 lra_update_insn_regno_info (usage_insn
);
4844 if (lra_dump_file
!= NULL
)
4846 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4847 original_regno
, REGNO (new_reg
));
4848 dump_insn_slim (lra_dump_file
, usage_insn
);
4851 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4852 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4853 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4854 after_p
? restore
: NULL_RTX
,
4856 ? "Add reg<-save" : "Add reg<-split");
4857 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4858 before_p
? NULL_RTX
: save
,
4860 ? "Add save<-reg" : "Add split<-reg");
4862 /* If we are trying to split multi-register. We should check
4863 conflicts on the next assignment sub-pass. IRA can allocate on
4864 sub-register levels, LRA do this on pseudos level right now and
4865 this discrepancy may create allocation conflicts after
4867 lra_risky_transformations_p
= true;
4868 if (lra_dump_file
!= NULL
)
4869 fprintf (lra_dump_file
,
4870 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4874 /* Recognize that we need a split transformation for insn INSN, which
4875 defines or uses REGNO in its insn biggest MODE (we use it only if
4876 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4877 hard registers which might be used for reloads since the EBB end.
4878 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4879 uid before starting INSN processing. Return true if we succeed in
4880 such transformation. */
4882 split_if_necessary (int regno
, enum machine_mode mode
,
4883 HARD_REG_SET potential_reload_hard_regs
,
4884 bool before_p
, rtx insn
, int max_uid
)
4888 rtx next_usage_insns
;
4890 if (regno
< FIRST_PSEUDO_REGISTER
)
4891 nregs
= hard_regno_nregs
[regno
][mode
];
4892 for (i
= 0; i
< nregs
; i
++)
4893 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4894 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4895 /* To avoid processing the register twice or more. */
4896 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4897 && INSN_UID (next_usage_insns
) < max_uid
)
4898 || (GET_CODE (next_usage_insns
) == INSN_LIST
4899 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4900 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4901 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4906 /* Check only registers living at the current program point in the
4908 static bitmap_head live_regs
;
4910 /* Update live info in EBB given by its HEAD and TAIL insns after
4911 inheritance/split transformation. The function removes dead moves
4914 update_ebb_live_info (rtx head
, rtx tail
)
4921 basic_block last_bb
, prev_bb
, curr_bb
;
4923 struct lra_insn_reg
*reg
;
4927 last_bb
= BLOCK_FOR_INSN (tail
);
4929 for (curr_insn
= tail
;
4930 curr_insn
!= PREV_INSN (head
);
4931 curr_insn
= prev_insn
)
4933 prev_insn
= PREV_INSN (curr_insn
);
4934 /* We need to process empty blocks too. They contain
4935 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4936 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4938 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4939 if (curr_bb
!= prev_bb
)
4941 if (prev_bb
!= NULL
)
4943 /* Update df_get_live_in (prev_bb): */
4944 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4945 if (bitmap_bit_p (&live_regs
, j
))
4946 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4948 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4950 if (curr_bb
!= last_bb
)
4952 /* Update df_get_live_out (curr_bb): */
4953 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4955 live_p
= bitmap_bit_p (&live_regs
, j
);
4957 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4958 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4964 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4966 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4970 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4972 if (! NONDEBUG_INSN_P (curr_insn
))
4974 curr_id
= lra_get_insn_recog_data (curr_insn
);
4975 curr_static_id
= curr_id
->insn_static_data
;
4977 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4978 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4979 && bitmap_bit_p (&check_only_regs
, regno
)
4980 && ! bitmap_bit_p (&live_regs
, regno
))
4982 /* See which defined values die here. */
4983 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4984 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4985 bitmap_clear_bit (&live_regs
, reg
->regno
);
4986 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
4987 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4988 bitmap_clear_bit (&live_regs
, reg
->regno
);
4989 /* Mark each used value as live. */
4990 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4991 if (reg
->type
!= OP_OUT
4992 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4993 bitmap_set_bit (&live_regs
, reg
->regno
);
4994 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
4995 if (reg
->type
!= OP_OUT
4996 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4997 bitmap_set_bit (&live_regs
, reg
->regno
);
4998 if (curr_id
->arg_hard_regs
!= NULL
)
4999 /* Make argument hard registers live. */
5000 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5001 if (bitmap_bit_p (&check_only_regs
, regno
))
5002 bitmap_set_bit (&live_regs
, regno
);
5003 /* It is quite important to remove dead move insns because it
5004 means removing dead store. We don't need to process them for
5008 if (lra_dump_file
!= NULL
)
5010 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5011 dump_insn_slim (lra_dump_file
, curr_insn
);
5013 lra_set_insn_deleted (curr_insn
);
5018 /* The structure describes info to do an inheritance for the current
5019 insn. We need to collect such info first before doing the
5020 transformations because the transformations change the insn
5021 internal representation. */
5024 /* Original regno. */
5026 /* Subsequent insns which can inherit original reg value. */
5030 /* Array containing all info for doing inheritance from the current
5032 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5034 /* Number elements in the previous array. */
5035 static int to_inherit_num
;
5037 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5038 structure to_inherit. */
5040 add_to_inherit (int regno
, rtx insns
)
5044 for (i
= 0; i
< to_inherit_num
; i
++)
5045 if (to_inherit
[i
].regno
== regno
)
5047 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5048 to_inherit
[to_inherit_num
].regno
= regno
;
5049 to_inherit
[to_inherit_num
++].insns
= insns
;
5052 /* Return the last non-debug insn in basic block BB, or the block begin
5055 get_last_insertion_point (basic_block bb
)
5059 FOR_BB_INSNS_REVERSE (bb
, insn
)
5060 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5065 /* Set up RES by registers living on edges FROM except the edge (FROM,
5066 TO) or by registers set up in a jump insn in BB FROM. */
5068 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5071 struct lra_insn_reg
*reg
;
5075 lra_assert (to
!= NULL
);
5077 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5079 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5080 last
= get_last_insertion_point (from
);
5081 if (! JUMP_P (last
))
5083 curr_id
= lra_get_insn_recog_data (last
);
5084 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5085 if (reg
->type
!= OP_IN
)
5086 bitmap_set_bit (res
, reg
->regno
);
5089 /* Used as a temporary results of some bitmap calculations. */
5090 static bitmap_head temp_bitmap
;
5092 /* We split for reloads of small class of hard regs. The following
5093 defines how many hard regs the class should have to be qualified as
5094 small. The code is mostly oriented to x86/x86-64 architecture
5095 where some insns need to use only specific register or pair of
5096 registers and these register can live in RTL explicitly, e.g. for
5097 parameter passing. */
5098 static const int max_small_class_regs_num
= 2;
5100 /* Do inheritance/split transformations in EBB starting with HEAD and
5101 finishing on TAIL. We process EBB insns in the reverse order.
5102 Return true if we did any inheritance/split transformation in the
5105 We should avoid excessive splitting which results in worse code
5106 because of inaccurate cost calculations for spilling new split
5107 pseudos in such case. To achieve this we do splitting only if
5108 register pressure is high in given basic block and there are reload
5109 pseudos requiring hard registers. We could do more register
5110 pressure calculations at any given program point to avoid necessary
5111 splitting even more but it is to expensive and the current approach
5112 works well enough. */
5114 inherit_in_ebb (rtx head
, rtx tail
)
5116 int i
, src_regno
, dst_regno
, nregs
;
5117 bool change_p
, succ_p
, update_reloads_num_p
;
5118 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
5120 struct lra_insn_reg
*reg
;
5121 basic_block last_processed_bb
, curr_bb
= NULL
;
5122 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5126 bool head_p
, after_p
;
5129 curr_usage_insns_check
++;
5130 reloads_num
= calls_num
= 0;
5131 bitmap_clear (&check_only_regs
);
5132 last_processed_bb
= NULL
;
5133 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5134 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5135 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5136 /* We don't process new insns generated in the loop. */
5137 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5139 prev_insn
= PREV_INSN (curr_insn
);
5140 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5141 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5142 if (last_processed_bb
!= curr_bb
)
5144 /* We are at the end of BB. Add qualified living
5145 pseudos for potential splitting. */
5146 to_process
= df_get_live_out (curr_bb
);
5147 if (last_processed_bb
!= NULL
)
5149 /* We are somewhere in the middle of EBB. */
5150 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5152 to_process
= &temp_bitmap
;
5154 last_processed_bb
= curr_bb
;
5155 last_insn
= get_last_insertion_point (curr_bb
);
5156 after_p
= (! JUMP_P (last_insn
)
5157 && (! CALL_P (last_insn
)
5158 || (find_reg_note (last_insn
,
5159 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5160 && ! SIBLING_CALL_P (last_insn
))));
5161 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5162 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5164 if ((int) j
>= lra_constraint_new_regno_start
)
5166 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5168 if (j
< FIRST_PSEUDO_REGISTER
)
5169 SET_HARD_REG_BIT (live_hard_regs
, j
);
5171 add_to_hard_reg_set (&live_hard_regs
,
5172 PSEUDO_REGNO_MODE (j
),
5174 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5178 src_regno
= dst_regno
= -1;
5179 if (NONDEBUG_INSN_P (curr_insn
)
5180 && (set
= single_set (curr_insn
)) != NULL_RTX
5181 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5183 src_regno
= REGNO (SET_SRC (set
));
5184 dst_regno
= REGNO (SET_DEST (set
));
5186 update_reloads_num_p
= true;
5187 if (src_regno
< lra_constraint_new_regno_start
5188 && src_regno
>= FIRST_PSEUDO_REGISTER
5189 && reg_renumber
[src_regno
] < 0
5190 && dst_regno
>= lra_constraint_new_regno_start
5191 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5193 /* 'reload_pseudo <- original_pseudo'. */
5194 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5196 update_reloads_num_p
= false;
5198 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5199 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5200 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5201 curr_insn
, next_usage_insns
);
5205 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5206 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5207 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5208 reg_class_contents
[cl
]);
5210 else if (src_regno
>= lra_constraint_new_regno_start
5211 && dst_regno
< lra_constraint_new_regno_start
5212 && dst_regno
>= FIRST_PSEUDO_REGISTER
5213 && reg_renumber
[dst_regno
] < 0
5214 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5215 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5216 && (next_usage_insns
5217 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5219 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5221 update_reloads_num_p
= false;
5222 /* 'original_pseudo <- reload_pseudo'. */
5223 if (! JUMP_P (curr_insn
)
5224 && inherit_reload_reg (true, dst_regno
, cl
,
5225 curr_insn
, next_usage_insns
))
5228 usage_insns
[dst_regno
].check
= 0;
5229 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5230 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5231 reg_class_contents
[cl
]);
5233 else if (INSN_P (curr_insn
))
5236 int max_uid
= get_max_uid ();
5238 curr_id
= lra_get_insn_recog_data (curr_insn
);
5239 curr_static_id
= curr_id
->insn_static_data
;
5241 /* Process insn definitions. */
5242 for (iter
= 0; iter
< 2; iter
++)
5243 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5246 if (reg
->type
!= OP_IN
5247 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5249 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5250 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5251 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5252 && (next_usage_insns
5253 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5255 struct lra_insn_reg
*r
;
5257 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5258 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5260 /* Don't do inheritance if the pseudo is also
5261 used in the insn. */
5263 /* We can not do inheritance right now
5264 because the current insn reg info (chain
5265 regs) can change after that. */
5266 add_to_inherit (dst_regno
, next_usage_insns
);
5268 /* We can not process one reg twice here because of
5269 usage_insns invalidation. */
5270 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5271 || reg_renumber
[dst_regno
] >= 0)
5272 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5276 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5277 potential_reload_hard_regs
,
5278 false, curr_insn
, max_uid
))
5280 CLEAR_HARD_REG_SET (s
);
5281 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5282 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5284 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5285 reg_renumber
[dst_regno
]);
5286 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5288 /* We should invalidate potential inheritance or
5289 splitting for the current insn usages to the next
5290 usage insns (see code below) as the output pseudo
5292 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5293 && reg_renumber
[dst_regno
] < 0)
5294 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5295 && (dst_regno
< FIRST_PSEUDO_REGISTER
5296 || reg_renumber
[dst_regno
] >= 0)))
5298 /* Invalidate and mark definitions. */
5299 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5300 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5303 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5304 for (i
= 0; i
< nregs
; i
++)
5305 usage_insns
[dst_regno
+ i
].check
5306 = -(int) INSN_UID (curr_insn
);
5310 if (! JUMP_P (curr_insn
))
5311 for (i
= 0; i
< to_inherit_num
; i
++)
5312 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5313 ALL_REGS
, curr_insn
,
5314 to_inherit
[i
].insns
))
5316 if (CALL_P (curr_insn
))
5318 rtx cheap
, pat
, dest
, restore
;
5319 int regno
, hard_regno
;
5322 if ((cheap
= find_reg_note (curr_insn
,
5323 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5324 && ((cheap
= XEXP (cheap
, 0)), true)
5325 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5326 && (hard_regno
= reg_renumber
[regno
]) >= 0
5327 /* If there are pending saves/restores, the
5328 optimization is not worth. */
5329 && usage_insns
[regno
].calls_num
== calls_num
- 1
5330 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5332 /* Restore the pseudo from the call result as
5333 REG_RETURNED note says that the pseudo value is
5334 in the call result and the pseudo is an argument
5336 pat
= PATTERN (curr_insn
);
5337 if (GET_CODE (pat
) == PARALLEL
)
5338 pat
= XVECEXP (pat
, 0, 0);
5339 dest
= SET_DEST (pat
);
5341 emit_move_insn (cheap
, copy_rtx (dest
));
5342 restore
= get_insns ();
5344 lra_process_new_insns (curr_insn
, NULL
, restore
,
5345 "Inserting call parameter restore");
5346 /* We don't need to save/restore of the pseudo from
5348 usage_insns
[regno
].calls_num
= calls_num
;
5349 bitmap_set_bit (&check_only_regs
, regno
);
5353 /* Process insn usages. */
5354 for (iter
= 0; iter
< 2; iter
++)
5355 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5358 if ((reg
->type
!= OP_OUT
5359 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5360 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5362 if (src_regno
>= FIRST_PSEUDO_REGISTER
5363 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5365 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5366 && (next_usage_insns
5367 = usage_insns
[src_regno
].insns
) != NULL_RTX
5368 && NONDEBUG_INSN_P (curr_insn
))
5369 add_to_inherit (src_regno
, next_usage_insns
);
5370 else if (usage_insns
[src_regno
].check
5371 != -(int) INSN_UID (curr_insn
))
5372 /* Add usages but only if the reg is not set up
5373 in the same insn. */
5374 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5376 else if (src_regno
< FIRST_PSEUDO_REGISTER
5377 || reg_renumber
[src_regno
] >= 0)
5380 rtx use_insn
= curr_insn
;
5382 before_p
= (JUMP_P (curr_insn
)
5383 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5384 if (NONDEBUG_INSN_P (curr_insn
)
5385 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5386 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5387 potential_reload_hard_regs
,
5388 before_p
, curr_insn
, max_uid
))
5391 lra_risky_transformations_p
= true;
5394 usage_insns
[src_regno
].check
= 0;
5396 use_insn
= PREV_INSN (curr_insn
);
5398 if (NONDEBUG_INSN_P (curr_insn
))
5400 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5401 add_to_hard_reg_set (&live_hard_regs
,
5402 reg
->biggest_mode
, src_regno
);
5404 add_to_hard_reg_set (&live_hard_regs
,
5405 PSEUDO_REGNO_MODE (src_regno
),
5406 reg_renumber
[src_regno
]);
5408 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5411 /* Process call args. */
5412 if (curr_id
->arg_hard_regs
!= NULL
)
5413 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5414 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5416 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5417 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5419 for (i
= 0; i
< to_inherit_num
; i
++)
5421 src_regno
= to_inherit
[i
].regno
;
5422 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5423 curr_insn
, to_inherit
[i
].insns
))
5426 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5429 if (update_reloads_num_p
5430 && NONDEBUG_INSN_P (curr_insn
)
5431 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5434 if ((REG_P (SET_DEST (set
))
5435 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5436 && reg_renumber
[regno
] < 0
5437 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5438 || (REG_P (SET_SRC (set
))
5439 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5440 && reg_renumber
[regno
] < 0
5441 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5443 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5445 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5446 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5447 reg_class_contents
[cl
]);
5450 /* We reached the start of the current basic block. */
5451 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5452 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5454 /* We reached the beginning of the current block -- do
5455 rest of spliting in the current BB. */
5456 to_process
= df_get_live_in (curr_bb
);
5457 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5459 /* We are somewhere in the middle of EBB. */
5460 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5461 curr_bb
, &temp_bitmap
);
5462 to_process
= &temp_bitmap
;
5465 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5467 if ((int) j
>= lra_constraint_new_regno_start
)
5469 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5470 && usage_insns
[j
].check
== curr_usage_insns_check
5471 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5473 if (need_for_split_p (potential_reload_hard_regs
, j
))
5475 if (lra_dump_file
!= NULL
&& head_p
)
5477 fprintf (lra_dump_file
,
5478 " ----------------------------------\n");
5481 if (split_reg (false, j
, bb_note (curr_bb
),
5485 usage_insns
[j
].check
= 0;
5493 /* This value affects EBB forming. If probability of edge from EBB to
5494 a BB is not greater than the following value, we don't add the BB
5496 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5498 /* Current number of inheritance/split iteration. */
5499 int lra_inheritance_iter
;
5501 /* Entry function for inheritance/split pass. */
5503 lra_inheritance (void)
5506 basic_block bb
, start_bb
;
5509 lra_inheritance_iter
++;
5510 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5512 timevar_push (TV_LRA_INHERITANCE
);
5513 if (lra_dump_file
!= NULL
)
5514 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5515 lra_inheritance_iter
);
5516 curr_usage_insns_check
= 0;
5517 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5518 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5519 usage_insns
[i
].check
= 0;
5520 bitmap_initialize (&check_only_regs
, ®_obstack
);
5521 bitmap_initialize (&live_regs
, ®_obstack
);
5522 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5523 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5524 FOR_EACH_BB_FN (bb
, cfun
)
5527 if (lra_dump_file
!= NULL
)
5528 fprintf (lra_dump_file
, "EBB");
5529 /* Form a EBB starting with BB. */
5530 bitmap_clear (&ebb_global_regs
);
5531 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5534 if (lra_dump_file
!= NULL
)
5535 fprintf (lra_dump_file
, " %d", bb
->index
);
5536 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5537 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5539 e
= find_fallthru_edge (bb
->succs
);
5542 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5546 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5547 if (lra_dump_file
!= NULL
)
5548 fprintf (lra_dump_file
, "\n");
5549 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5550 /* Remember that the EBB head and tail can change in
5552 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5554 bitmap_clear (&ebb_global_regs
);
5555 bitmap_clear (&temp_bitmap
);
5556 bitmap_clear (&live_regs
);
5557 bitmap_clear (&check_only_regs
);
5560 timevar_pop (TV_LRA_INHERITANCE
);
5565 /* This page contains code to undo failed inheritance/split
5568 /* Current number of iteration undoing inheritance/split. */
5569 int lra_undo_inheritance_iter
;
5571 /* Fix BB live info LIVE after removing pseudos created on pass doing
5572 inheritance/split which are REMOVED_PSEUDOS. */
5574 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5579 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5580 if (bitmap_clear_bit (live
, regno
))
5581 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5584 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5589 if (GET_CODE (reg
) == SUBREG
)
5590 reg
= SUBREG_REG (reg
);
5596 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5597 return true if we did any change. The undo transformations for
5598 inheritance looks like
5602 p <- i, i <- p, and i <- i3
5603 where p is original pseudo from which inheritance pseudo i was
5604 created, i and i3 are removed inheritance pseudos, i2 is another
5605 not removed inheritance pseudo. All split pseudos or other
5606 occurrences of removed inheritance pseudos are changed on the
5607 corresponding original pseudos.
5609 The function also schedules insns changed and created during
5610 inheritance/split pass for processing by the subsequent constraint
5613 remove_inheritance_pseudos (bitmap remove_pseudos
)
5616 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5617 rtx set
, prev_set
, prev_insn
;
5618 bool change_p
, done_p
;
5620 change_p
= ! bitmap_empty_p (remove_pseudos
);
5621 /* We can not finish the function right away if CHANGE_P is true
5622 because we need to marks insns affected by previous
5623 inheritance/split pass for processing by the subsequent
5625 FOR_EACH_BB_FN (bb
, cfun
)
5627 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5628 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5629 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5631 if (! INSN_P (curr_insn
))
5634 sregno
= dregno
= -1;
5635 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5636 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5638 dregno
= get_regno (SET_DEST (set
));
5639 sregno
= get_regno (SET_SRC (set
));
5642 if (sregno
>= 0 && dregno
>= 0)
5644 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5645 && (lra_reg_info
[sregno
].restore_regno
== dregno
5646 || (bitmap_bit_p (remove_pseudos
, dregno
)
5647 && (lra_reg_info
[sregno
].restore_regno
5648 == lra_reg_info
[dregno
].restore_regno
))))
5649 || (bitmap_bit_p (remove_pseudos
, dregno
)
5650 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5651 /* One of the following cases:
5652 original <- removed inheritance pseudo
5653 removed inherit pseudo <- another removed inherit pseudo
5654 removed inherit pseudo <- original pseudo
5656 removed_split_pseudo <- original_reg
5657 original_reg <- removed_split_pseudo */
5659 if (lra_dump_file
!= NULL
)
5661 fprintf (lra_dump_file
, " Removing %s:\n",
5662 bitmap_bit_p (&lra_split_regs
, sregno
)
5663 || bitmap_bit_p (&lra_split_regs
, dregno
)
5664 ? "split" : "inheritance");
5665 dump_insn_slim (lra_dump_file
, curr_insn
);
5667 lra_set_insn_deleted (curr_insn
);
5670 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5671 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5673 /* Search the following pattern:
5674 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5675 original_pseudo <- inherit_or_split_pseudo1
5676 where the 2nd insn is the current insn and
5677 inherit_or_split_pseudo2 is not removed. If it is found,
5678 change the current insn onto:
5679 original_pseudo <- inherit_or_split_pseudo2. */
5680 for (prev_insn
= PREV_INSN (curr_insn
);
5681 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5682 prev_insn
= PREV_INSN (prev_insn
))
5684 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5685 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5686 /* There should be no subregs in insn we are
5687 searching because only the original reg might
5688 be in subreg when we changed the mode of
5689 load/store for splitting. */
5690 && REG_P (SET_DEST (prev_set
))
5691 && REG_P (SET_SRC (prev_set
))
5692 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5693 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5694 >= FIRST_PSEUDO_REGISTER
)
5695 /* As we consider chain of inheritance or
5696 splitting described in above comment we should
5697 check that sregno and prev_sregno were
5698 inheritance/split pseudos created from the
5699 same original regno. */
5700 && (lra_reg_info
[sregno
].restore_regno
5701 == lra_reg_info
[prev_sregno
].restore_regno
)
5702 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5704 lra_assert (GET_MODE (SET_SRC (prev_set
))
5705 == GET_MODE (regno_reg_rtx
[sregno
]));
5706 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5707 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5709 SET_SRC (set
) = SET_SRC (prev_set
);
5710 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5711 lra_set_used_insn_alternative_by_uid
5712 (INSN_UID (curr_insn
), -1);
5714 if (lra_dump_file
!= NULL
)
5716 fprintf (lra_dump_file
, " Change reload insn:\n");
5717 dump_insn_slim (lra_dump_file
, curr_insn
);
5724 struct lra_insn_reg
*reg
;
5725 bool restored_regs_p
= false;
5726 bool kept_regs_p
= false;
5728 curr_id
= lra_get_insn_recog_data (curr_insn
);
5729 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5732 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5733 if (restore_regno
>= 0)
5735 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5737 substitute_pseudo (&curr_insn
, regno
,
5738 regno_reg_rtx
[restore_regno
]);
5739 restored_regs_p
= true;
5745 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5747 /* The instruction has changed since the previous
5748 constraints pass. */
5749 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5750 lra_set_used_insn_alternative_by_uid
5751 (INSN_UID (curr_insn
), -1);
5753 else if (restored_regs_p
)
5754 /* The instruction has been restored to the form that
5755 it had during the previous constraints pass. */
5756 lra_update_insn_regno_info (curr_insn
);
5757 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5759 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5760 dump_insn_slim (lra_dump_file
, curr_insn
);
5768 /* If optional reload pseudos failed to get a hard register or was not
5769 inherited, it is better to remove optional reloads. We do this
5770 transformation after undoing inheritance to figure out necessity to
5771 remove optional reloads easier. Return true if we do any
5774 undo_optional_reloads (void)
5776 bool change_p
, keep_p
;
5777 unsigned int regno
, uid
;
5778 bitmap_iterator bi
, bi2
;
5779 rtx insn
, set
, src
, dest
;
5780 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5782 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5783 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5784 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5787 /* Keep optional reloads from previous subpasses. */
5788 if (lra_reg_info
[regno
].restore_regno
< 0
5789 /* If the original pseudo changed its allocation, just
5790 removing the optional pseudo is dangerous as the original
5791 pseudo will have longer live range. */
5792 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5794 else if (reg_renumber
[regno
] >= 0)
5795 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5797 insn
= lra_insn_recog_data
[uid
]->insn
;
5798 if ((set
= single_set (insn
)) == NULL_RTX
)
5800 src
= SET_SRC (set
);
5801 dest
= SET_DEST (set
);
5802 if (! REG_P (src
) || ! REG_P (dest
))
5804 if (REGNO (dest
) == regno
5805 /* Ignore insn for optional reloads itself. */
5806 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5807 /* Check only inheritance on last inheritance pass. */
5808 && (int) REGNO (src
) >= new_regno_start
5809 /* Check that the optional reload was inherited. */
5810 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5818 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5819 if (lra_dump_file
!= NULL
)
5820 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5823 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5824 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5825 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5827 if (lra_dump_file
!= NULL
)
5828 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5829 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5830 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5832 insn
= lra_insn_recog_data
[uid
]->insn
;
5833 if ((set
= single_set (insn
)) != NULL_RTX
)
5835 src
= SET_SRC (set
);
5836 dest
= SET_DEST (set
);
5837 if (REG_P (src
) && REG_P (dest
)
5838 && ((REGNO (src
) == regno
5839 && (lra_reg_info
[regno
].restore_regno
5840 == (int) REGNO (dest
)))
5841 || (REGNO (dest
) == regno
5842 && (lra_reg_info
[regno
].restore_regno
5843 == (int) REGNO (src
)))))
5845 if (lra_dump_file
!= NULL
)
5847 fprintf (lra_dump_file
, " Deleting move %u\n",
5849 dump_insn_slim (lra_dump_file
, insn
);
5851 lra_set_insn_deleted (insn
);
5854 /* We should not worry about generation memory-memory
5855 moves here as if the corresponding inheritance did
5856 not work (inheritance pseudo did not get a hard reg),
5857 we remove the inheritance pseudo and the optional
5860 substitute_pseudo (&insn
, regno
,
5861 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5862 lra_update_insn_regno_info (insn
);
5863 if (lra_dump_file
!= NULL
)
5865 fprintf (lra_dump_file
,
5866 " Restoring original insn:\n");
5867 dump_insn_slim (lra_dump_file
, insn
);
5871 /* Clear restore_regnos. */
5872 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5873 lra_reg_info
[regno
].restore_regno
= -1;
5874 bitmap_clear (&insn_bitmap
);
5875 bitmap_clear (&removed_optional_reload_pseudos
);
5879 /* Entry function for undoing inheritance/split transformation. Return true
5880 if we did any RTL change in this pass. */
5882 lra_undo_inheritance (void)
5885 int restore_regno
, hard_regno
;
5886 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5887 bitmap_head remove_pseudos
;
5891 lra_undo_inheritance_iter
++;
5892 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5894 if (lra_dump_file
!= NULL
)
5895 fprintf (lra_dump_file
,
5896 "\n********** Undoing inheritance #%d: **********\n\n",
5897 lra_undo_inheritance_iter
);
5898 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5899 n_inherit
= n_all_inherit
= 0;
5900 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5901 if (lra_reg_info
[regno
].restore_regno
>= 0)
5904 if (reg_renumber
[regno
] < 0
5905 /* If the original pseudo changed its allocation, just
5906 removing inheritance is dangerous as for changing
5907 allocation we used shorter live-ranges. */
5908 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5909 bitmap_set_bit (&remove_pseudos
, regno
);
5913 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5914 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5915 n_inherit
, n_all_inherit
,
5916 (double) n_inherit
/ n_all_inherit
* 100);
5917 n_split
= n_all_split
= 0;
5918 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5919 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5922 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5923 ? reg_renumber
[restore_regno
] : restore_regno
);
5924 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5925 bitmap_set_bit (&remove_pseudos
, regno
);
5929 if (lra_dump_file
!= NULL
)
5930 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5931 regno
, restore_regno
);
5934 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5935 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5936 n_split
, n_all_split
,
5937 (double) n_split
/ n_all_split
* 100);
5938 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5939 bitmap_clear (&remove_pseudos
);
5940 /* Clear restore_regnos. */
5941 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5942 lra_reg_info
[regno
].restore_regno
= -1;
5943 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5944 lra_reg_info
[regno
].restore_regno
= -1;
5945 change_p
= undo_optional_reloads () || change_p
;