1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2020 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
132 #include "print-rtl.h"
133 #include "function-abi.h"
134 #include "rtl-iter.h"
136 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
137 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
139 static int bb_reload_num
;
141 /* The current insn being processed and corresponding its single set
142 (NULL otherwise), its data (basic block, the insn data, the insn
143 static data, and the mode of each operand). */
144 static rtx_insn
*curr_insn
;
145 static rtx curr_insn_set
;
146 static basic_block curr_bb
;
147 static lra_insn_recog_data_t curr_id
;
148 static struct lra_static_insn_data
*curr_static_id
;
149 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Mode of the register substituted by its equivalence with VOIDmode
151 (e.g. constant) and whose subreg is given operand of the current
152 insn. VOIDmode in all other cases. */
153 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
157 /* Start numbers for new registers and insns at the current constraints
159 static int new_regno_start
;
160 static int new_insn_uid_start
;
162 /* If LOC is nonnull, strip any outer subreg from it. */
164 strip_subreg (rtx
*loc
)
166 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
169 /* Return hard regno of REGNO or if it is was not assigned to a hard
170 register, use a hard register from its allocno class. */
172 get_try_hard_regno (int regno
)
175 enum reg_class rclass
;
177 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
178 hard_regno
= lra_get_regno_hard_regno (regno
);
181 rclass
= lra_get_allocno_class (regno
);
182 if (rclass
== NO_REGS
)
184 return ira_class_hard_regs
[rclass
][0];
187 /* Return the hard regno of X after removing its subreg. If X is not
188 a register or a subreg of a register, return -1. If X is a pseudo,
189 use its assignment. If FINAL_P return the final hard regno which will
190 be after elimination. */
192 get_hard_regno (rtx x
, bool final_p
)
199 reg
= SUBREG_REG (x
);
202 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
203 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
207 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
209 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
210 SUBREG_BYTE (x
), GET_MODE (x
));
214 /* If REGNO is a hard register or has been allocated a hard register,
215 return the class of that register. If REGNO is a reload pseudo
216 created by the current constraints pass, return its allocno class.
217 Return NO_REGS otherwise. */
218 static enum reg_class
219 get_reg_class (int regno
)
223 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
224 hard_regno
= lra_get_regno_hard_regno (regno
);
227 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
228 return REGNO_REG_CLASS (hard_regno
);
230 if (regno
>= new_regno_start
)
231 return lra_get_allocno_class (regno
);
235 /* Return true if REG satisfies (or will satisfy) reg class constraint
236 CL. Use elimination first if REG is a hard register. If REG is a
237 reload pseudo created by this constraints pass, assume that it will
238 be allocated a hard register from its allocno class, but allow that
239 class to be narrowed to CL if it is currently a superset of CL.
241 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
242 REGNO (reg), or NO_REGS if no change in its class was needed. */
244 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
246 enum reg_class rclass
, common_class
;
247 machine_mode reg_mode
;
248 int class_size
, hard_regno
, nregs
, i
, j
;
249 int regno
= REGNO (reg
);
251 if (new_class
!= NULL
)
252 *new_class
= NO_REGS
;
253 if (regno
< FIRST_PSEUDO_REGISTER
)
256 rtx
*final_loc
= &final_reg
;
258 lra_eliminate_reg_if_possible (final_loc
);
259 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
261 reg_mode
= GET_MODE (reg
);
262 rclass
= get_reg_class (regno
);
263 if (regno
< new_regno_start
264 /* Do not allow the constraints for reload instructions to
265 influence the classes of new pseudos. These reloads are
266 typically moves that have many alternatives, and restricting
267 reload pseudos for one alternative may lead to situations
268 where other reload pseudos are no longer allocatable. */
269 || (INSN_UID (curr_insn
) >= new_insn_uid_start
270 && curr_insn_set
!= NULL
271 && ((OBJECT_P (SET_SRC (curr_insn_set
))
272 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
273 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
274 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
275 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
276 /* When we don't know what class will be used finally for reload
277 pseudos, we use ALL_REGS. */
278 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
279 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
280 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
281 lra_no_alloc_regs
)));
284 common_class
= ira_reg_class_subset
[rclass
][cl
];
285 if (new_class
!= NULL
)
286 *new_class
= common_class
;
287 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
290 /* Check that there are enough allocatable regs. */
291 class_size
= ira_class_hard_regs_num
[common_class
];
292 for (i
= 0; i
< class_size
; i
++)
294 hard_regno
= ira_class_hard_regs
[common_class
][i
];
295 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
298 for (j
= 0; j
< nregs
; j
++)
299 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
300 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
310 /* Return true if REGNO satisfies a memory constraint. */
314 return get_reg_class (regno
) == NO_REGS
;
317 /* Return 1 if ADDR is a valid memory address for mode MODE in address
318 space AS, and check that each pseudo has the proper kind of hard
321 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
322 rtx addr
, addr_space_t as
)
324 #ifdef GO_IF_LEGITIMATE_ADDRESS
325 lra_assert (ADDR_SPACE_GENERIC_P (as
));
326 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
332 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
337 /* Temporarily eliminates registers in an address (for the lifetime of
339 class address_eliminator
{
341 address_eliminator (struct address_info
*ad
);
342 ~address_eliminator ();
345 struct address_info
*m_ad
;
353 address_eliminator::address_eliminator (struct address_info
*ad
)
355 m_base_loc (strip_subreg (ad
->base_term
)),
356 m_base_reg (NULL_RTX
),
357 m_index_loc (strip_subreg (ad
->index_term
)),
358 m_index_reg (NULL_RTX
)
360 if (m_base_loc
!= NULL
)
362 m_base_reg
= *m_base_loc
;
363 /* If we have non-legitimate address which is decomposed not in
364 the way we expected, don't do elimination here. In such case
365 the address will be reloaded and elimination will be done in
366 reload insn finally. */
367 if (REG_P (m_base_reg
))
368 lra_eliminate_reg_if_possible (m_base_loc
);
369 if (m_ad
->base_term2
!= NULL
)
370 *m_ad
->base_term2
= *m_ad
->base_term
;
372 if (m_index_loc
!= NULL
)
374 m_index_reg
= *m_index_loc
;
375 if (REG_P (m_index_reg
))
376 lra_eliminate_reg_if_possible (m_index_loc
);
380 address_eliminator::~address_eliminator ()
382 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
384 *m_base_loc
= m_base_reg
;
385 if (m_ad
->base_term2
!= NULL
)
386 *m_ad
->base_term2
= *m_ad
->base_term
;
388 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
389 *m_index_loc
= m_index_reg
;
392 /* Return true if the eliminated form of AD is a legitimate target address.
393 If OP is a MEM, AD is the address within OP, otherwise OP should be
394 ignored. CONSTRAINT is one constraint that the operand may need
397 valid_address_p (rtx op
, struct address_info
*ad
,
398 enum constraint_num constraint
)
400 address_eliminator
eliminator (ad
);
402 /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more
403 forgiving than "m". */
405 && (insn_extra_memory_constraint (constraint
)
406 || insn_extra_special_memory_constraint (constraint
))
407 && constraint_satisfied_p (op
, constraint
))
410 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
413 /* Return true if the eliminated form of memory reference OP satisfies
414 extra (special) memory constraint CONSTRAINT. */
416 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
418 struct address_info ad
;
420 decompose_mem_address (&ad
, op
);
421 address_eliminator
eliminator (&ad
);
422 return constraint_satisfied_p (op
, constraint
);
425 /* Return true if the eliminated form of address AD satisfies extra
426 address constraint CONSTRAINT. */
428 satisfies_address_constraint_p (struct address_info
*ad
,
429 enum constraint_num constraint
)
431 address_eliminator
eliminator (ad
);
432 return constraint_satisfied_p (*ad
->outer
, constraint
);
435 /* Return true if the eliminated form of address OP satisfies extra
436 address constraint CONSTRAINT. */
438 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
440 struct address_info ad
;
442 decompose_lea_address (&ad
, &op
);
443 return satisfies_address_constraint_p (&ad
, constraint
);
446 /* Initiate equivalences for LRA. As we keep original equivalences
447 before any elimination, we need to make copies otherwise any change
448 in insns might change the equivalences. */
450 lra_init_equiv (void)
452 ira_expand_reg_equiv ();
453 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
457 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
458 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
459 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
460 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
464 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
466 /* Update equivalence for REGNO. We need to this as the equivalence
467 might contain other pseudos which are changed by their
470 update_equiv (int regno
)
474 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
475 ira_reg_equiv
[regno
].memory
476 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
478 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
479 ira_reg_equiv
[regno
].invariant
480 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
484 /* If we have decided to substitute X with another value, return that
485 value, otherwise return X. */
492 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
493 || ! ira_reg_equiv
[regno
].defined_p
494 || ! ira_reg_equiv
[regno
].profitable_p
495 || lra_get_regno_hard_regno (regno
) >= 0)
497 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
499 if (targetm
.cannot_substitute_mem_equiv_p (res
))
503 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
505 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
510 /* If we have decided to substitute X with the equivalent value,
511 return that value after elimination for INSN, otherwise return
514 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
516 rtx res
= get_equiv (x
);
518 if (x
== res
|| CONSTANT_P (res
))
520 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
521 false, false, 0, true);
524 /* Set up curr_operand_mode. */
526 init_curr_operand_mode (void)
528 int nop
= curr_static_id
->n_operands
;
529 for (int i
= 0; i
< nop
; i
++)
531 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
532 if (mode
== VOIDmode
)
534 /* The .md mode for address operands is the mode of the
535 addressed value rather than the mode of the address itself. */
536 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
539 mode
= curr_static_id
->operand
[i
].mode
;
541 curr_operand_mode
[i
] = mode
;
547 /* The page contains code to reuse input reloads. */
549 /* Structure describes input reload of the current insns. */
552 /* True for input reload of matched operands. */
554 /* Reloaded value. */
556 /* Reload pseudo used. */
560 /* The number of elements in the following array. */
561 static int curr_insn_input_reloads_num
;
562 /* Array containing info about input reloads. It is used to find the
563 same input reload and reuse the reload pseudo in this case. */
564 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
566 /* Initiate data concerning reuse of input reloads for the current
569 init_curr_insn_input_reloads (void)
571 curr_insn_input_reloads_num
= 0;
574 /* The canonical form of an rtx inside a MEM is not necessarily the same as the
575 canonical form of the rtx outside the MEM. Fix this up in the case that
576 we're reloading an address (and therefore pulling it outside a MEM). */
578 canonicalize_reload_addr (rtx addr
)
580 subrtx_var_iterator::array_type array
;
581 FOR_EACH_SUBRTX_VAR (iter
, array
, addr
, NONCONST
)
584 if (GET_CODE (x
) == MULT
&& CONST_INT_P (XEXP (x
, 1)))
586 const HOST_WIDE_INT ci
= INTVAL (XEXP (x
, 1));
587 const int pwr2
= exact_log2 (ci
);
590 /* Rewrite this to use a shift instead, which is canonical when
592 PUT_CODE (x
, ASHIFT
);
593 XEXP (x
, 1) = GEN_INT (pwr2
);
601 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
602 created input reload pseudo (only if TYPE is not OP_OUT). Don't
603 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
604 wrapped up in SUBREG. The result pseudo is returned through
605 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
606 reused the already created input reload pseudo. Use TITLE to
607 describe new registers for debug purposes. */
609 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
610 enum reg_class rclass
, bool in_subreg_p
,
611 const char *title
, rtx
*result_reg
)
614 enum reg_class new_class
;
615 bool unique_p
= false;
620 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
623 /* Prevent reuse value of expression with side effects,
624 e.g. volatile memory. */
625 if (! side_effects_p (original
))
626 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
628 if (! curr_insn_input_reloads
[i
].match_p
629 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
630 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
632 rtx reg
= curr_insn_input_reloads
[i
].reg
;
634 /* If input is equal to original and both are VOIDmode,
635 GET_MODE (reg) might be still different from mode.
636 Ensure we don't return *result_reg with wrong mode. */
637 if (GET_MODE (reg
) != mode
)
641 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg
)),
642 GET_MODE_SIZE (mode
)))
644 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
645 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
649 if (lra_dump_file
!= NULL
)
651 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
652 dump_value_slim (lra_dump_file
, original
, 1);
654 if (new_class
!= lra_get_allocno_class (regno
))
655 lra_change_class (regno
, new_class
, ", change to", false);
656 if (lra_dump_file
!= NULL
)
657 fprintf (lra_dump_file
, "\n");
660 /* If we have an input reload with a different mode, make sure it
661 will get a different hard reg. */
662 else if (REG_P (original
)
663 && REG_P (curr_insn_input_reloads
[i
].input
)
664 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
665 && (GET_MODE (original
)
666 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
669 *result_reg
= (unique_p
670 ? lra_create_new_reg_with_unique_value
671 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
672 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
673 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
674 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
675 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
680 /* The page contains major code to choose the current insn alternative
681 and generate reloads for it. */
683 /* Return the offset from REGNO of the least significant register
686 This function is used to tell whether two registers satisfy
687 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
689 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
690 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
692 lra_constraint_offset (int regno
, machine_mode mode
)
694 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
696 scalar_int_mode int_mode
;
698 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
699 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
700 return hard_regno_nregs (regno
, mode
) - 1;
704 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
705 if they are the same hard reg, and has special hacks for
706 auto-increment and auto-decrement. This is specifically intended for
707 process_alt_operands to use in determining whether two operands
708 match. X is the operand whose number is the lower of the two.
710 It is supposed that X is the output operand and Y is the input
711 operand. Y_HARD_REGNO is the final hard regno of register Y or
712 register in subreg Y as we know it now. Otherwise, it is a
715 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
718 RTX_CODE code
= GET_CODE (x
);
723 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
724 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
728 i
= get_hard_regno (x
, false);
732 if ((j
= y_hard_regno
) < 0)
735 i
+= lra_constraint_offset (i
, GET_MODE (x
));
736 j
+= lra_constraint_offset (j
, GET_MODE (y
));
741 /* If two operands must match, because they are really a single
742 operand of an assembler insn, then two post-increments are invalid
743 because the assembler insn would increment only once. On the
744 other hand, a post-increment matches ordinary indexing if the
745 post-increment is the output operand. */
746 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
747 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
749 /* Two pre-increments are invalid because the assembler insn would
750 increment only once. On the other hand, a pre-increment matches
751 ordinary indexing if the pre-increment is the input operand. */
752 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
753 || GET_CODE (y
) == PRE_MODIFY
)
754 return operands_match_p (x
, XEXP (y
, 0), -1);
758 if (code
== REG
&& REG_P (y
))
759 return REGNO (x
) == REGNO (y
);
761 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
762 && x
== SUBREG_REG (y
))
764 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
765 && SUBREG_REG (x
) == y
)
768 /* Now we have disposed of all the cases in which different rtx
770 if (code
!= GET_CODE (y
))
773 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
774 if (GET_MODE (x
) != GET_MODE (y
))
783 return label_ref_label (x
) == label_ref_label (y
);
785 return XSTR (x
, 0) == XSTR (y
, 0);
791 /* Compare the elements. If any pair of corresponding elements fail
792 to match, return false for the whole things. */
794 fmt
= GET_RTX_FORMAT (code
);
795 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
801 if (XWINT (x
, i
) != XWINT (y
, i
))
806 if (XINT (x
, i
) != XINT (y
, i
))
811 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
816 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
825 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
827 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
829 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
835 /* It is believed that rtx's at this level will never
836 contain anything but integers and other rtx's, except for
837 within LABEL_REFs and SYMBOL_REFs. */
845 /* True if X is a constant that can be forced into the constant pool.
846 MODE is the mode of the operand, or VOIDmode if not known. */
847 #define CONST_POOL_OK_P(MODE, X) \
848 ((MODE) != VOIDmode \
850 && GET_CODE (X) != HIGH \
851 && GET_MODE_SIZE (MODE).is_constant () \
852 && !targetm.cannot_force_const_mem (MODE, X))
854 /* True if C is a non-empty register class that has too few registers
855 to be safely used as a reload target class. */
856 #define SMALL_REGISTER_CLASS_P(C) \
857 (ira_class_hard_regs_num [(C)] == 1 \
858 || (ira_class_hard_regs_num [(C)] >= 1 \
859 && targetm.class_likely_spilled_p (C)))
861 /* If REG is a reload pseudo, try to make its class satisfying CL. */
863 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
865 enum reg_class rclass
;
867 /* Do not make more accurate class from reloads generated. They are
868 mostly moves with a lot of constraints. Making more accurate
869 class may results in very narrow class and impossibility of find
870 registers for several reloads of one insn. */
871 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
873 if (GET_CODE (reg
) == SUBREG
)
874 reg
= SUBREG_REG (reg
);
875 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
877 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
878 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
881 /* Searches X for any reference to a reg with the same value as REGNO,
882 returning the rtx of the reference found if any. Otherwise,
885 regno_val_use_in (unsigned int regno
, rtx x
)
891 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
894 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
895 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
899 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
902 else if (fmt
[i
] == 'E')
903 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
904 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
911 /* Return true if all current insn non-output operands except INS (it
912 has a negaitve end marker) do not use pseudos with the same value
915 check_conflict_input_operands (int regno
, signed char *ins
)
918 int n_operands
= curr_static_id
->n_operands
;
920 for (int nop
= 0; nop
< n_operands
; nop
++)
921 if (! curr_static_id
->operand
[nop
].is_operator
922 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
924 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
928 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
934 /* Generate reloads for matching OUT and INS (array of input operand
935 numbers with end marker -1) with reg class GOAL_CLASS, considering
936 output operands OUTS (similar array to INS) needing to be in different
937 registers. Add input and output reloads correspondingly to the lists
938 *BEFORE and *AFTER. OUT might be negative. In this case we generate
939 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
940 that the output operand is early clobbered for chosen alternative. */
942 match_reload (signed char out
, signed char *ins
, signed char *outs
,
943 enum reg_class goal_class
, rtx_insn
**before
,
944 rtx_insn
**after
, bool early_clobber_p
)
948 rtx new_in_reg
, new_out_reg
, reg
;
949 machine_mode inmode
, outmode
;
950 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
951 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
953 inmode
= curr_operand_mode
[ins
[0]];
954 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
955 push_to_sequence (*before
);
956 if (inmode
!= outmode
)
958 /* process_alt_operands has already checked that the mode sizes
960 if (partial_subreg_p (outmode
, inmode
))
963 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
965 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
966 LRA_SUBREG_P (new_out_reg
) = 1;
967 /* If the input reg is dying here, we can use the same hard
968 register for REG and IN_RTX. We do it only for original
969 pseudos as reload pseudos can die although original
970 pseudos still live where reload pseudos dies. */
971 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
972 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
974 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
975 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
980 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
982 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
983 /* NEW_IN_REG is non-paradoxical subreg. We don't want
984 NEW_OUT_REG living above. We add clobber clause for
985 this. This is just a temporary clobber. We can remove
986 it at the end of LRA work. */
987 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
988 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
989 LRA_SUBREG_P (new_in_reg
) = 1;
990 if (GET_CODE (in_rtx
) == SUBREG
)
992 rtx subreg_reg
= SUBREG_REG (in_rtx
);
994 /* If SUBREG_REG is dying here and sub-registers IN_RTX
995 and NEW_IN_REG are similar, we can use the same hard
996 register for REG and SUBREG_REG. */
997 if (REG_P (subreg_reg
)
998 && (int) REGNO (subreg_reg
) < lra_new_regno_start
999 && GET_MODE (subreg_reg
) == outmode
1000 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
1001 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
1002 && (! early_clobber_p
1003 || check_conflict_input_operands (REGNO (subreg_reg
),
1005 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
1011 /* Pseudos have values -- see comments for lra_reg_info.
1012 Different pseudos with the same value do not conflict even if
1013 they live in the same place. When we create a pseudo we
1014 assign value of original pseudo (if any) from which we
1015 created the new pseudo. If we create the pseudo from the
1016 input pseudo, the new pseudo will have no conflict with the
1017 input pseudo which is wrong when the input pseudo lives after
1018 the insn and as the new pseudo value is changed by the insn
1019 output. Therefore we create the new pseudo from the output
1020 except the case when we have single matched dying input
1023 We cannot reuse the current output register because we might
1024 have a situation like "a <- a op b", where the constraints
1025 force the second input operand ("b") to match the output
1026 operand ("a"). "b" must then be copied into a new register
1027 so that it doesn't clobber the current value of "a".
1029 We cannot use the same value if the output pseudo is
1030 early clobbered or the input pseudo is mentioned in the
1031 output, e.g. as an address part in memory, because
1032 output reload will actually extend the pseudo liveness.
1033 We don't care about eliminable hard regs here as we are
1034 interesting only in pseudos. */
1036 /* Matching input's register value is the same as one of the other
1037 output operand. Output operands in a parallel insn must be in
1038 different registers. */
1039 out_conflict
= false;
1042 for (i
= 0; outs
[i
] >= 0; i
++)
1044 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1045 if (REG_P (other_out_rtx
)
1046 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1049 out_conflict
= true;
1055 new_in_reg
= new_out_reg
1056 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1057 && (int) REGNO (in_rtx
) < lra_new_regno_start
1058 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1059 && (! early_clobber_p
1060 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1062 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1064 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1065 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1068 /* In operand can be got from transformations before processing insn
1069 constraints. One example of such transformations is subreg
1070 reloading (see function simplify_operand_subreg). The new
1071 pseudos created by the transformations might have inaccurate
1072 class (ALL_REGS) and we should make their classes more
1074 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1075 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1076 *before
= get_insns ();
1078 /* Add the new pseudo to consider values of subsequent input reload
1080 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1081 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1082 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1083 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1084 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1085 if (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1086 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]))
1087 *curr_id
->operand_loc
[in
] = new_in_reg
;
1091 (GET_MODE (new_out_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1092 *curr_id
->operand_loc
[in
] = new_out_reg
;
1094 lra_update_dups (curr_id
, ins
);
1097 /* See a comment for the input operand above. */
1098 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1099 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1102 if (out
>= 0 && curr_static_id
->operand
[out
].strict_low
)
1103 out_rtx
= gen_rtx_STRICT_LOW_PART (VOIDmode
, out_rtx
);
1104 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1106 *after
= get_insns ();
1109 *curr_id
->operand_loc
[out
] = new_out_reg
;
1110 lra_update_dup (curr_id
, out
);
1113 /* Return register class which is union of all reg classes in insn
1114 constraint alternative string starting with P. */
1115 static enum reg_class
1116 reg_class_from_constraints (const char *p
)
1119 enum reg_class op_class
= NO_REGS
;
1122 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1129 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1133 enum constraint_num cn
= lookup_constraint (p
);
1134 enum reg_class cl
= reg_class_for_constraint (cn
);
1137 if (insn_extra_address_constraint (cn
))
1139 = (reg_class_subunion
1140 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1141 ADDRESS
, SCRATCH
)]);
1145 op_class
= reg_class_subunion
[op_class
][cl
];
1148 while ((p
+= len
), c
);
1152 /* If OP is a register, return the class of the register as per
1153 get_reg_class, otherwise return NO_REGS. */
1154 static inline enum reg_class
1155 get_op_class (rtx op
)
1157 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1160 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1161 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1162 SUBREG for VAL to make them equal. */
1164 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1166 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1168 /* Usually size of mem_pseudo is greater than val size but in
1169 rare cases it can be less as it can be defined by target
1170 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1173 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1174 GET_CODE (val
) == SUBREG
1175 ? SUBREG_REG (val
) : val
);
1176 LRA_SUBREG_P (val
) = 1;
1180 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1181 LRA_SUBREG_P (mem_pseudo
) = 1;
1184 return to_p
? gen_move_insn (mem_pseudo
, val
)
1185 : gen_move_insn (val
, mem_pseudo
);
1188 /* Process a special case insn (register move), return true if we
1189 don't need to process it anymore. INSN should be a single set
1190 insn. Set up that RTL was changed through CHANGE_P and that hook
1191 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1194 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1197 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1199 enum reg_class dclass
, sclass
, secondary_class
;
1200 secondary_reload_info sri
;
1202 lra_assert (curr_insn_set
!= NULL_RTX
);
1203 dreg
= dest
= SET_DEST (curr_insn_set
);
1204 sreg
= src
= SET_SRC (curr_insn_set
);
1205 if (GET_CODE (dest
) == SUBREG
)
1206 dreg
= SUBREG_REG (dest
);
1207 if (GET_CODE (src
) == SUBREG
)
1208 sreg
= SUBREG_REG (src
);
1209 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1211 sclass
= dclass
= NO_REGS
;
1213 dclass
= get_reg_class (REGNO (dreg
));
1214 gcc_assert (dclass
< LIM_REG_CLASSES
);
1215 if (dclass
== ALL_REGS
)
1216 /* ALL_REGS is used for new pseudos created by transformations
1217 like reload of SUBREG_REG (see function
1218 simplify_operand_subreg). We don't know their class yet. We
1219 should figure out the class from processing the insn
1220 constraints not in this fast path function. Even if ALL_REGS
1221 were a right class for the pseudo, secondary_... hooks usually
1222 are not define for ALL_REGS. */
1225 sclass
= get_reg_class (REGNO (sreg
));
1226 gcc_assert (sclass
< LIM_REG_CLASSES
);
1227 if (sclass
== ALL_REGS
)
1228 /* See comments above. */
1230 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1232 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1233 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1235 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1240 if (! REG_P (dreg
) || ! REG_P (sreg
))
1242 sri
.prev_sri
= NULL
;
1243 sri
.icode
= CODE_FOR_nothing
;
1245 secondary_class
= NO_REGS
;
1246 /* Set up hard register for a reload pseudo for hook
1247 secondary_reload because some targets just ignore unassigned
1248 pseudos in the hook. */
1249 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1251 dregno
= REGNO (dreg
);
1252 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1256 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1258 sregno
= REGNO (sreg
);
1259 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1263 if (sclass
!= NO_REGS
)
1265 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1266 (reg_class_t
) sclass
,
1267 GET_MODE (src
), &sri
);
1268 if (sclass
== NO_REGS
1269 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1270 && dclass
!= NO_REGS
))
1272 enum reg_class old_sclass
= secondary_class
;
1273 secondary_reload_info old_sri
= sri
;
1275 sri
.prev_sri
= NULL
;
1276 sri
.icode
= CODE_FOR_nothing
;
1279 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1280 (reg_class_t
) dclass
,
1281 GET_MODE (src
), &sri
);
1282 /* Check the target hook consistency. */
1284 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1285 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1286 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1289 reg_renumber
[sregno
] = -1;
1291 reg_renumber
[dregno
] = -1;
1292 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1296 if (secondary_class
!= NO_REGS
)
1297 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1301 if (sri
.icode
== CODE_FOR_nothing
)
1302 lra_emit_move (new_reg
, src
);
1305 enum reg_class scratch_class
;
1307 scratch_class
= (reg_class_from_constraints
1308 (insn_data
[sri
.icode
].operand
[2].constraint
));
1309 scratch_reg
= (lra_create_new_reg_with_unique_value
1310 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1311 scratch_class
, "scratch"));
1312 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1315 before
= get_insns ();
1317 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1318 if (new_reg
!= NULL_RTX
)
1319 SET_SRC (curr_insn_set
) = new_reg
;
1322 if (lra_dump_file
!= NULL
)
1324 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1325 dump_insn_slim (lra_dump_file
, curr_insn
);
1327 lra_set_insn_deleted (curr_insn
);
1333 /* The following data describe the result of process_alt_operands.
1334 The data are used in curr_insn_transform to generate reloads. */
1336 /* The chosen reg classes which should be used for the corresponding
1338 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1339 /* True if the operand should be the same as another operand and that
1340 other operand does not need a reload. */
1341 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1342 /* True if the operand does not need a reload. */
1343 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1344 /* True if the operand can be offsetable memory. */
1345 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1346 /* The number of an operand to which given operand can be matched to. */
1347 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1348 /* The number of elements in the following array. */
1349 static int goal_alt_dont_inherit_ops_num
;
1350 /* Numbers of operands whose reload pseudos should not be inherited. */
1351 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1352 /* True if the insn commutative operands should be swapped. */
1353 static bool goal_alt_swapped
;
1354 /* The chosen insn alternative. */
1355 static int goal_alt_number
;
1357 /* True if the corresponding operand is the result of an equivalence
1359 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1361 /* The following five variables are used to choose the best insn
1362 alternative. They reflect final characteristics of the best
1365 /* Number of necessary reloads and overall cost reflecting the
1366 previous value and other unpleasantness of the best alternative. */
1367 static int best_losers
, best_overall
;
1368 /* Overall number hard registers used for reloads. For example, on
1369 some targets we need 2 general registers to reload DFmode and only
1370 one floating point register. */
1371 static int best_reload_nregs
;
1372 /* Overall number reflecting distances of previous reloading the same
1373 value. The distances are counted from the current BB start. It is
1374 used to improve inheritance chances. */
1375 static int best_reload_sum
;
1377 /* True if the current insn should have no correspondingly input or
1379 static bool no_input_reloads_p
, no_output_reloads_p
;
1381 /* True if we swapped the commutative operands in the current
1383 static int curr_swapped
;
1385 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1386 register of class CL. Add any input reloads to list BEFORE. AFTER
1387 is nonnull if *LOC is an automodified value; handle that case by
1388 adding the required output reloads to list AFTER. Return true if
1389 the RTL was changed.
1391 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1392 register. Return false if the address register is correct. */
1394 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1398 enum reg_class rclass
, new_class
;
1402 bool subreg_p
, before_p
= false;
1404 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1407 reg
= SUBREG_REG (*loc
);
1408 mode
= GET_MODE (reg
);
1410 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1411 between two registers with different classes, but there normally will
1412 be "mov" which transfers element of vector register into the general
1413 register, and this normally will be a subreg which should be reloaded
1414 as a whole. This is particularly likely to be triggered when
1415 -fno-split-wide-types specified. */
1417 || in_class_p (reg
, cl
, &new_class
)
1418 || known_le (GET_MODE_SIZE (mode
), GET_MODE_SIZE (ptr_mode
)))
1419 loc
= &SUBREG_REG (*loc
);
1423 mode
= GET_MODE (reg
);
1428 /* Always reload memory in an address even if the target supports
1430 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1435 regno
= REGNO (reg
);
1436 rclass
= get_reg_class (regno
);
1438 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1440 if (lra_dump_file
!= NULL
)
1442 fprintf (lra_dump_file
,
1443 "Changing pseudo %d in address of insn %u on equiv ",
1444 REGNO (reg
), INSN_UID (curr_insn
));
1445 dump_value_slim (lra_dump_file
, *loc
, 1);
1446 fprintf (lra_dump_file
, "\n");
1448 *loc
= copy_rtx (*loc
);
1450 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1455 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1456 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1459 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1463 lra_change_class (regno
, new_class
, " Change to", true);
1471 push_to_sequence (*before
);
1472 lra_emit_move (new_reg
, reg
);
1473 *before
= get_insns ();
1480 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1482 *after
= get_insns ();
1488 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1489 the insn to be inserted before curr insn. AFTER returns the
1490 the insn to be inserted after curr insn. ORIGREG and NEWREG
1491 are the original reg and new reg for reload. */
1493 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1498 push_to_sequence (*before
);
1499 lra_emit_move (newreg
, origreg
);
1500 *before
= get_insns ();
1506 lra_emit_move (origreg
, newreg
);
1508 *after
= get_insns ();
1513 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1514 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1516 /* Make reloads for subreg in operand NOP with internal subreg mode
1517 REG_MODE, add new reloads for further processing. Return true if
1518 any change was done. */
1520 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1522 int hard_regno
, inner_hard_regno
;
1523 rtx_insn
*before
, *after
;
1524 machine_mode mode
, innermode
;
1526 rtx operand
= *curr_id
->operand_loc
[nop
];
1527 enum reg_class regclass
;
1530 before
= after
= NULL
;
1532 if (GET_CODE (operand
) != SUBREG
)
1535 mode
= GET_MODE (operand
);
1536 reg
= SUBREG_REG (operand
);
1537 innermode
= GET_MODE (reg
);
1538 type
= curr_static_id
->operand
[nop
].type
;
1541 const bool addr_was_valid
1542 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1543 alter_subreg (curr_id
->operand_loc
[nop
], false);
1544 rtx subst
= *curr_id
->operand_loc
[nop
];
1545 lra_assert (MEM_P (subst
));
1546 const bool addr_is_valid
= valid_address_p (GET_MODE (subst
),
1548 MEM_ADDR_SPACE (subst
));
1551 || ((get_constraint_type (lookup_constraint
1552 (curr_static_id
->operand
[nop
].constraint
))
1553 != CT_SPECIAL_MEMORY
)
1554 /* We still can reload address and if the address is
1555 valid, we can remove subreg without reloading its
1557 && valid_address_p (GET_MODE (subst
),
1559 [ira_class_hard_regs
1560 [base_reg_class (GET_MODE (subst
),
1561 MEM_ADDR_SPACE (subst
),
1562 ADDRESS
, SCRATCH
)][0]],
1563 MEM_ADDR_SPACE (subst
))))
1565 /* If we change the address for a paradoxical subreg of memory, the
1566 new address might violate the necessary alignment or the access
1567 might be slow; take this into consideration. We need not worry
1568 about accesses beyond allocated memory for paradoxical memory
1569 subregs as we don't substitute such equiv memory (see processing
1570 equivalences in function lra_constraints) and because for spilled
1571 pseudos we allocate stack memory enough for the biggest
1572 corresponding paradoxical subreg.
1574 However, do not blindly simplify a (subreg (mem ...)) for
1575 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1576 data into a register when the inner is narrower than outer or
1577 missing important data from memory when the inner is wider than
1578 outer. This rule only applies to modes that are no wider than
1581 If valid memory becomes invalid after subreg elimination
1582 and address might be different we still have to reload
1585 if ((! addr_was_valid
1587 || known_eq (GET_MODE_SIZE (mode
), GET_MODE_SIZE (innermode
)))
1588 && !(maybe_ne (GET_MODE_PRECISION (mode
),
1589 GET_MODE_PRECISION (innermode
))
1590 && known_le (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
1591 && known_le (GET_MODE_SIZE (innermode
), UNITS_PER_WORD
)
1592 && WORD_REGISTER_OPERATIONS
)
1593 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1594 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1595 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1596 && targetm
.slow_unaligned_access (innermode
,
1600 *curr_id
->operand_loc
[nop
] = operand
;
1602 /* But if the address was not valid, we cannot reload the MEM without
1603 reloading the address first. */
1604 if (!addr_was_valid
)
1605 process_address (nop
, false, &before
, &after
);
1607 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1608 enum reg_class rclass
1609 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1610 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1611 reg
, rclass
, TRUE
, "slow/invalid mem", &new_reg
))
1613 bool insert_before
, insert_after
;
1614 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1616 insert_before
= (type
!= OP_OUT
1617 || partial_subreg_p (mode
, innermode
));
1618 insert_after
= type
!= OP_IN
;
1619 insert_move_for_subreg (insert_before
? &before
: NULL
,
1620 insert_after
? &after
: NULL
,
1623 SUBREG_REG (operand
) = new_reg
;
1625 /* Convert to MODE. */
1628 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1629 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1630 rclass
, TRUE
, "slow/invalid mem", &new_reg
))
1632 bool insert_before
, insert_after
;
1633 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1635 insert_before
= type
!= OP_OUT
;
1636 insert_after
= type
!= OP_IN
;
1637 insert_move_for_subreg (insert_before
? &before
: NULL
,
1638 insert_after
? &after
: NULL
,
1641 *curr_id
->operand_loc
[nop
] = new_reg
;
1642 lra_process_new_insns (curr_insn
, before
, after
,
1643 "Inserting slow/invalid mem reload");
1647 /* If the address was valid and became invalid, prefer to reload
1648 the memory. Typical case is when the index scale should
1649 correspond the memory. */
1650 *curr_id
->operand_loc
[nop
] = operand
;
1651 /* Do not return false here as the MEM_P (reg) will be processed
1652 later in this function. */
1654 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1656 alter_subreg (curr_id
->operand_loc
[nop
], false);
1659 else if (CONSTANT_P (reg
))
1661 /* Try to simplify subreg of constant. It is usually result of
1662 equivalence substitution. */
1663 if (innermode
== VOIDmode
1664 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1665 innermode
= curr_static_id
->operand
[nop
].mode
;
1666 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1667 SUBREG_BYTE (operand
))) != NULL_RTX
)
1669 *curr_id
->operand_loc
[nop
] = new_reg
;
1673 /* Put constant into memory when we have mixed modes. It generates
1674 a better code in most cases as it does not need a secondary
1675 reload memory. It also prevents LRA looping when LRA is using
1676 secondary reload memory again and again. */
1677 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1678 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1680 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1681 alter_subreg (curr_id
->operand_loc
[nop
], false);
1684 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1685 if there may be a problem accessing OPERAND in the outer
1688 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1689 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1690 /* Don't reload paradoxical subregs because we could be looping
1691 having repeatedly final regno out of hard regs range. */
1692 && (hard_regno_nregs (hard_regno
, innermode
)
1693 >= hard_regno_nregs (hard_regno
, mode
))
1694 && simplify_subreg_regno (hard_regno
, innermode
,
1695 SUBREG_BYTE (operand
), mode
) < 0
1696 /* Don't reload subreg for matching reload. It is actually
1697 valid subreg in LRA. */
1698 && ! LRA_SUBREG_P (operand
))
1699 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1701 enum reg_class rclass
;
1704 /* There is a big probability that we will get the same class
1705 for the new pseudo and we will get the same insn which
1706 means infinite looping. So spill the new pseudo. */
1709 /* The class will be defined later in curr_insn_transform. */
1711 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1713 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1714 rclass
, TRUE
, "subreg reg", &new_reg
))
1716 bool insert_before
, insert_after
;
1717 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1719 insert_before
= (type
!= OP_OUT
1720 || read_modify_subreg_p (operand
));
1721 insert_after
= (type
!= OP_IN
);
1722 insert_move_for_subreg (insert_before
? &before
: NULL
,
1723 insert_after
? &after
: NULL
,
1726 SUBREG_REG (operand
) = new_reg
;
1727 lra_process_new_insns (curr_insn
, before
, after
,
1728 "Inserting subreg reload");
1731 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1732 IRA allocates hardreg to the inner pseudo reg according to its mode
1733 instead of the outermode, so the size of the hardreg may not be enough
1734 to contain the outermode operand, in that case we may need to insert
1735 reload for the reg. For the following two types of paradoxical subreg,
1736 we need to insert reload:
1737 1. If the op_type is OP_IN, and the hardreg could not be paired with
1738 other hardreg to contain the outermode operand
1739 (checked by in_hard_reg_set_p), we need to insert the reload.
1740 2. If the op_type is OP_OUT or OP_INOUT.
1742 Here is a paradoxical subreg example showing how the reload is generated:
1744 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1745 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1747 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1748 here, if reg107 is assigned to hardreg R15, because R15 is the last
1749 hardreg, compiler cannot find another hardreg to pair with R15 to
1750 contain TImode data. So we insert a TImode reload reg180 for it.
1751 After reload is inserted:
1753 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1754 (reg:DI 107 [ __comp ])) -1
1755 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1756 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1758 Two reload hard registers will be allocated to reg180 to save TImode data
1761 For LRA pseudos this should normally be handled by the biggest_mode
1762 mechanism. However, it's possible for new uses of an LRA pseudo
1763 to be introduced after we've allocated it, such as when undoing
1764 inheritance, and the allocated register might not then be appropriate
1765 for the new uses. */
1766 else if (REG_P (reg
)
1767 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1768 && paradoxical_subreg_p (operand
)
1769 && (inner_hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1771 = simplify_subreg_regno (inner_hard_regno
, innermode
,
1772 SUBREG_BYTE (operand
), mode
)) < 0
1773 || ((hard_regno_nregs (inner_hard_regno
, innermode
)
1774 < hard_regno_nregs (hard_regno
, mode
))
1775 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1777 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1779 || overlaps_hard_reg_set_p (lra_no_alloc_regs
,
1780 mode
, hard_regno
)))))
1782 /* The class will be defined later in curr_insn_transform. */
1783 enum reg_class rclass
1784 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1786 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1787 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1790 bool insert_before
, insert_after
;
1792 PUT_MODE (new_reg
, mode
);
1793 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1794 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1796 insert_before
= (type
!= OP_OUT
);
1797 insert_after
= (type
!= OP_IN
);
1798 insert_move_for_subreg (insert_before
? &before
: NULL
,
1799 insert_after
? &after
: NULL
,
1802 SUBREG_REG (operand
) = new_reg
;
1803 lra_process_new_insns (curr_insn
, before
, after
,
1804 "Inserting paradoxical subreg reload");
1810 /* Return TRUE if X refers for a hard register from SET. */
1812 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1814 int i
, j
, x_hard_regno
;
1821 code
= GET_CODE (x
);
1822 mode
= GET_MODE (x
);
1826 /* For all SUBREGs we want to check whether the full multi-register
1827 overlaps the set. For normal SUBREGs this means 'get_hard_regno' of
1828 the inner register, for paradoxical SUBREGs this means the
1829 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
1830 fine. Use the wider mode for all cases. */
1831 rtx subreg
= SUBREG_REG (x
);
1832 mode
= wider_subreg_mode (x
);
1833 if (mode
== GET_MODE (subreg
))
1836 code
= GET_CODE (x
);
1840 if (REG_P (x
) || SUBREG_P (x
))
1842 x_hard_regno
= get_hard_regno (x
, true);
1843 return (x_hard_regno
>= 0
1844 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1848 struct address_info ad
;
1850 decompose_mem_address (&ad
, x
);
1851 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1853 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1856 fmt
= GET_RTX_FORMAT (code
);
1857 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1861 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1864 else if (fmt
[i
] == 'E')
1866 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1867 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1874 /* Return true if OP is a spilled pseudo. */
1876 spilled_pseudo_p (rtx op
)
1879 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1882 /* Return true if X is a general constant. */
1884 general_constant_p (rtx x
)
1886 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1890 reg_in_class_p (rtx reg
, enum reg_class cl
)
1893 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1894 return in_class_p (reg
, cl
, NULL
);
1897 /* Return true if SET of RCLASS contains no hard regs which can be
1900 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1906 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1907 temp
= set
& ~lra_no_alloc_regs
;
1908 return (hard_reg_set_subset_p
1909 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1913 /* Used to check validity info about small class input operands. It
1914 should be incremented at start of processing an insn
1916 static unsigned int curr_small_class_check
= 0;
1918 /* Update number of used inputs of class OP_CLASS for operand NOP
1919 of alternative NALT. Return true if we have more such class operands
1920 than the number of available regs. */
1922 update_and_check_small_class_inputs (int nop
, int nalt
,
1923 enum reg_class op_class
)
1925 static unsigned int small_class_check
[LIM_REG_CLASSES
];
1926 static int small_class_input_nums
[LIM_REG_CLASSES
];
1928 if (SMALL_REGISTER_CLASS_P (op_class
)
1929 /* We are interesting in classes became small because of fixing
1930 some hard regs, e.g. by an user through GCC options. */
1931 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
1933 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
1934 || TEST_BIT (curr_static_id
->operand
[nop
].early_clobber_alts
, nalt
)))
1936 if (small_class_check
[op_class
] == curr_small_class_check
)
1937 small_class_input_nums
[op_class
]++;
1940 small_class_check
[op_class
] = curr_small_class_check
;
1941 small_class_input_nums
[op_class
] = 1;
1943 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
1949 /* Major function to choose the current insn alternative and what
1950 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1951 negative we should consider only this alternative. Return false if
1952 we cannot choose the alternative or find how to reload the
1955 process_alt_operands (int only_alternative
)
1958 int nop
, overall
, nalt
;
1959 int n_alternatives
= curr_static_id
->n_alternatives
;
1960 int n_operands
= curr_static_id
->n_operands
;
1961 /* LOSERS counts the operands that don't fit this alternative and
1962 would require loading. */
1965 /* REJECT is a count of how undesirable this alternative says it is
1966 if any reloading is required. If the alternative matches exactly
1967 then REJECT is ignored, but otherwise it gets this much counted
1968 against it in addition to the reloading needed. */
1970 /* This is defined by '!' or '?' alternative constraint and added to
1971 reject. But in some cases it can be ignored. */
1974 /* The number of elements in the following array. */
1975 int early_clobbered_regs_num
;
1976 /* Numbers of operands which are early clobber registers. */
1977 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1978 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1979 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1980 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1981 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1982 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1983 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1984 /* The number of elements in the following array. */
1985 int curr_alt_dont_inherit_ops_num
;
1986 /* Numbers of operands whose reload pseudos should not be inherited. */
1987 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1989 /* The register when the operand is a subreg of register, otherwise the
1991 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1992 /* The register if the operand is a register or subreg of register,
1994 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1995 int hard_regno
[MAX_RECOG_OPERANDS
];
1996 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1997 int reload_nregs
, reload_sum
;
2001 /* Calculate some data common for all alternatives to speed up the
2003 for (nop
= 0; nop
< n_operands
; nop
++)
2007 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
2008 /* The real hard regno of the operand after the allocation. */
2009 hard_regno
[nop
] = get_hard_regno (op
, true);
2011 operand_reg
[nop
] = reg
= op
;
2012 biggest_mode
[nop
] = GET_MODE (op
);
2013 if (GET_CODE (op
) == SUBREG
)
2015 biggest_mode
[nop
] = wider_subreg_mode (op
);
2016 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
2019 operand_reg
[nop
] = NULL_RTX
;
2020 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2021 || ((int) REGNO (reg
)
2022 == lra_get_elimination_hard_regno (REGNO (reg
))))
2023 no_subreg_reg_operand
[nop
] = reg
;
2025 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
2026 /* Just use natural mode for elimination result. It should
2027 be enough for extra constraints hooks. */
2028 = regno_reg_rtx
[hard_regno
[nop
]];
2031 /* The constraints are made of several alternatives. Each operand's
2032 constraint looks like foo,bar,... with commas separating the
2033 alternatives. The first alternatives for all operands go
2034 together, the second alternatives go together, etc.
2036 First loop over alternatives. */
2037 alternative_mask preferred
= curr_id
->preferred_alternatives
;
2038 if (only_alternative
>= 0)
2039 preferred
&= ALTERNATIVE_BIT (only_alternative
);
2041 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
2043 /* Loop over operands for one constraint alternative. */
2044 if (!TEST_BIT (preferred
, nalt
))
2047 bool matching_early_clobber
[MAX_RECOG_OPERANDS
];
2048 curr_small_class_check
++;
2049 overall
= losers
= addr_losers
= 0;
2050 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
2051 for (nop
= 0; nop
< n_operands
; nop
++)
2053 int inc
= (curr_static_id
2054 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
2055 if (lra_dump_file
!= NULL
&& inc
!= 0)
2056 fprintf (lra_dump_file
,
2057 " Staticly defined alt reject+=%d\n", inc
);
2058 static_reject
+= inc
;
2059 matching_early_clobber
[nop
] = 0;
2061 reject
+= static_reject
;
2062 early_clobbered_regs_num
= 0;
2064 for (nop
= 0; nop
< n_operands
; nop
++)
2068 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2069 bool win
, did_match
, offmemok
, early_clobber_p
;
2070 /* false => this operand can be reloaded somehow for this
2073 /* true => this operand can be reloaded if the alternative
2076 /* True if a constant forced into memory would be OK for
2079 enum reg_class this_alternative
, this_costly_alternative
;
2080 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2081 bool this_alternative_match_win
, this_alternative_win
;
2082 bool this_alternative_offmemok
;
2085 enum constraint_num cn
;
2087 opalt_num
= nalt
* n_operands
+ nop
;
2088 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2090 /* Fast track for no constraints at all. */
2091 curr_alt
[nop
] = NO_REGS
;
2092 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2093 curr_alt_win
[nop
] = true;
2094 curr_alt_match_win
[nop
] = false;
2095 curr_alt_offmemok
[nop
] = false;
2096 curr_alt_matches
[nop
] = -1;
2100 op
= no_subreg_reg_operand
[nop
];
2101 mode
= curr_operand_mode
[nop
];
2103 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2106 early_clobber_p
= false;
2107 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2109 this_costly_alternative
= this_alternative
= NO_REGS
;
2110 /* We update set of possible hard regs besides its class
2111 because reg class might be inaccurate. For example,
2112 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2113 is translated in HI_REGS because classes are merged by
2114 pairs and there is no accurate intermediate class. */
2115 CLEAR_HARD_REG_SET (this_alternative_set
);
2116 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2117 this_alternative_win
= false;
2118 this_alternative_match_win
= false;
2119 this_alternative_offmemok
= false;
2120 this_alternative_matches
= -1;
2122 /* An empty constraint should be excluded by the fast
2124 lra_assert (*p
!= 0 && *p
!= ',');
2127 /* Scan this alternative's specs for this operand; set WIN
2128 if the operand fits any letter in this alternative.
2129 Otherwise, clear BADOP if this operand could fit some
2130 letter after reloads, or set WINREG if this operand could
2131 fit after reloads provided the constraint allows some
2136 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2146 early_clobber_p
= true;
2150 op_reject
+= LRA_MAX_REJECT
;
2153 op_reject
+= LRA_LOSER_COST_FACTOR
;
2157 /* Ignore rest of this alternative. */
2161 case '0': case '1': case '2': case '3': case '4':
2162 case '5': case '6': case '7': case '8': case '9':
2167 m
= strtoul (p
, &end
, 10);
2170 lra_assert (nop
> m
);
2172 /* Reject matches if we don't know which operand is
2173 bigger. This situation would arguably be a bug in
2174 an .md pattern, but could also occur in a user asm. */
2175 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2176 GET_MODE_SIZE (biggest_mode
[nop
])))
2179 /* Don't match wrong asm insn operands for proper
2180 diagnostic later. */
2181 if (INSN_CODE (curr_insn
) < 0
2182 && (curr_operand_mode
[m
] == BLKmode
2183 || curr_operand_mode
[nop
] == BLKmode
)
2184 && curr_operand_mode
[m
] != curr_operand_mode
[nop
])
2187 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2188 /* We are supposed to match a previous operand.
2189 If we do, we win if that one did. If we do
2190 not, count both of the operands as losers.
2191 (This is too conservative, since most of the
2192 time only a single reload insn will be needed
2193 to make the two operands win. As a result,
2194 this alternative may be rejected when it is
2195 actually desirable.) */
2197 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2198 *curr_id
->operand_loc
[m
], m_hregno
))
2200 /* We should reject matching of an early
2201 clobber operand if the matching operand is
2202 not dying in the insn. */
2203 if (!TEST_BIT (curr_static_id
->operand
[m
]
2204 .early_clobber_alts
, nalt
)
2205 || operand_reg
[nop
] == NULL_RTX
2206 || (find_regno_note (curr_insn
, REG_DEAD
,
2208 || REGNO (op
) == REGNO (operand_reg
[m
])))
2213 /* If we are matching a non-offsettable
2214 address where an offsettable address was
2215 expected, then we must reject this
2216 combination, because we can't reload
2218 if (curr_alt_offmemok
[m
]
2219 && MEM_P (*curr_id
->operand_loc
[m
])
2220 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2225 /* If the operands do not match and one
2226 operand is INOUT, we can not match them.
2227 Try other possibilities, e.g. other
2228 alternatives or commutative operand
2230 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
2231 || curr_static_id
->operand
[m
].type
== OP_INOUT
)
2233 /* Operands don't match. If the operands are
2234 different user defined explicit hard
2235 registers, then we cannot make them match
2236 when one is early clobber operand. */
2237 if ((REG_P (*curr_id
->operand_loc
[nop
])
2238 || SUBREG_P (*curr_id
->operand_loc
[nop
]))
2239 && (REG_P (*curr_id
->operand_loc
[m
])
2240 || SUBREG_P (*curr_id
->operand_loc
[m
])))
2242 rtx nop_reg
= *curr_id
->operand_loc
[nop
];
2243 if (SUBREG_P (nop_reg
))
2244 nop_reg
= SUBREG_REG (nop_reg
);
2245 rtx m_reg
= *curr_id
->operand_loc
[m
];
2246 if (SUBREG_P (m_reg
))
2247 m_reg
= SUBREG_REG (m_reg
);
2250 && HARD_REGISTER_P (nop_reg
)
2251 && REG_USERVAR_P (nop_reg
)
2253 && HARD_REGISTER_P (m_reg
)
2254 && REG_USERVAR_P (m_reg
))
2258 for (i
= 0; i
< early_clobbered_regs_num
; i
++)
2259 if (m
== early_clobbered_nops
[i
])
2261 if (i
< early_clobbered_regs_num
2266 /* Both operands must allow a reload register,
2267 otherwise we cannot make them match. */
2268 if (curr_alt
[m
] == NO_REGS
)
2270 /* Retroactively mark the operand we had to
2271 match as a loser, if it wasn't already and
2272 it wasn't matched to a register constraint
2273 (e.g it might be matched by memory). */
2275 && (operand_reg
[m
] == NULL_RTX
2276 || hard_regno
[m
] < 0))
2280 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2281 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2284 /* Prefer matching earlyclobber alternative as
2285 it results in less hard regs required for
2286 the insn than a non-matching earlyclobber
2288 if (TEST_BIT (curr_static_id
->operand
[m
]
2289 .early_clobber_alts
, nalt
))
2291 if (lra_dump_file
!= NULL
)
2294 " %d Matching earlyclobber alt:"
2297 if (!matching_early_clobber
[m
])
2300 matching_early_clobber
[m
] = 1;
2303 /* Otherwise we prefer no matching
2304 alternatives because it gives more freedom
2306 else if (operand_reg
[nop
] == NULL_RTX
2307 || (find_regno_note (curr_insn
, REG_DEAD
,
2308 REGNO (operand_reg
[nop
]))
2311 if (lra_dump_file
!= NULL
)
2314 " %d Matching alt: reject+=2\n",
2319 /* If we have to reload this operand and some
2320 previous operand also had to match the same
2321 thing as this operand, we don't know how to do
2323 if (!match_p
|| !curr_alt_win
[m
])
2325 for (i
= 0; i
< nop
; i
++)
2326 if (curr_alt_matches
[i
] == m
)
2334 this_alternative_matches
= m
;
2335 /* This can be fixed with reloads if the operand
2336 we are supposed to match can be fixed with
2339 this_alternative
= curr_alt
[m
];
2340 this_alternative_set
= curr_alt_set
[m
];
2341 winreg
= this_alternative
!= NO_REGS
;
2347 || general_constant_p (op
)
2348 || spilled_pseudo_p (op
))
2354 cn
= lookup_constraint (p
);
2355 switch (get_constraint_type (cn
))
2358 cl
= reg_class_for_constraint (cn
);
2364 if (CONST_INT_P (op
)
2365 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2371 && satisfies_memory_constraint_p (op
, cn
))
2373 else if (spilled_pseudo_p (op
))
2376 /* If we didn't already win, we can reload constants
2377 via force_const_mem or put the pseudo value into
2378 memory, or make other memory by reloading the
2379 address like for 'o'. */
2380 if (CONST_POOL_OK_P (mode
, op
)
2381 || MEM_P (op
) || REG_P (op
)
2382 /* We can restore the equiv insn by a
2384 || equiv_substition_p
[nop
])
2391 /* An asm operand with an address constraint
2392 that doesn't satisfy address_operand has
2393 is_address cleared, so that we don't try to
2394 make a non-address fit. */
2395 if (!curr_static_id
->operand
[nop
].is_address
)
2397 /* If we didn't already win, we can reload the address
2398 into a base register. */
2399 if (satisfies_address_constraint_p (op
, cn
))
2401 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2407 if (constraint_satisfied_p (op
, cn
))
2411 case CT_SPECIAL_MEMORY
:
2413 && satisfies_memory_constraint_p (op
, cn
))
2415 else if (spilled_pseudo_p (op
))
2422 if (mode
== BLKmode
)
2424 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2425 this_alternative_set
|= reg_class_contents
[cl
];
2428 this_costly_alternative
2429 = reg_class_subunion
[this_costly_alternative
][cl
];
2430 this_costly_alternative_set
|= reg_class_contents
[cl
];
2435 if (hard_regno
[nop
] >= 0
2436 && in_hard_reg_set_p (this_alternative_set
,
2437 mode
, hard_regno
[nop
]))
2439 else if (hard_regno
[nop
] < 0
2440 && in_class_p (op
, this_alternative
, NULL
))
2445 if (c
!= ' ' && c
!= '\t')
2446 costly_p
= c
== '*';
2448 while ((p
+= len
), c
);
2450 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2451 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2452 /* Record which operands fit this alternative. */
2455 this_alternative_win
= true;
2456 if (operand_reg
[nop
] != NULL_RTX
)
2458 if (hard_regno
[nop
] >= 0)
2460 if (in_hard_reg_set_p (this_costly_alternative_set
,
2461 mode
, hard_regno
[nop
]))
2463 if (lra_dump_file
!= NULL
)
2464 fprintf (lra_dump_file
,
2465 " %d Costly set: reject++\n",
2472 /* Prefer won reg to spilled pseudo under other
2473 equal conditions for possibe inheritance. */
2476 if (lra_dump_file
!= NULL
)
2479 " %d Non pseudo reload: reject++\n",
2483 if (in_class_p (operand_reg
[nop
],
2484 this_costly_alternative
, NULL
))
2486 if (lra_dump_file
!= NULL
)
2489 " %d Non pseudo costly reload:"
2495 /* We simulate the behavior of old reload here.
2496 Although scratches need hard registers and it
2497 might result in spilling other pseudos, no reload
2498 insns are generated for the scratches. So it
2499 might cost something but probably less than old
2500 reload pass believes. */
2503 if (lra_dump_file
!= NULL
)
2504 fprintf (lra_dump_file
,
2505 " %d Scratch win: reject+=2\n",
2512 this_alternative_match_win
= true;
2515 int const_to_mem
= 0;
2518 reject
+= op_reject
;
2519 /* Never do output reload of stack pointer. It makes
2520 impossible to do elimination when SP is changed in
2522 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2523 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2526 /* If this alternative asks for a specific reg class, see if there
2527 is at least one allocatable register in that class. */
2529 = (this_alternative
== NO_REGS
2530 || (hard_reg_set_subset_p
2531 (reg_class_contents
[this_alternative
],
2532 lra_no_alloc_regs
)));
2534 /* For asms, verify that the class for this alternative is possible
2535 for the mode that is specified. */
2536 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2539 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2540 if (targetm
.hard_regno_mode_ok (i
, mode
)
2541 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2544 if (i
== FIRST_PSEUDO_REGISTER
)
2548 /* If this operand accepts a register, and if the
2549 register class has at least one allocatable register,
2550 then this operand can be reloaded. */
2551 if (winreg
&& !no_regs_p
)
2556 if (lra_dump_file
!= NULL
)
2557 fprintf (lra_dump_file
,
2558 " alt=%d: Bad operand -- refuse\n",
2563 if (this_alternative
!= NO_REGS
)
2565 HARD_REG_SET available_regs
2566 = (reg_class_contents
[this_alternative
]
2567 & ~((ira_prohibited_class_mode_regs
2568 [this_alternative
][mode
])
2569 | lra_no_alloc_regs
));
2570 if (hard_reg_set_empty_p (available_regs
))
2572 /* There are no hard regs holding a value of given
2576 this_alternative
= NO_REGS
;
2577 if (lra_dump_file
!= NULL
)
2578 fprintf (lra_dump_file
,
2579 " %d Using memory because of"
2580 " a bad mode: reject+=2\n",
2586 if (lra_dump_file
!= NULL
)
2587 fprintf (lra_dump_file
,
2588 " alt=%d: Wrong mode -- refuse\n",
2595 /* If not assigned pseudo has a class which a subset of
2596 required reg class, it is a less costly alternative
2597 as the pseudo still can get a hard reg of necessary
2599 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2600 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2601 && ira_class_subset_p
[this_alternative
][cl
])
2603 if (lra_dump_file
!= NULL
)
2606 " %d Super set class reg: reject-=3\n", nop
);
2610 this_alternative_offmemok
= offmemok
;
2611 if (this_costly_alternative
!= NO_REGS
)
2613 if (lra_dump_file
!= NULL
)
2614 fprintf (lra_dump_file
,
2615 " %d Costly loser: reject++\n", nop
);
2618 /* If the operand is dying, has a matching constraint,
2619 and satisfies constraints of the matched operand
2620 which failed to satisfy the own constraints, most probably
2621 the reload for this operand will be gone. */
2622 if (this_alternative_matches
>= 0
2623 && !curr_alt_win
[this_alternative_matches
]
2625 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2626 && (hard_regno
[nop
] >= 0
2627 ? in_hard_reg_set_p (this_alternative_set
,
2628 mode
, hard_regno
[nop
])
2629 : in_class_p (op
, this_alternative
, NULL
)))
2631 if (lra_dump_file
!= NULL
)
2634 " %d Dying matched operand reload: reject++\n",
2640 /* Strict_low_part requires to reload the register
2641 not the sub-register. In this case we should
2642 check that a final reload hard reg can hold the
2644 if (curr_static_id
->operand
[nop
].strict_low
2646 && hard_regno
[nop
] < 0
2647 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2648 && ira_class_hard_regs_num
[this_alternative
] > 0
2649 && (!targetm
.hard_regno_mode_ok
2650 (ira_class_hard_regs
[this_alternative
][0],
2651 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2653 if (lra_dump_file
!= NULL
)
2656 " alt=%d: Strict low subreg reload -- refuse\n",
2662 if (operand_reg
[nop
] != NULL_RTX
2663 /* Output operands and matched input operands are
2664 not inherited. The following conditions do not
2665 exactly describe the previous statement but they
2666 are pretty close. */
2667 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2668 && (this_alternative_matches
< 0
2669 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2671 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2675 /* The value of reload_sum has sense only if we
2676 process insns in their order. It happens only on
2677 the first constraints sub-pass when we do most of
2679 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2680 reload_sum
+= last_reload
- bb_reload_num
;
2682 /* If this is a constant that is reloaded into the
2683 desired class by copying it to memory first, count
2684 that as another reload. This is consistent with
2685 other code and is required to avoid choosing another
2686 alternative when the constant is moved into memory.
2687 Note that the test here is precisely the same as in
2688 the code below that calls force_const_mem. */
2689 if (CONST_POOL_OK_P (mode
, op
)
2690 && ((targetm
.preferred_reload_class
2691 (op
, this_alternative
) == NO_REGS
)
2692 || no_input_reloads_p
))
2699 /* Alternative loses if it requires a type of reload not
2700 permitted for this insn. We can always reload
2701 objects with a REG_UNUSED note. */
2702 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2703 && no_output_reloads_p
2704 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2705 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2706 && no_input_reloads_p
&& ! const_to_mem
)
2707 || (this_alternative_matches
>= 0
2708 && (no_input_reloads_p
2709 || (no_output_reloads_p
2710 && (curr_static_id
->operand
2711 [this_alternative_matches
].type
!= OP_IN
)
2712 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2713 no_subreg_reg_operand
2714 [this_alternative_matches
])))))
2716 if (lra_dump_file
!= NULL
)
2719 " alt=%d: No input/otput reload -- refuse\n",
2724 /* Alternative loses if it required class pseudo cannot
2725 hold value of required mode. Such insns can be
2726 described by insn definitions with mode iterators. */
2727 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2728 && ! hard_reg_set_empty_p (this_alternative_set
)
2729 /* It is common practice for constraints to use a
2730 class which does not have actually enough regs to
2731 hold the value (e.g. x86 AREG for mode requiring
2732 more one general reg). Therefore we have 2
2733 conditions to check that the reload pseudo cannot
2734 hold the mode value. */
2735 && (!targetm
.hard_regno_mode_ok
2736 (ira_class_hard_regs
[this_alternative
][0],
2737 GET_MODE (*curr_id
->operand_loc
[nop
])))
2738 /* The above condition is not enough as the first
2739 reg in ira_class_hard_regs can be not aligned for
2740 multi-words mode values. */
2741 && (prohibited_class_reg_set_mode_p
2742 (this_alternative
, this_alternative_set
,
2743 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2745 if (lra_dump_file
!= NULL
)
2746 fprintf (lra_dump_file
,
2747 " alt=%d: reload pseudo for op %d "
2748 "cannot hold the mode value -- refuse\n",
2753 /* Check strong discouragement of reload of non-constant
2754 into class THIS_ALTERNATIVE. */
2755 if (! CONSTANT_P (op
) && ! no_regs_p
2756 && (targetm
.preferred_reload_class
2757 (op
, this_alternative
) == NO_REGS
2758 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2759 && (targetm
.preferred_output_reload_class
2760 (op
, this_alternative
) == NO_REGS
))))
2762 if (offmemok
&& REG_P (op
))
2764 if (lra_dump_file
!= NULL
)
2767 " %d Spill pseudo into memory: reject+=3\n",
2773 if (lra_dump_file
!= NULL
)
2776 " %d Non-prefered reload: reject+=%d\n",
2777 nop
, LRA_MAX_REJECT
);
2778 reject
+= LRA_MAX_REJECT
;
2782 if (! (MEM_P (op
) && offmemok
)
2783 && ! (const_to_mem
&& constmemok
))
2785 /* We prefer to reload pseudos over reloading other
2786 things, since such reloads may be able to be
2787 eliminated later. So bump REJECT in other cases.
2788 Don't do this in the case where we are forcing a
2789 constant into memory and it will then win since
2790 we don't want to have a different alternative
2792 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2794 if (lra_dump_file
!= NULL
)
2797 " %d Non-pseudo reload: reject+=2\n",
2804 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2806 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2808 if (lra_dump_file
!= NULL
)
2811 " %d Small class reload: reject+=%d\n",
2812 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2813 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2817 /* We are trying to spill pseudo into memory. It is
2818 usually more costly than moving to a hard register
2819 although it might takes the same number of
2822 Non-pseudo spill may happen also. Suppose a target allows both
2823 register and memory in the operand constraint alternatives,
2824 then it's typical that an eliminable register has a substition
2825 of "base + offset" which can either be reloaded by a simple
2826 "new_reg <= base + offset" which will match the register
2827 constraint, or a similar reg addition followed by further spill
2828 to and reload from memory which will match the memory
2829 constraint, but this memory spill will be much more costly
2832 Code below increases the reject for both pseudo and non-pseudo
2835 && !(MEM_P (op
) && offmemok
)
2836 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2838 if (lra_dump_file
!= NULL
)
2841 " %d Spill %spseudo into memory: reject+=3\n",
2842 nop
, REG_P (op
) ? "" : "Non-");
2844 if (VECTOR_MODE_P (mode
))
2846 /* Spilling vectors into memory is usually more
2847 costly as they contain big values. */
2848 if (lra_dump_file
!= NULL
)
2851 " %d Spill vector pseudo: reject+=2\n",
2857 /* When we use an operand requiring memory in given
2858 alternative, the insn should write *and* read the
2859 value to/from memory it is costly in comparison with
2860 an insn alternative which does not use memory
2861 (e.g. register or immediate operand). We exclude
2862 memory operand for such case as we can satisfy the
2863 memory constraints by reloading address. */
2864 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
2866 if (lra_dump_file
!= NULL
)
2869 " Using memory insn operand %d: reject+=3\n",
2874 /* If reload requires moving value through secondary
2875 memory, it will need one more insn at least. */
2876 if (this_alternative
!= NO_REGS
2877 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2878 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2879 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
2881 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2882 && (targetm
.secondary_memory_needed
2883 (GET_MODE (op
), this_alternative
, cl
)))))
2886 if (MEM_P (op
) && offmemok
)
2890 /* Input reloads can be inherited more often than
2891 output reloads can be removed, so penalize output
2893 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2895 if (lra_dump_file
!= NULL
)
2898 " %d Non input pseudo reload: reject++\n",
2903 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
2905 if (lra_dump_file
!= NULL
)
2908 " %d Input/Output reload: reject+=%d\n",
2909 nop
, LRA_LOSER_COST_FACTOR
);
2910 reject
+= LRA_LOSER_COST_FACTOR
;
2915 if (early_clobber_p
&& ! scratch_p
)
2917 if (lra_dump_file
!= NULL
)
2918 fprintf (lra_dump_file
,
2919 " %d Early clobber: reject++\n", nop
);
2922 /* ??? We check early clobbers after processing all operands
2923 (see loop below) and there we update the costs more.
2924 Should we update the cost (may be approximately) here
2925 because of early clobber register reloads or it is a rare
2926 or non-important thing to be worth to do it. */
2927 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
2928 - (addr_losers
== losers
? static_reject
: 0));
2929 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2931 if (lra_dump_file
!= NULL
)
2932 fprintf (lra_dump_file
,
2933 " alt=%d,overall=%d,losers=%d -- refuse\n",
2934 nalt
, overall
, losers
);
2938 if (update_and_check_small_class_inputs (nop
, nalt
,
2941 if (lra_dump_file
!= NULL
)
2942 fprintf (lra_dump_file
,
2943 " alt=%d, not enough small class regs -- refuse\n",
2947 curr_alt
[nop
] = this_alternative
;
2948 curr_alt_set
[nop
] = this_alternative_set
;
2949 curr_alt_win
[nop
] = this_alternative_win
;
2950 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2951 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2952 curr_alt_matches
[nop
] = this_alternative_matches
;
2954 if (this_alternative_matches
>= 0
2955 && !did_match
&& !this_alternative_win
)
2956 curr_alt_win
[this_alternative_matches
] = false;
2958 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2959 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2962 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2963 /* Prevent processing non-move insns. */
2964 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2965 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2966 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2967 && REG_P (no_subreg_reg_operand
[0])
2968 && REG_P (no_subreg_reg_operand
[1])
2969 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2970 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2971 || (! curr_alt_win
[0] && curr_alt_win
[1]
2972 && REG_P (no_subreg_reg_operand
[1])
2973 /* Check that we reload memory not the memory
2975 && ! (curr_alt_offmemok
[0]
2976 && MEM_P (no_subreg_reg_operand
[0]))
2977 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2978 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2979 && REG_P (no_subreg_reg_operand
[0])
2980 /* Check that we reload memory not the memory
2982 && ! (curr_alt_offmemok
[1]
2983 && MEM_P (no_subreg_reg_operand
[1]))
2984 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2985 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2986 no_subreg_reg_operand
[1])
2987 || (targetm
.preferred_reload_class
2988 (no_subreg_reg_operand
[1],
2989 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2990 /* If it is a result of recent elimination in move
2991 insn we can transform it into an add still by
2992 using this alternative. */
2993 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
2994 /* Likewise if the source has been replaced with an
2995 equivalent value. This only happens once -- the reload
2996 will use the equivalent value instead of the register it
2997 replaces -- so there should be no danger of cycling. */
2998 && !equiv_substition_p
[1])))
3000 /* We have a move insn and a new reload insn will be similar
3001 to the current insn. We should avoid such situation as
3002 it results in LRA cycling. */
3003 if (lra_dump_file
!= NULL
)
3004 fprintf (lra_dump_file
,
3005 " Cycle danger: overall += LRA_MAX_REJECT\n");
3006 overall
+= LRA_MAX_REJECT
;
3009 curr_alt_dont_inherit_ops_num
= 0;
3010 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
3012 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
3013 HARD_REG_SET temp_set
;
3015 i
= early_clobbered_nops
[nop
];
3016 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
3017 || hard_regno
[i
] < 0)
3019 lra_assert (operand_reg
[i
] != NULL_RTX
);
3020 clobbered_hard_regno
= hard_regno
[i
];
3021 CLEAR_HARD_REG_SET (temp_set
);
3022 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
3023 first_conflict_j
= last_conflict_j
= -1;
3024 for (j
= 0; j
< n_operands
; j
++)
3026 /* We don't want process insides of match_operator and
3027 match_parallel because otherwise we would process
3028 their operands once again generating a wrong
3030 || curr_static_id
->operand
[j
].is_operator
)
3032 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
3033 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
3035 /* If we don't reload j-th operand, check conflicts. */
3036 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
3037 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
3039 if (first_conflict_j
< 0)
3040 first_conflict_j
= j
;
3041 last_conflict_j
= j
;
3042 /* Both the earlyclobber operand and conflicting operand
3043 cannot both be user defined hard registers. */
3044 if (HARD_REGISTER_P (operand_reg
[i
])
3045 && REG_USERVAR_P (operand_reg
[i
])
3046 && operand_reg
[j
] != NULL_RTX
3047 && HARD_REGISTER_P (operand_reg
[j
])
3048 && REG_USERVAR_P (operand_reg
[j
]))
3049 fatal_insn ("unable to generate reloads for "
3050 "impossible constraints:", curr_insn
);
3052 if (last_conflict_j
< 0)
3055 /* If an earlyclobber operand conflicts with another non-matching
3056 operand (ie, they have been assigned the same hard register),
3057 then it is better to reload the other operand, as there may
3058 exist yet another operand with a matching constraint associated
3059 with the earlyclobber operand. However, if one of the operands
3060 is an explicit use of a hard register, then we must reload the
3061 other non-hard register operand. */
3062 if (HARD_REGISTER_P (operand_reg
[i
])
3063 || (first_conflict_j
== last_conflict_j
3064 && operand_reg
[last_conflict_j
] != NULL_RTX
3065 && !curr_alt_match_win
[last_conflict_j
]
3066 && !HARD_REGISTER_P (operand_reg
[last_conflict_j
])))
3068 curr_alt_win
[last_conflict_j
] = false;
3069 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
3072 if (lra_dump_file
!= NULL
)
3075 " %d Conflict early clobber reload: reject--\n",
3080 /* We need to reload early clobbered register and the
3081 matched registers. */
3082 for (j
= 0; j
< n_operands
; j
++)
3083 if (curr_alt_matches
[j
] == i
)
3085 curr_alt_match_win
[j
] = false;
3087 overall
+= LRA_LOSER_COST_FACTOR
;
3089 if (! curr_alt_match_win
[i
])
3090 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
3093 /* Remember pseudos used for match reloads are never
3095 lra_assert (curr_alt_matches
[i
] >= 0);
3096 curr_alt_win
[curr_alt_matches
[i
]] = false;
3098 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
3100 if (lra_dump_file
!= NULL
)
3103 " %d Matched conflict early clobber reloads: "
3107 /* Early clobber was already reflected in REJECT. */
3108 if (!matching_early_clobber
[i
])
3110 lra_assert (reject
> 0);
3112 matching_early_clobber
[i
] = 1;
3114 overall
+= LRA_LOSER_COST_FACTOR
- 1;
3116 if (lra_dump_file
!= NULL
)
3117 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
3118 nalt
, overall
, losers
, reload_nregs
);
3120 /* If this alternative can be made to work by reloading, and it
3121 needs less reloading than the others checked so far, record
3122 it as the chosen goal for reloading. */
3123 if ((best_losers
!= 0 && losers
== 0)
3124 || (((best_losers
== 0 && losers
== 0)
3125 || (best_losers
!= 0 && losers
!= 0))
3126 && (best_overall
> overall
3127 || (best_overall
== overall
3128 /* If the cost of the reloads is the same,
3129 prefer alternative which requires minimal
3130 number of reload regs. */
3131 && (reload_nregs
< best_reload_nregs
3132 || (reload_nregs
== best_reload_nregs
3133 && (best_reload_sum
< reload_sum
3134 || (best_reload_sum
== reload_sum
3135 && nalt
< goal_alt_number
))))))))
3137 for (nop
= 0; nop
< n_operands
; nop
++)
3139 goal_alt_win
[nop
] = curr_alt_win
[nop
];
3140 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
3141 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
3142 goal_alt
[nop
] = curr_alt
[nop
];
3143 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3145 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3146 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3147 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3148 goal_alt_swapped
= curr_swapped
;
3149 best_overall
= overall
;
3150 best_losers
= losers
;
3151 best_reload_nregs
= reload_nregs
;
3152 best_reload_sum
= reload_sum
;
3153 goal_alt_number
= nalt
;
3156 /* Everything is satisfied. Do not process alternatives
3165 /* Make reload base reg from address AD. */
3167 base_to_reg (struct address_info
*ad
)
3171 rtx new_inner
= NULL_RTX
;
3172 rtx new_reg
= NULL_RTX
;
3174 rtx_insn
*last_insn
= get_last_insn();
3176 lra_assert (ad
->disp
== ad
->disp_term
);
3177 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3178 get_index_code (ad
));
3179 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
,
3181 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3182 ad
->disp_term
== NULL
3185 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3187 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3188 code
= recog_memoized (insn
);
3191 delete_insns_since (last_insn
);
3198 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3200 base_plus_disp_to_reg (struct address_info
*ad
, rtx disp
)
3205 lra_assert (ad
->base
== ad
->base_term
);
3206 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3207 get_index_code (ad
));
3208 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
3210 lra_emit_add (new_reg
, *ad
->base_term
, disp
);
3214 /* Make reload of index part of address AD. Return the new
3217 index_part_to_reg (struct address_info
*ad
)
3221 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3222 INDEX_REG_CLASS
, "index term");
3223 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3224 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3228 /* Return true if we can add a displacement to address AD, even if that
3229 makes the address invalid. The fix-up code requires any new address
3230 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3232 can_add_disp_p (struct address_info
*ad
)
3234 return (!ad
->autoinc_p
3235 && ad
->segment
== NULL
3236 && ad
->base
== ad
->base_term
3237 && ad
->disp
== ad
->disp_term
);
3240 /* Make equiv substitution in address AD. Return true if a substitution
3243 equiv_address_substitution (struct address_info
*ad
)
3245 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3247 HOST_WIDE_INT scale
;
3250 base_term
= strip_subreg (ad
->base_term
);
3251 if (base_term
== NULL
)
3252 base_reg
= new_base_reg
= NULL_RTX
;
3255 base_reg
= *base_term
;
3256 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3258 index_term
= strip_subreg (ad
->index_term
);
3259 if (index_term
== NULL
)
3260 index_reg
= new_index_reg
= NULL_RTX
;
3263 index_reg
= *index_term
;
3264 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3266 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3270 if (lra_dump_file
!= NULL
)
3272 fprintf (lra_dump_file
, "Changing address in insn %d ",
3273 INSN_UID (curr_insn
));
3274 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3276 if (base_reg
!= new_base_reg
)
3279 if (REG_P (new_base_reg
))
3281 *base_term
= new_base_reg
;
3284 else if (GET_CODE (new_base_reg
) == PLUS
3285 && REG_P (XEXP (new_base_reg
, 0))
3286 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3287 && can_add_disp_p (ad
))
3290 *base_term
= XEXP (new_base_reg
, 0);
3293 if (ad
->base_term2
!= NULL
)
3294 *ad
->base_term2
= *ad
->base_term
;
3296 if (index_reg
!= new_index_reg
)
3299 if (REG_P (new_index_reg
))
3301 *index_term
= new_index_reg
;
3304 else if (GET_CODE (new_index_reg
) == PLUS
3305 && REG_P (XEXP (new_index_reg
, 0))
3306 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3307 && can_add_disp_p (ad
)
3308 && (scale
= get_index_scale (ad
)))
3310 disp
+= offset
* scale
;
3311 *index_term
= XEXP (new_index_reg
, 0);
3315 if (maybe_ne (disp
, 0))
3317 if (ad
->disp
!= NULL
)
3318 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3321 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3322 update_address (ad
);
3326 if (lra_dump_file
!= NULL
)
3329 fprintf (lra_dump_file
, " -- no change\n");
3332 fprintf (lra_dump_file
, " on equiv ");
3333 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3334 fprintf (lra_dump_file
, "\n");
3340 /* Major function to make reloads for an address in operand NOP or
3341 check its correctness (If CHECK_ONLY_P is true). The supported
3344 1) an address that existed before LRA started, at which point it
3345 must have been valid. These addresses are subject to elimination
3346 and may have become invalid due to the elimination offset being out
3349 2) an address created by forcing a constant to memory
3350 (force_const_to_mem). The initial form of these addresses might
3351 not be valid, and it is this function's job to make them valid.
3353 3) a frame address formed from a register and a (possibly zero)
3354 constant offset. As above, these addresses might not be valid and
3355 this function must make them so.
3357 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3358 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3359 address. Return true for any RTL change.
3361 The function is a helper function which does not produce all
3362 transformations (when CHECK_ONLY_P is false) which can be
3363 necessary. It does just basic steps. To do all necessary
3364 transformations use function process_address. */
3366 process_address_1 (int nop
, bool check_only_p
,
3367 rtx_insn
**before
, rtx_insn
**after
)
3369 struct address_info ad
;
3371 HOST_WIDE_INT scale
;
3372 rtx op
= *curr_id
->operand_loc
[nop
];
3373 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3374 enum constraint_num cn
= lookup_constraint (constraint
);
3375 bool change_p
= false;
3378 && GET_MODE (op
) == BLKmode
3379 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3382 if (insn_extra_address_constraint (cn
)
3383 /* When we find an asm operand with an address constraint that
3384 doesn't satisfy address_operand to begin with, we clear
3385 is_address, so that we don't try to make a non-address fit.
3386 If the asm statement got this far, it's because other
3387 constraints are available, and we'll use them, disregarding
3388 the unsatisfiable address ones. */
3389 && curr_static_id
->operand
[nop
].is_address
)
3390 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3391 /* Do not attempt to decompose arbitrary addresses generated by combine
3392 for asm operands with loose constraints, e.g 'X'. */
3394 && !(INSN_CODE (curr_insn
) < 0
3395 && get_constraint_type (cn
) == CT_FIXED_FORM
3396 && constraint_satisfied_p (op
, cn
)))
3397 decompose_mem_address (&ad
, op
);
3398 else if (GET_CODE (op
) == SUBREG
3399 && MEM_P (SUBREG_REG (op
)))
3400 decompose_mem_address (&ad
, SUBREG_REG (op
));
3403 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3404 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3405 when INDEX_REG_CLASS is a single register class. */
3406 if (ad
.base_term
!= NULL
3407 && ad
.index_term
!= NULL
3408 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3409 && REG_P (*ad
.base_term
)
3410 && REG_P (*ad
.index_term
)
3411 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3412 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3414 std::swap (ad
.base
, ad
.index
);
3415 std::swap (ad
.base_term
, ad
.index_term
);
3418 change_p
= equiv_address_substitution (&ad
);
3419 if (ad
.base_term
!= NULL
3420 && (process_addr_reg
3421 (ad
.base_term
, check_only_p
, before
,
3423 && !(REG_P (*ad
.base_term
)
3424 && find_regno_note (curr_insn
, REG_DEAD
,
3425 REGNO (*ad
.base_term
)) != NULL_RTX
)
3427 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3428 get_index_code (&ad
)))))
3431 if (ad
.base_term2
!= NULL
)
3432 *ad
.base_term2
= *ad
.base_term
;
3434 if (ad
.index_term
!= NULL
3435 && process_addr_reg (ad
.index_term
, check_only_p
,
3436 before
, NULL
, INDEX_REG_CLASS
))
3439 /* Target hooks sometimes don't treat extra-constraint addresses as
3440 legitimate address_operands, so handle them specially. */
3441 if (insn_extra_address_constraint (cn
)
3442 && satisfies_address_constraint_p (&ad
, cn
))
3448 /* There are three cases where the shape of *AD.INNER may now be invalid:
3450 1) the original address was valid, but either elimination or
3451 equiv_address_substitution was applied and that made
3452 the address invalid.
3454 2) the address is an invalid symbolic address created by
3457 3) the address is a frame address with an invalid offset.
3459 4) the address is a frame address with an invalid base.
3461 All these cases involve a non-autoinc address, so there is no
3462 point revalidating other types. */
3463 if (ad
.autoinc_p
|| valid_address_p (op
, &ad
, cn
))
3466 /* Any index existed before LRA started, so we can assume that the
3467 presence and shape of the index is valid. */
3468 push_to_sequence (*before
);
3469 lra_assert (ad
.disp
== ad
.disp_term
);
3470 if (ad
.base
== NULL
)
3472 if (ad
.index
== NULL
)
3475 rtx_insn
*last
= get_last_insn ();
3477 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3479 rtx addr
= *ad
.inner
;
3481 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3484 /* addr => lo_sum (new_base, addr), case (2) above. */
3485 insn
= emit_insn (gen_rtx_SET
3487 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3488 code
= recog_memoized (insn
);
3491 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3492 if (!valid_address_p (op
, &ad
, cn
))
3494 /* Try to put lo_sum into register. */
3495 insn
= emit_insn (gen_rtx_SET
3497 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3498 code
= recog_memoized (insn
);
3501 *ad
.inner
= new_reg
;
3502 if (!valid_address_p (op
, &ad
, cn
))
3512 delete_insns_since (last
);
3517 /* addr => new_base, case (2) above. */
3518 lra_emit_move (new_reg
, addr
);
3520 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3522 insn
= NEXT_INSN (insn
))
3523 if (recog_memoized (insn
) < 0)
3525 if (insn
!= NULL_RTX
)
3527 /* Do nothing if we cannot generate right insns.
3528 This is analogous to reload pass behavior. */
3529 delete_insns_since (last
);
3533 *ad
.inner
= new_reg
;
3538 /* index * scale + disp => new base + index * scale,
3540 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3541 GET_CODE (*ad
.index
));
3543 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3544 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3545 lra_emit_move (new_reg
, *ad
.disp
);
3546 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3547 new_reg
, *ad
.index
);
3550 else if (ad
.index
== NULL
)
3555 rtx_insn
*insns
, *last_insn
;
3556 /* Try to reload base into register only if the base is invalid
3557 for the address but with valid offset, case (4) above. */
3559 new_reg
= base_to_reg (&ad
);
3561 /* base + disp => new base, cases (1) and (3) above. */
3562 /* Another option would be to reload the displacement into an
3563 index register. However, postreload has code to optimize
3564 address reloads that have the same base and different
3565 displacements, so reloading into an index register would
3566 not necessarily be a win. */
3567 if (new_reg
== NULL_RTX
)
3569 /* See if the target can split the displacement into a
3570 legitimate new displacement from a local anchor. */
3571 gcc_assert (ad
.disp
== ad
.disp_term
);
3572 poly_int64 orig_offset
;
3573 rtx offset1
, offset2
;
3574 if (poly_int_rtx_p (*ad
.disp
, &orig_offset
)
3575 && targetm
.legitimize_address_displacement (&offset1
, &offset2
,
3579 new_reg
= base_plus_disp_to_reg (&ad
, offset1
);
3580 new_reg
= gen_rtx_PLUS (GET_MODE (new_reg
), new_reg
, offset2
);
3583 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3585 insns
= get_insns ();
3586 last_insn
= get_last_insn ();
3587 /* If we generated at least two insns, try last insn source as
3588 an address. If we succeed, we generate one less insn. */
3590 && last_insn
!= insns
3591 && (set
= single_set (last_insn
)) != NULL_RTX
3592 && GET_CODE (SET_SRC (set
)) == PLUS
3593 && REG_P (XEXP (SET_SRC (set
), 0))
3594 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3596 *ad
.inner
= SET_SRC (set
);
3597 if (valid_address_p (op
, &ad
, cn
))
3599 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3600 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3601 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3602 get_index_code (&ad
));
3603 regno
= REGNO (*ad
.base_term
);
3604 if (regno
>= FIRST_PSEUDO_REGISTER
3605 && cl
!= lra_get_allocno_class (regno
))
3606 lra_change_class (regno
, cl
, " Change to", true);
3607 new_reg
= SET_SRC (set
);
3608 delete_insns_since (PREV_INSN (last_insn
));
3613 *ad
.inner
= new_reg
;
3615 else if (ad
.disp_term
!= NULL
)
3617 /* base + scale * index + disp => new base + scale * index,
3619 gcc_assert (ad
.disp
== ad
.disp_term
);
3620 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3621 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3622 new_reg
, *ad
.index
);
3624 else if ((scale
= get_index_scale (&ad
)) == 1)
3626 /* The last transformation to one reg will be made in
3627 curr_insn_transform function. */
3631 else if (scale
!= 0)
3633 /* base + scale * index => base + new_reg,
3635 Index part of address may become invalid. For example, we
3636 changed pseudo on the equivalent memory and a subreg of the
3637 pseudo onto the memory of different mode for which the scale is
3639 new_reg
= index_part_to_reg (&ad
);
3640 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3641 *ad
.base_term
, new_reg
);
3645 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3647 rtx addr
= *ad
.inner
;
3649 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3650 /* addr => new_base. */
3651 lra_emit_move (new_reg
, addr
);
3652 *ad
.inner
= new_reg
;
3654 *before
= get_insns ();
3659 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3660 Use process_address_1 as a helper function. Return true for any
3663 If CHECK_ONLY_P is true, just check address correctness. Return
3664 false if the address correct. */
3666 process_address (int nop
, bool check_only_p
,
3667 rtx_insn
**before
, rtx_insn
**after
)
3671 while (process_address_1 (nop
, check_only_p
, before
, after
))
3680 /* Emit insns to reload VALUE into a new register. VALUE is an
3681 auto-increment or auto-decrement RTX whose operand is a register or
3682 memory location; so reloading involves incrementing that location.
3683 IN is either identical to VALUE, or some cheaper place to reload
3684 value being incremented/decremented from.
3686 INC_AMOUNT is the number to increment or decrement by (always
3687 positive and ignored for POST_MODIFY/PRE_MODIFY).
3689 Return pseudo containing the result. */
3691 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, poly_int64 inc_amount
)
3693 /* REG or MEM to be copied and incremented. */
3694 rtx incloc
= XEXP (value
, 0);
3695 /* Nonzero if increment after copying. */
3696 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3697 || GET_CODE (value
) == POST_MODIFY
);
3702 rtx real_in
= in
== value
? incloc
: in
;
3706 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3708 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3709 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3710 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3711 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3712 inc
= XEXP (XEXP (value
, 1), 1);
3716 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3717 inc_amount
= -inc_amount
;
3719 inc
= gen_int_mode (inc_amount
, GET_MODE (value
));
3722 if (! post
&& REG_P (incloc
))
3725 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3728 if (real_in
!= result
)
3730 /* First copy the location to the result register. */
3731 lra_assert (REG_P (result
));
3732 emit_insn (gen_move_insn (result
, real_in
));
3735 /* We suppose that there are insns to add/sub with the constant
3736 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3737 old reload worked with this assumption. If the assumption
3738 becomes wrong, we should use approach in function
3739 base_plus_disp_to_reg. */
3742 /* See if we can directly increment INCLOC. */
3743 last
= get_last_insn ();
3744 add_insn
= emit_insn (plus_p
3745 ? gen_add2_insn (incloc
, inc
)
3746 : gen_sub2_insn (incloc
, inc
));
3748 code
= recog_memoized (add_insn
);
3751 if (! post
&& result
!= incloc
)
3752 emit_insn (gen_move_insn (result
, incloc
));
3755 delete_insns_since (last
);
3758 /* If couldn't do the increment directly, must increment in RESULT.
3759 The way we do this depends on whether this is pre- or
3760 post-increment. For pre-increment, copy INCLOC to the reload
3761 register, increment it there, then save back. */
3764 if (real_in
!= result
)
3765 emit_insn (gen_move_insn (result
, real_in
));
3767 emit_insn (gen_add2_insn (result
, inc
));
3769 emit_insn (gen_sub2_insn (result
, inc
));
3770 if (result
!= incloc
)
3771 emit_insn (gen_move_insn (incloc
, result
));
3777 Because this might be a jump insn or a compare, and because
3778 RESULT may not be available after the insn in an input
3779 reload, we must do the incrementing before the insn being
3782 We have already copied IN to RESULT. Increment the copy in
3783 RESULT, save that back, then decrement RESULT so it has
3784 the original value. */
3786 emit_insn (gen_add2_insn (result
, inc
));
3788 emit_insn (gen_sub2_insn (result
, inc
));
3789 emit_insn (gen_move_insn (incloc
, result
));
3790 /* Restore non-modified value for the result. We prefer this
3791 way because it does not require an additional hard
3796 if (poly_int_rtx_p (inc
, &offset
))
3797 emit_insn (gen_add2_insn (result
,
3798 gen_int_mode (-offset
,
3799 GET_MODE (result
))));
3801 emit_insn (gen_sub2_insn (result
, inc
));
3804 emit_insn (gen_add2_insn (result
, inc
));
3809 /* Return true if the current move insn does not need processing as we
3810 already know that it satisfies its constraints. */
3812 simple_move_p (void)
3815 enum reg_class dclass
, sclass
;
3817 lra_assert (curr_insn_set
!= NULL_RTX
);
3818 dest
= SET_DEST (curr_insn_set
);
3819 src
= SET_SRC (curr_insn_set
);
3821 /* If the instruction has multiple sets we need to process it even if it
3822 is single_set. This can happen if one or more of the SETs are dead.
3824 if (multiple_sets (curr_insn
))
3827 return ((dclass
= get_op_class (dest
)) != NO_REGS
3828 && (sclass
= get_op_class (src
)) != NO_REGS
3829 /* The backend guarantees that register moves of cost 2
3830 never need reloads. */
3831 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3834 /* Swap operands NOP and NOP + 1. */
3836 swap_operands (int nop
)
3838 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3839 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3840 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3841 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3842 /* Swap the duplicates too. */
3843 lra_update_dup (curr_id
, nop
);
3844 lra_update_dup (curr_id
, nop
+ 1);
3847 /* Main entry point of the constraint code: search the body of the
3848 current insn to choose the best alternative. It is mimicking insn
3849 alternative cost calculation model of former reload pass. That is
3850 because machine descriptions were written to use this model. This
3851 model can be changed in future. Make commutative operand exchange
3854 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3855 constraints. Return true if any change happened during function
3858 If CHECK_ONLY_P is true then don't do any transformation. Just
3859 check that the insn satisfies all constraints. If the insn does
3860 not satisfy any constraint, return true. */
3862 curr_insn_transform (bool check_only_p
)
3869 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3870 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3871 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3872 rtx_insn
*before
, *after
;
3874 /* Flag that the insn has been changed through a transformation. */
3878 int max_regno_before
;
3879 int reused_alternative_num
;
3881 curr_insn_set
= single_set (curr_insn
);
3882 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3884 /* We assume that the corresponding insn alternative has no
3885 earlier clobbers. If it is not the case, don't define move
3886 cost equal to 2 for the corresponding register classes. */
3887 lra_set_used_insn_alternative (curr_insn
, LRA_NON_CLOBBERED_ALT
);
3891 no_input_reloads_p
= no_output_reloads_p
= false;
3892 goal_alt_number
= -1;
3893 change_p
= sec_mem_p
= false;
3894 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3895 reloads; neither are insns that SET cc0. Insns that use CC0 are
3896 not allowed to have any input reloads. */
3897 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3898 no_output_reloads_p
= true;
3900 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3901 no_input_reloads_p
= true;
3902 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3903 no_output_reloads_p
= true;
3905 n_operands
= curr_static_id
->n_operands
;
3906 n_alternatives
= curr_static_id
->n_alternatives
;
3908 /* Just return "no reloads" if insn has no operands with
3910 if (n_operands
== 0 || n_alternatives
== 0)
3913 max_regno_before
= max_reg_num ();
3915 for (i
= 0; i
< n_operands
; i
++)
3917 goal_alt_matched
[i
][0] = -1;
3918 goal_alt_matches
[i
] = -1;
3921 commutative
= curr_static_id
->commutative
;
3923 /* Now see what we need for pseudos that didn't get hard regs or got
3924 the wrong kind of hard reg. For this, we must consider all the
3925 operands together against the register constraints. */
3927 best_losers
= best_overall
= INT_MAX
;
3928 best_reload_sum
= 0;
3930 curr_swapped
= false;
3931 goal_alt_swapped
= false;
3934 /* Make equivalence substitution and memory subreg elimination
3935 before address processing because an address legitimacy can
3936 depend on memory mode. */
3937 for (i
= 0; i
< n_operands
; i
++)
3940 bool op_change_p
= false;
3942 if (curr_static_id
->operand
[i
].is_operator
)
3945 old
= op
= *curr_id
->operand_loc
[i
];
3946 if (GET_CODE (old
) == SUBREG
)
3947 old
= SUBREG_REG (old
);
3948 subst
= get_equiv_with_elimination (old
, curr_insn
);
3949 original_subreg_reg_mode
[i
] = VOIDmode
;
3950 equiv_substition_p
[i
] = false;
3953 equiv_substition_p
[i
] = true;
3954 subst
= copy_rtx (subst
);
3955 lra_assert (REG_P (old
));
3956 if (GET_CODE (op
) != SUBREG
)
3957 *curr_id
->operand_loc
[i
] = subst
;
3960 SUBREG_REG (op
) = subst
;
3961 if (GET_MODE (subst
) == VOIDmode
)
3962 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3964 if (lra_dump_file
!= NULL
)
3966 fprintf (lra_dump_file
,
3967 "Changing pseudo %d in operand %i of insn %u on equiv ",
3968 REGNO (old
), i
, INSN_UID (curr_insn
));
3969 dump_value_slim (lra_dump_file
, subst
, 1);
3970 fprintf (lra_dump_file
, "\n");
3972 op_change_p
= change_p
= true;
3974 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3977 lra_update_dup (curr_id
, i
);
3981 /* Reload address registers and displacements. We do it before
3982 finding an alternative because of memory constraints. */
3983 before
= after
= NULL
;
3984 for (i
= 0; i
< n_operands
; i
++)
3985 if (! curr_static_id
->operand
[i
].is_operator
3986 && process_address (i
, check_only_p
, &before
, &after
))
3991 lra_update_dup (curr_id
, i
);
3995 /* If we've changed the instruction then any alternative that
3996 we chose previously may no longer be valid. */
3997 lra_set_used_insn_alternative (curr_insn
, LRA_UNKNOWN_ALT
);
3999 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
4000 && check_and_process_move (&change_p
, &sec_mem_p
))
4005 reused_alternative_num
= check_only_p
? LRA_UNKNOWN_ALT
: curr_id
->used_insn_alternative
;
4006 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
4007 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
4008 reused_alternative_num
, INSN_UID (curr_insn
));
4010 if (process_alt_operands (reused_alternative_num
))
4014 return ! alt_p
|| best_losers
!= 0;
4016 /* If insn is commutative (it's safe to exchange a certain pair of
4017 operands) then we need to try each alternative twice, the second
4018 time matching those two operands as if we had exchanged them. To
4019 do this, really exchange them in operands.
4021 If we have just tried the alternatives the second time, return
4022 operands to normal and drop through. */
4024 if (reused_alternative_num
< 0 && commutative
>= 0)
4026 curr_swapped
= !curr_swapped
;
4029 swap_operands (commutative
);
4033 swap_operands (commutative
);
4036 if (! alt_p
&& ! sec_mem_p
)
4038 /* No alternative works with reloads?? */
4039 if (INSN_CODE (curr_insn
) >= 0)
4040 fatal_insn ("unable to generate reloads for:", curr_insn
);
4041 error_for_asm (curr_insn
,
4042 "inconsistent operand constraints in an %<asm%>");
4043 lra_asm_error_p
= true;
4044 /* Avoid further trouble with this insn. Don't generate use
4045 pattern here as we could use the insn SP offset. */
4046 lra_set_insn_deleted (curr_insn
);
4050 /* If the best alternative is with operands 1 and 2 swapped, swap
4051 them. Update the operand numbers of any reloads already
4054 if (goal_alt_swapped
)
4056 if (lra_dump_file
!= NULL
)
4057 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
4058 INSN_UID (curr_insn
));
4060 /* Swap the duplicates too. */
4061 swap_operands (commutative
);
4065 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
4066 too conservatively. So we use the secondary memory only if there
4067 is no any alternative without reloads. */
4068 use_sec_mem_p
= false;
4070 use_sec_mem_p
= true;
4073 for (i
= 0; i
< n_operands
; i
++)
4074 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
4076 use_sec_mem_p
= i
< n_operands
;
4081 int in
= -1, out
= -1;
4082 rtx new_reg
, src
, dest
, rld
;
4083 machine_mode sec_mode
, rld_mode
;
4085 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
4086 dest
= SET_DEST (curr_insn_set
);
4087 src
= SET_SRC (curr_insn_set
);
4088 for (i
= 0; i
< n_operands
; i
++)
4089 if (*curr_id
->operand_loc
[i
] == dest
)
4091 else if (*curr_id
->operand_loc
[i
] == src
)
4093 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
4094 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
4095 out
= curr_static_id
->dup_num
[i
];
4096 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
4097 in
= curr_static_id
->dup_num
[i
];
4098 lra_assert (out
>= 0 && in
>= 0
4099 && curr_static_id
->operand
[out
].type
== OP_OUT
4100 && curr_static_id
->operand
[in
].type
== OP_IN
);
4101 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
4102 rld_mode
= GET_MODE (rld
);
4103 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
4104 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
4105 NO_REGS
, "secondary");
4106 /* If the mode is changed, it should be wider. */
4107 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
4108 if (sec_mode
!= rld_mode
)
4110 /* If the target says specifically to use another mode for
4111 secondary memory moves we cannot reuse the original
4113 after
= emit_spill_move (false, new_reg
, dest
);
4114 lra_process_new_insns (curr_insn
, NULL
, after
,
4115 "Inserting the sec. move");
4116 /* We may have non null BEFORE here (e.g. after address
4118 push_to_sequence (before
);
4119 before
= emit_spill_move (true, new_reg
, src
);
4121 before
= get_insns ();
4123 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
4124 lra_set_insn_deleted (curr_insn
);
4126 else if (dest
== rld
)
4128 *curr_id
->operand_loc
[out
] = new_reg
;
4129 lra_update_dup (curr_id
, out
);
4130 after
= emit_spill_move (false, new_reg
, dest
);
4131 lra_process_new_insns (curr_insn
, NULL
, after
,
4132 "Inserting the sec. move");
4136 *curr_id
->operand_loc
[in
] = new_reg
;
4137 lra_update_dup (curr_id
, in
);
4138 /* See comments above. */
4139 push_to_sequence (before
);
4140 before
= emit_spill_move (true, new_reg
, src
);
4142 before
= get_insns ();
4144 lra_process_new_insns (curr_insn
, before
, NULL
,
4145 "Inserting the sec. move");
4147 lra_update_insn_regno_info (curr_insn
);
4151 lra_assert (goal_alt_number
>= 0);
4152 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
4154 if (lra_dump_file
!= NULL
)
4158 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4159 goal_alt_number
, INSN_UID (curr_insn
));
4160 for (i
= 0; i
< n_operands
; i
++)
4162 p
= (curr_static_id
->operand_alternative
4163 [goal_alt_number
* n_operands
+ i
].constraint
);
4166 fprintf (lra_dump_file
, " (%d) ", i
);
4167 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
4168 fputc (*p
, lra_dump_file
);
4170 if (INSN_CODE (curr_insn
) >= 0
4171 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4172 fprintf (lra_dump_file
, " {%s}", p
);
4173 if (maybe_ne (curr_id
->sp_offset
, 0))
4175 fprintf (lra_dump_file
, " (sp_off=");
4176 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4177 fprintf (lra_dump_file
, ")");
4179 fprintf (lra_dump_file
, "\n");
4182 /* Right now, for any pair of operands I and J that are required to
4183 match, with J < I, goal_alt_matches[I] is J. Add I to
4184 goal_alt_matched[J]. */
4186 for (i
= 0; i
< n_operands
; i
++)
4187 if ((j
= goal_alt_matches
[i
]) >= 0)
4189 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4191 /* We allow matching one output operand and several input
4194 || (curr_static_id
->operand
[j
].type
== OP_OUT
4195 && curr_static_id
->operand
[i
].type
== OP_IN
4196 && (curr_static_id
->operand
4197 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4198 goal_alt_matched
[j
][k
] = i
;
4199 goal_alt_matched
[j
][k
+ 1] = -1;
4202 for (i
= 0; i
< n_operands
; i
++)
4203 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4205 /* Any constants that aren't allowed and can't be reloaded into
4206 registers are here changed into memory references. */
4207 for (i
= 0; i
< n_operands
; i
++)
4208 if (goal_alt_win
[i
])
4211 enum reg_class new_class
;
4212 rtx reg
= *curr_id
->operand_loc
[i
];
4214 if (GET_CODE (reg
) == SUBREG
)
4215 reg
= SUBREG_REG (reg
);
4217 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4219 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4221 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4224 lra_change_class (regno
, new_class
, " Change to", true);
4230 const char *constraint
;
4232 rtx op
= *curr_id
->operand_loc
[i
];
4233 rtx subreg
= NULL_RTX
;
4234 machine_mode mode
= curr_operand_mode
[i
];
4236 if (GET_CODE (op
) == SUBREG
)
4239 op
= SUBREG_REG (op
);
4240 mode
= GET_MODE (op
);
4243 if (CONST_POOL_OK_P (mode
, op
)
4244 && ((targetm
.preferred_reload_class
4245 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4246 || no_input_reloads_p
))
4248 rtx tem
= force_const_mem (mode
, op
);
4251 if (subreg
!= NULL_RTX
)
4252 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4254 *curr_id
->operand_loc
[i
] = tem
;
4255 lra_update_dup (curr_id
, i
);
4256 process_address (i
, false, &before
, &after
);
4258 /* If the alternative accepts constant pool refs directly
4259 there will be no reload needed at all. */
4260 if (subreg
!= NULL_RTX
)
4262 /* Skip alternatives before the one requested. */
4263 constraint
= (curr_static_id
->operand_alternative
4264 [goal_alt_number
* n_operands
+ i
].constraint
);
4266 (c
= *constraint
) && c
!= ',' && c
!= '#';
4267 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4269 enum constraint_num cn
= lookup_constraint (constraint
);
4270 if ((insn_extra_memory_constraint (cn
)
4271 || insn_extra_special_memory_constraint (cn
))
4272 && satisfies_memory_constraint_p (tem
, cn
))
4275 if (c
== '\0' || c
== ',' || c
== '#')
4278 goal_alt_win
[i
] = true;
4284 for (i
= 0; i
< n_operands
; i
++)
4287 bool optional_p
= false;
4289 rtx op
= *curr_id
->operand_loc
[i
];
4291 if (goal_alt_win
[i
])
4293 if (goal_alt
[i
] == NO_REGS
4295 /* When we assign NO_REGS it means that we will not
4296 assign a hard register to the scratch pseudo by
4297 assigment pass and the scratch pseudo will be
4298 spilled. Spilled scratch pseudos are transformed
4299 back to scratches at the LRA end. */
4300 && lra_former_scratch_operand_p (curr_insn
, i
)
4301 && lra_former_scratch_p (REGNO (op
)))
4303 int regno
= REGNO (op
);
4304 lra_change_class (regno
, NO_REGS
, " Change to", true);
4305 if (lra_get_regno_hard_regno (regno
) >= 0)
4306 /* We don't have to mark all insn affected by the
4307 spilled pseudo as there is only one such insn, the
4309 reg_renumber
[regno
] = -1;
4310 lra_assert (bitmap_single_bit_set_p
4311 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4313 /* We can do an optional reload. If the pseudo got a hard
4314 reg, we might improve the code through inheritance. If
4315 it does not get a hard register we coalesce memory/memory
4316 moves later. Ignore move insns to avoid cycling. */
4318 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4319 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4320 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4321 && regno
< new_regno_start
4322 && ! lra_former_scratch_p (regno
)
4323 && reg_renumber
[regno
] < 0
4324 /* Check that the optional reload pseudo will be able to
4325 hold given mode value. */
4326 && ! (prohibited_class_reg_set_mode_p
4327 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4328 PSEUDO_REGNO_MODE (regno
)))
4329 && (curr_insn_set
== NULL_RTX
4330 || !((REG_P (SET_SRC (curr_insn_set
))
4331 || MEM_P (SET_SRC (curr_insn_set
))
4332 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4333 && (REG_P (SET_DEST (curr_insn_set
))
4334 || MEM_P (SET_DEST (curr_insn_set
))
4335 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4337 else if (goal_alt_matched
[i
][0] != -1
4338 && curr_static_id
->operand
[i
].type
== OP_OUT
4339 && (curr_static_id
->operand_alternative
4340 [goal_alt_number
* n_operands
+ i
].earlyclobber
)
4343 for (j
= 0; goal_alt_matched
[i
][j
] != -1; j
++)
4345 rtx op2
= *curr_id
->operand_loc
[goal_alt_matched
[i
][j
]];
4347 if (REG_P (op2
) && REGNO (op
) != REGNO (op2
))
4350 if (goal_alt_matched
[i
][j
] != -1)
4352 /* Generate reloads for different output and matched
4353 input registers. This is the easiest way to avoid
4354 creation of non-existing register conflicts in
4356 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4358 outputs
[n_outputs
++] = i
;
4359 outputs
[n_outputs
] = -1;
4367 /* Operands that match previous ones have already been handled. */
4368 if (goal_alt_matches
[i
] >= 0)
4371 /* We should not have an operand with a non-offsettable address
4372 appearing where an offsettable address will do. It also may
4373 be a case when the address should be special in other words
4374 not a general one (e.g. it needs no index reg). */
4375 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4377 enum reg_class rclass
;
4378 rtx
*loc
= &XEXP (op
, 0);
4379 enum rtx_code code
= GET_CODE (*loc
);
4381 push_to_sequence (before
);
4382 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4384 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4385 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4386 /* This value does not matter for MODIFY. */
4387 GET_MODE_SIZE (GET_MODE (op
)));
4388 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4389 "offsetable address", &new_reg
))
4392 enum rtx_code code
= GET_CODE (addr
);
4393 bool align_p
= false;
4395 if (code
== AND
&& CONST_INT_P (XEXP (addr
, 1)))
4397 /* (and ... (const_int -X)) is used to align to X bytes. */
4399 addr
= XEXP (*loc
, 0);
4402 addr
= canonicalize_reload_addr (addr
);
4404 lra_emit_move (new_reg
, addr
);
4406 emit_move_insn (new_reg
, gen_rtx_AND (GET_MODE (new_reg
), new_reg
, XEXP (*loc
, 1)));
4408 before
= get_insns ();
4411 lra_update_dup (curr_id
, i
);
4413 else if (goal_alt_matched
[i
][0] == -1)
4418 enum op_type type
= curr_static_id
->operand
[i
].type
;
4420 loc
= curr_id
->operand_loc
[i
];
4421 mode
= curr_operand_mode
[i
];
4422 if (GET_CODE (*loc
) == SUBREG
)
4424 reg
= SUBREG_REG (*loc
);
4425 poly_int64 byte
= SUBREG_BYTE (*loc
);
4427 /* Strict_low_part requires reloading the register and not
4428 just the subreg. Likewise for a strict subreg no wider
4429 than a word for WORD_REGISTER_OPERATIONS targets. */
4430 && (curr_static_id
->operand
[i
].strict_low
4431 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4433 = get_try_hard_regno (REGNO (reg
))) >= 0
4434 && (simplify_subreg_regno
4436 GET_MODE (reg
), byte
, mode
) < 0)
4437 && (goal_alt
[i
] == NO_REGS
4438 || (simplify_subreg_regno
4439 (ira_class_hard_regs
[goal_alt
[i
]][0],
4440 GET_MODE (reg
), byte
, mode
) >= 0)))
4441 || (partial_subreg_p (mode
, GET_MODE (reg
))
4442 && known_le (GET_MODE_SIZE (GET_MODE (reg
)),
4444 && WORD_REGISTER_OPERATIONS
)))
4446 /* An OP_INOUT is required when reloading a subreg of a
4447 mode wider than a word to ensure that data beyond the
4448 word being reloaded is preserved. Also automatically
4449 ensure that strict_low_part reloads are made into
4450 OP_INOUT which should already be true from the backend
4453 && (curr_static_id
->operand
[i
].strict_low
4454 || read_modify_subreg_p (*loc
)))
4456 loc
= &SUBREG_REG (*loc
);
4457 mode
= GET_MODE (*loc
);
4461 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4462 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4465 push_to_sequence (before
);
4466 lra_emit_move (new_reg
, old
);
4467 before
= get_insns ();
4472 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4475 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4477 after
= get_insns ();
4481 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4482 if (goal_alt_dont_inherit_ops
[j
] == i
)
4484 lra_set_regno_unique_value (REGNO (new_reg
));
4487 lra_update_dup (curr_id
, i
);
4489 else if (curr_static_id
->operand
[i
].type
== OP_IN
4490 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4492 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4494 && (operands_match_p
4495 (*curr_id
->operand_loc
[i
],
4496 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4499 /* generate reloads for input and matched outputs. */
4500 match_inputs
[0] = i
;
4501 match_inputs
[1] = -1;
4502 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4503 goal_alt
[i
], &before
, &after
,
4504 curr_static_id
->operand_alternative
4505 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4508 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4509 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4510 && (operands_match_p
4511 (*curr_id
->operand_loc
[i
],
4512 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4514 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4516 /* Generate reloads for output and matched inputs. */
4517 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4518 &after
, curr_static_id
->operand_alternative
4519 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4520 else if (curr_static_id
->operand
[i
].type
== OP_IN
4521 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4524 /* Generate reloads for matched inputs. */
4525 match_inputs
[0] = i
;
4526 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4527 match_inputs
[j
+ 1] = k
;
4528 match_inputs
[j
+ 1] = -1;
4529 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4533 /* We must generate code in any case when function
4534 process_alt_operands decides that it is possible. */
4537 /* Memorise processed outputs so that output remaining to be processed
4538 can avoid using the same register value (see match_reload). */
4539 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4541 outputs
[n_outputs
++] = i
;
4542 outputs
[n_outputs
] = -1;
4549 lra_assert (REG_P (reg
));
4550 regno
= REGNO (reg
);
4551 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4552 if (GET_CODE (op
) == SUBREG
)
4553 op
= SUBREG_REG (op
);
4554 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4555 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4556 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4557 if (lra_dump_file
!= NULL
)
4558 fprintf (lra_dump_file
,
4559 " Making reload reg %d for reg %d optional\n",
4563 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4564 || max_regno_before
!= max_reg_num ())
4568 lra_update_operator_dups (curr_id
);
4569 /* Something changes -- process the insn. */
4570 lra_update_insn_regno_info (curr_insn
);
4572 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4576 /* Return true if INSN satisfies all constraints. In other words, no
4577 reload insns are needed. */
4579 lra_constrain_insn (rtx_insn
*insn
)
4581 int saved_new_regno_start
= new_regno_start
;
4582 int saved_new_insn_uid_start
= new_insn_uid_start
;
4586 curr_id
= lra_get_insn_recog_data (curr_insn
);
4587 curr_static_id
= curr_id
->insn_static_data
;
4588 new_insn_uid_start
= get_max_uid ();
4589 new_regno_start
= max_reg_num ();
4590 change_p
= curr_insn_transform (true);
4591 new_regno_start
= saved_new_regno_start
;
4592 new_insn_uid_start
= saved_new_insn_uid_start
;
4596 /* Return true if X is in LIST. */
4598 in_list_p (rtx x
, rtx list
)
4600 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4601 if (XEXP (list
, 0) == x
)
4606 /* Return true if X contains an allocatable hard register (if
4607 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4609 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4615 code
= GET_CODE (x
);
4618 int regno
= REGNO (x
);
4619 HARD_REG_SET alloc_regs
;
4623 if (regno
>= FIRST_PSEUDO_REGISTER
)
4624 regno
= lra_get_regno_hard_regno (regno
);
4627 alloc_regs
= ~lra_no_alloc_regs
;
4628 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4632 if (regno
< FIRST_PSEUDO_REGISTER
)
4636 return lra_get_regno_hard_regno (regno
) < 0;
4639 fmt
= GET_RTX_FORMAT (code
);
4640 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4644 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4647 else if (fmt
[i
] == 'E')
4649 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4650 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4657 /* Process all regs in location *LOC and change them on equivalent
4658 substitution. Return true if any change was done. */
4660 loc_equivalence_change_p (rtx
*loc
)
4662 rtx subst
, reg
, x
= *loc
;
4663 bool result
= false;
4664 enum rtx_code code
= GET_CODE (x
);
4670 reg
= SUBREG_REG (x
);
4671 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4672 && GET_MODE (subst
) == VOIDmode
)
4674 /* We cannot reload debug location. Simplify subreg here
4675 while we know the inner mode. */
4676 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4677 GET_MODE (reg
), SUBREG_BYTE (x
));
4681 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4687 /* Scan all the operand sub-expressions. */
4688 fmt
= GET_RTX_FORMAT (code
);
4689 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4692 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4693 else if (fmt
[i
] == 'E')
4694 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4696 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4701 /* Similar to loc_equivalence_change_p, but for use as
4702 simplify_replace_fn_rtx callback. DATA is insn for which the
4703 elimination is done. If it null we don't do the elimination. */
4705 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4710 rtx subst
= (data
== NULL
4711 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4718 /* Maximum number of generated reload insns per an insn. It is for
4719 preventing this pass cycling in a bug case. */
4720 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4722 /* The current iteration number of this LRA pass. */
4723 int lra_constraint_iter
;
4725 /* True if we should during assignment sub-pass check assignment
4726 correctness for all pseudos and spill some of them to correct
4727 conflicts. It can be necessary when we substitute equiv which
4728 needs checking register allocation correctness because the
4729 equivalent value contains allocatable hard registers, or when we
4730 restore multi-register pseudo, or when we change the insn code and
4731 its operand became INOUT operand when it was IN one before. */
4732 bool check_and_force_assignment_correctness_p
;
4734 /* Return true if REGNO is referenced in more than one block. */
4736 multi_block_pseudo_p (int regno
)
4738 basic_block bb
= NULL
;
4742 if (regno
< FIRST_PSEUDO_REGISTER
)
4745 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4747 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4748 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4753 /* Return true if LIST contains a deleted insn. */
4755 contains_deleted_insn_p (rtx_insn_list
*list
)
4757 for (; list
!= NULL_RTX
; list
= list
->next ())
4758 if (NOTE_P (list
->insn ())
4759 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4764 /* Return true if X contains a pseudo dying in INSN. */
4766 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4773 return (insn
!= NULL_RTX
4774 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4775 code
= GET_CODE (x
);
4776 fmt
= GET_RTX_FORMAT (code
);
4777 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4781 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4784 else if (fmt
[i
] == 'E')
4786 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4787 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4794 /* Return true if INSN contains a dying pseudo in INSN right hand
4797 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4799 rtx set
= single_set (insn
);
4801 gcc_assert (set
!= NULL
);
4802 return dead_pseudo_p (SET_SRC (set
), insn
);
4805 /* Return true if any init insn of REGNO contains a dying pseudo in
4806 insn right hand side. */
4808 init_insn_rhs_dead_pseudo_p (int regno
)
4810 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4814 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4815 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4820 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4821 reverse only if we have one init insn with given REGNO as a
4824 reverse_equiv_p (int regno
)
4826 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4831 if (! INSN_P (insns
->insn ())
4832 || insns
->next () != NULL
)
4834 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4836 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4839 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4840 call this function only for non-reverse equivalence. */
4842 contains_reloaded_insn_p (int regno
)
4845 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4847 for (; list
!= NULL
; list
= list
->next ())
4848 if ((set
= single_set (list
->insn ())) == NULL_RTX
4849 || ! REG_P (SET_DEST (set
))
4850 || (int) REGNO (SET_DEST (set
)) != regno
)
4855 /* Entry function of LRA constraint pass. Return true if the
4856 constraint pass did change the code. */
4858 lra_constraints (bool first_p
)
4861 int i
, hard_regno
, new_insns_num
;
4862 unsigned int min_len
, new_min_len
, uid
;
4863 rtx set
, x
, reg
, dest_reg
;
4864 basic_block last_bb
;
4867 lra_constraint_iter
++;
4868 if (lra_dump_file
!= NULL
)
4869 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4870 lra_constraint_iter
);
4872 if (pic_offset_table_rtx
4873 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4874 check_and_force_assignment_correctness_p
= true;
4876 /* On the first iteration we should check IRA assignment
4877 correctness. In rare cases, the assignments can be wrong as
4878 early clobbers operands are ignored in IRA or usages of
4879 paradoxical sub-registers are not taken into account by
4881 check_and_force_assignment_correctness_p
= true;
4882 new_insn_uid_start
= get_max_uid ();
4883 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4884 /* Mark used hard regs for target stack size calulations. */
4885 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4886 if (lra_reg_info
[i
].nrefs
!= 0
4887 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4891 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
4892 for (j
= 0; j
< nregs
; j
++)
4893 df_set_regs_ever_live (hard_regno
+ j
, true);
4895 /* Do elimination before the equivalence processing as we can spill
4896 some pseudos during elimination. */
4897 lra_eliminate (false, first_p
);
4898 auto_bitmap
equiv_insn_bitmap (®_obstack
);
4899 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4900 if (lra_reg_info
[i
].nrefs
!= 0)
4902 ira_reg_equiv
[i
].profitable_p
= true;
4903 reg
= regno_reg_rtx
[i
];
4904 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4906 bool pseudo_p
= contains_reg_p (x
, false, false);
4908 /* After RTL transformation, we cannot guarantee that
4909 pseudo in the substitution was not reloaded which might
4910 make equivalence invalid. For example, in reverse
4917 the memory address register was reloaded before the 2nd
4919 if ((! first_p
&& pseudo_p
)
4920 /* We don't use DF for compilation speed sake. So it
4921 is problematic to update live info when we use an
4922 equivalence containing pseudos in more than one
4924 || (pseudo_p
&& multi_block_pseudo_p (i
))
4925 /* If an init insn was deleted for some reason, cancel
4926 the equiv. We could update the equiv insns after
4927 transformations including an equiv insn deletion
4928 but it is not worthy as such cases are extremely
4930 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4931 /* If it is not a reverse equivalence, we check that a
4932 pseudo in rhs of the init insn is not dying in the
4933 insn. Otherwise, the live info at the beginning of
4934 the corresponding BB might be wrong after we
4935 removed the insn. When the equiv can be a
4936 constant, the right hand side of the init insn can
4938 || (! reverse_equiv_p (i
)
4939 && (init_insn_rhs_dead_pseudo_p (i
)
4940 /* If we reloaded the pseudo in an equivalence
4941 init insn, we cannot remove the equiv init
4942 insns and the init insns might write into
4943 const memory in this case. */
4944 || contains_reloaded_insn_p (i
)))
4945 /* Prevent access beyond equivalent memory for
4946 paradoxical subregs. */
4948 && maybe_gt (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
),
4949 GET_MODE_SIZE (GET_MODE (x
))))
4950 || (pic_offset_table_rtx
4951 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4952 && (targetm
.preferred_reload_class
4953 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4954 || contains_symbol_ref_p (x
))))
4955 ira_reg_equiv
[i
].defined_p
= false;
4956 if (contains_reg_p (x
, false, true))
4957 ira_reg_equiv
[i
].profitable_p
= false;
4958 if (get_equiv (reg
) != reg
)
4959 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4962 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4964 /* We should add all insns containing pseudos which should be
4965 substituted by their equivalences. */
4966 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
4967 lra_push_insn_by_uid (uid
);
4968 min_len
= lra_insn_stack_length ();
4972 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4974 curr_insn
= lra_pop_insn ();
4976 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4977 if (curr_bb
!= last_bb
)
4980 bb_reload_num
= lra_curr_reload_num
;
4982 if (min_len
> new_min_len
)
4984 min_len
= new_min_len
;
4987 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4989 ("maximum number of generated reload insns per insn achieved (%d)",
4990 MAX_RELOAD_INSNS_NUMBER
);
4992 if (DEBUG_INSN_P (curr_insn
))
4994 /* We need to check equivalence in debug insn and change
4995 pseudo to the equivalent value if necessary. */
4996 curr_id
= lra_get_insn_recog_data (curr_insn
);
4997 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4999 rtx old
= *curr_id
->operand_loc
[0];
5000 *curr_id
->operand_loc
[0]
5001 = simplify_replace_fn_rtx (old
, NULL_RTX
,
5002 loc_equivalence_callback
, curr_insn
);
5003 if (old
!= *curr_id
->operand_loc
[0])
5005 lra_update_insn_regno_info (curr_insn
);
5010 else if (INSN_P (curr_insn
))
5012 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
5014 dest_reg
= SET_DEST (set
);
5015 /* The equivalence pseudo could be set up as SUBREG in a
5016 case when it is a call restore insn in a mode
5017 different from the pseudo mode. */
5018 if (GET_CODE (dest_reg
) == SUBREG
)
5019 dest_reg
= SUBREG_REG (dest_reg
);
5020 if ((REG_P (dest_reg
)
5021 && (x
= get_equiv (dest_reg
)) != dest_reg
5022 /* Remove insns which set up a pseudo whose value
5023 cannot be changed. Such insns might be not in
5024 init_insns because we don't update equiv data
5025 during insn transformations.
5027 As an example, let suppose that a pseudo got
5028 hard register and on the 1st pass was not
5029 changed to equivalent constant. We generate an
5030 additional insn setting up the pseudo because of
5031 secondary memory movement. Then the pseudo is
5032 spilled and we use the equiv constant. In this
5033 case we should remove the additional insn and
5034 this insn is not init_insns list. */
5035 && (! MEM_P (x
) || MEM_READONLY_P (x
)
5036 /* Check that this is actually an insn setting
5037 up the equivalence. */
5038 || in_list_p (curr_insn
,
5040 [REGNO (dest_reg
)].init_insns
)))
5041 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
5042 && in_list_p (curr_insn
,
5044 [REGNO (SET_SRC (set
))].init_insns
)))
5046 /* This is equiv init insn of pseudo which did not get a
5047 hard register -- remove the insn. */
5048 if (lra_dump_file
!= NULL
)
5050 fprintf (lra_dump_file
,
5051 " Removing equiv init insn %i (freq=%d)\n",
5052 INSN_UID (curr_insn
),
5053 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
5054 dump_insn_slim (lra_dump_file
, curr_insn
);
5056 if (contains_reg_p (x
, true, false))
5057 check_and_force_assignment_correctness_p
= true;
5058 lra_set_insn_deleted (curr_insn
);
5062 curr_id
= lra_get_insn_recog_data (curr_insn
);
5063 curr_static_id
= curr_id
->insn_static_data
;
5064 init_curr_insn_input_reloads ();
5065 init_curr_operand_mode ();
5066 if (curr_insn_transform (false))
5068 /* Check non-transformed insns too for equiv change as USE
5069 or CLOBBER don't need reloads but can contain pseudos
5070 being changed on their equivalences. */
5071 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
5072 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
5074 lra_update_insn_regno_info (curr_insn
);
5080 /* If we used a new hard regno, changed_p should be true because the
5081 hard reg is assigned to a new pseudo. */
5082 if (flag_checking
&& !changed_p
)
5084 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5085 if (lra_reg_info
[i
].nrefs
!= 0
5086 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
5088 int j
, nregs
= hard_regno_nregs (hard_regno
,
5089 PSEUDO_REGNO_MODE (i
));
5091 for (j
= 0; j
< nregs
; j
++)
5092 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
5098 static void initiate_invariants (void);
5099 static void finish_invariants (void);
5101 /* Initiate the LRA constraint pass. It is done once per
5104 lra_constraints_init (void)
5106 initiate_invariants ();
5109 /* Finalize the LRA constraint pass. It is done once per
5112 lra_constraints_finish (void)
5114 finish_invariants ();
5119 /* Structure describes invariants for ineheritance. */
5120 struct lra_invariant
5122 /* The order number of the invariant. */
5124 /* The invariant RTX. */
5126 /* The origin insn of the invariant. */
5130 typedef lra_invariant invariant_t
;
5131 typedef invariant_t
*invariant_ptr_t
;
5132 typedef const invariant_t
*const_invariant_ptr_t
;
5134 /* Pointer to the inheritance invariants. */
5135 static vec
<invariant_ptr_t
> invariants
;
5137 /* Allocation pool for the invariants. */
5138 static object_allocator
<lra_invariant
> *invariants_pool
;
5140 /* Hash table for the invariants. */
5141 static htab_t invariant_table
;
5143 /* Hash function for INVARIANT. */
5145 invariant_hash (const void *invariant
)
5147 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
5148 return lra_rtx_hash (inv
);
5151 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
5153 invariant_eq_p (const void *invariant1
, const void *invariant2
)
5155 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
5156 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
5158 return rtx_equal_p (inv1
, inv2
);
5161 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5162 invariant which is in the table. */
5163 static invariant_ptr_t
5164 insert_invariant (rtx invariant_rtx
)
5167 invariant_t invariant
;
5168 invariant_ptr_t invariant_ptr
;
5170 invariant
.invariant_rtx
= invariant_rtx
;
5171 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
5172 if (*entry_ptr
== NULL
)
5174 invariant_ptr
= invariants_pool
->allocate ();
5175 invariant_ptr
->invariant_rtx
= invariant_rtx
;
5176 invariant_ptr
->insn
= NULL
;
5177 invariants
.safe_push (invariant_ptr
);
5178 *entry_ptr
= (void *) invariant_ptr
;
5180 return (invariant_ptr_t
) *entry_ptr
;
5183 /* Initiate the invariant table. */
5185 initiate_invariants (void)
5187 invariants
.create (100);
5189 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
5190 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
5193 /* Finish the invariant table. */
5195 finish_invariants (void)
5197 htab_delete (invariant_table
);
5198 delete invariants_pool
;
5199 invariants
.release ();
5202 /* Make the invariant table empty. */
5204 clear_invariants (void)
5206 htab_empty (invariant_table
);
5207 invariants_pool
->release ();
5208 invariants
.truncate (0);
5213 /* This page contains code to do inheritance/split
5216 /* Number of reloads passed so far in current EBB. */
5217 static int reloads_num
;
5219 /* Number of calls passed so far in current EBB. */
5220 static int calls_num
;
5222 /* Index ID is the CALLS_NUM associated the last call we saw with
5223 ABI identifier ID. */
5224 static int last_call_for_abi
[NUM_ABI_IDS
];
5226 /* Which registers have been fully or partially clobbered by a call
5227 since they were last used. */
5228 static HARD_REG_SET full_and_partial_call_clobbers
;
5230 /* Current reload pseudo check for validity of elements in
5232 static int curr_usage_insns_check
;
5234 /* Info about last usage of registers in EBB to do inheritance/split
5235 transformation. Inheritance transformation is done from a spilled
5236 pseudo and split transformations from a hard register or a pseudo
5237 assigned to a hard register. */
5240 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5241 value INSNS is valid. The insns is chain of optional debug insns
5242 and a finishing non-debug insn using the corresponding reg. The
5243 value is also used to mark the registers which are set up in the
5244 current insn. The negated insn uid is used for this. */
5246 /* Value of global reloads_num at the last insn in INSNS. */
5248 /* Value of global reloads_nums at the last insn in INSNS. */
5250 /* It can be true only for splitting. And it means that the restore
5251 insn should be put after insn given by the following member. */
5253 /* Next insns in the current EBB which use the original reg and the
5254 original reg value is not changed between the current insn and
5255 the next insns. In order words, e.g. for inheritance, if we need
5256 to use the original reg value again in the next insns we can try
5257 to use the value in a hard register from a reload insn of the
5262 /* Map: regno -> corresponding pseudo usage insns. */
5263 static struct usage_insns
*usage_insns
;
5266 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5268 usage_insns
[regno
].check
= curr_usage_insns_check
;
5269 usage_insns
[regno
].insns
= insn
;
5270 usage_insns
[regno
].reloads_num
= reloads_num
;
5271 usage_insns
[regno
].calls_num
= calls_num
;
5272 usage_insns
[regno
].after_p
= after_p
;
5273 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0)
5274 remove_from_hard_reg_set (&full_and_partial_call_clobbers
,
5275 PSEUDO_REGNO_MODE (regno
),
5276 reg_renumber
[regno
]);
5279 /* The function is used to form list REGNO usages which consists of
5280 optional debug insns finished by a non-debug insn using REGNO.
5281 RELOADS_NUM is current number of reload insns processed so far. */
5283 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5285 rtx next_usage_insns
;
5287 if (usage_insns
[regno
].check
== curr_usage_insns_check
5288 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5289 && DEBUG_INSN_P (insn
))
5291 /* Check that we did not add the debug insn yet. */
5292 if (next_usage_insns
!= insn
5293 && (GET_CODE (next_usage_insns
) != INSN_LIST
5294 || XEXP (next_usage_insns
, 0) != insn
))
5295 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5298 else if (NONDEBUG_INSN_P (insn
))
5299 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5301 usage_insns
[regno
].check
= 0;
5304 /* Return first non-debug insn in list USAGE_INSNS. */
5306 skip_usage_debug_insns (rtx usage_insns
)
5310 /* Skip debug insns. */
5311 for (insn
= usage_insns
;
5312 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5313 insn
= XEXP (insn
, 1))
5315 return safe_as_a
<rtx_insn
*> (insn
);
5318 /* Return true if we need secondary memory moves for insn in
5319 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5322 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5323 rtx usage_insns ATTRIBUTE_UNUSED
)
5329 if (inher_cl
== ALL_REGS
5330 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5332 lra_assert (INSN_P (insn
));
5333 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5335 dest
= SET_DEST (set
);
5338 lra_assert (inher_cl
!= NO_REGS
);
5339 cl
= get_reg_class (REGNO (dest
));
5340 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5341 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5344 /* Registers involved in inheritance/split in the current EBB
5345 (inheritance/split pseudos and original registers). */
5346 static bitmap_head check_only_regs
;
5348 /* Reload pseudos cannot be involded in invariant inheritance in the
5350 static bitmap_head invalid_invariant_regs
;
5352 /* Do inheritance transformations for insn INSN, which defines (if
5353 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5354 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5355 form as the "insns" field of usage_insns. Return true if we
5356 succeed in such transformation.
5358 The transformations look like:
5361 ... p <- i (new insn)
5363 <- ... p ... <- ... i ...
5365 ... i <- p (new insn)
5366 <- ... p ... <- ... i ...
5368 <- ... p ... <- ... i ...
5369 where p is a spilled original pseudo and i is a new inheritance pseudo.
5372 The inheritance pseudo has the smallest class of two classes CL and
5373 class of ORIGINAL REGNO. */
5375 inherit_reload_reg (bool def_p
, int original_regno
,
5376 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5378 if (optimize_function_for_size_p (cfun
))
5381 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5382 rtx original_reg
= regno_reg_rtx
[original_regno
];
5383 rtx new_reg
, usage_insn
;
5384 rtx_insn
*new_insns
;
5386 lra_assert (! usage_insns
[original_regno
].after_p
);
5387 if (lra_dump_file
!= NULL
)
5388 fprintf (lra_dump_file
,
5389 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5390 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5392 if (lra_dump_file
!= NULL
)
5394 fprintf (lra_dump_file
,
5395 " Rejecting inheritance for %d "
5396 "because of disjoint classes %s and %s\n",
5397 original_regno
, reg_class_names
[cl
],
5398 reg_class_names
[rclass
]);
5399 fprintf (lra_dump_file
,
5400 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5404 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5405 /* We don't use a subset of two classes because it can be
5406 NO_REGS. This transformation is still profitable in most
5407 cases even if the classes are not intersected as register
5408 move is probably cheaper than a memory load. */
5409 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5411 if (lra_dump_file
!= NULL
)
5412 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5413 reg_class_names
[cl
], reg_class_names
[rclass
]);
5417 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5419 /* Reject inheritance resulting in secondary memory moves.
5420 Otherwise, there is a danger in LRA cycling. Also such
5421 transformation will be unprofitable. */
5422 if (lra_dump_file
!= NULL
)
5424 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5425 rtx set
= single_set (insn
);
5427 lra_assert (set
!= NULL_RTX
);
5429 rtx dest
= SET_DEST (set
);
5431 lra_assert (REG_P (dest
));
5432 fprintf (lra_dump_file
,
5433 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5434 "as secondary mem is needed\n",
5435 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5436 original_regno
, reg_class_names
[rclass
]);
5437 fprintf (lra_dump_file
,
5438 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5442 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5443 rclass
, "inheritance");
5446 lra_emit_move (original_reg
, new_reg
);
5448 lra_emit_move (new_reg
, original_reg
);
5449 new_insns
= get_insns ();
5451 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5453 if (lra_dump_file
!= NULL
)
5455 fprintf (lra_dump_file
,
5456 " Rejecting inheritance %d->%d "
5457 "as it results in 2 or more insns:\n",
5458 original_regno
, REGNO (new_reg
));
5459 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5460 fprintf (lra_dump_file
,
5461 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5465 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5466 lra_update_insn_regno_info (insn
);
5468 /* We now have a new usage insn for original regno. */
5469 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5470 if (lra_dump_file
!= NULL
)
5471 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5472 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5473 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5474 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5475 bitmap_set_bit (&check_only_regs
, original_regno
);
5476 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5478 lra_process_new_insns (insn
, NULL
, new_insns
,
5479 "Add original<-inheritance");
5481 lra_process_new_insns (insn
, new_insns
, NULL
,
5482 "Add inheritance<-original");
5483 while (next_usage_insns
!= NULL_RTX
)
5485 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5487 usage_insn
= next_usage_insns
;
5488 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5489 next_usage_insns
= NULL
;
5493 usage_insn
= XEXP (next_usage_insns
, 0);
5494 lra_assert (DEBUG_INSN_P (usage_insn
));
5495 next_usage_insns
= XEXP (next_usage_insns
, 1);
5497 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5498 DEBUG_INSN_P (usage_insn
));
5499 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5500 if (lra_dump_file
!= NULL
)
5502 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5503 fprintf (lra_dump_file
,
5504 " Inheritance reuse change %d->%d (bb%d):\n",
5505 original_regno
, REGNO (new_reg
),
5506 bb
? bb
->index
: -1);
5507 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5510 if (lra_dump_file
!= NULL
)
5511 fprintf (lra_dump_file
,
5512 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5516 /* Return true if we need a caller save/restore for pseudo REGNO which
5517 was assigned to a hard register. */
5519 need_for_call_save_p (int regno
)
5521 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5522 if (usage_insns
[regno
].calls_num
< calls_num
)
5524 unsigned int abis
= 0;
5525 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
5526 if (last_call_for_abi
[i
] > usage_insns
[regno
].calls_num
)
5529 if (call_clobbered_in_region_p (abis
, full_and_partial_call_clobbers
,
5530 PSEUDO_REGNO_MODE (regno
),
5531 reg_renumber
[regno
]))
5537 /* Global registers occurring in the current EBB. */
5538 static bitmap_head ebb_global_regs
;
5540 /* Return true if we need a split for hard register REGNO or pseudo
5541 REGNO which was assigned to a hard register.
5542 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5543 used for reloads since the EBB end. It is an approximation of the
5544 used hard registers in the split range. The exact value would
5545 require expensive calculations. If we were aggressive with
5546 splitting because of the approximation, the split pseudo will save
5547 the same hard register assignment and will be removed in the undo
5548 pass. We still need the approximation because too aggressive
5549 splitting would result in too inaccurate cost calculation in the
5550 assignment pass because of too many generated moves which will be
5551 probably removed in the undo pass. */
5553 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5555 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5557 lra_assert (hard_regno
>= 0);
5558 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5559 /* Don't split eliminable hard registers, otherwise we can
5560 split hard registers like hard frame pointer, which
5561 lives on BB start/end according to DF-infrastructure,
5562 when there is a pseudo assigned to the register and
5563 living in the same BB. */
5564 && (regno
>= FIRST_PSEUDO_REGISTER
5565 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5566 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5567 /* Don't split call clobbered hard regs living through
5568 calls, otherwise we might have a check problem in the
5569 assign sub-pass as in the most cases (exception is a
5570 situation when check_and_force_assignment_correctness_p value is
5571 true) the assign pass assumes that all pseudos living
5572 through calls are assigned to call saved hard regs. */
5573 && (regno
>= FIRST_PSEUDO_REGISTER
5574 || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers
, regno
))
5575 /* We need at least 2 reloads to make pseudo splitting
5576 profitable. We should provide hard regno splitting in
5577 any case to solve 1st insn scheduling problem when
5578 moving hard register definition up might result in
5579 impossibility to find hard register for reload pseudo of
5580 small register class. */
5581 && (usage_insns
[regno
].reloads_num
5582 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5583 && (regno
< FIRST_PSEUDO_REGISTER
5584 /* For short living pseudos, spilling + inheritance can
5585 be considered a substitution for splitting.
5586 Therefore we do not splitting for local pseudos. It
5587 decreases also aggressiveness of splitting. The
5588 minimal number of references is chosen taking into
5589 account that for 2 references splitting has no sense
5590 as we can just spill the pseudo. */
5591 || (regno
>= FIRST_PSEUDO_REGISTER
5592 && lra_reg_info
[regno
].nrefs
> 3
5593 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5594 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5597 /* Return class for the split pseudo created from original pseudo with
5598 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5599 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5600 results in no secondary memory movements. */
5601 static enum reg_class
5602 choose_split_class (enum reg_class allocno_class
,
5603 int hard_regno ATTRIBUTE_UNUSED
,
5604 machine_mode mode ATTRIBUTE_UNUSED
)
5607 enum reg_class cl
, best_cl
= NO_REGS
;
5608 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5609 = REGNO_REG_CLASS (hard_regno
);
5611 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
5612 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5613 return allocno_class
;
5615 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5617 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
5618 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
5619 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5620 && (best_cl
== NO_REGS
5621 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5626 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5627 It only makes sense to call this function if NEW_REGNO is always
5628 equal to ORIGINAL_REGNO. */
5631 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
)
5633 if (!ira_reg_equiv
[original_regno
].defined_p
)
5636 ira_expand_reg_equiv ();
5637 ira_reg_equiv
[new_regno
].defined_p
= true;
5638 if (ira_reg_equiv
[original_regno
].memory
)
5639 ira_reg_equiv
[new_regno
].memory
5640 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5641 if (ira_reg_equiv
[original_regno
].constant
)
5642 ira_reg_equiv
[new_regno
].constant
5643 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5644 if (ira_reg_equiv
[original_regno
].invariant
)
5645 ira_reg_equiv
[new_regno
].invariant
5646 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
5649 /* Do split transformations for insn INSN, which defines or uses
5650 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5651 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5652 "insns" field of usage_insns. If TO is not NULL, we don't use
5653 usage_insns, we put restore insns after TO insn. It is a case when
5654 we call it from lra_split_hard_reg_for, outside the inheritance
5657 The transformations look like:
5660 ... s <- p (new insn -- save)
5662 ... p <- s (new insn -- restore)
5663 <- ... p ... <- ... p ...
5665 <- ... p ... <- ... p ...
5666 ... s <- p (new insn -- save)
5668 ... p <- s (new insn -- restore)
5669 <- ... p ... <- ... p ...
5671 where p is an original pseudo got a hard register or a hard
5672 register and s is a new split pseudo. The save is put before INSN
5673 if BEFORE_P is true. Return true if we succeed in such
5676 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5677 rtx next_usage_insns
, rtx_insn
*to
)
5679 enum reg_class rclass
;
5681 int hard_regno
, nregs
;
5682 rtx new_reg
, usage_insn
;
5683 rtx_insn
*restore
, *save
;
5688 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5690 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5691 hard_regno
= original_regno
;
5692 call_save_p
= false;
5694 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5695 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5696 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5697 as part of a multi-word register. In that case, or if the biggest
5698 mode was larger than a register, just use the reg_rtx. Otherwise,
5699 limit the size to that of the biggest access in the function. */
5700 if (mode
== VOIDmode
5701 || paradoxical_subreg_p (mode
, reg_rtx_mode
))
5703 original_reg
= regno_reg_rtx
[hard_regno
];
5704 mode
= reg_rtx_mode
;
5707 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5711 mode
= PSEUDO_REGNO_MODE (original_regno
);
5712 hard_regno
= reg_renumber
[original_regno
];
5713 nregs
= hard_regno_nregs (hard_regno
, mode
);
5714 rclass
= lra_get_allocno_class (original_regno
);
5715 original_reg
= regno_reg_rtx
[original_regno
];
5716 call_save_p
= need_for_call_save_p (original_regno
);
5718 lra_assert (hard_regno
>= 0);
5719 if (lra_dump_file
!= NULL
)
5720 fprintf (lra_dump_file
,
5721 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5725 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5726 hard_regno_nregs (hard_regno
, mode
),
5728 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5732 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5733 if (rclass
== NO_REGS
)
5735 if (lra_dump_file
!= NULL
)
5737 fprintf (lra_dump_file
,
5738 " Rejecting split of %d(%s): "
5739 "no good reg class for %d(%s)\n",
5741 reg_class_names
[lra_get_allocno_class (original_regno
)],
5743 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5746 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5750 /* Split_if_necessary can split hard registers used as part of a
5751 multi-register mode but splits each register individually. The
5752 mode used for each independent register may not be supported
5753 so reject the split. Splitting the wider mode should theoretically
5754 be possible but is not implemented. */
5755 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
5757 if (lra_dump_file
!= NULL
)
5759 fprintf (lra_dump_file
,
5760 " Rejecting split of %d(%s): unsuitable mode %s\n",
5762 reg_class_names
[lra_get_allocno_class (original_regno
)],
5763 GET_MODE_NAME (mode
));
5766 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5770 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5771 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5773 int new_regno
= REGNO (new_reg
);
5774 save
= emit_spill_move (true, new_reg
, original_reg
);
5775 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5777 if (lra_dump_file
!= NULL
)
5781 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5782 original_regno
, new_regno
);
5783 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5784 fprintf (lra_dump_file
,
5785 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5789 restore
= emit_spill_move (false, new_reg
, original_reg
);
5790 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5792 if (lra_dump_file
!= NULL
)
5794 fprintf (lra_dump_file
,
5795 " Rejecting split %d->%d "
5796 "resulting in > 2 restore insns:\n",
5797 original_regno
, new_regno
);
5798 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5799 fprintf (lra_dump_file
,
5800 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5804 /* Transfer equivalence information to the spill register, so that
5805 if we fail to allocate the spill register, we have the option of
5806 rematerializing the original value instead of spilling to the stack. */
5807 if (!HARD_REGISTER_NUM_P (original_regno
)
5808 && mode
== PSEUDO_REGNO_MODE (original_regno
))
5809 lra_copy_reg_equiv (new_regno
, original_regno
);
5810 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
5811 bitmap_set_bit (&lra_split_regs
, new_regno
);
5814 lra_assert (next_usage_insns
== NULL
);
5820 /* We need check_only_regs only inside the inheritance pass. */
5821 bitmap_set_bit (&check_only_regs
, new_regno
);
5822 bitmap_set_bit (&check_only_regs
, original_regno
);
5823 after_p
= usage_insns
[original_regno
].after_p
;
5826 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5828 usage_insn
= next_usage_insns
;
5831 usage_insn
= XEXP (next_usage_insns
, 0);
5832 lra_assert (DEBUG_INSN_P (usage_insn
));
5833 next_usage_insns
= XEXP (next_usage_insns
, 1);
5834 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5836 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5837 if (lra_dump_file
!= NULL
)
5839 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5840 original_regno
, new_regno
);
5841 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5845 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5846 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5847 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5848 after_p
? NULL
: restore
,
5849 after_p
? restore
: NULL
,
5851 ? "Add reg<-save" : "Add reg<-split");
5852 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5853 before_p
? NULL
: save
,
5855 ? "Add save<-reg" : "Add split<-reg");
5857 /* If we are trying to split multi-register. We should check
5858 conflicts on the next assignment sub-pass. IRA can allocate on
5859 sub-register levels, LRA do this on pseudos level right now and
5860 this discrepancy may create allocation conflicts after
5862 check_and_force_assignment_correctness_p
= true;
5863 if (lra_dump_file
!= NULL
)
5864 fprintf (lra_dump_file
,
5865 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5869 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
5870 in the range [FROM, TO]. Return true if did a split. Otherwise,
5873 spill_hard_reg_in_range (int regno
, enum reg_class rclass
, rtx_insn
*from
, rtx_insn
*to
)
5880 HARD_REG_SET ignore
;
5882 lra_assert (from
!= NULL
&& to
!= NULL
);
5883 CLEAR_HARD_REG_SET (ignore
);
5884 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
5886 lra_insn_recog_data_t id
= lra_insn_recog_data
[uid
];
5887 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
5888 struct lra_insn_reg
*reg
;
5890 for (reg
= id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5891 if (reg
->regno
< FIRST_PSEUDO_REGISTER
)
5892 SET_HARD_REG_BIT (ignore
, reg
->regno
);
5893 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5894 SET_HARD_REG_BIT (ignore
, reg
->regno
);
5896 rclass_size
= ira_class_hard_regs_num
[rclass
];
5897 for (i
= 0; i
< rclass_size
; i
++)
5899 hard_regno
= ira_class_hard_regs
[rclass
][i
];
5900 if (! TEST_HARD_REG_BIT (lra_reg_info
[regno
].conflict_hard_regs
, hard_regno
)
5901 || TEST_HARD_REG_BIT (ignore
, hard_regno
))
5903 for (insn
= from
; insn
!= NEXT_INSN (to
); insn
= NEXT_INSN (insn
))
5905 struct lra_static_insn_data
*static_id
;
5906 struct lra_insn_reg
*reg
;
5910 if (bitmap_bit_p (&lra_reg_info
[hard_regno
].insn_bitmap
,
5913 static_id
= lra_get_insn_recog_data (insn
)->insn_static_data
;
5914 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5915 if (reg
->regno
== hard_regno
)
5920 if (insn
!= NEXT_INSN (to
))
5922 if (split_reg (TRUE
, hard_regno
, from
, NULL
, to
))
5928 /* Recognize that we need a split transformation for insn INSN, which
5929 defines or uses REGNO in its insn biggest MODE (we use it only if
5930 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5931 hard registers which might be used for reloads since the EBB end.
5932 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5933 uid before starting INSN processing. Return true if we succeed in
5934 such transformation. */
5936 split_if_necessary (int regno
, machine_mode mode
,
5937 HARD_REG_SET potential_reload_hard_regs
,
5938 bool before_p
, rtx_insn
*insn
, int max_uid
)
5942 rtx next_usage_insns
;
5944 if (regno
< FIRST_PSEUDO_REGISTER
)
5945 nregs
= hard_regno_nregs (regno
, mode
);
5946 for (i
= 0; i
< nregs
; i
++)
5947 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5948 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5949 /* To avoid processing the register twice or more. */
5950 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5951 && INSN_UID (next_usage_insns
) < max_uid
)
5952 || (GET_CODE (next_usage_insns
) == INSN_LIST
5953 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5954 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5955 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
, NULL
))
5960 /* Return TRUE if rtx X is considered as an invariant for
5963 invariant_p (const_rtx x
)
5970 if (side_effects_p (x
))
5973 code
= GET_CODE (x
);
5974 mode
= GET_MODE (x
);
5978 code
= GET_CODE (x
);
5979 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
5987 int i
, nregs
, regno
= REGNO (x
);
5989 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5990 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5991 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5993 nregs
= hard_regno_nregs (regno
, mode
);
5994 for (i
= 0; i
< nregs
; i
++)
5995 if (! fixed_regs
[regno
+ i
]
5996 /* A hard register may be clobbered in the current insn
5997 but we can ignore this case because if the hard
5998 register is used it should be set somewhere after the
6000 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
6003 fmt
= GET_RTX_FORMAT (code
);
6004 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6008 if (! invariant_p (XEXP (x
, i
)))
6011 else if (fmt
[i
] == 'E')
6013 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6014 if (! invariant_p (XVECEXP (x
, i
, j
)))
6021 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
6022 inheritance transformation (using dest_reg instead invariant in a
6023 subsequent insn). */
6025 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
6027 invariant_ptr_t invariant_ptr
;
6028 rtx_insn
*insn
, *new_insns
;
6029 rtx insn_set
, insn_reg
, new_reg
;
6031 bool succ_p
= false;
6032 int dst_regno
= REGNO (dst_reg
);
6033 machine_mode dst_mode
= GET_MODE (dst_reg
);
6034 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
6036 invariant_ptr
= insert_invariant (invariant_rtx
);
6037 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
6039 /* We have a subsequent insn using the invariant. */
6040 insn_set
= single_set (insn
);
6041 lra_assert (insn_set
!= NULL
);
6042 insn_reg
= SET_DEST (insn_set
);
6043 lra_assert (REG_P (insn_reg
));
6044 insn_regno
= REGNO (insn_reg
);
6045 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
6047 if (dst_mode
== GET_MODE (insn_reg
)
6048 /* We should consider only result move reg insns which are
6050 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
6051 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
6053 if (lra_dump_file
!= NULL
)
6054 fprintf (lra_dump_file
,
6055 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
6056 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
6057 cl
, "invariant inheritance");
6058 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
6059 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
6060 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
6062 lra_emit_move (new_reg
, dst_reg
);
6063 new_insns
= get_insns ();
6065 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6066 "Add invariant inheritance<-original");
6068 lra_emit_move (SET_DEST (insn_set
), new_reg
);
6069 new_insns
= get_insns ();
6071 lra_process_new_insns (insn
, NULL
, new_insns
,
6072 "Changing reload<-inheritance");
6073 lra_set_insn_deleted (insn
);
6075 if (lra_dump_file
!= NULL
)
6077 fprintf (lra_dump_file
,
6078 " Invariant inheritance reuse change %d (bb%d):\n",
6079 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
6080 dump_insn_slim (lra_dump_file
, insn
);
6081 fprintf (lra_dump_file
,
6082 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
6086 invariant_ptr
->insn
= curr_insn
;
6090 /* Check only registers living at the current program point in the
6092 static bitmap_head live_regs
;
6094 /* Update live info in EBB given by its HEAD and TAIL insns after
6095 inheritance/split transformation. The function removes dead moves
6098 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
6103 rtx_insn
*prev_insn
;
6106 basic_block last_bb
, prev_bb
, curr_bb
;
6108 struct lra_insn_reg
*reg
;
6112 last_bb
= BLOCK_FOR_INSN (tail
);
6114 for (curr_insn
= tail
;
6115 curr_insn
!= PREV_INSN (head
);
6116 curr_insn
= prev_insn
)
6118 prev_insn
= PREV_INSN (curr_insn
);
6119 /* We need to process empty blocks too. They contain
6120 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
6121 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
6123 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6124 if (curr_bb
!= prev_bb
)
6126 if (prev_bb
!= NULL
)
6128 /* Update df_get_live_in (prev_bb): */
6129 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6130 if (bitmap_bit_p (&live_regs
, j
))
6131 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
6133 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
6135 if (curr_bb
!= last_bb
)
6137 /* Update df_get_live_out (curr_bb): */
6138 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6140 live_p
= bitmap_bit_p (&live_regs
, j
);
6142 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
6143 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
6149 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
6151 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
6155 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
6157 if (! NONDEBUG_INSN_P (curr_insn
))
6159 curr_id
= lra_get_insn_recog_data (curr_insn
);
6160 curr_static_id
= curr_id
->insn_static_data
;
6162 if ((set
= single_set (curr_insn
)) != NULL_RTX
6163 && REG_P (SET_DEST (set
))
6164 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
6165 && SET_DEST (set
) != pic_offset_table_rtx
6166 && bitmap_bit_p (&check_only_regs
, regno
)
6167 && ! bitmap_bit_p (&live_regs
, regno
))
6169 /* See which defined values die here. */
6170 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6171 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6172 bitmap_clear_bit (&live_regs
, reg
->regno
);
6173 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6174 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6175 bitmap_clear_bit (&live_regs
, reg
->regno
);
6176 if (curr_id
->arg_hard_regs
!= NULL
)
6177 /* Make clobbered argument hard registers die. */
6178 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6179 if (regno
>= FIRST_PSEUDO_REGISTER
)
6180 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
6181 /* Mark each used value as live. */
6182 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6183 if (reg
->type
!= OP_OUT
6184 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6185 bitmap_set_bit (&live_regs
, reg
->regno
);
6186 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6187 if (reg
->type
!= OP_OUT
6188 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6189 bitmap_set_bit (&live_regs
, reg
->regno
);
6190 if (curr_id
->arg_hard_regs
!= NULL
)
6191 /* Make used argument hard registers live. */
6192 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6193 if (regno
< FIRST_PSEUDO_REGISTER
6194 && bitmap_bit_p (&check_only_regs
, regno
))
6195 bitmap_set_bit (&live_regs
, regno
);
6196 /* It is quite important to remove dead move insns because it
6197 means removing dead store. We don't need to process them for
6201 if (lra_dump_file
!= NULL
)
6203 fprintf (lra_dump_file
, " Removing dead insn:\n ");
6204 dump_insn_slim (lra_dump_file
, curr_insn
);
6206 lra_set_insn_deleted (curr_insn
);
6211 /* The structure describes info to do an inheritance for the current
6212 insn. We need to collect such info first before doing the
6213 transformations because the transformations change the insn
6214 internal representation. */
6217 /* Original regno. */
6219 /* Subsequent insns which can inherit original reg value. */
6223 /* Array containing all info for doing inheritance from the current
6225 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
6227 /* Number elements in the previous array. */
6228 static int to_inherit_num
;
6230 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6231 structure to_inherit. */
6233 add_to_inherit (int regno
, rtx insns
)
6237 for (i
= 0; i
< to_inherit_num
; i
++)
6238 if (to_inherit
[i
].regno
== regno
)
6240 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
6241 to_inherit
[to_inherit_num
].regno
= regno
;
6242 to_inherit
[to_inherit_num
++].insns
= insns
;
6245 /* Return the last non-debug insn in basic block BB, or the block begin
6248 get_last_insertion_point (basic_block bb
)
6252 FOR_BB_INSNS_REVERSE (bb
, insn
)
6253 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
6258 /* Set up RES by registers living on edges FROM except the edge (FROM,
6259 TO) or by registers set up in a jump insn in BB FROM. */
6261 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
6264 struct lra_insn_reg
*reg
;
6268 lra_assert (to
!= NULL
);
6270 FOR_EACH_EDGE (e
, ei
, from
->succs
)
6272 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
6273 last
= get_last_insertion_point (from
);
6274 if (! JUMP_P (last
))
6276 curr_id
= lra_get_insn_recog_data (last
);
6277 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6278 if (reg
->type
!= OP_IN
)
6279 bitmap_set_bit (res
, reg
->regno
);
6282 /* Used as a temporary results of some bitmap calculations. */
6283 static bitmap_head temp_bitmap
;
6285 /* We split for reloads of small class of hard regs. The following
6286 defines how many hard regs the class should have to be qualified as
6287 small. The code is mostly oriented to x86/x86-64 architecture
6288 where some insns need to use only specific register or pair of
6289 registers and these register can live in RTL explicitly, e.g. for
6290 parameter passing. */
6291 static const int max_small_class_regs_num
= 2;
6293 /* Do inheritance/split transformations in EBB starting with HEAD and
6294 finishing on TAIL. We process EBB insns in the reverse order.
6295 Return true if we did any inheritance/split transformation in the
6298 We should avoid excessive splitting which results in worse code
6299 because of inaccurate cost calculations for spilling new split
6300 pseudos in such case. To achieve this we do splitting only if
6301 register pressure is high in given basic block and there are reload
6302 pseudos requiring hard registers. We could do more register
6303 pressure calculations at any given program point to avoid necessary
6304 splitting even more but it is to expensive and the current approach
6305 works well enough. */
6307 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6309 int i
, src_regno
, dst_regno
, nregs
;
6310 bool change_p
, succ_p
, update_reloads_num_p
;
6311 rtx_insn
*prev_insn
, *last_insn
;
6312 rtx next_usage_insns
, curr_set
;
6314 struct lra_insn_reg
*reg
;
6315 basic_block last_processed_bb
, curr_bb
= NULL
;
6316 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6320 bool head_p
, after_p
;
6323 curr_usage_insns_check
++;
6324 clear_invariants ();
6325 reloads_num
= calls_num
= 0;
6326 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
6327 last_call_for_abi
[i
] = 0;
6328 CLEAR_HARD_REG_SET (full_and_partial_call_clobbers
);
6329 bitmap_clear (&check_only_regs
);
6330 bitmap_clear (&invalid_invariant_regs
);
6331 last_processed_bb
= NULL
;
6332 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6333 live_hard_regs
= eliminable_regset
| lra_no_alloc_regs
;
6334 /* We don't process new insns generated in the loop. */
6335 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6337 prev_insn
= PREV_INSN (curr_insn
);
6338 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6339 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6340 if (last_processed_bb
!= curr_bb
)
6342 /* We are at the end of BB. Add qualified living
6343 pseudos for potential splitting. */
6344 to_process
= df_get_live_out (curr_bb
);
6345 if (last_processed_bb
!= NULL
)
6347 /* We are somewhere in the middle of EBB. */
6348 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6350 to_process
= &temp_bitmap
;
6352 last_processed_bb
= curr_bb
;
6353 last_insn
= get_last_insertion_point (curr_bb
);
6354 after_p
= (! JUMP_P (last_insn
)
6355 && (! CALL_P (last_insn
)
6356 || (find_reg_note (last_insn
,
6357 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6358 && ! SIBLING_CALL_P (last_insn
))));
6359 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6360 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6362 if ((int) j
>= lra_constraint_new_regno_start
)
6364 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6366 if (j
< FIRST_PSEUDO_REGISTER
)
6367 SET_HARD_REG_BIT (live_hard_regs
, j
);
6369 add_to_hard_reg_set (&live_hard_regs
,
6370 PSEUDO_REGNO_MODE (j
),
6372 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6376 src_regno
= dst_regno
= -1;
6377 curr_set
= single_set (curr_insn
);
6378 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6379 dst_regno
= REGNO (SET_DEST (curr_set
));
6380 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6381 src_regno
= REGNO (SET_SRC (curr_set
));
6382 update_reloads_num_p
= true;
6383 if (src_regno
< lra_constraint_new_regno_start
6384 && src_regno
>= FIRST_PSEUDO_REGISTER
6385 && reg_renumber
[src_regno
] < 0
6386 && dst_regno
>= lra_constraint_new_regno_start
6387 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6389 /* 'reload_pseudo <- original_pseudo'. */
6390 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6392 update_reloads_num_p
= false;
6394 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6395 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6396 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6397 curr_insn
, next_usage_insns
);
6401 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6402 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6403 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6405 else if (src_regno
< 0
6406 && dst_regno
>= lra_constraint_new_regno_start
6407 && invariant_p (SET_SRC (curr_set
))
6408 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6409 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6410 && ! bitmap_bit_p (&invalid_invariant_regs
,
6411 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6413 /* 'reload_pseudo <- invariant'. */
6414 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6416 update_reloads_num_p
= false;
6417 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6419 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6420 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6422 else if (src_regno
>= lra_constraint_new_regno_start
6423 && dst_regno
< lra_constraint_new_regno_start
6424 && dst_regno
>= FIRST_PSEUDO_REGISTER
6425 && reg_renumber
[dst_regno
] < 0
6426 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6427 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6428 && (next_usage_insns
6429 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6431 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6433 update_reloads_num_p
= false;
6434 /* 'original_pseudo <- reload_pseudo'. */
6435 if (! JUMP_P (curr_insn
)
6436 && inherit_reload_reg (true, dst_regno
, cl
,
6437 curr_insn
, next_usage_insns
))
6440 usage_insns
[dst_regno
].check
= 0;
6441 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6442 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6444 else if (INSN_P (curr_insn
))
6447 int max_uid
= get_max_uid ();
6449 curr_id
= lra_get_insn_recog_data (curr_insn
);
6450 curr_static_id
= curr_id
->insn_static_data
;
6452 /* Process insn definitions. */
6453 for (iter
= 0; iter
< 2; iter
++)
6454 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6457 if (reg
->type
!= OP_IN
6458 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6460 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6461 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6462 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6463 && (next_usage_insns
6464 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6466 struct lra_insn_reg
*r
;
6468 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6469 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6471 /* Don't do inheritance if the pseudo is also
6472 used in the insn. */
6474 /* We cannot do inheritance right now
6475 because the current insn reg info (chain
6476 regs) can change after that. */
6477 add_to_inherit (dst_regno
, next_usage_insns
);
6479 /* We cannot process one reg twice here because of
6480 usage_insns invalidation. */
6481 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6482 || reg_renumber
[dst_regno
] >= 0)
6483 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6487 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6488 potential_reload_hard_regs
,
6489 false, curr_insn
, max_uid
))
6491 CLEAR_HARD_REG_SET (s
);
6492 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6493 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6495 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6496 reg_renumber
[dst_regno
]);
6497 live_hard_regs
&= ~s
;
6498 potential_reload_hard_regs
&= ~s
;
6500 /* We should invalidate potential inheritance or
6501 splitting for the current insn usages to the next
6502 usage insns (see code below) as the output pseudo
6504 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6505 && reg_renumber
[dst_regno
] < 0)
6506 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6507 && (dst_regno
< FIRST_PSEUDO_REGISTER
6508 || reg_renumber
[dst_regno
] >= 0)))
6510 /* Invalidate and mark definitions. */
6511 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6512 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6515 nregs
= hard_regno_nregs (dst_regno
,
6517 for (i
= 0; i
< nregs
; i
++)
6518 usage_insns
[dst_regno
+ i
].check
6519 = -(int) INSN_UID (curr_insn
);
6523 /* Process clobbered call regs. */
6524 if (curr_id
->arg_hard_regs
!= NULL
)
6525 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6526 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6527 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6528 = -(int) INSN_UID (curr_insn
);
6529 if (! JUMP_P (curr_insn
))
6530 for (i
= 0; i
< to_inherit_num
; i
++)
6531 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6532 ALL_REGS
, curr_insn
,
6533 to_inherit
[i
].insns
))
6535 if (CALL_P (curr_insn
))
6537 rtx cheap
, pat
, dest
;
6539 int regno
, hard_regno
;
6542 function_abi callee_abi
= insn_callee_abi (curr_insn
);
6543 last_call_for_abi
[callee_abi
.id ()] = calls_num
;
6544 full_and_partial_call_clobbers
6545 |= callee_abi
.full_and_partial_reg_clobbers ();
6546 if ((cheap
= find_reg_note (curr_insn
,
6547 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6548 && ((cheap
= XEXP (cheap
, 0)), true)
6549 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6550 && (hard_regno
= reg_renumber
[regno
]) >= 0
6551 && usage_insns
[regno
].check
== curr_usage_insns_check
6552 /* If there are pending saves/restores, the
6553 optimization is not worth. */
6554 && usage_insns
[regno
].calls_num
== calls_num
- 1
6555 && callee_abi
.clobbers_reg_p (GET_MODE (cheap
), hard_regno
))
6557 /* Restore the pseudo from the call result as
6558 REG_RETURNED note says that the pseudo value is
6559 in the call result and the pseudo is an argument
6561 pat
= PATTERN (curr_insn
);
6562 if (GET_CODE (pat
) == PARALLEL
)
6563 pat
= XVECEXP (pat
, 0, 0);
6564 dest
= SET_DEST (pat
);
6565 /* For multiple return values dest is PARALLEL.
6566 Currently we handle only single return value case. */
6570 emit_move_insn (cheap
, copy_rtx (dest
));
6571 restore
= get_insns ();
6573 lra_process_new_insns (curr_insn
, NULL
, restore
,
6574 "Inserting call parameter restore");
6575 /* We don't need to save/restore of the pseudo from
6577 usage_insns
[regno
].calls_num
= calls_num
;
6578 remove_from_hard_reg_set
6579 (&full_and_partial_call_clobbers
,
6580 GET_MODE (cheap
), hard_regno
);
6581 bitmap_set_bit (&check_only_regs
, regno
);
6586 /* Process insn usages. */
6587 for (iter
= 0; iter
< 2; iter
++)
6588 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6591 if ((reg
->type
!= OP_OUT
6592 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6593 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6595 if (src_regno
>= FIRST_PSEUDO_REGISTER
6596 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6598 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6599 && (next_usage_insns
6600 = usage_insns
[src_regno
].insns
) != NULL_RTX
6601 && NONDEBUG_INSN_P (curr_insn
))
6602 add_to_inherit (src_regno
, next_usage_insns
);
6603 else if (usage_insns
[src_regno
].check
6604 != -(int) INSN_UID (curr_insn
))
6605 /* Add usages but only if the reg is not set up
6606 in the same insn. */
6607 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6609 else if (src_regno
< FIRST_PSEUDO_REGISTER
6610 || reg_renumber
[src_regno
] >= 0)
6613 rtx_insn
*use_insn
= curr_insn
;
6615 before_p
= (JUMP_P (curr_insn
)
6616 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6617 if (NONDEBUG_INSN_P (curr_insn
)
6618 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6619 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6620 potential_reload_hard_regs
,
6621 before_p
, curr_insn
, max_uid
))
6624 check_and_force_assignment_correctness_p
= true;
6627 usage_insns
[src_regno
].check
= 0;
6629 use_insn
= PREV_INSN (curr_insn
);
6631 if (NONDEBUG_INSN_P (curr_insn
))
6633 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6634 add_to_hard_reg_set (&live_hard_regs
,
6635 reg
->biggest_mode
, src_regno
);
6637 add_to_hard_reg_set (&live_hard_regs
,
6638 PSEUDO_REGNO_MODE (src_regno
),
6639 reg_renumber
[src_regno
]);
6641 if (src_regno
>= FIRST_PSEUDO_REGISTER
)
6642 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6645 for (i
= 0; i
< hard_regno_nregs (src_regno
, reg
->biggest_mode
); i
++)
6646 add_next_usage_insn (src_regno
+ i
, use_insn
, reloads_num
);
6650 /* Process used call regs. */
6651 if (curr_id
->arg_hard_regs
!= NULL
)
6652 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6653 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6655 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6656 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6658 for (i
= 0; i
< to_inherit_num
; i
++)
6660 src_regno
= to_inherit
[i
].regno
;
6661 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6662 curr_insn
, to_inherit
[i
].insns
))
6665 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6668 if (update_reloads_num_p
6669 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6672 if ((REG_P (SET_DEST (curr_set
))
6673 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6674 && reg_renumber
[regno
] < 0
6675 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6676 || (REG_P (SET_SRC (curr_set
))
6677 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6678 && reg_renumber
[regno
] < 0
6679 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6681 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6683 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6684 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6687 if (NONDEBUG_INSN_P (curr_insn
))
6691 /* Invalidate invariants with changed regs. */
6692 curr_id
= lra_get_insn_recog_data (curr_insn
);
6693 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6694 if (reg
->type
!= OP_IN
)
6696 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6697 bitmap_set_bit (&invalid_invariant_regs
,
6698 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6700 curr_static_id
= curr_id
->insn_static_data
;
6701 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6702 if (reg
->type
!= OP_IN
)
6703 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6704 if (curr_id
->arg_hard_regs
!= NULL
)
6705 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6706 if (regno
>= FIRST_PSEUDO_REGISTER
)
6707 bitmap_set_bit (&invalid_invariant_regs
,
6708 regno
- FIRST_PSEUDO_REGISTER
);
6710 /* We reached the start of the current basic block. */
6711 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6712 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6714 /* We reached the beginning of the current block -- do
6715 rest of spliting in the current BB. */
6716 to_process
= df_get_live_in (curr_bb
);
6717 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6719 /* We are somewhere in the middle of EBB. */
6720 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6721 curr_bb
, &temp_bitmap
);
6722 to_process
= &temp_bitmap
;
6725 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6727 if ((int) j
>= lra_constraint_new_regno_start
)
6729 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6730 && usage_insns
[j
].check
== curr_usage_insns_check
6731 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6733 if (need_for_split_p (potential_reload_hard_regs
, j
))
6735 if (lra_dump_file
!= NULL
&& head_p
)
6737 fprintf (lra_dump_file
,
6738 " ----------------------------------\n");
6741 if (split_reg (false, j
, bb_note (curr_bb
),
6742 next_usage_insns
, NULL
))
6745 usage_insns
[j
].check
= 0;
6753 /* This value affects EBB forming. If probability of edge from EBB to
6754 a BB is not greater than the following value, we don't add the BB
6756 #define EBB_PROBABILITY_CUTOFF \
6757 ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100)
6759 /* Current number of inheritance/split iteration. */
6760 int lra_inheritance_iter
;
6762 /* Entry function for inheritance/split pass. */
6764 lra_inheritance (void)
6767 basic_block bb
, start_bb
;
6770 lra_inheritance_iter
++;
6771 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6773 timevar_push (TV_LRA_INHERITANCE
);
6774 if (lra_dump_file
!= NULL
)
6775 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6776 lra_inheritance_iter
);
6777 curr_usage_insns_check
= 0;
6778 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6779 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6780 usage_insns
[i
].check
= 0;
6781 bitmap_initialize (&check_only_regs
, ®_obstack
);
6782 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6783 bitmap_initialize (&live_regs
, ®_obstack
);
6784 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6785 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6786 FOR_EACH_BB_FN (bb
, cfun
)
6789 if (lra_dump_file
!= NULL
)
6790 fprintf (lra_dump_file
, "EBB");
6791 /* Form a EBB starting with BB. */
6792 bitmap_clear (&ebb_global_regs
);
6793 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6796 if (lra_dump_file
!= NULL
)
6797 fprintf (lra_dump_file
, " %d", bb
->index
);
6798 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6799 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6801 e
= find_fallthru_edge (bb
->succs
);
6804 if (e
->probability
.initialized_p ()
6805 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
6809 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6810 if (lra_dump_file
!= NULL
)
6811 fprintf (lra_dump_file
, "\n");
6812 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6813 /* Remember that the EBB head and tail can change in
6815 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6817 bitmap_release (&ebb_global_regs
);
6818 bitmap_release (&temp_bitmap
);
6819 bitmap_release (&live_regs
);
6820 bitmap_release (&invalid_invariant_regs
);
6821 bitmap_release (&check_only_regs
);
6824 timevar_pop (TV_LRA_INHERITANCE
);
6829 /* This page contains code to undo failed inheritance/split
6832 /* Current number of iteration undoing inheritance/split. */
6833 int lra_undo_inheritance_iter
;
6835 /* Fix BB live info LIVE after removing pseudos created on pass doing
6836 inheritance/split which are REMOVED_PSEUDOS. */
6838 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6843 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6844 if (bitmap_clear_bit (live
, regno
)
6845 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6846 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6849 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6854 if (GET_CODE (reg
) == SUBREG
)
6855 reg
= SUBREG_REG (reg
);
6861 /* Delete a move INSN with destination reg DREGNO and a previous
6862 clobber insn with the same regno. The inheritance/split code can
6863 generate moves with preceding clobber and when we delete such moves
6864 we should delete the clobber insn too to keep the correct life
6867 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6869 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6871 lra_set_insn_deleted (insn
);
6872 lra_assert (dregno
>= 0);
6873 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6874 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6875 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6876 lra_set_insn_deleted (prev_insn
);
6879 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6880 return true if we did any change. The undo transformations for
6881 inheritance looks like
6885 p <- i, i <- p, and i <- i3
6886 where p is original pseudo from which inheritance pseudo i was
6887 created, i and i3 are removed inheritance pseudos, i2 is another
6888 not removed inheritance pseudo. All split pseudos or other
6889 occurrences of removed inheritance pseudos are changed on the
6890 corresponding original pseudos.
6892 The function also schedules insns changed and created during
6893 inheritance/split pass for processing by the subsequent constraint
6896 remove_inheritance_pseudos (bitmap remove_pseudos
)
6899 int regno
, sregno
, prev_sregno
, dregno
;
6902 rtx_insn
*prev_insn
;
6903 bool change_p
, done_p
;
6905 change_p
= ! bitmap_empty_p (remove_pseudos
);
6906 /* We cannot finish the function right away if CHANGE_P is true
6907 because we need to marks insns affected by previous
6908 inheritance/split pass for processing by the subsequent
6910 FOR_EACH_BB_FN (bb
, cfun
)
6912 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6913 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6914 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6916 if (! INSN_P (curr_insn
))
6919 sregno
= dregno
= -1;
6920 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6921 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6923 dregno
= get_regno (SET_DEST (set
));
6924 sregno
= get_regno (SET_SRC (set
));
6927 if (sregno
>= 0 && dregno
>= 0)
6929 if (bitmap_bit_p (remove_pseudos
, dregno
)
6930 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6932 /* invariant inheritance pseudo <- original pseudo */
6933 if (lra_dump_file
!= NULL
)
6935 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6936 dump_insn_slim (lra_dump_file
, curr_insn
);
6937 fprintf (lra_dump_file
, "\n");
6939 delete_move_and_clobber (curr_insn
, dregno
);
6942 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6943 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6945 /* reload pseudo <- invariant inheritance pseudo */
6947 /* We cannot just change the source. It might be
6948 an insn different from the move. */
6949 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6950 rtx_insn
*new_insns
= get_insns ();
6952 lra_assert (single_set (new_insns
) != NULL
6953 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6954 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6955 "Changing reload<-invariant inheritance");
6956 delete_move_and_clobber (curr_insn
, dregno
);
6959 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6960 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6961 || (bitmap_bit_p (remove_pseudos
, dregno
)
6962 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6963 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6964 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6965 || (bitmap_bit_p (remove_pseudos
, dregno
)
6966 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6967 /* One of the following cases:
6968 original <- removed inheritance pseudo
6969 removed inherit pseudo <- another removed inherit pseudo
6970 removed inherit pseudo <- original pseudo
6972 removed_split_pseudo <- original_reg
6973 original_reg <- removed_split_pseudo */
6975 if (lra_dump_file
!= NULL
)
6977 fprintf (lra_dump_file
, " Removing %s:\n",
6978 bitmap_bit_p (&lra_split_regs
, sregno
)
6979 || bitmap_bit_p (&lra_split_regs
, dregno
)
6980 ? "split" : "inheritance");
6981 dump_insn_slim (lra_dump_file
, curr_insn
);
6983 delete_move_and_clobber (curr_insn
, dregno
);
6986 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6987 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6989 /* Search the following pattern:
6990 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6991 original_pseudo <- inherit_or_split_pseudo1
6992 where the 2nd insn is the current insn and
6993 inherit_or_split_pseudo2 is not removed. If it is found,
6994 change the current insn onto:
6995 original_pseudo <- inherit_or_split_pseudo2. */
6996 for (prev_insn
= PREV_INSN (curr_insn
);
6997 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6998 prev_insn
= PREV_INSN (prev_insn
))
7000 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
7001 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
7002 /* There should be no subregs in insn we are
7003 searching because only the original reg might
7004 be in subreg when we changed the mode of
7005 load/store for splitting. */
7006 && REG_P (SET_DEST (prev_set
))
7007 && REG_P (SET_SRC (prev_set
))
7008 && (int) REGNO (SET_DEST (prev_set
)) == sregno
7009 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
7010 >= FIRST_PSEUDO_REGISTER
)
7011 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
7013 /* As we consider chain of inheritance or
7014 splitting described in above comment we should
7015 check that sregno and prev_sregno were
7016 inheritance/split pseudos created from the
7017 same original regno. */
7018 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
7019 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
7020 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
7021 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
7023 lra_assert (GET_MODE (SET_SRC (prev_set
))
7024 == GET_MODE (regno_reg_rtx
[sregno
]));
7025 /* Although we have a single set, the insn can
7026 contain more one sregno register occurrence
7027 as a source. Change all occurrences. */
7028 lra_substitute_pseudo_within_insn (curr_insn
, sregno
,
7031 /* As we are finishing with processing the insn
7032 here, check the destination too as it might
7033 inheritance pseudo for another pseudo. */
7034 if (bitmap_bit_p (remove_pseudos
, dregno
)
7035 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
7037 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
7039 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
7040 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
7042 SET_DEST (set
) = restore_rtx
;
7044 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7045 lra_set_used_insn_alternative_by_uid
7046 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7048 if (lra_dump_file
!= NULL
)
7050 fprintf (lra_dump_file
, " Change reload insn:\n");
7051 dump_insn_slim (lra_dump_file
, curr_insn
);
7058 struct lra_insn_reg
*reg
;
7059 bool restored_regs_p
= false;
7060 bool kept_regs_p
= false;
7062 curr_id
= lra_get_insn_recog_data (curr_insn
);
7063 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
7066 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
7067 if (restore_rtx
!= NULL_RTX
)
7069 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
7071 lra_substitute_pseudo_within_insn
7072 (curr_insn
, regno
, restore_rtx
, false);
7073 restored_regs_p
= true;
7079 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
7081 /* The instruction has changed since the previous
7082 constraints pass. */
7083 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7084 lra_set_used_insn_alternative_by_uid
7085 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7087 else if (restored_regs_p
)
7088 /* The instruction has been restored to the form that
7089 it had during the previous constraints pass. */
7090 lra_update_insn_regno_info (curr_insn
);
7091 if (restored_regs_p
&& lra_dump_file
!= NULL
)
7093 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
7094 dump_insn_slim (lra_dump_file
, curr_insn
);
7102 /* If optional reload pseudos failed to get a hard register or was not
7103 inherited, it is better to remove optional reloads. We do this
7104 transformation after undoing inheritance to figure out necessity to
7105 remove optional reloads easier. Return true if we do any
7108 undo_optional_reloads (void)
7110 bool change_p
, keep_p
;
7111 unsigned int regno
, uid
;
7112 bitmap_iterator bi
, bi2
;
7115 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
7117 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
7118 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7121 /* Keep optional reloads from previous subpasses. */
7122 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
7123 /* If the original pseudo changed its allocation, just
7124 removing the optional pseudo is dangerous as the original
7125 pseudo will have longer live range. */
7126 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
7128 else if (reg_renumber
[regno
] >= 0)
7129 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
7131 insn
= lra_insn_recog_data
[uid
]->insn
;
7132 if ((set
= single_set (insn
)) == NULL_RTX
)
7134 src
= SET_SRC (set
);
7135 dest
= SET_DEST (set
);
7136 if (! REG_P (src
) || ! REG_P (dest
))
7138 if (REGNO (dest
) == regno
7139 /* Ignore insn for optional reloads itself. */
7140 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
7141 /* Check only inheritance on last inheritance pass. */
7142 && (int) REGNO (src
) >= new_regno_start
7143 /* Check that the optional reload was inherited. */
7144 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
7152 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
7153 if (lra_dump_file
!= NULL
)
7154 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
7157 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
7158 auto_bitmap
insn_bitmap (®_obstack
);
7159 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
7161 if (lra_dump_file
!= NULL
)
7162 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
7163 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
7164 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
7166 insn
= lra_insn_recog_data
[uid
]->insn
;
7167 if ((set
= single_set (insn
)) != NULL_RTX
)
7169 src
= SET_SRC (set
);
7170 dest
= SET_DEST (set
);
7171 if (REG_P (src
) && REG_P (dest
)
7172 && ((REGNO (src
) == regno
7173 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
7175 || (REGNO (dest
) == regno
7176 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
7179 if (lra_dump_file
!= NULL
)
7181 fprintf (lra_dump_file
, " Deleting move %u\n",
7183 dump_insn_slim (lra_dump_file
, insn
);
7185 delete_move_and_clobber (insn
, REGNO (dest
));
7188 /* We should not worry about generation memory-memory
7189 moves here as if the corresponding inheritance did
7190 not work (inheritance pseudo did not get a hard reg),
7191 we remove the inheritance pseudo and the optional
7194 lra_substitute_pseudo_within_insn
7195 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
7196 lra_update_insn_regno_info (insn
);
7197 if (lra_dump_file
!= NULL
)
7199 fprintf (lra_dump_file
,
7200 " Restoring original insn:\n");
7201 dump_insn_slim (lra_dump_file
, insn
);
7205 /* Clear restore_regnos. */
7206 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7207 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7211 /* Entry function for undoing inheritance/split transformation. Return true
7212 if we did any RTL change in this pass. */
7214 lra_undo_inheritance (void)
7218 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
7223 lra_undo_inheritance_iter
++;
7224 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
7226 if (lra_dump_file
!= NULL
)
7227 fprintf (lra_dump_file
,
7228 "\n********** Undoing inheritance #%d: **********\n\n",
7229 lra_undo_inheritance_iter
);
7230 auto_bitmap
remove_pseudos (®_obstack
);
7231 n_inherit
= n_all_inherit
= 0;
7232 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7233 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
7236 if (reg_renumber
[regno
] < 0
7237 /* If the original pseudo changed its allocation, just
7238 removing inheritance is dangerous as for changing
7239 allocation we used shorter live-ranges. */
7240 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
7241 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
7242 bitmap_set_bit (remove_pseudos
, regno
);
7246 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
7247 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
7248 n_inherit
, n_all_inherit
,
7249 (double) n_inherit
/ n_all_inherit
* 100);
7250 n_split
= n_all_split
= 0;
7251 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7252 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
7254 int restore_regno
= REGNO (restore_rtx
);
7257 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
7258 ? reg_renumber
[restore_regno
] : restore_regno
);
7259 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
7260 bitmap_set_bit (remove_pseudos
, regno
);
7264 if (lra_dump_file
!= NULL
)
7265 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
7266 regno
, restore_regno
);
7269 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
7270 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
7271 n_split
, n_all_split
,
7272 (double) n_split
/ n_all_split
* 100);
7273 change_p
= remove_inheritance_pseudos (remove_pseudos
);
7274 /* Clear restore_regnos. */
7275 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7276 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7277 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7278 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7279 change_p
= undo_optional_reloads () || change_p
;