1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || (INSN_UID (curr_insn
) >= new_insn_uid_start
273 && curr_insn_set
!= NULL
274 && ((OBJECT_P (SET_SRC (curr_insn_set
))
275 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
276 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
277 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
278 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
279 /* When we don't know what class will be used finally for reload
280 pseudos, we use ALL_REGS. */
281 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
282 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
283 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
284 lra_no_alloc_regs
)));
287 common_class
= ira_reg_class_subset
[rclass
][cl
];
288 if (new_class
!= NULL
)
289 *new_class
= common_class
;
290 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
293 /* Check that there are enough allocatable regs. */
294 class_size
= ira_class_hard_regs_num
[common_class
];
295 for (i
= 0; i
< class_size
; i
++)
297 hard_regno
= ira_class_hard_regs
[common_class
][i
];
298 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
301 for (j
= 0; j
< nregs
; j
++)
302 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
303 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
313 /* Return true if REGNO satisfies a memory constraint. */
317 return get_reg_class (regno
) == NO_REGS
;
320 /* Return 1 if ADDR is a valid memory address for mode MODE in address
321 space AS, and check that each pseudo has the proper kind of hard
324 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
325 rtx addr
, addr_space_t as
)
327 #ifdef GO_IF_LEGITIMATE_ADDRESS
328 lra_assert (ADDR_SPACE_GENERIC_P (as
));
329 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
335 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
340 /* Temporarily eliminates registers in an address (for the lifetime of
342 class address_eliminator
{
344 address_eliminator (struct address_info
*ad
);
345 ~address_eliminator ();
348 struct address_info
*m_ad
;
356 address_eliminator::address_eliminator (struct address_info
*ad
)
358 m_base_loc (strip_subreg (ad
->base_term
)),
359 m_base_reg (NULL_RTX
),
360 m_index_loc (strip_subreg (ad
->index_term
)),
361 m_index_reg (NULL_RTX
)
363 if (m_base_loc
!= NULL
)
365 m_base_reg
= *m_base_loc
;
366 lra_eliminate_reg_if_possible (m_base_loc
);
367 if (m_ad
->base_term2
!= NULL
)
368 *m_ad
->base_term2
= *m_ad
->base_term
;
370 if (m_index_loc
!= NULL
)
372 m_index_reg
= *m_index_loc
;
373 lra_eliminate_reg_if_possible (m_index_loc
);
377 address_eliminator::~address_eliminator ()
379 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
381 *m_base_loc
= m_base_reg
;
382 if (m_ad
->base_term2
!= NULL
)
383 *m_ad
->base_term2
= *m_ad
->base_term
;
385 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
386 *m_index_loc
= m_index_reg
;
389 /* Return true if the eliminated form of AD is a legitimate target address. */
391 valid_address_p (struct address_info
*ad
)
393 address_eliminator
eliminator (ad
);
394 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
397 /* Return true if the eliminated form of memory reference OP satisfies
398 extra memory constraint CONSTRAINT. */
400 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
402 struct address_info ad
;
404 decompose_mem_address (&ad
, op
);
405 address_eliminator
eliminator (&ad
);
406 return constraint_satisfied_p (op
, constraint
);
409 /* Return true if the eliminated form of address AD satisfies extra
410 address constraint CONSTRAINT. */
412 satisfies_address_constraint_p (struct address_info
*ad
,
413 enum constraint_num constraint
)
415 address_eliminator
eliminator (ad
);
416 return constraint_satisfied_p (*ad
->outer
, constraint
);
419 /* Return true if the eliminated form of address OP satisfies extra
420 address constraint CONSTRAINT. */
422 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
424 struct address_info ad
;
426 decompose_lea_address (&ad
, &op
);
427 return satisfies_address_constraint_p (&ad
, constraint
);
430 /* Initiate equivalences for LRA. As we keep original equivalences
431 before any elimination, we need to make copies otherwise any change
432 in insns might change the equivalences. */
434 lra_init_equiv (void)
436 ira_expand_reg_equiv ();
437 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
441 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
442 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
443 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
444 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
448 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
450 /* Update equivalence for REGNO. We need to this as the equivalence
451 might contain other pseudos which are changed by their
454 update_equiv (int regno
)
458 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].memory
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
462 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
463 ira_reg_equiv
[regno
].invariant
464 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
468 /* If we have decided to substitute X with another value, return that
469 value, otherwise return X. */
476 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
477 || ! ira_reg_equiv
[regno
].defined_p
478 || ! ira_reg_equiv
[regno
].profitable_p
479 || lra_get_regno_hard_regno (regno
) >= 0)
481 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
), false, false, true);
503 /* Set up curr_operand_mode. */
505 init_curr_operand_mode (void)
507 int nop
= curr_static_id
->n_operands
;
508 for (int i
= 0; i
< nop
; i
++)
510 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
511 if (mode
== VOIDmode
)
513 /* The .md mode for address operands is the mode of the
514 addressed value rather than the mode of the address itself. */
515 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
518 mode
= curr_static_id
->operand
[i
].mode
;
520 curr_operand_mode
[i
] = mode
;
526 /* The page contains code to reuse input reloads. */
528 /* Structure describes input reload of the current insns. */
531 /* Reloaded value. */
533 /* Reload pseudo used. */
537 /* The number of elements in the following array. */
538 static int curr_insn_input_reloads_num
;
539 /* Array containing info about input reloads. It is used to find the
540 same input reload and reuse the reload pseudo in this case. */
541 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
543 /* Initiate data concerning reuse of input reloads for the current
546 init_curr_insn_input_reloads (void)
548 curr_insn_input_reloads_num
= 0;
551 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
552 created input reload pseudo (only if TYPE is not OP_OUT). Don't
553 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
554 wrapped up in SUBREG. The result pseudo is returned through
555 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
556 reused the already created input reload pseudo. Use TITLE to
557 describe new registers for debug purposes. */
559 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
560 enum reg_class rclass
, bool in_subreg_p
,
561 const char *title
, rtx
*result_reg
)
564 enum reg_class new_class
;
569 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
572 /* Prevent reuse value of expression with side effects,
573 e.g. volatile memory. */
574 if (! side_effects_p (original
))
575 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
576 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
577 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
579 rtx reg
= curr_insn_input_reloads
[i
].reg
;
581 /* If input is equal to original and both are VOIDmode,
582 GET_MODE (reg) might be still different from mode.
583 Ensure we don't return *result_reg with wrong mode. */
584 if (GET_MODE (reg
) != mode
)
588 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
590 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
591 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
595 if (lra_dump_file
!= NULL
)
597 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
598 dump_value_slim (lra_dump_file
, original
, 1);
600 if (new_class
!= lra_get_allocno_class (regno
))
601 lra_change_class (regno
, new_class
, ", change to", false);
602 if (lra_dump_file
!= NULL
)
603 fprintf (lra_dump_file
, "\n");
606 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
607 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
608 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
609 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
615 /* The page contains code to extract memory address parts. */
617 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
619 ok_for_index_p_nonstrict (rtx reg
)
621 unsigned regno
= REGNO (reg
);
623 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
626 /* A version of regno_ok_for_base_p for use here, when all pseudos
627 should count as OK. Arguments as for regno_ok_for_base_p. */
629 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
630 enum rtx_code outer_code
, enum rtx_code index_code
)
632 unsigned regno
= REGNO (reg
);
634 if (regno
>= FIRST_PSEUDO_REGISTER
)
636 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
641 /* The page contains major code to choose the current insn alternative
642 and generate reloads for it. */
644 /* Return the offset from REGNO of the least significant register
647 This function is used to tell whether two registers satisfy
648 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
650 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
651 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
653 lra_constraint_offset (int regno
, enum machine_mode mode
)
655 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
656 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
657 && SCALAR_INT_MODE_P (mode
))
658 return hard_regno_nregs
[regno
][mode
] - 1;
662 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
663 if they are the same hard reg, and has special hacks for
664 auto-increment and auto-decrement. This is specifically intended for
665 process_alt_operands to use in determining whether two operands
666 match. X is the operand whose number is the lower of the two.
668 It is supposed that X is the output operand and Y is the input
669 operand. Y_HARD_REGNO is the final hard regno of register Y or
670 register in subreg Y as we know it now. Otherwise, it is a
673 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
676 RTX_CODE code
= GET_CODE (x
);
681 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
682 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
686 i
= get_hard_regno (x
);
690 if ((j
= y_hard_regno
) < 0)
693 i
+= lra_constraint_offset (i
, GET_MODE (x
));
694 j
+= lra_constraint_offset (j
, GET_MODE (y
));
699 /* If two operands must match, because they are really a single
700 operand of an assembler insn, then two post-increments are invalid
701 because the assembler insn would increment only once. On the
702 other hand, a post-increment matches ordinary indexing if the
703 post-increment is the output operand. */
704 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
705 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
707 /* Two pre-increments are invalid because the assembler insn would
708 increment only once. On the other hand, a pre-increment matches
709 ordinary indexing if the pre-increment is the input operand. */
710 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
711 || GET_CODE (y
) == PRE_MODIFY
)
712 return operands_match_p (x
, XEXP (y
, 0), -1);
716 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
717 && x
== SUBREG_REG (y
))
719 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
720 && SUBREG_REG (x
) == y
)
723 /* Now we have disposed of all the cases in which different rtx
725 if (code
!= GET_CODE (y
))
728 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
729 if (GET_MODE (x
) != GET_MODE (y
))
738 return XEXP (x
, 0) == XEXP (y
, 0);
740 return XSTR (x
, 0) == XSTR (y
, 0);
746 /* Compare the elements. If any pair of corresponding elements fail
747 to match, return false for the whole things. */
749 fmt
= GET_RTX_FORMAT (code
);
750 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
756 if (XWINT (x
, i
) != XWINT (y
, i
))
761 if (XINT (x
, i
) != XINT (y
, i
))
766 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
775 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
777 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
779 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
785 /* It is believed that rtx's at this level will never
786 contain anything but integers and other rtx's, except for
787 within LABEL_REFs and SYMBOL_REFs. */
795 /* True if X is a constant that can be forced into the constant pool.
796 MODE is the mode of the operand, or VOIDmode if not known. */
797 #define CONST_POOL_OK_P(MODE, X) \
798 ((MODE) != VOIDmode \
800 && GET_CODE (X) != HIGH \
801 && !targetm.cannot_force_const_mem (MODE, X))
803 /* True if C is a non-empty register class that has too few registers
804 to be safely used as a reload target class. */
805 #define SMALL_REGISTER_CLASS_P(C) \
806 (ira_class_hard_regs_num [(C)] == 1 \
807 || (ira_class_hard_regs_num [(C)] >= 1 \
808 && targetm.class_likely_spilled_p (C)))
810 /* If REG is a reload pseudo, try to make its class satisfying CL. */
812 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
814 enum reg_class rclass
;
816 /* Do not make more accurate class from reloads generated. They are
817 mostly moves with a lot of constraints. Making more accurate
818 class may results in very narrow class and impossibility of find
819 registers for several reloads of one insn. */
820 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
822 if (GET_CODE (reg
) == SUBREG
)
823 reg
= SUBREG_REG (reg
);
824 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
826 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
827 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
830 /* Generate reloads for matching OUT and INS (array of input operand
831 numbers with end marker -1) with reg class GOAL_CLASS. Add input
832 and output reloads correspondingly to the lists *BEFORE and *AFTER.
833 OUT might be negative. In this case we generate input reloads for
834 matched input operands INS. */
836 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
837 rtx
*before
, rtx
*after
)
840 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
841 enum machine_mode inmode
, outmode
;
842 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
843 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
845 inmode
= curr_operand_mode
[ins
[0]];
846 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
847 push_to_sequence (*before
);
848 if (inmode
!= outmode
)
850 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
853 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
855 if (SCALAR_INT_MODE_P (inmode
))
856 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
858 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
859 LRA_SUBREG_P (new_out_reg
) = 1;
860 /* If the input reg is dying here, we can use the same hard
861 register for REG and IN_RTX. We do it only for original
862 pseudos as reload pseudos can die although original
863 pseudos still live where reload pseudos dies. */
864 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
865 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
866 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
871 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
873 if (SCALAR_INT_MODE_P (outmode
))
874 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
876 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
877 /* NEW_IN_REG is non-paradoxical subreg. We don't want
878 NEW_OUT_REG living above. We add clobber clause for
879 this. This is just a temporary clobber. We can remove
880 it at the end of LRA work. */
881 clobber
= emit_clobber (new_out_reg
);
882 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
883 LRA_SUBREG_P (new_in_reg
) = 1;
884 if (GET_CODE (in_rtx
) == SUBREG
)
886 rtx subreg_reg
= SUBREG_REG (in_rtx
);
888 /* If SUBREG_REG is dying here and sub-registers IN_RTX
889 and NEW_IN_REG are similar, we can use the same hard
890 register for REG and SUBREG_REG. */
891 if (REG_P (subreg_reg
)
892 && (int) REGNO (subreg_reg
) < lra_new_regno_start
893 && GET_MODE (subreg_reg
) == outmode
894 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
895 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
896 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
902 /* Pseudos have values -- see comments for lra_reg_info.
903 Different pseudos with the same value do not conflict even if
904 they live in the same place. When we create a pseudo we
905 assign value of original pseudo (if any) from which we
906 created the new pseudo. If we create the pseudo from the
907 input pseudo, the new pseudo will no conflict with the input
908 pseudo which is wrong when the input pseudo lives after the
909 insn and as the new pseudo value is changed by the insn
910 output. Therefore we create the new pseudo from the output.
912 We cannot reuse the current output register because we might
913 have a situation like "a <- a op b", where the constraints
914 force the second input operand ("b") to match the output
915 operand ("a"). "b" must then be copied into a new register
916 so that it doesn't clobber the current value of "a". */
918 new_in_reg
= new_out_reg
919 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
922 /* In operand can be got from transformations before processing insn
923 constraints. One example of such transformations is subreg
924 reloading (see function simplify_operand_subreg). The new
925 pseudos created by the transformations might have inaccurate
926 class (ALL_REGS) and we should make their classes more
928 narrow_reload_pseudo_class (in_rtx
, goal_class
);
929 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
930 *before
= get_insns ();
932 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
935 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
936 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
937 *curr_id
->operand_loc
[in
] = new_in_reg
;
939 lra_update_dups (curr_id
, ins
);
942 /* See a comment for the input operand above. */
943 narrow_reload_pseudo_class (out_rtx
, goal_class
);
944 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
947 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
949 *after
= get_insns ();
952 *curr_id
->operand_loc
[out
] = new_out_reg
;
953 lra_update_dup (curr_id
, out
);
956 /* Return register class which is union of all reg classes in insn
957 constraint alternative string starting with P. */
958 static enum reg_class
959 reg_class_from_constraints (const char *p
)
962 enum reg_class op_class
= NO_REGS
;
965 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
972 op_class
= (reg_class_subunion
973 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
979 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
983 enum constraint_num cn
= lookup_constraint (p
);
984 enum reg_class cl
= reg_class_for_constraint (cn
);
987 if (insn_extra_address_constraint (cn
))
989 = (reg_class_subunion
990 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
995 op_class
= reg_class_subunion
[op_class
][cl
];
998 while ((p
+= len
), c
);
1002 /* If OP is a register, return the class of the register as per
1003 get_reg_class, otherwise return NO_REGS. */
1004 static inline enum reg_class
1005 get_op_class (rtx op
)
1007 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1010 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1011 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1012 SUBREG for VAL to make them equal. */
1014 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1016 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1018 /* Usually size of mem_pseudo is greater than val size but in
1019 rare cases it can be less as it can be defined by target
1020 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1023 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1024 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1026 LRA_SUBREG_P (val
) = 1;
1030 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1031 LRA_SUBREG_P (mem_pseudo
) = 1;
1035 ? gen_move_insn (mem_pseudo
, val
)
1036 : gen_move_insn (val
, mem_pseudo
));
1039 /* Process a special case insn (register move), return true if we
1040 don't need to process it anymore. INSN should be a single set
1041 insn. Set up that RTL was changed through CHANGE_P and macro
1042 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1045 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1048 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
1049 enum reg_class dclass
, sclass
, secondary_class
;
1050 enum machine_mode sreg_mode
;
1051 secondary_reload_info sri
;
1053 lra_assert (curr_insn_set
!= NULL_RTX
);
1054 dreg
= dest
= SET_DEST (curr_insn_set
);
1055 sreg
= src
= SET_SRC (curr_insn_set
);
1056 if (GET_CODE (dest
) == SUBREG
)
1057 dreg
= SUBREG_REG (dest
);
1058 if (GET_CODE (src
) == SUBREG
)
1059 sreg
= SUBREG_REG (src
);
1060 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1062 sclass
= dclass
= NO_REGS
;
1064 dclass
= get_reg_class (REGNO (dreg
));
1065 if (dclass
== ALL_REGS
)
1066 /* ALL_REGS is used for new pseudos created by transformations
1067 like reload of SUBREG_REG (see function
1068 simplify_operand_subreg). We don't know their class yet. We
1069 should figure out the class from processing the insn
1070 constraints not in this fast path function. Even if ALL_REGS
1071 were a right class for the pseudo, secondary_... hooks usually
1072 are not define for ALL_REGS. */
1074 sreg_mode
= GET_MODE (sreg
);
1077 sclass
= get_reg_class (REGNO (sreg
));
1078 if (sclass
== ALL_REGS
)
1079 /* See comments above. */
1081 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1083 #ifdef SECONDARY_MEMORY_NEEDED
1084 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1085 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1086 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1087 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1095 if (! REG_P (dreg
) || ! REG_P (sreg
))
1097 sri
.prev_sri
= NULL
;
1098 sri
.icode
= CODE_FOR_nothing
;
1100 secondary_class
= NO_REGS
;
1101 /* Set up hard register for a reload pseudo for hook
1102 secondary_reload because some targets just ignore unassigned
1103 pseudos in the hook. */
1104 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1106 dregno
= REGNO (dreg
);
1107 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1111 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1113 sregno
= REGNO (sreg
);
1114 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1118 if (sclass
!= NO_REGS
)
1120 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1121 (reg_class_t
) sclass
,
1122 GET_MODE (src
), &sri
);
1123 if (sclass
== NO_REGS
1124 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1125 && dclass
!= NO_REGS
))
1127 enum reg_class old_sclass
= secondary_class
;
1128 secondary_reload_info old_sri
= sri
;
1130 sri
.prev_sri
= NULL
;
1131 sri
.icode
= CODE_FOR_nothing
;
1134 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1135 (reg_class_t
) dclass
,
1137 /* Check the target hook consistency. */
1139 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1140 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1141 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1144 reg_renumber
[sregno
] = -1;
1146 reg_renumber
[dregno
] = -1;
1147 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1151 if (secondary_class
!= NO_REGS
)
1152 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1156 if (old_sreg
!= sreg
)
1157 sreg
= copy_rtx (sreg
);
1158 if (sri
.icode
== CODE_FOR_nothing
)
1159 lra_emit_move (new_reg
, sreg
);
1162 enum reg_class scratch_class
;
1164 scratch_class
= (reg_class_from_constraints
1165 (insn_data
[sri
.icode
].operand
[2].constraint
));
1166 scratch_reg
= (lra_create_new_reg_with_unique_value
1167 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1168 scratch_class
, "scratch"));
1169 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1170 sreg
, scratch_reg
));
1172 before
= get_insns ();
1174 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1175 if (new_reg
!= NULL_RTX
)
1177 if (GET_CODE (src
) == SUBREG
)
1178 SUBREG_REG (src
) = new_reg
;
1180 SET_SRC (curr_insn_set
) = new_reg
;
1184 if (lra_dump_file
!= NULL
)
1186 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1187 dump_insn_slim (lra_dump_file
, curr_insn
);
1189 lra_set_insn_deleted (curr_insn
);
1195 /* The following data describe the result of process_alt_operands.
1196 The data are used in curr_insn_transform to generate reloads. */
1198 /* The chosen reg classes which should be used for the corresponding
1200 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1201 /* True if the operand should be the same as another operand and that
1202 other operand does not need a reload. */
1203 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1204 /* True if the operand does not need a reload. */
1205 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1206 /* True if the operand can be offsetable memory. */
1207 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1208 /* The number of an operand to which given operand can be matched to. */
1209 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1210 /* The number of elements in the following array. */
1211 static int goal_alt_dont_inherit_ops_num
;
1212 /* Numbers of operands whose reload pseudos should not be inherited. */
1213 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1214 /* True if the insn commutative operands should be swapped. */
1215 static bool goal_alt_swapped
;
1216 /* The chosen insn alternative. */
1217 static int goal_alt_number
;
1219 /* The following five variables are used to choose the best insn
1220 alternative. They reflect final characteristics of the best
1223 /* Number of necessary reloads and overall cost reflecting the
1224 previous value and other unpleasantness of the best alternative. */
1225 static int best_losers
, best_overall
;
1226 /* Overall number hard registers used for reloads. For example, on
1227 some targets we need 2 general registers to reload DFmode and only
1228 one floating point register. */
1229 static int best_reload_nregs
;
1230 /* Overall number reflecting distances of previous reloading the same
1231 value. The distances are counted from the current BB start. It is
1232 used to improve inheritance chances. */
1233 static int best_reload_sum
;
1235 /* True if the current insn should have no correspondingly input or
1237 static bool no_input_reloads_p
, no_output_reloads_p
;
1239 /* True if we swapped the commutative operands in the current
1241 static int curr_swapped
;
1243 /* Arrange for address element *LOC to be a register of class CL.
1244 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1245 automodified value; handle that case by adding the required output
1246 reloads to list AFTER. Return true if the RTL was changed. */
1248 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1251 enum reg_class rclass
, new_class
;
1254 enum machine_mode mode
;
1255 bool subreg_p
, before_p
= false;
1257 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1259 loc
= &SUBREG_REG (*loc
);
1261 mode
= GET_MODE (reg
);
1264 /* Always reload memory in an address even if the target supports
1266 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1271 regno
= REGNO (reg
);
1272 rclass
= get_reg_class (regno
);
1273 if ((*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1275 if (lra_dump_file
!= NULL
)
1277 fprintf (lra_dump_file
,
1278 "Changing pseudo %d in address of insn %u on equiv ",
1279 REGNO (reg
), INSN_UID (curr_insn
));
1280 dump_value_slim (lra_dump_file
, *loc
, 1);
1281 fprintf (lra_dump_file
, "\n");
1283 *loc
= copy_rtx (*loc
);
1285 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1288 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1289 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1292 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1294 lra_change_class (regno
, new_class
, " Change to", true);
1302 push_to_sequence (*before
);
1303 lra_emit_move (new_reg
, reg
);
1304 *before
= get_insns ();
1311 lra_emit_move (reg
, new_reg
);
1313 *after
= get_insns ();
1319 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1320 the insn to be inserted before curr insn. AFTER returns the
1321 the insn to be inserted after curr insn. ORIGREG and NEWREG
1322 are the original reg and new reg for reload. */
1324 insert_move_for_subreg (rtx
*before
, rtx
*after
, rtx origreg
, rtx newreg
)
1328 push_to_sequence (*before
);
1329 lra_emit_move (newreg
, origreg
);
1330 *before
= get_insns ();
1336 lra_emit_move (origreg
, newreg
);
1338 *after
= get_insns ();
1343 /* Make reloads for subreg in operand NOP with internal subreg mode
1344 REG_MODE, add new reloads for further processing. Return true if
1345 any reload was generated. */
1347 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1351 enum machine_mode mode
;
1353 rtx operand
= *curr_id
->operand_loc
[nop
];
1354 enum reg_class regclass
;
1357 before
= after
= NULL_RTX
;
1359 if (GET_CODE (operand
) != SUBREG
)
1362 mode
= GET_MODE (operand
);
1363 reg
= SUBREG_REG (operand
);
1364 type
= curr_static_id
->operand
[nop
].type
;
1365 /* If we change address for paradoxical subreg of memory, the
1366 address might violate the necessary alignment or the access might
1367 be slow. So take this into consideration. We should not worry
1368 about access beyond allocated memory for paradoxical memory
1369 subregs as we don't substitute such equiv memory (see processing
1370 equivalences in function lra_constraints) and because for spilled
1371 pseudos we allocate stack memory enough for the biggest
1372 corresponding paradoxical subreg. */
1374 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1375 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1376 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1378 alter_subreg (curr_id
->operand_loc
[nop
], false);
1381 /* Put constant into memory when we have mixed modes. It generates
1382 a better code in most cases as it does not need a secondary
1383 reload memory. It also prevents LRA looping when LRA is using
1384 secondary reload memory again and again. */
1385 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1386 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1388 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1389 alter_subreg (curr_id
->operand_loc
[nop
], false);
1392 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1393 if there may be a problem accessing OPERAND in the outer
1396 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1397 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1398 /* Don't reload paradoxical subregs because we could be looping
1399 having repeatedly final regno out of hard regs range. */
1400 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1401 >= hard_regno_nregs
[hard_regno
][mode
])
1402 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1403 SUBREG_BYTE (operand
), mode
) < 0
1404 /* Don't reload subreg for matching reload. It is actually
1405 valid subreg in LRA. */
1406 && ! LRA_SUBREG_P (operand
))
1407 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1409 enum reg_class rclass
;
1412 /* There is a big probability that we will get the same class
1413 for the new pseudo and we will get the same insn which
1414 means infinite looping. So spill the new pseudo. */
1417 /* The class will be defined later in curr_insn_transform. */
1419 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1421 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1422 rclass
, TRUE
, "subreg reg", &new_reg
))
1424 bool insert_before
, insert_after
;
1425 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1427 insert_before
= (type
!= OP_OUT
1428 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1429 insert_after
= (type
!= OP_IN
);
1430 insert_move_for_subreg (insert_before
? &before
: NULL
,
1431 insert_after
? &after
: NULL
,
1434 SUBREG_REG (operand
) = new_reg
;
1435 lra_process_new_insns (curr_insn
, before
, after
,
1436 "Inserting subreg reload");
1439 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1440 IRA allocates hardreg to the inner pseudo reg according to its mode
1441 instead of the outermode, so the size of the hardreg may not be enough
1442 to contain the outermode operand, in that case we may need to insert
1443 reload for the reg. For the following two types of paradoxical subreg,
1444 we need to insert reload:
1445 1. If the op_type is OP_IN, and the hardreg could not be paired with
1446 other hardreg to contain the outermode operand
1447 (checked by in_hard_reg_set_p), we need to insert the reload.
1448 2. If the op_type is OP_OUT or OP_INOUT.
1450 Here is a paradoxical subreg example showing how the reload is generated:
1452 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1453 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1455 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1456 here, if reg107 is assigned to hardreg R15, because R15 is the last
1457 hardreg, compiler cannot find another hardreg to pair with R15 to
1458 contain TImode data. So we insert a TImode reload reg180 for it.
1459 After reload is inserted:
1461 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1462 (reg:DI 107 [ __comp ])) -1
1463 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1464 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1466 Two reload hard registers will be allocated to reg180 to save TImode data
1468 else if (REG_P (reg
)
1469 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1470 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1471 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1472 < hard_regno_nregs
[hard_regno
][mode
])
1473 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1475 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1478 /* The class will be defined later in curr_insn_transform. */
1479 enum reg_class rclass
1480 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1482 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1483 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1486 bool insert_before
, insert_after
;
1488 PUT_MODE (new_reg
, mode
);
1489 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1490 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1492 insert_before
= (type
!= OP_OUT
);
1493 insert_after
= (type
!= OP_IN
);
1494 insert_move_for_subreg (insert_before
? &before
: NULL
,
1495 insert_after
? &after
: NULL
,
1498 SUBREG_REG (operand
) = new_reg
;
1499 lra_process_new_insns (curr_insn
, before
, after
,
1500 "Inserting paradoxical subreg reload");
1506 /* Return TRUE if X refers for a hard register from SET. */
1508 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1510 int i
, j
, x_hard_regno
;
1511 enum machine_mode mode
;
1517 code
= GET_CODE (x
);
1518 mode
= GET_MODE (x
);
1522 code
= GET_CODE (x
);
1523 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1524 mode
= GET_MODE (x
);
1529 x_hard_regno
= get_hard_regno (x
);
1530 return (x_hard_regno
>= 0
1531 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1535 struct address_info ad
;
1537 decompose_mem_address (&ad
, x
);
1538 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1540 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1543 fmt
= GET_RTX_FORMAT (code
);
1544 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1548 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1551 else if (fmt
[i
] == 'E')
1553 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1554 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1561 /* Return true if OP is a spilled pseudo. */
1563 spilled_pseudo_p (rtx op
)
1566 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1569 /* Return true if X is a general constant. */
1571 general_constant_p (rtx x
)
1573 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1577 reg_in_class_p (rtx reg
, enum reg_class cl
)
1580 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1581 return in_class_p (reg
, cl
, NULL
);
1584 /* Major function to choose the current insn alternative and what
1585 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1586 negative we should consider only this alternative. Return false if
1587 we can not choose the alternative or find how to reload the
1590 process_alt_operands (int only_alternative
)
1593 int nop
, overall
, nalt
;
1594 int n_alternatives
= curr_static_id
->n_alternatives
;
1595 int n_operands
= curr_static_id
->n_operands
;
1596 /* LOSERS counts the operands that don't fit this alternative and
1597 would require loading. */
1599 /* REJECT is a count of how undesirable this alternative says it is
1600 if any reloading is required. If the alternative matches exactly
1601 then REJECT is ignored, but otherwise it gets this much counted
1602 against it in addition to the reloading needed. */
1604 /* The number of elements in the following array. */
1605 int early_clobbered_regs_num
;
1606 /* Numbers of operands which are early clobber registers. */
1607 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1608 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1609 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1610 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1611 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1612 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1613 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1614 /* The number of elements in the following array. */
1615 int curr_alt_dont_inherit_ops_num
;
1616 /* Numbers of operands whose reload pseudos should not be inherited. */
1617 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1619 /* The register when the operand is a subreg of register, otherwise the
1621 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1622 /* The register if the operand is a register or subreg of register,
1624 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1625 int hard_regno
[MAX_RECOG_OPERANDS
];
1626 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1627 int reload_nregs
, reload_sum
;
1631 /* Calculate some data common for all alternatives to speed up the
1633 for (nop
= 0; nop
< n_operands
; nop
++)
1637 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1638 /* The real hard regno of the operand after the allocation. */
1639 hard_regno
[nop
] = get_hard_regno (op
);
1641 operand_reg
[nop
] = reg
= op
;
1642 biggest_mode
[nop
] = GET_MODE (op
);
1643 if (GET_CODE (op
) == SUBREG
)
1645 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1646 if (GET_MODE_SIZE (biggest_mode
[nop
])
1647 < GET_MODE_SIZE (GET_MODE (reg
)))
1648 biggest_mode
[nop
] = GET_MODE (reg
);
1651 operand_reg
[nop
] = NULL_RTX
;
1652 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1653 || ((int) REGNO (reg
)
1654 == lra_get_elimination_hard_regno (REGNO (reg
))))
1655 no_subreg_reg_operand
[nop
] = reg
;
1657 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1658 /* Just use natural mode for elimination result. It should
1659 be enough for extra constraints hooks. */
1660 = regno_reg_rtx
[hard_regno
[nop
]];
1663 /* The constraints are made of several alternatives. Each operand's
1664 constraint looks like foo,bar,... with commas separating the
1665 alternatives. The first alternatives for all operands go
1666 together, the second alternatives go together, etc.
1668 First loop over alternatives. */
1669 alternative_mask enabled
= curr_id
->enabled_alternatives
;
1670 if (only_alternative
>= 0)
1671 enabled
&= ALTERNATIVE_BIT (only_alternative
);
1673 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1675 /* Loop over operands for one constraint alternative. */
1676 if (!TEST_BIT (enabled
, nalt
))
1679 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1680 for (nop
= 0; nop
< n_operands
; nop
++)
1682 int inc
= (curr_static_id
1683 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1684 if (lra_dump_file
!= NULL
&& inc
!= 0)
1685 fprintf (lra_dump_file
,
1686 " Staticly defined alt reject+=%d\n", inc
);
1689 early_clobbered_regs_num
= 0;
1691 for (nop
= 0; nop
< n_operands
; nop
++)
1695 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1696 bool win
, did_match
, offmemok
, early_clobber_p
;
1697 /* false => this operand can be reloaded somehow for this
1700 /* true => this operand can be reloaded if the alternative
1703 /* True if a constant forced into memory would be OK for
1706 enum reg_class this_alternative
, this_costly_alternative
;
1707 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1708 bool this_alternative_match_win
, this_alternative_win
;
1709 bool this_alternative_offmemok
;
1711 enum machine_mode mode
;
1712 enum constraint_num cn
;
1714 opalt_num
= nalt
* n_operands
+ nop
;
1715 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1717 /* Fast track for no constraints at all. */
1718 curr_alt
[nop
] = NO_REGS
;
1719 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1720 curr_alt_win
[nop
] = true;
1721 curr_alt_match_win
[nop
] = false;
1722 curr_alt_offmemok
[nop
] = false;
1723 curr_alt_matches
[nop
] = -1;
1727 op
= no_subreg_reg_operand
[nop
];
1728 mode
= curr_operand_mode
[nop
];
1730 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1733 early_clobber_p
= false;
1734 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1736 this_costly_alternative
= this_alternative
= NO_REGS
;
1737 /* We update set of possible hard regs besides its class
1738 because reg class might be inaccurate. For example,
1739 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1740 is translated in HI_REGS because classes are merged by
1741 pairs and there is no accurate intermediate class. */
1742 CLEAR_HARD_REG_SET (this_alternative_set
);
1743 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1744 this_alternative_win
= false;
1745 this_alternative_match_win
= false;
1746 this_alternative_offmemok
= false;
1747 this_alternative_matches
= -1;
1749 /* An empty constraint should be excluded by the fast
1751 lra_assert (*p
!= 0 && *p
!= ',');
1753 /* Scan this alternative's specs for this operand; set WIN
1754 if the operand fits any letter in this alternative.
1755 Otherwise, clear BADOP if this operand could fit some
1756 letter after reloads, or set WINREG if this operand could
1757 fit after reloads provided the constraint allows some
1762 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1771 case '=': case '+': case '?': case '*': case '!':
1772 case ' ': case '\t':
1776 /* We only support one commutative marker, the first
1777 one. We already set commutative above. */
1781 early_clobber_p
= true;
1785 /* Ignore rest of this alternative. */
1789 case '0': case '1': case '2': case '3': case '4':
1790 case '5': case '6': case '7': case '8': case '9':
1795 m
= strtoul (p
, &end
, 10);
1798 lra_assert (nop
> m
);
1800 this_alternative_matches
= m
;
1801 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1802 /* We are supposed to match a previous operand.
1803 If we do, we win if that one did. If we do
1804 not, count both of the operands as losers.
1805 (This is too conservative, since most of the
1806 time only a single reload insn will be needed
1807 to make the two operands win. As a result,
1808 this alternative may be rejected when it is
1809 actually desirable.) */
1811 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1812 *curr_id
->operand_loc
[m
], m_hregno
))
1814 /* We should reject matching of an early
1815 clobber operand if the matching operand is
1816 not dying in the insn. */
1817 if (! curr_static_id
->operand
[m
].early_clobber
1818 || operand_reg
[nop
] == NULL_RTX
1819 || (find_regno_note (curr_insn
, REG_DEAD
,
1821 || REGNO (op
) == REGNO (operand_reg
[m
])))
1826 /* If we are matching a non-offsettable
1827 address where an offsettable address was
1828 expected, then we must reject this
1829 combination, because we can't reload
1831 if (curr_alt_offmemok
[m
]
1832 && MEM_P (*curr_id
->operand_loc
[m
])
1833 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1838 /* Operands don't match. Both operands must
1839 allow a reload register, otherwise we
1840 cannot make them match. */
1841 if (curr_alt
[m
] == NO_REGS
)
1843 /* Retroactively mark the operand we had to
1844 match as a loser, if it wasn't already and
1845 it wasn't matched to a register constraint
1846 (e.g it might be matched by memory). */
1848 && (operand_reg
[m
] == NULL_RTX
1849 || hard_regno
[m
] < 0))
1853 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1854 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1857 /* Prefer matching earlyclobber alternative as
1858 it results in less hard regs required for
1859 the insn than a non-matching earlyclobber
1861 if (curr_static_id
->operand
[m
].early_clobber
)
1863 if (lra_dump_file
!= NULL
)
1866 " %d Matching earlyclobber alt:"
1871 /* Otherwise we prefer no matching
1872 alternatives because it gives more freedom
1874 else if (operand_reg
[nop
] == NULL_RTX
1875 || (find_regno_note (curr_insn
, REG_DEAD
,
1876 REGNO (operand_reg
[nop
]))
1879 if (lra_dump_file
!= NULL
)
1882 " %d Matching alt: reject+=2\n",
1887 /* If we have to reload this operand and some
1888 previous operand also had to match the same
1889 thing as this operand, we don't know how to do
1891 if (!match_p
|| !curr_alt_win
[m
])
1893 for (i
= 0; i
< nop
; i
++)
1894 if (curr_alt_matches
[i
] == m
)
1902 /* This can be fixed with reloads if the operand
1903 we are supposed to match can be fixed with
1906 this_alternative
= curr_alt
[m
];
1907 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1908 winreg
= this_alternative
!= NO_REGS
;
1913 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1915 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1916 IOR_HARD_REG_SET (this_alternative_set
,
1917 reg_class_contents
[cl
]);
1920 this_costly_alternative
1921 = reg_class_subunion
[this_costly_alternative
][cl
];
1922 IOR_HARD_REG_SET (this_costly_alternative_set
,
1923 reg_class_contents
[cl
]);
1929 case TARGET_MEM_CONSTRAINT
:
1930 if (MEM_P (op
) || spilled_pseudo_p (op
))
1932 /* We can put constant or pseudo value into memory
1933 to satisfy the constraint. */
1934 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1941 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1942 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1948 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1949 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1953 /* Memory op whose address is not offsettable. */
1956 && ! offsettable_nonstrict_memref_p (op
))
1960 /* Memory operand whose address is offsettable. */
1963 && offsettable_nonstrict_memref_p (op
))
1964 || spilled_pseudo_p (op
))
1966 /* We can put constant or pseudo value into memory
1967 or make memory address offsetable to satisfy the
1969 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1977 if (GET_CODE (op
) == CONST_DOUBLE
1978 || (GET_CODE (op
) == CONST_VECTOR
1979 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1985 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1986 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1991 if (CONST_SCALAR_INT_P (op
))
1995 if (general_constant_p (op
))
2000 if (CONST_SCALAR_INT_P (op
))
2012 if (CONST_INT_P (op
)
2013 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2018 /* This constraint should be excluded by the fast
2025 || general_constant_p (op
)
2026 || spilled_pseudo_p (op
))
2028 /* Drop through into 'r' case. */
2035 cn
= lookup_constraint (p
);
2036 switch (get_constraint_type (cn
))
2039 cl
= reg_class_for_constraint (cn
);
2046 && satisfies_memory_constraint_p (op
, cn
))
2048 else if (spilled_pseudo_p (op
))
2051 /* If we didn't already win, we can reload constants
2052 via force_const_mem or put the pseudo value into
2053 memory, or make other memory by reloading the
2054 address like for 'o'. */
2055 if (CONST_POOL_OK_P (mode
, op
)
2056 || MEM_P (op
) || REG_P (op
))
2063 /* If we didn't already win, we can reload the address
2064 into a base register. */
2065 if (satisfies_address_constraint_p (op
, cn
))
2067 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2073 if (constraint_satisfied_p (op
, cn
))
2080 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2081 IOR_HARD_REG_SET (this_alternative_set
,
2082 reg_class_contents
[cl
]);
2085 this_costly_alternative
2086 = reg_class_subunion
[this_costly_alternative
][cl
];
2087 IOR_HARD_REG_SET (this_costly_alternative_set
,
2088 reg_class_contents
[cl
]);
2090 if (mode
== BLKmode
)
2095 if (hard_regno
[nop
] >= 0
2096 && in_hard_reg_set_p (this_alternative_set
,
2097 mode
, hard_regno
[nop
]))
2099 else if (hard_regno
[nop
] < 0
2100 && in_class_p (op
, this_alternative
, NULL
))
2105 if (c
!= ' ' && c
!= '\t')
2106 costly_p
= c
== '*';
2108 while ((p
+= len
), c
);
2110 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2111 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2112 /* Record which operands fit this alternative. */
2115 this_alternative_win
= true;
2116 if (operand_reg
[nop
] != NULL_RTX
)
2118 if (hard_regno
[nop
] >= 0)
2120 if (in_hard_reg_set_p (this_costly_alternative_set
,
2121 mode
, hard_regno
[nop
]))
2123 if (lra_dump_file
!= NULL
)
2124 fprintf (lra_dump_file
,
2125 " %d Costly set: reject++\n",
2132 /* Prefer won reg to spilled pseudo under other
2133 equal conditions for possibe inheritance. */
2136 if (lra_dump_file
!= NULL
)
2139 " %d Non pseudo reload: reject++\n",
2143 if (in_class_p (operand_reg
[nop
],
2144 this_costly_alternative
, NULL
))
2146 if (lra_dump_file
!= NULL
)
2149 " %d Non pseudo costly reload:"
2155 /* We simulate the behaviour of old reload here.
2156 Although scratches need hard registers and it
2157 might result in spilling other pseudos, no reload
2158 insns are generated for the scratches. So it
2159 might cost something but probably less than old
2160 reload pass believes. */
2163 if (lra_dump_file
!= NULL
)
2164 fprintf (lra_dump_file
,
2165 " %d Scratch win: reject+=2\n",
2172 this_alternative_match_win
= true;
2175 int const_to_mem
= 0;
2178 /* Never do output reload of stack pointer. It makes
2179 impossible to do elimination when SP is changed in
2181 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2182 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2185 /* If this alternative asks for a specific reg class, see if there
2186 is at least one allocatable register in that class. */
2188 = (this_alternative
== NO_REGS
2189 || (hard_reg_set_subset_p
2190 (reg_class_contents
[this_alternative
],
2191 lra_no_alloc_regs
)));
2193 /* For asms, verify that the class for this alternative is possible
2194 for the mode that is specified. */
2195 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2198 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2199 if (HARD_REGNO_MODE_OK (i
, mode
)
2200 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2203 if (i
== FIRST_PSEUDO_REGISTER
)
2207 /* If this operand accepts a register, and if the
2208 register class has at least one allocatable register,
2209 then this operand can be reloaded. */
2210 if (winreg
&& !no_regs_p
)
2215 if (lra_dump_file
!= NULL
)
2216 fprintf (lra_dump_file
,
2217 " alt=%d: Bad operand -- refuse\n",
2222 /* If not assigned pseudo has a class which a subset of
2223 required reg class, it is a less costly alternative
2224 as the pseudo still can get a hard reg of necessary
2226 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2227 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2228 && ira_class_subset_p
[this_alternative
][cl
])
2230 if (lra_dump_file
!= NULL
)
2233 " %d Super set class reg: reject-=3\n", nop
);
2237 this_alternative_offmemok
= offmemok
;
2238 if (this_costly_alternative
!= NO_REGS
)
2240 if (lra_dump_file
!= NULL
)
2241 fprintf (lra_dump_file
,
2242 " %d Costly loser: reject++\n", nop
);
2245 /* If the operand is dying, has a matching constraint,
2246 and satisfies constraints of the matched operand
2247 which failed to satisfy the own constraints, most probably
2248 the reload for this operand will be gone. */
2249 if (this_alternative_matches
>= 0
2250 && !curr_alt_win
[this_alternative_matches
]
2252 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2253 && (hard_regno
[nop
] >= 0
2254 ? in_hard_reg_set_p (this_alternative_set
,
2255 mode
, hard_regno
[nop
])
2256 : in_class_p (op
, this_alternative
, NULL
)))
2258 if (lra_dump_file
!= NULL
)
2261 " %d Dying matched operand reload: reject++\n",
2267 /* Strict_low_part requires to reload the register
2268 not the sub-register. In this case we should
2269 check that a final reload hard reg can hold the
2271 if (curr_static_id
->operand
[nop
].strict_low
2273 && hard_regno
[nop
] < 0
2274 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2275 && ira_class_hard_regs_num
[this_alternative
] > 0
2276 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2277 [this_alternative
][0],
2279 (*curr_id
->operand_loc
[nop
])))
2281 if (lra_dump_file
!= NULL
)
2284 " alt=%d: Strict low subreg reload -- refuse\n",
2290 if (operand_reg
[nop
] != NULL_RTX
2291 /* Output operands and matched input operands are
2292 not inherited. The following conditions do not
2293 exactly describe the previous statement but they
2294 are pretty close. */
2295 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2296 && (this_alternative_matches
< 0
2297 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2299 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2303 /* The value of reload_sum has sense only if we
2304 process insns in their order. It happens only on
2305 the first constraints sub-pass when we do most of
2307 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2308 reload_sum
+= last_reload
- bb_reload_num
;
2310 /* If this is a constant that is reloaded into the
2311 desired class by copying it to memory first, count
2312 that as another reload. This is consistent with
2313 other code and is required to avoid choosing another
2314 alternative when the constant is moved into memory.
2315 Note that the test here is precisely the same as in
2316 the code below that calls force_const_mem. */
2317 if (CONST_POOL_OK_P (mode
, op
)
2318 && ((targetm
.preferred_reload_class
2319 (op
, this_alternative
) == NO_REGS
)
2320 || no_input_reloads_p
))
2327 /* Alternative loses if it requires a type of reload not
2328 permitted for this insn. We can always reload
2329 objects with a REG_UNUSED note. */
2330 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2331 && no_output_reloads_p
2332 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2333 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2334 && no_input_reloads_p
&& ! const_to_mem
)
2335 || (this_alternative_matches
>= 0
2336 && (no_input_reloads_p
2337 || (no_output_reloads_p
2338 && (curr_static_id
->operand
2339 [this_alternative_matches
].type
!= OP_IN
)
2340 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2341 no_subreg_reg_operand
2342 [this_alternative_matches
])))))
2344 if (lra_dump_file
!= NULL
)
2347 " alt=%d: No input/otput reload -- refuse\n",
2352 /* Check strong discouragement of reload of non-constant
2353 into class THIS_ALTERNATIVE. */
2354 if (! CONSTANT_P (op
) && ! no_regs_p
2355 && (targetm
.preferred_reload_class
2356 (op
, this_alternative
) == NO_REGS
2357 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2358 && (targetm
.preferred_output_reload_class
2359 (op
, this_alternative
) == NO_REGS
))))
2361 if (lra_dump_file
!= NULL
)
2362 fprintf (lra_dump_file
,
2363 " %d Non-prefered reload: reject+=%d\n",
2364 nop
, LRA_MAX_REJECT
);
2365 reject
+= LRA_MAX_REJECT
;
2368 if (! (MEM_P (op
) && offmemok
)
2369 && ! (const_to_mem
&& constmemok
))
2371 /* We prefer to reload pseudos over reloading other
2372 things, since such reloads may be able to be
2373 eliminated later. So bump REJECT in other cases.
2374 Don't do this in the case where we are forcing a
2375 constant into memory and it will then win since
2376 we don't want to have a different alternative
2378 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2380 if (lra_dump_file
!= NULL
)
2383 " %d Non-pseudo reload: reject+=2\n",
2390 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2392 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2394 if (lra_dump_file
!= NULL
)
2397 " %d Small class reload: reject+=%d\n",
2398 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2399 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2403 /* We are trying to spill pseudo into memory. It is
2404 usually more costly than moving to a hard register
2405 although it might takes the same number of
2407 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2409 if (lra_dump_file
!= NULL
)
2412 " %d Spill pseudo into memory: reject+=3\n",
2415 if (VECTOR_MODE_P (mode
))
2417 /* Spilling vectors into memory is usually more
2418 costly as they contain big values. */
2419 if (lra_dump_file
!= NULL
)
2422 " %d Spill vector pseudo: reject+=2\n",
2428 #ifdef SECONDARY_MEMORY_NEEDED
2429 /* If reload requires moving value through secondary
2430 memory, it will need one more insn at least. */
2431 if (this_alternative
!= NO_REGS
2432 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2433 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2434 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2436 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2437 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2441 /* Input reloads can be inherited more often than output
2442 reloads can be removed, so penalize output
2444 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2446 if (lra_dump_file
!= NULL
)
2449 " %d Non input pseudo reload: reject++\n",
2455 if (early_clobber_p
&& ! scratch_p
)
2457 if (lra_dump_file
!= NULL
)
2458 fprintf (lra_dump_file
,
2459 " %d Early clobber: reject++\n", nop
);
2462 /* ??? We check early clobbers after processing all operands
2463 (see loop below) and there we update the costs more.
2464 Should we update the cost (may be approximately) here
2465 because of early clobber register reloads or it is a rare
2466 or non-important thing to be worth to do it. */
2467 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2468 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2470 if (lra_dump_file
!= NULL
)
2471 fprintf (lra_dump_file
,
2472 " alt=%d,overall=%d,losers=%d -- refuse\n",
2473 nalt
, overall
, losers
);
2477 curr_alt
[nop
] = this_alternative
;
2478 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2479 curr_alt_win
[nop
] = this_alternative_win
;
2480 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2481 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2482 curr_alt_matches
[nop
] = this_alternative_matches
;
2484 if (this_alternative_matches
>= 0
2485 && !did_match
&& !this_alternative_win
)
2486 curr_alt_win
[this_alternative_matches
] = false;
2488 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2489 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2491 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2492 /* Prevent processing non-move insns. */
2493 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2494 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2495 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2496 && REG_P (no_subreg_reg_operand
[0])
2497 && REG_P (no_subreg_reg_operand
[1])
2498 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2499 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2500 || (! curr_alt_win
[0] && curr_alt_win
[1]
2501 && REG_P (no_subreg_reg_operand
[1])
2502 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2503 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2504 && REG_P (no_subreg_reg_operand
[0])
2505 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2506 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2507 no_subreg_reg_operand
[1])
2508 || (targetm
.preferred_reload_class
2509 (no_subreg_reg_operand
[1],
2510 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2511 /* If it is a result of recent elimination in move
2512 insn we can transform it into an add still by
2513 using this alternative. */
2514 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2516 /* We have a move insn and a new reload insn will be similar
2517 to the current insn. We should avoid such situation as it
2518 results in LRA cycling. */
2519 overall
+= LRA_MAX_REJECT
;
2522 curr_alt_dont_inherit_ops_num
= 0;
2523 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2525 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2526 HARD_REG_SET temp_set
;
2528 i
= early_clobbered_nops
[nop
];
2529 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2530 || hard_regno
[i
] < 0)
2532 lra_assert (operand_reg
[i
] != NULL_RTX
);
2533 clobbered_hard_regno
= hard_regno
[i
];
2534 CLEAR_HARD_REG_SET (temp_set
);
2535 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2536 first_conflict_j
= last_conflict_j
= -1;
2537 for (j
= 0; j
< n_operands
; j
++)
2539 /* We don't want process insides of match_operator and
2540 match_parallel because otherwise we would process
2541 their operands once again generating a wrong
2543 || curr_static_id
->operand
[j
].is_operator
)
2545 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2546 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2548 /* If we don't reload j-th operand, check conflicts. */
2549 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2550 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2552 if (first_conflict_j
< 0)
2553 first_conflict_j
= j
;
2554 last_conflict_j
= j
;
2556 if (last_conflict_j
< 0)
2558 /* If earlyclobber operand conflicts with another
2559 non-matching operand which is actually the same register
2560 as the earlyclobber operand, it is better to reload the
2561 another operand as an operand matching the earlyclobber
2562 operand can be also the same. */
2563 if (first_conflict_j
== last_conflict_j
2564 && operand_reg
[last_conflict_j
]
2565 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2566 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2568 curr_alt_win
[last_conflict_j
] = false;
2569 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2572 /* Early clobber was already reflected in REJECT. */
2573 lra_assert (reject
> 0);
2574 if (lra_dump_file
!= NULL
)
2577 " %d Conflict early clobber reload: reject--\n",
2580 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2584 /* We need to reload early clobbered register and the
2585 matched registers. */
2586 for (j
= 0; j
< n_operands
; j
++)
2587 if (curr_alt_matches
[j
] == i
)
2589 curr_alt_match_win
[j
] = false;
2591 overall
+= LRA_LOSER_COST_FACTOR
;
2593 if (! curr_alt_match_win
[i
])
2594 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2597 /* Remember pseudos used for match reloads are never
2599 lra_assert (curr_alt_matches
[i
] >= 0);
2600 curr_alt_win
[curr_alt_matches
[i
]] = false;
2602 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2604 /* Early clobber was already reflected in REJECT. */
2605 lra_assert (reject
> 0);
2606 if (lra_dump_file
!= NULL
)
2609 " %d Matched conflict early clobber reloads:"
2613 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2616 if (lra_dump_file
!= NULL
)
2617 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2618 nalt
, overall
, losers
, reload_nregs
);
2620 /* If this alternative can be made to work by reloading, and it
2621 needs less reloading than the others checked so far, record
2622 it as the chosen goal for reloading. */
2623 if ((best_losers
!= 0 && losers
== 0)
2624 || (((best_losers
== 0 && losers
== 0)
2625 || (best_losers
!= 0 && losers
!= 0))
2626 && (best_overall
> overall
2627 || (best_overall
== overall
2628 /* If the cost of the reloads is the same,
2629 prefer alternative which requires minimal
2630 number of reload regs. */
2631 && (reload_nregs
< best_reload_nregs
2632 || (reload_nregs
== best_reload_nregs
2633 && (best_reload_sum
< reload_sum
2634 || (best_reload_sum
== reload_sum
2635 && nalt
< goal_alt_number
))))))))
2637 for (nop
= 0; nop
< n_operands
; nop
++)
2639 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2640 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2641 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2642 goal_alt
[nop
] = curr_alt
[nop
];
2643 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2645 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2646 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2647 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2648 goal_alt_swapped
= curr_swapped
;
2649 best_overall
= overall
;
2650 best_losers
= losers
;
2651 best_reload_nregs
= reload_nregs
;
2652 best_reload_sum
= reload_sum
;
2653 goal_alt_number
= nalt
;
2656 /* Everything is satisfied. Do not process alternatives
2665 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2667 base_plus_disp_to_reg (struct address_info
*ad
)
2672 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2673 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2674 get_index_code (ad
));
2675 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2677 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2681 /* Make reload of index part of address AD. Return the new
2684 index_part_to_reg (struct address_info
*ad
)
2688 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2689 INDEX_REG_CLASS
, "index term");
2690 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2691 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2695 /* Return true if we can add a displacement to address AD, even if that
2696 makes the address invalid. The fix-up code requires any new address
2697 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2699 can_add_disp_p (struct address_info
*ad
)
2701 return (!ad
->autoinc_p
2702 && ad
->segment
== NULL
2703 && ad
->base
== ad
->base_term
2704 && ad
->disp
== ad
->disp_term
);
2707 /* Make equiv substitution in address AD. Return true if a substitution
2710 equiv_address_substitution (struct address_info
*ad
)
2712 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2713 HOST_WIDE_INT disp
, scale
;
2716 base_term
= strip_subreg (ad
->base_term
);
2717 if (base_term
== NULL
)
2718 base_reg
= new_base_reg
= NULL_RTX
;
2721 base_reg
= *base_term
;
2722 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2724 index_term
= strip_subreg (ad
->index_term
);
2725 if (index_term
== NULL
)
2726 index_reg
= new_index_reg
= NULL_RTX
;
2729 index_reg
= *index_term
;
2730 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2732 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2736 if (lra_dump_file
!= NULL
)
2738 fprintf (lra_dump_file
, "Changing address in insn %d ",
2739 INSN_UID (curr_insn
));
2740 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2742 if (base_reg
!= new_base_reg
)
2744 if (REG_P (new_base_reg
))
2746 *base_term
= new_base_reg
;
2749 else if (GET_CODE (new_base_reg
) == PLUS
2750 && REG_P (XEXP (new_base_reg
, 0))
2751 && CONST_INT_P (XEXP (new_base_reg
, 1))
2752 && can_add_disp_p (ad
))
2754 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2755 *base_term
= XEXP (new_base_reg
, 0);
2758 if (ad
->base_term2
!= NULL
)
2759 *ad
->base_term2
= *ad
->base_term
;
2761 if (index_reg
!= new_index_reg
)
2763 if (REG_P (new_index_reg
))
2765 *index_term
= new_index_reg
;
2768 else if (GET_CODE (new_index_reg
) == PLUS
2769 && REG_P (XEXP (new_index_reg
, 0))
2770 && CONST_INT_P (XEXP (new_index_reg
, 1))
2771 && can_add_disp_p (ad
)
2772 && (scale
= get_index_scale (ad
)))
2774 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2775 *index_term
= XEXP (new_index_reg
, 0);
2781 if (ad
->disp
!= NULL
)
2782 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2785 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2786 update_address (ad
);
2790 if (lra_dump_file
!= NULL
)
2793 fprintf (lra_dump_file
, " -- no change\n");
2796 fprintf (lra_dump_file
, " on equiv ");
2797 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2798 fprintf (lra_dump_file
, "\n");
2804 /* Major function to make reloads for an address in operand NOP.
2805 The supported cases are:
2807 1) an address that existed before LRA started, at which point it
2808 must have been valid. These addresses are subject to elimination
2809 and may have become invalid due to the elimination offset being out
2812 2) an address created by forcing a constant to memory
2813 (force_const_to_mem). The initial form of these addresses might
2814 not be valid, and it is this function's job to make them valid.
2816 3) a frame address formed from a register and a (possibly zero)
2817 constant offset. As above, these addresses might not be valid and
2818 this function must make them so.
2820 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2821 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2822 address. Return true for any RTL change.
2824 The function is a helper function which does not produce all
2825 transformations which can be necessary. It does just basic steps.
2826 To do all necessary transformations use function
2829 process_address_1 (int nop
, rtx
*before
, rtx
*after
)
2831 struct address_info ad
;
2833 rtx op
= *curr_id
->operand_loc
[nop
];
2834 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2835 enum constraint_num cn
= lookup_constraint (constraint
);
2838 if (constraint
[0] == 'p'
2839 || insn_extra_address_constraint (cn
))
2840 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2841 else if (MEM_P (op
))
2842 decompose_mem_address (&ad
, op
);
2843 else if (GET_CODE (op
) == SUBREG
2844 && MEM_P (SUBREG_REG (op
)))
2845 decompose_mem_address (&ad
, SUBREG_REG (op
));
2848 change_p
= equiv_address_substitution (&ad
);
2849 if (ad
.base_term
!= NULL
2850 && (process_addr_reg
2851 (ad
.base_term
, before
,
2853 && !(REG_P (*ad
.base_term
)
2854 && find_regno_note (curr_insn
, REG_DEAD
,
2855 REGNO (*ad
.base_term
)) != NULL_RTX
)
2857 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2858 get_index_code (&ad
)))))
2861 if (ad
.base_term2
!= NULL
)
2862 *ad
.base_term2
= *ad
.base_term
;
2864 if (ad
.index_term
!= NULL
2865 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2868 /* Target hooks sometimes don't treat extra-constraint addresses as
2869 legitimate address_operands, so handle them specially. */
2870 if (constraint
[0] != 'p'
2871 && insn_extra_address_constraint (cn
)
2872 && satisfies_address_constraint_p (&ad
, cn
))
2875 /* There are three cases where the shape of *AD.INNER may now be invalid:
2877 1) the original address was valid, but either elimination or
2878 equiv_address_substitution was applied and that made
2879 the address invalid.
2881 2) the address is an invalid symbolic address created by
2884 3) the address is a frame address with an invalid offset.
2886 All these cases involve a non-autoinc address, so there is no
2887 point revalidating other types. */
2888 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2891 /* Any index existed before LRA started, so we can assume that the
2892 presence and shape of the index is valid. */
2893 push_to_sequence (*before
);
2894 lra_assert (ad
.disp
== ad
.disp_term
);
2895 if (ad
.base
== NULL
)
2897 if (ad
.index
== NULL
)
2900 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2902 rtx addr
= *ad
.inner
;
2904 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2908 rtx last
= get_last_insn ();
2910 /* addr => lo_sum (new_base, addr), case (2) above. */
2911 insn
= emit_insn (gen_rtx_SET
2913 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2914 code
= recog_memoized (insn
);
2917 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2918 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2920 /* Try to put lo_sum into register. */
2921 insn
= emit_insn (gen_rtx_SET
2923 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2924 code
= recog_memoized (insn
);
2927 *ad
.inner
= new_reg
;
2928 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2938 delete_insns_since (last
);
2943 /* addr => new_base, case (2) above. */
2944 lra_emit_move (new_reg
, addr
);
2945 *ad
.inner
= new_reg
;
2950 /* index * scale + disp => new base + index * scale,
2952 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2953 GET_CODE (*ad
.index
));
2955 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2956 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2957 lra_emit_move (new_reg
, *ad
.disp
);
2958 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2959 new_reg
, *ad
.index
);
2962 else if (ad
.index
== NULL
)
2966 rtx set
, insns
, last_insn
;
2967 /* base + disp => new base, cases (1) and (3) above. */
2968 /* Another option would be to reload the displacement into an
2969 index register. However, postreload has code to optimize
2970 address reloads that have the same base and different
2971 displacements, so reloading into an index register would
2972 not necessarily be a win. */
2974 new_reg
= base_plus_disp_to_reg (&ad
);
2975 insns
= get_insns ();
2976 last_insn
= get_last_insn ();
2977 /* If we generated at least two insns, try last insn source as
2978 an address. If we succeed, we generate one less insn. */
2979 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2980 && GET_CODE (SET_SRC (set
)) == PLUS
2981 && REG_P (XEXP (SET_SRC (set
), 0))
2982 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2984 *ad
.inner
= SET_SRC (set
);
2985 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2987 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2988 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2989 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2990 get_index_code (&ad
));
2991 regno
= REGNO (*ad
.base_term
);
2992 if (regno
>= FIRST_PSEUDO_REGISTER
2993 && cl
!= lra_get_allocno_class (regno
))
2994 lra_change_class (regno
, cl
, " Change to", true);
2995 new_reg
= SET_SRC (set
);
2996 delete_insns_since (PREV_INSN (last_insn
));
3001 *ad
.inner
= new_reg
;
3003 else if (ad
.disp_term
!= NULL
)
3005 /* base + scale * index + disp => new base + scale * index,
3007 new_reg
= base_plus_disp_to_reg (&ad
);
3008 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3009 new_reg
, *ad
.index
);
3011 else if (get_index_scale (&ad
) == 1)
3013 /* The last transformation to one reg will be made in
3014 curr_insn_transform function. */
3020 /* base + scale * index => base + new_reg,
3022 Index part of address may become invalid. For example, we
3023 changed pseudo on the equivalent memory and a subreg of the
3024 pseudo onto the memory of different mode for which the scale is
3026 new_reg
= index_part_to_reg (&ad
);
3027 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3028 *ad
.base_term
, new_reg
);
3030 *before
= get_insns ();
3035 /* Do address reloads until it is necessary. Use process_address_1 as
3036 a helper function. Return true for any RTL changes. */
3038 process_address (int nop
, rtx
*before
, rtx
*after
)
3042 while (process_address_1 (nop
, before
, after
))
3047 /* Emit insns to reload VALUE into a new register. VALUE is an
3048 auto-increment or auto-decrement RTX whose operand is a register or
3049 memory location; so reloading involves incrementing that location.
3050 IN is either identical to VALUE, or some cheaper place to reload
3051 value being incremented/decremented from.
3053 INC_AMOUNT is the number to increment or decrement by (always
3054 positive and ignored for POST_MODIFY/PRE_MODIFY).
3056 Return pseudo containing the result. */
3058 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3060 /* REG or MEM to be copied and incremented. */
3061 rtx incloc
= XEXP (value
, 0);
3062 /* Nonzero if increment after copying. */
3063 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3064 || GET_CODE (value
) == POST_MODIFY
);
3069 rtx real_in
= in
== value
? incloc
: in
;
3073 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3075 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3076 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3077 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3078 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3079 inc
= XEXP (XEXP (value
, 1), 1);
3083 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3084 inc_amount
= -inc_amount
;
3086 inc
= GEN_INT (inc_amount
);
3089 if (! post
&& REG_P (incloc
))
3092 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3095 if (real_in
!= result
)
3097 /* First copy the location to the result register. */
3098 lra_assert (REG_P (result
));
3099 emit_insn (gen_move_insn (result
, real_in
));
3102 /* We suppose that there are insns to add/sub with the constant
3103 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3104 old reload worked with this assumption. If the assumption
3105 becomes wrong, we should use approach in function
3106 base_plus_disp_to_reg. */
3109 /* See if we can directly increment INCLOC. */
3110 last
= get_last_insn ();
3111 add_insn
= emit_insn (plus_p
3112 ? gen_add2_insn (incloc
, inc
)
3113 : gen_sub2_insn (incloc
, inc
));
3115 code
= recog_memoized (add_insn
);
3118 if (! post
&& result
!= incloc
)
3119 emit_insn (gen_move_insn (result
, incloc
));
3122 delete_insns_since (last
);
3125 /* If couldn't do the increment directly, must increment in RESULT.
3126 The way we do this depends on whether this is pre- or
3127 post-increment. For pre-increment, copy INCLOC to the reload
3128 register, increment it there, then save back. */
3131 if (real_in
!= result
)
3132 emit_insn (gen_move_insn (result
, real_in
));
3134 emit_insn (gen_add2_insn (result
, inc
));
3136 emit_insn (gen_sub2_insn (result
, inc
));
3137 if (result
!= incloc
)
3138 emit_insn (gen_move_insn (incloc
, result
));
3144 Because this might be a jump insn or a compare, and because
3145 RESULT may not be available after the insn in an input
3146 reload, we must do the incrementing before the insn being
3149 We have already copied IN to RESULT. Increment the copy in
3150 RESULT, save that back, then decrement RESULT so it has
3151 the original value. */
3153 emit_insn (gen_add2_insn (result
, inc
));
3155 emit_insn (gen_sub2_insn (result
, inc
));
3156 emit_insn (gen_move_insn (incloc
, result
));
3157 /* Restore non-modified value for the result. We prefer this
3158 way because it does not require an additional hard
3162 if (CONST_INT_P (inc
))
3163 emit_insn (gen_add2_insn (result
,
3164 gen_int_mode (-INTVAL (inc
),
3165 GET_MODE (result
))));
3167 emit_insn (gen_sub2_insn (result
, inc
));
3170 emit_insn (gen_add2_insn (result
, inc
));
3175 /* Return true if the current move insn does not need processing as we
3176 already know that it satisfies its constraints. */
3178 simple_move_p (void)
3181 enum reg_class dclass
, sclass
;
3183 lra_assert (curr_insn_set
!= NULL_RTX
);
3184 dest
= SET_DEST (curr_insn_set
);
3185 src
= SET_SRC (curr_insn_set
);
3186 return ((dclass
= get_op_class (dest
)) != NO_REGS
3187 && (sclass
= get_op_class (src
)) != NO_REGS
3188 /* The backend guarantees that register moves of cost 2
3189 never need reloads. */
3190 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3193 /* Swap operands NOP and NOP + 1. */
3195 swap_operands (int nop
)
3197 enum machine_mode mode
= curr_operand_mode
[nop
];
3198 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3199 curr_operand_mode
[nop
+ 1] = mode
;
3200 rtx x
= *curr_id
->operand_loc
[nop
];
3201 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3202 *curr_id
->operand_loc
[nop
+ 1] = x
;
3203 /* Swap the duplicates too. */
3204 lra_update_dup (curr_id
, nop
);
3205 lra_update_dup (curr_id
, nop
+ 1);
3208 /* Main entry point of the constraint code: search the body of the
3209 current insn to choose the best alternative. It is mimicking insn
3210 alternative cost calculation model of former reload pass. That is
3211 because machine descriptions were written to use this model. This
3212 model can be changed in future. Make commutative operand exchange
3215 Return true if some RTL changes happened during function call. */
3217 curr_insn_transform (void)
3223 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3224 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3227 /* Flag that the insn has been changed through a transformation. */
3230 #ifdef SECONDARY_MEMORY_NEEDED
3233 int max_regno_before
;
3234 int reused_alternative_num
;
3236 curr_insn_set
= single_set (curr_insn
);
3237 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3240 no_input_reloads_p
= no_output_reloads_p
= false;
3241 goal_alt_number
= -1;
3242 change_p
= sec_mem_p
= false;
3243 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3244 reloads; neither are insns that SET cc0. Insns that use CC0 are
3245 not allowed to have any input reloads. */
3246 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3247 no_output_reloads_p
= true;
3250 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3251 no_input_reloads_p
= true;
3252 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3253 no_output_reloads_p
= true;
3256 n_operands
= curr_static_id
->n_operands
;
3257 n_alternatives
= curr_static_id
->n_alternatives
;
3259 /* Just return "no reloads" if insn has no operands with
3261 if (n_operands
== 0 || n_alternatives
== 0)
3264 max_regno_before
= max_reg_num ();
3266 for (i
= 0; i
< n_operands
; i
++)
3268 goal_alt_matched
[i
][0] = -1;
3269 goal_alt_matches
[i
] = -1;
3272 commutative
= curr_static_id
->commutative
;
3274 /* Now see what we need for pseudos that didn't get hard regs or got
3275 the wrong kind of hard reg. For this, we must consider all the
3276 operands together against the register constraints. */
3278 best_losers
= best_overall
= INT_MAX
;
3279 best_reload_sum
= 0;
3281 curr_swapped
= false;
3282 goal_alt_swapped
= false;
3284 /* Make equivalence substitution and memory subreg elimination
3285 before address processing because an address legitimacy can
3286 depend on memory mode. */
3287 for (i
= 0; i
< n_operands
; i
++)
3289 rtx op
= *curr_id
->operand_loc
[i
];
3290 rtx subst
, old
= op
;
3291 bool op_change_p
= false;
3293 if (GET_CODE (old
) == SUBREG
)
3294 old
= SUBREG_REG (old
);
3295 subst
= get_equiv_with_elimination (old
, curr_insn
);
3298 subst
= copy_rtx (subst
);
3299 lra_assert (REG_P (old
));
3300 if (GET_CODE (op
) == SUBREG
)
3301 SUBREG_REG (op
) = subst
;
3303 *curr_id
->operand_loc
[i
] = subst
;
3304 if (lra_dump_file
!= NULL
)
3306 fprintf (lra_dump_file
,
3307 "Changing pseudo %d in operand %i of insn %u on equiv ",
3308 REGNO (old
), i
, INSN_UID (curr_insn
));
3309 dump_value_slim (lra_dump_file
, subst
, 1);
3310 fprintf (lra_dump_file
, "\n");
3312 op_change_p
= change_p
= true;
3314 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3317 lra_update_dup (curr_id
, i
);
3321 /* Reload address registers and displacements. We do it before
3322 finding an alternative because of memory constraints. */
3323 before
= after
= NULL_RTX
;
3324 for (i
= 0; i
< n_operands
; i
++)
3325 if (! curr_static_id
->operand
[i
].is_operator
3326 && process_address (i
, &before
, &after
))
3329 lra_update_dup (curr_id
, i
);
3333 /* If we've changed the instruction then any alternative that
3334 we chose previously may no longer be valid. */
3335 lra_set_used_insn_alternative (curr_insn
, -1);
3337 if (curr_insn_set
!= NULL_RTX
3338 && check_and_process_move (&change_p
, &sec_mem_p
))
3343 reused_alternative_num
= curr_id
->used_insn_alternative
;
3344 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3345 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3346 reused_alternative_num
, INSN_UID (curr_insn
));
3348 if (process_alt_operands (reused_alternative_num
))
3351 /* If insn is commutative (it's safe to exchange a certain pair of
3352 operands) then we need to try each alternative twice, the second
3353 time matching those two operands as if we had exchanged them. To
3354 do this, really exchange them in operands.
3356 If we have just tried the alternatives the second time, return
3357 operands to normal and drop through. */
3359 if (reused_alternative_num
< 0 && commutative
>= 0)
3361 curr_swapped
= !curr_swapped
;
3364 swap_operands (commutative
);
3368 swap_operands (commutative
);
3371 if (! alt_p
&& ! sec_mem_p
)
3373 /* No alternative works with reloads?? */
3374 if (INSN_CODE (curr_insn
) >= 0)
3375 fatal_insn ("unable to generate reloads for:", curr_insn
);
3376 error_for_asm (curr_insn
,
3377 "inconsistent operand constraints in an %<asm%>");
3378 /* Avoid further trouble with this insn. */
3379 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3380 lra_invalidate_insn_data (curr_insn
);
3384 /* If the best alternative is with operands 1 and 2 swapped, swap
3385 them. Update the operand numbers of any reloads already
3388 if (goal_alt_swapped
)
3390 if (lra_dump_file
!= NULL
)
3391 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3392 INSN_UID (curr_insn
));
3394 /* Swap the duplicates too. */
3395 swap_operands (commutative
);
3399 #ifdef SECONDARY_MEMORY_NEEDED
3400 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3401 too conservatively. So we use the secondary memory only if there
3402 is no any alternative without reloads. */
3403 use_sec_mem_p
= false;
3405 use_sec_mem_p
= true;
3408 for (i
= 0; i
< n_operands
; i
++)
3409 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3411 use_sec_mem_p
= i
< n_operands
;
3416 rtx new_reg
, src
, dest
, rld
;
3417 enum machine_mode sec_mode
, rld_mode
;
3419 lra_assert (sec_mem_p
);
3420 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3421 && curr_static_id
->operand
[1].type
== OP_IN
);
3422 dest
= *curr_id
->operand_loc
[0];
3423 src
= *curr_id
->operand_loc
[1];
3424 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3426 rld_mode
= GET_MODE (rld
);
3427 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3428 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3430 sec_mode
= rld_mode
;
3432 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3433 NO_REGS
, "secondary");
3434 /* If the mode is changed, it should be wider. */
3435 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3436 if (sec_mode
!= rld_mode
)
3438 /* If the target says specifically to use another mode for
3439 secondary memory moves we can not reuse the original
3441 after
= emit_spill_move (false, new_reg
, dest
);
3442 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3443 "Inserting the sec. move");
3444 /* We may have non null BEFORE here (e.g. after address
3446 push_to_sequence (before
);
3447 before
= emit_spill_move (true, new_reg
, src
);
3449 before
= get_insns ();
3451 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3452 lra_set_insn_deleted (curr_insn
);
3454 else if (dest
== rld
)
3456 *curr_id
->operand_loc
[0] = new_reg
;
3457 after
= emit_spill_move (false, new_reg
, dest
);
3458 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3459 "Inserting the sec. move");
3463 *curr_id
->operand_loc
[1] = new_reg
;
3464 /* See comments above. */
3465 push_to_sequence (before
);
3466 before
= emit_spill_move (true, new_reg
, src
);
3468 before
= get_insns ();
3470 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3471 "Inserting the sec. move");
3473 lra_update_insn_regno_info (curr_insn
);
3478 lra_assert (goal_alt_number
>= 0);
3479 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3481 if (lra_dump_file
!= NULL
)
3485 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3486 goal_alt_number
, INSN_UID (curr_insn
));
3487 for (i
= 0; i
< n_operands
; i
++)
3489 p
= (curr_static_id
->operand_alternative
3490 [goal_alt_number
* n_operands
+ i
].constraint
);
3493 fprintf (lra_dump_file
, " (%d) ", i
);
3494 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3495 fputc (*p
, lra_dump_file
);
3497 if (INSN_CODE (curr_insn
) >= 0
3498 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3499 fprintf (lra_dump_file
, " {%s}", p
);
3500 if (curr_id
->sp_offset
!= 0)
3501 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3502 curr_id
->sp_offset
);
3503 fprintf (lra_dump_file
, "\n");
3506 /* Right now, for any pair of operands I and J that are required to
3507 match, with J < I, goal_alt_matches[I] is J. Add I to
3508 goal_alt_matched[J]. */
3510 for (i
= 0; i
< n_operands
; i
++)
3511 if ((j
= goal_alt_matches
[i
]) >= 0)
3513 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3515 /* We allow matching one output operand and several input
3518 || (curr_static_id
->operand
[j
].type
== OP_OUT
3519 && curr_static_id
->operand
[i
].type
== OP_IN
3520 && (curr_static_id
->operand
3521 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3522 goal_alt_matched
[j
][k
] = i
;
3523 goal_alt_matched
[j
][k
+ 1] = -1;
3526 for (i
= 0; i
< n_operands
; i
++)
3527 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3529 /* Any constants that aren't allowed and can't be reloaded into
3530 registers are here changed into memory references. */
3531 for (i
= 0; i
< n_operands
; i
++)
3532 if (goal_alt_win
[i
])
3535 enum reg_class new_class
;
3536 rtx reg
= *curr_id
->operand_loc
[i
];
3538 if (GET_CODE (reg
) == SUBREG
)
3539 reg
= SUBREG_REG (reg
);
3541 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3543 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3545 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3548 lra_change_class (regno
, new_class
, " Change to", true);
3554 const char *constraint
;
3556 rtx op
= *curr_id
->operand_loc
[i
];
3557 rtx subreg
= NULL_RTX
;
3558 enum machine_mode mode
= curr_operand_mode
[i
];
3560 if (GET_CODE (op
) == SUBREG
)
3563 op
= SUBREG_REG (op
);
3564 mode
= GET_MODE (op
);
3567 if (CONST_POOL_OK_P (mode
, op
)
3568 && ((targetm
.preferred_reload_class
3569 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3570 || no_input_reloads_p
))
3572 rtx tem
= force_const_mem (mode
, op
);
3575 if (subreg
!= NULL_RTX
)
3576 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3578 *curr_id
->operand_loc
[i
] = tem
;
3579 lra_update_dup (curr_id
, i
);
3580 process_address (i
, &before
, &after
);
3582 /* If the alternative accepts constant pool refs directly
3583 there will be no reload needed at all. */
3584 if (subreg
!= NULL_RTX
)
3586 /* Skip alternatives before the one requested. */
3587 constraint
= (curr_static_id
->operand_alternative
3588 [goal_alt_number
* n_operands
+ i
].constraint
);
3590 (c
= *constraint
) && c
!= ',' && c
!= '#';
3591 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3593 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3595 enum constraint_num cn
= lookup_constraint (constraint
);
3596 if (insn_extra_memory_constraint (cn
)
3597 && satisfies_memory_constraint_p (tem
, cn
))
3600 if (c
== '\0' || c
== ',' || c
== '#')
3603 goal_alt_win
[i
] = true;
3607 for (i
= 0; i
< n_operands
; i
++)
3610 bool optional_p
= false;
3612 rtx op
= *curr_id
->operand_loc
[i
];
3614 if (goal_alt_win
[i
])
3616 if (goal_alt
[i
] == NO_REGS
3618 /* When we assign NO_REGS it means that we will not
3619 assign a hard register to the scratch pseudo by
3620 assigment pass and the scratch pseudo will be
3621 spilled. Spilled scratch pseudos are transformed
3622 back to scratches at the LRA end. */
3623 && lra_former_scratch_operand_p (curr_insn
, i
))
3625 int regno
= REGNO (op
);
3626 lra_change_class (regno
, NO_REGS
, " Change to", true);
3627 if (lra_get_regno_hard_regno (regno
) >= 0)
3628 /* We don't have to mark all insn affected by the
3629 spilled pseudo as there is only one such insn, the
3631 reg_renumber
[regno
] = -1;
3633 /* We can do an optional reload. If the pseudo got a hard
3634 reg, we might improve the code through inheritance. If
3635 it does not get a hard register we coalesce memory/memory
3636 moves later. Ignore move insns to avoid cycling. */
3638 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3639 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3640 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3641 && regno
< new_regno_start
3642 && ! lra_former_scratch_p (regno
)
3643 && reg_renumber
[regno
] < 0
3644 && (curr_insn_set
== NULL_RTX
3645 || !((REG_P (SET_SRC (curr_insn_set
))
3646 || MEM_P (SET_SRC (curr_insn_set
))
3647 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3648 && (REG_P (SET_DEST (curr_insn_set
))
3649 || MEM_P (SET_DEST (curr_insn_set
))
3650 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3656 /* Operands that match previous ones have already been handled. */
3657 if (goal_alt_matches
[i
] >= 0)
3660 /* We should not have an operand with a non-offsettable address
3661 appearing where an offsettable address will do. It also may
3662 be a case when the address should be special in other words
3663 not a general one (e.g. it needs no index reg). */
3664 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3666 enum reg_class rclass
;
3667 rtx
*loc
= &XEXP (op
, 0);
3668 enum rtx_code code
= GET_CODE (*loc
);
3670 push_to_sequence (before
);
3671 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3673 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3674 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3675 /* This value does not matter for MODIFY. */
3676 GET_MODE_SIZE (GET_MODE (op
)));
3677 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3678 "offsetable address", &new_reg
))
3679 lra_emit_move (new_reg
, *loc
);
3680 before
= get_insns ();
3683 lra_update_dup (curr_id
, i
);
3685 else if (goal_alt_matched
[i
][0] == -1)
3687 enum machine_mode mode
;
3689 int hard_regno
, byte
;
3690 enum op_type type
= curr_static_id
->operand
[i
].type
;
3692 loc
= curr_id
->operand_loc
[i
];
3693 mode
= curr_operand_mode
[i
];
3694 if (GET_CODE (*loc
) == SUBREG
)
3696 reg
= SUBREG_REG (*loc
);
3697 byte
= SUBREG_BYTE (*loc
);
3699 /* Strict_low_part requires reload the register not
3700 the sub-register. */
3701 && (curr_static_id
->operand
[i
].strict_low
3702 || (GET_MODE_SIZE (mode
)
3703 <= GET_MODE_SIZE (GET_MODE (reg
))
3705 = get_try_hard_regno (REGNO (reg
))) >= 0
3706 && (simplify_subreg_regno
3708 GET_MODE (reg
), byte
, mode
) < 0)
3709 && (goal_alt
[i
] == NO_REGS
3710 || (simplify_subreg_regno
3711 (ira_class_hard_regs
[goal_alt
[i
]][0],
3712 GET_MODE (reg
), byte
, mode
) >= 0)))))
3714 loc
= &SUBREG_REG (*loc
);
3715 mode
= GET_MODE (*loc
);
3719 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3720 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3723 push_to_sequence (before
);
3724 lra_emit_move (new_reg
, old
);
3725 before
= get_insns ();
3730 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3733 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3735 after
= get_insns ();
3739 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3740 if (goal_alt_dont_inherit_ops
[j
] == i
)
3742 lra_set_regno_unique_value (REGNO (new_reg
));
3745 lra_update_dup (curr_id
, i
);
3747 else if (curr_static_id
->operand
[i
].type
== OP_IN
3748 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3751 /* generate reloads for input and matched outputs. */
3752 match_inputs
[0] = i
;
3753 match_inputs
[1] = -1;
3754 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3755 goal_alt
[i
], &before
, &after
);
3757 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3758 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3760 /* Generate reloads for output and matched inputs. */
3761 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3762 else if (curr_static_id
->operand
[i
].type
== OP_IN
3763 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3766 /* Generate reloads for matched inputs. */
3767 match_inputs
[0] = i
;
3768 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3769 match_inputs
[j
+ 1] = k
;
3770 match_inputs
[j
+ 1] = -1;
3771 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3774 /* We must generate code in any case when function
3775 process_alt_operands decides that it is possible. */
3779 lra_assert (REG_P (op
));
3781 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3782 if (GET_CODE (op
) == SUBREG
)
3783 op
= SUBREG_REG (op
);
3784 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3785 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3786 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3787 if (lra_dump_file
!= NULL
)
3788 fprintf (lra_dump_file
,
3789 " Making reload reg %d for reg %d optional\n",
3793 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3794 || max_regno_before
!= max_reg_num ())
3798 lra_update_operator_dups (curr_id
);
3799 /* Something changes -- process the insn. */
3800 lra_update_insn_regno_info (curr_insn
);
3802 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3806 /* Return true if X is in LIST. */
3808 in_list_p (rtx x
, rtx list
)
3810 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3811 if (XEXP (list
, 0) == x
)
3816 /* Return true if X contains an allocatable hard register (if
3817 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3819 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3825 code
= GET_CODE (x
);
3828 int regno
= REGNO (x
);
3829 HARD_REG_SET alloc_regs
;
3833 if (regno
>= FIRST_PSEUDO_REGISTER
)
3834 regno
= lra_get_regno_hard_regno (regno
);
3837 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3838 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3842 if (regno
< FIRST_PSEUDO_REGISTER
)
3846 return lra_get_regno_hard_regno (regno
) < 0;
3849 fmt
= GET_RTX_FORMAT (code
);
3850 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3854 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3857 else if (fmt
[i
] == 'E')
3859 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3860 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3867 /* Process all regs in location *LOC and change them on equivalent
3868 substitution. Return true if any change was done. */
3870 loc_equivalence_change_p (rtx
*loc
)
3872 rtx subst
, reg
, x
= *loc
;
3873 bool result
= false;
3874 enum rtx_code code
= GET_CODE (x
);
3880 reg
= SUBREG_REG (x
);
3881 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3882 && GET_MODE (subst
) == VOIDmode
)
3884 /* We cannot reload debug location. Simplify subreg here
3885 while we know the inner mode. */
3886 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3887 GET_MODE (reg
), SUBREG_BYTE (x
));
3891 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3897 /* Scan all the operand sub-expressions. */
3898 fmt
= GET_RTX_FORMAT (code
);
3899 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3902 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3903 else if (fmt
[i
] == 'E')
3904 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3906 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3911 /* Similar to loc_equivalence_change_p, but for use as
3912 simplify_replace_fn_rtx callback. DATA is insn for which the
3913 elimination is done. If it null we don't do the elimination. */
3915 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3920 rtx subst
= (data
== NULL
3921 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx
) data
));
3928 /* Maximum number of generated reload insns per an insn. It is for
3929 preventing this pass cycling in a bug case. */
3930 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3932 /* The current iteration number of this LRA pass. */
3933 int lra_constraint_iter
;
3935 /* The current iteration number of this LRA pass after the last spill
3937 int lra_constraint_iter_after_spill
;
3939 /* True if we substituted equiv which needs checking register
3940 allocation correctness because the equivalent value contains
3941 allocatable hard registers or when we restore multi-register
3943 bool lra_risky_transformations_p
;
3945 /* Return true if REGNO is referenced in more than one block. */
3947 multi_block_pseudo_p (int regno
)
3949 basic_block bb
= NULL
;
3953 if (regno
< FIRST_PSEUDO_REGISTER
)
3956 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3958 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3959 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3964 /* Return true if LIST contains a deleted insn. */
3966 contains_deleted_insn_p (rtx list
)
3968 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3969 if (NOTE_P (XEXP (list
, 0))
3970 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3975 /* Return true if X contains a pseudo dying in INSN. */
3977 dead_pseudo_p (rtx x
, rtx insn
)
3984 return (insn
!= NULL_RTX
3985 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3986 code
= GET_CODE (x
);
3987 fmt
= GET_RTX_FORMAT (code
);
3988 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3992 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3995 else if (fmt
[i
] == 'E')
3997 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3998 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4005 /* Return true if INSN contains a dying pseudo in INSN right hand
4008 insn_rhs_dead_pseudo_p (rtx insn
)
4010 rtx set
= single_set (insn
);
4012 gcc_assert (set
!= NULL
);
4013 return dead_pseudo_p (SET_SRC (set
), insn
);
4016 /* Return true if any init insn of REGNO contains a dying pseudo in
4017 insn right hand side. */
4019 init_insn_rhs_dead_pseudo_p (int regno
)
4021 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
4026 return insn_rhs_dead_pseudo_p (insns
);
4027 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
4028 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
4033 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4034 reverse only if we have one init insn with given REGNO as a
4037 reverse_equiv_p (int regno
)
4041 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
4043 if (! INSN_P (XEXP (insns
, 0))
4044 || XEXP (insns
, 1) != NULL_RTX
)
4046 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
4048 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4051 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4052 call this function only for non-reverse equivalence. */
4054 contains_reloaded_insn_p (int regno
)
4057 rtx list
= ira_reg_equiv
[regno
].init_insns
;
4059 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4060 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
4061 || ! REG_P (SET_DEST (set
))
4062 || (int) REGNO (SET_DEST (set
)) != regno
)
4067 /* Entry function of LRA constraint pass. Return true if the
4068 constraint pass did change the code. */
4070 lra_constraints (bool first_p
)
4073 int i
, hard_regno
, new_insns_num
;
4074 unsigned int min_len
, new_min_len
, uid
;
4075 rtx set
, x
, reg
, dest_reg
;
4076 basic_block last_bb
;
4077 bitmap_head equiv_insn_bitmap
;
4080 lra_constraint_iter
++;
4081 if (lra_dump_file
!= NULL
)
4082 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4083 lra_constraint_iter
);
4084 lra_constraint_iter_after_spill
++;
4085 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
4087 ("Maximum number of LRA constraint passes is achieved (%d)\n",
4088 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
4090 lra_risky_transformations_p
= false;
4091 new_insn_uid_start
= get_max_uid ();
4092 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4093 /* Mark used hard regs for target stack size calulations. */
4094 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4095 if (lra_reg_info
[i
].nrefs
!= 0
4096 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4100 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4101 for (j
= 0; j
< nregs
; j
++)
4102 df_set_regs_ever_live (hard_regno
+ j
, true);
4104 /* Do elimination before the equivalence processing as we can spill
4105 some pseudos during elimination. */
4106 lra_eliminate (false, first_p
);
4107 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
4108 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4109 if (lra_reg_info
[i
].nrefs
!= 0)
4111 ira_reg_equiv
[i
].profitable_p
= true;
4112 reg
= regno_reg_rtx
[i
];
4113 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4115 bool pseudo_p
= contains_reg_p (x
, false, false);
4117 /* After RTL transformation, we can not guarantee that
4118 pseudo in the substitution was not reloaded which might
4119 make equivalence invalid. For example, in reverse
4126 the memory address register was reloaded before the 2nd
4128 if ((! first_p
&& pseudo_p
)
4129 /* We don't use DF for compilation speed sake. So it
4130 is problematic to update live info when we use an
4131 equivalence containing pseudos in more than one
4133 || (pseudo_p
&& multi_block_pseudo_p (i
))
4134 /* If an init insn was deleted for some reason, cancel
4135 the equiv. We could update the equiv insns after
4136 transformations including an equiv insn deletion
4137 but it is not worthy as such cases are extremely
4139 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4140 /* If it is not a reverse equivalence, we check that a
4141 pseudo in rhs of the init insn is not dying in the
4142 insn. Otherwise, the live info at the beginning of
4143 the corresponding BB might be wrong after we
4144 removed the insn. When the equiv can be a
4145 constant, the right hand side of the init insn can
4147 || (! reverse_equiv_p (i
)
4148 && (init_insn_rhs_dead_pseudo_p (i
)
4149 /* If we reloaded the pseudo in an equivalence
4150 init insn, we can not remove the equiv init
4151 insns and the init insns might write into
4152 const memory in this case. */
4153 || contains_reloaded_insn_p (i
)))
4154 /* Prevent access beyond equivalent memory for
4155 paradoxical subregs. */
4157 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4158 > GET_MODE_SIZE (GET_MODE (x
)))))
4159 ira_reg_equiv
[i
].defined_p
= false;
4160 if (contains_reg_p (x
, false, true))
4161 ira_reg_equiv
[i
].profitable_p
= false;
4162 if (get_equiv (reg
) != reg
)
4163 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4166 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4168 /* We should add all insns containing pseudos which should be
4169 substituted by their equivalences. */
4170 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4171 lra_push_insn_by_uid (uid
);
4172 min_len
= lra_insn_stack_length ();
4176 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4178 curr_insn
= lra_pop_insn ();
4180 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4181 if (curr_bb
!= last_bb
)
4184 bb_reload_num
= lra_curr_reload_num
;
4186 if (min_len
> new_min_len
)
4188 min_len
= new_min_len
;
4191 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4193 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4194 MAX_RELOAD_INSNS_NUMBER
);
4196 if (DEBUG_INSN_P (curr_insn
))
4198 /* We need to check equivalence in debug insn and change
4199 pseudo to the equivalent value if necessary. */
4200 curr_id
= lra_get_insn_recog_data (curr_insn
);
4201 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4203 rtx old
= *curr_id
->operand_loc
[0];
4204 *curr_id
->operand_loc
[0]
4205 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4206 loc_equivalence_callback
, curr_insn
);
4207 if (old
!= *curr_id
->operand_loc
[0])
4209 lra_update_insn_regno_info (curr_insn
);
4214 else if (INSN_P (curr_insn
))
4216 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4218 dest_reg
= SET_DEST (set
);
4219 /* The equivalence pseudo could be set up as SUBREG in a
4220 case when it is a call restore insn in a mode
4221 different from the pseudo mode. */
4222 if (GET_CODE (dest_reg
) == SUBREG
)
4223 dest_reg
= SUBREG_REG (dest_reg
);
4224 if ((REG_P (dest_reg
)
4225 && (x
= get_equiv (dest_reg
)) != dest_reg
4226 /* Remove insns which set up a pseudo whose value
4227 can not be changed. Such insns might be not in
4228 init_insns because we don't update equiv data
4229 during insn transformations.
4231 As an example, let suppose that a pseudo got
4232 hard register and on the 1st pass was not
4233 changed to equivalent constant. We generate an
4234 additional insn setting up the pseudo because of
4235 secondary memory movement. Then the pseudo is
4236 spilled and we use the equiv constant. In this
4237 case we should remove the additional insn and
4238 this insn is not init_insns list. */
4239 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4240 /* Check that this is actually an insn setting
4241 up the equivalence. */
4242 || in_list_p (curr_insn
,
4244 [REGNO (dest_reg
)].init_insns
)))
4245 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4246 && in_list_p (curr_insn
,
4248 [REGNO (SET_SRC (set
))].init_insns
)))
4250 /* This is equiv init insn of pseudo which did not get a
4251 hard register -- remove the insn. */
4252 if (lra_dump_file
!= NULL
)
4254 fprintf (lra_dump_file
,
4255 " Removing equiv init insn %i (freq=%d)\n",
4256 INSN_UID (curr_insn
),
4257 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4258 dump_insn_slim (lra_dump_file
, curr_insn
);
4260 if (contains_reg_p (x
, true, false))
4261 lra_risky_transformations_p
= true;
4262 lra_set_insn_deleted (curr_insn
);
4266 curr_id
= lra_get_insn_recog_data (curr_insn
);
4267 curr_static_id
= curr_id
->insn_static_data
;
4268 init_curr_insn_input_reloads ();
4269 init_curr_operand_mode ();
4270 if (curr_insn_transform ())
4272 /* Check non-transformed insns too for equiv change as USE
4273 or CLOBBER don't need reloads but can contain pseudos
4274 being changed on their equivalences. */
4275 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4276 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4278 lra_update_insn_regno_info (curr_insn
);
4283 bitmap_clear (&equiv_insn_bitmap
);
4284 /* If we used a new hard regno, changed_p should be true because the
4285 hard reg is assigned to a new pseudo. */
4286 #ifdef ENABLE_CHECKING
4289 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4290 if (lra_reg_info
[i
].nrefs
!= 0
4291 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4293 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4295 for (j
= 0; j
< nregs
; j
++)
4296 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4303 /* Initiate the LRA constraint pass. It is done once per
4306 lra_constraints_init (void)
4310 /* Finalize the LRA constraint pass. It is done once per
4313 lra_constraints_finish (void)
4319 /* This page contains code to do inheritance/split
4322 /* Number of reloads passed so far in current EBB. */
4323 static int reloads_num
;
4325 /* Number of calls passed so far in current EBB. */
4326 static int calls_num
;
4328 /* Current reload pseudo check for validity of elements in
4330 static int curr_usage_insns_check
;
4332 /* Info about last usage of registers in EBB to do inheritance/split
4333 transformation. Inheritance transformation is done from a spilled
4334 pseudo and split transformations from a hard register or a pseudo
4335 assigned to a hard register. */
4338 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4339 value INSNS is valid. The insns is chain of optional debug insns
4340 and a finishing non-debug insn using the corresponding reg. The
4341 value is also used to mark the registers which are set up in the
4342 current insn. The negated insn uid is used for this. */
4344 /* Value of global reloads_num at the last insn in INSNS. */
4346 /* Value of global reloads_nums at the last insn in INSNS. */
4348 /* It can be true only for splitting. And it means that the restore
4349 insn should be put after insn given by the following member. */
4351 /* Next insns in the current EBB which use the original reg and the
4352 original reg value is not changed between the current insn and
4353 the next insns. In order words, e.g. for inheritance, if we need
4354 to use the original reg value again in the next insns we can try
4355 to use the value in a hard register from a reload insn of the
4360 /* Map: regno -> corresponding pseudo usage insns. */
4361 static struct usage_insns
*usage_insns
;
4364 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4366 usage_insns
[regno
].check
= curr_usage_insns_check
;
4367 usage_insns
[regno
].insns
= insn
;
4368 usage_insns
[regno
].reloads_num
= reloads_num
;
4369 usage_insns
[regno
].calls_num
= calls_num
;
4370 usage_insns
[regno
].after_p
= after_p
;
4373 /* The function is used to form list REGNO usages which consists of
4374 optional debug insns finished by a non-debug insn using REGNO.
4375 RELOADS_NUM is current number of reload insns processed so far. */
4377 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4379 rtx next_usage_insns
;
4381 if (usage_insns
[regno
].check
== curr_usage_insns_check
4382 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4383 && DEBUG_INSN_P (insn
))
4385 /* Check that we did not add the debug insn yet. */
4386 if (next_usage_insns
!= insn
4387 && (GET_CODE (next_usage_insns
) != INSN_LIST
4388 || XEXP (next_usage_insns
, 0) != insn
))
4389 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4392 else if (NONDEBUG_INSN_P (insn
))
4393 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4395 usage_insns
[regno
].check
= 0;
4398 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4399 register NEW_REG. Return true if any change was made. */
4401 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4404 bool result
= false;
4412 code
= GET_CODE (x
);
4413 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4415 enum machine_mode mode
= GET_MODE (*loc
);
4416 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4418 if (mode
!= inner_mode
)
4420 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4421 || ! SCALAR_INT_MODE_P (inner_mode
))
4422 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4424 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4430 /* Scan all the operand sub-expressions. */
4431 fmt
= GET_RTX_FORMAT (code
);
4432 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4436 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4439 else if (fmt
[i
] == 'E')
4441 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4442 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4449 /* Return first non-debug insn in list USAGE_INSNS. */
4451 skip_usage_debug_insns (rtx usage_insns
)
4455 /* Skip debug insns. */
4456 for (insn
= usage_insns
;
4457 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4458 insn
= XEXP (insn
, 1))
4463 /* Return true if we need secondary memory moves for insn in
4464 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4467 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4468 rtx usage_insns ATTRIBUTE_UNUSED
)
4470 #ifndef SECONDARY_MEMORY_NEEDED
4473 rtx insn
, set
, dest
;
4476 if (inher_cl
== ALL_REGS
4477 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4479 lra_assert (INSN_P (insn
));
4480 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4482 dest
= SET_DEST (set
);
4485 lra_assert (inher_cl
!= NO_REGS
);
4486 cl
= get_reg_class (REGNO (dest
));
4487 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4488 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4492 /* Registers involved in inheritance/split in the current EBB
4493 (inheritance/split pseudos and original registers). */
4494 static bitmap_head check_only_regs
;
4496 /* Do inheritance transformations for insn INSN, which defines (if
4497 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4498 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4499 form as the "insns" field of usage_insns. Return true if we
4500 succeed in such transformation.
4502 The transformations look like:
4505 ... p <- i (new insn)
4507 <- ... p ... <- ... i ...
4509 ... i <- p (new insn)
4510 <- ... p ... <- ... i ...
4512 <- ... p ... <- ... i ...
4513 where p is a spilled original pseudo and i is a new inheritance pseudo.
4516 The inheritance pseudo has the smallest class of two classes CL and
4517 class of ORIGINAL REGNO. */
4519 inherit_reload_reg (bool def_p
, int original_regno
,
4520 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4522 if (optimize_function_for_size_p (cfun
))
4525 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4526 rtx original_reg
= regno_reg_rtx
[original_regno
];
4527 rtx new_reg
, new_insns
, usage_insn
;
4529 lra_assert (! usage_insns
[original_regno
].after_p
);
4530 if (lra_dump_file
!= NULL
)
4531 fprintf (lra_dump_file
,
4532 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4533 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4535 if (lra_dump_file
!= NULL
)
4537 fprintf (lra_dump_file
,
4538 " Rejecting inheritance for %d "
4539 "because of disjoint classes %s and %s\n",
4540 original_regno
, reg_class_names
[cl
],
4541 reg_class_names
[rclass
]);
4542 fprintf (lra_dump_file
,
4543 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4547 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4548 /* We don't use a subset of two classes because it can be
4549 NO_REGS. This transformation is still profitable in most
4550 cases even if the classes are not intersected as register
4551 move is probably cheaper than a memory load. */
4552 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4554 if (lra_dump_file
!= NULL
)
4555 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4556 reg_class_names
[cl
], reg_class_names
[rclass
]);
4560 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4562 /* Reject inheritance resulting in secondary memory moves.
4563 Otherwise, there is a danger in LRA cycling. Also such
4564 transformation will be unprofitable. */
4565 if (lra_dump_file
!= NULL
)
4567 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4568 rtx set
= single_set (insn
);
4570 lra_assert (set
!= NULL_RTX
);
4572 rtx dest
= SET_DEST (set
);
4574 lra_assert (REG_P (dest
));
4575 fprintf (lra_dump_file
,
4576 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4577 "as secondary mem is needed\n",
4578 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4579 original_regno
, reg_class_names
[rclass
]);
4580 fprintf (lra_dump_file
,
4581 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4585 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4586 rclass
, "inheritance");
4589 lra_emit_move (original_reg
, new_reg
);
4591 lra_emit_move (new_reg
, original_reg
);
4592 new_insns
= get_insns ();
4594 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4596 if (lra_dump_file
!= NULL
)
4598 fprintf (lra_dump_file
,
4599 " Rejecting inheritance %d->%d "
4600 "as it results in 2 or more insns:\n",
4601 original_regno
, REGNO (new_reg
));
4602 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4603 fprintf (lra_dump_file
,
4604 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4608 substitute_pseudo (&insn
, original_regno
, new_reg
);
4609 lra_update_insn_regno_info (insn
);
4611 /* We now have a new usage insn for original regno. */
4612 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4613 if (lra_dump_file
!= NULL
)
4614 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4615 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4616 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4617 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4618 bitmap_set_bit (&check_only_regs
, original_regno
);
4619 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4621 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4622 "Add original<-inheritance");
4624 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4625 "Add inheritance<-original");
4626 while (next_usage_insns
!= NULL_RTX
)
4628 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4630 usage_insn
= next_usage_insns
;
4631 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4632 next_usage_insns
= NULL
;
4636 usage_insn
= XEXP (next_usage_insns
, 0);
4637 lra_assert (DEBUG_INSN_P (usage_insn
));
4638 next_usage_insns
= XEXP (next_usage_insns
, 1);
4640 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4641 lra_update_insn_regno_info (usage_insn
);
4642 if (lra_dump_file
!= NULL
)
4644 fprintf (lra_dump_file
,
4645 " Inheritance reuse change %d->%d (bb%d):\n",
4646 original_regno
, REGNO (new_reg
),
4647 BLOCK_FOR_INSN (usage_insn
)->index
);
4648 dump_insn_slim (lra_dump_file
, usage_insn
);
4651 if (lra_dump_file
!= NULL
)
4652 fprintf (lra_dump_file
,
4653 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4657 /* Return true if we need a caller save/restore for pseudo REGNO which
4658 was assigned to a hard register. */
4660 need_for_call_save_p (int regno
)
4662 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4663 return (usage_insns
[regno
].calls_num
< calls_num
4664 && (overlaps_hard_reg_set_p
4665 ((flag_use_caller_save
&&
4666 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4667 ? lra_reg_info
[regno
].actual_call_used_reg_set
4668 : call_used_reg_set
,
4669 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4670 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4671 PSEUDO_REGNO_MODE (regno
))));
4674 /* Global registers occurring in the current EBB. */
4675 static bitmap_head ebb_global_regs
;
4677 /* Return true if we need a split for hard register REGNO or pseudo
4678 REGNO which was assigned to a hard register.
4679 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4680 used for reloads since the EBB end. It is an approximation of the
4681 used hard registers in the split range. The exact value would
4682 require expensive calculations. If we were aggressive with
4683 splitting because of the approximation, the split pseudo will save
4684 the same hard register assignment and will be removed in the undo
4685 pass. We still need the approximation because too aggressive
4686 splitting would result in too inaccurate cost calculation in the
4687 assignment pass because of too many generated moves which will be
4688 probably removed in the undo pass. */
4690 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4692 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4694 lra_assert (hard_regno
>= 0);
4695 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4696 /* Don't split eliminable hard registers, otherwise we can
4697 split hard registers like hard frame pointer, which
4698 lives on BB start/end according to DF-infrastructure,
4699 when there is a pseudo assigned to the register and
4700 living in the same BB. */
4701 && (regno
>= FIRST_PSEUDO_REGISTER
4702 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4703 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4704 /* Don't split call clobbered hard regs living through
4705 calls, otherwise we might have a check problem in the
4706 assign sub-pass as in the most cases (exception is a
4707 situation when lra_risky_transformations_p value is
4708 true) the assign pass assumes that all pseudos living
4709 through calls are assigned to call saved hard regs. */
4710 && (regno
>= FIRST_PSEUDO_REGISTER
4711 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4712 || usage_insns
[regno
].calls_num
== calls_num
)
4713 /* We need at least 2 reloads to make pseudo splitting
4714 profitable. We should provide hard regno splitting in
4715 any case to solve 1st insn scheduling problem when
4716 moving hard register definition up might result in
4717 impossibility to find hard register for reload pseudo of
4718 small register class. */
4719 && (usage_insns
[regno
].reloads_num
4720 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4721 && (regno
< FIRST_PSEUDO_REGISTER
4722 /* For short living pseudos, spilling + inheritance can
4723 be considered a substitution for splitting.
4724 Therefore we do not splitting for local pseudos. It
4725 decreases also aggressiveness of splitting. The
4726 minimal number of references is chosen taking into
4727 account that for 2 references splitting has no sense
4728 as we can just spill the pseudo. */
4729 || (regno
>= FIRST_PSEUDO_REGISTER
4730 && lra_reg_info
[regno
].nrefs
> 3
4731 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4732 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4735 /* Return class for the split pseudo created from original pseudo with
4736 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4737 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4738 results in no secondary memory movements. */
4739 static enum reg_class
4740 choose_split_class (enum reg_class allocno_class
,
4741 int hard_regno ATTRIBUTE_UNUSED
,
4742 enum machine_mode mode ATTRIBUTE_UNUSED
)
4744 #ifndef SECONDARY_MEMORY_NEEDED
4745 return allocno_class
;
4748 enum reg_class cl
, best_cl
= NO_REGS
;
4749 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4750 = REGNO_REG_CLASS (hard_regno
);
4752 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4753 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4754 return allocno_class
;
4756 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4758 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4759 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4760 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4761 && (best_cl
== NO_REGS
4762 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4768 /* Do split transformations for insn INSN, which defines or uses
4769 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4770 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4771 "insns" field of usage_insns.
4773 The transformations look like:
4776 ... s <- p (new insn -- save)
4778 ... p <- s (new insn -- restore)
4779 <- ... p ... <- ... p ...
4781 <- ... p ... <- ... p ...
4782 ... s <- p (new insn -- save)
4784 ... p <- s (new insn -- restore)
4785 <- ... p ... <- ... p ...
4787 where p is an original pseudo got a hard register or a hard
4788 register and s is a new split pseudo. The save is put before INSN
4789 if BEFORE_P is true. Return true if we succeed in such
4792 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4794 enum reg_class rclass
;
4796 int hard_regno
, nregs
;
4797 rtx new_reg
, save
, restore
, usage_insn
;
4801 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4803 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4804 hard_regno
= original_regno
;
4805 call_save_p
= false;
4810 hard_regno
= reg_renumber
[original_regno
];
4811 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4812 rclass
= lra_get_allocno_class (original_regno
);
4813 original_reg
= regno_reg_rtx
[original_regno
];
4814 call_save_p
= need_for_call_save_p (original_regno
);
4816 original_reg
= regno_reg_rtx
[original_regno
];
4817 lra_assert (hard_regno
>= 0);
4818 if (lra_dump_file
!= NULL
)
4819 fprintf (lra_dump_file
,
4820 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4823 enum machine_mode mode
= GET_MODE (original_reg
);
4825 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4826 hard_regno_nregs
[hard_regno
][mode
],
4828 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4832 rclass
= choose_split_class (rclass
, hard_regno
,
4833 GET_MODE (original_reg
));
4834 if (rclass
== NO_REGS
)
4836 if (lra_dump_file
!= NULL
)
4838 fprintf (lra_dump_file
,
4839 " Rejecting split of %d(%s): "
4840 "no good reg class for %d(%s)\n",
4842 reg_class_names
[lra_get_allocno_class (original_regno
)],
4844 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4847 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4851 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4853 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4855 save
= emit_spill_move (true, new_reg
, original_reg
);
4856 if (NEXT_INSN (save
) != NULL_RTX
)
4858 lra_assert (! call_save_p
);
4859 if (lra_dump_file
!= NULL
)
4863 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4864 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4865 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4866 fprintf (lra_dump_file
,
4867 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4871 restore
= emit_spill_move (false, new_reg
, original_reg
);
4872 if (NEXT_INSN (restore
) != NULL_RTX
)
4874 lra_assert (! call_save_p
);
4875 if (lra_dump_file
!= NULL
)
4877 fprintf (lra_dump_file
,
4878 " Rejecting split %d->%d "
4879 "resulting in > 2 %s restore insns:\n",
4880 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4881 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4882 fprintf (lra_dump_file
,
4883 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4887 after_p
= usage_insns
[original_regno
].after_p
;
4888 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4889 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4890 bitmap_set_bit (&check_only_regs
, original_regno
);
4891 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4894 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4896 usage_insn
= next_usage_insns
;
4899 usage_insn
= XEXP (next_usage_insns
, 0);
4900 lra_assert (DEBUG_INSN_P (usage_insn
));
4901 next_usage_insns
= XEXP (next_usage_insns
, 1);
4902 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4903 lra_update_insn_regno_info (usage_insn
);
4904 if (lra_dump_file
!= NULL
)
4906 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4907 original_regno
, REGNO (new_reg
));
4908 dump_insn_slim (lra_dump_file
, usage_insn
);
4911 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4912 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4913 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4914 after_p
? restore
: NULL_RTX
,
4916 ? "Add reg<-save" : "Add reg<-split");
4917 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4918 before_p
? NULL_RTX
: save
,
4920 ? "Add save<-reg" : "Add split<-reg");
4922 /* If we are trying to split multi-register. We should check
4923 conflicts on the next assignment sub-pass. IRA can allocate on
4924 sub-register levels, LRA do this on pseudos level right now and
4925 this discrepancy may create allocation conflicts after
4927 lra_risky_transformations_p
= true;
4928 if (lra_dump_file
!= NULL
)
4929 fprintf (lra_dump_file
,
4930 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4934 /* Recognize that we need a split transformation for insn INSN, which
4935 defines or uses REGNO in its insn biggest MODE (we use it only if
4936 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4937 hard registers which might be used for reloads since the EBB end.
4938 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4939 uid before starting INSN processing. Return true if we succeed in
4940 such transformation. */
4942 split_if_necessary (int regno
, enum machine_mode mode
,
4943 HARD_REG_SET potential_reload_hard_regs
,
4944 bool before_p
, rtx insn
, int max_uid
)
4948 rtx next_usage_insns
;
4950 if (regno
< FIRST_PSEUDO_REGISTER
)
4951 nregs
= hard_regno_nregs
[regno
][mode
];
4952 for (i
= 0; i
< nregs
; i
++)
4953 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4954 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4955 /* To avoid processing the register twice or more. */
4956 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4957 && INSN_UID (next_usage_insns
) < max_uid
)
4958 || (GET_CODE (next_usage_insns
) == INSN_LIST
4959 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4960 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4961 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4966 /* Check only registers living at the current program point in the
4968 static bitmap_head live_regs
;
4970 /* Update live info in EBB given by its HEAD and TAIL insns after
4971 inheritance/split transformation. The function removes dead moves
4974 update_ebb_live_info (rtx head
, rtx tail
)
4981 basic_block last_bb
, prev_bb
, curr_bb
;
4983 struct lra_insn_reg
*reg
;
4987 last_bb
= BLOCK_FOR_INSN (tail
);
4989 for (curr_insn
= tail
;
4990 curr_insn
!= PREV_INSN (head
);
4991 curr_insn
= prev_insn
)
4993 prev_insn
= PREV_INSN (curr_insn
);
4994 /* We need to process empty blocks too. They contain
4995 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4996 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4998 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4999 if (curr_bb
!= prev_bb
)
5001 if (prev_bb
!= NULL
)
5003 /* Update df_get_live_in (prev_bb): */
5004 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5005 if (bitmap_bit_p (&live_regs
, j
))
5006 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5008 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5010 if (curr_bb
!= last_bb
)
5012 /* Update df_get_live_out (curr_bb): */
5013 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5015 live_p
= bitmap_bit_p (&live_regs
, j
);
5017 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5018 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5024 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5026 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5030 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5032 if (! NONDEBUG_INSN_P (curr_insn
))
5034 curr_id
= lra_get_insn_recog_data (curr_insn
);
5035 curr_static_id
= curr_id
->insn_static_data
;
5037 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
5038 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5039 && bitmap_bit_p (&check_only_regs
, regno
)
5040 && ! bitmap_bit_p (&live_regs
, regno
))
5042 /* See which defined values die here. */
5043 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5044 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5045 bitmap_clear_bit (&live_regs
, reg
->regno
);
5046 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5047 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5048 bitmap_clear_bit (&live_regs
, reg
->regno
);
5049 /* Mark each used value as live. */
5050 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5051 if (reg
->type
!= OP_OUT
5052 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5053 bitmap_set_bit (&live_regs
, reg
->regno
);
5054 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5055 if (reg
->type
!= OP_OUT
5056 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5057 bitmap_set_bit (&live_regs
, reg
->regno
);
5058 if (curr_id
->arg_hard_regs
!= NULL
)
5059 /* Make argument hard registers live. */
5060 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5061 if (bitmap_bit_p (&check_only_regs
, regno
))
5062 bitmap_set_bit (&live_regs
, regno
);
5063 /* It is quite important to remove dead move insns because it
5064 means removing dead store. We don't need to process them for
5068 if (lra_dump_file
!= NULL
)
5070 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5071 dump_insn_slim (lra_dump_file
, curr_insn
);
5073 lra_set_insn_deleted (curr_insn
);
5078 /* The structure describes info to do an inheritance for the current
5079 insn. We need to collect such info first before doing the
5080 transformations because the transformations change the insn
5081 internal representation. */
5084 /* Original regno. */
5086 /* Subsequent insns which can inherit original reg value. */
5090 /* Array containing all info for doing inheritance from the current
5092 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5094 /* Number elements in the previous array. */
5095 static int to_inherit_num
;
5097 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5098 structure to_inherit. */
5100 add_to_inherit (int regno
, rtx insns
)
5104 for (i
= 0; i
< to_inherit_num
; i
++)
5105 if (to_inherit
[i
].regno
== regno
)
5107 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5108 to_inherit
[to_inherit_num
].regno
= regno
;
5109 to_inherit
[to_inherit_num
++].insns
= insns
;
5112 /* Return the last non-debug insn in basic block BB, or the block begin
5115 get_last_insertion_point (basic_block bb
)
5119 FOR_BB_INSNS_REVERSE (bb
, insn
)
5120 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5125 /* Set up RES by registers living on edges FROM except the edge (FROM,
5126 TO) or by registers set up in a jump insn in BB FROM. */
5128 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5131 struct lra_insn_reg
*reg
;
5135 lra_assert (to
!= NULL
);
5137 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5139 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5140 last
= get_last_insertion_point (from
);
5141 if (! JUMP_P (last
))
5143 curr_id
= lra_get_insn_recog_data (last
);
5144 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5145 if (reg
->type
!= OP_IN
)
5146 bitmap_set_bit (res
, reg
->regno
);
5149 /* Used as a temporary results of some bitmap calculations. */
5150 static bitmap_head temp_bitmap
;
5152 /* We split for reloads of small class of hard regs. The following
5153 defines how many hard regs the class should have to be qualified as
5154 small. The code is mostly oriented to x86/x86-64 architecture
5155 where some insns need to use only specific register or pair of
5156 registers and these register can live in RTL explicitly, e.g. for
5157 parameter passing. */
5158 static const int max_small_class_regs_num
= 2;
5160 /* Do inheritance/split transformations in EBB starting with HEAD and
5161 finishing on TAIL. We process EBB insns in the reverse order.
5162 Return true if we did any inheritance/split transformation in the
5165 We should avoid excessive splitting which results in worse code
5166 because of inaccurate cost calculations for spilling new split
5167 pseudos in such case. To achieve this we do splitting only if
5168 register pressure is high in given basic block and there are reload
5169 pseudos requiring hard registers. We could do more register
5170 pressure calculations at any given program point to avoid necessary
5171 splitting even more but it is to expensive and the current approach
5172 works well enough. */
5174 inherit_in_ebb (rtx head
, rtx tail
)
5176 int i
, src_regno
, dst_regno
, nregs
;
5177 bool change_p
, succ_p
, update_reloads_num_p
;
5178 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
5180 struct lra_insn_reg
*reg
;
5181 basic_block last_processed_bb
, curr_bb
= NULL
;
5182 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5186 bool head_p
, after_p
;
5189 curr_usage_insns_check
++;
5190 reloads_num
= calls_num
= 0;
5191 bitmap_clear (&check_only_regs
);
5192 last_processed_bb
= NULL
;
5193 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5194 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5195 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5196 /* We don't process new insns generated in the loop. */
5197 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5199 prev_insn
= PREV_INSN (curr_insn
);
5200 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5201 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5202 if (last_processed_bb
!= curr_bb
)
5204 /* We are at the end of BB. Add qualified living
5205 pseudos for potential splitting. */
5206 to_process
= df_get_live_out (curr_bb
);
5207 if (last_processed_bb
!= NULL
)
5209 /* We are somewhere in the middle of EBB. */
5210 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5212 to_process
= &temp_bitmap
;
5214 last_processed_bb
= curr_bb
;
5215 last_insn
= get_last_insertion_point (curr_bb
);
5216 after_p
= (! JUMP_P (last_insn
)
5217 && (! CALL_P (last_insn
)
5218 || (find_reg_note (last_insn
,
5219 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5220 && ! SIBLING_CALL_P (last_insn
))));
5221 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5222 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5224 if ((int) j
>= lra_constraint_new_regno_start
)
5226 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5228 if (j
< FIRST_PSEUDO_REGISTER
)
5229 SET_HARD_REG_BIT (live_hard_regs
, j
);
5231 add_to_hard_reg_set (&live_hard_regs
,
5232 PSEUDO_REGNO_MODE (j
),
5234 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5238 src_regno
= dst_regno
= -1;
5239 if (NONDEBUG_INSN_P (curr_insn
)
5240 && (set
= single_set (curr_insn
)) != NULL_RTX
5241 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5243 src_regno
= REGNO (SET_SRC (set
));
5244 dst_regno
= REGNO (SET_DEST (set
));
5246 update_reloads_num_p
= true;
5247 if (src_regno
< lra_constraint_new_regno_start
5248 && src_regno
>= FIRST_PSEUDO_REGISTER
5249 && reg_renumber
[src_regno
] < 0
5250 && dst_regno
>= lra_constraint_new_regno_start
5251 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5253 /* 'reload_pseudo <- original_pseudo'. */
5254 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5256 update_reloads_num_p
= false;
5258 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5259 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5260 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5261 curr_insn
, next_usage_insns
);
5265 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5266 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5267 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5268 reg_class_contents
[cl
]);
5270 else if (src_regno
>= lra_constraint_new_regno_start
5271 && dst_regno
< lra_constraint_new_regno_start
5272 && dst_regno
>= FIRST_PSEUDO_REGISTER
5273 && reg_renumber
[dst_regno
] < 0
5274 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5275 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5276 && (next_usage_insns
5277 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5279 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5281 update_reloads_num_p
= false;
5282 /* 'original_pseudo <- reload_pseudo'. */
5283 if (! JUMP_P (curr_insn
)
5284 && inherit_reload_reg (true, dst_regno
, cl
,
5285 curr_insn
, next_usage_insns
))
5288 usage_insns
[dst_regno
].check
= 0;
5289 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5290 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5291 reg_class_contents
[cl
]);
5293 else if (INSN_P (curr_insn
))
5296 int max_uid
= get_max_uid ();
5298 curr_id
= lra_get_insn_recog_data (curr_insn
);
5299 curr_static_id
= curr_id
->insn_static_data
;
5301 /* Process insn definitions. */
5302 for (iter
= 0; iter
< 2; iter
++)
5303 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5306 if (reg
->type
!= OP_IN
5307 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5309 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5310 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5311 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5312 && (next_usage_insns
5313 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5315 struct lra_insn_reg
*r
;
5317 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5318 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5320 /* Don't do inheritance if the pseudo is also
5321 used in the insn. */
5323 /* We can not do inheritance right now
5324 because the current insn reg info (chain
5325 regs) can change after that. */
5326 add_to_inherit (dst_regno
, next_usage_insns
);
5328 /* We can not process one reg twice here because of
5329 usage_insns invalidation. */
5330 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5331 || reg_renumber
[dst_regno
] >= 0)
5332 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5336 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5337 potential_reload_hard_regs
,
5338 false, curr_insn
, max_uid
))
5340 CLEAR_HARD_REG_SET (s
);
5341 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5342 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5344 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5345 reg_renumber
[dst_regno
]);
5346 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5348 /* We should invalidate potential inheritance or
5349 splitting for the current insn usages to the next
5350 usage insns (see code below) as the output pseudo
5352 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5353 && reg_renumber
[dst_regno
] < 0)
5354 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5355 && (dst_regno
< FIRST_PSEUDO_REGISTER
5356 || reg_renumber
[dst_regno
] >= 0)))
5358 /* Invalidate and mark definitions. */
5359 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5360 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5363 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5364 for (i
= 0; i
< nregs
; i
++)
5365 usage_insns
[dst_regno
+ i
].check
5366 = -(int) INSN_UID (curr_insn
);
5370 if (! JUMP_P (curr_insn
))
5371 for (i
= 0; i
< to_inherit_num
; i
++)
5372 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5373 ALL_REGS
, curr_insn
,
5374 to_inherit
[i
].insns
))
5376 if (CALL_P (curr_insn
))
5378 rtx cheap
, pat
, dest
, restore
;
5379 int regno
, hard_regno
;
5382 if ((cheap
= find_reg_note (curr_insn
,
5383 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5384 && ((cheap
= XEXP (cheap
, 0)), true)
5385 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5386 && (hard_regno
= reg_renumber
[regno
]) >= 0
5387 /* If there are pending saves/restores, the
5388 optimization is not worth. */
5389 && usage_insns
[regno
].calls_num
== calls_num
- 1
5390 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5392 /* Restore the pseudo from the call result as
5393 REG_RETURNED note says that the pseudo value is
5394 in the call result and the pseudo is an argument
5396 pat
= PATTERN (curr_insn
);
5397 if (GET_CODE (pat
) == PARALLEL
)
5398 pat
= XVECEXP (pat
, 0, 0);
5399 dest
= SET_DEST (pat
);
5401 emit_move_insn (cheap
, copy_rtx (dest
));
5402 restore
= get_insns ();
5404 lra_process_new_insns (curr_insn
, NULL
, restore
,
5405 "Inserting call parameter restore");
5406 /* We don't need to save/restore of the pseudo from
5408 usage_insns
[regno
].calls_num
= calls_num
;
5409 bitmap_set_bit (&check_only_regs
, regno
);
5413 /* Process insn usages. */
5414 for (iter
= 0; iter
< 2; iter
++)
5415 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5418 if ((reg
->type
!= OP_OUT
5419 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5420 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5422 if (src_regno
>= FIRST_PSEUDO_REGISTER
5423 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5425 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5426 && (next_usage_insns
5427 = usage_insns
[src_regno
].insns
) != NULL_RTX
5428 && NONDEBUG_INSN_P (curr_insn
))
5429 add_to_inherit (src_regno
, next_usage_insns
);
5430 else if (usage_insns
[src_regno
].check
5431 != -(int) INSN_UID (curr_insn
))
5432 /* Add usages but only if the reg is not set up
5433 in the same insn. */
5434 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5436 else if (src_regno
< FIRST_PSEUDO_REGISTER
5437 || reg_renumber
[src_regno
] >= 0)
5440 rtx use_insn
= curr_insn
;
5442 before_p
= (JUMP_P (curr_insn
)
5443 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5444 if (NONDEBUG_INSN_P (curr_insn
)
5445 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5446 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5447 potential_reload_hard_regs
,
5448 before_p
, curr_insn
, max_uid
))
5451 lra_risky_transformations_p
= true;
5454 usage_insns
[src_regno
].check
= 0;
5456 use_insn
= PREV_INSN (curr_insn
);
5458 if (NONDEBUG_INSN_P (curr_insn
))
5460 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5461 add_to_hard_reg_set (&live_hard_regs
,
5462 reg
->biggest_mode
, src_regno
);
5464 add_to_hard_reg_set (&live_hard_regs
,
5465 PSEUDO_REGNO_MODE (src_regno
),
5466 reg_renumber
[src_regno
]);
5468 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5471 /* Process call args. */
5472 if (curr_id
->arg_hard_regs
!= NULL
)
5473 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5474 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5476 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5477 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5479 for (i
= 0; i
< to_inherit_num
; i
++)
5481 src_regno
= to_inherit
[i
].regno
;
5482 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5483 curr_insn
, to_inherit
[i
].insns
))
5486 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5489 if (update_reloads_num_p
5490 && NONDEBUG_INSN_P (curr_insn
)
5491 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5494 if ((REG_P (SET_DEST (set
))
5495 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5496 && reg_renumber
[regno
] < 0
5497 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5498 || (REG_P (SET_SRC (set
))
5499 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5500 && reg_renumber
[regno
] < 0
5501 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5503 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5505 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5506 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5507 reg_class_contents
[cl
]);
5510 /* We reached the start of the current basic block. */
5511 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5512 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5514 /* We reached the beginning of the current block -- do
5515 rest of spliting in the current BB. */
5516 to_process
= df_get_live_in (curr_bb
);
5517 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5519 /* We are somewhere in the middle of EBB. */
5520 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5521 curr_bb
, &temp_bitmap
);
5522 to_process
= &temp_bitmap
;
5525 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5527 if ((int) j
>= lra_constraint_new_regno_start
)
5529 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5530 && usage_insns
[j
].check
== curr_usage_insns_check
5531 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5533 if (need_for_split_p (potential_reload_hard_regs
, j
))
5535 if (lra_dump_file
!= NULL
&& head_p
)
5537 fprintf (lra_dump_file
,
5538 " ----------------------------------\n");
5541 if (split_reg (false, j
, bb_note (curr_bb
),
5545 usage_insns
[j
].check
= 0;
5553 /* This value affects EBB forming. If probability of edge from EBB to
5554 a BB is not greater than the following value, we don't add the BB
5556 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5558 /* Current number of inheritance/split iteration. */
5559 int lra_inheritance_iter
;
5561 /* Entry function for inheritance/split pass. */
5563 lra_inheritance (void)
5566 basic_block bb
, start_bb
;
5569 lra_inheritance_iter
++;
5570 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5572 timevar_push (TV_LRA_INHERITANCE
);
5573 if (lra_dump_file
!= NULL
)
5574 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5575 lra_inheritance_iter
);
5576 curr_usage_insns_check
= 0;
5577 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5578 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5579 usage_insns
[i
].check
= 0;
5580 bitmap_initialize (&check_only_regs
, ®_obstack
);
5581 bitmap_initialize (&live_regs
, ®_obstack
);
5582 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5583 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5584 FOR_EACH_BB_FN (bb
, cfun
)
5587 if (lra_dump_file
!= NULL
)
5588 fprintf (lra_dump_file
, "EBB");
5589 /* Form a EBB starting with BB. */
5590 bitmap_clear (&ebb_global_regs
);
5591 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5594 if (lra_dump_file
!= NULL
)
5595 fprintf (lra_dump_file
, " %d", bb
->index
);
5596 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5597 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5599 e
= find_fallthru_edge (bb
->succs
);
5602 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5606 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5607 if (lra_dump_file
!= NULL
)
5608 fprintf (lra_dump_file
, "\n");
5609 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5610 /* Remember that the EBB head and tail can change in
5612 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5614 bitmap_clear (&ebb_global_regs
);
5615 bitmap_clear (&temp_bitmap
);
5616 bitmap_clear (&live_regs
);
5617 bitmap_clear (&check_only_regs
);
5620 timevar_pop (TV_LRA_INHERITANCE
);
5625 /* This page contains code to undo failed inheritance/split
5628 /* Current number of iteration undoing inheritance/split. */
5629 int lra_undo_inheritance_iter
;
5631 /* Fix BB live info LIVE after removing pseudos created on pass doing
5632 inheritance/split which are REMOVED_PSEUDOS. */
5634 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5639 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5640 if (bitmap_clear_bit (live
, regno
))
5641 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5644 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5649 if (GET_CODE (reg
) == SUBREG
)
5650 reg
= SUBREG_REG (reg
);
5656 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5657 return true if we did any change. The undo transformations for
5658 inheritance looks like
5662 p <- i, i <- p, and i <- i3
5663 where p is original pseudo from which inheritance pseudo i was
5664 created, i and i3 are removed inheritance pseudos, i2 is another
5665 not removed inheritance pseudo. All split pseudos or other
5666 occurrences of removed inheritance pseudos are changed on the
5667 corresponding original pseudos.
5669 The function also schedules insns changed and created during
5670 inheritance/split pass for processing by the subsequent constraint
5673 remove_inheritance_pseudos (bitmap remove_pseudos
)
5676 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5677 rtx set
, prev_set
, prev_insn
;
5678 bool change_p
, done_p
;
5680 change_p
= ! bitmap_empty_p (remove_pseudos
);
5681 /* We can not finish the function right away if CHANGE_P is true
5682 because we need to marks insns affected by previous
5683 inheritance/split pass for processing by the subsequent
5685 FOR_EACH_BB_FN (bb
, cfun
)
5687 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5688 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5689 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5691 if (! INSN_P (curr_insn
))
5694 sregno
= dregno
= -1;
5695 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5696 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5698 dregno
= get_regno (SET_DEST (set
));
5699 sregno
= get_regno (SET_SRC (set
));
5702 if (sregno
>= 0 && dregno
>= 0)
5704 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5705 && (lra_reg_info
[sregno
].restore_regno
== dregno
5706 || (bitmap_bit_p (remove_pseudos
, dregno
)
5707 && (lra_reg_info
[sregno
].restore_regno
5708 == lra_reg_info
[dregno
].restore_regno
))))
5709 || (bitmap_bit_p (remove_pseudos
, dregno
)
5710 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5711 /* One of the following cases:
5712 original <- removed inheritance pseudo
5713 removed inherit pseudo <- another removed inherit pseudo
5714 removed inherit pseudo <- original pseudo
5716 removed_split_pseudo <- original_reg
5717 original_reg <- removed_split_pseudo */
5719 if (lra_dump_file
!= NULL
)
5721 fprintf (lra_dump_file
, " Removing %s:\n",
5722 bitmap_bit_p (&lra_split_regs
, sregno
)
5723 || bitmap_bit_p (&lra_split_regs
, dregno
)
5724 ? "split" : "inheritance");
5725 dump_insn_slim (lra_dump_file
, curr_insn
);
5727 lra_set_insn_deleted (curr_insn
);
5730 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5731 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5733 /* Search the following pattern:
5734 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5735 original_pseudo <- inherit_or_split_pseudo1
5736 where the 2nd insn is the current insn and
5737 inherit_or_split_pseudo2 is not removed. If it is found,
5738 change the current insn onto:
5739 original_pseudo <- inherit_or_split_pseudo2. */
5740 for (prev_insn
= PREV_INSN (curr_insn
);
5741 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5742 prev_insn
= PREV_INSN (prev_insn
))
5744 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5745 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5746 /* There should be no subregs in insn we are
5747 searching because only the original reg might
5748 be in subreg when we changed the mode of
5749 load/store for splitting. */
5750 && REG_P (SET_DEST (prev_set
))
5751 && REG_P (SET_SRC (prev_set
))
5752 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5753 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5754 >= FIRST_PSEUDO_REGISTER
)
5755 /* As we consider chain of inheritance or
5756 splitting described in above comment we should
5757 check that sregno and prev_sregno were
5758 inheritance/split pseudos created from the
5759 same original regno. */
5760 && (lra_reg_info
[sregno
].restore_regno
5761 == lra_reg_info
[prev_sregno
].restore_regno
)
5762 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5764 lra_assert (GET_MODE (SET_SRC (prev_set
))
5765 == GET_MODE (regno_reg_rtx
[sregno
]));
5766 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5767 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5769 SET_SRC (set
) = SET_SRC (prev_set
);
5770 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5771 lra_set_used_insn_alternative_by_uid
5772 (INSN_UID (curr_insn
), -1);
5774 if (lra_dump_file
!= NULL
)
5776 fprintf (lra_dump_file
, " Change reload insn:\n");
5777 dump_insn_slim (lra_dump_file
, curr_insn
);
5784 struct lra_insn_reg
*reg
;
5785 bool restored_regs_p
= false;
5786 bool kept_regs_p
= false;
5788 curr_id
= lra_get_insn_recog_data (curr_insn
);
5789 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5792 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5793 if (restore_regno
>= 0)
5795 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5797 substitute_pseudo (&curr_insn
, regno
,
5798 regno_reg_rtx
[restore_regno
]);
5799 restored_regs_p
= true;
5805 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5807 /* The instruction has changed since the previous
5808 constraints pass. */
5809 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5810 lra_set_used_insn_alternative_by_uid
5811 (INSN_UID (curr_insn
), -1);
5813 else if (restored_regs_p
)
5814 /* The instruction has been restored to the form that
5815 it had during the previous constraints pass. */
5816 lra_update_insn_regno_info (curr_insn
);
5817 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5819 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5820 dump_insn_slim (lra_dump_file
, curr_insn
);
5828 /* If optional reload pseudos failed to get a hard register or was not
5829 inherited, it is better to remove optional reloads. We do this
5830 transformation after undoing inheritance to figure out necessity to
5831 remove optional reloads easier. Return true if we do any
5834 undo_optional_reloads (void)
5836 bool change_p
, keep_p
;
5837 unsigned int regno
, uid
;
5838 bitmap_iterator bi
, bi2
;
5839 rtx insn
, set
, src
, dest
;
5840 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5842 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5843 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5844 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5847 /* Keep optional reloads from previous subpasses. */
5848 if (lra_reg_info
[regno
].restore_regno
< 0
5849 /* If the original pseudo changed its allocation, just
5850 removing the optional pseudo is dangerous as the original
5851 pseudo will have longer live range. */
5852 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5854 else if (reg_renumber
[regno
] >= 0)
5855 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5857 insn
= lra_insn_recog_data
[uid
]->insn
;
5858 if ((set
= single_set (insn
)) == NULL_RTX
)
5860 src
= SET_SRC (set
);
5861 dest
= SET_DEST (set
);
5862 if (! REG_P (src
) || ! REG_P (dest
))
5864 if (REGNO (dest
) == regno
5865 /* Ignore insn for optional reloads itself. */
5866 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5867 /* Check only inheritance on last inheritance pass. */
5868 && (int) REGNO (src
) >= new_regno_start
5869 /* Check that the optional reload was inherited. */
5870 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5878 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5879 if (lra_dump_file
!= NULL
)
5880 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5883 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5884 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5885 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5887 if (lra_dump_file
!= NULL
)
5888 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5889 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5890 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5892 insn
= lra_insn_recog_data
[uid
]->insn
;
5893 if ((set
= single_set (insn
)) != NULL_RTX
)
5895 src
= SET_SRC (set
);
5896 dest
= SET_DEST (set
);
5897 if (REG_P (src
) && REG_P (dest
)
5898 && ((REGNO (src
) == regno
5899 && (lra_reg_info
[regno
].restore_regno
5900 == (int) REGNO (dest
)))
5901 || (REGNO (dest
) == regno
5902 && (lra_reg_info
[regno
].restore_regno
5903 == (int) REGNO (src
)))))
5905 if (lra_dump_file
!= NULL
)
5907 fprintf (lra_dump_file
, " Deleting move %u\n",
5909 dump_insn_slim (lra_dump_file
, insn
);
5911 lra_set_insn_deleted (insn
);
5914 /* We should not worry about generation memory-memory
5915 moves here as if the corresponding inheritance did
5916 not work (inheritance pseudo did not get a hard reg),
5917 we remove the inheritance pseudo and the optional
5920 substitute_pseudo (&insn
, regno
,
5921 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5922 lra_update_insn_regno_info (insn
);
5923 if (lra_dump_file
!= NULL
)
5925 fprintf (lra_dump_file
,
5926 " Restoring original insn:\n");
5927 dump_insn_slim (lra_dump_file
, insn
);
5931 /* Clear restore_regnos. */
5932 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5933 lra_reg_info
[regno
].restore_regno
= -1;
5934 bitmap_clear (&insn_bitmap
);
5935 bitmap_clear (&removed_optional_reload_pseudos
);
5939 /* Entry function for undoing inheritance/split transformation. Return true
5940 if we did any RTL change in this pass. */
5942 lra_undo_inheritance (void)
5945 int restore_regno
, hard_regno
;
5946 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5947 bitmap_head remove_pseudos
;
5951 lra_undo_inheritance_iter
++;
5952 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5954 if (lra_dump_file
!= NULL
)
5955 fprintf (lra_dump_file
,
5956 "\n********** Undoing inheritance #%d: **********\n\n",
5957 lra_undo_inheritance_iter
);
5958 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5959 n_inherit
= n_all_inherit
= 0;
5960 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5961 if (lra_reg_info
[regno
].restore_regno
>= 0)
5964 if (reg_renumber
[regno
] < 0
5965 /* If the original pseudo changed its allocation, just
5966 removing inheritance is dangerous as for changing
5967 allocation we used shorter live-ranges. */
5968 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5969 bitmap_set_bit (&remove_pseudos
, regno
);
5973 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5974 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5975 n_inherit
, n_all_inherit
,
5976 (double) n_inherit
/ n_all_inherit
* 100);
5977 n_split
= n_all_split
= 0;
5978 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5979 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5982 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5983 ? reg_renumber
[restore_regno
] : restore_regno
);
5984 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5985 bitmap_set_bit (&remove_pseudos
, regno
);
5989 if (lra_dump_file
!= NULL
)
5990 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5991 regno
, restore_regno
);
5994 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5995 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5996 n_split
, n_all_split
,
5997 (double) n_split
/ n_all_split
* 100);
5998 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5999 bitmap_clear (&remove_pseudos
);
6000 /* Clear restore_regnos. */
6001 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6002 lra_reg_info
[regno
].restore_regno
= -1;
6003 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6004 lra_reg_info
[regno
].restore_regno
= -1;
6005 change_p
= undo_optional_reloads () || change_p
;