1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || INSN_UID (curr_insn
) >= new_insn_uid_start
)
273 /* When we don't know what class will be used finally for reload
274 pseudos, we use ALL_REGS. */
275 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
276 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
277 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
278 lra_no_alloc_regs
)));
281 common_class
= ira_reg_class_subset
[rclass
][cl
];
282 if (new_class
!= NULL
)
283 *new_class
= common_class
;
284 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
287 /* Check that there are enough allocatable regs. */
288 class_size
= ira_class_hard_regs_num
[common_class
];
289 for (i
= 0; i
< class_size
; i
++)
291 hard_regno
= ira_class_hard_regs
[common_class
][i
];
292 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
295 for (j
= 0; j
< nregs
; j
++)
296 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
297 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
307 /* Return true if REGNO satisfies a memory constraint. */
311 return get_reg_class (regno
) == NO_REGS
;
314 /* If we have decided to substitute X with another value, return that
315 value, otherwise return X. */
317 get_equiv_substitution (rtx x
)
322 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
323 || ! ira_reg_equiv
[regno
].defined_p
324 || ! ira_reg_equiv
[regno
].profitable_p
325 || lra_get_regno_hard_regno (regno
) >= 0)
327 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
329 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
331 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
336 /* Set up curr_operand_mode. */
338 init_curr_operand_mode (void)
340 int nop
= curr_static_id
->n_operands
;
341 for (int i
= 0; i
< nop
; i
++)
343 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
344 if (mode
== VOIDmode
)
346 /* The .md mode for address operands is the mode of the
347 addressed value rather than the mode of the address itself. */
348 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
351 mode
= curr_static_id
->operand
[i
].mode
;
353 curr_operand_mode
[i
] = mode
;
359 /* The page contains code to reuse input reloads. */
361 /* Structure describes input reload of the current insns. */
364 /* Reloaded value. */
366 /* Reload pseudo used. */
370 /* The number of elements in the following array. */
371 static int curr_insn_input_reloads_num
;
372 /* Array containing info about input reloads. It is used to find the
373 same input reload and reuse the reload pseudo in this case. */
374 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
376 /* Initiate data concerning reuse of input reloads for the current
379 init_curr_insn_input_reloads (void)
381 curr_insn_input_reloads_num
= 0;
384 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
385 using TITLE. Output a new line if NL_P. */
387 change_class (int regno
, enum reg_class new_class
,
388 const char *title
, bool nl_p
)
390 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
);
391 if (lra_dump_file
!= NULL
)
392 fprintf (lra_dump_file
, "%s to class %s for r%d",
393 title
, reg_class_names
[new_class
], regno
);
394 setup_reg_classes (regno
, new_class
, NO_REGS
, new_class
);
395 if (lra_dump_file
!= NULL
&& nl_p
)
396 fprintf (lra_dump_file
, "\n");
399 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
400 created input reload pseudo (only if TYPE is not OP_OUT). The
401 result pseudo is returned through RESULT_REG. Return TRUE if we
402 created a new pseudo, FALSE if we reused the already created input
403 reload pseudo. Use TITLE to describe new registers for debug
406 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
407 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
410 enum reg_class new_class
;
415 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
418 /* Prevent reuse value of expression with side effects,
419 e.g. volatile memory. */
420 if (! side_effects_p (original
))
421 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
422 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
423 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
425 rtx reg
= curr_insn_input_reloads
[i
].reg
;
427 /* If input is equal to original and both are VOIDmode,
428 GET_MODE (reg) might be still different from mode.
429 Ensure we don't return *result_reg with wrong mode. */
430 if (GET_MODE (reg
) != mode
)
432 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
434 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
435 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
439 if (lra_dump_file
!= NULL
)
441 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
442 dump_value_slim (lra_dump_file
, original
, 1);
444 if (new_class
!= lra_get_allocno_class (regno
))
445 change_class (regno
, new_class
, ", change", false);
446 if (lra_dump_file
!= NULL
)
447 fprintf (lra_dump_file
, "\n");
450 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
451 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
452 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
453 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
459 /* The page contains code to extract memory address parts. */
461 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
463 ok_for_index_p_nonstrict (rtx reg
)
465 unsigned regno
= REGNO (reg
);
467 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
470 /* A version of regno_ok_for_base_p for use here, when all pseudos
471 should count as OK. Arguments as for regno_ok_for_base_p. */
473 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
474 enum rtx_code outer_code
, enum rtx_code index_code
)
476 unsigned regno
= REGNO (reg
);
478 if (regno
>= FIRST_PSEUDO_REGISTER
)
480 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
485 /* The page contains major code to choose the current insn alternative
486 and generate reloads for it. */
488 /* Return the offset from REGNO of the least significant register
491 This function is used to tell whether two registers satisfy
492 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
494 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
495 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
497 lra_constraint_offset (int regno
, enum machine_mode mode
)
499 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
500 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
501 && SCALAR_INT_MODE_P (mode
))
502 return hard_regno_nregs
[regno
][mode
] - 1;
506 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
507 if they are the same hard reg, and has special hacks for
508 auto-increment and auto-decrement. This is specifically intended for
509 process_alt_operands to use in determining whether two operands
510 match. X is the operand whose number is the lower of the two.
512 It is supposed that X is the output operand and Y is the input
513 operand. Y_HARD_REGNO is the final hard regno of register Y or
514 register in subreg Y as we know it now. Otherwise, it is a
517 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
520 RTX_CODE code
= GET_CODE (x
);
525 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
526 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
530 i
= get_hard_regno (x
);
534 if ((j
= y_hard_regno
) < 0)
537 i
+= lra_constraint_offset (i
, GET_MODE (x
));
538 j
+= lra_constraint_offset (j
, GET_MODE (y
));
543 /* If two operands must match, because they are really a single
544 operand of an assembler insn, then two post-increments are invalid
545 because the assembler insn would increment only once. On the
546 other hand, a post-increment matches ordinary indexing if the
547 post-increment is the output operand. */
548 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
549 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
551 /* Two pre-increments are invalid because the assembler insn would
552 increment only once. On the other hand, a pre-increment matches
553 ordinary indexing if the pre-increment is the input operand. */
554 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
555 || GET_CODE (y
) == PRE_MODIFY
)
556 return operands_match_p (x
, XEXP (y
, 0), -1);
560 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
561 && x
== SUBREG_REG (y
))
563 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
564 && SUBREG_REG (x
) == y
)
567 /* Now we have disposed of all the cases in which different rtx
569 if (code
!= GET_CODE (y
))
572 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
573 if (GET_MODE (x
) != GET_MODE (y
))
582 return XEXP (x
, 0) == XEXP (y
, 0);
584 return XSTR (x
, 0) == XSTR (y
, 0);
590 /* Compare the elements. If any pair of corresponding elements fail
591 to match, return false for the whole things. */
593 fmt
= GET_RTX_FORMAT (code
);
594 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
600 if (XWINT (x
, i
) != XWINT (y
, i
))
605 if (XINT (x
, i
) != XINT (y
, i
))
610 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
619 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
621 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
623 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
629 /* It is believed that rtx's at this level will never
630 contain anything but integers and other rtx's, except for
631 within LABEL_REFs and SYMBOL_REFs. */
639 /* True if X is a constant that can be forced into the constant pool.
640 MODE is the mode of the operand, or VOIDmode if not known. */
641 #define CONST_POOL_OK_P(MODE, X) \
642 ((MODE) != VOIDmode \
644 && GET_CODE (X) != HIGH \
645 && !targetm.cannot_force_const_mem (MODE, X))
647 /* True if C is a non-empty register class that has too few registers
648 to be safely used as a reload target class. */
649 #define SMALL_REGISTER_CLASS_P(C) \
650 (reg_class_size [(C)] == 1 \
651 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
653 /* If REG is a reload pseudo, try to make its class satisfying CL. */
655 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
657 enum reg_class rclass
;
659 /* Do not make more accurate class from reloads generated. They are
660 mostly moves with a lot of constraints. Making more accurate
661 class may results in very narrow class and impossibility of find
662 registers for several reloads of one insn. */
663 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
665 if (GET_CODE (reg
) == SUBREG
)
666 reg
= SUBREG_REG (reg
);
667 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
669 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
670 change_class (REGNO (reg
), rclass
, " Change", true);
673 /* Generate reloads for matching OUT and INS (array of input operand
674 numbers with end marker -1) with reg class GOAL_CLASS. Add input
675 and output reloads correspondingly to the lists *BEFORE and *AFTER.
676 OUT might be negative. In this case we generate input reloads for
677 matched input operands INS. */
679 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
680 rtx
*before
, rtx
*after
)
683 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
684 enum machine_mode inmode
, outmode
;
685 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
686 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
688 inmode
= curr_operand_mode
[ins
[0]];
689 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
690 push_to_sequence (*before
);
691 if (inmode
!= outmode
)
693 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
696 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
698 if (SCALAR_INT_MODE_P (inmode
))
699 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
701 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
702 LRA_SUBREG_P (new_out_reg
) = 1;
703 /* If the input reg is dying here, we can use the same hard
704 register for REG and IN_RTX. We do it only for original
705 pseudos as reload pseudos can die although original
706 pseudos still live where reload pseudos dies. */
707 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
708 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
709 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
714 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
716 if (SCALAR_INT_MODE_P (outmode
))
717 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
719 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
720 /* NEW_IN_REG is non-paradoxical subreg. We don't want
721 NEW_OUT_REG living above. We add clobber clause for
722 this. This is just a temporary clobber. We can remove
723 it at the end of LRA work. */
724 clobber
= emit_clobber (new_out_reg
);
725 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
726 LRA_SUBREG_P (new_in_reg
) = 1;
727 if (GET_CODE (in_rtx
) == SUBREG
)
729 rtx subreg_reg
= SUBREG_REG (in_rtx
);
731 /* If SUBREG_REG is dying here and sub-registers IN_RTX
732 and NEW_IN_REG are similar, we can use the same hard
733 register for REG and SUBREG_REG. */
734 if (REG_P (subreg_reg
)
735 && (int) REGNO (subreg_reg
) < lra_new_regno_start
736 && GET_MODE (subreg_reg
) == outmode
737 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
738 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
739 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
745 /* Pseudos have values -- see comments for lra_reg_info.
746 Different pseudos with the same value do not conflict even if
747 they live in the same place. When we create a pseudo we
748 assign value of original pseudo (if any) from which we
749 created the new pseudo. If we create the pseudo from the
750 input pseudo, the new pseudo will no conflict with the input
751 pseudo which is wrong when the input pseudo lives after the
752 insn and as the new pseudo value is changed by the insn
753 output. Therefore we create the new pseudo from the output.
755 We cannot reuse the current output register because we might
756 have a situation like "a <- a op b", where the constraints
757 force the second input operand ("b") to match the output
758 operand ("a"). "b" must then be copied into a new register
759 so that it doesn't clobber the current value of "a". */
761 new_in_reg
= new_out_reg
762 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
765 /* In operand can be got from transformations before processing insn
766 constraints. One example of such transformations is subreg
767 reloading (see function simplify_operand_subreg). The new
768 pseudos created by the transformations might have inaccurate
769 class (ALL_REGS) and we should make their classes more
771 narrow_reload_pseudo_class (in_rtx
, goal_class
);
772 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
773 *before
= get_insns ();
775 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
778 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
779 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
780 *curr_id
->operand_loc
[in
] = new_in_reg
;
782 lra_update_dups (curr_id
, ins
);
785 /* See a comment for the input operand above. */
786 narrow_reload_pseudo_class (out_rtx
, goal_class
);
787 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
790 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
792 *after
= get_insns ();
795 *curr_id
->operand_loc
[out
] = new_out_reg
;
796 lra_update_dup (curr_id
, out
);
799 /* Return register class which is union of all reg classes in insn
800 constraint alternative string starting with P. */
801 static enum reg_class
802 reg_class_from_constraints (const char *p
)
805 enum reg_class op_class
= NO_REGS
;
808 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
815 op_class
= (reg_class_subunion
816 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
822 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
826 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
828 #ifdef EXTRA_CONSTRAINT_STR
829 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
831 = (reg_class_subunion
832 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
839 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
842 while ((p
+= len
), c
);
846 /* If OP is a register, return the class of the register as per
847 get_reg_class, otherwise return NO_REGS. */
848 static inline enum reg_class
849 get_op_class (rtx op
)
851 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
854 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
855 otherwise. If modes of MEM_PSEUDO and VAL are different, use
856 SUBREG for VAL to make them equal. */
858 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
860 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
862 /* Usually size of mem_pseudo is greater than val size but in
863 rare cases it can be less as it can be defined by target
864 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
867 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
868 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
870 LRA_SUBREG_P (val
) = 1;
874 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
875 LRA_SUBREG_P (mem_pseudo
) = 1;
879 ? gen_move_insn (mem_pseudo
, val
)
880 : gen_move_insn (val
, mem_pseudo
));
883 /* Process a special case insn (register move), return true if we
884 don't need to process it anymore. INSN should be a single set
885 insn. Set up that RTL was changed through CHANGE_P and macro
886 SECONDARY_MEMORY_NEEDED says to use secondary memory through
889 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
892 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
893 enum reg_class dclass
, sclass
, secondary_class
;
894 enum machine_mode sreg_mode
;
895 secondary_reload_info sri
;
897 lra_assert (curr_insn_set
!= NULL_RTX
);
898 dreg
= dest
= SET_DEST (curr_insn_set
);
899 sreg
= src
= SET_SRC (curr_insn_set
);
900 if (GET_CODE (dest
) == SUBREG
)
901 dreg
= SUBREG_REG (dest
);
902 if (GET_CODE (src
) == SUBREG
)
903 sreg
= SUBREG_REG (src
);
904 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
906 sclass
= dclass
= NO_REGS
;
908 dclass
= get_reg_class (REGNO (dreg
));
909 if (dclass
== ALL_REGS
)
910 /* ALL_REGS is used for new pseudos created by transformations
911 like reload of SUBREG_REG (see function
912 simplify_operand_subreg). We don't know their class yet. We
913 should figure out the class from processing the insn
914 constraints not in this fast path function. Even if ALL_REGS
915 were a right class for the pseudo, secondary_... hooks usually
916 are not define for ALL_REGS. */
918 sreg_mode
= GET_MODE (sreg
);
921 sclass
= get_reg_class (REGNO (sreg
));
922 if (sclass
== ALL_REGS
)
923 /* See comments above. */
925 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
927 #ifdef SECONDARY_MEMORY_NEEDED
928 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
929 #ifdef SECONDARY_MEMORY_NEEDED_MODE
930 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
931 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
939 if (! REG_P (dreg
) || ! REG_P (sreg
))
942 sri
.icode
= CODE_FOR_nothing
;
944 secondary_class
= NO_REGS
;
945 /* Set up hard register for a reload pseudo for hook
946 secondary_reload because some targets just ignore unassigned
947 pseudos in the hook. */
948 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
950 dregno
= REGNO (dreg
);
951 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
955 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
957 sregno
= REGNO (sreg
);
958 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
962 if (sclass
!= NO_REGS
)
964 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
965 (reg_class_t
) sclass
,
966 GET_MODE (src
), &sri
);
967 if (sclass
== NO_REGS
968 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
969 && dclass
!= NO_REGS
))
971 enum reg_class old_sclass
= secondary_class
;
972 secondary_reload_info old_sri
= sri
;
975 sri
.icode
= CODE_FOR_nothing
;
978 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
979 (reg_class_t
) dclass
,
981 /* Check the target hook consistency. */
983 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
984 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
985 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
988 reg_renumber
[sregno
] = -1;
990 reg_renumber
[dregno
] = -1;
991 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
995 if (secondary_class
!= NO_REGS
)
996 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1000 if (old_sreg
!= sreg
)
1001 sreg
= copy_rtx (sreg
);
1002 if (sri
.icode
== CODE_FOR_nothing
)
1003 lra_emit_move (new_reg
, sreg
);
1006 enum reg_class scratch_class
;
1008 scratch_class
= (reg_class_from_constraints
1009 (insn_data
[sri
.icode
].operand
[2].constraint
));
1010 scratch_reg
= (lra_create_new_reg_with_unique_value
1011 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1012 scratch_class
, "scratch"));
1013 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1014 sreg
, scratch_reg
));
1016 before
= get_insns ();
1018 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1019 if (new_reg
!= NULL_RTX
)
1021 if (GET_CODE (src
) == SUBREG
)
1022 SUBREG_REG (src
) = new_reg
;
1024 SET_SRC (curr_insn_set
) = new_reg
;
1028 if (lra_dump_file
!= NULL
)
1030 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1031 dump_insn_slim (lra_dump_file
, curr_insn
);
1033 lra_set_insn_deleted (curr_insn
);
1039 /* The following data describe the result of process_alt_operands.
1040 The data are used in curr_insn_transform to generate reloads. */
1042 /* The chosen reg classes which should be used for the corresponding
1044 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1045 /* True if the operand should be the same as another operand and that
1046 other operand does not need a reload. */
1047 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1048 /* True if the operand does not need a reload. */
1049 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1050 /* True if the operand can be offsetable memory. */
1051 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1052 /* The number of an operand to which given operand can be matched to. */
1053 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1054 /* The number of elements in the following array. */
1055 static int goal_alt_dont_inherit_ops_num
;
1056 /* Numbers of operands whose reload pseudos should not be inherited. */
1057 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1058 /* True if the insn commutative operands should be swapped. */
1059 static bool goal_alt_swapped
;
1060 /* The chosen insn alternative. */
1061 static int goal_alt_number
;
1063 /* The following five variables are used to choose the best insn
1064 alternative. They reflect final characteristics of the best
1067 /* Number of necessary reloads and overall cost reflecting the
1068 previous value and other unpleasantness of the best alternative. */
1069 static int best_losers
, best_overall
;
1070 /* Overall number hard registers used for reloads. For example, on
1071 some targets we need 2 general registers to reload DFmode and only
1072 one floating point register. */
1073 static int best_reload_nregs
;
1074 /* Overall number reflecting distances of previous reloading the same
1075 value. The distances are counted from the current BB start. It is
1076 used to improve inheritance chances. */
1077 static int best_reload_sum
;
1079 /* True if the current insn should have no correspondingly input or
1081 static bool no_input_reloads_p
, no_output_reloads_p
;
1083 /* True if we swapped the commutative operands in the current
1085 static int curr_swapped
;
1087 /* Arrange for address element *LOC to be a register of class CL.
1088 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1089 automodified value; handle that case by adding the required output
1090 reloads to list AFTER. Return true if the RTL was changed. */
1092 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1095 enum reg_class rclass
, new_class
;
1098 enum machine_mode mode
;
1099 bool before_p
= false;
1101 loc
= strip_subreg (loc
);
1103 mode
= GET_MODE (reg
);
1106 /* Always reload memory in an address even if the target supports
1108 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1113 regno
= REGNO (reg
);
1114 rclass
= get_reg_class (regno
);
1115 if ((*loc
= get_equiv_substitution (reg
)) != reg
)
1117 if (lra_dump_file
!= NULL
)
1119 fprintf (lra_dump_file
,
1120 "Changing pseudo %d in address of insn %u on equiv ",
1121 REGNO (reg
), INSN_UID (curr_insn
));
1122 dump_value_slim (lra_dump_file
, *loc
, 1);
1123 fprintf (lra_dump_file
, "\n");
1125 *loc
= copy_rtx (*loc
);
1127 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1130 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1131 mode
, reg
, cl
, "address", &new_reg
))
1134 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1136 change_class (regno
, new_class
, " Change", true);
1144 push_to_sequence (*before
);
1145 lra_emit_move (new_reg
, reg
);
1146 *before
= get_insns ();
1153 lra_emit_move (reg
, new_reg
);
1155 *after
= get_insns ();
1161 /* Make reloads for subreg in operand NOP with internal subreg mode
1162 REG_MODE, add new reloads for further processing. Return true if
1163 any reload was generated. */
1165 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1169 enum machine_mode mode
;
1171 rtx operand
= *curr_id
->operand_loc
[nop
];
1173 before
= after
= NULL_RTX
;
1175 if (GET_CODE (operand
) != SUBREG
)
1178 mode
= GET_MODE (operand
);
1179 reg
= SUBREG_REG (operand
);
1180 /* If we change address for paradoxical subreg of memory, the
1181 address might violate the necessary alignment or the access might
1182 be slow. So take this into consideration. We should not worry
1183 about access beyond allocated memory for paradoxical memory
1184 subregs as we don't substitute such equiv memory (see processing
1185 equivalences in function lra_constraints) and because for spilled
1186 pseudos we allocate stack memory enough for the biggest
1187 corresponding paradoxical subreg. */
1189 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1190 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1191 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1193 alter_subreg (curr_id
->operand_loc
[nop
], false);
1196 /* Put constant into memory when we have mixed modes. It generates
1197 a better code in most cases as it does not need a secondary
1198 reload memory. It also prevents LRA looping when LRA is using
1199 secondary reload memory again and again. */
1200 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1201 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1203 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1204 alter_subreg (curr_id
->operand_loc
[nop
], false);
1207 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1208 if there may be a problem accessing OPERAND in the outer
1211 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1212 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1213 /* Don't reload paradoxical subregs because we could be looping
1214 having repeatedly final regno out of hard regs range. */
1215 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1216 >= hard_regno_nregs
[hard_regno
][mode
])
1217 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1218 SUBREG_BYTE (operand
), mode
) < 0
1219 /* Don't reload subreg for matching reload. It is actually
1220 valid subreg in LRA. */
1221 && ! LRA_SUBREG_P (operand
))
1222 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1224 enum op_type type
= curr_static_id
->operand
[nop
].type
;
1225 /* The class will be defined later in curr_insn_transform. */
1226 enum reg_class rclass
1227 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1229 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1230 rclass
, "subreg reg", &new_reg
))
1232 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1234 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
))
1236 push_to_sequence (before
);
1237 lra_emit_move (new_reg
, reg
);
1238 before
= get_insns ();
1244 lra_emit_move (reg
, new_reg
);
1246 after
= get_insns ();
1250 SUBREG_REG (operand
) = new_reg
;
1251 lra_process_new_insns (curr_insn
, before
, after
,
1252 "Inserting subreg reload");
1258 /* Return TRUE if X refers for a hard register from SET. */
1260 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1262 int i
, j
, x_hard_regno
;
1263 enum machine_mode mode
;
1269 code
= GET_CODE (x
);
1270 mode
= GET_MODE (x
);
1274 code
= GET_CODE (x
);
1275 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1276 mode
= GET_MODE (x
);
1281 x_hard_regno
= get_hard_regno (x
);
1282 return (x_hard_regno
>= 0
1283 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1287 struct address_info ad
;
1289 decompose_mem_address (&ad
, x
);
1290 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1292 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1295 fmt
= GET_RTX_FORMAT (code
);
1296 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1300 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1303 else if (fmt
[i
] == 'E')
1305 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1306 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1313 /* Return true if OP is a spilled pseudo. */
1315 spilled_pseudo_p (rtx op
)
1318 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1321 /* Return true if X is a general constant. */
1323 general_constant_p (rtx x
)
1325 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1329 reg_in_class_p (rtx reg
, enum reg_class cl
)
1332 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1333 return in_class_p (reg
, cl
, NULL
);
1336 /* Major function to choose the current insn alternative and what
1337 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1338 negative we should consider only this alternative. Return false if
1339 we can not choose the alternative or find how to reload the
1342 process_alt_operands (int only_alternative
)
1345 int nop
, overall
, nalt
;
1346 int n_alternatives
= curr_static_id
->n_alternatives
;
1347 int n_operands
= curr_static_id
->n_operands
;
1348 /* LOSERS counts the operands that don't fit this alternative and
1349 would require loading. */
1351 /* REJECT is a count of how undesirable this alternative says it is
1352 if any reloading is required. If the alternative matches exactly
1353 then REJECT is ignored, but otherwise it gets this much counted
1354 against it in addition to the reloading needed. */
1356 /* The number of elements in the following array. */
1357 int early_clobbered_regs_num
;
1358 /* Numbers of operands which are early clobber registers. */
1359 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1360 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1361 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1362 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1363 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1364 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1365 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1366 /* The number of elements in the following array. */
1367 int curr_alt_dont_inherit_ops_num
;
1368 /* Numbers of operands whose reload pseudos should not be inherited. */
1369 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1371 /* The register when the operand is a subreg of register, otherwise the
1373 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1374 /* The register if the operand is a register or subreg of register,
1376 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1377 int hard_regno
[MAX_RECOG_OPERANDS
];
1378 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1379 int reload_nregs
, reload_sum
;
1383 /* Calculate some data common for all alternatives to speed up the
1385 for (nop
= 0; nop
< n_operands
; nop
++)
1387 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1388 /* The real hard regno of the operand after the allocation. */
1389 hard_regno
[nop
] = get_hard_regno (op
);
1391 operand_reg
[nop
] = op
;
1392 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1393 if (GET_CODE (operand_reg
[nop
]) == SUBREG
)
1395 operand_reg
[nop
] = SUBREG_REG (operand_reg
[nop
]);
1396 if (GET_MODE_SIZE (biggest_mode
[nop
])
1397 < GET_MODE_SIZE (GET_MODE (operand_reg
[nop
])))
1398 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1400 if (REG_P (operand_reg
[nop
]))
1401 no_subreg_reg_operand
[nop
] = operand_reg
[nop
];
1403 operand_reg
[nop
] = NULL_RTX
;
1406 /* The constraints are made of several alternatives. Each operand's
1407 constraint looks like foo,bar,... with commas separating the
1408 alternatives. The first alternatives for all operands go
1409 together, the second alternatives go together, etc.
1411 First loop over alternatives. */
1412 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1414 /* Loop over operands for one constraint alternative. */
1415 #if HAVE_ATTR_enabled
1416 if (curr_id
->alternative_enabled_p
!= NULL
1417 && ! curr_id
->alternative_enabled_p
[nalt
])
1421 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1425 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1426 for (nop
= 0; nop
< n_operands
; nop
++)
1428 int inc
= (curr_static_id
1429 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1430 if (lra_dump_file
!= NULL
&& inc
!= 0)
1431 fprintf (lra_dump_file
,
1432 " Staticly defined alt reject+=%d\n", inc
);
1435 early_clobbered_regs_num
= 0;
1437 for (nop
= 0; nop
< n_operands
; nop
++)
1441 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1442 bool win
, did_match
, offmemok
, early_clobber_p
;
1443 /* false => this operand can be reloaded somehow for this
1446 /* true => this operand can be reloaded if the alternative
1449 /* True if a constant forced into memory would be OK for
1452 enum reg_class this_alternative
, this_costly_alternative
;
1453 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1454 bool this_alternative_match_win
, this_alternative_win
;
1455 bool this_alternative_offmemok
;
1457 enum machine_mode mode
;
1459 opalt_num
= nalt
* n_operands
+ nop
;
1460 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1462 /* Fast track for no constraints at all. */
1463 curr_alt
[nop
] = NO_REGS
;
1464 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1465 curr_alt_win
[nop
] = true;
1466 curr_alt_match_win
[nop
] = false;
1467 curr_alt_offmemok
[nop
] = false;
1468 curr_alt_matches
[nop
] = -1;
1472 op
= no_subreg_reg_operand
[nop
];
1473 mode
= curr_operand_mode
[nop
];
1475 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1478 early_clobber_p
= false;
1479 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1481 this_costly_alternative
= this_alternative
= NO_REGS
;
1482 /* We update set of possible hard regs besides its class
1483 because reg class might be inaccurate. For example,
1484 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1485 is translated in HI_REGS because classes are merged by
1486 pairs and there is no accurate intermediate class. */
1487 CLEAR_HARD_REG_SET (this_alternative_set
);
1488 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1489 this_alternative_win
= false;
1490 this_alternative_match_win
= false;
1491 this_alternative_offmemok
= false;
1492 this_alternative_matches
= -1;
1494 /* An empty constraint should be excluded by the fast
1496 lra_assert (*p
!= 0 && *p
!= ',');
1498 /* Scan this alternative's specs for this operand; set WIN
1499 if the operand fits any letter in this alternative.
1500 Otherwise, clear BADOP if this operand could fit some
1501 letter after reloads, or set WINREG if this operand could
1502 fit after reloads provided the constraint allows some
1507 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1516 case '=': case '+': case '?': case '*': case '!':
1517 case ' ': case '\t':
1521 /* We only support one commutative marker, the first
1522 one. We already set commutative above. */
1526 early_clobber_p
= true;
1530 /* Ignore rest of this alternative. */
1534 case '0': case '1': case '2': case '3': case '4':
1535 case '5': case '6': case '7': case '8': case '9':
1540 m
= strtoul (p
, &end
, 10);
1543 lra_assert (nop
> m
);
1545 this_alternative_matches
= m
;
1546 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1547 /* We are supposed to match a previous operand.
1548 If we do, we win if that one did. If we do
1549 not, count both of the operands as losers.
1550 (This is too conservative, since most of the
1551 time only a single reload insn will be needed
1552 to make the two operands win. As a result,
1553 this alternative may be rejected when it is
1554 actually desirable.) */
1556 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1557 *curr_id
->operand_loc
[m
], m_hregno
))
1559 /* We should reject matching of an early
1560 clobber operand if the matching operand is
1561 not dying in the insn. */
1562 if (! curr_static_id
->operand
[m
].early_clobber
1563 || operand_reg
[nop
] == NULL_RTX
1564 || (find_regno_note (curr_insn
, REG_DEAD
,
1566 || REGNO (op
) == REGNO (operand_reg
[m
])))
1571 /* If we are matching a non-offsettable
1572 address where an offsettable address was
1573 expected, then we must reject this
1574 combination, because we can't reload
1576 if (curr_alt_offmemok
[m
]
1577 && MEM_P (*curr_id
->operand_loc
[m
])
1578 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1584 /* Operands don't match. Both operands must
1585 allow a reload register, otherwise we
1586 cannot make them match. */
1587 if (curr_alt
[m
] == NO_REGS
)
1589 /* Retroactively mark the operand we had to
1590 match as a loser, if it wasn't already and
1591 it wasn't matched to a register constraint
1592 (e.g it might be matched by memory). */
1594 && (operand_reg
[m
] == NULL_RTX
1595 || hard_regno
[m
] < 0))
1599 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1600 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1603 /* We prefer no matching alternatives because
1604 it gives more freedom in RA. */
1605 if (operand_reg
[nop
] == NULL_RTX
1606 || (find_regno_note (curr_insn
, REG_DEAD
,
1607 REGNO (operand_reg
[nop
]))
1610 if (lra_dump_file
!= NULL
)
1613 " %d Matching alt: reject+=2\n",
1618 /* If we have to reload this operand and some
1619 previous operand also had to match the same
1620 thing as this operand, we don't know how to do
1622 if (!match_p
|| !curr_alt_win
[m
])
1624 for (i
= 0; i
< nop
; i
++)
1625 if (curr_alt_matches
[i
] == m
)
1633 /* This can be fixed with reloads if the operand
1634 we are supposed to match can be fixed with
1637 this_alternative
= curr_alt
[m
];
1638 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1639 winreg
= this_alternative
!= NO_REGS
;
1644 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1646 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1647 IOR_HARD_REG_SET (this_alternative_set
,
1648 reg_class_contents
[cl
]);
1651 this_costly_alternative
1652 = reg_class_subunion
[this_costly_alternative
][cl
];
1653 IOR_HARD_REG_SET (this_costly_alternative_set
,
1654 reg_class_contents
[cl
]);
1660 case TARGET_MEM_CONSTRAINT
:
1661 if (MEM_P (op
) || spilled_pseudo_p (op
))
1663 /* We can put constant or pseudo value into memory
1664 to satisfy the constraint. */
1665 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1672 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1673 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1679 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1680 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1684 /* Memory op whose address is not offsettable. */
1687 && ! offsettable_nonstrict_memref_p (op
))
1691 /* Memory operand whose address is offsettable. */
1694 && offsettable_nonstrict_memref_p (op
))
1695 || spilled_pseudo_p (op
))
1697 /* We can put constant or pseudo value into memory
1698 or make memory address offsetable to satisfy the
1700 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1708 if (GET_CODE (op
) == CONST_DOUBLE
1709 || (GET_CODE (op
) == CONST_VECTOR
1710 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1716 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1717 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1722 if (CONST_SCALAR_INT_P (op
))
1726 if (general_constant_p (op
))
1731 if (CONST_SCALAR_INT_P (op
))
1743 if (CONST_INT_P (op
)
1744 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1749 /* This constraint should be excluded by the fast
1756 || general_constant_p (op
)
1757 || spilled_pseudo_p (op
))
1759 /* Drop through into 'r' case. */
1763 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1764 IOR_HARD_REG_SET (this_alternative_set
,
1765 reg_class_contents
[GENERAL_REGS
]);
1768 this_costly_alternative
1769 = (reg_class_subunion
1770 [this_costly_alternative
][GENERAL_REGS
]);
1771 IOR_HARD_REG_SET (this_costly_alternative_set
,
1772 reg_class_contents
[GENERAL_REGS
]);
1777 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1779 #ifdef EXTRA_CONSTRAINT_STR
1780 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1782 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1784 else if (spilled_pseudo_p (op
))
1787 /* If we didn't already win, we can reload
1788 constants via force_const_mem or put the
1789 pseudo value into memory, or make other
1790 memory by reloading the address like for
1792 if (CONST_POOL_OK_P (mode
, op
)
1793 || MEM_P (op
) || REG_P (op
))
1799 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1801 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1804 /* If we didn't already win, we can reload
1805 the address into a base register. */
1806 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1809 = reg_class_subunion
[this_alternative
][cl
];
1810 IOR_HARD_REG_SET (this_alternative_set
,
1811 reg_class_contents
[cl
]);
1814 this_costly_alternative
1815 = (reg_class_subunion
1816 [this_costly_alternative
][cl
]);
1817 IOR_HARD_REG_SET (this_costly_alternative_set
,
1818 reg_class_contents
[cl
]);
1824 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1830 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1831 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1832 IOR_HARD_REG_SET (this_alternative_set
,
1833 reg_class_contents
[cl
]);
1836 this_costly_alternative
1837 = reg_class_subunion
[this_costly_alternative
][cl
];
1838 IOR_HARD_REG_SET (this_costly_alternative_set
,
1839 reg_class_contents
[cl
]);
1842 if (mode
== BLKmode
)
1847 if (hard_regno
[nop
] >= 0
1848 && in_hard_reg_set_p (this_alternative_set
,
1849 mode
, hard_regno
[nop
]))
1851 else if (hard_regno
[nop
] < 0
1852 && in_class_p (op
, this_alternative
, NULL
))
1857 if (c
!= ' ' && c
!= '\t')
1858 costly_p
= c
== '*';
1860 while ((p
+= len
), c
);
1862 scratch_p
= (operand_reg
[nop
] != NULL_RTX
1863 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
1864 /* Record which operands fit this alternative. */
1867 this_alternative_win
= true;
1868 if (operand_reg
[nop
] != NULL_RTX
)
1870 if (hard_regno
[nop
] >= 0)
1872 if (in_hard_reg_set_p (this_costly_alternative_set
,
1873 mode
, hard_regno
[nop
]))
1875 if (lra_dump_file
!= NULL
)
1876 fprintf (lra_dump_file
,
1877 " %d Costly set: reject++\n",
1884 /* Prefer won reg to spilled pseudo under other
1885 equal conditions for possibe inheritance. */
1888 if (lra_dump_file
!= NULL
)
1891 " %d Non pseudo reload: reject++\n",
1895 if (in_class_p (operand_reg
[nop
],
1896 this_costly_alternative
, NULL
))
1898 if (lra_dump_file
!= NULL
)
1901 " %d Non pseudo costly reload:"
1907 /* We simulate the behaviour of old reload here.
1908 Although scratches need hard registers and it
1909 might result in spilling other pseudos, no reload
1910 insns are generated for the scratches. So it
1911 might cost something but probably less than old
1912 reload pass believes. */
1915 if (lra_dump_file
!= NULL
)
1916 fprintf (lra_dump_file
,
1917 " %d Scratch win: reject+=2\n",
1924 this_alternative_match_win
= true;
1927 int const_to_mem
= 0;
1930 /* If this alternative asks for a specific reg class, see if there
1931 is at least one allocatable register in that class. */
1933 = (this_alternative
== NO_REGS
1934 || (hard_reg_set_subset_p
1935 (reg_class_contents
[this_alternative
],
1936 lra_no_alloc_regs
)));
1938 /* For asms, verify that the class for this alternative is possible
1939 for the mode that is specified. */
1940 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
1943 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1944 if (HARD_REGNO_MODE_OK (i
, mode
)
1945 && in_hard_reg_set_p (reg_class_contents
[this_alternative
], mode
, i
))
1947 if (i
== FIRST_PSEUDO_REGISTER
)
1951 /* If this operand accepts a register, and if the
1952 register class has at least one allocatable register,
1953 then this operand can be reloaded. */
1954 if (winreg
&& !no_regs_p
)
1960 this_alternative_offmemok
= offmemok
;
1961 if (this_costly_alternative
!= NO_REGS
)
1963 if (lra_dump_file
!= NULL
)
1964 fprintf (lra_dump_file
,
1965 " %d Costly loser: reject++\n", nop
);
1968 /* If the operand is dying, has a matching constraint,
1969 and satisfies constraints of the matched operand
1970 which failed to satisfy the own constraints, we do
1971 not need to generate a reload insn for this
1973 if (!(this_alternative_matches
>= 0
1974 && !curr_alt_win
[this_alternative_matches
]
1976 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
1977 && (hard_regno
[nop
] >= 0
1978 ? in_hard_reg_set_p (this_alternative_set
,
1979 mode
, hard_regno
[nop
])
1980 : in_class_p (op
, this_alternative
, NULL
))))
1982 /* Strict_low_part requires to reload the register
1983 not the sub-register. In this case we should
1984 check that a final reload hard reg can hold the
1986 if (curr_static_id
->operand
[nop
].strict_low
1988 && hard_regno
[nop
] < 0
1989 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
1990 && ira_class_hard_regs_num
[this_alternative
] > 0
1991 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
1992 [this_alternative
][0],
1994 (*curr_id
->operand_loc
[nop
])))
1998 if (operand_reg
[nop
] != NULL_RTX
1999 /* Output operands and matched input operands are
2000 not inherited. The following conditions do not
2001 exactly describe the previous statement but they
2002 are pretty close. */
2003 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2004 && (this_alternative_matches
< 0
2005 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2007 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2011 if (last_reload
> bb_reload_num
)
2012 reload_sum
+= last_reload
- bb_reload_num
;
2014 /* If this is a constant that is reloaded into the
2015 desired class by copying it to memory first, count
2016 that as another reload. This is consistent with
2017 other code and is required to avoid choosing another
2018 alternative when the constant is moved into memory.
2019 Note that the test here is precisely the same as in
2020 the code below that calls force_const_mem. */
2021 if (CONST_POOL_OK_P (mode
, op
)
2022 && ((targetm
.preferred_reload_class
2023 (op
, this_alternative
) == NO_REGS
)
2024 || no_input_reloads_p
))
2031 /* Alternative loses if it requires a type of reload not
2032 permitted for this insn. We can always reload
2033 objects with a REG_UNUSED note. */
2034 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2035 && no_output_reloads_p
2036 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2037 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2038 && no_input_reloads_p
&& ! const_to_mem
))
2041 /* Check strong discouragement of reload of non-constant
2042 into class THIS_ALTERNATIVE. */
2043 if (! CONSTANT_P (op
) && ! no_regs_p
2044 && (targetm
.preferred_reload_class
2045 (op
, this_alternative
) == NO_REGS
2046 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2047 && (targetm
.preferred_output_reload_class
2048 (op
, this_alternative
) == NO_REGS
))))
2050 if (lra_dump_file
!= NULL
)
2051 fprintf (lra_dump_file
,
2052 " %d Non-prefered reload: reject+=%d\n",
2053 nop
, LRA_MAX_REJECT
);
2054 reject
+= LRA_MAX_REJECT
;
2057 if (! (MEM_P (op
) && offmemok
)
2058 && ! (const_to_mem
&& constmemok
))
2060 /* We prefer to reload pseudos over reloading other
2061 things, since such reloads may be able to be
2062 eliminated later. So bump REJECT in other cases.
2063 Don't do this in the case where we are forcing a
2064 constant into memory and it will then win since
2065 we don't want to have a different alternative
2067 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2069 if (lra_dump_file
!= NULL
)
2072 " %d Non-pseudo reload: reject+=2\n",
2079 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2081 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2083 if (lra_dump_file
!= NULL
)
2086 " %d Small class reload: reject+=%d\n",
2087 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2088 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2092 /* We are trying to spill pseudo into memory. It is
2093 usually more costly than moving to a hard register
2094 although it might takes the same number of
2096 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2098 if (lra_dump_file
!= NULL
)
2101 " %d Spill pseudo in memory: reject+=3\n",
2106 #ifdef SECONDARY_MEMORY_NEEDED
2107 /* If reload requires moving value through secondary
2108 memory, it will need one more insn at least. */
2109 if (this_alternative
!= NO_REGS
2110 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2111 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2112 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2114 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2115 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2119 /* Input reloads can be inherited more often than output
2120 reloads can be removed, so penalize output
2122 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2124 if (lra_dump_file
!= NULL
)
2127 " %d Non input pseudo reload: reject++\n",
2133 if (early_clobber_p
&& ! scratch_p
)
2135 if (lra_dump_file
!= NULL
)
2136 fprintf (lra_dump_file
,
2137 " %d Early clobber: reject++\n", nop
);
2140 /* ??? We check early clobbers after processing all operands
2141 (see loop below) and there we update the costs more.
2142 Should we update the cost (may be approximately) here
2143 because of early clobber register reloads or it is a rare
2144 or non-important thing to be worth to do it. */
2145 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2146 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2148 if (lra_dump_file
!= NULL
)
2149 fprintf (lra_dump_file
,
2150 " alt=%d,overall=%d,losers=%d -- refuse\n",
2151 nalt
, overall
, losers
);
2155 curr_alt
[nop
] = this_alternative
;
2156 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2157 curr_alt_win
[nop
] = this_alternative_win
;
2158 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2159 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2160 curr_alt_matches
[nop
] = this_alternative_matches
;
2162 if (this_alternative_matches
>= 0
2163 && !did_match
&& !this_alternative_win
)
2164 curr_alt_win
[this_alternative_matches
] = false;
2166 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2167 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2169 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2170 /* Prevent processing non-move insns. */
2171 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2172 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2173 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2174 && REG_P (no_subreg_reg_operand
[0])
2175 && REG_P (no_subreg_reg_operand
[1])
2176 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2177 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2178 || (! curr_alt_win
[0] && curr_alt_win
[1]
2179 && REG_P (no_subreg_reg_operand
[1])
2180 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2181 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2182 && REG_P (no_subreg_reg_operand
[0])
2183 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2184 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2185 no_subreg_reg_operand
[1])
2186 || (targetm
.preferred_reload_class
2187 (no_subreg_reg_operand
[1],
2188 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2189 /* If it is a result of recent elimination in move
2190 insn we can transform it into an add still by
2191 using this alternative. */
2192 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2194 /* We have a move insn and a new reload insn will be similar
2195 to the current insn. We should avoid such situation as it
2196 results in LRA cycling. */
2197 overall
+= LRA_MAX_REJECT
;
2200 curr_alt_dont_inherit_ops_num
= 0;
2201 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2203 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2204 HARD_REG_SET temp_set
;
2206 i
= early_clobbered_nops
[nop
];
2207 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2208 || hard_regno
[i
] < 0)
2210 lra_assert (operand_reg
[i
] != NULL_RTX
);
2211 clobbered_hard_regno
= hard_regno
[i
];
2212 CLEAR_HARD_REG_SET (temp_set
);
2213 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2214 first_conflict_j
= last_conflict_j
= -1;
2215 for (j
= 0; j
< n_operands
; j
++)
2217 /* We don't want process insides of match_operator and
2218 match_parallel because otherwise we would process
2219 their operands once again generating a wrong
2221 || curr_static_id
->operand
[j
].is_operator
)
2223 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2224 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2226 /* If we don't reload j-th operand, check conflicts. */
2227 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2228 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2230 if (first_conflict_j
< 0)
2231 first_conflict_j
= j
;
2232 last_conflict_j
= j
;
2234 if (last_conflict_j
< 0)
2236 /* If earlyclobber operand conflicts with another
2237 non-matching operand which is actually the same register
2238 as the earlyclobber operand, it is better to reload the
2239 another operand as an operand matching the earlyclobber
2240 operand can be also the same. */
2241 if (first_conflict_j
== last_conflict_j
2242 && operand_reg
[last_conflict_j
]
2243 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2244 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2246 curr_alt_win
[last_conflict_j
] = false;
2247 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2250 /* Early clobber was already reflected in REJECT. */
2251 lra_assert (reject
> 0);
2252 if (lra_dump_file
!= NULL
)
2255 " %d Conflict early clobber reload: reject--\n",
2258 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2262 /* We need to reload early clobbered register and the
2263 matched registers. */
2264 for (j
= 0; j
< n_operands
; j
++)
2265 if (curr_alt_matches
[j
] == i
)
2267 curr_alt_match_win
[j
] = false;
2269 overall
+= LRA_LOSER_COST_FACTOR
;
2271 if (! curr_alt_match_win
[i
])
2272 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2275 /* Remember pseudos used for match reloads are never
2277 lra_assert (curr_alt_matches
[i
] >= 0);
2278 curr_alt_win
[curr_alt_matches
[i
]] = false;
2280 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2282 /* Early clobber was already reflected in REJECT. */
2283 lra_assert (reject
> 0);
2284 if (lra_dump_file
!= NULL
)
2287 " %d Matched conflict early clobber reloads:"
2291 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2294 if (lra_dump_file
!= NULL
)
2295 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2296 nalt
, overall
, losers
, reload_nregs
);
2298 /* If this alternative can be made to work by reloading, and it
2299 needs less reloading than the others checked so far, record
2300 it as the chosen goal for reloading. */
2301 if ((best_losers
!= 0 && losers
== 0)
2302 || (((best_losers
== 0 && losers
== 0)
2303 || (best_losers
!= 0 && losers
!= 0))
2304 && (best_overall
> overall
2305 || (best_overall
== overall
2306 /* If the cost of the reloads is the same,
2307 prefer alternative which requires minimal
2308 number of reload regs. */
2309 && (reload_nregs
< best_reload_nregs
2310 || (reload_nregs
== best_reload_nregs
2311 && (best_reload_sum
< reload_sum
2312 || (best_reload_sum
== reload_sum
2313 && nalt
< goal_alt_number
))))))))
2315 for (nop
= 0; nop
< n_operands
; nop
++)
2317 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2318 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2319 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2320 goal_alt
[nop
] = curr_alt
[nop
];
2321 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2323 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2324 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2325 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2326 goal_alt_swapped
= curr_swapped
;
2327 best_overall
= overall
;
2328 best_losers
= losers
;
2329 best_reload_nregs
= reload_nregs
;
2330 best_reload_sum
= reload_sum
;
2331 goal_alt_number
= nalt
;
2334 /* Everything is satisfied. Do not process alternatives
2343 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2344 space AS, and check that each pseudo has the proper kind of hard
2347 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2348 rtx addr
, addr_space_t as
)
2350 #ifdef GO_IF_LEGITIMATE_ADDRESS
2351 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2352 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2358 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2362 /* Return whether address AD is valid. */
2365 valid_address_p (struct address_info
*ad
)
2367 /* Some ports do not check displacements for eliminable registers,
2368 so we replace them temporarily with the elimination target. */
2369 rtx saved_base_reg
= NULL_RTX
;
2370 rtx saved_index_reg
= NULL_RTX
;
2371 rtx
*base_term
= strip_subreg (ad
->base_term
);
2372 rtx
*index_term
= strip_subreg (ad
->index_term
);
2373 if (base_term
!= NULL
)
2375 saved_base_reg
= *base_term
;
2376 lra_eliminate_reg_if_possible (base_term
);
2377 if (ad
->base_term2
!= NULL
)
2378 *ad
->base_term2
= *ad
->base_term
;
2380 if (index_term
!= NULL
)
2382 saved_index_reg
= *index_term
;
2383 lra_eliminate_reg_if_possible (index_term
);
2385 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2386 if (saved_base_reg
!= NULL_RTX
)
2388 *base_term
= saved_base_reg
;
2389 if (ad
->base_term2
!= NULL
)
2390 *ad
->base_term2
= *ad
->base_term
;
2392 if (saved_index_reg
!= NULL_RTX
)
2393 *index_term
= saved_index_reg
;
2397 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2399 base_plus_disp_to_reg (struct address_info
*ad
)
2404 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2405 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2406 get_index_code (ad
));
2407 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2409 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2413 /* Return true if we can add a displacement to address AD, even if that
2414 makes the address invalid. The fix-up code requires any new address
2415 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2417 can_add_disp_p (struct address_info
*ad
)
2419 return (!ad
->autoinc_p
2420 && ad
->segment
== NULL
2421 && ad
->base
== ad
->base_term
2422 && ad
->disp
== ad
->disp_term
);
2425 /* Make equiv substitution in address AD. Return true if a substitution
2428 equiv_address_substitution (struct address_info
*ad
)
2430 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2431 HOST_WIDE_INT disp
, scale
;
2434 base_term
= strip_subreg (ad
->base_term
);
2435 if (base_term
== NULL
)
2436 base_reg
= new_base_reg
= NULL_RTX
;
2439 base_reg
= *base_term
;
2440 new_base_reg
= get_equiv_substitution (base_reg
);
2442 index_term
= strip_subreg (ad
->index_term
);
2443 if (index_term
== NULL
)
2444 index_reg
= new_index_reg
= NULL_RTX
;
2447 index_reg
= *index_term
;
2448 new_index_reg
= get_equiv_substitution (index_reg
);
2450 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2454 if (lra_dump_file
!= NULL
)
2456 fprintf (lra_dump_file
, "Changing address in insn %d ",
2457 INSN_UID (curr_insn
));
2458 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2460 if (base_reg
!= new_base_reg
)
2462 if (REG_P (new_base_reg
))
2464 *base_term
= new_base_reg
;
2467 else if (GET_CODE (new_base_reg
) == PLUS
2468 && REG_P (XEXP (new_base_reg
, 0))
2469 && CONST_INT_P (XEXP (new_base_reg
, 1))
2470 && can_add_disp_p (ad
))
2472 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2473 *base_term
= XEXP (new_base_reg
, 0);
2476 if (ad
->base_term2
!= NULL
)
2477 *ad
->base_term2
= *ad
->base_term
;
2479 if (index_reg
!= new_index_reg
)
2481 if (REG_P (new_index_reg
))
2483 *index_term
= new_index_reg
;
2486 else if (GET_CODE (new_index_reg
) == PLUS
2487 && REG_P (XEXP (new_index_reg
, 0))
2488 && CONST_INT_P (XEXP (new_index_reg
, 1))
2489 && can_add_disp_p (ad
)
2490 && (scale
= get_index_scale (ad
)))
2492 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2493 *index_term
= XEXP (new_index_reg
, 0);
2499 if (ad
->disp
!= NULL
)
2500 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2503 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2504 update_address (ad
);
2508 if (lra_dump_file
!= NULL
)
2511 fprintf (lra_dump_file
, " -- no change\n");
2514 fprintf (lra_dump_file
, " on equiv ");
2515 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2516 fprintf (lra_dump_file
, "\n");
2522 /* Major function to make reloads for an address in operand NOP.
2523 The supported cases are:
2525 1) an address that existed before LRA started, at which point it
2526 must have been valid. These addresses are subject to elimination
2527 and may have become invalid due to the elimination offset being out
2530 2) an address created by forcing a constant to memory
2531 (force_const_to_mem). The initial form of these addresses might
2532 not be valid, and it is this function's job to make them valid.
2534 3) a frame address formed from a register and a (possibly zero)
2535 constant offset. As above, these addresses might not be valid and
2536 this function must make them so.
2538 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2539 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2540 address. Return true for any RTL change. */
2542 process_address (int nop
, rtx
*before
, rtx
*after
)
2544 struct address_info ad
;
2546 rtx op
= *curr_id
->operand_loc
[nop
];
2547 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2550 if (constraint
[0] == 'p'
2551 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2552 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2553 else if (MEM_P (op
))
2554 decompose_mem_address (&ad
, op
);
2555 else if (GET_CODE (op
) == SUBREG
2556 && MEM_P (SUBREG_REG (op
)))
2557 decompose_mem_address (&ad
, SUBREG_REG (op
));
2560 change_p
= equiv_address_substitution (&ad
);
2561 if (ad
.base_term
!= NULL
2562 && (process_addr_reg
2563 (ad
.base_term
, before
,
2565 && !(REG_P (*ad
.base_term
)
2566 && find_regno_note (curr_insn
, REG_DEAD
,
2567 REGNO (*ad
.base_term
)) != NULL_RTX
)
2569 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2570 get_index_code (&ad
)))))
2573 if (ad
.base_term2
!= NULL
)
2574 *ad
.base_term2
= *ad
.base_term
;
2576 if (ad
.index_term
!= NULL
2577 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2580 #ifdef EXTRA_CONSTRAINT_STR
2581 /* Target hooks sometimes reject extra constraint addresses -- use
2582 EXTRA_CONSTRAINT_STR for the validation. */
2583 if (constraint
[0] != 'p'
2584 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2585 && EXTRA_CONSTRAINT_STR (op
, constraint
[0], constraint
))
2589 /* There are three cases where the shape of *AD.INNER may now be invalid:
2591 1) the original address was valid, but either elimination or
2592 equiv_address_substitution was applied and that made
2593 the address invalid.
2595 2) the address is an invalid symbolic address created by
2598 3) the address is a frame address with an invalid offset.
2600 All these cases involve a non-autoinc address, so there is no
2601 point revalidating other types. */
2602 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2605 /* Any index existed before LRA started, so we can assume that the
2606 presence and shape of the index is valid. */
2607 push_to_sequence (*before
);
2608 lra_assert (ad
.disp
== ad
.disp_term
);
2609 if (ad
.base
== NULL
)
2611 if (ad
.index
== NULL
)
2614 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2616 rtx addr
= *ad
.inner
;
2618 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2622 rtx last
= get_last_insn ();
2624 /* addr => lo_sum (new_base, addr), case (2) above. */
2625 insn
= emit_insn (gen_rtx_SET
2627 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2628 code
= recog_memoized (insn
);
2631 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2632 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2634 /* Try to put lo_sum into register. */
2635 insn
= emit_insn (gen_rtx_SET
2637 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2638 code
= recog_memoized (insn
);
2641 *ad
.inner
= new_reg
;
2642 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2652 delete_insns_since (last
);
2657 /* addr => new_base, case (2) above. */
2658 lra_emit_move (new_reg
, addr
);
2659 *ad
.inner
= new_reg
;
2664 /* index * scale + disp => new base + index * scale,
2666 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2667 GET_CODE (*ad
.index
));
2669 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2670 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2671 lra_emit_move (new_reg
, *ad
.disp
);
2672 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2673 new_reg
, *ad
.index
);
2676 else if (ad
.index
== NULL
)
2680 rtx set
, insns
, last_insn
;
2681 /* base + disp => new base, cases (1) and (3) above. */
2682 /* Another option would be to reload the displacement into an
2683 index register. However, postreload has code to optimize
2684 address reloads that have the same base and different
2685 displacements, so reloading into an index register would
2686 not necessarily be a win. */
2688 new_reg
= base_plus_disp_to_reg (&ad
);
2689 insns
= get_insns ();
2690 last_insn
= get_last_insn ();
2691 /* If we generated at least two insns, try last insn source as
2692 an address. If we succeed, we generate one less insn. */
2693 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2694 && GET_CODE (SET_SRC (set
)) == PLUS
2695 && REG_P (XEXP (SET_SRC (set
), 0))
2696 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2698 *ad
.inner
= SET_SRC (set
);
2699 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2701 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2702 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2703 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2704 get_index_code (&ad
));
2705 regno
= REGNO (*ad
.base_term
);
2706 if (regno
>= FIRST_PSEUDO_REGISTER
2707 && cl
!= lra_get_allocno_class (regno
))
2708 change_class (regno
, cl
, " Change", true);
2709 new_reg
= SET_SRC (set
);
2710 delete_insns_since (PREV_INSN (last_insn
));
2715 *ad
.inner
= new_reg
;
2719 /* base + scale * index + disp => new base + scale * index,
2721 new_reg
= base_plus_disp_to_reg (&ad
);
2722 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2723 new_reg
, *ad
.index
);
2725 *before
= get_insns ();
2730 /* Emit insns to reload VALUE into a new register. VALUE is an
2731 auto-increment or auto-decrement RTX whose operand is a register or
2732 memory location; so reloading involves incrementing that location.
2733 IN is either identical to VALUE, or some cheaper place to reload
2734 value being incremented/decremented from.
2736 INC_AMOUNT is the number to increment or decrement by (always
2737 positive and ignored for POST_MODIFY/PRE_MODIFY).
2739 Return pseudo containing the result. */
2741 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2743 /* REG or MEM to be copied and incremented. */
2744 rtx incloc
= XEXP (value
, 0);
2745 /* Nonzero if increment after copying. */
2746 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2747 || GET_CODE (value
) == POST_MODIFY
);
2752 rtx real_in
= in
== value
? incloc
: in
;
2756 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2758 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2759 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2760 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2761 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2762 inc
= XEXP (XEXP (value
, 1), 1);
2766 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2767 inc_amount
= -inc_amount
;
2769 inc
= GEN_INT (inc_amount
);
2772 if (! post
&& REG_P (incloc
))
2775 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2778 if (real_in
!= result
)
2780 /* First copy the location to the result register. */
2781 lra_assert (REG_P (result
));
2782 emit_insn (gen_move_insn (result
, real_in
));
2785 /* We suppose that there are insns to add/sub with the constant
2786 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2787 old reload worked with this assumption. If the assumption
2788 becomes wrong, we should use approach in function
2789 base_plus_disp_to_reg. */
2792 /* See if we can directly increment INCLOC. */
2793 last
= get_last_insn ();
2794 add_insn
= emit_insn (plus_p
2795 ? gen_add2_insn (incloc
, inc
)
2796 : gen_sub2_insn (incloc
, inc
));
2798 code
= recog_memoized (add_insn
);
2801 if (! post
&& result
!= incloc
)
2802 emit_insn (gen_move_insn (result
, incloc
));
2805 delete_insns_since (last
);
2808 /* If couldn't do the increment directly, must increment in RESULT.
2809 The way we do this depends on whether this is pre- or
2810 post-increment. For pre-increment, copy INCLOC to the reload
2811 register, increment it there, then save back. */
2814 if (real_in
!= result
)
2815 emit_insn (gen_move_insn (result
, real_in
));
2817 emit_insn (gen_add2_insn (result
, inc
));
2819 emit_insn (gen_sub2_insn (result
, inc
));
2820 if (result
!= incloc
)
2821 emit_insn (gen_move_insn (incloc
, result
));
2827 Because this might be a jump insn or a compare, and because
2828 RESULT may not be available after the insn in an input
2829 reload, we must do the incrementing before the insn being
2832 We have already copied IN to RESULT. Increment the copy in
2833 RESULT, save that back, then decrement RESULT so it has
2834 the original value. */
2836 emit_insn (gen_add2_insn (result
, inc
));
2838 emit_insn (gen_sub2_insn (result
, inc
));
2839 emit_insn (gen_move_insn (incloc
, result
));
2840 /* Restore non-modified value for the result. We prefer this
2841 way because it does not require an additional hard
2845 if (CONST_INT_P (inc
))
2846 emit_insn (gen_add2_insn (result
,
2847 gen_int_mode (-INTVAL (inc
),
2848 GET_MODE (result
))));
2850 emit_insn (gen_sub2_insn (result
, inc
));
2853 emit_insn (gen_add2_insn (result
, inc
));
2858 /* Return true if the current move insn does not need processing as we
2859 already know that it satisfies its constraints. */
2861 simple_move_p (void)
2864 enum reg_class dclass
, sclass
;
2866 lra_assert (curr_insn_set
!= NULL_RTX
);
2867 dest
= SET_DEST (curr_insn_set
);
2868 src
= SET_SRC (curr_insn_set
);
2869 return ((dclass
= get_op_class (dest
)) != NO_REGS
2870 && (sclass
= get_op_class (src
)) != NO_REGS
2871 /* The backend guarantees that register moves of cost 2
2872 never need reloads. */
2873 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
2876 /* Swap operands NOP and NOP + 1. */
2878 swap_operands (int nop
)
2880 enum machine_mode mode
= curr_operand_mode
[nop
];
2881 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
2882 curr_operand_mode
[nop
+ 1] = mode
;
2883 rtx x
= *curr_id
->operand_loc
[nop
];
2884 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
2885 *curr_id
->operand_loc
[nop
+ 1] = x
;
2886 /* Swap the duplicates too. */
2887 lra_update_dup (curr_id
, nop
);
2888 lra_update_dup (curr_id
, nop
+ 1);
2891 /* Main entry point of the constraint code: search the body of the
2892 current insn to choose the best alternative. It is mimicking insn
2893 alternative cost calculation model of former reload pass. That is
2894 because machine descriptions were written to use this model. This
2895 model can be changed in future. Make commutative operand exchange
2898 Return true if some RTL changes happened during function call. */
2900 curr_insn_transform (void)
2906 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
2907 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
2910 /* Flag that the insn has been changed through a transformation. */
2913 #ifdef SECONDARY_MEMORY_NEEDED
2916 int max_regno_before
;
2917 int reused_alternative_num
;
2919 curr_insn_set
= single_set (curr_insn
);
2920 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
2923 no_input_reloads_p
= no_output_reloads_p
= false;
2924 goal_alt_number
= -1;
2925 change_p
= sec_mem_p
= false;
2926 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
2927 reloads; neither are insns that SET cc0. Insns that use CC0 are
2928 not allowed to have any input reloads. */
2929 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
2930 no_output_reloads_p
= true;
2933 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
2934 no_input_reloads_p
= true;
2935 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
2936 no_output_reloads_p
= true;
2939 n_operands
= curr_static_id
->n_operands
;
2940 n_alternatives
= curr_static_id
->n_alternatives
;
2942 /* Just return "no reloads" if insn has no operands with
2944 if (n_operands
== 0 || n_alternatives
== 0)
2947 max_regno_before
= max_reg_num ();
2949 for (i
= 0; i
< n_operands
; i
++)
2951 goal_alt_matched
[i
][0] = -1;
2952 goal_alt_matches
[i
] = -1;
2955 commutative
= curr_static_id
->commutative
;
2957 /* Now see what we need for pseudos that didn't get hard regs or got
2958 the wrong kind of hard reg. For this, we must consider all the
2959 operands together against the register constraints. */
2961 best_losers
= best_overall
= INT_MAX
;
2962 best_reload_sum
= 0;
2964 curr_swapped
= false;
2965 goal_alt_swapped
= false;
2967 /* Make equivalence substitution and memory subreg elimination
2968 before address processing because an address legitimacy can
2969 depend on memory mode. */
2970 for (i
= 0; i
< n_operands
; i
++)
2972 rtx op
= *curr_id
->operand_loc
[i
];
2973 rtx subst
, old
= op
;
2974 bool op_change_p
= false;
2976 if (GET_CODE (old
) == SUBREG
)
2977 old
= SUBREG_REG (old
);
2978 subst
= get_equiv_substitution (old
);
2981 subst
= copy_rtx (subst
);
2982 lra_assert (REG_P (old
));
2983 if (GET_CODE (op
) == SUBREG
)
2984 SUBREG_REG (op
) = subst
;
2986 *curr_id
->operand_loc
[i
] = subst
;
2987 if (lra_dump_file
!= NULL
)
2989 fprintf (lra_dump_file
,
2990 "Changing pseudo %d in operand %i of insn %u on equiv ",
2991 REGNO (old
), i
, INSN_UID (curr_insn
));
2992 dump_value_slim (lra_dump_file
, subst
, 1);
2993 fprintf (lra_dump_file
, "\n");
2995 op_change_p
= change_p
= true;
2997 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3000 lra_update_dup (curr_id
, i
);
3004 /* Reload address registers and displacements. We do it before
3005 finding an alternative because of memory constraints. */
3006 before
= after
= NULL_RTX
;
3007 for (i
= 0; i
< n_operands
; i
++)
3008 if (! curr_static_id
->operand
[i
].is_operator
3009 && process_address (i
, &before
, &after
))
3012 lra_update_dup (curr_id
, i
);
3016 /* If we've changed the instruction then any alternative that
3017 we chose previously may no longer be valid. */
3018 lra_set_used_insn_alternative (curr_insn
, -1);
3020 if (curr_insn_set
!= NULL_RTX
3021 && check_and_process_move (&change_p
, &sec_mem_p
))
3026 reused_alternative_num
= curr_id
->used_insn_alternative
;
3027 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3028 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3029 reused_alternative_num
, INSN_UID (curr_insn
));
3031 if (process_alt_operands (reused_alternative_num
))
3034 /* If insn is commutative (it's safe to exchange a certain pair of
3035 operands) then we need to try each alternative twice, the second
3036 time matching those two operands as if we had exchanged them. To
3037 do this, really exchange them in operands.
3039 If we have just tried the alternatives the second time, return
3040 operands to normal and drop through. */
3042 if (reused_alternative_num
< 0 && commutative
>= 0)
3044 curr_swapped
= !curr_swapped
;
3047 swap_operands (commutative
);
3051 swap_operands (commutative
);
3054 if (! alt_p
&& ! sec_mem_p
)
3056 /* No alternative works with reloads?? */
3057 if (INSN_CODE (curr_insn
) >= 0)
3058 fatal_insn ("unable to generate reloads for:", curr_insn
);
3059 error_for_asm (curr_insn
,
3060 "inconsistent operand constraints in an %<asm%>");
3061 /* Avoid further trouble with this insn. */
3062 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3063 lra_invalidate_insn_data (curr_insn
);
3067 /* If the best alternative is with operands 1 and 2 swapped, swap
3068 them. Update the operand numbers of any reloads already
3071 if (goal_alt_swapped
)
3073 if (lra_dump_file
!= NULL
)
3074 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3075 INSN_UID (curr_insn
));
3077 /* Swap the duplicates too. */
3078 swap_operands (commutative
);
3082 #ifdef SECONDARY_MEMORY_NEEDED
3083 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3084 too conservatively. So we use the secondary memory only if there
3085 is no any alternative without reloads. */
3086 use_sec_mem_p
= false;
3088 use_sec_mem_p
= true;
3091 for (i
= 0; i
< n_operands
; i
++)
3092 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3094 use_sec_mem_p
= i
< n_operands
;
3099 rtx new_reg
, src
, dest
, rld
;
3100 enum machine_mode sec_mode
, rld_mode
;
3102 lra_assert (sec_mem_p
);
3103 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3104 && curr_static_id
->operand
[1].type
== OP_IN
);
3105 dest
= *curr_id
->operand_loc
[0];
3106 src
= *curr_id
->operand_loc
[1];
3107 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3109 rld_mode
= GET_MODE (rld
);
3110 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3111 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3113 sec_mode
= rld_mode
;
3115 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3116 NO_REGS
, "secondary");
3117 /* If the mode is changed, it should be wider. */
3118 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3119 if (sec_mode
!= rld_mode
)
3121 /* If the target says specifically to use another mode for
3122 secondary memory moves we can not reuse the original
3124 after
= emit_spill_move (false, new_reg
, dest
);
3125 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3126 "Inserting the sec. move");
3127 /* We may have non null BEFORE here (e.g. after address
3129 push_to_sequence (before
);
3130 before
= emit_spill_move (true, new_reg
, src
);
3132 before
= get_insns ();
3134 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3135 lra_set_insn_deleted (curr_insn
);
3137 else if (dest
== rld
)
3139 *curr_id
->operand_loc
[0] = new_reg
;
3140 after
= emit_spill_move (false, new_reg
, dest
);
3141 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3142 "Inserting the sec. move");
3146 *curr_id
->operand_loc
[1] = new_reg
;
3147 /* See comments above. */
3148 push_to_sequence (before
);
3149 before
= emit_spill_move (true, new_reg
, src
);
3151 before
= get_insns ();
3153 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3154 "Inserting the sec. move");
3156 lra_update_insn_regno_info (curr_insn
);
3161 lra_assert (goal_alt_number
>= 0);
3162 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3164 if (lra_dump_file
!= NULL
)
3168 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3169 goal_alt_number
, INSN_UID (curr_insn
));
3170 for (i
= 0; i
< n_operands
; i
++)
3172 p
= (curr_static_id
->operand_alternative
3173 [goal_alt_number
* n_operands
+ i
].constraint
);
3176 fprintf (lra_dump_file
, " (%d) ", i
);
3177 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3178 fputc (*p
, lra_dump_file
);
3180 if (INSN_CODE (curr_insn
) >= 0
3181 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3182 fprintf (lra_dump_file
, " {%s}", p
);
3183 fprintf (lra_dump_file
, "\n");
3186 /* Right now, for any pair of operands I and J that are required to
3187 match, with J < I, goal_alt_matches[I] is J. Add I to
3188 goal_alt_matched[J]. */
3190 for (i
= 0; i
< n_operands
; i
++)
3191 if ((j
= goal_alt_matches
[i
]) >= 0)
3193 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3195 /* We allow matching one output operand and several input
3198 || (curr_static_id
->operand
[j
].type
== OP_OUT
3199 && curr_static_id
->operand
[i
].type
== OP_IN
3200 && (curr_static_id
->operand
3201 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3202 goal_alt_matched
[j
][k
] = i
;
3203 goal_alt_matched
[j
][k
+ 1] = -1;
3206 for (i
= 0; i
< n_operands
; i
++)
3207 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3209 /* Any constants that aren't allowed and can't be reloaded into
3210 registers are here changed into memory references. */
3211 for (i
= 0; i
< n_operands
; i
++)
3212 if (goal_alt_win
[i
])
3215 enum reg_class new_class
;
3216 rtx reg
= *curr_id
->operand_loc
[i
];
3218 if (GET_CODE (reg
) == SUBREG
)
3219 reg
= SUBREG_REG (reg
);
3221 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3223 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3225 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3228 change_class (regno
, new_class
, " Change", true);
3234 const char *constraint
;
3236 rtx op
= *curr_id
->operand_loc
[i
];
3237 rtx subreg
= NULL_RTX
;
3238 enum machine_mode mode
= curr_operand_mode
[i
];
3240 if (GET_CODE (op
) == SUBREG
)
3243 op
= SUBREG_REG (op
);
3244 mode
= GET_MODE (op
);
3247 if (CONST_POOL_OK_P (mode
, op
)
3248 && ((targetm
.preferred_reload_class
3249 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3250 || no_input_reloads_p
))
3252 rtx tem
= force_const_mem (mode
, op
);
3255 if (subreg
!= NULL_RTX
)
3256 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3258 *curr_id
->operand_loc
[i
] = tem
;
3259 lra_update_dup (curr_id
, i
);
3260 process_address (i
, &before
, &after
);
3262 /* If the alternative accepts constant pool refs directly
3263 there will be no reload needed at all. */
3264 if (subreg
!= NULL_RTX
)
3266 /* Skip alternatives before the one requested. */
3267 constraint
= (curr_static_id
->operand_alternative
3268 [goal_alt_number
* n_operands
+ i
].constraint
);
3270 (c
= *constraint
) && c
!= ',' && c
!= '#';
3271 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3273 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3275 #ifdef EXTRA_CONSTRAINT_STR
3276 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3277 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3281 if (c
== '\0' || c
== ',' || c
== '#')
3284 goal_alt_win
[i
] = true;
3288 for (i
= 0; i
< n_operands
; i
++)
3291 bool optional_p
= false;
3293 rtx op
= *curr_id
->operand_loc
[i
];
3295 if (goal_alt_win
[i
])
3297 if (goal_alt
[i
] == NO_REGS
3299 /* When we assign NO_REGS it means that we will not
3300 assign a hard register to the scratch pseudo by
3301 assigment pass and the scratch pseudo will be
3302 spilled. Spilled scratch pseudos are transformed
3303 back to scratches at the LRA end. */
3304 && lra_former_scratch_operand_p (curr_insn
, i
))
3306 int regno
= REGNO (op
);
3307 change_class (regno
, NO_REGS
, " Change", true);
3308 if (lra_get_regno_hard_regno (regno
) >= 0)
3309 /* We don't have to mark all insn affected by the
3310 spilled pseudo as there is only one such insn, the
3312 reg_renumber
[regno
] = -1;
3314 /* We can do an optional reload. If the pseudo got a hard
3315 reg, we might improve the code through inheritance. If
3316 it does not get a hard register we coalesce memory/memory
3317 moves later. Ignore move insns to avoid cycling. */
3319 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3320 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3321 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3322 && ! lra_former_scratch_p (regno
)
3323 && reg_renumber
[regno
] < 0
3324 && (curr_insn_set
== NULL_RTX
3325 || !((REG_P (SET_SRC (curr_insn_set
))
3326 || MEM_P (SET_SRC (curr_insn_set
))
3327 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3328 && (REG_P (SET_DEST (curr_insn_set
))
3329 || MEM_P (SET_DEST (curr_insn_set
))
3330 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3336 /* Operands that match previous ones have already been handled. */
3337 if (goal_alt_matches
[i
] >= 0)
3340 /* We should not have an operand with a non-offsettable address
3341 appearing where an offsettable address will do. It also may
3342 be a case when the address should be special in other words
3343 not a general one (e.g. it needs no index reg). */
3344 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3346 enum reg_class rclass
;
3347 rtx
*loc
= &XEXP (op
, 0);
3348 enum rtx_code code
= GET_CODE (*loc
);
3350 push_to_sequence (before
);
3351 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3353 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3354 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3355 /* This value does not matter for MODIFY. */
3356 GET_MODE_SIZE (GET_MODE (op
)));
3357 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
3358 "offsetable address", &new_reg
))
3359 lra_emit_move (new_reg
, *loc
);
3360 before
= get_insns ();
3363 lra_update_dup (curr_id
, i
);
3365 else if (goal_alt_matched
[i
][0] == -1)
3367 enum machine_mode mode
;
3369 int hard_regno
, byte
;
3370 enum op_type type
= curr_static_id
->operand
[i
].type
;
3372 loc
= curr_id
->operand_loc
[i
];
3373 mode
= curr_operand_mode
[i
];
3374 if (GET_CODE (*loc
) == SUBREG
)
3376 reg
= SUBREG_REG (*loc
);
3377 byte
= SUBREG_BYTE (*loc
);
3379 /* Strict_low_part requires reload the register not
3380 the sub-register. */
3381 && (curr_static_id
->operand
[i
].strict_low
3382 || (GET_MODE_SIZE (mode
)
3383 <= GET_MODE_SIZE (GET_MODE (reg
))
3385 = get_try_hard_regno (REGNO (reg
))) >= 0
3386 && (simplify_subreg_regno
3388 GET_MODE (reg
), byte
, mode
) < 0)
3389 && (goal_alt
[i
] == NO_REGS
3390 || (simplify_subreg_regno
3391 (ira_class_hard_regs
[goal_alt
[i
]][0],
3392 GET_MODE (reg
), byte
, mode
) >= 0)))))
3394 loc
= &SUBREG_REG (*loc
);
3395 mode
= GET_MODE (*loc
);
3399 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3402 push_to_sequence (before
);
3403 lra_emit_move (new_reg
, old
);
3404 before
= get_insns ();
3409 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3412 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3414 after
= get_insns ();
3418 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3419 if (goal_alt_dont_inherit_ops
[j
] == i
)
3421 lra_set_regno_unique_value (REGNO (new_reg
));
3424 lra_update_dup (curr_id
, i
);
3426 else if (curr_static_id
->operand
[i
].type
== OP_IN
3427 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3430 /* generate reloads for input and matched outputs. */
3431 match_inputs
[0] = i
;
3432 match_inputs
[1] = -1;
3433 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3434 goal_alt
[i
], &before
, &after
);
3436 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3437 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3439 /* Generate reloads for output and matched inputs. */
3440 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3441 else if (curr_static_id
->operand
[i
].type
== OP_IN
3442 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3445 /* Generate reloads for matched inputs. */
3446 match_inputs
[0] = i
;
3447 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3448 match_inputs
[j
+ 1] = k
;
3449 match_inputs
[j
+ 1] = -1;
3450 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3453 /* We must generate code in any case when function
3454 process_alt_operands decides that it is possible. */
3458 lra_assert (REG_P (op
));
3460 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3461 if (GET_CODE (op
) == SUBREG
)
3462 op
= SUBREG_REG (op
);
3463 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3464 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3465 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3466 if (lra_dump_file
!= NULL
)
3467 fprintf (lra_dump_file
,
3468 " Making reload reg %d for reg %d optional\n",
3472 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3473 || max_regno_before
!= max_reg_num ())
3477 lra_update_operator_dups (curr_id
);
3478 /* Something changes -- process the insn. */
3479 lra_update_insn_regno_info (curr_insn
);
3481 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3485 /* Return true if X is in LIST. */
3487 in_list_p (rtx x
, rtx list
)
3489 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3490 if (XEXP (list
, 0) == x
)
3495 /* Return true if X contains an allocatable hard register (if
3496 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3498 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3504 code
= GET_CODE (x
);
3507 int regno
= REGNO (x
);
3508 HARD_REG_SET alloc_regs
;
3512 if (regno
>= FIRST_PSEUDO_REGISTER
)
3513 regno
= lra_get_regno_hard_regno (regno
);
3516 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3517 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3521 if (regno
< FIRST_PSEUDO_REGISTER
)
3525 return lra_get_regno_hard_regno (regno
) < 0;
3528 fmt
= GET_RTX_FORMAT (code
);
3529 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3533 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3536 else if (fmt
[i
] == 'E')
3538 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3539 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3546 /* Process all regs in location *LOC and change them on equivalent
3547 substitution. Return true if any change was done. */
3549 loc_equivalence_change_p (rtx
*loc
)
3551 rtx subst
, reg
, x
= *loc
;
3552 bool result
= false;
3553 enum rtx_code code
= GET_CODE (x
);
3559 reg
= SUBREG_REG (x
);
3560 if ((subst
= get_equiv_substitution (reg
)) != reg
3561 && GET_MODE (subst
) == VOIDmode
)
3563 /* We cannot reload debug location. Simplify subreg here
3564 while we know the inner mode. */
3565 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3566 GET_MODE (reg
), SUBREG_BYTE (x
));
3570 if (code
== REG
&& (subst
= get_equiv_substitution (x
)) != x
)
3576 /* Scan all the operand sub-expressions. */
3577 fmt
= GET_RTX_FORMAT (code
);
3578 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3581 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3582 else if (fmt
[i
] == 'E')
3583 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3585 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3590 /* Similar to loc_equivalence_change_p, but for use as
3591 simplify_replace_fn_rtx callback. */
3593 loc_equivalence_callback (rtx loc
, const_rtx
, void *)
3598 rtx subst
= get_equiv_substitution (loc
);
3605 /* Maximum number of generated reload insns per an insn. It is for
3606 preventing this pass cycling in a bug case. */
3607 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3609 /* The current iteration number of this LRA pass. */
3610 int lra_constraint_iter
;
3612 /* The current iteration number of this LRA pass after the last spill
3614 int lra_constraint_iter_after_spill
;
3616 /* True if we substituted equiv which needs checking register
3617 allocation correctness because the equivalent value contains
3618 allocatable hard registers or when we restore multi-register
3620 bool lra_risky_transformations_p
;
3622 /* Return true if REGNO is referenced in more than one block. */
3624 multi_block_pseudo_p (int regno
)
3626 basic_block bb
= NULL
;
3630 if (regno
< FIRST_PSEUDO_REGISTER
)
3633 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3635 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3636 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3641 /* Return true if LIST contains a deleted insn. */
3643 contains_deleted_insn_p (rtx list
)
3645 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3646 if (NOTE_P (XEXP (list
, 0))
3647 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3652 /* Return true if X contains a pseudo dying in INSN. */
3654 dead_pseudo_p (rtx x
, rtx insn
)
3661 return (insn
!= NULL_RTX
3662 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3663 code
= GET_CODE (x
);
3664 fmt
= GET_RTX_FORMAT (code
);
3665 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3669 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3672 else if (fmt
[i
] == 'E')
3674 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3675 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3682 /* Return true if INSN contains a dying pseudo in INSN right hand
3685 insn_rhs_dead_pseudo_p (rtx insn
)
3687 rtx set
= single_set (insn
);
3689 gcc_assert (set
!= NULL
);
3690 return dead_pseudo_p (SET_SRC (set
), insn
);
3693 /* Return true if any init insn of REGNO contains a dying pseudo in
3694 insn right hand side. */
3696 init_insn_rhs_dead_pseudo_p (int regno
)
3698 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3703 return insn_rhs_dead_pseudo_p (insns
);
3704 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3705 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3710 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3711 reverse only if we have one init insn with given REGNO as a
3714 reverse_equiv_p (int regno
)
3718 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3720 if (! INSN_P (XEXP (insns
, 0))
3721 || XEXP (insns
, 1) != NULL_RTX
)
3723 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3725 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3728 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3729 call this function only for non-reverse equivalence. */
3731 contains_reloaded_insn_p (int regno
)
3734 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3736 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3737 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3738 || ! REG_P (SET_DEST (set
))
3739 || (int) REGNO (SET_DEST (set
)) != regno
)
3744 /* Entry function of LRA constraint pass. Return true if the
3745 constraint pass did change the code. */
3747 lra_constraints (bool first_p
)
3750 int i
, hard_regno
, new_insns_num
;
3751 unsigned int min_len
, new_min_len
, uid
;
3752 rtx set
, x
, reg
, dest_reg
;
3753 basic_block last_bb
;
3754 bitmap_head equiv_insn_bitmap
;
3757 lra_constraint_iter
++;
3758 if (lra_dump_file
!= NULL
)
3759 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3760 lra_constraint_iter
);
3761 lra_constraint_iter_after_spill
++;
3762 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3764 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3765 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3767 lra_risky_transformations_p
= false;
3768 new_insn_uid_start
= get_max_uid ();
3769 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3770 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3771 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3772 if (lra_reg_info
[i
].nrefs
!= 0)
3774 ira_reg_equiv
[i
].profitable_p
= true;
3775 reg
= regno_reg_rtx
[i
];
3776 if ((hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3780 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3781 for (j
= 0; j
< nregs
; j
++)
3782 df_set_regs_ever_live (hard_regno
+ j
, true);
3784 else if ((x
= get_equiv_substitution (reg
)) != reg
)
3786 bool pseudo_p
= contains_reg_p (x
, false, false);
3788 /* After RTL transformation, we can not guarantee that
3789 pseudo in the substitution was not reloaded which might
3790 make equivalence invalid. For example, in reverse
3797 the memory address register was reloaded before the 2nd
3799 if ((! first_p
&& pseudo_p
)
3800 /* We don't use DF for compilation speed sake. So it
3801 is problematic to update live info when we use an
3802 equivalence containing pseudos in more than one
3804 || (pseudo_p
&& multi_block_pseudo_p (i
))
3805 /* If an init insn was deleted for some reason, cancel
3806 the equiv. We could update the equiv insns after
3807 transformations including an equiv insn deletion
3808 but it is not worthy as such cases are extremely
3810 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
3811 /* If it is not a reverse equivalence, we check that a
3812 pseudo in rhs of the init insn is not dying in the
3813 insn. Otherwise, the live info at the beginning of
3814 the corresponding BB might be wrong after we
3815 removed the insn. When the equiv can be a
3816 constant, the right hand side of the init insn can
3818 || (! reverse_equiv_p (i
)
3819 && (init_insn_rhs_dead_pseudo_p (i
)
3820 /* If we reloaded the pseudo in an equivalence
3821 init insn, we can not remove the equiv init
3822 insns and the init insns might write into
3823 const memory in this case. */
3824 || contains_reloaded_insn_p (i
)))
3825 /* Prevent access beyond equivalent memory for
3826 paradoxical subregs. */
3828 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
3829 > GET_MODE_SIZE (GET_MODE (x
)))))
3830 ira_reg_equiv
[i
].defined_p
= false;
3831 if (contains_reg_p (x
, false, true))
3832 ira_reg_equiv
[i
].profitable_p
= false;
3833 if (get_equiv_substitution (reg
) != reg
)
3834 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
3837 /* We should add all insns containing pseudos which should be
3838 substituted by their equivalences. */
3839 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
3840 lra_push_insn_by_uid (uid
);
3841 lra_eliminate (false);
3842 min_len
= lra_insn_stack_length ();
3846 while ((new_min_len
= lra_insn_stack_length ()) != 0)
3848 curr_insn
= lra_pop_insn ();
3850 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
3851 if (curr_bb
!= last_bb
)
3854 bb_reload_num
= lra_curr_reload_num
;
3856 if (min_len
> new_min_len
)
3858 min_len
= new_min_len
;
3861 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
3863 ("Max. number of generated reload insns per insn is achieved (%d)\n",
3864 MAX_RELOAD_INSNS_NUMBER
);
3866 if (DEBUG_INSN_P (curr_insn
))
3868 /* We need to check equivalence in debug insn and change
3869 pseudo to the equivalent value if necessary. */
3870 curr_id
= lra_get_insn_recog_data (curr_insn
);
3871 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
3873 rtx old
= *curr_id
->operand_loc
[0];
3874 *curr_id
->operand_loc
[0]
3875 = simplify_replace_fn_rtx (old
, NULL_RTX
,
3876 loc_equivalence_callback
, NULL
);
3877 if (old
!= *curr_id
->operand_loc
[0])
3879 lra_update_insn_regno_info (curr_insn
);
3884 else if (INSN_P (curr_insn
))
3886 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
3888 dest_reg
= SET_DEST (set
);
3889 /* The equivalence pseudo could be set up as SUBREG in a
3890 case when it is a call restore insn in a mode
3891 different from the pseudo mode. */
3892 if (GET_CODE (dest_reg
) == SUBREG
)
3893 dest_reg
= SUBREG_REG (dest_reg
);
3894 if ((REG_P (dest_reg
)
3895 && (x
= get_equiv_substitution (dest_reg
)) != dest_reg
3896 /* Check that this is actually an insn setting up
3898 && (in_list_p (curr_insn
,
3900 [REGNO (dest_reg
)].init_insns
)
3901 /* Init insns may contain not all insns setting
3902 up equivalence as we have live range
3903 splitting. So here we use another condition
3904 to check insn setting up the equivalence
3905 which should be removed, e.g. in case when
3906 the equivalence is a constant. */
3908 /* Remove insns which set up a pseudo whose value
3909 can not be changed. Such insns might be not in
3910 init_insns because we don't update equiv data
3911 during insn transformations.
3913 As an example, let suppose that a pseudo got
3914 hard register and on the 1st pass was not
3915 changed to equivalent constant. We generate an
3916 additional insn setting up the pseudo because of
3917 secondary memory movement. Then the pseudo is
3918 spilled and we use the equiv constant. In this
3919 case we should remove the additional insn and
3920 this insn is not init_insns list. */
3921 && (! MEM_P (x
) || MEM_READONLY_P (x
)
3922 || in_list_p (curr_insn
,
3924 [REGNO (dest_reg
)].init_insns
)))
3925 || (((x
= get_equiv_substitution (SET_SRC (set
)))
3927 && in_list_p (curr_insn
,
3929 [REGNO (SET_SRC (set
))].init_insns
)))
3931 /* This is equiv init insn of pseudo which did not get a
3932 hard register -- remove the insn. */
3933 if (lra_dump_file
!= NULL
)
3935 fprintf (lra_dump_file
,
3936 " Removing equiv init insn %i (freq=%d)\n",
3937 INSN_UID (curr_insn
),
3938 BLOCK_FOR_INSN (curr_insn
)->frequency
);
3939 dump_insn_slim (lra_dump_file
, curr_insn
);
3941 if (contains_reg_p (x
, true, false))
3942 lra_risky_transformations_p
= true;
3943 lra_set_insn_deleted (curr_insn
);
3947 curr_id
= lra_get_insn_recog_data (curr_insn
);
3948 curr_static_id
= curr_id
->insn_static_data
;
3949 init_curr_insn_input_reloads ();
3950 init_curr_operand_mode ();
3951 if (curr_insn_transform ())
3953 /* Check non-transformed insns too for equiv change as USE
3954 or CLOBBER don't need reloads but can contain pseudos
3955 being changed on their equivalences. */
3956 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
3957 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
3959 lra_update_insn_regno_info (curr_insn
);
3964 bitmap_clear (&equiv_insn_bitmap
);
3965 /* If we used a new hard regno, changed_p should be true because the
3966 hard reg is assigned to a new pseudo. */
3967 #ifdef ENABLE_CHECKING
3970 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3971 if (lra_reg_info
[i
].nrefs
!= 0
3972 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3974 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3976 for (j
= 0; j
< nregs
; j
++)
3977 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
3984 /* Initiate the LRA constraint pass. It is done once per
3987 lra_constraints_init (void)
3991 /* Finalize the LRA constraint pass. It is done once per
3994 lra_constraints_finish (void)
4000 /* This page contains code to do inheritance/split
4003 /* Number of reloads passed so far in current EBB. */
4004 static int reloads_num
;
4006 /* Number of calls passed so far in current EBB. */
4007 static int calls_num
;
4009 /* Current reload pseudo check for validity of elements in
4011 static int curr_usage_insns_check
;
4013 /* Info about last usage of registers in EBB to do inheritance/split
4014 transformation. Inheritance transformation is done from a spilled
4015 pseudo and split transformations from a hard register or a pseudo
4016 assigned to a hard register. */
4019 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4020 value INSNS is valid. The insns is chain of optional debug insns
4021 and a finishing non-debug insn using the corresponding reg. The
4022 value is also used to mark the registers which are set up in the
4023 current insn. The negated insn uid is used for this. */
4025 /* Value of global reloads_num at the last insn in INSNS. */
4027 /* Value of global reloads_nums at the last insn in INSNS. */
4029 /* It can be true only for splitting. And it means that the restore
4030 insn should be put after insn given by the following member. */
4032 /* Next insns in the current EBB which use the original reg and the
4033 original reg value is not changed between the current insn and
4034 the next insns. In order words, e.g. for inheritance, if we need
4035 to use the original reg value again in the next insns we can try
4036 to use the value in a hard register from a reload insn of the
4041 /* Map: regno -> corresponding pseudo usage insns. */
4042 static struct usage_insns
*usage_insns
;
4045 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4047 usage_insns
[regno
].check
= curr_usage_insns_check
;
4048 usage_insns
[regno
].insns
= insn
;
4049 usage_insns
[regno
].reloads_num
= reloads_num
;
4050 usage_insns
[regno
].calls_num
= calls_num
;
4051 usage_insns
[regno
].after_p
= after_p
;
4054 /* The function is used to form list REGNO usages which consists of
4055 optional debug insns finished by a non-debug insn using REGNO.
4056 RELOADS_NUM is current number of reload insns processed so far. */
4058 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4060 rtx next_usage_insns
;
4062 if (usage_insns
[regno
].check
== curr_usage_insns_check
4063 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4064 && DEBUG_INSN_P (insn
))
4066 /* Check that we did not add the debug insn yet. */
4067 if (next_usage_insns
!= insn
4068 && (GET_CODE (next_usage_insns
) != INSN_LIST
4069 || XEXP (next_usage_insns
, 0) != insn
))
4070 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4073 else if (NONDEBUG_INSN_P (insn
))
4074 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4076 usage_insns
[regno
].check
= 0;
4079 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4080 register NEW_REG. Return true if any change was made. */
4082 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4085 bool result
= false;
4093 code
= GET_CODE (x
);
4094 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4096 enum machine_mode mode
= GET_MODE (*loc
);
4097 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4099 if (mode
!= inner_mode
)
4101 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4102 || ! SCALAR_INT_MODE_P (inner_mode
))
4103 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4105 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4111 /* Scan all the operand sub-expressions. */
4112 fmt
= GET_RTX_FORMAT (code
);
4113 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4117 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4120 else if (fmt
[i
] == 'E')
4122 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4123 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4130 /* Return first non-debug insn in list USAGE_INSNS. */
4132 skip_usage_debug_insns (rtx usage_insns
)
4136 /* Skip debug insns. */
4137 for (insn
= usage_insns
;
4138 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4139 insn
= XEXP (insn
, 1))
4144 /* Return true if we need secondary memory moves for insn in
4145 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4148 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4149 rtx usage_insns ATTRIBUTE_UNUSED
)
4151 #ifndef SECONDARY_MEMORY_NEEDED
4154 rtx insn
, set
, dest
;
4157 if (inher_cl
== ALL_REGS
4158 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4160 lra_assert (INSN_P (insn
));
4161 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4163 dest
= SET_DEST (set
);
4166 lra_assert (inher_cl
!= NO_REGS
);
4167 cl
= get_reg_class (REGNO (dest
));
4168 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4169 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4173 /* Registers involved in inheritance/split in the current EBB
4174 (inheritance/split pseudos and original registers). */
4175 static bitmap_head check_only_regs
;
4177 /* Do inheritance transformations for insn INSN, which defines (if
4178 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4179 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4180 form as the "insns" field of usage_insns. Return true if we
4181 succeed in such transformation.
4183 The transformations look like:
4186 ... p <- i (new insn)
4188 <- ... p ... <- ... i ...
4190 ... i <- p (new insn)
4191 <- ... p ... <- ... i ...
4193 <- ... p ... <- ... i ...
4194 where p is a spilled original pseudo and i is a new inheritance pseudo.
4197 The inheritance pseudo has the smallest class of two classes CL and
4198 class of ORIGINAL REGNO. */
4200 inherit_reload_reg (bool def_p
, int original_regno
,
4201 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4203 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4204 rtx original_reg
= regno_reg_rtx
[original_regno
];
4205 rtx new_reg
, new_insns
, usage_insn
;
4207 lra_assert (! usage_insns
[original_regno
].after_p
);
4208 if (lra_dump_file
!= NULL
)
4209 fprintf (lra_dump_file
,
4210 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4211 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4213 if (lra_dump_file
!= NULL
)
4215 fprintf (lra_dump_file
,
4216 " Rejecting inheritance for %d "
4217 "because of disjoint classes %s and %s\n",
4218 original_regno
, reg_class_names
[cl
],
4219 reg_class_names
[rclass
]);
4220 fprintf (lra_dump_file
,
4221 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4225 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4226 /* We don't use a subset of two classes because it can be
4227 NO_REGS. This transformation is still profitable in most
4228 cases even if the classes are not intersected as register
4229 move is probably cheaper than a memory load. */
4230 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4232 if (lra_dump_file
!= NULL
)
4233 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4234 reg_class_names
[cl
], reg_class_names
[rclass
]);
4238 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4240 /* Reject inheritance resulting in secondary memory moves.
4241 Otherwise, there is a danger in LRA cycling. Also such
4242 transformation will be unprofitable. */
4243 if (lra_dump_file
!= NULL
)
4245 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4246 rtx set
= single_set (insn
);
4248 lra_assert (set
!= NULL_RTX
);
4250 rtx dest
= SET_DEST (set
);
4252 lra_assert (REG_P (dest
));
4253 fprintf (lra_dump_file
,
4254 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4255 "as secondary mem is needed\n",
4256 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4257 original_regno
, reg_class_names
[rclass
]);
4258 fprintf (lra_dump_file
,
4259 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4263 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4264 rclass
, "inheritance");
4267 emit_move_insn (original_reg
, new_reg
);
4269 emit_move_insn (new_reg
, original_reg
);
4270 new_insns
= get_insns ();
4272 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4274 if (lra_dump_file
!= NULL
)
4276 fprintf (lra_dump_file
,
4277 " Rejecting inheritance %d->%d "
4278 "as it results in 2 or more insns:\n",
4279 original_regno
, REGNO (new_reg
));
4280 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4281 fprintf (lra_dump_file
,
4282 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4286 substitute_pseudo (&insn
, original_regno
, new_reg
);
4287 lra_update_insn_regno_info (insn
);
4289 /* We now have a new usage insn for original regno. */
4290 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4291 if (lra_dump_file
!= NULL
)
4292 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4293 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4294 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4295 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4296 bitmap_set_bit (&check_only_regs
, original_regno
);
4297 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4299 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4300 "Add original<-inheritance");
4302 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4303 "Add inheritance<-original");
4304 while (next_usage_insns
!= NULL_RTX
)
4306 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4308 usage_insn
= next_usage_insns
;
4309 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4310 next_usage_insns
= NULL
;
4314 usage_insn
= XEXP (next_usage_insns
, 0);
4315 lra_assert (DEBUG_INSN_P (usage_insn
));
4316 next_usage_insns
= XEXP (next_usage_insns
, 1);
4318 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4319 lra_update_insn_regno_info (usage_insn
);
4320 if (lra_dump_file
!= NULL
)
4322 fprintf (lra_dump_file
,
4323 " Inheritance reuse change %d->%d (bb%d):\n",
4324 original_regno
, REGNO (new_reg
),
4325 BLOCK_FOR_INSN (usage_insn
)->index
);
4326 dump_insn_slim (lra_dump_file
, usage_insn
);
4329 if (lra_dump_file
!= NULL
)
4330 fprintf (lra_dump_file
,
4331 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4335 /* Return true if we need a caller save/restore for pseudo REGNO which
4336 was assigned to a hard register. */
4338 need_for_call_save_p (int regno
)
4340 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4341 return (usage_insns
[regno
].calls_num
< calls_num
4342 && (overlaps_hard_reg_set_p
4344 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4345 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4346 PSEUDO_REGNO_MODE (regno
))));
4349 /* Global registers occurring in the current EBB. */
4350 static bitmap_head ebb_global_regs
;
4352 /* Return true if we need a split for hard register REGNO or pseudo
4353 REGNO which was assigned to a hard register.
4354 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4355 used for reloads since the EBB end. It is an approximation of the
4356 used hard registers in the split range. The exact value would
4357 require expensive calculations. If we were aggressive with
4358 splitting because of the approximation, the split pseudo will save
4359 the same hard register assignment and will be removed in the undo
4360 pass. We still need the approximation because too aggressive
4361 splitting would result in too inaccurate cost calculation in the
4362 assignment pass because of too many generated moves which will be
4363 probably removed in the undo pass. */
4365 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4367 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4369 lra_assert (hard_regno
>= 0);
4370 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4371 /* Don't split eliminable hard registers, otherwise we can
4372 split hard registers like hard frame pointer, which
4373 lives on BB start/end according to DF-infrastructure,
4374 when there is a pseudo assigned to the register and
4375 living in the same BB. */
4376 && (regno
>= FIRST_PSEUDO_REGISTER
4377 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4378 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4379 /* Don't split call clobbered hard regs living through
4380 calls, otherwise we might have a check problem in the
4381 assign sub-pass as in the most cases (exception is a
4382 situation when lra_risky_transformations_p value is
4383 true) the assign pass assumes that all pseudos living
4384 through calls are assigned to call saved hard regs. */
4385 && (regno
>= FIRST_PSEUDO_REGISTER
4386 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4387 || usage_insns
[regno
].calls_num
== calls_num
)
4388 /* We need at least 2 reloads to make pseudo splitting
4389 profitable. We should provide hard regno splitting in
4390 any case to solve 1st insn scheduling problem when
4391 moving hard register definition up might result in
4392 impossibility to find hard register for reload pseudo of
4393 small register class. */
4394 && (usage_insns
[regno
].reloads_num
4395 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
4396 && (regno
< FIRST_PSEUDO_REGISTER
4397 /* For short living pseudos, spilling + inheritance can
4398 be considered a substitution for splitting.
4399 Therefore we do not splitting for local pseudos. It
4400 decreases also aggressiveness of splitting. The
4401 minimal number of references is chosen taking into
4402 account that for 2 references splitting has no sense
4403 as we can just spill the pseudo. */
4404 || (regno
>= FIRST_PSEUDO_REGISTER
4405 && lra_reg_info
[regno
].nrefs
> 3
4406 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4407 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4410 /* Return class for the split pseudo created from original pseudo with
4411 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4412 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4413 results in no secondary memory movements. */
4414 static enum reg_class
4415 choose_split_class (enum reg_class allocno_class
,
4416 int hard_regno ATTRIBUTE_UNUSED
,
4417 enum machine_mode mode ATTRIBUTE_UNUSED
)
4419 #ifndef SECONDARY_MEMORY_NEEDED
4420 return allocno_class
;
4423 enum reg_class cl
, best_cl
= NO_REGS
;
4424 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4425 = REGNO_REG_CLASS (hard_regno
);
4427 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4428 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4429 return allocno_class
;
4431 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4433 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4434 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4435 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4436 && (best_cl
== NO_REGS
4437 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4443 /* Do split transformations for insn INSN, which defines or uses
4444 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4445 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4446 "insns" field of usage_insns.
4448 The transformations look like:
4451 ... s <- p (new insn -- save)
4453 ... p <- s (new insn -- restore)
4454 <- ... p ... <- ... p ...
4456 <- ... p ... <- ... p ...
4457 ... s <- p (new insn -- save)
4459 ... p <- s (new insn -- restore)
4460 <- ... p ... <- ... p ...
4462 where p is an original pseudo got a hard register or a hard
4463 register and s is a new split pseudo. The save is put before INSN
4464 if BEFORE_P is true. Return true if we succeed in such
4467 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4469 enum reg_class rclass
;
4471 int hard_regno
, nregs
;
4472 rtx new_reg
, save
, restore
, usage_insn
;
4476 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4478 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4479 hard_regno
= original_regno
;
4480 call_save_p
= false;
4485 hard_regno
= reg_renumber
[original_regno
];
4486 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4487 rclass
= lra_get_allocno_class (original_regno
);
4488 original_reg
= regno_reg_rtx
[original_regno
];
4489 call_save_p
= need_for_call_save_p (original_regno
);
4491 original_reg
= regno_reg_rtx
[original_regno
];
4492 lra_assert (hard_regno
>= 0);
4493 if (lra_dump_file
!= NULL
)
4494 fprintf (lra_dump_file
,
4495 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4498 enum machine_mode mode
= GET_MODE (original_reg
);
4500 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4501 hard_regno_nregs
[hard_regno
][mode
],
4503 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4507 rclass
= choose_split_class (rclass
, hard_regno
,
4508 GET_MODE (original_reg
));
4509 if (rclass
== NO_REGS
)
4511 if (lra_dump_file
!= NULL
)
4513 fprintf (lra_dump_file
,
4514 " Rejecting split of %d(%s): "
4515 "no good reg class for %d(%s)\n",
4517 reg_class_names
[lra_get_allocno_class (original_regno
)],
4519 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4522 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4526 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4528 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4530 save
= emit_spill_move (true, new_reg
, original_reg
);
4531 if (NEXT_INSN (save
) != NULL_RTX
)
4533 lra_assert (! call_save_p
);
4534 if (lra_dump_file
!= NULL
)
4538 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4539 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4540 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4541 fprintf (lra_dump_file
,
4542 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4546 restore
= emit_spill_move (false, new_reg
, original_reg
);
4547 if (NEXT_INSN (restore
) != NULL_RTX
)
4549 lra_assert (! call_save_p
);
4550 if (lra_dump_file
!= NULL
)
4552 fprintf (lra_dump_file
,
4553 " Rejecting split %d->%d "
4554 "resulting in > 2 %s restore insns:\n",
4555 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4556 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4557 fprintf (lra_dump_file
,
4558 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4562 after_p
= usage_insns
[original_regno
].after_p
;
4563 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4564 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4565 bitmap_set_bit (&check_only_regs
, original_regno
);
4566 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4569 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4571 usage_insn
= next_usage_insns
;
4574 usage_insn
= XEXP (next_usage_insns
, 0);
4575 lra_assert (DEBUG_INSN_P (usage_insn
));
4576 next_usage_insns
= XEXP (next_usage_insns
, 1);
4577 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4578 lra_update_insn_regno_info (usage_insn
);
4579 if (lra_dump_file
!= NULL
)
4581 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4582 original_regno
, REGNO (new_reg
));
4583 dump_insn_slim (lra_dump_file
, usage_insn
);
4586 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4587 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4588 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4589 after_p
? restore
: NULL_RTX
,
4591 ? "Add reg<-save" : "Add reg<-split");
4592 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4593 before_p
? NULL_RTX
: save
,
4595 ? "Add save<-reg" : "Add split<-reg");
4597 /* If we are trying to split multi-register. We should check
4598 conflicts on the next assignment sub-pass. IRA can allocate on
4599 sub-register levels, LRA do this on pseudos level right now and
4600 this discrepancy may create allocation conflicts after
4602 lra_risky_transformations_p
= true;
4603 if (lra_dump_file
!= NULL
)
4604 fprintf (lra_dump_file
,
4605 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4609 /* Recognize that we need a split transformation for insn INSN, which
4610 defines or uses REGNO in its insn biggest MODE (we use it only if
4611 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4612 hard registers which might be used for reloads since the EBB end.
4613 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4614 uid before starting INSN processing. Return true if we succeed in
4615 such transformation. */
4617 split_if_necessary (int regno
, enum machine_mode mode
,
4618 HARD_REG_SET potential_reload_hard_regs
,
4619 bool before_p
, rtx insn
, int max_uid
)
4623 rtx next_usage_insns
;
4625 if (regno
< FIRST_PSEUDO_REGISTER
)
4626 nregs
= hard_regno_nregs
[regno
][mode
];
4627 for (i
= 0; i
< nregs
; i
++)
4628 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4629 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4630 /* To avoid processing the register twice or more. */
4631 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4632 && INSN_UID (next_usage_insns
) < max_uid
)
4633 || (GET_CODE (next_usage_insns
) == INSN_LIST
4634 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4635 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4636 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4641 /* Check only registers living at the current program point in the
4643 static bitmap_head live_regs
;
4645 /* Update live info in EBB given by its HEAD and TAIL insns after
4646 inheritance/split transformation. The function removes dead moves
4649 update_ebb_live_info (rtx head
, rtx tail
)
4656 basic_block last_bb
, prev_bb
, curr_bb
;
4658 struct lra_insn_reg
*reg
;
4662 last_bb
= BLOCK_FOR_INSN (tail
);
4664 for (curr_insn
= tail
;
4665 curr_insn
!= PREV_INSN (head
);
4666 curr_insn
= prev_insn
)
4668 prev_insn
= PREV_INSN (curr_insn
);
4669 /* We need to process empty blocks too. They contain
4670 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4671 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4673 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4674 if (curr_bb
!= prev_bb
)
4676 if (prev_bb
!= NULL
)
4678 /* Update df_get_live_in (prev_bb): */
4679 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4680 if (bitmap_bit_p (&live_regs
, j
))
4681 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4683 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4685 if (curr_bb
!= last_bb
)
4687 /* Update df_get_live_out (curr_bb): */
4688 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4690 live_p
= bitmap_bit_p (&live_regs
, j
);
4692 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4693 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4699 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4701 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4705 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4707 if (! NONDEBUG_INSN_P (curr_insn
))
4709 curr_id
= lra_get_insn_recog_data (curr_insn
);
4711 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4712 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4713 && bitmap_bit_p (&check_only_regs
, regno
)
4714 && ! bitmap_bit_p (&live_regs
, regno
))
4716 /* See which defined values die here. */
4717 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4718 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4719 bitmap_clear_bit (&live_regs
, reg
->regno
);
4720 /* Mark each used value as live. */
4721 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4722 if (reg
->type
!= OP_OUT
4723 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4724 bitmap_set_bit (&live_regs
, reg
->regno
);
4725 /* It is quite important to remove dead move insns because it
4726 means removing dead store. We don't need to process them for
4730 if (lra_dump_file
!= NULL
)
4732 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4733 dump_insn_slim (lra_dump_file
, curr_insn
);
4735 lra_set_insn_deleted (curr_insn
);
4740 /* The structure describes info to do an inheritance for the current
4741 insn. We need to collect such info first before doing the
4742 transformations because the transformations change the insn
4743 internal representation. */
4746 /* Original regno. */
4748 /* Subsequent insns which can inherit original reg value. */
4752 /* Array containing all info for doing inheritance from the current
4754 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4756 /* Number elements in the previous array. */
4757 static int to_inherit_num
;
4759 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4760 structure to_inherit. */
4762 add_to_inherit (int regno
, rtx insns
)
4766 for (i
= 0; i
< to_inherit_num
; i
++)
4767 if (to_inherit
[i
].regno
== regno
)
4769 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4770 to_inherit
[to_inherit_num
].regno
= regno
;
4771 to_inherit
[to_inherit_num
++].insns
= insns
;
4774 /* Return the last non-debug insn in basic block BB, or the block begin
4777 get_last_insertion_point (basic_block bb
)
4781 FOR_BB_INSNS_REVERSE (bb
, insn
)
4782 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4787 /* Set up RES by registers living on edges FROM except the edge (FROM,
4788 TO) or by registers set up in a jump insn in BB FROM. */
4790 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4793 struct lra_insn_reg
*reg
;
4797 lra_assert (to
!= NULL
);
4799 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4801 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4802 last
= get_last_insertion_point (from
);
4803 if (! JUMP_P (last
))
4805 curr_id
= lra_get_insn_recog_data (last
);
4806 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4807 if (reg
->type
!= OP_IN
)
4808 bitmap_set_bit (res
, reg
->regno
);
4811 /* Used as a temporary results of some bitmap calculations. */
4812 static bitmap_head temp_bitmap
;
4814 /* Do inheritance/split transformations in EBB starting with HEAD and
4815 finishing on TAIL. We process EBB insns in the reverse order.
4816 Return true if we did any inheritance/split transformation in the
4819 We should avoid excessive splitting which results in worse code
4820 because of inaccurate cost calculations for spilling new split
4821 pseudos in such case. To achieve this we do splitting only if
4822 register pressure is high in given basic block and there are reload
4823 pseudos requiring hard registers. We could do more register
4824 pressure calculations at any given program point to avoid necessary
4825 splitting even more but it is to expensive and the current approach
4826 works well enough. */
4828 inherit_in_ebb (rtx head
, rtx tail
)
4830 int i
, src_regno
, dst_regno
, nregs
;
4831 bool change_p
, succ_p
;
4832 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4834 struct lra_insn_reg
*reg
;
4835 basic_block last_processed_bb
, curr_bb
= NULL
;
4836 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
4840 bool head_p
, after_p
;
4843 curr_usage_insns_check
++;
4844 reloads_num
= calls_num
= 0;
4845 bitmap_clear (&check_only_regs
);
4846 last_processed_bb
= NULL
;
4847 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4848 CLEAR_HARD_REG_SET (live_hard_regs
);
4849 /* We don't process new insns generated in the loop. */
4850 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
4852 prev_insn
= PREV_INSN (curr_insn
);
4853 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
4854 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4855 if (last_processed_bb
!= curr_bb
)
4857 /* We are at the end of BB. Add qualified living
4858 pseudos for potential splitting. */
4859 to_process
= df_get_live_out (curr_bb
);
4860 if (last_processed_bb
!= NULL
)
4862 /* We are somewhere in the middle of EBB. */
4863 get_live_on_other_edges (curr_bb
, last_processed_bb
,
4865 to_process
= &temp_bitmap
;
4867 last_processed_bb
= curr_bb
;
4868 last_insn
= get_last_insertion_point (curr_bb
);
4869 after_p
= (! JUMP_P (last_insn
)
4870 && (! CALL_P (last_insn
)
4871 || (find_reg_note (last_insn
,
4872 REG_NORETURN
, NULL_RTX
) == NULL_RTX
4873 && ! SIBLING_CALL_P (last_insn
))));
4874 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
4875 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
4876 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
4877 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4878 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4880 if ((int) j
>= lra_constraint_new_regno_start
)
4882 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4884 if (j
< FIRST_PSEUDO_REGISTER
)
4885 SET_HARD_REG_BIT (live_hard_regs
, j
);
4887 add_to_hard_reg_set (&live_hard_regs
,
4888 PSEUDO_REGNO_MODE (j
),
4890 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
4894 src_regno
= dst_regno
= -1;
4895 if (NONDEBUG_INSN_P (curr_insn
)
4896 && (set
= single_set (curr_insn
)) != NULL_RTX
4897 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
4899 src_regno
= REGNO (SET_SRC (set
));
4900 dst_regno
= REGNO (SET_DEST (set
));
4902 if (src_regno
< lra_constraint_new_regno_start
4903 && src_regno
>= FIRST_PSEUDO_REGISTER
4904 && reg_renumber
[src_regno
] < 0
4905 && dst_regno
>= lra_constraint_new_regno_start
4906 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
4908 /* 'reload_pseudo <- original_pseudo'. */
4911 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4912 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
4913 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
4914 curr_insn
, next_usage_insns
);
4918 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4919 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4920 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4921 reg_class_contents
[cl
]);
4923 else if (src_regno
>= lra_constraint_new_regno_start
4924 && dst_regno
< lra_constraint_new_regno_start
4925 && dst_regno
>= FIRST_PSEUDO_REGISTER
4926 && reg_renumber
[dst_regno
] < 0
4927 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
4928 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4929 && (next_usage_insns
4930 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4933 /* 'original_pseudo <- reload_pseudo'. */
4934 if (! JUMP_P (curr_insn
)
4935 && inherit_reload_reg (true, dst_regno
, cl
,
4936 curr_insn
, next_usage_insns
))
4939 usage_insns
[dst_regno
].check
= 0;
4940 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4941 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4942 reg_class_contents
[cl
]);
4944 else if (INSN_P (curr_insn
))
4947 int max_uid
= get_max_uid ();
4949 curr_id
= lra_get_insn_recog_data (curr_insn
);
4950 curr_static_id
= curr_id
->insn_static_data
;
4952 /* Process insn definitions. */
4953 for (iter
= 0; iter
< 2; iter
++)
4954 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
4957 if (reg
->type
!= OP_IN
4958 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4960 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
4961 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
4962 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4963 && (next_usage_insns
4964 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4966 struct lra_insn_reg
*r
;
4968 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
4969 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
4971 /* Don't do inheritance if the pseudo is also
4972 used in the insn. */
4974 /* We can not do inheritance right now
4975 because the current insn reg info (chain
4976 regs) can change after that. */
4977 add_to_inherit (dst_regno
, next_usage_insns
);
4979 /* We can not process one reg twice here because of
4980 usage_insns invalidation. */
4981 if ((dst_regno
< FIRST_PSEUDO_REGISTER
4982 || reg_renumber
[dst_regno
] >= 0)
4983 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
4987 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
4988 potential_reload_hard_regs
,
4989 false, curr_insn
, max_uid
))
4991 CLEAR_HARD_REG_SET (s
);
4992 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
4993 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
4995 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
4996 reg_renumber
[dst_regno
]);
4997 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
4999 /* We should invalidate potential inheritance or
5000 splitting for the current insn usages to the next
5001 usage insns (see code below) as the output pseudo
5003 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5004 && reg_renumber
[dst_regno
] < 0)
5005 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5006 && (dst_regno
< FIRST_PSEUDO_REGISTER
5007 || reg_renumber
[dst_regno
] >= 0)))
5009 /* Invalidate and mark definitions. */
5010 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5011 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5014 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5015 for (i
= 0; i
< nregs
; i
++)
5016 usage_insns
[dst_regno
+ i
].check
5017 = -(int) INSN_UID (curr_insn
);
5021 if (! JUMP_P (curr_insn
))
5022 for (i
= 0; i
< to_inherit_num
; i
++)
5023 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5024 ALL_REGS
, curr_insn
,
5025 to_inherit
[i
].insns
))
5027 if (CALL_P (curr_insn
))
5029 rtx cheap
, pat
, dest
, restore
;
5030 int regno
, hard_regno
;
5033 if ((cheap
= find_reg_note (curr_insn
,
5034 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5035 && ((cheap
= XEXP (cheap
, 0)), true)
5036 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5037 && (hard_regno
= reg_renumber
[regno
]) >= 0
5038 /* If there are pending saves/restores, the
5039 optimization is not worth. */
5040 && usage_insns
[regno
].calls_num
== calls_num
- 1
5041 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5043 /* Restore the pseudo from the call result as
5044 REG_RETURNED note says that the pseudo value is
5045 in the call result and the pseudo is an argument
5047 pat
= PATTERN (curr_insn
);
5048 if (GET_CODE (pat
) == PARALLEL
)
5049 pat
= XVECEXP (pat
, 0, 0);
5050 dest
= SET_DEST (pat
);
5052 emit_move_insn (cheap
, copy_rtx (dest
));
5053 restore
= get_insns ();
5055 lra_process_new_insns (curr_insn
, NULL
, restore
,
5056 "Inserting call parameter restore");
5057 /* We don't need to save/restore of the pseudo from
5059 usage_insns
[regno
].calls_num
= calls_num
;
5060 bitmap_set_bit (&check_only_regs
, regno
);
5064 /* Process insn usages. */
5065 for (iter
= 0; iter
< 2; iter
++)
5066 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5069 if ((reg
->type
!= OP_OUT
5070 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5071 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5073 if (src_regno
>= FIRST_PSEUDO_REGISTER
5074 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5076 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5077 && (next_usage_insns
5078 = usage_insns
[src_regno
].insns
) != NULL_RTX
5079 && NONDEBUG_INSN_P (curr_insn
))
5080 add_to_inherit (src_regno
, next_usage_insns
);
5081 else if (usage_insns
[src_regno
].check
5082 != -(int) INSN_UID (curr_insn
))
5083 /* Add usages but only if the reg is not set up
5084 in the same insn. */
5085 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5087 else if (src_regno
< FIRST_PSEUDO_REGISTER
5088 || reg_renumber
[src_regno
] >= 0)
5091 rtx use_insn
= curr_insn
;
5093 before_p
= (JUMP_P (curr_insn
)
5094 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5095 if (NONDEBUG_INSN_P (curr_insn
)
5096 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5097 potential_reload_hard_regs
,
5098 before_p
, curr_insn
, max_uid
))
5101 lra_risky_transformations_p
= true;
5104 usage_insns
[src_regno
].check
= 0;
5106 use_insn
= PREV_INSN (curr_insn
);
5108 if (NONDEBUG_INSN_P (curr_insn
))
5110 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5111 add_to_hard_reg_set (&live_hard_regs
,
5112 reg
->biggest_mode
, src_regno
);
5114 add_to_hard_reg_set (&live_hard_regs
,
5115 PSEUDO_REGNO_MODE (src_regno
),
5116 reg_renumber
[src_regno
]);
5118 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5121 for (i
= 0; i
< to_inherit_num
; i
++)
5123 src_regno
= to_inherit
[i
].regno
;
5124 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5125 curr_insn
, to_inherit
[i
].insns
))
5128 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5131 /* We reached the start of the current basic block. */
5132 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5133 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5135 /* We reached the beginning of the current block -- do
5136 rest of spliting in the current BB. */
5137 to_process
= df_get_live_in (curr_bb
);
5138 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5140 /* We are somewhere in the middle of EBB. */
5141 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5142 curr_bb
, &temp_bitmap
);
5143 to_process
= &temp_bitmap
;
5146 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5148 if ((int) j
>= lra_constraint_new_regno_start
)
5150 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5151 && usage_insns
[j
].check
== curr_usage_insns_check
5152 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5154 if (need_for_split_p (potential_reload_hard_regs
, j
))
5156 if (lra_dump_file
!= NULL
&& head_p
)
5158 fprintf (lra_dump_file
,
5159 " ----------------------------------\n");
5162 if (split_reg (false, j
, bb_note (curr_bb
),
5166 usage_insns
[j
].check
= 0;
5174 /* This value affects EBB forming. If probability of edge from EBB to
5175 a BB is not greater than the following value, we don't add the BB
5177 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5179 /* Current number of inheritance/split iteration. */
5180 int lra_inheritance_iter
;
5182 /* Entry function for inheritance/split pass. */
5184 lra_inheritance (void)
5187 basic_block bb
, start_bb
;
5190 lra_inheritance_iter
++;
5191 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5193 timevar_push (TV_LRA_INHERITANCE
);
5194 if (lra_dump_file
!= NULL
)
5195 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5196 lra_inheritance_iter
);
5197 curr_usage_insns_check
= 0;
5198 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5199 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5200 usage_insns
[i
].check
= 0;
5201 bitmap_initialize (&check_only_regs
, ®_obstack
);
5202 bitmap_initialize (&live_regs
, ®_obstack
);
5203 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5204 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5208 if (lra_dump_file
!= NULL
)
5209 fprintf (lra_dump_file
, "EBB");
5210 /* Form a EBB starting with BB. */
5211 bitmap_clear (&ebb_global_regs
);
5212 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5215 if (lra_dump_file
!= NULL
)
5216 fprintf (lra_dump_file
, " %d", bb
->index
);
5217 if (bb
->next_bb
== EXIT_BLOCK_PTR
|| LABEL_P (BB_HEAD (bb
->next_bb
)))
5219 e
= find_fallthru_edge (bb
->succs
);
5222 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5226 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5227 if (lra_dump_file
!= NULL
)
5228 fprintf (lra_dump_file
, "\n");
5229 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5230 /* Remember that the EBB head and tail can change in
5232 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5234 bitmap_clear (&ebb_global_regs
);
5235 bitmap_clear (&temp_bitmap
);
5236 bitmap_clear (&live_regs
);
5237 bitmap_clear (&check_only_regs
);
5240 timevar_pop (TV_LRA_INHERITANCE
);
5245 /* This page contains code to undo failed inheritance/split
5248 /* Current number of iteration undoing inheritance/split. */
5249 int lra_undo_inheritance_iter
;
5251 /* Fix BB live info LIVE after removing pseudos created on pass doing
5252 inheritance/split which are REMOVED_PSEUDOS. */
5254 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5259 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5260 if (bitmap_clear_bit (live
, regno
))
5261 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5264 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5269 if (GET_CODE (reg
) == SUBREG
)
5270 reg
= SUBREG_REG (reg
);
5276 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5277 return true if we did any change. The undo transformations for
5278 inheritance looks like
5282 p <- i, i <- p, and i <- i3
5283 where p is original pseudo from which inheritance pseudo i was
5284 created, i and i3 are removed inheritance pseudos, i2 is another
5285 not removed inheritance pseudo. All split pseudos or other
5286 occurrences of removed inheritance pseudos are changed on the
5287 corresponding original pseudos.
5289 The function also schedules insns changed and created during
5290 inheritance/split pass for processing by the subsequent constraint
5293 remove_inheritance_pseudos (bitmap remove_pseudos
)
5296 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5297 rtx set
, prev_set
, prev_insn
;
5298 bool change_p
, done_p
;
5300 change_p
= ! bitmap_empty_p (remove_pseudos
);
5301 /* We can not finish the function right away if CHANGE_P is true
5302 because we need to marks insns affected by previous
5303 inheritance/split pass for processing by the subsequent
5307 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5308 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5309 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5311 if (! INSN_P (curr_insn
))
5314 sregno
= dregno
= -1;
5315 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5316 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5318 dregno
= get_regno (SET_DEST (set
));
5319 sregno
= get_regno (SET_SRC (set
));
5322 if (sregno
>= 0 && dregno
>= 0)
5324 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5325 && (lra_reg_info
[sregno
].restore_regno
== dregno
5326 || (bitmap_bit_p (remove_pseudos
, dregno
)
5327 && (lra_reg_info
[sregno
].restore_regno
5328 == lra_reg_info
[dregno
].restore_regno
))))
5329 || (bitmap_bit_p (remove_pseudos
, dregno
)
5330 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5331 /* One of the following cases:
5332 original <- removed inheritance pseudo
5333 removed inherit pseudo <- another removed inherit pseudo
5334 removed inherit pseudo <- original pseudo
5336 removed_split_pseudo <- original_reg
5337 original_reg <- removed_split_pseudo */
5339 if (lra_dump_file
!= NULL
)
5341 fprintf (lra_dump_file
, " Removing %s:\n",
5342 bitmap_bit_p (&lra_split_regs
, sregno
)
5343 || bitmap_bit_p (&lra_split_regs
, dregno
)
5344 ? "split" : "inheritance");
5345 dump_insn_slim (lra_dump_file
, curr_insn
);
5347 lra_set_insn_deleted (curr_insn
);
5350 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5351 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5353 /* Search the following pattern:
5354 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5355 original_pseudo <- inherit_or_split_pseudo1
5356 where the 2nd insn is the current insn and
5357 inherit_or_split_pseudo2 is not removed. If it is found,
5358 change the current insn onto:
5359 original_pseudo <- inherit_or_split_pseudo2. */
5360 for (prev_insn
= PREV_INSN (curr_insn
);
5361 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5362 prev_insn
= PREV_INSN (prev_insn
))
5364 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5365 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5366 /* There should be no subregs in insn we are
5367 searching because only the original reg might
5368 be in subreg when we changed the mode of
5369 load/store for splitting. */
5370 && REG_P (SET_DEST (prev_set
))
5371 && REG_P (SET_SRC (prev_set
))
5372 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5373 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5374 >= FIRST_PSEUDO_REGISTER
)
5375 /* As we consider chain of inheritance or
5376 splitting described in above comment we should
5377 check that sregno and prev_sregno were
5378 inheritance/split pseudos created from the
5379 same original regno. */
5380 && (lra_reg_info
[sregno
].restore_regno
5381 == lra_reg_info
[prev_sregno
].restore_regno
)
5382 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5384 lra_assert (GET_MODE (SET_SRC (prev_set
))
5385 == GET_MODE (regno_reg_rtx
[sregno
]));
5386 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5387 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5389 SET_SRC (set
) = SET_SRC (prev_set
);
5390 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5391 lra_set_used_insn_alternative_by_uid
5392 (INSN_UID (curr_insn
), -1);
5394 if (lra_dump_file
!= NULL
)
5396 fprintf (lra_dump_file
, " Change reload insn:\n");
5397 dump_insn_slim (lra_dump_file
, curr_insn
);
5404 struct lra_insn_reg
*reg
;
5405 bool restored_regs_p
= false;
5406 bool kept_regs_p
= false;
5408 curr_id
= lra_get_insn_recog_data (curr_insn
);
5409 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5412 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5413 if (restore_regno
>= 0)
5415 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5417 substitute_pseudo (&curr_insn
, regno
,
5418 regno_reg_rtx
[restore_regno
]);
5419 restored_regs_p
= true;
5425 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5427 /* The instruction has changed since the previous
5428 constraints pass. */
5429 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5430 lra_set_used_insn_alternative_by_uid
5431 (INSN_UID (curr_insn
), -1);
5433 else if (restored_regs_p
)
5434 /* The instruction has been restored to the form that
5435 it had during the previous constraints pass. */
5436 lra_update_insn_regno_info (curr_insn
);
5437 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5439 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5440 dump_insn_slim (lra_dump_file
, curr_insn
);
5448 /* If optional reload pseudos failed to get a hard register or was not
5449 inherited, it is better to remove optional reloads. We do this
5450 transformation after undoing inheritance to figure out necessity to
5451 remove optional reloads easier. Return true if we do any
5454 undo_optional_reloads (void)
5456 bool change_p
, keep_p
;
5457 unsigned int regno
, uid
;
5458 bitmap_iterator bi
, bi2
;
5459 rtx insn
, set
, src
, dest
;
5460 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5462 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5463 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5464 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5467 /* Keep optional reloads from previous subpasses. */
5468 if (lra_reg_info
[regno
].restore_regno
< 0
5469 /* If the original pseudo changed its allocation, just
5470 removing the optional pseudo is dangerous as the original
5471 pseudo will have longer live range. */
5472 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5474 else if (reg_renumber
[regno
] >= 0)
5475 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5477 insn
= lra_insn_recog_data
[uid
]->insn
;
5478 if ((set
= single_set (insn
)) == NULL_RTX
)
5480 src
= SET_SRC (set
);
5481 dest
= SET_DEST (set
);
5482 if (! REG_P (src
) || ! REG_P (dest
))
5484 if (REGNO (dest
) == regno
5485 /* Ignore insn for optional reloads itself. */
5486 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5487 /* Check only inheritance on last inheritance pass. */
5488 && (int) REGNO (src
) >= new_regno_start
5489 /* Check that the optional reload was inherited. */
5490 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5498 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5499 if (lra_dump_file
!= NULL
)
5500 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5503 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5504 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5505 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5507 if (lra_dump_file
!= NULL
)
5508 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5509 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5510 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5512 insn
= lra_insn_recog_data
[uid
]->insn
;
5513 if ((set
= single_set (insn
)) != NULL_RTX
)
5515 src
= SET_SRC (set
);
5516 dest
= SET_DEST (set
);
5517 if (REG_P (src
) && REG_P (dest
)
5518 && ((REGNO (src
) == regno
5519 && (lra_reg_info
[regno
].restore_regno
5520 == (int) REGNO (dest
)))
5521 || (REGNO (dest
) == regno
5522 && (lra_reg_info
[regno
].restore_regno
5523 == (int) REGNO (src
)))))
5525 if (lra_dump_file
!= NULL
)
5527 fprintf (lra_dump_file
, " Deleting move %u\n",
5529 dump_insn_slim (lra_dump_file
, insn
);
5531 lra_set_insn_deleted (insn
);
5534 /* We should not worry about generation memory-memory
5535 moves here as if the corresponding inheritance did
5536 not work (inheritance pseudo did not get a hard reg),
5537 we remove the inheritance pseudo and the optional
5540 substitute_pseudo (&insn
, regno
,
5541 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5542 lra_update_insn_regno_info (insn
);
5543 if (lra_dump_file
!= NULL
)
5545 fprintf (lra_dump_file
,
5546 " Restoring original insn:\n");
5547 dump_insn_slim (lra_dump_file
, insn
);
5551 /* Clear restore_regnos. */
5552 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5553 lra_reg_info
[regno
].restore_regno
= -1;
5554 bitmap_clear (&insn_bitmap
);
5555 bitmap_clear (&removed_optional_reload_pseudos
);
5559 /* Entry function for undoing inheritance/split transformation. Return true
5560 if we did any RTL change in this pass. */
5562 lra_undo_inheritance (void)
5565 int restore_regno
, hard_regno
;
5566 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5567 bitmap_head remove_pseudos
;
5571 lra_undo_inheritance_iter
++;
5572 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5574 if (lra_dump_file
!= NULL
)
5575 fprintf (lra_dump_file
,
5576 "\n********** Undoing inheritance #%d: **********\n\n",
5577 lra_undo_inheritance_iter
);
5578 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5579 n_inherit
= n_all_inherit
= 0;
5580 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5581 if (lra_reg_info
[regno
].restore_regno
>= 0)
5584 if (reg_renumber
[regno
] < 0
5585 /* If the original pseudo changed its allocation, just
5586 removing inheritance is dangerous as for changing
5587 allocation we used shorter live-ranges. */
5588 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5589 bitmap_set_bit (&remove_pseudos
, regno
);
5593 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5594 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5595 n_inherit
, n_all_inherit
,
5596 (double) n_inherit
/ n_all_inherit
* 100);
5597 n_split
= n_all_split
= 0;
5598 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5599 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5602 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5603 ? reg_renumber
[restore_regno
] : restore_regno
);
5604 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5605 bitmap_set_bit (&remove_pseudos
, regno
);
5609 if (lra_dump_file
!= NULL
)
5610 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5611 regno
, restore_regno
);
5614 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5615 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5616 n_split
, n_all_split
,
5617 (double) n_split
/ n_all_split
* 100);
5618 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5619 bitmap_clear (&remove_pseudos
);
5620 /* Clear restore_regnos. */
5621 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5622 lra_reg_info
[regno
].restore_regno
= -1;
5623 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5624 lra_reg_info
[regno
].restore_regno
= -1;
5625 change_p
= undo_optional_reloads () || change_p
;