1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 lra_eliminate_reg_if_possible (m_base_loc
);
363 if (m_ad
->base_term2
!= NULL
)
364 *m_ad
->base_term2
= *m_ad
->base_term
;
366 if (m_index_loc
!= NULL
)
368 m_index_reg
= *m_index_loc
;
369 lra_eliminate_reg_if_possible (m_index_loc
);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
377 *m_base_loc
= m_base_reg
;
378 if (m_ad
->base_term2
!= NULL
)
379 *m_ad
->base_term2
= *m_ad
->base_term
;
381 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
382 *m_index_loc
= m_index_reg
;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
387 valid_address_p (struct address_info
*ad
)
389 address_eliminator
eliminator (ad
);
390 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
396 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
398 struct address_info ad
;
400 decompose_mem_address (&ad
, op
);
401 address_eliminator
eliminator (&ad
);
402 return constraint_satisfied_p (op
, constraint
);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
408 satisfies_address_constraint_p (struct address_info
*ad
,
409 enum constraint_num constraint
)
411 address_eliminator
eliminator (ad
);
412 return constraint_satisfied_p (*ad
->outer
, constraint
);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
418 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
420 struct address_info ad
;
422 decompose_lea_address (&ad
, &op
);
423 return satisfies_address_constraint_p (&ad
, constraint
);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
437 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
438 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
439 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
440 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
444 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
450 update_equiv (int regno
)
454 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
455 ira_reg_equiv
[regno
].memory
456 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
458 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].invariant
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
472 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv
[regno
].defined_p
474 || ! ira_reg_equiv
[regno
].profitable_p
475 || lra_get_regno_hard_regno (regno
) >= 0)
477 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
479 if (targetm
.cannot_substitute_mem_equiv_p (res
))
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
506 init_curr_operand_mode (void)
508 int nop
= curr_static_id
->n_operands
;
509 for (int i
= 0; i
< nop
; i
++)
511 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
512 if (mode
== VOIDmode
)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
519 mode
= curr_static_id
->operand
[i
].mode
;
521 curr_operand_mode
[i
] = mode
;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
532 /* True for input reload of matched operands. */
534 /* Reloaded value. */
536 /* Reload pseudo used. */
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num
;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
546 /* Initiate data concerning reuse of input reloads for the current
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num
= 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
562 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
563 enum reg_class rclass
, bool in_subreg_p
,
564 const char *title
, rtx
*result_reg
)
567 enum reg_class new_class
;
568 bool unique_p
= false;
573 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original
))
579 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
581 if (! curr_insn_input_reloads
[i
].match_p
582 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
583 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
585 rtx reg
= curr_insn_input_reloads
[i
].reg
;
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg
) != mode
)
594 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
596 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
597 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
601 if (lra_dump_file
!= NULL
)
603 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
604 dump_value_slim (lra_dump_file
, original
, 1);
606 if (new_class
!= lra_get_allocno_class (regno
))
607 lra_change_class (regno
, new_class
, ", change to", false);
608 if (lra_dump_file
!= NULL
)
609 fprintf (lra_dump_file
, "\n");
612 /* If we have an input reload with a different mode, make sure it
613 will get a different hard reg. */
614 else if (REG_P (original
)
615 && REG_P (curr_insn_input_reloads
[i
].input
)
616 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
617 && (GET_MODE (original
)
618 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
621 *result_reg
= (unique_p
622 ? lra_create_new_reg_with_unique_value
623 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
624 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
625 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
626 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
627 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
633 /* The page contains code to extract memory address parts. */
635 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
637 ok_for_index_p_nonstrict (rtx reg
)
639 unsigned regno
= REGNO (reg
);
641 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
644 /* A version of regno_ok_for_base_p for use here, when all pseudos
645 should count as OK. Arguments as for regno_ok_for_base_p. */
647 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
648 enum rtx_code outer_code
, enum rtx_code index_code
)
650 unsigned regno
= REGNO (reg
);
652 if (regno
>= FIRST_PSEUDO_REGISTER
)
654 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
659 /* The page contains major code to choose the current insn alternative
660 and generate reloads for it. */
662 /* Return the offset from REGNO of the least significant register
665 This function is used to tell whether two registers satisfy
666 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
668 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
669 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
671 lra_constraint_offset (int regno
, machine_mode mode
)
673 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
675 scalar_int_mode int_mode
;
677 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
678 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
679 return hard_regno_nregs (regno
, mode
) - 1;
683 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
684 if they are the same hard reg, and has special hacks for
685 auto-increment and auto-decrement. This is specifically intended for
686 process_alt_operands to use in determining whether two operands
687 match. X is the operand whose number is the lower of the two.
689 It is supposed that X is the output operand and Y is the input
690 operand. Y_HARD_REGNO is the final hard regno of register Y or
691 register in subreg Y as we know it now. Otherwise, it is a
694 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
697 RTX_CODE code
= GET_CODE (x
);
702 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
703 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
707 i
= get_hard_regno (x
, false);
711 if ((j
= y_hard_regno
) < 0)
714 i
+= lra_constraint_offset (i
, GET_MODE (x
));
715 j
+= lra_constraint_offset (j
, GET_MODE (y
));
720 /* If two operands must match, because they are really a single
721 operand of an assembler insn, then two post-increments are invalid
722 because the assembler insn would increment only once. On the
723 other hand, a post-increment matches ordinary indexing if the
724 post-increment is the output operand. */
725 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
726 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
728 /* Two pre-increments are invalid because the assembler insn would
729 increment only once. On the other hand, a pre-increment matches
730 ordinary indexing if the pre-increment is the input operand. */
731 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
732 || GET_CODE (y
) == PRE_MODIFY
)
733 return operands_match_p (x
, XEXP (y
, 0), -1);
737 if (code
== REG
&& REG_P (y
))
738 return REGNO (x
) == REGNO (y
);
740 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
741 && x
== SUBREG_REG (y
))
743 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
744 && SUBREG_REG (x
) == y
)
747 /* Now we have disposed of all the cases in which different rtx
749 if (code
!= GET_CODE (y
))
752 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
753 if (GET_MODE (x
) != GET_MODE (y
))
762 return label_ref_label (x
) == label_ref_label (y
);
764 return XSTR (x
, 0) == XSTR (y
, 0);
770 /* Compare the elements. If any pair of corresponding elements fail
771 to match, return false for the whole things. */
773 fmt
= GET_RTX_FORMAT (code
);
774 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
780 if (XWINT (x
, i
) != XWINT (y
, i
))
785 if (XINT (x
, i
) != XINT (y
, i
))
790 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
795 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
804 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
806 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
808 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
814 /* It is believed that rtx's at this level will never
815 contain anything but integers and other rtx's, except for
816 within LABEL_REFs and SYMBOL_REFs. */
824 /* True if X is a constant that can be forced into the constant pool.
825 MODE is the mode of the operand, or VOIDmode if not known. */
826 #define CONST_POOL_OK_P(MODE, X) \
827 ((MODE) != VOIDmode \
829 && GET_CODE (X) != HIGH \
830 && !targetm.cannot_force_const_mem (MODE, X))
832 /* True if C is a non-empty register class that has too few registers
833 to be safely used as a reload target class. */
834 #define SMALL_REGISTER_CLASS_P(C) \
835 (ira_class_hard_regs_num [(C)] == 1 \
836 || (ira_class_hard_regs_num [(C)] >= 1 \
837 && targetm.class_likely_spilled_p (C)))
839 /* If REG is a reload pseudo, try to make its class satisfying CL. */
841 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
843 enum reg_class rclass
;
845 /* Do not make more accurate class from reloads generated. They are
846 mostly moves with a lot of constraints. Making more accurate
847 class may results in very narrow class and impossibility of find
848 registers for several reloads of one insn. */
849 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
851 if (GET_CODE (reg
) == SUBREG
)
852 reg
= SUBREG_REG (reg
);
853 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
855 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
856 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
859 /* Searches X for any reference to a reg with the same value as REGNO,
860 returning the rtx of the reference found if any. Otherwise,
863 regno_val_use_in (unsigned int regno
, rtx x
)
869 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
872 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
873 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
877 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
880 else if (fmt
[i
] == 'E')
881 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
882 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
889 /* Return true if all current insn non-output operands except INS (it
890 has a negaitve end marker) do not use pseudos with the same value
893 check_conflict_input_operands (int regno
, signed char *ins
)
896 int n_operands
= curr_static_id
->n_operands
;
898 for (int nop
= 0; nop
< n_operands
; nop
++)
899 if (! curr_static_id
->operand
[nop
].is_operator
900 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
902 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
906 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
912 /* Generate reloads for matching OUT and INS (array of input operand
913 numbers with end marker -1) with reg class GOAL_CLASS, considering
914 output operands OUTS (similar array to INS) needing to be in different
915 registers. Add input and output reloads correspondingly to the lists
916 *BEFORE and *AFTER. OUT might be negative. In this case we generate
917 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
918 that the output operand is early clobbered for chosen alternative. */
920 match_reload (signed char out
, signed char *ins
, signed char *outs
,
921 enum reg_class goal_class
, rtx_insn
**before
,
922 rtx_insn
**after
, bool early_clobber_p
)
926 rtx new_in_reg
, new_out_reg
, reg
;
927 machine_mode inmode
, outmode
;
928 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
929 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
931 inmode
= curr_operand_mode
[ins
[0]];
932 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
933 push_to_sequence (*before
);
934 if (inmode
!= outmode
)
936 /* process_alt_operands has already checked that the mode sizes
938 if (partial_subreg_p (outmode
, inmode
))
941 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
943 if (SCALAR_INT_MODE_P (inmode
))
944 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
946 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
947 LRA_SUBREG_P (new_out_reg
) = 1;
948 /* If the input reg is dying here, we can use the same hard
949 register for REG and IN_RTX. We do it only for original
950 pseudos as reload pseudos can die although original
951 pseudos still live where reload pseudos dies. */
952 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
953 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
955 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
956 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
961 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
963 if (SCALAR_INT_MODE_P (outmode
))
964 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
966 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
967 /* NEW_IN_REG is non-paradoxical subreg. We don't want
968 NEW_OUT_REG living above. We add clobber clause for
969 this. This is just a temporary clobber. We can remove
970 it at the end of LRA work. */
971 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
972 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
973 LRA_SUBREG_P (new_in_reg
) = 1;
974 if (GET_CODE (in_rtx
) == SUBREG
)
976 rtx subreg_reg
= SUBREG_REG (in_rtx
);
978 /* If SUBREG_REG is dying here and sub-registers IN_RTX
979 and NEW_IN_REG are similar, we can use the same hard
980 register for REG and SUBREG_REG. */
981 if (REG_P (subreg_reg
)
982 && (int) REGNO (subreg_reg
) < lra_new_regno_start
983 && GET_MODE (subreg_reg
) == outmode
984 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
985 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
986 && (! early_clobber_p
987 || check_conflict_input_operands (REGNO (subreg_reg
),
989 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
995 /* Pseudos have values -- see comments for lra_reg_info.
996 Different pseudos with the same value do not conflict even if
997 they live in the same place. When we create a pseudo we
998 assign value of original pseudo (if any) from which we
999 created the new pseudo. If we create the pseudo from the
1000 input pseudo, the new pseudo will have no conflict with the
1001 input pseudo which is wrong when the input pseudo lives after
1002 the insn and as the new pseudo value is changed by the insn
1003 output. Therefore we create the new pseudo from the output
1004 except the case when we have single matched dying input
1007 We cannot reuse the current output register because we might
1008 have a situation like "a <- a op b", where the constraints
1009 force the second input operand ("b") to match the output
1010 operand ("a"). "b" must then be copied into a new register
1011 so that it doesn't clobber the current value of "a".
1013 We can not use the same value if the output pseudo is
1014 early clobbered or the input pseudo is mentioned in the
1015 output, e.g. as an address part in memory, because
1016 output reload will actually extend the pseudo liveness.
1017 We don't care about eliminable hard regs here as we are
1018 interesting only in pseudos. */
1020 /* Matching input's register value is the same as one of the other
1021 output operand. Output operands in a parallel insn must be in
1022 different registers. */
1023 out_conflict
= false;
1026 for (i
= 0; outs
[i
] >= 0; i
++)
1028 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1029 if (REG_P (other_out_rtx
)
1030 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1033 out_conflict
= true;
1039 new_in_reg
= new_out_reg
1040 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1041 && (int) REGNO (in_rtx
) < lra_new_regno_start
1042 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1043 && (! early_clobber_p
1044 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1046 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1048 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1049 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1052 /* In operand can be got from transformations before processing insn
1053 constraints. One example of such transformations is subreg
1054 reloading (see function simplify_operand_subreg). The new
1055 pseudos created by the transformations might have inaccurate
1056 class (ALL_REGS) and we should make their classes more
1058 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1059 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1060 *before
= get_insns ();
1062 /* Add the new pseudo to consider values of subsequent input reload
1064 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1065 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1066 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1067 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1068 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1071 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1072 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1073 *curr_id
->operand_loc
[in
] = new_in_reg
;
1075 lra_update_dups (curr_id
, ins
);
1078 /* See a comment for the input operand above. */
1079 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1080 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1083 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1085 *after
= get_insns ();
1088 *curr_id
->operand_loc
[out
] = new_out_reg
;
1089 lra_update_dup (curr_id
, out
);
1092 /* Return register class which is union of all reg classes in insn
1093 constraint alternative string starting with P. */
1094 static enum reg_class
1095 reg_class_from_constraints (const char *p
)
1098 enum reg_class op_class
= NO_REGS
;
1101 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1108 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1112 enum constraint_num cn
= lookup_constraint (p
);
1113 enum reg_class cl
= reg_class_for_constraint (cn
);
1116 if (insn_extra_address_constraint (cn
))
1118 = (reg_class_subunion
1119 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1120 ADDRESS
, SCRATCH
)]);
1124 op_class
= reg_class_subunion
[op_class
][cl
];
1127 while ((p
+= len
), c
);
1131 /* If OP is a register, return the class of the register as per
1132 get_reg_class, otherwise return NO_REGS. */
1133 static inline enum reg_class
1134 get_op_class (rtx op
)
1136 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1139 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1140 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1141 SUBREG for VAL to make them equal. */
1143 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1145 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1147 /* Usually size of mem_pseudo is greater than val size but in
1148 rare cases it can be less as it can be defined by target
1149 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1152 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1153 GET_CODE (val
) == SUBREG
1154 ? SUBREG_REG (val
) : val
);
1155 LRA_SUBREG_P (val
) = 1;
1159 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1160 LRA_SUBREG_P (mem_pseudo
) = 1;
1163 return to_p
? gen_move_insn (mem_pseudo
, val
)
1164 : gen_move_insn (val
, mem_pseudo
);
1167 /* Process a special case insn (register move), return true if we
1168 don't need to process it anymore. INSN should be a single set
1169 insn. Set up that RTL was changed through CHANGE_P and that hook
1170 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1173 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1176 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1178 enum reg_class dclass
, sclass
, secondary_class
;
1179 secondary_reload_info sri
;
1181 lra_assert (curr_insn_set
!= NULL_RTX
);
1182 dreg
= dest
= SET_DEST (curr_insn_set
);
1183 sreg
= src
= SET_SRC (curr_insn_set
);
1184 if (GET_CODE (dest
) == SUBREG
)
1185 dreg
= SUBREG_REG (dest
);
1186 if (GET_CODE (src
) == SUBREG
)
1187 sreg
= SUBREG_REG (src
);
1188 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1190 sclass
= dclass
= NO_REGS
;
1192 dclass
= get_reg_class (REGNO (dreg
));
1193 gcc_assert (dclass
< LIM_REG_CLASSES
);
1194 if (dclass
== ALL_REGS
)
1195 /* ALL_REGS is used for new pseudos created by transformations
1196 like reload of SUBREG_REG (see function
1197 simplify_operand_subreg). We don't know their class yet. We
1198 should figure out the class from processing the insn
1199 constraints not in this fast path function. Even if ALL_REGS
1200 were a right class for the pseudo, secondary_... hooks usually
1201 are not define for ALL_REGS. */
1204 sclass
= get_reg_class (REGNO (sreg
));
1205 gcc_assert (sclass
< LIM_REG_CLASSES
);
1206 if (sclass
== ALL_REGS
)
1207 /* See comments above. */
1209 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1211 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1212 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1214 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1219 if (! REG_P (dreg
) || ! REG_P (sreg
))
1221 sri
.prev_sri
= NULL
;
1222 sri
.icode
= CODE_FOR_nothing
;
1224 secondary_class
= NO_REGS
;
1225 /* Set up hard register for a reload pseudo for hook
1226 secondary_reload because some targets just ignore unassigned
1227 pseudos in the hook. */
1228 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1230 dregno
= REGNO (dreg
);
1231 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1235 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1237 sregno
= REGNO (sreg
);
1238 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1242 if (sclass
!= NO_REGS
)
1244 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1245 (reg_class_t
) sclass
,
1246 GET_MODE (src
), &sri
);
1247 if (sclass
== NO_REGS
1248 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1249 && dclass
!= NO_REGS
))
1251 enum reg_class old_sclass
= secondary_class
;
1252 secondary_reload_info old_sri
= sri
;
1254 sri
.prev_sri
= NULL
;
1255 sri
.icode
= CODE_FOR_nothing
;
1258 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1259 (reg_class_t
) dclass
,
1260 GET_MODE (src
), &sri
);
1261 /* Check the target hook consistency. */
1263 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1264 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1265 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1268 reg_renumber
[sregno
] = -1;
1270 reg_renumber
[dregno
] = -1;
1271 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1275 if (secondary_class
!= NO_REGS
)
1276 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1280 if (sri
.icode
== CODE_FOR_nothing
)
1281 lra_emit_move (new_reg
, src
);
1284 enum reg_class scratch_class
;
1286 scratch_class
= (reg_class_from_constraints
1287 (insn_data
[sri
.icode
].operand
[2].constraint
));
1288 scratch_reg
= (lra_create_new_reg_with_unique_value
1289 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1290 scratch_class
, "scratch"));
1291 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1294 before
= get_insns ();
1296 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1297 if (new_reg
!= NULL_RTX
)
1298 SET_SRC (curr_insn_set
) = new_reg
;
1301 if (lra_dump_file
!= NULL
)
1303 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1304 dump_insn_slim (lra_dump_file
, curr_insn
);
1306 lra_set_insn_deleted (curr_insn
);
1312 /* The following data describe the result of process_alt_operands.
1313 The data are used in curr_insn_transform to generate reloads. */
1315 /* The chosen reg classes which should be used for the corresponding
1317 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1318 /* True if the operand should be the same as another operand and that
1319 other operand does not need a reload. */
1320 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1321 /* True if the operand does not need a reload. */
1322 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1323 /* True if the operand can be offsetable memory. */
1324 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1325 /* The number of an operand to which given operand can be matched to. */
1326 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1327 /* The number of elements in the following array. */
1328 static int goal_alt_dont_inherit_ops_num
;
1329 /* Numbers of operands whose reload pseudos should not be inherited. */
1330 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1331 /* True if the insn commutative operands should be swapped. */
1332 static bool goal_alt_swapped
;
1333 /* The chosen insn alternative. */
1334 static int goal_alt_number
;
1336 /* True if the corresponding operand is the result of an equivalence
1338 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1340 /* The following five variables are used to choose the best insn
1341 alternative. They reflect final characteristics of the best
1344 /* Number of necessary reloads and overall cost reflecting the
1345 previous value and other unpleasantness of the best alternative. */
1346 static int best_losers
, best_overall
;
1347 /* Overall number hard registers used for reloads. For example, on
1348 some targets we need 2 general registers to reload DFmode and only
1349 one floating point register. */
1350 static int best_reload_nregs
;
1351 /* Overall number reflecting distances of previous reloading the same
1352 value. The distances are counted from the current BB start. It is
1353 used to improve inheritance chances. */
1354 static int best_reload_sum
;
1356 /* True if the current insn should have no correspondingly input or
1358 static bool no_input_reloads_p
, no_output_reloads_p
;
1360 /* True if we swapped the commutative operands in the current
1362 static int curr_swapped
;
1364 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1365 register of class CL. Add any input reloads to list BEFORE. AFTER
1366 is nonnull if *LOC is an automodified value; handle that case by
1367 adding the required output reloads to list AFTER. Return true if
1368 the RTL was changed.
1370 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1371 register. Return false if the address register is correct. */
1373 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1377 enum reg_class rclass
, new_class
;
1381 bool subreg_p
, before_p
= false;
1383 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1386 reg
= SUBREG_REG (*loc
);
1387 mode
= GET_MODE (reg
);
1389 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1390 between two registers with different classes, but there normally will
1391 be "mov" which transfers element of vector register into the general
1392 register, and this normally will be a subreg which should be reloaded
1393 as a whole. This is particularly likely to be triggered when
1394 -fno-split-wide-types specified. */
1396 || in_class_p (reg
, cl
, &new_class
)
1397 || GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (ptr_mode
))
1398 loc
= &SUBREG_REG (*loc
);
1402 mode
= GET_MODE (reg
);
1407 /* Always reload memory in an address even if the target supports
1409 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1414 regno
= REGNO (reg
);
1415 rclass
= get_reg_class (regno
);
1417 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1419 if (lra_dump_file
!= NULL
)
1421 fprintf (lra_dump_file
,
1422 "Changing pseudo %d in address of insn %u on equiv ",
1423 REGNO (reg
), INSN_UID (curr_insn
));
1424 dump_value_slim (lra_dump_file
, *loc
, 1);
1425 fprintf (lra_dump_file
, "\n");
1427 *loc
= copy_rtx (*loc
);
1429 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1434 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1435 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1438 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1442 lra_change_class (regno
, new_class
, " Change to", true);
1450 push_to_sequence (*before
);
1451 lra_emit_move (new_reg
, reg
);
1452 *before
= get_insns ();
1459 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1461 *after
= get_insns ();
1467 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1468 the insn to be inserted before curr insn. AFTER returns the
1469 the insn to be inserted after curr insn. ORIGREG and NEWREG
1470 are the original reg and new reg for reload. */
1472 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1477 push_to_sequence (*before
);
1478 lra_emit_move (newreg
, origreg
);
1479 *before
= get_insns ();
1485 lra_emit_move (origreg
, newreg
);
1487 *after
= get_insns ();
1492 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1493 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1495 /* Make reloads for subreg in operand NOP with internal subreg mode
1496 REG_MODE, add new reloads for further processing. Return true if
1497 any change was done. */
1499 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1502 rtx_insn
*before
, *after
;
1503 machine_mode mode
, innermode
;
1505 rtx operand
= *curr_id
->operand_loc
[nop
];
1506 enum reg_class regclass
;
1509 before
= after
= NULL
;
1511 if (GET_CODE (operand
) != SUBREG
)
1514 mode
= GET_MODE (operand
);
1515 reg
= SUBREG_REG (operand
);
1516 innermode
= GET_MODE (reg
);
1517 type
= curr_static_id
->operand
[nop
].type
;
1520 const bool addr_was_valid
1521 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1522 alter_subreg (curr_id
->operand_loc
[nop
], false);
1523 rtx subst
= *curr_id
->operand_loc
[nop
];
1524 lra_assert (MEM_P (subst
));
1527 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1528 MEM_ADDR_SPACE (subst
))
1529 || ((get_constraint_type (lookup_constraint
1530 (curr_static_id
->operand
[nop
].constraint
))
1531 != CT_SPECIAL_MEMORY
)
1532 /* We still can reload address and if the address is
1533 valid, we can remove subreg without reloading its
1535 && valid_address_p (GET_MODE (subst
),
1537 [ira_class_hard_regs
1538 [base_reg_class (GET_MODE (subst
),
1539 MEM_ADDR_SPACE (subst
),
1540 ADDRESS
, SCRATCH
)][0]],
1541 MEM_ADDR_SPACE (subst
))))
1543 /* If we change the address for a paradoxical subreg of memory, the
1544 new address might violate the necessary alignment or the access
1545 might be slow; take this into consideration. We need not worry
1546 about accesses beyond allocated memory for paradoxical memory
1547 subregs as we don't substitute such equiv memory (see processing
1548 equivalences in function lra_constraints) and because for spilled
1549 pseudos we allocate stack memory enough for the biggest
1550 corresponding paradoxical subreg.
1552 However, do not blindly simplify a (subreg (mem ...)) for
1553 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1554 data into a register when the inner is narrower than outer or
1555 missing important data from memory when the inner is wider than
1556 outer. This rule only applies to modes that are no wider than
1558 if (!(GET_MODE_PRECISION (mode
) != GET_MODE_PRECISION (innermode
)
1559 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1560 && GET_MODE_SIZE (innermode
) <= UNITS_PER_WORD
1561 && WORD_REGISTER_OPERATIONS
)
1562 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1563 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1564 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1565 && targetm
.slow_unaligned_access (innermode
,
1569 *curr_id
->operand_loc
[nop
] = operand
;
1571 /* But if the address was not valid, we cannot reload the MEM without
1572 reloading the address first. */
1573 if (!addr_was_valid
)
1574 process_address (nop
, false, &before
, &after
);
1576 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1577 enum reg_class rclass
1578 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1579 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1580 reg
, rclass
, TRUE
, "slow mem", &new_reg
))
1582 bool insert_before
, insert_after
;
1583 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1585 insert_before
= (type
!= OP_OUT
1586 || partial_subreg_p (mode
, innermode
));
1587 insert_after
= type
!= OP_IN
;
1588 insert_move_for_subreg (insert_before
? &before
: NULL
,
1589 insert_after
? &after
: NULL
,
1592 SUBREG_REG (operand
) = new_reg
;
1594 /* Convert to MODE. */
1597 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1598 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1599 rclass
, TRUE
, "slow mem", &new_reg
))
1601 bool insert_before
, insert_after
;
1602 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1604 insert_before
= type
!= OP_OUT
;
1605 insert_after
= type
!= OP_IN
;
1606 insert_move_for_subreg (insert_before
? &before
: NULL
,
1607 insert_after
? &after
: NULL
,
1610 *curr_id
->operand_loc
[nop
] = new_reg
;
1611 lra_process_new_insns (curr_insn
, before
, after
,
1612 "Inserting slow mem reload");
1616 /* If the address was valid and became invalid, prefer to reload
1617 the memory. Typical case is when the index scale should
1618 correspond the memory. */
1619 *curr_id
->operand_loc
[nop
] = operand
;
1620 /* Do not return false here as the MEM_P (reg) will be processed
1621 later in this function. */
1623 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1625 alter_subreg (curr_id
->operand_loc
[nop
], false);
1628 else if (CONSTANT_P (reg
))
1630 /* Try to simplify subreg of constant. It is usually result of
1631 equivalence substitution. */
1632 if (innermode
== VOIDmode
1633 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1634 innermode
= curr_static_id
->operand
[nop
].mode
;
1635 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1636 SUBREG_BYTE (operand
))) != NULL_RTX
)
1638 *curr_id
->operand_loc
[nop
] = new_reg
;
1642 /* Put constant into memory when we have mixed modes. It generates
1643 a better code in most cases as it does not need a secondary
1644 reload memory. It also prevents LRA looping when LRA is using
1645 secondary reload memory again and again. */
1646 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1647 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1649 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1650 alter_subreg (curr_id
->operand_loc
[nop
], false);
1653 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1654 if there may be a problem accessing OPERAND in the outer
1657 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1658 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1659 /* Don't reload paradoxical subregs because we could be looping
1660 having repeatedly final regno out of hard regs range. */
1661 && (hard_regno_nregs (hard_regno
, innermode
)
1662 >= hard_regno_nregs (hard_regno
, mode
))
1663 && simplify_subreg_regno (hard_regno
, innermode
,
1664 SUBREG_BYTE (operand
), mode
) < 0
1665 /* Don't reload subreg for matching reload. It is actually
1666 valid subreg in LRA. */
1667 && ! LRA_SUBREG_P (operand
))
1668 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1670 enum reg_class rclass
;
1673 /* There is a big probability that we will get the same class
1674 for the new pseudo and we will get the same insn which
1675 means infinite looping. So spill the new pseudo. */
1678 /* The class will be defined later in curr_insn_transform. */
1680 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1682 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1683 rclass
, TRUE
, "subreg reg", &new_reg
))
1685 bool insert_before
, insert_after
;
1686 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1688 insert_before
= (type
!= OP_OUT
1689 || read_modify_subreg_p (operand
));
1690 insert_after
= (type
!= OP_IN
);
1691 insert_move_for_subreg (insert_before
? &before
: NULL
,
1692 insert_after
? &after
: NULL
,
1695 SUBREG_REG (operand
) = new_reg
;
1696 lra_process_new_insns (curr_insn
, before
, after
,
1697 "Inserting subreg reload");
1700 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1701 IRA allocates hardreg to the inner pseudo reg according to its mode
1702 instead of the outermode, so the size of the hardreg may not be enough
1703 to contain the outermode operand, in that case we may need to insert
1704 reload for the reg. For the following two types of paradoxical subreg,
1705 we need to insert reload:
1706 1. If the op_type is OP_IN, and the hardreg could not be paired with
1707 other hardreg to contain the outermode operand
1708 (checked by in_hard_reg_set_p), we need to insert the reload.
1709 2. If the op_type is OP_OUT or OP_INOUT.
1711 Here is a paradoxical subreg example showing how the reload is generated:
1713 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1714 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1716 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1717 here, if reg107 is assigned to hardreg R15, because R15 is the last
1718 hardreg, compiler cannot find another hardreg to pair with R15 to
1719 contain TImode data. So we insert a TImode reload reg180 for it.
1720 After reload is inserted:
1722 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1723 (reg:DI 107 [ __comp ])) -1
1724 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1725 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1727 Two reload hard registers will be allocated to reg180 to save TImode data
1729 else if (REG_P (reg
)
1730 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1731 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1732 && (hard_regno_nregs (hard_regno
, innermode
)
1733 < hard_regno_nregs (hard_regno
, mode
))
1734 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1736 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1739 /* The class will be defined later in curr_insn_transform. */
1740 enum reg_class rclass
1741 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1743 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1744 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1747 bool insert_before
, insert_after
;
1749 PUT_MODE (new_reg
, mode
);
1750 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1751 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1753 insert_before
= (type
!= OP_OUT
);
1754 insert_after
= (type
!= OP_IN
);
1755 insert_move_for_subreg (insert_before
? &before
: NULL
,
1756 insert_after
? &after
: NULL
,
1759 SUBREG_REG (operand
) = new_reg
;
1760 lra_process_new_insns (curr_insn
, before
, after
,
1761 "Inserting paradoxical subreg reload");
1767 /* Return TRUE if X refers for a hard register from SET. */
1769 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1771 int i
, j
, x_hard_regno
;
1778 code
= GET_CODE (x
);
1779 mode
= GET_MODE (x
);
1782 mode
= wider_subreg_mode (x
);
1784 code
= GET_CODE (x
);
1789 x_hard_regno
= get_hard_regno (x
, true);
1790 return (x_hard_regno
>= 0
1791 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1795 struct address_info ad
;
1797 decompose_mem_address (&ad
, x
);
1798 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1800 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1803 fmt
= GET_RTX_FORMAT (code
);
1804 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1808 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1811 else if (fmt
[i
] == 'E')
1813 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1814 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1821 /* Return true if OP is a spilled pseudo. */
1823 spilled_pseudo_p (rtx op
)
1826 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1829 /* Return true if X is a general constant. */
1831 general_constant_p (rtx x
)
1833 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1837 reg_in_class_p (rtx reg
, enum reg_class cl
)
1840 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1841 return in_class_p (reg
, cl
, NULL
);
1844 /* Return true if SET of RCLASS contains no hard regs which can be
1847 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1853 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1854 COPY_HARD_REG_SET (temp
, set
);
1855 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1856 return (hard_reg_set_subset_p
1857 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1861 /* Used to check validity info about small class input operands. It
1862 should be incremented at start of processing an insn
1864 static unsigned int curr_small_class_check
= 0;
1866 /* Update number of used inputs of class OP_CLASS for operand NOP.
1867 Return true if we have more such class operands than the number of
1870 update_and_check_small_class_inputs (int nop
, enum reg_class op_class
)
1872 static unsigned int small_class_check
[LIM_REG_CLASSES
];
1873 static int small_class_input_nums
[LIM_REG_CLASSES
];
1875 if (SMALL_REGISTER_CLASS_P (op_class
)
1876 /* We are interesting in classes became small because of fixing
1877 some hard regs, e.g. by an user through GCC options. */
1878 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
1880 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
1881 || curr_static_id
->operand
[nop
].early_clobber
))
1883 if (small_class_check
[op_class
] == curr_small_class_check
)
1884 small_class_input_nums
[op_class
]++;
1887 small_class_check
[op_class
] = curr_small_class_check
;
1888 small_class_input_nums
[op_class
] = 1;
1890 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
1896 /* Major function to choose the current insn alternative and what
1897 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1898 negative we should consider only this alternative. Return false if
1899 we can not choose the alternative or find how to reload the
1902 process_alt_operands (int only_alternative
)
1905 int nop
, overall
, nalt
;
1906 int n_alternatives
= curr_static_id
->n_alternatives
;
1907 int n_operands
= curr_static_id
->n_operands
;
1908 /* LOSERS counts the operands that don't fit this alternative and
1909 would require loading. */
1912 /* REJECT is a count of how undesirable this alternative says it is
1913 if any reloading is required. If the alternative matches exactly
1914 then REJECT is ignored, but otherwise it gets this much counted
1915 against it in addition to the reloading needed. */
1917 /* This is defined by '!' or '?' alternative constraint and added to
1918 reject. But in some cases it can be ignored. */
1921 /* The number of elements in the following array. */
1922 int early_clobbered_regs_num
;
1923 /* Numbers of operands which are early clobber registers. */
1924 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1925 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1926 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1927 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1928 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1929 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1930 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1931 /* The number of elements in the following array. */
1932 int curr_alt_dont_inherit_ops_num
;
1933 /* Numbers of operands whose reload pseudos should not be inherited. */
1934 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1936 /* The register when the operand is a subreg of register, otherwise the
1938 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1939 /* The register if the operand is a register or subreg of register,
1941 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1942 int hard_regno
[MAX_RECOG_OPERANDS
];
1943 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1944 int reload_nregs
, reload_sum
;
1948 /* Calculate some data common for all alternatives to speed up the
1950 for (nop
= 0; nop
< n_operands
; nop
++)
1954 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1955 /* The real hard regno of the operand after the allocation. */
1956 hard_regno
[nop
] = get_hard_regno (op
, true);
1958 operand_reg
[nop
] = reg
= op
;
1959 biggest_mode
[nop
] = GET_MODE (op
);
1960 if (GET_CODE (op
) == SUBREG
)
1962 biggest_mode
[nop
] = wider_subreg_mode (op
);
1963 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1966 operand_reg
[nop
] = NULL_RTX
;
1967 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1968 || ((int) REGNO (reg
)
1969 == lra_get_elimination_hard_regno (REGNO (reg
))))
1970 no_subreg_reg_operand
[nop
] = reg
;
1972 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1973 /* Just use natural mode for elimination result. It should
1974 be enough for extra constraints hooks. */
1975 = regno_reg_rtx
[hard_regno
[nop
]];
1978 /* The constraints are made of several alternatives. Each operand's
1979 constraint looks like foo,bar,... with commas separating the
1980 alternatives. The first alternatives for all operands go
1981 together, the second alternatives go together, etc.
1983 First loop over alternatives. */
1984 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1985 if (only_alternative
>= 0)
1986 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1988 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1990 /* Loop over operands for one constraint alternative. */
1991 if (!TEST_BIT (preferred
, nalt
))
1994 curr_small_class_check
++;
1995 overall
= losers
= addr_losers
= 0;
1996 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
1997 for (nop
= 0; nop
< n_operands
; nop
++)
1999 int inc
= (curr_static_id
2000 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
2001 if (lra_dump_file
!= NULL
&& inc
!= 0)
2002 fprintf (lra_dump_file
,
2003 " Staticly defined alt reject+=%d\n", inc
);
2004 static_reject
+= inc
;
2006 reject
+= static_reject
;
2007 early_clobbered_regs_num
= 0;
2009 for (nop
= 0; nop
< n_operands
; nop
++)
2013 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2014 bool win
, did_match
, offmemok
, early_clobber_p
;
2015 /* false => this operand can be reloaded somehow for this
2018 /* true => this operand can be reloaded if the alternative
2021 /* True if a constant forced into memory would be OK for
2024 enum reg_class this_alternative
, this_costly_alternative
;
2025 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2026 bool this_alternative_match_win
, this_alternative_win
;
2027 bool this_alternative_offmemok
;
2030 enum constraint_num cn
;
2032 opalt_num
= nalt
* n_operands
+ nop
;
2033 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2035 /* Fast track for no constraints at all. */
2036 curr_alt
[nop
] = NO_REGS
;
2037 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2038 curr_alt_win
[nop
] = true;
2039 curr_alt_match_win
[nop
] = false;
2040 curr_alt_offmemok
[nop
] = false;
2041 curr_alt_matches
[nop
] = -1;
2045 op
= no_subreg_reg_operand
[nop
];
2046 mode
= curr_operand_mode
[nop
];
2048 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2051 early_clobber_p
= false;
2052 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2054 this_costly_alternative
= this_alternative
= NO_REGS
;
2055 /* We update set of possible hard regs besides its class
2056 because reg class might be inaccurate. For example,
2057 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2058 is translated in HI_REGS because classes are merged by
2059 pairs and there is no accurate intermediate class. */
2060 CLEAR_HARD_REG_SET (this_alternative_set
);
2061 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2062 this_alternative_win
= false;
2063 this_alternative_match_win
= false;
2064 this_alternative_offmemok
= false;
2065 this_alternative_matches
= -1;
2067 /* An empty constraint should be excluded by the fast
2069 lra_assert (*p
!= 0 && *p
!= ',');
2072 /* Scan this alternative's specs for this operand; set WIN
2073 if the operand fits any letter in this alternative.
2074 Otherwise, clear BADOP if this operand could fit some
2075 letter after reloads, or set WINREG if this operand could
2076 fit after reloads provided the constraint allows some
2081 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2091 early_clobber_p
= true;
2095 op_reject
+= LRA_MAX_REJECT
;
2098 op_reject
+= LRA_LOSER_COST_FACTOR
;
2102 /* Ignore rest of this alternative. */
2106 case '0': case '1': case '2': case '3': case '4':
2107 case '5': case '6': case '7': case '8': case '9':
2112 m
= strtoul (p
, &end
, 10);
2115 lra_assert (nop
> m
);
2117 /* Reject matches if we don't know which operand is
2118 bigger. This situation would arguably be a bug in
2119 an .md pattern, but could also occur in a user asm. */
2120 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2121 GET_MODE_SIZE (biggest_mode
[nop
])))
2124 this_alternative_matches
= m
;
2125 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2126 /* We are supposed to match a previous operand.
2127 If we do, we win if that one did. If we do
2128 not, count both of the operands as losers.
2129 (This is too conservative, since most of the
2130 time only a single reload insn will be needed
2131 to make the two operands win. As a result,
2132 this alternative may be rejected when it is
2133 actually desirable.) */
2135 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2136 *curr_id
->operand_loc
[m
], m_hregno
))
2138 /* We should reject matching of an early
2139 clobber operand if the matching operand is
2140 not dying in the insn. */
2141 if (! curr_static_id
->operand
[m
].early_clobber
2142 || operand_reg
[nop
] == NULL_RTX
2143 || (find_regno_note (curr_insn
, REG_DEAD
,
2145 || REGNO (op
) == REGNO (operand_reg
[m
])))
2150 /* If we are matching a non-offsettable
2151 address where an offsettable address was
2152 expected, then we must reject this
2153 combination, because we can't reload
2155 if (curr_alt_offmemok
[m
]
2156 && MEM_P (*curr_id
->operand_loc
[m
])
2157 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2162 /* Operands don't match. Both operands must
2163 allow a reload register, otherwise we
2164 cannot make them match. */
2165 if (curr_alt
[m
] == NO_REGS
)
2167 /* Retroactively mark the operand we had to
2168 match as a loser, if it wasn't already and
2169 it wasn't matched to a register constraint
2170 (e.g it might be matched by memory). */
2172 && (operand_reg
[m
] == NULL_RTX
2173 || hard_regno
[m
] < 0))
2177 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2178 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2181 /* Prefer matching earlyclobber alternative as
2182 it results in less hard regs required for
2183 the insn than a non-matching earlyclobber
2185 if (curr_static_id
->operand
[m
].early_clobber
)
2187 if (lra_dump_file
!= NULL
)
2190 " %d Matching earlyclobber alt:"
2195 /* Otherwise we prefer no matching
2196 alternatives because it gives more freedom
2198 else if (operand_reg
[nop
] == NULL_RTX
2199 || (find_regno_note (curr_insn
, REG_DEAD
,
2200 REGNO (operand_reg
[nop
]))
2203 if (lra_dump_file
!= NULL
)
2206 " %d Matching alt: reject+=2\n",
2211 /* If we have to reload this operand and some
2212 previous operand also had to match the same
2213 thing as this operand, we don't know how to do
2215 if (!match_p
|| !curr_alt_win
[m
])
2217 for (i
= 0; i
< nop
; i
++)
2218 if (curr_alt_matches
[i
] == m
)
2226 /* This can be fixed with reloads if the operand
2227 we are supposed to match can be fixed with
2230 this_alternative
= curr_alt
[m
];
2231 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2232 winreg
= this_alternative
!= NO_REGS
;
2238 || general_constant_p (op
)
2239 || spilled_pseudo_p (op
))
2245 cn
= lookup_constraint (p
);
2246 switch (get_constraint_type (cn
))
2249 cl
= reg_class_for_constraint (cn
);
2255 if (CONST_INT_P (op
)
2256 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2262 && satisfies_memory_constraint_p (op
, cn
))
2264 else if (spilled_pseudo_p (op
))
2267 /* If we didn't already win, we can reload constants
2268 via force_const_mem or put the pseudo value into
2269 memory, or make other memory by reloading the
2270 address like for 'o'. */
2271 if (CONST_POOL_OK_P (mode
, op
)
2272 || MEM_P (op
) || REG_P (op
)
2273 /* We can restore the equiv insn by a
2275 || equiv_substition_p
[nop
])
2282 /* If we didn't already win, we can reload the address
2283 into a base register. */
2284 if (satisfies_address_constraint_p (op
, cn
))
2286 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2292 if (constraint_satisfied_p (op
, cn
))
2296 case CT_SPECIAL_MEMORY
:
2298 && satisfies_memory_constraint_p (op
, cn
))
2300 else if (spilled_pseudo_p (op
))
2307 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2308 IOR_HARD_REG_SET (this_alternative_set
,
2309 reg_class_contents
[cl
]);
2312 this_costly_alternative
2313 = reg_class_subunion
[this_costly_alternative
][cl
];
2314 IOR_HARD_REG_SET (this_costly_alternative_set
,
2315 reg_class_contents
[cl
]);
2317 if (mode
== BLKmode
)
2322 if (hard_regno
[nop
] >= 0
2323 && in_hard_reg_set_p (this_alternative_set
,
2324 mode
, hard_regno
[nop
]))
2326 else if (hard_regno
[nop
] < 0
2327 && in_class_p (op
, this_alternative
, NULL
))
2332 if (c
!= ' ' && c
!= '\t')
2333 costly_p
= c
== '*';
2335 while ((p
+= len
), c
);
2337 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2338 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2339 /* Record which operands fit this alternative. */
2342 this_alternative_win
= true;
2343 if (operand_reg
[nop
] != NULL_RTX
)
2345 if (hard_regno
[nop
] >= 0)
2347 if (in_hard_reg_set_p (this_costly_alternative_set
,
2348 mode
, hard_regno
[nop
]))
2350 if (lra_dump_file
!= NULL
)
2351 fprintf (lra_dump_file
,
2352 " %d Costly set: reject++\n",
2359 /* Prefer won reg to spilled pseudo under other
2360 equal conditions for possibe inheritance. */
2363 if (lra_dump_file
!= NULL
)
2366 " %d Non pseudo reload: reject++\n",
2370 if (in_class_p (operand_reg
[nop
],
2371 this_costly_alternative
, NULL
))
2373 if (lra_dump_file
!= NULL
)
2376 " %d Non pseudo costly reload:"
2382 /* We simulate the behavior of old reload here.
2383 Although scratches need hard registers and it
2384 might result in spilling other pseudos, no reload
2385 insns are generated for the scratches. So it
2386 might cost something but probably less than old
2387 reload pass believes. */
2390 if (lra_dump_file
!= NULL
)
2391 fprintf (lra_dump_file
,
2392 " %d Scratch win: reject+=2\n",
2399 this_alternative_match_win
= true;
2402 int const_to_mem
= 0;
2405 reject
+= op_reject
;
2406 /* Never do output reload of stack pointer. It makes
2407 impossible to do elimination when SP is changed in
2409 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2410 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2413 /* If this alternative asks for a specific reg class, see if there
2414 is at least one allocatable register in that class. */
2416 = (this_alternative
== NO_REGS
2417 || (hard_reg_set_subset_p
2418 (reg_class_contents
[this_alternative
],
2419 lra_no_alloc_regs
)));
2421 /* For asms, verify that the class for this alternative is possible
2422 for the mode that is specified. */
2423 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2426 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2427 if (targetm
.hard_regno_mode_ok (i
, mode
)
2428 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2431 if (i
== FIRST_PSEUDO_REGISTER
)
2435 /* If this operand accepts a register, and if the
2436 register class has at least one allocatable register,
2437 then this operand can be reloaded. */
2438 if (winreg
&& !no_regs_p
)
2443 if (lra_dump_file
!= NULL
)
2444 fprintf (lra_dump_file
,
2445 " alt=%d: Bad operand -- refuse\n",
2450 if (this_alternative
!= NO_REGS
)
2452 HARD_REG_SET available_regs
;
2454 COPY_HARD_REG_SET (available_regs
,
2455 reg_class_contents
[this_alternative
]);
2456 AND_COMPL_HARD_REG_SET
2458 ira_prohibited_class_mode_regs
[this_alternative
][mode
]);
2459 AND_COMPL_HARD_REG_SET (available_regs
, lra_no_alloc_regs
);
2460 if (hard_reg_set_empty_p (available_regs
))
2462 /* There are no hard regs holding a value of given
2466 this_alternative
= NO_REGS
;
2467 if (lra_dump_file
!= NULL
)
2468 fprintf (lra_dump_file
,
2469 " %d Using memory because of"
2470 " a bad mode: reject+=2\n",
2476 if (lra_dump_file
!= NULL
)
2477 fprintf (lra_dump_file
,
2478 " alt=%d: Wrong mode -- refuse\n",
2485 /* If not assigned pseudo has a class which a subset of
2486 required reg class, it is a less costly alternative
2487 as the pseudo still can get a hard reg of necessary
2489 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2490 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2491 && ira_class_subset_p
[this_alternative
][cl
])
2493 if (lra_dump_file
!= NULL
)
2496 " %d Super set class reg: reject-=3\n", nop
);
2500 this_alternative_offmemok
= offmemok
;
2501 if (this_costly_alternative
!= NO_REGS
)
2503 if (lra_dump_file
!= NULL
)
2504 fprintf (lra_dump_file
,
2505 " %d Costly loser: reject++\n", nop
);
2508 /* If the operand is dying, has a matching constraint,
2509 and satisfies constraints of the matched operand
2510 which failed to satisfy the own constraints, most probably
2511 the reload for this operand will be gone. */
2512 if (this_alternative_matches
>= 0
2513 && !curr_alt_win
[this_alternative_matches
]
2515 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2516 && (hard_regno
[nop
] >= 0
2517 ? in_hard_reg_set_p (this_alternative_set
,
2518 mode
, hard_regno
[nop
])
2519 : in_class_p (op
, this_alternative
, NULL
)))
2521 if (lra_dump_file
!= NULL
)
2524 " %d Dying matched operand reload: reject++\n",
2530 /* Strict_low_part requires to reload the register
2531 not the sub-register. In this case we should
2532 check that a final reload hard reg can hold the
2534 if (curr_static_id
->operand
[nop
].strict_low
2536 && hard_regno
[nop
] < 0
2537 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2538 && ira_class_hard_regs_num
[this_alternative
] > 0
2539 && (!targetm
.hard_regno_mode_ok
2540 (ira_class_hard_regs
[this_alternative
][0],
2541 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2543 if (lra_dump_file
!= NULL
)
2546 " alt=%d: Strict low subreg reload -- refuse\n",
2552 if (operand_reg
[nop
] != NULL_RTX
2553 /* Output operands and matched input operands are
2554 not inherited. The following conditions do not
2555 exactly describe the previous statement but they
2556 are pretty close. */
2557 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2558 && (this_alternative_matches
< 0
2559 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2561 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2565 /* The value of reload_sum has sense only if we
2566 process insns in their order. It happens only on
2567 the first constraints sub-pass when we do most of
2569 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2570 reload_sum
+= last_reload
- bb_reload_num
;
2572 /* If this is a constant that is reloaded into the
2573 desired class by copying it to memory first, count
2574 that as another reload. This is consistent with
2575 other code and is required to avoid choosing another
2576 alternative when the constant is moved into memory.
2577 Note that the test here is precisely the same as in
2578 the code below that calls force_const_mem. */
2579 if (CONST_POOL_OK_P (mode
, op
)
2580 && ((targetm
.preferred_reload_class
2581 (op
, this_alternative
) == NO_REGS
)
2582 || no_input_reloads_p
))
2589 /* Alternative loses if it requires a type of reload not
2590 permitted for this insn. We can always reload
2591 objects with a REG_UNUSED note. */
2592 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2593 && no_output_reloads_p
2594 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2595 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2596 && no_input_reloads_p
&& ! const_to_mem
)
2597 || (this_alternative_matches
>= 0
2598 && (no_input_reloads_p
2599 || (no_output_reloads_p
2600 && (curr_static_id
->operand
2601 [this_alternative_matches
].type
!= OP_IN
)
2602 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2603 no_subreg_reg_operand
2604 [this_alternative_matches
])))))
2606 if (lra_dump_file
!= NULL
)
2609 " alt=%d: No input/otput reload -- refuse\n",
2614 /* Alternative loses if it required class pseudo can not
2615 hold value of required mode. Such insns can be
2616 described by insn definitions with mode iterators. */
2617 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2618 && ! hard_reg_set_empty_p (this_alternative_set
)
2619 /* It is common practice for constraints to use a
2620 class which does not have actually enough regs to
2621 hold the value (e.g. x86 AREG for mode requiring
2622 more one general reg). Therefore we have 2
2623 conditions to check that the reload pseudo can
2624 not hold the mode value. */
2625 && (!targetm
.hard_regno_mode_ok
2626 (ira_class_hard_regs
[this_alternative
][0],
2627 GET_MODE (*curr_id
->operand_loc
[nop
])))
2628 /* The above condition is not enough as the first
2629 reg in ira_class_hard_regs can be not aligned for
2630 multi-words mode values. */
2631 && (prohibited_class_reg_set_mode_p
2632 (this_alternative
, this_alternative_set
,
2633 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2635 if (lra_dump_file
!= NULL
)
2636 fprintf (lra_dump_file
,
2637 " alt=%d: reload pseudo for op %d "
2638 " can not hold the mode value -- refuse\n",
2643 /* Check strong discouragement of reload of non-constant
2644 into class THIS_ALTERNATIVE. */
2645 if (! CONSTANT_P (op
) && ! no_regs_p
2646 && (targetm
.preferred_reload_class
2647 (op
, this_alternative
) == NO_REGS
2648 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2649 && (targetm
.preferred_output_reload_class
2650 (op
, this_alternative
) == NO_REGS
))))
2652 if (lra_dump_file
!= NULL
)
2653 fprintf (lra_dump_file
,
2654 " %d Non-prefered reload: reject+=%d\n",
2655 nop
, LRA_MAX_REJECT
);
2656 reject
+= LRA_MAX_REJECT
;
2659 if (! (MEM_P (op
) && offmemok
)
2660 && ! (const_to_mem
&& constmemok
))
2662 /* We prefer to reload pseudos over reloading other
2663 things, since such reloads may be able to be
2664 eliminated later. So bump REJECT in other cases.
2665 Don't do this in the case where we are forcing a
2666 constant into memory and it will then win since
2667 we don't want to have a different alternative
2669 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2671 if (lra_dump_file
!= NULL
)
2674 " %d Non-pseudo reload: reject+=2\n",
2681 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2683 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2685 if (lra_dump_file
!= NULL
)
2688 " %d Small class reload: reject+=%d\n",
2689 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2690 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2694 /* We are trying to spill pseudo into memory. It is
2695 usually more costly than moving to a hard register
2696 although it might takes the same number of
2699 Non-pseudo spill may happen also. Suppose a target allows both
2700 register and memory in the operand constraint alternatives,
2701 then it's typical that an eliminable register has a substition
2702 of "base + offset" which can either be reloaded by a simple
2703 "new_reg <= base + offset" which will match the register
2704 constraint, or a similar reg addition followed by further spill
2705 to and reload from memory which will match the memory
2706 constraint, but this memory spill will be much more costly
2709 Code below increases the reject for both pseudo and non-pseudo
2712 && !(MEM_P (op
) && offmemok
)
2713 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2715 if (lra_dump_file
!= NULL
)
2718 " %d Spill %spseudo into memory: reject+=3\n",
2719 nop
, REG_P (op
) ? "" : "Non-");
2721 if (VECTOR_MODE_P (mode
))
2723 /* Spilling vectors into memory is usually more
2724 costly as they contain big values. */
2725 if (lra_dump_file
!= NULL
)
2728 " %d Spill vector pseudo: reject+=2\n",
2734 /* When we use an operand requiring memory in given
2735 alternative, the insn should write *and* read the
2736 value to/from memory it is costly in comparison with
2737 an insn alternative which does not use memory
2738 (e.g. register or immediate operand). We exclude
2739 memory operand for such case as we can satisfy the
2740 memory constraints by reloading address. */
2741 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
2743 if (lra_dump_file
!= NULL
)
2746 " Using memory insn operand %d: reject+=3\n",
2751 /* If reload requires moving value through secondary
2752 memory, it will need one more insn at least. */
2753 if (this_alternative
!= NO_REGS
2754 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2755 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2756 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
2758 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2759 && (targetm
.secondary_memory_needed
2760 (GET_MODE (op
), this_alternative
, cl
)))))
2763 /* Input reloads can be inherited more often than output
2764 reloads can be removed, so penalize output
2766 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2768 if (lra_dump_file
!= NULL
)
2771 " %d Non input pseudo reload: reject++\n",
2776 if (MEM_P (op
) && offmemok
)
2778 else if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
2780 if (lra_dump_file
!= NULL
)
2783 " %d Input/Output reload: reject+=%d\n",
2784 nop
, LRA_LOSER_COST_FACTOR
);
2785 reject
+= LRA_LOSER_COST_FACTOR
;
2789 if (early_clobber_p
&& ! scratch_p
)
2791 if (lra_dump_file
!= NULL
)
2792 fprintf (lra_dump_file
,
2793 " %d Early clobber: reject++\n", nop
);
2796 /* ??? We check early clobbers after processing all operands
2797 (see loop below) and there we update the costs more.
2798 Should we update the cost (may be approximately) here
2799 because of early clobber register reloads or it is a rare
2800 or non-important thing to be worth to do it. */
2801 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
2802 - (addr_losers
== losers
? static_reject
: 0));
2803 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2805 if (lra_dump_file
!= NULL
)
2806 fprintf (lra_dump_file
,
2807 " alt=%d,overall=%d,losers=%d -- refuse\n",
2808 nalt
, overall
, losers
);
2812 if (update_and_check_small_class_inputs (nop
, this_alternative
))
2814 if (lra_dump_file
!= NULL
)
2815 fprintf (lra_dump_file
,
2816 " alt=%d, not enough small class regs -- refuse\n",
2820 curr_alt
[nop
] = this_alternative
;
2821 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2822 curr_alt_win
[nop
] = this_alternative_win
;
2823 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2824 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2825 curr_alt_matches
[nop
] = this_alternative_matches
;
2827 if (this_alternative_matches
>= 0
2828 && !did_match
&& !this_alternative_win
)
2829 curr_alt_win
[this_alternative_matches
] = false;
2831 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2832 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2835 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2836 /* Prevent processing non-move insns. */
2837 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2838 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2839 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2840 && REG_P (no_subreg_reg_operand
[0])
2841 && REG_P (no_subreg_reg_operand
[1])
2842 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2843 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2844 || (! curr_alt_win
[0] && curr_alt_win
[1]
2845 && REG_P (no_subreg_reg_operand
[1])
2846 /* Check that we reload memory not the memory
2848 && ! (curr_alt_offmemok
[0]
2849 && MEM_P (no_subreg_reg_operand
[0]))
2850 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2851 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2852 && REG_P (no_subreg_reg_operand
[0])
2853 /* Check that we reload memory not the memory
2855 && ! (curr_alt_offmemok
[1]
2856 && MEM_P (no_subreg_reg_operand
[1]))
2857 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2858 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2859 no_subreg_reg_operand
[1])
2860 || (targetm
.preferred_reload_class
2861 (no_subreg_reg_operand
[1],
2862 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2863 /* If it is a result of recent elimination in move
2864 insn we can transform it into an add still by
2865 using this alternative. */
2866 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2868 /* We have a move insn and a new reload insn will be similar
2869 to the current insn. We should avoid such situation as
2870 it results in LRA cycling. */
2871 if (lra_dump_file
!= NULL
)
2872 fprintf (lra_dump_file
,
2873 " Cycle danger: overall += LRA_MAX_REJECT\n");
2874 overall
+= LRA_MAX_REJECT
;
2877 curr_alt_dont_inherit_ops_num
= 0;
2878 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2880 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2881 HARD_REG_SET temp_set
;
2883 i
= early_clobbered_nops
[nop
];
2884 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2885 || hard_regno
[i
] < 0)
2887 lra_assert (operand_reg
[i
] != NULL_RTX
);
2888 clobbered_hard_regno
= hard_regno
[i
];
2889 CLEAR_HARD_REG_SET (temp_set
);
2890 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2891 first_conflict_j
= last_conflict_j
= -1;
2892 for (j
= 0; j
< n_operands
; j
++)
2894 /* We don't want process insides of match_operator and
2895 match_parallel because otherwise we would process
2896 their operands once again generating a wrong
2898 || curr_static_id
->operand
[j
].is_operator
)
2900 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2901 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2903 /* If we don't reload j-th operand, check conflicts. */
2904 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2905 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2907 if (first_conflict_j
< 0)
2908 first_conflict_j
= j
;
2909 last_conflict_j
= j
;
2911 if (last_conflict_j
< 0)
2913 /* If earlyclobber operand conflicts with another
2914 non-matching operand which is actually the same register
2915 as the earlyclobber operand, it is better to reload the
2916 another operand as an operand matching the earlyclobber
2917 operand can be also the same. */
2918 if (first_conflict_j
== last_conflict_j
2919 && operand_reg
[last_conflict_j
] != NULL_RTX
2920 && ! curr_alt_match_win
[last_conflict_j
]
2921 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2923 curr_alt_win
[last_conflict_j
] = false;
2924 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2927 /* Early clobber was already reflected in REJECT. */
2928 lra_assert (reject
> 0);
2929 if (lra_dump_file
!= NULL
)
2932 " %d Conflict early clobber reload: reject--\n",
2935 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2939 /* We need to reload early clobbered register and the
2940 matched registers. */
2941 for (j
= 0; j
< n_operands
; j
++)
2942 if (curr_alt_matches
[j
] == i
)
2944 curr_alt_match_win
[j
] = false;
2946 overall
+= LRA_LOSER_COST_FACTOR
;
2948 if (! curr_alt_match_win
[i
])
2949 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2952 /* Remember pseudos used for match reloads are never
2954 lra_assert (curr_alt_matches
[i
] >= 0);
2955 curr_alt_win
[curr_alt_matches
[i
]] = false;
2957 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2959 /* Early clobber was already reflected in REJECT. */
2960 lra_assert (reject
> 0);
2961 if (lra_dump_file
!= NULL
)
2964 " %d Matched conflict early clobber reloads: "
2968 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2971 if (lra_dump_file
!= NULL
)
2972 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2973 nalt
, overall
, losers
, reload_nregs
);
2975 /* If this alternative can be made to work by reloading, and it
2976 needs less reloading than the others checked so far, record
2977 it as the chosen goal for reloading. */
2978 if ((best_losers
!= 0 && losers
== 0)
2979 || (((best_losers
== 0 && losers
== 0)
2980 || (best_losers
!= 0 && losers
!= 0))
2981 && (best_overall
> overall
2982 || (best_overall
== overall
2983 /* If the cost of the reloads is the same,
2984 prefer alternative which requires minimal
2985 number of reload regs. */
2986 && (reload_nregs
< best_reload_nregs
2987 || (reload_nregs
== best_reload_nregs
2988 && (best_reload_sum
< reload_sum
2989 || (best_reload_sum
== reload_sum
2990 && nalt
< goal_alt_number
))))))))
2992 for (nop
= 0; nop
< n_operands
; nop
++)
2994 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2995 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2996 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2997 goal_alt
[nop
] = curr_alt
[nop
];
2998 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3000 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3001 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3002 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3003 goal_alt_swapped
= curr_swapped
;
3004 best_overall
= overall
;
3005 best_losers
= losers
;
3006 best_reload_nregs
= reload_nregs
;
3007 best_reload_sum
= reload_sum
;
3008 goal_alt_number
= nalt
;
3011 /* Everything is satisfied. Do not process alternatives
3020 /* Make reload base reg from address AD. */
3022 base_to_reg (struct address_info
*ad
)
3026 rtx new_inner
= NULL_RTX
;
3027 rtx new_reg
= NULL_RTX
;
3029 rtx_insn
*last_insn
= get_last_insn();
3031 lra_assert (ad
->disp
== ad
->disp_term
);
3032 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3033 get_index_code (ad
));
3034 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
,
3036 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3037 ad
->disp_term
== NULL
3040 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3042 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3043 code
= recog_memoized (insn
);
3046 delete_insns_since (last_insn
);
3053 /* Make reload base reg + disp from address AD. Return the new pseudo. */
3055 base_plus_disp_to_reg (struct address_info
*ad
)
3060 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
3061 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3062 get_index_code (ad
));
3063 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
3065 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
3069 /* Make reload of index part of address AD. Return the new
3072 index_part_to_reg (struct address_info
*ad
)
3076 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3077 INDEX_REG_CLASS
, "index term");
3078 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3079 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3083 /* Return true if we can add a displacement to address AD, even if that
3084 makes the address invalid. The fix-up code requires any new address
3085 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3087 can_add_disp_p (struct address_info
*ad
)
3089 return (!ad
->autoinc_p
3090 && ad
->segment
== NULL
3091 && ad
->base
== ad
->base_term
3092 && ad
->disp
== ad
->disp_term
);
3095 /* Make equiv substitution in address AD. Return true if a substitution
3098 equiv_address_substitution (struct address_info
*ad
)
3100 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3102 HOST_WIDE_INT scale
;
3105 base_term
= strip_subreg (ad
->base_term
);
3106 if (base_term
== NULL
)
3107 base_reg
= new_base_reg
= NULL_RTX
;
3110 base_reg
= *base_term
;
3111 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3113 index_term
= strip_subreg (ad
->index_term
);
3114 if (index_term
== NULL
)
3115 index_reg
= new_index_reg
= NULL_RTX
;
3118 index_reg
= *index_term
;
3119 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3121 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3125 if (lra_dump_file
!= NULL
)
3127 fprintf (lra_dump_file
, "Changing address in insn %d ",
3128 INSN_UID (curr_insn
));
3129 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3131 if (base_reg
!= new_base_reg
)
3134 if (REG_P (new_base_reg
))
3136 *base_term
= new_base_reg
;
3139 else if (GET_CODE (new_base_reg
) == PLUS
3140 && REG_P (XEXP (new_base_reg
, 0))
3141 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3142 && can_add_disp_p (ad
))
3145 *base_term
= XEXP (new_base_reg
, 0);
3148 if (ad
->base_term2
!= NULL
)
3149 *ad
->base_term2
= *ad
->base_term
;
3151 if (index_reg
!= new_index_reg
)
3154 if (REG_P (new_index_reg
))
3156 *index_term
= new_index_reg
;
3159 else if (GET_CODE (new_index_reg
) == PLUS
3160 && REG_P (XEXP (new_index_reg
, 0))
3161 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3162 && can_add_disp_p (ad
)
3163 && (scale
= get_index_scale (ad
)))
3165 disp
+= offset
* scale
;
3166 *index_term
= XEXP (new_index_reg
, 0);
3170 if (maybe_ne (disp
, 0))
3172 if (ad
->disp
!= NULL
)
3173 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3176 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3177 update_address (ad
);
3181 if (lra_dump_file
!= NULL
)
3184 fprintf (lra_dump_file
, " -- no change\n");
3187 fprintf (lra_dump_file
, " on equiv ");
3188 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3189 fprintf (lra_dump_file
, "\n");
3195 /* Major function to make reloads for an address in operand NOP or
3196 check its correctness (If CHECK_ONLY_P is true). The supported
3199 1) an address that existed before LRA started, at which point it
3200 must have been valid. These addresses are subject to elimination
3201 and may have become invalid due to the elimination offset being out
3204 2) an address created by forcing a constant to memory
3205 (force_const_to_mem). The initial form of these addresses might
3206 not be valid, and it is this function's job to make them valid.
3208 3) a frame address formed from a register and a (possibly zero)
3209 constant offset. As above, these addresses might not be valid and
3210 this function must make them so.
3212 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3213 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3214 address. Return true for any RTL change.
3216 The function is a helper function which does not produce all
3217 transformations (when CHECK_ONLY_P is false) which can be
3218 necessary. It does just basic steps. To do all necessary
3219 transformations use function process_address. */
3221 process_address_1 (int nop
, bool check_only_p
,
3222 rtx_insn
**before
, rtx_insn
**after
)
3224 struct address_info ad
;
3226 HOST_WIDE_INT scale
;
3227 rtx op
= *curr_id
->operand_loc
[nop
];
3228 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3229 enum constraint_num cn
= lookup_constraint (constraint
);
3230 bool change_p
= false;
3233 && GET_MODE (op
) == BLKmode
3234 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3237 if (insn_extra_address_constraint (cn
))
3238 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3239 /* Do not attempt to decompose arbitrary addresses generated by combine
3240 for asm operands with loose constraints, e.g 'X'. */
3242 && !(INSN_CODE (curr_insn
) < 0
3243 && get_constraint_type (cn
) == CT_FIXED_FORM
3244 && constraint_satisfied_p (op
, cn
)))
3245 decompose_mem_address (&ad
, op
);
3246 else if (GET_CODE (op
) == SUBREG
3247 && MEM_P (SUBREG_REG (op
)))
3248 decompose_mem_address (&ad
, SUBREG_REG (op
));
3251 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3252 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3253 when INDEX_REG_CLASS is a single register class. */
3254 if (ad
.base_term
!= NULL
3255 && ad
.index_term
!= NULL
3256 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3257 && REG_P (*ad
.base_term
)
3258 && REG_P (*ad
.index_term
)
3259 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3260 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3262 std::swap (ad
.base
, ad
.index
);
3263 std::swap (ad
.base_term
, ad
.index_term
);
3266 change_p
= equiv_address_substitution (&ad
);
3267 if (ad
.base_term
!= NULL
3268 && (process_addr_reg
3269 (ad
.base_term
, check_only_p
, before
,
3271 && !(REG_P (*ad
.base_term
)
3272 && find_regno_note (curr_insn
, REG_DEAD
,
3273 REGNO (*ad
.base_term
)) != NULL_RTX
)
3275 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3276 get_index_code (&ad
)))))
3279 if (ad
.base_term2
!= NULL
)
3280 *ad
.base_term2
= *ad
.base_term
;
3282 if (ad
.index_term
!= NULL
3283 && process_addr_reg (ad
.index_term
, check_only_p
,
3284 before
, NULL
, INDEX_REG_CLASS
))
3287 /* Target hooks sometimes don't treat extra-constraint addresses as
3288 legitimate address_operands, so handle them specially. */
3289 if (insn_extra_address_constraint (cn
)
3290 && satisfies_address_constraint_p (&ad
, cn
))
3296 /* There are three cases where the shape of *AD.INNER may now be invalid:
3298 1) the original address was valid, but either elimination or
3299 equiv_address_substitution was applied and that made
3300 the address invalid.
3302 2) the address is an invalid symbolic address created by
3305 3) the address is a frame address with an invalid offset.
3307 4) the address is a frame address with an invalid base.
3309 All these cases involve a non-autoinc address, so there is no
3310 point revalidating other types. */
3311 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3314 /* Any index existed before LRA started, so we can assume that the
3315 presence and shape of the index is valid. */
3316 push_to_sequence (*before
);
3317 lra_assert (ad
.disp
== ad
.disp_term
);
3318 if (ad
.base
== NULL
)
3320 if (ad
.index
== NULL
)
3323 rtx_insn
*last
= get_last_insn ();
3325 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3327 rtx addr
= *ad
.inner
;
3329 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3332 /* addr => lo_sum (new_base, addr), case (2) above. */
3333 insn
= emit_insn (gen_rtx_SET
3335 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3336 code
= recog_memoized (insn
);
3339 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3340 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3342 /* Try to put lo_sum into register. */
3343 insn
= emit_insn (gen_rtx_SET
3345 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3346 code
= recog_memoized (insn
);
3349 *ad
.inner
= new_reg
;
3350 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3360 delete_insns_since (last
);
3365 /* addr => new_base, case (2) above. */
3366 lra_emit_move (new_reg
, addr
);
3368 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3370 insn
= NEXT_INSN (insn
))
3371 if (recog_memoized (insn
) < 0)
3373 if (insn
!= NULL_RTX
)
3375 /* Do nothing if we cannot generate right insns.
3376 This is analogous to reload pass behavior. */
3377 delete_insns_since (last
);
3381 *ad
.inner
= new_reg
;
3386 /* index * scale + disp => new base + index * scale,
3388 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3389 GET_CODE (*ad
.index
));
3391 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3392 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3393 lra_emit_move (new_reg
, *ad
.disp
);
3394 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3395 new_reg
, *ad
.index
);
3398 else if (ad
.index
== NULL
)
3403 rtx_insn
*insns
, *last_insn
;
3404 /* Try to reload base into register only if the base is invalid
3405 for the address but with valid offset, case (4) above. */
3407 new_reg
= base_to_reg (&ad
);
3409 /* base + disp => new base, cases (1) and (3) above. */
3410 /* Another option would be to reload the displacement into an
3411 index register. However, postreload has code to optimize
3412 address reloads that have the same base and different
3413 displacements, so reloading into an index register would
3414 not necessarily be a win. */
3415 if (new_reg
== NULL_RTX
)
3416 new_reg
= base_plus_disp_to_reg (&ad
);
3417 insns
= get_insns ();
3418 last_insn
= get_last_insn ();
3419 /* If we generated at least two insns, try last insn source as
3420 an address. If we succeed, we generate one less insn. */
3421 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3422 && GET_CODE (SET_SRC (set
)) == PLUS
3423 && REG_P (XEXP (SET_SRC (set
), 0))
3424 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3426 *ad
.inner
= SET_SRC (set
);
3427 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3429 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3430 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3431 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3432 get_index_code (&ad
));
3433 regno
= REGNO (*ad
.base_term
);
3434 if (regno
>= FIRST_PSEUDO_REGISTER
3435 && cl
!= lra_get_allocno_class (regno
))
3436 lra_change_class (regno
, cl
, " Change to", true);
3437 new_reg
= SET_SRC (set
);
3438 delete_insns_since (PREV_INSN (last_insn
));
3441 /* Try if target can split displacement into legitimite new disp
3442 and offset. If it's the case, we replace the last insn with
3443 insns for base + offset => new_reg and set new_reg + new disp
3445 last_insn
= get_last_insn ();
3446 if ((set
= single_set (last_insn
)) != NULL_RTX
3447 && GET_CODE (SET_SRC (set
)) == PLUS
3448 && REG_P (XEXP (SET_SRC (set
), 0))
3449 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3450 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3452 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3453 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3456 rtx_insn
*new_insns
;
3458 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3459 new_insns
= get_insns ();
3461 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3462 delete_insns_since (PREV_INSN (last_insn
));
3463 add_insn (new_insns
);
3464 insns
= get_insns ();
3469 *ad
.inner
= new_reg
;
3471 else if (ad
.disp_term
!= NULL
)
3473 /* base + scale * index + disp => new base + scale * index,
3475 new_reg
= base_plus_disp_to_reg (&ad
);
3476 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3477 new_reg
, *ad
.index
);
3479 else if ((scale
= get_index_scale (&ad
)) == 1)
3481 /* The last transformation to one reg will be made in
3482 curr_insn_transform function. */
3486 else if (scale
!= 0)
3488 /* base + scale * index => base + new_reg,
3490 Index part of address may become invalid. For example, we
3491 changed pseudo on the equivalent memory and a subreg of the
3492 pseudo onto the memory of different mode for which the scale is
3494 new_reg
= index_part_to_reg (&ad
);
3495 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3496 *ad
.base_term
, new_reg
);
3500 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3502 rtx addr
= *ad
.inner
;
3504 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3505 /* addr => new_base. */
3506 lra_emit_move (new_reg
, addr
);
3507 *ad
.inner
= new_reg
;
3509 *before
= get_insns ();
3514 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3515 Use process_address_1 as a helper function. Return true for any
3518 If CHECK_ONLY_P is true, just check address correctness. Return
3519 false if the address correct. */
3521 process_address (int nop
, bool check_only_p
,
3522 rtx_insn
**before
, rtx_insn
**after
)
3526 while (process_address_1 (nop
, check_only_p
, before
, after
))
3535 /* Emit insns to reload VALUE into a new register. VALUE is an
3536 auto-increment or auto-decrement RTX whose operand is a register or
3537 memory location; so reloading involves incrementing that location.
3538 IN is either identical to VALUE, or some cheaper place to reload
3539 value being incremented/decremented from.
3541 INC_AMOUNT is the number to increment or decrement by (always
3542 positive and ignored for POST_MODIFY/PRE_MODIFY).
3544 Return pseudo containing the result. */
3546 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, poly_int64 inc_amount
)
3548 /* REG or MEM to be copied and incremented. */
3549 rtx incloc
= XEXP (value
, 0);
3550 /* Nonzero if increment after copying. */
3551 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3552 || GET_CODE (value
) == POST_MODIFY
);
3557 rtx real_in
= in
== value
? incloc
: in
;
3561 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3563 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3564 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3565 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3566 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3567 inc
= XEXP (XEXP (value
, 1), 1);
3571 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3572 inc_amount
= -inc_amount
;
3574 inc
= gen_int_mode (inc_amount
, GET_MODE (value
));
3577 if (! post
&& REG_P (incloc
))
3580 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3583 if (real_in
!= result
)
3585 /* First copy the location to the result register. */
3586 lra_assert (REG_P (result
));
3587 emit_insn (gen_move_insn (result
, real_in
));
3590 /* We suppose that there are insns to add/sub with the constant
3591 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3592 old reload worked with this assumption. If the assumption
3593 becomes wrong, we should use approach in function
3594 base_plus_disp_to_reg. */
3597 /* See if we can directly increment INCLOC. */
3598 last
= get_last_insn ();
3599 add_insn
= emit_insn (plus_p
3600 ? gen_add2_insn (incloc
, inc
)
3601 : gen_sub2_insn (incloc
, inc
));
3603 code
= recog_memoized (add_insn
);
3606 if (! post
&& result
!= incloc
)
3607 emit_insn (gen_move_insn (result
, incloc
));
3610 delete_insns_since (last
);
3613 /* If couldn't do the increment directly, must increment in RESULT.
3614 The way we do this depends on whether this is pre- or
3615 post-increment. For pre-increment, copy INCLOC to the reload
3616 register, increment it there, then save back. */
3619 if (real_in
!= result
)
3620 emit_insn (gen_move_insn (result
, real_in
));
3622 emit_insn (gen_add2_insn (result
, inc
));
3624 emit_insn (gen_sub2_insn (result
, inc
));
3625 if (result
!= incloc
)
3626 emit_insn (gen_move_insn (incloc
, result
));
3632 Because this might be a jump insn or a compare, and because
3633 RESULT may not be available after the insn in an input
3634 reload, we must do the incrementing before the insn being
3637 We have already copied IN to RESULT. Increment the copy in
3638 RESULT, save that back, then decrement RESULT so it has
3639 the original value. */
3641 emit_insn (gen_add2_insn (result
, inc
));
3643 emit_insn (gen_sub2_insn (result
, inc
));
3644 emit_insn (gen_move_insn (incloc
, result
));
3645 /* Restore non-modified value for the result. We prefer this
3646 way because it does not require an additional hard
3651 if (poly_int_rtx_p (inc
, &offset
))
3652 emit_insn (gen_add2_insn (result
,
3653 gen_int_mode (-offset
,
3654 GET_MODE (result
))));
3656 emit_insn (gen_sub2_insn (result
, inc
));
3659 emit_insn (gen_add2_insn (result
, inc
));
3664 /* Return true if the current move insn does not need processing as we
3665 already know that it satisfies its constraints. */
3667 simple_move_p (void)
3670 enum reg_class dclass
, sclass
;
3672 lra_assert (curr_insn_set
!= NULL_RTX
);
3673 dest
= SET_DEST (curr_insn_set
);
3674 src
= SET_SRC (curr_insn_set
);
3676 /* If the instruction has multiple sets we need to process it even if it
3677 is single_set. This can happen if one or more of the SETs are dead.
3679 if (multiple_sets (curr_insn
))
3682 return ((dclass
= get_op_class (dest
)) != NO_REGS
3683 && (sclass
= get_op_class (src
)) != NO_REGS
3684 /* The backend guarantees that register moves of cost 2
3685 never need reloads. */
3686 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3689 /* Swap operands NOP and NOP + 1. */
3691 swap_operands (int nop
)
3693 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3694 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3695 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3696 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3697 /* Swap the duplicates too. */
3698 lra_update_dup (curr_id
, nop
);
3699 lra_update_dup (curr_id
, nop
+ 1);
3702 /* Main entry point of the constraint code: search the body of the
3703 current insn to choose the best alternative. It is mimicking insn
3704 alternative cost calculation model of former reload pass. That is
3705 because machine descriptions were written to use this model. This
3706 model can be changed in future. Make commutative operand exchange
3709 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3710 constraints. Return true if any change happened during function
3713 If CHECK_ONLY_P is true then don't do any transformation. Just
3714 check that the insn satisfies all constraints. If the insn does
3715 not satisfy any constraint, return true. */
3717 curr_insn_transform (bool check_only_p
)
3724 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3725 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3726 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3727 rtx_insn
*before
, *after
;
3729 /* Flag that the insn has been changed through a transformation. */
3733 int max_regno_before
;
3734 int reused_alternative_num
;
3736 curr_insn_set
= single_set (curr_insn
);
3737 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3740 no_input_reloads_p
= no_output_reloads_p
= false;
3741 goal_alt_number
= -1;
3742 change_p
= sec_mem_p
= false;
3743 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3744 reloads; neither are insns that SET cc0. Insns that use CC0 are
3745 not allowed to have any input reloads. */
3746 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3747 no_output_reloads_p
= true;
3749 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3750 no_input_reloads_p
= true;
3751 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3752 no_output_reloads_p
= true;
3754 n_operands
= curr_static_id
->n_operands
;
3755 n_alternatives
= curr_static_id
->n_alternatives
;
3757 /* Just return "no reloads" if insn has no operands with
3759 if (n_operands
== 0 || n_alternatives
== 0)
3762 max_regno_before
= max_reg_num ();
3764 for (i
= 0; i
< n_operands
; i
++)
3766 goal_alt_matched
[i
][0] = -1;
3767 goal_alt_matches
[i
] = -1;
3770 commutative
= curr_static_id
->commutative
;
3772 /* Now see what we need for pseudos that didn't get hard regs or got
3773 the wrong kind of hard reg. For this, we must consider all the
3774 operands together against the register constraints. */
3776 best_losers
= best_overall
= INT_MAX
;
3777 best_reload_sum
= 0;
3779 curr_swapped
= false;
3780 goal_alt_swapped
= false;
3783 /* Make equivalence substitution and memory subreg elimination
3784 before address processing because an address legitimacy can
3785 depend on memory mode. */
3786 for (i
= 0; i
< n_operands
; i
++)
3789 bool op_change_p
= false;
3791 if (curr_static_id
->operand
[i
].is_operator
)
3794 old
= op
= *curr_id
->operand_loc
[i
];
3795 if (GET_CODE (old
) == SUBREG
)
3796 old
= SUBREG_REG (old
);
3797 subst
= get_equiv_with_elimination (old
, curr_insn
);
3798 original_subreg_reg_mode
[i
] = VOIDmode
;
3799 equiv_substition_p
[i
] = false;
3802 equiv_substition_p
[i
] = true;
3803 subst
= copy_rtx (subst
);
3804 lra_assert (REG_P (old
));
3805 if (GET_CODE (op
) != SUBREG
)
3806 *curr_id
->operand_loc
[i
] = subst
;
3809 SUBREG_REG (op
) = subst
;
3810 if (GET_MODE (subst
) == VOIDmode
)
3811 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3813 if (lra_dump_file
!= NULL
)
3815 fprintf (lra_dump_file
,
3816 "Changing pseudo %d in operand %i of insn %u on equiv ",
3817 REGNO (old
), i
, INSN_UID (curr_insn
));
3818 dump_value_slim (lra_dump_file
, subst
, 1);
3819 fprintf (lra_dump_file
, "\n");
3821 op_change_p
= change_p
= true;
3823 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3826 lra_update_dup (curr_id
, i
);
3830 /* Reload address registers and displacements. We do it before
3831 finding an alternative because of memory constraints. */
3832 before
= after
= NULL
;
3833 for (i
= 0; i
< n_operands
; i
++)
3834 if (! curr_static_id
->operand
[i
].is_operator
3835 && process_address (i
, check_only_p
, &before
, &after
))
3840 lra_update_dup (curr_id
, i
);
3844 /* If we've changed the instruction then any alternative that
3845 we chose previously may no longer be valid. */
3846 lra_set_used_insn_alternative (curr_insn
, -1);
3848 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3849 && check_and_process_move (&change_p
, &sec_mem_p
))
3854 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3855 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3856 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3857 reused_alternative_num
, INSN_UID (curr_insn
));
3859 if (process_alt_operands (reused_alternative_num
))
3863 return ! alt_p
|| best_losers
!= 0;
3865 /* If insn is commutative (it's safe to exchange a certain pair of
3866 operands) then we need to try each alternative twice, the second
3867 time matching those two operands as if we had exchanged them. To
3868 do this, really exchange them in operands.
3870 If we have just tried the alternatives the second time, return
3871 operands to normal and drop through. */
3873 if (reused_alternative_num
< 0 && commutative
>= 0)
3875 curr_swapped
= !curr_swapped
;
3878 swap_operands (commutative
);
3882 swap_operands (commutative
);
3885 if (! alt_p
&& ! sec_mem_p
)
3887 /* No alternative works with reloads?? */
3888 if (INSN_CODE (curr_insn
) >= 0)
3889 fatal_insn ("unable to generate reloads for:", curr_insn
);
3890 error_for_asm (curr_insn
,
3891 "inconsistent operand constraints in an %<asm%>");
3892 /* Avoid further trouble with this insn. Don't generate use
3893 pattern here as we could use the insn SP offset. */
3894 lra_set_insn_deleted (curr_insn
);
3898 /* If the best alternative is with operands 1 and 2 swapped, swap
3899 them. Update the operand numbers of any reloads already
3902 if (goal_alt_swapped
)
3904 if (lra_dump_file
!= NULL
)
3905 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3906 INSN_UID (curr_insn
));
3908 /* Swap the duplicates too. */
3909 swap_operands (commutative
);
3913 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3914 too conservatively. So we use the secondary memory only if there
3915 is no any alternative without reloads. */
3916 use_sec_mem_p
= false;
3918 use_sec_mem_p
= true;
3921 for (i
= 0; i
< n_operands
; i
++)
3922 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3924 use_sec_mem_p
= i
< n_operands
;
3929 int in
= -1, out
= -1;
3930 rtx new_reg
, src
, dest
, rld
;
3931 machine_mode sec_mode
, rld_mode
;
3933 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3934 dest
= SET_DEST (curr_insn_set
);
3935 src
= SET_SRC (curr_insn_set
);
3936 for (i
= 0; i
< n_operands
; i
++)
3937 if (*curr_id
->operand_loc
[i
] == dest
)
3939 else if (*curr_id
->operand_loc
[i
] == src
)
3941 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3942 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3943 out
= curr_static_id
->dup_num
[i
];
3944 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3945 in
= curr_static_id
->dup_num
[i
];
3946 lra_assert (out
>= 0 && in
>= 0
3947 && curr_static_id
->operand
[out
].type
== OP_OUT
3948 && curr_static_id
->operand
[in
].type
== OP_IN
);
3949 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
3950 rld_mode
= GET_MODE (rld
);
3951 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
3952 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3953 NO_REGS
, "secondary");
3954 /* If the mode is changed, it should be wider. */
3955 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
3956 if (sec_mode
!= rld_mode
)
3958 /* If the target says specifically to use another mode for
3959 secondary memory moves we can not reuse the original
3961 after
= emit_spill_move (false, new_reg
, dest
);
3962 lra_process_new_insns (curr_insn
, NULL
, after
,
3963 "Inserting the sec. move");
3964 /* We may have non null BEFORE here (e.g. after address
3966 push_to_sequence (before
);
3967 before
= emit_spill_move (true, new_reg
, src
);
3969 before
= get_insns ();
3971 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3972 lra_set_insn_deleted (curr_insn
);
3974 else if (dest
== rld
)
3976 *curr_id
->operand_loc
[out
] = new_reg
;
3977 lra_update_dup (curr_id
, out
);
3978 after
= emit_spill_move (false, new_reg
, dest
);
3979 lra_process_new_insns (curr_insn
, NULL
, after
,
3980 "Inserting the sec. move");
3984 *curr_id
->operand_loc
[in
] = new_reg
;
3985 lra_update_dup (curr_id
, in
);
3986 /* See comments above. */
3987 push_to_sequence (before
);
3988 before
= emit_spill_move (true, new_reg
, src
);
3990 before
= get_insns ();
3992 lra_process_new_insns (curr_insn
, before
, NULL
,
3993 "Inserting the sec. move");
3995 lra_update_insn_regno_info (curr_insn
);
3999 lra_assert (goal_alt_number
>= 0);
4000 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
4002 if (lra_dump_file
!= NULL
)
4006 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4007 goal_alt_number
, INSN_UID (curr_insn
));
4008 for (i
= 0; i
< n_operands
; i
++)
4010 p
= (curr_static_id
->operand_alternative
4011 [goal_alt_number
* n_operands
+ i
].constraint
);
4014 fprintf (lra_dump_file
, " (%d) ", i
);
4015 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
4016 fputc (*p
, lra_dump_file
);
4018 if (INSN_CODE (curr_insn
) >= 0
4019 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4020 fprintf (lra_dump_file
, " {%s}", p
);
4021 if (maybe_ne (curr_id
->sp_offset
, 0))
4023 fprintf (lra_dump_file
, " (sp_off=");
4024 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4025 fprintf (lra_dump_file
, ")");
4027 fprintf (lra_dump_file
, "\n");
4030 /* Right now, for any pair of operands I and J that are required to
4031 match, with J < I, goal_alt_matches[I] is J. Add I to
4032 goal_alt_matched[J]. */
4034 for (i
= 0; i
< n_operands
; i
++)
4035 if ((j
= goal_alt_matches
[i
]) >= 0)
4037 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4039 /* We allow matching one output operand and several input
4042 || (curr_static_id
->operand
[j
].type
== OP_OUT
4043 && curr_static_id
->operand
[i
].type
== OP_IN
4044 && (curr_static_id
->operand
4045 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4046 goal_alt_matched
[j
][k
] = i
;
4047 goal_alt_matched
[j
][k
+ 1] = -1;
4050 for (i
= 0; i
< n_operands
; i
++)
4051 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4053 /* Any constants that aren't allowed and can't be reloaded into
4054 registers are here changed into memory references. */
4055 for (i
= 0; i
< n_operands
; i
++)
4056 if (goal_alt_win
[i
])
4059 enum reg_class new_class
;
4060 rtx reg
= *curr_id
->operand_loc
[i
];
4062 if (GET_CODE (reg
) == SUBREG
)
4063 reg
= SUBREG_REG (reg
);
4065 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4067 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4069 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4072 lra_change_class (regno
, new_class
, " Change to", true);
4078 const char *constraint
;
4080 rtx op
= *curr_id
->operand_loc
[i
];
4081 rtx subreg
= NULL_RTX
;
4082 machine_mode mode
= curr_operand_mode
[i
];
4084 if (GET_CODE (op
) == SUBREG
)
4087 op
= SUBREG_REG (op
);
4088 mode
= GET_MODE (op
);
4091 if (CONST_POOL_OK_P (mode
, op
)
4092 && ((targetm
.preferred_reload_class
4093 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4094 || no_input_reloads_p
))
4096 rtx tem
= force_const_mem (mode
, op
);
4099 if (subreg
!= NULL_RTX
)
4100 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4102 *curr_id
->operand_loc
[i
] = tem
;
4103 lra_update_dup (curr_id
, i
);
4104 process_address (i
, false, &before
, &after
);
4106 /* If the alternative accepts constant pool refs directly
4107 there will be no reload needed at all. */
4108 if (subreg
!= NULL_RTX
)
4110 /* Skip alternatives before the one requested. */
4111 constraint
= (curr_static_id
->operand_alternative
4112 [goal_alt_number
* n_operands
+ i
].constraint
);
4114 (c
= *constraint
) && c
!= ',' && c
!= '#';
4115 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4117 enum constraint_num cn
= lookup_constraint (constraint
);
4118 if ((insn_extra_memory_constraint (cn
)
4119 || insn_extra_special_memory_constraint (cn
))
4120 && satisfies_memory_constraint_p (tem
, cn
))
4123 if (c
== '\0' || c
== ',' || c
== '#')
4126 goal_alt_win
[i
] = true;
4132 for (i
= 0; i
< n_operands
; i
++)
4135 bool optional_p
= false;
4137 rtx op
= *curr_id
->operand_loc
[i
];
4139 if (goal_alt_win
[i
])
4141 if (goal_alt
[i
] == NO_REGS
4143 /* When we assign NO_REGS it means that we will not
4144 assign a hard register to the scratch pseudo by
4145 assigment pass and the scratch pseudo will be
4146 spilled. Spilled scratch pseudos are transformed
4147 back to scratches at the LRA end. */
4148 && lra_former_scratch_operand_p (curr_insn
, i
)
4149 && lra_former_scratch_p (REGNO (op
)))
4151 int regno
= REGNO (op
);
4152 lra_change_class (regno
, NO_REGS
, " Change to", true);
4153 if (lra_get_regno_hard_regno (regno
) >= 0)
4154 /* We don't have to mark all insn affected by the
4155 spilled pseudo as there is only one such insn, the
4157 reg_renumber
[regno
] = -1;
4158 lra_assert (bitmap_single_bit_set_p
4159 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4161 /* We can do an optional reload. If the pseudo got a hard
4162 reg, we might improve the code through inheritance. If
4163 it does not get a hard register we coalesce memory/memory
4164 moves later. Ignore move insns to avoid cycling. */
4166 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4167 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4168 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4169 && regno
< new_regno_start
4170 && ! lra_former_scratch_p (regno
)
4171 && reg_renumber
[regno
] < 0
4172 /* Check that the optional reload pseudo will be able to
4173 hold given mode value. */
4174 && ! (prohibited_class_reg_set_mode_p
4175 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4176 PSEUDO_REGNO_MODE (regno
)))
4177 && (curr_insn_set
== NULL_RTX
4178 || !((REG_P (SET_SRC (curr_insn_set
))
4179 || MEM_P (SET_SRC (curr_insn_set
))
4180 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4181 && (REG_P (SET_DEST (curr_insn_set
))
4182 || MEM_P (SET_DEST (curr_insn_set
))
4183 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4189 /* Operands that match previous ones have already been handled. */
4190 if (goal_alt_matches
[i
] >= 0)
4193 /* We should not have an operand with a non-offsettable address
4194 appearing where an offsettable address will do. It also may
4195 be a case when the address should be special in other words
4196 not a general one (e.g. it needs no index reg). */
4197 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4199 enum reg_class rclass
;
4200 rtx
*loc
= &XEXP (op
, 0);
4201 enum rtx_code code
= GET_CODE (*loc
);
4203 push_to_sequence (before
);
4204 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4206 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4207 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4208 /* This value does not matter for MODIFY. */
4209 GET_MODE_SIZE (GET_MODE (op
)));
4210 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4211 "offsetable address", &new_reg
))
4212 lra_emit_move (new_reg
, *loc
);
4213 before
= get_insns ();
4216 lra_update_dup (curr_id
, i
);
4218 else if (goal_alt_matched
[i
][0] == -1)
4223 enum op_type type
= curr_static_id
->operand
[i
].type
;
4225 loc
= curr_id
->operand_loc
[i
];
4226 mode
= curr_operand_mode
[i
];
4227 if (GET_CODE (*loc
) == SUBREG
)
4229 reg
= SUBREG_REG (*loc
);
4230 poly_int64 byte
= SUBREG_BYTE (*loc
);
4232 /* Strict_low_part requires reloading the register and not
4233 just the subreg. Likewise for a strict subreg no wider
4234 than a word for WORD_REGISTER_OPERATIONS targets. */
4235 && (curr_static_id
->operand
[i
].strict_low
4236 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4238 = get_try_hard_regno (REGNO (reg
))) >= 0
4239 && (simplify_subreg_regno
4241 GET_MODE (reg
), byte
, mode
) < 0)
4242 && (goal_alt
[i
] == NO_REGS
4243 || (simplify_subreg_regno
4244 (ira_class_hard_regs
[goal_alt
[i
]][0],
4245 GET_MODE (reg
), byte
, mode
) >= 0)))
4246 || (GET_MODE_PRECISION (mode
)
4247 < GET_MODE_PRECISION (GET_MODE (reg
))
4248 && GET_MODE_SIZE (GET_MODE (reg
)) <= UNITS_PER_WORD
4249 && WORD_REGISTER_OPERATIONS
)))
4251 /* An OP_INOUT is required when reloading a subreg of a
4252 mode wider than a word to ensure that data beyond the
4253 word being reloaded is preserved. Also automatically
4254 ensure that strict_low_part reloads are made into
4255 OP_INOUT which should already be true from the backend
4258 && (curr_static_id
->operand
[i
].strict_low
4259 || read_modify_subreg_p (*loc
)))
4261 loc
= &SUBREG_REG (*loc
);
4262 mode
= GET_MODE (*loc
);
4266 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4267 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4270 push_to_sequence (before
);
4271 lra_emit_move (new_reg
, old
);
4272 before
= get_insns ();
4277 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4280 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4282 after
= get_insns ();
4286 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4287 if (goal_alt_dont_inherit_ops
[j
] == i
)
4289 lra_set_regno_unique_value (REGNO (new_reg
));
4292 lra_update_dup (curr_id
, i
);
4294 else if (curr_static_id
->operand
[i
].type
== OP_IN
4295 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4297 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4299 && (operands_match_p
4300 (*curr_id
->operand_loc
[i
],
4301 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4304 /* generate reloads for input and matched outputs. */
4305 match_inputs
[0] = i
;
4306 match_inputs
[1] = -1;
4307 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4308 goal_alt
[i
], &before
, &after
,
4309 curr_static_id
->operand_alternative
4310 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4313 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4314 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4315 && (operands_match_p
4316 (*curr_id
->operand_loc
[i
],
4317 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4319 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4321 /* Generate reloads for output and matched inputs. */
4322 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4323 &after
, curr_static_id
->operand_alternative
4324 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4325 else if (curr_static_id
->operand
[i
].type
== OP_IN
4326 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4329 /* Generate reloads for matched inputs. */
4330 match_inputs
[0] = i
;
4331 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4332 match_inputs
[j
+ 1] = k
;
4333 match_inputs
[j
+ 1] = -1;
4334 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4338 /* We must generate code in any case when function
4339 process_alt_operands decides that it is possible. */
4342 /* Memorise processed outputs so that output remaining to be processed
4343 can avoid using the same register value (see match_reload). */
4344 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4346 outputs
[n_outputs
++] = i
;
4347 outputs
[n_outputs
] = -1;
4354 lra_assert (REG_P (reg
));
4355 regno
= REGNO (reg
);
4356 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4357 if (GET_CODE (op
) == SUBREG
)
4358 op
= SUBREG_REG (op
);
4359 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4360 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4361 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4362 if (lra_dump_file
!= NULL
)
4363 fprintf (lra_dump_file
,
4364 " Making reload reg %d for reg %d optional\n",
4368 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4369 || max_regno_before
!= max_reg_num ())
4373 lra_update_operator_dups (curr_id
);
4374 /* Something changes -- process the insn. */
4375 lra_update_insn_regno_info (curr_insn
);
4377 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4381 /* Return true if INSN satisfies all constraints. In other words, no
4382 reload insns are needed. */
4384 lra_constrain_insn (rtx_insn
*insn
)
4386 int saved_new_regno_start
= new_regno_start
;
4387 int saved_new_insn_uid_start
= new_insn_uid_start
;
4391 curr_id
= lra_get_insn_recog_data (curr_insn
);
4392 curr_static_id
= curr_id
->insn_static_data
;
4393 new_insn_uid_start
= get_max_uid ();
4394 new_regno_start
= max_reg_num ();
4395 change_p
= curr_insn_transform (true);
4396 new_regno_start
= saved_new_regno_start
;
4397 new_insn_uid_start
= saved_new_insn_uid_start
;
4401 /* Return true if X is in LIST. */
4403 in_list_p (rtx x
, rtx list
)
4405 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4406 if (XEXP (list
, 0) == x
)
4411 /* Return true if X contains an allocatable hard register (if
4412 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4414 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4420 code
= GET_CODE (x
);
4423 int regno
= REGNO (x
);
4424 HARD_REG_SET alloc_regs
;
4428 if (regno
>= FIRST_PSEUDO_REGISTER
)
4429 regno
= lra_get_regno_hard_regno (regno
);
4432 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4433 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4437 if (regno
< FIRST_PSEUDO_REGISTER
)
4441 return lra_get_regno_hard_regno (regno
) < 0;
4444 fmt
= GET_RTX_FORMAT (code
);
4445 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4449 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4452 else if (fmt
[i
] == 'E')
4454 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4455 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4462 /* Process all regs in location *LOC and change them on equivalent
4463 substitution. Return true if any change was done. */
4465 loc_equivalence_change_p (rtx
*loc
)
4467 rtx subst
, reg
, x
= *loc
;
4468 bool result
= false;
4469 enum rtx_code code
= GET_CODE (x
);
4475 reg
= SUBREG_REG (x
);
4476 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4477 && GET_MODE (subst
) == VOIDmode
)
4479 /* We cannot reload debug location. Simplify subreg here
4480 while we know the inner mode. */
4481 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4482 GET_MODE (reg
), SUBREG_BYTE (x
));
4486 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4492 /* Scan all the operand sub-expressions. */
4493 fmt
= GET_RTX_FORMAT (code
);
4494 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4497 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4498 else if (fmt
[i
] == 'E')
4499 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4501 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4506 /* Similar to loc_equivalence_change_p, but for use as
4507 simplify_replace_fn_rtx callback. DATA is insn for which the
4508 elimination is done. If it null we don't do the elimination. */
4510 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4515 rtx subst
= (data
== NULL
4516 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4523 /* Maximum number of generated reload insns per an insn. It is for
4524 preventing this pass cycling in a bug case. */
4525 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4527 /* The current iteration number of this LRA pass. */
4528 int lra_constraint_iter
;
4530 /* True if we substituted equiv which needs checking register
4531 allocation correctness because the equivalent value contains
4532 allocatable hard registers or when we restore multi-register
4534 bool lra_risky_transformations_p
;
4536 /* Return true if REGNO is referenced in more than one block. */
4538 multi_block_pseudo_p (int regno
)
4540 basic_block bb
= NULL
;
4544 if (regno
< FIRST_PSEUDO_REGISTER
)
4547 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4549 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4550 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4555 /* Return true if LIST contains a deleted insn. */
4557 contains_deleted_insn_p (rtx_insn_list
*list
)
4559 for (; list
!= NULL_RTX
; list
= list
->next ())
4560 if (NOTE_P (list
->insn ())
4561 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4566 /* Return true if X contains a pseudo dying in INSN. */
4568 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4575 return (insn
!= NULL_RTX
4576 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4577 code
= GET_CODE (x
);
4578 fmt
= GET_RTX_FORMAT (code
);
4579 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4583 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4586 else if (fmt
[i
] == 'E')
4588 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4589 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4596 /* Return true if INSN contains a dying pseudo in INSN right hand
4599 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4601 rtx set
= single_set (insn
);
4603 gcc_assert (set
!= NULL
);
4604 return dead_pseudo_p (SET_SRC (set
), insn
);
4607 /* Return true if any init insn of REGNO contains a dying pseudo in
4608 insn right hand side. */
4610 init_insn_rhs_dead_pseudo_p (int regno
)
4612 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4616 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4617 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4622 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4623 reverse only if we have one init insn with given REGNO as a
4626 reverse_equiv_p (int regno
)
4628 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4633 if (! INSN_P (insns
->insn ())
4634 || insns
->next () != NULL
)
4636 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4638 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4641 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4642 call this function only for non-reverse equivalence. */
4644 contains_reloaded_insn_p (int regno
)
4647 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4649 for (; list
!= NULL
; list
= list
->next ())
4650 if ((set
= single_set (list
->insn ())) == NULL_RTX
4651 || ! REG_P (SET_DEST (set
))
4652 || (int) REGNO (SET_DEST (set
)) != regno
)
4657 /* Entry function of LRA constraint pass. Return true if the
4658 constraint pass did change the code. */
4660 lra_constraints (bool first_p
)
4663 int i
, hard_regno
, new_insns_num
;
4664 unsigned int min_len
, new_min_len
, uid
;
4665 rtx set
, x
, reg
, dest_reg
;
4666 basic_block last_bb
;
4669 lra_constraint_iter
++;
4670 if (lra_dump_file
!= NULL
)
4671 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4672 lra_constraint_iter
);
4674 if (pic_offset_table_rtx
4675 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4676 lra_risky_transformations_p
= true;
4678 /* On the first iteration we should check IRA assignment
4679 correctness. In rare cases, the assignments can be wrong as
4680 early clobbers operands are ignored in IRA. */
4681 lra_risky_transformations_p
= first_p
;
4682 new_insn_uid_start
= get_max_uid ();
4683 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4684 /* Mark used hard regs for target stack size calulations. */
4685 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4686 if (lra_reg_info
[i
].nrefs
!= 0
4687 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4691 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
4692 for (j
= 0; j
< nregs
; j
++)
4693 df_set_regs_ever_live (hard_regno
+ j
, true);
4695 /* Do elimination before the equivalence processing as we can spill
4696 some pseudos during elimination. */
4697 lra_eliminate (false, first_p
);
4698 auto_bitmap
equiv_insn_bitmap (®_obstack
);
4699 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4700 if (lra_reg_info
[i
].nrefs
!= 0)
4702 ira_reg_equiv
[i
].profitable_p
= true;
4703 reg
= regno_reg_rtx
[i
];
4704 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4706 bool pseudo_p
= contains_reg_p (x
, false, false);
4708 /* After RTL transformation, we can not guarantee that
4709 pseudo in the substitution was not reloaded which might
4710 make equivalence invalid. For example, in reverse
4717 the memory address register was reloaded before the 2nd
4719 if ((! first_p
&& pseudo_p
)
4720 /* We don't use DF for compilation speed sake. So it
4721 is problematic to update live info when we use an
4722 equivalence containing pseudos in more than one
4724 || (pseudo_p
&& multi_block_pseudo_p (i
))
4725 /* If an init insn was deleted for some reason, cancel
4726 the equiv. We could update the equiv insns after
4727 transformations including an equiv insn deletion
4728 but it is not worthy as such cases are extremely
4730 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4731 /* If it is not a reverse equivalence, we check that a
4732 pseudo in rhs of the init insn is not dying in the
4733 insn. Otherwise, the live info at the beginning of
4734 the corresponding BB might be wrong after we
4735 removed the insn. When the equiv can be a
4736 constant, the right hand side of the init insn can
4738 || (! reverse_equiv_p (i
)
4739 && (init_insn_rhs_dead_pseudo_p (i
)
4740 /* If we reloaded the pseudo in an equivalence
4741 init insn, we can not remove the equiv init
4742 insns and the init insns might write into
4743 const memory in this case. */
4744 || contains_reloaded_insn_p (i
)))
4745 /* Prevent access beyond equivalent memory for
4746 paradoxical subregs. */
4748 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4749 > GET_MODE_SIZE (GET_MODE (x
))))
4750 || (pic_offset_table_rtx
4751 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4752 && (targetm
.preferred_reload_class
4753 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4754 || contains_symbol_ref_p (x
))))
4755 ira_reg_equiv
[i
].defined_p
= false;
4756 if (contains_reg_p (x
, false, true))
4757 ira_reg_equiv
[i
].profitable_p
= false;
4758 if (get_equiv (reg
) != reg
)
4759 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4762 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4764 /* We should add all insns containing pseudos which should be
4765 substituted by their equivalences. */
4766 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
4767 lra_push_insn_by_uid (uid
);
4768 min_len
= lra_insn_stack_length ();
4772 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4774 curr_insn
= lra_pop_insn ();
4776 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4777 if (curr_bb
!= last_bb
)
4780 bb_reload_num
= lra_curr_reload_num
;
4782 if (min_len
> new_min_len
)
4784 min_len
= new_min_len
;
4787 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4789 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4790 MAX_RELOAD_INSNS_NUMBER
);
4792 if (DEBUG_INSN_P (curr_insn
))
4794 /* We need to check equivalence in debug insn and change
4795 pseudo to the equivalent value if necessary. */
4796 curr_id
= lra_get_insn_recog_data (curr_insn
);
4797 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4799 rtx old
= *curr_id
->operand_loc
[0];
4800 *curr_id
->operand_loc
[0]
4801 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4802 loc_equivalence_callback
, curr_insn
);
4803 if (old
!= *curr_id
->operand_loc
[0])
4805 lra_update_insn_regno_info (curr_insn
);
4810 else if (INSN_P (curr_insn
))
4812 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4814 dest_reg
= SET_DEST (set
);
4815 /* The equivalence pseudo could be set up as SUBREG in a
4816 case when it is a call restore insn in a mode
4817 different from the pseudo mode. */
4818 if (GET_CODE (dest_reg
) == SUBREG
)
4819 dest_reg
= SUBREG_REG (dest_reg
);
4820 if ((REG_P (dest_reg
)
4821 && (x
= get_equiv (dest_reg
)) != dest_reg
4822 /* Remove insns which set up a pseudo whose value
4823 can not be changed. Such insns might be not in
4824 init_insns because we don't update equiv data
4825 during insn transformations.
4827 As an example, let suppose that a pseudo got
4828 hard register and on the 1st pass was not
4829 changed to equivalent constant. We generate an
4830 additional insn setting up the pseudo because of
4831 secondary memory movement. Then the pseudo is
4832 spilled and we use the equiv constant. In this
4833 case we should remove the additional insn and
4834 this insn is not init_insns list. */
4835 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4836 /* Check that this is actually an insn setting
4837 up the equivalence. */
4838 || in_list_p (curr_insn
,
4840 [REGNO (dest_reg
)].init_insns
)))
4841 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4842 && in_list_p (curr_insn
,
4844 [REGNO (SET_SRC (set
))].init_insns
)))
4846 /* This is equiv init insn of pseudo which did not get a
4847 hard register -- remove the insn. */
4848 if (lra_dump_file
!= NULL
)
4850 fprintf (lra_dump_file
,
4851 " Removing equiv init insn %i (freq=%d)\n",
4852 INSN_UID (curr_insn
),
4853 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4854 dump_insn_slim (lra_dump_file
, curr_insn
);
4856 if (contains_reg_p (x
, true, false))
4857 lra_risky_transformations_p
= true;
4858 lra_set_insn_deleted (curr_insn
);
4862 curr_id
= lra_get_insn_recog_data (curr_insn
);
4863 curr_static_id
= curr_id
->insn_static_data
;
4864 init_curr_insn_input_reloads ();
4865 init_curr_operand_mode ();
4866 if (curr_insn_transform (false))
4868 /* Check non-transformed insns too for equiv change as USE
4869 or CLOBBER don't need reloads but can contain pseudos
4870 being changed on their equivalences. */
4871 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
4872 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4874 lra_update_insn_regno_info (curr_insn
);
4880 /* If we used a new hard regno, changed_p should be true because the
4881 hard reg is assigned to a new pseudo. */
4882 if (flag_checking
&& !changed_p
)
4884 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4885 if (lra_reg_info
[i
].nrefs
!= 0
4886 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4888 int j
, nregs
= hard_regno_nregs (hard_regno
,
4889 PSEUDO_REGNO_MODE (i
));
4891 for (j
= 0; j
< nregs
; j
++)
4892 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4898 static void initiate_invariants (void);
4899 static void finish_invariants (void);
4901 /* Initiate the LRA constraint pass. It is done once per
4904 lra_constraints_init (void)
4906 initiate_invariants ();
4909 /* Finalize the LRA constraint pass. It is done once per
4912 lra_constraints_finish (void)
4914 finish_invariants ();
4919 /* Structure describes invariants for ineheritance. */
4920 struct lra_invariant
4922 /* The order number of the invariant. */
4924 /* The invariant RTX. */
4926 /* The origin insn of the invariant. */
4930 typedef lra_invariant invariant_t
;
4931 typedef invariant_t
*invariant_ptr_t
;
4932 typedef const invariant_t
*const_invariant_ptr_t
;
4934 /* Pointer to the inheritance invariants. */
4935 static vec
<invariant_ptr_t
> invariants
;
4937 /* Allocation pool for the invariants. */
4938 static object_allocator
<lra_invariant
> *invariants_pool
;
4940 /* Hash table for the invariants. */
4941 static htab_t invariant_table
;
4943 /* Hash function for INVARIANT. */
4945 invariant_hash (const void *invariant
)
4947 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
4948 return lra_rtx_hash (inv
);
4951 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4953 invariant_eq_p (const void *invariant1
, const void *invariant2
)
4955 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
4956 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
4958 return rtx_equal_p (inv1
, inv2
);
4961 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
4962 invariant which is in the table. */
4963 static invariant_ptr_t
4964 insert_invariant (rtx invariant_rtx
)
4967 invariant_t invariant
;
4968 invariant_ptr_t invariant_ptr
;
4970 invariant
.invariant_rtx
= invariant_rtx
;
4971 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
4972 if (*entry_ptr
== NULL
)
4974 invariant_ptr
= invariants_pool
->allocate ();
4975 invariant_ptr
->invariant_rtx
= invariant_rtx
;
4976 invariant_ptr
->insn
= NULL
;
4977 invariants
.safe_push (invariant_ptr
);
4978 *entry_ptr
= (void *) invariant_ptr
;
4980 return (invariant_ptr_t
) *entry_ptr
;
4983 /* Initiate the invariant table. */
4985 initiate_invariants (void)
4987 invariants
.create (100);
4989 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
4990 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
4993 /* Finish the invariant table. */
4995 finish_invariants (void)
4997 htab_delete (invariant_table
);
4998 delete invariants_pool
;
4999 invariants
.release ();
5002 /* Make the invariant table empty. */
5004 clear_invariants (void)
5006 htab_empty (invariant_table
);
5007 invariants_pool
->release ();
5008 invariants
.truncate (0);
5013 /* This page contains code to do inheritance/split
5016 /* Number of reloads passed so far in current EBB. */
5017 static int reloads_num
;
5019 /* Number of calls passed so far in current EBB. */
5020 static int calls_num
;
5022 /* Current reload pseudo check for validity of elements in
5024 static int curr_usage_insns_check
;
5026 /* Info about last usage of registers in EBB to do inheritance/split
5027 transformation. Inheritance transformation is done from a spilled
5028 pseudo and split transformations from a hard register or a pseudo
5029 assigned to a hard register. */
5032 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5033 value INSNS is valid. The insns is chain of optional debug insns
5034 and a finishing non-debug insn using the corresponding reg. The
5035 value is also used to mark the registers which are set up in the
5036 current insn. The negated insn uid is used for this. */
5038 /* Value of global reloads_num at the last insn in INSNS. */
5040 /* Value of global reloads_nums at the last insn in INSNS. */
5042 /* It can be true only for splitting. And it means that the restore
5043 insn should be put after insn given by the following member. */
5045 /* Next insns in the current EBB which use the original reg and the
5046 original reg value is not changed between the current insn and
5047 the next insns. In order words, e.g. for inheritance, if we need
5048 to use the original reg value again in the next insns we can try
5049 to use the value in a hard register from a reload insn of the
5054 /* Map: regno -> corresponding pseudo usage insns. */
5055 static struct usage_insns
*usage_insns
;
5058 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5060 usage_insns
[regno
].check
= curr_usage_insns_check
;
5061 usage_insns
[regno
].insns
= insn
;
5062 usage_insns
[regno
].reloads_num
= reloads_num
;
5063 usage_insns
[regno
].calls_num
= calls_num
;
5064 usage_insns
[regno
].after_p
= after_p
;
5067 /* The function is used to form list REGNO usages which consists of
5068 optional debug insns finished by a non-debug insn using REGNO.
5069 RELOADS_NUM is current number of reload insns processed so far. */
5071 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5073 rtx next_usage_insns
;
5075 if (usage_insns
[regno
].check
== curr_usage_insns_check
5076 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5077 && DEBUG_INSN_P (insn
))
5079 /* Check that we did not add the debug insn yet. */
5080 if (next_usage_insns
!= insn
5081 && (GET_CODE (next_usage_insns
) != INSN_LIST
5082 || XEXP (next_usage_insns
, 0) != insn
))
5083 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5086 else if (NONDEBUG_INSN_P (insn
))
5087 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5089 usage_insns
[regno
].check
= 0;
5092 /* Return first non-debug insn in list USAGE_INSNS. */
5094 skip_usage_debug_insns (rtx usage_insns
)
5098 /* Skip debug insns. */
5099 for (insn
= usage_insns
;
5100 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5101 insn
= XEXP (insn
, 1))
5103 return safe_as_a
<rtx_insn
*> (insn
);
5106 /* Return true if we need secondary memory moves for insn in
5107 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5110 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5111 rtx usage_insns ATTRIBUTE_UNUSED
)
5117 if (inher_cl
== ALL_REGS
5118 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5120 lra_assert (INSN_P (insn
));
5121 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5123 dest
= SET_DEST (set
);
5126 lra_assert (inher_cl
!= NO_REGS
);
5127 cl
= get_reg_class (REGNO (dest
));
5128 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5129 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5132 /* Registers involved in inheritance/split in the current EBB
5133 (inheritance/split pseudos and original registers). */
5134 static bitmap_head check_only_regs
;
5136 /* Reload pseudos can not be involded in invariant inheritance in the
5138 static bitmap_head invalid_invariant_regs
;
5140 /* Do inheritance transformations for insn INSN, which defines (if
5141 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5142 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5143 form as the "insns" field of usage_insns. Return true if we
5144 succeed in such transformation.
5146 The transformations look like:
5149 ... p <- i (new insn)
5151 <- ... p ... <- ... i ...
5153 ... i <- p (new insn)
5154 <- ... p ... <- ... i ...
5156 <- ... p ... <- ... i ...
5157 where p is a spilled original pseudo and i is a new inheritance pseudo.
5160 The inheritance pseudo has the smallest class of two classes CL and
5161 class of ORIGINAL REGNO. */
5163 inherit_reload_reg (bool def_p
, int original_regno
,
5164 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5166 if (optimize_function_for_size_p (cfun
))
5169 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5170 rtx original_reg
= regno_reg_rtx
[original_regno
];
5171 rtx new_reg
, usage_insn
;
5172 rtx_insn
*new_insns
;
5174 lra_assert (! usage_insns
[original_regno
].after_p
);
5175 if (lra_dump_file
!= NULL
)
5176 fprintf (lra_dump_file
,
5177 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5178 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5180 if (lra_dump_file
!= NULL
)
5182 fprintf (lra_dump_file
,
5183 " Rejecting inheritance for %d "
5184 "because of disjoint classes %s and %s\n",
5185 original_regno
, reg_class_names
[cl
],
5186 reg_class_names
[rclass
]);
5187 fprintf (lra_dump_file
,
5188 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5192 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5193 /* We don't use a subset of two classes because it can be
5194 NO_REGS. This transformation is still profitable in most
5195 cases even if the classes are not intersected as register
5196 move is probably cheaper than a memory load. */
5197 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5199 if (lra_dump_file
!= NULL
)
5200 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5201 reg_class_names
[cl
], reg_class_names
[rclass
]);
5205 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5207 /* Reject inheritance resulting in secondary memory moves.
5208 Otherwise, there is a danger in LRA cycling. Also such
5209 transformation will be unprofitable. */
5210 if (lra_dump_file
!= NULL
)
5212 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5213 rtx set
= single_set (insn
);
5215 lra_assert (set
!= NULL_RTX
);
5217 rtx dest
= SET_DEST (set
);
5219 lra_assert (REG_P (dest
));
5220 fprintf (lra_dump_file
,
5221 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5222 "as secondary mem is needed\n",
5223 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5224 original_regno
, reg_class_names
[rclass
]);
5225 fprintf (lra_dump_file
,
5226 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5230 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5231 rclass
, "inheritance");
5234 lra_emit_move (original_reg
, new_reg
);
5236 lra_emit_move (new_reg
, original_reg
);
5237 new_insns
= get_insns ();
5239 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5241 if (lra_dump_file
!= NULL
)
5243 fprintf (lra_dump_file
,
5244 " Rejecting inheritance %d->%d "
5245 "as it results in 2 or more insns:\n",
5246 original_regno
, REGNO (new_reg
));
5247 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5248 fprintf (lra_dump_file
,
5249 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5253 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5254 lra_update_insn_regno_info (insn
);
5256 /* We now have a new usage insn for original regno. */
5257 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5258 if (lra_dump_file
!= NULL
)
5259 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5260 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5261 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5262 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5263 bitmap_set_bit (&check_only_regs
, original_regno
);
5264 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5266 lra_process_new_insns (insn
, NULL
, new_insns
,
5267 "Add original<-inheritance");
5269 lra_process_new_insns (insn
, new_insns
, NULL
,
5270 "Add inheritance<-original");
5271 while (next_usage_insns
!= NULL_RTX
)
5273 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5275 usage_insn
= next_usage_insns
;
5276 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5277 next_usage_insns
= NULL
;
5281 usage_insn
= XEXP (next_usage_insns
, 0);
5282 lra_assert (DEBUG_INSN_P (usage_insn
));
5283 next_usage_insns
= XEXP (next_usage_insns
, 1);
5285 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5286 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5287 if (lra_dump_file
!= NULL
)
5289 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5290 fprintf (lra_dump_file
,
5291 " Inheritance reuse change %d->%d (bb%d):\n",
5292 original_regno
, REGNO (new_reg
),
5293 bb
? bb
->index
: -1);
5294 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5297 if (lra_dump_file
!= NULL
)
5298 fprintf (lra_dump_file
,
5299 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5303 /* Return true if we need a caller save/restore for pseudo REGNO which
5304 was assigned to a hard register. */
5306 need_for_call_save_p (int regno
)
5308 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5309 return (usage_insns
[regno
].calls_num
< calls_num
5310 && (overlaps_hard_reg_set_p
5312 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
5313 ? lra_reg_info
[regno
].actual_call_used_reg_set
5314 : call_used_reg_set
,
5315 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
5316 || (targetm
.hard_regno_call_part_clobbered
5317 (reg_renumber
[regno
], PSEUDO_REGNO_MODE (regno
)))));
5320 /* Global registers occurring in the current EBB. */
5321 static bitmap_head ebb_global_regs
;
5323 /* Return true if we need a split for hard register REGNO or pseudo
5324 REGNO which was assigned to a hard register.
5325 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5326 used for reloads since the EBB end. It is an approximation of the
5327 used hard registers in the split range. The exact value would
5328 require expensive calculations. If we were aggressive with
5329 splitting because of the approximation, the split pseudo will save
5330 the same hard register assignment and will be removed in the undo
5331 pass. We still need the approximation because too aggressive
5332 splitting would result in too inaccurate cost calculation in the
5333 assignment pass because of too many generated moves which will be
5334 probably removed in the undo pass. */
5336 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5338 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5340 lra_assert (hard_regno
>= 0);
5341 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5342 /* Don't split eliminable hard registers, otherwise we can
5343 split hard registers like hard frame pointer, which
5344 lives on BB start/end according to DF-infrastructure,
5345 when there is a pseudo assigned to the register and
5346 living in the same BB. */
5347 && (regno
>= FIRST_PSEUDO_REGISTER
5348 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5349 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5350 /* Don't split call clobbered hard regs living through
5351 calls, otherwise we might have a check problem in the
5352 assign sub-pass as in the most cases (exception is a
5353 situation when lra_risky_transformations_p value is
5354 true) the assign pass assumes that all pseudos living
5355 through calls are assigned to call saved hard regs. */
5356 && (regno
>= FIRST_PSEUDO_REGISTER
5357 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
5358 || usage_insns
[regno
].calls_num
== calls_num
)
5359 /* We need at least 2 reloads to make pseudo splitting
5360 profitable. We should provide hard regno splitting in
5361 any case to solve 1st insn scheduling problem when
5362 moving hard register definition up might result in
5363 impossibility to find hard register for reload pseudo of
5364 small register class. */
5365 && (usage_insns
[regno
].reloads_num
5366 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5367 && (regno
< FIRST_PSEUDO_REGISTER
5368 /* For short living pseudos, spilling + inheritance can
5369 be considered a substitution for splitting.
5370 Therefore we do not splitting for local pseudos. It
5371 decreases also aggressiveness of splitting. The
5372 minimal number of references is chosen taking into
5373 account that for 2 references splitting has no sense
5374 as we can just spill the pseudo. */
5375 || (regno
>= FIRST_PSEUDO_REGISTER
5376 && lra_reg_info
[regno
].nrefs
> 3
5377 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5378 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5381 /* Return class for the split pseudo created from original pseudo with
5382 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5383 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5384 results in no secondary memory movements. */
5385 static enum reg_class
5386 choose_split_class (enum reg_class allocno_class
,
5387 int hard_regno ATTRIBUTE_UNUSED
,
5388 machine_mode mode ATTRIBUTE_UNUSED
)
5391 enum reg_class cl
, best_cl
= NO_REGS
;
5392 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5393 = REGNO_REG_CLASS (hard_regno
);
5395 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
5396 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5397 return allocno_class
;
5399 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5401 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
5402 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
5403 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5404 && (best_cl
== NO_REGS
5405 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5410 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5411 It only makes sense to call this function if NEW_REGNO is always
5412 equal to ORIGINAL_REGNO. */
5415 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
)
5417 if (!ira_reg_equiv
[original_regno
].defined_p
)
5420 ira_expand_reg_equiv ();
5421 ira_reg_equiv
[new_regno
].defined_p
= true;
5422 if (ira_reg_equiv
[original_regno
].memory
)
5423 ira_reg_equiv
[new_regno
].memory
5424 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5425 if (ira_reg_equiv
[original_regno
].constant
)
5426 ira_reg_equiv
[new_regno
].constant
5427 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5428 if (ira_reg_equiv
[original_regno
].invariant
)
5429 ira_reg_equiv
[new_regno
].invariant
5430 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
5433 /* Do split transformations for insn INSN, which defines or uses
5434 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5435 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5436 "insns" field of usage_insns.
5438 The transformations look like:
5441 ... s <- p (new insn -- save)
5443 ... p <- s (new insn -- restore)
5444 <- ... p ... <- ... p ...
5446 <- ... p ... <- ... p ...
5447 ... s <- p (new insn -- save)
5449 ... p <- s (new insn -- restore)
5450 <- ... p ... <- ... p ...
5452 where p is an original pseudo got a hard register or a hard
5453 register and s is a new split pseudo. The save is put before INSN
5454 if BEFORE_P is true. Return true if we succeed in such
5457 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5458 rtx next_usage_insns
)
5460 enum reg_class rclass
;
5462 int hard_regno
, nregs
;
5463 rtx new_reg
, usage_insn
;
5464 rtx_insn
*restore
, *save
;
5469 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5471 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5472 hard_regno
= original_regno
;
5473 call_save_p
= false;
5475 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5476 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5477 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5478 as part of a multi-word register. In that case, or if the biggest
5479 mode was larger than a register, just use the reg_rtx. Otherwise,
5480 limit the size to that of the biggest access in the function. */
5481 if (mode
== VOIDmode
5482 || paradoxical_subreg_p (mode
, reg_rtx_mode
))
5484 original_reg
= regno_reg_rtx
[hard_regno
];
5485 mode
= reg_rtx_mode
;
5488 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5492 mode
= PSEUDO_REGNO_MODE (original_regno
);
5493 hard_regno
= reg_renumber
[original_regno
];
5494 nregs
= hard_regno_nregs (hard_regno
, mode
);
5495 rclass
= lra_get_allocno_class (original_regno
);
5496 original_reg
= regno_reg_rtx
[original_regno
];
5497 call_save_p
= need_for_call_save_p (original_regno
);
5499 lra_assert (hard_regno
>= 0);
5500 if (lra_dump_file
!= NULL
)
5501 fprintf (lra_dump_file
,
5502 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5506 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5507 hard_regno_nregs (hard_regno
, mode
),
5509 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5513 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5514 if (rclass
== NO_REGS
)
5516 if (lra_dump_file
!= NULL
)
5518 fprintf (lra_dump_file
,
5519 " Rejecting split of %d(%s): "
5520 "no good reg class for %d(%s)\n",
5522 reg_class_names
[lra_get_allocno_class (original_regno
)],
5524 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5527 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5531 /* Split_if_necessary can split hard registers used as part of a
5532 multi-register mode but splits each register individually. The
5533 mode used for each independent register may not be supported
5534 so reject the split. Splitting the wider mode should theoretically
5535 be possible but is not implemented. */
5536 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
5538 if (lra_dump_file
!= NULL
)
5540 fprintf (lra_dump_file
,
5541 " Rejecting split of %d(%s): unsuitable mode %s\n",
5543 reg_class_names
[lra_get_allocno_class (original_regno
)],
5544 GET_MODE_NAME (mode
));
5547 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5551 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5552 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5554 int new_regno
= REGNO (new_reg
);
5555 save
= emit_spill_move (true, new_reg
, original_reg
);
5556 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5558 if (lra_dump_file
!= NULL
)
5562 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5563 original_regno
, new_regno
);
5564 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5565 fprintf (lra_dump_file
,
5566 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5570 restore
= emit_spill_move (false, new_reg
, original_reg
);
5571 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5573 if (lra_dump_file
!= NULL
)
5575 fprintf (lra_dump_file
,
5576 " Rejecting split %d->%d "
5577 "resulting in > 2 restore insns:\n",
5578 original_regno
, new_regno
);
5579 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5580 fprintf (lra_dump_file
,
5581 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5585 /* Transfer equivalence information to the spill register, so that
5586 if we fail to allocate the spill register, we have the option of
5587 rematerializing the original value instead of spilling to the stack. */
5588 if (!HARD_REGISTER_NUM_P (original_regno
)
5589 && mode
== PSEUDO_REGNO_MODE (original_regno
))
5590 lra_copy_reg_equiv (new_regno
, original_regno
);
5591 after_p
= usage_insns
[original_regno
].after_p
;
5592 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
5593 bitmap_set_bit (&check_only_regs
, new_regno
);
5594 bitmap_set_bit (&check_only_regs
, original_regno
);
5595 bitmap_set_bit (&lra_split_regs
, new_regno
);
5598 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5600 usage_insn
= next_usage_insns
;
5603 usage_insn
= XEXP (next_usage_insns
, 0);
5604 lra_assert (DEBUG_INSN_P (usage_insn
));
5605 next_usage_insns
= XEXP (next_usage_insns
, 1);
5606 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5607 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5608 if (lra_dump_file
!= NULL
)
5610 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5611 original_regno
, new_regno
);
5612 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5615 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5616 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5617 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5618 after_p
? NULL
: restore
,
5619 after_p
? restore
: NULL
,
5621 ? "Add reg<-save" : "Add reg<-split");
5622 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5623 before_p
? NULL
: save
,
5625 ? "Add save<-reg" : "Add split<-reg");
5627 /* If we are trying to split multi-register. We should check
5628 conflicts on the next assignment sub-pass. IRA can allocate on
5629 sub-register levels, LRA do this on pseudos level right now and
5630 this discrepancy may create allocation conflicts after
5632 lra_risky_transformations_p
= true;
5633 if (lra_dump_file
!= NULL
)
5634 fprintf (lra_dump_file
,
5635 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5639 /* Recognize that we need a split transformation for insn INSN, which
5640 defines or uses REGNO in its insn biggest MODE (we use it only if
5641 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5642 hard registers which might be used for reloads since the EBB end.
5643 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5644 uid before starting INSN processing. Return true if we succeed in
5645 such transformation. */
5647 split_if_necessary (int regno
, machine_mode mode
,
5648 HARD_REG_SET potential_reload_hard_regs
,
5649 bool before_p
, rtx_insn
*insn
, int max_uid
)
5653 rtx next_usage_insns
;
5655 if (regno
< FIRST_PSEUDO_REGISTER
)
5656 nregs
= hard_regno_nregs (regno
, mode
);
5657 for (i
= 0; i
< nregs
; i
++)
5658 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5659 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5660 /* To avoid processing the register twice or more. */
5661 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5662 && INSN_UID (next_usage_insns
) < max_uid
)
5663 || (GET_CODE (next_usage_insns
) == INSN_LIST
5664 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5665 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5666 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5671 /* Return TRUE if rtx X is considered as an invariant for
5674 invariant_p (const_rtx x
)
5681 code
= GET_CODE (x
);
5682 mode
= GET_MODE (x
);
5686 code
= GET_CODE (x
);
5687 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
5695 int i
, nregs
, regno
= REGNO (x
);
5697 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5698 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5699 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5701 nregs
= hard_regno_nregs (regno
, mode
);
5702 for (i
= 0; i
< nregs
; i
++)
5703 if (! fixed_regs
[regno
+ i
]
5704 /* A hard register may be clobbered in the current insn
5705 but we can ignore this case because if the hard
5706 register is used it should be set somewhere after the
5708 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5711 fmt
= GET_RTX_FORMAT (code
);
5712 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5716 if (! invariant_p (XEXP (x
, i
)))
5719 else if (fmt
[i
] == 'E')
5721 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5722 if (! invariant_p (XVECEXP (x
, i
, j
)))
5729 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5730 inheritance transformation (using dest_reg instead invariant in a
5731 subsequent insn). */
5733 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5735 invariant_ptr_t invariant_ptr
;
5736 rtx_insn
*insn
, *new_insns
;
5737 rtx insn_set
, insn_reg
, new_reg
;
5739 bool succ_p
= false;
5740 int dst_regno
= REGNO (dst_reg
);
5741 machine_mode dst_mode
= GET_MODE (dst_reg
);
5742 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5744 invariant_ptr
= insert_invariant (invariant_rtx
);
5745 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
5747 /* We have a subsequent insn using the invariant. */
5748 insn_set
= single_set (insn
);
5749 lra_assert (insn_set
!= NULL
);
5750 insn_reg
= SET_DEST (insn_set
);
5751 lra_assert (REG_P (insn_reg
));
5752 insn_regno
= REGNO (insn_reg
);
5753 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
5755 if (dst_mode
== GET_MODE (insn_reg
)
5756 /* We should consider only result move reg insns which are
5758 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
5759 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
5761 if (lra_dump_file
!= NULL
)
5762 fprintf (lra_dump_file
,
5763 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5764 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
5765 cl
, "invariant inheritance");
5766 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5767 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5768 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
5770 lra_emit_move (new_reg
, dst_reg
);
5771 new_insns
= get_insns ();
5773 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
5774 "Add invariant inheritance<-original");
5776 lra_emit_move (SET_DEST (insn_set
), new_reg
);
5777 new_insns
= get_insns ();
5779 lra_process_new_insns (insn
, NULL
, new_insns
,
5780 "Changing reload<-inheritance");
5781 lra_set_insn_deleted (insn
);
5783 if (lra_dump_file
!= NULL
)
5785 fprintf (lra_dump_file
,
5786 " Invariant inheritance reuse change %d (bb%d):\n",
5787 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5788 dump_insn_slim (lra_dump_file
, insn
);
5789 fprintf (lra_dump_file
,
5790 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5794 invariant_ptr
->insn
= curr_insn
;
5798 /* Check only registers living at the current program point in the
5800 static bitmap_head live_regs
;
5802 /* Update live info in EBB given by its HEAD and TAIL insns after
5803 inheritance/split transformation. The function removes dead moves
5806 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5811 rtx_insn
*prev_insn
;
5814 basic_block last_bb
, prev_bb
, curr_bb
;
5816 struct lra_insn_reg
*reg
;
5820 last_bb
= BLOCK_FOR_INSN (tail
);
5822 for (curr_insn
= tail
;
5823 curr_insn
!= PREV_INSN (head
);
5824 curr_insn
= prev_insn
)
5826 prev_insn
= PREV_INSN (curr_insn
);
5827 /* We need to process empty blocks too. They contain
5828 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5829 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5831 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5832 if (curr_bb
!= prev_bb
)
5834 if (prev_bb
!= NULL
)
5836 /* Update df_get_live_in (prev_bb): */
5837 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5838 if (bitmap_bit_p (&live_regs
, j
))
5839 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5841 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5843 if (curr_bb
!= last_bb
)
5845 /* Update df_get_live_out (curr_bb): */
5846 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5848 live_p
= bitmap_bit_p (&live_regs
, j
);
5850 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5851 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5857 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5859 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5863 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5865 if (! NONDEBUG_INSN_P (curr_insn
))
5867 curr_id
= lra_get_insn_recog_data (curr_insn
);
5868 curr_static_id
= curr_id
->insn_static_data
;
5870 if ((set
= single_set (curr_insn
)) != NULL_RTX
5871 && REG_P (SET_DEST (set
))
5872 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5873 && SET_DEST (set
) != pic_offset_table_rtx
5874 && bitmap_bit_p (&check_only_regs
, regno
)
5875 && ! bitmap_bit_p (&live_regs
, regno
))
5877 /* See which defined values die here. */
5878 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5879 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5880 bitmap_clear_bit (&live_regs
, reg
->regno
);
5881 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5882 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5883 bitmap_clear_bit (&live_regs
, reg
->regno
);
5884 if (curr_id
->arg_hard_regs
!= NULL
)
5885 /* Make clobbered argument hard registers die. */
5886 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5887 if (regno
>= FIRST_PSEUDO_REGISTER
)
5888 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5889 /* Mark each used value as live. */
5890 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5891 if (reg
->type
!= OP_OUT
5892 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5893 bitmap_set_bit (&live_regs
, reg
->regno
);
5894 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5895 if (reg
->type
!= OP_OUT
5896 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5897 bitmap_set_bit (&live_regs
, reg
->regno
);
5898 if (curr_id
->arg_hard_regs
!= NULL
)
5899 /* Make used argument hard registers live. */
5900 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5901 if (regno
< FIRST_PSEUDO_REGISTER
5902 && bitmap_bit_p (&check_only_regs
, regno
))
5903 bitmap_set_bit (&live_regs
, regno
);
5904 /* It is quite important to remove dead move insns because it
5905 means removing dead store. We don't need to process them for
5909 if (lra_dump_file
!= NULL
)
5911 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5912 dump_insn_slim (lra_dump_file
, curr_insn
);
5914 lra_set_insn_deleted (curr_insn
);
5919 /* The structure describes info to do an inheritance for the current
5920 insn. We need to collect such info first before doing the
5921 transformations because the transformations change the insn
5922 internal representation. */
5925 /* Original regno. */
5927 /* Subsequent insns which can inherit original reg value. */
5931 /* Array containing all info for doing inheritance from the current
5933 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5935 /* Number elements in the previous array. */
5936 static int to_inherit_num
;
5938 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5939 structure to_inherit. */
5941 add_to_inherit (int regno
, rtx insns
)
5945 for (i
= 0; i
< to_inherit_num
; i
++)
5946 if (to_inherit
[i
].regno
== regno
)
5948 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5949 to_inherit
[to_inherit_num
].regno
= regno
;
5950 to_inherit
[to_inherit_num
++].insns
= insns
;
5953 /* Return the last non-debug insn in basic block BB, or the block begin
5956 get_last_insertion_point (basic_block bb
)
5960 FOR_BB_INSNS_REVERSE (bb
, insn
)
5961 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5966 /* Set up RES by registers living on edges FROM except the edge (FROM,
5967 TO) or by registers set up in a jump insn in BB FROM. */
5969 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5972 struct lra_insn_reg
*reg
;
5976 lra_assert (to
!= NULL
);
5978 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5980 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5981 last
= get_last_insertion_point (from
);
5982 if (! JUMP_P (last
))
5984 curr_id
= lra_get_insn_recog_data (last
);
5985 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5986 if (reg
->type
!= OP_IN
)
5987 bitmap_set_bit (res
, reg
->regno
);
5990 /* Used as a temporary results of some bitmap calculations. */
5991 static bitmap_head temp_bitmap
;
5993 /* We split for reloads of small class of hard regs. The following
5994 defines how many hard regs the class should have to be qualified as
5995 small. The code is mostly oriented to x86/x86-64 architecture
5996 where some insns need to use only specific register or pair of
5997 registers and these register can live in RTL explicitly, e.g. for
5998 parameter passing. */
5999 static const int max_small_class_regs_num
= 2;
6001 /* Do inheritance/split transformations in EBB starting with HEAD and
6002 finishing on TAIL. We process EBB insns in the reverse order.
6003 Return true if we did any inheritance/split transformation in the
6006 We should avoid excessive splitting which results in worse code
6007 because of inaccurate cost calculations for spilling new split
6008 pseudos in such case. To achieve this we do splitting only if
6009 register pressure is high in given basic block and there are reload
6010 pseudos requiring hard registers. We could do more register
6011 pressure calculations at any given program point to avoid necessary
6012 splitting even more but it is to expensive and the current approach
6013 works well enough. */
6015 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6017 int i
, src_regno
, dst_regno
, nregs
;
6018 bool change_p
, succ_p
, update_reloads_num_p
;
6019 rtx_insn
*prev_insn
, *last_insn
;
6020 rtx next_usage_insns
, curr_set
;
6022 struct lra_insn_reg
*reg
;
6023 basic_block last_processed_bb
, curr_bb
= NULL
;
6024 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6028 bool head_p
, after_p
;
6031 curr_usage_insns_check
++;
6032 clear_invariants ();
6033 reloads_num
= calls_num
= 0;
6034 bitmap_clear (&check_only_regs
);
6035 bitmap_clear (&invalid_invariant_regs
);
6036 last_processed_bb
= NULL
;
6037 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6038 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
6039 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
6040 /* We don't process new insns generated in the loop. */
6041 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6043 prev_insn
= PREV_INSN (curr_insn
);
6044 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6045 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6046 if (last_processed_bb
!= curr_bb
)
6048 /* We are at the end of BB. Add qualified living
6049 pseudos for potential splitting. */
6050 to_process
= df_get_live_out (curr_bb
);
6051 if (last_processed_bb
!= NULL
)
6053 /* We are somewhere in the middle of EBB. */
6054 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6056 to_process
= &temp_bitmap
;
6058 last_processed_bb
= curr_bb
;
6059 last_insn
= get_last_insertion_point (curr_bb
);
6060 after_p
= (! JUMP_P (last_insn
)
6061 && (! CALL_P (last_insn
)
6062 || (find_reg_note (last_insn
,
6063 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6064 && ! SIBLING_CALL_P (last_insn
))));
6065 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6066 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6068 if ((int) j
>= lra_constraint_new_regno_start
)
6070 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6072 if (j
< FIRST_PSEUDO_REGISTER
)
6073 SET_HARD_REG_BIT (live_hard_regs
, j
);
6075 add_to_hard_reg_set (&live_hard_regs
,
6076 PSEUDO_REGNO_MODE (j
),
6078 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6082 src_regno
= dst_regno
= -1;
6083 curr_set
= single_set (curr_insn
);
6084 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6085 dst_regno
= REGNO (SET_DEST (curr_set
));
6086 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6087 src_regno
= REGNO (SET_SRC (curr_set
));
6088 update_reloads_num_p
= true;
6089 if (src_regno
< lra_constraint_new_regno_start
6090 && src_regno
>= FIRST_PSEUDO_REGISTER
6091 && reg_renumber
[src_regno
] < 0
6092 && dst_regno
>= lra_constraint_new_regno_start
6093 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6095 /* 'reload_pseudo <- original_pseudo'. */
6096 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6098 update_reloads_num_p
= false;
6100 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6101 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6102 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6103 curr_insn
, next_usage_insns
);
6107 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6108 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6109 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6110 reg_class_contents
[cl
]);
6112 else if (src_regno
< 0
6113 && dst_regno
>= lra_constraint_new_regno_start
6114 && invariant_p (SET_SRC (curr_set
))
6115 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6116 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6117 && ! bitmap_bit_p (&invalid_invariant_regs
,
6118 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6120 /* 'reload_pseudo <- invariant'. */
6121 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6123 update_reloads_num_p
= false;
6124 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6126 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6127 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6128 reg_class_contents
[cl
]);
6130 else if (src_regno
>= lra_constraint_new_regno_start
6131 && dst_regno
< lra_constraint_new_regno_start
6132 && dst_regno
>= FIRST_PSEUDO_REGISTER
6133 && reg_renumber
[dst_regno
] < 0
6134 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6135 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6136 && (next_usage_insns
6137 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6139 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6141 update_reloads_num_p
= false;
6142 /* 'original_pseudo <- reload_pseudo'. */
6143 if (! JUMP_P (curr_insn
)
6144 && inherit_reload_reg (true, dst_regno
, cl
,
6145 curr_insn
, next_usage_insns
))
6148 usage_insns
[dst_regno
].check
= 0;
6149 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6150 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6151 reg_class_contents
[cl
]);
6153 else if (INSN_P (curr_insn
))
6156 int max_uid
= get_max_uid ();
6158 curr_id
= lra_get_insn_recog_data (curr_insn
);
6159 curr_static_id
= curr_id
->insn_static_data
;
6161 /* Process insn definitions. */
6162 for (iter
= 0; iter
< 2; iter
++)
6163 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6166 if (reg
->type
!= OP_IN
6167 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6169 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6170 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6171 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6172 && (next_usage_insns
6173 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6175 struct lra_insn_reg
*r
;
6177 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6178 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6180 /* Don't do inheritance if the pseudo is also
6181 used in the insn. */
6183 /* We can not do inheritance right now
6184 because the current insn reg info (chain
6185 regs) can change after that. */
6186 add_to_inherit (dst_regno
, next_usage_insns
);
6188 /* We can not process one reg twice here because of
6189 usage_insns invalidation. */
6190 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6191 || reg_renumber
[dst_regno
] >= 0)
6192 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6196 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6197 potential_reload_hard_regs
,
6198 false, curr_insn
, max_uid
))
6200 CLEAR_HARD_REG_SET (s
);
6201 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6202 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6204 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6205 reg_renumber
[dst_regno
]);
6206 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
6208 /* We should invalidate potential inheritance or
6209 splitting for the current insn usages to the next
6210 usage insns (see code below) as the output pseudo
6212 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6213 && reg_renumber
[dst_regno
] < 0)
6214 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6215 && (dst_regno
< FIRST_PSEUDO_REGISTER
6216 || reg_renumber
[dst_regno
] >= 0)))
6218 /* Invalidate and mark definitions. */
6219 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6220 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6223 nregs
= hard_regno_nregs (dst_regno
,
6225 for (i
= 0; i
< nregs
; i
++)
6226 usage_insns
[dst_regno
+ i
].check
6227 = -(int) INSN_UID (curr_insn
);
6231 /* Process clobbered call regs. */
6232 if (curr_id
->arg_hard_regs
!= NULL
)
6233 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6234 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6235 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6236 = -(int) INSN_UID (curr_insn
);
6237 if (! JUMP_P (curr_insn
))
6238 for (i
= 0; i
< to_inherit_num
; i
++)
6239 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6240 ALL_REGS
, curr_insn
,
6241 to_inherit
[i
].insns
))
6243 if (CALL_P (curr_insn
))
6245 rtx cheap
, pat
, dest
;
6247 int regno
, hard_regno
;
6250 if ((cheap
= find_reg_note (curr_insn
,
6251 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6252 && ((cheap
= XEXP (cheap
, 0)), true)
6253 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6254 && (hard_regno
= reg_renumber
[regno
]) >= 0
6255 && usage_insns
[regno
].check
== curr_usage_insns_check
6256 /* If there are pending saves/restores, the
6257 optimization is not worth. */
6258 && usage_insns
[regno
].calls_num
== calls_num
- 1
6259 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
6261 /* Restore the pseudo from the call result as
6262 REG_RETURNED note says that the pseudo value is
6263 in the call result and the pseudo is an argument
6265 pat
= PATTERN (curr_insn
);
6266 if (GET_CODE (pat
) == PARALLEL
)
6267 pat
= XVECEXP (pat
, 0, 0);
6268 dest
= SET_DEST (pat
);
6269 /* For multiple return values dest is PARALLEL.
6270 Currently we handle only single return value case. */
6274 emit_move_insn (cheap
, copy_rtx (dest
));
6275 restore
= get_insns ();
6277 lra_process_new_insns (curr_insn
, NULL
, restore
,
6278 "Inserting call parameter restore");
6279 /* We don't need to save/restore of the pseudo from
6281 usage_insns
[regno
].calls_num
= calls_num
;
6282 bitmap_set_bit (&check_only_regs
, regno
);
6287 /* Process insn usages. */
6288 for (iter
= 0; iter
< 2; iter
++)
6289 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6292 if ((reg
->type
!= OP_OUT
6293 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6294 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6296 if (src_regno
>= FIRST_PSEUDO_REGISTER
6297 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6299 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6300 && (next_usage_insns
6301 = usage_insns
[src_regno
].insns
) != NULL_RTX
6302 && NONDEBUG_INSN_P (curr_insn
))
6303 add_to_inherit (src_regno
, next_usage_insns
);
6304 else if (usage_insns
[src_regno
].check
6305 != -(int) INSN_UID (curr_insn
))
6306 /* Add usages but only if the reg is not set up
6307 in the same insn. */
6308 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6310 else if (src_regno
< FIRST_PSEUDO_REGISTER
6311 || reg_renumber
[src_regno
] >= 0)
6314 rtx_insn
*use_insn
= curr_insn
;
6316 before_p
= (JUMP_P (curr_insn
)
6317 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6318 if (NONDEBUG_INSN_P (curr_insn
)
6319 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6320 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6321 potential_reload_hard_regs
,
6322 before_p
, curr_insn
, max_uid
))
6325 lra_risky_transformations_p
= true;
6328 usage_insns
[src_regno
].check
= 0;
6330 use_insn
= PREV_INSN (curr_insn
);
6332 if (NONDEBUG_INSN_P (curr_insn
))
6334 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6335 add_to_hard_reg_set (&live_hard_regs
,
6336 reg
->biggest_mode
, src_regno
);
6338 add_to_hard_reg_set (&live_hard_regs
,
6339 PSEUDO_REGNO_MODE (src_regno
),
6340 reg_renumber
[src_regno
]);
6342 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6345 /* Process used call regs. */
6346 if (curr_id
->arg_hard_regs
!= NULL
)
6347 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6348 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6350 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6351 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6353 for (i
= 0; i
< to_inherit_num
; i
++)
6355 src_regno
= to_inherit
[i
].regno
;
6356 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6357 curr_insn
, to_inherit
[i
].insns
))
6360 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6363 if (update_reloads_num_p
6364 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6367 if ((REG_P (SET_DEST (curr_set
))
6368 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6369 && reg_renumber
[regno
] < 0
6370 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6371 || (REG_P (SET_SRC (curr_set
))
6372 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6373 && reg_renumber
[regno
] < 0
6374 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6376 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6378 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6379 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6380 reg_class_contents
[cl
]);
6383 if (NONDEBUG_INSN_P (curr_insn
))
6387 /* Invalidate invariants with changed regs. */
6388 curr_id
= lra_get_insn_recog_data (curr_insn
);
6389 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6390 if (reg
->type
!= OP_IN
)
6392 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6393 bitmap_set_bit (&invalid_invariant_regs
,
6394 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6396 curr_static_id
= curr_id
->insn_static_data
;
6397 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6398 if (reg
->type
!= OP_IN
)
6399 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6400 if (curr_id
->arg_hard_regs
!= NULL
)
6401 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6402 if (regno
>= FIRST_PSEUDO_REGISTER
)
6403 bitmap_set_bit (&invalid_invariant_regs
,
6404 regno
- FIRST_PSEUDO_REGISTER
);
6406 /* We reached the start of the current basic block. */
6407 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6408 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6410 /* We reached the beginning of the current block -- do
6411 rest of spliting in the current BB. */
6412 to_process
= df_get_live_in (curr_bb
);
6413 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6415 /* We are somewhere in the middle of EBB. */
6416 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6417 curr_bb
, &temp_bitmap
);
6418 to_process
= &temp_bitmap
;
6421 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6423 if ((int) j
>= lra_constraint_new_regno_start
)
6425 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6426 && usage_insns
[j
].check
== curr_usage_insns_check
6427 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6429 if (need_for_split_p (potential_reload_hard_regs
, j
))
6431 if (lra_dump_file
!= NULL
&& head_p
)
6433 fprintf (lra_dump_file
,
6434 " ----------------------------------\n");
6437 if (split_reg (false, j
, bb_note (curr_bb
),
6441 usage_insns
[j
].check
= 0;
6449 /* This value affects EBB forming. If probability of edge from EBB to
6450 a BB is not greater than the following value, we don't add the BB
6452 #define EBB_PROBABILITY_CUTOFF \
6453 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6455 /* Current number of inheritance/split iteration. */
6456 int lra_inheritance_iter
;
6458 /* Entry function for inheritance/split pass. */
6460 lra_inheritance (void)
6463 basic_block bb
, start_bb
;
6466 lra_inheritance_iter
++;
6467 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6469 timevar_push (TV_LRA_INHERITANCE
);
6470 if (lra_dump_file
!= NULL
)
6471 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6472 lra_inheritance_iter
);
6473 curr_usage_insns_check
= 0;
6474 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6475 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6476 usage_insns
[i
].check
= 0;
6477 bitmap_initialize (&check_only_regs
, ®_obstack
);
6478 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6479 bitmap_initialize (&live_regs
, ®_obstack
);
6480 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6481 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6482 FOR_EACH_BB_FN (bb
, cfun
)
6485 if (lra_dump_file
!= NULL
)
6486 fprintf (lra_dump_file
, "EBB");
6487 /* Form a EBB starting with BB. */
6488 bitmap_clear (&ebb_global_regs
);
6489 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6492 if (lra_dump_file
!= NULL
)
6493 fprintf (lra_dump_file
, " %d", bb
->index
);
6494 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6495 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6497 e
= find_fallthru_edge (bb
->succs
);
6500 if (e
->probability
.initialized_p ()
6501 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
6505 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6506 if (lra_dump_file
!= NULL
)
6507 fprintf (lra_dump_file
, "\n");
6508 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6509 /* Remember that the EBB head and tail can change in
6511 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6513 bitmap_clear (&ebb_global_regs
);
6514 bitmap_clear (&temp_bitmap
);
6515 bitmap_clear (&live_regs
);
6516 bitmap_clear (&invalid_invariant_regs
);
6517 bitmap_clear (&check_only_regs
);
6520 timevar_pop (TV_LRA_INHERITANCE
);
6525 /* This page contains code to undo failed inheritance/split
6528 /* Current number of iteration undoing inheritance/split. */
6529 int lra_undo_inheritance_iter
;
6531 /* Fix BB live info LIVE after removing pseudos created on pass doing
6532 inheritance/split which are REMOVED_PSEUDOS. */
6534 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6539 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6540 if (bitmap_clear_bit (live
, regno
)
6541 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6542 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6545 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6550 if (GET_CODE (reg
) == SUBREG
)
6551 reg
= SUBREG_REG (reg
);
6557 /* Delete a move INSN with destination reg DREGNO and a previous
6558 clobber insn with the same regno. The inheritance/split code can
6559 generate moves with preceding clobber and when we delete such moves
6560 we should delete the clobber insn too to keep the correct life
6563 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6565 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6567 lra_set_insn_deleted (insn
);
6568 lra_assert (dregno
>= 0);
6569 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6570 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6571 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6572 lra_set_insn_deleted (prev_insn
);
6575 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6576 return true if we did any change. The undo transformations for
6577 inheritance looks like
6581 p <- i, i <- p, and i <- i3
6582 where p is original pseudo from which inheritance pseudo i was
6583 created, i and i3 are removed inheritance pseudos, i2 is another
6584 not removed inheritance pseudo. All split pseudos or other
6585 occurrences of removed inheritance pseudos are changed on the
6586 corresponding original pseudos.
6588 The function also schedules insns changed and created during
6589 inheritance/split pass for processing by the subsequent constraint
6592 remove_inheritance_pseudos (bitmap remove_pseudos
)
6595 int regno
, sregno
, prev_sregno
, dregno
;
6598 rtx_insn
*prev_insn
;
6599 bool change_p
, done_p
;
6601 change_p
= ! bitmap_empty_p (remove_pseudos
);
6602 /* We can not finish the function right away if CHANGE_P is true
6603 because we need to marks insns affected by previous
6604 inheritance/split pass for processing by the subsequent
6606 FOR_EACH_BB_FN (bb
, cfun
)
6608 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6609 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6610 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6612 if (! INSN_P (curr_insn
))
6615 sregno
= dregno
= -1;
6616 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6617 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6619 dregno
= get_regno (SET_DEST (set
));
6620 sregno
= get_regno (SET_SRC (set
));
6623 if (sregno
>= 0 && dregno
>= 0)
6625 if (bitmap_bit_p (remove_pseudos
, dregno
)
6626 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6628 /* invariant inheritance pseudo <- original pseudo */
6629 if (lra_dump_file
!= NULL
)
6631 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6632 dump_insn_slim (lra_dump_file
, curr_insn
);
6633 fprintf (lra_dump_file
, "\n");
6635 delete_move_and_clobber (curr_insn
, dregno
);
6638 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6639 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6641 /* reload pseudo <- invariant inheritance pseudo */
6643 /* We can not just change the source. It might be
6644 an insn different from the move. */
6645 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6646 rtx_insn
*new_insns
= get_insns ();
6648 lra_assert (single_set (new_insns
) != NULL
6649 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6650 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6651 "Changing reload<-invariant inheritance");
6652 delete_move_and_clobber (curr_insn
, dregno
);
6655 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6656 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6657 || (bitmap_bit_p (remove_pseudos
, dregno
)
6658 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6659 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6660 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6661 || (bitmap_bit_p (remove_pseudos
, dregno
)
6662 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6663 /* One of the following cases:
6664 original <- removed inheritance pseudo
6665 removed inherit pseudo <- another removed inherit pseudo
6666 removed inherit pseudo <- original pseudo
6668 removed_split_pseudo <- original_reg
6669 original_reg <- removed_split_pseudo */
6671 if (lra_dump_file
!= NULL
)
6673 fprintf (lra_dump_file
, " Removing %s:\n",
6674 bitmap_bit_p (&lra_split_regs
, sregno
)
6675 || bitmap_bit_p (&lra_split_regs
, dregno
)
6676 ? "split" : "inheritance");
6677 dump_insn_slim (lra_dump_file
, curr_insn
);
6679 delete_move_and_clobber (curr_insn
, dregno
);
6682 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6683 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6685 /* Search the following pattern:
6686 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6687 original_pseudo <- inherit_or_split_pseudo1
6688 where the 2nd insn is the current insn and
6689 inherit_or_split_pseudo2 is not removed. If it is found,
6690 change the current insn onto:
6691 original_pseudo <- inherit_or_split_pseudo2. */
6692 for (prev_insn
= PREV_INSN (curr_insn
);
6693 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6694 prev_insn
= PREV_INSN (prev_insn
))
6696 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6697 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6698 /* There should be no subregs in insn we are
6699 searching because only the original reg might
6700 be in subreg when we changed the mode of
6701 load/store for splitting. */
6702 && REG_P (SET_DEST (prev_set
))
6703 && REG_P (SET_SRC (prev_set
))
6704 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6705 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6706 >= FIRST_PSEUDO_REGISTER
)
6707 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6709 /* As we consider chain of inheritance or
6710 splitting described in above comment we should
6711 check that sregno and prev_sregno were
6712 inheritance/split pseudos created from the
6713 same original regno. */
6714 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6715 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6716 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6717 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6719 lra_assert (GET_MODE (SET_SRC (prev_set
))
6720 == GET_MODE (regno_reg_rtx
[sregno
]));
6721 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
6722 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
6724 SET_SRC (set
) = SET_SRC (prev_set
);
6725 /* As we are finishing with processing the insn
6726 here, check the destination too as it might
6727 inheritance pseudo for another pseudo. */
6728 if (bitmap_bit_p (remove_pseudos
, dregno
)
6729 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6731 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
6733 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6734 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
6736 SET_DEST (set
) = restore_rtx
;
6738 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6739 lra_set_used_insn_alternative_by_uid
6740 (INSN_UID (curr_insn
), -1);
6742 if (lra_dump_file
!= NULL
)
6744 fprintf (lra_dump_file
, " Change reload insn:\n");
6745 dump_insn_slim (lra_dump_file
, curr_insn
);
6752 struct lra_insn_reg
*reg
;
6753 bool restored_regs_p
= false;
6754 bool kept_regs_p
= false;
6756 curr_id
= lra_get_insn_recog_data (curr_insn
);
6757 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6760 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
6761 if (restore_rtx
!= NULL_RTX
)
6763 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6765 lra_substitute_pseudo_within_insn
6766 (curr_insn
, regno
, restore_rtx
, false);
6767 restored_regs_p
= true;
6773 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6775 /* The instruction has changed since the previous
6776 constraints pass. */
6777 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6778 lra_set_used_insn_alternative_by_uid
6779 (INSN_UID (curr_insn
), -1);
6781 else if (restored_regs_p
)
6782 /* The instruction has been restored to the form that
6783 it had during the previous constraints pass. */
6784 lra_update_insn_regno_info (curr_insn
);
6785 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6787 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6788 dump_insn_slim (lra_dump_file
, curr_insn
);
6796 /* If optional reload pseudos failed to get a hard register or was not
6797 inherited, it is better to remove optional reloads. We do this
6798 transformation after undoing inheritance to figure out necessity to
6799 remove optional reloads easier. Return true if we do any
6802 undo_optional_reloads (void)
6804 bool change_p
, keep_p
;
6805 unsigned int regno
, uid
;
6806 bitmap_iterator bi
, bi2
;
6809 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
6811 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6812 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6815 /* Keep optional reloads from previous subpasses. */
6816 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
6817 /* If the original pseudo changed its allocation, just
6818 removing the optional pseudo is dangerous as the original
6819 pseudo will have longer live range. */
6820 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
6822 else if (reg_renumber
[regno
] >= 0)
6823 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6825 insn
= lra_insn_recog_data
[uid
]->insn
;
6826 if ((set
= single_set (insn
)) == NULL_RTX
)
6828 src
= SET_SRC (set
);
6829 dest
= SET_DEST (set
);
6830 if (! REG_P (src
) || ! REG_P (dest
))
6832 if (REGNO (dest
) == regno
6833 /* Ignore insn for optional reloads itself. */
6834 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
6835 /* Check only inheritance on last inheritance pass. */
6836 && (int) REGNO (src
) >= new_regno_start
6837 /* Check that the optional reload was inherited. */
6838 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6846 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
6847 if (lra_dump_file
!= NULL
)
6848 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6851 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
6852 auto_bitmap
insn_bitmap (®_obstack
);
6853 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
6855 if (lra_dump_file
!= NULL
)
6856 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6857 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6858 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
6860 insn
= lra_insn_recog_data
[uid
]->insn
;
6861 if ((set
= single_set (insn
)) != NULL_RTX
)
6863 src
= SET_SRC (set
);
6864 dest
= SET_DEST (set
);
6865 if (REG_P (src
) && REG_P (dest
)
6866 && ((REGNO (src
) == regno
6867 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6869 || (REGNO (dest
) == regno
6870 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6873 if (lra_dump_file
!= NULL
)
6875 fprintf (lra_dump_file
, " Deleting move %u\n",
6877 dump_insn_slim (lra_dump_file
, insn
);
6879 delete_move_and_clobber (insn
, REGNO (dest
));
6882 /* We should not worry about generation memory-memory
6883 moves here as if the corresponding inheritance did
6884 not work (inheritance pseudo did not get a hard reg),
6885 we remove the inheritance pseudo and the optional
6888 lra_substitute_pseudo_within_insn
6889 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
6890 lra_update_insn_regno_info (insn
);
6891 if (lra_dump_file
!= NULL
)
6893 fprintf (lra_dump_file
,
6894 " Restoring original insn:\n");
6895 dump_insn_slim (lra_dump_file
, insn
);
6899 /* Clear restore_regnos. */
6900 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6901 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6905 /* Entry function for undoing inheritance/split transformation. Return true
6906 if we did any RTL change in this pass. */
6908 lra_undo_inheritance (void)
6912 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6917 lra_undo_inheritance_iter
++;
6918 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6920 if (lra_dump_file
!= NULL
)
6921 fprintf (lra_dump_file
,
6922 "\n********** Undoing inheritance #%d: **********\n\n",
6923 lra_undo_inheritance_iter
);
6924 auto_bitmap
remove_pseudos (®_obstack
);
6925 n_inherit
= n_all_inherit
= 0;
6926 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6927 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
6930 if (reg_renumber
[regno
] < 0
6931 /* If the original pseudo changed its allocation, just
6932 removing inheritance is dangerous as for changing
6933 allocation we used shorter live-ranges. */
6934 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
6935 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
6936 bitmap_set_bit (remove_pseudos
, regno
);
6940 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6941 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6942 n_inherit
, n_all_inherit
,
6943 (double) n_inherit
/ n_all_inherit
* 100);
6944 n_split
= n_all_split
= 0;
6945 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6946 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
6948 int restore_regno
= REGNO (restore_rtx
);
6951 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6952 ? reg_renumber
[restore_regno
] : restore_regno
);
6953 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6954 bitmap_set_bit (remove_pseudos
, regno
);
6958 if (lra_dump_file
!= NULL
)
6959 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6960 regno
, restore_regno
);
6963 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6964 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6965 n_split
, n_all_split
,
6966 (double) n_split
/ n_all_split
* 100);
6967 change_p
= remove_inheritance_pseudos (remove_pseudos
);
6968 /* Clear restore_regnos. */
6969 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6970 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6971 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6972 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6973 change_p
= undo_optional_reloads () || change_p
;