1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || (INSN_UID (curr_insn
) >= new_insn_uid_start
273 && curr_insn_set
!= NULL
274 && ((OBJECT_P (SET_SRC (curr_insn_set
))
275 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
276 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
277 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
278 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
279 /* When we don't know what class will be used finally for reload
280 pseudos, we use ALL_REGS. */
281 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
282 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
283 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
284 lra_no_alloc_regs
)));
287 common_class
= ira_reg_class_subset
[rclass
][cl
];
288 if (new_class
!= NULL
)
289 *new_class
= common_class
;
290 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
293 /* Check that there are enough allocatable regs. */
294 class_size
= ira_class_hard_regs_num
[common_class
];
295 for (i
= 0; i
< class_size
; i
++)
297 hard_regno
= ira_class_hard_regs
[common_class
][i
];
298 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
301 for (j
= 0; j
< nregs
; j
++)
302 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
303 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
313 /* Return true if REGNO satisfies a memory constraint. */
317 return get_reg_class (regno
) == NO_REGS
;
320 /* Return 1 if ADDR is a valid memory address for mode MODE in address
321 space AS, and check that each pseudo has the proper kind of hard
324 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
325 rtx addr
, addr_space_t as
)
327 #ifdef GO_IF_LEGITIMATE_ADDRESS
328 lra_assert (ADDR_SPACE_GENERIC_P (as
));
329 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
335 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
340 /* Temporarily eliminates registers in an address (for the lifetime of
342 class address_eliminator
{
344 address_eliminator (struct address_info
*ad
);
345 ~address_eliminator ();
348 struct address_info
*m_ad
;
356 address_eliminator::address_eliminator (struct address_info
*ad
)
358 m_base_loc (strip_subreg (ad
->base_term
)),
359 m_base_reg (NULL_RTX
),
360 m_index_loc (strip_subreg (ad
->index_term
)),
361 m_index_reg (NULL_RTX
)
363 if (m_base_loc
!= NULL
)
365 m_base_reg
= *m_base_loc
;
366 lra_eliminate_reg_if_possible (m_base_loc
);
367 if (m_ad
->base_term2
!= NULL
)
368 *m_ad
->base_term2
= *m_ad
->base_term
;
370 if (m_index_loc
!= NULL
)
372 m_index_reg
= *m_index_loc
;
373 lra_eliminate_reg_if_possible (m_index_loc
);
377 address_eliminator::~address_eliminator ()
379 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
381 *m_base_loc
= m_base_reg
;
382 if (m_ad
->base_term2
!= NULL
)
383 *m_ad
->base_term2
= *m_ad
->base_term
;
385 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
386 *m_index_loc
= m_index_reg
;
389 /* Return true if the eliminated form of AD is a legitimate target address. */
391 valid_address_p (struct address_info
*ad
)
393 address_eliminator
eliminator (ad
);
394 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
397 /* Return true if the eliminated form of memory reference OP satisfies
398 extra memory constraint CONSTRAINT. */
400 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
402 struct address_info ad
;
404 decompose_mem_address (&ad
, op
);
405 address_eliminator
eliminator (&ad
);
406 return constraint_satisfied_p (op
, constraint
);
409 /* Return true if the eliminated form of address AD satisfies extra
410 address constraint CONSTRAINT. */
412 satisfies_address_constraint_p (struct address_info
*ad
,
413 enum constraint_num constraint
)
415 address_eliminator
eliminator (ad
);
416 return constraint_satisfied_p (*ad
->outer
, constraint
);
419 /* Return true if the eliminated form of address OP satisfies extra
420 address constraint CONSTRAINT. */
422 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
424 struct address_info ad
;
426 decompose_lea_address (&ad
, &op
);
427 return satisfies_address_constraint_p (&ad
, constraint
);
430 /* Initiate equivalences for LRA. As we keep original equivalences
431 before any elimination, we need to make copies otherwise any change
432 in insns might change the equivalences. */
434 lra_init_equiv (void)
436 ira_expand_reg_equiv ();
437 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
441 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
442 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
443 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
444 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
448 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
450 /* Update equivalence for REGNO. We need to this as the equivalence
451 might contain other pseudos which are changed by their
454 update_equiv (int regno
)
458 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].memory
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
462 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
463 ira_reg_equiv
[regno
].invariant
464 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
468 /* If we have decided to substitute X with another value, return that
469 value, otherwise return X. */
476 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
477 || ! ira_reg_equiv
[regno
].defined_p
478 || ! ira_reg_equiv
[regno
].profitable_p
479 || lra_get_regno_hard_regno (regno
) >= 0)
481 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
), false, false, true);
503 /* Set up curr_operand_mode. */
505 init_curr_operand_mode (void)
507 int nop
= curr_static_id
->n_operands
;
508 for (int i
= 0; i
< nop
; i
++)
510 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
511 if (mode
== VOIDmode
)
513 /* The .md mode for address operands is the mode of the
514 addressed value rather than the mode of the address itself. */
515 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
518 mode
= curr_static_id
->operand
[i
].mode
;
520 curr_operand_mode
[i
] = mode
;
526 /* The page contains code to reuse input reloads. */
528 /* Structure describes input reload of the current insns. */
531 /* Reloaded value. */
533 /* Reload pseudo used. */
537 /* The number of elements in the following array. */
538 static int curr_insn_input_reloads_num
;
539 /* Array containing info about input reloads. It is used to find the
540 same input reload and reuse the reload pseudo in this case. */
541 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
543 /* Initiate data concerning reuse of input reloads for the current
546 init_curr_insn_input_reloads (void)
548 curr_insn_input_reloads_num
= 0;
551 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
552 created input reload pseudo (only if TYPE is not OP_OUT). Don't
553 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
554 wrapped up in SUBREG. The result pseudo is returned through
555 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
556 reused the already created input reload pseudo. Use TITLE to
557 describe new registers for debug purposes. */
559 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
560 enum reg_class rclass
, bool in_subreg_p
,
561 const char *title
, rtx
*result_reg
)
564 enum reg_class new_class
;
569 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
572 /* Prevent reuse value of expression with side effects,
573 e.g. volatile memory. */
574 if (! side_effects_p (original
))
575 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
576 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
577 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
579 rtx reg
= curr_insn_input_reloads
[i
].reg
;
581 /* If input is equal to original and both are VOIDmode,
582 GET_MODE (reg) might be still different from mode.
583 Ensure we don't return *result_reg with wrong mode. */
584 if (GET_MODE (reg
) != mode
)
588 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
590 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
591 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
595 if (lra_dump_file
!= NULL
)
597 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
598 dump_value_slim (lra_dump_file
, original
, 1);
600 if (new_class
!= lra_get_allocno_class (regno
))
601 lra_change_class (regno
, new_class
, ", change to", false);
602 if (lra_dump_file
!= NULL
)
603 fprintf (lra_dump_file
, "\n");
606 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
607 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
608 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
609 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
615 /* The page contains code to extract memory address parts. */
617 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
619 ok_for_index_p_nonstrict (rtx reg
)
621 unsigned regno
= REGNO (reg
);
623 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
626 /* A version of regno_ok_for_base_p for use here, when all pseudos
627 should count as OK. Arguments as for regno_ok_for_base_p. */
629 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
630 enum rtx_code outer_code
, enum rtx_code index_code
)
632 unsigned regno
= REGNO (reg
);
634 if (regno
>= FIRST_PSEUDO_REGISTER
)
636 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
641 /* The page contains major code to choose the current insn alternative
642 and generate reloads for it. */
644 /* Return the offset from REGNO of the least significant register
647 This function is used to tell whether two registers satisfy
648 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
650 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
651 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
653 lra_constraint_offset (int regno
, enum machine_mode mode
)
655 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
656 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
657 && SCALAR_INT_MODE_P (mode
))
658 return hard_regno_nregs
[regno
][mode
] - 1;
662 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
663 if they are the same hard reg, and has special hacks for
664 auto-increment and auto-decrement. This is specifically intended for
665 process_alt_operands to use in determining whether two operands
666 match. X is the operand whose number is the lower of the two.
668 It is supposed that X is the output operand and Y is the input
669 operand. Y_HARD_REGNO is the final hard regno of register Y or
670 register in subreg Y as we know it now. Otherwise, it is a
673 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
676 RTX_CODE code
= GET_CODE (x
);
681 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
682 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
686 i
= get_hard_regno (x
);
690 if ((j
= y_hard_regno
) < 0)
693 i
+= lra_constraint_offset (i
, GET_MODE (x
));
694 j
+= lra_constraint_offset (j
, GET_MODE (y
));
699 /* If two operands must match, because they are really a single
700 operand of an assembler insn, then two post-increments are invalid
701 because the assembler insn would increment only once. On the
702 other hand, a post-increment matches ordinary indexing if the
703 post-increment is the output operand. */
704 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
705 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
707 /* Two pre-increments are invalid because the assembler insn would
708 increment only once. On the other hand, a pre-increment matches
709 ordinary indexing if the pre-increment is the input operand. */
710 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
711 || GET_CODE (y
) == PRE_MODIFY
)
712 return operands_match_p (x
, XEXP (y
, 0), -1);
716 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
717 && x
== SUBREG_REG (y
))
719 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
720 && SUBREG_REG (x
) == y
)
723 /* Now we have disposed of all the cases in which different rtx
725 if (code
!= GET_CODE (y
))
728 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
729 if (GET_MODE (x
) != GET_MODE (y
))
738 return XEXP (x
, 0) == XEXP (y
, 0);
740 return XSTR (x
, 0) == XSTR (y
, 0);
746 /* Compare the elements. If any pair of corresponding elements fail
747 to match, return false for the whole things. */
749 fmt
= GET_RTX_FORMAT (code
);
750 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
756 if (XWINT (x
, i
) != XWINT (y
, i
))
761 if (XINT (x
, i
) != XINT (y
, i
))
766 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
775 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
777 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
779 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
785 /* It is believed that rtx's at this level will never
786 contain anything but integers and other rtx's, except for
787 within LABEL_REFs and SYMBOL_REFs. */
795 /* True if X is a constant that can be forced into the constant pool.
796 MODE is the mode of the operand, or VOIDmode if not known. */
797 #define CONST_POOL_OK_P(MODE, X) \
798 ((MODE) != VOIDmode \
800 && GET_CODE (X) != HIGH \
801 && !targetm.cannot_force_const_mem (MODE, X))
803 /* True if C is a non-empty register class that has too few registers
804 to be safely used as a reload target class. */
805 #define SMALL_REGISTER_CLASS_P(C) \
806 (ira_class_hard_regs_num [(C)] == 1 \
807 || (ira_class_hard_regs_num [(C)] >= 1 \
808 && targetm.class_likely_spilled_p (C)))
810 /* If REG is a reload pseudo, try to make its class satisfying CL. */
812 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
814 enum reg_class rclass
;
816 /* Do not make more accurate class from reloads generated. They are
817 mostly moves with a lot of constraints. Making more accurate
818 class may results in very narrow class and impossibility of find
819 registers for several reloads of one insn. */
820 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
822 if (GET_CODE (reg
) == SUBREG
)
823 reg
= SUBREG_REG (reg
);
824 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
826 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
827 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
830 /* Generate reloads for matching OUT and INS (array of input operand
831 numbers with end marker -1) with reg class GOAL_CLASS. Add input
832 and output reloads correspondingly to the lists *BEFORE and *AFTER.
833 OUT might be negative. In this case we generate input reloads for
834 matched input operands INS. */
836 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
837 rtx
*before
, rtx
*after
)
840 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
841 enum machine_mode inmode
, outmode
;
842 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
843 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
845 inmode
= curr_operand_mode
[ins
[0]];
846 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
847 push_to_sequence (*before
);
848 if (inmode
!= outmode
)
850 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
853 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
855 if (SCALAR_INT_MODE_P (inmode
))
856 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
858 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
859 LRA_SUBREG_P (new_out_reg
) = 1;
860 /* If the input reg is dying here, we can use the same hard
861 register for REG and IN_RTX. We do it only for original
862 pseudos as reload pseudos can die although original
863 pseudos still live where reload pseudos dies. */
864 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
865 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
866 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
871 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
873 if (SCALAR_INT_MODE_P (outmode
))
874 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
876 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
877 /* NEW_IN_REG is non-paradoxical subreg. We don't want
878 NEW_OUT_REG living above. We add clobber clause for
879 this. This is just a temporary clobber. We can remove
880 it at the end of LRA work. */
881 clobber
= emit_clobber (new_out_reg
);
882 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
883 LRA_SUBREG_P (new_in_reg
) = 1;
884 if (GET_CODE (in_rtx
) == SUBREG
)
886 rtx subreg_reg
= SUBREG_REG (in_rtx
);
888 /* If SUBREG_REG is dying here and sub-registers IN_RTX
889 and NEW_IN_REG are similar, we can use the same hard
890 register for REG and SUBREG_REG. */
891 if (REG_P (subreg_reg
)
892 && (int) REGNO (subreg_reg
) < lra_new_regno_start
893 && GET_MODE (subreg_reg
) == outmode
894 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
895 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
896 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
902 /* Pseudos have values -- see comments for lra_reg_info.
903 Different pseudos with the same value do not conflict even if
904 they live in the same place. When we create a pseudo we
905 assign value of original pseudo (if any) from which we
906 created the new pseudo. If we create the pseudo from the
907 input pseudo, the new pseudo will no conflict with the input
908 pseudo which is wrong when the input pseudo lives after the
909 insn and as the new pseudo value is changed by the insn
910 output. Therefore we create the new pseudo from the output.
912 We cannot reuse the current output register because we might
913 have a situation like "a <- a op b", where the constraints
914 force the second input operand ("b") to match the output
915 operand ("a"). "b" must then be copied into a new register
916 so that it doesn't clobber the current value of "a". */
918 new_in_reg
= new_out_reg
919 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
922 /* In operand can be got from transformations before processing insn
923 constraints. One example of such transformations is subreg
924 reloading (see function simplify_operand_subreg). The new
925 pseudos created by the transformations might have inaccurate
926 class (ALL_REGS) and we should make their classes more
928 narrow_reload_pseudo_class (in_rtx
, goal_class
);
929 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
930 *before
= get_insns ();
932 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
935 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
936 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
937 *curr_id
->operand_loc
[in
] = new_in_reg
;
939 lra_update_dups (curr_id
, ins
);
942 /* See a comment for the input operand above. */
943 narrow_reload_pseudo_class (out_rtx
, goal_class
);
944 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
947 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
949 *after
= get_insns ();
952 *curr_id
->operand_loc
[out
] = new_out_reg
;
953 lra_update_dup (curr_id
, out
);
956 /* Return register class which is union of all reg classes in insn
957 constraint alternative string starting with P. */
958 static enum reg_class
959 reg_class_from_constraints (const char *p
)
962 enum reg_class op_class
= NO_REGS
;
965 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
972 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
976 enum constraint_num cn
= lookup_constraint (p
);
977 enum reg_class cl
= reg_class_for_constraint (cn
);
980 if (insn_extra_address_constraint (cn
))
982 = (reg_class_subunion
983 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
988 op_class
= reg_class_subunion
[op_class
][cl
];
991 while ((p
+= len
), c
);
995 /* If OP is a register, return the class of the register as per
996 get_reg_class, otherwise return NO_REGS. */
997 static inline enum reg_class
998 get_op_class (rtx op
)
1000 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1003 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1004 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1005 SUBREG for VAL to make them equal. */
1007 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1009 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1011 /* Usually size of mem_pseudo is greater than val size but in
1012 rare cases it can be less as it can be defined by target
1013 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1016 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1017 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1019 LRA_SUBREG_P (val
) = 1;
1023 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1024 LRA_SUBREG_P (mem_pseudo
) = 1;
1028 ? gen_move_insn (mem_pseudo
, val
)
1029 : gen_move_insn (val
, mem_pseudo
));
1032 /* Process a special case insn (register move), return true if we
1033 don't need to process it anymore. INSN should be a single set
1034 insn. Set up that RTL was changed through CHANGE_P and macro
1035 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1038 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1041 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
1042 enum reg_class dclass
, sclass
, secondary_class
;
1043 enum machine_mode sreg_mode
;
1044 secondary_reload_info sri
;
1046 lra_assert (curr_insn_set
!= NULL_RTX
);
1047 dreg
= dest
= SET_DEST (curr_insn_set
);
1048 sreg
= src
= SET_SRC (curr_insn_set
);
1049 if (GET_CODE (dest
) == SUBREG
)
1050 dreg
= SUBREG_REG (dest
);
1051 if (GET_CODE (src
) == SUBREG
)
1052 sreg
= SUBREG_REG (src
);
1053 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1055 sclass
= dclass
= NO_REGS
;
1057 dclass
= get_reg_class (REGNO (dreg
));
1058 if (dclass
== ALL_REGS
)
1059 /* ALL_REGS is used for new pseudos created by transformations
1060 like reload of SUBREG_REG (see function
1061 simplify_operand_subreg). We don't know their class yet. We
1062 should figure out the class from processing the insn
1063 constraints not in this fast path function. Even if ALL_REGS
1064 were a right class for the pseudo, secondary_... hooks usually
1065 are not define for ALL_REGS. */
1067 sreg_mode
= GET_MODE (sreg
);
1070 sclass
= get_reg_class (REGNO (sreg
));
1071 if (sclass
== ALL_REGS
)
1072 /* See comments above. */
1074 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1076 #ifdef SECONDARY_MEMORY_NEEDED
1077 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1078 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1079 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1080 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1088 if (! REG_P (dreg
) || ! REG_P (sreg
))
1090 sri
.prev_sri
= NULL
;
1091 sri
.icode
= CODE_FOR_nothing
;
1093 secondary_class
= NO_REGS
;
1094 /* Set up hard register for a reload pseudo for hook
1095 secondary_reload because some targets just ignore unassigned
1096 pseudos in the hook. */
1097 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1099 dregno
= REGNO (dreg
);
1100 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1104 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1106 sregno
= REGNO (sreg
);
1107 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1111 if (sclass
!= NO_REGS
)
1113 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1114 (reg_class_t
) sclass
,
1115 GET_MODE (src
), &sri
);
1116 if (sclass
== NO_REGS
1117 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1118 && dclass
!= NO_REGS
))
1120 enum reg_class old_sclass
= secondary_class
;
1121 secondary_reload_info old_sri
= sri
;
1123 sri
.prev_sri
= NULL
;
1124 sri
.icode
= CODE_FOR_nothing
;
1127 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1128 (reg_class_t
) dclass
,
1130 /* Check the target hook consistency. */
1132 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1133 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1134 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1137 reg_renumber
[sregno
] = -1;
1139 reg_renumber
[dregno
] = -1;
1140 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1144 if (secondary_class
!= NO_REGS
)
1145 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1149 if (old_sreg
!= sreg
)
1150 sreg
= copy_rtx (sreg
);
1151 if (sri
.icode
== CODE_FOR_nothing
)
1152 lra_emit_move (new_reg
, sreg
);
1155 enum reg_class scratch_class
;
1157 scratch_class
= (reg_class_from_constraints
1158 (insn_data
[sri
.icode
].operand
[2].constraint
));
1159 scratch_reg
= (lra_create_new_reg_with_unique_value
1160 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1161 scratch_class
, "scratch"));
1162 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1163 sreg
, scratch_reg
));
1165 before
= get_insns ();
1167 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1168 if (new_reg
!= NULL_RTX
)
1170 if (GET_CODE (src
) == SUBREG
)
1171 SUBREG_REG (src
) = new_reg
;
1173 SET_SRC (curr_insn_set
) = new_reg
;
1177 if (lra_dump_file
!= NULL
)
1179 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1180 dump_insn_slim (lra_dump_file
, curr_insn
);
1182 lra_set_insn_deleted (curr_insn
);
1188 /* The following data describe the result of process_alt_operands.
1189 The data are used in curr_insn_transform to generate reloads. */
1191 /* The chosen reg classes which should be used for the corresponding
1193 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1194 /* True if the operand should be the same as another operand and that
1195 other operand does not need a reload. */
1196 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1197 /* True if the operand does not need a reload. */
1198 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1199 /* True if the operand can be offsetable memory. */
1200 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1201 /* The number of an operand to which given operand can be matched to. */
1202 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1203 /* The number of elements in the following array. */
1204 static int goal_alt_dont_inherit_ops_num
;
1205 /* Numbers of operands whose reload pseudos should not be inherited. */
1206 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1207 /* True if the insn commutative operands should be swapped. */
1208 static bool goal_alt_swapped
;
1209 /* The chosen insn alternative. */
1210 static int goal_alt_number
;
1212 /* The following five variables are used to choose the best insn
1213 alternative. They reflect final characteristics of the best
1216 /* Number of necessary reloads and overall cost reflecting the
1217 previous value and other unpleasantness of the best alternative. */
1218 static int best_losers
, best_overall
;
1219 /* Overall number hard registers used for reloads. For example, on
1220 some targets we need 2 general registers to reload DFmode and only
1221 one floating point register. */
1222 static int best_reload_nregs
;
1223 /* Overall number reflecting distances of previous reloading the same
1224 value. The distances are counted from the current BB start. It is
1225 used to improve inheritance chances. */
1226 static int best_reload_sum
;
1228 /* True if the current insn should have no correspondingly input or
1230 static bool no_input_reloads_p
, no_output_reloads_p
;
1232 /* True if we swapped the commutative operands in the current
1234 static int curr_swapped
;
1236 /* Arrange for address element *LOC to be a register of class CL.
1237 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1238 automodified value; handle that case by adding the required output
1239 reloads to list AFTER. Return true if the RTL was changed. */
1241 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1244 enum reg_class rclass
, new_class
;
1247 enum machine_mode mode
;
1248 bool subreg_p
, before_p
= false;
1250 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1252 loc
= &SUBREG_REG (*loc
);
1254 mode
= GET_MODE (reg
);
1257 /* Always reload memory in an address even if the target supports
1259 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1264 regno
= REGNO (reg
);
1265 rclass
= get_reg_class (regno
);
1266 if ((*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1268 if (lra_dump_file
!= NULL
)
1270 fprintf (lra_dump_file
,
1271 "Changing pseudo %d in address of insn %u on equiv ",
1272 REGNO (reg
), INSN_UID (curr_insn
));
1273 dump_value_slim (lra_dump_file
, *loc
, 1);
1274 fprintf (lra_dump_file
, "\n");
1276 *loc
= copy_rtx (*loc
);
1278 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1281 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1282 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1285 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1287 lra_change_class (regno
, new_class
, " Change to", true);
1295 push_to_sequence (*before
);
1296 lra_emit_move (new_reg
, reg
);
1297 *before
= get_insns ();
1304 lra_emit_move (reg
, new_reg
);
1306 *after
= get_insns ();
1312 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1313 the insn to be inserted before curr insn. AFTER returns the
1314 the insn to be inserted after curr insn. ORIGREG and NEWREG
1315 are the original reg and new reg for reload. */
1317 insert_move_for_subreg (rtx
*before
, rtx
*after
, rtx origreg
, rtx newreg
)
1321 push_to_sequence (*before
);
1322 lra_emit_move (newreg
, origreg
);
1323 *before
= get_insns ();
1329 lra_emit_move (origreg
, newreg
);
1331 *after
= get_insns ();
1336 /* Make reloads for subreg in operand NOP with internal subreg mode
1337 REG_MODE, add new reloads for further processing. Return true if
1338 any reload was generated. */
1340 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1344 enum machine_mode mode
;
1346 rtx operand
= *curr_id
->operand_loc
[nop
];
1347 enum reg_class regclass
;
1350 before
= after
= NULL_RTX
;
1352 if (GET_CODE (operand
) != SUBREG
)
1355 mode
= GET_MODE (operand
);
1356 reg
= SUBREG_REG (operand
);
1357 type
= curr_static_id
->operand
[nop
].type
;
1358 /* If we change address for paradoxical subreg of memory, the
1359 address might violate the necessary alignment or the access might
1360 be slow. So take this into consideration. We should not worry
1361 about access beyond allocated memory for paradoxical memory
1362 subregs as we don't substitute such equiv memory (see processing
1363 equivalences in function lra_constraints) and because for spilled
1364 pseudos we allocate stack memory enough for the biggest
1365 corresponding paradoxical subreg. */
1367 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1368 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1369 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1371 alter_subreg (curr_id
->operand_loc
[nop
], false);
1374 /* Put constant into memory when we have mixed modes. It generates
1375 a better code in most cases as it does not need a secondary
1376 reload memory. It also prevents LRA looping when LRA is using
1377 secondary reload memory again and again. */
1378 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1379 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1381 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1382 alter_subreg (curr_id
->operand_loc
[nop
], false);
1385 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1386 if there may be a problem accessing OPERAND in the outer
1389 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1390 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1391 /* Don't reload paradoxical subregs because we could be looping
1392 having repeatedly final regno out of hard regs range. */
1393 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1394 >= hard_regno_nregs
[hard_regno
][mode
])
1395 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1396 SUBREG_BYTE (operand
), mode
) < 0
1397 /* Don't reload subreg for matching reload. It is actually
1398 valid subreg in LRA. */
1399 && ! LRA_SUBREG_P (operand
))
1400 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1402 enum reg_class rclass
;
1405 /* There is a big probability that we will get the same class
1406 for the new pseudo and we will get the same insn which
1407 means infinite looping. So spill the new pseudo. */
1410 /* The class will be defined later in curr_insn_transform. */
1412 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1414 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1415 rclass
, TRUE
, "subreg reg", &new_reg
))
1417 bool insert_before
, insert_after
;
1418 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1420 insert_before
= (type
!= OP_OUT
1421 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1422 insert_after
= (type
!= OP_IN
);
1423 insert_move_for_subreg (insert_before
? &before
: NULL
,
1424 insert_after
? &after
: NULL
,
1427 SUBREG_REG (operand
) = new_reg
;
1428 lra_process_new_insns (curr_insn
, before
, after
,
1429 "Inserting subreg reload");
1432 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1433 IRA allocates hardreg to the inner pseudo reg according to its mode
1434 instead of the outermode, so the size of the hardreg may not be enough
1435 to contain the outermode operand, in that case we may need to insert
1436 reload for the reg. For the following two types of paradoxical subreg,
1437 we need to insert reload:
1438 1. If the op_type is OP_IN, and the hardreg could not be paired with
1439 other hardreg to contain the outermode operand
1440 (checked by in_hard_reg_set_p), we need to insert the reload.
1441 2. If the op_type is OP_OUT or OP_INOUT.
1443 Here is a paradoxical subreg example showing how the reload is generated:
1445 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1446 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1448 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1449 here, if reg107 is assigned to hardreg R15, because R15 is the last
1450 hardreg, compiler cannot find another hardreg to pair with R15 to
1451 contain TImode data. So we insert a TImode reload reg180 for it.
1452 After reload is inserted:
1454 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1455 (reg:DI 107 [ __comp ])) -1
1456 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1457 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1459 Two reload hard registers will be allocated to reg180 to save TImode data
1461 else if (REG_P (reg
)
1462 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1463 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1464 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1465 < hard_regno_nregs
[hard_regno
][mode
])
1466 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1468 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1471 /* The class will be defined later in curr_insn_transform. */
1472 enum reg_class rclass
1473 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1475 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1476 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1479 bool insert_before
, insert_after
;
1481 PUT_MODE (new_reg
, mode
);
1482 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1483 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1485 insert_before
= (type
!= OP_OUT
);
1486 insert_after
= (type
!= OP_IN
);
1487 insert_move_for_subreg (insert_before
? &before
: NULL
,
1488 insert_after
? &after
: NULL
,
1491 SUBREG_REG (operand
) = new_reg
;
1492 lra_process_new_insns (curr_insn
, before
, after
,
1493 "Inserting paradoxical subreg reload");
1499 /* Return TRUE if X refers for a hard register from SET. */
1501 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1503 int i
, j
, x_hard_regno
;
1504 enum machine_mode mode
;
1510 code
= GET_CODE (x
);
1511 mode
= GET_MODE (x
);
1515 code
= GET_CODE (x
);
1516 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1517 mode
= GET_MODE (x
);
1522 x_hard_regno
= get_hard_regno (x
);
1523 return (x_hard_regno
>= 0
1524 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1528 struct address_info ad
;
1530 decompose_mem_address (&ad
, x
);
1531 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1533 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1536 fmt
= GET_RTX_FORMAT (code
);
1537 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1541 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1544 else if (fmt
[i
] == 'E')
1546 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1547 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1554 /* Return true if OP is a spilled pseudo. */
1556 spilled_pseudo_p (rtx op
)
1559 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1562 /* Return true if X is a general constant. */
1564 general_constant_p (rtx x
)
1566 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1570 reg_in_class_p (rtx reg
, enum reg_class cl
)
1573 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1574 return in_class_p (reg
, cl
, NULL
);
1577 /* Major function to choose the current insn alternative and what
1578 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1579 negative we should consider only this alternative. Return false if
1580 we can not choose the alternative or find how to reload the
1583 process_alt_operands (int only_alternative
)
1586 int nop
, overall
, nalt
;
1587 int n_alternatives
= curr_static_id
->n_alternatives
;
1588 int n_operands
= curr_static_id
->n_operands
;
1589 /* LOSERS counts the operands that don't fit this alternative and
1590 would require loading. */
1592 /* REJECT is a count of how undesirable this alternative says it is
1593 if any reloading is required. If the alternative matches exactly
1594 then REJECT is ignored, but otherwise it gets this much counted
1595 against it in addition to the reloading needed. */
1597 /* The number of elements in the following array. */
1598 int early_clobbered_regs_num
;
1599 /* Numbers of operands which are early clobber registers. */
1600 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1601 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1602 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1603 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1604 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1605 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1606 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1607 /* The number of elements in the following array. */
1608 int curr_alt_dont_inherit_ops_num
;
1609 /* Numbers of operands whose reload pseudos should not be inherited. */
1610 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1612 /* The register when the operand is a subreg of register, otherwise the
1614 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1615 /* The register if the operand is a register or subreg of register,
1617 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1618 int hard_regno
[MAX_RECOG_OPERANDS
];
1619 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1620 int reload_nregs
, reload_sum
;
1624 /* Calculate some data common for all alternatives to speed up the
1626 for (nop
= 0; nop
< n_operands
; nop
++)
1630 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1631 /* The real hard regno of the operand after the allocation. */
1632 hard_regno
[nop
] = get_hard_regno (op
);
1634 operand_reg
[nop
] = reg
= op
;
1635 biggest_mode
[nop
] = GET_MODE (op
);
1636 if (GET_CODE (op
) == SUBREG
)
1638 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1639 if (GET_MODE_SIZE (biggest_mode
[nop
])
1640 < GET_MODE_SIZE (GET_MODE (reg
)))
1641 biggest_mode
[nop
] = GET_MODE (reg
);
1644 operand_reg
[nop
] = NULL_RTX
;
1645 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1646 || ((int) REGNO (reg
)
1647 == lra_get_elimination_hard_regno (REGNO (reg
))))
1648 no_subreg_reg_operand
[nop
] = reg
;
1650 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1651 /* Just use natural mode for elimination result. It should
1652 be enough for extra constraints hooks. */
1653 = regno_reg_rtx
[hard_regno
[nop
]];
1656 /* The constraints are made of several alternatives. Each operand's
1657 constraint looks like foo,bar,... with commas separating the
1658 alternatives. The first alternatives for all operands go
1659 together, the second alternatives go together, etc.
1661 First loop over alternatives. */
1662 alternative_mask enabled
= curr_id
->enabled_alternatives
;
1663 if (only_alternative
>= 0)
1664 enabled
&= ALTERNATIVE_BIT (only_alternative
);
1666 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1668 /* Loop over operands for one constraint alternative. */
1669 if (!TEST_BIT (enabled
, nalt
))
1672 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1673 for (nop
= 0; nop
< n_operands
; nop
++)
1675 int inc
= (curr_static_id
1676 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1677 if (lra_dump_file
!= NULL
&& inc
!= 0)
1678 fprintf (lra_dump_file
,
1679 " Staticly defined alt reject+=%d\n", inc
);
1682 early_clobbered_regs_num
= 0;
1684 for (nop
= 0; nop
< n_operands
; nop
++)
1688 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1689 bool win
, did_match
, offmemok
, early_clobber_p
;
1690 /* false => this operand can be reloaded somehow for this
1693 /* true => this operand can be reloaded if the alternative
1696 /* True if a constant forced into memory would be OK for
1699 enum reg_class this_alternative
, this_costly_alternative
;
1700 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1701 bool this_alternative_match_win
, this_alternative_win
;
1702 bool this_alternative_offmemok
;
1704 enum machine_mode mode
;
1705 enum constraint_num cn
;
1707 opalt_num
= nalt
* n_operands
+ nop
;
1708 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1710 /* Fast track for no constraints at all. */
1711 curr_alt
[nop
] = NO_REGS
;
1712 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1713 curr_alt_win
[nop
] = true;
1714 curr_alt_match_win
[nop
] = false;
1715 curr_alt_offmemok
[nop
] = false;
1716 curr_alt_matches
[nop
] = -1;
1720 op
= no_subreg_reg_operand
[nop
];
1721 mode
= curr_operand_mode
[nop
];
1723 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1726 early_clobber_p
= false;
1727 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1729 this_costly_alternative
= this_alternative
= NO_REGS
;
1730 /* We update set of possible hard regs besides its class
1731 because reg class might be inaccurate. For example,
1732 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1733 is translated in HI_REGS because classes are merged by
1734 pairs and there is no accurate intermediate class. */
1735 CLEAR_HARD_REG_SET (this_alternative_set
);
1736 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1737 this_alternative_win
= false;
1738 this_alternative_match_win
= false;
1739 this_alternative_offmemok
= false;
1740 this_alternative_matches
= -1;
1742 /* An empty constraint should be excluded by the fast
1744 lra_assert (*p
!= 0 && *p
!= ',');
1746 /* Scan this alternative's specs for this operand; set WIN
1747 if the operand fits any letter in this alternative.
1748 Otherwise, clear BADOP if this operand could fit some
1749 letter after reloads, or set WINREG if this operand could
1750 fit after reloads provided the constraint allows some
1755 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1765 early_clobber_p
= true;
1769 /* Ignore rest of this alternative. */
1773 case '0': case '1': case '2': case '3': case '4':
1774 case '5': case '6': case '7': case '8': case '9':
1779 m
= strtoul (p
, &end
, 10);
1782 lra_assert (nop
> m
);
1784 this_alternative_matches
= m
;
1785 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1786 /* We are supposed to match a previous operand.
1787 If we do, we win if that one did. If we do
1788 not, count both of the operands as losers.
1789 (This is too conservative, since most of the
1790 time only a single reload insn will be needed
1791 to make the two operands win. As a result,
1792 this alternative may be rejected when it is
1793 actually desirable.) */
1795 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1796 *curr_id
->operand_loc
[m
], m_hregno
))
1798 /* We should reject matching of an early
1799 clobber operand if the matching operand is
1800 not dying in the insn. */
1801 if (! curr_static_id
->operand
[m
].early_clobber
1802 || operand_reg
[nop
] == NULL_RTX
1803 || (find_regno_note (curr_insn
, REG_DEAD
,
1805 || REGNO (op
) == REGNO (operand_reg
[m
])))
1810 /* If we are matching a non-offsettable
1811 address where an offsettable address was
1812 expected, then we must reject this
1813 combination, because we can't reload
1815 if (curr_alt_offmemok
[m
]
1816 && MEM_P (*curr_id
->operand_loc
[m
])
1817 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1822 /* Operands don't match. Both operands must
1823 allow a reload register, otherwise we
1824 cannot make them match. */
1825 if (curr_alt
[m
] == NO_REGS
)
1827 /* Retroactively mark the operand we had to
1828 match as a loser, if it wasn't already and
1829 it wasn't matched to a register constraint
1830 (e.g it might be matched by memory). */
1832 && (operand_reg
[m
] == NULL_RTX
1833 || hard_regno
[m
] < 0))
1837 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1838 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1841 /* Prefer matching earlyclobber alternative as
1842 it results in less hard regs required for
1843 the insn than a non-matching earlyclobber
1845 if (curr_static_id
->operand
[m
].early_clobber
)
1847 if (lra_dump_file
!= NULL
)
1850 " %d Matching earlyclobber alt:"
1855 /* Otherwise we prefer no matching
1856 alternatives because it gives more freedom
1858 else if (operand_reg
[nop
] == NULL_RTX
1859 || (find_regno_note (curr_insn
, REG_DEAD
,
1860 REGNO (operand_reg
[nop
]))
1863 if (lra_dump_file
!= NULL
)
1866 " %d Matching alt: reject+=2\n",
1871 /* If we have to reload this operand and some
1872 previous operand also had to match the same
1873 thing as this operand, we don't know how to do
1875 if (!match_p
|| !curr_alt_win
[m
])
1877 for (i
= 0; i
< nop
; i
++)
1878 if (curr_alt_matches
[i
] == m
)
1886 /* This can be fixed with reloads if the operand
1887 we are supposed to match can be fixed with
1890 this_alternative
= curr_alt
[m
];
1891 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1892 winreg
= this_alternative
!= NO_REGS
;
1898 || general_constant_p (op
)
1899 || spilled_pseudo_p (op
))
1905 cn
= lookup_constraint (p
);
1906 switch (get_constraint_type (cn
))
1909 cl
= reg_class_for_constraint (cn
);
1915 if (CONST_INT_P (op
)
1916 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1922 && satisfies_memory_constraint_p (op
, cn
))
1924 else if (spilled_pseudo_p (op
))
1927 /* If we didn't already win, we can reload constants
1928 via force_const_mem or put the pseudo value into
1929 memory, or make other memory by reloading the
1930 address like for 'o'. */
1931 if (CONST_POOL_OK_P (mode
, op
)
1932 || MEM_P (op
) || REG_P (op
))
1939 /* If we didn't already win, we can reload the address
1940 into a base register. */
1941 if (satisfies_address_constraint_p (op
, cn
))
1943 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1949 if (constraint_satisfied_p (op
, cn
))
1956 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1957 IOR_HARD_REG_SET (this_alternative_set
,
1958 reg_class_contents
[cl
]);
1961 this_costly_alternative
1962 = reg_class_subunion
[this_costly_alternative
][cl
];
1963 IOR_HARD_REG_SET (this_costly_alternative_set
,
1964 reg_class_contents
[cl
]);
1966 if (mode
== BLKmode
)
1971 if (hard_regno
[nop
] >= 0
1972 && in_hard_reg_set_p (this_alternative_set
,
1973 mode
, hard_regno
[nop
]))
1975 else if (hard_regno
[nop
] < 0
1976 && in_class_p (op
, this_alternative
, NULL
))
1981 if (c
!= ' ' && c
!= '\t')
1982 costly_p
= c
== '*';
1984 while ((p
+= len
), c
);
1986 scratch_p
= (operand_reg
[nop
] != NULL_RTX
1987 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
1988 /* Record which operands fit this alternative. */
1991 this_alternative_win
= true;
1992 if (operand_reg
[nop
] != NULL_RTX
)
1994 if (hard_regno
[nop
] >= 0)
1996 if (in_hard_reg_set_p (this_costly_alternative_set
,
1997 mode
, hard_regno
[nop
]))
1999 if (lra_dump_file
!= NULL
)
2000 fprintf (lra_dump_file
,
2001 " %d Costly set: reject++\n",
2008 /* Prefer won reg to spilled pseudo under other
2009 equal conditions for possibe inheritance. */
2012 if (lra_dump_file
!= NULL
)
2015 " %d Non pseudo reload: reject++\n",
2019 if (in_class_p (operand_reg
[nop
],
2020 this_costly_alternative
, NULL
))
2022 if (lra_dump_file
!= NULL
)
2025 " %d Non pseudo costly reload:"
2031 /* We simulate the behaviour of old reload here.
2032 Although scratches need hard registers and it
2033 might result in spilling other pseudos, no reload
2034 insns are generated for the scratches. So it
2035 might cost something but probably less than old
2036 reload pass believes. */
2039 if (lra_dump_file
!= NULL
)
2040 fprintf (lra_dump_file
,
2041 " %d Scratch win: reject+=2\n",
2048 this_alternative_match_win
= true;
2051 int const_to_mem
= 0;
2054 /* Never do output reload of stack pointer. It makes
2055 impossible to do elimination when SP is changed in
2057 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2058 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2061 /* If this alternative asks for a specific reg class, see if there
2062 is at least one allocatable register in that class. */
2064 = (this_alternative
== NO_REGS
2065 || (hard_reg_set_subset_p
2066 (reg_class_contents
[this_alternative
],
2067 lra_no_alloc_regs
)));
2069 /* For asms, verify that the class for this alternative is possible
2070 for the mode that is specified. */
2071 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2074 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2075 if (HARD_REGNO_MODE_OK (i
, mode
)
2076 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2079 if (i
== FIRST_PSEUDO_REGISTER
)
2083 /* If this operand accepts a register, and if the
2084 register class has at least one allocatable register,
2085 then this operand can be reloaded. */
2086 if (winreg
&& !no_regs_p
)
2091 if (lra_dump_file
!= NULL
)
2092 fprintf (lra_dump_file
,
2093 " alt=%d: Bad operand -- refuse\n",
2098 /* If not assigned pseudo has a class which a subset of
2099 required reg class, it is a less costly alternative
2100 as the pseudo still can get a hard reg of necessary
2102 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2103 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2104 && ira_class_subset_p
[this_alternative
][cl
])
2106 if (lra_dump_file
!= NULL
)
2109 " %d Super set class reg: reject-=3\n", nop
);
2113 this_alternative_offmemok
= offmemok
;
2114 if (this_costly_alternative
!= NO_REGS
)
2116 if (lra_dump_file
!= NULL
)
2117 fprintf (lra_dump_file
,
2118 " %d Costly loser: reject++\n", nop
);
2121 /* If the operand is dying, has a matching constraint,
2122 and satisfies constraints of the matched operand
2123 which failed to satisfy the own constraints, most probably
2124 the reload for this operand will be gone. */
2125 if (this_alternative_matches
>= 0
2126 && !curr_alt_win
[this_alternative_matches
]
2128 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2129 && (hard_regno
[nop
] >= 0
2130 ? in_hard_reg_set_p (this_alternative_set
,
2131 mode
, hard_regno
[nop
])
2132 : in_class_p (op
, this_alternative
, NULL
)))
2134 if (lra_dump_file
!= NULL
)
2137 " %d Dying matched operand reload: reject++\n",
2143 /* Strict_low_part requires to reload the register
2144 not the sub-register. In this case we should
2145 check that a final reload hard reg can hold the
2147 if (curr_static_id
->operand
[nop
].strict_low
2149 && hard_regno
[nop
] < 0
2150 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2151 && ira_class_hard_regs_num
[this_alternative
] > 0
2152 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2153 [this_alternative
][0],
2155 (*curr_id
->operand_loc
[nop
])))
2157 if (lra_dump_file
!= NULL
)
2160 " alt=%d: Strict low subreg reload -- refuse\n",
2166 if (operand_reg
[nop
] != NULL_RTX
2167 /* Output operands and matched input operands are
2168 not inherited. The following conditions do not
2169 exactly describe the previous statement but they
2170 are pretty close. */
2171 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2172 && (this_alternative_matches
< 0
2173 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2175 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2179 /* The value of reload_sum has sense only if we
2180 process insns in their order. It happens only on
2181 the first constraints sub-pass when we do most of
2183 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2184 reload_sum
+= last_reload
- bb_reload_num
;
2186 /* If this is a constant that is reloaded into the
2187 desired class by copying it to memory first, count
2188 that as another reload. This is consistent with
2189 other code and is required to avoid choosing another
2190 alternative when the constant is moved into memory.
2191 Note that the test here is precisely the same as in
2192 the code below that calls force_const_mem. */
2193 if (CONST_POOL_OK_P (mode
, op
)
2194 && ((targetm
.preferred_reload_class
2195 (op
, this_alternative
) == NO_REGS
)
2196 || no_input_reloads_p
))
2203 /* Alternative loses if it requires a type of reload not
2204 permitted for this insn. We can always reload
2205 objects with a REG_UNUSED note. */
2206 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2207 && no_output_reloads_p
2208 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2209 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2210 && no_input_reloads_p
&& ! const_to_mem
)
2211 || (this_alternative_matches
>= 0
2212 && (no_input_reloads_p
2213 || (no_output_reloads_p
2214 && (curr_static_id
->operand
2215 [this_alternative_matches
].type
!= OP_IN
)
2216 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2217 no_subreg_reg_operand
2218 [this_alternative_matches
])))))
2220 if (lra_dump_file
!= NULL
)
2223 " alt=%d: No input/otput reload -- refuse\n",
2228 /* Check strong discouragement of reload of non-constant
2229 into class THIS_ALTERNATIVE. */
2230 if (! CONSTANT_P (op
) && ! no_regs_p
2231 && (targetm
.preferred_reload_class
2232 (op
, this_alternative
) == NO_REGS
2233 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2234 && (targetm
.preferred_output_reload_class
2235 (op
, this_alternative
) == NO_REGS
))))
2237 if (lra_dump_file
!= NULL
)
2238 fprintf (lra_dump_file
,
2239 " %d Non-prefered reload: reject+=%d\n",
2240 nop
, LRA_MAX_REJECT
);
2241 reject
+= LRA_MAX_REJECT
;
2244 if (! (MEM_P (op
) && offmemok
)
2245 && ! (const_to_mem
&& constmemok
))
2247 /* We prefer to reload pseudos over reloading other
2248 things, since such reloads may be able to be
2249 eliminated later. So bump REJECT in other cases.
2250 Don't do this in the case where we are forcing a
2251 constant into memory and it will then win since
2252 we don't want to have a different alternative
2254 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2256 if (lra_dump_file
!= NULL
)
2259 " %d Non-pseudo reload: reject+=2\n",
2266 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2268 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2270 if (lra_dump_file
!= NULL
)
2273 " %d Small class reload: reject+=%d\n",
2274 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2275 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2279 /* We are trying to spill pseudo into memory. It is
2280 usually more costly than moving to a hard register
2281 although it might takes the same number of
2283 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2285 if (lra_dump_file
!= NULL
)
2288 " %d Spill pseudo into memory: reject+=3\n",
2291 if (VECTOR_MODE_P (mode
))
2293 /* Spilling vectors into memory is usually more
2294 costly as they contain big values. */
2295 if (lra_dump_file
!= NULL
)
2298 " %d Spill vector pseudo: reject+=2\n",
2304 #ifdef SECONDARY_MEMORY_NEEDED
2305 /* If reload requires moving value through secondary
2306 memory, it will need one more insn at least. */
2307 if (this_alternative
!= NO_REGS
2308 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2309 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2310 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2312 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2313 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2317 /* Input reloads can be inherited more often than output
2318 reloads can be removed, so penalize output
2320 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2322 if (lra_dump_file
!= NULL
)
2325 " %d Non input pseudo reload: reject++\n",
2331 if (early_clobber_p
&& ! scratch_p
)
2333 if (lra_dump_file
!= NULL
)
2334 fprintf (lra_dump_file
,
2335 " %d Early clobber: reject++\n", nop
);
2338 /* ??? We check early clobbers after processing all operands
2339 (see loop below) and there we update the costs more.
2340 Should we update the cost (may be approximately) here
2341 because of early clobber register reloads or it is a rare
2342 or non-important thing to be worth to do it. */
2343 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2344 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2346 if (lra_dump_file
!= NULL
)
2347 fprintf (lra_dump_file
,
2348 " alt=%d,overall=%d,losers=%d -- refuse\n",
2349 nalt
, overall
, losers
);
2353 curr_alt
[nop
] = this_alternative
;
2354 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2355 curr_alt_win
[nop
] = this_alternative_win
;
2356 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2357 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2358 curr_alt_matches
[nop
] = this_alternative_matches
;
2360 if (this_alternative_matches
>= 0
2361 && !did_match
&& !this_alternative_win
)
2362 curr_alt_win
[this_alternative_matches
] = false;
2364 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2365 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2367 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2368 /* Prevent processing non-move insns. */
2369 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2370 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2371 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2372 && REG_P (no_subreg_reg_operand
[0])
2373 && REG_P (no_subreg_reg_operand
[1])
2374 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2375 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2376 || (! curr_alt_win
[0] && curr_alt_win
[1]
2377 && REG_P (no_subreg_reg_operand
[1])
2378 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2379 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2380 && REG_P (no_subreg_reg_operand
[0])
2381 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2382 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2383 no_subreg_reg_operand
[1])
2384 || (targetm
.preferred_reload_class
2385 (no_subreg_reg_operand
[1],
2386 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2387 /* If it is a result of recent elimination in move
2388 insn we can transform it into an add still by
2389 using this alternative. */
2390 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2392 /* We have a move insn and a new reload insn will be similar
2393 to the current insn. We should avoid such situation as it
2394 results in LRA cycling. */
2395 overall
+= LRA_MAX_REJECT
;
2398 curr_alt_dont_inherit_ops_num
= 0;
2399 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2401 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2402 HARD_REG_SET temp_set
;
2404 i
= early_clobbered_nops
[nop
];
2405 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2406 || hard_regno
[i
] < 0)
2408 lra_assert (operand_reg
[i
] != NULL_RTX
);
2409 clobbered_hard_regno
= hard_regno
[i
];
2410 CLEAR_HARD_REG_SET (temp_set
);
2411 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2412 first_conflict_j
= last_conflict_j
= -1;
2413 for (j
= 0; j
< n_operands
; j
++)
2415 /* We don't want process insides of match_operator and
2416 match_parallel because otherwise we would process
2417 their operands once again generating a wrong
2419 || curr_static_id
->operand
[j
].is_operator
)
2421 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2422 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2424 /* If we don't reload j-th operand, check conflicts. */
2425 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2426 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2428 if (first_conflict_j
< 0)
2429 first_conflict_j
= j
;
2430 last_conflict_j
= j
;
2432 if (last_conflict_j
< 0)
2434 /* If earlyclobber operand conflicts with another
2435 non-matching operand which is actually the same register
2436 as the earlyclobber operand, it is better to reload the
2437 another operand as an operand matching the earlyclobber
2438 operand can be also the same. */
2439 if (first_conflict_j
== last_conflict_j
2440 && operand_reg
[last_conflict_j
]
2441 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2442 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2444 curr_alt_win
[last_conflict_j
] = false;
2445 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2448 /* Early clobber was already reflected in REJECT. */
2449 lra_assert (reject
> 0);
2450 if (lra_dump_file
!= NULL
)
2453 " %d Conflict early clobber reload: reject--\n",
2456 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2460 /* We need to reload early clobbered register and the
2461 matched registers. */
2462 for (j
= 0; j
< n_operands
; j
++)
2463 if (curr_alt_matches
[j
] == i
)
2465 curr_alt_match_win
[j
] = false;
2467 overall
+= LRA_LOSER_COST_FACTOR
;
2469 if (! curr_alt_match_win
[i
])
2470 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2473 /* Remember pseudos used for match reloads are never
2475 lra_assert (curr_alt_matches
[i
] >= 0);
2476 curr_alt_win
[curr_alt_matches
[i
]] = false;
2478 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2480 /* Early clobber was already reflected in REJECT. */
2481 lra_assert (reject
> 0);
2482 if (lra_dump_file
!= NULL
)
2485 " %d Matched conflict early clobber reloads:"
2489 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2492 if (lra_dump_file
!= NULL
)
2493 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2494 nalt
, overall
, losers
, reload_nregs
);
2496 /* If this alternative can be made to work by reloading, and it
2497 needs less reloading than the others checked so far, record
2498 it as the chosen goal for reloading. */
2499 if ((best_losers
!= 0 && losers
== 0)
2500 || (((best_losers
== 0 && losers
== 0)
2501 || (best_losers
!= 0 && losers
!= 0))
2502 && (best_overall
> overall
2503 || (best_overall
== overall
2504 /* If the cost of the reloads is the same,
2505 prefer alternative which requires minimal
2506 number of reload regs. */
2507 && (reload_nregs
< best_reload_nregs
2508 || (reload_nregs
== best_reload_nregs
2509 && (best_reload_sum
< reload_sum
2510 || (best_reload_sum
== reload_sum
2511 && nalt
< goal_alt_number
))))))))
2513 for (nop
= 0; nop
< n_operands
; nop
++)
2515 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2516 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2517 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2518 goal_alt
[nop
] = curr_alt
[nop
];
2519 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2521 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2522 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2523 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2524 goal_alt_swapped
= curr_swapped
;
2525 best_overall
= overall
;
2526 best_losers
= losers
;
2527 best_reload_nregs
= reload_nregs
;
2528 best_reload_sum
= reload_sum
;
2529 goal_alt_number
= nalt
;
2532 /* Everything is satisfied. Do not process alternatives
2541 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2543 base_plus_disp_to_reg (struct address_info
*ad
)
2548 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2549 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2550 get_index_code (ad
));
2551 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2553 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2557 /* Make reload of index part of address AD. Return the new
2560 index_part_to_reg (struct address_info
*ad
)
2564 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
2565 INDEX_REG_CLASS
, "index term");
2566 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
2567 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
2571 /* Return true if we can add a displacement to address AD, even if that
2572 makes the address invalid. The fix-up code requires any new address
2573 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2575 can_add_disp_p (struct address_info
*ad
)
2577 return (!ad
->autoinc_p
2578 && ad
->segment
== NULL
2579 && ad
->base
== ad
->base_term
2580 && ad
->disp
== ad
->disp_term
);
2583 /* Make equiv substitution in address AD. Return true if a substitution
2586 equiv_address_substitution (struct address_info
*ad
)
2588 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2589 HOST_WIDE_INT disp
, scale
;
2592 base_term
= strip_subreg (ad
->base_term
);
2593 if (base_term
== NULL
)
2594 base_reg
= new_base_reg
= NULL_RTX
;
2597 base_reg
= *base_term
;
2598 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
2600 index_term
= strip_subreg (ad
->index_term
);
2601 if (index_term
== NULL
)
2602 index_reg
= new_index_reg
= NULL_RTX
;
2605 index_reg
= *index_term
;
2606 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
2608 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2612 if (lra_dump_file
!= NULL
)
2614 fprintf (lra_dump_file
, "Changing address in insn %d ",
2615 INSN_UID (curr_insn
));
2616 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2618 if (base_reg
!= new_base_reg
)
2620 if (REG_P (new_base_reg
))
2622 *base_term
= new_base_reg
;
2625 else if (GET_CODE (new_base_reg
) == PLUS
2626 && REG_P (XEXP (new_base_reg
, 0))
2627 && CONST_INT_P (XEXP (new_base_reg
, 1))
2628 && can_add_disp_p (ad
))
2630 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2631 *base_term
= XEXP (new_base_reg
, 0);
2634 if (ad
->base_term2
!= NULL
)
2635 *ad
->base_term2
= *ad
->base_term
;
2637 if (index_reg
!= new_index_reg
)
2639 if (REG_P (new_index_reg
))
2641 *index_term
= new_index_reg
;
2644 else if (GET_CODE (new_index_reg
) == PLUS
2645 && REG_P (XEXP (new_index_reg
, 0))
2646 && CONST_INT_P (XEXP (new_index_reg
, 1))
2647 && can_add_disp_p (ad
)
2648 && (scale
= get_index_scale (ad
)))
2650 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2651 *index_term
= XEXP (new_index_reg
, 0);
2657 if (ad
->disp
!= NULL
)
2658 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2661 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2662 update_address (ad
);
2666 if (lra_dump_file
!= NULL
)
2669 fprintf (lra_dump_file
, " -- no change\n");
2672 fprintf (lra_dump_file
, " on equiv ");
2673 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2674 fprintf (lra_dump_file
, "\n");
2680 /* Major function to make reloads for an address in operand NOP.
2681 The supported cases are:
2683 1) an address that existed before LRA started, at which point it
2684 must have been valid. These addresses are subject to elimination
2685 and may have become invalid due to the elimination offset being out
2688 2) an address created by forcing a constant to memory
2689 (force_const_to_mem). The initial form of these addresses might
2690 not be valid, and it is this function's job to make them valid.
2692 3) a frame address formed from a register and a (possibly zero)
2693 constant offset. As above, these addresses might not be valid and
2694 this function must make them so.
2696 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2697 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2698 address. Return true for any RTL change.
2700 The function is a helper function which does not produce all
2701 transformations which can be necessary. It does just basic steps.
2702 To do all necessary transformations use function
2705 process_address_1 (int nop
, rtx
*before
, rtx
*after
)
2707 struct address_info ad
;
2709 rtx op
= *curr_id
->operand_loc
[nop
];
2710 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2711 enum constraint_num cn
= lookup_constraint (constraint
);
2714 if (insn_extra_address_constraint (cn
))
2715 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2716 else if (MEM_P (op
))
2717 decompose_mem_address (&ad
, op
);
2718 else if (GET_CODE (op
) == SUBREG
2719 && MEM_P (SUBREG_REG (op
)))
2720 decompose_mem_address (&ad
, SUBREG_REG (op
));
2723 change_p
= equiv_address_substitution (&ad
);
2724 if (ad
.base_term
!= NULL
2725 && (process_addr_reg
2726 (ad
.base_term
, before
,
2728 && !(REG_P (*ad
.base_term
)
2729 && find_regno_note (curr_insn
, REG_DEAD
,
2730 REGNO (*ad
.base_term
)) != NULL_RTX
)
2732 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2733 get_index_code (&ad
)))))
2736 if (ad
.base_term2
!= NULL
)
2737 *ad
.base_term2
= *ad
.base_term
;
2739 if (ad
.index_term
!= NULL
2740 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2743 /* Target hooks sometimes don't treat extra-constraint addresses as
2744 legitimate address_operands, so handle them specially. */
2745 if (insn_extra_address_constraint (cn
)
2746 && satisfies_address_constraint_p (&ad
, cn
))
2749 /* There are three cases where the shape of *AD.INNER may now be invalid:
2751 1) the original address was valid, but either elimination or
2752 equiv_address_substitution was applied and that made
2753 the address invalid.
2755 2) the address is an invalid symbolic address created by
2758 3) the address is a frame address with an invalid offset.
2760 All these cases involve a non-autoinc address, so there is no
2761 point revalidating other types. */
2762 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2765 /* Any index existed before LRA started, so we can assume that the
2766 presence and shape of the index is valid. */
2767 push_to_sequence (*before
);
2768 lra_assert (ad
.disp
== ad
.disp_term
);
2769 if (ad
.base
== NULL
)
2771 if (ad
.index
== NULL
)
2774 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2776 rtx addr
= *ad
.inner
;
2778 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2782 rtx last
= get_last_insn ();
2784 /* addr => lo_sum (new_base, addr), case (2) above. */
2785 insn
= emit_insn (gen_rtx_SET
2787 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2788 code
= recog_memoized (insn
);
2791 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2792 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2794 /* Try to put lo_sum into register. */
2795 insn
= emit_insn (gen_rtx_SET
2797 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2798 code
= recog_memoized (insn
);
2801 *ad
.inner
= new_reg
;
2802 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2812 delete_insns_since (last
);
2817 /* addr => new_base, case (2) above. */
2818 lra_emit_move (new_reg
, addr
);
2819 *ad
.inner
= new_reg
;
2824 /* index * scale + disp => new base + index * scale,
2826 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2827 GET_CODE (*ad
.index
));
2829 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2830 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2831 lra_emit_move (new_reg
, *ad
.disp
);
2832 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2833 new_reg
, *ad
.index
);
2836 else if (ad
.index
== NULL
)
2840 rtx set
, insns
, last_insn
;
2841 /* base + disp => new base, cases (1) and (3) above. */
2842 /* Another option would be to reload the displacement into an
2843 index register. However, postreload has code to optimize
2844 address reloads that have the same base and different
2845 displacements, so reloading into an index register would
2846 not necessarily be a win. */
2848 new_reg
= base_plus_disp_to_reg (&ad
);
2849 insns
= get_insns ();
2850 last_insn
= get_last_insn ();
2851 /* If we generated at least two insns, try last insn source as
2852 an address. If we succeed, we generate one less insn. */
2853 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2854 && GET_CODE (SET_SRC (set
)) == PLUS
2855 && REG_P (XEXP (SET_SRC (set
), 0))
2856 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2858 *ad
.inner
= SET_SRC (set
);
2859 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2861 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2862 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2863 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2864 get_index_code (&ad
));
2865 regno
= REGNO (*ad
.base_term
);
2866 if (regno
>= FIRST_PSEUDO_REGISTER
2867 && cl
!= lra_get_allocno_class (regno
))
2868 lra_change_class (regno
, cl
, " Change to", true);
2869 new_reg
= SET_SRC (set
);
2870 delete_insns_since (PREV_INSN (last_insn
));
2875 *ad
.inner
= new_reg
;
2877 else if (ad
.disp_term
!= NULL
)
2879 /* base + scale * index + disp => new base + scale * index,
2881 new_reg
= base_plus_disp_to_reg (&ad
);
2882 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2883 new_reg
, *ad
.index
);
2885 else if (get_index_scale (&ad
) == 1)
2887 /* The last transformation to one reg will be made in
2888 curr_insn_transform function. */
2894 /* base + scale * index => base + new_reg,
2896 Index part of address may become invalid. For example, we
2897 changed pseudo on the equivalent memory and a subreg of the
2898 pseudo onto the memory of different mode for which the scale is
2900 new_reg
= index_part_to_reg (&ad
);
2901 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2902 *ad
.base_term
, new_reg
);
2904 *before
= get_insns ();
2909 /* Do address reloads until it is necessary. Use process_address_1 as
2910 a helper function. Return true for any RTL changes. */
2912 process_address (int nop
, rtx
*before
, rtx
*after
)
2916 while (process_address_1 (nop
, before
, after
))
2921 /* Emit insns to reload VALUE into a new register. VALUE is an
2922 auto-increment or auto-decrement RTX whose operand is a register or
2923 memory location; so reloading involves incrementing that location.
2924 IN is either identical to VALUE, or some cheaper place to reload
2925 value being incremented/decremented from.
2927 INC_AMOUNT is the number to increment or decrement by (always
2928 positive and ignored for POST_MODIFY/PRE_MODIFY).
2930 Return pseudo containing the result. */
2932 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2934 /* REG or MEM to be copied and incremented. */
2935 rtx incloc
= XEXP (value
, 0);
2936 /* Nonzero if increment after copying. */
2937 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2938 || GET_CODE (value
) == POST_MODIFY
);
2943 rtx real_in
= in
== value
? incloc
: in
;
2947 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2949 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2950 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2951 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2952 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2953 inc
= XEXP (XEXP (value
, 1), 1);
2957 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2958 inc_amount
= -inc_amount
;
2960 inc
= GEN_INT (inc_amount
);
2963 if (! post
&& REG_P (incloc
))
2966 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2969 if (real_in
!= result
)
2971 /* First copy the location to the result register. */
2972 lra_assert (REG_P (result
));
2973 emit_insn (gen_move_insn (result
, real_in
));
2976 /* We suppose that there are insns to add/sub with the constant
2977 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2978 old reload worked with this assumption. If the assumption
2979 becomes wrong, we should use approach in function
2980 base_plus_disp_to_reg. */
2983 /* See if we can directly increment INCLOC. */
2984 last
= get_last_insn ();
2985 add_insn
= emit_insn (plus_p
2986 ? gen_add2_insn (incloc
, inc
)
2987 : gen_sub2_insn (incloc
, inc
));
2989 code
= recog_memoized (add_insn
);
2992 if (! post
&& result
!= incloc
)
2993 emit_insn (gen_move_insn (result
, incloc
));
2996 delete_insns_since (last
);
2999 /* If couldn't do the increment directly, must increment in RESULT.
3000 The way we do this depends on whether this is pre- or
3001 post-increment. For pre-increment, copy INCLOC to the reload
3002 register, increment it there, then save back. */
3005 if (real_in
!= result
)
3006 emit_insn (gen_move_insn (result
, real_in
));
3008 emit_insn (gen_add2_insn (result
, inc
));
3010 emit_insn (gen_sub2_insn (result
, inc
));
3011 if (result
!= incloc
)
3012 emit_insn (gen_move_insn (incloc
, result
));
3018 Because this might be a jump insn or a compare, and because
3019 RESULT may not be available after the insn in an input
3020 reload, we must do the incrementing before the insn being
3023 We have already copied IN to RESULT. Increment the copy in
3024 RESULT, save that back, then decrement RESULT so it has
3025 the original value. */
3027 emit_insn (gen_add2_insn (result
, inc
));
3029 emit_insn (gen_sub2_insn (result
, inc
));
3030 emit_insn (gen_move_insn (incloc
, result
));
3031 /* Restore non-modified value for the result. We prefer this
3032 way because it does not require an additional hard
3036 if (CONST_INT_P (inc
))
3037 emit_insn (gen_add2_insn (result
,
3038 gen_int_mode (-INTVAL (inc
),
3039 GET_MODE (result
))));
3041 emit_insn (gen_sub2_insn (result
, inc
));
3044 emit_insn (gen_add2_insn (result
, inc
));
3049 /* Return true if the current move insn does not need processing as we
3050 already know that it satisfies its constraints. */
3052 simple_move_p (void)
3055 enum reg_class dclass
, sclass
;
3057 lra_assert (curr_insn_set
!= NULL_RTX
);
3058 dest
= SET_DEST (curr_insn_set
);
3059 src
= SET_SRC (curr_insn_set
);
3060 return ((dclass
= get_op_class (dest
)) != NO_REGS
3061 && (sclass
= get_op_class (src
)) != NO_REGS
3062 /* The backend guarantees that register moves of cost 2
3063 never need reloads. */
3064 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
3067 /* Swap operands NOP and NOP + 1. */
3069 swap_operands (int nop
)
3071 enum machine_mode mode
= curr_operand_mode
[nop
];
3072 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
3073 curr_operand_mode
[nop
+ 1] = mode
;
3074 rtx x
= *curr_id
->operand_loc
[nop
];
3075 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
3076 *curr_id
->operand_loc
[nop
+ 1] = x
;
3077 /* Swap the duplicates too. */
3078 lra_update_dup (curr_id
, nop
);
3079 lra_update_dup (curr_id
, nop
+ 1);
3082 /* Main entry point of the constraint code: search the body of the
3083 current insn to choose the best alternative. It is mimicking insn
3084 alternative cost calculation model of former reload pass. That is
3085 because machine descriptions were written to use this model. This
3086 model can be changed in future. Make commutative operand exchange
3089 Return true if some RTL changes happened during function call. */
3091 curr_insn_transform (void)
3097 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3098 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3101 /* Flag that the insn has been changed through a transformation. */
3104 #ifdef SECONDARY_MEMORY_NEEDED
3107 int max_regno_before
;
3108 int reused_alternative_num
;
3110 curr_insn_set
= single_set (curr_insn
);
3111 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3114 no_input_reloads_p
= no_output_reloads_p
= false;
3115 goal_alt_number
= -1;
3116 change_p
= sec_mem_p
= false;
3117 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3118 reloads; neither are insns that SET cc0. Insns that use CC0 are
3119 not allowed to have any input reloads. */
3120 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3121 no_output_reloads_p
= true;
3124 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3125 no_input_reloads_p
= true;
3126 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3127 no_output_reloads_p
= true;
3130 n_operands
= curr_static_id
->n_operands
;
3131 n_alternatives
= curr_static_id
->n_alternatives
;
3133 /* Just return "no reloads" if insn has no operands with
3135 if (n_operands
== 0 || n_alternatives
== 0)
3138 max_regno_before
= max_reg_num ();
3140 for (i
= 0; i
< n_operands
; i
++)
3142 goal_alt_matched
[i
][0] = -1;
3143 goal_alt_matches
[i
] = -1;
3146 commutative
= curr_static_id
->commutative
;
3148 /* Now see what we need for pseudos that didn't get hard regs or got
3149 the wrong kind of hard reg. For this, we must consider all the
3150 operands together against the register constraints. */
3152 best_losers
= best_overall
= INT_MAX
;
3153 best_reload_sum
= 0;
3155 curr_swapped
= false;
3156 goal_alt_swapped
= false;
3158 /* Make equivalence substitution and memory subreg elimination
3159 before address processing because an address legitimacy can
3160 depend on memory mode. */
3161 for (i
= 0; i
< n_operands
; i
++)
3163 rtx op
= *curr_id
->operand_loc
[i
];
3164 rtx subst
, old
= op
;
3165 bool op_change_p
= false;
3167 if (GET_CODE (old
) == SUBREG
)
3168 old
= SUBREG_REG (old
);
3169 subst
= get_equiv_with_elimination (old
, curr_insn
);
3172 subst
= copy_rtx (subst
);
3173 lra_assert (REG_P (old
));
3174 if (GET_CODE (op
) == SUBREG
)
3175 SUBREG_REG (op
) = subst
;
3177 *curr_id
->operand_loc
[i
] = subst
;
3178 if (lra_dump_file
!= NULL
)
3180 fprintf (lra_dump_file
,
3181 "Changing pseudo %d in operand %i of insn %u on equiv ",
3182 REGNO (old
), i
, INSN_UID (curr_insn
));
3183 dump_value_slim (lra_dump_file
, subst
, 1);
3184 fprintf (lra_dump_file
, "\n");
3186 op_change_p
= change_p
= true;
3188 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3191 lra_update_dup (curr_id
, i
);
3195 /* Reload address registers and displacements. We do it before
3196 finding an alternative because of memory constraints. */
3197 before
= after
= NULL_RTX
;
3198 for (i
= 0; i
< n_operands
; i
++)
3199 if (! curr_static_id
->operand
[i
].is_operator
3200 && process_address (i
, &before
, &after
))
3203 lra_update_dup (curr_id
, i
);
3207 /* If we've changed the instruction then any alternative that
3208 we chose previously may no longer be valid. */
3209 lra_set_used_insn_alternative (curr_insn
, -1);
3211 if (curr_insn_set
!= NULL_RTX
3212 && check_and_process_move (&change_p
, &sec_mem_p
))
3217 reused_alternative_num
= curr_id
->used_insn_alternative
;
3218 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3219 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3220 reused_alternative_num
, INSN_UID (curr_insn
));
3222 if (process_alt_operands (reused_alternative_num
))
3225 /* If insn is commutative (it's safe to exchange a certain pair of
3226 operands) then we need to try each alternative twice, the second
3227 time matching those two operands as if we had exchanged them. To
3228 do this, really exchange them in operands.
3230 If we have just tried the alternatives the second time, return
3231 operands to normal and drop through. */
3233 if (reused_alternative_num
< 0 && commutative
>= 0)
3235 curr_swapped
= !curr_swapped
;
3238 swap_operands (commutative
);
3242 swap_operands (commutative
);
3245 if (! alt_p
&& ! sec_mem_p
)
3247 /* No alternative works with reloads?? */
3248 if (INSN_CODE (curr_insn
) >= 0)
3249 fatal_insn ("unable to generate reloads for:", curr_insn
);
3250 error_for_asm (curr_insn
,
3251 "inconsistent operand constraints in an %<asm%>");
3252 /* Avoid further trouble with this insn. */
3253 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3254 lra_invalidate_insn_data (curr_insn
);
3258 /* If the best alternative is with operands 1 and 2 swapped, swap
3259 them. Update the operand numbers of any reloads already
3262 if (goal_alt_swapped
)
3264 if (lra_dump_file
!= NULL
)
3265 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3266 INSN_UID (curr_insn
));
3268 /* Swap the duplicates too. */
3269 swap_operands (commutative
);
3273 #ifdef SECONDARY_MEMORY_NEEDED
3274 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3275 too conservatively. So we use the secondary memory only if there
3276 is no any alternative without reloads. */
3277 use_sec_mem_p
= false;
3279 use_sec_mem_p
= true;
3282 for (i
= 0; i
< n_operands
; i
++)
3283 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3285 use_sec_mem_p
= i
< n_operands
;
3290 rtx new_reg
, src
, dest
, rld
;
3291 enum machine_mode sec_mode
, rld_mode
;
3293 lra_assert (sec_mem_p
);
3294 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3295 && curr_static_id
->operand
[1].type
== OP_IN
);
3296 dest
= *curr_id
->operand_loc
[0];
3297 src
= *curr_id
->operand_loc
[1];
3298 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3300 rld_mode
= GET_MODE (rld
);
3301 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3302 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3304 sec_mode
= rld_mode
;
3306 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3307 NO_REGS
, "secondary");
3308 /* If the mode is changed, it should be wider. */
3309 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3310 if (sec_mode
!= rld_mode
)
3312 /* If the target says specifically to use another mode for
3313 secondary memory moves we can not reuse the original
3315 after
= emit_spill_move (false, new_reg
, dest
);
3316 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3317 "Inserting the sec. move");
3318 /* We may have non null BEFORE here (e.g. after address
3320 push_to_sequence (before
);
3321 before
= emit_spill_move (true, new_reg
, src
);
3323 before
= get_insns ();
3325 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3326 lra_set_insn_deleted (curr_insn
);
3328 else if (dest
== rld
)
3330 *curr_id
->operand_loc
[0] = new_reg
;
3331 after
= emit_spill_move (false, new_reg
, dest
);
3332 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3333 "Inserting the sec. move");
3337 *curr_id
->operand_loc
[1] = new_reg
;
3338 /* See comments above. */
3339 push_to_sequence (before
);
3340 before
= emit_spill_move (true, new_reg
, src
);
3342 before
= get_insns ();
3344 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3345 "Inserting the sec. move");
3347 lra_update_insn_regno_info (curr_insn
);
3352 lra_assert (goal_alt_number
>= 0);
3353 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3355 if (lra_dump_file
!= NULL
)
3359 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3360 goal_alt_number
, INSN_UID (curr_insn
));
3361 for (i
= 0; i
< n_operands
; i
++)
3363 p
= (curr_static_id
->operand_alternative
3364 [goal_alt_number
* n_operands
+ i
].constraint
);
3367 fprintf (lra_dump_file
, " (%d) ", i
);
3368 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3369 fputc (*p
, lra_dump_file
);
3371 if (INSN_CODE (curr_insn
) >= 0
3372 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3373 fprintf (lra_dump_file
, " {%s}", p
);
3374 if (curr_id
->sp_offset
!= 0)
3375 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
3376 curr_id
->sp_offset
);
3377 fprintf (lra_dump_file
, "\n");
3380 /* Right now, for any pair of operands I and J that are required to
3381 match, with J < I, goal_alt_matches[I] is J. Add I to
3382 goal_alt_matched[J]. */
3384 for (i
= 0; i
< n_operands
; i
++)
3385 if ((j
= goal_alt_matches
[i
]) >= 0)
3387 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3389 /* We allow matching one output operand and several input
3392 || (curr_static_id
->operand
[j
].type
== OP_OUT
3393 && curr_static_id
->operand
[i
].type
== OP_IN
3394 && (curr_static_id
->operand
3395 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3396 goal_alt_matched
[j
][k
] = i
;
3397 goal_alt_matched
[j
][k
+ 1] = -1;
3400 for (i
= 0; i
< n_operands
; i
++)
3401 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3403 /* Any constants that aren't allowed and can't be reloaded into
3404 registers are here changed into memory references. */
3405 for (i
= 0; i
< n_operands
; i
++)
3406 if (goal_alt_win
[i
])
3409 enum reg_class new_class
;
3410 rtx reg
= *curr_id
->operand_loc
[i
];
3412 if (GET_CODE (reg
) == SUBREG
)
3413 reg
= SUBREG_REG (reg
);
3415 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3417 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3419 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3422 lra_change_class (regno
, new_class
, " Change to", true);
3428 const char *constraint
;
3430 rtx op
= *curr_id
->operand_loc
[i
];
3431 rtx subreg
= NULL_RTX
;
3432 enum machine_mode mode
= curr_operand_mode
[i
];
3434 if (GET_CODE (op
) == SUBREG
)
3437 op
= SUBREG_REG (op
);
3438 mode
= GET_MODE (op
);
3441 if (CONST_POOL_OK_P (mode
, op
)
3442 && ((targetm
.preferred_reload_class
3443 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3444 || no_input_reloads_p
))
3446 rtx tem
= force_const_mem (mode
, op
);
3449 if (subreg
!= NULL_RTX
)
3450 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3452 *curr_id
->operand_loc
[i
] = tem
;
3453 lra_update_dup (curr_id
, i
);
3454 process_address (i
, &before
, &after
);
3456 /* If the alternative accepts constant pool refs directly
3457 there will be no reload needed at all. */
3458 if (subreg
!= NULL_RTX
)
3460 /* Skip alternatives before the one requested. */
3461 constraint
= (curr_static_id
->operand_alternative
3462 [goal_alt_number
* n_operands
+ i
].constraint
);
3464 (c
= *constraint
) && c
!= ',' && c
!= '#';
3465 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3467 enum constraint_num cn
= lookup_constraint (constraint
);
3468 if (insn_extra_memory_constraint (cn
)
3469 && satisfies_memory_constraint_p (tem
, cn
))
3472 if (c
== '\0' || c
== ',' || c
== '#')
3475 goal_alt_win
[i
] = true;
3479 for (i
= 0; i
< n_operands
; i
++)
3482 bool optional_p
= false;
3484 rtx op
= *curr_id
->operand_loc
[i
];
3486 if (goal_alt_win
[i
])
3488 if (goal_alt
[i
] == NO_REGS
3490 /* When we assign NO_REGS it means that we will not
3491 assign a hard register to the scratch pseudo by
3492 assigment pass and the scratch pseudo will be
3493 spilled. Spilled scratch pseudos are transformed
3494 back to scratches at the LRA end. */
3495 && lra_former_scratch_operand_p (curr_insn
, i
))
3497 int regno
= REGNO (op
);
3498 lra_change_class (regno
, NO_REGS
, " Change to", true);
3499 if (lra_get_regno_hard_regno (regno
) >= 0)
3500 /* We don't have to mark all insn affected by the
3501 spilled pseudo as there is only one such insn, the
3503 reg_renumber
[regno
] = -1;
3505 /* We can do an optional reload. If the pseudo got a hard
3506 reg, we might improve the code through inheritance. If
3507 it does not get a hard register we coalesce memory/memory
3508 moves later. Ignore move insns to avoid cycling. */
3510 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3511 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3512 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3513 && regno
< new_regno_start
3514 && ! lra_former_scratch_p (regno
)
3515 && reg_renumber
[regno
] < 0
3516 && (curr_insn_set
== NULL_RTX
3517 || !((REG_P (SET_SRC (curr_insn_set
))
3518 || MEM_P (SET_SRC (curr_insn_set
))
3519 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3520 && (REG_P (SET_DEST (curr_insn_set
))
3521 || MEM_P (SET_DEST (curr_insn_set
))
3522 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3528 /* Operands that match previous ones have already been handled. */
3529 if (goal_alt_matches
[i
] >= 0)
3532 /* We should not have an operand with a non-offsettable address
3533 appearing where an offsettable address will do. It also may
3534 be a case when the address should be special in other words
3535 not a general one (e.g. it needs no index reg). */
3536 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3538 enum reg_class rclass
;
3539 rtx
*loc
= &XEXP (op
, 0);
3540 enum rtx_code code
= GET_CODE (*loc
);
3542 push_to_sequence (before
);
3543 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3545 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3546 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3547 /* This value does not matter for MODIFY. */
3548 GET_MODE_SIZE (GET_MODE (op
)));
3549 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
3550 "offsetable address", &new_reg
))
3551 lra_emit_move (new_reg
, *loc
);
3552 before
= get_insns ();
3555 lra_update_dup (curr_id
, i
);
3557 else if (goal_alt_matched
[i
][0] == -1)
3559 enum machine_mode mode
;
3561 int hard_regno
, byte
;
3562 enum op_type type
= curr_static_id
->operand
[i
].type
;
3564 loc
= curr_id
->operand_loc
[i
];
3565 mode
= curr_operand_mode
[i
];
3566 if (GET_CODE (*loc
) == SUBREG
)
3568 reg
= SUBREG_REG (*loc
);
3569 byte
= SUBREG_BYTE (*loc
);
3571 /* Strict_low_part requires reload the register not
3572 the sub-register. */
3573 && (curr_static_id
->operand
[i
].strict_low
3574 || (GET_MODE_SIZE (mode
)
3575 <= GET_MODE_SIZE (GET_MODE (reg
))
3577 = get_try_hard_regno (REGNO (reg
))) >= 0
3578 && (simplify_subreg_regno
3580 GET_MODE (reg
), byte
, mode
) < 0)
3581 && (goal_alt
[i
] == NO_REGS
3582 || (simplify_subreg_regno
3583 (ira_class_hard_regs
[goal_alt
[i
]][0],
3584 GET_MODE (reg
), byte
, mode
) >= 0)))))
3586 loc
= &SUBREG_REG (*loc
);
3587 mode
= GET_MODE (*loc
);
3591 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
3592 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
3595 push_to_sequence (before
);
3596 lra_emit_move (new_reg
, old
);
3597 before
= get_insns ();
3602 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3605 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3607 after
= get_insns ();
3611 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3612 if (goal_alt_dont_inherit_ops
[j
] == i
)
3614 lra_set_regno_unique_value (REGNO (new_reg
));
3617 lra_update_dup (curr_id
, i
);
3619 else if (curr_static_id
->operand
[i
].type
== OP_IN
3620 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3623 /* generate reloads for input and matched outputs. */
3624 match_inputs
[0] = i
;
3625 match_inputs
[1] = -1;
3626 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3627 goal_alt
[i
], &before
, &after
);
3629 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3630 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3632 /* Generate reloads for output and matched inputs. */
3633 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3634 else if (curr_static_id
->operand
[i
].type
== OP_IN
3635 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3638 /* Generate reloads for matched inputs. */
3639 match_inputs
[0] = i
;
3640 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3641 match_inputs
[j
+ 1] = k
;
3642 match_inputs
[j
+ 1] = -1;
3643 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3646 /* We must generate code in any case when function
3647 process_alt_operands decides that it is possible. */
3651 lra_assert (REG_P (op
));
3653 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3654 if (GET_CODE (op
) == SUBREG
)
3655 op
= SUBREG_REG (op
);
3656 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3657 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3658 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3659 if (lra_dump_file
!= NULL
)
3660 fprintf (lra_dump_file
,
3661 " Making reload reg %d for reg %d optional\n",
3665 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3666 || max_regno_before
!= max_reg_num ())
3670 lra_update_operator_dups (curr_id
);
3671 /* Something changes -- process the insn. */
3672 lra_update_insn_regno_info (curr_insn
);
3674 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3678 /* Return true if X is in LIST. */
3680 in_list_p (rtx x
, rtx list
)
3682 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3683 if (XEXP (list
, 0) == x
)
3688 /* Return true if X contains an allocatable hard register (if
3689 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3691 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3697 code
= GET_CODE (x
);
3700 int regno
= REGNO (x
);
3701 HARD_REG_SET alloc_regs
;
3705 if (regno
>= FIRST_PSEUDO_REGISTER
)
3706 regno
= lra_get_regno_hard_regno (regno
);
3709 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3710 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3714 if (regno
< FIRST_PSEUDO_REGISTER
)
3718 return lra_get_regno_hard_regno (regno
) < 0;
3721 fmt
= GET_RTX_FORMAT (code
);
3722 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3726 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3729 else if (fmt
[i
] == 'E')
3731 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3732 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3739 /* Process all regs in location *LOC and change them on equivalent
3740 substitution. Return true if any change was done. */
3742 loc_equivalence_change_p (rtx
*loc
)
3744 rtx subst
, reg
, x
= *loc
;
3745 bool result
= false;
3746 enum rtx_code code
= GET_CODE (x
);
3752 reg
= SUBREG_REG (x
);
3753 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
3754 && GET_MODE (subst
) == VOIDmode
)
3756 /* We cannot reload debug location. Simplify subreg here
3757 while we know the inner mode. */
3758 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3759 GET_MODE (reg
), SUBREG_BYTE (x
));
3763 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
3769 /* Scan all the operand sub-expressions. */
3770 fmt
= GET_RTX_FORMAT (code
);
3771 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3774 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3775 else if (fmt
[i
] == 'E')
3776 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3778 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3783 /* Similar to loc_equivalence_change_p, but for use as
3784 simplify_replace_fn_rtx callback. DATA is insn for which the
3785 elimination is done. If it null we don't do the elimination. */
3787 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
3792 rtx subst
= (data
== NULL
3793 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx
) data
));
3800 /* Maximum number of generated reload insns per an insn. It is for
3801 preventing this pass cycling in a bug case. */
3802 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3804 /* The current iteration number of this LRA pass. */
3805 int lra_constraint_iter
;
3807 /* The current iteration number of this LRA pass after the last spill
3809 int lra_constraint_iter_after_spill
;
3811 /* True if we substituted equiv which needs checking register
3812 allocation correctness because the equivalent value contains
3813 allocatable hard registers or when we restore multi-register
3815 bool lra_risky_transformations_p
;
3817 /* Return true if REGNO is referenced in more than one block. */
3819 multi_block_pseudo_p (int regno
)
3821 basic_block bb
= NULL
;
3825 if (regno
< FIRST_PSEUDO_REGISTER
)
3828 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3830 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3831 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3836 /* Return true if LIST contains a deleted insn. */
3838 contains_deleted_insn_p (rtx list
)
3840 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3841 if (NOTE_P (XEXP (list
, 0))
3842 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3847 /* Return true if X contains a pseudo dying in INSN. */
3849 dead_pseudo_p (rtx x
, rtx insn
)
3856 return (insn
!= NULL_RTX
3857 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3858 code
= GET_CODE (x
);
3859 fmt
= GET_RTX_FORMAT (code
);
3860 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3864 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3867 else if (fmt
[i
] == 'E')
3869 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3870 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3877 /* Return true if INSN contains a dying pseudo in INSN right hand
3880 insn_rhs_dead_pseudo_p (rtx insn
)
3882 rtx set
= single_set (insn
);
3884 gcc_assert (set
!= NULL
);
3885 return dead_pseudo_p (SET_SRC (set
), insn
);
3888 /* Return true if any init insn of REGNO contains a dying pseudo in
3889 insn right hand side. */
3891 init_insn_rhs_dead_pseudo_p (int regno
)
3893 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3898 return insn_rhs_dead_pseudo_p (insns
);
3899 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3900 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3905 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3906 reverse only if we have one init insn with given REGNO as a
3909 reverse_equiv_p (int regno
)
3913 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3915 if (! INSN_P (XEXP (insns
, 0))
3916 || XEXP (insns
, 1) != NULL_RTX
)
3918 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3920 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3923 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3924 call this function only for non-reverse equivalence. */
3926 contains_reloaded_insn_p (int regno
)
3929 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3931 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3932 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3933 || ! REG_P (SET_DEST (set
))
3934 || (int) REGNO (SET_DEST (set
)) != regno
)
3939 /* Entry function of LRA constraint pass. Return true if the
3940 constraint pass did change the code. */
3942 lra_constraints (bool first_p
)
3945 int i
, hard_regno
, new_insns_num
;
3946 unsigned int min_len
, new_min_len
, uid
;
3947 rtx set
, x
, reg
, dest_reg
;
3948 basic_block last_bb
;
3949 bitmap_head equiv_insn_bitmap
;
3952 lra_constraint_iter
++;
3953 if (lra_dump_file
!= NULL
)
3954 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3955 lra_constraint_iter
);
3956 lra_constraint_iter_after_spill
++;
3957 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3959 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3960 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3962 lra_risky_transformations_p
= false;
3963 new_insn_uid_start
= get_max_uid ();
3964 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3965 /* Mark used hard regs for target stack size calulations. */
3966 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3967 if (lra_reg_info
[i
].nrefs
!= 0
3968 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3972 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3973 for (j
= 0; j
< nregs
; j
++)
3974 df_set_regs_ever_live (hard_regno
+ j
, true);
3976 /* Do elimination before the equivalence processing as we can spill
3977 some pseudos during elimination. */
3978 lra_eliminate (false, first_p
);
3979 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3980 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3981 if (lra_reg_info
[i
].nrefs
!= 0)
3983 ira_reg_equiv
[i
].profitable_p
= true;
3984 reg
= regno_reg_rtx
[i
];
3985 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
3987 bool pseudo_p
= contains_reg_p (x
, false, false);
3989 /* After RTL transformation, we can not guarantee that
3990 pseudo in the substitution was not reloaded which might
3991 make equivalence invalid. For example, in reverse
3998 the memory address register was reloaded before the 2nd
4000 if ((! first_p
&& pseudo_p
)
4001 /* We don't use DF for compilation speed sake. So it
4002 is problematic to update live info when we use an
4003 equivalence containing pseudos in more than one
4005 || (pseudo_p
&& multi_block_pseudo_p (i
))
4006 /* If an init insn was deleted for some reason, cancel
4007 the equiv. We could update the equiv insns after
4008 transformations including an equiv insn deletion
4009 but it is not worthy as such cases are extremely
4011 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4012 /* If it is not a reverse equivalence, we check that a
4013 pseudo in rhs of the init insn is not dying in the
4014 insn. Otherwise, the live info at the beginning of
4015 the corresponding BB might be wrong after we
4016 removed the insn. When the equiv can be a
4017 constant, the right hand side of the init insn can
4019 || (! reverse_equiv_p (i
)
4020 && (init_insn_rhs_dead_pseudo_p (i
)
4021 /* If we reloaded the pseudo in an equivalence
4022 init insn, we can not remove the equiv init
4023 insns and the init insns might write into
4024 const memory in this case. */
4025 || contains_reloaded_insn_p (i
)))
4026 /* Prevent access beyond equivalent memory for
4027 paradoxical subregs. */
4029 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4030 > GET_MODE_SIZE (GET_MODE (x
)))))
4031 ira_reg_equiv
[i
].defined_p
= false;
4032 if (contains_reg_p (x
, false, true))
4033 ira_reg_equiv
[i
].profitable_p
= false;
4034 if (get_equiv (reg
) != reg
)
4035 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4038 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4040 /* We should add all insns containing pseudos which should be
4041 substituted by their equivalences. */
4042 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
4043 lra_push_insn_by_uid (uid
);
4044 min_len
= lra_insn_stack_length ();
4048 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4050 curr_insn
= lra_pop_insn ();
4052 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4053 if (curr_bb
!= last_bb
)
4056 bb_reload_num
= lra_curr_reload_num
;
4058 if (min_len
> new_min_len
)
4060 min_len
= new_min_len
;
4063 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4065 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4066 MAX_RELOAD_INSNS_NUMBER
);
4068 if (DEBUG_INSN_P (curr_insn
))
4070 /* We need to check equivalence in debug insn and change
4071 pseudo to the equivalent value if necessary. */
4072 curr_id
= lra_get_insn_recog_data (curr_insn
);
4073 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4075 rtx old
= *curr_id
->operand_loc
[0];
4076 *curr_id
->operand_loc
[0]
4077 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4078 loc_equivalence_callback
, curr_insn
);
4079 if (old
!= *curr_id
->operand_loc
[0])
4081 lra_update_insn_regno_info (curr_insn
);
4086 else if (INSN_P (curr_insn
))
4088 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4090 dest_reg
= SET_DEST (set
);
4091 /* The equivalence pseudo could be set up as SUBREG in a
4092 case when it is a call restore insn in a mode
4093 different from the pseudo mode. */
4094 if (GET_CODE (dest_reg
) == SUBREG
)
4095 dest_reg
= SUBREG_REG (dest_reg
);
4096 if ((REG_P (dest_reg
)
4097 && (x
= get_equiv (dest_reg
)) != dest_reg
4098 /* Remove insns which set up a pseudo whose value
4099 can not be changed. Such insns might be not in
4100 init_insns because we don't update equiv data
4101 during insn transformations.
4103 As an example, let suppose that a pseudo got
4104 hard register and on the 1st pass was not
4105 changed to equivalent constant. We generate an
4106 additional insn setting up the pseudo because of
4107 secondary memory movement. Then the pseudo is
4108 spilled and we use the equiv constant. In this
4109 case we should remove the additional insn and
4110 this insn is not init_insns list. */
4111 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4112 /* Check that this is actually an insn setting
4113 up the equivalence. */
4114 || in_list_p (curr_insn
,
4116 [REGNO (dest_reg
)].init_insns
)))
4117 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4118 && in_list_p (curr_insn
,
4120 [REGNO (SET_SRC (set
))].init_insns
)))
4122 /* This is equiv init insn of pseudo which did not get a
4123 hard register -- remove the insn. */
4124 if (lra_dump_file
!= NULL
)
4126 fprintf (lra_dump_file
,
4127 " Removing equiv init insn %i (freq=%d)\n",
4128 INSN_UID (curr_insn
),
4129 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4130 dump_insn_slim (lra_dump_file
, curr_insn
);
4132 if (contains_reg_p (x
, true, false))
4133 lra_risky_transformations_p
= true;
4134 lra_set_insn_deleted (curr_insn
);
4138 curr_id
= lra_get_insn_recog_data (curr_insn
);
4139 curr_static_id
= curr_id
->insn_static_data
;
4140 init_curr_insn_input_reloads ();
4141 init_curr_operand_mode ();
4142 if (curr_insn_transform ())
4144 /* Check non-transformed insns too for equiv change as USE
4145 or CLOBBER don't need reloads but can contain pseudos
4146 being changed on their equivalences. */
4147 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4148 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4150 lra_update_insn_regno_info (curr_insn
);
4155 bitmap_clear (&equiv_insn_bitmap
);
4156 /* If we used a new hard regno, changed_p should be true because the
4157 hard reg is assigned to a new pseudo. */
4158 #ifdef ENABLE_CHECKING
4161 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4162 if (lra_reg_info
[i
].nrefs
!= 0
4163 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4165 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4167 for (j
= 0; j
< nregs
; j
++)
4168 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4175 /* Initiate the LRA constraint pass. It is done once per
4178 lra_constraints_init (void)
4182 /* Finalize the LRA constraint pass. It is done once per
4185 lra_constraints_finish (void)
4191 /* This page contains code to do inheritance/split
4194 /* Number of reloads passed so far in current EBB. */
4195 static int reloads_num
;
4197 /* Number of calls passed so far in current EBB. */
4198 static int calls_num
;
4200 /* Current reload pseudo check for validity of elements in
4202 static int curr_usage_insns_check
;
4204 /* Info about last usage of registers in EBB to do inheritance/split
4205 transformation. Inheritance transformation is done from a spilled
4206 pseudo and split transformations from a hard register or a pseudo
4207 assigned to a hard register. */
4210 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4211 value INSNS is valid. The insns is chain of optional debug insns
4212 and a finishing non-debug insn using the corresponding reg. The
4213 value is also used to mark the registers which are set up in the
4214 current insn. The negated insn uid is used for this. */
4216 /* Value of global reloads_num at the last insn in INSNS. */
4218 /* Value of global reloads_nums at the last insn in INSNS. */
4220 /* It can be true only for splitting. And it means that the restore
4221 insn should be put after insn given by the following member. */
4223 /* Next insns in the current EBB which use the original reg and the
4224 original reg value is not changed between the current insn and
4225 the next insns. In order words, e.g. for inheritance, if we need
4226 to use the original reg value again in the next insns we can try
4227 to use the value in a hard register from a reload insn of the
4232 /* Map: regno -> corresponding pseudo usage insns. */
4233 static struct usage_insns
*usage_insns
;
4236 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4238 usage_insns
[regno
].check
= curr_usage_insns_check
;
4239 usage_insns
[regno
].insns
= insn
;
4240 usage_insns
[regno
].reloads_num
= reloads_num
;
4241 usage_insns
[regno
].calls_num
= calls_num
;
4242 usage_insns
[regno
].after_p
= after_p
;
4245 /* The function is used to form list REGNO usages which consists of
4246 optional debug insns finished by a non-debug insn using REGNO.
4247 RELOADS_NUM is current number of reload insns processed so far. */
4249 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4251 rtx next_usage_insns
;
4253 if (usage_insns
[regno
].check
== curr_usage_insns_check
4254 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4255 && DEBUG_INSN_P (insn
))
4257 /* Check that we did not add the debug insn yet. */
4258 if (next_usage_insns
!= insn
4259 && (GET_CODE (next_usage_insns
) != INSN_LIST
4260 || XEXP (next_usage_insns
, 0) != insn
))
4261 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4264 else if (NONDEBUG_INSN_P (insn
))
4265 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4267 usage_insns
[regno
].check
= 0;
4270 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4271 register NEW_REG. Return true if any change was made. */
4273 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4276 bool result
= false;
4284 code
= GET_CODE (x
);
4285 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4287 enum machine_mode mode
= GET_MODE (*loc
);
4288 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4290 if (mode
!= inner_mode
)
4292 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4293 || ! SCALAR_INT_MODE_P (inner_mode
))
4294 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4296 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4302 /* Scan all the operand sub-expressions. */
4303 fmt
= GET_RTX_FORMAT (code
);
4304 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4308 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4311 else if (fmt
[i
] == 'E')
4313 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4314 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4321 /* Return first non-debug insn in list USAGE_INSNS. */
4323 skip_usage_debug_insns (rtx usage_insns
)
4327 /* Skip debug insns. */
4328 for (insn
= usage_insns
;
4329 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4330 insn
= XEXP (insn
, 1))
4335 /* Return true if we need secondary memory moves for insn in
4336 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4339 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4340 rtx usage_insns ATTRIBUTE_UNUSED
)
4342 #ifndef SECONDARY_MEMORY_NEEDED
4345 rtx insn
, set
, dest
;
4348 if (inher_cl
== ALL_REGS
4349 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4351 lra_assert (INSN_P (insn
));
4352 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4354 dest
= SET_DEST (set
);
4357 lra_assert (inher_cl
!= NO_REGS
);
4358 cl
= get_reg_class (REGNO (dest
));
4359 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4360 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4364 /* Registers involved in inheritance/split in the current EBB
4365 (inheritance/split pseudos and original registers). */
4366 static bitmap_head check_only_regs
;
4368 /* Do inheritance transformations for insn INSN, which defines (if
4369 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4370 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4371 form as the "insns" field of usage_insns. Return true if we
4372 succeed in such transformation.
4374 The transformations look like:
4377 ... p <- i (new insn)
4379 <- ... p ... <- ... i ...
4381 ... i <- p (new insn)
4382 <- ... p ... <- ... i ...
4384 <- ... p ... <- ... i ...
4385 where p is a spilled original pseudo and i is a new inheritance pseudo.
4388 The inheritance pseudo has the smallest class of two classes CL and
4389 class of ORIGINAL REGNO. */
4391 inherit_reload_reg (bool def_p
, int original_regno
,
4392 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4394 if (optimize_function_for_size_p (cfun
))
4397 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4398 rtx original_reg
= regno_reg_rtx
[original_regno
];
4399 rtx new_reg
, new_insns
, usage_insn
;
4401 lra_assert (! usage_insns
[original_regno
].after_p
);
4402 if (lra_dump_file
!= NULL
)
4403 fprintf (lra_dump_file
,
4404 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4405 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4407 if (lra_dump_file
!= NULL
)
4409 fprintf (lra_dump_file
,
4410 " Rejecting inheritance for %d "
4411 "because of disjoint classes %s and %s\n",
4412 original_regno
, reg_class_names
[cl
],
4413 reg_class_names
[rclass
]);
4414 fprintf (lra_dump_file
,
4415 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4419 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4420 /* We don't use a subset of two classes because it can be
4421 NO_REGS. This transformation is still profitable in most
4422 cases even if the classes are not intersected as register
4423 move is probably cheaper than a memory load. */
4424 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4426 if (lra_dump_file
!= NULL
)
4427 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4428 reg_class_names
[cl
], reg_class_names
[rclass
]);
4432 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4434 /* Reject inheritance resulting in secondary memory moves.
4435 Otherwise, there is a danger in LRA cycling. Also such
4436 transformation will be unprofitable. */
4437 if (lra_dump_file
!= NULL
)
4439 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4440 rtx set
= single_set (insn
);
4442 lra_assert (set
!= NULL_RTX
);
4444 rtx dest
= SET_DEST (set
);
4446 lra_assert (REG_P (dest
));
4447 fprintf (lra_dump_file
,
4448 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4449 "as secondary mem is needed\n",
4450 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4451 original_regno
, reg_class_names
[rclass
]);
4452 fprintf (lra_dump_file
,
4453 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4457 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4458 rclass
, "inheritance");
4461 lra_emit_move (original_reg
, new_reg
);
4463 lra_emit_move (new_reg
, original_reg
);
4464 new_insns
= get_insns ();
4466 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4468 if (lra_dump_file
!= NULL
)
4470 fprintf (lra_dump_file
,
4471 " Rejecting inheritance %d->%d "
4472 "as it results in 2 or more insns:\n",
4473 original_regno
, REGNO (new_reg
));
4474 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4475 fprintf (lra_dump_file
,
4476 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4480 substitute_pseudo (&insn
, original_regno
, new_reg
);
4481 lra_update_insn_regno_info (insn
);
4483 /* We now have a new usage insn for original regno. */
4484 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4485 if (lra_dump_file
!= NULL
)
4486 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4487 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4488 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4489 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4490 bitmap_set_bit (&check_only_regs
, original_regno
);
4491 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4493 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4494 "Add original<-inheritance");
4496 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4497 "Add inheritance<-original");
4498 while (next_usage_insns
!= NULL_RTX
)
4500 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4502 usage_insn
= next_usage_insns
;
4503 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4504 next_usage_insns
= NULL
;
4508 usage_insn
= XEXP (next_usage_insns
, 0);
4509 lra_assert (DEBUG_INSN_P (usage_insn
));
4510 next_usage_insns
= XEXP (next_usage_insns
, 1);
4512 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4513 lra_update_insn_regno_info (usage_insn
);
4514 if (lra_dump_file
!= NULL
)
4516 fprintf (lra_dump_file
,
4517 " Inheritance reuse change %d->%d (bb%d):\n",
4518 original_regno
, REGNO (new_reg
),
4519 BLOCK_FOR_INSN (usage_insn
)->index
);
4520 dump_insn_slim (lra_dump_file
, usage_insn
);
4523 if (lra_dump_file
!= NULL
)
4524 fprintf (lra_dump_file
,
4525 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4529 /* Return true if we need a caller save/restore for pseudo REGNO which
4530 was assigned to a hard register. */
4532 need_for_call_save_p (int regno
)
4534 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4535 return (usage_insns
[regno
].calls_num
< calls_num
4536 && (overlaps_hard_reg_set_p
4537 ((flag_use_caller_save
&&
4538 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
4539 ? lra_reg_info
[regno
].actual_call_used_reg_set
4540 : call_used_reg_set
,
4541 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4542 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4543 PSEUDO_REGNO_MODE (regno
))));
4546 /* Global registers occurring in the current EBB. */
4547 static bitmap_head ebb_global_regs
;
4549 /* Return true if we need a split for hard register REGNO or pseudo
4550 REGNO which was assigned to a hard register.
4551 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4552 used for reloads since the EBB end. It is an approximation of the
4553 used hard registers in the split range. The exact value would
4554 require expensive calculations. If we were aggressive with
4555 splitting because of the approximation, the split pseudo will save
4556 the same hard register assignment and will be removed in the undo
4557 pass. We still need the approximation because too aggressive
4558 splitting would result in too inaccurate cost calculation in the
4559 assignment pass because of too many generated moves which will be
4560 probably removed in the undo pass. */
4562 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4564 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4566 lra_assert (hard_regno
>= 0);
4567 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4568 /* Don't split eliminable hard registers, otherwise we can
4569 split hard registers like hard frame pointer, which
4570 lives on BB start/end according to DF-infrastructure,
4571 when there is a pseudo assigned to the register and
4572 living in the same BB. */
4573 && (regno
>= FIRST_PSEUDO_REGISTER
4574 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4575 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4576 /* Don't split call clobbered hard regs living through
4577 calls, otherwise we might have a check problem in the
4578 assign sub-pass as in the most cases (exception is a
4579 situation when lra_risky_transformations_p value is
4580 true) the assign pass assumes that all pseudos living
4581 through calls are assigned to call saved hard regs. */
4582 && (regno
>= FIRST_PSEUDO_REGISTER
4583 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4584 || usage_insns
[regno
].calls_num
== calls_num
)
4585 /* We need at least 2 reloads to make pseudo splitting
4586 profitable. We should provide hard regno splitting in
4587 any case to solve 1st insn scheduling problem when
4588 moving hard register definition up might result in
4589 impossibility to find hard register for reload pseudo of
4590 small register class. */
4591 && (usage_insns
[regno
].reloads_num
4592 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
4593 && (regno
< FIRST_PSEUDO_REGISTER
4594 /* For short living pseudos, spilling + inheritance can
4595 be considered a substitution for splitting.
4596 Therefore we do not splitting for local pseudos. It
4597 decreases also aggressiveness of splitting. The
4598 minimal number of references is chosen taking into
4599 account that for 2 references splitting has no sense
4600 as we can just spill the pseudo. */
4601 || (regno
>= FIRST_PSEUDO_REGISTER
4602 && lra_reg_info
[regno
].nrefs
> 3
4603 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4604 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4607 /* Return class for the split pseudo created from original pseudo with
4608 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4609 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4610 results in no secondary memory movements. */
4611 static enum reg_class
4612 choose_split_class (enum reg_class allocno_class
,
4613 int hard_regno ATTRIBUTE_UNUSED
,
4614 enum machine_mode mode ATTRIBUTE_UNUSED
)
4616 #ifndef SECONDARY_MEMORY_NEEDED
4617 return allocno_class
;
4620 enum reg_class cl
, best_cl
= NO_REGS
;
4621 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4622 = REGNO_REG_CLASS (hard_regno
);
4624 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4625 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4626 return allocno_class
;
4628 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4630 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4631 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4632 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4633 && (best_cl
== NO_REGS
4634 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4640 /* Do split transformations for insn INSN, which defines or uses
4641 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4642 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4643 "insns" field of usage_insns.
4645 The transformations look like:
4648 ... s <- p (new insn -- save)
4650 ... p <- s (new insn -- restore)
4651 <- ... p ... <- ... p ...
4653 <- ... p ... <- ... p ...
4654 ... s <- p (new insn -- save)
4656 ... p <- s (new insn -- restore)
4657 <- ... p ... <- ... p ...
4659 where p is an original pseudo got a hard register or a hard
4660 register and s is a new split pseudo. The save is put before INSN
4661 if BEFORE_P is true. Return true if we succeed in such
4664 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4666 enum reg_class rclass
;
4668 int hard_regno
, nregs
;
4669 rtx new_reg
, save
, restore
, usage_insn
;
4673 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4675 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4676 hard_regno
= original_regno
;
4677 call_save_p
= false;
4682 hard_regno
= reg_renumber
[original_regno
];
4683 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4684 rclass
= lra_get_allocno_class (original_regno
);
4685 original_reg
= regno_reg_rtx
[original_regno
];
4686 call_save_p
= need_for_call_save_p (original_regno
);
4688 original_reg
= regno_reg_rtx
[original_regno
];
4689 lra_assert (hard_regno
>= 0);
4690 if (lra_dump_file
!= NULL
)
4691 fprintf (lra_dump_file
,
4692 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4695 enum machine_mode mode
= GET_MODE (original_reg
);
4697 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4698 hard_regno_nregs
[hard_regno
][mode
],
4700 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4704 rclass
= choose_split_class (rclass
, hard_regno
,
4705 GET_MODE (original_reg
));
4706 if (rclass
== NO_REGS
)
4708 if (lra_dump_file
!= NULL
)
4710 fprintf (lra_dump_file
,
4711 " Rejecting split of %d(%s): "
4712 "no good reg class for %d(%s)\n",
4714 reg_class_names
[lra_get_allocno_class (original_regno
)],
4716 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4719 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4723 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4725 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4727 save
= emit_spill_move (true, new_reg
, original_reg
);
4728 if (NEXT_INSN (save
) != NULL_RTX
)
4730 lra_assert (! call_save_p
);
4731 if (lra_dump_file
!= NULL
)
4735 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4736 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4737 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4738 fprintf (lra_dump_file
,
4739 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4743 restore
= emit_spill_move (false, new_reg
, original_reg
);
4744 if (NEXT_INSN (restore
) != NULL_RTX
)
4746 lra_assert (! call_save_p
);
4747 if (lra_dump_file
!= NULL
)
4749 fprintf (lra_dump_file
,
4750 " Rejecting split %d->%d "
4751 "resulting in > 2 %s restore insns:\n",
4752 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4753 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4754 fprintf (lra_dump_file
,
4755 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4759 after_p
= usage_insns
[original_regno
].after_p
;
4760 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4761 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4762 bitmap_set_bit (&check_only_regs
, original_regno
);
4763 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4766 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4768 usage_insn
= next_usage_insns
;
4771 usage_insn
= XEXP (next_usage_insns
, 0);
4772 lra_assert (DEBUG_INSN_P (usage_insn
));
4773 next_usage_insns
= XEXP (next_usage_insns
, 1);
4774 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4775 lra_update_insn_regno_info (usage_insn
);
4776 if (lra_dump_file
!= NULL
)
4778 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4779 original_regno
, REGNO (new_reg
));
4780 dump_insn_slim (lra_dump_file
, usage_insn
);
4783 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4784 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4785 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4786 after_p
? restore
: NULL_RTX
,
4788 ? "Add reg<-save" : "Add reg<-split");
4789 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4790 before_p
? NULL_RTX
: save
,
4792 ? "Add save<-reg" : "Add split<-reg");
4794 /* If we are trying to split multi-register. We should check
4795 conflicts on the next assignment sub-pass. IRA can allocate on
4796 sub-register levels, LRA do this on pseudos level right now and
4797 this discrepancy may create allocation conflicts after
4799 lra_risky_transformations_p
= true;
4800 if (lra_dump_file
!= NULL
)
4801 fprintf (lra_dump_file
,
4802 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4806 /* Recognize that we need a split transformation for insn INSN, which
4807 defines or uses REGNO in its insn biggest MODE (we use it only if
4808 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4809 hard registers which might be used for reloads since the EBB end.
4810 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4811 uid before starting INSN processing. Return true if we succeed in
4812 such transformation. */
4814 split_if_necessary (int regno
, enum machine_mode mode
,
4815 HARD_REG_SET potential_reload_hard_regs
,
4816 bool before_p
, rtx insn
, int max_uid
)
4820 rtx next_usage_insns
;
4822 if (regno
< FIRST_PSEUDO_REGISTER
)
4823 nregs
= hard_regno_nregs
[regno
][mode
];
4824 for (i
= 0; i
< nregs
; i
++)
4825 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4826 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4827 /* To avoid processing the register twice or more. */
4828 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4829 && INSN_UID (next_usage_insns
) < max_uid
)
4830 || (GET_CODE (next_usage_insns
) == INSN_LIST
4831 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4832 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4833 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4838 /* Check only registers living at the current program point in the
4840 static bitmap_head live_regs
;
4842 /* Update live info in EBB given by its HEAD and TAIL insns after
4843 inheritance/split transformation. The function removes dead moves
4846 update_ebb_live_info (rtx head
, rtx tail
)
4853 basic_block last_bb
, prev_bb
, curr_bb
;
4855 struct lra_insn_reg
*reg
;
4859 last_bb
= BLOCK_FOR_INSN (tail
);
4861 for (curr_insn
= tail
;
4862 curr_insn
!= PREV_INSN (head
);
4863 curr_insn
= prev_insn
)
4865 prev_insn
= PREV_INSN (curr_insn
);
4866 /* We need to process empty blocks too. They contain
4867 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4868 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4870 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4871 if (curr_bb
!= prev_bb
)
4873 if (prev_bb
!= NULL
)
4875 /* Update df_get_live_in (prev_bb): */
4876 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4877 if (bitmap_bit_p (&live_regs
, j
))
4878 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4880 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4882 if (curr_bb
!= last_bb
)
4884 /* Update df_get_live_out (curr_bb): */
4885 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4887 live_p
= bitmap_bit_p (&live_regs
, j
);
4889 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4890 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4896 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4898 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4902 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4904 if (! NONDEBUG_INSN_P (curr_insn
))
4906 curr_id
= lra_get_insn_recog_data (curr_insn
);
4907 curr_static_id
= curr_id
->insn_static_data
;
4909 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4910 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4911 && bitmap_bit_p (&check_only_regs
, regno
)
4912 && ! bitmap_bit_p (&live_regs
, regno
))
4914 /* See which defined values die here. */
4915 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4916 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4917 bitmap_clear_bit (&live_regs
, reg
->regno
);
4918 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
4919 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4920 bitmap_clear_bit (&live_regs
, reg
->regno
);
4921 /* Mark each used value as live. */
4922 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4923 if (reg
->type
!= OP_OUT
4924 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4925 bitmap_set_bit (&live_regs
, reg
->regno
);
4926 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
4927 if (reg
->type
!= OP_OUT
4928 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4929 bitmap_set_bit (&live_regs
, reg
->regno
);
4930 if (curr_id
->arg_hard_regs
!= NULL
)
4931 /* Make argument hard registers live. */
4932 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
4933 if (bitmap_bit_p (&check_only_regs
, regno
))
4934 bitmap_set_bit (&live_regs
, regno
);
4935 /* It is quite important to remove dead move insns because it
4936 means removing dead store. We don't need to process them for
4940 if (lra_dump_file
!= NULL
)
4942 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4943 dump_insn_slim (lra_dump_file
, curr_insn
);
4945 lra_set_insn_deleted (curr_insn
);
4950 /* The structure describes info to do an inheritance for the current
4951 insn. We need to collect such info first before doing the
4952 transformations because the transformations change the insn
4953 internal representation. */
4956 /* Original regno. */
4958 /* Subsequent insns which can inherit original reg value. */
4962 /* Array containing all info for doing inheritance from the current
4964 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4966 /* Number elements in the previous array. */
4967 static int to_inherit_num
;
4969 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4970 structure to_inherit. */
4972 add_to_inherit (int regno
, rtx insns
)
4976 for (i
= 0; i
< to_inherit_num
; i
++)
4977 if (to_inherit
[i
].regno
== regno
)
4979 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4980 to_inherit
[to_inherit_num
].regno
= regno
;
4981 to_inherit
[to_inherit_num
++].insns
= insns
;
4984 /* Return the last non-debug insn in basic block BB, or the block begin
4987 get_last_insertion_point (basic_block bb
)
4991 FOR_BB_INSNS_REVERSE (bb
, insn
)
4992 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4997 /* Set up RES by registers living on edges FROM except the edge (FROM,
4998 TO) or by registers set up in a jump insn in BB FROM. */
5000 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5003 struct lra_insn_reg
*reg
;
5007 lra_assert (to
!= NULL
);
5009 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5011 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5012 last
= get_last_insertion_point (from
);
5013 if (! JUMP_P (last
))
5015 curr_id
= lra_get_insn_recog_data (last
);
5016 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5017 if (reg
->type
!= OP_IN
)
5018 bitmap_set_bit (res
, reg
->regno
);
5021 /* Used as a temporary results of some bitmap calculations. */
5022 static bitmap_head temp_bitmap
;
5024 /* We split for reloads of small class of hard regs. The following
5025 defines how many hard regs the class should have to be qualified as
5026 small. The code is mostly oriented to x86/x86-64 architecture
5027 where some insns need to use only specific register or pair of
5028 registers and these register can live in RTL explicitly, e.g. for
5029 parameter passing. */
5030 static const int max_small_class_regs_num
= 2;
5032 /* Do inheritance/split transformations in EBB starting with HEAD and
5033 finishing on TAIL. We process EBB insns in the reverse order.
5034 Return true if we did any inheritance/split transformation in the
5037 We should avoid excessive splitting which results in worse code
5038 because of inaccurate cost calculations for spilling new split
5039 pseudos in such case. To achieve this we do splitting only if
5040 register pressure is high in given basic block and there are reload
5041 pseudos requiring hard registers. We could do more register
5042 pressure calculations at any given program point to avoid necessary
5043 splitting even more but it is to expensive and the current approach
5044 works well enough. */
5046 inherit_in_ebb (rtx head
, rtx tail
)
5048 int i
, src_regno
, dst_regno
, nregs
;
5049 bool change_p
, succ_p
, update_reloads_num_p
;
5050 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
5052 struct lra_insn_reg
*reg
;
5053 basic_block last_processed_bb
, curr_bb
= NULL
;
5054 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
5058 bool head_p
, after_p
;
5061 curr_usage_insns_check
++;
5062 reloads_num
= calls_num
= 0;
5063 bitmap_clear (&check_only_regs
);
5064 last_processed_bb
= NULL
;
5065 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5066 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
5067 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
5068 /* We don't process new insns generated in the loop. */
5069 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
5071 prev_insn
= PREV_INSN (curr_insn
);
5072 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
5073 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5074 if (last_processed_bb
!= curr_bb
)
5076 /* We are at the end of BB. Add qualified living
5077 pseudos for potential splitting. */
5078 to_process
= df_get_live_out (curr_bb
);
5079 if (last_processed_bb
!= NULL
)
5081 /* We are somewhere in the middle of EBB. */
5082 get_live_on_other_edges (curr_bb
, last_processed_bb
,
5084 to_process
= &temp_bitmap
;
5086 last_processed_bb
= curr_bb
;
5087 last_insn
= get_last_insertion_point (curr_bb
);
5088 after_p
= (! JUMP_P (last_insn
)
5089 && (! CALL_P (last_insn
)
5090 || (find_reg_note (last_insn
,
5091 REG_NORETURN
, NULL_RTX
) == NULL_RTX
5092 && ! SIBLING_CALL_P (last_insn
))));
5093 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
5094 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5096 if ((int) j
>= lra_constraint_new_regno_start
)
5098 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5100 if (j
< FIRST_PSEUDO_REGISTER
)
5101 SET_HARD_REG_BIT (live_hard_regs
, j
);
5103 add_to_hard_reg_set (&live_hard_regs
,
5104 PSEUDO_REGNO_MODE (j
),
5106 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
5110 src_regno
= dst_regno
= -1;
5111 if (NONDEBUG_INSN_P (curr_insn
)
5112 && (set
= single_set (curr_insn
)) != NULL_RTX
5113 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
5115 src_regno
= REGNO (SET_SRC (set
));
5116 dst_regno
= REGNO (SET_DEST (set
));
5118 update_reloads_num_p
= true;
5119 if (src_regno
< lra_constraint_new_regno_start
5120 && src_regno
>= FIRST_PSEUDO_REGISTER
5121 && reg_renumber
[src_regno
] < 0
5122 && dst_regno
>= lra_constraint_new_regno_start
5123 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
5125 /* 'reload_pseudo <- original_pseudo'. */
5126 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5128 update_reloads_num_p
= false;
5130 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5131 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
5132 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
5133 curr_insn
, next_usage_insns
);
5137 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5138 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5139 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5140 reg_class_contents
[cl
]);
5142 else if (src_regno
>= lra_constraint_new_regno_start
5143 && dst_regno
< lra_constraint_new_regno_start
5144 && dst_regno
>= FIRST_PSEUDO_REGISTER
5145 && reg_renumber
[dst_regno
] < 0
5146 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5147 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5148 && (next_usage_insns
5149 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5151 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5153 update_reloads_num_p
= false;
5154 /* 'original_pseudo <- reload_pseudo'. */
5155 if (! JUMP_P (curr_insn
)
5156 && inherit_reload_reg (true, dst_regno
, cl
,
5157 curr_insn
, next_usage_insns
))
5160 usage_insns
[dst_regno
].check
= 0;
5161 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5162 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5163 reg_class_contents
[cl
]);
5165 else if (INSN_P (curr_insn
))
5168 int max_uid
= get_max_uid ();
5170 curr_id
= lra_get_insn_recog_data (curr_insn
);
5171 curr_static_id
= curr_id
->insn_static_data
;
5173 /* Process insn definitions. */
5174 for (iter
= 0; iter
< 2; iter
++)
5175 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5178 if (reg
->type
!= OP_IN
5179 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5181 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5182 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5183 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5184 && (next_usage_insns
5185 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5187 struct lra_insn_reg
*r
;
5189 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5190 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5192 /* Don't do inheritance if the pseudo is also
5193 used in the insn. */
5195 /* We can not do inheritance right now
5196 because the current insn reg info (chain
5197 regs) can change after that. */
5198 add_to_inherit (dst_regno
, next_usage_insns
);
5200 /* We can not process one reg twice here because of
5201 usage_insns invalidation. */
5202 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5203 || reg_renumber
[dst_regno
] >= 0)
5204 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5208 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5209 potential_reload_hard_regs
,
5210 false, curr_insn
, max_uid
))
5212 CLEAR_HARD_REG_SET (s
);
5213 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5214 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5216 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5217 reg_renumber
[dst_regno
]);
5218 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5220 /* We should invalidate potential inheritance or
5221 splitting for the current insn usages to the next
5222 usage insns (see code below) as the output pseudo
5224 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5225 && reg_renumber
[dst_regno
] < 0)
5226 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5227 && (dst_regno
< FIRST_PSEUDO_REGISTER
5228 || reg_renumber
[dst_regno
] >= 0)))
5230 /* Invalidate and mark definitions. */
5231 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5232 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5235 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5236 for (i
= 0; i
< nregs
; i
++)
5237 usage_insns
[dst_regno
+ i
].check
5238 = -(int) INSN_UID (curr_insn
);
5242 if (! JUMP_P (curr_insn
))
5243 for (i
= 0; i
< to_inherit_num
; i
++)
5244 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5245 ALL_REGS
, curr_insn
,
5246 to_inherit
[i
].insns
))
5248 if (CALL_P (curr_insn
))
5250 rtx cheap
, pat
, dest
, restore
;
5251 int regno
, hard_regno
;
5254 if ((cheap
= find_reg_note (curr_insn
,
5255 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5256 && ((cheap
= XEXP (cheap
, 0)), true)
5257 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5258 && (hard_regno
= reg_renumber
[regno
]) >= 0
5259 /* If there are pending saves/restores, the
5260 optimization is not worth. */
5261 && usage_insns
[regno
].calls_num
== calls_num
- 1
5262 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5264 /* Restore the pseudo from the call result as
5265 REG_RETURNED note says that the pseudo value is
5266 in the call result and the pseudo is an argument
5268 pat
= PATTERN (curr_insn
);
5269 if (GET_CODE (pat
) == PARALLEL
)
5270 pat
= XVECEXP (pat
, 0, 0);
5271 dest
= SET_DEST (pat
);
5273 emit_move_insn (cheap
, copy_rtx (dest
));
5274 restore
= get_insns ();
5276 lra_process_new_insns (curr_insn
, NULL
, restore
,
5277 "Inserting call parameter restore");
5278 /* We don't need to save/restore of the pseudo from
5280 usage_insns
[regno
].calls_num
= calls_num
;
5281 bitmap_set_bit (&check_only_regs
, regno
);
5285 /* Process insn usages. */
5286 for (iter
= 0; iter
< 2; iter
++)
5287 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5290 if ((reg
->type
!= OP_OUT
5291 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5292 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5294 if (src_regno
>= FIRST_PSEUDO_REGISTER
5295 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5297 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5298 && (next_usage_insns
5299 = usage_insns
[src_regno
].insns
) != NULL_RTX
5300 && NONDEBUG_INSN_P (curr_insn
))
5301 add_to_inherit (src_regno
, next_usage_insns
);
5302 else if (usage_insns
[src_regno
].check
5303 != -(int) INSN_UID (curr_insn
))
5304 /* Add usages but only if the reg is not set up
5305 in the same insn. */
5306 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5308 else if (src_regno
< FIRST_PSEUDO_REGISTER
5309 || reg_renumber
[src_regno
] >= 0)
5312 rtx use_insn
= curr_insn
;
5314 before_p
= (JUMP_P (curr_insn
)
5315 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5316 if (NONDEBUG_INSN_P (curr_insn
)
5317 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
5318 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5319 potential_reload_hard_regs
,
5320 before_p
, curr_insn
, max_uid
))
5323 lra_risky_transformations_p
= true;
5326 usage_insns
[src_regno
].check
= 0;
5328 use_insn
= PREV_INSN (curr_insn
);
5330 if (NONDEBUG_INSN_P (curr_insn
))
5332 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5333 add_to_hard_reg_set (&live_hard_regs
,
5334 reg
->biggest_mode
, src_regno
);
5336 add_to_hard_reg_set (&live_hard_regs
,
5337 PSEUDO_REGNO_MODE (src_regno
),
5338 reg_renumber
[src_regno
]);
5340 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5343 /* Process call args. */
5344 if (curr_id
->arg_hard_regs
!= NULL
)
5345 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5346 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5348 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
5349 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5351 for (i
= 0; i
< to_inherit_num
; i
++)
5353 src_regno
= to_inherit
[i
].regno
;
5354 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5355 curr_insn
, to_inherit
[i
].insns
))
5358 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5361 if (update_reloads_num_p
5362 && NONDEBUG_INSN_P (curr_insn
)
5363 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5366 if ((REG_P (SET_DEST (set
))
5367 && (regno
= REGNO (SET_DEST (set
))) >= lra_constraint_new_regno_start
5368 && reg_renumber
[regno
] < 0
5369 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
5370 || (REG_P (SET_SRC (set
))
5371 && (regno
= REGNO (SET_SRC (set
))) >= lra_constraint_new_regno_start
5372 && reg_renumber
[regno
] < 0
5373 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
5375 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
5377 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5378 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5379 reg_class_contents
[cl
]);
5382 /* We reached the start of the current basic block. */
5383 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5384 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5386 /* We reached the beginning of the current block -- do
5387 rest of spliting in the current BB. */
5388 to_process
= df_get_live_in (curr_bb
);
5389 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5391 /* We are somewhere in the middle of EBB. */
5392 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5393 curr_bb
, &temp_bitmap
);
5394 to_process
= &temp_bitmap
;
5397 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5399 if ((int) j
>= lra_constraint_new_regno_start
)
5401 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5402 && usage_insns
[j
].check
== curr_usage_insns_check
5403 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5405 if (need_for_split_p (potential_reload_hard_regs
, j
))
5407 if (lra_dump_file
!= NULL
&& head_p
)
5409 fprintf (lra_dump_file
,
5410 " ----------------------------------\n");
5413 if (split_reg (false, j
, bb_note (curr_bb
),
5417 usage_insns
[j
].check
= 0;
5425 /* This value affects EBB forming. If probability of edge from EBB to
5426 a BB is not greater than the following value, we don't add the BB
5428 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5430 /* Current number of inheritance/split iteration. */
5431 int lra_inheritance_iter
;
5433 /* Entry function for inheritance/split pass. */
5435 lra_inheritance (void)
5438 basic_block bb
, start_bb
;
5441 lra_inheritance_iter
++;
5442 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5444 timevar_push (TV_LRA_INHERITANCE
);
5445 if (lra_dump_file
!= NULL
)
5446 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5447 lra_inheritance_iter
);
5448 curr_usage_insns_check
= 0;
5449 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5450 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5451 usage_insns
[i
].check
= 0;
5452 bitmap_initialize (&check_only_regs
, ®_obstack
);
5453 bitmap_initialize (&live_regs
, ®_obstack
);
5454 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5455 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5456 FOR_EACH_BB_FN (bb
, cfun
)
5459 if (lra_dump_file
!= NULL
)
5460 fprintf (lra_dump_file
, "EBB");
5461 /* Form a EBB starting with BB. */
5462 bitmap_clear (&ebb_global_regs
);
5463 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5466 if (lra_dump_file
!= NULL
)
5467 fprintf (lra_dump_file
, " %d", bb
->index
);
5468 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
5469 || LABEL_P (BB_HEAD (bb
->next_bb
)))
5471 e
= find_fallthru_edge (bb
->succs
);
5474 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5478 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5479 if (lra_dump_file
!= NULL
)
5480 fprintf (lra_dump_file
, "\n");
5481 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5482 /* Remember that the EBB head and tail can change in
5484 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5486 bitmap_clear (&ebb_global_regs
);
5487 bitmap_clear (&temp_bitmap
);
5488 bitmap_clear (&live_regs
);
5489 bitmap_clear (&check_only_regs
);
5492 timevar_pop (TV_LRA_INHERITANCE
);
5497 /* This page contains code to undo failed inheritance/split
5500 /* Current number of iteration undoing inheritance/split. */
5501 int lra_undo_inheritance_iter
;
5503 /* Fix BB live info LIVE after removing pseudos created on pass doing
5504 inheritance/split which are REMOVED_PSEUDOS. */
5506 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5511 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5512 if (bitmap_clear_bit (live
, regno
))
5513 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5516 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5521 if (GET_CODE (reg
) == SUBREG
)
5522 reg
= SUBREG_REG (reg
);
5528 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5529 return true if we did any change. The undo transformations for
5530 inheritance looks like
5534 p <- i, i <- p, and i <- i3
5535 where p is original pseudo from which inheritance pseudo i was
5536 created, i and i3 are removed inheritance pseudos, i2 is another
5537 not removed inheritance pseudo. All split pseudos or other
5538 occurrences of removed inheritance pseudos are changed on the
5539 corresponding original pseudos.
5541 The function also schedules insns changed and created during
5542 inheritance/split pass for processing by the subsequent constraint
5545 remove_inheritance_pseudos (bitmap remove_pseudos
)
5548 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5549 rtx set
, prev_set
, prev_insn
;
5550 bool change_p
, done_p
;
5552 change_p
= ! bitmap_empty_p (remove_pseudos
);
5553 /* We can not finish the function right away if CHANGE_P is true
5554 because we need to marks insns affected by previous
5555 inheritance/split pass for processing by the subsequent
5557 FOR_EACH_BB_FN (bb
, cfun
)
5559 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5560 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5561 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5563 if (! INSN_P (curr_insn
))
5566 sregno
= dregno
= -1;
5567 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5568 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5570 dregno
= get_regno (SET_DEST (set
));
5571 sregno
= get_regno (SET_SRC (set
));
5574 if (sregno
>= 0 && dregno
>= 0)
5576 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5577 && (lra_reg_info
[sregno
].restore_regno
== dregno
5578 || (bitmap_bit_p (remove_pseudos
, dregno
)
5579 && (lra_reg_info
[sregno
].restore_regno
5580 == lra_reg_info
[dregno
].restore_regno
))))
5581 || (bitmap_bit_p (remove_pseudos
, dregno
)
5582 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5583 /* One of the following cases:
5584 original <- removed inheritance pseudo
5585 removed inherit pseudo <- another removed inherit pseudo
5586 removed inherit pseudo <- original pseudo
5588 removed_split_pseudo <- original_reg
5589 original_reg <- removed_split_pseudo */
5591 if (lra_dump_file
!= NULL
)
5593 fprintf (lra_dump_file
, " Removing %s:\n",
5594 bitmap_bit_p (&lra_split_regs
, sregno
)
5595 || bitmap_bit_p (&lra_split_regs
, dregno
)
5596 ? "split" : "inheritance");
5597 dump_insn_slim (lra_dump_file
, curr_insn
);
5599 lra_set_insn_deleted (curr_insn
);
5602 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5603 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5605 /* Search the following pattern:
5606 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5607 original_pseudo <- inherit_or_split_pseudo1
5608 where the 2nd insn is the current insn and
5609 inherit_or_split_pseudo2 is not removed. If it is found,
5610 change the current insn onto:
5611 original_pseudo <- inherit_or_split_pseudo2. */
5612 for (prev_insn
= PREV_INSN (curr_insn
);
5613 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5614 prev_insn
= PREV_INSN (prev_insn
))
5616 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5617 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5618 /* There should be no subregs in insn we are
5619 searching because only the original reg might
5620 be in subreg when we changed the mode of
5621 load/store for splitting. */
5622 && REG_P (SET_DEST (prev_set
))
5623 && REG_P (SET_SRC (prev_set
))
5624 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5625 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5626 >= FIRST_PSEUDO_REGISTER
)
5627 /* As we consider chain of inheritance or
5628 splitting described in above comment we should
5629 check that sregno and prev_sregno were
5630 inheritance/split pseudos created from the
5631 same original regno. */
5632 && (lra_reg_info
[sregno
].restore_regno
5633 == lra_reg_info
[prev_sregno
].restore_regno
)
5634 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5636 lra_assert (GET_MODE (SET_SRC (prev_set
))
5637 == GET_MODE (regno_reg_rtx
[sregno
]));
5638 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5639 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5641 SET_SRC (set
) = SET_SRC (prev_set
);
5642 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5643 lra_set_used_insn_alternative_by_uid
5644 (INSN_UID (curr_insn
), -1);
5646 if (lra_dump_file
!= NULL
)
5648 fprintf (lra_dump_file
, " Change reload insn:\n");
5649 dump_insn_slim (lra_dump_file
, curr_insn
);
5656 struct lra_insn_reg
*reg
;
5657 bool restored_regs_p
= false;
5658 bool kept_regs_p
= false;
5660 curr_id
= lra_get_insn_recog_data (curr_insn
);
5661 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5664 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5665 if (restore_regno
>= 0)
5667 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5669 substitute_pseudo (&curr_insn
, regno
,
5670 regno_reg_rtx
[restore_regno
]);
5671 restored_regs_p
= true;
5677 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5679 /* The instruction has changed since the previous
5680 constraints pass. */
5681 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5682 lra_set_used_insn_alternative_by_uid
5683 (INSN_UID (curr_insn
), -1);
5685 else if (restored_regs_p
)
5686 /* The instruction has been restored to the form that
5687 it had during the previous constraints pass. */
5688 lra_update_insn_regno_info (curr_insn
);
5689 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5691 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5692 dump_insn_slim (lra_dump_file
, curr_insn
);
5700 /* If optional reload pseudos failed to get a hard register or was not
5701 inherited, it is better to remove optional reloads. We do this
5702 transformation after undoing inheritance to figure out necessity to
5703 remove optional reloads easier. Return true if we do any
5706 undo_optional_reloads (void)
5708 bool change_p
, keep_p
;
5709 unsigned int regno
, uid
;
5710 bitmap_iterator bi
, bi2
;
5711 rtx insn
, set
, src
, dest
;
5712 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5714 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5715 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5716 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5719 /* Keep optional reloads from previous subpasses. */
5720 if (lra_reg_info
[regno
].restore_regno
< 0
5721 /* If the original pseudo changed its allocation, just
5722 removing the optional pseudo is dangerous as the original
5723 pseudo will have longer live range. */
5724 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5726 else if (reg_renumber
[regno
] >= 0)
5727 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5729 insn
= lra_insn_recog_data
[uid
]->insn
;
5730 if ((set
= single_set (insn
)) == NULL_RTX
)
5732 src
= SET_SRC (set
);
5733 dest
= SET_DEST (set
);
5734 if (! REG_P (src
) || ! REG_P (dest
))
5736 if (REGNO (dest
) == regno
5737 /* Ignore insn for optional reloads itself. */
5738 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5739 /* Check only inheritance on last inheritance pass. */
5740 && (int) REGNO (src
) >= new_regno_start
5741 /* Check that the optional reload was inherited. */
5742 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5750 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5751 if (lra_dump_file
!= NULL
)
5752 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5755 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5756 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5757 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5759 if (lra_dump_file
!= NULL
)
5760 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5761 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5762 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5764 insn
= lra_insn_recog_data
[uid
]->insn
;
5765 if ((set
= single_set (insn
)) != NULL_RTX
)
5767 src
= SET_SRC (set
);
5768 dest
= SET_DEST (set
);
5769 if (REG_P (src
) && REG_P (dest
)
5770 && ((REGNO (src
) == regno
5771 && (lra_reg_info
[regno
].restore_regno
5772 == (int) REGNO (dest
)))
5773 || (REGNO (dest
) == regno
5774 && (lra_reg_info
[regno
].restore_regno
5775 == (int) REGNO (src
)))))
5777 if (lra_dump_file
!= NULL
)
5779 fprintf (lra_dump_file
, " Deleting move %u\n",
5781 dump_insn_slim (lra_dump_file
, insn
);
5783 lra_set_insn_deleted (insn
);
5786 /* We should not worry about generation memory-memory
5787 moves here as if the corresponding inheritance did
5788 not work (inheritance pseudo did not get a hard reg),
5789 we remove the inheritance pseudo and the optional
5792 substitute_pseudo (&insn
, regno
,
5793 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5794 lra_update_insn_regno_info (insn
);
5795 if (lra_dump_file
!= NULL
)
5797 fprintf (lra_dump_file
,
5798 " Restoring original insn:\n");
5799 dump_insn_slim (lra_dump_file
, insn
);
5803 /* Clear restore_regnos. */
5804 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5805 lra_reg_info
[regno
].restore_regno
= -1;
5806 bitmap_clear (&insn_bitmap
);
5807 bitmap_clear (&removed_optional_reload_pseudos
);
5811 /* Entry function for undoing inheritance/split transformation. Return true
5812 if we did any RTL change in this pass. */
5814 lra_undo_inheritance (void)
5817 int restore_regno
, hard_regno
;
5818 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5819 bitmap_head remove_pseudos
;
5823 lra_undo_inheritance_iter
++;
5824 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5826 if (lra_dump_file
!= NULL
)
5827 fprintf (lra_dump_file
,
5828 "\n********** Undoing inheritance #%d: **********\n\n",
5829 lra_undo_inheritance_iter
);
5830 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5831 n_inherit
= n_all_inherit
= 0;
5832 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5833 if (lra_reg_info
[regno
].restore_regno
>= 0)
5836 if (reg_renumber
[regno
] < 0
5837 /* If the original pseudo changed its allocation, just
5838 removing inheritance is dangerous as for changing
5839 allocation we used shorter live-ranges. */
5840 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5841 bitmap_set_bit (&remove_pseudos
, regno
);
5845 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5846 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5847 n_inherit
, n_all_inherit
,
5848 (double) n_inherit
/ n_all_inherit
* 100);
5849 n_split
= n_all_split
= 0;
5850 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5851 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5854 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5855 ? reg_renumber
[restore_regno
] : restore_regno
);
5856 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5857 bitmap_set_bit (&remove_pseudos
, regno
);
5861 if (lra_dump_file
!= NULL
)
5862 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5863 regno
, restore_regno
);
5866 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5867 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5868 n_split
, n_all_split
,
5869 (double) n_split
/ n_all_split
* 100);
5870 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5871 bitmap_clear (&remove_pseudos
);
5872 /* Clear restore_regnos. */
5873 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5874 lra_reg_info
[regno
].restore_regno
= -1;
5875 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5876 lra_reg_info
[regno
].restore_regno
= -1;
5877 change_p
= undo_optional_reloads () || change_p
;